1 /* 2 * All test cases of nested virtualization should be in this file 3 * 4 * Author : Arthur Chunqi Li <yzt356@gmail.com> 5 */ 6 7 #include <asm/debugreg.h> 8 9 #include "vmx.h" 10 #include "msr.h" 11 #include "processor.h" 12 #include "pmu.h" 13 #include "vm.h" 14 #include "pci.h" 15 #include "fwcfg.h" 16 #include "isr.h" 17 #include "desc.h" 18 #include "apic.h" 19 #include "vmalloc.h" 20 #include "alloc_page.h" 21 #include "smp.h" 22 #include "delay.h" 23 #include "access.h" 24 #include "x86/usermode.h" 25 26 /* 27 * vmcs.GUEST_PENDING_DEBUG has the same format as DR6, although some bits that 28 * are legal in DR6 are reserved in vmcs.GUEST_PENDING_DEBUG. And if any data 29 * or I/O breakpoint matches *and* was enabled, bit 12 is also set. 30 */ 31 #define PENDING_DBG_TRAP BIT(12) 32 33 #define VPID_CAP_INVVPID_TYPES_SHIFT 40 34 35 u64 ia32_pat; 36 u64 ia32_efer; 37 void *io_bitmap_a, *io_bitmap_b; 38 u16 ioport; 39 40 unsigned long *pml4; 41 u64 eptp; 42 void *data_page1, *data_page2; 43 44 phys_addr_t pci_physaddr; 45 46 void *pml_log; 47 #define PML_INDEX 512 48 49 static inline unsigned ffs(unsigned x) 50 { 51 int pos = -1; 52 53 __asm__ __volatile__("bsf %1, %%eax; cmovnz %%eax, %0" 54 : "+r"(pos) : "rm"(x) : "eax"); 55 return pos + 1; 56 } 57 58 static inline void vmcall(void) 59 { 60 asm volatile("vmcall"); 61 } 62 63 static void basic_guest_main(void) 64 { 65 report_pass("Basic VMX test"); 66 } 67 68 static int basic_exit_handler(union exit_reason exit_reason) 69 { 70 report_fail("Basic VMX test"); 71 print_vmexit_info(exit_reason); 72 return VMX_TEST_EXIT; 73 } 74 75 static void vmenter_main(void) 76 { 77 u64 rax; 78 u64 rsp, resume_rsp; 79 80 report_pass("test vmlaunch"); 81 82 asm volatile( 83 "mov %%rsp, %0\n\t" 84 "mov %3, %%rax\n\t" 85 "vmcall\n\t" 86 "mov %%rax, %1\n\t" 87 "mov %%rsp, %2\n\t" 88 : "=r"(rsp), "=r"(rax), "=r"(resume_rsp) 89 : "g"(0xABCD)); 90 report((rax == 0xFFFF) && (rsp == resume_rsp), "test vmresume"); 91 } 92 93 static int vmenter_exit_handler(union exit_reason exit_reason) 94 { 95 u64 guest_rip = vmcs_read(GUEST_RIP); 96 97 switch (exit_reason.basic) { 98 case VMX_VMCALL: 99 if (regs.rax != 0xABCD) { 100 report_fail("test vmresume"); 101 return VMX_TEST_VMEXIT; 102 } 103 regs.rax = 0xFFFF; 104 vmcs_write(GUEST_RIP, guest_rip + 3); 105 return VMX_TEST_RESUME; 106 default: 107 report_fail("test vmresume"); 108 print_vmexit_info(exit_reason); 109 } 110 return VMX_TEST_VMEXIT; 111 } 112 113 u32 preempt_scale; 114 volatile unsigned long long tsc_val; 115 volatile u32 preempt_val; 116 u64 saved_rip; 117 118 static int preemption_timer_init(struct vmcs *vmcs) 119 { 120 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 121 printf("\tPreemption timer is not supported\n"); 122 return VMX_TEST_EXIT; 123 } 124 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 125 preempt_val = 10000000; 126 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 127 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 128 129 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 130 printf("\tSave preemption value is not supported\n"); 131 132 return VMX_TEST_START; 133 } 134 135 static void preemption_timer_main(void) 136 { 137 tsc_val = rdtsc(); 138 if (ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) { 139 vmx_set_test_stage(0); 140 vmcall(); 141 if (vmx_get_test_stage() == 1) 142 vmcall(); 143 } 144 vmx_set_test_stage(1); 145 while (vmx_get_test_stage() == 1) { 146 if (((rdtsc() - tsc_val) >> preempt_scale) 147 > 10 * preempt_val) { 148 vmx_set_test_stage(2); 149 vmcall(); 150 } 151 } 152 tsc_val = rdtsc(); 153 asm volatile ("hlt"); 154 vmcall(); 155 vmx_set_test_stage(5); 156 vmcall(); 157 } 158 159 static int preemption_timer_exit_handler(union exit_reason exit_reason) 160 { 161 bool guest_halted; 162 u64 guest_rip; 163 u32 insn_len; 164 u32 ctrl_exit; 165 166 guest_rip = vmcs_read(GUEST_RIP); 167 insn_len = vmcs_read(EXI_INST_LEN); 168 switch (exit_reason.basic) { 169 case VMX_PREEMPT: 170 switch (vmx_get_test_stage()) { 171 case 1: 172 case 2: 173 report(((rdtsc() - tsc_val) >> preempt_scale) >= preempt_val, 174 "busy-wait for preemption timer"); 175 vmx_set_test_stage(3); 176 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 177 return VMX_TEST_RESUME; 178 case 3: 179 guest_halted = 180 (vmcs_read(GUEST_ACTV_STATE) == ACTV_HLT); 181 report(((rdtsc() - tsc_val) >> preempt_scale) >= preempt_val 182 && guest_halted, 183 "preemption timer during hlt"); 184 vmx_set_test_stage(4); 185 vmcs_write(PIN_CONTROLS, 186 vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 187 vmcs_write(EXI_CONTROLS, 188 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_PREEMPT); 189 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 190 return VMX_TEST_RESUME; 191 case 4: 192 report(saved_rip == guest_rip, 193 "preemption timer with 0 value"); 194 break; 195 default: 196 report_fail("Invalid stage."); 197 print_vmexit_info(exit_reason); 198 break; 199 } 200 break; 201 case VMX_VMCALL: 202 vmcs_write(GUEST_RIP, guest_rip + insn_len); 203 switch (vmx_get_test_stage()) { 204 case 0: 205 report(vmcs_read(PREEMPT_TIMER_VALUE) == preempt_val, 206 "Keep preemption value"); 207 vmx_set_test_stage(1); 208 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 209 ctrl_exit = (vmcs_read(EXI_CONTROLS) | 210 EXI_SAVE_PREEMPT) & ctrl_exit_rev.clr; 211 vmcs_write(EXI_CONTROLS, ctrl_exit); 212 return VMX_TEST_RESUME; 213 case 1: 214 report(vmcs_read(PREEMPT_TIMER_VALUE) < preempt_val, 215 "Save preemption value"); 216 return VMX_TEST_RESUME; 217 case 2: 218 report_fail("busy-wait for preemption timer"); 219 vmx_set_test_stage(3); 220 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 221 return VMX_TEST_RESUME; 222 case 3: 223 report_fail("preemption timer during hlt"); 224 vmx_set_test_stage(4); 225 /* fall through */ 226 case 4: 227 vmcs_write(PIN_CONTROLS, 228 vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 229 vmcs_write(PREEMPT_TIMER_VALUE, 0); 230 saved_rip = guest_rip + insn_len; 231 return VMX_TEST_RESUME; 232 case 5: 233 report_fail("preemption timer with 0 value (vmcall stage 5)"); 234 break; 235 default: 236 // Should not reach here 237 report_fail("unexpected stage, %d", 238 vmx_get_test_stage()); 239 print_vmexit_info(exit_reason); 240 return VMX_TEST_VMEXIT; 241 } 242 break; 243 default: 244 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 245 print_vmexit_info(exit_reason); 246 } 247 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 248 return VMX_TEST_VMEXIT; 249 } 250 251 static void msr_bmp_init(void) 252 { 253 void *msr_bitmap; 254 u32 ctrl_cpu0; 255 256 msr_bitmap = alloc_page(); 257 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 258 ctrl_cpu0 |= CPU_MSR_BITMAP; 259 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 260 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 261 } 262 263 static void *get_msr_bitmap(void) 264 { 265 void *msr_bitmap; 266 267 if (vmcs_read(CPU_EXEC_CTRL0) & CPU_MSR_BITMAP) { 268 msr_bitmap = (void *)vmcs_read(MSR_BITMAP); 269 } else { 270 msr_bitmap = alloc_page(); 271 memset(msr_bitmap, 0xff, PAGE_SIZE); 272 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 273 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_MSR_BITMAP); 274 } 275 276 return msr_bitmap; 277 } 278 279 static void disable_intercept_for_x2apic_msrs(void) 280 { 281 unsigned long *msr_bitmap = (unsigned long *)get_msr_bitmap(); 282 u32 msr; 283 284 for (msr = APIC_BASE_MSR; 285 msr < (APIC_BASE_MSR+0xff); 286 msr += BITS_PER_LONG) { 287 unsigned int word = msr / BITS_PER_LONG; 288 289 msr_bitmap[word] = 0; 290 msr_bitmap[word + (0x800 / sizeof(long))] = 0; 291 } 292 } 293 294 static int test_ctrl_pat_init(struct vmcs *vmcs) 295 { 296 u64 ctrl_ent; 297 u64 ctrl_exi; 298 299 msr_bmp_init(); 300 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT) && 301 !(ctrl_exit_rev.clr & EXI_LOAD_PAT) && 302 !(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 303 printf("\tSave/load PAT is not supported\n"); 304 return 1; 305 } 306 307 ctrl_ent = vmcs_read(ENT_CONTROLS); 308 ctrl_exi = vmcs_read(EXI_CONTROLS); 309 ctrl_ent |= ctrl_enter_rev.clr & ENT_LOAD_PAT; 310 ctrl_exi |= ctrl_exit_rev.clr & (EXI_SAVE_PAT | EXI_LOAD_PAT); 311 vmcs_write(ENT_CONTROLS, ctrl_ent); 312 vmcs_write(EXI_CONTROLS, ctrl_exi); 313 ia32_pat = rdmsr(MSR_IA32_CR_PAT); 314 vmcs_write(GUEST_PAT, 0x0); 315 vmcs_write(HOST_PAT, ia32_pat); 316 return VMX_TEST_START; 317 } 318 319 static void test_ctrl_pat_main(void) 320 { 321 u64 guest_ia32_pat; 322 323 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 324 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) 325 printf("\tENT_LOAD_PAT is not supported.\n"); 326 else { 327 if (guest_ia32_pat != 0) { 328 report_fail("Entry load PAT"); 329 return; 330 } 331 } 332 wrmsr(MSR_IA32_CR_PAT, 0x6); 333 vmcall(); 334 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 335 if (ctrl_enter_rev.clr & ENT_LOAD_PAT) 336 report(guest_ia32_pat == ia32_pat, "Entry load PAT"); 337 } 338 339 static int test_ctrl_pat_exit_handler(union exit_reason exit_reason) 340 { 341 u64 guest_rip; 342 u64 guest_pat; 343 344 guest_rip = vmcs_read(GUEST_RIP); 345 switch (exit_reason.basic) { 346 case VMX_VMCALL: 347 guest_pat = vmcs_read(GUEST_PAT); 348 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT)) { 349 printf("\tEXI_SAVE_PAT is not supported\n"); 350 vmcs_write(GUEST_PAT, 0x6); 351 } else { 352 report(guest_pat == 0x6, "Exit save PAT"); 353 } 354 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) 355 printf("\tEXI_LOAD_PAT is not supported\n"); 356 else 357 report(rdmsr(MSR_IA32_CR_PAT) == ia32_pat, 358 "Exit load PAT"); 359 vmcs_write(GUEST_PAT, ia32_pat); 360 vmcs_write(GUEST_RIP, guest_rip + 3); 361 return VMX_TEST_RESUME; 362 default: 363 printf("ERROR : Unknown exit reason, 0x%x.\n", exit_reason.full); 364 break; 365 } 366 return VMX_TEST_VMEXIT; 367 } 368 369 static int test_ctrl_efer_init(struct vmcs *vmcs) 370 { 371 u64 ctrl_ent; 372 u64 ctrl_exi; 373 374 msr_bmp_init(); 375 ctrl_ent = vmcs_read(ENT_CONTROLS) | ENT_LOAD_EFER; 376 ctrl_exi = vmcs_read(EXI_CONTROLS) | EXI_SAVE_EFER | EXI_LOAD_EFER; 377 vmcs_write(ENT_CONTROLS, ctrl_ent & ctrl_enter_rev.clr); 378 vmcs_write(EXI_CONTROLS, ctrl_exi & ctrl_exit_rev.clr); 379 ia32_efer = rdmsr(MSR_EFER); 380 vmcs_write(GUEST_EFER, ia32_efer ^ EFER_NX); 381 vmcs_write(HOST_EFER, ia32_efer ^ EFER_NX); 382 return VMX_TEST_START; 383 } 384 385 static void test_ctrl_efer_main(void) 386 { 387 u64 guest_ia32_efer; 388 389 guest_ia32_efer = rdmsr(MSR_EFER); 390 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) 391 printf("\tENT_LOAD_EFER is not supported.\n"); 392 else { 393 if (guest_ia32_efer != (ia32_efer ^ EFER_NX)) { 394 report_fail("Entry load EFER"); 395 return; 396 } 397 } 398 wrmsr(MSR_EFER, ia32_efer); 399 vmcall(); 400 guest_ia32_efer = rdmsr(MSR_EFER); 401 if (ctrl_enter_rev.clr & ENT_LOAD_EFER) 402 report(guest_ia32_efer == ia32_efer, "Entry load EFER"); 403 } 404 405 static int test_ctrl_efer_exit_handler(union exit_reason exit_reason) 406 { 407 u64 guest_rip; 408 u64 guest_efer; 409 410 guest_rip = vmcs_read(GUEST_RIP); 411 switch (exit_reason.basic) { 412 case VMX_VMCALL: 413 guest_efer = vmcs_read(GUEST_EFER); 414 if (!(ctrl_exit_rev.clr & EXI_SAVE_EFER)) { 415 printf("\tEXI_SAVE_EFER is not supported\n"); 416 vmcs_write(GUEST_EFER, ia32_efer); 417 } else { 418 report(guest_efer == ia32_efer, "Exit save EFER"); 419 } 420 if (!(ctrl_exit_rev.clr & EXI_LOAD_EFER)) { 421 printf("\tEXI_LOAD_EFER is not supported\n"); 422 wrmsr(MSR_EFER, ia32_efer ^ EFER_NX); 423 } else { 424 report(rdmsr(MSR_EFER) == (ia32_efer ^ EFER_NX), 425 "Exit load EFER"); 426 } 427 vmcs_write(GUEST_PAT, ia32_efer); 428 vmcs_write(GUEST_RIP, guest_rip + 3); 429 return VMX_TEST_RESUME; 430 default: 431 printf("ERROR : Unknown exit reason, 0x%x.\n", exit_reason.full); 432 break; 433 } 434 return VMX_TEST_VMEXIT; 435 } 436 437 u32 guest_cr0, guest_cr4; 438 439 static void cr_shadowing_main(void) 440 { 441 u32 cr0, cr4, tmp; 442 443 // Test read through 444 vmx_set_test_stage(0); 445 guest_cr0 = read_cr0(); 446 if (vmx_get_test_stage() == 1) 447 report_fail("Read through CR0"); 448 else 449 vmcall(); 450 vmx_set_test_stage(1); 451 guest_cr4 = read_cr4(); 452 if (vmx_get_test_stage() == 2) 453 report_fail("Read through CR4"); 454 else 455 vmcall(); 456 // Test write through 457 guest_cr0 = guest_cr0 ^ (X86_CR0_TS | X86_CR0_MP); 458 guest_cr4 = guest_cr4 ^ (X86_CR4_TSD | X86_CR4_DE); 459 vmx_set_test_stage(2); 460 write_cr0(guest_cr0); 461 if (vmx_get_test_stage() == 3) 462 report_fail("Write through CR0"); 463 else 464 vmcall(); 465 vmx_set_test_stage(3); 466 write_cr4(guest_cr4); 467 if (vmx_get_test_stage() == 4) 468 report_fail("Write through CR4"); 469 else 470 vmcall(); 471 // Test read shadow 472 vmx_set_test_stage(4); 473 vmcall(); 474 cr0 = read_cr0(); 475 if (vmx_get_test_stage() != 5) 476 report(cr0 == guest_cr0, "Read shadowing CR0"); 477 vmx_set_test_stage(5); 478 cr4 = read_cr4(); 479 if (vmx_get_test_stage() != 6) 480 report(cr4 == guest_cr4, "Read shadowing CR4"); 481 // Test write shadow (same value with shadow) 482 vmx_set_test_stage(6); 483 write_cr0(guest_cr0); 484 if (vmx_get_test_stage() == 7) 485 report_fail("Write shadowing CR0 (same value with shadow)"); 486 else 487 vmcall(); 488 vmx_set_test_stage(7); 489 write_cr4(guest_cr4); 490 if (vmx_get_test_stage() == 8) 491 report_fail("Write shadowing CR4 (same value with shadow)"); 492 else 493 vmcall(); 494 // Test write shadow (different value) 495 vmx_set_test_stage(8); 496 tmp = guest_cr0 ^ X86_CR0_TS; 497 asm volatile("mov %0, %%rsi\n\t" 498 "mov %%rsi, %%cr0\n\t" 499 ::"m"(tmp) 500 :"rsi", "memory", "cc"); 501 report(vmx_get_test_stage() == 9, 502 "Write shadowing different X86_CR0_TS"); 503 vmx_set_test_stage(9); 504 tmp = guest_cr0 ^ X86_CR0_MP; 505 asm volatile("mov %0, %%rsi\n\t" 506 "mov %%rsi, %%cr0\n\t" 507 ::"m"(tmp) 508 :"rsi", "memory", "cc"); 509 report(vmx_get_test_stage() == 10, 510 "Write shadowing different X86_CR0_MP"); 511 vmx_set_test_stage(10); 512 tmp = guest_cr4 ^ X86_CR4_TSD; 513 asm volatile("mov %0, %%rsi\n\t" 514 "mov %%rsi, %%cr4\n\t" 515 ::"m"(tmp) 516 :"rsi", "memory", "cc"); 517 report(vmx_get_test_stage() == 11, 518 "Write shadowing different X86_CR4_TSD"); 519 vmx_set_test_stage(11); 520 tmp = guest_cr4 ^ X86_CR4_DE; 521 asm volatile("mov %0, %%rsi\n\t" 522 "mov %%rsi, %%cr4\n\t" 523 ::"m"(tmp) 524 :"rsi", "memory", "cc"); 525 report(vmx_get_test_stage() == 12, 526 "Write shadowing different X86_CR4_DE"); 527 } 528 529 static int cr_shadowing_exit_handler(union exit_reason exit_reason) 530 { 531 u64 guest_rip; 532 u32 insn_len; 533 u32 exit_qual; 534 535 guest_rip = vmcs_read(GUEST_RIP); 536 insn_len = vmcs_read(EXI_INST_LEN); 537 exit_qual = vmcs_read(EXI_QUALIFICATION); 538 switch (exit_reason.basic) { 539 case VMX_VMCALL: 540 switch (vmx_get_test_stage()) { 541 case 0: 542 report(guest_cr0 == vmcs_read(GUEST_CR0), 543 "Read through CR0"); 544 break; 545 case 1: 546 report(guest_cr4 == vmcs_read(GUEST_CR4), 547 "Read through CR4"); 548 break; 549 case 2: 550 report(guest_cr0 == vmcs_read(GUEST_CR0), 551 "Write through CR0"); 552 break; 553 case 3: 554 report(guest_cr4 == vmcs_read(GUEST_CR4), 555 "Write through CR4"); 556 break; 557 case 4: 558 guest_cr0 = vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP); 559 guest_cr4 = vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE); 560 vmcs_write(CR0_MASK, X86_CR0_TS | X86_CR0_MP); 561 vmcs_write(CR0_READ_SHADOW, guest_cr0 & (X86_CR0_TS | X86_CR0_MP)); 562 vmcs_write(CR4_MASK, X86_CR4_TSD | X86_CR4_DE); 563 vmcs_write(CR4_READ_SHADOW, guest_cr4 & (X86_CR4_TSD | X86_CR4_DE)); 564 break; 565 case 6: 566 report(guest_cr0 == (vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP)), 567 "Write shadowing CR0 (same value)"); 568 break; 569 case 7: 570 report(guest_cr4 == (vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE)), 571 "Write shadowing CR4 (same value)"); 572 break; 573 default: 574 // Should not reach here 575 report_fail("unexpected stage, %d", 576 vmx_get_test_stage()); 577 print_vmexit_info(exit_reason); 578 return VMX_TEST_VMEXIT; 579 } 580 vmcs_write(GUEST_RIP, guest_rip + insn_len); 581 return VMX_TEST_RESUME; 582 case VMX_CR: 583 switch (vmx_get_test_stage()) { 584 case 4: 585 report_fail("Read shadowing CR0"); 586 vmx_inc_test_stage(); 587 break; 588 case 5: 589 report_fail("Read shadowing CR4"); 590 vmx_inc_test_stage(); 591 break; 592 case 6: 593 report_fail("Write shadowing CR0 (same value)"); 594 vmx_inc_test_stage(); 595 break; 596 case 7: 597 report_fail("Write shadowing CR4 (same value)"); 598 vmx_inc_test_stage(); 599 break; 600 case 8: 601 case 9: 602 // 0x600 encodes "mov %esi, %cr0" 603 if (exit_qual == 0x600) 604 vmx_inc_test_stage(); 605 break; 606 case 10: 607 case 11: 608 // 0x604 encodes "mov %esi, %cr4" 609 if (exit_qual == 0x604) 610 vmx_inc_test_stage(); 611 break; 612 default: 613 // Should not reach here 614 report_fail("unexpected stage, %d", 615 vmx_get_test_stage()); 616 print_vmexit_info(exit_reason); 617 return VMX_TEST_VMEXIT; 618 } 619 vmcs_write(GUEST_RIP, guest_rip + insn_len); 620 return VMX_TEST_RESUME; 621 default: 622 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 623 print_vmexit_info(exit_reason); 624 } 625 return VMX_TEST_VMEXIT; 626 } 627 628 static int iobmp_init(struct vmcs *vmcs) 629 { 630 u32 ctrl_cpu0; 631 632 io_bitmap_a = alloc_page(); 633 io_bitmap_b = alloc_page(); 634 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 635 ctrl_cpu0 |= CPU_IO_BITMAP; 636 ctrl_cpu0 &= (~CPU_IO); 637 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 638 vmcs_write(IO_BITMAP_A, (u64)io_bitmap_a); 639 vmcs_write(IO_BITMAP_B, (u64)io_bitmap_b); 640 return VMX_TEST_START; 641 } 642 643 static void iobmp_main(void) 644 { 645 // stage 0, test IO pass 646 vmx_set_test_stage(0); 647 inb(0x5000); 648 outb(0x0, 0x5000); 649 report(vmx_get_test_stage() == 0, "I/O bitmap - I/O pass"); 650 // test IO width, in/out 651 ((u8 *)io_bitmap_a)[0] = 0xFF; 652 vmx_set_test_stage(2); 653 inb(0x0); 654 report(vmx_get_test_stage() == 3, "I/O bitmap - trap in"); 655 vmx_set_test_stage(3); 656 outw(0x0, 0x0); 657 report(vmx_get_test_stage() == 4, "I/O bitmap - trap out"); 658 vmx_set_test_stage(4); 659 inl(0x0); 660 report(vmx_get_test_stage() == 5, "I/O bitmap - I/O width, long"); 661 // test low/high IO port 662 vmx_set_test_stage(5); 663 ((u8 *)io_bitmap_a)[0x5000 / 8] = (1 << (0x5000 % 8)); 664 inb(0x5000); 665 report(vmx_get_test_stage() == 6, "I/O bitmap - I/O port, low part"); 666 vmx_set_test_stage(6); 667 ((u8 *)io_bitmap_b)[0x1000 / 8] = (1 << (0x1000 % 8)); 668 inb(0x9000); 669 report(vmx_get_test_stage() == 7, "I/O bitmap - I/O port, high part"); 670 // test partial pass 671 vmx_set_test_stage(7); 672 inl(0x4FFF); 673 report(vmx_get_test_stage() == 8, "I/O bitmap - partial pass"); 674 // test overrun 675 vmx_set_test_stage(8); 676 memset(io_bitmap_a, 0x0, PAGE_SIZE); 677 memset(io_bitmap_b, 0x0, PAGE_SIZE); 678 inl(0xFFFF); 679 report(vmx_get_test_stage() == 9, "I/O bitmap - overrun"); 680 vmx_set_test_stage(9); 681 vmcall(); 682 outb(0x0, 0x0); 683 report(vmx_get_test_stage() == 9, 684 "I/O bitmap - ignore unconditional exiting"); 685 vmx_set_test_stage(10); 686 vmcall(); 687 outb(0x0, 0x0); 688 report(vmx_get_test_stage() == 11, 689 "I/O bitmap - unconditional exiting"); 690 } 691 692 static int iobmp_exit_handler(union exit_reason exit_reason) 693 { 694 u64 guest_rip; 695 ulong exit_qual; 696 u32 insn_len, ctrl_cpu0; 697 698 guest_rip = vmcs_read(GUEST_RIP); 699 exit_qual = vmcs_read(EXI_QUALIFICATION); 700 insn_len = vmcs_read(EXI_INST_LEN); 701 switch (exit_reason.basic) { 702 case VMX_IO: 703 switch (vmx_get_test_stage()) { 704 case 0: 705 case 1: 706 vmx_inc_test_stage(); 707 break; 708 case 2: 709 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_BYTE, 710 "I/O bitmap - I/O width, byte"); 711 report(exit_qual & VMX_IO_IN, 712 "I/O bitmap - I/O direction, in"); 713 vmx_inc_test_stage(); 714 break; 715 case 3: 716 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_WORD, 717 "I/O bitmap - I/O width, word"); 718 report(!(exit_qual & VMX_IO_IN), 719 "I/O bitmap - I/O direction, out"); 720 vmx_inc_test_stage(); 721 break; 722 case 4: 723 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_LONG, 724 "I/O bitmap - I/O width, long"); 725 vmx_inc_test_stage(); 726 break; 727 case 5: 728 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x5000) 729 vmx_inc_test_stage(); 730 break; 731 case 6: 732 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x9000) 733 vmx_inc_test_stage(); 734 break; 735 case 7: 736 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x4FFF) 737 vmx_inc_test_stage(); 738 break; 739 case 8: 740 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0xFFFF) 741 vmx_inc_test_stage(); 742 break; 743 case 9: 744 case 10: 745 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 746 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0 & ~CPU_IO); 747 vmx_inc_test_stage(); 748 break; 749 default: 750 // Should not reach here 751 report_fail("unexpected stage, %d", 752 vmx_get_test_stage()); 753 print_vmexit_info(exit_reason); 754 return VMX_TEST_VMEXIT; 755 } 756 vmcs_write(GUEST_RIP, guest_rip + insn_len); 757 return VMX_TEST_RESUME; 758 case VMX_VMCALL: 759 switch (vmx_get_test_stage()) { 760 case 9: 761 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 762 ctrl_cpu0 |= CPU_IO | CPU_IO_BITMAP; 763 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 764 break; 765 case 10: 766 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 767 ctrl_cpu0 = (ctrl_cpu0 & ~CPU_IO_BITMAP) | CPU_IO; 768 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 769 break; 770 default: 771 // Should not reach here 772 report_fail("unexpected stage, %d", 773 vmx_get_test_stage()); 774 print_vmexit_info(exit_reason); 775 return VMX_TEST_VMEXIT; 776 } 777 vmcs_write(GUEST_RIP, guest_rip + insn_len); 778 return VMX_TEST_RESUME; 779 default: 780 printf("guest_rip = %#lx\n", guest_rip); 781 printf("\tERROR : Unknown exit reason, 0x%x\n", exit_reason.full); 782 break; 783 } 784 return VMX_TEST_VMEXIT; 785 } 786 787 #define INSN_CPU0 0 788 #define INSN_CPU1 1 789 #define INSN_ALWAYS_TRAP 2 790 791 #define FIELD_EXIT_QUAL (1 << 0) 792 #define FIELD_INSN_INFO (1 << 1) 793 794 asm( 795 "insn_hlt: hlt;ret\n\t" 796 "insn_invlpg: invlpg 0x12345678;ret\n\t" 797 "insn_mwait: xor %eax, %eax; xor %ecx, %ecx; mwait;ret\n\t" 798 "insn_rdpmc: xor %ecx, %ecx; rdpmc;ret\n\t" 799 "insn_rdtsc: rdtsc;ret\n\t" 800 "insn_cr3_load: mov cr3,%rax; mov %rax,%cr3;ret\n\t" 801 "insn_cr3_store: mov %cr3,%rax;ret\n\t" 802 "insn_cr8_load: xor %eax, %eax; mov %rax,%cr8;ret\n\t" 803 "insn_cr8_store: mov %cr8,%rax;ret\n\t" 804 "insn_monitor: xor %eax, %eax; xor %ecx, %ecx; xor %edx, %edx; monitor;ret\n\t" 805 "insn_pause: pause;ret\n\t" 806 "insn_wbinvd: wbinvd;ret\n\t" 807 "insn_cpuid: mov $10, %eax; cpuid;ret\n\t" 808 "insn_invd: invd;ret\n\t" 809 "insn_sgdt: sgdt gdt_descr;ret\n\t" 810 "insn_lgdt: lgdt gdt_descr;ret\n\t" 811 "insn_sidt: sidt idt_descr;ret\n\t" 812 "insn_lidt: lidt idt_descr;ret\n\t" 813 "insn_sldt: sldt %ax;ret\n\t" 814 "insn_lldt: xor %eax, %eax; lldt %ax;ret\n\t" 815 "insn_str: str %ax;ret\n\t" 816 "insn_rdrand: rdrand %rax;ret\n\t" 817 "insn_rdseed: rdseed %rax;ret\n\t" 818 ); 819 extern void insn_hlt(void); 820 extern void insn_invlpg(void); 821 extern void insn_mwait(void); 822 extern void insn_rdpmc(void); 823 extern void insn_rdtsc(void); 824 extern void insn_cr3_load(void); 825 extern void insn_cr3_store(void); 826 extern void insn_cr8_load(void); 827 extern void insn_cr8_store(void); 828 extern void insn_monitor(void); 829 extern void insn_pause(void); 830 extern void insn_wbinvd(void); 831 extern void insn_sgdt(void); 832 extern void insn_lgdt(void); 833 extern void insn_sidt(void); 834 extern void insn_lidt(void); 835 extern void insn_sldt(void); 836 extern void insn_lldt(void); 837 extern void insn_str(void); 838 extern void insn_cpuid(void); 839 extern void insn_invd(void); 840 extern void insn_rdrand(void); 841 extern void insn_rdseed(void); 842 843 u32 cur_insn; 844 u64 cr3; 845 846 typedef bool (*supported_fn)(void); 847 848 static bool this_cpu_has_mwait(void) 849 { 850 return this_cpu_has(X86_FEATURE_MWAIT); 851 } 852 853 struct insn_table { 854 const char *name; 855 u32 flag; 856 void (*insn_func)(void); 857 u32 type; 858 u32 reason; 859 ulong exit_qual; 860 u32 insn_info; 861 // Use FIELD_EXIT_QUAL and FIELD_INSN_INFO to define 862 // which field need to be tested, reason is always tested 863 u32 test_field; 864 const supported_fn supported_fn; 865 u8 disabled; 866 }; 867 868 /* 869 * Add more test cases of instruction intercept here. Elements in this 870 * table is: 871 * name/control flag/insn function/type/exit reason/exit qulification/ 872 * instruction info/field to test 873 * The last field defines which fields (exit_qual and insn_info) need to be 874 * tested in exit handler. If set to 0, only "reason" is checked. 875 */ 876 static struct insn_table insn_table[] = { 877 // Flags for Primary Processor-Based VM-Execution Controls 878 {"HLT", CPU_HLT, insn_hlt, INSN_CPU0, 12, 0, 0, 0}, 879 {"INVLPG", CPU_INVLPG, insn_invlpg, INSN_CPU0, 14, 880 0x12345678, 0, FIELD_EXIT_QUAL}, 881 {"MWAIT", CPU_MWAIT, insn_mwait, INSN_CPU0, 36, 0, 0, 0, this_cpu_has_mwait}, 882 {"RDPMC", CPU_RDPMC, insn_rdpmc, INSN_CPU0, 15, 0, 0, 0, this_cpu_has_pmu}, 883 {"RDTSC", CPU_RDTSC, insn_rdtsc, INSN_CPU0, 16, 0, 0, 0}, 884 {"CR3 load", CPU_CR3_LOAD, insn_cr3_load, INSN_CPU0, 28, 0x3, 0, 885 FIELD_EXIT_QUAL}, 886 {"CR3 store", CPU_CR3_STORE, insn_cr3_store, INSN_CPU0, 28, 0x13, 0, 887 FIELD_EXIT_QUAL}, 888 {"CR8 load", CPU_CR8_LOAD, insn_cr8_load, INSN_CPU0, 28, 0x8, 0, 889 FIELD_EXIT_QUAL}, 890 {"CR8 store", CPU_CR8_STORE, insn_cr8_store, INSN_CPU0, 28, 0x18, 0, 891 FIELD_EXIT_QUAL}, 892 {"MONITOR", CPU_MONITOR, insn_monitor, INSN_CPU0, 39, 0, 0, 0, this_cpu_has_mwait}, 893 {"PAUSE", CPU_PAUSE, insn_pause, INSN_CPU0, 40, 0, 0, 0}, 894 // Flags for Secondary Processor-Based VM-Execution Controls 895 {"WBINVD", CPU_WBINVD, insn_wbinvd, INSN_CPU1, 54, 0, 0, 0}, 896 {"DESC_TABLE (SGDT)", CPU_DESC_TABLE, insn_sgdt, INSN_CPU1, 46, 0, 0, 0}, 897 {"DESC_TABLE (LGDT)", CPU_DESC_TABLE, insn_lgdt, INSN_CPU1, 46, 0, 0, 0}, 898 {"DESC_TABLE (SIDT)", CPU_DESC_TABLE, insn_sidt, INSN_CPU1, 46, 0, 0, 0}, 899 {"DESC_TABLE (LIDT)", CPU_DESC_TABLE, insn_lidt, INSN_CPU1, 46, 0, 0, 0}, 900 {"DESC_TABLE (SLDT)", CPU_DESC_TABLE, insn_sldt, INSN_CPU1, 47, 0, 0, 0}, 901 {"DESC_TABLE (LLDT)", CPU_DESC_TABLE, insn_lldt, INSN_CPU1, 47, 0, 0, 0}, 902 {"DESC_TABLE (STR)", CPU_DESC_TABLE, insn_str, INSN_CPU1, 47, 0, 0, 0}, 903 /* LTR causes a #GP if done with a busy selector, so it is not tested. */ 904 {"RDRAND", CPU_RDRAND, insn_rdrand, INSN_CPU1, VMX_RDRAND, 0, 0, 0}, 905 {"RDSEED", CPU_RDSEED, insn_rdseed, INSN_CPU1, VMX_RDSEED, 0, 0, 0}, 906 // Instructions always trap 907 {"CPUID", 0, insn_cpuid, INSN_ALWAYS_TRAP, 10, 0, 0, 0}, 908 {"INVD", 0, insn_invd, INSN_ALWAYS_TRAP, 13, 0, 0, 0}, 909 // Instructions never trap 910 {NULL}, 911 }; 912 913 static int insn_intercept_init(struct vmcs *vmcs) 914 { 915 u32 ctrl_cpu, cur_insn; 916 917 ctrl_cpu = ctrl_cpu_rev[0].set | CPU_SECONDARY; 918 ctrl_cpu &= ctrl_cpu_rev[0].clr; 919 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu); 920 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu_rev[1].set); 921 cr3 = read_cr3(); 922 923 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 924 if (insn_table[cur_insn].supported_fn == NULL) 925 continue; 926 insn_table[cur_insn].disabled = !insn_table[cur_insn].supported_fn(); 927 } 928 return VMX_TEST_START; 929 } 930 931 static void insn_intercept_main(void) 932 { 933 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 934 vmx_set_test_stage(cur_insn * 2); 935 if ((insn_table[cur_insn].type == INSN_CPU0 && 936 !(ctrl_cpu_rev[0].clr & insn_table[cur_insn].flag)) || 937 (insn_table[cur_insn].type == INSN_CPU1 && 938 !(ctrl_cpu_rev[1].clr & insn_table[cur_insn].flag))) { 939 printf("\tCPU_CTRL%d.CPU_%s is not supported.\n", 940 insn_table[cur_insn].type - INSN_CPU0, 941 insn_table[cur_insn].name); 942 continue; 943 } 944 945 if (insn_table[cur_insn].disabled) { 946 printf("\tFeature required for %s is not supported.\n", 947 insn_table[cur_insn].name); 948 continue; 949 } 950 951 if ((insn_table[cur_insn].type == INSN_CPU0 && 952 !(ctrl_cpu_rev[0].set & insn_table[cur_insn].flag)) || 953 (insn_table[cur_insn].type == INSN_CPU1 && 954 !(ctrl_cpu_rev[1].set & insn_table[cur_insn].flag))) { 955 /* skip hlt, it stalls the guest and is tested below */ 956 if (insn_table[cur_insn].insn_func != insn_hlt) 957 insn_table[cur_insn].insn_func(); 958 report(vmx_get_test_stage() == cur_insn * 2, 959 "execute %s", 960 insn_table[cur_insn].name); 961 } else if (insn_table[cur_insn].type != INSN_ALWAYS_TRAP) 962 printf("\tCPU_CTRL%d.CPU_%s always traps.\n", 963 insn_table[cur_insn].type - INSN_CPU0, 964 insn_table[cur_insn].name); 965 966 vmcall(); 967 968 insn_table[cur_insn].insn_func(); 969 report(vmx_get_test_stage() == cur_insn * 2 + 1, 970 "intercept %s", 971 insn_table[cur_insn].name); 972 973 vmx_set_test_stage(cur_insn * 2 + 1); 974 vmcall(); 975 } 976 } 977 978 static int insn_intercept_exit_handler(union exit_reason exit_reason) 979 { 980 u64 guest_rip; 981 ulong exit_qual; 982 u32 insn_len; 983 u32 insn_info; 984 bool pass; 985 986 guest_rip = vmcs_read(GUEST_RIP); 987 exit_qual = vmcs_read(EXI_QUALIFICATION); 988 insn_len = vmcs_read(EXI_INST_LEN); 989 insn_info = vmcs_read(EXI_INST_INFO); 990 991 if (exit_reason.basic == VMX_VMCALL) { 992 u32 val = 0; 993 994 if (insn_table[cur_insn].type == INSN_CPU0) 995 val = vmcs_read(CPU_EXEC_CTRL0); 996 else if (insn_table[cur_insn].type == INSN_CPU1) 997 val = vmcs_read(CPU_EXEC_CTRL1); 998 999 if (vmx_get_test_stage() & 1) 1000 val &= ~insn_table[cur_insn].flag; 1001 else 1002 val |= insn_table[cur_insn].flag; 1003 1004 if (insn_table[cur_insn].type == INSN_CPU0) 1005 vmcs_write(CPU_EXEC_CTRL0, val | ctrl_cpu_rev[0].set); 1006 else if (insn_table[cur_insn].type == INSN_CPU1) 1007 vmcs_write(CPU_EXEC_CTRL1, val | ctrl_cpu_rev[1].set); 1008 } else { 1009 pass = (cur_insn * 2 == vmx_get_test_stage()) && 1010 insn_table[cur_insn].reason == exit_reason.full; 1011 if (insn_table[cur_insn].test_field & FIELD_EXIT_QUAL && 1012 insn_table[cur_insn].exit_qual != exit_qual) 1013 pass = false; 1014 if (insn_table[cur_insn].test_field & FIELD_INSN_INFO && 1015 insn_table[cur_insn].insn_info != insn_info) 1016 pass = false; 1017 if (pass) 1018 vmx_inc_test_stage(); 1019 } 1020 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1021 return VMX_TEST_RESUME; 1022 } 1023 1024 /** 1025 * __setup_ept - Setup the VMCS fields to enable Extended Page Tables (EPT) 1026 * @hpa: Host physical address of the top-level, a.k.a. root, EPT table 1027 * @enable_ad: Whether or not to enable Access/Dirty bits for EPT entries 1028 * 1029 * Returns 0 on success, 1 on failure. 1030 * 1031 * Note that @hpa doesn't need to point at actual memory if VM-Launch is 1032 * expected to fail, e.g. setup_dummy_ept() arbitrarily passes '0' to satisfy 1033 * the various EPTP consistency checks, but doesn't ensure backing for HPA '0'. 1034 */ 1035 static int __setup_ept(u64 hpa, bool enable_ad) 1036 { 1037 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1038 !(ctrl_cpu_rev[1].clr & CPU_EPT)) { 1039 printf("\tEPT is not supported\n"); 1040 return 1; 1041 } 1042 if (!is_ept_memtype_supported(EPT_MEM_TYPE_WB)) { 1043 printf("\tWB memtype for EPT walks not supported\n"); 1044 return 1; 1045 } 1046 1047 if (!is_4_level_ept_supported()) { 1048 /* Support for 4-level EPT is mandatory. */ 1049 report(false, "4-level EPT support check"); 1050 printf("\tPWL4 is not supported\n"); 1051 return 1; 1052 } 1053 1054 eptp = EPT_MEM_TYPE_WB; 1055 eptp |= (3 << EPTP_PG_WALK_LEN_SHIFT); 1056 eptp |= hpa; 1057 if (enable_ad) 1058 eptp |= EPTP_AD_FLAG; 1059 1060 vmcs_write(EPTP, eptp); 1061 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0)| CPU_SECONDARY); 1062 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1)| CPU_EPT); 1063 1064 return 0; 1065 } 1066 1067 /** 1068 * setup_ept - Enable Extended Page Tables (EPT) and setup an identity map 1069 * @enable_ad: Whether or not to enable Access/Dirty bits for EPT entries 1070 * 1071 * Returns 0 on success, 1 on failure. 1072 * 1073 * This is the "real" function for setting up EPT tables, i.e. use this for 1074 * tests that need to run code in the guest with EPT enabled. 1075 */ 1076 static int setup_ept(bool enable_ad) 1077 { 1078 unsigned long end_of_memory; 1079 1080 pml4 = alloc_page(); 1081 1082 if (__setup_ept(virt_to_phys(pml4), enable_ad)) 1083 return 1; 1084 1085 end_of_memory = fwcfg_get_u64(FW_CFG_RAM_SIZE); 1086 if (end_of_memory < (1ul << 32)) 1087 end_of_memory = (1ul << 32); 1088 /* Cannot use large EPT pages if we need to track EPT 1089 * accessed/dirty bits at 4K granularity. 1090 */ 1091 setup_ept_range(pml4, 0, end_of_memory, 0, 1092 !enable_ad && ept_2m_supported(), 1093 EPT_WA | EPT_RA | EPT_EA); 1094 return 0; 1095 } 1096 1097 /** 1098 * setup_dummy_ept - Enable Extended Page Tables (EPT) with a dummy root HPA 1099 * 1100 * Setup EPT using a semi-arbitrary dummy root HPA. This function is intended 1101 * for use by tests that need EPT enabled to verify dependent VMCS controls 1102 * but never expect to fully enter the guest, i.e. don't need setup the actual 1103 * EPT tables. 1104 */ 1105 static void setup_dummy_ept(void) 1106 { 1107 if (__setup_ept(0, false)) 1108 report_abort("EPT setup unexpectedly failed"); 1109 } 1110 1111 static int enable_unrestricted_guest(bool need_valid_ept) 1112 { 1113 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1114 !(ctrl_cpu_rev[1].clr & CPU_URG) || 1115 !(ctrl_cpu_rev[1].clr & CPU_EPT)) 1116 return 1; 1117 1118 if (need_valid_ept) 1119 setup_ept(false); 1120 else 1121 setup_dummy_ept(); 1122 1123 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 1124 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | CPU_URG); 1125 1126 return 0; 1127 } 1128 1129 static void ept_enable_ad_bits(void) 1130 { 1131 eptp |= EPTP_AD_FLAG; 1132 vmcs_write(EPTP, eptp); 1133 } 1134 1135 static void ept_disable_ad_bits(void) 1136 { 1137 eptp &= ~EPTP_AD_FLAG; 1138 vmcs_write(EPTP, eptp); 1139 } 1140 1141 static int ept_ad_enabled(void) 1142 { 1143 return eptp & EPTP_AD_FLAG; 1144 } 1145 1146 static void ept_enable_ad_bits_or_skip_test(void) 1147 { 1148 if (!ept_ad_bits_supported()) 1149 test_skip("EPT AD bits not supported."); 1150 ept_enable_ad_bits(); 1151 } 1152 1153 static int apic_version; 1154 1155 static int ept_init_common(bool have_ad) 1156 { 1157 int ret; 1158 struct pci_dev pcidev; 1159 1160 /* INVEPT is required by the EPT violation handler. */ 1161 if (!is_invept_type_supported(INVEPT_SINGLE)) 1162 return VMX_TEST_EXIT; 1163 1164 if (setup_ept(have_ad)) 1165 return VMX_TEST_EXIT; 1166 1167 data_page1 = alloc_page(); 1168 data_page2 = alloc_page(); 1169 *((u32 *)data_page1) = MAGIC_VAL_1; 1170 *((u32 *)data_page2) = MAGIC_VAL_2; 1171 install_ept(pml4, (unsigned long)data_page1, (unsigned long)data_page2, 1172 EPT_RA | EPT_WA | EPT_EA); 1173 1174 apic_version = apic_read(APIC_LVR); 1175 1176 ret = pci_find_dev(PCI_VENDOR_ID_REDHAT, PCI_DEVICE_ID_REDHAT_TEST); 1177 if (ret != PCIDEVADDR_INVALID) { 1178 pci_dev_init(&pcidev, ret); 1179 pci_physaddr = pcidev.resource[PCI_TESTDEV_BAR_MEM]; 1180 } 1181 1182 return VMX_TEST_START; 1183 } 1184 1185 static int ept_init(struct vmcs *vmcs) 1186 { 1187 return ept_init_common(false); 1188 } 1189 1190 static void ept_common(void) 1191 { 1192 vmx_set_test_stage(0); 1193 if (*((u32 *)data_page2) != MAGIC_VAL_1 || 1194 *((u32 *)data_page1) != MAGIC_VAL_1) 1195 report_fail("EPT basic framework - read"); 1196 else { 1197 *((u32 *)data_page2) = MAGIC_VAL_3; 1198 vmcall(); 1199 if (vmx_get_test_stage() == 1) { 1200 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1201 *((u32 *)data_page2) == MAGIC_VAL_2) 1202 report_pass("EPT basic framework"); 1203 else 1204 report_pass("EPT basic framework - remap"); 1205 } 1206 } 1207 // Test EPT Misconfigurations 1208 vmx_set_test_stage(1); 1209 vmcall(); 1210 *((u32 *)data_page1) = MAGIC_VAL_1; 1211 if (vmx_get_test_stage() != 2) { 1212 report_fail("EPT misconfigurations"); 1213 goto t1; 1214 } 1215 vmx_set_test_stage(2); 1216 vmcall(); 1217 *((u32 *)data_page1) = MAGIC_VAL_1; 1218 report(vmx_get_test_stage() == 3, "EPT misconfigurations"); 1219 t1: 1220 // Test EPT violation 1221 vmx_set_test_stage(3); 1222 vmcall(); 1223 *((u32 *)data_page1) = MAGIC_VAL_1; 1224 report(vmx_get_test_stage() == 4, "EPT violation - page permission"); 1225 // Violation caused by EPT paging structure 1226 vmx_set_test_stage(4); 1227 vmcall(); 1228 *((u32 *)data_page1) = MAGIC_VAL_2; 1229 report(vmx_get_test_stage() == 5, "EPT violation - paging structure"); 1230 1231 // MMIO Read/Write 1232 vmx_set_test_stage(5); 1233 vmcall(); 1234 1235 *(u32 volatile *)pci_physaddr; 1236 report(vmx_get_test_stage() == 6, "MMIO EPT violation - read"); 1237 1238 *(u32 volatile *)pci_physaddr = MAGIC_VAL_1; 1239 report(vmx_get_test_stage() == 7, "MMIO EPT violation - write"); 1240 } 1241 1242 static void ept_main(void) 1243 { 1244 ept_common(); 1245 1246 // Test EPT access to L1 MMIO 1247 vmx_set_test_stage(7); 1248 report(*((u32 *)0xfee00030UL) == apic_version, "EPT - MMIO access"); 1249 1250 // Test invalid operand for INVEPT 1251 vmcall(); 1252 report(vmx_get_test_stage() == 8, "EPT - unsupported INVEPT"); 1253 } 1254 1255 static bool invept_test(int type, u64 eptp) 1256 { 1257 bool ret, supported; 1258 1259 supported = ept_vpid.val & (EPT_CAP_INVEPT_SINGLE >> INVEPT_SINGLE << type); 1260 ret = __invept(type, eptp); 1261 1262 if (ret == !supported) 1263 return false; 1264 1265 if (!supported) 1266 printf("WARNING: unsupported invept passed!\n"); 1267 else 1268 printf("WARNING: invept failed!\n"); 1269 1270 return true; 1271 } 1272 1273 static int pml_exit_handler(union exit_reason exit_reason) 1274 { 1275 u16 index, count; 1276 u64 *pmlbuf = pml_log; 1277 u64 guest_rip = vmcs_read(GUEST_RIP);; 1278 u64 guest_cr3 = vmcs_read(GUEST_CR3); 1279 u32 insn_len = vmcs_read(EXI_INST_LEN); 1280 1281 switch (exit_reason.basic) { 1282 case VMX_VMCALL: 1283 switch (vmx_get_test_stage()) { 1284 case 0: 1285 index = vmcs_read(GUEST_PML_INDEX); 1286 for (count = index + 1; count < PML_INDEX; count++) { 1287 if (pmlbuf[count] == (u64)data_page2) { 1288 vmx_inc_test_stage(); 1289 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1290 break; 1291 } 1292 } 1293 break; 1294 case 1: 1295 index = vmcs_read(GUEST_PML_INDEX); 1296 /* Keep clearing the dirty bit till a overflow */ 1297 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1298 break; 1299 default: 1300 report_fail("unexpected stage, %d.", 1301 vmx_get_test_stage()); 1302 print_vmexit_info(exit_reason); 1303 return VMX_TEST_VMEXIT; 1304 } 1305 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1306 return VMX_TEST_RESUME; 1307 case VMX_PML_FULL: 1308 vmx_inc_test_stage(); 1309 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1310 return VMX_TEST_RESUME; 1311 default: 1312 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 1313 print_vmexit_info(exit_reason); 1314 } 1315 return VMX_TEST_VMEXIT; 1316 } 1317 1318 static int ept_exit_handler_common(union exit_reason exit_reason, bool have_ad) 1319 { 1320 u64 guest_rip; 1321 u64 guest_cr3; 1322 u32 insn_len; 1323 u32 exit_qual; 1324 static unsigned long data_page1_pte, data_page1_pte_pte, memaddr_pte, 1325 guest_pte_addr; 1326 1327 guest_rip = vmcs_read(GUEST_RIP); 1328 guest_cr3 = vmcs_read(GUEST_CR3); 1329 insn_len = vmcs_read(EXI_INST_LEN); 1330 exit_qual = vmcs_read(EXI_QUALIFICATION); 1331 pteval_t *ptep; 1332 switch (exit_reason.basic) { 1333 case VMX_VMCALL: 1334 switch (vmx_get_test_stage()) { 1335 case 0: 1336 check_ept_ad(pml4, guest_cr3, 1337 (unsigned long)data_page1, 1338 have_ad ? EPT_ACCESS_FLAG : 0, 1339 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1340 check_ept_ad(pml4, guest_cr3, 1341 (unsigned long)data_page2, 1342 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0, 1343 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1344 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1345 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1346 if (have_ad) 1347 invept(INVEPT_SINGLE, eptp); 1348 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1349 *((u32 *)data_page2) == MAGIC_VAL_2) { 1350 vmx_inc_test_stage(); 1351 install_ept(pml4, (unsigned long)data_page2, 1352 (unsigned long)data_page2, 1353 EPT_RA | EPT_WA | EPT_EA); 1354 } else 1355 report_fail("EPT basic framework - write"); 1356 break; 1357 case 1: 1358 install_ept(pml4, (unsigned long)data_page1, 1359 (unsigned long)data_page1, EPT_WA); 1360 invept(INVEPT_SINGLE, eptp); 1361 break; 1362 case 2: 1363 install_ept(pml4, (unsigned long)data_page1, 1364 (unsigned long)data_page1, 1365 EPT_RA | EPT_WA | EPT_EA | 1366 (2 << EPT_MEM_TYPE_SHIFT)); 1367 invept(INVEPT_SINGLE, eptp); 1368 break; 1369 case 3: 1370 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1371 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)data_page1, 1372 1, &data_page1_pte)); 1373 set_ept_pte(pml4, (unsigned long)data_page1, 1374 1, data_page1_pte & ~EPT_PRESENT); 1375 invept(INVEPT_SINGLE, eptp); 1376 break; 1377 case 4: 1378 ptep = get_pte_level((pgd_t *)guest_cr3, data_page1, /*level=*/2); 1379 guest_pte_addr = virt_to_phys(ptep) & PAGE_MASK; 1380 1381 TEST_ASSERT(get_ept_pte(pml4, guest_pte_addr, 2, &data_page1_pte_pte)); 1382 set_ept_pte(pml4, guest_pte_addr, 2, 1383 data_page1_pte_pte & ~EPT_PRESENT); 1384 invept(INVEPT_SINGLE, eptp); 1385 break; 1386 case 5: 1387 install_ept(pml4, (unsigned long)pci_physaddr, 1388 (unsigned long)pci_physaddr, 0); 1389 invept(INVEPT_SINGLE, eptp); 1390 break; 1391 case 7: 1392 if (!invept_test(0, eptp)) 1393 vmx_inc_test_stage(); 1394 break; 1395 // Should not reach here 1396 default: 1397 report_fail("ERROR - unexpected stage, %d.", 1398 vmx_get_test_stage()); 1399 print_vmexit_info(exit_reason); 1400 return VMX_TEST_VMEXIT; 1401 } 1402 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1403 return VMX_TEST_RESUME; 1404 case VMX_EPT_MISCONFIG: 1405 switch (vmx_get_test_stage()) { 1406 case 1: 1407 case 2: 1408 vmx_inc_test_stage(); 1409 install_ept(pml4, (unsigned long)data_page1, 1410 (unsigned long)data_page1, 1411 EPT_RA | EPT_WA | EPT_EA); 1412 invept(INVEPT_SINGLE, eptp); 1413 break; 1414 // Should not reach here 1415 default: 1416 report_fail("ERROR - unexpected stage, %d.", 1417 vmx_get_test_stage()); 1418 print_vmexit_info(exit_reason); 1419 return VMX_TEST_VMEXIT; 1420 } 1421 return VMX_TEST_RESUME; 1422 case VMX_EPT_VIOLATION: 1423 /* 1424 * Exit-qualifications are masked not to account for advanced 1425 * VM-exit information. Once KVM supports this feature, this 1426 * masking should be removed. 1427 */ 1428 exit_qual &= ~EPT_VLT_GUEST_MASK; 1429 1430 switch(vmx_get_test_stage()) { 1431 case 3: 1432 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1433 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1434 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1435 if (exit_qual == (EPT_VLT_WR | EPT_VLT_LADDR_VLD | 1436 EPT_VLT_PADDR)) 1437 vmx_inc_test_stage(); 1438 set_ept_pte(pml4, (unsigned long)data_page1, 1439 1, data_page1_pte | (EPT_PRESENT)); 1440 invept(INVEPT_SINGLE, eptp); 1441 break; 1442 case 4: 1443 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1444 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1445 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1446 if (exit_qual == (EPT_VLT_RD | 1447 (have_ad ? EPT_VLT_WR : 0) | 1448 EPT_VLT_LADDR_VLD)) 1449 vmx_inc_test_stage(); 1450 set_ept_pte(pml4, guest_pte_addr, 2, 1451 data_page1_pte_pte | (EPT_PRESENT)); 1452 invept(INVEPT_SINGLE, eptp); 1453 break; 1454 case 5: 1455 if (exit_qual & EPT_VLT_RD) 1456 vmx_inc_test_stage(); 1457 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1458 1, &memaddr_pte)); 1459 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA); 1460 invept(INVEPT_SINGLE, eptp); 1461 break; 1462 case 6: 1463 if (exit_qual & EPT_VLT_WR) 1464 vmx_inc_test_stage(); 1465 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1466 1, &memaddr_pte)); 1467 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA | EPT_WA); 1468 invept(INVEPT_SINGLE, eptp); 1469 break; 1470 default: 1471 // Should not reach here 1472 report_fail("ERROR : unexpected stage, %d", 1473 vmx_get_test_stage()); 1474 print_vmexit_info(exit_reason); 1475 return VMX_TEST_VMEXIT; 1476 } 1477 return VMX_TEST_RESUME; 1478 default: 1479 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 1480 print_vmexit_info(exit_reason); 1481 } 1482 return VMX_TEST_VMEXIT; 1483 } 1484 1485 static int ept_exit_handler(union exit_reason exit_reason) 1486 { 1487 return ept_exit_handler_common(exit_reason, false); 1488 } 1489 1490 static int eptad_init(struct vmcs *vmcs) 1491 { 1492 int r = ept_init_common(true); 1493 1494 if (r == VMX_TEST_EXIT) 1495 return r; 1496 1497 if (!ept_ad_bits_supported()) { 1498 printf("\tEPT A/D bits are not supported"); 1499 return VMX_TEST_EXIT; 1500 } 1501 1502 return r; 1503 } 1504 1505 static int pml_init(struct vmcs *vmcs) 1506 { 1507 u32 ctrl_cpu; 1508 int r = eptad_init(vmcs); 1509 1510 if (r == VMX_TEST_EXIT) 1511 return r; 1512 1513 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1514 !(ctrl_cpu_rev[1].clr & CPU_PML)) { 1515 printf("\tPML is not supported"); 1516 return VMX_TEST_EXIT; 1517 } 1518 1519 pml_log = alloc_page(); 1520 vmcs_write(PMLADDR, (u64)pml_log); 1521 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1522 1523 ctrl_cpu = vmcs_read(CPU_EXEC_CTRL1) | CPU_PML; 1524 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu); 1525 1526 return VMX_TEST_START; 1527 } 1528 1529 static void pml_main(void) 1530 { 1531 int count = 0; 1532 1533 vmx_set_test_stage(0); 1534 *((u32 *)data_page2) = 0x1; 1535 vmcall(); 1536 report(vmx_get_test_stage() == 1, "PML - Dirty GPA Logging"); 1537 1538 while (vmx_get_test_stage() == 1) { 1539 vmcall(); 1540 *((u32 *)data_page2) = 0x1; 1541 if (count++ > PML_INDEX) 1542 break; 1543 } 1544 report(vmx_get_test_stage() == 2, "PML Full Event"); 1545 } 1546 1547 static void eptad_main(void) 1548 { 1549 ept_common(); 1550 } 1551 1552 static int eptad_exit_handler(union exit_reason exit_reason) 1553 { 1554 return ept_exit_handler_common(exit_reason, true); 1555 } 1556 1557 #define TIMER_VECTOR 222 1558 1559 static volatile bool timer_fired; 1560 1561 static void timer_isr(isr_regs_t *regs) 1562 { 1563 timer_fired = true; 1564 apic_write(APIC_EOI, 0); 1565 } 1566 1567 static int interrupt_init(struct vmcs *vmcs) 1568 { 1569 msr_bmp_init(); 1570 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1571 handle_irq(TIMER_VECTOR, timer_isr); 1572 return VMX_TEST_START; 1573 } 1574 1575 static void interrupt_main(void) 1576 { 1577 long long start, loops; 1578 1579 vmx_set_test_stage(0); 1580 1581 apic_write(APIC_LVTT, TIMER_VECTOR); 1582 sti(); 1583 1584 apic_write(APIC_TMICT, 1); 1585 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1586 asm volatile ("nop"); 1587 report(timer_fired, "direct interrupt while running guest"); 1588 1589 apic_write(APIC_TMICT, 0); 1590 cli(); 1591 vmcall(); 1592 timer_fired = false; 1593 apic_write(APIC_TMICT, 1); 1594 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1595 asm volatile ("nop"); 1596 report(timer_fired, "intercepted interrupt while running guest"); 1597 1598 sti(); 1599 apic_write(APIC_TMICT, 0); 1600 cli(); 1601 vmcall(); 1602 timer_fired = false; 1603 start = rdtsc(); 1604 apic_write(APIC_TMICT, 1000000); 1605 1606 safe_halt(); 1607 1608 report(rdtsc() - start > 1000000 && timer_fired, 1609 "direct interrupt + hlt"); 1610 1611 apic_write(APIC_TMICT, 0); 1612 cli(); 1613 vmcall(); 1614 timer_fired = false; 1615 start = rdtsc(); 1616 apic_write(APIC_TMICT, 1000000); 1617 1618 safe_halt(); 1619 1620 report(rdtsc() - start > 10000 && timer_fired, 1621 "intercepted interrupt + hlt"); 1622 1623 apic_write(APIC_TMICT, 0); 1624 cli(); 1625 vmcall(); 1626 timer_fired = false; 1627 start = rdtsc(); 1628 apic_write(APIC_TMICT, 1000000); 1629 1630 sti_nop(); 1631 vmcall(); 1632 1633 report(rdtsc() - start > 10000 && timer_fired, 1634 "direct interrupt + activity state hlt"); 1635 1636 apic_write(APIC_TMICT, 0); 1637 cli(); 1638 vmcall(); 1639 timer_fired = false; 1640 start = rdtsc(); 1641 apic_write(APIC_TMICT, 1000000); 1642 1643 sti_nop(); 1644 vmcall(); 1645 1646 report(rdtsc() - start > 10000 && timer_fired, 1647 "intercepted interrupt + activity state hlt"); 1648 1649 apic_write(APIC_TMICT, 0); 1650 cli(); 1651 vmx_set_test_stage(7); 1652 vmcall(); 1653 timer_fired = false; 1654 apic_write(APIC_TMICT, 1); 1655 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1656 asm volatile ("nop"); 1657 report(timer_fired, 1658 "running a guest with interrupt acknowledgement set"); 1659 1660 apic_write(APIC_TMICT, 0); 1661 sti(); 1662 timer_fired = false; 1663 vmcall(); 1664 report(timer_fired, "Inject an event to a halted guest"); 1665 } 1666 1667 static int interrupt_exit_handler(union exit_reason exit_reason) 1668 { 1669 u64 guest_rip = vmcs_read(GUEST_RIP); 1670 u32 insn_len = vmcs_read(EXI_INST_LEN); 1671 1672 switch (exit_reason.basic) { 1673 case VMX_VMCALL: 1674 switch (vmx_get_test_stage()) { 1675 case 0: 1676 case 2: 1677 case 5: 1678 vmcs_write(PIN_CONTROLS, 1679 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1680 break; 1681 case 7: 1682 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_INTA); 1683 vmcs_write(PIN_CONTROLS, 1684 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1685 break; 1686 case 1: 1687 case 3: 1688 vmcs_write(PIN_CONTROLS, 1689 vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1690 break; 1691 case 4: 1692 case 6: 1693 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1694 break; 1695 1696 case 8: 1697 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1698 vmcs_write(ENT_INTR_INFO, 1699 TIMER_VECTOR | 1700 (VMX_INTR_TYPE_EXT_INTR << INTR_INFO_INTR_TYPE_SHIFT) | 1701 INTR_INFO_VALID_MASK); 1702 break; 1703 } 1704 vmx_inc_test_stage(); 1705 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1706 return VMX_TEST_RESUME; 1707 case VMX_EXTINT: 1708 if (vmcs_read(EXI_CONTROLS) & EXI_INTA) { 1709 int vector = vmcs_read(EXI_INTR_INFO) & 0xff; 1710 handle_external_interrupt(vector); 1711 } else { 1712 sti_nop_cli(); 1713 } 1714 if (vmx_get_test_stage() >= 2) 1715 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 1716 return VMX_TEST_RESUME; 1717 default: 1718 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 1719 print_vmexit_info(exit_reason); 1720 } 1721 1722 return VMX_TEST_VMEXIT; 1723 } 1724 1725 1726 static volatile int nmi_fired; 1727 1728 #define NMI_DELAY 100000000ULL 1729 1730 static void nmi_isr(isr_regs_t *regs) 1731 { 1732 nmi_fired = true; 1733 } 1734 1735 static int nmi_hlt_init(struct vmcs *vmcs) 1736 { 1737 msr_bmp_init(); 1738 handle_irq(NMI_VECTOR, nmi_isr); 1739 vmcs_write(PIN_CONTROLS, 1740 vmcs_read(PIN_CONTROLS) & ~PIN_NMI); 1741 vmcs_write(PIN_CONTROLS, 1742 vmcs_read(PIN_CONTROLS) & ~PIN_VIRT_NMI); 1743 return VMX_TEST_START; 1744 } 1745 1746 static void nmi_message_thread(void *data) 1747 { 1748 while (vmx_get_test_stage() != 1) 1749 pause(); 1750 1751 delay(NMI_DELAY); 1752 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_NMI | APIC_INT_ASSERT, id_map[0]); 1753 1754 while (vmx_get_test_stage() != 2) 1755 pause(); 1756 1757 delay(NMI_DELAY); 1758 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_NMI | APIC_INT_ASSERT, id_map[0]); 1759 } 1760 1761 static void nmi_hlt_main(void) 1762 { 1763 long long start; 1764 1765 if (cpu_count() < 2) { 1766 report_skip("%s : CPU count < 2", __func__); 1767 vmx_set_test_stage(-1); 1768 return; 1769 } 1770 1771 vmx_set_test_stage(0); 1772 on_cpu_async(1, nmi_message_thread, NULL); 1773 start = rdtsc(); 1774 vmx_set_test_stage(1); 1775 asm volatile ("hlt"); 1776 report((rdtsc() - start > NMI_DELAY) && nmi_fired, 1777 "direct NMI + hlt"); 1778 if (!nmi_fired) 1779 vmx_set_test_stage(-1); 1780 nmi_fired = false; 1781 1782 vmcall(); 1783 1784 start = rdtsc(); 1785 vmx_set_test_stage(2); 1786 asm volatile ("hlt"); 1787 report((rdtsc() - start > NMI_DELAY) && !nmi_fired, 1788 "intercepted NMI + hlt"); 1789 if (nmi_fired) { 1790 report(!nmi_fired, "intercepted NMI was dispatched"); 1791 vmx_set_test_stage(-1); 1792 return; 1793 } 1794 vmx_set_test_stage(3); 1795 } 1796 1797 static int nmi_hlt_exit_handler(union exit_reason exit_reason) 1798 { 1799 u64 guest_rip = vmcs_read(GUEST_RIP); 1800 u32 insn_len = vmcs_read(EXI_INST_LEN); 1801 1802 switch (vmx_get_test_stage()) { 1803 case 1: 1804 if (exit_reason.basic != VMX_VMCALL) { 1805 report_fail("VMEXIT not due to vmcall. Exit reason 0x%x", 1806 exit_reason.full); 1807 print_vmexit_info(exit_reason); 1808 return VMX_TEST_VMEXIT; 1809 } 1810 1811 vmcs_write(PIN_CONTROLS, 1812 vmcs_read(PIN_CONTROLS) | PIN_NMI); 1813 vmcs_write(PIN_CONTROLS, 1814 vmcs_read(PIN_CONTROLS) | PIN_VIRT_NMI); 1815 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1816 break; 1817 1818 case 2: 1819 if (exit_reason.basic != VMX_EXC_NMI) { 1820 report_fail("VMEXIT not due to NMI intercept. Exit reason 0x%x", 1821 exit_reason.full); 1822 print_vmexit_info(exit_reason); 1823 return VMX_TEST_VMEXIT; 1824 } 1825 report_pass("NMI intercept while running guest"); 1826 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 1827 break; 1828 1829 case 3: 1830 break; 1831 1832 default: 1833 return VMX_TEST_VMEXIT; 1834 } 1835 1836 if (vmx_get_test_stage() == 3) 1837 return VMX_TEST_VMEXIT; 1838 1839 return VMX_TEST_RESUME; 1840 } 1841 1842 1843 static int dbgctls_init(struct vmcs *vmcs) 1844 { 1845 u64 dr7 = 0x402; 1846 u64 zero = 0; 1847 1848 msr_bmp_init(); 1849 asm volatile( 1850 "mov %0,%%dr0\n\t" 1851 "mov %0,%%dr1\n\t" 1852 "mov %0,%%dr2\n\t" 1853 "mov %1,%%dr7\n\t" 1854 : : "r" (zero), "r" (dr7)); 1855 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1856 vmcs_write(GUEST_DR7, 0x404); 1857 vmcs_write(GUEST_DEBUGCTL, 0x2); 1858 1859 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 1860 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_SAVE_DBGCTLS); 1861 1862 return VMX_TEST_START; 1863 } 1864 1865 static void dbgctls_main(void) 1866 { 1867 u64 dr7, debugctl; 1868 1869 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1870 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1871 /* Commented out: KVM does not support DEBUGCTL so far */ 1872 (void)debugctl; 1873 report(dr7 == 0x404, "Load debug controls" /* && debugctl == 0x2 */); 1874 1875 dr7 = 0x408; 1876 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1877 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1878 1879 vmx_set_test_stage(0); 1880 vmcall(); 1881 report(vmx_get_test_stage() == 1, "Save debug controls"); 1882 1883 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS || 1884 ctrl_exit_rev.set & EXI_SAVE_DBGCTLS) { 1885 printf("\tDebug controls are always loaded/saved\n"); 1886 return; 1887 } 1888 vmx_set_test_stage(2); 1889 vmcall(); 1890 1891 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1892 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1893 /* Commented out: KVM does not support DEBUGCTL so far */ 1894 (void)debugctl; 1895 report(dr7 == 0x402, 1896 "Guest=host debug controls" /* && debugctl == 0x1 */); 1897 1898 dr7 = 0x408; 1899 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1900 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1901 1902 vmx_set_test_stage(3); 1903 vmcall(); 1904 report(vmx_get_test_stage() == 4, "Don't save debug controls"); 1905 } 1906 1907 static int dbgctls_exit_handler(union exit_reason exit_reason) 1908 { 1909 u32 insn_len = vmcs_read(EXI_INST_LEN); 1910 u64 guest_rip = vmcs_read(GUEST_RIP); 1911 u64 dr7, debugctl; 1912 1913 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1914 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1915 1916 switch (exit_reason.basic) { 1917 case VMX_VMCALL: 1918 switch (vmx_get_test_stage()) { 1919 case 0: 1920 if (dr7 == 0x400 && debugctl == 0 && 1921 vmcs_read(GUEST_DR7) == 0x408 /* && 1922 Commented out: KVM does not support DEBUGCTL so far 1923 vmcs_read(GUEST_DEBUGCTL) == 0x3 */) 1924 vmx_inc_test_stage(); 1925 break; 1926 case 2: 1927 dr7 = 0x402; 1928 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1929 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1930 vmcs_write(GUEST_DR7, 0x404); 1931 vmcs_write(GUEST_DEBUGCTL, 0x2); 1932 1933 vmcs_write(ENT_CONTROLS, 1934 vmcs_read(ENT_CONTROLS) & ~ENT_LOAD_DBGCTLS); 1935 vmcs_write(EXI_CONTROLS, 1936 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_DBGCTLS); 1937 break; 1938 case 3: 1939 if (dr7 == 0x400 && debugctl == 0 && 1940 vmcs_read(GUEST_DR7) == 0x404 /* && 1941 Commented out: KVM does not support DEBUGCTL so far 1942 vmcs_read(GUEST_DEBUGCTL) == 0x2 */) 1943 vmx_inc_test_stage(); 1944 break; 1945 } 1946 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1947 return VMX_TEST_RESUME; 1948 default: 1949 report_fail("Unknown exit reason, %d", exit_reason.full); 1950 print_vmexit_info(exit_reason); 1951 } 1952 return VMX_TEST_VMEXIT; 1953 } 1954 1955 struct vmx_msr_entry { 1956 u32 index; 1957 u32 reserved; 1958 u64 value; 1959 } __attribute__((packed)); 1960 1961 #define MSR_MAGIC 0x31415926 1962 struct vmx_msr_entry *exit_msr_store, *entry_msr_load, *exit_msr_load; 1963 1964 static int msr_switch_init(struct vmcs *vmcs) 1965 { 1966 msr_bmp_init(); 1967 exit_msr_store = alloc_page(); 1968 exit_msr_load = alloc_page(); 1969 entry_msr_load = alloc_page(); 1970 entry_msr_load[0].index = MSR_KERNEL_GS_BASE; 1971 entry_msr_load[0].value = MSR_MAGIC; 1972 1973 vmx_set_test_stage(1); 1974 vmcs_write(ENT_MSR_LD_CNT, 1); 1975 vmcs_write(ENTER_MSR_LD_ADDR, (u64)entry_msr_load); 1976 vmcs_write(EXI_MSR_ST_CNT, 1); 1977 vmcs_write(EXIT_MSR_ST_ADDR, (u64)exit_msr_store); 1978 vmcs_write(EXI_MSR_LD_CNT, 1); 1979 vmcs_write(EXIT_MSR_LD_ADDR, (u64)exit_msr_load); 1980 return VMX_TEST_START; 1981 } 1982 1983 static void msr_switch_main(void) 1984 { 1985 if (vmx_get_test_stage() == 1) { 1986 report(rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC, 1987 "VM entry MSR load"); 1988 vmx_set_test_stage(2); 1989 wrmsr(MSR_KERNEL_GS_BASE, MSR_MAGIC + 1); 1990 exit_msr_store[0].index = MSR_KERNEL_GS_BASE; 1991 exit_msr_load[0].index = MSR_KERNEL_GS_BASE; 1992 exit_msr_load[0].value = MSR_MAGIC + 2; 1993 } 1994 vmcall(); 1995 } 1996 1997 static int msr_switch_exit_handler(union exit_reason exit_reason) 1998 { 1999 if (exit_reason.basic == VMX_VMCALL && vmx_get_test_stage() == 2) { 2000 report(exit_msr_store[0].value == MSR_MAGIC + 1, 2001 "VM exit MSR store"); 2002 report(rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC + 2, 2003 "VM exit MSR load"); 2004 vmx_set_test_stage(3); 2005 entry_msr_load[0].index = MSR_FS_BASE; 2006 return VMX_TEST_RESUME; 2007 } 2008 printf("ERROR %s: unexpected stage=%u or reason=0x%x\n", 2009 __func__, vmx_get_test_stage(), exit_reason.full); 2010 return VMX_TEST_EXIT; 2011 } 2012 2013 static int msr_switch_entry_failure(struct vmentry_result *result) 2014 { 2015 if (result->vm_fail) { 2016 printf("ERROR %s: VM-Fail on %s\n", __func__, result->instr); 2017 return VMX_TEST_EXIT; 2018 } 2019 2020 if (result->exit_reason.failed_vmentry && 2021 result->exit_reason.basic == VMX_FAIL_MSR && 2022 vmx_get_test_stage() == 3) { 2023 report(vmcs_read(EXI_QUALIFICATION) == 1, 2024 "VM entry MSR load: try to load FS_BASE"); 2025 return VMX_TEST_VMEXIT; 2026 } 2027 printf("ERROR %s: unexpected stage=%u or reason=%x\n", 2028 __func__, vmx_get_test_stage(), result->exit_reason.full); 2029 return VMX_TEST_EXIT; 2030 } 2031 2032 static int vmmcall_init(struct vmcs *vmcs) 2033 { 2034 vmcs_write(EXC_BITMAP, 1 << UD_VECTOR); 2035 return VMX_TEST_START; 2036 } 2037 2038 static void vmmcall_main(void) 2039 { 2040 asm volatile( 2041 "mov $0xABCD, %%rax\n\t" 2042 "vmmcall\n\t" 2043 ::: "rax"); 2044 2045 report_fail("VMMCALL"); 2046 } 2047 2048 static int vmmcall_exit_handler(union exit_reason exit_reason) 2049 { 2050 switch (exit_reason.basic) { 2051 case VMX_VMCALL: 2052 printf("here\n"); 2053 report_fail("VMMCALL triggers #UD"); 2054 break; 2055 case VMX_EXC_NMI: 2056 report((vmcs_read(EXI_INTR_INFO) & 0xff) == UD_VECTOR, 2057 "VMMCALL triggers #UD"); 2058 break; 2059 default: 2060 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 2061 print_vmexit_info(exit_reason); 2062 } 2063 2064 return VMX_TEST_VMEXIT; 2065 } 2066 2067 static int disable_rdtscp_init(struct vmcs *vmcs) 2068 { 2069 u32 ctrl_cpu1; 2070 2071 if (ctrl_cpu_rev[0].clr & CPU_SECONDARY) { 2072 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 2073 ctrl_cpu1 &= ~CPU_RDTSCP; 2074 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 2075 } 2076 2077 return VMX_TEST_START; 2078 } 2079 2080 static void disable_rdtscp_ud_handler(struct ex_regs *regs) 2081 { 2082 switch (vmx_get_test_stage()) { 2083 case 0: 2084 report_pass("RDTSCP triggers #UD"); 2085 vmx_inc_test_stage(); 2086 regs->rip += 3; 2087 break; 2088 case 2: 2089 report_pass("RDPID triggers #UD"); 2090 vmx_inc_test_stage(); 2091 regs->rip += 4; 2092 break; 2093 } 2094 return; 2095 2096 } 2097 2098 static void disable_rdtscp_main(void) 2099 { 2100 /* Test that #UD is properly injected in L2. */ 2101 handle_exception(UD_VECTOR, disable_rdtscp_ud_handler); 2102 2103 vmx_set_test_stage(0); 2104 asm volatile("rdtscp" : : : "eax", "ecx", "edx"); 2105 vmcall(); 2106 asm volatile(".byte 0xf3, 0x0f, 0xc7, 0xf8" : : : "eax"); 2107 2108 handle_exception(UD_VECTOR, 0); 2109 vmcall(); 2110 } 2111 2112 static int disable_rdtscp_exit_handler(union exit_reason exit_reason) 2113 { 2114 switch (exit_reason.basic) { 2115 case VMX_VMCALL: 2116 switch (vmx_get_test_stage()) { 2117 case 0: 2118 report_fail("RDTSCP triggers #UD"); 2119 vmx_inc_test_stage(); 2120 /* fallthrough */ 2121 case 1: 2122 vmx_inc_test_stage(); 2123 vmcs_write(GUEST_RIP, vmcs_read(GUEST_RIP) + 3); 2124 return VMX_TEST_RESUME; 2125 case 2: 2126 report_fail("RDPID triggers #UD"); 2127 break; 2128 } 2129 break; 2130 2131 default: 2132 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 2133 print_vmexit_info(exit_reason); 2134 } 2135 return VMX_TEST_VMEXIT; 2136 } 2137 2138 static void exit_monitor_from_l2_main(void) 2139 { 2140 printf("Calling exit(0) from l2...\n"); 2141 exit(0); 2142 } 2143 2144 static int exit_monitor_from_l2_handler(union exit_reason exit_reason) 2145 { 2146 report_fail("The guest should have killed the VMM"); 2147 return VMX_TEST_EXIT; 2148 } 2149 2150 static void assert_exit_reason(u64 expected) 2151 { 2152 u64 actual = vmcs_read(EXI_REASON); 2153 2154 TEST_ASSERT_EQ_MSG(expected, actual, "Expected %s, got %s.", 2155 exit_reason_description(expected), 2156 exit_reason_description(actual)); 2157 } 2158 2159 static void skip_exit_insn(void) 2160 { 2161 u64 guest_rip = vmcs_read(GUEST_RIP); 2162 u32 insn_len = vmcs_read(EXI_INST_LEN); 2163 vmcs_write(GUEST_RIP, guest_rip + insn_len); 2164 } 2165 2166 static void skip_exit_vmcall(void) 2167 { 2168 assert_exit_reason(VMX_VMCALL); 2169 skip_exit_insn(); 2170 } 2171 2172 static void v2_null_test_guest(void) 2173 { 2174 } 2175 2176 static void v2_null_test(void) 2177 { 2178 test_set_guest(v2_null_test_guest); 2179 enter_guest(); 2180 report_pass(__func__); 2181 } 2182 2183 static void v2_multiple_entries_test_guest(void) 2184 { 2185 vmx_set_test_stage(1); 2186 vmcall(); 2187 vmx_set_test_stage(2); 2188 } 2189 2190 static void v2_multiple_entries_test(void) 2191 { 2192 test_set_guest(v2_multiple_entries_test_guest); 2193 enter_guest(); 2194 TEST_ASSERT_EQ(vmx_get_test_stage(), 1); 2195 skip_exit_vmcall(); 2196 enter_guest(); 2197 TEST_ASSERT_EQ(vmx_get_test_stage(), 2); 2198 report_pass(__func__); 2199 } 2200 2201 static int fixture_test_data = 1; 2202 2203 static void fixture_test_teardown(void *data) 2204 { 2205 *((int *) data) = 1; 2206 } 2207 2208 static void fixture_test_guest(void) 2209 { 2210 fixture_test_data++; 2211 } 2212 2213 2214 static void fixture_test_setup(void) 2215 { 2216 TEST_ASSERT_EQ_MSG(1, fixture_test_data, 2217 "fixture_test_teardown didn't run?!"); 2218 fixture_test_data = 2; 2219 test_add_teardown(fixture_test_teardown, &fixture_test_data); 2220 test_set_guest(fixture_test_guest); 2221 } 2222 2223 static void fixture_test_case1(void) 2224 { 2225 fixture_test_setup(); 2226 TEST_ASSERT_EQ(2, fixture_test_data); 2227 enter_guest(); 2228 TEST_ASSERT_EQ(3, fixture_test_data); 2229 report_pass(__func__); 2230 } 2231 2232 static void fixture_test_case2(void) 2233 { 2234 fixture_test_setup(); 2235 TEST_ASSERT_EQ(2, fixture_test_data); 2236 enter_guest(); 2237 TEST_ASSERT_EQ(3, fixture_test_data); 2238 report_pass(__func__); 2239 } 2240 2241 enum ept_access_op { 2242 OP_READ, 2243 OP_WRITE, 2244 OP_EXEC, 2245 OP_FLUSH_TLB, 2246 OP_EXIT, 2247 }; 2248 2249 static struct ept_access_test_data { 2250 unsigned long gpa; 2251 unsigned long *gva; 2252 unsigned long hpa; 2253 unsigned long *hva; 2254 enum ept_access_op op; 2255 } ept_access_test_data; 2256 2257 extern unsigned char ret42_start; 2258 extern unsigned char ret42_end; 2259 2260 /* Returns 42. */ 2261 asm( 2262 ".align 64\n" 2263 "ret42_start:\n" 2264 "mov $42, %eax\n" 2265 "ret\n" 2266 "ret42_end:\n" 2267 ); 2268 2269 static void 2270 diagnose_ept_violation_qual(u64 expected, u64 actual) 2271 { 2272 2273 #define DIAGNOSE(flag) \ 2274 do { \ 2275 if ((expected & flag) != (actual & flag)) \ 2276 printf(#flag " %sexpected\n", \ 2277 (expected & flag) ? "" : "un"); \ 2278 } while (0) 2279 2280 DIAGNOSE(EPT_VLT_RD); 2281 DIAGNOSE(EPT_VLT_WR); 2282 DIAGNOSE(EPT_VLT_FETCH); 2283 DIAGNOSE(EPT_VLT_PERM_RD); 2284 DIAGNOSE(EPT_VLT_PERM_WR); 2285 DIAGNOSE(EPT_VLT_PERM_EX); 2286 DIAGNOSE(EPT_VLT_LADDR_VLD); 2287 DIAGNOSE(EPT_VLT_PADDR); 2288 2289 #undef DIAGNOSE 2290 } 2291 2292 static void do_ept_access_op(enum ept_access_op op) 2293 { 2294 ept_access_test_data.op = op; 2295 enter_guest(); 2296 } 2297 2298 /* 2299 * Force the guest to flush its TLB (i.e., flush gva -> gpa mappings). Only 2300 * needed by tests that modify guest PTEs. 2301 */ 2302 static void ept_access_test_guest_flush_tlb(void) 2303 { 2304 do_ept_access_op(OP_FLUSH_TLB); 2305 skip_exit_vmcall(); 2306 } 2307 2308 /* 2309 * Modifies the EPT entry at @level in the mapping of @gpa. First clears the 2310 * bits in @clear then sets the bits in @set. @mkhuge transforms the entry into 2311 * a huge page. 2312 */ 2313 static unsigned long ept_twiddle(unsigned long gpa, bool mkhuge, int level, 2314 unsigned long clear, unsigned long set) 2315 { 2316 struct ept_access_test_data *data = &ept_access_test_data; 2317 unsigned long orig_pte; 2318 unsigned long pte; 2319 2320 /* Screw with the mapping at the requested level. */ 2321 TEST_ASSERT(get_ept_pte(pml4, gpa, level, &orig_pte)); 2322 pte = orig_pte; 2323 if (mkhuge) 2324 pte = (orig_pte & ~EPT_ADDR_MASK) | data->hpa | EPT_LARGE_PAGE; 2325 else 2326 pte = orig_pte; 2327 pte = (pte & ~clear) | set; 2328 set_ept_pte(pml4, gpa, level, pte); 2329 invept(INVEPT_SINGLE, eptp); 2330 2331 return orig_pte; 2332 } 2333 2334 static void ept_untwiddle(unsigned long gpa, int level, unsigned long orig_pte) 2335 { 2336 set_ept_pte(pml4, gpa, level, orig_pte); 2337 invept(INVEPT_SINGLE, eptp); 2338 } 2339 2340 static void do_ept_violation(bool leaf, enum ept_access_op op, 2341 u64 expected_qual, u64 expected_paddr) 2342 { 2343 u64 qual; 2344 2345 /* Try the access and observe the violation. */ 2346 do_ept_access_op(op); 2347 2348 assert_exit_reason(VMX_EPT_VIOLATION); 2349 2350 qual = vmcs_read(EXI_QUALIFICATION); 2351 2352 /* Mask undefined bits (which may later be defined in certain cases). */ 2353 qual &= ~(EPT_VLT_GUEST_USER | EPT_VLT_GUEST_RW | EPT_VLT_GUEST_EX | 2354 EPT_VLT_PERM_USER_EX); 2355 2356 diagnose_ept_violation_qual(expected_qual, qual); 2357 TEST_EXPECT_EQ(expected_qual, qual); 2358 2359 #if 0 2360 /* Disable for now otherwise every test will fail */ 2361 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2362 (unsigned long) ( 2363 op == OP_EXEC ? data->gva + 1 : data->gva)); 2364 #endif 2365 /* 2366 * TODO: tests that probe expected_paddr in pages other than the one at 2367 * the beginning of the 1g region. 2368 */ 2369 TEST_EXPECT_EQ(vmcs_read(INFO_PHYS_ADDR), expected_paddr); 2370 } 2371 2372 static void 2373 ept_violation_at_level_mkhuge(bool mkhuge, int level, unsigned long clear, 2374 unsigned long set, enum ept_access_op op, 2375 u64 expected_qual) 2376 { 2377 struct ept_access_test_data *data = &ept_access_test_data; 2378 unsigned long orig_pte; 2379 2380 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2381 2382 do_ept_violation(level == 1 || mkhuge, op, expected_qual, 2383 op == OP_EXEC ? data->gpa + sizeof(unsigned long) : 2384 data->gpa); 2385 2386 /* Fix the violation and resume the op loop. */ 2387 ept_untwiddle(data->gpa, level, orig_pte); 2388 enter_guest(); 2389 skip_exit_vmcall(); 2390 } 2391 2392 static void 2393 ept_violation_at_level(int level, unsigned long clear, unsigned long set, 2394 enum ept_access_op op, u64 expected_qual) 2395 { 2396 ept_violation_at_level_mkhuge(false, level, clear, set, op, 2397 expected_qual); 2398 if (ept_huge_pages_supported(level)) 2399 ept_violation_at_level_mkhuge(true, level, clear, set, op, 2400 expected_qual); 2401 } 2402 2403 static void ept_violation(unsigned long clear, unsigned long set, 2404 enum ept_access_op op, u64 expected_qual) 2405 { 2406 ept_violation_at_level(1, clear, set, op, expected_qual); 2407 ept_violation_at_level(2, clear, set, op, expected_qual); 2408 ept_violation_at_level(3, clear, set, op, expected_qual); 2409 ept_violation_at_level(4, clear, set, op, expected_qual); 2410 } 2411 2412 static void ept_access_violation(unsigned long access, enum ept_access_op op, 2413 u64 expected_qual) 2414 { 2415 ept_violation(EPT_PRESENT, access, op, 2416 expected_qual | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2417 } 2418 2419 /* 2420 * For translations that don't involve a GVA, that is physical address (paddr) 2421 * accesses, EPT violations don't set the flag EPT_VLT_PADDR. For a typical 2422 * guest memory access, the hardware does GVA -> GPA -> HPA. However, certain 2423 * translations don't involve GVAs, such as when the hardware does the guest 2424 * page table walk. For example, in translating GVA_1 -> GPA_1, the guest MMU 2425 * might try to set an A bit on a guest PTE. If the GPA_2 that the PTE resides 2426 * on isn't present in the EPT, then the EPT violation will be for GPA_2 and 2427 * the EPT_VLT_PADDR bit will be clear in the exit qualification. 2428 * 2429 * Note that paddr violations can also be triggered by loading PAE page tables 2430 * with wonky addresses. We don't test that yet. 2431 * 2432 * This function modifies the EPT entry that maps the GPA that the guest page 2433 * table entry mapping ept_access_test_data.gva resides on. 2434 * 2435 * @ept_access EPT permissions to set. Other permissions are cleared. 2436 * 2437 * @pte_ad Set the A/D bits on the guest PTE accordingly. 2438 * 2439 * @op Guest operation to perform with 2440 * ept_access_test_data.gva. 2441 * 2442 * @expect_violation 2443 * Is a violation expected during the paddr access? 2444 * 2445 * @expected_qual Expected qualification for the EPT violation. 2446 * EPT_VLT_PADDR should be clear. 2447 */ 2448 static void ept_access_paddr(unsigned long ept_access, unsigned long pte_ad, 2449 enum ept_access_op op, bool expect_violation, 2450 u64 expected_qual) 2451 { 2452 struct ept_access_test_data *data = &ept_access_test_data; 2453 unsigned long *ptep; 2454 unsigned long gpa; 2455 unsigned long orig_epte; 2456 unsigned long epte; 2457 int i; 2458 2459 /* Modify the guest PTE mapping data->gva according to @pte_ad. */ 2460 ptep = get_pte_level(current_page_table(), data->gva, /*level=*/1); 2461 TEST_ASSERT(ptep); 2462 TEST_ASSERT_EQ(*ptep & PT_ADDR_MASK, data->gpa); 2463 *ptep = (*ptep & ~PT_AD_MASK) | pte_ad; 2464 ept_access_test_guest_flush_tlb(); 2465 2466 /* 2467 * Now modify the access bits on the EPT entry for the GPA that the 2468 * guest PTE resides on. Note that by modifying a single EPT entry, 2469 * we're potentially affecting 512 guest PTEs. However, we've carefully 2470 * constructed our test such that those other 511 PTEs aren't used by 2471 * the guest: data->gva is at the beginning of a 1G huge page, thus the 2472 * PTE we're modifying is at the beginning of a 4K page and the 2473 * following 511 entries are also under our control (and not touched by 2474 * the guest). 2475 */ 2476 gpa = virt_to_phys(ptep); 2477 TEST_ASSERT_EQ(gpa & ~PAGE_MASK, 0); 2478 /* 2479 * Make sure the guest page table page is mapped with a 4K EPT entry, 2480 * otherwise our level=1 twiddling below will fail. We use the 2481 * identity map (gpa = gpa) since page tables are shared with the host. 2482 */ 2483 install_ept(pml4, gpa, gpa, EPT_PRESENT); 2484 orig_epte = ept_twiddle(gpa, /*mkhuge=*/0, /*level=*/1, 2485 /*clear=*/EPT_PRESENT, /*set=*/ept_access); 2486 2487 if (expect_violation) { 2488 do_ept_violation(/*leaf=*/true, op, 2489 expected_qual | EPT_VLT_LADDR_VLD, gpa); 2490 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2491 do_ept_access_op(op); 2492 } else { 2493 do_ept_access_op(op); 2494 if (ept_ad_enabled()) { 2495 for (i = EPT_PAGE_LEVEL; i > 0; i--) { 2496 TEST_ASSERT(get_ept_pte(pml4, gpa, i, &epte)); 2497 TEST_ASSERT(epte & EPT_ACCESS_FLAG); 2498 if (i == 1) 2499 TEST_ASSERT(epte & EPT_DIRTY_FLAG); 2500 else 2501 TEST_ASSERT_EQ(epte & EPT_DIRTY_FLAG, 0); 2502 } 2503 } 2504 2505 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2506 } 2507 2508 TEST_ASSERT(*ptep & PT_ACCESSED_MASK); 2509 if ((pte_ad & PT_DIRTY_MASK) || op == OP_WRITE) 2510 TEST_ASSERT(*ptep & PT_DIRTY_MASK); 2511 2512 skip_exit_vmcall(); 2513 } 2514 2515 static void ept_access_allowed_paddr(unsigned long ept_access, 2516 unsigned long pte_ad, 2517 enum ept_access_op op) 2518 { 2519 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/false, 2520 /*expected_qual=*/-1); 2521 } 2522 2523 static void ept_access_violation_paddr(unsigned long ept_access, 2524 unsigned long pte_ad, 2525 enum ept_access_op op, 2526 u64 expected_qual) 2527 { 2528 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/true, 2529 expected_qual); 2530 } 2531 2532 2533 static void ept_allowed_at_level_mkhuge(bool mkhuge, int level, 2534 unsigned long clear, 2535 unsigned long set, 2536 enum ept_access_op op) 2537 { 2538 struct ept_access_test_data *data = &ept_access_test_data; 2539 unsigned long orig_pte; 2540 2541 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2542 2543 /* No violation. Should proceed to vmcall. */ 2544 do_ept_access_op(op); 2545 skip_exit_vmcall(); 2546 2547 ept_untwiddle(data->gpa, level, orig_pte); 2548 } 2549 2550 static void ept_allowed_at_level(int level, unsigned long clear, 2551 unsigned long set, enum ept_access_op op) 2552 { 2553 ept_allowed_at_level_mkhuge(false, level, clear, set, op); 2554 if (ept_huge_pages_supported(level)) 2555 ept_allowed_at_level_mkhuge(true, level, clear, set, op); 2556 } 2557 2558 static void ept_allowed(unsigned long clear, unsigned long set, 2559 enum ept_access_op op) 2560 { 2561 ept_allowed_at_level(1, clear, set, op); 2562 ept_allowed_at_level(2, clear, set, op); 2563 ept_allowed_at_level(3, clear, set, op); 2564 ept_allowed_at_level(4, clear, set, op); 2565 } 2566 2567 static void ept_ignored_bit(int bit) 2568 { 2569 /* Set the bit. */ 2570 ept_allowed(0, 1ul << bit, OP_READ); 2571 ept_allowed(0, 1ul << bit, OP_WRITE); 2572 ept_allowed(0, 1ul << bit, OP_EXEC); 2573 2574 /* Clear the bit. */ 2575 ept_allowed(1ul << bit, 0, OP_READ); 2576 ept_allowed(1ul << bit, 0, OP_WRITE); 2577 ept_allowed(1ul << bit, 0, OP_EXEC); 2578 } 2579 2580 static void ept_access_allowed(unsigned long access, enum ept_access_op op) 2581 { 2582 ept_allowed(EPT_PRESENT, access, op); 2583 } 2584 2585 2586 static void ept_misconfig_at_level_mkhuge_op(bool mkhuge, int level, 2587 unsigned long clear, 2588 unsigned long set, 2589 enum ept_access_op op) 2590 { 2591 struct ept_access_test_data *data = &ept_access_test_data; 2592 unsigned long orig_pte; 2593 2594 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2595 2596 do_ept_access_op(op); 2597 assert_exit_reason(VMX_EPT_MISCONFIG); 2598 2599 /* Intel 27.2.1, "For all other VM exits, this field is cleared." */ 2600 #if 0 2601 /* broken: */ 2602 TEST_EXPECT_EQ_MSG(vmcs_read(EXI_QUALIFICATION), 0); 2603 #endif 2604 #if 0 2605 /* 2606 * broken: 2607 * According to description of exit qual for EPT violation, 2608 * EPT_VLT_LADDR_VLD indicates if GUEST_LINEAR_ADDRESS is valid. 2609 * However, I can't find anything that says GUEST_LINEAR_ADDRESS ought 2610 * to be set for msiconfig. 2611 */ 2612 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2613 (unsigned long) ( 2614 op == OP_EXEC ? data->gva + 1 : data->gva)); 2615 #endif 2616 2617 /* Fix the violation and resume the op loop. */ 2618 ept_untwiddle(data->gpa, level, orig_pte); 2619 enter_guest(); 2620 skip_exit_vmcall(); 2621 } 2622 2623 static void ept_misconfig_at_level_mkhuge(bool mkhuge, int level, 2624 unsigned long clear, 2625 unsigned long set) 2626 { 2627 /* The op shouldn't matter (read, write, exec), so try them all! */ 2628 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_READ); 2629 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_WRITE); 2630 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_EXEC); 2631 } 2632 2633 static void ept_misconfig_at_level(int level, unsigned long clear, 2634 unsigned long set) 2635 { 2636 ept_misconfig_at_level_mkhuge(false, level, clear, set); 2637 if (ept_huge_pages_supported(level)) 2638 ept_misconfig_at_level_mkhuge(true, level, clear, set); 2639 } 2640 2641 static void ept_misconfig(unsigned long clear, unsigned long set) 2642 { 2643 ept_misconfig_at_level(1, clear, set); 2644 ept_misconfig_at_level(2, clear, set); 2645 ept_misconfig_at_level(3, clear, set); 2646 ept_misconfig_at_level(4, clear, set); 2647 } 2648 2649 static void ept_access_misconfig(unsigned long access) 2650 { 2651 ept_misconfig(EPT_PRESENT, access); 2652 } 2653 2654 static void ept_reserved_bit_at_level_nohuge(int level, int bit) 2655 { 2656 /* Setting the bit causes a misconfig. */ 2657 ept_misconfig_at_level_mkhuge(false, level, 0, 1ul << bit); 2658 2659 /* Making the entry non-present turns reserved bits into ignored. */ 2660 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2661 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2662 } 2663 2664 static void ept_reserved_bit_at_level_huge(int level, int bit) 2665 { 2666 /* Setting the bit causes a misconfig. */ 2667 ept_misconfig_at_level_mkhuge(true, level, 0, 1ul << bit); 2668 2669 /* Making the entry non-present turns reserved bits into ignored. */ 2670 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2671 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2672 } 2673 2674 static void ept_reserved_bit_at_level(int level, int bit) 2675 { 2676 /* Setting the bit causes a misconfig. */ 2677 ept_misconfig_at_level(level, 0, 1ul << bit); 2678 2679 /* Making the entry non-present turns reserved bits into ignored. */ 2680 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2681 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2682 } 2683 2684 static void ept_reserved_bit(int bit) 2685 { 2686 ept_reserved_bit_at_level(1, bit); 2687 ept_reserved_bit_at_level(2, bit); 2688 ept_reserved_bit_at_level(3, bit); 2689 ept_reserved_bit_at_level(4, bit); 2690 } 2691 2692 #define PAGE_2M_ORDER 9 2693 #define PAGE_1G_ORDER 18 2694 2695 static void *get_1g_page(void) 2696 { 2697 static void *alloc; 2698 2699 if (!alloc) 2700 alloc = alloc_pages(PAGE_1G_ORDER); 2701 return alloc; 2702 } 2703 2704 static void ept_access_test_teardown(void *unused) 2705 { 2706 /* Exit the guest cleanly. */ 2707 do_ept_access_op(OP_EXIT); 2708 } 2709 2710 static void ept_access_test_guest(void) 2711 { 2712 struct ept_access_test_data *data = &ept_access_test_data; 2713 int (*code)(void) = (int (*)(void)) &data->gva[1]; 2714 2715 while (true) { 2716 switch (data->op) { 2717 case OP_READ: 2718 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_1); 2719 break; 2720 case OP_WRITE: 2721 *data->gva = MAGIC_VAL_2; 2722 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_2); 2723 *data->gva = MAGIC_VAL_1; 2724 break; 2725 case OP_EXEC: 2726 TEST_ASSERT_EQ(42, code()); 2727 break; 2728 case OP_FLUSH_TLB: 2729 write_cr3(read_cr3()); 2730 break; 2731 case OP_EXIT: 2732 return; 2733 default: 2734 TEST_ASSERT_MSG(false, "Unknown op %d", data->op); 2735 } 2736 vmcall(); 2737 } 2738 } 2739 2740 static void ept_access_test_setup(void) 2741 { 2742 struct ept_access_test_data *data = &ept_access_test_data; 2743 unsigned long npages = 1ul << PAGE_1G_ORDER; 2744 unsigned long size = npages * PAGE_SIZE; 2745 unsigned long *page_table = current_page_table(); 2746 unsigned long pte; 2747 2748 if (setup_ept(false)) 2749 test_skip("EPT not supported"); 2750 2751 /* We use data->gpa = 1 << 39 so that test data has a separate pml4 entry */ 2752 if (cpuid_maxphyaddr() < 40) 2753 test_skip("Test needs MAXPHYADDR >= 40"); 2754 2755 test_set_guest(ept_access_test_guest); 2756 test_add_teardown(ept_access_test_teardown, NULL); 2757 2758 data->hva = get_1g_page(); 2759 TEST_ASSERT(data->hva); 2760 data->hpa = virt_to_phys(data->hva); 2761 2762 data->gpa = 1ul << 39; 2763 data->gva = (void *) ALIGN((unsigned long) alloc_vpages(npages * 2), 2764 size); 2765 TEST_ASSERT(!any_present_pages(page_table, data->gva, size)); 2766 install_pages(page_table, data->gpa, size, data->gva); 2767 2768 /* 2769 * Make sure nothing's mapped here so the tests that screw with the 2770 * pml4 entry don't inadvertently break something. 2771 */ 2772 TEST_ASSERT(get_ept_pte(pml4, data->gpa, 4, &pte) && pte == 0); 2773 TEST_ASSERT(get_ept_pte(pml4, data->gpa + size - 1, 4, &pte) && pte == 0); 2774 install_ept(pml4, data->hpa, data->gpa, EPT_PRESENT); 2775 2776 data->hva[0] = MAGIC_VAL_1; 2777 memcpy(&data->hva[1], &ret42_start, &ret42_end - &ret42_start); 2778 } 2779 2780 static void ept_access_test_not_present(void) 2781 { 2782 ept_access_test_setup(); 2783 /* --- */ 2784 ept_access_violation(0, OP_READ, EPT_VLT_RD); 2785 ept_access_violation(0, OP_WRITE, EPT_VLT_WR); 2786 ept_access_violation(0, OP_EXEC, EPT_VLT_FETCH); 2787 } 2788 2789 static void ept_access_test_read_only(void) 2790 { 2791 ept_access_test_setup(); 2792 2793 /* r-- */ 2794 ept_access_allowed(EPT_RA, OP_READ); 2795 ept_access_violation(EPT_RA, OP_WRITE, EPT_VLT_WR | EPT_VLT_PERM_RD); 2796 ept_access_violation(EPT_RA, OP_EXEC, EPT_VLT_FETCH | EPT_VLT_PERM_RD); 2797 } 2798 2799 static void ept_access_test_write_only(void) 2800 { 2801 ept_access_test_setup(); 2802 /* -w- */ 2803 ept_access_misconfig(EPT_WA); 2804 } 2805 2806 static void ept_access_test_read_write(void) 2807 { 2808 ept_access_test_setup(); 2809 /* rw- */ 2810 ept_access_allowed(EPT_RA | EPT_WA, OP_READ); 2811 ept_access_allowed(EPT_RA | EPT_WA, OP_WRITE); 2812 ept_access_violation(EPT_RA | EPT_WA, OP_EXEC, 2813 EPT_VLT_FETCH | EPT_VLT_PERM_RD | EPT_VLT_PERM_WR); 2814 } 2815 2816 2817 static void ept_access_test_execute_only(void) 2818 { 2819 ept_access_test_setup(); 2820 /* --x */ 2821 if (ept_execute_only_supported()) { 2822 ept_access_violation(EPT_EA, OP_READ, 2823 EPT_VLT_RD | EPT_VLT_PERM_EX); 2824 ept_access_violation(EPT_EA, OP_WRITE, 2825 EPT_VLT_WR | EPT_VLT_PERM_EX); 2826 ept_access_allowed(EPT_EA, OP_EXEC); 2827 } else { 2828 ept_access_misconfig(EPT_EA); 2829 } 2830 } 2831 2832 static void ept_access_test_read_execute(void) 2833 { 2834 ept_access_test_setup(); 2835 /* r-x */ 2836 ept_access_allowed(EPT_RA | EPT_EA, OP_READ); 2837 ept_access_violation(EPT_RA | EPT_EA, OP_WRITE, 2838 EPT_VLT_WR | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX); 2839 ept_access_allowed(EPT_RA | EPT_EA, OP_EXEC); 2840 } 2841 2842 static void ept_access_test_write_execute(void) 2843 { 2844 ept_access_test_setup(); 2845 /* -wx */ 2846 ept_access_misconfig(EPT_WA | EPT_EA); 2847 } 2848 2849 static void ept_access_test_read_write_execute(void) 2850 { 2851 ept_access_test_setup(); 2852 /* rwx */ 2853 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_READ); 2854 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_WRITE); 2855 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_EXEC); 2856 } 2857 2858 static void ept_access_test_reserved_bits(void) 2859 { 2860 int i; 2861 int maxphyaddr; 2862 2863 ept_access_test_setup(); 2864 2865 /* Reserved bits above maxphyaddr. */ 2866 maxphyaddr = cpuid_maxphyaddr(); 2867 for (i = maxphyaddr; i <= 51; i++) { 2868 report_prefix_pushf("reserved_bit=%d", i); 2869 ept_reserved_bit(i); 2870 report_prefix_pop(); 2871 } 2872 2873 /* Level-specific reserved bits. */ 2874 ept_reserved_bit_at_level_nohuge(2, 3); 2875 ept_reserved_bit_at_level_nohuge(2, 4); 2876 ept_reserved_bit_at_level_nohuge(2, 5); 2877 ept_reserved_bit_at_level_nohuge(2, 6); 2878 /* 2M alignment. */ 2879 for (i = 12; i < 20; i++) { 2880 report_prefix_pushf("reserved_bit=%d", i); 2881 ept_reserved_bit_at_level_huge(2, i); 2882 report_prefix_pop(); 2883 } 2884 ept_reserved_bit_at_level_nohuge(3, 3); 2885 ept_reserved_bit_at_level_nohuge(3, 4); 2886 ept_reserved_bit_at_level_nohuge(3, 5); 2887 ept_reserved_bit_at_level_nohuge(3, 6); 2888 /* 1G alignment. */ 2889 for (i = 12; i < 29; i++) { 2890 report_prefix_pushf("reserved_bit=%d", i); 2891 ept_reserved_bit_at_level_huge(3, i); 2892 report_prefix_pop(); 2893 } 2894 ept_reserved_bit_at_level(4, 3); 2895 ept_reserved_bit_at_level(4, 4); 2896 ept_reserved_bit_at_level(4, 5); 2897 ept_reserved_bit_at_level(4, 6); 2898 ept_reserved_bit_at_level(4, 7); 2899 } 2900 2901 static void ept_access_test_ignored_bits(void) 2902 { 2903 ept_access_test_setup(); 2904 /* 2905 * Bits ignored at every level. Bits 8 and 9 (A and D) are ignored as 2906 * far as translation is concerned even if AD bits are enabled in the 2907 * EPTP. Bit 63 is ignored because "EPT-violation #VE" VM-execution 2908 * control is 0. 2909 */ 2910 ept_ignored_bit(8); 2911 ept_ignored_bit(9); 2912 ept_ignored_bit(10); 2913 ept_ignored_bit(11); 2914 ept_ignored_bit(52); 2915 ept_ignored_bit(53); 2916 ept_ignored_bit(54); 2917 ept_ignored_bit(55); 2918 ept_ignored_bit(56); 2919 ept_ignored_bit(57); 2920 ept_ignored_bit(58); 2921 ept_ignored_bit(59); 2922 ept_ignored_bit(60); 2923 ept_ignored_bit(61); 2924 ept_ignored_bit(62); 2925 ept_ignored_bit(63); 2926 } 2927 2928 static void ept_access_test_paddr_not_present_ad_disabled(void) 2929 { 2930 ept_access_test_setup(); 2931 ept_disable_ad_bits(); 2932 2933 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, EPT_VLT_RD); 2934 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, EPT_VLT_RD); 2935 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, EPT_VLT_RD); 2936 } 2937 2938 static void ept_access_test_paddr_not_present_ad_enabled(void) 2939 { 2940 u64 qual = EPT_VLT_RD | EPT_VLT_WR; 2941 2942 ept_access_test_setup(); 2943 ept_enable_ad_bits_or_skip_test(); 2944 2945 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, qual); 2946 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, qual); 2947 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, qual); 2948 } 2949 2950 static void ept_access_test_paddr_read_only_ad_disabled(void) 2951 { 2952 /* 2953 * When EPT AD bits are disabled, all accesses to guest paging 2954 * structures are reported separately as a read and (after 2955 * translation of the GPA to host physical address) a read+write 2956 * if the A/D bits have to be set. 2957 */ 2958 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 2959 2960 ept_access_test_setup(); 2961 ept_disable_ad_bits(); 2962 2963 /* Can't update A bit, so all accesses fail. */ 2964 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 2965 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 2966 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 2967 /* AD bits disabled, so only writes try to update the D bit. */ 2968 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ); 2969 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 2970 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC); 2971 /* Both A and D already set, so read-only is OK. */ 2972 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_READ); 2973 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_WRITE); 2974 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_EXEC); 2975 } 2976 2977 static void ept_access_test_paddr_read_only_ad_enabled(void) 2978 { 2979 /* 2980 * When EPT AD bits are enabled, all accesses to guest paging 2981 * structures are considered writes as far as EPT translation 2982 * is concerned. 2983 */ 2984 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 2985 2986 ept_access_test_setup(); 2987 ept_enable_ad_bits_or_skip_test(); 2988 2989 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 2990 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 2991 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 2992 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ, qual); 2993 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 2994 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC, qual); 2995 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_READ, qual); 2996 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_WRITE, qual); 2997 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_EXEC, qual); 2998 } 2999 3000 static void ept_access_test_paddr_read_write(void) 3001 { 3002 ept_access_test_setup(); 3003 /* Read-write access to paging structure. */ 3004 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_READ); 3005 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_WRITE); 3006 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_EXEC); 3007 } 3008 3009 static void ept_access_test_paddr_read_write_execute(void) 3010 { 3011 ept_access_test_setup(); 3012 /* RWX access to paging structure. */ 3013 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_READ); 3014 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_WRITE); 3015 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_EXEC); 3016 } 3017 3018 static void ept_access_test_paddr_read_execute_ad_disabled(void) 3019 { 3020 /* 3021 * When EPT AD bits are disabled, all accesses to guest paging 3022 * structures are reported separately as a read and (after 3023 * translation of the GPA to host physical address) a read+write 3024 * if the A/D bits have to be set. 3025 */ 3026 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3027 3028 ept_access_test_setup(); 3029 ept_disable_ad_bits(); 3030 3031 /* Can't update A bit, so all accesses fail. */ 3032 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3033 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3034 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3035 /* AD bits disabled, so only writes try to update the D bit. */ 3036 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ); 3037 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3038 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC); 3039 /* Both A and D already set, so read-only is OK. */ 3040 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ); 3041 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE); 3042 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC); 3043 } 3044 3045 static void ept_access_test_paddr_read_execute_ad_enabled(void) 3046 { 3047 /* 3048 * When EPT AD bits are enabled, all accesses to guest paging 3049 * structures are considered writes as far as EPT translation 3050 * is concerned. 3051 */ 3052 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3053 3054 ept_access_test_setup(); 3055 ept_enable_ad_bits_or_skip_test(); 3056 3057 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3058 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3059 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3060 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ, qual); 3061 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3062 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC, qual); 3063 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ, qual); 3064 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE, qual); 3065 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC, qual); 3066 } 3067 3068 static void ept_access_test_paddr_not_present_page_fault(void) 3069 { 3070 ept_access_test_setup(); 3071 /* 3072 * TODO: test no EPT violation as long as guest PF occurs. e.g., GPA is 3073 * page is read-only in EPT but GVA is also mapped read only in PT. 3074 * Thus guest page fault before host takes EPT violation for trying to 3075 * update A bit. 3076 */ 3077 } 3078 3079 static void ept_access_test_force_2m_page(void) 3080 { 3081 ept_access_test_setup(); 3082 3083 TEST_ASSERT_EQ(ept_2m_supported(), true); 3084 ept_allowed_at_level_mkhuge(true, 2, 0, 0, OP_READ); 3085 ept_violation_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_RA, OP_WRITE, 3086 EPT_VLT_WR | EPT_VLT_PERM_RD | 3087 EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 3088 ept_misconfig_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_WA); 3089 } 3090 3091 static bool invvpid_valid(u64 type, u64 vpid, u64 gla) 3092 { 3093 if (!is_invvpid_type_supported(type)) 3094 return false; 3095 3096 if (vpid >> 16) 3097 return false; 3098 3099 if (type != INVVPID_ALL && !vpid) 3100 return false; 3101 3102 if (type == INVVPID_ADDR && !is_canonical(gla)) 3103 return false; 3104 3105 return true; 3106 } 3107 3108 static void try_invvpid(u64 type, u64 vpid, u64 gla) 3109 { 3110 int rc; 3111 bool valid = invvpid_valid(type, vpid, gla); 3112 u64 expected = valid ? VMXERR_UNSUPPORTED_VMCS_COMPONENT 3113 : VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID; 3114 /* 3115 * Set VMX_INST_ERROR to VMXERR_UNVALID_VMCS_COMPONENT, so 3116 * that we can tell if it is updated by INVVPID. 3117 */ 3118 vmcs_read(~0); 3119 rc = __invvpid(type, vpid, gla); 3120 report(!rc == valid, "INVVPID type %ld VPID %lx GLA %lx %s", type, 3121 vpid, gla, 3122 valid ? "passes" : "fails"); 3123 report(vmcs_read(VMX_INST_ERROR) == expected, 3124 "After %s INVVPID, VMX_INST_ERR is %ld (actual %ld)", 3125 rc ? "failed" : "successful", 3126 expected, vmcs_read(VMX_INST_ERROR)); 3127 } 3128 3129 static inline unsigned long get_first_supported_invvpid_type(void) 3130 { 3131 u64 type = ffs(ept_vpid.val >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 3132 3133 __TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 3134 return type; 3135 } 3136 3137 static void ds_invvpid(void *data) 3138 { 3139 asm volatile("invvpid %0, %1" 3140 : 3141 : "m"(*(struct invvpid_operand *)data), 3142 "r"(get_first_supported_invvpid_type())); 3143 } 3144 3145 /* 3146 * The SS override is ignored in 64-bit mode, so we use an addressing 3147 * mode with %rsp as the base register to generate an implicit SS 3148 * reference. 3149 */ 3150 static void ss_invvpid(void *data) 3151 { 3152 asm volatile("sub %%rsp,%0; invvpid (%%rsp,%0,1), %1" 3153 : "+r"(data) 3154 : "r"(get_first_supported_invvpid_type())); 3155 } 3156 3157 static void invvpid_test_gp(void) 3158 { 3159 bool fault; 3160 3161 fault = test_for_exception(GP_VECTOR, &ds_invvpid, 3162 (void *)NONCANONICAL); 3163 report(fault, "INVVPID with non-canonical DS operand raises #GP"); 3164 } 3165 3166 static void invvpid_test_ss(void) 3167 { 3168 bool fault; 3169 3170 fault = test_for_exception(SS_VECTOR, &ss_invvpid, 3171 (void *)NONCANONICAL); 3172 report(fault, "INVVPID with non-canonical SS operand raises #SS"); 3173 } 3174 3175 static void invvpid_test_pf(void) 3176 { 3177 void *vpage = alloc_vpage(); 3178 bool fault; 3179 3180 fault = test_for_exception(PF_VECTOR, &ds_invvpid, vpage); 3181 report(fault, "INVVPID with unmapped operand raises #PF"); 3182 } 3183 3184 static void try_compat_invvpid(void *unused) 3185 { 3186 struct far_pointer32 fp = { 3187 .offset = (uintptr_t)&&invvpid, 3188 .selector = KERNEL_CS32, 3189 }; 3190 uintptr_t rsp; 3191 3192 asm volatile ("mov %%rsp, %0" : "=r"(rsp)); 3193 3194 TEST_ASSERT_MSG(fp.offset == (uintptr_t)&&invvpid, 3195 "Code address too high."); 3196 TEST_ASSERT_MSG(rsp == (u32)rsp, "Stack address too high."); 3197 3198 asm goto ("lcall *%0" : : "m" (fp) : "rax" : invvpid); 3199 return; 3200 invvpid: 3201 asm volatile (".code32;" 3202 "invvpid (%eax), %eax;" 3203 "lret;" 3204 ".code64"); 3205 __builtin_unreachable(); 3206 } 3207 3208 static void invvpid_test_compatibility_mode(void) 3209 { 3210 bool fault; 3211 3212 fault = test_for_exception(UD_VECTOR, &try_compat_invvpid, NULL); 3213 report(fault, "Compatibility mode INVVPID raises #UD"); 3214 } 3215 3216 static void invvpid_test_not_in_vmx_operation(void) 3217 { 3218 bool fault; 3219 3220 TEST_ASSERT(!vmx_off()); 3221 fault = test_for_exception(UD_VECTOR, &ds_invvpid, NULL); 3222 report(fault, "INVVPID outside of VMX operation raises #UD"); 3223 TEST_ASSERT(!vmx_on()); 3224 } 3225 3226 /* 3227 * This does not test real-address mode, virtual-8086 mode, protected mode, 3228 * or CPL > 0. 3229 */ 3230 static void invvpid_test(void) 3231 { 3232 int i; 3233 unsigned types = 0; 3234 unsigned type; 3235 3236 if (!is_vpid_supported()) 3237 test_skip("VPID not supported"); 3238 3239 if (!is_invvpid_supported()) 3240 test_skip("INVVPID not supported.\n"); 3241 3242 if (is_invvpid_type_supported(INVVPID_ADDR)) 3243 types |= 1u << INVVPID_ADDR; 3244 if (is_invvpid_type_supported(INVVPID_CONTEXT_GLOBAL)) 3245 types |= 1u << INVVPID_CONTEXT_GLOBAL; 3246 if (is_invvpid_type_supported(INVVPID_ALL)) 3247 types |= 1u << INVVPID_ALL; 3248 if (is_invvpid_type_supported(INVVPID_CONTEXT_LOCAL)) 3249 types |= 1u << INVVPID_CONTEXT_LOCAL; 3250 3251 if (!types) 3252 test_skip("No INVVPID types supported.\n"); 3253 3254 for (i = -127; i < 128; i++) 3255 try_invvpid(i, 0xffff, 0); 3256 3257 /* 3258 * VPID must not be more than 16 bits. 3259 */ 3260 for (i = 0; i < 64; i++) 3261 for (type = 0; type < 4; type++) 3262 if (types & (1u << type)) 3263 try_invvpid(type, 1ul << i, 0); 3264 3265 /* 3266 * VPID must not be zero, except for "all contexts." 3267 */ 3268 for (type = 0; type < 4; type++) 3269 if (types & (1u << type)) 3270 try_invvpid(type, 0, 0); 3271 3272 /* 3273 * The gla operand is only validated for single-address INVVPID. 3274 */ 3275 if (types & (1u << INVVPID_ADDR)) 3276 try_invvpid(INVVPID_ADDR, 0xffff, NONCANONICAL); 3277 3278 invvpid_test_gp(); 3279 invvpid_test_ss(); 3280 invvpid_test_pf(); 3281 invvpid_test_compatibility_mode(); 3282 invvpid_test_not_in_vmx_operation(); 3283 } 3284 3285 static void test_assert_vmlaunch_inst_error(u32 expected_error) 3286 { 3287 u32 vmx_inst_err = vmcs_read(VMX_INST_ERROR); 3288 3289 report(vmx_inst_err == expected_error, 3290 "VMX inst error is %d (actual %d)", expected_error, vmx_inst_err); 3291 } 3292 3293 /* 3294 * This version is wildly unsafe and should _only_ be used to test VM-Fail 3295 * scenarios involving HOST_RIP. 3296 */ 3297 static void test_vmx_vmlaunch_must_fail(u32 expected_error) 3298 { 3299 /* Read the function name. */ 3300 TEST_ASSERT(expected_error); 3301 3302 /* 3303 * Don't bother with any prep work, if VMLAUNCH passes the VM-Fail 3304 * consistency checks and generates a VM-Exit, then the test is doomed 3305 * no matter what as it will jump to a garbage RIP. 3306 */ 3307 __asm__ __volatile__ ("vmlaunch"); 3308 test_assert_vmlaunch_inst_error(expected_error); 3309 } 3310 3311 /* 3312 * Test for early VMLAUNCH failure. Returns true if VMLAUNCH makes it 3313 * at least as far as the guest-state checks. Returns false if the 3314 * VMLAUNCH fails early and execution falls through to the next 3315 * instruction. 3316 */ 3317 static bool vmlaunch(void) 3318 { 3319 u32 exit_reason; 3320 3321 /* 3322 * Indirectly set VMX_INST_ERR to 12 ("VMREAD/VMWRITE from/to 3323 * unsupported VMCS component"). The caller can then check 3324 * to see if a failed VM-entry sets VMX_INST_ERR as expected. 3325 */ 3326 vmcs_write(~0u, 0); 3327 3328 vmcs_write(HOST_RIP, (uintptr_t)&&success); 3329 __asm__ __volatile__ goto ("vmwrite %%rsp, %0; vmlaunch" 3330 : 3331 : "r" ((u64)HOST_RSP) 3332 : "cc", "memory" 3333 : success); 3334 return false; 3335 success: 3336 exit_reason = vmcs_read(EXI_REASON); 3337 TEST_ASSERT(exit_reason == (VMX_FAIL_STATE | VMX_ENTRY_FAILURE) || 3338 exit_reason == (VMX_FAIL_MSR | VMX_ENTRY_FAILURE)); 3339 return true; 3340 } 3341 3342 /* 3343 * Try to launch the current VMCS. 3344 */ 3345 static void test_vmx_vmlaunch(u32 xerror) 3346 { 3347 bool success = vmlaunch(); 3348 3349 report(success == !xerror, "vmlaunch %s", 3350 !xerror ? "succeeds" : "fails"); 3351 if (!success && xerror) 3352 test_assert_vmlaunch_inst_error(xerror); 3353 } 3354 3355 /* 3356 * Try to launch the current VMCS, and expect one of two possible 3357 * errors (or success) codes. 3358 */ 3359 static void test_vmx_vmlaunch2(u32 xerror1, u32 xerror2) 3360 { 3361 bool success = vmlaunch(); 3362 u32 vmx_inst_err; 3363 3364 if (!xerror1 == !xerror2) 3365 report(success == !xerror1, "vmlaunch %s", 3366 !xerror1 ? "succeeds" : "fails"); 3367 3368 if (!success && (xerror1 || xerror2)) { 3369 vmx_inst_err = vmcs_read(VMX_INST_ERROR); 3370 report(vmx_inst_err == xerror1 || vmx_inst_err == xerror2, 3371 "VMX inst error is %d or %d (actual %d)", xerror1, 3372 xerror2, vmx_inst_err); 3373 } 3374 } 3375 3376 static void test_vmx_invalid_controls(void) 3377 { 3378 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_CONTROL_FIELD); 3379 } 3380 3381 static void test_vmx_valid_controls(void) 3382 { 3383 test_vmx_vmlaunch(0); 3384 } 3385 3386 /* 3387 * Test a particular value of a VM-execution control bit, if the value 3388 * is required or if the value is zero. 3389 */ 3390 static void test_rsvd_ctl_bit_value(const char *name, union vmx_ctrl_msr msr, 3391 enum Encoding encoding, unsigned bit, 3392 unsigned val) 3393 { 3394 u32 mask = 1u << bit; 3395 bool expected; 3396 u32 controls; 3397 3398 if (msr.set & mask) 3399 TEST_ASSERT(msr.clr & mask); 3400 3401 /* 3402 * We can't arbitrarily turn on a control bit, because it may 3403 * introduce dependencies on other VMCS fields. So, we only 3404 * test turning on bits that have a required setting. 3405 */ 3406 if (val && (msr.clr & mask) && !(msr.set & mask)) 3407 return; 3408 3409 report_prefix_pushf("%s %s bit %d", 3410 val ? "Set" : "Clear", name, bit); 3411 3412 controls = vmcs_read(encoding); 3413 if (val) { 3414 vmcs_write(encoding, msr.set | mask); 3415 expected = (msr.clr & mask); 3416 } else { 3417 vmcs_write(encoding, msr.set & ~mask); 3418 expected = !(msr.set & mask); 3419 } 3420 if (expected) 3421 test_vmx_valid_controls(); 3422 else 3423 test_vmx_invalid_controls(); 3424 vmcs_write(encoding, controls); 3425 report_prefix_pop(); 3426 } 3427 3428 /* 3429 * Test reserved values of a VM-execution control bit, based on the 3430 * allowed bit settings from the corresponding VMX capability MSR. 3431 */ 3432 static void test_rsvd_ctl_bit(const char *name, union vmx_ctrl_msr msr, 3433 enum Encoding encoding, unsigned bit) 3434 { 3435 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 0); 3436 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 1); 3437 } 3438 3439 /* 3440 * Reserved bits in the pin-based VM-execution controls must be set 3441 * properly. Software may consult the VMX capability MSRs to determine 3442 * the proper settings. 3443 * [Intel SDM] 3444 */ 3445 static void test_pin_based_ctls(void) 3446 { 3447 unsigned bit; 3448 3449 printf("%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PIN" : 3450 "MSR_IA32_VMX_PINBASED_CTLS", ctrl_pin_rev.val); 3451 for (bit = 0; bit < 32; bit++) 3452 test_rsvd_ctl_bit("pin-based controls", 3453 ctrl_pin_rev, PIN_CONTROLS, bit); 3454 } 3455 3456 /* 3457 * Reserved bits in the primary processor-based VM-execution controls 3458 * must be set properly. Software may consult the VMX capability MSRs 3459 * to determine the proper settings. 3460 * [Intel SDM] 3461 */ 3462 static void test_primary_processor_based_ctls(void) 3463 { 3464 unsigned bit; 3465 3466 printf("\n%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PROC" : 3467 "MSR_IA32_VMX_PROCBASED_CTLS", ctrl_cpu_rev[0].val); 3468 for (bit = 0; bit < 32; bit++) 3469 test_rsvd_ctl_bit("primary processor-based controls", 3470 ctrl_cpu_rev[0], CPU_EXEC_CTRL0, bit); 3471 } 3472 3473 /* 3474 * If the "activate secondary controls" primary processor-based 3475 * VM-execution control is 1, reserved bits in the secondary 3476 * processor-based VM-execution controls must be cleared. Software may 3477 * consult the VMX capability MSRs to determine which bits are 3478 * reserved. 3479 * If the "activate secondary controls" primary processor-based 3480 * VM-execution control is 0 (or if the processor does not support the 3481 * 1-setting of that control), no checks are performed on the 3482 * secondary processor-based VM-execution controls. 3483 * [Intel SDM] 3484 */ 3485 static void test_secondary_processor_based_ctls(void) 3486 { 3487 u32 primary; 3488 u32 secondary; 3489 unsigned bit; 3490 3491 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) 3492 return; 3493 3494 primary = vmcs_read(CPU_EXEC_CTRL0); 3495 secondary = vmcs_read(CPU_EXEC_CTRL1); 3496 3497 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3498 printf("\nMSR_IA32_VMX_PROCBASED_CTLS2: %lx\n", ctrl_cpu_rev[1].val); 3499 for (bit = 0; bit < 32; bit++) 3500 test_rsvd_ctl_bit("secondary processor-based controls", 3501 ctrl_cpu_rev[1], CPU_EXEC_CTRL1, bit); 3502 3503 /* 3504 * When the "activate secondary controls" VM-execution control 3505 * is clear, there are no checks on the secondary controls. 3506 */ 3507 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3508 vmcs_write(CPU_EXEC_CTRL1, ~0); 3509 report(vmlaunch(), 3510 "Secondary processor-based controls ignored"); 3511 vmcs_write(CPU_EXEC_CTRL1, secondary); 3512 vmcs_write(CPU_EXEC_CTRL0, primary); 3513 } 3514 3515 static void try_cr3_target_count(unsigned i, unsigned max) 3516 { 3517 report_prefix_pushf("CR3 target count 0x%x", i); 3518 vmcs_write(CR3_TARGET_COUNT, i); 3519 if (i <= max) 3520 test_vmx_valid_controls(); 3521 else 3522 test_vmx_invalid_controls(); 3523 report_prefix_pop(); 3524 } 3525 3526 /* 3527 * The CR3-target count must not be greater than 4. Future processors 3528 * may support a different number of CR3-target values. Software 3529 * should read the VMX capability MSR IA32_VMX_MISC to determine the 3530 * number of values supported. 3531 * [Intel SDM] 3532 */ 3533 static void test_cr3_targets(void) 3534 { 3535 unsigned supported_targets = (rdmsr(MSR_IA32_VMX_MISC) >> 16) & 0x1ff; 3536 u32 cr3_targets = vmcs_read(CR3_TARGET_COUNT); 3537 unsigned i; 3538 3539 printf("\nSupported CR3 targets: %d\n", supported_targets); 3540 TEST_ASSERT(supported_targets <= 256); 3541 3542 try_cr3_target_count(-1u, supported_targets); 3543 try_cr3_target_count(0x80000000, supported_targets); 3544 try_cr3_target_count(0x7fffffff, supported_targets); 3545 for (i = 0; i <= supported_targets + 1; i++) 3546 try_cr3_target_count(i, supported_targets); 3547 vmcs_write(CR3_TARGET_COUNT, cr3_targets); 3548 3549 /* VMWRITE to nonexistent target fields should fail. */ 3550 for (i = supported_targets; i < 256; i++) 3551 TEST_ASSERT(vmcs_write(CR3_TARGET_0 + i*2, 0)); 3552 } 3553 3554 /* 3555 * Test a particular address setting in the VMCS 3556 */ 3557 static void test_vmcs_addr(const char *name, 3558 enum Encoding encoding, 3559 u64 align, 3560 bool ignored, 3561 bool skip_beyond_mapped_ram, 3562 u64 addr) 3563 { 3564 report_prefix_pushf("%s = %lx", name, addr); 3565 vmcs_write(encoding, addr); 3566 if (skip_beyond_mapped_ram && 3567 addr > fwcfg_get_u64(FW_CFG_RAM_SIZE) - align && 3568 addr < (1ul << cpuid_maxphyaddr())) 3569 printf("Skipping physical address beyond mapped RAM\n"); 3570 else if (ignored || (IS_ALIGNED(addr, align) && 3571 addr < (1ul << cpuid_maxphyaddr()))) 3572 test_vmx_valid_controls(); 3573 else 3574 test_vmx_invalid_controls(); 3575 report_prefix_pop(); 3576 } 3577 3578 /* 3579 * Test interesting values for a VMCS address 3580 */ 3581 static void test_vmcs_addr_values(const char *name, 3582 enum Encoding encoding, 3583 u64 align, 3584 bool ignored, 3585 bool skip_beyond_mapped_ram, 3586 u32 bit_start, u32 bit_end) 3587 { 3588 unsigned i; 3589 u64 orig_val = vmcs_read(encoding); 3590 3591 for (i = bit_start; i <= bit_end; i++) 3592 test_vmcs_addr(name, encoding, align, ignored, 3593 skip_beyond_mapped_ram, 1ul << i); 3594 3595 test_vmcs_addr(name, encoding, align, ignored, 3596 skip_beyond_mapped_ram, PAGE_SIZE - 1); 3597 test_vmcs_addr(name, encoding, align, ignored, 3598 skip_beyond_mapped_ram, PAGE_SIZE); 3599 test_vmcs_addr(name, encoding, align, ignored, 3600 skip_beyond_mapped_ram, 3601 (1ul << cpuid_maxphyaddr()) - PAGE_SIZE); 3602 test_vmcs_addr(name, encoding, align, ignored, 3603 skip_beyond_mapped_ram, -1ul); 3604 3605 vmcs_write(encoding, orig_val); 3606 } 3607 3608 /* 3609 * Test a physical address reference in the VMCS, when the corresponding 3610 * feature is enabled and when the corresponding feature is disabled. 3611 */ 3612 static void test_vmcs_addr_reference(u32 control_bit, enum Encoding field, 3613 const char *field_name, 3614 const char *control_name, u64 align, 3615 bool skip_beyond_mapped_ram, 3616 bool control_primary) 3617 { 3618 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 3619 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 3620 u64 page_addr; 3621 3622 if (control_primary) { 3623 if (!(ctrl_cpu_rev[0].clr & control_bit)) 3624 return; 3625 } else { 3626 if (!(ctrl_cpu_rev[1].clr & control_bit)) 3627 return; 3628 } 3629 3630 page_addr = vmcs_read(field); 3631 3632 report_prefix_pushf("%s enabled", control_name); 3633 if (control_primary) { 3634 vmcs_write(CPU_EXEC_CTRL0, primary | control_bit); 3635 } else { 3636 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3637 vmcs_write(CPU_EXEC_CTRL1, secondary | control_bit); 3638 } 3639 3640 test_vmcs_addr_values(field_name, field, align, false, 3641 skip_beyond_mapped_ram, 0, 63); 3642 report_prefix_pop(); 3643 3644 report_prefix_pushf("%s disabled", control_name); 3645 if (control_primary) { 3646 vmcs_write(CPU_EXEC_CTRL0, primary & ~control_bit); 3647 } else { 3648 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3649 vmcs_write(CPU_EXEC_CTRL1, secondary & ~control_bit); 3650 } 3651 3652 test_vmcs_addr_values(field_name, field, align, true, false, 0, 63); 3653 report_prefix_pop(); 3654 3655 vmcs_write(field, page_addr); 3656 vmcs_write(CPU_EXEC_CTRL0, primary); 3657 vmcs_write(CPU_EXEC_CTRL1, secondary); 3658 } 3659 3660 /* 3661 * If the "use I/O bitmaps" VM-execution control is 1, bits 11:0 of 3662 * each I/O-bitmap address must be 0. Neither address should set any 3663 * bits beyond the processor's physical-address width. 3664 * [Intel SDM] 3665 */ 3666 static void test_io_bitmaps(void) 3667 { 3668 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_A, 3669 "I/O bitmap A", "Use I/O bitmaps", 3670 PAGE_SIZE, false, true); 3671 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_B, 3672 "I/O bitmap B", "Use I/O bitmaps", 3673 PAGE_SIZE, false, true); 3674 } 3675 3676 /* 3677 * If the "use MSR bitmaps" VM-execution control is 1, bits 11:0 of 3678 * the MSR-bitmap address must be 0. The address should not set any 3679 * bits beyond the processor's physical-address width. 3680 * [Intel SDM] 3681 */ 3682 static void test_msr_bitmap(void) 3683 { 3684 test_vmcs_addr_reference(CPU_MSR_BITMAP, MSR_BITMAP, 3685 "MSR bitmap", "Use MSR bitmaps", 3686 PAGE_SIZE, false, true); 3687 } 3688 3689 /* 3690 * If the "use TPR shadow" VM-execution control is 1, the virtual-APIC 3691 * address must satisfy the following checks: 3692 * - Bits 11:0 of the address must be 0. 3693 * - The address should not set any bits beyond the processor's 3694 * physical-address width. 3695 * [Intel SDM] 3696 */ 3697 static void test_apic_virt_addr(void) 3698 { 3699 /* 3700 * Ensure the processor will never use the virtual-APIC page, since 3701 * we will point it to invalid RAM. Otherwise KVM is puzzled about 3702 * what we're trying to achieve and fails vmentry. 3703 */ 3704 u32 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 3705 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0 | CPU_CR8_LOAD | CPU_CR8_STORE); 3706 test_vmcs_addr_reference(CPU_TPR_SHADOW, APIC_VIRT_ADDR, 3707 "virtual-APIC address", "Use TPR shadow", 3708 PAGE_SIZE, false, true); 3709 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 3710 } 3711 3712 /* 3713 * If the "virtualize APIC-accesses" VM-execution control is 1, the 3714 * APIC-access address must satisfy the following checks: 3715 * - Bits 11:0 of the address must be 0. 3716 * - The address should not set any bits beyond the processor's 3717 * physical-address width. 3718 * [Intel SDM] 3719 */ 3720 static void test_apic_access_addr(void) 3721 { 3722 void *apic_access_page = alloc_page(); 3723 3724 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_page)); 3725 3726 test_vmcs_addr_reference(CPU_VIRT_APIC_ACCESSES, APIC_ACCS_ADDR, 3727 "APIC-access address", 3728 "virtualize APIC-accesses", PAGE_SIZE, 3729 true, false); 3730 } 3731 3732 static bool set_bit_pattern(u8 mask, u32 *secondary) 3733 { 3734 u8 i; 3735 bool flag = false; 3736 u32 test_bits[3] = { 3737 CPU_VIRT_X2APIC, 3738 CPU_APIC_REG_VIRT, 3739 CPU_VINTD 3740 }; 3741 3742 for (i = 0; i < ARRAY_SIZE(test_bits); i++) { 3743 if ((mask & (1u << i)) && 3744 (ctrl_cpu_rev[1].clr & test_bits[i])) { 3745 *secondary |= test_bits[i]; 3746 flag = true; 3747 } 3748 } 3749 3750 return (flag); 3751 } 3752 3753 /* 3754 * If the "use TPR shadow" VM-execution control is 0, the following 3755 * VM-execution controls must also be 0: 3756 * - virtualize x2APIC mode 3757 * - APIC-register virtualization 3758 * - virtual-interrupt delivery 3759 * [Intel SDM] 3760 * 3761 * 2. If the "virtualize x2APIC mode" VM-execution control is 1, the 3762 * "virtualize APIC accesses" VM-execution control must be 0. 3763 * [Intel SDM] 3764 */ 3765 static void test_apic_virtual_ctls(void) 3766 { 3767 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3768 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3769 u32 primary = saved_primary; 3770 u32 secondary = saved_secondary; 3771 bool is_ctrl_valid = false; 3772 char str[10] = "disabled"; 3773 u8 i = 0, j; 3774 3775 /* 3776 * First test 3777 */ 3778 if (!((ctrl_cpu_rev[0].clr & (CPU_SECONDARY | CPU_TPR_SHADOW)) == 3779 (CPU_SECONDARY | CPU_TPR_SHADOW))) 3780 return; 3781 3782 primary |= CPU_SECONDARY; 3783 primary &= ~CPU_TPR_SHADOW; 3784 vmcs_write(CPU_EXEC_CTRL0, primary); 3785 3786 while (1) { 3787 for (j = 1; j < 8; j++) { 3788 secondary &= ~(CPU_VIRT_X2APIC | CPU_APIC_REG_VIRT | CPU_VINTD); 3789 if (primary & CPU_TPR_SHADOW) { 3790 is_ctrl_valid = true; 3791 } else { 3792 if (! set_bit_pattern(j, &secondary)) 3793 is_ctrl_valid = true; 3794 else 3795 is_ctrl_valid = false; 3796 } 3797 3798 vmcs_write(CPU_EXEC_CTRL1, secondary); 3799 report_prefix_pushf("Use TPR shadow %s, virtualize x2APIC mode %s, APIC-register virtualization %s, virtual-interrupt delivery %s", 3800 str, (secondary & CPU_VIRT_X2APIC) ? "enabled" : "disabled", (secondary & CPU_APIC_REG_VIRT) ? "enabled" : "disabled", (secondary & CPU_VINTD) ? "enabled" : "disabled"); 3801 if (is_ctrl_valid) 3802 test_vmx_valid_controls(); 3803 else 3804 test_vmx_invalid_controls(); 3805 report_prefix_pop(); 3806 } 3807 3808 if (i == 1) 3809 break; 3810 i++; 3811 3812 primary |= CPU_TPR_SHADOW; 3813 vmcs_write(CPU_EXEC_CTRL0, primary); 3814 strcpy(str, "enabled"); 3815 } 3816 3817 /* 3818 * Second test 3819 */ 3820 u32 apic_virt_ctls = (CPU_VIRT_X2APIC | CPU_VIRT_APIC_ACCESSES); 3821 3822 primary = saved_primary; 3823 secondary = saved_secondary; 3824 if (!((ctrl_cpu_rev[1].clr & apic_virt_ctls) == apic_virt_ctls)) 3825 return; 3826 3827 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3828 secondary &= ~CPU_VIRT_APIC_ACCESSES; 3829 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_X2APIC); 3830 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access disabled"); 3831 test_vmx_valid_controls(); 3832 report_prefix_pop(); 3833 3834 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_APIC_ACCESSES); 3835 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access enabled"); 3836 test_vmx_valid_controls(); 3837 report_prefix_pop(); 3838 3839 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_X2APIC); 3840 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access enabled"); 3841 test_vmx_invalid_controls(); 3842 report_prefix_pop(); 3843 3844 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_APIC_ACCESSES); 3845 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access disabled"); 3846 test_vmx_valid_controls(); 3847 report_prefix_pop(); 3848 3849 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3850 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3851 } 3852 3853 /* 3854 * If the "virtual-interrupt delivery" VM-execution control is 1, the 3855 * "external-interrupt exiting" VM-execution control must be 1. 3856 * [Intel SDM] 3857 */ 3858 static void test_virtual_intr_ctls(void) 3859 { 3860 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3861 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3862 u32 saved_pin = vmcs_read(PIN_CONTROLS); 3863 u32 primary = saved_primary; 3864 u32 secondary = saved_secondary; 3865 u32 pin = saved_pin; 3866 3867 if (!((ctrl_cpu_rev[1].clr & CPU_VINTD) && 3868 (ctrl_pin_rev.clr & PIN_EXTINT))) 3869 return; 3870 3871 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 3872 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VINTD); 3873 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 3874 report_prefix_pushf("Virtualize interrupt-delivery disabled; external-interrupt exiting disabled"); 3875 test_vmx_valid_controls(); 3876 report_prefix_pop(); 3877 3878 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VINTD); 3879 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 3880 test_vmx_invalid_controls(); 3881 report_prefix_pop(); 3882 3883 vmcs_write(PIN_CONTROLS, pin | PIN_EXTINT); 3884 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting enabled"); 3885 test_vmx_valid_controls(); 3886 report_prefix_pop(); 3887 3888 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 3889 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 3890 test_vmx_invalid_controls(); 3891 report_prefix_pop(); 3892 3893 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3894 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3895 vmcs_write(PIN_CONTROLS, saved_pin); 3896 } 3897 3898 static void test_pi_desc_addr(u64 addr, bool is_ctrl_valid) 3899 { 3900 vmcs_write(POSTED_INTR_DESC_ADDR, addr); 3901 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-descriptor-address 0x%lx", addr); 3902 if (is_ctrl_valid) 3903 test_vmx_valid_controls(); 3904 else 3905 test_vmx_invalid_controls(); 3906 report_prefix_pop(); 3907 } 3908 3909 /* 3910 * If the "process posted interrupts" VM-execution control is 1, the 3911 * following must be true: 3912 * 3913 * - The "virtual-interrupt delivery" VM-execution control is 1. 3914 * - The "acknowledge interrupt on exit" VM-exit control is 1. 3915 * - The posted-interrupt notification vector has a value in the 3916 * - range 0 - 255 (bits 15:8 are all 0). 3917 * - Bits 5:0 of the posted-interrupt descriptor address are all 0. 3918 * - The posted-interrupt descriptor address does not set any bits 3919 * beyond the processor's physical-address width. 3920 * [Intel SDM] 3921 */ 3922 static void test_posted_intr(void) 3923 { 3924 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3925 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3926 u32 saved_pin = vmcs_read(PIN_CONTROLS); 3927 u32 exit_ctl_saved = vmcs_read(EXI_CONTROLS); 3928 u32 primary = saved_primary; 3929 u32 secondary = saved_secondary; 3930 u32 pin = saved_pin; 3931 u32 exit_ctl = exit_ctl_saved; 3932 u16 vec; 3933 int i; 3934 3935 if (!((ctrl_pin_rev.clr & PIN_POST_INTR) && 3936 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 3937 (ctrl_exit_rev.clr & EXI_INTA))) 3938 return; 3939 3940 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 3941 3942 /* 3943 * Test virtual-interrupt-delivery and acknowledge-interrupt-on-exit 3944 */ 3945 pin |= PIN_POST_INTR; 3946 vmcs_write(PIN_CONTROLS, pin); 3947 secondary &= ~CPU_VINTD; 3948 vmcs_write(CPU_EXEC_CTRL1, secondary); 3949 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled"); 3950 test_vmx_invalid_controls(); 3951 report_prefix_pop(); 3952 3953 secondary |= CPU_VINTD; 3954 vmcs_write(CPU_EXEC_CTRL1, secondary); 3955 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled"); 3956 test_vmx_invalid_controls(); 3957 report_prefix_pop(); 3958 3959 exit_ctl &= ~EXI_INTA; 3960 vmcs_write(EXI_CONTROLS, exit_ctl); 3961 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit disabled"); 3962 test_vmx_invalid_controls(); 3963 report_prefix_pop(); 3964 3965 exit_ctl |= EXI_INTA; 3966 vmcs_write(EXI_CONTROLS, exit_ctl); 3967 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 3968 test_vmx_valid_controls(); 3969 report_prefix_pop(); 3970 3971 secondary &= ~CPU_VINTD; 3972 vmcs_write(CPU_EXEC_CTRL1, secondary); 3973 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled; acknowledge-interrupt-on-exit enabled"); 3974 test_vmx_invalid_controls(); 3975 report_prefix_pop(); 3976 3977 secondary |= CPU_VINTD; 3978 vmcs_write(CPU_EXEC_CTRL1, secondary); 3979 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 3980 test_vmx_valid_controls(); 3981 report_prefix_pop(); 3982 3983 /* 3984 * Test posted-interrupt notification vector 3985 */ 3986 for (i = 0; i < 8; i++) { 3987 vec = (1ul << i); 3988 vmcs_write(PINV, vec); 3989 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 3990 test_vmx_valid_controls(); 3991 report_prefix_pop(); 3992 } 3993 for (i = 8; i < 16; i++) { 3994 vec = (1ul << i); 3995 vmcs_write(PINV, vec); 3996 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 3997 test_vmx_invalid_controls(); 3998 report_prefix_pop(); 3999 } 4000 4001 vec &= ~(0xff << 8); 4002 vmcs_write(PINV, vec); 4003 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 4004 test_vmx_valid_controls(); 4005 report_prefix_pop(); 4006 4007 /* 4008 * Test posted-interrupt descriptor address 4009 */ 4010 for (i = 0; i < 6; i++) { 4011 test_pi_desc_addr(1ul << i, false); 4012 } 4013 4014 test_pi_desc_addr(0xf0, false); 4015 test_pi_desc_addr(0xff, false); 4016 test_pi_desc_addr(0x0f, false); 4017 test_pi_desc_addr(0x8000, true); 4018 test_pi_desc_addr(0x00, true); 4019 test_pi_desc_addr(0xc000, true); 4020 4021 test_vmcs_addr_values("process-posted interrupts", 4022 POSTED_INTR_DESC_ADDR, 64, 4023 false, false, 0, 63); 4024 4025 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 4026 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 4027 vmcs_write(PIN_CONTROLS, saved_pin); 4028 } 4029 4030 static void test_apic_ctls(void) 4031 { 4032 test_apic_virt_addr(); 4033 test_apic_access_addr(); 4034 test_apic_virtual_ctls(); 4035 test_virtual_intr_ctls(); 4036 test_posted_intr(); 4037 } 4038 4039 /* 4040 * If the "enable VPID" VM-execution control is 1, the value of the 4041 * of the VPID VM-execution control field must not be 0000H. 4042 * [Intel SDM] 4043 */ 4044 static void test_vpid(void) 4045 { 4046 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 4047 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 4048 u16 vpid = 0x0000; 4049 int i; 4050 4051 if (!is_vpid_supported()) { 4052 report_skip("%s : Secondary controls and/or VPID not supported", __func__); 4053 return; 4054 } 4055 4056 vmcs_write(CPU_EXEC_CTRL0, saved_primary | CPU_SECONDARY); 4057 vmcs_write(CPU_EXEC_CTRL1, saved_secondary & ~CPU_VPID); 4058 vmcs_write(VPID, vpid); 4059 report_prefix_pushf("VPID disabled; VPID value %x", vpid); 4060 test_vmx_valid_controls(); 4061 report_prefix_pop(); 4062 4063 vmcs_write(CPU_EXEC_CTRL1, saved_secondary | CPU_VPID); 4064 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 4065 test_vmx_invalid_controls(); 4066 report_prefix_pop(); 4067 4068 for (i = 0; i < 16; i++) { 4069 vpid = (short)1 << i;; 4070 vmcs_write(VPID, vpid); 4071 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 4072 test_vmx_valid_controls(); 4073 report_prefix_pop(); 4074 } 4075 4076 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 4077 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 4078 } 4079 4080 static void set_vtpr(unsigned vtpr) 4081 { 4082 *(u32 *)phys_to_virt(vmcs_read(APIC_VIRT_ADDR) + APIC_TASKPRI) = vtpr; 4083 } 4084 4085 static void try_tpr_threshold_and_vtpr(unsigned threshold, unsigned vtpr) 4086 { 4087 bool valid = true; 4088 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4089 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4090 4091 if ((primary & CPU_TPR_SHADOW) && 4092 (!(primary & CPU_SECONDARY) || 4093 !(secondary & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 4094 valid = (threshold & 0xf) <= ((vtpr >> 4) & 0xf); 4095 4096 set_vtpr(vtpr); 4097 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0x%x", 4098 threshold, (vtpr >> 4) & 0xf); 4099 if (valid) 4100 test_vmx_valid_controls(); 4101 else 4102 test_vmx_invalid_controls(); 4103 report_prefix_pop(); 4104 } 4105 4106 static void test_invalid_event_injection(void) 4107 { 4108 u32 ent_intr_info_save = vmcs_read(ENT_INTR_INFO); 4109 u32 ent_intr_error_save = vmcs_read(ENT_INTR_ERROR); 4110 u32 ent_inst_len_save = vmcs_read(ENT_INST_LEN); 4111 u32 primary_save = vmcs_read(CPU_EXEC_CTRL0); 4112 u32 secondary_save = vmcs_read(CPU_EXEC_CTRL1); 4113 u64 guest_cr0_save = vmcs_read(GUEST_CR0); 4114 u32 ent_intr_info_base = INTR_INFO_VALID_MASK; 4115 u32 ent_intr_info, ent_intr_err, ent_intr_len; 4116 u32 cnt; 4117 4118 /* Setup */ 4119 report_prefix_push("invalid event injection"); 4120 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4121 vmcs_write(ENT_INST_LEN, 0x00000001); 4122 4123 /* The field's interruption type is not set to a reserved value. */ 4124 ent_intr_info = ent_intr_info_base | INTR_TYPE_RESERVED | DE_VECTOR; 4125 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4126 "RESERVED interruption type invalid [-]", 4127 ent_intr_info); 4128 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4129 test_vmx_invalid_controls(); 4130 report_prefix_pop(); 4131 4132 ent_intr_info = ent_intr_info_base | INTR_TYPE_EXT_INTR | 4133 DE_VECTOR; 4134 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4135 "RESERVED interruption type invalid [+]", 4136 ent_intr_info); 4137 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4138 test_vmx_valid_controls(); 4139 report_prefix_pop(); 4140 4141 /* If the interruption type is other event, the vector is 0. */ 4142 ent_intr_info = ent_intr_info_base | INTR_TYPE_OTHER_EVENT | DB_VECTOR; 4143 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4144 "(OTHER EVENT && vector != 0) invalid [-]", 4145 ent_intr_info); 4146 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4147 test_vmx_invalid_controls(); 4148 report_prefix_pop(); 4149 4150 /* If the interruption type is NMI, the vector is 2 (negative case). */ 4151 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | DE_VECTOR; 4152 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4153 "(NMI && vector != 2) invalid [-]", ent_intr_info); 4154 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4155 test_vmx_invalid_controls(); 4156 report_prefix_pop(); 4157 4158 /* If the interruption type is NMI, the vector is 2 (positive case). */ 4159 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | NMI_VECTOR; 4160 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4161 "(NMI && vector == 2) valid [+]", ent_intr_info); 4162 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4163 test_vmx_valid_controls(); 4164 report_prefix_pop(); 4165 4166 /* 4167 * If the interruption type 4168 * is HW exception, the vector is at most 31. 4169 */ 4170 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 0x20; 4171 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4172 "(HW exception && vector > 31) invalid [-]", 4173 ent_intr_info); 4174 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4175 test_vmx_invalid_controls(); 4176 report_prefix_pop(); 4177 4178 /* 4179 * deliver-error-code is 1 iff either 4180 * (a) the "unrestricted guest" VM-execution control is 0 4181 * (b) CR0.PE is set. 4182 */ 4183 4184 /* Assert that unrestricted guest is disabled or unsupported */ 4185 assert(!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 4186 !(secondary_save & CPU_URG)); 4187 4188 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4189 GP_VECTOR; 4190 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4191 "error code <-> (!URG || prot_mode) [-]", 4192 ent_intr_info); 4193 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4194 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4195 test_vmx_invalid_controls(); 4196 report_prefix_pop(); 4197 4198 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4199 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4200 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4201 "error code <-> (!URG || prot_mode) [+]", 4202 ent_intr_info); 4203 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4204 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4205 test_vmx_valid_controls(); 4206 report_prefix_pop(); 4207 4208 if (enable_unrestricted_guest(false)) 4209 goto skip_unrestricted_guest; 4210 4211 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4212 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4213 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4214 "error code <-> (!URG || prot_mode) [-]", 4215 ent_intr_info); 4216 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4217 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4218 test_vmx_invalid_controls(); 4219 report_prefix_pop(); 4220 4221 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4222 GP_VECTOR; 4223 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4224 "error code <-> (!URG || prot_mode) [-]", 4225 ent_intr_info); 4226 vmcs_write(GUEST_CR0, guest_cr0_save | X86_CR0_PE); 4227 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4228 test_vmx_invalid_controls(); 4229 report_prefix_pop(); 4230 4231 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4232 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4233 4234 skip_unrestricted_guest: 4235 vmcs_write(GUEST_CR0, guest_cr0_save); 4236 4237 /* deliver-error-code is 1 iff the interruption type is HW exception */ 4238 report_prefix_push("error code <-> HW exception"); 4239 for (cnt = 0; cnt < 8; cnt++) { 4240 u32 exception_type_mask = cnt << 8; 4241 u32 deliver_error_code_mask = 4242 exception_type_mask != INTR_TYPE_HARD_EXCEPTION ? 4243 INTR_INFO_DELIVER_CODE_MASK : 0; 4244 4245 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4246 exception_type_mask | GP_VECTOR; 4247 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4248 ent_intr_info); 4249 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4250 test_vmx_invalid_controls(); 4251 report_prefix_pop(); 4252 } 4253 report_prefix_pop(); 4254 4255 /* 4256 * deliver-error-code is 1 iff the the vector 4257 * indicates an exception that would normally deliver an error code 4258 */ 4259 report_prefix_push("error code <-> vector delivers error code"); 4260 for (cnt = 0; cnt < 32; cnt++) { 4261 bool has_error_code = false; 4262 u32 deliver_error_code_mask; 4263 4264 switch (cnt) { 4265 case DF_VECTOR: 4266 case TS_VECTOR: 4267 case NP_VECTOR: 4268 case SS_VECTOR: 4269 case GP_VECTOR: 4270 case PF_VECTOR: 4271 case AC_VECTOR: 4272 has_error_code = true; 4273 case CP_VECTOR: 4274 /* Some CPUs have error code and some do not, skip */ 4275 continue; 4276 } 4277 4278 /* Negative case */ 4279 deliver_error_code_mask = has_error_code ? 4280 0 : 4281 INTR_INFO_DELIVER_CODE_MASK; 4282 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4283 INTR_TYPE_HARD_EXCEPTION | cnt; 4284 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4285 ent_intr_info); 4286 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4287 test_vmx_invalid_controls(); 4288 report_prefix_pop(); 4289 4290 /* Positive case */ 4291 deliver_error_code_mask = has_error_code ? 4292 INTR_INFO_DELIVER_CODE_MASK : 4293 0; 4294 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4295 INTR_TYPE_HARD_EXCEPTION | cnt; 4296 report_prefix_pushf("VM-entry intr info=0x%x [+]", 4297 ent_intr_info); 4298 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4299 test_vmx_valid_controls(); 4300 report_prefix_pop(); 4301 } 4302 report_prefix_pop(); 4303 4304 /* Reserved bits in the field (30:12) are 0. */ 4305 report_prefix_push("reserved bits clear"); 4306 for (cnt = 12; cnt <= 30; cnt++) { 4307 ent_intr_info = ent_intr_info_base | 4308 INTR_INFO_DELIVER_CODE_MASK | 4309 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR | 4310 (1U << cnt); 4311 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4312 ent_intr_info); 4313 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4314 test_vmx_invalid_controls(); 4315 report_prefix_pop(); 4316 } 4317 report_prefix_pop(); 4318 4319 /* 4320 * If deliver-error-code is 1 4321 * bits 31:16 of the VM-entry exception error-code field are 0. 4322 */ 4323 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4324 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4325 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4326 "VM-entry exception error code[31:16] clear", 4327 ent_intr_info); 4328 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4329 for (cnt = 16; cnt <= 31; cnt++) { 4330 ent_intr_err = 1U << cnt; 4331 report_prefix_pushf("VM-entry intr error=0x%x [-]", 4332 ent_intr_err); 4333 vmcs_write(ENT_INTR_ERROR, ent_intr_err); 4334 test_vmx_invalid_controls(); 4335 report_prefix_pop(); 4336 } 4337 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4338 report_prefix_pop(); 4339 4340 /* 4341 * If the interruption type is software interrupt, software exception, 4342 * or privileged software exception, the VM-entry instruction-length 4343 * field is in the range 0 - 15. 4344 */ 4345 4346 for (cnt = 0; cnt < 3; cnt++) { 4347 switch (cnt) { 4348 case 0: 4349 ent_intr_info = ent_intr_info_base | 4350 INTR_TYPE_SOFT_INTR; 4351 break; 4352 case 1: 4353 ent_intr_info = ent_intr_info_base | 4354 INTR_TYPE_SOFT_EXCEPTION; 4355 break; 4356 case 2: 4357 ent_intr_info = ent_intr_info_base | 4358 INTR_TYPE_PRIV_SW_EXCEPTION; 4359 break; 4360 } 4361 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4362 "VM-entry instruction-length check", 4363 ent_intr_info); 4364 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4365 4366 /* Instruction length set to -1 (0xFFFFFFFF) should fail */ 4367 ent_intr_len = -1; 4368 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4369 ent_intr_len); 4370 vmcs_write(ENT_INST_LEN, ent_intr_len); 4371 test_vmx_invalid_controls(); 4372 report_prefix_pop(); 4373 4374 /* Instruction length set to 16 should fail */ 4375 ent_intr_len = 0x00000010; 4376 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4377 ent_intr_len); 4378 vmcs_write(ENT_INST_LEN, 0x00000010); 4379 test_vmx_invalid_controls(); 4380 report_prefix_pop(); 4381 4382 report_prefix_pop(); 4383 } 4384 4385 /* Cleanup */ 4386 vmcs_write(ENT_INTR_INFO, ent_intr_info_save); 4387 vmcs_write(ENT_INTR_ERROR, ent_intr_error_save); 4388 vmcs_write(ENT_INST_LEN, ent_inst_len_save); 4389 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4390 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4391 vmcs_write(GUEST_CR0, guest_cr0_save); 4392 report_prefix_pop(); 4393 } 4394 4395 /* 4396 * Test interesting vTPR values for a given TPR threshold. 4397 */ 4398 static void test_vtpr_values(unsigned threshold) 4399 { 4400 try_tpr_threshold_and_vtpr(threshold, (threshold - 1) << 4); 4401 try_tpr_threshold_and_vtpr(threshold, threshold << 4); 4402 try_tpr_threshold_and_vtpr(threshold, (threshold + 1) << 4); 4403 } 4404 4405 static void try_tpr_threshold(unsigned threshold) 4406 { 4407 bool valid = true; 4408 4409 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4410 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4411 4412 if ((primary & CPU_TPR_SHADOW) && !((primary & CPU_SECONDARY) && 4413 (secondary & CPU_VINTD))) 4414 valid = !(threshold >> 4); 4415 4416 set_vtpr(-1); 4417 vmcs_write(TPR_THRESHOLD, threshold); 4418 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0xf", threshold); 4419 if (valid) 4420 test_vmx_valid_controls(); 4421 else 4422 test_vmx_invalid_controls(); 4423 report_prefix_pop(); 4424 4425 if (valid) 4426 test_vtpr_values(threshold); 4427 } 4428 4429 /* 4430 * Test interesting TPR threshold values. 4431 */ 4432 static void test_tpr_threshold_values(void) 4433 { 4434 unsigned i; 4435 4436 for (i = 0; i < 0x10; i++) 4437 try_tpr_threshold(i); 4438 for (i = 4; i < 32; i++) 4439 try_tpr_threshold(1u << i); 4440 try_tpr_threshold(-1u); 4441 try_tpr_threshold(0x7fffffff); 4442 } 4443 4444 /* 4445 * This test covers the following two VM entry checks: 4446 * 4447 * i) If the "use TPR shadow" VM-execution control is 1 and the 4448 * "virtual-interrupt delivery" VM-execution control is 0, bits 4449 * 31:4 of the TPR threshold VM-execution control field must 4450 be 0. 4451 * [Intel SDM] 4452 * 4453 * ii) If the "use TPR shadow" VM-execution control is 1, the 4454 * "virtual-interrupt delivery" VM-execution control is 0 4455 * and the "virtualize APIC accesses" VM-execution control 4456 * is 0, the value of bits 3:0 of the TPR threshold VM-execution 4457 * control field must not be greater than the value of bits 4458 * 7:4 of VTPR. 4459 * [Intel SDM] 4460 */ 4461 static void test_tpr_threshold(void) 4462 { 4463 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4464 u64 apic_virt_addr = vmcs_read(APIC_VIRT_ADDR); 4465 u64 threshold = vmcs_read(TPR_THRESHOLD); 4466 void *virtual_apic_page; 4467 4468 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) 4469 return; 4470 4471 virtual_apic_page = alloc_page(); 4472 memset(virtual_apic_page, 0xff, PAGE_SIZE); 4473 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 4474 4475 vmcs_write(CPU_EXEC_CTRL0, primary & ~(CPU_TPR_SHADOW | CPU_SECONDARY)); 4476 report_prefix_pushf("Use TPR shadow disabled, secondary controls disabled"); 4477 test_tpr_threshold_values(); 4478 report_prefix_pop(); 4479 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_TPR_SHADOW); 4480 report_prefix_pushf("Use TPR shadow enabled, secondary controls disabled"); 4481 test_tpr_threshold_values(); 4482 report_prefix_pop(); 4483 4484 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4485 (ctrl_cpu_rev[1].clr & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 4486 goto out; 4487 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4488 4489 if (ctrl_cpu_rev[1].clr & CPU_VINTD) { 4490 vmcs_write(CPU_EXEC_CTRL1, CPU_VINTD); 4491 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4492 test_tpr_threshold_values(); 4493 report_prefix_pop(); 4494 4495 vmcs_write(CPU_EXEC_CTRL0, 4496 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4497 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4498 test_tpr_threshold_values(); 4499 report_prefix_pop(); 4500 } 4501 4502 if (ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES) { 4503 vmcs_write(CPU_EXEC_CTRL0, 4504 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4505 vmcs_write(CPU_EXEC_CTRL1, CPU_VIRT_APIC_ACCESSES); 4506 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4507 test_tpr_threshold_values(); 4508 report_prefix_pop(); 4509 4510 vmcs_write(CPU_EXEC_CTRL0, 4511 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4512 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4513 test_tpr_threshold_values(); 4514 report_prefix_pop(); 4515 } 4516 4517 if ((ctrl_cpu_rev[1].clr & 4518 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) == 4519 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) { 4520 vmcs_write(CPU_EXEC_CTRL0, 4521 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4522 vmcs_write(CPU_EXEC_CTRL1, 4523 CPU_VINTD | CPU_VIRT_APIC_ACCESSES); 4524 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4525 test_tpr_threshold_values(); 4526 report_prefix_pop(); 4527 4528 vmcs_write(CPU_EXEC_CTRL0, 4529 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4530 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4531 test_tpr_threshold_values(); 4532 report_prefix_pop(); 4533 } 4534 4535 vmcs_write(CPU_EXEC_CTRL1, secondary); 4536 out: 4537 vmcs_write(TPR_THRESHOLD, threshold); 4538 vmcs_write(APIC_VIRT_ADDR, apic_virt_addr); 4539 vmcs_write(CPU_EXEC_CTRL0, primary); 4540 } 4541 4542 /* 4543 * This test verifies the following two vmentry checks: 4544 * 4545 * If the "NMI exiting" VM-execution control is 0, "Virtual NMIs" 4546 * VM-execution control must be 0. 4547 * [Intel SDM] 4548 * 4549 * If the "virtual NMIs" VM-execution control is 0, the "NMI-window 4550 * exiting" VM-execution control must be 0. 4551 * [Intel SDM] 4552 */ 4553 static void test_nmi_ctrls(void) 4554 { 4555 u32 pin_ctrls, cpu_ctrls0, test_pin_ctrls, test_cpu_ctrls0; 4556 4557 if ((ctrl_pin_rev.clr & (PIN_NMI | PIN_VIRT_NMI)) != 4558 (PIN_NMI | PIN_VIRT_NMI)) { 4559 report_skip("%s : NMI exiting and/or Virtual NMIs not supported", __func__); 4560 return; 4561 } 4562 4563 /* Save the controls so that we can restore them after our tests */ 4564 pin_ctrls = vmcs_read(PIN_CONTROLS); 4565 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 4566 4567 test_pin_ctrls = pin_ctrls & ~(PIN_NMI | PIN_VIRT_NMI); 4568 test_cpu_ctrls0 = cpu_ctrls0 & ~CPU_NMI_WINDOW; 4569 4570 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4571 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs disabled"); 4572 test_vmx_valid_controls(); 4573 report_prefix_pop(); 4574 4575 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_VIRT_NMI); 4576 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs enabled"); 4577 test_vmx_invalid_controls(); 4578 report_prefix_pop(); 4579 4580 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4581 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs enabled"); 4582 test_vmx_valid_controls(); 4583 report_prefix_pop(); 4584 4585 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_NMI); 4586 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs disabled"); 4587 test_vmx_valid_controls(); 4588 report_prefix_pop(); 4589 4590 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 4591 report_info("NMI-window exiting is not supported, skipping..."); 4592 goto done; 4593 } 4594 4595 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4596 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4597 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting enabled"); 4598 test_vmx_invalid_controls(); 4599 report_prefix_pop(); 4600 4601 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4602 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4603 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting disabled"); 4604 test_vmx_valid_controls(); 4605 report_prefix_pop(); 4606 4607 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4608 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4609 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting enabled"); 4610 test_vmx_valid_controls(); 4611 report_prefix_pop(); 4612 4613 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4614 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4615 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting disabled"); 4616 test_vmx_valid_controls(); 4617 report_prefix_pop(); 4618 4619 /* Restore the controls to their original values */ 4620 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 4621 done: 4622 vmcs_write(PIN_CONTROLS, pin_ctrls); 4623 } 4624 4625 static void test_eptp_ad_bit(u64 eptp, bool is_ctrl_valid) 4626 { 4627 vmcs_write(EPTP, eptp); 4628 report_prefix_pushf("Enable-EPT enabled; EPT accessed and dirty flag %s", 4629 (eptp & EPTP_AD_FLAG) ? "1": "0"); 4630 if (is_ctrl_valid) 4631 test_vmx_valid_controls(); 4632 else 4633 test_vmx_invalid_controls(); 4634 report_prefix_pop(); 4635 4636 } 4637 4638 /* 4639 * 1. If the "enable EPT" VM-execution control is 1, the "EPTP VM-execution" 4640 * control field must satisfy the following checks: 4641 * 4642 * - The EPT memory type (bits 2:0) must be a value supported by the 4643 * processor as indicated in the IA32_VMX_EPT_VPID_CAP MSR. 4644 * - Bits 5:3 (1 less than the EPT page-walk length) must indicate a 4645 * supported EPT page-walk length. 4646 * - Bit 6 (enable bit for accessed and dirty flags for EPT) must be 4647 * 0 if bit 21 of the IA32_VMX_EPT_VPID_CAP MSR is read as 0, 4648 * indicating that the processor does not support accessed and dirty 4649 * dirty flags for EPT. 4650 * - Reserved bits 11:7 and 63:N (where N is the processor's 4651 * physical-address width) must all be 0. 4652 * 4653 * 2. If the "unrestricted guest" VM-execution control is 1, the 4654 * "enable EPT" VM-execution control must also be 1. 4655 */ 4656 static void test_ept_eptp(void) 4657 { 4658 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4659 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4660 u64 eptp_saved = vmcs_read(EPTP); 4661 u32 secondary; 4662 u64 eptp; 4663 u32 i, maxphysaddr; 4664 u64 j, resv_bits_mask = 0; 4665 4666 if (__setup_ept(0xfed40000, false)) { 4667 report_skip("%s : EPT not supported", __func__); 4668 return; 4669 } 4670 4671 test_vmx_valid_controls(); 4672 4673 setup_dummy_ept(); 4674 4675 secondary = vmcs_read(CPU_EXEC_CTRL1); 4676 eptp = vmcs_read(EPTP); 4677 4678 for (i = 0; i < 8; i++) { 4679 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | i; 4680 vmcs_write(EPTP, eptp); 4681 report_prefix_pushf("Enable-EPT enabled; EPT memory type %lu", 4682 eptp & EPT_MEM_TYPE_MASK); 4683 if (is_ept_memtype_supported(i)) 4684 test_vmx_valid_controls(); 4685 else 4686 test_vmx_invalid_controls(); 4687 report_prefix_pop(); 4688 } 4689 4690 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | 6ul; 4691 4692 /* 4693 * Page walk length (bits 5:3). Note, the value in VMCS.EPTP "is 1 4694 * less than the EPT page-walk length". 4695 */ 4696 for (i = 0; i < 8; i++) { 4697 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4698 (i << EPTP_PG_WALK_LEN_SHIFT); 4699 4700 vmcs_write(EPTP, eptp); 4701 report_prefix_pushf("Enable-EPT enabled; EPT page walk length %lu", 4702 eptp & EPTP_PG_WALK_LEN_MASK); 4703 if (i == 3 || (i == 4 && is_5_level_ept_supported())) 4704 test_vmx_valid_controls(); 4705 else 4706 test_vmx_invalid_controls(); 4707 report_prefix_pop(); 4708 } 4709 4710 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4711 3ul << EPTP_PG_WALK_LEN_SHIFT; 4712 4713 /* 4714 * Accessed and dirty flag (bit 6) 4715 */ 4716 if (ept_ad_bits_supported()) { 4717 report_info("Processor supports accessed and dirty flag"); 4718 eptp &= ~EPTP_AD_FLAG; 4719 test_eptp_ad_bit(eptp, true); 4720 4721 eptp |= EPTP_AD_FLAG; 4722 test_eptp_ad_bit(eptp, true); 4723 } else { 4724 report_info("Processor does not supports accessed and dirty flag"); 4725 eptp &= ~EPTP_AD_FLAG; 4726 test_eptp_ad_bit(eptp, true); 4727 4728 eptp |= EPTP_AD_FLAG; 4729 test_eptp_ad_bit(eptp, false); 4730 } 4731 4732 /* 4733 * Reserved bits [11:7] and [63:N] 4734 */ 4735 for (i = 0; i < 32; i++) { 4736 eptp = (eptp & 4737 ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)) | 4738 (i << EPTP_RESERV_BITS_SHIFT); 4739 vmcs_write(EPTP, eptp); 4740 report_prefix_pushf("Enable-EPT enabled; reserved bits [11:7] %lu", 4741 (eptp >> EPTP_RESERV_BITS_SHIFT) & 4742 EPTP_RESERV_BITS_MASK); 4743 if (i == 0) 4744 test_vmx_valid_controls(); 4745 else 4746 test_vmx_invalid_controls(); 4747 report_prefix_pop(); 4748 } 4749 4750 eptp = (eptp & ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)); 4751 4752 maxphysaddr = cpuid_maxphyaddr(); 4753 for (i = 0; i < (63 - maxphysaddr + 1); i++) { 4754 resv_bits_mask |= 1ul << i; 4755 } 4756 4757 for (j = maxphysaddr - 1; j <= 63; j++) { 4758 eptp = (eptp & ~(resv_bits_mask << maxphysaddr)) | 4759 (j < maxphysaddr ? 0 : 1ul << j); 4760 vmcs_write(EPTP, eptp); 4761 report_prefix_pushf("Enable-EPT enabled; reserved bits [63:N] %lu", 4762 (eptp >> maxphysaddr) & resv_bits_mask); 4763 if (j < maxphysaddr) 4764 test_vmx_valid_controls(); 4765 else 4766 test_vmx_invalid_controls(); 4767 report_prefix_pop(); 4768 } 4769 4770 secondary &= ~(CPU_EPT | CPU_URG); 4771 vmcs_write(CPU_EXEC_CTRL1, secondary); 4772 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest disabled"); 4773 test_vmx_valid_controls(); 4774 report_prefix_pop(); 4775 4776 if (!(ctrl_cpu_rev[1].clr & CPU_URG)) 4777 goto skip_unrestricted_guest; 4778 4779 secondary |= CPU_URG; 4780 vmcs_write(CPU_EXEC_CTRL1, secondary); 4781 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest enabled"); 4782 test_vmx_invalid_controls(); 4783 report_prefix_pop(); 4784 4785 secondary |= CPU_EPT; 4786 setup_dummy_ept(); 4787 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest enabled"); 4788 test_vmx_valid_controls(); 4789 report_prefix_pop(); 4790 4791 skip_unrestricted_guest: 4792 secondary &= ~CPU_URG; 4793 vmcs_write(CPU_EXEC_CTRL1, secondary); 4794 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest disabled"); 4795 test_vmx_valid_controls(); 4796 report_prefix_pop(); 4797 4798 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4799 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4800 vmcs_write(EPTP, eptp_saved); 4801 } 4802 4803 /* 4804 * If the 'enable PML' VM-execution control is 1, the 'enable EPT' 4805 * VM-execution control must also be 1. In addition, the PML address 4806 * must satisfy the following checks: 4807 * 4808 * * Bits 11:0 of the address must be 0. 4809 * * The address should not set any bits beyond the processor's 4810 * physical-address width. 4811 * 4812 * [Intel SDM] 4813 */ 4814 static void test_pml(void) 4815 { 4816 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4817 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4818 u32 primary = primary_saved; 4819 u32 secondary = secondary_saved; 4820 4821 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4822 (ctrl_cpu_rev[1].clr & CPU_EPT) && (ctrl_cpu_rev[1].clr & CPU_PML))) { 4823 report_skip("%s : \"Secondary execution\" or \"enable EPT\" or \"enable PML\" control not supported", __func__); 4824 return; 4825 } 4826 4827 primary |= CPU_SECONDARY; 4828 vmcs_write(CPU_EXEC_CTRL0, primary); 4829 secondary &= ~(CPU_PML | CPU_EPT); 4830 vmcs_write(CPU_EXEC_CTRL1, secondary); 4831 report_prefix_pushf("enable-PML disabled, enable-EPT disabled"); 4832 test_vmx_valid_controls(); 4833 report_prefix_pop(); 4834 4835 secondary |= CPU_PML; 4836 vmcs_write(CPU_EXEC_CTRL1, secondary); 4837 report_prefix_pushf("enable-PML enabled, enable-EPT disabled"); 4838 test_vmx_invalid_controls(); 4839 report_prefix_pop(); 4840 4841 secondary |= CPU_EPT; 4842 setup_dummy_ept(); 4843 report_prefix_pushf("enable-PML enabled, enable-EPT enabled"); 4844 test_vmx_valid_controls(); 4845 report_prefix_pop(); 4846 4847 secondary &= ~CPU_PML; 4848 vmcs_write(CPU_EXEC_CTRL1, secondary); 4849 report_prefix_pushf("enable-PML disabled, enable EPT enabled"); 4850 test_vmx_valid_controls(); 4851 report_prefix_pop(); 4852 4853 test_vmcs_addr_reference(CPU_PML, PMLADDR, "PML address", "PML", 4854 PAGE_SIZE, false, false); 4855 4856 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4857 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4858 } 4859 4860 /* 4861 * If the "activate VMX-preemption timer" VM-execution control is 0, the 4862 * the "save VMX-preemption timer value" VM-exit control must also be 0. 4863 * 4864 * [Intel SDM] 4865 */ 4866 static void test_vmx_preemption_timer(void) 4867 { 4868 u32 saved_pin = vmcs_read(PIN_CONTROLS); 4869 u32 saved_exit = vmcs_read(EXI_CONTROLS); 4870 u32 pin = saved_pin; 4871 u32 exit = saved_exit; 4872 4873 if (!((ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) || 4874 (ctrl_pin_rev.clr & PIN_PREEMPT))) { 4875 report_skip("%s : \"Save-VMX-preemption-timer\" and/or \"Enable-VMX-preemption-timer\" control not supported", __func__); 4876 return; 4877 } 4878 4879 pin |= PIN_PREEMPT; 4880 vmcs_write(PIN_CONTROLS, pin); 4881 exit &= ~EXI_SAVE_PREEMPT; 4882 vmcs_write(EXI_CONTROLS, exit); 4883 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer disabled"); 4884 test_vmx_valid_controls(); 4885 report_prefix_pop(); 4886 4887 exit |= EXI_SAVE_PREEMPT; 4888 vmcs_write(EXI_CONTROLS, exit); 4889 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer enabled"); 4890 test_vmx_valid_controls(); 4891 report_prefix_pop(); 4892 4893 pin &= ~PIN_PREEMPT; 4894 vmcs_write(PIN_CONTROLS, pin); 4895 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer enabled"); 4896 test_vmx_invalid_controls(); 4897 report_prefix_pop(); 4898 4899 exit &= ~EXI_SAVE_PREEMPT; 4900 vmcs_write(EXI_CONTROLS, exit); 4901 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer disabled"); 4902 test_vmx_valid_controls(); 4903 report_prefix_pop(); 4904 4905 vmcs_write(PIN_CONTROLS, saved_pin); 4906 vmcs_write(EXI_CONTROLS, saved_exit); 4907 } 4908 4909 extern unsigned char test_mtf1; 4910 extern unsigned char test_mtf2; 4911 extern unsigned char test_mtf3; 4912 extern unsigned char test_mtf4; 4913 4914 static void test_mtf_guest(void) 4915 { 4916 asm ("vmcall;\n\t" 4917 "out %al, $0x80;\n\t" 4918 "test_mtf1:\n\t" 4919 "vmcall;\n\t" 4920 "out %al, $0x80;\n\t" 4921 "test_mtf2:\n\t" 4922 /* 4923 * Prepare for the 'MOV CR3' test. Attempt to induce a 4924 * general-protection fault by moving a non-canonical address into 4925 * CR3. The 'MOV CR3' instruction does not take an imm64 operand, 4926 * so we must MOV the desired value into a register first. 4927 * 4928 * MOV RAX is done before the VMCALL such that MTF is only enabled 4929 * for the instruction under test. 4930 */ 4931 "mov $0xaaaaaaaaaaaaaaaa, %rax;\n\t" 4932 "vmcall;\n\t" 4933 "mov %rax, %cr3;\n\t" 4934 "test_mtf3:\n\t" 4935 "vmcall;\n\t" 4936 /* 4937 * ICEBP/INT1 instruction. Though the instruction is now 4938 * documented, don't rely on assemblers enumerating the 4939 * instruction. Resort to hand assembly. 4940 */ 4941 ".byte 0xf1;\n\t" 4942 "vmcall;\n\t" 4943 "test_mtf4:\n\t" 4944 "mov $0, %eax;\n\t"); 4945 } 4946 4947 static void test_mtf_gp_handler(struct ex_regs *regs) 4948 { 4949 regs->rip = (unsigned long) &test_mtf3; 4950 } 4951 4952 static void test_mtf_db_handler(struct ex_regs *regs) 4953 { 4954 } 4955 4956 static void enable_mtf(void) 4957 { 4958 u32 ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 4959 4960 vmcs_write(CPU_EXEC_CTRL0, ctrl0 | CPU_MTF); 4961 } 4962 4963 static void disable_mtf(void) 4964 { 4965 u32 ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 4966 4967 vmcs_write(CPU_EXEC_CTRL0, ctrl0 & ~CPU_MTF); 4968 } 4969 4970 static void enable_tf(void) 4971 { 4972 unsigned long rflags = vmcs_read(GUEST_RFLAGS); 4973 4974 vmcs_write(GUEST_RFLAGS, rflags | X86_EFLAGS_TF); 4975 } 4976 4977 static void disable_tf(void) 4978 { 4979 unsigned long rflags = vmcs_read(GUEST_RFLAGS); 4980 4981 vmcs_write(GUEST_RFLAGS, rflags & ~X86_EFLAGS_TF); 4982 } 4983 4984 static void report_mtf(const char *insn_name, unsigned long exp_rip) 4985 { 4986 unsigned long rip = vmcs_read(GUEST_RIP); 4987 4988 assert_exit_reason(VMX_MTF); 4989 report(rip == exp_rip, "MTF VM-exit after %s. RIP: 0x%lx (expected 0x%lx)", 4990 insn_name, rip, exp_rip); 4991 } 4992 4993 static void vmx_mtf_test(void) 4994 { 4995 unsigned long pending_dbg; 4996 handler old_gp, old_db; 4997 4998 if (!(ctrl_cpu_rev[0].clr & CPU_MTF)) { 4999 report_skip("%s : \"Monitor trap flag\" exec control not supported", __func__); 5000 return; 5001 } 5002 5003 test_set_guest(test_mtf_guest); 5004 5005 /* Expect an MTF VM-exit after OUT instruction */ 5006 enter_guest(); 5007 skip_exit_vmcall(); 5008 5009 enable_mtf(); 5010 enter_guest(); 5011 report_mtf("OUT", (unsigned long) &test_mtf1); 5012 disable_mtf(); 5013 5014 /* 5015 * Concurrent #DB trap and MTF on instruction boundary. Expect MTF 5016 * VM-exit with populated 'pending debug exceptions' VMCS field. 5017 */ 5018 enter_guest(); 5019 skip_exit_vmcall(); 5020 5021 enable_mtf(); 5022 enable_tf(); 5023 5024 enter_guest(); 5025 report_mtf("OUT", (unsigned long) &test_mtf2); 5026 pending_dbg = vmcs_read(GUEST_PENDING_DEBUG); 5027 report(pending_dbg & DR6_BS, 5028 "'pending debug exceptions' field after MTF VM-exit: 0x%lx (expected 0x%lx)", 5029 pending_dbg, (unsigned long) DR6_BS); 5030 5031 disable_mtf(); 5032 disable_tf(); 5033 vmcs_write(GUEST_PENDING_DEBUG, 0); 5034 5035 /* 5036 * #GP exception takes priority over MTF. Expect MTF VM-exit with RIP 5037 * advanced to first instruction of #GP handler. 5038 */ 5039 enter_guest(); 5040 skip_exit_vmcall(); 5041 5042 old_gp = handle_exception(GP_VECTOR, test_mtf_gp_handler); 5043 5044 enable_mtf(); 5045 enter_guest(); 5046 report_mtf("MOV CR3", (unsigned long) get_idt_addr(&boot_idt[GP_VECTOR])); 5047 disable_mtf(); 5048 5049 /* 5050 * Concurrent MTF and privileged software exception (i.e. ICEBP/INT1). 5051 * MTF should follow the delivery of #DB trap, though the SDM doesn't 5052 * provide clear indication of the relative priority. 5053 */ 5054 enter_guest(); 5055 skip_exit_vmcall(); 5056 5057 handle_exception(GP_VECTOR, old_gp); 5058 old_db = handle_exception(DB_VECTOR, test_mtf_db_handler); 5059 5060 enable_mtf(); 5061 enter_guest(); 5062 report_mtf("INT1", (unsigned long) get_idt_addr(&boot_idt[DB_VECTOR])); 5063 disable_mtf(); 5064 5065 enter_guest(); 5066 skip_exit_vmcall(); 5067 handle_exception(DB_VECTOR, old_db); 5068 vmcs_write(ENT_INTR_INFO, INTR_INFO_VALID_MASK | INTR_TYPE_OTHER_EVENT); 5069 enter_guest(); 5070 report_mtf("injected MTF", (unsigned long) &test_mtf4); 5071 enter_guest(); 5072 } 5073 5074 extern char vmx_mtf_pdpte_guest_begin; 5075 extern char vmx_mtf_pdpte_guest_end; 5076 5077 asm("vmx_mtf_pdpte_guest_begin:\n\t" 5078 "mov %cr0, %rax\n\t" /* save CR0 with PG=1 */ 5079 "vmcall\n\t" /* on return from this CR0.PG=0 */ 5080 "mov %rax, %cr0\n\t" /* restore CR0.PG=1 to enter PAE mode */ 5081 "vmcall\n\t" 5082 "retq\n\t" 5083 "vmx_mtf_pdpte_guest_end:"); 5084 5085 static void vmx_mtf_pdpte_test(void) 5086 { 5087 void *test_mtf_pdpte_guest; 5088 pteval_t *pdpt; 5089 u32 guest_ar_cs; 5090 u64 guest_efer; 5091 pteval_t *pte; 5092 u64 guest_cr0; 5093 u64 guest_cr3; 5094 u64 guest_cr4; 5095 u64 ent_ctls; 5096 int i; 5097 5098 if (setup_ept(false)) 5099 return; 5100 5101 if (!(ctrl_cpu_rev[0].clr & CPU_MTF)) { 5102 report_skip("%s : \"Monitor trap flag\" exec control not supported", __func__); 5103 return; 5104 } 5105 5106 if (!(ctrl_cpu_rev[1].clr & CPU_URG)) { 5107 report_skip("%s : \"Unrestricted guest\" exec control not supported", __func__); 5108 return; 5109 } 5110 5111 vmcs_write(EXC_BITMAP, ~0); 5112 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | CPU_URG); 5113 5114 /* 5115 * Copy the guest code to an identity-mapped page. 5116 */ 5117 test_mtf_pdpte_guest = alloc_page(); 5118 memcpy(test_mtf_pdpte_guest, &vmx_mtf_pdpte_guest_begin, 5119 &vmx_mtf_pdpte_guest_end - &vmx_mtf_pdpte_guest_begin); 5120 5121 test_set_guest(test_mtf_pdpte_guest); 5122 5123 enter_guest(); 5124 skip_exit_vmcall(); 5125 5126 /* 5127 * Put the guest in non-paged 32-bit protected mode, ready to enter 5128 * PAE mode when CR0.PG is set. CR4.PAE will already have been set 5129 * when the guest started out in long mode. 5130 */ 5131 ent_ctls = vmcs_read(ENT_CONTROLS); 5132 vmcs_write(ENT_CONTROLS, ent_ctls & ~ENT_GUEST_64); 5133 5134 guest_efer = vmcs_read(GUEST_EFER); 5135 vmcs_write(GUEST_EFER, guest_efer & ~(EFER_LMA | EFER_LME)); 5136 5137 /* 5138 * Set CS access rights bits for 32-bit protected mode: 5139 * 3:0 B execute/read/accessed 5140 * 4 1 code or data 5141 * 6:5 0 descriptor privilege level 5142 * 7 1 present 5143 * 11:8 0 reserved 5144 * 12 0 available for use by system software 5145 * 13 0 64 bit mode not active 5146 * 14 1 default operation size 32-bit segment 5147 * 15 1 page granularity: segment limit in 4K units 5148 * 16 0 segment usable 5149 * 31:17 0 reserved 5150 */ 5151 guest_ar_cs = vmcs_read(GUEST_AR_CS); 5152 vmcs_write(GUEST_AR_CS, 0xc09b); 5153 5154 guest_cr0 = vmcs_read(GUEST_CR0); 5155 vmcs_write(GUEST_CR0, guest_cr0 & ~X86_CR0_PG); 5156 5157 guest_cr4 = vmcs_read(GUEST_CR4); 5158 vmcs_write(GUEST_CR4, guest_cr4 & ~X86_CR4_PCIDE); 5159 5160 guest_cr3 = vmcs_read(GUEST_CR3); 5161 5162 /* 5163 * Turn the 4-level page table into a PAE page table by following the 0th 5164 * PML4 entry to a PDPT page, and grab the first four PDPTEs from that 5165 * page. 5166 * 5167 * Why does this work? 5168 * 5169 * PAE uses 32-bit addressing which implies: 5170 * Bits 11:0 page offset 5171 * Bits 20:12 entry into 512-entry page table 5172 * Bits 29:21 entry into a 512-entry directory table 5173 * Bits 31:30 entry into the page directory pointer table. 5174 * Bits 63:32 zero 5175 * 5176 * As only 2 bits are needed to select the PDPTEs for the entire 5177 * 32-bit address space, take the first 4 PDPTEs in the level 3 page 5178 * directory pointer table. It doesn't matter which of these PDPTEs 5179 * are present because they must cover the guest code given that it 5180 * has already run successfully. 5181 * 5182 * Get a pointer to PTE for GVA=0 in the page directory pointer table 5183 */ 5184 pte = get_pte_level( 5185 (pgd_t *)phys_to_virt(guest_cr3 & ~X86_CR3_PCID_MASK), 0, 5186 PDPT_LEVEL); 5187 5188 /* 5189 * Need some memory for the 4-entry PAE page directory pointer 5190 * table. Use the end of the identity-mapped page where the guest code 5191 * is stored. There is definitely space as the guest code is only a 5192 * few bytes. 5193 */ 5194 pdpt = test_mtf_pdpte_guest + PAGE_SIZE - 4 * sizeof(pteval_t); 5195 5196 /* 5197 * Copy the first four PDPTEs into the PAE page table with reserved 5198 * bits cleared. Note that permission bits from the PML4E and PDPTE 5199 * are not propagated. 5200 */ 5201 for (i = 0; i < 4; i++) { 5202 TEST_ASSERT_EQ_MSG(0, (pte[i] & PDPTE64_RSVD_MASK), 5203 "PDPTE has invalid reserved bits"); 5204 TEST_ASSERT_EQ_MSG(0, (pte[i] & PDPTE64_PAGE_SIZE_MASK), 5205 "Cannot use 1GB super pages for PAE"); 5206 pdpt[i] = pte[i] & ~(PAE_PDPTE_RSVD_MASK); 5207 } 5208 vmcs_write(GUEST_CR3, virt_to_phys(pdpt)); 5209 5210 enable_mtf(); 5211 enter_guest(); 5212 assert_exit_reason(VMX_MTF); 5213 disable_mtf(); 5214 5215 /* 5216 * The four PDPTEs should have been loaded into the VMCS when 5217 * the guest set CR0.PG to enter PAE mode. 5218 */ 5219 for (i = 0; i < 4; i++) { 5220 u64 pdpte = vmcs_read(GUEST_PDPTE + 2 * i); 5221 5222 report(pdpte == pdpt[i], "PDPTE%d is 0x%lx (expected 0x%lx)", 5223 i, pdpte, pdpt[i]); 5224 } 5225 5226 /* 5227 * Now, try to enter the guest in PAE mode. If the PDPTEs in the 5228 * vmcs are wrong, this will fail. 5229 */ 5230 enter_guest(); 5231 skip_exit_vmcall(); 5232 5233 /* 5234 * Return guest to 64-bit mode and wrap up. 5235 */ 5236 vmcs_write(ENT_CONTROLS, ent_ctls); 5237 vmcs_write(GUEST_EFER, guest_efer); 5238 vmcs_write(GUEST_AR_CS, guest_ar_cs); 5239 vmcs_write(GUEST_CR0, guest_cr0); 5240 vmcs_write(GUEST_CR4, guest_cr4); 5241 vmcs_write(GUEST_CR3, guest_cr3); 5242 5243 enter_guest(); 5244 } 5245 5246 /* 5247 * Tests for VM-execution control fields 5248 */ 5249 static void test_vm_execution_ctls(void) 5250 { 5251 test_pin_based_ctls(); 5252 test_primary_processor_based_ctls(); 5253 test_secondary_processor_based_ctls(); 5254 test_cr3_targets(); 5255 test_io_bitmaps(); 5256 test_msr_bitmap(); 5257 test_apic_ctls(); 5258 test_tpr_threshold(); 5259 test_nmi_ctrls(); 5260 test_pml(); 5261 test_vpid(); 5262 test_ept_eptp(); 5263 test_vmx_preemption_timer(); 5264 } 5265 5266 /* 5267 * The following checks are performed for the VM-entry MSR-load address if 5268 * the VM-entry MSR-load count field is non-zero: 5269 * 5270 * - The lower 4 bits of the VM-entry MSR-load address must be 0. 5271 * The address should not set any bits beyond the processor's 5272 * physical-address width. 5273 * 5274 * - The address of the last byte in the VM-entry MSR-load area 5275 * should not set any bits beyond the processor's physical-address 5276 * width. The address of this last byte is VM-entry MSR-load address 5277 * + (MSR count * 16) - 1. (The arithmetic used for the computation 5278 * uses more bits than the processor's physical-address width.) 5279 * 5280 * 5281 * [Intel SDM] 5282 */ 5283 static void test_entry_msr_load(void) 5284 { 5285 entry_msr_load = alloc_page(); 5286 u64 tmp; 5287 u32 entry_msr_ld_cnt = 1; 5288 int i; 5289 u32 addr_len = 64; 5290 5291 vmcs_write(ENT_MSR_LD_CNT, entry_msr_ld_cnt); 5292 5293 /* Check first 4 bits of VM-entry MSR-load address */ 5294 for (i = 0; i < 4; i++) { 5295 tmp = (u64)entry_msr_load | 1ull << i; 5296 vmcs_write(ENTER_MSR_LD_ADDR, tmp); 5297 report_prefix_pushf("VM-entry MSR-load addr [4:0] %lx", 5298 tmp & 0xf); 5299 test_vmx_invalid_controls(); 5300 report_prefix_pop(); 5301 } 5302 5303 if (basic.val & (1ul << 48)) 5304 addr_len = 32; 5305 5306 test_vmcs_addr_values("VM-entry-MSR-load address", 5307 ENTER_MSR_LD_ADDR, 16, false, false, 5308 4, addr_len - 1); 5309 5310 /* 5311 * Check last byte of VM-entry MSR-load address 5312 */ 5313 entry_msr_load = (struct vmx_msr_entry *)((u64)entry_msr_load & ~0xf); 5314 5315 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 5316 i < 64; i++) { 5317 tmp = ((u64)entry_msr_load + entry_msr_ld_cnt * 16 - 1) | 5318 1ul << i; 5319 vmcs_write(ENTER_MSR_LD_ADDR, 5320 tmp - (entry_msr_ld_cnt * 16 - 1)); 5321 test_vmx_invalid_controls(); 5322 } 5323 5324 vmcs_write(ENT_MSR_LD_CNT, 2); 5325 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 5326 test_vmx_invalid_controls(); 5327 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 5328 test_vmx_valid_controls(); 5329 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 5330 test_vmx_valid_controls(); 5331 } 5332 5333 static struct vmx_state_area_test_data { 5334 u32 msr; 5335 u64 exp; 5336 bool enabled; 5337 } vmx_state_area_test_data; 5338 5339 static void guest_state_test_main(void) 5340 { 5341 u64 obs; 5342 struct vmx_state_area_test_data *data = &vmx_state_area_test_data; 5343 5344 while (1) { 5345 if (vmx_get_test_stage() == 2) 5346 break; 5347 5348 if (data->enabled) { 5349 obs = rdmsr(data->msr); 5350 report(data->exp == obs, 5351 "Guest state is 0x%lx (expected 0x%lx)", 5352 obs, data->exp); 5353 } 5354 5355 vmcall(); 5356 } 5357 5358 asm volatile("fnop"); 5359 } 5360 5361 static void test_guest_state(const char *test, bool xfail, u64 field, 5362 const char * field_name) 5363 { 5364 struct vmentry_result result; 5365 u8 abort_flags; 5366 5367 abort_flags = ABORT_ON_EARLY_VMENTRY_FAIL; 5368 if (!xfail) 5369 abort_flags = ABORT_ON_INVALID_GUEST_STATE; 5370 5371 __enter_guest(abort_flags, &result); 5372 5373 report(result.exit_reason.failed_vmentry == xfail && 5374 ((xfail && result.exit_reason.basic == VMX_FAIL_STATE) || 5375 (!xfail && result.exit_reason.basic == VMX_VMCALL)) && 5376 (!xfail || vmcs_read(EXI_QUALIFICATION) == ENTRY_FAIL_DEFAULT), 5377 "%s, %s = %lx", test, field_name, field); 5378 5379 if (!result.exit_reason.failed_vmentry) 5380 skip_exit_insn(); 5381 } 5382 5383 /* 5384 * Tests for VM-entry control fields 5385 */ 5386 static void test_vm_entry_ctls(void) 5387 { 5388 test_invalid_event_injection(); 5389 test_entry_msr_load(); 5390 } 5391 5392 /* 5393 * The following checks are performed for the VM-exit MSR-store address if 5394 * the VM-exit MSR-store count field is non-zero: 5395 * 5396 * - The lower 4 bits of the VM-exit MSR-store address must be 0. 5397 * The address should not set any bits beyond the processor's 5398 * physical-address width. 5399 * 5400 * - The address of the last byte in the VM-exit MSR-store area 5401 * should not set any bits beyond the processor's physical-address 5402 * width. The address of this last byte is VM-exit MSR-store address 5403 * + (MSR count * 16) - 1. (The arithmetic used for the computation 5404 * uses more bits than the processor's physical-address width.) 5405 * 5406 * If IA32_VMX_BASIC[48] is read as 1, neither address should set any bits 5407 * in the range 63:32. 5408 * 5409 * [Intel SDM] 5410 */ 5411 static void test_exit_msr_store(void) 5412 { 5413 exit_msr_store = alloc_page(); 5414 u64 tmp; 5415 u32 exit_msr_st_cnt = 1; 5416 int i; 5417 u32 addr_len = 64; 5418 5419 vmcs_write(EXI_MSR_ST_CNT, exit_msr_st_cnt); 5420 5421 /* Check first 4 bits of VM-exit MSR-store address */ 5422 for (i = 0; i < 4; i++) { 5423 tmp = (u64)exit_msr_store | 1ull << i; 5424 vmcs_write(EXIT_MSR_ST_ADDR, tmp); 5425 report_prefix_pushf("VM-exit MSR-store addr [4:0] %lx", 5426 tmp & 0xf); 5427 test_vmx_invalid_controls(); 5428 report_prefix_pop(); 5429 } 5430 5431 if (basic.val & (1ul << 48)) 5432 addr_len = 32; 5433 5434 test_vmcs_addr_values("VM-exit-MSR-store address", 5435 EXIT_MSR_ST_ADDR, 16, false, false, 5436 4, addr_len - 1); 5437 5438 /* 5439 * Check last byte of VM-exit MSR-store address 5440 */ 5441 exit_msr_store = (struct vmx_msr_entry *)((u64)exit_msr_store & ~0xf); 5442 5443 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 5444 i < 64; i++) { 5445 tmp = ((u64)exit_msr_store + exit_msr_st_cnt * 16 - 1) | 5446 1ul << i; 5447 vmcs_write(EXIT_MSR_ST_ADDR, 5448 tmp - (exit_msr_st_cnt * 16 - 1)); 5449 test_vmx_invalid_controls(); 5450 } 5451 5452 vmcs_write(EXI_MSR_ST_CNT, 2); 5453 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 5454 test_vmx_invalid_controls(); 5455 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 5456 test_vmx_valid_controls(); 5457 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 5458 test_vmx_valid_controls(); 5459 } 5460 5461 /* 5462 * Tests for VM-exit controls 5463 */ 5464 static void test_vm_exit_ctls(void) 5465 { 5466 test_exit_msr_store(); 5467 } 5468 5469 /* 5470 * Check that the virtual CPU checks all of the VMX controls as 5471 * documented in the Intel SDM. 5472 */ 5473 static void vmx_controls_test(void) 5474 { 5475 /* 5476 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 5477 * fail due to invalid guest state, should we make it that 5478 * far. 5479 */ 5480 vmcs_write(GUEST_RFLAGS, 0); 5481 5482 test_vm_execution_ctls(); 5483 test_vm_exit_ctls(); 5484 test_vm_entry_ctls(); 5485 } 5486 5487 struct apic_reg_virt_config { 5488 bool apic_register_virtualization; 5489 bool use_tpr_shadow; 5490 bool virtualize_apic_accesses; 5491 bool virtualize_x2apic_mode; 5492 bool activate_secondary_controls; 5493 }; 5494 5495 struct apic_reg_test { 5496 const char *name; 5497 struct apic_reg_virt_config apic_reg_virt_config; 5498 }; 5499 5500 struct apic_reg_virt_expectation { 5501 enum Reason rd_exit_reason; 5502 enum Reason wr_exit_reason; 5503 u32 val; 5504 u32 (*virt_fn)(u32); 5505 5506 /* 5507 * If false, accessing the APIC access address from L2 is treated as a 5508 * normal memory operation, rather than triggering virtualization. 5509 */ 5510 bool virtualize_apic_accesses; 5511 }; 5512 5513 static u32 apic_virt_identity(u32 val) 5514 { 5515 return val; 5516 } 5517 5518 static u32 apic_virt_nibble1(u32 val) 5519 { 5520 return val & 0xf0; 5521 } 5522 5523 static u32 apic_virt_byte3(u32 val) 5524 { 5525 return val & (0xff << 24); 5526 } 5527 5528 static bool apic_reg_virt_exit_expectation( 5529 u32 reg, struct apic_reg_virt_config *config, 5530 struct apic_reg_virt_expectation *expectation) 5531 { 5532 /* Good configs, where some L2 APIC accesses are virtualized. */ 5533 bool virtualize_apic_accesses_only = 5534 config->virtualize_apic_accesses && 5535 !config->use_tpr_shadow && 5536 !config->apic_register_virtualization && 5537 !config->virtualize_x2apic_mode && 5538 config->activate_secondary_controls; 5539 bool virtualize_apic_accesses_and_use_tpr_shadow = 5540 config->virtualize_apic_accesses && 5541 config->use_tpr_shadow && 5542 !config->apic_register_virtualization && 5543 !config->virtualize_x2apic_mode && 5544 config->activate_secondary_controls; 5545 bool apic_register_virtualization = 5546 config->virtualize_apic_accesses && 5547 config->use_tpr_shadow && 5548 config->apic_register_virtualization && 5549 !config->virtualize_x2apic_mode && 5550 config->activate_secondary_controls; 5551 5552 expectation->val = MAGIC_VAL_1; 5553 expectation->virt_fn = apic_virt_identity; 5554 expectation->virtualize_apic_accesses = 5555 config->virtualize_apic_accesses && 5556 config->activate_secondary_controls; 5557 if (virtualize_apic_accesses_only) { 5558 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5559 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5560 } else if (virtualize_apic_accesses_and_use_tpr_shadow) { 5561 switch (reg) { 5562 case APIC_TASKPRI: 5563 expectation->rd_exit_reason = VMX_VMCALL; 5564 expectation->wr_exit_reason = VMX_VMCALL; 5565 expectation->virt_fn = apic_virt_nibble1; 5566 break; 5567 default: 5568 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5569 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5570 } 5571 } else if (apic_register_virtualization) { 5572 expectation->rd_exit_reason = VMX_VMCALL; 5573 5574 switch (reg) { 5575 case APIC_ID: 5576 case APIC_EOI: 5577 case APIC_LDR: 5578 case APIC_DFR: 5579 case APIC_SPIV: 5580 case APIC_ESR: 5581 case APIC_ICR: 5582 case APIC_LVTT: 5583 case APIC_LVTTHMR: 5584 case APIC_LVTPC: 5585 case APIC_LVT0: 5586 case APIC_LVT1: 5587 case APIC_LVTERR: 5588 case APIC_TMICT: 5589 case APIC_TDCR: 5590 expectation->wr_exit_reason = VMX_APIC_WRITE; 5591 break; 5592 case APIC_LVR: 5593 case APIC_ISR ... APIC_ISR + 0x70: 5594 case APIC_TMR ... APIC_TMR + 0x70: 5595 case APIC_IRR ... APIC_IRR + 0x70: 5596 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5597 break; 5598 case APIC_TASKPRI: 5599 expectation->wr_exit_reason = VMX_VMCALL; 5600 expectation->virt_fn = apic_virt_nibble1; 5601 break; 5602 case APIC_ICR2: 5603 expectation->wr_exit_reason = VMX_VMCALL; 5604 expectation->virt_fn = apic_virt_byte3; 5605 break; 5606 default: 5607 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5608 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5609 } 5610 } else if (!expectation->virtualize_apic_accesses) { 5611 /* 5612 * No APIC registers are directly virtualized. This includes 5613 * VTPR, which can be virtualized through MOV to/from CR8 via 5614 * the use TPR shadow control, but not through directly 5615 * accessing VTPR. 5616 */ 5617 expectation->rd_exit_reason = VMX_VMCALL; 5618 expectation->wr_exit_reason = VMX_VMCALL; 5619 } else { 5620 printf("Cannot parse APIC register virtualization config:\n" 5621 "\tvirtualize_apic_accesses: %d\n" 5622 "\tuse_tpr_shadow: %d\n" 5623 "\tapic_register_virtualization: %d\n" 5624 "\tvirtualize_x2apic_mode: %d\n" 5625 "\tactivate_secondary_controls: %d\n", 5626 config->virtualize_apic_accesses, 5627 config->use_tpr_shadow, 5628 config->apic_register_virtualization, 5629 config->virtualize_x2apic_mode, 5630 config->activate_secondary_controls); 5631 5632 return false; 5633 } 5634 5635 return true; 5636 } 5637 5638 struct apic_reg_test apic_reg_tests[] = { 5639 /* Good configs, where some L2 APIC accesses are virtualized. */ 5640 { 5641 .name = "Virtualize APIC accesses", 5642 .apic_reg_virt_config = { 5643 .virtualize_apic_accesses = true, 5644 .use_tpr_shadow = false, 5645 .apic_register_virtualization = false, 5646 .virtualize_x2apic_mode = false, 5647 .activate_secondary_controls = true, 5648 }, 5649 }, 5650 { 5651 .name = "Virtualize APIC accesses + Use TPR shadow", 5652 .apic_reg_virt_config = { 5653 .virtualize_apic_accesses = true, 5654 .use_tpr_shadow = true, 5655 .apic_register_virtualization = false, 5656 .virtualize_x2apic_mode = false, 5657 .activate_secondary_controls = true, 5658 }, 5659 }, 5660 { 5661 .name = "APIC-register virtualization", 5662 .apic_reg_virt_config = { 5663 .virtualize_apic_accesses = true, 5664 .use_tpr_shadow = true, 5665 .apic_register_virtualization = true, 5666 .virtualize_x2apic_mode = false, 5667 .activate_secondary_controls = true, 5668 }, 5669 }, 5670 5671 /* 5672 * Test that the secondary processor-based VM-execution controls are 5673 * correctly ignored when "activate secondary controls" is disabled. 5674 */ 5675 { 5676 .name = "Activate secondary controls off", 5677 .apic_reg_virt_config = { 5678 .virtualize_apic_accesses = true, 5679 .use_tpr_shadow = false, 5680 .apic_register_virtualization = true, 5681 .virtualize_x2apic_mode = true, 5682 .activate_secondary_controls = false, 5683 }, 5684 }, 5685 { 5686 .name = "Activate secondary controls off + Use TPR shadow", 5687 .apic_reg_virt_config = { 5688 .virtualize_apic_accesses = true, 5689 .use_tpr_shadow = true, 5690 .apic_register_virtualization = true, 5691 .virtualize_x2apic_mode = true, 5692 .activate_secondary_controls = false, 5693 }, 5694 }, 5695 5696 /* 5697 * Test that the APIC access address is treated like an arbitrary memory 5698 * address when "virtualize APIC accesses" is disabled. 5699 */ 5700 { 5701 .name = "Virtualize APIC accesses off + Use TPR shadow", 5702 .apic_reg_virt_config = { 5703 .virtualize_apic_accesses = false, 5704 .use_tpr_shadow = true, 5705 .apic_register_virtualization = true, 5706 .virtualize_x2apic_mode = true, 5707 .activate_secondary_controls = true, 5708 }, 5709 }, 5710 5711 /* 5712 * Test that VM entry fails due to invalid controls when 5713 * "APIC-register virtualization" is enabled while "use TPR shadow" is 5714 * disabled. 5715 */ 5716 { 5717 .name = "APIC-register virtualization + Use TPR shadow off", 5718 .apic_reg_virt_config = { 5719 .virtualize_apic_accesses = true, 5720 .use_tpr_shadow = false, 5721 .apic_register_virtualization = true, 5722 .virtualize_x2apic_mode = false, 5723 .activate_secondary_controls = true, 5724 }, 5725 }, 5726 5727 /* 5728 * Test that VM entry fails due to invalid controls when 5729 * "Virtualize x2APIC mode" is enabled while "use TPR shadow" is 5730 * disabled. 5731 */ 5732 { 5733 .name = "Virtualize x2APIC mode + Use TPR shadow off", 5734 .apic_reg_virt_config = { 5735 .virtualize_apic_accesses = false, 5736 .use_tpr_shadow = false, 5737 .apic_register_virtualization = false, 5738 .virtualize_x2apic_mode = true, 5739 .activate_secondary_controls = true, 5740 }, 5741 }, 5742 { 5743 .name = "Virtualize x2APIC mode + Use TPR shadow off v2", 5744 .apic_reg_virt_config = { 5745 .virtualize_apic_accesses = false, 5746 .use_tpr_shadow = false, 5747 .apic_register_virtualization = true, 5748 .virtualize_x2apic_mode = true, 5749 .activate_secondary_controls = true, 5750 }, 5751 }, 5752 5753 /* 5754 * Test that VM entry fails due to invalid controls when 5755 * "virtualize x2APIC mode" is enabled while "virtualize APIC accesses" 5756 * is enabled. 5757 */ 5758 { 5759 .name = "Virtualize x2APIC mode + Virtualize APIC accesses", 5760 .apic_reg_virt_config = { 5761 .virtualize_apic_accesses = true, 5762 .use_tpr_shadow = true, 5763 .apic_register_virtualization = false, 5764 .virtualize_x2apic_mode = true, 5765 .activate_secondary_controls = true, 5766 }, 5767 }, 5768 { 5769 .name = "Virtualize x2APIC mode + Virtualize APIC accesses v2", 5770 .apic_reg_virt_config = { 5771 .virtualize_apic_accesses = true, 5772 .use_tpr_shadow = true, 5773 .apic_register_virtualization = true, 5774 .virtualize_x2apic_mode = true, 5775 .activate_secondary_controls = true, 5776 }, 5777 }, 5778 }; 5779 5780 enum Apic_op { 5781 APIC_OP_XAPIC_RD, 5782 APIC_OP_XAPIC_WR, 5783 TERMINATE, 5784 }; 5785 5786 static u32 vmx_xapic_read(u32 *apic_access_address, u32 reg) 5787 { 5788 return *(volatile u32 *)((uintptr_t)apic_access_address + reg); 5789 } 5790 5791 static void vmx_xapic_write(u32 *apic_access_address, u32 reg, u32 val) 5792 { 5793 *(volatile u32 *)((uintptr_t)apic_access_address + reg) = val; 5794 } 5795 5796 struct apic_reg_virt_guest_args { 5797 enum Apic_op op; 5798 u32 *apic_access_address; 5799 u32 reg; 5800 u32 val; 5801 bool check_rd; 5802 u32 (*virt_fn)(u32); 5803 } apic_reg_virt_guest_args; 5804 5805 static void apic_reg_virt_guest(void) 5806 { 5807 volatile struct apic_reg_virt_guest_args *args = 5808 &apic_reg_virt_guest_args; 5809 5810 for (;;) { 5811 enum Apic_op op = args->op; 5812 u32 *apic_access_address = args->apic_access_address; 5813 u32 reg = args->reg; 5814 u32 val = args->val; 5815 bool check_rd = args->check_rd; 5816 u32 (*virt_fn)(u32) = args->virt_fn; 5817 5818 if (op == TERMINATE) 5819 break; 5820 5821 if (op == APIC_OP_XAPIC_RD) { 5822 u32 ret = vmx_xapic_read(apic_access_address, reg); 5823 5824 if (check_rd) { 5825 u32 want = virt_fn(val); 5826 u32 got = virt_fn(ret); 5827 5828 report(got == want, 5829 "read 0x%x, expected 0x%x.", got, want); 5830 } 5831 } else if (op == APIC_OP_XAPIC_WR) { 5832 vmx_xapic_write(apic_access_address, reg, val); 5833 } 5834 5835 /* 5836 * The L1 should always execute a vmcall after it's done testing 5837 * an individual APIC operation. This helps to validate that the 5838 * L1 and L2 are in sync with each other, as expected. 5839 */ 5840 vmcall(); 5841 } 5842 } 5843 5844 static void test_xapic_rd( 5845 u32 reg, struct apic_reg_virt_expectation *expectation, 5846 u32 *apic_access_address, u32 *virtual_apic_page) 5847 { 5848 u32 val = expectation->val; 5849 u32 exit_reason_want = expectation->rd_exit_reason; 5850 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 5851 5852 report_prefix_pushf("xapic - reading 0x%03x", reg); 5853 5854 /* Configure guest to do an xapic read */ 5855 args->op = APIC_OP_XAPIC_RD; 5856 args->apic_access_address = apic_access_address; 5857 args->reg = reg; 5858 args->val = val; 5859 args->check_rd = exit_reason_want == VMX_VMCALL; 5860 args->virt_fn = expectation->virt_fn; 5861 5862 /* Setup virtual APIC page */ 5863 if (!expectation->virtualize_apic_accesses) { 5864 apic_access_address[apic_reg_index(reg)] = val; 5865 virtual_apic_page[apic_reg_index(reg)] = 0; 5866 } else if (exit_reason_want == VMX_VMCALL) { 5867 apic_access_address[apic_reg_index(reg)] = 0; 5868 virtual_apic_page[apic_reg_index(reg)] = val; 5869 } 5870 5871 /* Enter guest */ 5872 enter_guest(); 5873 5874 /* 5875 * Validate the behavior and 5876 * pass a magic value back to the guest. 5877 */ 5878 if (exit_reason_want == VMX_APIC_ACCESS) { 5879 u32 apic_page_offset = vmcs_read(EXI_QUALIFICATION) & 0xfff; 5880 5881 assert_exit_reason(exit_reason_want); 5882 report(apic_page_offset == reg, 5883 "got APIC access exit @ page offset 0x%03x, want 0x%03x", 5884 apic_page_offset, reg); 5885 skip_exit_insn(); 5886 5887 /* Reenter guest so it can consume/check rcx and exit again. */ 5888 enter_guest(); 5889 } else if (exit_reason_want != VMX_VMCALL) { 5890 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 5891 } 5892 5893 skip_exit_vmcall(); 5894 report_prefix_pop(); 5895 } 5896 5897 static void test_xapic_wr( 5898 u32 reg, struct apic_reg_virt_expectation *expectation, 5899 u32 *apic_access_address, u32 *virtual_apic_page) 5900 { 5901 u32 val = expectation->val; 5902 u32 exit_reason_want = expectation->wr_exit_reason; 5903 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 5904 bool virtualized = 5905 expectation->virtualize_apic_accesses && 5906 (exit_reason_want == VMX_APIC_WRITE || 5907 exit_reason_want == VMX_VMCALL); 5908 bool checked = false; 5909 5910 report_prefix_pushf("xapic - writing 0x%x to 0x%03x", val, reg); 5911 5912 /* Configure guest to do an xapic read */ 5913 args->op = APIC_OP_XAPIC_WR; 5914 args->apic_access_address = apic_access_address; 5915 args->reg = reg; 5916 args->val = val; 5917 5918 /* Setup virtual APIC page */ 5919 if (virtualized || !expectation->virtualize_apic_accesses) { 5920 apic_access_address[apic_reg_index(reg)] = 0; 5921 virtual_apic_page[apic_reg_index(reg)] = 0; 5922 } 5923 5924 /* Enter guest */ 5925 enter_guest(); 5926 5927 /* 5928 * Validate the behavior and 5929 * pass a magic value back to the guest. 5930 */ 5931 if (exit_reason_want == VMX_APIC_ACCESS) { 5932 u32 apic_page_offset = vmcs_read(EXI_QUALIFICATION) & 0xfff; 5933 5934 assert_exit_reason(exit_reason_want); 5935 report(apic_page_offset == reg, 5936 "got APIC access exit @ page offset 0x%03x, want 0x%03x", 5937 apic_page_offset, reg); 5938 skip_exit_insn(); 5939 5940 /* Reenter guest so it can consume/check rcx and exit again. */ 5941 enter_guest(); 5942 } else if (exit_reason_want == VMX_APIC_WRITE) { 5943 assert_exit_reason(exit_reason_want); 5944 report(virtual_apic_page[apic_reg_index(reg)] == val, 5945 "got APIC write exit @ page offset 0x%03x; val is 0x%x, want 0x%x", 5946 apic_reg_index(reg), 5947 virtual_apic_page[apic_reg_index(reg)], val); 5948 checked = true; 5949 5950 /* Reenter guest so it can consume/check rcx and exit again. */ 5951 enter_guest(); 5952 } else if (exit_reason_want != VMX_VMCALL) { 5953 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 5954 } 5955 5956 assert_exit_reason(VMX_VMCALL); 5957 if (virtualized && !checked) { 5958 u32 want = expectation->virt_fn(val); 5959 u32 got = virtual_apic_page[apic_reg_index(reg)]; 5960 got = expectation->virt_fn(got); 5961 5962 report(got == want, "exitless write; val is 0x%x, want 0x%x", 5963 got, want); 5964 } else if (!expectation->virtualize_apic_accesses && !checked) { 5965 u32 got = apic_access_address[apic_reg_index(reg)]; 5966 5967 report(got == val, 5968 "non-virtualized write; val is 0x%x, want 0x%x", got, 5969 val); 5970 } else if (!expectation->virtualize_apic_accesses && checked) { 5971 report_fail("Non-virtualized write was prematurely checked!"); 5972 } 5973 5974 skip_exit_vmcall(); 5975 report_prefix_pop(); 5976 } 5977 5978 enum Config_type { 5979 CONFIG_TYPE_GOOD, 5980 CONFIG_TYPE_UNSUPPORTED, 5981 CONFIG_TYPE_VMENTRY_FAILS_EARLY, 5982 }; 5983 5984 static enum Config_type configure_apic_reg_virt_test( 5985 struct apic_reg_virt_config *apic_reg_virt_config) 5986 { 5987 u32 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 5988 u32 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 5989 /* Configs where L2 entry fails early, due to invalid controls. */ 5990 bool use_tpr_shadow_incorrectly_off = 5991 !apic_reg_virt_config->use_tpr_shadow && 5992 (apic_reg_virt_config->apic_register_virtualization || 5993 apic_reg_virt_config->virtualize_x2apic_mode) && 5994 apic_reg_virt_config->activate_secondary_controls; 5995 bool virtualize_apic_accesses_incorrectly_on = 5996 apic_reg_virt_config->virtualize_apic_accesses && 5997 apic_reg_virt_config->virtualize_x2apic_mode && 5998 apic_reg_virt_config->activate_secondary_controls; 5999 bool vmentry_fails_early = 6000 use_tpr_shadow_incorrectly_off || 6001 virtualize_apic_accesses_incorrectly_on; 6002 6003 if (apic_reg_virt_config->activate_secondary_controls) { 6004 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 6005 printf("VM-execution control \"activate secondary controls\" NOT supported.\n"); 6006 return CONFIG_TYPE_UNSUPPORTED; 6007 } 6008 cpu_exec_ctrl0 |= CPU_SECONDARY; 6009 } else { 6010 cpu_exec_ctrl0 &= ~CPU_SECONDARY; 6011 } 6012 6013 if (apic_reg_virt_config->virtualize_apic_accesses) { 6014 if (!(ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES)) { 6015 printf("VM-execution control \"virtualize APIC accesses\" NOT supported.\n"); 6016 return CONFIG_TYPE_UNSUPPORTED; 6017 } 6018 cpu_exec_ctrl1 |= CPU_VIRT_APIC_ACCESSES; 6019 } else { 6020 cpu_exec_ctrl1 &= ~CPU_VIRT_APIC_ACCESSES; 6021 } 6022 6023 if (apic_reg_virt_config->use_tpr_shadow) { 6024 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) { 6025 printf("VM-execution control \"use TPR shadow\" NOT supported.\n"); 6026 return CONFIG_TYPE_UNSUPPORTED; 6027 } 6028 cpu_exec_ctrl0 |= CPU_TPR_SHADOW; 6029 } else { 6030 cpu_exec_ctrl0 &= ~CPU_TPR_SHADOW; 6031 } 6032 6033 if (apic_reg_virt_config->apic_register_virtualization) { 6034 if (!(ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT)) { 6035 printf("VM-execution control \"APIC-register virtualization\" NOT supported.\n"); 6036 return CONFIG_TYPE_UNSUPPORTED; 6037 } 6038 cpu_exec_ctrl1 |= CPU_APIC_REG_VIRT; 6039 } else { 6040 cpu_exec_ctrl1 &= ~CPU_APIC_REG_VIRT; 6041 } 6042 6043 if (apic_reg_virt_config->virtualize_x2apic_mode) { 6044 if (!(ctrl_cpu_rev[1].clr & CPU_VIRT_X2APIC)) { 6045 printf("VM-execution control \"virtualize x2APIC mode\" NOT supported.\n"); 6046 return CONFIG_TYPE_UNSUPPORTED; 6047 } 6048 cpu_exec_ctrl1 |= CPU_VIRT_X2APIC; 6049 } else { 6050 cpu_exec_ctrl1 &= ~CPU_VIRT_X2APIC; 6051 } 6052 6053 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6054 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6055 6056 if (vmentry_fails_early) 6057 return CONFIG_TYPE_VMENTRY_FAILS_EARLY; 6058 6059 return CONFIG_TYPE_GOOD; 6060 } 6061 6062 static bool cpu_has_apicv(void) 6063 { 6064 return ((ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT) && 6065 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 6066 (ctrl_pin_rev.clr & PIN_POST_INTR)); 6067 } 6068 6069 /* Validates APIC register access across valid virtualization configurations. */ 6070 static void apic_reg_virt_test(void) 6071 { 6072 u32 *apic_access_address; 6073 u32 *virtual_apic_page; 6074 u64 control; 6075 u64 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6076 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6077 int i; 6078 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 6079 6080 if (!cpu_has_apicv()) { 6081 report_skip("%s : Not all required APICv bits supported", __func__); 6082 return; 6083 } 6084 6085 control = cpu_exec_ctrl1; 6086 control &= ~CPU_VINTD; 6087 vmcs_write(CPU_EXEC_CTRL1, control); 6088 6089 test_set_guest(apic_reg_virt_guest); 6090 6091 /* 6092 * From the SDM: The 1-setting of the "virtualize APIC accesses" 6093 * VM-execution is guaranteed to apply only if translations to the 6094 * APIC-access address use a 4-KByte page. 6095 */ 6096 apic_access_address = alloc_page(); 6097 force_4k_page(apic_access_address); 6098 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_address)); 6099 6100 virtual_apic_page = alloc_page(); 6101 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 6102 6103 for (i = 0; i < ARRAY_SIZE(apic_reg_tests); i++) { 6104 struct apic_reg_test *apic_reg_test = &apic_reg_tests[i]; 6105 struct apic_reg_virt_config *apic_reg_virt_config = 6106 &apic_reg_test->apic_reg_virt_config; 6107 enum Config_type config_type; 6108 u32 reg; 6109 6110 printf("--- %s test ---\n", apic_reg_test->name); 6111 config_type = 6112 configure_apic_reg_virt_test(apic_reg_virt_config); 6113 if (config_type == CONFIG_TYPE_UNSUPPORTED) { 6114 printf("Skip because of missing features.\n"); 6115 continue; 6116 } 6117 6118 if (config_type == CONFIG_TYPE_VMENTRY_FAILS_EARLY) { 6119 enter_guest_with_bad_controls(); 6120 continue; 6121 } 6122 6123 for (reg = 0; reg < PAGE_SIZE / sizeof(u32); reg += 0x10) { 6124 struct apic_reg_virt_expectation expectation = {}; 6125 bool ok; 6126 6127 ok = apic_reg_virt_exit_expectation( 6128 reg, apic_reg_virt_config, &expectation); 6129 if (!ok) { 6130 report_fail("Malformed test."); 6131 break; 6132 } 6133 6134 test_xapic_rd(reg, &expectation, apic_access_address, 6135 virtual_apic_page); 6136 test_xapic_wr(reg, &expectation, apic_access_address, 6137 virtual_apic_page); 6138 } 6139 } 6140 6141 /* Terminate the guest */ 6142 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6143 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6144 args->op = TERMINATE; 6145 enter_guest(); 6146 assert_exit_reason(VMX_VMCALL); 6147 } 6148 6149 struct virt_x2apic_mode_config { 6150 struct apic_reg_virt_config apic_reg_virt_config; 6151 bool virtual_interrupt_delivery; 6152 bool use_msr_bitmaps; 6153 bool disable_x2apic_msr_intercepts; 6154 bool disable_x2apic; 6155 }; 6156 6157 struct virt_x2apic_mode_test_case { 6158 const char *name; 6159 struct virt_x2apic_mode_config virt_x2apic_mode_config; 6160 }; 6161 6162 enum Virt_x2apic_mode_behavior_type { 6163 X2APIC_ACCESS_VIRTUALIZED, 6164 X2APIC_ACCESS_PASSED_THROUGH, 6165 X2APIC_ACCESS_TRIGGERS_GP, 6166 }; 6167 6168 struct virt_x2apic_mode_expectation { 6169 enum Reason rd_exit_reason; 6170 enum Reason wr_exit_reason; 6171 6172 /* 6173 * RDMSR and WRMSR handle 64-bit values. However, except for ICR, all of 6174 * the x2APIC registers are 32 bits. Notice: 6175 * 1. vmx_x2apic_read() clears the upper 32 bits for 32-bit registers. 6176 * 2. vmx_x2apic_write() expects the val arg to be well-formed. 6177 */ 6178 u64 rd_val; 6179 u64 wr_val; 6180 6181 /* 6182 * Compares input to virtualized output; 6183 * 1st arg is pointer to return expected virtualization output. 6184 */ 6185 u64 (*virt_fn)(u64); 6186 6187 enum Virt_x2apic_mode_behavior_type rd_behavior; 6188 enum Virt_x2apic_mode_behavior_type wr_behavior; 6189 bool wr_only; 6190 }; 6191 6192 static u64 virt_x2apic_mode_identity(u64 val) 6193 { 6194 return val; 6195 } 6196 6197 static u64 virt_x2apic_mode_nibble1(u64 val) 6198 { 6199 return val & 0xf0; 6200 } 6201 6202 static void virt_x2apic_mode_rd_expectation( 6203 u32 reg, bool virt_x2apic_mode_on, bool disable_x2apic, 6204 bool apic_register_virtualization, bool virtual_interrupt_delivery, 6205 struct virt_x2apic_mode_expectation *expectation) 6206 { 6207 enum x2apic_reg_semantics semantics = get_x2apic_reg_semantics(reg); 6208 6209 expectation->rd_exit_reason = VMX_VMCALL; 6210 expectation->virt_fn = virt_x2apic_mode_identity; 6211 if (virt_x2apic_mode_on && apic_register_virtualization) { 6212 expectation->rd_val = MAGIC_VAL_1; 6213 if (reg == APIC_PROCPRI && virtual_interrupt_delivery) 6214 expectation->virt_fn = virt_x2apic_mode_nibble1; 6215 else if (reg == APIC_TASKPRI) 6216 expectation->virt_fn = virt_x2apic_mode_nibble1; 6217 expectation->rd_behavior = X2APIC_ACCESS_VIRTUALIZED; 6218 } else if (virt_x2apic_mode_on && !apic_register_virtualization && 6219 reg == APIC_TASKPRI) { 6220 expectation->rd_val = MAGIC_VAL_1; 6221 expectation->virt_fn = virt_x2apic_mode_nibble1; 6222 expectation->rd_behavior = X2APIC_ACCESS_VIRTUALIZED; 6223 } else if (!disable_x2apic && (semantics & X2APIC_READABLE)) { 6224 expectation->rd_val = apic_read(reg); 6225 expectation->rd_behavior = X2APIC_ACCESS_PASSED_THROUGH; 6226 } else { 6227 expectation->rd_behavior = X2APIC_ACCESS_TRIGGERS_GP; 6228 } 6229 } 6230 6231 /* 6232 * get_x2apic_wr_val() creates an innocuous write value for an x2APIC register. 6233 * 6234 * For writable registers, get_x2apic_wr_val() deposits the write value into the 6235 * val pointer arg and returns true. For non-writable registers, val is not 6236 * modified and get_x2apic_wr_val() returns false. 6237 */ 6238 static bool get_x2apic_wr_val(u32 reg, u64 *val) 6239 { 6240 switch (reg) { 6241 case APIC_TASKPRI: 6242 /* Bits 31:8 are reserved. */ 6243 *val &= 0xff; 6244 break; 6245 case APIC_EOI: 6246 case APIC_ESR: 6247 case APIC_TMICT: 6248 /* 6249 * EOI, ESR: WRMSR of a non-zero value causes #GP(0). 6250 * TMICT: A write of 0 to the initial-count register effectively 6251 * stops the local APIC timer, in both one-shot and 6252 * periodic mode. 6253 */ 6254 *val = 0; 6255 break; 6256 case APIC_SPIV: 6257 case APIC_LVTT: 6258 case APIC_LVTTHMR: 6259 case APIC_LVTPC: 6260 case APIC_LVT0: 6261 case APIC_LVT1: 6262 case APIC_LVTERR: 6263 case APIC_TDCR: 6264 /* 6265 * To avoid writing a 1 to a reserved bit or causing some other 6266 * unintended side effect, read the current value and use it as 6267 * the write value. 6268 */ 6269 *val = apic_read(reg); 6270 break; 6271 case APIC_CMCI: 6272 if (!apic_lvt_entry_supported(6)) 6273 return false; 6274 *val = apic_read(reg); 6275 break; 6276 case APIC_ICR: 6277 *val = 0x40000 | 0xf1; 6278 break; 6279 case APIC_SELF_IPI: 6280 /* 6281 * With special processing (i.e., virtualize x2APIC mode + 6282 * virtual interrupt delivery), writing zero causes an 6283 * APIC-write VM exit. We plan to add a test for enabling 6284 * "virtual-interrupt delivery" in VMCS12, and that's where we 6285 * will test a self IPI with special processing. 6286 */ 6287 *val = 0x0; 6288 break; 6289 default: 6290 return false; 6291 } 6292 6293 return true; 6294 } 6295 6296 static bool special_processing_applies(u32 reg, u64 *val, 6297 bool virt_int_delivery) 6298 { 6299 bool special_processing = 6300 (reg == APIC_TASKPRI) || 6301 (virt_int_delivery && 6302 (reg == APIC_EOI || reg == APIC_SELF_IPI)); 6303 6304 if (special_processing) { 6305 TEST_ASSERT(get_x2apic_wr_val(reg, val)); 6306 return true; 6307 } 6308 6309 return false; 6310 } 6311 6312 static void virt_x2apic_mode_wr_expectation( 6313 u32 reg, bool virt_x2apic_mode_on, bool disable_x2apic, 6314 bool virt_int_delivery, 6315 struct virt_x2apic_mode_expectation *expectation) 6316 { 6317 expectation->wr_exit_reason = VMX_VMCALL; 6318 expectation->wr_val = MAGIC_VAL_1; 6319 expectation->wr_only = false; 6320 6321 if (virt_x2apic_mode_on && 6322 special_processing_applies(reg, &expectation->wr_val, 6323 virt_int_delivery)) { 6324 expectation->wr_behavior = X2APIC_ACCESS_VIRTUALIZED; 6325 if (reg == APIC_SELF_IPI) 6326 expectation->wr_exit_reason = VMX_APIC_WRITE; 6327 } else if (!disable_x2apic && 6328 get_x2apic_wr_val(reg, &expectation->wr_val)) { 6329 expectation->wr_behavior = X2APIC_ACCESS_PASSED_THROUGH; 6330 if (reg == APIC_EOI || reg == APIC_SELF_IPI) 6331 expectation->wr_only = true; 6332 if (reg == APIC_ICR) 6333 expectation->wr_exit_reason = VMX_EXTINT; 6334 } else { 6335 expectation->wr_behavior = X2APIC_ACCESS_TRIGGERS_GP; 6336 /* 6337 * Writing 1 to a reserved bit triggers a #GP. 6338 * Thus, set the write value to 0, which seems 6339 * the most likely to detect a missed #GP. 6340 */ 6341 expectation->wr_val = 0; 6342 } 6343 } 6344 6345 static void virt_x2apic_mode_exit_expectation( 6346 u32 reg, struct virt_x2apic_mode_config *config, 6347 struct virt_x2apic_mode_expectation *expectation) 6348 { 6349 struct apic_reg_virt_config *base_config = 6350 &config->apic_reg_virt_config; 6351 bool virt_x2apic_mode_on = 6352 base_config->virtualize_x2apic_mode && 6353 config->use_msr_bitmaps && 6354 config->disable_x2apic_msr_intercepts && 6355 base_config->activate_secondary_controls; 6356 6357 virt_x2apic_mode_wr_expectation( 6358 reg, virt_x2apic_mode_on, config->disable_x2apic, 6359 config->virtual_interrupt_delivery, expectation); 6360 virt_x2apic_mode_rd_expectation( 6361 reg, virt_x2apic_mode_on, config->disable_x2apic, 6362 base_config->apic_register_virtualization, 6363 config->virtual_interrupt_delivery, expectation); 6364 } 6365 6366 struct virt_x2apic_mode_test_case virt_x2apic_mode_tests[] = { 6367 /* 6368 * Baseline "virtualize x2APIC mode" configuration: 6369 * - virtualize x2APIC mode 6370 * - virtual-interrupt delivery 6371 * - APIC-register virtualization 6372 * - x2APIC MSR intercepts disabled 6373 * 6374 * Reads come from virtual APIC page, special processing applies to 6375 * VTPR, EOI, and SELF IPI, and all other writes pass through to L1 6376 * APIC. 6377 */ 6378 { 6379 .name = "Baseline", 6380 .virt_x2apic_mode_config = { 6381 .virtual_interrupt_delivery = true, 6382 .use_msr_bitmaps = true, 6383 .disable_x2apic_msr_intercepts = true, 6384 .disable_x2apic = false, 6385 .apic_reg_virt_config = { 6386 .apic_register_virtualization = true, 6387 .use_tpr_shadow = true, 6388 .virtualize_apic_accesses = false, 6389 .virtualize_x2apic_mode = true, 6390 .activate_secondary_controls = true, 6391 }, 6392 }, 6393 }, 6394 { 6395 .name = "Baseline w/ x2apic disabled", 6396 .virt_x2apic_mode_config = { 6397 .virtual_interrupt_delivery = true, 6398 .use_msr_bitmaps = true, 6399 .disable_x2apic_msr_intercepts = true, 6400 .disable_x2apic = true, 6401 .apic_reg_virt_config = { 6402 .apic_register_virtualization = true, 6403 .use_tpr_shadow = true, 6404 .virtualize_apic_accesses = false, 6405 .virtualize_x2apic_mode = true, 6406 .activate_secondary_controls = true, 6407 }, 6408 }, 6409 }, 6410 6411 /* 6412 * Baseline, minus virtual-interrupt delivery. Reads come from virtual 6413 * APIC page, special processing applies to VTPR, and all other writes 6414 * pass through to L1 APIC. 6415 */ 6416 { 6417 .name = "Baseline - virtual interrupt delivery", 6418 .virt_x2apic_mode_config = { 6419 .virtual_interrupt_delivery = false, 6420 .use_msr_bitmaps = true, 6421 .disable_x2apic_msr_intercepts = true, 6422 .disable_x2apic = false, 6423 .apic_reg_virt_config = { 6424 .apic_register_virtualization = true, 6425 .use_tpr_shadow = true, 6426 .virtualize_apic_accesses = false, 6427 .virtualize_x2apic_mode = true, 6428 .activate_secondary_controls = true, 6429 }, 6430 }, 6431 }, 6432 6433 /* 6434 * Baseline, minus APIC-register virtualization. x2APIC reads pass 6435 * through to L1's APIC, unless reading VTPR 6436 */ 6437 { 6438 .name = "Virtualize x2APIC mode, no APIC reg virt", 6439 .virt_x2apic_mode_config = { 6440 .virtual_interrupt_delivery = true, 6441 .use_msr_bitmaps = true, 6442 .disable_x2apic_msr_intercepts = true, 6443 .disable_x2apic = false, 6444 .apic_reg_virt_config = { 6445 .apic_register_virtualization = false, 6446 .use_tpr_shadow = true, 6447 .virtualize_apic_accesses = false, 6448 .virtualize_x2apic_mode = true, 6449 .activate_secondary_controls = true, 6450 }, 6451 }, 6452 }, 6453 { 6454 .name = "Virtualize x2APIC mode, no APIC reg virt, x2APIC off", 6455 .virt_x2apic_mode_config = { 6456 .virtual_interrupt_delivery = true, 6457 .use_msr_bitmaps = true, 6458 .disable_x2apic_msr_intercepts = true, 6459 .disable_x2apic = true, 6460 .apic_reg_virt_config = { 6461 .apic_register_virtualization = false, 6462 .use_tpr_shadow = true, 6463 .virtualize_apic_accesses = false, 6464 .virtualize_x2apic_mode = true, 6465 .activate_secondary_controls = true, 6466 }, 6467 }, 6468 }, 6469 6470 /* 6471 * Enable "virtualize x2APIC mode" and "APIC-register virtualization", 6472 * and disable intercepts for the x2APIC MSRs, but fail to enable 6473 * "activate secondary controls" (i.e. L2 gets access to L1's x2APIC 6474 * MSRs). 6475 */ 6476 { 6477 .name = "Fail to enable activate secondary controls", 6478 .virt_x2apic_mode_config = { 6479 .virtual_interrupt_delivery = true, 6480 .use_msr_bitmaps = true, 6481 .disable_x2apic_msr_intercepts = true, 6482 .disable_x2apic = false, 6483 .apic_reg_virt_config = { 6484 .apic_register_virtualization = true, 6485 .use_tpr_shadow = true, 6486 .virtualize_apic_accesses = false, 6487 .virtualize_x2apic_mode = true, 6488 .activate_secondary_controls = false, 6489 }, 6490 }, 6491 }, 6492 6493 /* 6494 * Enable "APIC-register virtualization" and enable "activate secondary 6495 * controls" and disable intercepts for the x2APIC MSRs, but do not 6496 * enable the "virtualize x2APIC mode" VM-execution control (i.e. L2 6497 * gets access to L1's x2APIC MSRs). 6498 */ 6499 { 6500 .name = "Fail to enable virtualize x2APIC mode", 6501 .virt_x2apic_mode_config = { 6502 .virtual_interrupt_delivery = true, 6503 .use_msr_bitmaps = true, 6504 .disable_x2apic_msr_intercepts = true, 6505 .disable_x2apic = false, 6506 .apic_reg_virt_config = { 6507 .apic_register_virtualization = true, 6508 .use_tpr_shadow = true, 6509 .virtualize_apic_accesses = false, 6510 .virtualize_x2apic_mode = false, 6511 .activate_secondary_controls = true, 6512 }, 6513 }, 6514 }, 6515 6516 /* 6517 * Disable "Virtualize x2APIC mode", disable x2APIC MSR intercepts, and 6518 * enable "APIC-register virtualization" --> L2 gets L1's x2APIC MSRs. 6519 */ 6520 { 6521 .name = "Baseline", 6522 .virt_x2apic_mode_config = { 6523 .virtual_interrupt_delivery = true, 6524 .use_msr_bitmaps = true, 6525 .disable_x2apic_msr_intercepts = true, 6526 .disable_x2apic = false, 6527 .apic_reg_virt_config = { 6528 .apic_register_virtualization = true, 6529 .use_tpr_shadow = true, 6530 .virtualize_apic_accesses = false, 6531 .virtualize_x2apic_mode = false, 6532 .activate_secondary_controls = true, 6533 }, 6534 }, 6535 }, 6536 }; 6537 6538 enum X2apic_op { 6539 X2APIC_OP_RD, 6540 X2APIC_OP_WR, 6541 X2APIC_TERMINATE, 6542 }; 6543 6544 static u64 vmx_x2apic_read(u32 reg) 6545 { 6546 u32 msr_addr = x2apic_msr(reg); 6547 u64 val; 6548 6549 val = rdmsr(msr_addr); 6550 6551 return val; 6552 } 6553 6554 static void vmx_x2apic_write(u32 reg, u64 val) 6555 { 6556 u32 msr_addr = x2apic_msr(reg); 6557 6558 wrmsr(msr_addr, val); 6559 } 6560 6561 struct virt_x2apic_mode_guest_args { 6562 enum X2apic_op op; 6563 u32 reg; 6564 u64 val; 6565 bool should_gp; 6566 u64 (*virt_fn)(u64); 6567 } virt_x2apic_mode_guest_args; 6568 6569 static volatile bool handle_x2apic_gp_ran; 6570 static volatile u32 handle_x2apic_gp_insn_len; 6571 static void handle_x2apic_gp(struct ex_regs *regs) 6572 { 6573 handle_x2apic_gp_ran = true; 6574 regs->rip += handle_x2apic_gp_insn_len; 6575 } 6576 6577 static handler setup_x2apic_gp_handler(void) 6578 { 6579 handler old_handler; 6580 6581 old_handler = handle_exception(GP_VECTOR, handle_x2apic_gp); 6582 /* RDMSR and WRMSR are both 2 bytes, assuming no prefixes. */ 6583 handle_x2apic_gp_insn_len = 2; 6584 6585 return old_handler; 6586 } 6587 6588 static void teardown_x2apic_gp_handler(handler old_handler) 6589 { 6590 handle_exception(GP_VECTOR, old_handler); 6591 6592 /* 6593 * Defensively reset instruction length, so that if the handler is 6594 * incorrectly used, it will loop infinitely, rather than run off into 6595 * la la land. 6596 */ 6597 handle_x2apic_gp_insn_len = 0; 6598 handle_x2apic_gp_ran = false; 6599 } 6600 6601 static void virt_x2apic_mode_guest(void) 6602 { 6603 volatile struct virt_x2apic_mode_guest_args *args = 6604 &virt_x2apic_mode_guest_args; 6605 6606 for (;;) { 6607 enum X2apic_op op = args->op; 6608 u32 reg = args->reg; 6609 u64 val = args->val; 6610 bool should_gp = args->should_gp; 6611 u64 (*virt_fn)(u64) = args->virt_fn; 6612 handler old_handler; 6613 6614 if (op == X2APIC_TERMINATE) 6615 break; 6616 6617 if (should_gp) { 6618 TEST_ASSERT(!handle_x2apic_gp_ran); 6619 old_handler = setup_x2apic_gp_handler(); 6620 } 6621 6622 if (op == X2APIC_OP_RD) { 6623 u64 ret = vmx_x2apic_read(reg); 6624 6625 if (!should_gp) { 6626 u64 want = virt_fn(val); 6627 u64 got = virt_fn(ret); 6628 6629 report(got == want, 6630 "APIC read; got 0x%lx, want 0x%lx.", 6631 got, want); 6632 } 6633 } else if (op == X2APIC_OP_WR) { 6634 vmx_x2apic_write(reg, val); 6635 } 6636 6637 if (should_gp) { 6638 report(handle_x2apic_gp_ran, 6639 "x2APIC op triggered GP."); 6640 teardown_x2apic_gp_handler(old_handler); 6641 } 6642 6643 /* 6644 * The L1 should always execute a vmcall after it's done testing 6645 * an individual APIC operation. This helps to validate that the 6646 * L1 and L2 are in sync with each other, as expected. 6647 */ 6648 vmcall(); 6649 } 6650 } 6651 6652 static void test_x2apic_rd( 6653 u32 reg, struct virt_x2apic_mode_expectation *expectation, 6654 u32 *virtual_apic_page) 6655 { 6656 u64 val = expectation->rd_val; 6657 u32 exit_reason_want = expectation->rd_exit_reason; 6658 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6659 6660 report_prefix_pushf("x2apic - reading 0x%03x", reg); 6661 6662 /* Configure guest to do an x2apic read */ 6663 args->op = X2APIC_OP_RD; 6664 args->reg = reg; 6665 args->val = val; 6666 args->should_gp = expectation->rd_behavior == X2APIC_ACCESS_TRIGGERS_GP; 6667 args->virt_fn = expectation->virt_fn; 6668 6669 /* Setup virtual APIC page */ 6670 if (expectation->rd_behavior == X2APIC_ACCESS_VIRTUALIZED) 6671 virtual_apic_page[apic_reg_index(reg)] = (u32)val; 6672 6673 /* Enter guest */ 6674 enter_guest(); 6675 6676 if (exit_reason_want != VMX_VMCALL) { 6677 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 6678 } 6679 6680 skip_exit_vmcall(); 6681 report_prefix_pop(); 6682 } 6683 6684 static volatile bool handle_x2apic_ipi_ran; 6685 static void handle_x2apic_ipi(isr_regs_t *regs) 6686 { 6687 handle_x2apic_ipi_ran = true; 6688 eoi(); 6689 } 6690 6691 static void test_x2apic_wr( 6692 u32 reg, struct virt_x2apic_mode_expectation *expectation, 6693 u32 *virtual_apic_page) 6694 { 6695 u64 val = expectation->wr_val; 6696 u32 exit_reason_want = expectation->wr_exit_reason; 6697 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6698 int ipi_vector = 0xf1; 6699 u32 restore_val = 0; 6700 6701 report_prefix_pushf("x2apic - writing 0x%lx to 0x%03x", val, reg); 6702 6703 /* Configure guest to do an x2apic read */ 6704 args->op = X2APIC_OP_WR; 6705 args->reg = reg; 6706 args->val = val; 6707 args->should_gp = expectation->wr_behavior == X2APIC_ACCESS_TRIGGERS_GP; 6708 6709 /* Setup virtual APIC page */ 6710 if (expectation->wr_behavior == X2APIC_ACCESS_VIRTUALIZED) 6711 virtual_apic_page[apic_reg_index(reg)] = 0; 6712 if (expectation->wr_behavior == X2APIC_ACCESS_PASSED_THROUGH && !expectation->wr_only) 6713 restore_val = apic_read(reg); 6714 6715 /* Setup IPI handler */ 6716 handle_x2apic_ipi_ran = false; 6717 handle_irq(ipi_vector, handle_x2apic_ipi); 6718 6719 /* Enter guest */ 6720 enter_guest(); 6721 6722 /* 6723 * Validate the behavior and 6724 * pass a magic value back to the guest. 6725 */ 6726 if (exit_reason_want == VMX_EXTINT) { 6727 assert_exit_reason(exit_reason_want); 6728 6729 /* Clear the external interrupt. */ 6730 sti_nop_cli(); 6731 report(handle_x2apic_ipi_ran, 6732 "Got pending interrupt after IRQ enabled."); 6733 6734 enter_guest(); 6735 } else if (exit_reason_want == VMX_APIC_WRITE) { 6736 assert_exit_reason(exit_reason_want); 6737 report(virtual_apic_page[apic_reg_index(reg)] == val, 6738 "got APIC write exit @ page offset 0x%03x; val is 0x%x, want 0x%lx", 6739 apic_reg_index(reg), 6740 virtual_apic_page[apic_reg_index(reg)], val); 6741 6742 /* Reenter guest so it can consume/check rcx and exit again. */ 6743 enter_guest(); 6744 } else if (exit_reason_want != VMX_VMCALL) { 6745 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 6746 } 6747 6748 assert_exit_reason(VMX_VMCALL); 6749 if (expectation->wr_behavior == X2APIC_ACCESS_VIRTUALIZED) { 6750 u64 want = val; 6751 u32 got = virtual_apic_page[apic_reg_index(reg)]; 6752 6753 report(got == want, "x2APIC write; got 0x%x, want 0x%lx", got, 6754 want); 6755 } else if (expectation->wr_behavior == X2APIC_ACCESS_PASSED_THROUGH) { 6756 if (!expectation->wr_only) { 6757 u32 got = apic_read(reg); 6758 bool ok; 6759 6760 /* 6761 * When L1's TPR is passed through to L2, the lower 6762 * nibble can be lost. For example, if L2 executes 6763 * WRMSR(0x808, 0x78), then, L1 might read 0x70. 6764 * 6765 * Here's how the lower nibble can get lost: 6766 * 1. L2 executes WRMSR(0x808, 0x78). 6767 * 2. L2 exits to L0 with a WRMSR exit. 6768 * 3. L0 emulates WRMSR, by writing L1's TPR. 6769 * 4. L0 re-enters L2. 6770 * 5. L2 exits to L0 (reason doesn't matter). 6771 * 6. L0 reflects L2's exit to L1. 6772 * 7. Before entering L1, L0 exits to user-space 6773 * (e.g., to satisfy TPR access reporting). 6774 * 8. User-space executes KVM_SET_REGS ioctl, which 6775 * clears the lower nibble of L1's TPR. 6776 */ 6777 if (reg == APIC_TASKPRI) { 6778 got = apic_virt_nibble1(got); 6779 val = apic_virt_nibble1(val); 6780 } 6781 6782 ok = got == val; 6783 report(ok, 6784 "non-virtualized write; val is 0x%x, want 0x%lx", 6785 got, val); 6786 apic_write(reg, restore_val); 6787 } else { 6788 report_pass("non-virtualized and write-only OK"); 6789 } 6790 } 6791 skip_exit_insn(); 6792 6793 report_prefix_pop(); 6794 } 6795 6796 static enum Config_type configure_virt_x2apic_mode_test( 6797 struct virt_x2apic_mode_config *virt_x2apic_mode_config, 6798 u8 *msr_bitmap_page) 6799 { 6800 int msr; 6801 u32 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6802 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6803 6804 /* x2apic-specific VMCS config */ 6805 if (virt_x2apic_mode_config->use_msr_bitmaps) { 6806 /* virt_x2apic_mode_test() checks for MSR bitmaps support */ 6807 cpu_exec_ctrl0 |= CPU_MSR_BITMAP; 6808 } else { 6809 cpu_exec_ctrl0 &= ~CPU_MSR_BITMAP; 6810 } 6811 6812 if (virt_x2apic_mode_config->virtual_interrupt_delivery) { 6813 if (!(ctrl_cpu_rev[1].clr & CPU_VINTD)) { 6814 report_skip("%s : \"virtual-interrupt delivery\" exec control not supported", __func__); 6815 return CONFIG_TYPE_UNSUPPORTED; 6816 } 6817 cpu_exec_ctrl1 |= CPU_VINTD; 6818 } else { 6819 cpu_exec_ctrl1 &= ~CPU_VINTD; 6820 } 6821 6822 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6823 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6824 6825 /* x2APIC MSR intercepts are usually off for "Virtualize x2APIC mode" */ 6826 for (msr = 0x800; msr <= 0x8ff; msr++) { 6827 if (virt_x2apic_mode_config->disable_x2apic_msr_intercepts) { 6828 clear_bit(msr, msr_bitmap_page + 0x000); 6829 clear_bit(msr, msr_bitmap_page + 0x800); 6830 } else { 6831 set_bit(msr, msr_bitmap_page + 0x000); 6832 set_bit(msr, msr_bitmap_page + 0x800); 6833 } 6834 } 6835 6836 /* x2APIC mode can impact virtualization */ 6837 reset_apic(); 6838 if (!virt_x2apic_mode_config->disable_x2apic) 6839 enable_x2apic(); 6840 6841 return configure_apic_reg_virt_test( 6842 &virt_x2apic_mode_config->apic_reg_virt_config); 6843 } 6844 6845 static void virt_x2apic_mode_test(void) 6846 { 6847 u32 *virtual_apic_page; 6848 u8 *msr_bitmap_page; 6849 u64 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6850 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6851 int i; 6852 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6853 6854 if (!cpu_has_apicv()) { 6855 report_skip("%s : Not all required APICv bits supported", __func__); 6856 return; 6857 } 6858 6859 /* 6860 * This is to exercise an issue in KVM's logic to merge L0's and L1's 6861 * MSR bitmaps. Previously, an L1 could get at L0's x2APIC MSRs by 6862 * writing the IA32_SPEC_CTRL MSR or the IA32_PRED_CMD MSRs. KVM would 6863 * then proceed to manipulate the MSR bitmaps, as if VMCS12 had the 6864 * "Virtualize x2APIC mod" control set, even when it didn't. 6865 */ 6866 if (this_cpu_has(X86_FEATURE_SPEC_CTRL)) 6867 wrmsr(MSR_IA32_SPEC_CTRL, 1); 6868 6869 /* 6870 * Check that VMCS12 supports: 6871 * - "Virtual-APIC address", indicated by "use TPR shadow" 6872 * - "MSR-bitmap address", indicated by "use MSR bitmaps" 6873 */ 6874 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) { 6875 report_skip("%s : \"Use TPR shadow\" exec control not supported", __func__); 6876 return; 6877 } else if (!(ctrl_cpu_rev[0].clr & CPU_MSR_BITMAP)) { 6878 report_skip("%s : \"Use MSR bitmaps\" exec control not supported", __func__); 6879 return; 6880 } 6881 6882 test_set_guest(virt_x2apic_mode_guest); 6883 6884 virtual_apic_page = alloc_page(); 6885 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 6886 6887 msr_bitmap_page = alloc_page(); 6888 memset(msr_bitmap_page, 0xff, PAGE_SIZE); 6889 vmcs_write(MSR_BITMAP, virt_to_phys(msr_bitmap_page)); 6890 6891 for (i = 0; i < ARRAY_SIZE(virt_x2apic_mode_tests); i++) { 6892 struct virt_x2apic_mode_test_case *virt_x2apic_mode_test_case = 6893 &virt_x2apic_mode_tests[i]; 6894 struct virt_x2apic_mode_config *virt_x2apic_mode_config = 6895 &virt_x2apic_mode_test_case->virt_x2apic_mode_config; 6896 enum Config_type config_type; 6897 u32 reg; 6898 6899 printf("--- %s test ---\n", virt_x2apic_mode_test_case->name); 6900 config_type = 6901 configure_virt_x2apic_mode_test(virt_x2apic_mode_config, 6902 msr_bitmap_page); 6903 if (config_type == CONFIG_TYPE_UNSUPPORTED) { 6904 report_skip("Skip because of missing features."); 6905 continue; 6906 } else if (config_type == CONFIG_TYPE_VMENTRY_FAILS_EARLY) { 6907 enter_guest_with_bad_controls(); 6908 continue; 6909 } 6910 6911 for (reg = 0; reg < PAGE_SIZE / sizeof(u32); reg += 0x10) { 6912 struct virt_x2apic_mode_expectation expectation; 6913 6914 virt_x2apic_mode_exit_expectation( 6915 reg, virt_x2apic_mode_config, &expectation); 6916 6917 test_x2apic_rd(reg, &expectation, virtual_apic_page); 6918 test_x2apic_wr(reg, &expectation, virtual_apic_page); 6919 } 6920 } 6921 6922 6923 /* Terminate the guest */ 6924 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6925 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6926 args->op = X2APIC_TERMINATE; 6927 enter_guest(); 6928 assert_exit_reason(VMX_VMCALL); 6929 } 6930 6931 static void test_ctl_reg(const char *cr_name, u64 cr, u64 fixed0, u64 fixed1) 6932 { 6933 u64 val; 6934 u64 cr_saved = vmcs_read(cr); 6935 int i; 6936 6937 val = fixed0 & fixed1; 6938 if (cr == HOST_CR4) 6939 vmcs_write(cr, val | X86_CR4_PAE); 6940 else 6941 vmcs_write(cr, val); 6942 report_prefix_pushf("%s %lx", cr_name, val); 6943 if (val == fixed0) 6944 test_vmx_vmlaunch(0); 6945 else 6946 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 6947 report_prefix_pop(); 6948 6949 for (i = 0; i < 64; i++) { 6950 6951 /* Set a bit when the corresponding bit in fixed1 is 0 */ 6952 if ((fixed1 & (1ull << i)) == 0) { 6953 if (cr == HOST_CR4 && ((1ull << i) & X86_CR4_SMEP || 6954 (1ull << i) & X86_CR4_SMAP)) 6955 continue; 6956 6957 vmcs_write(cr, cr_saved | (1ull << i)); 6958 report_prefix_pushf("%s %llx", cr_name, 6959 cr_saved | (1ull << i)); 6960 test_vmx_vmlaunch( 6961 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 6962 report_prefix_pop(); 6963 } 6964 6965 /* Unset a bit when the corresponding bit in fixed0 is 1 */ 6966 if (fixed0 & (1ull << i)) { 6967 vmcs_write(cr, cr_saved & ~(1ull << i)); 6968 report_prefix_pushf("%s %llx", cr_name, 6969 cr_saved & ~(1ull << i)); 6970 test_vmx_vmlaunch( 6971 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 6972 report_prefix_pop(); 6973 } 6974 } 6975 6976 vmcs_write(cr, cr_saved); 6977 } 6978 6979 /* 6980 * 1. The CR0 field must not set any bit to a value not supported in VMX 6981 * operation. 6982 * 2. The CR4 field must not set any bit to a value not supported in VMX 6983 * operation. 6984 * 3. On processors that support Intel 64 architecture, the CR3 field must 6985 * be such that bits 63:52 and bits in the range 51:32 beyond the 6986 * processor's physical-address width must be 0. 6987 * 6988 * [Intel SDM] 6989 */ 6990 static void test_host_ctl_regs(void) 6991 { 6992 u64 fixed0, fixed1, cr3, cr3_saved; 6993 int i; 6994 6995 /* Test CR0 */ 6996 fixed0 = rdmsr(MSR_IA32_VMX_CR0_FIXED0); 6997 fixed1 = rdmsr(MSR_IA32_VMX_CR0_FIXED1); 6998 test_ctl_reg("HOST_CR0", HOST_CR0, fixed0, fixed1); 6999 7000 /* Test CR4 */ 7001 fixed0 = rdmsr(MSR_IA32_VMX_CR4_FIXED0); 7002 fixed1 = rdmsr(MSR_IA32_VMX_CR4_FIXED1) & 7003 ~(X86_CR4_SMEP | X86_CR4_SMAP); 7004 test_ctl_reg("HOST_CR4", HOST_CR4, fixed0, fixed1); 7005 7006 /* Test CR3 */ 7007 cr3_saved = vmcs_read(HOST_CR3); 7008 for (i = cpuid_maxphyaddr(); i < 64; i++) { 7009 cr3 = cr3_saved | (1ul << i); 7010 vmcs_write(HOST_CR3, cr3); 7011 report_prefix_pushf("HOST_CR3 %lx", cr3); 7012 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7013 report_prefix_pop(); 7014 } 7015 7016 vmcs_write(HOST_CR3, cr3_saved); 7017 } 7018 7019 static void test_efer_vmlaunch(u32 fld, bool ok) 7020 { 7021 if (fld == HOST_EFER) { 7022 if (ok) 7023 test_vmx_vmlaunch(0); 7024 else 7025 test_vmx_vmlaunch2(VMXERR_ENTRY_INVALID_CONTROL_FIELD, 7026 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7027 } else { 7028 test_guest_state("EFER test", !ok, GUEST_EFER, "GUEST_EFER"); 7029 } 7030 } 7031 7032 static void test_efer_one(u32 fld, const char * fld_name, u64 efer, 7033 u32 ctrl_fld, u64 ctrl, 7034 int i, const char *efer_bit_name) 7035 { 7036 bool ok; 7037 7038 ok = true; 7039 if (ctrl_fld == EXI_CONTROLS && (ctrl & EXI_LOAD_EFER)) { 7040 if (!!(efer & EFER_LMA) != !!(ctrl & EXI_HOST_64)) 7041 ok = false; 7042 if (!!(efer & EFER_LME) != !!(ctrl & EXI_HOST_64)) 7043 ok = false; 7044 } 7045 if (ctrl_fld == ENT_CONTROLS && (ctrl & ENT_LOAD_EFER)) { 7046 /* Check LMA too since CR0.PG is set. */ 7047 if (!!(efer & EFER_LMA) != !!(ctrl & ENT_GUEST_64)) 7048 ok = false; 7049 if (!!(efer & EFER_LME) != !!(ctrl & ENT_GUEST_64)) 7050 ok = false; 7051 } 7052 7053 /* 7054 * Skip the test if it would enter the guest in 32-bit mode. 7055 * Perhaps write the test in assembly and make sure it 7056 * can be run in either mode? 7057 */ 7058 if (fld == GUEST_EFER && ok && !(ctrl & ENT_GUEST_64)) 7059 return; 7060 7061 vmcs_write(ctrl_fld, ctrl); 7062 vmcs_write(fld, efer); 7063 report_prefix_pushf("%s %s bit turned %s, controls %s", 7064 fld_name, efer_bit_name, 7065 (i & 1) ? "on" : "off", 7066 (i & 2) ? "on" : "off"); 7067 7068 test_efer_vmlaunch(fld, ok); 7069 report_prefix_pop(); 7070 } 7071 7072 static void test_efer_bit(u32 fld, const char * fld_name, 7073 u32 ctrl_fld, u64 ctrl_bit, u64 efer_bit, 7074 const char *efer_bit_name) 7075 { 7076 u64 efer_saved = vmcs_read(fld); 7077 u32 ctrl_saved = vmcs_read(ctrl_fld); 7078 int i; 7079 7080 for (i = 0; i < 4; i++) { 7081 u64 efer = efer_saved & ~efer_bit; 7082 u64 ctrl = ctrl_saved & ~ctrl_bit; 7083 7084 if (i & 1) 7085 efer |= efer_bit; 7086 if (i & 2) 7087 ctrl |= ctrl_bit; 7088 7089 test_efer_one(fld, fld_name, efer, ctrl_fld, ctrl, 7090 i, efer_bit_name); 7091 } 7092 7093 vmcs_write(ctrl_fld, ctrl_saved); 7094 vmcs_write(fld, efer_saved); 7095 } 7096 7097 static void test_efer(u32 fld, const char * fld_name, u32 ctrl_fld, 7098 u64 ctrl_bit1, u64 ctrl_bit2) 7099 { 7100 u64 efer_saved = vmcs_read(fld); 7101 u32 ctrl_saved = vmcs_read(ctrl_fld); 7102 u64 efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 7103 u64 i; 7104 u64 efer; 7105 7106 if (this_cpu_has(X86_FEATURE_NX)) 7107 efer_reserved_bits &= ~EFER_NX; 7108 7109 if (!ctrl_bit1) { 7110 report_skip("%s : \"Load-IA32-EFER\" exit control not supported", __func__); 7111 goto test_entry_exit_mode; 7112 } 7113 7114 report_prefix_pushf("%s %lx", fld_name, efer_saved); 7115 test_efer_vmlaunch(fld, true); 7116 report_prefix_pop(); 7117 7118 /* 7119 * Check reserved bits 7120 */ 7121 vmcs_write(ctrl_fld, ctrl_saved & ~ctrl_bit1); 7122 for (i = 0; i < 64; i++) { 7123 if ((1ull << i) & efer_reserved_bits) { 7124 efer = efer_saved | (1ull << i); 7125 vmcs_write(fld, efer); 7126 report_prefix_pushf("%s %lx", fld_name, efer); 7127 test_efer_vmlaunch(fld, true); 7128 report_prefix_pop(); 7129 } 7130 } 7131 7132 vmcs_write(ctrl_fld, ctrl_saved | ctrl_bit1); 7133 for (i = 0; i < 64; i++) { 7134 if ((1ull << i) & efer_reserved_bits) { 7135 efer = efer_saved | (1ull << i); 7136 vmcs_write(fld, efer); 7137 report_prefix_pushf("%s %lx", fld_name, efer); 7138 test_efer_vmlaunch(fld, false); 7139 report_prefix_pop(); 7140 } 7141 } 7142 7143 vmcs_write(ctrl_fld, ctrl_saved); 7144 vmcs_write(fld, efer_saved); 7145 7146 /* 7147 * Check LMA and LME bits 7148 */ 7149 test_efer_bit(fld, fld_name, 7150 ctrl_fld, ctrl_bit1, 7151 EFER_LMA, 7152 "EFER_LMA"); 7153 test_efer_bit(fld, fld_name, 7154 ctrl_fld, ctrl_bit1, 7155 EFER_LME, 7156 "EFER_LME"); 7157 7158 test_entry_exit_mode: 7159 test_efer_bit(fld, fld_name, 7160 ctrl_fld, ctrl_bit2, 7161 EFER_LMA, 7162 "EFER_LMA"); 7163 test_efer_bit(fld, fld_name, 7164 ctrl_fld, ctrl_bit2, 7165 EFER_LME, 7166 "EFER_LME"); 7167 } 7168 7169 /* 7170 * If the 'load IA32_EFER' VM-exit control is 1, bits reserved in the 7171 * IA32_EFER MSR must be 0 in the field for that register. In addition, 7172 * the values of the LMA and LME bits in the field must each be that of 7173 * the 'host address-space size' VM-exit control. 7174 * 7175 * [Intel SDM] 7176 */ 7177 static void test_host_efer(void) 7178 { 7179 test_efer(HOST_EFER, "HOST_EFER", EXI_CONTROLS, 7180 ctrl_exit_rev.clr & EXI_LOAD_EFER, 7181 EXI_HOST_64); 7182 } 7183 7184 /* 7185 * If the 'load IA32_EFER' VM-enter control is 1, bits reserved in the 7186 * IA32_EFER MSR must be 0 in the field for that register. In addition, 7187 * the values of the LMA and LME bits in the field must each be that of 7188 * the 'IA32e-mode guest' VM-exit control. 7189 */ 7190 static void test_guest_efer(void) 7191 { 7192 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) { 7193 report_skip("%s : \"Load-IA32-EFER\" entry control not supported", __func__); 7194 return; 7195 } 7196 7197 vmcs_write(GUEST_EFER, rdmsr(MSR_EFER)); 7198 test_efer(GUEST_EFER, "GUEST_EFER", ENT_CONTROLS, 7199 ctrl_enter_rev.clr & ENT_LOAD_EFER, 7200 ENT_GUEST_64); 7201 } 7202 7203 /* 7204 * PAT values higher than 8 are uninteresting since they're likely lumped 7205 * in with "8". We only test values above 8 one bit at a time, 7206 * in order to reduce the number of VM-Entries and keep the runtime reasonable. 7207 */ 7208 #define PAT_VAL_LIMIT 8 7209 7210 static void test_pat(u32 field, const char * field_name, u32 ctrl_field, 7211 u64 ctrl_bit) 7212 { 7213 u32 ctrl_saved = vmcs_read(ctrl_field); 7214 u64 pat_saved = vmcs_read(field); 7215 u64 i, val; 7216 u32 j; 7217 int error; 7218 7219 vmcs_clear_bits(ctrl_field, ctrl_bit); 7220 7221 for (i = 0; i < 256; i = (i < PAT_VAL_LIMIT) ? i + 1 : i * 2) { 7222 /* Test PAT0..PAT7 fields */ 7223 for (j = 0; j < (i ? 8 : 1); j++) { 7224 val = i << j * 8; 7225 vmcs_write(field, val); 7226 if (field == HOST_PAT) { 7227 report_prefix_pushf("%s %lx", field_name, val); 7228 test_vmx_vmlaunch(0); 7229 report_prefix_pop(); 7230 7231 } else { // GUEST_PAT 7232 test_guest_state("ENT_LOAD_PAT enabled", false, 7233 val, "GUEST_PAT"); 7234 } 7235 } 7236 } 7237 7238 vmcs_set_bits(ctrl_field, ctrl_bit); 7239 for (i = 0; i < 256; i = (i < PAT_VAL_LIMIT) ? i + 1 : i * 2) { 7240 /* Test PAT0..PAT7 fields */ 7241 for (j = 0; j < (i ? 8 : 1); j++) { 7242 val = i << j * 8; 7243 vmcs_write(field, val); 7244 7245 if (field == HOST_PAT) { 7246 report_prefix_pushf("%s %lx", field_name, val); 7247 if (i == 0x2 || i == 0x3 || i >= 0x8) 7248 error = 7249 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD; 7250 else 7251 error = 0; 7252 7253 test_vmx_vmlaunch(error); 7254 report_prefix_pop(); 7255 7256 } else { // GUEST_PAT 7257 error = (i == 0x2 || i == 0x3 || i >= 0x8); 7258 test_guest_state("ENT_LOAD_PAT enabled", !!error, 7259 val, "GUEST_PAT"); 7260 } 7261 7262 } 7263 } 7264 7265 vmcs_write(ctrl_field, ctrl_saved); 7266 vmcs_write(field, pat_saved); 7267 } 7268 7269 /* 7270 * If the "load IA32_PAT" VM-exit control is 1, the value of the field 7271 * for the IA32_PAT MSR must be one that could be written by WRMSR 7272 * without fault at CPL 0. Specifically, each of the 8 bytes in the 7273 * field must have one of the values 0 (UC), 1 (WC), 4 (WT), 5 (WP), 7274 * 6 (WB), or 7 (UC-). 7275 * 7276 * [Intel SDM] 7277 */ 7278 static void test_load_host_pat(void) 7279 { 7280 /* 7281 * "load IA32_PAT" VM-exit control 7282 */ 7283 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) { 7284 report_skip("%s : \"Load-IA32-PAT\" exit control not supported", __func__); 7285 return; 7286 } 7287 7288 test_pat(HOST_PAT, "HOST_PAT", EXI_CONTROLS, EXI_LOAD_PAT); 7289 } 7290 7291 union cpuidA_eax { 7292 struct { 7293 unsigned int version_id:8; 7294 unsigned int num_counters_gp:8; 7295 unsigned int bit_width:8; 7296 unsigned int mask_length:8; 7297 } split; 7298 unsigned int full; 7299 }; 7300 7301 union cpuidA_edx { 7302 struct { 7303 unsigned int num_counters_fixed:5; 7304 unsigned int bit_width_fixed:8; 7305 unsigned int reserved:9; 7306 } split; 7307 unsigned int full; 7308 }; 7309 7310 static bool valid_pgc(u64 val) 7311 { 7312 struct cpuid id; 7313 union cpuidA_eax eax; 7314 union cpuidA_edx edx; 7315 u64 mask; 7316 7317 id = cpuid(0xA); 7318 eax.full = id.a; 7319 edx.full = id.d; 7320 mask = ~(((1ull << eax.split.num_counters_gp) - 1) | 7321 (((1ull << edx.split.num_counters_fixed) - 1) << 32)); 7322 7323 return !(val & mask); 7324 } 7325 7326 static void test_pgc_vmlaunch(u32 xerror, u32 xreason, bool xfail, bool host) 7327 { 7328 u32 inst_err; 7329 u64 obs; 7330 bool success; 7331 struct vmx_state_area_test_data *data = &vmx_state_area_test_data; 7332 7333 if (host) { 7334 success = vmlaunch(); 7335 obs = rdmsr(data->msr); 7336 if (!success) { 7337 inst_err = vmcs_read(VMX_INST_ERROR); 7338 report(xerror == inst_err, "vmlaunch failed, " 7339 "VMX Inst Error is %d (expected %d)", 7340 inst_err, xerror); 7341 } else { 7342 report(!data->enabled || data->exp == obs, 7343 "Host state is 0x%lx (expected 0x%lx)", 7344 obs, data->exp); 7345 report(success != xfail, "vmlaunch succeeded"); 7346 } 7347 } else { 7348 test_guest_state("load GUEST_PERF_GLOBAL_CTRL", xfail, 7349 GUEST_PERF_GLOBAL_CTRL, 7350 "GUEST_PERF_GLOBAL_CTRL"); 7351 } 7352 } 7353 7354 /* 7355 * test_load_perf_global_ctrl is a generic function for testing the 7356 * "load IA32_PERF_GLOBAL_CTRL" VM-{Entry,Exit} controls. This test function 7357 * tests the provided ctrl_val when disabled and enabled. 7358 * 7359 * @nr: VMCS field number corresponding to the host/guest state field 7360 * @name: Name of the above VMCS field for printing in test report 7361 * @ctrl_nr: VMCS field number corresponding to the VM-{Entry,Exit} control 7362 * @ctrl_val: Bit to set on the ctrl_field 7363 */ 7364 static void test_perf_global_ctrl(u32 nr, const char *name, u32 ctrl_nr, 7365 const char *ctrl_name, u64 ctrl_val) 7366 { 7367 u64 ctrl_saved = vmcs_read(ctrl_nr); 7368 u64 pgc_saved = vmcs_read(nr); 7369 u64 i, val; 7370 bool host = nr == HOST_PERF_GLOBAL_CTRL; 7371 struct vmx_state_area_test_data *data = &vmx_state_area_test_data; 7372 7373 data->msr = MSR_CORE_PERF_GLOBAL_CTRL; 7374 msr_bmp_init(); 7375 vmcs_write(ctrl_nr, ctrl_saved & ~ctrl_val); 7376 data->enabled = false; 7377 report_prefix_pushf("\"load IA32_PERF_GLOBAL_CTRL\"=0 on %s", 7378 ctrl_name); 7379 7380 for (i = 0; i < 64; i++) { 7381 val = 1ull << i; 7382 vmcs_write(nr, val); 7383 report_prefix_pushf("%s = 0x%lx", name, val); 7384 test_pgc_vmlaunch(0, VMX_VMCALL, false, host); 7385 report_prefix_pop(); 7386 } 7387 report_prefix_pop(); 7388 7389 vmcs_write(ctrl_nr, ctrl_saved | ctrl_val); 7390 data->enabled = true; 7391 report_prefix_pushf("\"load IA32_PERF_GLOBAL_CTRL\"=1 on %s", 7392 ctrl_name); 7393 for (i = 0; i < 64; i++) { 7394 val = 1ull << i; 7395 data->exp = val; 7396 vmcs_write(nr, val); 7397 report_prefix_pushf("%s = 0x%lx", name, val); 7398 if (valid_pgc(val)) { 7399 test_pgc_vmlaunch(0, VMX_VMCALL, false, host); 7400 } else { 7401 if (host) 7402 test_pgc_vmlaunch( 7403 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, 7404 0, 7405 true, 7406 host); 7407 else 7408 test_pgc_vmlaunch( 7409 0, 7410 VMX_ENTRY_FAILURE | VMX_FAIL_STATE, 7411 true, 7412 host); 7413 } 7414 report_prefix_pop(); 7415 } 7416 7417 data->enabled = false; 7418 report_prefix_pop(); 7419 vmcs_write(ctrl_nr, ctrl_saved); 7420 vmcs_write(nr, pgc_saved); 7421 } 7422 7423 static void test_load_host_perf_global_ctrl(void) 7424 { 7425 if (!this_cpu_has_perf_global_ctrl()) { 7426 report_skip("%s : \"IA32_PERF_GLOBAL_CTRL\" MSR not supported", __func__); 7427 return; 7428 } 7429 7430 if (!(ctrl_exit_rev.clr & EXI_LOAD_PERF)) { 7431 report_skip("%s : \"Load IA32_PERF_GLOBAL_CTRL\" exit control not supported", __func__); 7432 return; 7433 } 7434 7435 test_perf_global_ctrl(HOST_PERF_GLOBAL_CTRL, "HOST_PERF_GLOBAL_CTRL", 7436 EXI_CONTROLS, "EXI_CONTROLS", EXI_LOAD_PERF); 7437 } 7438 7439 7440 static void test_load_guest_perf_global_ctrl(void) 7441 { 7442 if (!this_cpu_has_perf_global_ctrl()) { 7443 report_skip("%s : \"IA32_PERF_GLOBAL_CTRL\" MSR not supported", __func__); 7444 return; 7445 } 7446 7447 if (!(ctrl_enter_rev.clr & ENT_LOAD_PERF)) { 7448 report_skip("%s : \"Load IA32_PERF_GLOBAL_CTRL\" entry control not supported", __func__); 7449 return; 7450 } 7451 7452 test_perf_global_ctrl(GUEST_PERF_GLOBAL_CTRL, "GUEST_PERF_GLOBAL_CTRL", 7453 ENT_CONTROLS, "ENT_CONTROLS", ENT_LOAD_PERF); 7454 } 7455 7456 7457 /* 7458 * test_vmcs_field - test a value for the given VMCS field 7459 * @field: VMCS field 7460 * @field_name: string name of VMCS field 7461 * @bit_start: starting bit 7462 * @bit_end: ending bit 7463 * @val: value that the bit range must or must not contain 7464 * @valid_val: whether value given in 'val' must be valid or not 7465 * @error: expected VMCS error when vmentry fails for an invalid value 7466 */ 7467 static void test_vmcs_field(u64 field, const char *field_name, u32 bit_start, 7468 u32 bit_end, u64 val, bool valid_val, u32 error) 7469 { 7470 u64 field_saved = vmcs_read(field); 7471 u32 i; 7472 u64 tmp; 7473 u32 bit_on; 7474 u64 mask = ~0ull; 7475 7476 mask = (mask >> bit_end) << bit_end; 7477 mask = mask | ((1 << bit_start) - 1); 7478 tmp = (field_saved & mask) | (val << bit_start); 7479 7480 vmcs_write(field, tmp); 7481 report_prefix_pushf("%s %lx", field_name, tmp); 7482 if (valid_val) 7483 test_vmx_vmlaunch(0); 7484 else 7485 test_vmx_vmlaunch(error); 7486 report_prefix_pop(); 7487 7488 for (i = bit_start; i <= bit_end; i = i + 2) { 7489 bit_on = ((1ull < i) & (val << bit_start)) ? 0 : 1; 7490 if (bit_on) 7491 tmp = field_saved | (1ull << i); 7492 else 7493 tmp = field_saved & ~(1ull << i); 7494 vmcs_write(field, tmp); 7495 report_prefix_pushf("%s %lx", field_name, tmp); 7496 if (valid_val) 7497 test_vmx_vmlaunch(error); 7498 else 7499 test_vmx_vmlaunch(0); 7500 report_prefix_pop(); 7501 } 7502 7503 vmcs_write(field, field_saved); 7504 } 7505 7506 static void test_canonical(u64 field, const char * field_name, bool host) 7507 { 7508 u64 addr_saved = vmcs_read(field); 7509 7510 /* 7511 * Use the existing value if possible. Writing a random canonical 7512 * value is not an option as doing so would corrupt the field being 7513 * tested and likely hose the test. 7514 */ 7515 if (is_canonical(addr_saved)) { 7516 if (host) { 7517 report_prefix_pushf("%s %lx", field_name, addr_saved); 7518 test_vmx_vmlaunch(0); 7519 report_prefix_pop(); 7520 } else { 7521 test_guest_state("Test canonical address", false, 7522 addr_saved, field_name); 7523 } 7524 } 7525 7526 vmcs_write(field, NONCANONICAL); 7527 7528 if (host) { 7529 report_prefix_pushf("%s %llx", field_name, NONCANONICAL); 7530 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7531 report_prefix_pop(); 7532 } else { 7533 test_guest_state("Test non-canonical address", true, 7534 NONCANONICAL, field_name); 7535 } 7536 7537 vmcs_write(field, addr_saved); 7538 } 7539 7540 #define TEST_RPL_TI_FLAGS(reg, name) \ 7541 test_vmcs_field(reg, name, 0, 2, 0x0, true, \ 7542 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7543 7544 #define TEST_CS_TR_FLAGS(reg, name) \ 7545 test_vmcs_field(reg, name, 3, 15, 0x0000, false, \ 7546 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7547 7548 /* 7549 * 1. In the selector field for each of CS, SS, DS, ES, FS, GS and TR, the 7550 * RPL (bits 1:0) and the TI flag (bit 2) must be 0. 7551 * 2. The selector fields for CS and TR cannot be 0000H. 7552 * 3. The selector field for SS cannot be 0000H if the "host address-space 7553 * size" VM-exit control is 0. 7554 * 4. On processors that support Intel 64 architecture, the base-address 7555 * fields for FS, GS and TR must contain canonical addresses. 7556 */ 7557 static void test_host_segment_regs(void) 7558 { 7559 u16 selector_saved; 7560 7561 /* 7562 * Test RPL and TI flags 7563 */ 7564 TEST_RPL_TI_FLAGS(HOST_SEL_CS, "HOST_SEL_CS"); 7565 TEST_RPL_TI_FLAGS(HOST_SEL_SS, "HOST_SEL_SS"); 7566 TEST_RPL_TI_FLAGS(HOST_SEL_DS, "HOST_SEL_DS"); 7567 TEST_RPL_TI_FLAGS(HOST_SEL_ES, "HOST_SEL_ES"); 7568 TEST_RPL_TI_FLAGS(HOST_SEL_FS, "HOST_SEL_FS"); 7569 TEST_RPL_TI_FLAGS(HOST_SEL_GS, "HOST_SEL_GS"); 7570 TEST_RPL_TI_FLAGS(HOST_SEL_TR, "HOST_SEL_TR"); 7571 7572 /* 7573 * Test that CS and TR fields can not be 0x0000 7574 */ 7575 TEST_CS_TR_FLAGS(HOST_SEL_CS, "HOST_SEL_CS"); 7576 TEST_CS_TR_FLAGS(HOST_SEL_TR, "HOST_SEL_TR"); 7577 7578 /* 7579 * SS field can not be 0x0000 if "host address-space size" VM-exit 7580 * control is 0 7581 */ 7582 selector_saved = vmcs_read(HOST_SEL_SS); 7583 vmcs_write(HOST_SEL_SS, 0); 7584 report_prefix_pushf("HOST_SEL_SS 0"); 7585 if (vmcs_read(EXI_CONTROLS) & EXI_HOST_64) { 7586 test_vmx_vmlaunch(0); 7587 } else { 7588 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7589 } 7590 report_prefix_pop(); 7591 7592 vmcs_write(HOST_SEL_SS, selector_saved); 7593 7594 /* 7595 * Base address for FS, GS and TR must be canonical 7596 */ 7597 test_canonical(HOST_BASE_FS, "HOST_BASE_FS", true); 7598 test_canonical(HOST_BASE_GS, "HOST_BASE_GS", true); 7599 test_canonical(HOST_BASE_TR, "HOST_BASE_TR", true); 7600 } 7601 7602 /* 7603 * On processors that support Intel 64 architecture, the base-address 7604 * fields for GDTR and IDTR must contain canonical addresses. 7605 */ 7606 static void test_host_desc_tables(void) 7607 { 7608 test_canonical(HOST_BASE_GDTR, "HOST_BASE_GDTR", true); 7609 test_canonical(HOST_BASE_IDTR, "HOST_BASE_IDTR", true); 7610 } 7611 7612 /* 7613 * If the "host address-space size" VM-exit control is 0, the following must 7614 * hold: 7615 * - The "IA-32e mode guest" VM-entry control is 0. 7616 * - Bit 17 of the CR4 field (corresponding to CR4.PCIDE) is 0. 7617 * - Bits 63:32 in the RIP field are 0. 7618 * 7619 * If the "host address-space size" VM-exit control is 1, the following must 7620 * hold: 7621 * - Bit 5 of the CR4 field (corresponding to CR4.PAE) is 1. 7622 * - The RIP field contains a canonical address. 7623 * 7624 */ 7625 static void test_host_addr_size(void) 7626 { 7627 u64 cr4_saved = vmcs_read(HOST_CR4); 7628 u64 rip_saved = vmcs_read(HOST_RIP); 7629 u64 entry_ctrl_saved = vmcs_read(ENT_CONTROLS); 7630 7631 assert(vmcs_read(EXI_CONTROLS) & EXI_HOST_64); 7632 assert(cr4_saved & X86_CR4_PAE); 7633 7634 vmcs_write(ENT_CONTROLS, entry_ctrl_saved | ENT_GUEST_64); 7635 report_prefix_pushf("\"IA-32e mode guest\" enabled"); 7636 test_vmx_vmlaunch(0); 7637 report_prefix_pop(); 7638 7639 if (this_cpu_has(X86_FEATURE_PCID)) { 7640 vmcs_write(HOST_CR4, cr4_saved | X86_CR4_PCIDE); 7641 report_prefix_pushf("\"CR4.PCIDE\" set"); 7642 test_vmx_vmlaunch(0); 7643 report_prefix_pop(); 7644 } 7645 7646 vmcs_write(HOST_CR4, cr4_saved & ~X86_CR4_PAE); 7647 report_prefix_pushf("\"CR4.PAE\" unset"); 7648 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7649 vmcs_write(HOST_CR4, cr4_saved); 7650 report_prefix_pop(); 7651 7652 vmcs_write(HOST_RIP, NONCANONICAL); 7653 report_prefix_pushf("HOST_RIP %llx", NONCANONICAL); 7654 test_vmx_vmlaunch_must_fail(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7655 report_prefix_pop(); 7656 7657 vmcs_write(ENT_CONTROLS, entry_ctrl_saved | ENT_GUEST_64); 7658 vmcs_write(HOST_RIP, rip_saved); 7659 vmcs_write(HOST_CR4, cr4_saved); 7660 7661 /* 7662 * Restore host's active CR4 and RIP values by triggering a VM-Exit. 7663 * The original CR4 and RIP values in the VMCS are restored between 7664 * testcases as needed, but don't guarantee a VM-Exit and so the active 7665 * CR4 and RIP may still hold a test value. Running with the test CR4 7666 * and RIP values at some point is unavoidable, and the active values 7667 * are unlikely to affect VM-Enter, so the above doesn't force a VM-exit 7668 * between testcases. Note, if VM-Enter is surrounded by CALL+RET then 7669 * the active RIP will already be restored, but that's also not 7670 * guaranteed, and CR4 needs to be restored regardless. 7671 */ 7672 report_prefix_pushf("restore host state"); 7673 test_vmx_vmlaunch(0); 7674 report_prefix_pop(); 7675 } 7676 7677 /* 7678 * Check that the virtual CPU checks the VMX Host State Area as 7679 * documented in the Intel SDM. 7680 */ 7681 static void vmx_host_state_area_test(void) 7682 { 7683 /* 7684 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 7685 * fail due to invalid guest state, should we make it that 7686 * far. 7687 */ 7688 vmcs_write(GUEST_RFLAGS, 0); 7689 7690 test_host_ctl_regs(); 7691 7692 test_canonical(HOST_SYSENTER_ESP, "HOST_SYSENTER_ESP", true); 7693 test_canonical(HOST_SYSENTER_EIP, "HOST_SYSENTER_EIP", true); 7694 7695 test_host_efer(); 7696 test_load_host_pat(); 7697 test_host_segment_regs(); 7698 test_host_desc_tables(); 7699 test_host_addr_size(); 7700 test_load_host_perf_global_ctrl(); 7701 } 7702 7703 /* 7704 * If the "load debug controls" VM-entry control is 1, bits 63:32 in 7705 * the DR7 field must be 0. 7706 * 7707 * [Intel SDM] 7708 */ 7709 static void test_guest_dr7(void) 7710 { 7711 u32 ent_saved = vmcs_read(ENT_CONTROLS); 7712 u64 dr7_saved = vmcs_read(GUEST_DR7); 7713 u64 val; 7714 int i; 7715 7716 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS) { 7717 vmcs_clear_bits(ENT_CONTROLS, ENT_LOAD_DBGCTLS); 7718 for (i = 0; i < 64; i++) { 7719 val = 1ull << i; 7720 vmcs_write(GUEST_DR7, val); 7721 test_guest_state("ENT_LOAD_DBGCTLS disabled", false, 7722 val, "GUEST_DR7"); 7723 } 7724 } 7725 if (ctrl_enter_rev.clr & ENT_LOAD_DBGCTLS) { 7726 vmcs_set_bits(ENT_CONTROLS, ENT_LOAD_DBGCTLS); 7727 for (i = 0; i < 64; i++) { 7728 val = 1ull << i; 7729 vmcs_write(GUEST_DR7, val); 7730 test_guest_state("ENT_LOAD_DBGCTLS enabled", i >= 32, 7731 val, "GUEST_DR7"); 7732 } 7733 } 7734 vmcs_write(GUEST_DR7, dr7_saved); 7735 vmcs_write(ENT_CONTROLS, ent_saved); 7736 } 7737 7738 /* 7739 * If the "load IA32_PAT" VM-entry control is 1, the value of the field 7740 * for the IA32_PAT MSR must be one that could be written by WRMSR 7741 * without fault at CPL 0. Specifically, each of the 8 bytes in the 7742 * field must have one of the values 0 (UC), 1 (WC), 4 (WT), 5 (WP), 7743 * 6 (WB), or 7 (UC-). 7744 * 7745 * [Intel SDM] 7746 */ 7747 static void test_load_guest_pat(void) 7748 { 7749 /* 7750 * "load IA32_PAT" VM-entry control 7751 */ 7752 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 7753 report_skip("%s : \"Load-IA32-PAT\" entry control not supported", __func__); 7754 return; 7755 } 7756 7757 test_pat(GUEST_PAT, "GUEST_PAT", ENT_CONTROLS, ENT_LOAD_PAT); 7758 } 7759 7760 #define MSR_IA32_BNDCFGS_RSVD_MASK 0x00000ffc 7761 7762 /* 7763 * If the "load IA32_BNDCFGS" VM-entry control is 1, the following 7764 * checks are performed on the field for the IA32_BNDCFGS MSR: 7765 * 7766 * - Bits reserved in the IA32_BNDCFGS MSR must be 0. 7767 * - The linear address in bits 63:12 must be canonical. 7768 * 7769 * [Intel SDM] 7770 */ 7771 static void test_load_guest_bndcfgs(void) 7772 { 7773 u64 bndcfgs_saved = vmcs_read(GUEST_BNDCFGS); 7774 u64 bndcfgs; 7775 7776 if (!(ctrl_enter_rev.clr & ENT_LOAD_BNDCFGS)) { 7777 report_skip("%s : \"Load-IA32-BNDCFGS\" entry control not supported", __func__); 7778 return; 7779 } 7780 7781 vmcs_clear_bits(ENT_CONTROLS, ENT_LOAD_BNDCFGS); 7782 7783 vmcs_write(GUEST_BNDCFGS, NONCANONICAL); 7784 test_guest_state("ENT_LOAD_BNDCFGS disabled", false, 7785 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7786 bndcfgs = bndcfgs_saved | MSR_IA32_BNDCFGS_RSVD_MASK; 7787 vmcs_write(GUEST_BNDCFGS, bndcfgs); 7788 test_guest_state("ENT_LOAD_BNDCFGS disabled", false, 7789 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7790 7791 vmcs_set_bits(ENT_CONTROLS, ENT_LOAD_BNDCFGS); 7792 7793 vmcs_write(GUEST_BNDCFGS, NONCANONICAL); 7794 test_guest_state("ENT_LOAD_BNDCFGS enabled", true, 7795 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7796 bndcfgs = bndcfgs_saved | MSR_IA32_BNDCFGS_RSVD_MASK; 7797 vmcs_write(GUEST_BNDCFGS, bndcfgs); 7798 test_guest_state("ENT_LOAD_BNDCFGS enabled", true, 7799 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7800 7801 vmcs_write(GUEST_BNDCFGS, bndcfgs_saved); 7802 } 7803 7804 #define GUEST_SEG_UNUSABLE_MASK (1u << 16) 7805 #define GUEST_SEG_SEL_TI_MASK (1u << 2) 7806 7807 7808 #define TEST_SEGMENT_SEL(test, xfail, sel, val) \ 7809 do { \ 7810 vmcs_write(sel, val); \ 7811 test_guest_state(test " segment", xfail, val, xstr(sel)); \ 7812 } while (0) 7813 7814 #define TEST_INVALID_SEG_SEL(sel, val) \ 7815 TEST_SEGMENT_SEL("Invalid: " xstr(val), true, sel, val); 7816 7817 #define TEST_VALID_SEG_SEL(sel, val) \ 7818 TEST_SEGMENT_SEL("Valid: " xstr(val), false, sel, val); 7819 7820 /* 7821 * The following checks are done on the Selector field of the Guest Segment 7822 * Registers: 7823 * - TR. The TI flag (bit 2) must be 0. 7824 * - LDTR. If LDTR is usable, the TI flag (bit 2) must be 0. 7825 * - SS. If the guest will not be virtual-8086 and the "unrestricted 7826 * guest" VM-execution control is 0, the RPL (bits 1:0) must equal 7827 * the RPL of the selector field for CS. 7828 * 7829 * [Intel SDM] 7830 */ 7831 static void test_guest_segment_sel_fields(void) 7832 { 7833 u16 sel_saved; 7834 u32 ar_saved; 7835 u32 cpu_ctrl0_saved; 7836 u32 cpu_ctrl1_saved; 7837 u16 cs_rpl_bits; 7838 7839 /* 7840 * Test for GUEST_SEL_TR 7841 */ 7842 sel_saved = vmcs_read(GUEST_SEL_TR); 7843 TEST_INVALID_SEG_SEL(GUEST_SEL_TR, sel_saved | GUEST_SEG_SEL_TI_MASK); 7844 vmcs_write(GUEST_SEL_TR, sel_saved); 7845 7846 /* 7847 * Test for GUEST_SEL_LDTR 7848 */ 7849 sel_saved = vmcs_read(GUEST_SEL_LDTR); 7850 ar_saved = vmcs_read(GUEST_AR_LDTR); 7851 /* LDTR is set unusable */ 7852 vmcs_write(GUEST_AR_LDTR, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7853 TEST_VALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved | GUEST_SEG_SEL_TI_MASK); 7854 TEST_VALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved & ~GUEST_SEG_SEL_TI_MASK); 7855 /* LDTR is set usable */ 7856 vmcs_write(GUEST_AR_LDTR, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7857 TEST_INVALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved | GUEST_SEG_SEL_TI_MASK); 7858 7859 TEST_VALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved & ~GUEST_SEG_SEL_TI_MASK); 7860 7861 vmcs_write(GUEST_AR_LDTR, ar_saved); 7862 vmcs_write(GUEST_SEL_LDTR, sel_saved); 7863 7864 /* 7865 * Test for GUEST_SEL_SS 7866 */ 7867 cpu_ctrl0_saved = vmcs_read(CPU_EXEC_CTRL0); 7868 cpu_ctrl1_saved = vmcs_read(CPU_EXEC_CTRL1); 7869 ar_saved = vmcs_read(GUEST_AR_SS); 7870 /* Turn off "unrestricted guest" vm-execution control */ 7871 vmcs_write(CPU_EXEC_CTRL1, cpu_ctrl1_saved & ~CPU_URG); 7872 cs_rpl_bits = vmcs_read(GUEST_SEL_CS) & 0x3; 7873 sel_saved = vmcs_read(GUEST_SEL_SS); 7874 TEST_INVALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 7875 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 7876 /* Make SS usable if it's unusable or vice-versa */ 7877 if (ar_saved & GUEST_SEG_UNUSABLE_MASK) 7878 vmcs_write(GUEST_AR_SS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7879 else 7880 vmcs_write(GUEST_AR_SS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7881 TEST_INVALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 7882 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 7883 7884 /* Need a valid EPTP as the passing case fully enters the guest. */ 7885 if (enable_unrestricted_guest(true)) 7886 goto skip_ss_tests; 7887 7888 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 7889 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 7890 7891 /* Make SS usable if it's unusable or vice-versa */ 7892 if (vmcs_read(GUEST_AR_SS) & GUEST_SEG_UNUSABLE_MASK) 7893 vmcs_write(GUEST_AR_SS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7894 else 7895 vmcs_write(GUEST_AR_SS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7896 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 7897 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 7898 skip_ss_tests: 7899 7900 vmcs_write(GUEST_AR_SS, ar_saved); 7901 vmcs_write(GUEST_SEL_SS, sel_saved); 7902 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrl0_saved); 7903 vmcs_write(CPU_EXEC_CTRL1, cpu_ctrl1_saved); 7904 } 7905 7906 #define TEST_SEGMENT_BASE_ADDR_UPPER_BITS(xfail, seg_base) \ 7907 do { \ 7908 addr_saved = vmcs_read(seg_base); \ 7909 for (i = 32; i < 63; i = i + 4) { \ 7910 addr = addr_saved | 1ull << i; \ 7911 vmcs_write(seg_base, addr); \ 7912 test_guest_state("seg.BASE[63:32] != 0, usable = " xstr(xfail), \ 7913 xfail, addr, xstr(seg_base)); \ 7914 } \ 7915 vmcs_write(seg_base, addr_saved); \ 7916 } while (0) 7917 7918 #define TEST_SEGMENT_BASE_ADDR_CANONICAL(xfail, seg_base) \ 7919 do { \ 7920 addr_saved = vmcs_read(seg_base); \ 7921 vmcs_write(seg_base, NONCANONICAL); \ 7922 test_guest_state("seg.BASE non-canonical, usable = " xstr(xfail), \ 7923 xfail, NONCANONICAL, xstr(seg_base)); \ 7924 vmcs_write(seg_base, addr_saved); \ 7925 } while (0) 7926 7927 /* 7928 * The following checks are done on the Base Address field of the Guest 7929 * Segment Registers on processors that support Intel 64 architecture: 7930 * - TR, FS, GS : The address must be canonical. 7931 * - LDTR : If LDTR is usable, the address must be canonical. 7932 * - CS : Bits 63:32 of the address must be zero. 7933 * - SS, DS, ES : If the register is usable, bits 63:32 of the address 7934 * must be zero. 7935 * 7936 * [Intel SDM] 7937 */ 7938 static void test_guest_segment_base_addr_fields(void) 7939 { 7940 u64 addr_saved; 7941 u64 addr; 7942 u32 ar_saved; 7943 int i; 7944 7945 /* 7946 * The address of TR, FS, GS and LDTR must be canonical. 7947 */ 7948 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_TR); 7949 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_FS); 7950 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_GS); 7951 ar_saved = vmcs_read(GUEST_AR_LDTR); 7952 /* Make LDTR unusable */ 7953 vmcs_write(GUEST_AR_LDTR, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7954 TEST_SEGMENT_BASE_ADDR_CANONICAL(false, GUEST_BASE_LDTR); 7955 /* Make LDTR usable */ 7956 vmcs_write(GUEST_AR_LDTR, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7957 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_LDTR); 7958 7959 vmcs_write(GUEST_AR_LDTR, ar_saved); 7960 7961 /* 7962 * Bits 63:32 in CS, SS, DS and ES base address must be zero 7963 */ 7964 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_CS); 7965 ar_saved = vmcs_read(GUEST_AR_SS); 7966 /* Make SS unusable */ 7967 vmcs_write(GUEST_AR_SS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7968 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(false, GUEST_BASE_SS); 7969 /* Make SS usable */ 7970 vmcs_write(GUEST_AR_SS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7971 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_SS); 7972 vmcs_write(GUEST_AR_SS, ar_saved); 7973 7974 ar_saved = vmcs_read(GUEST_AR_DS); 7975 /* Make DS unusable */ 7976 vmcs_write(GUEST_AR_DS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7977 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(false, GUEST_BASE_DS); 7978 /* Make DS usable */ 7979 vmcs_write(GUEST_AR_DS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7980 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_DS); 7981 vmcs_write(GUEST_AR_DS, ar_saved); 7982 7983 ar_saved = vmcs_read(GUEST_AR_ES); 7984 /* Make ES unusable */ 7985 vmcs_write(GUEST_AR_ES, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7986 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(false, GUEST_BASE_ES); 7987 /* Make ES usable */ 7988 vmcs_write(GUEST_AR_ES, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7989 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_ES); 7990 vmcs_write(GUEST_AR_ES, ar_saved); 7991 } 7992 7993 /* 7994 * Check that the virtual CPU checks the VMX Guest State Area as 7995 * documented in the Intel SDM. 7996 */ 7997 static void vmx_guest_state_area_test(void) 7998 { 7999 vmx_set_test_stage(1); 8000 test_set_guest(guest_state_test_main); 8001 8002 /* 8003 * The IA32_SYSENTER_ESP field and the IA32_SYSENTER_EIP field 8004 * must each contain a canonical address. 8005 */ 8006 test_canonical(GUEST_SYSENTER_ESP, "GUEST_SYSENTER_ESP", false); 8007 test_canonical(GUEST_SYSENTER_EIP, "GUEST_SYSENTER_EIP", false); 8008 8009 test_guest_dr7(); 8010 test_load_guest_pat(); 8011 test_guest_efer(); 8012 test_load_guest_perf_global_ctrl(); 8013 test_load_guest_bndcfgs(); 8014 8015 test_guest_segment_sel_fields(); 8016 test_guest_segment_base_addr_fields(); 8017 8018 test_canonical(GUEST_BASE_GDTR, "GUEST_BASE_GDTR", false); 8019 test_canonical(GUEST_BASE_IDTR, "GUEST_BASE_IDTR", false); 8020 8021 u32 guest_desc_limit_saved = vmcs_read(GUEST_LIMIT_GDTR); 8022 int i; 8023 for (i = 16; i <= 31; i++) { 8024 u32 tmp = guest_desc_limit_saved | (1ull << i); 8025 vmcs_write(GUEST_LIMIT_GDTR, tmp); 8026 test_guest_state("GDT.limit > 0xffff", true, tmp, "GUEST_LIMIT_GDTR"); 8027 } 8028 vmcs_write(GUEST_LIMIT_GDTR, guest_desc_limit_saved); 8029 8030 guest_desc_limit_saved = vmcs_read(GUEST_LIMIT_IDTR); 8031 for (i = 16; i <= 31; i++) { 8032 u32 tmp = guest_desc_limit_saved | (1ull << i); 8033 vmcs_write(GUEST_LIMIT_IDTR, tmp); 8034 test_guest_state("IDT.limit > 0xffff", true, tmp, "GUEST_LIMIT_IDTR"); 8035 } 8036 vmcs_write(GUEST_LIMIT_IDTR, guest_desc_limit_saved); 8037 8038 /* 8039 * Let the guest finish execution 8040 */ 8041 vmx_set_test_stage(2); 8042 enter_guest(); 8043 } 8044 8045 extern void unrestricted_guest_main(void); 8046 asm (".code32\n" 8047 "unrestricted_guest_main:\n" 8048 "vmcall\n" 8049 "nop\n" 8050 "mov $1, %edi\n" 8051 "call hypercall\n" 8052 ".code64\n"); 8053 8054 static void setup_unrestricted_guest(void) 8055 { 8056 vmcs_write(GUEST_CR0, vmcs_read(GUEST_CR0) & ~(X86_CR0_PG)); 8057 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) & ~ENT_GUEST_64); 8058 vmcs_write(GUEST_EFER, vmcs_read(GUEST_EFER) & ~EFER_LMA); 8059 vmcs_write(GUEST_RIP, virt_to_phys(unrestricted_guest_main)); 8060 } 8061 8062 static void unsetup_unrestricted_guest(void) 8063 { 8064 vmcs_write(GUEST_CR0, vmcs_read(GUEST_CR0) | X86_CR0_PG); 8065 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) | ENT_GUEST_64); 8066 vmcs_write(GUEST_EFER, vmcs_read(GUEST_EFER) | EFER_LMA); 8067 vmcs_write(GUEST_RIP, (u64) phys_to_virt(vmcs_read(GUEST_RIP))); 8068 vmcs_write(GUEST_RSP, (u64) phys_to_virt(vmcs_read(GUEST_RSP))); 8069 } 8070 8071 /* 8072 * If "unrestricted guest" secondary VM-execution control is set, guests 8073 * can run in unpaged protected mode. 8074 */ 8075 static void vmentry_unrestricted_guest_test(void) 8076 { 8077 if (enable_unrestricted_guest(true)) { 8078 report_skip("%s: \"Unrestricted guest\" exec control not supported", __func__); 8079 return; 8080 } 8081 8082 test_set_guest(unrestricted_guest_main); 8083 setup_unrestricted_guest(); 8084 test_guest_state("Unrestricted guest test", false, CPU_URG, "CPU_URG"); 8085 8086 /* 8087 * Let the guest finish execution as a regular guest 8088 */ 8089 unsetup_unrestricted_guest(); 8090 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) & ~CPU_URG); 8091 enter_guest(); 8092 } 8093 8094 static bool valid_vmcs_for_vmentry(void) 8095 { 8096 struct vmcs *current_vmcs = NULL; 8097 8098 if (vmcs_save(¤t_vmcs)) 8099 return false; 8100 8101 return current_vmcs && !current_vmcs->hdr.shadow_vmcs; 8102 } 8103 8104 static void try_vmentry_in_movss_shadow(void) 8105 { 8106 u32 vm_inst_err; 8107 u32 flags; 8108 bool early_failure = false; 8109 u32 expected_flags = X86_EFLAGS_FIXED; 8110 bool valid_vmcs = valid_vmcs_for_vmentry(); 8111 8112 expected_flags |= valid_vmcs ? X86_EFLAGS_ZF : X86_EFLAGS_CF; 8113 8114 /* 8115 * Indirectly set VM_INST_ERR to 12 ("VMREAD/VMWRITE from/to 8116 * unsupported VMCS component"). 8117 */ 8118 vmcs_write(~0u, 0); 8119 8120 __asm__ __volatile__ ("mov %[host_rsp], %%edx;" 8121 "vmwrite %%rsp, %%rdx;" 8122 "mov 0f, %%rax;" 8123 "mov %[host_rip], %%edx;" 8124 "vmwrite %%rax, %%rdx;" 8125 "mov $-1, %%ah;" 8126 "sahf;" 8127 "mov %%ss, %%ax;" 8128 "mov %%ax, %%ss;" 8129 "vmlaunch;" 8130 "mov $1, %[early_failure];" 8131 "0: lahf;" 8132 "movzbl %%ah, %[flags]" 8133 : [early_failure] "+r" (early_failure), 8134 [flags] "=&a" (flags) 8135 : [host_rsp] "i" (HOST_RSP), 8136 [host_rip] "i" (HOST_RIP) 8137 : "rdx", "cc", "memory"); 8138 vm_inst_err = vmcs_read(VMX_INST_ERROR); 8139 8140 report(early_failure, "Early VM-entry failure"); 8141 report(flags == expected_flags, "RFLAGS[8:0] is %x (actual %x)", 8142 expected_flags, flags); 8143 if (valid_vmcs) 8144 report(vm_inst_err == VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, 8145 "VM-instruction error is %d (actual %d)", 8146 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, vm_inst_err); 8147 } 8148 8149 static void vmentry_movss_shadow_test(void) 8150 { 8151 struct vmcs *orig_vmcs; 8152 8153 TEST_ASSERT(!vmcs_save(&orig_vmcs)); 8154 8155 /* 8156 * Set the launched flag on the current VMCS to verify the correct 8157 * error priority, below. 8158 */ 8159 test_set_guest(v2_null_test_guest); 8160 enter_guest(); 8161 8162 /* 8163 * With bit 1 of the guest's RFLAGS clear, VM-entry should 8164 * fail due to invalid guest state (if we make it that far). 8165 */ 8166 vmcs_write(GUEST_RFLAGS, 0); 8167 8168 /* 8169 * "VM entry with events blocked by MOV SS" takes precedence over 8170 * "VMLAUNCH with non-clear VMCS." 8171 */ 8172 report_prefix_push("valid current-VMCS"); 8173 try_vmentry_in_movss_shadow(); 8174 report_prefix_pop(); 8175 8176 /* 8177 * VMfailInvalid takes precedence over "VM entry with events 8178 * blocked by MOV SS." 8179 */ 8180 TEST_ASSERT(!vmcs_clear(orig_vmcs)); 8181 report_prefix_push("no current-VMCS"); 8182 try_vmentry_in_movss_shadow(); 8183 report_prefix_pop(); 8184 8185 TEST_ASSERT(!make_vmcs_current(orig_vmcs)); 8186 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 8187 } 8188 8189 static void vmx_ldtr_test_guest(void) 8190 { 8191 u16 ldtr = sldt(); 8192 8193 report(ldtr == NP_SEL, "Expected %x for L2 LDTR selector (got %x)", 8194 NP_SEL, ldtr); 8195 } 8196 8197 /* 8198 * Ensure that the L1 LDTR is set to 0 on VM-exit. 8199 */ 8200 static void vmx_ldtr_test(void) 8201 { 8202 const u8 ldt_ar = 0x82; /* Present LDT */ 8203 u16 sel = FIRST_SPARE_SEL; 8204 8205 /* Set up a non-zero L1 LDTR prior to VM-entry. */ 8206 set_gdt_entry(sel, 0, 0, ldt_ar, 0); 8207 lldt(sel); 8208 8209 test_set_guest(vmx_ldtr_test_guest); 8210 /* 8211 * Set up a different LDTR for L2. The actual GDT contents are 8212 * irrelevant, since we stuff the hidden descriptor state 8213 * straight into the VMCS rather than reading it from the GDT. 8214 */ 8215 vmcs_write(GUEST_SEL_LDTR, NP_SEL); 8216 vmcs_write(GUEST_AR_LDTR, ldt_ar); 8217 enter_guest(); 8218 8219 /* 8220 * VM-exit should clear LDTR (and make it unusable, but we 8221 * won't verify that here). 8222 */ 8223 sel = sldt(); 8224 report(!sel, "Expected 0 for L1 LDTR selector (got %x)", sel); 8225 } 8226 8227 static void vmx_single_vmcall_guest(void) 8228 { 8229 vmcall(); 8230 } 8231 8232 static void vmx_cr_load_test(void) 8233 { 8234 unsigned long cr3, cr4, orig_cr3, orig_cr4; 8235 u32 ctrls[2] = {0}; 8236 pgd_t *pml5; 8237 8238 orig_cr4 = read_cr4(); 8239 orig_cr3 = read_cr3(); 8240 8241 if (!this_cpu_has(X86_FEATURE_PCID)) { 8242 report_skip("%s : PCID not detected", __func__); 8243 return; 8244 } 8245 if (!this_cpu_has(X86_FEATURE_MCE)) { 8246 report_skip("%s : MCE not detected", __func__); 8247 return; 8248 } 8249 8250 TEST_ASSERT(!(orig_cr3 & X86_CR3_PCID_MASK)); 8251 8252 /* Enable PCID for L1. */ 8253 cr4 = orig_cr4 | X86_CR4_PCIDE; 8254 cr3 = orig_cr3 | 0x1; 8255 TEST_ASSERT(!write_cr4_safe(cr4)); 8256 write_cr3(cr3); 8257 8258 test_set_guest(vmx_single_vmcall_guest); 8259 vmcs_write(HOST_CR4, cr4); 8260 vmcs_write(HOST_CR3, cr3); 8261 enter_guest(); 8262 8263 /* 8264 * No exception is expected. 8265 * 8266 * NB. KVM loads the last guest write to CR4 into CR4 read 8267 * shadow. In order to trigger an exit to KVM, we can toggle a 8268 * bit that is owned by KVM. We use CR4.MCE, which shall 8269 * have no side effect because normally no guest MCE (e.g., as the 8270 * result of bad memory) would happen during this test. 8271 */ 8272 TEST_ASSERT(!write_cr4_safe(cr4 ^ X86_CR4_MCE)); 8273 8274 /* Cleanup L1 state. */ 8275 write_cr3(orig_cr3); 8276 TEST_ASSERT(!write_cr4_safe(orig_cr4)); 8277 8278 if (!this_cpu_has(X86_FEATURE_LA57)) 8279 goto done; 8280 8281 /* 8282 * Allocate a full page for PML5 to guarantee alignment, though only 8283 * the first entry needs to be filled (the test's virtual addresses 8284 * most definitely do not have any of bits 56:48 set). 8285 */ 8286 pml5 = alloc_page(); 8287 *pml5 = orig_cr3 | PT_PRESENT_MASK | PT_WRITABLE_MASK; 8288 8289 /* 8290 * Transition to/from 5-level paging in the host via VM-Exit. CR4.LA57 8291 * can't be toggled while long is active via MOV CR4, but there are no 8292 * such restrictions on VM-Exit. 8293 */ 8294 lol_5level: 8295 vmcs_write(HOST_CR4, orig_cr4 | X86_CR4_LA57); 8296 vmcs_write(HOST_CR3, virt_to_phys(pml5)); 8297 enter_guest(); 8298 8299 /* 8300 * VMREAD with a memory operand to verify KVM detects the LA57 change, 8301 * e.g. uses the correct guest root level in gva_to_gpa(). 8302 */ 8303 TEST_ASSERT(vmcs_readm(HOST_CR3) == virt_to_phys(pml5)); 8304 TEST_ASSERT(vmcs_readm(HOST_CR4) == (orig_cr4 | X86_CR4_LA57)); 8305 8306 vmcs_write(HOST_CR4, orig_cr4); 8307 vmcs_write(HOST_CR3, orig_cr3); 8308 enter_guest(); 8309 8310 TEST_ASSERT(vmcs_readm(HOST_CR3) == orig_cr3); 8311 TEST_ASSERT(vmcs_readm(HOST_CR4) == orig_cr4); 8312 8313 /* 8314 * And now do the same LA57 shenanigans with EPT enabled. KVM uses 8315 * two separate MMUs when L1 uses TDP, whereas the above shadow paging 8316 * version shares an MMU between L1 and L2. 8317 * 8318 * If the saved execution controls are non-zero then the EPT version 8319 * has already run. In that case, restore the old controls. If EPT 8320 * setup fails, e.g. EPT isn't supported, fall through and finish up. 8321 */ 8322 if (ctrls[0]) { 8323 vmcs_write(CPU_EXEC_CTRL0, ctrls[0]); 8324 vmcs_write(CPU_EXEC_CTRL1, ctrls[1]); 8325 } else if (!setup_ept(false)) { 8326 ctrls[0] = vmcs_read(CPU_EXEC_CTRL0); 8327 ctrls[1] = vmcs_read(CPU_EXEC_CTRL1); 8328 goto lol_5level; 8329 } 8330 8331 free_page(pml5); 8332 8333 done: 8334 skip_exit_vmcall(); 8335 enter_guest(); 8336 } 8337 8338 static void vmx_cr4_osxsave_test_guest(void) 8339 { 8340 write_cr4(read_cr4() & ~X86_CR4_OSXSAVE); 8341 } 8342 8343 /* 8344 * Ensure that kvm recalculates the L1 guest's CPUID.01H:ECX.OSXSAVE 8345 * after VM-exit from an L2 guest that sets CR4.OSXSAVE to a different 8346 * value than in L1. 8347 */ 8348 static void vmx_cr4_osxsave_test(void) 8349 { 8350 if (!this_cpu_has(X86_FEATURE_XSAVE)) { 8351 report_skip("%s : XSAVE not detected", __func__); 8352 return; 8353 } 8354 8355 if (!(read_cr4() & X86_CR4_OSXSAVE)) { 8356 unsigned long cr4 = read_cr4() | X86_CR4_OSXSAVE; 8357 8358 write_cr4(cr4); 8359 vmcs_write(GUEST_CR4, cr4); 8360 vmcs_write(HOST_CR4, cr4); 8361 } 8362 8363 TEST_ASSERT(this_cpu_has(X86_FEATURE_OSXSAVE)); 8364 8365 test_set_guest(vmx_cr4_osxsave_test_guest); 8366 enter_guest(); 8367 8368 TEST_ASSERT(this_cpu_has(X86_FEATURE_OSXSAVE)); 8369 } 8370 8371 /* 8372 * FNOP with both CR0.TS and CR0.EM clear should not generate #NM, and the L2 8373 * guest should exit normally. 8374 */ 8375 static void vmx_no_nm_test(void) 8376 { 8377 test_set_guest(fnop); 8378 vmcs_write(GUEST_CR0, read_cr0() & ~(X86_CR0_TS | X86_CR0_EM)); 8379 enter_guest(); 8380 } 8381 8382 bool vmx_pending_event_ipi_fired; 8383 static void vmx_pending_event_ipi_isr(isr_regs_t *regs) 8384 { 8385 vmx_pending_event_ipi_fired = true; 8386 eoi(); 8387 } 8388 8389 bool vmx_pending_event_guest_run; 8390 static void vmx_pending_event_guest(void) 8391 { 8392 vmcall(); 8393 vmx_pending_event_guest_run = true; 8394 } 8395 8396 static void vmx_pending_event_test_core(bool guest_hlt) 8397 { 8398 int ipi_vector = 0xf1; 8399 8400 vmx_pending_event_ipi_fired = false; 8401 handle_irq(ipi_vector, vmx_pending_event_ipi_isr); 8402 8403 vmx_pending_event_guest_run = false; 8404 test_set_guest(vmx_pending_event_guest); 8405 8406 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 8407 8408 enter_guest(); 8409 skip_exit_vmcall(); 8410 8411 if (guest_hlt) 8412 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8413 8414 cli(); 8415 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | 8416 APIC_DM_FIXED | ipi_vector, 8417 0); 8418 8419 enter_guest(); 8420 8421 assert_exit_reason(VMX_EXTINT); 8422 report(!vmx_pending_event_guest_run, 8423 "Guest did not run before host received IPI"); 8424 8425 sti_nop_cli(); 8426 report(vmx_pending_event_ipi_fired, 8427 "Got pending interrupt after IRQ enabled"); 8428 8429 if (guest_hlt) 8430 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 8431 8432 enter_guest(); 8433 report(vmx_pending_event_guest_run, 8434 "Guest finished running when no interrupt"); 8435 } 8436 8437 static void vmx_pending_event_test(void) 8438 { 8439 vmx_pending_event_test_core(false); 8440 } 8441 8442 static void vmx_pending_event_hlt_test(void) 8443 { 8444 vmx_pending_event_test_core(true); 8445 } 8446 8447 static int vmx_window_test_db_count; 8448 8449 static void vmx_window_test_db_handler(struct ex_regs *regs) 8450 { 8451 vmx_window_test_db_count++; 8452 } 8453 8454 static void vmx_nmi_window_test_guest(void) 8455 { 8456 handle_exception(DB_VECTOR, vmx_window_test_db_handler); 8457 8458 asm volatile("vmcall\n\t" 8459 "nop\n\t"); 8460 8461 handle_exception(DB_VECTOR, NULL); 8462 } 8463 8464 static void verify_nmi_window_exit(u64 rip) 8465 { 8466 u32 exit_reason = vmcs_read(EXI_REASON); 8467 8468 report(exit_reason == VMX_NMI_WINDOW, 8469 "Exit reason (%d) is 'NMI window'", exit_reason); 8470 report(vmcs_read(GUEST_RIP) == rip, "RIP (%#lx) is %#lx", 8471 vmcs_read(GUEST_RIP), rip); 8472 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 8473 } 8474 8475 static void vmx_nmi_window_test(void) 8476 { 8477 u64 nop_addr; 8478 void *db_fault_addr = get_idt_addr(&boot_idt[DB_VECTOR]); 8479 8480 if (!(ctrl_pin_rev.clr & PIN_VIRT_NMI)) { 8481 report_skip("%s : \"Virtual NMIs\" exec control not supported", __func__); 8482 return; 8483 } 8484 8485 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 8486 report_skip("%s : \"NMI-window exiting\" exec control not supported", __func__); 8487 return; 8488 } 8489 8490 vmx_window_test_db_count = 0; 8491 8492 report_prefix_push("NMI-window"); 8493 test_set_guest(vmx_nmi_window_test_guest); 8494 vmcs_set_bits(PIN_CONTROLS, PIN_VIRT_NMI); 8495 enter_guest(); 8496 skip_exit_vmcall(); 8497 nop_addr = vmcs_read(GUEST_RIP); 8498 8499 /* 8500 * Ask for "NMI-window exiting," and expect an immediate VM-exit. 8501 * RIP will not advance. 8502 */ 8503 report_prefix_push("active, no blocking"); 8504 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 8505 enter_guest(); 8506 verify_nmi_window_exit(nop_addr); 8507 report_prefix_pop(); 8508 8509 /* 8510 * Ask for "NMI-window exiting" in a MOV-SS shadow, and expect 8511 * a VM-exit on the next instruction after the nop. (The nop 8512 * is one byte.) 8513 */ 8514 report_prefix_push("active, blocking by MOV-SS"); 8515 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 8516 enter_guest(); 8517 verify_nmi_window_exit(nop_addr + 1); 8518 report_prefix_pop(); 8519 8520 /* 8521 * Ask for "NMI-window exiting" (with event injection), and 8522 * expect a VM-exit after the event is injected. (RIP should 8523 * be at the address specified in the IDT entry for #DB.) 8524 */ 8525 report_prefix_push("active, no blocking, injecting #DB"); 8526 vmcs_write(ENT_INTR_INFO, 8527 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 8528 enter_guest(); 8529 verify_nmi_window_exit((u64)db_fault_addr); 8530 report_prefix_pop(); 8531 8532 /* 8533 * Ask for "NMI-window exiting" with NMI blocking, and expect 8534 * a VM-exit after the next IRET (i.e. after the #DB handler 8535 * returns). So, RIP should be back at one byte past the nop. 8536 */ 8537 report_prefix_push("active, blocking by NMI"); 8538 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_NMI); 8539 enter_guest(); 8540 verify_nmi_window_exit(nop_addr + 1); 8541 report(vmx_window_test_db_count == 1, 8542 "#DB handler executed once (actual %d times)", 8543 vmx_window_test_db_count); 8544 report_prefix_pop(); 8545 8546 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 8547 report_skip("CPU does not support activity state HLT."); 8548 } else { 8549 /* 8550 * Ask for "NMI-window exiting" when entering activity 8551 * state HLT, and expect an immediate VM-exit. RIP is 8552 * still one byte past the nop. 8553 */ 8554 report_prefix_push("halted, no blocking"); 8555 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8556 enter_guest(); 8557 verify_nmi_window_exit(nop_addr + 1); 8558 report_prefix_pop(); 8559 8560 /* 8561 * Ask for "NMI-window exiting" when entering activity 8562 * state HLT (with event injection), and expect a 8563 * VM-exit after the event is injected. (RIP should be 8564 * at the address specified in the IDT entry for #DB.) 8565 */ 8566 report_prefix_push("halted, no blocking, injecting #DB"); 8567 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8568 vmcs_write(ENT_INTR_INFO, 8569 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 8570 DB_VECTOR); 8571 enter_guest(); 8572 verify_nmi_window_exit((u64)db_fault_addr); 8573 report_prefix_pop(); 8574 } 8575 8576 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 8577 enter_guest(); 8578 report_prefix_pop(); 8579 } 8580 8581 static void vmx_intr_window_test_guest(void) 8582 { 8583 handle_exception(DB_VECTOR, vmx_window_test_db_handler); 8584 8585 /* 8586 * The two consecutive STIs are to ensure that only the first 8587 * one has a shadow. Note that NOP and STI are one byte 8588 * instructions. 8589 */ 8590 asm volatile("vmcall\n\t" 8591 "nop\n\t" 8592 "sti\n\t" 8593 "sti\n\t"); 8594 8595 handle_exception(DB_VECTOR, NULL); 8596 } 8597 8598 static void verify_intr_window_exit(u64 rip) 8599 { 8600 u32 exit_reason = vmcs_read(EXI_REASON); 8601 8602 report(exit_reason == VMX_INTR_WINDOW, 8603 "Exit reason (%d) is 'interrupt window'", exit_reason); 8604 report(vmcs_read(GUEST_RIP) == rip, "RIP (%#lx) is %#lx", 8605 vmcs_read(GUEST_RIP), rip); 8606 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 8607 } 8608 8609 static void vmx_intr_window_test(void) 8610 { 8611 u64 vmcall_addr; 8612 u64 nop_addr; 8613 unsigned int orig_db_gate_type; 8614 void *db_fault_addr = get_idt_addr(&boot_idt[DB_VECTOR]); 8615 8616 if (!(ctrl_cpu_rev[0].clr & CPU_INTR_WINDOW)) { 8617 report_skip("%s : \"Interrupt-window exiting\" exec control not supported", __func__); 8618 return; 8619 } 8620 8621 /* 8622 * Change the IDT entry for #DB from interrupt gate to trap gate, 8623 * so that it won't clear RFLAGS.IF. We don't want interrupts to 8624 * be disabled after vectoring a #DB. 8625 */ 8626 orig_db_gate_type = boot_idt[DB_VECTOR].type; 8627 boot_idt[DB_VECTOR].type = 15; 8628 8629 report_prefix_push("interrupt-window"); 8630 test_set_guest(vmx_intr_window_test_guest); 8631 enter_guest(); 8632 assert_exit_reason(VMX_VMCALL); 8633 vmcall_addr = vmcs_read(GUEST_RIP); 8634 8635 /* 8636 * Ask for "interrupt-window exiting" with RFLAGS.IF set and 8637 * no blocking; expect an immediate VM-exit. Note that we have 8638 * not advanced past the vmcall instruction yet, so RIP should 8639 * point to the vmcall instruction. 8640 */ 8641 report_prefix_push("active, no blocking, RFLAGS.IF=1"); 8642 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8643 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_IF); 8644 enter_guest(); 8645 verify_intr_window_exit(vmcall_addr); 8646 report_prefix_pop(); 8647 8648 /* 8649 * Ask for "interrupt-window exiting" (with event injection) 8650 * with RFLAGS.IF set and no blocking; expect a VM-exit after 8651 * the event is injected. That is, RIP should should be at the 8652 * address specified in the IDT entry for #DB. 8653 */ 8654 report_prefix_push("active, no blocking, RFLAGS.IF=1, injecting #DB"); 8655 vmcs_write(ENT_INTR_INFO, 8656 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 8657 vmcall_addr = vmcs_read(GUEST_RIP); 8658 enter_guest(); 8659 verify_intr_window_exit((u64)db_fault_addr); 8660 report_prefix_pop(); 8661 8662 /* 8663 * Let the L2 guest run through the IRET, back to the VMCALL. 8664 * We have to clear the "interrupt-window exiting" 8665 * VM-execution control, or it would just keep causing 8666 * VM-exits. Then, advance past the VMCALL and set the 8667 * "interrupt-window exiting" VM-execution control again. 8668 */ 8669 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8670 enter_guest(); 8671 skip_exit_vmcall(); 8672 nop_addr = vmcs_read(GUEST_RIP); 8673 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8674 8675 /* 8676 * Ask for "interrupt-window exiting" in a MOV-SS shadow with 8677 * RFLAGS.IF set, and expect a VM-exit on the next 8678 * instruction. (NOP is one byte.) 8679 */ 8680 report_prefix_push("active, blocking by MOV-SS, RFLAGS.IF=1"); 8681 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 8682 enter_guest(); 8683 verify_intr_window_exit(nop_addr + 1); 8684 report_prefix_pop(); 8685 8686 /* 8687 * Back up to the NOP and ask for "interrupt-window exiting" 8688 * in an STI shadow with RFLAGS.IF set, and expect a VM-exit 8689 * on the next instruction. (NOP is one byte.) 8690 */ 8691 report_prefix_push("active, blocking by STI, RFLAGS.IF=1"); 8692 vmcs_write(GUEST_RIP, nop_addr); 8693 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_STI); 8694 enter_guest(); 8695 verify_intr_window_exit(nop_addr + 1); 8696 report_prefix_pop(); 8697 8698 /* 8699 * Ask for "interrupt-window exiting" with RFLAGS.IF clear, 8700 * and expect a VM-exit on the instruction following the STI 8701 * shadow. Only the first STI (which is one byte past the NOP) 8702 * should have a shadow. The second STI (which is two bytes 8703 * past the NOP) has no shadow. Therefore, the interrupt 8704 * window opens at three bytes past the NOP. 8705 */ 8706 report_prefix_push("active, RFLAGS.IF = 0"); 8707 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 8708 enter_guest(); 8709 verify_intr_window_exit(nop_addr + 3); 8710 report_prefix_pop(); 8711 8712 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 8713 report_skip("CPU does not support activity state HLT."); 8714 } else { 8715 /* 8716 * Ask for "interrupt-window exiting" when entering 8717 * activity state HLT, and expect an immediate 8718 * VM-exit. RIP is still three bytes past the nop. 8719 */ 8720 report_prefix_push("halted, no blocking"); 8721 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8722 enter_guest(); 8723 verify_intr_window_exit(nop_addr + 3); 8724 report_prefix_pop(); 8725 8726 /* 8727 * Ask for "interrupt-window exiting" when entering 8728 * activity state HLT (with event injection), and 8729 * expect a VM-exit after the event is injected. That 8730 * is, RIP should should be at the address specified 8731 * in the IDT entry for #DB. 8732 */ 8733 report_prefix_push("halted, no blocking, injecting #DB"); 8734 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8735 vmcs_write(ENT_INTR_INFO, 8736 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 8737 DB_VECTOR); 8738 enter_guest(); 8739 verify_intr_window_exit((u64)db_fault_addr); 8740 report_prefix_pop(); 8741 } 8742 8743 boot_idt[DB_VECTOR].type = orig_db_gate_type; 8744 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8745 enter_guest(); 8746 report_prefix_pop(); 8747 } 8748 8749 #define GUEST_TSC_OFFSET (1u << 30) 8750 8751 static u64 guest_tsc; 8752 8753 static void vmx_store_tsc_test_guest(void) 8754 { 8755 guest_tsc = rdtsc(); 8756 } 8757 8758 /* 8759 * This test ensures that when IA32_TSC is in the VM-exit MSR-store 8760 * list, the value saved is not subject to the TSC offset that is 8761 * applied to RDTSC/RDTSCP/RDMSR(IA32_TSC) in guest execution. 8762 */ 8763 static void vmx_store_tsc_test(void) 8764 { 8765 struct vmx_msr_entry msr_entry = { .index = MSR_IA32_TSC }; 8766 u64 low, high; 8767 8768 if (!(ctrl_cpu_rev[0].clr & CPU_USE_TSC_OFFSET)) { 8769 report_skip("%s : \"Use TSC offsetting\" exec control not supported", __func__); 8770 return; 8771 } 8772 8773 test_set_guest(vmx_store_tsc_test_guest); 8774 8775 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_USE_TSC_OFFSET); 8776 vmcs_write(EXI_MSR_ST_CNT, 1); 8777 vmcs_write(EXIT_MSR_ST_ADDR, virt_to_phys(&msr_entry)); 8778 vmcs_write(TSC_OFFSET, GUEST_TSC_OFFSET); 8779 8780 low = rdtsc(); 8781 enter_guest(); 8782 high = rdtsc(); 8783 8784 report(low + GUEST_TSC_OFFSET <= guest_tsc && 8785 guest_tsc <= high + GUEST_TSC_OFFSET, 8786 "RDTSC value in the guest (%lu) is in range [%lu, %lu]", 8787 guest_tsc, low + GUEST_TSC_OFFSET, high + GUEST_TSC_OFFSET); 8788 report(low <= msr_entry.value && msr_entry.value <= high, 8789 "IA32_TSC value saved in the VM-exit MSR-store list (%lu) is in range [%lu, %lu]", 8790 msr_entry.value, low, high); 8791 } 8792 8793 static void vmx_preemption_timer_zero_test_db_handler(struct ex_regs *regs) 8794 { 8795 } 8796 8797 static void vmx_preemption_timer_zero_test_guest(void) 8798 { 8799 while (vmx_get_test_stage() < 3) 8800 vmcall(); 8801 } 8802 8803 static void vmx_preemption_timer_zero_activate_preemption_timer(void) 8804 { 8805 vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT); 8806 vmcs_write(PREEMPT_TIMER_VALUE, 0); 8807 } 8808 8809 static void vmx_preemption_timer_zero_advance_past_vmcall(void) 8810 { 8811 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 8812 enter_guest(); 8813 skip_exit_vmcall(); 8814 } 8815 8816 static void vmx_preemption_timer_zero_inject_db(bool intercept_db) 8817 { 8818 vmx_preemption_timer_zero_activate_preemption_timer(); 8819 vmcs_write(ENT_INTR_INFO, INTR_INFO_VALID_MASK | 8820 INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 8821 vmcs_write(EXC_BITMAP, intercept_db ? 1 << DB_VECTOR : 0); 8822 enter_guest(); 8823 } 8824 8825 static void vmx_preemption_timer_zero_set_pending_dbg(u32 exception_bitmap) 8826 { 8827 vmx_preemption_timer_zero_activate_preemption_timer(); 8828 vmcs_write(GUEST_PENDING_DEBUG, PENDING_DBG_TRAP | DR6_TRAP1); 8829 vmcs_write(EXC_BITMAP, exception_bitmap); 8830 enter_guest(); 8831 } 8832 8833 static void vmx_preemption_timer_zero_expect_preempt_at_rip(u64 expected_rip) 8834 { 8835 u32 reason = (u32)vmcs_read(EXI_REASON); 8836 u64 guest_rip = vmcs_read(GUEST_RIP); 8837 8838 report(reason == VMX_PREEMPT && guest_rip == expected_rip, 8839 "Exit reason is 0x%x (expected 0x%x) and guest RIP is %lx (0x%lx expected).", 8840 reason, VMX_PREEMPT, guest_rip, expected_rip); 8841 } 8842 8843 /* 8844 * This test ensures that when the VMX preemption timer is zero at 8845 * VM-entry, a VM-exit occurs after any event injection and after any 8846 * pending debug exceptions are raised, but before execution of any 8847 * guest instructions. 8848 */ 8849 static void vmx_preemption_timer_zero_test(void) 8850 { 8851 u64 db_fault_address = (u64)get_idt_addr(&boot_idt[DB_VECTOR]); 8852 handler old_db; 8853 u32 reason; 8854 8855 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 8856 report_skip("%s : \"Activate VMX-preemption timer\" pin control not supported", __func__); 8857 return; 8858 } 8859 8860 /* 8861 * Install a custom #DB handler that doesn't abort. 8862 */ 8863 old_db = handle_exception(DB_VECTOR, 8864 vmx_preemption_timer_zero_test_db_handler); 8865 8866 test_set_guest(vmx_preemption_timer_zero_test_guest); 8867 8868 /* 8869 * VMX-preemption timer should fire after event injection. 8870 */ 8871 vmx_set_test_stage(0); 8872 vmx_preemption_timer_zero_inject_db(0); 8873 vmx_preemption_timer_zero_expect_preempt_at_rip(db_fault_address); 8874 vmx_preemption_timer_zero_advance_past_vmcall(); 8875 8876 /* 8877 * VMX-preemption timer should fire after event injection. 8878 * Exception bitmap is irrelevant, since you can't intercept 8879 * an event that you injected. 8880 */ 8881 vmx_set_test_stage(1); 8882 vmx_preemption_timer_zero_inject_db(true); 8883 vmx_preemption_timer_zero_expect_preempt_at_rip(db_fault_address); 8884 vmx_preemption_timer_zero_advance_past_vmcall(); 8885 8886 /* 8887 * VMX-preemption timer should fire after pending debug exceptions 8888 * have delivered a #DB trap. 8889 */ 8890 vmx_set_test_stage(2); 8891 vmx_preemption_timer_zero_set_pending_dbg(0); 8892 vmx_preemption_timer_zero_expect_preempt_at_rip(db_fault_address); 8893 vmx_preemption_timer_zero_advance_past_vmcall(); 8894 8895 /* 8896 * VMX-preemption timer would fire after pending debug exceptions 8897 * have delivered a #DB trap, but in this case, the #DB trap is 8898 * intercepted. 8899 */ 8900 vmx_set_test_stage(3); 8901 vmx_preemption_timer_zero_set_pending_dbg(1 << DB_VECTOR); 8902 reason = (u32)vmcs_read(EXI_REASON); 8903 report(reason == VMX_EXC_NMI, "Exit reason is 0x%x (expected 0x%x)", 8904 reason, VMX_EXC_NMI); 8905 8906 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 8907 enter_guest(); 8908 8909 handle_exception(DB_VECTOR, old_db); 8910 } 8911 8912 static u64 vmx_preemption_timer_tf_test_prev_rip; 8913 8914 static void vmx_preemption_timer_tf_test_db_handler(struct ex_regs *regs) 8915 { 8916 extern char vmx_preemption_timer_tf_test_endloop; 8917 8918 if (vmx_get_test_stage() == 2) { 8919 /* 8920 * Stage 2 means that we're done, one way or another. 8921 * Arrange for the iret to drop us out of the wbinvd 8922 * loop and stop single-stepping. 8923 */ 8924 regs->rip = (u64)&vmx_preemption_timer_tf_test_endloop; 8925 regs->rflags &= ~X86_EFLAGS_TF; 8926 } else if (regs->rip == vmx_preemption_timer_tf_test_prev_rip) { 8927 /* 8928 * The RIP should alternate between the wbinvd and the 8929 * jmp instruction in the code below. If we ever see 8930 * the same instruction twice in a row, that means a 8931 * single-step trap has been dropped. Let the 8932 * hypervisor know about the failure by executing a 8933 * VMCALL. 8934 */ 8935 vmcall(); 8936 } 8937 vmx_preemption_timer_tf_test_prev_rip = regs->rip; 8938 } 8939 8940 static void vmx_preemption_timer_tf_test_guest(void) 8941 { 8942 /* 8943 * The hypervisor doesn't intercept WBINVD, so the loop below 8944 * shouldn't be a problem--it's just two instructions 8945 * executing in VMX non-root mode. However, when the 8946 * hypervisor is running in a virtual environment, the parent 8947 * hypervisor might intercept WBINVD and emulate it. If the 8948 * parent hypervisor is broken, the single-step trap after the 8949 * WBINVD might be lost. 8950 */ 8951 asm volatile("vmcall\n\t" 8952 "0: wbinvd\n\t" 8953 "1: jmp 0b\n\t" 8954 "vmx_preemption_timer_tf_test_endloop:"); 8955 } 8956 8957 /* 8958 * Ensure that the delivery of a "VMX-preemption timer expired" 8959 * VM-exit doesn't disrupt single-stepping in the guest. Note that 8960 * passing this test doesn't ensure correctness, because the test will 8961 * only fail if the VMX-preemtion timer fires at the right time (or 8962 * the wrong time, as it were). 8963 */ 8964 static void vmx_preemption_timer_tf_test(void) 8965 { 8966 handler old_db; 8967 u32 reason; 8968 int i; 8969 8970 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 8971 report_skip("%s : \"Activate VMX-preemption timer\" pin control not supported", __func__); 8972 return; 8973 } 8974 8975 old_db = handle_exception(DB_VECTOR, 8976 vmx_preemption_timer_tf_test_db_handler); 8977 8978 test_set_guest(vmx_preemption_timer_tf_test_guest); 8979 8980 enter_guest(); 8981 skip_exit_vmcall(); 8982 8983 vmx_set_test_stage(1); 8984 vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT); 8985 vmcs_write(PREEMPT_TIMER_VALUE, 50000); 8986 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_TF); 8987 8988 /* 8989 * The only exit we should see is "VMX-preemption timer 8990 * expired." If we get a VMCALL exit, that means the #DB 8991 * handler has detected a missing single-step trap. It doesn't 8992 * matter where the guest RIP is when the VMX-preemption timer 8993 * expires (whether it's in the WBINVD loop or in the #DB 8994 * handler)--a single-step trap should never be discarded. 8995 */ 8996 for (i = 0; i < 10000; i++) { 8997 enter_guest(); 8998 reason = (u32)vmcs_read(EXI_REASON); 8999 if (reason == VMX_PREEMPT) 9000 continue; 9001 TEST_ASSERT(reason == VMX_VMCALL); 9002 skip_exit_insn(); 9003 break; 9004 } 9005 9006 report(reason == VMX_PREEMPT, "No single-step traps skipped"); 9007 9008 vmx_set_test_stage(2); 9009 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 9010 enter_guest(); 9011 9012 handle_exception(DB_VECTOR, old_db); 9013 } 9014 9015 #define VMX_PREEMPTION_TIMER_EXPIRY_CYCLES 1000000 9016 9017 static u64 vmx_preemption_timer_expiry_start; 9018 static u64 vmx_preemption_timer_expiry_finish; 9019 9020 static void vmx_preemption_timer_expiry_test_guest(void) 9021 { 9022 vmcall(); 9023 vmx_preemption_timer_expiry_start = fenced_rdtsc(); 9024 9025 while (vmx_get_test_stage() == 0) 9026 vmx_preemption_timer_expiry_finish = fenced_rdtsc(); 9027 } 9028 9029 /* 9030 * Test that the VMX-preemption timer is not excessively delayed. 9031 * 9032 * Per the SDM, volume 3, VM-entry starts the VMX-preemption timer 9033 * with the unsigned value in the VMX-preemption timer-value field, 9034 * and the VMX-preemption timer counts down by 1 every time bit X in 9035 * the TSC changes due to a TSC increment (where X is 9036 * IA32_VMX_MISC[4:0]). If the timer counts down to zero in any state 9037 * other than the wait-for-SIPI state, the logical processor 9038 * transitions to the C0 C-state and causes a VM-exit. 9039 * 9040 * The guest code above reads the starting TSC after VM-entry. At this 9041 * point, the VMX-preemption timer has already been activated. Next, 9042 * the guest code reads the current TSC in a loop, storing the value 9043 * read to memory. 9044 * 9045 * If the RDTSC in the loop reads a value past the VMX-preemption 9046 * timer deadline, then the VMX-preemption timer VM-exit must be 9047 * delivered before the next instruction retires. Even if a higher 9048 * priority SMI is delivered first, the VMX-preemption timer VM-exit 9049 * must be delivered before the next instruction retires. Hence, a TSC 9050 * value past the VMX-preemption timer deadline might be read, but it 9051 * cannot be stored. If a TSC value past the deadline *is* stored, 9052 * then the architectural specification has been violated. 9053 */ 9054 static void vmx_preemption_timer_expiry_test(void) 9055 { 9056 u32 preemption_timer_value; 9057 union vmx_misc misc; 9058 u64 tsc_deadline; 9059 u32 reason; 9060 9061 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 9062 report_skip("%s : \"Activate VMX-preemption timer\" pin control not supported", __func__); 9063 return; 9064 } 9065 9066 test_set_guest(vmx_preemption_timer_expiry_test_guest); 9067 9068 enter_guest(); 9069 skip_exit_vmcall(); 9070 9071 misc.val = rdmsr(MSR_IA32_VMX_MISC); 9072 preemption_timer_value = 9073 VMX_PREEMPTION_TIMER_EXPIRY_CYCLES >> misc.pt_bit; 9074 9075 vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT); 9076 vmcs_write(PREEMPT_TIMER_VALUE, preemption_timer_value); 9077 vmx_set_test_stage(0); 9078 9079 enter_guest(); 9080 reason = (u32)vmcs_read(EXI_REASON); 9081 TEST_ASSERT(reason == VMX_PREEMPT); 9082 9083 tsc_deadline = ((vmx_preemption_timer_expiry_start >> misc.pt_bit) << 9084 misc.pt_bit) + (preemption_timer_value << misc.pt_bit); 9085 9086 report(vmx_preemption_timer_expiry_finish < tsc_deadline, 9087 "Last stored guest TSC (%lu) < TSC deadline (%lu)", 9088 vmx_preemption_timer_expiry_finish, tsc_deadline); 9089 9090 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 9091 vmx_set_test_stage(1); 9092 enter_guest(); 9093 } 9094 9095 static void vmx_db_test_guest(void) 9096 { 9097 /* 9098 * For a hardware generated single-step #DB. 9099 */ 9100 asm volatile("vmcall;" 9101 "nop;" 9102 ".Lpost_nop:"); 9103 /* 9104 * ...in a MOVSS shadow, with pending debug exceptions. 9105 */ 9106 asm volatile("vmcall;" 9107 "nop;" 9108 ".Lpost_movss_nop:"); 9109 /* 9110 * For an L0 synthesized single-step #DB. (L0 intercepts WBINVD and 9111 * emulates it in software.) 9112 */ 9113 asm volatile("vmcall;" 9114 "wbinvd;" 9115 ".Lpost_wbinvd:"); 9116 /* 9117 * ...in a MOVSS shadow, with pending debug exceptions. 9118 */ 9119 asm volatile("vmcall;" 9120 "wbinvd;" 9121 ".Lpost_movss_wbinvd:"); 9122 /* 9123 * For a hardware generated single-step #DB in a transactional region. 9124 */ 9125 asm volatile("vmcall;" 9126 ".Lxbegin: xbegin .Lskip_rtm;" 9127 "xend;" 9128 ".Lskip_rtm:"); 9129 } 9130 9131 /* 9132 * Clear the pending debug exceptions and RFLAGS.TF and re-enter 9133 * L2. No #DB is delivered and L2 continues to the next point of 9134 * interest. 9135 */ 9136 static void dismiss_db(void) 9137 { 9138 vmcs_write(GUEST_PENDING_DEBUG, 0); 9139 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 9140 enter_guest(); 9141 } 9142 9143 /* 9144 * Check a variety of VMCS fields relevant to an intercepted #DB exception. 9145 * Then throw away the #DB exception and resume L2. 9146 */ 9147 static void check_db_exit(bool xfail_qual, bool xfail_dr6, bool xfail_pdbg, 9148 void *expected_rip, u64 expected_exit_qual, 9149 u64 expected_dr6) 9150 { 9151 u32 reason = vmcs_read(EXI_REASON); 9152 u32 intr_info = vmcs_read(EXI_INTR_INFO); 9153 u64 exit_qual = vmcs_read(EXI_QUALIFICATION); 9154 u64 guest_rip = vmcs_read(GUEST_RIP); 9155 u64 guest_pending_dbg = vmcs_read(GUEST_PENDING_DEBUG); 9156 u64 dr6 = read_dr6(); 9157 const u32 expected_intr_info = INTR_INFO_VALID_MASK | 9158 INTR_TYPE_HARD_EXCEPTION | DB_VECTOR; 9159 9160 report(reason == VMX_EXC_NMI && intr_info == expected_intr_info, 9161 "Expected #DB VM-exit"); 9162 report((u64)expected_rip == guest_rip, "Expected RIP %p (actual %lx)", 9163 expected_rip, guest_rip); 9164 report_xfail(xfail_pdbg, 0 == guest_pending_dbg, 9165 "Expected pending debug exceptions 0 (actual %lx)", 9166 guest_pending_dbg); 9167 report_xfail(xfail_qual, expected_exit_qual == exit_qual, 9168 "Expected exit qualification %lx (actual %lx)", 9169 expected_exit_qual, exit_qual); 9170 report_xfail(xfail_dr6, expected_dr6 == dr6, 9171 "Expected DR6 %lx (actual %lx)", expected_dr6, dr6); 9172 dismiss_db(); 9173 } 9174 9175 /* 9176 * Assuming the guest has just exited on a VMCALL instruction, skip 9177 * over the vmcall, and set the guest's RFLAGS.TF in the VMCS. If 9178 * pending debug exceptions are non-zero, set the VMCS up as if the 9179 * previous instruction was a MOVSS that generated the indicated 9180 * pending debug exceptions. Then enter L2. 9181 */ 9182 static void single_step_guest(const char *test_name, u64 starting_dr6, 9183 u64 pending_debug_exceptions) 9184 { 9185 printf("\n%s\n", test_name); 9186 skip_exit_vmcall(); 9187 write_dr6(starting_dr6); 9188 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_TF); 9189 if (pending_debug_exceptions) { 9190 vmcs_write(GUEST_PENDING_DEBUG, pending_debug_exceptions); 9191 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 9192 } 9193 enter_guest(); 9194 } 9195 9196 /* 9197 * When L1 intercepts #DB, verify that a single-step trap clears 9198 * pending debug exceptions, populates the exit qualification field 9199 * properly, and that DR6 is not prematurely clobbered. In a 9200 * (simulated) MOVSS shadow, make sure that the pending debug 9201 * exception bits are properly accumulated into the exit qualification 9202 * field. 9203 */ 9204 static void vmx_db_test(void) 9205 { 9206 /* 9207 * We are going to set a few arbitrary bits in DR6 to verify that 9208 * (a) DR6 is not modified by an intercepted #DB, and 9209 * (b) stale bits in DR6 (DR6.BD, in particular) don't leak into 9210 * the exit qualification field for a subsequent #DB exception. 9211 */ 9212 const u64 starting_dr6 = DR6_ACTIVE_LOW | DR6_BS | DR6_TRAP3 | DR6_TRAP1; 9213 extern char post_nop asm(".Lpost_nop"); 9214 extern char post_movss_nop asm(".Lpost_movss_nop"); 9215 extern char post_wbinvd asm(".Lpost_wbinvd"); 9216 extern char post_movss_wbinvd asm(".Lpost_movss_wbinvd"); 9217 extern char xbegin asm(".Lxbegin"); 9218 extern char skip_rtm asm(".Lskip_rtm"); 9219 9220 /* 9221 * L1 wants to intercept #DB exceptions encountered in L2. 9222 */ 9223 vmcs_write(EXC_BITMAP, BIT(DB_VECTOR)); 9224 9225 /* 9226 * Start L2 and run it up to the first point of interest. 9227 */ 9228 test_set_guest(vmx_db_test_guest); 9229 enter_guest(); 9230 9231 /* 9232 * Hardware-delivered #DB trap for single-step sets the 9233 * standard that L0 has to follow for emulated instructions. 9234 */ 9235 single_step_guest("Hardware delivered single-step", starting_dr6, 0); 9236 check_db_exit(false, false, false, &post_nop, DR6_BS, starting_dr6); 9237 9238 /* 9239 * Hardware-delivered #DB trap for single-step in MOVSS shadow 9240 * also sets the standard that L0 has to follow for emulated 9241 * instructions. Here, we establish the VMCS pending debug 9242 * exceptions to indicate that the simulated MOVSS triggered a 9243 * data breakpoint as well as the single-step trap. 9244 */ 9245 single_step_guest("Hardware delivered single-step in MOVSS shadow", 9246 starting_dr6, DR6_BS | PENDING_DBG_TRAP | DR6_TRAP0); 9247 check_db_exit(false, false, false, &post_movss_nop, DR6_BS | DR6_TRAP0, 9248 starting_dr6); 9249 9250 /* 9251 * L0 synthesized #DB trap for single-step is buggy, because 9252 * kvm (a) clobbers DR6 too early, and (b) tries its best to 9253 * reconstitute the exit qualification from the prematurely 9254 * modified DR6, but fails miserably. 9255 */ 9256 single_step_guest("Software synthesized single-step", starting_dr6, 0); 9257 check_db_exit(false, false, false, &post_wbinvd, DR6_BS, starting_dr6); 9258 9259 /* 9260 * L0 synthesized #DB trap for single-step in MOVSS shadow is 9261 * even worse, because L0 also leaves the pending debug 9262 * exceptions in the VMCS instead of accumulating them into 9263 * the exit qualification field for the #DB exception. 9264 */ 9265 single_step_guest("Software synthesized single-step in MOVSS shadow", 9266 starting_dr6, DR6_BS | PENDING_DBG_TRAP | DR6_TRAP0); 9267 check_db_exit(true, false, true, &post_movss_wbinvd, DR6_BS | DR6_TRAP0, 9268 starting_dr6); 9269 9270 /* 9271 * Optional RTM test for hardware that supports RTM, to 9272 * demonstrate that the current volume 3 of the SDM 9273 * (325384-067US), table 27-1 is incorrect. Bit 16 of the exit 9274 * qualification for debug exceptions is not reserved. It is 9275 * set to 1 if a debug exception (#DB) or a breakpoint 9276 * exception (#BP) occurs inside an RTM region while advanced 9277 * debugging of RTM transactional regions is enabled. 9278 */ 9279 if (this_cpu_has(X86_FEATURE_RTM)) { 9280 vmcs_write(ENT_CONTROLS, 9281 vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 9282 /* 9283 * Set DR7.RTM[bit 11] and IA32_DEBUGCTL.RTM[bit 15] 9284 * in the guest to enable advanced debugging of RTM 9285 * transactional regions. 9286 */ 9287 vmcs_write(GUEST_DR7, BIT(11)); 9288 vmcs_write(GUEST_DEBUGCTL, BIT(15)); 9289 single_step_guest("Hardware delivered single-step in " 9290 "transactional region", starting_dr6, 0); 9291 check_db_exit(false, false, false, &xbegin, BIT(16), 9292 starting_dr6); 9293 } else { 9294 vmcs_write(GUEST_RIP, (u64)&skip_rtm); 9295 enter_guest(); 9296 } 9297 } 9298 9299 static void enable_vid(void) 9300 { 9301 void *virtual_apic_page; 9302 9303 assert(cpu_has_apicv()); 9304 9305 disable_intercept_for_x2apic_msrs(); 9306 9307 virtual_apic_page = alloc_page(); 9308 vmcs_write(APIC_VIRT_ADDR, (u64)virtual_apic_page); 9309 9310 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 9311 9312 vmcs_write(EOI_EXIT_BITMAP0, 0x0); 9313 vmcs_write(EOI_EXIT_BITMAP1, 0x0); 9314 vmcs_write(EOI_EXIT_BITMAP2, 0x0); 9315 vmcs_write(EOI_EXIT_BITMAP3, 0x0); 9316 9317 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY | CPU_TPR_SHADOW); 9318 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_VINTD | CPU_VIRT_X2APIC); 9319 } 9320 9321 static void trigger_ioapic_scan_thread(void *data) 9322 { 9323 /* Wait until other CPU entered L2 */ 9324 while (vmx_get_test_stage() != 1) 9325 ; 9326 9327 /* Trigger ioapic scan */ 9328 ioapic_set_redir(0xf, 0x79, TRIGGER_LEVEL); 9329 vmx_set_test_stage(2); 9330 } 9331 9332 static void irq_79_handler_guest(isr_regs_t *regs) 9333 { 9334 eoi(); 9335 9336 /* L1 expects vmexit on VMX_VMCALL and not VMX_EOI_INDUCED */ 9337 vmcall(); 9338 } 9339 9340 /* 9341 * Constant for num of busy-loop iterations after which 9342 * a timer interrupt should have happened in host 9343 */ 9344 #define TIMER_INTERRUPT_DELAY 100000000 9345 9346 static void vmx_eoi_bitmap_ioapic_scan_test_guest(void) 9347 { 9348 handle_irq(0x79, irq_79_handler_guest); 9349 sti(); 9350 9351 /* Signal to L1 CPU to trigger ioapic scan */ 9352 vmx_set_test_stage(1); 9353 /* Wait until L1 CPU to trigger ioapic scan */ 9354 while (vmx_get_test_stage() != 2) 9355 ; 9356 9357 /* 9358 * Wait for L0 timer interrupt to be raised while we run in L2 9359 * such that L0 will process the IOAPIC scan request before 9360 * resuming L2 9361 */ 9362 delay(TIMER_INTERRUPT_DELAY); 9363 9364 asm volatile ("int $0x79"); 9365 } 9366 9367 static void vmx_eoi_bitmap_ioapic_scan_test(void) 9368 { 9369 if (!cpu_has_apicv() || (cpu_count() < 2)) { 9370 report_skip("%s : Not all required APICv bits supported or CPU count < 2", __func__); 9371 return; 9372 } 9373 9374 enable_vid(); 9375 9376 on_cpu_async(1, trigger_ioapic_scan_thread, NULL); 9377 test_set_guest(vmx_eoi_bitmap_ioapic_scan_test_guest); 9378 9379 /* 9380 * Launch L2. 9381 * We expect the exit reason to be VMX_VMCALL (and not EOI INDUCED). 9382 * In case the reason isn't VMX_VMCALL, the assertion inside 9383 * skip_exit_vmcall() will fail. 9384 */ 9385 enter_guest(); 9386 skip_exit_vmcall(); 9387 9388 /* Let L2 finish */ 9389 enter_guest(); 9390 report_pass(__func__); 9391 } 9392 9393 #define HLT_WITH_RVI_VECTOR (0xf1) 9394 9395 bool vmx_hlt_with_rvi_guest_isr_fired; 9396 static void vmx_hlt_with_rvi_guest_isr(isr_regs_t *regs) 9397 { 9398 vmx_hlt_with_rvi_guest_isr_fired = true; 9399 eoi(); 9400 } 9401 9402 static void vmx_hlt_with_rvi_guest(void) 9403 { 9404 handle_irq(HLT_WITH_RVI_VECTOR, vmx_hlt_with_rvi_guest_isr); 9405 9406 sti_nop(); 9407 asm volatile ("nop"); 9408 9409 vmcall(); 9410 } 9411 9412 static void vmx_hlt_with_rvi_test(void) 9413 { 9414 if (!cpu_has_apicv()) { 9415 report_skip("%s : Not all required APICv bits supported", __func__); 9416 return; 9417 } 9418 9419 enable_vid(); 9420 9421 vmx_hlt_with_rvi_guest_isr_fired = false; 9422 test_set_guest(vmx_hlt_with_rvi_guest); 9423 9424 enter_guest(); 9425 skip_exit_vmcall(); 9426 9427 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 9428 vmcs_write(GUEST_INT_STATUS, HLT_WITH_RVI_VECTOR); 9429 enter_guest(); 9430 9431 report(vmx_hlt_with_rvi_guest_isr_fired, "Interrupt raised in guest"); 9432 } 9433 9434 static void set_irq_line_thread(void *data) 9435 { 9436 /* Wait until other CPU entered L2 */ 9437 while (vmx_get_test_stage() != 1) 9438 ; 9439 9440 /* Set irq-line 0xf to raise vector 0x78 for vCPU 0 */ 9441 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 9442 vmx_set_test_stage(2); 9443 } 9444 9445 static bool irq_78_handler_vmcall_before_eoi; 9446 static void irq_78_handler_guest(isr_regs_t *regs) 9447 { 9448 set_irq_line(0xf, 0); 9449 if (irq_78_handler_vmcall_before_eoi) 9450 vmcall(); 9451 eoi(); 9452 vmcall(); 9453 } 9454 9455 static void vmx_apic_passthrough_guest(void) 9456 { 9457 handle_irq(0x78, irq_78_handler_guest); 9458 sti(); 9459 9460 /* If requested, wait for other CPU to trigger ioapic scan */ 9461 if (vmx_get_test_stage() < 1) { 9462 vmx_set_test_stage(1); 9463 while (vmx_get_test_stage() != 2) 9464 ; 9465 } 9466 9467 set_irq_line(0xf, 1); 9468 } 9469 9470 static void vmx_apic_passthrough(bool set_irq_line_from_thread) 9471 { 9472 if (set_irq_line_from_thread && (cpu_count() < 2)) { 9473 report_skip("%s : CPU count < 2", __func__); 9474 return; 9475 } 9476 9477 /* Test device is required for generating IRQs */ 9478 if (!test_device_enabled()) { 9479 report_skip("%s : No test device enabled", __func__); 9480 return; 9481 } 9482 u64 cpu_ctrl_0 = CPU_SECONDARY; 9483 u64 cpu_ctrl_1 = 0; 9484 9485 disable_intercept_for_x2apic_msrs(); 9486 9487 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 9488 9489 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 9490 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 9491 9492 if (set_irq_line_from_thread) { 9493 irq_78_handler_vmcall_before_eoi = false; 9494 on_cpu_async(1, set_irq_line_thread, NULL); 9495 } else { 9496 irq_78_handler_vmcall_before_eoi = true; 9497 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 9498 vmx_set_test_stage(2); 9499 } 9500 test_set_guest(vmx_apic_passthrough_guest); 9501 9502 if (irq_78_handler_vmcall_before_eoi) { 9503 /* Before EOI remote_irr should still be set */ 9504 enter_guest(); 9505 skip_exit_vmcall(); 9506 TEST_ASSERT_EQ_MSG(1, (int)ioapic_read_redir(0xf).remote_irr, 9507 "IOAPIC pass-through: remote_irr=1 before EOI"); 9508 } 9509 9510 /* After EOI remote_irr should be cleared */ 9511 enter_guest(); 9512 skip_exit_vmcall(); 9513 TEST_ASSERT_EQ_MSG(0, (int)ioapic_read_redir(0xf).remote_irr, 9514 "IOAPIC pass-through: remote_irr=0 after EOI"); 9515 9516 /* Let L2 finish */ 9517 enter_guest(); 9518 report_pass(__func__); 9519 } 9520 9521 static void vmx_apic_passthrough_test(void) 9522 { 9523 vmx_apic_passthrough(false); 9524 } 9525 9526 static void vmx_apic_passthrough_thread_test(void) 9527 { 9528 vmx_apic_passthrough(true); 9529 } 9530 9531 static void vmx_apic_passthrough_tpr_threshold_guest(void) 9532 { 9533 cli(); 9534 apic_set_tpr(0); 9535 } 9536 9537 static bool vmx_apic_passthrough_tpr_threshold_ipi_isr_fired; 9538 static void vmx_apic_passthrough_tpr_threshold_ipi_isr(isr_regs_t *regs) 9539 { 9540 vmx_apic_passthrough_tpr_threshold_ipi_isr_fired = true; 9541 eoi(); 9542 } 9543 9544 static void vmx_apic_passthrough_tpr_threshold_test(void) 9545 { 9546 int ipi_vector = 0xe1; 9547 9548 disable_intercept_for_x2apic_msrs(); 9549 vmcs_clear_bits(PIN_CONTROLS, PIN_EXTINT); 9550 9551 /* Raise L0 TPR-threshold by queueing vector in LAPIC IRR */ 9552 cli(); 9553 apic_set_tpr((ipi_vector >> 4) + 1); 9554 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | 9555 APIC_DM_FIXED | ipi_vector, 9556 0); 9557 9558 test_set_guest(vmx_apic_passthrough_tpr_threshold_guest); 9559 enter_guest(); 9560 9561 report(apic_get_tpr() == 0, "TPR was zero by guest"); 9562 9563 /* Clean pending self-IPI */ 9564 vmx_apic_passthrough_tpr_threshold_ipi_isr_fired = false; 9565 handle_irq(ipi_vector, vmx_apic_passthrough_tpr_threshold_ipi_isr); 9566 sti_nop(); 9567 report(vmx_apic_passthrough_tpr_threshold_ipi_isr_fired, "self-IPI fired"); 9568 9569 report_pass(__func__); 9570 } 9571 9572 static u64 init_signal_test_exit_reason; 9573 static bool init_signal_test_thread_continued; 9574 9575 static void init_signal_test_thread(void *data) 9576 { 9577 struct vmcs *test_vmcs = data; 9578 9579 /* Enter VMX operation (i.e. exec VMXON) */ 9580 u64 *ap_vmxon_region = alloc_page(); 9581 enable_vmx(); 9582 init_vmx(ap_vmxon_region); 9583 TEST_ASSERT(!__vmxon_safe(ap_vmxon_region)); 9584 9585 /* Signal CPU have entered VMX operation */ 9586 vmx_set_test_stage(1); 9587 9588 /* Wait for BSP CPU to send INIT signal */ 9589 while (vmx_get_test_stage() != 2) 9590 ; 9591 9592 /* 9593 * Signal that we continue as usual as INIT signal 9594 * should be blocked while CPU is in VMX operation 9595 */ 9596 vmx_set_test_stage(3); 9597 9598 /* Wait for signal to enter VMX non-root mode */ 9599 while (vmx_get_test_stage() != 4) 9600 ; 9601 9602 /* Enter VMX non-root mode */ 9603 test_set_guest(v2_null_test_guest); 9604 make_vmcs_current(test_vmcs); 9605 enter_guest(); 9606 /* Save exit reason for BSP CPU to compare to expected result */ 9607 init_signal_test_exit_reason = vmcs_read(EXI_REASON); 9608 /* VMCLEAR test-vmcs so it could be loaded by BSP CPU */ 9609 vmcs_clear(test_vmcs); 9610 launched = false; 9611 /* Signal that CPU exited to VMX root mode */ 9612 vmx_set_test_stage(5); 9613 9614 /* Wait for BSP CPU to signal to exit VMX operation */ 9615 while (vmx_get_test_stage() != 6) 9616 ; 9617 9618 /* Exit VMX operation (i.e. exec VMXOFF) */ 9619 vmx_off(); 9620 9621 /* 9622 * Signal to BSP CPU that we continue as usual as INIT signal 9623 * should have been consumed by VMX_INIT exit from guest 9624 */ 9625 vmx_set_test_stage(7); 9626 9627 /* Wait for BSP CPU to signal to enter VMX operation */ 9628 while (vmx_get_test_stage() != 8) 9629 ; 9630 /* Enter VMX operation (i.e. exec VMXON) */ 9631 TEST_ASSERT(!__vmxon_safe(ap_vmxon_region)); 9632 /* Signal to BSP we are in VMX operation */ 9633 vmx_set_test_stage(9); 9634 9635 /* Wait for BSP CPU to send INIT signal */ 9636 while (vmx_get_test_stage() != 10) 9637 ; 9638 9639 /* Exit VMX operation (i.e. exec VMXOFF) */ 9640 vmx_off(); 9641 9642 /* 9643 * Exiting VMX operation should result in latched 9644 * INIT signal being processed. Therefore, we should 9645 * never reach the below code. Thus, signal to BSP 9646 * CPU if we have reached here so it is able to 9647 * report an issue if it happens. 9648 */ 9649 init_signal_test_thread_continued = true; 9650 } 9651 9652 #define INIT_SIGNAL_TEST_DELAY 100000000ULL 9653 9654 static void vmx_init_signal_test(void) 9655 { 9656 struct vmcs *test_vmcs; 9657 9658 if (cpu_count() < 2) { 9659 report_skip("%s : CPU count < 2", __func__); 9660 return; 9661 } 9662 9663 /* VMCLEAR test-vmcs so it could be loaded by other CPU */ 9664 vmcs_save(&test_vmcs); 9665 vmcs_clear(test_vmcs); 9666 9667 vmx_set_test_stage(0); 9668 on_cpu_async(1, init_signal_test_thread, test_vmcs); 9669 9670 /* Wait for other CPU to enter VMX operation */ 9671 while (vmx_get_test_stage() != 1) 9672 ; 9673 9674 /* Send INIT signal to other CPU */ 9675 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_INIT | APIC_INT_ASSERT, 9676 id_map[1]); 9677 /* Signal other CPU we have sent INIT signal */ 9678 vmx_set_test_stage(2); 9679 9680 /* 9681 * Wait reasonable amount of time for INIT signal to 9682 * be received on other CPU and verify that other CPU 9683 * have proceed as usual to next test stage as INIT 9684 * signal should be blocked while other CPU in 9685 * VMX operation 9686 */ 9687 delay(INIT_SIGNAL_TEST_DELAY); 9688 report(vmx_get_test_stage() == 3, 9689 "INIT signal blocked when CPU in VMX operation"); 9690 /* No point to continue if we failed at this point */ 9691 if (vmx_get_test_stage() != 3) 9692 return; 9693 9694 /* Signal other CPU to enter VMX non-root mode */ 9695 init_signal_test_exit_reason = -1ull; 9696 vmx_set_test_stage(4); 9697 /* 9698 * Wait reasonable amount of time for other CPU 9699 * to exit to VMX root mode 9700 */ 9701 delay(INIT_SIGNAL_TEST_DELAY); 9702 if (vmx_get_test_stage() != 5) { 9703 report_fail("Pending INIT signal didn't result in VMX exit"); 9704 return; 9705 } 9706 report(init_signal_test_exit_reason == VMX_INIT, 9707 "INIT signal during VMX non-root mode result in exit-reason %s (%lu)", 9708 exit_reason_description(init_signal_test_exit_reason), 9709 init_signal_test_exit_reason); 9710 9711 /* Run guest to completion */ 9712 make_vmcs_current(test_vmcs); 9713 enter_guest(); 9714 9715 /* Signal other CPU to exit VMX operation */ 9716 init_signal_test_thread_continued = false; 9717 vmx_set_test_stage(6); 9718 9719 /* Wait reasonable amount of time for other CPU to exit VMX operation */ 9720 delay(INIT_SIGNAL_TEST_DELAY); 9721 report(vmx_get_test_stage() == 7, 9722 "INIT signal consumed on VMX_INIT exit"); 9723 /* No point to continue if we failed at this point */ 9724 if (vmx_get_test_stage() != 7) 9725 return; 9726 9727 /* Signal other CPU to enter VMX operation */ 9728 vmx_set_test_stage(8); 9729 /* Wait for other CPU to enter VMX operation */ 9730 while (vmx_get_test_stage() != 9) 9731 ; 9732 9733 /* Send INIT signal to other CPU */ 9734 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_INIT | APIC_INT_ASSERT, 9735 id_map[1]); 9736 /* Signal other CPU we have sent INIT signal */ 9737 vmx_set_test_stage(10); 9738 9739 /* 9740 * Wait reasonable amount of time for other CPU 9741 * to exit VMX operation and process INIT signal 9742 */ 9743 delay(INIT_SIGNAL_TEST_DELAY); 9744 report(!init_signal_test_thread_continued, 9745 "INIT signal processed after exit VMX operation"); 9746 9747 /* 9748 * TODO: Send SIPI to other CPU to sipi_entry (See x86/cstart64.S) 9749 * to re-init it to kvm-unit-tests standard environment. 9750 * Somehow (?) verify that SIPI was indeed received. 9751 */ 9752 } 9753 9754 #define SIPI_SIGNAL_TEST_DELAY 100000000ULL 9755 9756 static void vmx_sipi_test_guest(void) 9757 { 9758 if (apic_id() == 0) { 9759 /* wait AP enter guest with activity=WAIT_SIPI */ 9760 while (vmx_get_test_stage() != 1) 9761 ; 9762 delay(SIPI_SIGNAL_TEST_DELAY); 9763 9764 /* First SIPI signal */ 9765 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_STARTUP | APIC_INT_ASSERT, id_map[1]); 9766 report_pass("BSP(L2): Send first SIPI to cpu[%d]", id_map[1]); 9767 9768 /* wait AP enter guest */ 9769 while (vmx_get_test_stage() != 2) 9770 ; 9771 delay(SIPI_SIGNAL_TEST_DELAY); 9772 9773 /* Second SIPI signal should be ignored since AP is not in WAIT_SIPI state */ 9774 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_STARTUP | APIC_INT_ASSERT, id_map[1]); 9775 report_pass("BSP(L2): Send second SIPI to cpu[%d]", id_map[1]); 9776 9777 /* Delay a while to check whether second SIPI would cause VMExit */ 9778 delay(SIPI_SIGNAL_TEST_DELAY); 9779 9780 /* Test is done, notify AP to exit test */ 9781 vmx_set_test_stage(3); 9782 9783 /* wait AP exit non-root mode */ 9784 while (vmx_get_test_stage() != 5) 9785 ; 9786 } else { 9787 /* wait BSP notify test is done */ 9788 while (vmx_get_test_stage() != 3) 9789 ; 9790 9791 /* AP exit guest */ 9792 vmx_set_test_stage(4); 9793 } 9794 } 9795 9796 static void sipi_test_ap_thread(void *data) 9797 { 9798 struct vmcs *ap_vmcs; 9799 u64 *ap_vmxon_region; 9800 void *ap_stack, *ap_syscall_stack; 9801 u64 cpu_ctrl_0 = CPU_SECONDARY; 9802 u64 cpu_ctrl_1 = 0; 9803 9804 /* Enter VMX operation (i.e. exec VMXON) */ 9805 ap_vmxon_region = alloc_page(); 9806 enable_vmx(); 9807 init_vmx(ap_vmxon_region); 9808 TEST_ASSERT(!__vmxon_safe(ap_vmxon_region)); 9809 init_vmcs(&ap_vmcs); 9810 make_vmcs_current(ap_vmcs); 9811 9812 /* Set stack for AP */ 9813 ap_stack = alloc_page(); 9814 ap_syscall_stack = alloc_page(); 9815 vmcs_write(GUEST_RSP, (u64)(ap_stack + PAGE_SIZE - 1)); 9816 vmcs_write(GUEST_SYSENTER_ESP, (u64)(ap_syscall_stack + PAGE_SIZE - 1)); 9817 9818 /* passthrough lapic to L2 */ 9819 disable_intercept_for_x2apic_msrs(); 9820 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 9821 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 9822 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 9823 9824 /* Set guest activity state to wait-for-SIPI state */ 9825 vmcs_write(GUEST_ACTV_STATE, ACTV_WAIT_SIPI); 9826 9827 vmx_set_test_stage(1); 9828 9829 /* AP enter guest */ 9830 enter_guest(); 9831 9832 if (vmcs_read(EXI_REASON) == VMX_SIPI) { 9833 report_pass("AP: Handle SIPI VMExit"); 9834 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 9835 vmx_set_test_stage(2); 9836 } else { 9837 report_fail("AP: Unexpected VMExit, reason=%ld", vmcs_read(EXI_REASON)); 9838 vmx_off(); 9839 return; 9840 } 9841 9842 /* AP enter guest */ 9843 enter_guest(); 9844 9845 report(vmcs_read(EXI_REASON) != VMX_SIPI, 9846 "AP: should no SIPI VMExit since activity is not in WAIT_SIPI state"); 9847 9848 /* notify BSP that AP is already exit from non-root mode */ 9849 vmx_set_test_stage(5); 9850 9851 /* Leave VMX operation */ 9852 vmx_off(); 9853 } 9854 9855 static void vmx_sipi_signal_test(void) 9856 { 9857 if (!(rdmsr(MSR_IA32_VMX_MISC) & MSR_IA32_VMX_MISC_ACTIVITY_WAIT_SIPI)) { 9858 report_skip("%s : \"ACTIVITY_WAIT_SIPI state\" not supported", __func__); 9859 return; 9860 } 9861 9862 if (cpu_count() < 2) { 9863 report_skip("%s : CPU count < 2", __func__); 9864 return; 9865 } 9866 9867 u64 cpu_ctrl_0 = CPU_SECONDARY; 9868 u64 cpu_ctrl_1 = 0; 9869 9870 /* passthrough lapic to L2 */ 9871 disable_intercept_for_x2apic_msrs(); 9872 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 9873 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 9874 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 9875 9876 test_set_guest(vmx_sipi_test_guest); 9877 9878 /* update CR3 on AP */ 9879 on_cpu(1, update_cr3, (void *)read_cr3()); 9880 9881 /* start AP */ 9882 on_cpu_async(1, sipi_test_ap_thread, NULL); 9883 9884 vmx_set_test_stage(0); 9885 9886 /* BSP enter guest */ 9887 enter_guest(); 9888 } 9889 9890 9891 enum vmcs_access { 9892 ACCESS_VMREAD, 9893 ACCESS_VMWRITE, 9894 ACCESS_NONE, 9895 }; 9896 9897 struct vmcs_shadow_test_common { 9898 enum vmcs_access op; 9899 enum Reason reason; 9900 u64 field; 9901 u64 value; 9902 u64 flags; 9903 u64 time; 9904 } l1_l2_common; 9905 9906 static inline u64 vmread_flags(u64 field, u64 *val) 9907 { 9908 u64 flags; 9909 9910 asm volatile ("vmread %2, %1; pushf; pop %0" 9911 : "=r" (flags), "=rm" (*val) : "r" (field) : "cc"); 9912 return flags & X86_EFLAGS_ALU; 9913 } 9914 9915 static inline u64 vmwrite_flags(u64 field, u64 val) 9916 { 9917 u64 flags; 9918 9919 asm volatile ("vmwrite %1, %2; pushf; pop %0" 9920 : "=r"(flags) : "rm" (val), "r" (field) : "cc"); 9921 return flags & X86_EFLAGS_ALU; 9922 } 9923 9924 static void vmx_vmcs_shadow_test_guest(void) 9925 { 9926 struct vmcs_shadow_test_common *c = &l1_l2_common; 9927 u64 start; 9928 9929 while (c->op != ACCESS_NONE) { 9930 start = rdtsc(); 9931 switch (c->op) { 9932 default: 9933 c->flags = -1ull; 9934 break; 9935 case ACCESS_VMREAD: 9936 c->flags = vmread_flags(c->field, &c->value); 9937 break; 9938 case ACCESS_VMWRITE: 9939 c->flags = vmwrite_flags(c->field, 0); 9940 break; 9941 } 9942 c->time = rdtsc() - start; 9943 vmcall(); 9944 } 9945 } 9946 9947 static u64 vmread_from_shadow(u64 field) 9948 { 9949 struct vmcs *primary; 9950 struct vmcs *shadow; 9951 u64 value; 9952 9953 TEST_ASSERT(!vmcs_save(&primary)); 9954 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 9955 TEST_ASSERT(!make_vmcs_current(shadow)); 9956 value = vmcs_read(field); 9957 TEST_ASSERT(!make_vmcs_current(primary)); 9958 return value; 9959 } 9960 9961 static u64 vmwrite_to_shadow(u64 field, u64 value) 9962 { 9963 struct vmcs *primary; 9964 struct vmcs *shadow; 9965 9966 TEST_ASSERT(!vmcs_save(&primary)); 9967 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 9968 TEST_ASSERT(!make_vmcs_current(shadow)); 9969 vmcs_write(field, value); 9970 value = vmcs_read(field); 9971 TEST_ASSERT(!make_vmcs_current(primary)); 9972 return value; 9973 } 9974 9975 static void vmcs_shadow_test_access(u8 *bitmap[2], enum vmcs_access access) 9976 { 9977 struct vmcs_shadow_test_common *c = &l1_l2_common; 9978 9979 c->op = access; 9980 vmcs_write(VMX_INST_ERROR, 0); 9981 enter_guest(); 9982 c->reason = vmcs_read(EXI_REASON) & 0xffff; 9983 if (c->reason != VMX_VMCALL) { 9984 skip_exit_insn(); 9985 enter_guest(); 9986 } 9987 skip_exit_vmcall(); 9988 } 9989 9990 static void vmcs_shadow_test_field(u8 *bitmap[2], u64 field) 9991 { 9992 struct vmcs_shadow_test_common *c = &l1_l2_common; 9993 struct vmcs *shadow; 9994 u64 value; 9995 uintptr_t flags[2]; 9996 bool good_shadow; 9997 u32 vmx_inst_error; 9998 9999 report_prefix_pushf("field %lx", field); 10000 c->field = field; 10001 10002 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 10003 if (shadow != (struct vmcs *)-1ull) { 10004 flags[ACCESS_VMREAD] = vmread_flags(field, &value); 10005 flags[ACCESS_VMWRITE] = vmwrite_flags(field, value); 10006 good_shadow = !flags[ACCESS_VMREAD] && !flags[ACCESS_VMWRITE]; 10007 } else { 10008 /* 10009 * When VMCS link pointer is -1ull, VMWRITE/VMREAD on 10010 * shadowed-fields should fail with setting RFLAGS.CF. 10011 */ 10012 flags[ACCESS_VMREAD] = X86_EFLAGS_CF; 10013 flags[ACCESS_VMWRITE] = X86_EFLAGS_CF; 10014 good_shadow = false; 10015 } 10016 10017 /* Intercept both VMREAD and VMWRITE. */ 10018 report_prefix_push("no VMREAD/VMWRITE permission"); 10019 /* VMWRITE/VMREAD done on reserved-bit should always intercept */ 10020 if (!(field >> VMCS_FIELD_RESERVED_SHIFT)) { 10021 set_bit(field, bitmap[ACCESS_VMREAD]); 10022 set_bit(field, bitmap[ACCESS_VMWRITE]); 10023 } 10024 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10025 report(c->reason == VMX_VMWRITE, "not shadowed for VMWRITE"); 10026 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10027 report(c->reason == VMX_VMREAD, "not shadowed for VMREAD"); 10028 report_prefix_pop(); 10029 10030 if (field >> VMCS_FIELD_RESERVED_SHIFT) 10031 goto out; 10032 10033 /* Permit shadowed VMREAD. */ 10034 report_prefix_push("VMREAD permission only"); 10035 clear_bit(field, bitmap[ACCESS_VMREAD]); 10036 set_bit(field, bitmap[ACCESS_VMWRITE]); 10037 if (good_shadow) 10038 value = vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 10039 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10040 report(c->reason == VMX_VMWRITE, "not shadowed for VMWRITE"); 10041 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10042 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10043 report(c->reason == VMX_VMCALL, "shadowed for VMREAD (in %ld cycles)", 10044 c->time); 10045 report(c->flags == flags[ACCESS_VMREAD], 10046 "ALU flags after VMREAD (%lx) are as expected (%lx)", 10047 c->flags, flags[ACCESS_VMREAD]); 10048 if (good_shadow) 10049 report(c->value == value, 10050 "value read from shadow (%lx) is as expected (%lx)", 10051 c->value, value); 10052 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 10053 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10054 "VMX_INST_ERROR (%d) is as expected (%d)", 10055 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10056 report_prefix_pop(); 10057 10058 /* Permit shadowed VMWRITE. */ 10059 report_prefix_push("VMWRITE permission only"); 10060 set_bit(field, bitmap[ACCESS_VMREAD]); 10061 clear_bit(field, bitmap[ACCESS_VMWRITE]); 10062 if (good_shadow) 10063 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 10064 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10065 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10066 report(c->reason == VMX_VMCALL, 10067 "shadowed for VMWRITE (in %ld cycles)", 10068 c->time); 10069 report(c->flags == flags[ACCESS_VMREAD], 10070 "ALU flags after VMWRITE (%lx) are as expected (%lx)", 10071 c->flags, flags[ACCESS_VMREAD]); 10072 if (good_shadow) { 10073 value = vmread_from_shadow(field); 10074 report(value == 0, 10075 "shadow VMCS value (%lx) is as expected (%lx)", value, 10076 0ul); 10077 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 10078 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10079 "VMX_INST_ERROR (%d) is as expected (%d)", 10080 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10081 } 10082 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10083 report(c->reason == VMX_VMREAD, "not shadowed for VMREAD"); 10084 report_prefix_pop(); 10085 10086 /* Permit shadowed VMREAD and VMWRITE. */ 10087 report_prefix_push("VMREAD and VMWRITE permission"); 10088 clear_bit(field, bitmap[ACCESS_VMREAD]); 10089 clear_bit(field, bitmap[ACCESS_VMWRITE]); 10090 if (good_shadow) 10091 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 10092 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10093 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10094 report(c->reason == VMX_VMCALL, 10095 "shadowed for VMWRITE (in %ld cycles)", 10096 c->time); 10097 report(c->flags == flags[ACCESS_VMREAD], 10098 "ALU flags after VMWRITE (%lx) are as expected (%lx)", 10099 c->flags, flags[ACCESS_VMREAD]); 10100 if (good_shadow) { 10101 value = vmread_from_shadow(field); 10102 report(value == 0, 10103 "shadow VMCS value (%lx) is as expected (%lx)", value, 10104 0ul); 10105 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 10106 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10107 "VMX_INST_ERROR (%d) is as expected (%d)", 10108 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10109 } 10110 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10111 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10112 report(c->reason == VMX_VMCALL, "shadowed for VMREAD (in %ld cycles)", 10113 c->time); 10114 report(c->flags == flags[ACCESS_VMREAD], 10115 "ALU flags after VMREAD (%lx) are as expected (%lx)", 10116 c->flags, flags[ACCESS_VMREAD]); 10117 if (good_shadow) 10118 report(c->value == 0, 10119 "value read from shadow (%lx) is as expected (%lx)", 10120 c->value, 0ul); 10121 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 10122 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10123 "VMX_INST_ERROR (%d) is as expected (%d)", 10124 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10125 report_prefix_pop(); 10126 10127 out: 10128 report_prefix_pop(); 10129 } 10130 10131 static void vmx_vmcs_shadow_test_body(u8 *bitmap[2]) 10132 { 10133 unsigned base; 10134 unsigned index; 10135 unsigned bit; 10136 unsigned highest_index = rdmsr(MSR_IA32_VMX_VMCS_ENUM); 10137 10138 /* Run test on all possible valid VMCS fields */ 10139 for (base = 0; 10140 base < (1 << VMCS_FIELD_RESERVED_SHIFT); 10141 base += (1 << VMCS_FIELD_TYPE_SHIFT)) 10142 for (index = 0; index <= highest_index; index++) 10143 vmcs_shadow_test_field(bitmap, base + index); 10144 10145 /* 10146 * Run tests on some invalid VMCS fields 10147 * (Have reserved bit set). 10148 */ 10149 for (bit = VMCS_FIELD_RESERVED_SHIFT; bit < VMCS_FIELD_BIT_SIZE; bit++) 10150 vmcs_shadow_test_field(bitmap, (1ull << bit)); 10151 } 10152 10153 static void vmx_vmcs_shadow_test(void) 10154 { 10155 u8 *bitmap[2]; 10156 struct vmcs *shadow; 10157 10158 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 10159 report_skip("%s : \"Activate secondary controls\" not supported", __func__); 10160 return; 10161 } 10162 10163 if (!(ctrl_cpu_rev[1].clr & CPU_SHADOW_VMCS)) { 10164 report_skip("%s : \"VMCS shadowing\" not supported", __func__); 10165 return; 10166 } 10167 10168 if (!(rdmsr(MSR_IA32_VMX_MISC) & 10169 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS)) { 10170 report_skip("%s : VMWRITE can't modify VM-exit information fields.", __func__); 10171 return; 10172 } 10173 10174 test_set_guest(vmx_vmcs_shadow_test_guest); 10175 10176 bitmap[ACCESS_VMREAD] = alloc_page(); 10177 bitmap[ACCESS_VMWRITE] = alloc_page(); 10178 10179 vmcs_write(VMREAD_BITMAP, virt_to_phys(bitmap[ACCESS_VMREAD])); 10180 vmcs_write(VMWRITE_BITMAP, virt_to_phys(bitmap[ACCESS_VMWRITE])); 10181 10182 shadow = alloc_page(); 10183 shadow->hdr.revision_id = basic.revision; 10184 shadow->hdr.shadow_vmcs = 1; 10185 TEST_ASSERT(!vmcs_clear(shadow)); 10186 10187 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_RDTSC); 10188 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY); 10189 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_SHADOW_VMCS); 10190 10191 vmcs_write(VMCS_LINK_PTR, virt_to_phys(shadow)); 10192 report_prefix_push("valid link pointer"); 10193 vmx_vmcs_shadow_test_body(bitmap); 10194 report_prefix_pop(); 10195 10196 vmcs_write(VMCS_LINK_PTR, -1ull); 10197 report_prefix_push("invalid link pointer"); 10198 vmx_vmcs_shadow_test_body(bitmap); 10199 report_prefix_pop(); 10200 10201 l1_l2_common.op = ACCESS_NONE; 10202 enter_guest(); 10203 } 10204 10205 /* 10206 * This test monitors the difference between a guest RDTSC instruction 10207 * and the IA32_TIME_STAMP_COUNTER MSR value stored in the VMCS12 10208 * VM-exit MSR-store list when taking a VM-exit on the instruction 10209 * following RDTSC. 10210 */ 10211 #define RDTSC_DIFF_ITERS 100000 10212 #define RDTSC_DIFF_FAILS 100 10213 #define HOST_CAPTURED_GUEST_TSC_DIFF_THRESHOLD 750 10214 10215 /* 10216 * Set 'use TSC offsetting' and set the guest offset to the 10217 * inverse of the host's current TSC value, so that the guest starts running 10218 * with an effective TSC value of 0. 10219 */ 10220 static void reset_guest_tsc_to_zero(void) 10221 { 10222 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_USE_TSC_OFFSET); 10223 vmcs_write(TSC_OFFSET, -rdtsc()); 10224 } 10225 10226 static void rdtsc_vmexit_diff_test_guest(void) 10227 { 10228 int i; 10229 10230 for (i = 0; i < RDTSC_DIFF_ITERS; i++) 10231 /* Ensure rdtsc is the last instruction before the vmcall. */ 10232 asm volatile("rdtsc; vmcall" : : : "eax", "edx"); 10233 } 10234 10235 /* 10236 * This function only considers the "use TSC offsetting" VM-execution 10237 * control. It does not handle "use TSC scaling" (because the latter 10238 * isn't available to the host today.) 10239 */ 10240 static unsigned long long host_time_to_guest_time(unsigned long long t) 10241 { 10242 TEST_ASSERT(!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 10243 !(vmcs_read(CPU_EXEC_CTRL1) & CPU_USE_TSC_SCALING)); 10244 10245 if (vmcs_read(CPU_EXEC_CTRL0) & CPU_USE_TSC_OFFSET) 10246 t += vmcs_read(TSC_OFFSET); 10247 10248 return t; 10249 } 10250 10251 static unsigned long long rdtsc_vmexit_diff_test_iteration(void) 10252 { 10253 unsigned long long guest_tsc, host_to_guest_tsc; 10254 10255 enter_guest(); 10256 skip_exit_vmcall(); 10257 guest_tsc = (u32) regs.rax + (regs.rdx << 32); 10258 host_to_guest_tsc = host_time_to_guest_time(exit_msr_store[0].value); 10259 10260 return host_to_guest_tsc - guest_tsc; 10261 } 10262 10263 static void rdtsc_vmexit_diff_test(void) 10264 { 10265 unsigned long long delta; 10266 int fail = 0; 10267 int i; 10268 10269 if (!(ctrl_cpu_rev[0].clr & CPU_USE_TSC_OFFSET)) 10270 test_skip("CPU doesn't support the 'use TSC offsetting' processor-based VM-execution control.\n"); 10271 10272 test_set_guest(rdtsc_vmexit_diff_test_guest); 10273 10274 reset_guest_tsc_to_zero(); 10275 10276 /* 10277 * Set up the VMCS12 VM-exit MSR-store list to store just one 10278 * MSR: IA32_TIME_STAMP_COUNTER. Note that the value stored is 10279 * in the host time domain (i.e., it is not adjusted according 10280 * to the TSC multiplier and TSC offset fields in the VMCS12, 10281 * as a guest RDTSC would be.) 10282 */ 10283 exit_msr_store = alloc_page(); 10284 exit_msr_store[0].index = MSR_IA32_TSC; 10285 vmcs_write(EXI_MSR_ST_CNT, 1); 10286 vmcs_write(EXIT_MSR_ST_ADDR, virt_to_phys(exit_msr_store)); 10287 10288 for (i = 0; i < RDTSC_DIFF_ITERS && fail < RDTSC_DIFF_FAILS; i++) { 10289 delta = rdtsc_vmexit_diff_test_iteration(); 10290 if (delta >= HOST_CAPTURED_GUEST_TSC_DIFF_THRESHOLD) 10291 fail++; 10292 } 10293 10294 enter_guest(); 10295 10296 report(fail < RDTSC_DIFF_FAILS, 10297 "RDTSC to VM-exit delta too high in %d of %d iterations, last = %llu", 10298 fail, i, delta); 10299 } 10300 10301 static int invalid_msr_init(struct vmcs *vmcs) 10302 { 10303 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 10304 printf("\tPreemption timer is not supported\n"); 10305 return VMX_TEST_EXIT; 10306 } 10307 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 10308 preempt_val = 10000000; 10309 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 10310 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 10311 10312 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 10313 printf("\tSave preemption value is not supported\n"); 10314 10315 vmcs_write(ENT_MSR_LD_CNT, 1); 10316 vmcs_write(ENTER_MSR_LD_ADDR, (u64)0x13370000); 10317 10318 return VMX_TEST_START; 10319 } 10320 10321 10322 static void invalid_msr_main(void) 10323 { 10324 report_fail("Invalid MSR load"); 10325 } 10326 10327 static int invalid_msr_exit_handler(union exit_reason exit_reason) 10328 { 10329 report_fail("Invalid MSR load"); 10330 print_vmexit_info(exit_reason); 10331 return VMX_TEST_EXIT; 10332 } 10333 10334 static int invalid_msr_entry_failure(struct vmentry_result *result) 10335 { 10336 report(result->exit_reason.failed_vmentry && 10337 result->exit_reason.basic == VMX_FAIL_MSR, "Invalid MSR load"); 10338 return VMX_TEST_VMEXIT; 10339 } 10340 10341 /* 10342 * The max number of MSRs in an atomic switch MSR list is: 10343 * (111B + 1) * 512 = 4096 10344 * 10345 * Each list entry consumes: 10346 * 4-byte MSR index + 4 bytes reserved + 8-byte data = 16 bytes 10347 * 10348 * Allocate 128 kB to cover max_msr_list_size (i.e., 64 kB) and then some. 10349 */ 10350 static const u32 msr_list_page_order = 5; 10351 10352 static void atomic_switch_msr_limit_test_guest(void) 10353 { 10354 vmcall(); 10355 } 10356 10357 static void populate_msr_list(struct vmx_msr_entry *msr_list, 10358 size_t byte_capacity, int count) 10359 { 10360 int i; 10361 10362 for (i = 0; i < count; i++) { 10363 msr_list[i].index = MSR_IA32_TSC; 10364 msr_list[i].reserved = 0; 10365 msr_list[i].value = 0x1234567890abcdef; 10366 } 10367 10368 memset(msr_list + count, 0xff, 10369 byte_capacity - count * sizeof(*msr_list)); 10370 } 10371 10372 static int max_msr_list_size(void) 10373 { 10374 u32 vmx_misc = rdmsr(MSR_IA32_VMX_MISC); 10375 u32 factor = ((vmx_misc & GENMASK(27, 25)) >> 25) + 1; 10376 10377 return factor * 512; 10378 } 10379 10380 static void atomic_switch_msrs_test(int count) 10381 { 10382 struct vmx_msr_entry *vm_enter_load; 10383 struct vmx_msr_entry *vm_exit_load; 10384 struct vmx_msr_entry *vm_exit_store; 10385 int max_allowed = max_msr_list_size(); 10386 int byte_capacity = 1ul << (msr_list_page_order + PAGE_SHIFT); 10387 /* Exceeding the max MSR list size at exit triggers KVM to abort. */ 10388 int exit_count = count > max_allowed ? max_allowed : count; 10389 int cleanup_count = count > max_allowed ? 2 : 1; 10390 int i; 10391 10392 /* 10393 * Check for the IA32_TSC MSR, 10394 * available with the "TSC flag" and used to populate the MSR lists. 10395 */ 10396 if (!(cpuid(1).d & (1 << 4))) { 10397 report_skip("%s : \"Time Stamp Counter\" not supported", __func__); 10398 return; 10399 } 10400 10401 /* Set L2 guest. */ 10402 test_set_guest(atomic_switch_msr_limit_test_guest); 10403 10404 /* Setup atomic MSR switch lists. */ 10405 vm_enter_load = alloc_pages(msr_list_page_order); 10406 vm_exit_load = alloc_pages(msr_list_page_order); 10407 vm_exit_store = alloc_pages(msr_list_page_order); 10408 10409 vmcs_write(ENTER_MSR_LD_ADDR, (u64)vm_enter_load); 10410 vmcs_write(EXIT_MSR_LD_ADDR, (u64)vm_exit_load); 10411 vmcs_write(EXIT_MSR_ST_ADDR, (u64)vm_exit_store); 10412 10413 /* 10414 * VM-Enter should succeed up to the max number of MSRs per list, and 10415 * should not consume junk beyond the last entry. 10416 */ 10417 populate_msr_list(vm_enter_load, byte_capacity, count); 10418 populate_msr_list(vm_exit_load, byte_capacity, exit_count); 10419 populate_msr_list(vm_exit_store, byte_capacity, exit_count); 10420 10421 vmcs_write(ENT_MSR_LD_CNT, count); 10422 vmcs_write(EXI_MSR_LD_CNT, exit_count); 10423 vmcs_write(EXI_MSR_ST_CNT, exit_count); 10424 10425 if (count <= max_allowed) { 10426 enter_guest(); 10427 assert_exit_reason(VMX_VMCALL); 10428 skip_exit_vmcall(); 10429 } else { 10430 u32 exit_qual; 10431 10432 test_guest_state("Invalid MSR Load Count", true, count, 10433 "ENT_MSR_LD_CNT"); 10434 10435 exit_qual = vmcs_read(EXI_QUALIFICATION); 10436 report(exit_qual == max_allowed + 1, "exit_qual, %u, is %u.", 10437 exit_qual, max_allowed + 1); 10438 } 10439 10440 /* Cleanup. */ 10441 vmcs_write(ENT_MSR_LD_CNT, 0); 10442 vmcs_write(EXI_MSR_LD_CNT, 0); 10443 vmcs_write(EXI_MSR_ST_CNT, 0); 10444 for (i = 0; i < cleanup_count; i++) { 10445 enter_guest(); 10446 skip_exit_vmcall(); 10447 } 10448 free_pages_by_order(vm_enter_load, msr_list_page_order); 10449 free_pages_by_order(vm_exit_load, msr_list_page_order); 10450 free_pages_by_order(vm_exit_store, msr_list_page_order); 10451 } 10452 10453 static void atomic_switch_max_msrs_test(void) 10454 { 10455 atomic_switch_msrs_test(max_msr_list_size()); 10456 } 10457 10458 static void atomic_switch_overflow_msrs_test(void) 10459 { 10460 if (test_device_enabled()) 10461 atomic_switch_msrs_test(max_msr_list_size() + 1); 10462 else 10463 test_skip("Test is only supported on KVM"); 10464 } 10465 10466 static void vmx_pf_exception_test_guest(void) 10467 { 10468 ac_test_run(PT_LEVEL_PML4, false); 10469 } 10470 10471 static void vmx_pf_exception_forced_emulation_test_guest(void) 10472 { 10473 ac_test_run(PT_LEVEL_PML4, true); 10474 } 10475 10476 typedef void (*invalidate_tlb_t)(void *data); 10477 typedef void (*pf_exception_test_guest_t)(void); 10478 10479 10480 static void __vmx_pf_exception_test(invalidate_tlb_t inv_fn, void *data, 10481 pf_exception_test_guest_t guest_fn) 10482 { 10483 u64 efer; 10484 struct cpuid cpuid; 10485 10486 test_set_guest(guest_fn); 10487 10488 /* Intercept INVLPG when to perform TLB invalidation from L1 (this). */ 10489 if (inv_fn) 10490 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INVLPG); 10491 else 10492 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INVLPG); 10493 10494 enter_guest(); 10495 10496 while (vmcs_read(EXI_REASON) != VMX_VMCALL) { 10497 switch (vmcs_read(EXI_REASON)) { 10498 case VMX_RDMSR: 10499 assert(regs.rcx == MSR_EFER); 10500 efer = vmcs_read(GUEST_EFER); 10501 regs.rdx = efer >> 32; 10502 regs.rax = efer & 0xffffffff; 10503 break; 10504 case VMX_WRMSR: 10505 assert(regs.rcx == MSR_EFER); 10506 efer = regs.rdx << 32 | (regs.rax & 0xffffffff); 10507 vmcs_write(GUEST_EFER, efer); 10508 break; 10509 case VMX_CPUID: 10510 cpuid = (struct cpuid) {0, 0, 0, 0}; 10511 cpuid = raw_cpuid(regs.rax, regs.rcx); 10512 regs.rax = cpuid.a; 10513 regs.rbx = cpuid.b; 10514 regs.rcx = cpuid.c; 10515 regs.rdx = cpuid.d; 10516 break; 10517 case VMX_INVLPG: 10518 inv_fn(data); 10519 break; 10520 default: 10521 assert_msg(false, 10522 "Unexpected exit to L1, exit_reason: %s (0x%lx)", 10523 exit_reason_description(vmcs_read(EXI_REASON)), 10524 vmcs_read(EXI_REASON)); 10525 } 10526 skip_exit_insn(); 10527 enter_guest(); 10528 } 10529 10530 assert_exit_reason(VMX_VMCALL); 10531 } 10532 10533 static void vmx_pf_exception_test(void) 10534 { 10535 __vmx_pf_exception_test(NULL, NULL, vmx_pf_exception_test_guest); 10536 } 10537 10538 static void vmx_pf_exception_forced_emulation_test(void) 10539 { 10540 __vmx_pf_exception_test(NULL, NULL, vmx_pf_exception_forced_emulation_test_guest); 10541 } 10542 10543 static void invalidate_tlb_no_vpid(void *data) 10544 { 10545 /* If VPID is disabled, the TLB is flushed on VM-Enter and VM-Exit. */ 10546 } 10547 10548 static void vmx_pf_no_vpid_test(void) 10549 { 10550 if (is_vpid_supported()) 10551 vmcs_clear_bits(CPU_EXEC_CTRL1, CPU_VPID); 10552 10553 __vmx_pf_exception_test(invalidate_tlb_no_vpid, NULL, 10554 vmx_pf_exception_test_guest); 10555 } 10556 10557 static void invalidate_tlb_invvpid_addr(void *data) 10558 { 10559 invvpid(INVVPID_ALL, *(u16 *)data, vmcs_read(EXI_QUALIFICATION)); 10560 } 10561 10562 static void invalidate_tlb_new_vpid(void *data) 10563 { 10564 u16 *vpid = data; 10565 10566 /* 10567 * Bump VPID to effectively flush L2's TLB from L0's perspective. 10568 * Invalidate all VPIDs when the VPID wraps to zero as hardware/KVM is 10569 * architecturally allowed to keep TLB entries indefinitely. 10570 */ 10571 ++(*vpid); 10572 if (*vpid == 0) { 10573 ++(*vpid); 10574 invvpid(INVVPID_ALL, 0, 0); 10575 } 10576 vmcs_write(VPID, *vpid); 10577 } 10578 10579 static void __vmx_pf_vpid_test(invalidate_tlb_t inv_fn, u16 vpid) 10580 { 10581 if (!is_vpid_supported()) 10582 test_skip("VPID unsupported"); 10583 10584 if (!is_invvpid_supported()) 10585 test_skip("INVVPID unsupported"); 10586 10587 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY); 10588 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_VPID); 10589 vmcs_write(VPID, vpid); 10590 10591 __vmx_pf_exception_test(inv_fn, &vpid, vmx_pf_exception_test_guest); 10592 } 10593 10594 static void vmx_pf_invvpid_test(void) 10595 { 10596 if (!is_invvpid_type_supported(INVVPID_ADDR)) 10597 test_skip("INVVPID ADDR unsupported"); 10598 10599 __vmx_pf_vpid_test(invalidate_tlb_invvpid_addr, 0xaaaa); 10600 } 10601 10602 static void vmx_pf_vpid_test(void) 10603 { 10604 /* Need INVVPID(ALL) to flush VPIDs upon wrap/reuse. */ 10605 if (!is_invvpid_type_supported(INVVPID_ALL)) 10606 test_skip("INVVPID ALL unsupported"); 10607 10608 __vmx_pf_vpid_test(invalidate_tlb_new_vpid, 1); 10609 } 10610 10611 static void vmx_l2_ac_test(void) 10612 { 10613 bool hit_ac = false; 10614 10615 write_cr0(read_cr0() | X86_CR0_AM); 10616 write_rflags(read_rflags() | X86_EFLAGS_AC); 10617 10618 run_in_user(generate_usermode_ac, AC_VECTOR, 0, 0, 0, 0, &hit_ac); 10619 report(hit_ac, "Usermode #AC handled in L2"); 10620 vmcall(); 10621 } 10622 10623 struct vmx_exception_test { 10624 u8 vector; 10625 void (*guest_code)(void); 10626 }; 10627 10628 struct vmx_exception_test vmx_exception_tests[] = { 10629 { GP_VECTOR, generate_non_canonical_gp }, 10630 { UD_VECTOR, generate_ud }, 10631 { DE_VECTOR, generate_de }, 10632 { DB_VECTOR, generate_single_step_db }, 10633 { BP_VECTOR, generate_bp }, 10634 { AC_VECTOR, vmx_l2_ac_test }, 10635 { OF_VECTOR, generate_of }, 10636 { NM_VECTOR, generate_cr0_ts_nm }, 10637 { NM_VECTOR, generate_cr0_em_nm }, 10638 }; 10639 10640 static u8 vmx_exception_test_vector; 10641 10642 static void vmx_exception_handler(struct ex_regs *regs) 10643 { 10644 report(regs->vector == vmx_exception_test_vector, 10645 "Handling %s in L2's exception handler", 10646 exception_mnemonic(vmx_exception_test_vector)); 10647 vmcall(); 10648 } 10649 10650 static void handle_exception_in_l2(u8 vector) 10651 { 10652 handler old_handler = handle_exception(vector, vmx_exception_handler); 10653 10654 vmx_exception_test_vector = vector; 10655 10656 enter_guest(); 10657 report(vmcs_read(EXI_REASON) == VMX_VMCALL, 10658 "%s handled by L2", exception_mnemonic(vector)); 10659 10660 handle_exception(vector, old_handler); 10661 } 10662 10663 static void handle_exception_in_l1(u32 vector) 10664 { 10665 u32 old_eb = vmcs_read(EXC_BITMAP); 10666 u32 intr_type; 10667 u32 intr_info; 10668 10669 vmcs_write(EXC_BITMAP, old_eb | (1u << vector)); 10670 10671 enter_guest(); 10672 10673 if (vector == BP_VECTOR || vector == OF_VECTOR) 10674 intr_type = VMX_INTR_TYPE_SOFT_EXCEPTION; 10675 else 10676 intr_type = VMX_INTR_TYPE_HARD_EXCEPTION; 10677 10678 intr_info = vmcs_read(EXI_INTR_INFO); 10679 report((vmcs_read(EXI_REASON) == VMX_EXC_NMI) && 10680 (intr_info & INTR_INFO_VALID_MASK) && 10681 (intr_info & INTR_INFO_VECTOR_MASK) == vector && 10682 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> INTR_INFO_INTR_TYPE_SHIFT) == intr_type, 10683 "%s correctly routed to L1", exception_mnemonic(vector)); 10684 10685 vmcs_write(EXC_BITMAP, old_eb); 10686 } 10687 10688 static void vmx_exception_test(void) 10689 { 10690 struct vmx_exception_test *t; 10691 int i; 10692 10693 for (i = 0; i < ARRAY_SIZE(vmx_exception_tests); i++) { 10694 t = &vmx_exception_tests[i]; 10695 10696 /* 10697 * Override the guest code before each run even though it's the 10698 * same code, the VMCS guest state needs to be reinitialized. 10699 */ 10700 test_override_guest(t->guest_code); 10701 handle_exception_in_l2(t->vector); 10702 10703 test_override_guest(t->guest_code); 10704 handle_exception_in_l1(t->vector); 10705 } 10706 10707 test_set_guest_finished(); 10708 } 10709 10710 #define TEST(name) { #name, .v2 = name } 10711 10712 /* name/init/guest_main/exit_handler/syscall_handler/guest_regs */ 10713 struct vmx_test vmx_tests[] = { 10714 { "null", NULL, basic_guest_main, basic_exit_handler, NULL, {0} }, 10715 { "vmenter", NULL, vmenter_main, vmenter_exit_handler, NULL, {0} }, 10716 { "preemption timer", preemption_timer_init, preemption_timer_main, 10717 preemption_timer_exit_handler, NULL, {0} }, 10718 { "control field PAT", test_ctrl_pat_init, test_ctrl_pat_main, 10719 test_ctrl_pat_exit_handler, NULL, {0} }, 10720 { "control field EFER", test_ctrl_efer_init, test_ctrl_efer_main, 10721 test_ctrl_efer_exit_handler, NULL, {0} }, 10722 { "CR shadowing", NULL, cr_shadowing_main, 10723 cr_shadowing_exit_handler, NULL, {0} }, 10724 { "I/O bitmap", iobmp_init, iobmp_main, iobmp_exit_handler, 10725 NULL, {0} }, 10726 { "instruction intercept", insn_intercept_init, insn_intercept_main, 10727 insn_intercept_exit_handler, NULL, {0} }, 10728 { "EPT A/D disabled", ept_init, ept_main, ept_exit_handler, NULL, {0} }, 10729 { "EPT A/D enabled", eptad_init, eptad_main, eptad_exit_handler, NULL, {0} }, 10730 { "PML", pml_init, pml_main, pml_exit_handler, NULL, {0} }, 10731 { "interrupt", interrupt_init, interrupt_main, 10732 interrupt_exit_handler, NULL, {0} }, 10733 { "nmi_hlt", nmi_hlt_init, nmi_hlt_main, 10734 nmi_hlt_exit_handler, NULL, {0} }, 10735 { "debug controls", dbgctls_init, dbgctls_main, dbgctls_exit_handler, 10736 NULL, {0} }, 10737 { "MSR switch", msr_switch_init, msr_switch_main, 10738 msr_switch_exit_handler, NULL, {0}, msr_switch_entry_failure }, 10739 { "vmmcall", vmmcall_init, vmmcall_main, vmmcall_exit_handler, NULL, {0} }, 10740 { "disable RDTSCP", disable_rdtscp_init, disable_rdtscp_main, 10741 disable_rdtscp_exit_handler, NULL, {0} }, 10742 { "exit_monitor_from_l2_test", NULL, exit_monitor_from_l2_main, 10743 exit_monitor_from_l2_handler, NULL, {0} }, 10744 { "invalid_msr", invalid_msr_init, invalid_msr_main, 10745 invalid_msr_exit_handler, NULL, {0}, invalid_msr_entry_failure}, 10746 /* Basic V2 tests. */ 10747 TEST(v2_null_test), 10748 TEST(v2_multiple_entries_test), 10749 TEST(fixture_test_case1), 10750 TEST(fixture_test_case2), 10751 /* Opcode tests. */ 10752 TEST(invvpid_test), 10753 /* VM-entry tests */ 10754 TEST(vmx_controls_test), 10755 TEST(vmx_host_state_area_test), 10756 TEST(vmx_guest_state_area_test), 10757 TEST(vmentry_movss_shadow_test), 10758 TEST(vmentry_unrestricted_guest_test), 10759 /* APICv tests */ 10760 TEST(vmx_eoi_bitmap_ioapic_scan_test), 10761 TEST(vmx_hlt_with_rvi_test), 10762 TEST(apic_reg_virt_test), 10763 TEST(virt_x2apic_mode_test), 10764 /* APIC pass-through tests */ 10765 TEST(vmx_apic_passthrough_test), 10766 TEST(vmx_apic_passthrough_thread_test), 10767 TEST(vmx_apic_passthrough_tpr_threshold_test), 10768 TEST(vmx_init_signal_test), 10769 TEST(vmx_sipi_signal_test), 10770 /* VMCS Shadowing tests */ 10771 TEST(vmx_vmcs_shadow_test), 10772 /* Regression tests */ 10773 TEST(vmx_ldtr_test), 10774 TEST(vmx_cr_load_test), 10775 TEST(vmx_cr4_osxsave_test), 10776 TEST(vmx_no_nm_test), 10777 TEST(vmx_db_test), 10778 TEST(vmx_nmi_window_test), 10779 TEST(vmx_intr_window_test), 10780 TEST(vmx_pending_event_test), 10781 TEST(vmx_pending_event_hlt_test), 10782 TEST(vmx_store_tsc_test), 10783 TEST(vmx_preemption_timer_zero_test), 10784 TEST(vmx_preemption_timer_tf_test), 10785 TEST(vmx_preemption_timer_expiry_test), 10786 /* EPT access tests. */ 10787 TEST(ept_access_test_not_present), 10788 TEST(ept_access_test_read_only), 10789 TEST(ept_access_test_write_only), 10790 TEST(ept_access_test_read_write), 10791 TEST(ept_access_test_execute_only), 10792 TEST(ept_access_test_read_execute), 10793 TEST(ept_access_test_write_execute), 10794 TEST(ept_access_test_read_write_execute), 10795 TEST(ept_access_test_reserved_bits), 10796 TEST(ept_access_test_ignored_bits), 10797 TEST(ept_access_test_paddr_not_present_ad_disabled), 10798 TEST(ept_access_test_paddr_not_present_ad_enabled), 10799 TEST(ept_access_test_paddr_read_only_ad_disabled), 10800 TEST(ept_access_test_paddr_read_only_ad_enabled), 10801 TEST(ept_access_test_paddr_read_write), 10802 TEST(ept_access_test_paddr_read_write_execute), 10803 TEST(ept_access_test_paddr_read_execute_ad_disabled), 10804 TEST(ept_access_test_paddr_read_execute_ad_enabled), 10805 TEST(ept_access_test_paddr_not_present_page_fault), 10806 TEST(ept_access_test_force_2m_page), 10807 /* Atomic MSR switch tests. */ 10808 TEST(atomic_switch_max_msrs_test), 10809 TEST(atomic_switch_overflow_msrs_test), 10810 TEST(rdtsc_vmexit_diff_test), 10811 TEST(vmx_mtf_test), 10812 TEST(vmx_mtf_pdpte_test), 10813 TEST(vmx_pf_exception_test), 10814 TEST(vmx_pf_exception_forced_emulation_test), 10815 TEST(vmx_pf_no_vpid_test), 10816 TEST(vmx_pf_invvpid_test), 10817 TEST(vmx_pf_vpid_test), 10818 TEST(vmx_exception_test), 10819 { NULL, NULL, NULL, NULL, NULL, {0} }, 10820 }; 10821