1 /* 2 * All test cases of nested virtualization should be in this file 3 * 4 * Author : Arthur Chunqi Li <yzt356@gmail.com> 5 */ 6 7 #include <asm/debugreg.h> 8 9 #include "vmx.h" 10 #include "msr.h" 11 #include "processor.h" 12 #include "pmu.h" 13 #include "vm.h" 14 #include "pci.h" 15 #include "fwcfg.h" 16 #include "isr.h" 17 #include "desc.h" 18 #include "apic.h" 19 #include "types.h" 20 #include "vmalloc.h" 21 #include "alloc_page.h" 22 #include "smp.h" 23 #include "delay.h" 24 #include "access.h" 25 #include "x86/usermode.h" 26 27 /* 28 * vmcs.GUEST_PENDING_DEBUG has the same format as DR6, although some bits that 29 * are legal in DR6 are reserved in vmcs.GUEST_PENDING_DEBUG. And if any data 30 * or I/O breakpoint matches *and* was enabled, bit 12 is also set. 31 */ 32 #define PENDING_DBG_TRAP BIT(12) 33 34 #define VPID_CAP_INVVPID_TYPES_SHIFT 40 35 36 u64 ia32_pat; 37 u64 ia32_efer; 38 void *io_bitmap_a, *io_bitmap_b; 39 u16 ioport; 40 41 unsigned long *pml4; 42 u64 eptp; 43 void *data_page1, *data_page2; 44 45 phys_addr_t pci_physaddr; 46 47 void *pml_log; 48 #define PML_INDEX 512 49 50 static inline unsigned ffs(unsigned x) 51 { 52 int pos = -1; 53 54 __asm__ __volatile__("bsf %1, %%eax; cmovnz %%eax, %0" 55 : "+r"(pos) : "rm"(x) : "eax"); 56 return pos + 1; 57 } 58 59 static inline void vmcall(void) 60 { 61 asm volatile("vmcall"); 62 } 63 64 static void basic_guest_main(void) 65 { 66 report_pass("Basic VMX test"); 67 } 68 69 static int basic_exit_handler(union exit_reason exit_reason) 70 { 71 report_fail("Basic VMX test"); 72 print_vmexit_info(exit_reason); 73 return VMX_TEST_EXIT; 74 } 75 76 static void vmenter_main(void) 77 { 78 u64 rax; 79 u64 rsp, resume_rsp; 80 81 report_pass("test vmlaunch"); 82 83 asm volatile( 84 "mov %%rsp, %0\n\t" 85 "mov %3, %%rax\n\t" 86 "vmcall\n\t" 87 "mov %%rax, %1\n\t" 88 "mov %%rsp, %2\n\t" 89 : "=r"(rsp), "=r"(rax), "=r"(resume_rsp) 90 : "g"(0xABCD)); 91 report((rax == 0xFFFF) && (rsp == resume_rsp), "test vmresume"); 92 } 93 94 static int vmenter_exit_handler(union exit_reason exit_reason) 95 { 96 u64 guest_rip = vmcs_read(GUEST_RIP); 97 98 switch (exit_reason.basic) { 99 case VMX_VMCALL: 100 if (regs.rax != 0xABCD) { 101 report_fail("test vmresume"); 102 return VMX_TEST_VMEXIT; 103 } 104 regs.rax = 0xFFFF; 105 vmcs_write(GUEST_RIP, guest_rip + 3); 106 return VMX_TEST_RESUME; 107 default: 108 report_fail("test vmresume"); 109 print_vmexit_info(exit_reason); 110 } 111 return VMX_TEST_VMEXIT; 112 } 113 114 u32 preempt_scale; 115 volatile unsigned long long tsc_val; 116 volatile u32 preempt_val; 117 u64 saved_rip; 118 119 static int preemption_timer_init(struct vmcs *vmcs) 120 { 121 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 122 printf("\tPreemption timer is not supported\n"); 123 return VMX_TEST_EXIT; 124 } 125 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 126 preempt_val = 10000000; 127 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 128 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 129 130 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 131 printf("\tSave preemption value is not supported\n"); 132 133 return VMX_TEST_START; 134 } 135 136 static void preemption_timer_main(void) 137 { 138 tsc_val = rdtsc(); 139 if (ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) { 140 vmx_set_test_stage(0); 141 vmcall(); 142 if (vmx_get_test_stage() == 1) 143 vmcall(); 144 } 145 vmx_set_test_stage(1); 146 while (vmx_get_test_stage() == 1) { 147 if (((rdtsc() - tsc_val) >> preempt_scale) 148 > 10 * preempt_val) { 149 vmx_set_test_stage(2); 150 vmcall(); 151 } 152 } 153 tsc_val = rdtsc(); 154 asm volatile ("hlt"); 155 vmcall(); 156 vmx_set_test_stage(5); 157 vmcall(); 158 } 159 160 static int preemption_timer_exit_handler(union exit_reason exit_reason) 161 { 162 bool guest_halted; 163 u64 guest_rip; 164 u32 insn_len; 165 u32 ctrl_exit; 166 167 guest_rip = vmcs_read(GUEST_RIP); 168 insn_len = vmcs_read(EXI_INST_LEN); 169 switch (exit_reason.basic) { 170 case VMX_PREEMPT: 171 switch (vmx_get_test_stage()) { 172 case 1: 173 case 2: 174 report(((rdtsc() - tsc_val) >> preempt_scale) >= preempt_val, 175 "busy-wait for preemption timer"); 176 vmx_set_test_stage(3); 177 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 178 return VMX_TEST_RESUME; 179 case 3: 180 guest_halted = 181 (vmcs_read(GUEST_ACTV_STATE) == ACTV_HLT); 182 report(((rdtsc() - tsc_val) >> preempt_scale) >= preempt_val 183 && guest_halted, 184 "preemption timer during hlt"); 185 vmx_set_test_stage(4); 186 vmcs_write(PIN_CONTROLS, 187 vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 188 vmcs_write(EXI_CONTROLS, 189 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_PREEMPT); 190 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 191 return VMX_TEST_RESUME; 192 case 4: 193 report(saved_rip == guest_rip, 194 "preemption timer with 0 value"); 195 break; 196 default: 197 report_fail("Invalid stage."); 198 print_vmexit_info(exit_reason); 199 break; 200 } 201 break; 202 case VMX_VMCALL: 203 vmcs_write(GUEST_RIP, guest_rip + insn_len); 204 switch (vmx_get_test_stage()) { 205 case 0: 206 report(vmcs_read(PREEMPT_TIMER_VALUE) == preempt_val, 207 "Keep preemption value"); 208 vmx_set_test_stage(1); 209 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 210 ctrl_exit = (vmcs_read(EXI_CONTROLS) | 211 EXI_SAVE_PREEMPT) & ctrl_exit_rev.clr; 212 vmcs_write(EXI_CONTROLS, ctrl_exit); 213 return VMX_TEST_RESUME; 214 case 1: 215 report(vmcs_read(PREEMPT_TIMER_VALUE) < preempt_val, 216 "Save preemption value"); 217 return VMX_TEST_RESUME; 218 case 2: 219 report_fail("busy-wait for preemption timer"); 220 vmx_set_test_stage(3); 221 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 222 return VMX_TEST_RESUME; 223 case 3: 224 report_fail("preemption timer during hlt"); 225 vmx_set_test_stage(4); 226 /* fall through */ 227 case 4: 228 vmcs_write(PIN_CONTROLS, 229 vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 230 vmcs_write(PREEMPT_TIMER_VALUE, 0); 231 saved_rip = guest_rip + insn_len; 232 return VMX_TEST_RESUME; 233 case 5: 234 report_fail("preemption timer with 0 value (vmcall stage 5)"); 235 break; 236 default: 237 // Should not reach here 238 report_fail("unexpected stage, %d", 239 vmx_get_test_stage()); 240 print_vmexit_info(exit_reason); 241 return VMX_TEST_VMEXIT; 242 } 243 break; 244 default: 245 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 246 print_vmexit_info(exit_reason); 247 } 248 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 249 return VMX_TEST_VMEXIT; 250 } 251 252 static void msr_bmp_init(void) 253 { 254 void *msr_bitmap; 255 u32 ctrl_cpu0; 256 257 msr_bitmap = alloc_page(); 258 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 259 ctrl_cpu0 |= CPU_MSR_BITMAP; 260 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 261 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 262 } 263 264 static void *get_msr_bitmap(void) 265 { 266 void *msr_bitmap; 267 268 if (vmcs_read(CPU_EXEC_CTRL0) & CPU_MSR_BITMAP) { 269 msr_bitmap = (void *)vmcs_read(MSR_BITMAP); 270 } else { 271 msr_bitmap = alloc_page(); 272 memset(msr_bitmap, 0xff, PAGE_SIZE); 273 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 274 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_MSR_BITMAP); 275 } 276 277 return msr_bitmap; 278 } 279 280 static void disable_intercept_for_x2apic_msrs(void) 281 { 282 unsigned long *msr_bitmap = (unsigned long *)get_msr_bitmap(); 283 u32 msr; 284 285 for (msr = APIC_BASE_MSR; 286 msr < (APIC_BASE_MSR+0xff); 287 msr += BITS_PER_LONG) { 288 unsigned int word = msr / BITS_PER_LONG; 289 290 msr_bitmap[word] = 0; 291 msr_bitmap[word + (0x800 / sizeof(long))] = 0; 292 } 293 } 294 295 static int test_ctrl_pat_init(struct vmcs *vmcs) 296 { 297 u64 ctrl_ent; 298 u64 ctrl_exi; 299 300 msr_bmp_init(); 301 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT) && 302 !(ctrl_exit_rev.clr & EXI_LOAD_PAT) && 303 !(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 304 printf("\tSave/load PAT is not supported\n"); 305 return 1; 306 } 307 308 ctrl_ent = vmcs_read(ENT_CONTROLS); 309 ctrl_exi = vmcs_read(EXI_CONTROLS); 310 ctrl_ent |= ctrl_enter_rev.clr & ENT_LOAD_PAT; 311 ctrl_exi |= ctrl_exit_rev.clr & (EXI_SAVE_PAT | EXI_LOAD_PAT); 312 vmcs_write(ENT_CONTROLS, ctrl_ent); 313 vmcs_write(EXI_CONTROLS, ctrl_exi); 314 ia32_pat = rdmsr(MSR_IA32_CR_PAT); 315 vmcs_write(GUEST_PAT, 0x0); 316 vmcs_write(HOST_PAT, ia32_pat); 317 return VMX_TEST_START; 318 } 319 320 static void test_ctrl_pat_main(void) 321 { 322 u64 guest_ia32_pat; 323 324 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 325 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) 326 printf("\tENT_LOAD_PAT is not supported.\n"); 327 else { 328 if (guest_ia32_pat != 0) { 329 report_fail("Entry load PAT"); 330 return; 331 } 332 } 333 wrmsr(MSR_IA32_CR_PAT, 0x6); 334 vmcall(); 335 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 336 if (ctrl_enter_rev.clr & ENT_LOAD_PAT) 337 report(guest_ia32_pat == ia32_pat, "Entry load PAT"); 338 } 339 340 static int test_ctrl_pat_exit_handler(union exit_reason exit_reason) 341 { 342 u64 guest_rip; 343 u64 guest_pat; 344 345 guest_rip = vmcs_read(GUEST_RIP); 346 switch (exit_reason.basic) { 347 case VMX_VMCALL: 348 guest_pat = vmcs_read(GUEST_PAT); 349 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT)) { 350 printf("\tEXI_SAVE_PAT is not supported\n"); 351 vmcs_write(GUEST_PAT, 0x6); 352 } else { 353 report(guest_pat == 0x6, "Exit save PAT"); 354 } 355 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) 356 printf("\tEXI_LOAD_PAT is not supported\n"); 357 else 358 report(rdmsr(MSR_IA32_CR_PAT) == ia32_pat, 359 "Exit load PAT"); 360 vmcs_write(GUEST_PAT, ia32_pat); 361 vmcs_write(GUEST_RIP, guest_rip + 3); 362 return VMX_TEST_RESUME; 363 default: 364 printf("ERROR : Unknown exit reason, 0x%x.\n", exit_reason.full); 365 break; 366 } 367 return VMX_TEST_VMEXIT; 368 } 369 370 static int test_ctrl_efer_init(struct vmcs *vmcs) 371 { 372 u64 ctrl_ent; 373 u64 ctrl_exi; 374 375 msr_bmp_init(); 376 ctrl_ent = vmcs_read(ENT_CONTROLS) | ENT_LOAD_EFER; 377 ctrl_exi = vmcs_read(EXI_CONTROLS) | EXI_SAVE_EFER | EXI_LOAD_EFER; 378 vmcs_write(ENT_CONTROLS, ctrl_ent & ctrl_enter_rev.clr); 379 vmcs_write(EXI_CONTROLS, ctrl_exi & ctrl_exit_rev.clr); 380 ia32_efer = rdmsr(MSR_EFER); 381 vmcs_write(GUEST_EFER, ia32_efer ^ EFER_NX); 382 vmcs_write(HOST_EFER, ia32_efer ^ EFER_NX); 383 return VMX_TEST_START; 384 } 385 386 static void test_ctrl_efer_main(void) 387 { 388 u64 guest_ia32_efer; 389 390 guest_ia32_efer = rdmsr(MSR_EFER); 391 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) 392 printf("\tENT_LOAD_EFER is not supported.\n"); 393 else { 394 if (guest_ia32_efer != (ia32_efer ^ EFER_NX)) { 395 report_fail("Entry load EFER"); 396 return; 397 } 398 } 399 wrmsr(MSR_EFER, ia32_efer); 400 vmcall(); 401 guest_ia32_efer = rdmsr(MSR_EFER); 402 if (ctrl_enter_rev.clr & ENT_LOAD_EFER) 403 report(guest_ia32_efer == ia32_efer, "Entry load EFER"); 404 } 405 406 static int test_ctrl_efer_exit_handler(union exit_reason exit_reason) 407 { 408 u64 guest_rip; 409 u64 guest_efer; 410 411 guest_rip = vmcs_read(GUEST_RIP); 412 switch (exit_reason.basic) { 413 case VMX_VMCALL: 414 guest_efer = vmcs_read(GUEST_EFER); 415 if (!(ctrl_exit_rev.clr & EXI_SAVE_EFER)) { 416 printf("\tEXI_SAVE_EFER is not supported\n"); 417 vmcs_write(GUEST_EFER, ia32_efer); 418 } else { 419 report(guest_efer == ia32_efer, "Exit save EFER"); 420 } 421 if (!(ctrl_exit_rev.clr & EXI_LOAD_EFER)) { 422 printf("\tEXI_LOAD_EFER is not supported\n"); 423 wrmsr(MSR_EFER, ia32_efer ^ EFER_NX); 424 } else { 425 report(rdmsr(MSR_EFER) == (ia32_efer ^ EFER_NX), 426 "Exit load EFER"); 427 } 428 vmcs_write(GUEST_PAT, ia32_efer); 429 vmcs_write(GUEST_RIP, guest_rip + 3); 430 return VMX_TEST_RESUME; 431 default: 432 printf("ERROR : Unknown exit reason, 0x%x.\n", exit_reason.full); 433 break; 434 } 435 return VMX_TEST_VMEXIT; 436 } 437 438 u32 guest_cr0, guest_cr4; 439 440 static void cr_shadowing_main(void) 441 { 442 u32 cr0, cr4, tmp; 443 444 // Test read through 445 vmx_set_test_stage(0); 446 guest_cr0 = read_cr0(); 447 if (vmx_get_test_stage() == 1) 448 report_fail("Read through CR0"); 449 else 450 vmcall(); 451 vmx_set_test_stage(1); 452 guest_cr4 = read_cr4(); 453 if (vmx_get_test_stage() == 2) 454 report_fail("Read through CR4"); 455 else 456 vmcall(); 457 // Test write through 458 guest_cr0 = guest_cr0 ^ (X86_CR0_TS | X86_CR0_MP); 459 guest_cr4 = guest_cr4 ^ (X86_CR4_TSD | X86_CR4_DE); 460 vmx_set_test_stage(2); 461 write_cr0(guest_cr0); 462 if (vmx_get_test_stage() == 3) 463 report_fail("Write through CR0"); 464 else 465 vmcall(); 466 vmx_set_test_stage(3); 467 write_cr4(guest_cr4); 468 if (vmx_get_test_stage() == 4) 469 report_fail("Write through CR4"); 470 else 471 vmcall(); 472 // Test read shadow 473 vmx_set_test_stage(4); 474 vmcall(); 475 cr0 = read_cr0(); 476 if (vmx_get_test_stage() != 5) 477 report(cr0 == guest_cr0, "Read shadowing CR0"); 478 vmx_set_test_stage(5); 479 cr4 = read_cr4(); 480 if (vmx_get_test_stage() != 6) 481 report(cr4 == guest_cr4, "Read shadowing CR4"); 482 // Test write shadow (same value with shadow) 483 vmx_set_test_stage(6); 484 write_cr0(guest_cr0); 485 if (vmx_get_test_stage() == 7) 486 report_fail("Write shadowing CR0 (same value with shadow)"); 487 else 488 vmcall(); 489 vmx_set_test_stage(7); 490 write_cr4(guest_cr4); 491 if (vmx_get_test_stage() == 8) 492 report_fail("Write shadowing CR4 (same value with shadow)"); 493 else 494 vmcall(); 495 // Test write shadow (different value) 496 vmx_set_test_stage(8); 497 tmp = guest_cr0 ^ X86_CR0_TS; 498 asm volatile("mov %0, %%rsi\n\t" 499 "mov %%rsi, %%cr0\n\t" 500 ::"m"(tmp) 501 :"rsi", "memory", "cc"); 502 report(vmx_get_test_stage() == 9, 503 "Write shadowing different X86_CR0_TS"); 504 vmx_set_test_stage(9); 505 tmp = guest_cr0 ^ X86_CR0_MP; 506 asm volatile("mov %0, %%rsi\n\t" 507 "mov %%rsi, %%cr0\n\t" 508 ::"m"(tmp) 509 :"rsi", "memory", "cc"); 510 report(vmx_get_test_stage() == 10, 511 "Write shadowing different X86_CR0_MP"); 512 vmx_set_test_stage(10); 513 tmp = guest_cr4 ^ X86_CR4_TSD; 514 asm volatile("mov %0, %%rsi\n\t" 515 "mov %%rsi, %%cr4\n\t" 516 ::"m"(tmp) 517 :"rsi", "memory", "cc"); 518 report(vmx_get_test_stage() == 11, 519 "Write shadowing different X86_CR4_TSD"); 520 vmx_set_test_stage(11); 521 tmp = guest_cr4 ^ X86_CR4_DE; 522 asm volatile("mov %0, %%rsi\n\t" 523 "mov %%rsi, %%cr4\n\t" 524 ::"m"(tmp) 525 :"rsi", "memory", "cc"); 526 report(vmx_get_test_stage() == 12, 527 "Write shadowing different X86_CR4_DE"); 528 } 529 530 static int cr_shadowing_exit_handler(union exit_reason exit_reason) 531 { 532 u64 guest_rip; 533 u32 insn_len; 534 u32 exit_qual; 535 536 guest_rip = vmcs_read(GUEST_RIP); 537 insn_len = vmcs_read(EXI_INST_LEN); 538 exit_qual = vmcs_read(EXI_QUALIFICATION); 539 switch (exit_reason.basic) { 540 case VMX_VMCALL: 541 switch (vmx_get_test_stage()) { 542 case 0: 543 report(guest_cr0 == vmcs_read(GUEST_CR0), 544 "Read through CR0"); 545 break; 546 case 1: 547 report(guest_cr4 == vmcs_read(GUEST_CR4), 548 "Read through CR4"); 549 break; 550 case 2: 551 report(guest_cr0 == vmcs_read(GUEST_CR0), 552 "Write through CR0"); 553 break; 554 case 3: 555 report(guest_cr4 == vmcs_read(GUEST_CR4), 556 "Write through CR4"); 557 break; 558 case 4: 559 guest_cr0 = vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP); 560 guest_cr4 = vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE); 561 vmcs_write(CR0_MASK, X86_CR0_TS | X86_CR0_MP); 562 vmcs_write(CR0_READ_SHADOW, guest_cr0 & (X86_CR0_TS | X86_CR0_MP)); 563 vmcs_write(CR4_MASK, X86_CR4_TSD | X86_CR4_DE); 564 vmcs_write(CR4_READ_SHADOW, guest_cr4 & (X86_CR4_TSD | X86_CR4_DE)); 565 break; 566 case 6: 567 report(guest_cr0 == (vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP)), 568 "Write shadowing CR0 (same value)"); 569 break; 570 case 7: 571 report(guest_cr4 == (vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE)), 572 "Write shadowing CR4 (same value)"); 573 break; 574 default: 575 // Should not reach here 576 report_fail("unexpected stage, %d", 577 vmx_get_test_stage()); 578 print_vmexit_info(exit_reason); 579 return VMX_TEST_VMEXIT; 580 } 581 vmcs_write(GUEST_RIP, guest_rip + insn_len); 582 return VMX_TEST_RESUME; 583 case VMX_CR: 584 switch (vmx_get_test_stage()) { 585 case 4: 586 report_fail("Read shadowing CR0"); 587 vmx_inc_test_stage(); 588 break; 589 case 5: 590 report_fail("Read shadowing CR4"); 591 vmx_inc_test_stage(); 592 break; 593 case 6: 594 report_fail("Write shadowing CR0 (same value)"); 595 vmx_inc_test_stage(); 596 break; 597 case 7: 598 report_fail("Write shadowing CR4 (same value)"); 599 vmx_inc_test_stage(); 600 break; 601 case 8: 602 case 9: 603 // 0x600 encodes "mov %esi, %cr0" 604 if (exit_qual == 0x600) 605 vmx_inc_test_stage(); 606 break; 607 case 10: 608 case 11: 609 // 0x604 encodes "mov %esi, %cr4" 610 if (exit_qual == 0x604) 611 vmx_inc_test_stage(); 612 break; 613 default: 614 // Should not reach here 615 report_fail("unexpected stage, %d", 616 vmx_get_test_stage()); 617 print_vmexit_info(exit_reason); 618 return VMX_TEST_VMEXIT; 619 } 620 vmcs_write(GUEST_RIP, guest_rip + insn_len); 621 return VMX_TEST_RESUME; 622 default: 623 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 624 print_vmexit_info(exit_reason); 625 } 626 return VMX_TEST_VMEXIT; 627 } 628 629 static int iobmp_init(struct vmcs *vmcs) 630 { 631 u32 ctrl_cpu0; 632 633 io_bitmap_a = alloc_page(); 634 io_bitmap_b = alloc_page(); 635 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 636 ctrl_cpu0 |= CPU_IO_BITMAP; 637 ctrl_cpu0 &= (~CPU_IO); 638 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 639 vmcs_write(IO_BITMAP_A, (u64)io_bitmap_a); 640 vmcs_write(IO_BITMAP_B, (u64)io_bitmap_b); 641 return VMX_TEST_START; 642 } 643 644 static void iobmp_main(void) 645 { 646 // stage 0, test IO pass 647 vmx_set_test_stage(0); 648 inb(0x5000); 649 outb(0x0, 0x5000); 650 report(vmx_get_test_stage() == 0, "I/O bitmap - I/O pass"); 651 // test IO width, in/out 652 ((u8 *)io_bitmap_a)[0] = 0xFF; 653 vmx_set_test_stage(2); 654 inb(0x0); 655 report(vmx_get_test_stage() == 3, "I/O bitmap - trap in"); 656 vmx_set_test_stage(3); 657 outw(0x0, 0x0); 658 report(vmx_get_test_stage() == 4, "I/O bitmap - trap out"); 659 vmx_set_test_stage(4); 660 inl(0x0); 661 report(vmx_get_test_stage() == 5, "I/O bitmap - I/O width, long"); 662 // test low/high IO port 663 vmx_set_test_stage(5); 664 ((u8 *)io_bitmap_a)[0x5000 / 8] = (1 << (0x5000 % 8)); 665 inb(0x5000); 666 report(vmx_get_test_stage() == 6, "I/O bitmap - I/O port, low part"); 667 vmx_set_test_stage(6); 668 ((u8 *)io_bitmap_b)[0x1000 / 8] = (1 << (0x1000 % 8)); 669 inb(0x9000); 670 report(vmx_get_test_stage() == 7, "I/O bitmap - I/O port, high part"); 671 // test partial pass 672 vmx_set_test_stage(7); 673 inl(0x4FFF); 674 report(vmx_get_test_stage() == 8, "I/O bitmap - partial pass"); 675 // test overrun 676 vmx_set_test_stage(8); 677 memset(io_bitmap_a, 0x0, PAGE_SIZE); 678 memset(io_bitmap_b, 0x0, PAGE_SIZE); 679 inl(0xFFFF); 680 report(vmx_get_test_stage() == 9, "I/O bitmap - overrun"); 681 vmx_set_test_stage(9); 682 vmcall(); 683 outb(0x0, 0x0); 684 report(vmx_get_test_stage() == 9, 685 "I/O bitmap - ignore unconditional exiting"); 686 vmx_set_test_stage(10); 687 vmcall(); 688 outb(0x0, 0x0); 689 report(vmx_get_test_stage() == 11, 690 "I/O bitmap - unconditional exiting"); 691 } 692 693 static int iobmp_exit_handler(union exit_reason exit_reason) 694 { 695 u64 guest_rip; 696 ulong exit_qual; 697 u32 insn_len, ctrl_cpu0; 698 699 guest_rip = vmcs_read(GUEST_RIP); 700 exit_qual = vmcs_read(EXI_QUALIFICATION); 701 insn_len = vmcs_read(EXI_INST_LEN); 702 switch (exit_reason.basic) { 703 case VMX_IO: 704 switch (vmx_get_test_stage()) { 705 case 0: 706 case 1: 707 vmx_inc_test_stage(); 708 break; 709 case 2: 710 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_BYTE, 711 "I/O bitmap - I/O width, byte"); 712 report(exit_qual & VMX_IO_IN, 713 "I/O bitmap - I/O direction, in"); 714 vmx_inc_test_stage(); 715 break; 716 case 3: 717 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_WORD, 718 "I/O bitmap - I/O width, word"); 719 report(!(exit_qual & VMX_IO_IN), 720 "I/O bitmap - I/O direction, out"); 721 vmx_inc_test_stage(); 722 break; 723 case 4: 724 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_LONG, 725 "I/O bitmap - I/O width, long"); 726 vmx_inc_test_stage(); 727 break; 728 case 5: 729 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x5000) 730 vmx_inc_test_stage(); 731 break; 732 case 6: 733 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x9000) 734 vmx_inc_test_stage(); 735 break; 736 case 7: 737 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x4FFF) 738 vmx_inc_test_stage(); 739 break; 740 case 8: 741 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0xFFFF) 742 vmx_inc_test_stage(); 743 break; 744 case 9: 745 case 10: 746 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 747 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0 & ~CPU_IO); 748 vmx_inc_test_stage(); 749 break; 750 default: 751 // Should not reach here 752 report_fail("unexpected stage, %d", 753 vmx_get_test_stage()); 754 print_vmexit_info(exit_reason); 755 return VMX_TEST_VMEXIT; 756 } 757 vmcs_write(GUEST_RIP, guest_rip + insn_len); 758 return VMX_TEST_RESUME; 759 case VMX_VMCALL: 760 switch (vmx_get_test_stage()) { 761 case 9: 762 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 763 ctrl_cpu0 |= CPU_IO | CPU_IO_BITMAP; 764 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 765 break; 766 case 10: 767 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 768 ctrl_cpu0 = (ctrl_cpu0 & ~CPU_IO_BITMAP) | CPU_IO; 769 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 770 break; 771 default: 772 // Should not reach here 773 report_fail("unexpected stage, %d", 774 vmx_get_test_stage()); 775 print_vmexit_info(exit_reason); 776 return VMX_TEST_VMEXIT; 777 } 778 vmcs_write(GUEST_RIP, guest_rip + insn_len); 779 return VMX_TEST_RESUME; 780 default: 781 printf("guest_rip = %#lx\n", guest_rip); 782 printf("\tERROR : Unknown exit reason, 0x%x\n", exit_reason.full); 783 break; 784 } 785 return VMX_TEST_VMEXIT; 786 } 787 788 #define INSN_CPU0 0 789 #define INSN_CPU1 1 790 #define INSN_ALWAYS_TRAP 2 791 792 #define FIELD_EXIT_QUAL (1 << 0) 793 #define FIELD_INSN_INFO (1 << 1) 794 795 asm( 796 "insn_hlt: hlt;ret\n\t" 797 "insn_invlpg: invlpg 0x12345678;ret\n\t" 798 "insn_mwait: xor %eax, %eax; xor %ecx, %ecx; mwait;ret\n\t" 799 "insn_rdpmc: xor %ecx, %ecx; rdpmc;ret\n\t" 800 "insn_rdtsc: rdtsc;ret\n\t" 801 "insn_cr3_load: mov cr3,%rax; mov %rax,%cr3;ret\n\t" 802 "insn_cr3_store: mov %cr3,%rax;ret\n\t" 803 "insn_cr8_load: xor %eax, %eax; mov %rax,%cr8;ret\n\t" 804 "insn_cr8_store: mov %cr8,%rax;ret\n\t" 805 "insn_monitor: xor %eax, %eax; xor %ecx, %ecx; xor %edx, %edx; monitor;ret\n\t" 806 "insn_pause: pause;ret\n\t" 807 "insn_wbinvd: wbinvd;ret\n\t" 808 "insn_cpuid: mov $10, %eax; cpuid;ret\n\t" 809 "insn_invd: invd;ret\n\t" 810 "insn_sgdt: sgdt gdt_descr;ret\n\t" 811 "insn_lgdt: lgdt gdt_descr;ret\n\t" 812 "insn_sidt: sidt idt_descr;ret\n\t" 813 "insn_lidt: lidt idt_descr;ret\n\t" 814 "insn_sldt: sldt %ax;ret\n\t" 815 "insn_lldt: xor %eax, %eax; lldt %ax;ret\n\t" 816 "insn_str: str %ax;ret\n\t" 817 "insn_rdrand: rdrand %rax;ret\n\t" 818 "insn_rdseed: rdseed %rax;ret\n\t" 819 ); 820 extern void insn_hlt(void); 821 extern void insn_invlpg(void); 822 extern void insn_mwait(void); 823 extern void insn_rdpmc(void); 824 extern void insn_rdtsc(void); 825 extern void insn_cr3_load(void); 826 extern void insn_cr3_store(void); 827 extern void insn_cr8_load(void); 828 extern void insn_cr8_store(void); 829 extern void insn_monitor(void); 830 extern void insn_pause(void); 831 extern void insn_wbinvd(void); 832 extern void insn_sgdt(void); 833 extern void insn_lgdt(void); 834 extern void insn_sidt(void); 835 extern void insn_lidt(void); 836 extern void insn_sldt(void); 837 extern void insn_lldt(void); 838 extern void insn_str(void); 839 extern void insn_cpuid(void); 840 extern void insn_invd(void); 841 extern void insn_rdrand(void); 842 extern void insn_rdseed(void); 843 844 u32 cur_insn; 845 u64 cr3; 846 847 typedef bool (*supported_fn)(void); 848 849 static bool this_cpu_has_mwait(void) 850 { 851 return this_cpu_has(X86_FEATURE_MWAIT); 852 } 853 854 struct insn_table { 855 const char *name; 856 u32 flag; 857 void (*insn_func)(void); 858 u32 type; 859 u32 reason; 860 ulong exit_qual; 861 u32 insn_info; 862 // Use FIELD_EXIT_QUAL and FIELD_INSN_INFO to define 863 // which field need to be tested, reason is always tested 864 u32 test_field; 865 const supported_fn supported_fn; 866 u8 disabled; 867 }; 868 869 /* 870 * Add more test cases of instruction intercept here. Elements in this 871 * table is: 872 * name/control flag/insn function/type/exit reason/exit qulification/ 873 * instruction info/field to test 874 * The last field defines which fields (exit_qual and insn_info) need to be 875 * tested in exit handler. If set to 0, only "reason" is checked. 876 */ 877 static struct insn_table insn_table[] = { 878 // Flags for Primary Processor-Based VM-Execution Controls 879 {"HLT", CPU_HLT, insn_hlt, INSN_CPU0, 12, 0, 0, 0}, 880 {"INVLPG", CPU_INVLPG, insn_invlpg, INSN_CPU0, 14, 881 0x12345678, 0, FIELD_EXIT_QUAL}, 882 {"MWAIT", CPU_MWAIT, insn_mwait, INSN_CPU0, 36, 0, 0, 0, this_cpu_has_mwait}, 883 {"RDPMC", CPU_RDPMC, insn_rdpmc, INSN_CPU0, 15, 0, 0, 0, this_cpu_has_pmu}, 884 {"RDTSC", CPU_RDTSC, insn_rdtsc, INSN_CPU0, 16, 0, 0, 0}, 885 {"CR3 load", CPU_CR3_LOAD, insn_cr3_load, INSN_CPU0, 28, 0x3, 0, 886 FIELD_EXIT_QUAL}, 887 {"CR3 store", CPU_CR3_STORE, insn_cr3_store, INSN_CPU0, 28, 0x13, 0, 888 FIELD_EXIT_QUAL}, 889 {"CR8 load", CPU_CR8_LOAD, insn_cr8_load, INSN_CPU0, 28, 0x8, 0, 890 FIELD_EXIT_QUAL}, 891 {"CR8 store", CPU_CR8_STORE, insn_cr8_store, INSN_CPU0, 28, 0x18, 0, 892 FIELD_EXIT_QUAL}, 893 {"MONITOR", CPU_MONITOR, insn_monitor, INSN_CPU0, 39, 0, 0, 0, this_cpu_has_mwait}, 894 {"PAUSE", CPU_PAUSE, insn_pause, INSN_CPU0, 40, 0, 0, 0}, 895 // Flags for Secondary Processor-Based VM-Execution Controls 896 {"WBINVD", CPU_WBINVD, insn_wbinvd, INSN_CPU1, 54, 0, 0, 0}, 897 {"DESC_TABLE (SGDT)", CPU_DESC_TABLE, insn_sgdt, INSN_CPU1, 46, 0, 0, 0}, 898 {"DESC_TABLE (LGDT)", CPU_DESC_TABLE, insn_lgdt, INSN_CPU1, 46, 0, 0, 0}, 899 {"DESC_TABLE (SIDT)", CPU_DESC_TABLE, insn_sidt, INSN_CPU1, 46, 0, 0, 0}, 900 {"DESC_TABLE (LIDT)", CPU_DESC_TABLE, insn_lidt, INSN_CPU1, 46, 0, 0, 0}, 901 {"DESC_TABLE (SLDT)", CPU_DESC_TABLE, insn_sldt, INSN_CPU1, 47, 0, 0, 0}, 902 {"DESC_TABLE (LLDT)", CPU_DESC_TABLE, insn_lldt, INSN_CPU1, 47, 0, 0, 0}, 903 {"DESC_TABLE (STR)", CPU_DESC_TABLE, insn_str, INSN_CPU1, 47, 0, 0, 0}, 904 /* LTR causes a #GP if done with a busy selector, so it is not tested. */ 905 {"RDRAND", CPU_RDRAND, insn_rdrand, INSN_CPU1, VMX_RDRAND, 0, 0, 0}, 906 {"RDSEED", CPU_RDSEED, insn_rdseed, INSN_CPU1, VMX_RDSEED, 0, 0, 0}, 907 // Instructions always trap 908 {"CPUID", 0, insn_cpuid, INSN_ALWAYS_TRAP, 10, 0, 0, 0}, 909 {"INVD", 0, insn_invd, INSN_ALWAYS_TRAP, 13, 0, 0, 0}, 910 // Instructions never trap 911 {NULL}, 912 }; 913 914 static int insn_intercept_init(struct vmcs *vmcs) 915 { 916 u32 ctrl_cpu, cur_insn; 917 918 ctrl_cpu = ctrl_cpu_rev[0].set | CPU_SECONDARY; 919 ctrl_cpu &= ctrl_cpu_rev[0].clr; 920 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu); 921 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu_rev[1].set); 922 cr3 = read_cr3(); 923 924 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 925 if (insn_table[cur_insn].supported_fn == NULL) 926 continue; 927 insn_table[cur_insn].disabled = !insn_table[cur_insn].supported_fn(); 928 } 929 return VMX_TEST_START; 930 } 931 932 static void insn_intercept_main(void) 933 { 934 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 935 vmx_set_test_stage(cur_insn * 2); 936 if ((insn_table[cur_insn].type == INSN_CPU0 && 937 !(ctrl_cpu_rev[0].clr & insn_table[cur_insn].flag)) || 938 (insn_table[cur_insn].type == INSN_CPU1 && 939 !(ctrl_cpu_rev[1].clr & insn_table[cur_insn].flag))) { 940 printf("\tCPU_CTRL%d.CPU_%s is not supported.\n", 941 insn_table[cur_insn].type - INSN_CPU0, 942 insn_table[cur_insn].name); 943 continue; 944 } 945 946 if (insn_table[cur_insn].disabled) { 947 printf("\tFeature required for %s is not supported.\n", 948 insn_table[cur_insn].name); 949 continue; 950 } 951 952 if ((insn_table[cur_insn].type == INSN_CPU0 && 953 !(ctrl_cpu_rev[0].set & insn_table[cur_insn].flag)) || 954 (insn_table[cur_insn].type == INSN_CPU1 && 955 !(ctrl_cpu_rev[1].set & insn_table[cur_insn].flag))) { 956 /* skip hlt, it stalls the guest and is tested below */ 957 if (insn_table[cur_insn].insn_func != insn_hlt) 958 insn_table[cur_insn].insn_func(); 959 report(vmx_get_test_stage() == cur_insn * 2, 960 "execute %s", 961 insn_table[cur_insn].name); 962 } else if (insn_table[cur_insn].type != INSN_ALWAYS_TRAP) 963 printf("\tCPU_CTRL%d.CPU_%s always traps.\n", 964 insn_table[cur_insn].type - INSN_CPU0, 965 insn_table[cur_insn].name); 966 967 vmcall(); 968 969 insn_table[cur_insn].insn_func(); 970 report(vmx_get_test_stage() == cur_insn * 2 + 1, 971 "intercept %s", 972 insn_table[cur_insn].name); 973 974 vmx_set_test_stage(cur_insn * 2 + 1); 975 vmcall(); 976 } 977 } 978 979 static int insn_intercept_exit_handler(union exit_reason exit_reason) 980 { 981 u64 guest_rip; 982 ulong exit_qual; 983 u32 insn_len; 984 u32 insn_info; 985 bool pass; 986 987 guest_rip = vmcs_read(GUEST_RIP); 988 exit_qual = vmcs_read(EXI_QUALIFICATION); 989 insn_len = vmcs_read(EXI_INST_LEN); 990 insn_info = vmcs_read(EXI_INST_INFO); 991 992 if (exit_reason.basic == VMX_VMCALL) { 993 u32 val = 0; 994 995 if (insn_table[cur_insn].type == INSN_CPU0) 996 val = vmcs_read(CPU_EXEC_CTRL0); 997 else if (insn_table[cur_insn].type == INSN_CPU1) 998 val = vmcs_read(CPU_EXEC_CTRL1); 999 1000 if (vmx_get_test_stage() & 1) 1001 val &= ~insn_table[cur_insn].flag; 1002 else 1003 val |= insn_table[cur_insn].flag; 1004 1005 if (insn_table[cur_insn].type == INSN_CPU0) 1006 vmcs_write(CPU_EXEC_CTRL0, val | ctrl_cpu_rev[0].set); 1007 else if (insn_table[cur_insn].type == INSN_CPU1) 1008 vmcs_write(CPU_EXEC_CTRL1, val | ctrl_cpu_rev[1].set); 1009 } else { 1010 pass = (cur_insn * 2 == vmx_get_test_stage()) && 1011 insn_table[cur_insn].reason == exit_reason.full; 1012 if (insn_table[cur_insn].test_field & FIELD_EXIT_QUAL && 1013 insn_table[cur_insn].exit_qual != exit_qual) 1014 pass = false; 1015 if (insn_table[cur_insn].test_field & FIELD_INSN_INFO && 1016 insn_table[cur_insn].insn_info != insn_info) 1017 pass = false; 1018 if (pass) 1019 vmx_inc_test_stage(); 1020 } 1021 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1022 return VMX_TEST_RESUME; 1023 } 1024 1025 /** 1026 * __setup_ept - Setup the VMCS fields to enable Extended Page Tables (EPT) 1027 * @hpa: Host physical address of the top-level, a.k.a. root, EPT table 1028 * @enable_ad: Whether or not to enable Access/Dirty bits for EPT entries 1029 * 1030 * Returns 0 on success, 1 on failure. 1031 * 1032 * Note that @hpa doesn't need to point at actual memory if VM-Launch is 1033 * expected to fail, e.g. setup_dummy_ept() arbitrarily passes '0' to satisfy 1034 * the various EPTP consistency checks, but doesn't ensure backing for HPA '0'. 1035 */ 1036 static int __setup_ept(u64 hpa, bool enable_ad) 1037 { 1038 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1039 !(ctrl_cpu_rev[1].clr & CPU_EPT)) { 1040 printf("\tEPT is not supported\n"); 1041 return 1; 1042 } 1043 if (!(ept_vpid.val & EPT_CAP_WB)) { 1044 printf("\tWB memtype for EPT walks not supported\n"); 1045 return 1; 1046 } 1047 if (!(ept_vpid.val & EPT_CAP_PWL4)) { 1048 printf("\tPWL4 is not supported\n"); 1049 return 1; 1050 } 1051 1052 eptp = EPT_MEM_TYPE_WB; 1053 eptp |= (3 << EPTP_PG_WALK_LEN_SHIFT); 1054 eptp |= hpa; 1055 if (enable_ad) 1056 eptp |= EPTP_AD_FLAG; 1057 1058 vmcs_write(EPTP, eptp); 1059 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0)| CPU_SECONDARY); 1060 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1)| CPU_EPT); 1061 1062 return 0; 1063 } 1064 1065 /** 1066 * setup_ept - Enable Extended Page Tables (EPT) and setup an identity map 1067 * @enable_ad: Whether or not to enable Access/Dirty bits for EPT entries 1068 * 1069 * Returns 0 on success, 1 on failure. 1070 * 1071 * This is the "real" function for setting up EPT tables, i.e. use this for 1072 * tests that need to run code in the guest with EPT enabled. 1073 */ 1074 static int setup_ept(bool enable_ad) 1075 { 1076 unsigned long end_of_memory; 1077 1078 pml4 = alloc_page(); 1079 1080 if (__setup_ept(virt_to_phys(pml4), enable_ad)) 1081 return 1; 1082 1083 end_of_memory = fwcfg_get_u64(FW_CFG_RAM_SIZE); 1084 if (end_of_memory < (1ul << 32)) 1085 end_of_memory = (1ul << 32); 1086 /* Cannot use large EPT pages if we need to track EPT 1087 * accessed/dirty bits at 4K granularity. 1088 */ 1089 setup_ept_range(pml4, 0, end_of_memory, 0, 1090 !enable_ad && ept_2m_supported(), 1091 EPT_WA | EPT_RA | EPT_EA); 1092 return 0; 1093 } 1094 1095 /** 1096 * setup_dummy_ept - Enable Extended Page Tables (EPT) with a dummy root HPA 1097 * 1098 * Setup EPT using a semi-arbitrary dummy root HPA. This function is intended 1099 * for use by tests that need EPT enabled to verify dependent VMCS controls 1100 * but never expect to fully enter the guest, i.e. don't need setup the actual 1101 * EPT tables. 1102 */ 1103 static void setup_dummy_ept(void) 1104 { 1105 if (__setup_ept(0, false)) 1106 report_abort("EPT setup unexpectedly failed"); 1107 } 1108 1109 static int enable_unrestricted_guest(bool need_valid_ept) 1110 { 1111 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1112 !(ctrl_cpu_rev[1].clr & CPU_URG) || 1113 !(ctrl_cpu_rev[1].clr & CPU_EPT)) 1114 return 1; 1115 1116 if (need_valid_ept) 1117 setup_ept(false); 1118 else 1119 setup_dummy_ept(); 1120 1121 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 1122 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | CPU_URG); 1123 1124 return 0; 1125 } 1126 1127 static void ept_enable_ad_bits(void) 1128 { 1129 eptp |= EPTP_AD_FLAG; 1130 vmcs_write(EPTP, eptp); 1131 } 1132 1133 static void ept_disable_ad_bits(void) 1134 { 1135 eptp &= ~EPTP_AD_FLAG; 1136 vmcs_write(EPTP, eptp); 1137 } 1138 1139 static int ept_ad_enabled(void) 1140 { 1141 return eptp & EPTP_AD_FLAG; 1142 } 1143 1144 static void ept_enable_ad_bits_or_skip_test(void) 1145 { 1146 if (!ept_ad_bits_supported()) 1147 test_skip("EPT AD bits not supported."); 1148 ept_enable_ad_bits(); 1149 } 1150 1151 static int apic_version; 1152 1153 static int ept_init_common(bool have_ad) 1154 { 1155 int ret; 1156 struct pci_dev pcidev; 1157 1158 /* INVEPT is required by the EPT violation handler. */ 1159 if (!is_invept_type_supported(INVEPT_SINGLE)) 1160 return VMX_TEST_EXIT; 1161 1162 if (setup_ept(have_ad)) 1163 return VMX_TEST_EXIT; 1164 1165 data_page1 = alloc_page(); 1166 data_page2 = alloc_page(); 1167 *((u32 *)data_page1) = MAGIC_VAL_1; 1168 *((u32 *)data_page2) = MAGIC_VAL_2; 1169 install_ept(pml4, (unsigned long)data_page1, (unsigned long)data_page2, 1170 EPT_RA | EPT_WA | EPT_EA); 1171 1172 apic_version = apic_read(APIC_LVR); 1173 1174 ret = pci_find_dev(PCI_VENDOR_ID_REDHAT, PCI_DEVICE_ID_REDHAT_TEST); 1175 if (ret != PCIDEVADDR_INVALID) { 1176 pci_dev_init(&pcidev, ret); 1177 pci_physaddr = pcidev.resource[PCI_TESTDEV_BAR_MEM]; 1178 } 1179 1180 return VMX_TEST_START; 1181 } 1182 1183 static int ept_init(struct vmcs *vmcs) 1184 { 1185 return ept_init_common(false); 1186 } 1187 1188 static void ept_common(void) 1189 { 1190 vmx_set_test_stage(0); 1191 if (*((u32 *)data_page2) != MAGIC_VAL_1 || 1192 *((u32 *)data_page1) != MAGIC_VAL_1) 1193 report_fail("EPT basic framework - read"); 1194 else { 1195 *((u32 *)data_page2) = MAGIC_VAL_3; 1196 vmcall(); 1197 if (vmx_get_test_stage() == 1) { 1198 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1199 *((u32 *)data_page2) == MAGIC_VAL_2) 1200 report_pass("EPT basic framework"); 1201 else 1202 report_pass("EPT basic framework - remap"); 1203 } 1204 } 1205 // Test EPT Misconfigurations 1206 vmx_set_test_stage(1); 1207 vmcall(); 1208 *((u32 *)data_page1) = MAGIC_VAL_1; 1209 if (vmx_get_test_stage() != 2) { 1210 report_fail("EPT misconfigurations"); 1211 goto t1; 1212 } 1213 vmx_set_test_stage(2); 1214 vmcall(); 1215 *((u32 *)data_page1) = MAGIC_VAL_1; 1216 report(vmx_get_test_stage() == 3, "EPT misconfigurations"); 1217 t1: 1218 // Test EPT violation 1219 vmx_set_test_stage(3); 1220 vmcall(); 1221 *((u32 *)data_page1) = MAGIC_VAL_1; 1222 report(vmx_get_test_stage() == 4, "EPT violation - page permission"); 1223 // Violation caused by EPT paging structure 1224 vmx_set_test_stage(4); 1225 vmcall(); 1226 *((u32 *)data_page1) = MAGIC_VAL_2; 1227 report(vmx_get_test_stage() == 5, "EPT violation - paging structure"); 1228 1229 // MMIO Read/Write 1230 vmx_set_test_stage(5); 1231 vmcall(); 1232 1233 *(u32 volatile *)pci_physaddr; 1234 report(vmx_get_test_stage() == 6, "MMIO EPT violation - read"); 1235 1236 *(u32 volatile *)pci_physaddr = MAGIC_VAL_1; 1237 report(vmx_get_test_stage() == 7, "MMIO EPT violation - write"); 1238 } 1239 1240 static void ept_main(void) 1241 { 1242 ept_common(); 1243 1244 // Test EPT access to L1 MMIO 1245 vmx_set_test_stage(7); 1246 report(*((u32 *)0xfee00030UL) == apic_version, "EPT - MMIO access"); 1247 1248 // Test invalid operand for INVEPT 1249 vmcall(); 1250 report(vmx_get_test_stage() == 8, "EPT - unsupported INVEPT"); 1251 } 1252 1253 static bool invept_test(int type, u64 eptp) 1254 { 1255 bool ret, supported; 1256 1257 supported = ept_vpid.val & (EPT_CAP_INVEPT_SINGLE >> INVEPT_SINGLE << type); 1258 ret = __invept(type, eptp); 1259 1260 if (ret == !supported) 1261 return false; 1262 1263 if (!supported) 1264 printf("WARNING: unsupported invept passed!\n"); 1265 else 1266 printf("WARNING: invept failed!\n"); 1267 1268 return true; 1269 } 1270 1271 static int pml_exit_handler(union exit_reason exit_reason) 1272 { 1273 u16 index, count; 1274 u64 *pmlbuf = pml_log; 1275 u64 guest_rip = vmcs_read(GUEST_RIP);; 1276 u64 guest_cr3 = vmcs_read(GUEST_CR3); 1277 u32 insn_len = vmcs_read(EXI_INST_LEN); 1278 1279 switch (exit_reason.basic) { 1280 case VMX_VMCALL: 1281 switch (vmx_get_test_stage()) { 1282 case 0: 1283 index = vmcs_read(GUEST_PML_INDEX); 1284 for (count = index + 1; count < PML_INDEX; count++) { 1285 if (pmlbuf[count] == (u64)data_page2) { 1286 vmx_inc_test_stage(); 1287 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1288 break; 1289 } 1290 } 1291 break; 1292 case 1: 1293 index = vmcs_read(GUEST_PML_INDEX); 1294 /* Keep clearing the dirty bit till a overflow */ 1295 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1296 break; 1297 default: 1298 report_fail("unexpected stage, %d.", 1299 vmx_get_test_stage()); 1300 print_vmexit_info(exit_reason); 1301 return VMX_TEST_VMEXIT; 1302 } 1303 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1304 return VMX_TEST_RESUME; 1305 case VMX_PML_FULL: 1306 vmx_inc_test_stage(); 1307 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1308 return VMX_TEST_RESUME; 1309 default: 1310 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 1311 print_vmexit_info(exit_reason); 1312 } 1313 return VMX_TEST_VMEXIT; 1314 } 1315 1316 static int ept_exit_handler_common(union exit_reason exit_reason, bool have_ad) 1317 { 1318 u64 guest_rip; 1319 u64 guest_cr3; 1320 u32 insn_len; 1321 u32 exit_qual; 1322 static unsigned long data_page1_pte, data_page1_pte_pte, memaddr_pte, 1323 guest_pte_addr; 1324 1325 guest_rip = vmcs_read(GUEST_RIP); 1326 guest_cr3 = vmcs_read(GUEST_CR3); 1327 insn_len = vmcs_read(EXI_INST_LEN); 1328 exit_qual = vmcs_read(EXI_QUALIFICATION); 1329 pteval_t *ptep; 1330 switch (exit_reason.basic) { 1331 case VMX_VMCALL: 1332 switch (vmx_get_test_stage()) { 1333 case 0: 1334 check_ept_ad(pml4, guest_cr3, 1335 (unsigned long)data_page1, 1336 have_ad ? EPT_ACCESS_FLAG : 0, 1337 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1338 check_ept_ad(pml4, guest_cr3, 1339 (unsigned long)data_page2, 1340 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0, 1341 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1342 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1343 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1344 if (have_ad) 1345 invept(INVEPT_SINGLE, eptp); 1346 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1347 *((u32 *)data_page2) == MAGIC_VAL_2) { 1348 vmx_inc_test_stage(); 1349 install_ept(pml4, (unsigned long)data_page2, 1350 (unsigned long)data_page2, 1351 EPT_RA | EPT_WA | EPT_EA); 1352 } else 1353 report_fail("EPT basic framework - write"); 1354 break; 1355 case 1: 1356 install_ept(pml4, (unsigned long)data_page1, 1357 (unsigned long)data_page1, EPT_WA); 1358 invept(INVEPT_SINGLE, eptp); 1359 break; 1360 case 2: 1361 install_ept(pml4, (unsigned long)data_page1, 1362 (unsigned long)data_page1, 1363 EPT_RA | EPT_WA | EPT_EA | 1364 (2 << EPT_MEM_TYPE_SHIFT)); 1365 invept(INVEPT_SINGLE, eptp); 1366 break; 1367 case 3: 1368 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1369 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)data_page1, 1370 1, &data_page1_pte)); 1371 set_ept_pte(pml4, (unsigned long)data_page1, 1372 1, data_page1_pte & ~EPT_PRESENT); 1373 invept(INVEPT_SINGLE, eptp); 1374 break; 1375 case 4: 1376 ptep = get_pte_level((pgd_t *)guest_cr3, data_page1, /*level=*/2); 1377 guest_pte_addr = virt_to_phys(ptep) & PAGE_MASK; 1378 1379 TEST_ASSERT(get_ept_pte(pml4, guest_pte_addr, 2, &data_page1_pte_pte)); 1380 set_ept_pte(pml4, guest_pte_addr, 2, 1381 data_page1_pte_pte & ~EPT_PRESENT); 1382 invept(INVEPT_SINGLE, eptp); 1383 break; 1384 case 5: 1385 install_ept(pml4, (unsigned long)pci_physaddr, 1386 (unsigned long)pci_physaddr, 0); 1387 invept(INVEPT_SINGLE, eptp); 1388 break; 1389 case 7: 1390 if (!invept_test(0, eptp)) 1391 vmx_inc_test_stage(); 1392 break; 1393 // Should not reach here 1394 default: 1395 report_fail("ERROR - unexpected stage, %d.", 1396 vmx_get_test_stage()); 1397 print_vmexit_info(exit_reason); 1398 return VMX_TEST_VMEXIT; 1399 } 1400 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1401 return VMX_TEST_RESUME; 1402 case VMX_EPT_MISCONFIG: 1403 switch (vmx_get_test_stage()) { 1404 case 1: 1405 case 2: 1406 vmx_inc_test_stage(); 1407 install_ept(pml4, (unsigned long)data_page1, 1408 (unsigned long)data_page1, 1409 EPT_RA | EPT_WA | EPT_EA); 1410 invept(INVEPT_SINGLE, eptp); 1411 break; 1412 // Should not reach here 1413 default: 1414 report_fail("ERROR - unexpected stage, %d.", 1415 vmx_get_test_stage()); 1416 print_vmexit_info(exit_reason); 1417 return VMX_TEST_VMEXIT; 1418 } 1419 return VMX_TEST_RESUME; 1420 case VMX_EPT_VIOLATION: 1421 /* 1422 * Exit-qualifications are masked not to account for advanced 1423 * VM-exit information. Once KVM supports this feature, this 1424 * masking should be removed. 1425 */ 1426 exit_qual &= ~EPT_VLT_GUEST_MASK; 1427 1428 switch(vmx_get_test_stage()) { 1429 case 3: 1430 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1431 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1432 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1433 if (exit_qual == (EPT_VLT_WR | EPT_VLT_LADDR_VLD | 1434 EPT_VLT_PADDR)) 1435 vmx_inc_test_stage(); 1436 set_ept_pte(pml4, (unsigned long)data_page1, 1437 1, data_page1_pte | (EPT_PRESENT)); 1438 invept(INVEPT_SINGLE, eptp); 1439 break; 1440 case 4: 1441 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1442 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1443 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1444 if (exit_qual == (EPT_VLT_RD | 1445 (have_ad ? EPT_VLT_WR : 0) | 1446 EPT_VLT_LADDR_VLD)) 1447 vmx_inc_test_stage(); 1448 set_ept_pte(pml4, guest_pte_addr, 2, 1449 data_page1_pte_pte | (EPT_PRESENT)); 1450 invept(INVEPT_SINGLE, eptp); 1451 break; 1452 case 5: 1453 if (exit_qual & EPT_VLT_RD) 1454 vmx_inc_test_stage(); 1455 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1456 1, &memaddr_pte)); 1457 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA); 1458 invept(INVEPT_SINGLE, eptp); 1459 break; 1460 case 6: 1461 if (exit_qual & EPT_VLT_WR) 1462 vmx_inc_test_stage(); 1463 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1464 1, &memaddr_pte)); 1465 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA | EPT_WA); 1466 invept(INVEPT_SINGLE, eptp); 1467 break; 1468 default: 1469 // Should not reach here 1470 report_fail("ERROR : unexpected stage, %d", 1471 vmx_get_test_stage()); 1472 print_vmexit_info(exit_reason); 1473 return VMX_TEST_VMEXIT; 1474 } 1475 return VMX_TEST_RESUME; 1476 default: 1477 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 1478 print_vmexit_info(exit_reason); 1479 } 1480 return VMX_TEST_VMEXIT; 1481 } 1482 1483 static int ept_exit_handler(union exit_reason exit_reason) 1484 { 1485 return ept_exit_handler_common(exit_reason, false); 1486 } 1487 1488 static int eptad_init(struct vmcs *vmcs) 1489 { 1490 int r = ept_init_common(true); 1491 1492 if (r == VMX_TEST_EXIT) 1493 return r; 1494 1495 if (!ept_ad_bits_supported()) { 1496 printf("\tEPT A/D bits are not supported"); 1497 return VMX_TEST_EXIT; 1498 } 1499 1500 return r; 1501 } 1502 1503 static int pml_init(struct vmcs *vmcs) 1504 { 1505 u32 ctrl_cpu; 1506 int r = eptad_init(vmcs); 1507 1508 if (r == VMX_TEST_EXIT) 1509 return r; 1510 1511 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1512 !(ctrl_cpu_rev[1].clr & CPU_PML)) { 1513 printf("\tPML is not supported"); 1514 return VMX_TEST_EXIT; 1515 } 1516 1517 pml_log = alloc_page(); 1518 vmcs_write(PMLADDR, (u64)pml_log); 1519 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1520 1521 ctrl_cpu = vmcs_read(CPU_EXEC_CTRL1) | CPU_PML; 1522 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu); 1523 1524 return VMX_TEST_START; 1525 } 1526 1527 static void pml_main(void) 1528 { 1529 int count = 0; 1530 1531 vmx_set_test_stage(0); 1532 *((u32 *)data_page2) = 0x1; 1533 vmcall(); 1534 report(vmx_get_test_stage() == 1, "PML - Dirty GPA Logging"); 1535 1536 while (vmx_get_test_stage() == 1) { 1537 vmcall(); 1538 *((u32 *)data_page2) = 0x1; 1539 if (count++ > PML_INDEX) 1540 break; 1541 } 1542 report(vmx_get_test_stage() == 2, "PML Full Event"); 1543 } 1544 1545 static void eptad_main(void) 1546 { 1547 ept_common(); 1548 } 1549 1550 static int eptad_exit_handler(union exit_reason exit_reason) 1551 { 1552 return ept_exit_handler_common(exit_reason, true); 1553 } 1554 1555 #define TIMER_VECTOR 222 1556 1557 static volatile bool timer_fired; 1558 1559 static void timer_isr(isr_regs_t *regs) 1560 { 1561 timer_fired = true; 1562 apic_write(APIC_EOI, 0); 1563 } 1564 1565 static int interrupt_init(struct vmcs *vmcs) 1566 { 1567 msr_bmp_init(); 1568 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1569 handle_irq(TIMER_VECTOR, timer_isr); 1570 return VMX_TEST_START; 1571 } 1572 1573 static void interrupt_main(void) 1574 { 1575 long long start, loops; 1576 1577 vmx_set_test_stage(0); 1578 1579 apic_write(APIC_LVTT, TIMER_VECTOR); 1580 sti(); 1581 1582 apic_write(APIC_TMICT, 1); 1583 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1584 asm volatile ("nop"); 1585 report(timer_fired, "direct interrupt while running guest"); 1586 1587 apic_write(APIC_TMICT, 0); 1588 cli(); 1589 vmcall(); 1590 timer_fired = false; 1591 apic_write(APIC_TMICT, 1); 1592 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1593 asm volatile ("nop"); 1594 report(timer_fired, "intercepted interrupt while running guest"); 1595 1596 sti(); 1597 apic_write(APIC_TMICT, 0); 1598 cli(); 1599 vmcall(); 1600 timer_fired = false; 1601 start = rdtsc(); 1602 apic_write(APIC_TMICT, 1000000); 1603 1604 safe_halt(); 1605 1606 report(rdtsc() - start > 1000000 && timer_fired, 1607 "direct interrupt + hlt"); 1608 1609 apic_write(APIC_TMICT, 0); 1610 cli(); 1611 vmcall(); 1612 timer_fired = false; 1613 start = rdtsc(); 1614 apic_write(APIC_TMICT, 1000000); 1615 1616 safe_halt(); 1617 1618 report(rdtsc() - start > 10000 && timer_fired, 1619 "intercepted interrupt + hlt"); 1620 1621 apic_write(APIC_TMICT, 0); 1622 cli(); 1623 vmcall(); 1624 timer_fired = false; 1625 start = rdtsc(); 1626 apic_write(APIC_TMICT, 1000000); 1627 1628 sti_nop(); 1629 vmcall(); 1630 1631 report(rdtsc() - start > 10000 && timer_fired, 1632 "direct interrupt + activity state hlt"); 1633 1634 apic_write(APIC_TMICT, 0); 1635 cli(); 1636 vmcall(); 1637 timer_fired = false; 1638 start = rdtsc(); 1639 apic_write(APIC_TMICT, 1000000); 1640 1641 sti_nop(); 1642 vmcall(); 1643 1644 report(rdtsc() - start > 10000 && timer_fired, 1645 "intercepted interrupt + activity state hlt"); 1646 1647 apic_write(APIC_TMICT, 0); 1648 cli(); 1649 vmx_set_test_stage(7); 1650 vmcall(); 1651 timer_fired = false; 1652 apic_write(APIC_TMICT, 1); 1653 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1654 asm volatile ("nop"); 1655 report(timer_fired, 1656 "running a guest with interrupt acknowledgement set"); 1657 1658 apic_write(APIC_TMICT, 0); 1659 sti(); 1660 timer_fired = false; 1661 vmcall(); 1662 report(timer_fired, "Inject an event to a halted guest"); 1663 } 1664 1665 static int interrupt_exit_handler(union exit_reason exit_reason) 1666 { 1667 u64 guest_rip = vmcs_read(GUEST_RIP); 1668 u32 insn_len = vmcs_read(EXI_INST_LEN); 1669 1670 switch (exit_reason.basic) { 1671 case VMX_VMCALL: 1672 switch (vmx_get_test_stage()) { 1673 case 0: 1674 case 2: 1675 case 5: 1676 vmcs_write(PIN_CONTROLS, 1677 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1678 break; 1679 case 7: 1680 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_INTA); 1681 vmcs_write(PIN_CONTROLS, 1682 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1683 break; 1684 case 1: 1685 case 3: 1686 vmcs_write(PIN_CONTROLS, 1687 vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1688 break; 1689 case 4: 1690 case 6: 1691 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1692 break; 1693 1694 case 8: 1695 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1696 vmcs_write(ENT_INTR_INFO, 1697 TIMER_VECTOR | 1698 (VMX_INTR_TYPE_EXT_INTR << INTR_INFO_INTR_TYPE_SHIFT) | 1699 INTR_INFO_VALID_MASK); 1700 break; 1701 } 1702 vmx_inc_test_stage(); 1703 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1704 return VMX_TEST_RESUME; 1705 case VMX_EXTINT: 1706 if (vmcs_read(EXI_CONTROLS) & EXI_INTA) { 1707 int vector = vmcs_read(EXI_INTR_INFO) & 0xff; 1708 handle_external_interrupt(vector); 1709 } else { 1710 sti_nop_cli(); 1711 } 1712 if (vmx_get_test_stage() >= 2) 1713 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 1714 return VMX_TEST_RESUME; 1715 default: 1716 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 1717 print_vmexit_info(exit_reason); 1718 } 1719 1720 return VMX_TEST_VMEXIT; 1721 } 1722 1723 1724 static volatile int nmi_fired; 1725 1726 #define NMI_DELAY 100000000ULL 1727 1728 static void nmi_isr(isr_regs_t *regs) 1729 { 1730 nmi_fired = true; 1731 } 1732 1733 static int nmi_hlt_init(struct vmcs *vmcs) 1734 { 1735 msr_bmp_init(); 1736 handle_irq(NMI_VECTOR, nmi_isr); 1737 vmcs_write(PIN_CONTROLS, 1738 vmcs_read(PIN_CONTROLS) & ~PIN_NMI); 1739 vmcs_write(PIN_CONTROLS, 1740 vmcs_read(PIN_CONTROLS) & ~PIN_VIRT_NMI); 1741 return VMX_TEST_START; 1742 } 1743 1744 static void nmi_message_thread(void *data) 1745 { 1746 while (vmx_get_test_stage() != 1) 1747 pause(); 1748 1749 delay(NMI_DELAY); 1750 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_NMI | APIC_INT_ASSERT, id_map[0]); 1751 1752 while (vmx_get_test_stage() != 2) 1753 pause(); 1754 1755 delay(NMI_DELAY); 1756 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_NMI | APIC_INT_ASSERT, id_map[0]); 1757 } 1758 1759 static void nmi_hlt_main(void) 1760 { 1761 long long start; 1762 1763 if (cpu_count() < 2) { 1764 report_skip("%s : CPU count < 2", __func__); 1765 vmx_set_test_stage(-1); 1766 return; 1767 } 1768 1769 vmx_set_test_stage(0); 1770 on_cpu_async(1, nmi_message_thread, NULL); 1771 start = rdtsc(); 1772 vmx_set_test_stage(1); 1773 asm volatile ("hlt"); 1774 report((rdtsc() - start > NMI_DELAY) && nmi_fired, 1775 "direct NMI + hlt"); 1776 if (!nmi_fired) 1777 vmx_set_test_stage(-1); 1778 nmi_fired = false; 1779 1780 vmcall(); 1781 1782 start = rdtsc(); 1783 vmx_set_test_stage(2); 1784 asm volatile ("hlt"); 1785 report((rdtsc() - start > NMI_DELAY) && !nmi_fired, 1786 "intercepted NMI + hlt"); 1787 if (nmi_fired) { 1788 report(!nmi_fired, "intercepted NMI was dispatched"); 1789 vmx_set_test_stage(-1); 1790 return; 1791 } 1792 vmx_set_test_stage(3); 1793 } 1794 1795 static int nmi_hlt_exit_handler(union exit_reason exit_reason) 1796 { 1797 u64 guest_rip = vmcs_read(GUEST_RIP); 1798 u32 insn_len = vmcs_read(EXI_INST_LEN); 1799 1800 switch (vmx_get_test_stage()) { 1801 case 1: 1802 if (exit_reason.basic != VMX_VMCALL) { 1803 report_fail("VMEXIT not due to vmcall. Exit reason 0x%x", 1804 exit_reason.full); 1805 print_vmexit_info(exit_reason); 1806 return VMX_TEST_VMEXIT; 1807 } 1808 1809 vmcs_write(PIN_CONTROLS, 1810 vmcs_read(PIN_CONTROLS) | PIN_NMI); 1811 vmcs_write(PIN_CONTROLS, 1812 vmcs_read(PIN_CONTROLS) | PIN_VIRT_NMI); 1813 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1814 break; 1815 1816 case 2: 1817 if (exit_reason.basic != VMX_EXC_NMI) { 1818 report_fail("VMEXIT not due to NMI intercept. Exit reason 0x%x", 1819 exit_reason.full); 1820 print_vmexit_info(exit_reason); 1821 return VMX_TEST_VMEXIT; 1822 } 1823 report_pass("NMI intercept while running guest"); 1824 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 1825 break; 1826 1827 case 3: 1828 break; 1829 1830 default: 1831 return VMX_TEST_VMEXIT; 1832 } 1833 1834 if (vmx_get_test_stage() == 3) 1835 return VMX_TEST_VMEXIT; 1836 1837 return VMX_TEST_RESUME; 1838 } 1839 1840 1841 static int dbgctls_init(struct vmcs *vmcs) 1842 { 1843 u64 dr7 = 0x402; 1844 u64 zero = 0; 1845 1846 msr_bmp_init(); 1847 asm volatile( 1848 "mov %0,%%dr0\n\t" 1849 "mov %0,%%dr1\n\t" 1850 "mov %0,%%dr2\n\t" 1851 "mov %1,%%dr7\n\t" 1852 : : "r" (zero), "r" (dr7)); 1853 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1854 vmcs_write(GUEST_DR7, 0x404); 1855 vmcs_write(GUEST_DEBUGCTL, 0x2); 1856 1857 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 1858 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_SAVE_DBGCTLS); 1859 1860 return VMX_TEST_START; 1861 } 1862 1863 static void dbgctls_main(void) 1864 { 1865 u64 dr7, debugctl; 1866 1867 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1868 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1869 /* Commented out: KVM does not support DEBUGCTL so far */ 1870 (void)debugctl; 1871 report(dr7 == 0x404, "Load debug controls" /* && debugctl == 0x2 */); 1872 1873 dr7 = 0x408; 1874 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1875 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1876 1877 vmx_set_test_stage(0); 1878 vmcall(); 1879 report(vmx_get_test_stage() == 1, "Save debug controls"); 1880 1881 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS || 1882 ctrl_exit_rev.set & EXI_SAVE_DBGCTLS) { 1883 printf("\tDebug controls are always loaded/saved\n"); 1884 return; 1885 } 1886 vmx_set_test_stage(2); 1887 vmcall(); 1888 1889 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1890 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1891 /* Commented out: KVM does not support DEBUGCTL so far */ 1892 (void)debugctl; 1893 report(dr7 == 0x402, 1894 "Guest=host debug controls" /* && debugctl == 0x1 */); 1895 1896 dr7 = 0x408; 1897 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1898 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1899 1900 vmx_set_test_stage(3); 1901 vmcall(); 1902 report(vmx_get_test_stage() == 4, "Don't save debug controls"); 1903 } 1904 1905 static int dbgctls_exit_handler(union exit_reason exit_reason) 1906 { 1907 u32 insn_len = vmcs_read(EXI_INST_LEN); 1908 u64 guest_rip = vmcs_read(GUEST_RIP); 1909 u64 dr7, debugctl; 1910 1911 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1912 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1913 1914 switch (exit_reason.basic) { 1915 case VMX_VMCALL: 1916 switch (vmx_get_test_stage()) { 1917 case 0: 1918 if (dr7 == 0x400 && debugctl == 0 && 1919 vmcs_read(GUEST_DR7) == 0x408 /* && 1920 Commented out: KVM does not support DEBUGCTL so far 1921 vmcs_read(GUEST_DEBUGCTL) == 0x3 */) 1922 vmx_inc_test_stage(); 1923 break; 1924 case 2: 1925 dr7 = 0x402; 1926 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1927 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1928 vmcs_write(GUEST_DR7, 0x404); 1929 vmcs_write(GUEST_DEBUGCTL, 0x2); 1930 1931 vmcs_write(ENT_CONTROLS, 1932 vmcs_read(ENT_CONTROLS) & ~ENT_LOAD_DBGCTLS); 1933 vmcs_write(EXI_CONTROLS, 1934 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_DBGCTLS); 1935 break; 1936 case 3: 1937 if (dr7 == 0x400 && debugctl == 0 && 1938 vmcs_read(GUEST_DR7) == 0x404 /* && 1939 Commented out: KVM does not support DEBUGCTL so far 1940 vmcs_read(GUEST_DEBUGCTL) == 0x2 */) 1941 vmx_inc_test_stage(); 1942 break; 1943 } 1944 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1945 return VMX_TEST_RESUME; 1946 default: 1947 report_fail("Unknown exit reason, %d", exit_reason.full); 1948 print_vmexit_info(exit_reason); 1949 } 1950 return VMX_TEST_VMEXIT; 1951 } 1952 1953 struct vmx_msr_entry { 1954 u32 index; 1955 u32 reserved; 1956 u64 value; 1957 } __attribute__((packed)); 1958 1959 #define MSR_MAGIC 0x31415926 1960 struct vmx_msr_entry *exit_msr_store, *entry_msr_load, *exit_msr_load; 1961 1962 static int msr_switch_init(struct vmcs *vmcs) 1963 { 1964 msr_bmp_init(); 1965 exit_msr_store = alloc_page(); 1966 exit_msr_load = alloc_page(); 1967 entry_msr_load = alloc_page(); 1968 entry_msr_load[0].index = MSR_KERNEL_GS_BASE; 1969 entry_msr_load[0].value = MSR_MAGIC; 1970 1971 vmx_set_test_stage(1); 1972 vmcs_write(ENT_MSR_LD_CNT, 1); 1973 vmcs_write(ENTER_MSR_LD_ADDR, (u64)entry_msr_load); 1974 vmcs_write(EXI_MSR_ST_CNT, 1); 1975 vmcs_write(EXIT_MSR_ST_ADDR, (u64)exit_msr_store); 1976 vmcs_write(EXI_MSR_LD_CNT, 1); 1977 vmcs_write(EXIT_MSR_LD_ADDR, (u64)exit_msr_load); 1978 return VMX_TEST_START; 1979 } 1980 1981 static void msr_switch_main(void) 1982 { 1983 if (vmx_get_test_stage() == 1) { 1984 report(rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC, 1985 "VM entry MSR load"); 1986 vmx_set_test_stage(2); 1987 wrmsr(MSR_KERNEL_GS_BASE, MSR_MAGIC + 1); 1988 exit_msr_store[0].index = MSR_KERNEL_GS_BASE; 1989 exit_msr_load[0].index = MSR_KERNEL_GS_BASE; 1990 exit_msr_load[0].value = MSR_MAGIC + 2; 1991 } 1992 vmcall(); 1993 } 1994 1995 static int msr_switch_exit_handler(union exit_reason exit_reason) 1996 { 1997 if (exit_reason.basic == VMX_VMCALL && vmx_get_test_stage() == 2) { 1998 report(exit_msr_store[0].value == MSR_MAGIC + 1, 1999 "VM exit MSR store"); 2000 report(rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC + 2, 2001 "VM exit MSR load"); 2002 vmx_set_test_stage(3); 2003 entry_msr_load[0].index = MSR_FS_BASE; 2004 return VMX_TEST_RESUME; 2005 } 2006 printf("ERROR %s: unexpected stage=%u or reason=0x%x\n", 2007 __func__, vmx_get_test_stage(), exit_reason.full); 2008 return VMX_TEST_EXIT; 2009 } 2010 2011 static int msr_switch_entry_failure(struct vmentry_result *result) 2012 { 2013 if (result->vm_fail) { 2014 printf("ERROR %s: VM-Fail on %s\n", __func__, result->instr); 2015 return VMX_TEST_EXIT; 2016 } 2017 2018 if (result->exit_reason.failed_vmentry && 2019 result->exit_reason.basic == VMX_FAIL_MSR && 2020 vmx_get_test_stage() == 3) { 2021 report(vmcs_read(EXI_QUALIFICATION) == 1, 2022 "VM entry MSR load: try to load FS_BASE"); 2023 return VMX_TEST_VMEXIT; 2024 } 2025 printf("ERROR %s: unexpected stage=%u or reason=%x\n", 2026 __func__, vmx_get_test_stage(), result->exit_reason.full); 2027 return VMX_TEST_EXIT; 2028 } 2029 2030 static int vmmcall_init(struct vmcs *vmcs) 2031 { 2032 vmcs_write(EXC_BITMAP, 1 << UD_VECTOR); 2033 return VMX_TEST_START; 2034 } 2035 2036 static void vmmcall_main(void) 2037 { 2038 asm volatile( 2039 "mov $0xABCD, %%rax\n\t" 2040 "vmmcall\n\t" 2041 ::: "rax"); 2042 2043 report_fail("VMMCALL"); 2044 } 2045 2046 static int vmmcall_exit_handler(union exit_reason exit_reason) 2047 { 2048 switch (exit_reason.basic) { 2049 case VMX_VMCALL: 2050 printf("here\n"); 2051 report_fail("VMMCALL triggers #UD"); 2052 break; 2053 case VMX_EXC_NMI: 2054 report((vmcs_read(EXI_INTR_INFO) & 0xff) == UD_VECTOR, 2055 "VMMCALL triggers #UD"); 2056 break; 2057 default: 2058 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 2059 print_vmexit_info(exit_reason); 2060 } 2061 2062 return VMX_TEST_VMEXIT; 2063 } 2064 2065 static int disable_rdtscp_init(struct vmcs *vmcs) 2066 { 2067 u32 ctrl_cpu1; 2068 2069 if (ctrl_cpu_rev[0].clr & CPU_SECONDARY) { 2070 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 2071 ctrl_cpu1 &= ~CPU_RDTSCP; 2072 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 2073 } 2074 2075 return VMX_TEST_START; 2076 } 2077 2078 static void disable_rdtscp_ud_handler(struct ex_regs *regs) 2079 { 2080 switch (vmx_get_test_stage()) { 2081 case 0: 2082 report_pass("RDTSCP triggers #UD"); 2083 vmx_inc_test_stage(); 2084 regs->rip += 3; 2085 break; 2086 case 2: 2087 report_pass("RDPID triggers #UD"); 2088 vmx_inc_test_stage(); 2089 regs->rip += 4; 2090 break; 2091 } 2092 return; 2093 2094 } 2095 2096 static void disable_rdtscp_main(void) 2097 { 2098 /* Test that #UD is properly injected in L2. */ 2099 handle_exception(UD_VECTOR, disable_rdtscp_ud_handler); 2100 2101 vmx_set_test_stage(0); 2102 asm volatile("rdtscp" : : : "eax", "ecx", "edx"); 2103 vmcall(); 2104 asm volatile(".byte 0xf3, 0x0f, 0xc7, 0xf8" : : : "eax"); 2105 2106 handle_exception(UD_VECTOR, 0); 2107 vmcall(); 2108 } 2109 2110 static int disable_rdtscp_exit_handler(union exit_reason exit_reason) 2111 { 2112 switch (exit_reason.basic) { 2113 case VMX_VMCALL: 2114 switch (vmx_get_test_stage()) { 2115 case 0: 2116 report_fail("RDTSCP triggers #UD"); 2117 vmx_inc_test_stage(); 2118 /* fallthrough */ 2119 case 1: 2120 vmx_inc_test_stage(); 2121 vmcs_write(GUEST_RIP, vmcs_read(GUEST_RIP) + 3); 2122 return VMX_TEST_RESUME; 2123 case 2: 2124 report_fail("RDPID triggers #UD"); 2125 break; 2126 } 2127 break; 2128 2129 default: 2130 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 2131 print_vmexit_info(exit_reason); 2132 } 2133 return VMX_TEST_VMEXIT; 2134 } 2135 2136 static void exit_monitor_from_l2_main(void) 2137 { 2138 printf("Calling exit(0) from l2...\n"); 2139 exit(0); 2140 } 2141 2142 static int exit_monitor_from_l2_handler(union exit_reason exit_reason) 2143 { 2144 report_fail("The guest should have killed the VMM"); 2145 return VMX_TEST_EXIT; 2146 } 2147 2148 static void assert_exit_reason(u64 expected) 2149 { 2150 u64 actual = vmcs_read(EXI_REASON); 2151 2152 TEST_ASSERT_EQ_MSG(expected, actual, "Expected %s, got %s.", 2153 exit_reason_description(expected), 2154 exit_reason_description(actual)); 2155 } 2156 2157 static void skip_exit_insn(void) 2158 { 2159 u64 guest_rip = vmcs_read(GUEST_RIP); 2160 u32 insn_len = vmcs_read(EXI_INST_LEN); 2161 vmcs_write(GUEST_RIP, guest_rip + insn_len); 2162 } 2163 2164 static void skip_exit_vmcall(void) 2165 { 2166 assert_exit_reason(VMX_VMCALL); 2167 skip_exit_insn(); 2168 } 2169 2170 static void v2_null_test_guest(void) 2171 { 2172 } 2173 2174 static void v2_null_test(void) 2175 { 2176 test_set_guest(v2_null_test_guest); 2177 enter_guest(); 2178 report_pass(__func__); 2179 } 2180 2181 static void v2_multiple_entries_test_guest(void) 2182 { 2183 vmx_set_test_stage(1); 2184 vmcall(); 2185 vmx_set_test_stage(2); 2186 } 2187 2188 static void v2_multiple_entries_test(void) 2189 { 2190 test_set_guest(v2_multiple_entries_test_guest); 2191 enter_guest(); 2192 TEST_ASSERT_EQ(vmx_get_test_stage(), 1); 2193 skip_exit_vmcall(); 2194 enter_guest(); 2195 TEST_ASSERT_EQ(vmx_get_test_stage(), 2); 2196 report_pass(__func__); 2197 } 2198 2199 static int fixture_test_data = 1; 2200 2201 static void fixture_test_teardown(void *data) 2202 { 2203 *((int *) data) = 1; 2204 } 2205 2206 static void fixture_test_guest(void) 2207 { 2208 fixture_test_data++; 2209 } 2210 2211 2212 static void fixture_test_setup(void) 2213 { 2214 TEST_ASSERT_EQ_MSG(1, fixture_test_data, 2215 "fixture_test_teardown didn't run?!"); 2216 fixture_test_data = 2; 2217 test_add_teardown(fixture_test_teardown, &fixture_test_data); 2218 test_set_guest(fixture_test_guest); 2219 } 2220 2221 static void fixture_test_case1(void) 2222 { 2223 fixture_test_setup(); 2224 TEST_ASSERT_EQ(2, fixture_test_data); 2225 enter_guest(); 2226 TEST_ASSERT_EQ(3, fixture_test_data); 2227 report_pass(__func__); 2228 } 2229 2230 static void fixture_test_case2(void) 2231 { 2232 fixture_test_setup(); 2233 TEST_ASSERT_EQ(2, fixture_test_data); 2234 enter_guest(); 2235 TEST_ASSERT_EQ(3, fixture_test_data); 2236 report_pass(__func__); 2237 } 2238 2239 enum ept_access_op { 2240 OP_READ, 2241 OP_WRITE, 2242 OP_EXEC, 2243 OP_FLUSH_TLB, 2244 OP_EXIT, 2245 }; 2246 2247 static struct ept_access_test_data { 2248 unsigned long gpa; 2249 unsigned long *gva; 2250 unsigned long hpa; 2251 unsigned long *hva; 2252 enum ept_access_op op; 2253 } ept_access_test_data; 2254 2255 extern unsigned char ret42_start; 2256 extern unsigned char ret42_end; 2257 2258 /* Returns 42. */ 2259 asm( 2260 ".align 64\n" 2261 "ret42_start:\n" 2262 "mov $42, %eax\n" 2263 "ret\n" 2264 "ret42_end:\n" 2265 ); 2266 2267 static void 2268 diagnose_ept_violation_qual(u64 expected, u64 actual) 2269 { 2270 2271 #define DIAGNOSE(flag) \ 2272 do { \ 2273 if ((expected & flag) != (actual & flag)) \ 2274 printf(#flag " %sexpected\n", \ 2275 (expected & flag) ? "" : "un"); \ 2276 } while (0) 2277 2278 DIAGNOSE(EPT_VLT_RD); 2279 DIAGNOSE(EPT_VLT_WR); 2280 DIAGNOSE(EPT_VLT_FETCH); 2281 DIAGNOSE(EPT_VLT_PERM_RD); 2282 DIAGNOSE(EPT_VLT_PERM_WR); 2283 DIAGNOSE(EPT_VLT_PERM_EX); 2284 DIAGNOSE(EPT_VLT_LADDR_VLD); 2285 DIAGNOSE(EPT_VLT_PADDR); 2286 2287 #undef DIAGNOSE 2288 } 2289 2290 static void do_ept_access_op(enum ept_access_op op) 2291 { 2292 ept_access_test_data.op = op; 2293 enter_guest(); 2294 } 2295 2296 /* 2297 * Force the guest to flush its TLB (i.e., flush gva -> gpa mappings). Only 2298 * needed by tests that modify guest PTEs. 2299 */ 2300 static void ept_access_test_guest_flush_tlb(void) 2301 { 2302 do_ept_access_op(OP_FLUSH_TLB); 2303 skip_exit_vmcall(); 2304 } 2305 2306 /* 2307 * Modifies the EPT entry at @level in the mapping of @gpa. First clears the 2308 * bits in @clear then sets the bits in @set. @mkhuge transforms the entry into 2309 * a huge page. 2310 */ 2311 static unsigned long ept_twiddle(unsigned long gpa, bool mkhuge, int level, 2312 unsigned long clear, unsigned long set) 2313 { 2314 struct ept_access_test_data *data = &ept_access_test_data; 2315 unsigned long orig_pte; 2316 unsigned long pte; 2317 2318 /* Screw with the mapping at the requested level. */ 2319 TEST_ASSERT(get_ept_pte(pml4, gpa, level, &orig_pte)); 2320 pte = orig_pte; 2321 if (mkhuge) 2322 pte = (orig_pte & ~EPT_ADDR_MASK) | data->hpa | EPT_LARGE_PAGE; 2323 else 2324 pte = orig_pte; 2325 pte = (pte & ~clear) | set; 2326 set_ept_pte(pml4, gpa, level, pte); 2327 invept(INVEPT_SINGLE, eptp); 2328 2329 return orig_pte; 2330 } 2331 2332 static void ept_untwiddle(unsigned long gpa, int level, unsigned long orig_pte) 2333 { 2334 set_ept_pte(pml4, gpa, level, orig_pte); 2335 invept(INVEPT_SINGLE, eptp); 2336 } 2337 2338 static void do_ept_violation(bool leaf, enum ept_access_op op, 2339 u64 expected_qual, u64 expected_paddr) 2340 { 2341 u64 qual; 2342 2343 /* Try the access and observe the violation. */ 2344 do_ept_access_op(op); 2345 2346 assert_exit_reason(VMX_EPT_VIOLATION); 2347 2348 qual = vmcs_read(EXI_QUALIFICATION); 2349 2350 /* Mask undefined bits (which may later be defined in certain cases). */ 2351 qual &= ~(EPT_VLT_GUEST_USER | EPT_VLT_GUEST_RW | EPT_VLT_GUEST_EX | 2352 EPT_VLT_PERM_USER_EX); 2353 2354 diagnose_ept_violation_qual(expected_qual, qual); 2355 TEST_EXPECT_EQ(expected_qual, qual); 2356 2357 #if 0 2358 /* Disable for now otherwise every test will fail */ 2359 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2360 (unsigned long) ( 2361 op == OP_EXEC ? data->gva + 1 : data->gva)); 2362 #endif 2363 /* 2364 * TODO: tests that probe expected_paddr in pages other than the one at 2365 * the beginning of the 1g region. 2366 */ 2367 TEST_EXPECT_EQ(vmcs_read(INFO_PHYS_ADDR), expected_paddr); 2368 } 2369 2370 static void 2371 ept_violation_at_level_mkhuge(bool mkhuge, int level, unsigned long clear, 2372 unsigned long set, enum ept_access_op op, 2373 u64 expected_qual) 2374 { 2375 struct ept_access_test_data *data = &ept_access_test_data; 2376 unsigned long orig_pte; 2377 2378 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2379 2380 do_ept_violation(level == 1 || mkhuge, op, expected_qual, 2381 op == OP_EXEC ? data->gpa + sizeof(unsigned long) : 2382 data->gpa); 2383 2384 /* Fix the violation and resume the op loop. */ 2385 ept_untwiddle(data->gpa, level, orig_pte); 2386 enter_guest(); 2387 skip_exit_vmcall(); 2388 } 2389 2390 static void 2391 ept_violation_at_level(int level, unsigned long clear, unsigned long set, 2392 enum ept_access_op op, u64 expected_qual) 2393 { 2394 ept_violation_at_level_mkhuge(false, level, clear, set, op, 2395 expected_qual); 2396 if (ept_huge_pages_supported(level)) 2397 ept_violation_at_level_mkhuge(true, level, clear, set, op, 2398 expected_qual); 2399 } 2400 2401 static void ept_violation(unsigned long clear, unsigned long set, 2402 enum ept_access_op op, u64 expected_qual) 2403 { 2404 ept_violation_at_level(1, clear, set, op, expected_qual); 2405 ept_violation_at_level(2, clear, set, op, expected_qual); 2406 ept_violation_at_level(3, clear, set, op, expected_qual); 2407 ept_violation_at_level(4, clear, set, op, expected_qual); 2408 } 2409 2410 static void ept_access_violation(unsigned long access, enum ept_access_op op, 2411 u64 expected_qual) 2412 { 2413 ept_violation(EPT_PRESENT, access, op, 2414 expected_qual | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2415 } 2416 2417 /* 2418 * For translations that don't involve a GVA, that is physical address (paddr) 2419 * accesses, EPT violations don't set the flag EPT_VLT_PADDR. For a typical 2420 * guest memory access, the hardware does GVA -> GPA -> HPA. However, certain 2421 * translations don't involve GVAs, such as when the hardware does the guest 2422 * page table walk. For example, in translating GVA_1 -> GPA_1, the guest MMU 2423 * might try to set an A bit on a guest PTE. If the GPA_2 that the PTE resides 2424 * on isn't present in the EPT, then the EPT violation will be for GPA_2 and 2425 * the EPT_VLT_PADDR bit will be clear in the exit qualification. 2426 * 2427 * Note that paddr violations can also be triggered by loading PAE page tables 2428 * with wonky addresses. We don't test that yet. 2429 * 2430 * This function modifies the EPT entry that maps the GPA that the guest page 2431 * table entry mapping ept_access_test_data.gva resides on. 2432 * 2433 * @ept_access EPT permissions to set. Other permissions are cleared. 2434 * 2435 * @pte_ad Set the A/D bits on the guest PTE accordingly. 2436 * 2437 * @op Guest operation to perform with 2438 * ept_access_test_data.gva. 2439 * 2440 * @expect_violation 2441 * Is a violation expected during the paddr access? 2442 * 2443 * @expected_qual Expected qualification for the EPT violation. 2444 * EPT_VLT_PADDR should be clear. 2445 */ 2446 static void ept_access_paddr(unsigned long ept_access, unsigned long pte_ad, 2447 enum ept_access_op op, bool expect_violation, 2448 u64 expected_qual) 2449 { 2450 struct ept_access_test_data *data = &ept_access_test_data; 2451 unsigned long *ptep; 2452 unsigned long gpa; 2453 unsigned long orig_epte; 2454 unsigned long epte; 2455 int i; 2456 2457 /* Modify the guest PTE mapping data->gva according to @pte_ad. */ 2458 ptep = get_pte_level(current_page_table(), data->gva, /*level=*/1); 2459 TEST_ASSERT(ptep); 2460 TEST_ASSERT_EQ(*ptep & PT_ADDR_MASK, data->gpa); 2461 *ptep = (*ptep & ~PT_AD_MASK) | pte_ad; 2462 ept_access_test_guest_flush_tlb(); 2463 2464 /* 2465 * Now modify the access bits on the EPT entry for the GPA that the 2466 * guest PTE resides on. Note that by modifying a single EPT entry, 2467 * we're potentially affecting 512 guest PTEs. However, we've carefully 2468 * constructed our test such that those other 511 PTEs aren't used by 2469 * the guest: data->gva is at the beginning of a 1G huge page, thus the 2470 * PTE we're modifying is at the beginning of a 4K page and the 2471 * following 511 entries are also under our control (and not touched by 2472 * the guest). 2473 */ 2474 gpa = virt_to_phys(ptep); 2475 TEST_ASSERT_EQ(gpa & ~PAGE_MASK, 0); 2476 /* 2477 * Make sure the guest page table page is mapped with a 4K EPT entry, 2478 * otherwise our level=1 twiddling below will fail. We use the 2479 * identity map (gpa = gpa) since page tables are shared with the host. 2480 */ 2481 install_ept(pml4, gpa, gpa, EPT_PRESENT); 2482 orig_epte = ept_twiddle(gpa, /*mkhuge=*/0, /*level=*/1, 2483 /*clear=*/EPT_PRESENT, /*set=*/ept_access); 2484 2485 if (expect_violation) { 2486 do_ept_violation(/*leaf=*/true, op, 2487 expected_qual | EPT_VLT_LADDR_VLD, gpa); 2488 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2489 do_ept_access_op(op); 2490 } else { 2491 do_ept_access_op(op); 2492 if (ept_ad_enabled()) { 2493 for (i = EPT_PAGE_LEVEL; i > 0; i--) { 2494 TEST_ASSERT(get_ept_pte(pml4, gpa, i, &epte)); 2495 TEST_ASSERT(epte & EPT_ACCESS_FLAG); 2496 if (i == 1) 2497 TEST_ASSERT(epte & EPT_DIRTY_FLAG); 2498 else 2499 TEST_ASSERT_EQ(epte & EPT_DIRTY_FLAG, 0); 2500 } 2501 } 2502 2503 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2504 } 2505 2506 TEST_ASSERT(*ptep & PT_ACCESSED_MASK); 2507 if ((pte_ad & PT_DIRTY_MASK) || op == OP_WRITE) 2508 TEST_ASSERT(*ptep & PT_DIRTY_MASK); 2509 2510 skip_exit_vmcall(); 2511 } 2512 2513 static void ept_access_allowed_paddr(unsigned long ept_access, 2514 unsigned long pte_ad, 2515 enum ept_access_op op) 2516 { 2517 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/false, 2518 /*expected_qual=*/-1); 2519 } 2520 2521 static void ept_access_violation_paddr(unsigned long ept_access, 2522 unsigned long pte_ad, 2523 enum ept_access_op op, 2524 u64 expected_qual) 2525 { 2526 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/true, 2527 expected_qual); 2528 } 2529 2530 2531 static void ept_allowed_at_level_mkhuge(bool mkhuge, int level, 2532 unsigned long clear, 2533 unsigned long set, 2534 enum ept_access_op op) 2535 { 2536 struct ept_access_test_data *data = &ept_access_test_data; 2537 unsigned long orig_pte; 2538 2539 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2540 2541 /* No violation. Should proceed to vmcall. */ 2542 do_ept_access_op(op); 2543 skip_exit_vmcall(); 2544 2545 ept_untwiddle(data->gpa, level, orig_pte); 2546 } 2547 2548 static void ept_allowed_at_level(int level, unsigned long clear, 2549 unsigned long set, enum ept_access_op op) 2550 { 2551 ept_allowed_at_level_mkhuge(false, level, clear, set, op); 2552 if (ept_huge_pages_supported(level)) 2553 ept_allowed_at_level_mkhuge(true, level, clear, set, op); 2554 } 2555 2556 static void ept_allowed(unsigned long clear, unsigned long set, 2557 enum ept_access_op op) 2558 { 2559 ept_allowed_at_level(1, clear, set, op); 2560 ept_allowed_at_level(2, clear, set, op); 2561 ept_allowed_at_level(3, clear, set, op); 2562 ept_allowed_at_level(4, clear, set, op); 2563 } 2564 2565 static void ept_ignored_bit(int bit) 2566 { 2567 /* Set the bit. */ 2568 ept_allowed(0, 1ul << bit, OP_READ); 2569 ept_allowed(0, 1ul << bit, OP_WRITE); 2570 ept_allowed(0, 1ul << bit, OP_EXEC); 2571 2572 /* Clear the bit. */ 2573 ept_allowed(1ul << bit, 0, OP_READ); 2574 ept_allowed(1ul << bit, 0, OP_WRITE); 2575 ept_allowed(1ul << bit, 0, OP_EXEC); 2576 } 2577 2578 static void ept_access_allowed(unsigned long access, enum ept_access_op op) 2579 { 2580 ept_allowed(EPT_PRESENT, access, op); 2581 } 2582 2583 2584 static void ept_misconfig_at_level_mkhuge_op(bool mkhuge, int level, 2585 unsigned long clear, 2586 unsigned long set, 2587 enum ept_access_op op) 2588 { 2589 struct ept_access_test_data *data = &ept_access_test_data; 2590 unsigned long orig_pte; 2591 2592 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2593 2594 do_ept_access_op(op); 2595 assert_exit_reason(VMX_EPT_MISCONFIG); 2596 2597 /* Intel 27.2.1, "For all other VM exits, this field is cleared." */ 2598 #if 0 2599 /* broken: */ 2600 TEST_EXPECT_EQ_MSG(vmcs_read(EXI_QUALIFICATION), 0); 2601 #endif 2602 #if 0 2603 /* 2604 * broken: 2605 * According to description of exit qual for EPT violation, 2606 * EPT_VLT_LADDR_VLD indicates if GUEST_LINEAR_ADDRESS is valid. 2607 * However, I can't find anything that says GUEST_LINEAR_ADDRESS ought 2608 * to be set for msiconfig. 2609 */ 2610 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2611 (unsigned long) ( 2612 op == OP_EXEC ? data->gva + 1 : data->gva)); 2613 #endif 2614 2615 /* Fix the violation and resume the op loop. */ 2616 ept_untwiddle(data->gpa, level, orig_pte); 2617 enter_guest(); 2618 skip_exit_vmcall(); 2619 } 2620 2621 static void ept_misconfig_at_level_mkhuge(bool mkhuge, int level, 2622 unsigned long clear, 2623 unsigned long set) 2624 { 2625 /* The op shouldn't matter (read, write, exec), so try them all! */ 2626 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_READ); 2627 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_WRITE); 2628 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_EXEC); 2629 } 2630 2631 static void ept_misconfig_at_level(int level, unsigned long clear, 2632 unsigned long set) 2633 { 2634 ept_misconfig_at_level_mkhuge(false, level, clear, set); 2635 if (ept_huge_pages_supported(level)) 2636 ept_misconfig_at_level_mkhuge(true, level, clear, set); 2637 } 2638 2639 static void ept_misconfig(unsigned long clear, unsigned long set) 2640 { 2641 ept_misconfig_at_level(1, clear, set); 2642 ept_misconfig_at_level(2, clear, set); 2643 ept_misconfig_at_level(3, clear, set); 2644 ept_misconfig_at_level(4, clear, set); 2645 } 2646 2647 static void ept_access_misconfig(unsigned long access) 2648 { 2649 ept_misconfig(EPT_PRESENT, access); 2650 } 2651 2652 static void ept_reserved_bit_at_level_nohuge(int level, int bit) 2653 { 2654 /* Setting the bit causes a misconfig. */ 2655 ept_misconfig_at_level_mkhuge(false, level, 0, 1ul << bit); 2656 2657 /* Making the entry non-present turns reserved bits into ignored. */ 2658 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2659 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2660 } 2661 2662 static void ept_reserved_bit_at_level_huge(int level, int bit) 2663 { 2664 /* Setting the bit causes a misconfig. */ 2665 ept_misconfig_at_level_mkhuge(true, level, 0, 1ul << bit); 2666 2667 /* Making the entry non-present turns reserved bits into ignored. */ 2668 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2669 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2670 } 2671 2672 static void ept_reserved_bit_at_level(int level, int bit) 2673 { 2674 /* Setting the bit causes a misconfig. */ 2675 ept_misconfig_at_level(level, 0, 1ul << bit); 2676 2677 /* Making the entry non-present turns reserved bits into ignored. */ 2678 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2679 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2680 } 2681 2682 static void ept_reserved_bit(int bit) 2683 { 2684 ept_reserved_bit_at_level(1, bit); 2685 ept_reserved_bit_at_level(2, bit); 2686 ept_reserved_bit_at_level(3, bit); 2687 ept_reserved_bit_at_level(4, bit); 2688 } 2689 2690 #define PAGE_2M_ORDER 9 2691 #define PAGE_1G_ORDER 18 2692 2693 static void *get_1g_page(void) 2694 { 2695 static void *alloc; 2696 2697 if (!alloc) 2698 alloc = alloc_pages(PAGE_1G_ORDER); 2699 return alloc; 2700 } 2701 2702 static void ept_access_test_teardown(void *unused) 2703 { 2704 /* Exit the guest cleanly. */ 2705 do_ept_access_op(OP_EXIT); 2706 } 2707 2708 static void ept_access_test_guest(void) 2709 { 2710 struct ept_access_test_data *data = &ept_access_test_data; 2711 int (*code)(void) = (int (*)(void)) &data->gva[1]; 2712 2713 while (true) { 2714 switch (data->op) { 2715 case OP_READ: 2716 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_1); 2717 break; 2718 case OP_WRITE: 2719 *data->gva = MAGIC_VAL_2; 2720 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_2); 2721 *data->gva = MAGIC_VAL_1; 2722 break; 2723 case OP_EXEC: 2724 TEST_ASSERT_EQ(42, code()); 2725 break; 2726 case OP_FLUSH_TLB: 2727 write_cr3(read_cr3()); 2728 break; 2729 case OP_EXIT: 2730 return; 2731 default: 2732 TEST_ASSERT_MSG(false, "Unknown op %d", data->op); 2733 } 2734 vmcall(); 2735 } 2736 } 2737 2738 static void ept_access_test_setup(void) 2739 { 2740 struct ept_access_test_data *data = &ept_access_test_data; 2741 unsigned long npages = 1ul << PAGE_1G_ORDER; 2742 unsigned long size = npages * PAGE_SIZE; 2743 unsigned long *page_table = current_page_table(); 2744 unsigned long pte; 2745 2746 if (setup_ept(false)) 2747 test_skip("EPT not supported"); 2748 2749 /* We use data->gpa = 1 << 39 so that test data has a separate pml4 entry */ 2750 if (cpuid_maxphyaddr() < 40) 2751 test_skip("Test needs MAXPHYADDR >= 40"); 2752 2753 test_set_guest(ept_access_test_guest); 2754 test_add_teardown(ept_access_test_teardown, NULL); 2755 2756 data->hva = get_1g_page(); 2757 TEST_ASSERT(data->hva); 2758 data->hpa = virt_to_phys(data->hva); 2759 2760 data->gpa = 1ul << 39; 2761 data->gva = (void *) ALIGN((unsigned long) alloc_vpages(npages * 2), 2762 size); 2763 TEST_ASSERT(!any_present_pages(page_table, data->gva, size)); 2764 install_pages(page_table, data->gpa, size, data->gva); 2765 2766 /* 2767 * Make sure nothing's mapped here so the tests that screw with the 2768 * pml4 entry don't inadvertently break something. 2769 */ 2770 TEST_ASSERT(get_ept_pte(pml4, data->gpa, 4, &pte) && pte == 0); 2771 TEST_ASSERT(get_ept_pte(pml4, data->gpa + size - 1, 4, &pte) && pte == 0); 2772 install_ept(pml4, data->hpa, data->gpa, EPT_PRESENT); 2773 2774 data->hva[0] = MAGIC_VAL_1; 2775 memcpy(&data->hva[1], &ret42_start, &ret42_end - &ret42_start); 2776 } 2777 2778 static void ept_access_test_not_present(void) 2779 { 2780 ept_access_test_setup(); 2781 /* --- */ 2782 ept_access_violation(0, OP_READ, EPT_VLT_RD); 2783 ept_access_violation(0, OP_WRITE, EPT_VLT_WR); 2784 ept_access_violation(0, OP_EXEC, EPT_VLT_FETCH); 2785 } 2786 2787 static void ept_access_test_read_only(void) 2788 { 2789 ept_access_test_setup(); 2790 2791 /* r-- */ 2792 ept_access_allowed(EPT_RA, OP_READ); 2793 ept_access_violation(EPT_RA, OP_WRITE, EPT_VLT_WR | EPT_VLT_PERM_RD); 2794 ept_access_violation(EPT_RA, OP_EXEC, EPT_VLT_FETCH | EPT_VLT_PERM_RD); 2795 } 2796 2797 static void ept_access_test_write_only(void) 2798 { 2799 ept_access_test_setup(); 2800 /* -w- */ 2801 ept_access_misconfig(EPT_WA); 2802 } 2803 2804 static void ept_access_test_read_write(void) 2805 { 2806 ept_access_test_setup(); 2807 /* rw- */ 2808 ept_access_allowed(EPT_RA | EPT_WA, OP_READ); 2809 ept_access_allowed(EPT_RA | EPT_WA, OP_WRITE); 2810 ept_access_violation(EPT_RA | EPT_WA, OP_EXEC, 2811 EPT_VLT_FETCH | EPT_VLT_PERM_RD | EPT_VLT_PERM_WR); 2812 } 2813 2814 2815 static void ept_access_test_execute_only(void) 2816 { 2817 ept_access_test_setup(); 2818 /* --x */ 2819 if (ept_execute_only_supported()) { 2820 ept_access_violation(EPT_EA, OP_READ, 2821 EPT_VLT_RD | EPT_VLT_PERM_EX); 2822 ept_access_violation(EPT_EA, OP_WRITE, 2823 EPT_VLT_WR | EPT_VLT_PERM_EX); 2824 ept_access_allowed(EPT_EA, OP_EXEC); 2825 } else { 2826 ept_access_misconfig(EPT_EA); 2827 } 2828 } 2829 2830 static void ept_access_test_read_execute(void) 2831 { 2832 ept_access_test_setup(); 2833 /* r-x */ 2834 ept_access_allowed(EPT_RA | EPT_EA, OP_READ); 2835 ept_access_violation(EPT_RA | EPT_EA, OP_WRITE, 2836 EPT_VLT_WR | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX); 2837 ept_access_allowed(EPT_RA | EPT_EA, OP_EXEC); 2838 } 2839 2840 static void ept_access_test_write_execute(void) 2841 { 2842 ept_access_test_setup(); 2843 /* -wx */ 2844 ept_access_misconfig(EPT_WA | EPT_EA); 2845 } 2846 2847 static void ept_access_test_read_write_execute(void) 2848 { 2849 ept_access_test_setup(); 2850 /* rwx */ 2851 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_READ); 2852 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_WRITE); 2853 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_EXEC); 2854 } 2855 2856 static void ept_access_test_reserved_bits(void) 2857 { 2858 int i; 2859 int maxphyaddr; 2860 2861 ept_access_test_setup(); 2862 2863 /* Reserved bits above maxphyaddr. */ 2864 maxphyaddr = cpuid_maxphyaddr(); 2865 for (i = maxphyaddr; i <= 51; i++) { 2866 report_prefix_pushf("reserved_bit=%d", i); 2867 ept_reserved_bit(i); 2868 report_prefix_pop(); 2869 } 2870 2871 /* Level-specific reserved bits. */ 2872 ept_reserved_bit_at_level_nohuge(2, 3); 2873 ept_reserved_bit_at_level_nohuge(2, 4); 2874 ept_reserved_bit_at_level_nohuge(2, 5); 2875 ept_reserved_bit_at_level_nohuge(2, 6); 2876 /* 2M alignment. */ 2877 for (i = 12; i < 20; i++) { 2878 report_prefix_pushf("reserved_bit=%d", i); 2879 ept_reserved_bit_at_level_huge(2, i); 2880 report_prefix_pop(); 2881 } 2882 ept_reserved_bit_at_level_nohuge(3, 3); 2883 ept_reserved_bit_at_level_nohuge(3, 4); 2884 ept_reserved_bit_at_level_nohuge(3, 5); 2885 ept_reserved_bit_at_level_nohuge(3, 6); 2886 /* 1G alignment. */ 2887 for (i = 12; i < 29; i++) { 2888 report_prefix_pushf("reserved_bit=%d", i); 2889 ept_reserved_bit_at_level_huge(3, i); 2890 report_prefix_pop(); 2891 } 2892 ept_reserved_bit_at_level(4, 3); 2893 ept_reserved_bit_at_level(4, 4); 2894 ept_reserved_bit_at_level(4, 5); 2895 ept_reserved_bit_at_level(4, 6); 2896 ept_reserved_bit_at_level(4, 7); 2897 } 2898 2899 static void ept_access_test_ignored_bits(void) 2900 { 2901 ept_access_test_setup(); 2902 /* 2903 * Bits ignored at every level. Bits 8 and 9 (A and D) are ignored as 2904 * far as translation is concerned even if AD bits are enabled in the 2905 * EPTP. Bit 63 is ignored because "EPT-violation #VE" VM-execution 2906 * control is 0. 2907 */ 2908 ept_ignored_bit(8); 2909 ept_ignored_bit(9); 2910 ept_ignored_bit(10); 2911 ept_ignored_bit(11); 2912 ept_ignored_bit(52); 2913 ept_ignored_bit(53); 2914 ept_ignored_bit(54); 2915 ept_ignored_bit(55); 2916 ept_ignored_bit(56); 2917 ept_ignored_bit(57); 2918 ept_ignored_bit(58); 2919 ept_ignored_bit(59); 2920 ept_ignored_bit(60); 2921 ept_ignored_bit(61); 2922 ept_ignored_bit(62); 2923 ept_ignored_bit(63); 2924 } 2925 2926 static void ept_access_test_paddr_not_present_ad_disabled(void) 2927 { 2928 ept_access_test_setup(); 2929 ept_disable_ad_bits(); 2930 2931 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, EPT_VLT_RD); 2932 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, EPT_VLT_RD); 2933 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, EPT_VLT_RD); 2934 } 2935 2936 static void ept_access_test_paddr_not_present_ad_enabled(void) 2937 { 2938 u64 qual = EPT_VLT_RD | EPT_VLT_WR; 2939 2940 ept_access_test_setup(); 2941 ept_enable_ad_bits_or_skip_test(); 2942 2943 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, qual); 2944 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, qual); 2945 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, qual); 2946 } 2947 2948 static void ept_access_test_paddr_read_only_ad_disabled(void) 2949 { 2950 /* 2951 * When EPT AD bits are disabled, all accesses to guest paging 2952 * structures are reported separately as a read and (after 2953 * translation of the GPA to host physical address) a read+write 2954 * if the A/D bits have to be set. 2955 */ 2956 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 2957 2958 ept_access_test_setup(); 2959 ept_disable_ad_bits(); 2960 2961 /* Can't update A bit, so all accesses fail. */ 2962 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 2963 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 2964 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 2965 /* AD bits disabled, so only writes try to update the D bit. */ 2966 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ); 2967 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 2968 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC); 2969 /* Both A and D already set, so read-only is OK. */ 2970 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_READ); 2971 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_WRITE); 2972 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_EXEC); 2973 } 2974 2975 static void ept_access_test_paddr_read_only_ad_enabled(void) 2976 { 2977 /* 2978 * When EPT AD bits are enabled, all accesses to guest paging 2979 * structures are considered writes as far as EPT translation 2980 * is concerned. 2981 */ 2982 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 2983 2984 ept_access_test_setup(); 2985 ept_enable_ad_bits_or_skip_test(); 2986 2987 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 2988 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 2989 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 2990 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ, qual); 2991 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 2992 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC, qual); 2993 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_READ, qual); 2994 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_WRITE, qual); 2995 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_EXEC, qual); 2996 } 2997 2998 static void ept_access_test_paddr_read_write(void) 2999 { 3000 ept_access_test_setup(); 3001 /* Read-write access to paging structure. */ 3002 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_READ); 3003 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_WRITE); 3004 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_EXEC); 3005 } 3006 3007 static void ept_access_test_paddr_read_write_execute(void) 3008 { 3009 ept_access_test_setup(); 3010 /* RWX access to paging structure. */ 3011 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_READ); 3012 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_WRITE); 3013 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_EXEC); 3014 } 3015 3016 static void ept_access_test_paddr_read_execute_ad_disabled(void) 3017 { 3018 /* 3019 * When EPT AD bits are disabled, all accesses to guest paging 3020 * structures are reported separately as a read and (after 3021 * translation of the GPA to host physical address) a read+write 3022 * if the A/D bits have to be set. 3023 */ 3024 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3025 3026 ept_access_test_setup(); 3027 ept_disable_ad_bits(); 3028 3029 /* Can't update A bit, so all accesses fail. */ 3030 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3031 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3032 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3033 /* AD bits disabled, so only writes try to update the D bit. */ 3034 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ); 3035 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3036 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC); 3037 /* Both A and D already set, so read-only is OK. */ 3038 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ); 3039 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE); 3040 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC); 3041 } 3042 3043 static void ept_access_test_paddr_read_execute_ad_enabled(void) 3044 { 3045 /* 3046 * When EPT AD bits are enabled, all accesses to guest paging 3047 * structures are considered writes as far as EPT translation 3048 * is concerned. 3049 */ 3050 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3051 3052 ept_access_test_setup(); 3053 ept_enable_ad_bits_or_skip_test(); 3054 3055 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3056 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3057 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3058 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ, qual); 3059 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3060 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC, qual); 3061 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ, qual); 3062 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE, qual); 3063 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC, qual); 3064 } 3065 3066 static void ept_access_test_paddr_not_present_page_fault(void) 3067 { 3068 ept_access_test_setup(); 3069 /* 3070 * TODO: test no EPT violation as long as guest PF occurs. e.g., GPA is 3071 * page is read-only in EPT but GVA is also mapped read only in PT. 3072 * Thus guest page fault before host takes EPT violation for trying to 3073 * update A bit. 3074 */ 3075 } 3076 3077 static void ept_access_test_force_2m_page(void) 3078 { 3079 ept_access_test_setup(); 3080 3081 TEST_ASSERT_EQ(ept_2m_supported(), true); 3082 ept_allowed_at_level_mkhuge(true, 2, 0, 0, OP_READ); 3083 ept_violation_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_RA, OP_WRITE, 3084 EPT_VLT_WR | EPT_VLT_PERM_RD | 3085 EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 3086 ept_misconfig_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_WA); 3087 } 3088 3089 static bool invvpid_valid(u64 type, u64 vpid, u64 gla) 3090 { 3091 if (!is_invvpid_type_supported(type)) 3092 return false; 3093 3094 if (vpid >> 16) 3095 return false; 3096 3097 if (type != INVVPID_ALL && !vpid) 3098 return false; 3099 3100 if (type == INVVPID_ADDR && !is_canonical(gla)) 3101 return false; 3102 3103 return true; 3104 } 3105 3106 static void try_invvpid(u64 type, u64 vpid, u64 gla) 3107 { 3108 int rc; 3109 bool valid = invvpid_valid(type, vpid, gla); 3110 u64 expected = valid ? VMXERR_UNSUPPORTED_VMCS_COMPONENT 3111 : VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID; 3112 /* 3113 * Set VMX_INST_ERROR to VMXERR_UNVALID_VMCS_COMPONENT, so 3114 * that we can tell if it is updated by INVVPID. 3115 */ 3116 vmcs_read(~0); 3117 rc = __invvpid(type, vpid, gla); 3118 report(!rc == valid, "INVVPID type %ld VPID %lx GLA %lx %s", type, 3119 vpid, gla, 3120 valid ? "passes" : "fails"); 3121 report(vmcs_read(VMX_INST_ERROR) == expected, 3122 "After %s INVVPID, VMX_INST_ERR is %ld (actual %ld)", 3123 rc ? "failed" : "successful", 3124 expected, vmcs_read(VMX_INST_ERROR)); 3125 } 3126 3127 static inline unsigned long get_first_supported_invvpid_type(void) 3128 { 3129 u64 type = ffs(ept_vpid.val >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 3130 3131 __TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 3132 return type; 3133 } 3134 3135 static void ds_invvpid(void *data) 3136 { 3137 asm volatile("invvpid %0, %1" 3138 : 3139 : "m"(*(struct invvpid_operand *)data), 3140 "r"(get_first_supported_invvpid_type())); 3141 } 3142 3143 /* 3144 * The SS override is ignored in 64-bit mode, so we use an addressing 3145 * mode with %rsp as the base register to generate an implicit SS 3146 * reference. 3147 */ 3148 static void ss_invvpid(void *data) 3149 { 3150 asm volatile("sub %%rsp,%0; invvpid (%%rsp,%0,1), %1" 3151 : "+r"(data) 3152 : "r"(get_first_supported_invvpid_type())); 3153 } 3154 3155 static void invvpid_test_gp(void) 3156 { 3157 bool fault; 3158 3159 fault = test_for_exception(GP_VECTOR, &ds_invvpid, 3160 (void *)NONCANONICAL); 3161 report(fault, "INVVPID with non-canonical DS operand raises #GP"); 3162 } 3163 3164 static void invvpid_test_ss(void) 3165 { 3166 bool fault; 3167 3168 fault = test_for_exception(SS_VECTOR, &ss_invvpid, 3169 (void *)NONCANONICAL); 3170 report(fault, "INVVPID with non-canonical SS operand raises #SS"); 3171 } 3172 3173 static void invvpid_test_pf(void) 3174 { 3175 void *vpage = alloc_vpage(); 3176 bool fault; 3177 3178 fault = test_for_exception(PF_VECTOR, &ds_invvpid, vpage); 3179 report(fault, "INVVPID with unmapped operand raises #PF"); 3180 } 3181 3182 static void try_compat_invvpid(void *unused) 3183 { 3184 struct far_pointer32 fp = { 3185 .offset = (uintptr_t)&&invvpid, 3186 .selector = KERNEL_CS32, 3187 }; 3188 uintptr_t rsp; 3189 3190 asm volatile ("mov %%rsp, %0" : "=r"(rsp)); 3191 3192 TEST_ASSERT_MSG(fp.offset == (uintptr_t)&&invvpid, 3193 "Code address too high."); 3194 TEST_ASSERT_MSG(rsp == (u32)rsp, "Stack address too high."); 3195 3196 asm goto ("lcall *%0" : : "m" (fp) : "rax" : invvpid); 3197 return; 3198 invvpid: 3199 asm volatile (".code32;" 3200 "invvpid (%eax), %eax;" 3201 "lret;" 3202 ".code64"); 3203 __builtin_unreachable(); 3204 } 3205 3206 static void invvpid_test_compatibility_mode(void) 3207 { 3208 bool fault; 3209 3210 fault = test_for_exception(UD_VECTOR, &try_compat_invvpid, NULL); 3211 report(fault, "Compatibility mode INVVPID raises #UD"); 3212 } 3213 3214 static void invvpid_test_not_in_vmx_operation(void) 3215 { 3216 bool fault; 3217 3218 TEST_ASSERT(!vmx_off()); 3219 fault = test_for_exception(UD_VECTOR, &ds_invvpid, NULL); 3220 report(fault, "INVVPID outside of VMX operation raises #UD"); 3221 TEST_ASSERT(!vmx_on()); 3222 } 3223 3224 /* 3225 * This does not test real-address mode, virtual-8086 mode, protected mode, 3226 * or CPL > 0. 3227 */ 3228 static void invvpid_test(void) 3229 { 3230 int i; 3231 unsigned types = 0; 3232 unsigned type; 3233 3234 if (!is_vpid_supported()) 3235 test_skip("VPID not supported"); 3236 3237 if (!is_invvpid_supported()) 3238 test_skip("INVVPID not supported.\n"); 3239 3240 if (is_invvpid_type_supported(INVVPID_ADDR)) 3241 types |= 1u << INVVPID_ADDR; 3242 if (is_invvpid_type_supported(INVVPID_CONTEXT_GLOBAL)) 3243 types |= 1u << INVVPID_CONTEXT_GLOBAL; 3244 if (is_invvpid_type_supported(INVVPID_ALL)) 3245 types |= 1u << INVVPID_ALL; 3246 if (is_invvpid_type_supported(INVVPID_CONTEXT_LOCAL)) 3247 types |= 1u << INVVPID_CONTEXT_LOCAL; 3248 3249 if (!types) 3250 test_skip("No INVVPID types supported.\n"); 3251 3252 for (i = -127; i < 128; i++) 3253 try_invvpid(i, 0xffff, 0); 3254 3255 /* 3256 * VPID must not be more than 16 bits. 3257 */ 3258 for (i = 0; i < 64; i++) 3259 for (type = 0; type < 4; type++) 3260 if (types & (1u << type)) 3261 try_invvpid(type, 1ul << i, 0); 3262 3263 /* 3264 * VPID must not be zero, except for "all contexts." 3265 */ 3266 for (type = 0; type < 4; type++) 3267 if (types & (1u << type)) 3268 try_invvpid(type, 0, 0); 3269 3270 /* 3271 * The gla operand is only validated for single-address INVVPID. 3272 */ 3273 if (types & (1u << INVVPID_ADDR)) 3274 try_invvpid(INVVPID_ADDR, 0xffff, NONCANONICAL); 3275 3276 invvpid_test_gp(); 3277 invvpid_test_ss(); 3278 invvpid_test_pf(); 3279 invvpid_test_compatibility_mode(); 3280 invvpid_test_not_in_vmx_operation(); 3281 } 3282 3283 /* 3284 * Test for early VMLAUNCH failure. Returns true if VMLAUNCH makes it 3285 * at least as far as the guest-state checks. Returns false if the 3286 * VMLAUNCH fails early and execution falls through to the next 3287 * instruction. 3288 */ 3289 static bool vmlaunch_succeeds(void) 3290 { 3291 u32 exit_reason; 3292 3293 /* 3294 * Indirectly set VMX_INST_ERR to 12 ("VMREAD/VMWRITE from/to 3295 * unsupported VMCS component"). The caller can then check 3296 * to see if a failed VM-entry sets VMX_INST_ERR as expected. 3297 */ 3298 vmcs_write(~0u, 0); 3299 3300 vmcs_write(HOST_RIP, (uintptr_t)&&success); 3301 __asm__ __volatile__ goto ("vmwrite %%rsp, %0; vmlaunch" 3302 : 3303 : "r" ((u64)HOST_RSP) 3304 : "cc", "memory" 3305 : success); 3306 return false; 3307 success: 3308 exit_reason = vmcs_read(EXI_REASON); 3309 TEST_ASSERT(exit_reason == (VMX_FAIL_STATE | VMX_ENTRY_FAILURE) || 3310 exit_reason == (VMX_FAIL_MSR | VMX_ENTRY_FAILURE)); 3311 return true; 3312 } 3313 3314 /* 3315 * Try to launch the current VMCS. 3316 */ 3317 static void test_vmx_vmlaunch(u32 xerror) 3318 { 3319 bool success = vmlaunch_succeeds(); 3320 u32 vmx_inst_err; 3321 3322 report(success == !xerror, "vmlaunch %s", 3323 !xerror ? "succeeds" : "fails"); 3324 if (!success && xerror) { 3325 vmx_inst_err = vmcs_read(VMX_INST_ERROR); 3326 report(vmx_inst_err == xerror, 3327 "VMX inst error is %d (actual %d)", xerror, 3328 vmx_inst_err); 3329 } 3330 } 3331 3332 /* 3333 * Try to launch the current VMCS, and expect one of two possible 3334 * errors (or success) codes. 3335 */ 3336 static void test_vmx_vmlaunch2(u32 xerror1, u32 xerror2) 3337 { 3338 bool success = vmlaunch_succeeds(); 3339 u32 vmx_inst_err; 3340 3341 if (!xerror1 == !xerror2) 3342 report(success == !xerror1, "vmlaunch %s", 3343 !xerror1 ? "succeeds" : "fails"); 3344 3345 if (!success && (xerror1 || xerror2)) { 3346 vmx_inst_err = vmcs_read(VMX_INST_ERROR); 3347 report(vmx_inst_err == xerror1 || vmx_inst_err == xerror2, 3348 "VMX inst error is %d or %d (actual %d)", xerror1, 3349 xerror2, vmx_inst_err); 3350 } 3351 } 3352 3353 static void test_vmx_invalid_controls(void) 3354 { 3355 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_CONTROL_FIELD); 3356 } 3357 3358 static void test_vmx_valid_controls(void) 3359 { 3360 test_vmx_vmlaunch(0); 3361 } 3362 3363 /* 3364 * Test a particular value of a VM-execution control bit, if the value 3365 * is required or if the value is zero. 3366 */ 3367 static void test_rsvd_ctl_bit_value(const char *name, union vmx_ctrl_msr msr, 3368 enum Encoding encoding, unsigned bit, 3369 unsigned val) 3370 { 3371 u32 mask = 1u << bit; 3372 bool expected; 3373 u32 controls; 3374 3375 if (msr.set & mask) 3376 TEST_ASSERT(msr.clr & mask); 3377 3378 /* 3379 * We can't arbitrarily turn on a control bit, because it may 3380 * introduce dependencies on other VMCS fields. So, we only 3381 * test turning on bits that have a required setting. 3382 */ 3383 if (val && (msr.clr & mask) && !(msr.set & mask)) 3384 return; 3385 3386 report_prefix_pushf("%s %s bit %d", 3387 val ? "Set" : "Clear", name, bit); 3388 3389 controls = vmcs_read(encoding); 3390 if (val) { 3391 vmcs_write(encoding, msr.set | mask); 3392 expected = (msr.clr & mask); 3393 } else { 3394 vmcs_write(encoding, msr.set & ~mask); 3395 expected = !(msr.set & mask); 3396 } 3397 if (expected) 3398 test_vmx_valid_controls(); 3399 else 3400 test_vmx_invalid_controls(); 3401 vmcs_write(encoding, controls); 3402 report_prefix_pop(); 3403 } 3404 3405 /* 3406 * Test reserved values of a VM-execution control bit, based on the 3407 * allowed bit settings from the corresponding VMX capability MSR. 3408 */ 3409 static void test_rsvd_ctl_bit(const char *name, union vmx_ctrl_msr msr, 3410 enum Encoding encoding, unsigned bit) 3411 { 3412 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 0); 3413 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 1); 3414 } 3415 3416 /* 3417 * Reserved bits in the pin-based VM-execution controls must be set 3418 * properly. Software may consult the VMX capability MSRs to determine 3419 * the proper settings. 3420 * [Intel SDM] 3421 */ 3422 static void test_pin_based_ctls(void) 3423 { 3424 unsigned bit; 3425 3426 printf("%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PIN" : 3427 "MSR_IA32_VMX_PINBASED_CTLS", ctrl_pin_rev.val); 3428 for (bit = 0; bit < 32; bit++) 3429 test_rsvd_ctl_bit("pin-based controls", 3430 ctrl_pin_rev, PIN_CONTROLS, bit); 3431 } 3432 3433 /* 3434 * Reserved bits in the primary processor-based VM-execution controls 3435 * must be set properly. Software may consult the VMX capability MSRs 3436 * to determine the proper settings. 3437 * [Intel SDM] 3438 */ 3439 static void test_primary_processor_based_ctls(void) 3440 { 3441 unsigned bit; 3442 3443 printf("\n%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PROC" : 3444 "MSR_IA32_VMX_PROCBASED_CTLS", ctrl_cpu_rev[0].val); 3445 for (bit = 0; bit < 32; bit++) 3446 test_rsvd_ctl_bit("primary processor-based controls", 3447 ctrl_cpu_rev[0], CPU_EXEC_CTRL0, bit); 3448 } 3449 3450 /* 3451 * If the "activate secondary controls" primary processor-based 3452 * VM-execution control is 1, reserved bits in the secondary 3453 * processor-based VM-execution controls must be cleared. Software may 3454 * consult the VMX capability MSRs to determine which bits are 3455 * reserved. 3456 * If the "activate secondary controls" primary processor-based 3457 * VM-execution control is 0 (or if the processor does not support the 3458 * 1-setting of that control), no checks are performed on the 3459 * secondary processor-based VM-execution controls. 3460 * [Intel SDM] 3461 */ 3462 static void test_secondary_processor_based_ctls(void) 3463 { 3464 u32 primary; 3465 u32 secondary; 3466 unsigned bit; 3467 3468 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) 3469 return; 3470 3471 primary = vmcs_read(CPU_EXEC_CTRL0); 3472 secondary = vmcs_read(CPU_EXEC_CTRL1); 3473 3474 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3475 printf("\nMSR_IA32_VMX_PROCBASED_CTLS2: %lx\n", ctrl_cpu_rev[1].val); 3476 for (bit = 0; bit < 32; bit++) 3477 test_rsvd_ctl_bit("secondary processor-based controls", 3478 ctrl_cpu_rev[1], CPU_EXEC_CTRL1, bit); 3479 3480 /* 3481 * When the "activate secondary controls" VM-execution control 3482 * is clear, there are no checks on the secondary controls. 3483 */ 3484 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3485 vmcs_write(CPU_EXEC_CTRL1, ~0); 3486 report(vmlaunch_succeeds(), 3487 "Secondary processor-based controls ignored"); 3488 vmcs_write(CPU_EXEC_CTRL1, secondary); 3489 vmcs_write(CPU_EXEC_CTRL0, primary); 3490 } 3491 3492 static void try_cr3_target_count(unsigned i, unsigned max) 3493 { 3494 report_prefix_pushf("CR3 target count 0x%x", i); 3495 vmcs_write(CR3_TARGET_COUNT, i); 3496 if (i <= max) 3497 test_vmx_valid_controls(); 3498 else 3499 test_vmx_invalid_controls(); 3500 report_prefix_pop(); 3501 } 3502 3503 /* 3504 * The CR3-target count must not be greater than 4. Future processors 3505 * may support a different number of CR3-target values. Software 3506 * should read the VMX capability MSR IA32_VMX_MISC to determine the 3507 * number of values supported. 3508 * [Intel SDM] 3509 */ 3510 static void test_cr3_targets(void) 3511 { 3512 unsigned supported_targets = (rdmsr(MSR_IA32_VMX_MISC) >> 16) & 0x1ff; 3513 u32 cr3_targets = vmcs_read(CR3_TARGET_COUNT); 3514 unsigned i; 3515 3516 printf("\nSupported CR3 targets: %d\n", supported_targets); 3517 TEST_ASSERT(supported_targets <= 256); 3518 3519 try_cr3_target_count(-1u, supported_targets); 3520 try_cr3_target_count(0x80000000, supported_targets); 3521 try_cr3_target_count(0x7fffffff, supported_targets); 3522 for (i = 0; i <= supported_targets + 1; i++) 3523 try_cr3_target_count(i, supported_targets); 3524 vmcs_write(CR3_TARGET_COUNT, cr3_targets); 3525 3526 /* VMWRITE to nonexistent target fields should fail. */ 3527 for (i = supported_targets; i < 256; i++) 3528 TEST_ASSERT(vmcs_write(CR3_TARGET_0 + i*2, 0)); 3529 } 3530 3531 /* 3532 * Test a particular address setting in the VMCS 3533 */ 3534 static void test_vmcs_addr(const char *name, 3535 enum Encoding encoding, 3536 u64 align, 3537 bool ignored, 3538 bool skip_beyond_mapped_ram, 3539 u64 addr) 3540 { 3541 report_prefix_pushf("%s = %lx", name, addr); 3542 vmcs_write(encoding, addr); 3543 if (skip_beyond_mapped_ram && 3544 addr > fwcfg_get_u64(FW_CFG_RAM_SIZE) - align && 3545 addr < (1ul << cpuid_maxphyaddr())) 3546 printf("Skipping physical address beyond mapped RAM\n"); 3547 else if (ignored || (IS_ALIGNED(addr, align) && 3548 addr < (1ul << cpuid_maxphyaddr()))) 3549 test_vmx_valid_controls(); 3550 else 3551 test_vmx_invalid_controls(); 3552 report_prefix_pop(); 3553 } 3554 3555 /* 3556 * Test interesting values for a VMCS address 3557 */ 3558 static void test_vmcs_addr_values(const char *name, 3559 enum Encoding encoding, 3560 u64 align, 3561 bool ignored, 3562 bool skip_beyond_mapped_ram, 3563 u32 bit_start, u32 bit_end) 3564 { 3565 unsigned i; 3566 u64 orig_val = vmcs_read(encoding); 3567 3568 for (i = bit_start; i <= bit_end; i++) 3569 test_vmcs_addr(name, encoding, align, ignored, 3570 skip_beyond_mapped_ram, 1ul << i); 3571 3572 test_vmcs_addr(name, encoding, align, ignored, 3573 skip_beyond_mapped_ram, PAGE_SIZE - 1); 3574 test_vmcs_addr(name, encoding, align, ignored, 3575 skip_beyond_mapped_ram, PAGE_SIZE); 3576 test_vmcs_addr(name, encoding, align, ignored, 3577 skip_beyond_mapped_ram, 3578 (1ul << cpuid_maxphyaddr()) - PAGE_SIZE); 3579 test_vmcs_addr(name, encoding, align, ignored, 3580 skip_beyond_mapped_ram, -1ul); 3581 3582 vmcs_write(encoding, orig_val); 3583 } 3584 3585 /* 3586 * Test a physical address reference in the VMCS, when the corresponding 3587 * feature is enabled and when the corresponding feature is disabled. 3588 */ 3589 static void test_vmcs_addr_reference(u32 control_bit, enum Encoding field, 3590 const char *field_name, 3591 const char *control_name, u64 align, 3592 bool skip_beyond_mapped_ram, 3593 bool control_primary) 3594 { 3595 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 3596 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 3597 u64 page_addr; 3598 3599 if (control_primary) { 3600 if (!(ctrl_cpu_rev[0].clr & control_bit)) 3601 return; 3602 } else { 3603 if (!(ctrl_cpu_rev[1].clr & control_bit)) 3604 return; 3605 } 3606 3607 page_addr = vmcs_read(field); 3608 3609 report_prefix_pushf("%s enabled", control_name); 3610 if (control_primary) { 3611 vmcs_write(CPU_EXEC_CTRL0, primary | control_bit); 3612 } else { 3613 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3614 vmcs_write(CPU_EXEC_CTRL1, secondary | control_bit); 3615 } 3616 3617 test_vmcs_addr_values(field_name, field, align, false, 3618 skip_beyond_mapped_ram, 0, 63); 3619 report_prefix_pop(); 3620 3621 report_prefix_pushf("%s disabled", control_name); 3622 if (control_primary) { 3623 vmcs_write(CPU_EXEC_CTRL0, primary & ~control_bit); 3624 } else { 3625 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3626 vmcs_write(CPU_EXEC_CTRL1, secondary & ~control_bit); 3627 } 3628 3629 test_vmcs_addr_values(field_name, field, align, true, false, 0, 63); 3630 report_prefix_pop(); 3631 3632 vmcs_write(field, page_addr); 3633 vmcs_write(CPU_EXEC_CTRL0, primary); 3634 vmcs_write(CPU_EXEC_CTRL1, secondary); 3635 } 3636 3637 /* 3638 * If the "use I/O bitmaps" VM-execution control is 1, bits 11:0 of 3639 * each I/O-bitmap address must be 0. Neither address should set any 3640 * bits beyond the processor's physical-address width. 3641 * [Intel SDM] 3642 */ 3643 static void test_io_bitmaps(void) 3644 { 3645 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_A, 3646 "I/O bitmap A", "Use I/O bitmaps", 3647 PAGE_SIZE, false, true); 3648 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_B, 3649 "I/O bitmap B", "Use I/O bitmaps", 3650 PAGE_SIZE, false, true); 3651 } 3652 3653 /* 3654 * If the "use MSR bitmaps" VM-execution control is 1, bits 11:0 of 3655 * the MSR-bitmap address must be 0. The address should not set any 3656 * bits beyond the processor's physical-address width. 3657 * [Intel SDM] 3658 */ 3659 static void test_msr_bitmap(void) 3660 { 3661 test_vmcs_addr_reference(CPU_MSR_BITMAP, MSR_BITMAP, 3662 "MSR bitmap", "Use MSR bitmaps", 3663 PAGE_SIZE, false, true); 3664 } 3665 3666 /* 3667 * If the "use TPR shadow" VM-execution control is 1, the virtual-APIC 3668 * address must satisfy the following checks: 3669 * - Bits 11:0 of the address must be 0. 3670 * - The address should not set any bits beyond the processor's 3671 * physical-address width. 3672 * [Intel SDM] 3673 */ 3674 static void test_apic_virt_addr(void) 3675 { 3676 /* 3677 * Ensure the processor will never use the virtual-APIC page, since 3678 * we will point it to invalid RAM. Otherwise KVM is puzzled about 3679 * what we're trying to achieve and fails vmentry. 3680 */ 3681 u32 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 3682 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0 | CPU_CR8_LOAD | CPU_CR8_STORE); 3683 test_vmcs_addr_reference(CPU_TPR_SHADOW, APIC_VIRT_ADDR, 3684 "virtual-APIC address", "Use TPR shadow", 3685 PAGE_SIZE, false, true); 3686 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 3687 } 3688 3689 /* 3690 * If the "virtualize APIC-accesses" VM-execution control is 1, the 3691 * APIC-access address must satisfy the following checks: 3692 * - Bits 11:0 of the address must be 0. 3693 * - The address should not set any bits beyond the processor's 3694 * physical-address width. 3695 * [Intel SDM] 3696 */ 3697 static void test_apic_access_addr(void) 3698 { 3699 void *apic_access_page = alloc_page(); 3700 3701 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_page)); 3702 3703 test_vmcs_addr_reference(CPU_VIRT_APIC_ACCESSES, APIC_ACCS_ADDR, 3704 "APIC-access address", 3705 "virtualize APIC-accesses", PAGE_SIZE, 3706 true, false); 3707 } 3708 3709 static bool set_bit_pattern(u8 mask, u32 *secondary) 3710 { 3711 u8 i; 3712 bool flag = false; 3713 u32 test_bits[3] = { 3714 CPU_VIRT_X2APIC, 3715 CPU_APIC_REG_VIRT, 3716 CPU_VINTD 3717 }; 3718 3719 for (i = 0; i < ARRAY_SIZE(test_bits); i++) { 3720 if ((mask & (1u << i)) && 3721 (ctrl_cpu_rev[1].clr & test_bits[i])) { 3722 *secondary |= test_bits[i]; 3723 flag = true; 3724 } 3725 } 3726 3727 return (flag); 3728 } 3729 3730 /* 3731 * If the "use TPR shadow" VM-execution control is 0, the following 3732 * VM-execution controls must also be 0: 3733 * - virtualize x2APIC mode 3734 * - APIC-register virtualization 3735 * - virtual-interrupt delivery 3736 * [Intel SDM] 3737 * 3738 * 2. If the "virtualize x2APIC mode" VM-execution control is 1, the 3739 * "virtualize APIC accesses" VM-execution control must be 0. 3740 * [Intel SDM] 3741 */ 3742 static void test_apic_virtual_ctls(void) 3743 { 3744 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3745 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3746 u32 primary = saved_primary; 3747 u32 secondary = saved_secondary; 3748 bool is_ctrl_valid = false; 3749 char str[10] = "disabled"; 3750 u8 i = 0, j; 3751 3752 /* 3753 * First test 3754 */ 3755 if (!((ctrl_cpu_rev[0].clr & (CPU_SECONDARY | CPU_TPR_SHADOW)) == 3756 (CPU_SECONDARY | CPU_TPR_SHADOW))) 3757 return; 3758 3759 primary |= CPU_SECONDARY; 3760 primary &= ~CPU_TPR_SHADOW; 3761 vmcs_write(CPU_EXEC_CTRL0, primary); 3762 3763 while (1) { 3764 for (j = 1; j < 8; j++) { 3765 secondary &= ~(CPU_VIRT_X2APIC | CPU_APIC_REG_VIRT | CPU_VINTD); 3766 if (primary & CPU_TPR_SHADOW) { 3767 is_ctrl_valid = true; 3768 } else { 3769 if (! set_bit_pattern(j, &secondary)) 3770 is_ctrl_valid = true; 3771 else 3772 is_ctrl_valid = false; 3773 } 3774 3775 vmcs_write(CPU_EXEC_CTRL1, secondary); 3776 report_prefix_pushf("Use TPR shadow %s, virtualize x2APIC mode %s, APIC-register virtualization %s, virtual-interrupt delivery %s", 3777 str, (secondary & CPU_VIRT_X2APIC) ? "enabled" : "disabled", (secondary & CPU_APIC_REG_VIRT) ? "enabled" : "disabled", (secondary & CPU_VINTD) ? "enabled" : "disabled"); 3778 if (is_ctrl_valid) 3779 test_vmx_valid_controls(); 3780 else 3781 test_vmx_invalid_controls(); 3782 report_prefix_pop(); 3783 } 3784 3785 if (i == 1) 3786 break; 3787 i++; 3788 3789 primary |= CPU_TPR_SHADOW; 3790 vmcs_write(CPU_EXEC_CTRL0, primary); 3791 strcpy(str, "enabled"); 3792 } 3793 3794 /* 3795 * Second test 3796 */ 3797 u32 apic_virt_ctls = (CPU_VIRT_X2APIC | CPU_VIRT_APIC_ACCESSES); 3798 3799 primary = saved_primary; 3800 secondary = saved_secondary; 3801 if (!((ctrl_cpu_rev[1].clr & apic_virt_ctls) == apic_virt_ctls)) 3802 return; 3803 3804 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3805 secondary &= ~CPU_VIRT_APIC_ACCESSES; 3806 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_X2APIC); 3807 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access disabled"); 3808 test_vmx_valid_controls(); 3809 report_prefix_pop(); 3810 3811 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_APIC_ACCESSES); 3812 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access enabled"); 3813 test_vmx_valid_controls(); 3814 report_prefix_pop(); 3815 3816 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_X2APIC); 3817 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access enabled"); 3818 test_vmx_invalid_controls(); 3819 report_prefix_pop(); 3820 3821 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_APIC_ACCESSES); 3822 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access disabled"); 3823 test_vmx_valid_controls(); 3824 report_prefix_pop(); 3825 3826 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3827 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3828 } 3829 3830 /* 3831 * If the "virtual-interrupt delivery" VM-execution control is 1, the 3832 * "external-interrupt exiting" VM-execution control must be 1. 3833 * [Intel SDM] 3834 */ 3835 static void test_virtual_intr_ctls(void) 3836 { 3837 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3838 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3839 u32 saved_pin = vmcs_read(PIN_CONTROLS); 3840 u32 primary = saved_primary; 3841 u32 secondary = saved_secondary; 3842 u32 pin = saved_pin; 3843 3844 if (!((ctrl_cpu_rev[1].clr & CPU_VINTD) && 3845 (ctrl_pin_rev.clr & PIN_EXTINT))) 3846 return; 3847 3848 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 3849 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VINTD); 3850 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 3851 report_prefix_pushf("Virtualize interrupt-delivery disabled; external-interrupt exiting disabled"); 3852 test_vmx_valid_controls(); 3853 report_prefix_pop(); 3854 3855 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VINTD); 3856 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 3857 test_vmx_invalid_controls(); 3858 report_prefix_pop(); 3859 3860 vmcs_write(PIN_CONTROLS, pin | PIN_EXTINT); 3861 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting enabled"); 3862 test_vmx_valid_controls(); 3863 report_prefix_pop(); 3864 3865 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 3866 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 3867 test_vmx_invalid_controls(); 3868 report_prefix_pop(); 3869 3870 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3871 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3872 vmcs_write(PIN_CONTROLS, saved_pin); 3873 } 3874 3875 static void test_pi_desc_addr(u64 addr, bool is_ctrl_valid) 3876 { 3877 vmcs_write(POSTED_INTR_DESC_ADDR, addr); 3878 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-descriptor-address 0x%lx", addr); 3879 if (is_ctrl_valid) 3880 test_vmx_valid_controls(); 3881 else 3882 test_vmx_invalid_controls(); 3883 report_prefix_pop(); 3884 } 3885 3886 /* 3887 * If the "process posted interrupts" VM-execution control is 1, the 3888 * following must be true: 3889 * 3890 * - The "virtual-interrupt delivery" VM-execution control is 1. 3891 * - The "acknowledge interrupt on exit" VM-exit control is 1. 3892 * - The posted-interrupt notification vector has a value in the 3893 * - range 0 - 255 (bits 15:8 are all 0). 3894 * - Bits 5:0 of the posted-interrupt descriptor address are all 0. 3895 * - The posted-interrupt descriptor address does not set any bits 3896 * beyond the processor's physical-address width. 3897 * [Intel SDM] 3898 */ 3899 static void test_posted_intr(void) 3900 { 3901 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3902 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3903 u32 saved_pin = vmcs_read(PIN_CONTROLS); 3904 u32 exit_ctl_saved = vmcs_read(EXI_CONTROLS); 3905 u32 primary = saved_primary; 3906 u32 secondary = saved_secondary; 3907 u32 pin = saved_pin; 3908 u32 exit_ctl = exit_ctl_saved; 3909 u16 vec; 3910 int i; 3911 3912 if (!((ctrl_pin_rev.clr & PIN_POST_INTR) && 3913 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 3914 (ctrl_exit_rev.clr & EXI_INTA))) 3915 return; 3916 3917 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 3918 3919 /* 3920 * Test virtual-interrupt-delivery and acknowledge-interrupt-on-exit 3921 */ 3922 pin |= PIN_POST_INTR; 3923 vmcs_write(PIN_CONTROLS, pin); 3924 secondary &= ~CPU_VINTD; 3925 vmcs_write(CPU_EXEC_CTRL1, secondary); 3926 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled"); 3927 test_vmx_invalid_controls(); 3928 report_prefix_pop(); 3929 3930 secondary |= CPU_VINTD; 3931 vmcs_write(CPU_EXEC_CTRL1, secondary); 3932 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled"); 3933 test_vmx_invalid_controls(); 3934 report_prefix_pop(); 3935 3936 exit_ctl &= ~EXI_INTA; 3937 vmcs_write(EXI_CONTROLS, exit_ctl); 3938 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit disabled"); 3939 test_vmx_invalid_controls(); 3940 report_prefix_pop(); 3941 3942 exit_ctl |= EXI_INTA; 3943 vmcs_write(EXI_CONTROLS, exit_ctl); 3944 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 3945 test_vmx_valid_controls(); 3946 report_prefix_pop(); 3947 3948 secondary &= ~CPU_VINTD; 3949 vmcs_write(CPU_EXEC_CTRL1, secondary); 3950 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled; acknowledge-interrupt-on-exit enabled"); 3951 test_vmx_invalid_controls(); 3952 report_prefix_pop(); 3953 3954 secondary |= CPU_VINTD; 3955 vmcs_write(CPU_EXEC_CTRL1, secondary); 3956 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 3957 test_vmx_valid_controls(); 3958 report_prefix_pop(); 3959 3960 /* 3961 * Test posted-interrupt notification vector 3962 */ 3963 for (i = 0; i < 8; i++) { 3964 vec = (1ul << i); 3965 vmcs_write(PINV, vec); 3966 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 3967 test_vmx_valid_controls(); 3968 report_prefix_pop(); 3969 } 3970 for (i = 8; i < 16; i++) { 3971 vec = (1ul << i); 3972 vmcs_write(PINV, vec); 3973 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 3974 test_vmx_invalid_controls(); 3975 report_prefix_pop(); 3976 } 3977 3978 vec &= ~(0xff << 8); 3979 vmcs_write(PINV, vec); 3980 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 3981 test_vmx_valid_controls(); 3982 report_prefix_pop(); 3983 3984 /* 3985 * Test posted-interrupt descriptor address 3986 */ 3987 for (i = 0; i < 6; i++) { 3988 test_pi_desc_addr(1ul << i, false); 3989 } 3990 3991 test_pi_desc_addr(0xf0, false); 3992 test_pi_desc_addr(0xff, false); 3993 test_pi_desc_addr(0x0f, false); 3994 test_pi_desc_addr(0x8000, true); 3995 test_pi_desc_addr(0x00, true); 3996 test_pi_desc_addr(0xc000, true); 3997 3998 test_vmcs_addr_values("process-posted interrupts", 3999 POSTED_INTR_DESC_ADDR, 64, 4000 false, false, 0, 63); 4001 4002 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 4003 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 4004 vmcs_write(PIN_CONTROLS, saved_pin); 4005 } 4006 4007 static void test_apic_ctls(void) 4008 { 4009 test_apic_virt_addr(); 4010 test_apic_access_addr(); 4011 test_apic_virtual_ctls(); 4012 test_virtual_intr_ctls(); 4013 test_posted_intr(); 4014 } 4015 4016 /* 4017 * If the "enable VPID" VM-execution control is 1, the value of the 4018 * of the VPID VM-execution control field must not be 0000H. 4019 * [Intel SDM] 4020 */ 4021 static void test_vpid(void) 4022 { 4023 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 4024 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 4025 u16 vpid = 0x0000; 4026 int i; 4027 4028 if (!is_vpid_supported()) { 4029 report_skip("%s : Secondary controls and/or VPID not supported", __func__); 4030 return; 4031 } 4032 4033 vmcs_write(CPU_EXEC_CTRL0, saved_primary | CPU_SECONDARY); 4034 vmcs_write(CPU_EXEC_CTRL1, saved_secondary & ~CPU_VPID); 4035 vmcs_write(VPID, vpid); 4036 report_prefix_pushf("VPID disabled; VPID value %x", vpid); 4037 test_vmx_valid_controls(); 4038 report_prefix_pop(); 4039 4040 vmcs_write(CPU_EXEC_CTRL1, saved_secondary | CPU_VPID); 4041 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 4042 test_vmx_invalid_controls(); 4043 report_prefix_pop(); 4044 4045 for (i = 0; i < 16; i++) { 4046 vpid = (short)1 << i;; 4047 vmcs_write(VPID, vpid); 4048 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 4049 test_vmx_valid_controls(); 4050 report_prefix_pop(); 4051 } 4052 4053 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 4054 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 4055 } 4056 4057 static void set_vtpr(unsigned vtpr) 4058 { 4059 *(u32 *)phys_to_virt(vmcs_read(APIC_VIRT_ADDR) + APIC_TASKPRI) = vtpr; 4060 } 4061 4062 static void try_tpr_threshold_and_vtpr(unsigned threshold, unsigned vtpr) 4063 { 4064 bool valid = true; 4065 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4066 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4067 4068 if ((primary & CPU_TPR_SHADOW) && 4069 (!(primary & CPU_SECONDARY) || 4070 !(secondary & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 4071 valid = (threshold & 0xf) <= ((vtpr >> 4) & 0xf); 4072 4073 set_vtpr(vtpr); 4074 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0x%x", 4075 threshold, (vtpr >> 4) & 0xf); 4076 if (valid) 4077 test_vmx_valid_controls(); 4078 else 4079 test_vmx_invalid_controls(); 4080 report_prefix_pop(); 4081 } 4082 4083 static void test_invalid_event_injection(void) 4084 { 4085 u32 ent_intr_info_save = vmcs_read(ENT_INTR_INFO); 4086 u32 ent_intr_error_save = vmcs_read(ENT_INTR_ERROR); 4087 u32 ent_inst_len_save = vmcs_read(ENT_INST_LEN); 4088 u32 primary_save = vmcs_read(CPU_EXEC_CTRL0); 4089 u32 secondary_save = vmcs_read(CPU_EXEC_CTRL1); 4090 u64 guest_cr0_save = vmcs_read(GUEST_CR0); 4091 u32 ent_intr_info_base = INTR_INFO_VALID_MASK; 4092 u32 ent_intr_info, ent_intr_err, ent_intr_len; 4093 u32 cnt; 4094 4095 /* Setup */ 4096 report_prefix_push("invalid event injection"); 4097 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4098 vmcs_write(ENT_INST_LEN, 0x00000001); 4099 4100 /* The field's interruption type is not set to a reserved value. */ 4101 ent_intr_info = ent_intr_info_base | INTR_TYPE_RESERVED | DE_VECTOR; 4102 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4103 "RESERVED interruption type invalid [-]", 4104 ent_intr_info); 4105 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4106 test_vmx_invalid_controls(); 4107 report_prefix_pop(); 4108 4109 ent_intr_info = ent_intr_info_base | INTR_TYPE_EXT_INTR | 4110 DE_VECTOR; 4111 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4112 "RESERVED interruption type invalid [+]", 4113 ent_intr_info); 4114 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4115 test_vmx_valid_controls(); 4116 report_prefix_pop(); 4117 4118 /* If the interruption type is other event, the vector is 0. */ 4119 ent_intr_info = ent_intr_info_base | INTR_TYPE_OTHER_EVENT | DB_VECTOR; 4120 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4121 "(OTHER EVENT && vector != 0) invalid [-]", 4122 ent_intr_info); 4123 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4124 test_vmx_invalid_controls(); 4125 report_prefix_pop(); 4126 4127 /* If the interruption type is NMI, the vector is 2 (negative case). */ 4128 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | DE_VECTOR; 4129 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4130 "(NMI && vector != 2) invalid [-]", ent_intr_info); 4131 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4132 test_vmx_invalid_controls(); 4133 report_prefix_pop(); 4134 4135 /* If the interruption type is NMI, the vector is 2 (positive case). */ 4136 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | NMI_VECTOR; 4137 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4138 "(NMI && vector == 2) valid [+]", ent_intr_info); 4139 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4140 test_vmx_valid_controls(); 4141 report_prefix_pop(); 4142 4143 /* 4144 * If the interruption type 4145 * is HW exception, the vector is at most 31. 4146 */ 4147 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 0x20; 4148 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4149 "(HW exception && vector > 31) invalid [-]", 4150 ent_intr_info); 4151 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4152 test_vmx_invalid_controls(); 4153 report_prefix_pop(); 4154 4155 /* 4156 * deliver-error-code is 1 iff either 4157 * (a) the "unrestricted guest" VM-execution control is 0 4158 * (b) CR0.PE is set. 4159 */ 4160 4161 /* Assert that unrestricted guest is disabled or unsupported */ 4162 assert(!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 4163 !(secondary_save & CPU_URG)); 4164 4165 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4166 GP_VECTOR; 4167 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4168 "error code <-> (!URG || prot_mode) [-]", 4169 ent_intr_info); 4170 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4171 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4172 test_vmx_invalid_controls(); 4173 report_prefix_pop(); 4174 4175 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4176 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4177 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4178 "error code <-> (!URG || prot_mode) [+]", 4179 ent_intr_info); 4180 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4181 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4182 test_vmx_valid_controls(); 4183 report_prefix_pop(); 4184 4185 if (enable_unrestricted_guest(false)) 4186 goto skip_unrestricted_guest; 4187 4188 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4189 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4190 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4191 "error code <-> (!URG || prot_mode) [-]", 4192 ent_intr_info); 4193 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4194 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4195 test_vmx_invalid_controls(); 4196 report_prefix_pop(); 4197 4198 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4199 GP_VECTOR; 4200 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4201 "error code <-> (!URG || prot_mode) [-]", 4202 ent_intr_info); 4203 vmcs_write(GUEST_CR0, guest_cr0_save | X86_CR0_PE); 4204 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4205 test_vmx_invalid_controls(); 4206 report_prefix_pop(); 4207 4208 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4209 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4210 4211 skip_unrestricted_guest: 4212 vmcs_write(GUEST_CR0, guest_cr0_save); 4213 4214 /* deliver-error-code is 1 iff the interruption type is HW exception */ 4215 report_prefix_push("error code <-> HW exception"); 4216 for (cnt = 0; cnt < 8; cnt++) { 4217 u32 exception_type_mask = cnt << 8; 4218 u32 deliver_error_code_mask = 4219 exception_type_mask != INTR_TYPE_HARD_EXCEPTION ? 4220 INTR_INFO_DELIVER_CODE_MASK : 0; 4221 4222 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4223 exception_type_mask | GP_VECTOR; 4224 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4225 ent_intr_info); 4226 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4227 test_vmx_invalid_controls(); 4228 report_prefix_pop(); 4229 } 4230 report_prefix_pop(); 4231 4232 /* 4233 * deliver-error-code is 1 iff the the vector 4234 * indicates an exception that would normally deliver an error code 4235 */ 4236 report_prefix_push("error code <-> vector delivers error code"); 4237 for (cnt = 0; cnt < 32; cnt++) { 4238 bool has_error_code = false; 4239 u32 deliver_error_code_mask; 4240 4241 switch (cnt) { 4242 case DF_VECTOR: 4243 case TS_VECTOR: 4244 case NP_VECTOR: 4245 case SS_VECTOR: 4246 case GP_VECTOR: 4247 case PF_VECTOR: 4248 case AC_VECTOR: 4249 has_error_code = true; 4250 case CP_VECTOR: 4251 /* Some CPUs have error code and some do not, skip */ 4252 continue; 4253 } 4254 4255 /* Negative case */ 4256 deliver_error_code_mask = has_error_code ? 4257 0 : 4258 INTR_INFO_DELIVER_CODE_MASK; 4259 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4260 INTR_TYPE_HARD_EXCEPTION | cnt; 4261 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4262 ent_intr_info); 4263 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4264 test_vmx_invalid_controls(); 4265 report_prefix_pop(); 4266 4267 /* Positive case */ 4268 deliver_error_code_mask = has_error_code ? 4269 INTR_INFO_DELIVER_CODE_MASK : 4270 0; 4271 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4272 INTR_TYPE_HARD_EXCEPTION | cnt; 4273 report_prefix_pushf("VM-entry intr info=0x%x [+]", 4274 ent_intr_info); 4275 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4276 test_vmx_valid_controls(); 4277 report_prefix_pop(); 4278 } 4279 report_prefix_pop(); 4280 4281 /* Reserved bits in the field (30:12) are 0. */ 4282 report_prefix_push("reserved bits clear"); 4283 for (cnt = 12; cnt <= 30; cnt++) { 4284 ent_intr_info = ent_intr_info_base | 4285 INTR_INFO_DELIVER_CODE_MASK | 4286 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR | 4287 (1U << cnt); 4288 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4289 ent_intr_info); 4290 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4291 test_vmx_invalid_controls(); 4292 report_prefix_pop(); 4293 } 4294 report_prefix_pop(); 4295 4296 /* 4297 * If deliver-error-code is 1 4298 * bits 31:16 of the VM-entry exception error-code field are 0. 4299 */ 4300 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4301 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4302 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4303 "VM-entry exception error code[31:16] clear", 4304 ent_intr_info); 4305 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4306 for (cnt = 16; cnt <= 31; cnt++) { 4307 ent_intr_err = 1U << cnt; 4308 report_prefix_pushf("VM-entry intr error=0x%x [-]", 4309 ent_intr_err); 4310 vmcs_write(ENT_INTR_ERROR, ent_intr_err); 4311 test_vmx_invalid_controls(); 4312 report_prefix_pop(); 4313 } 4314 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4315 report_prefix_pop(); 4316 4317 /* 4318 * If the interruption type is software interrupt, software exception, 4319 * or privileged software exception, the VM-entry instruction-length 4320 * field is in the range 0 - 15. 4321 */ 4322 4323 for (cnt = 0; cnt < 3; cnt++) { 4324 switch (cnt) { 4325 case 0: 4326 ent_intr_info = ent_intr_info_base | 4327 INTR_TYPE_SOFT_INTR; 4328 break; 4329 case 1: 4330 ent_intr_info = ent_intr_info_base | 4331 INTR_TYPE_SOFT_EXCEPTION; 4332 break; 4333 case 2: 4334 ent_intr_info = ent_intr_info_base | 4335 INTR_TYPE_PRIV_SW_EXCEPTION; 4336 break; 4337 } 4338 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4339 "VM-entry instruction-length check", 4340 ent_intr_info); 4341 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4342 4343 /* Instruction length set to -1 (0xFFFFFFFF) should fail */ 4344 ent_intr_len = -1; 4345 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4346 ent_intr_len); 4347 vmcs_write(ENT_INST_LEN, ent_intr_len); 4348 test_vmx_invalid_controls(); 4349 report_prefix_pop(); 4350 4351 /* Instruction length set to 16 should fail */ 4352 ent_intr_len = 0x00000010; 4353 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4354 ent_intr_len); 4355 vmcs_write(ENT_INST_LEN, 0x00000010); 4356 test_vmx_invalid_controls(); 4357 report_prefix_pop(); 4358 4359 report_prefix_pop(); 4360 } 4361 4362 /* Cleanup */ 4363 vmcs_write(ENT_INTR_INFO, ent_intr_info_save); 4364 vmcs_write(ENT_INTR_ERROR, ent_intr_error_save); 4365 vmcs_write(ENT_INST_LEN, ent_inst_len_save); 4366 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4367 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4368 vmcs_write(GUEST_CR0, guest_cr0_save); 4369 report_prefix_pop(); 4370 } 4371 4372 /* 4373 * Test interesting vTPR values for a given TPR threshold. 4374 */ 4375 static void test_vtpr_values(unsigned threshold) 4376 { 4377 try_tpr_threshold_and_vtpr(threshold, (threshold - 1) << 4); 4378 try_tpr_threshold_and_vtpr(threshold, threshold << 4); 4379 try_tpr_threshold_and_vtpr(threshold, (threshold + 1) << 4); 4380 } 4381 4382 static void try_tpr_threshold(unsigned threshold) 4383 { 4384 bool valid = true; 4385 4386 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4387 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4388 4389 if ((primary & CPU_TPR_SHADOW) && !((primary & CPU_SECONDARY) && 4390 (secondary & CPU_VINTD))) 4391 valid = !(threshold >> 4); 4392 4393 set_vtpr(-1); 4394 vmcs_write(TPR_THRESHOLD, threshold); 4395 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0xf", threshold); 4396 if (valid) 4397 test_vmx_valid_controls(); 4398 else 4399 test_vmx_invalid_controls(); 4400 report_prefix_pop(); 4401 4402 if (valid) 4403 test_vtpr_values(threshold); 4404 } 4405 4406 /* 4407 * Test interesting TPR threshold values. 4408 */ 4409 static void test_tpr_threshold_values(void) 4410 { 4411 unsigned i; 4412 4413 for (i = 0; i < 0x10; i++) 4414 try_tpr_threshold(i); 4415 for (i = 4; i < 32; i++) 4416 try_tpr_threshold(1u << i); 4417 try_tpr_threshold(-1u); 4418 try_tpr_threshold(0x7fffffff); 4419 } 4420 4421 /* 4422 * This test covers the following two VM entry checks: 4423 * 4424 * i) If the "use TPR shadow" VM-execution control is 1 and the 4425 * "virtual-interrupt delivery" VM-execution control is 0, bits 4426 * 31:4 of the TPR threshold VM-execution control field must 4427 be 0. 4428 * [Intel SDM] 4429 * 4430 * ii) If the "use TPR shadow" VM-execution control is 1, the 4431 * "virtual-interrupt delivery" VM-execution control is 0 4432 * and the "virtualize APIC accesses" VM-execution control 4433 * is 0, the value of bits 3:0 of the TPR threshold VM-execution 4434 * control field must not be greater than the value of bits 4435 * 7:4 of VTPR. 4436 * [Intel SDM] 4437 */ 4438 static void test_tpr_threshold(void) 4439 { 4440 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4441 u64 apic_virt_addr = vmcs_read(APIC_VIRT_ADDR); 4442 u64 threshold = vmcs_read(TPR_THRESHOLD); 4443 void *virtual_apic_page; 4444 4445 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) 4446 return; 4447 4448 virtual_apic_page = alloc_page(); 4449 memset(virtual_apic_page, 0xff, PAGE_SIZE); 4450 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 4451 4452 vmcs_write(CPU_EXEC_CTRL0, primary & ~(CPU_TPR_SHADOW | CPU_SECONDARY)); 4453 report_prefix_pushf("Use TPR shadow disabled, secondary controls disabled"); 4454 test_tpr_threshold_values(); 4455 report_prefix_pop(); 4456 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_TPR_SHADOW); 4457 report_prefix_pushf("Use TPR shadow enabled, secondary controls disabled"); 4458 test_tpr_threshold_values(); 4459 report_prefix_pop(); 4460 4461 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4462 (ctrl_cpu_rev[1].clr & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 4463 goto out; 4464 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4465 4466 if (ctrl_cpu_rev[1].clr & CPU_VINTD) { 4467 vmcs_write(CPU_EXEC_CTRL1, CPU_VINTD); 4468 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4469 test_tpr_threshold_values(); 4470 report_prefix_pop(); 4471 4472 vmcs_write(CPU_EXEC_CTRL0, 4473 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4474 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4475 test_tpr_threshold_values(); 4476 report_prefix_pop(); 4477 } 4478 4479 if (ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES) { 4480 vmcs_write(CPU_EXEC_CTRL0, 4481 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4482 vmcs_write(CPU_EXEC_CTRL1, CPU_VIRT_APIC_ACCESSES); 4483 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4484 test_tpr_threshold_values(); 4485 report_prefix_pop(); 4486 4487 vmcs_write(CPU_EXEC_CTRL0, 4488 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4489 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4490 test_tpr_threshold_values(); 4491 report_prefix_pop(); 4492 } 4493 4494 if ((ctrl_cpu_rev[1].clr & 4495 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) == 4496 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) { 4497 vmcs_write(CPU_EXEC_CTRL0, 4498 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4499 vmcs_write(CPU_EXEC_CTRL1, 4500 CPU_VINTD | CPU_VIRT_APIC_ACCESSES); 4501 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4502 test_tpr_threshold_values(); 4503 report_prefix_pop(); 4504 4505 vmcs_write(CPU_EXEC_CTRL0, 4506 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4507 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4508 test_tpr_threshold_values(); 4509 report_prefix_pop(); 4510 } 4511 4512 vmcs_write(CPU_EXEC_CTRL1, secondary); 4513 out: 4514 vmcs_write(TPR_THRESHOLD, threshold); 4515 vmcs_write(APIC_VIRT_ADDR, apic_virt_addr); 4516 vmcs_write(CPU_EXEC_CTRL0, primary); 4517 } 4518 4519 /* 4520 * This test verifies the following two vmentry checks: 4521 * 4522 * If the "NMI exiting" VM-execution control is 0, "Virtual NMIs" 4523 * VM-execution control must be 0. 4524 * [Intel SDM] 4525 * 4526 * If the "virtual NMIs" VM-execution control is 0, the "NMI-window 4527 * exiting" VM-execution control must be 0. 4528 * [Intel SDM] 4529 */ 4530 static void test_nmi_ctrls(void) 4531 { 4532 u32 pin_ctrls, cpu_ctrls0, test_pin_ctrls, test_cpu_ctrls0; 4533 4534 if ((ctrl_pin_rev.clr & (PIN_NMI | PIN_VIRT_NMI)) != 4535 (PIN_NMI | PIN_VIRT_NMI)) { 4536 report_skip("%s : NMI exiting and/or Virtual NMIs not supported", __func__); 4537 return; 4538 } 4539 4540 /* Save the controls so that we can restore them after our tests */ 4541 pin_ctrls = vmcs_read(PIN_CONTROLS); 4542 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 4543 4544 test_pin_ctrls = pin_ctrls & ~(PIN_NMI | PIN_VIRT_NMI); 4545 test_cpu_ctrls0 = cpu_ctrls0 & ~CPU_NMI_WINDOW; 4546 4547 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4548 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs disabled"); 4549 test_vmx_valid_controls(); 4550 report_prefix_pop(); 4551 4552 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_VIRT_NMI); 4553 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs enabled"); 4554 test_vmx_invalid_controls(); 4555 report_prefix_pop(); 4556 4557 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4558 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs enabled"); 4559 test_vmx_valid_controls(); 4560 report_prefix_pop(); 4561 4562 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_NMI); 4563 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs disabled"); 4564 test_vmx_valid_controls(); 4565 report_prefix_pop(); 4566 4567 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 4568 report_info("NMI-window exiting is not supported, skipping..."); 4569 goto done; 4570 } 4571 4572 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4573 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4574 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting enabled"); 4575 test_vmx_invalid_controls(); 4576 report_prefix_pop(); 4577 4578 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4579 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4580 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting disabled"); 4581 test_vmx_valid_controls(); 4582 report_prefix_pop(); 4583 4584 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4585 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4586 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting enabled"); 4587 test_vmx_valid_controls(); 4588 report_prefix_pop(); 4589 4590 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4591 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4592 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting disabled"); 4593 test_vmx_valid_controls(); 4594 report_prefix_pop(); 4595 4596 /* Restore the controls to their original values */ 4597 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 4598 done: 4599 vmcs_write(PIN_CONTROLS, pin_ctrls); 4600 } 4601 4602 static void test_eptp_ad_bit(u64 eptp, bool is_ctrl_valid) 4603 { 4604 vmcs_write(EPTP, eptp); 4605 report_prefix_pushf("Enable-EPT enabled; EPT accessed and dirty flag %s", 4606 (eptp & EPTP_AD_FLAG) ? "1": "0"); 4607 if (is_ctrl_valid) 4608 test_vmx_valid_controls(); 4609 else 4610 test_vmx_invalid_controls(); 4611 report_prefix_pop(); 4612 4613 } 4614 4615 /* 4616 * 1. If the "enable EPT" VM-execution control is 1, the "EPTP VM-execution" 4617 * control field must satisfy the following checks: 4618 * 4619 * - The EPT memory type (bits 2:0) must be a value supported by the 4620 * processor as indicated in the IA32_VMX_EPT_VPID_CAP MSR. 4621 * - Bits 5:3 (1 less than the EPT page-walk length) must indicate a 4622 * supported EPT page-walk length. 4623 * - Bit 6 (enable bit for accessed and dirty flags for EPT) must be 4624 * 0 if bit 21 of the IA32_VMX_EPT_VPID_CAP MSR is read as 0, 4625 * indicating that the processor does not support accessed and dirty 4626 * dirty flags for EPT. 4627 * - Reserved bits 11:7 and 63:N (where N is the processor's 4628 * physical-address width) must all be 0. 4629 * 4630 * 2. If the "unrestricted guest" VM-execution control is 1, the 4631 * "enable EPT" VM-execution control must also be 1. 4632 */ 4633 static void test_ept_eptp(void) 4634 { 4635 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4636 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4637 u64 eptp_saved = vmcs_read(EPTP); 4638 u32 primary = primary_saved; 4639 u32 secondary = secondary_saved; 4640 u64 eptp = eptp_saved; 4641 u32 i, maxphysaddr; 4642 u64 j, resv_bits_mask = 0; 4643 4644 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4645 (ctrl_cpu_rev[1].clr & CPU_EPT))) { 4646 report_skip("%s : \"CPU secondary\" and/or \"enable EPT\" exec control not supported", __func__); 4647 return; 4648 } 4649 4650 /* Support for 4-level EPT is mandatory. */ 4651 report(is_4_level_ept_supported(), "4-level EPT support check"); 4652 4653 primary |= CPU_SECONDARY; 4654 vmcs_write(CPU_EXEC_CTRL0, primary); 4655 secondary |= CPU_EPT; 4656 vmcs_write(CPU_EXEC_CTRL1, secondary); 4657 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4658 (3ul << EPTP_PG_WALK_LEN_SHIFT); 4659 vmcs_write(EPTP, eptp); 4660 4661 for (i = 0; i < 8; i++) { 4662 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | i; 4663 vmcs_write(EPTP, eptp); 4664 report_prefix_pushf("Enable-EPT enabled; EPT memory type %lu", 4665 eptp & EPT_MEM_TYPE_MASK); 4666 if (is_ept_memtype_supported(i)) 4667 test_vmx_valid_controls(); 4668 else 4669 test_vmx_invalid_controls(); 4670 report_prefix_pop(); 4671 } 4672 4673 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | 6ul; 4674 4675 /* 4676 * Page walk length (bits 5:3). Note, the value in VMCS.EPTP "is 1 4677 * less than the EPT page-walk length". 4678 */ 4679 for (i = 0; i < 8; i++) { 4680 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4681 (i << EPTP_PG_WALK_LEN_SHIFT); 4682 4683 vmcs_write(EPTP, eptp); 4684 report_prefix_pushf("Enable-EPT enabled; EPT page walk length %lu", 4685 eptp & EPTP_PG_WALK_LEN_MASK); 4686 if (i == 3 || (i == 4 && is_5_level_ept_supported())) 4687 test_vmx_valid_controls(); 4688 else 4689 test_vmx_invalid_controls(); 4690 report_prefix_pop(); 4691 } 4692 4693 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4694 3ul << EPTP_PG_WALK_LEN_SHIFT; 4695 4696 /* 4697 * Accessed and dirty flag (bit 6) 4698 */ 4699 if (ept_ad_bits_supported()) { 4700 report_info("Processor supports accessed and dirty flag"); 4701 eptp &= ~EPTP_AD_FLAG; 4702 test_eptp_ad_bit(eptp, true); 4703 4704 eptp |= EPTP_AD_FLAG; 4705 test_eptp_ad_bit(eptp, true); 4706 } else { 4707 report_info("Processor does not supports accessed and dirty flag"); 4708 eptp &= ~EPTP_AD_FLAG; 4709 test_eptp_ad_bit(eptp, true); 4710 4711 eptp |= EPTP_AD_FLAG; 4712 test_eptp_ad_bit(eptp, false); 4713 } 4714 4715 /* 4716 * Reserved bits [11:7] and [63:N] 4717 */ 4718 for (i = 0; i < 32; i++) { 4719 eptp = (eptp & 4720 ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)) | 4721 (i << EPTP_RESERV_BITS_SHIFT); 4722 vmcs_write(EPTP, eptp); 4723 report_prefix_pushf("Enable-EPT enabled; reserved bits [11:7] %lu", 4724 (eptp >> EPTP_RESERV_BITS_SHIFT) & 4725 EPTP_RESERV_BITS_MASK); 4726 if (i == 0) 4727 test_vmx_valid_controls(); 4728 else 4729 test_vmx_invalid_controls(); 4730 report_prefix_pop(); 4731 } 4732 4733 eptp = (eptp & ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)); 4734 4735 maxphysaddr = cpuid_maxphyaddr(); 4736 for (i = 0; i < (63 - maxphysaddr + 1); i++) { 4737 resv_bits_mask |= 1ul << i; 4738 } 4739 4740 for (j = maxphysaddr - 1; j <= 63; j++) { 4741 eptp = (eptp & ~(resv_bits_mask << maxphysaddr)) | 4742 (j < maxphysaddr ? 0 : 1ul << j); 4743 vmcs_write(EPTP, eptp); 4744 report_prefix_pushf("Enable-EPT enabled; reserved bits [63:N] %lu", 4745 (eptp >> maxphysaddr) & resv_bits_mask); 4746 if (j < maxphysaddr) 4747 test_vmx_valid_controls(); 4748 else 4749 test_vmx_invalid_controls(); 4750 report_prefix_pop(); 4751 } 4752 4753 secondary &= ~(CPU_EPT | CPU_URG); 4754 vmcs_write(CPU_EXEC_CTRL1, secondary); 4755 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest disabled"); 4756 test_vmx_valid_controls(); 4757 report_prefix_pop(); 4758 4759 if (!(ctrl_cpu_rev[1].clr & CPU_URG)) 4760 goto skip_unrestricted_guest; 4761 4762 secondary |= CPU_URG; 4763 vmcs_write(CPU_EXEC_CTRL1, secondary); 4764 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest enabled"); 4765 test_vmx_invalid_controls(); 4766 report_prefix_pop(); 4767 4768 secondary |= CPU_EPT; 4769 setup_dummy_ept(); 4770 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest enabled"); 4771 test_vmx_valid_controls(); 4772 report_prefix_pop(); 4773 4774 skip_unrestricted_guest: 4775 secondary &= ~CPU_URG; 4776 vmcs_write(CPU_EXEC_CTRL1, secondary); 4777 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest disabled"); 4778 test_vmx_valid_controls(); 4779 report_prefix_pop(); 4780 4781 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4782 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4783 vmcs_write(EPTP, eptp_saved); 4784 } 4785 4786 /* 4787 * If the 'enable PML' VM-execution control is 1, the 'enable EPT' 4788 * VM-execution control must also be 1. In addition, the PML address 4789 * must satisfy the following checks: 4790 * 4791 * * Bits 11:0 of the address must be 0. 4792 * * The address should not set any bits beyond the processor's 4793 * physical-address width. 4794 * 4795 * [Intel SDM] 4796 */ 4797 static void test_pml(void) 4798 { 4799 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4800 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4801 u32 primary = primary_saved; 4802 u32 secondary = secondary_saved; 4803 4804 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4805 (ctrl_cpu_rev[1].clr & CPU_EPT) && (ctrl_cpu_rev[1].clr & CPU_PML))) { 4806 report_skip("%s : \"Secondary execution\" or \"enable EPT\" or \"enable PML\" control not supported", __func__); 4807 return; 4808 } 4809 4810 primary |= CPU_SECONDARY; 4811 vmcs_write(CPU_EXEC_CTRL0, primary); 4812 secondary &= ~(CPU_PML | CPU_EPT); 4813 vmcs_write(CPU_EXEC_CTRL1, secondary); 4814 report_prefix_pushf("enable-PML disabled, enable-EPT disabled"); 4815 test_vmx_valid_controls(); 4816 report_prefix_pop(); 4817 4818 secondary |= CPU_PML; 4819 vmcs_write(CPU_EXEC_CTRL1, secondary); 4820 report_prefix_pushf("enable-PML enabled, enable-EPT disabled"); 4821 test_vmx_invalid_controls(); 4822 report_prefix_pop(); 4823 4824 secondary |= CPU_EPT; 4825 setup_dummy_ept(); 4826 report_prefix_pushf("enable-PML enabled, enable-EPT enabled"); 4827 test_vmx_valid_controls(); 4828 report_prefix_pop(); 4829 4830 secondary &= ~CPU_PML; 4831 vmcs_write(CPU_EXEC_CTRL1, secondary); 4832 report_prefix_pushf("enable-PML disabled, enable EPT enabled"); 4833 test_vmx_valid_controls(); 4834 report_prefix_pop(); 4835 4836 test_vmcs_addr_reference(CPU_PML, PMLADDR, "PML address", "PML", 4837 PAGE_SIZE, false, false); 4838 4839 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4840 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4841 } 4842 4843 /* 4844 * If the "activate VMX-preemption timer" VM-execution control is 0, the 4845 * the "save VMX-preemption timer value" VM-exit control must also be 0. 4846 * 4847 * [Intel SDM] 4848 */ 4849 static void test_vmx_preemption_timer(void) 4850 { 4851 u32 saved_pin = vmcs_read(PIN_CONTROLS); 4852 u32 saved_exit = vmcs_read(EXI_CONTROLS); 4853 u32 pin = saved_pin; 4854 u32 exit = saved_exit; 4855 4856 if (!((ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) || 4857 (ctrl_pin_rev.clr & PIN_PREEMPT))) { 4858 report_skip("%s : \"Save-VMX-preemption-timer\" and/or \"Enable-VMX-preemption-timer\" control not supported", __func__); 4859 return; 4860 } 4861 4862 pin |= PIN_PREEMPT; 4863 vmcs_write(PIN_CONTROLS, pin); 4864 exit &= ~EXI_SAVE_PREEMPT; 4865 vmcs_write(EXI_CONTROLS, exit); 4866 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer disabled"); 4867 test_vmx_valid_controls(); 4868 report_prefix_pop(); 4869 4870 exit |= EXI_SAVE_PREEMPT; 4871 vmcs_write(EXI_CONTROLS, exit); 4872 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer enabled"); 4873 test_vmx_valid_controls(); 4874 report_prefix_pop(); 4875 4876 pin &= ~PIN_PREEMPT; 4877 vmcs_write(PIN_CONTROLS, pin); 4878 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer enabled"); 4879 test_vmx_invalid_controls(); 4880 report_prefix_pop(); 4881 4882 exit &= ~EXI_SAVE_PREEMPT; 4883 vmcs_write(EXI_CONTROLS, exit); 4884 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer disabled"); 4885 test_vmx_valid_controls(); 4886 report_prefix_pop(); 4887 4888 vmcs_write(PIN_CONTROLS, saved_pin); 4889 vmcs_write(EXI_CONTROLS, saved_exit); 4890 } 4891 4892 extern unsigned char test_mtf1; 4893 extern unsigned char test_mtf2; 4894 extern unsigned char test_mtf3; 4895 extern unsigned char test_mtf4; 4896 4897 static void test_mtf_guest(void) 4898 { 4899 asm ("vmcall;\n\t" 4900 "out %al, $0x80;\n\t" 4901 "test_mtf1:\n\t" 4902 "vmcall;\n\t" 4903 "out %al, $0x80;\n\t" 4904 "test_mtf2:\n\t" 4905 /* 4906 * Prepare for the 'MOV CR3' test. Attempt to induce a 4907 * general-protection fault by moving a non-canonical address into 4908 * CR3. The 'MOV CR3' instruction does not take an imm64 operand, 4909 * so we must MOV the desired value into a register first. 4910 * 4911 * MOV RAX is done before the VMCALL such that MTF is only enabled 4912 * for the instruction under test. 4913 */ 4914 "mov $0xaaaaaaaaaaaaaaaa, %rax;\n\t" 4915 "vmcall;\n\t" 4916 "mov %rax, %cr3;\n\t" 4917 "test_mtf3:\n\t" 4918 "vmcall;\n\t" 4919 /* 4920 * ICEBP/INT1 instruction. Though the instruction is now 4921 * documented, don't rely on assemblers enumerating the 4922 * instruction. Resort to hand assembly. 4923 */ 4924 ".byte 0xf1;\n\t" 4925 "vmcall;\n\t" 4926 "test_mtf4:\n\t" 4927 "mov $0, %eax;\n\t"); 4928 } 4929 4930 static void test_mtf_gp_handler(struct ex_regs *regs) 4931 { 4932 regs->rip = (unsigned long) &test_mtf3; 4933 } 4934 4935 static void test_mtf_db_handler(struct ex_regs *regs) 4936 { 4937 } 4938 4939 static void enable_mtf(void) 4940 { 4941 u32 ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 4942 4943 vmcs_write(CPU_EXEC_CTRL0, ctrl0 | CPU_MTF); 4944 } 4945 4946 static void disable_mtf(void) 4947 { 4948 u32 ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 4949 4950 vmcs_write(CPU_EXEC_CTRL0, ctrl0 & ~CPU_MTF); 4951 } 4952 4953 static void enable_tf(void) 4954 { 4955 unsigned long rflags = vmcs_read(GUEST_RFLAGS); 4956 4957 vmcs_write(GUEST_RFLAGS, rflags | X86_EFLAGS_TF); 4958 } 4959 4960 static void disable_tf(void) 4961 { 4962 unsigned long rflags = vmcs_read(GUEST_RFLAGS); 4963 4964 vmcs_write(GUEST_RFLAGS, rflags & ~X86_EFLAGS_TF); 4965 } 4966 4967 static void report_mtf(const char *insn_name, unsigned long exp_rip) 4968 { 4969 unsigned long rip = vmcs_read(GUEST_RIP); 4970 4971 assert_exit_reason(VMX_MTF); 4972 report(rip == exp_rip, "MTF VM-exit after %s. RIP: 0x%lx (expected 0x%lx)", 4973 insn_name, rip, exp_rip); 4974 } 4975 4976 static void vmx_mtf_test(void) 4977 { 4978 unsigned long pending_dbg; 4979 handler old_gp, old_db; 4980 4981 if (!(ctrl_cpu_rev[0].clr & CPU_MTF)) { 4982 report_skip("%s : \"Monitor trap flag\" exec control not supported", __func__); 4983 return; 4984 } 4985 4986 test_set_guest(test_mtf_guest); 4987 4988 /* Expect an MTF VM-exit after OUT instruction */ 4989 enter_guest(); 4990 skip_exit_vmcall(); 4991 4992 enable_mtf(); 4993 enter_guest(); 4994 report_mtf("OUT", (unsigned long) &test_mtf1); 4995 disable_mtf(); 4996 4997 /* 4998 * Concurrent #DB trap and MTF on instruction boundary. Expect MTF 4999 * VM-exit with populated 'pending debug exceptions' VMCS field. 5000 */ 5001 enter_guest(); 5002 skip_exit_vmcall(); 5003 5004 enable_mtf(); 5005 enable_tf(); 5006 5007 enter_guest(); 5008 report_mtf("OUT", (unsigned long) &test_mtf2); 5009 pending_dbg = vmcs_read(GUEST_PENDING_DEBUG); 5010 report(pending_dbg & DR6_BS, 5011 "'pending debug exceptions' field after MTF VM-exit: 0x%lx (expected 0x%lx)", 5012 pending_dbg, (unsigned long) DR6_BS); 5013 5014 disable_mtf(); 5015 disable_tf(); 5016 vmcs_write(GUEST_PENDING_DEBUG, 0); 5017 5018 /* 5019 * #GP exception takes priority over MTF. Expect MTF VM-exit with RIP 5020 * advanced to first instruction of #GP handler. 5021 */ 5022 enter_guest(); 5023 skip_exit_vmcall(); 5024 5025 old_gp = handle_exception(GP_VECTOR, test_mtf_gp_handler); 5026 5027 enable_mtf(); 5028 enter_guest(); 5029 report_mtf("MOV CR3", (unsigned long) get_idt_addr(&boot_idt[GP_VECTOR])); 5030 disable_mtf(); 5031 5032 /* 5033 * Concurrent MTF and privileged software exception (i.e. ICEBP/INT1). 5034 * MTF should follow the delivery of #DB trap, though the SDM doesn't 5035 * provide clear indication of the relative priority. 5036 */ 5037 enter_guest(); 5038 skip_exit_vmcall(); 5039 5040 handle_exception(GP_VECTOR, old_gp); 5041 old_db = handle_exception(DB_VECTOR, test_mtf_db_handler); 5042 5043 enable_mtf(); 5044 enter_guest(); 5045 report_mtf("INT1", (unsigned long) get_idt_addr(&boot_idt[DB_VECTOR])); 5046 disable_mtf(); 5047 5048 enter_guest(); 5049 skip_exit_vmcall(); 5050 handle_exception(DB_VECTOR, old_db); 5051 vmcs_write(ENT_INTR_INFO, INTR_INFO_VALID_MASK | INTR_TYPE_OTHER_EVENT); 5052 enter_guest(); 5053 report_mtf("injected MTF", (unsigned long) &test_mtf4); 5054 enter_guest(); 5055 } 5056 5057 extern char vmx_mtf_pdpte_guest_begin; 5058 extern char vmx_mtf_pdpte_guest_end; 5059 5060 asm("vmx_mtf_pdpte_guest_begin:\n\t" 5061 "mov %cr0, %rax\n\t" /* save CR0 with PG=1 */ 5062 "vmcall\n\t" /* on return from this CR0.PG=0 */ 5063 "mov %rax, %cr0\n\t" /* restore CR0.PG=1 to enter PAE mode */ 5064 "vmcall\n\t" 5065 "retq\n\t" 5066 "vmx_mtf_pdpte_guest_end:"); 5067 5068 static void vmx_mtf_pdpte_test(void) 5069 { 5070 void *test_mtf_pdpte_guest; 5071 pteval_t *pdpt; 5072 u32 guest_ar_cs; 5073 u64 guest_efer; 5074 pteval_t *pte; 5075 u64 guest_cr0; 5076 u64 guest_cr3; 5077 u64 guest_cr4; 5078 u64 ent_ctls; 5079 int i; 5080 5081 if (setup_ept(false)) 5082 return; 5083 5084 if (!(ctrl_cpu_rev[0].clr & CPU_MTF)) { 5085 report_skip("%s : \"Monitor trap flag\" exec control not supported", __func__); 5086 return; 5087 } 5088 5089 if (!(ctrl_cpu_rev[1].clr & CPU_URG)) { 5090 report_skip("%s : \"Unrestricted guest\" exec control not supported", __func__); 5091 return; 5092 } 5093 5094 vmcs_write(EXC_BITMAP, ~0); 5095 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | CPU_URG); 5096 5097 /* 5098 * Copy the guest code to an identity-mapped page. 5099 */ 5100 test_mtf_pdpte_guest = alloc_page(); 5101 memcpy(test_mtf_pdpte_guest, &vmx_mtf_pdpte_guest_begin, 5102 &vmx_mtf_pdpte_guest_end - &vmx_mtf_pdpte_guest_begin); 5103 5104 test_set_guest(test_mtf_pdpte_guest); 5105 5106 enter_guest(); 5107 skip_exit_vmcall(); 5108 5109 /* 5110 * Put the guest in non-paged 32-bit protected mode, ready to enter 5111 * PAE mode when CR0.PG is set. CR4.PAE will already have been set 5112 * when the guest started out in long mode. 5113 */ 5114 ent_ctls = vmcs_read(ENT_CONTROLS); 5115 vmcs_write(ENT_CONTROLS, ent_ctls & ~ENT_GUEST_64); 5116 5117 guest_efer = vmcs_read(GUEST_EFER); 5118 vmcs_write(GUEST_EFER, guest_efer & ~(EFER_LMA | EFER_LME)); 5119 5120 /* 5121 * Set CS access rights bits for 32-bit protected mode: 5122 * 3:0 B execute/read/accessed 5123 * 4 1 code or data 5124 * 6:5 0 descriptor privilege level 5125 * 7 1 present 5126 * 11:8 0 reserved 5127 * 12 0 available for use by system software 5128 * 13 0 64 bit mode not active 5129 * 14 1 default operation size 32-bit segment 5130 * 15 1 page granularity: segment limit in 4K units 5131 * 16 0 segment usable 5132 * 31:17 0 reserved 5133 */ 5134 guest_ar_cs = vmcs_read(GUEST_AR_CS); 5135 vmcs_write(GUEST_AR_CS, 0xc09b); 5136 5137 guest_cr0 = vmcs_read(GUEST_CR0); 5138 vmcs_write(GUEST_CR0, guest_cr0 & ~X86_CR0_PG); 5139 5140 guest_cr4 = vmcs_read(GUEST_CR4); 5141 vmcs_write(GUEST_CR4, guest_cr4 & ~X86_CR4_PCIDE); 5142 5143 guest_cr3 = vmcs_read(GUEST_CR3); 5144 5145 /* 5146 * Turn the 4-level page table into a PAE page table by following the 0th 5147 * PML4 entry to a PDPT page, and grab the first four PDPTEs from that 5148 * page. 5149 * 5150 * Why does this work? 5151 * 5152 * PAE uses 32-bit addressing which implies: 5153 * Bits 11:0 page offset 5154 * Bits 20:12 entry into 512-entry page table 5155 * Bits 29:21 entry into a 512-entry directory table 5156 * Bits 31:30 entry into the page directory pointer table. 5157 * Bits 63:32 zero 5158 * 5159 * As only 2 bits are needed to select the PDPTEs for the entire 5160 * 32-bit address space, take the first 4 PDPTEs in the level 3 page 5161 * directory pointer table. It doesn't matter which of these PDPTEs 5162 * are present because they must cover the guest code given that it 5163 * has already run successfully. 5164 * 5165 * Get a pointer to PTE for GVA=0 in the page directory pointer table 5166 */ 5167 pte = get_pte_level( 5168 (pgd_t *)phys_to_virt(guest_cr3 & ~X86_CR3_PCID_MASK), 0, 5169 PDPT_LEVEL); 5170 5171 /* 5172 * Need some memory for the 4-entry PAE page directory pointer 5173 * table. Use the end of the identity-mapped page where the guest code 5174 * is stored. There is definitely space as the guest code is only a 5175 * few bytes. 5176 */ 5177 pdpt = test_mtf_pdpte_guest + PAGE_SIZE - 4 * sizeof(pteval_t); 5178 5179 /* 5180 * Copy the first four PDPTEs into the PAE page table with reserved 5181 * bits cleared. Note that permission bits from the PML4E and PDPTE 5182 * are not propagated. 5183 */ 5184 for (i = 0; i < 4; i++) { 5185 TEST_ASSERT_EQ_MSG(0, (pte[i] & PDPTE64_RSVD_MASK), 5186 "PDPTE has invalid reserved bits"); 5187 TEST_ASSERT_EQ_MSG(0, (pte[i] & PDPTE64_PAGE_SIZE_MASK), 5188 "Cannot use 1GB super pages for PAE"); 5189 pdpt[i] = pte[i] & ~(PAE_PDPTE_RSVD_MASK); 5190 } 5191 vmcs_write(GUEST_CR3, virt_to_phys(pdpt)); 5192 5193 enable_mtf(); 5194 enter_guest(); 5195 assert_exit_reason(VMX_MTF); 5196 disable_mtf(); 5197 5198 /* 5199 * The four PDPTEs should have been loaded into the VMCS when 5200 * the guest set CR0.PG to enter PAE mode. 5201 */ 5202 for (i = 0; i < 4; i++) { 5203 u64 pdpte = vmcs_read(GUEST_PDPTE + 2 * i); 5204 5205 report(pdpte == pdpt[i], "PDPTE%d is 0x%lx (expected 0x%lx)", 5206 i, pdpte, pdpt[i]); 5207 } 5208 5209 /* 5210 * Now, try to enter the guest in PAE mode. If the PDPTEs in the 5211 * vmcs are wrong, this will fail. 5212 */ 5213 enter_guest(); 5214 skip_exit_vmcall(); 5215 5216 /* 5217 * Return guest to 64-bit mode and wrap up. 5218 */ 5219 vmcs_write(ENT_CONTROLS, ent_ctls); 5220 vmcs_write(GUEST_EFER, guest_efer); 5221 vmcs_write(GUEST_AR_CS, guest_ar_cs); 5222 vmcs_write(GUEST_CR0, guest_cr0); 5223 vmcs_write(GUEST_CR4, guest_cr4); 5224 vmcs_write(GUEST_CR3, guest_cr3); 5225 5226 enter_guest(); 5227 } 5228 5229 /* 5230 * Tests for VM-execution control fields 5231 */ 5232 static void test_vm_execution_ctls(void) 5233 { 5234 test_pin_based_ctls(); 5235 test_primary_processor_based_ctls(); 5236 test_secondary_processor_based_ctls(); 5237 test_cr3_targets(); 5238 test_io_bitmaps(); 5239 test_msr_bitmap(); 5240 test_apic_ctls(); 5241 test_tpr_threshold(); 5242 test_nmi_ctrls(); 5243 test_pml(); 5244 test_vpid(); 5245 test_ept_eptp(); 5246 test_vmx_preemption_timer(); 5247 } 5248 5249 /* 5250 * The following checks are performed for the VM-entry MSR-load address if 5251 * the VM-entry MSR-load count field is non-zero: 5252 * 5253 * - The lower 4 bits of the VM-entry MSR-load address must be 0. 5254 * The address should not set any bits beyond the processor's 5255 * physical-address width. 5256 * 5257 * - The address of the last byte in the VM-entry MSR-load area 5258 * should not set any bits beyond the processor's physical-address 5259 * width. The address of this last byte is VM-entry MSR-load address 5260 * + (MSR count * 16) - 1. (The arithmetic used for the computation 5261 * uses more bits than the processor's physical-address width.) 5262 * 5263 * 5264 * [Intel SDM] 5265 */ 5266 static void test_entry_msr_load(void) 5267 { 5268 entry_msr_load = alloc_page(); 5269 u64 tmp; 5270 u32 entry_msr_ld_cnt = 1; 5271 int i; 5272 u32 addr_len = 64; 5273 5274 vmcs_write(ENT_MSR_LD_CNT, entry_msr_ld_cnt); 5275 5276 /* Check first 4 bits of VM-entry MSR-load address */ 5277 for (i = 0; i < 4; i++) { 5278 tmp = (u64)entry_msr_load | 1ull << i; 5279 vmcs_write(ENTER_MSR_LD_ADDR, tmp); 5280 report_prefix_pushf("VM-entry MSR-load addr [4:0] %lx", 5281 tmp & 0xf); 5282 test_vmx_invalid_controls(); 5283 report_prefix_pop(); 5284 } 5285 5286 if (basic.val & (1ul << 48)) 5287 addr_len = 32; 5288 5289 test_vmcs_addr_values("VM-entry-MSR-load address", 5290 ENTER_MSR_LD_ADDR, 16, false, false, 5291 4, addr_len - 1); 5292 5293 /* 5294 * Check last byte of VM-entry MSR-load address 5295 */ 5296 entry_msr_load = (struct vmx_msr_entry *)((u64)entry_msr_load & ~0xf); 5297 5298 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 5299 i < 64; i++) { 5300 tmp = ((u64)entry_msr_load + entry_msr_ld_cnt * 16 - 1) | 5301 1ul << i; 5302 vmcs_write(ENTER_MSR_LD_ADDR, 5303 tmp - (entry_msr_ld_cnt * 16 - 1)); 5304 test_vmx_invalid_controls(); 5305 } 5306 5307 vmcs_write(ENT_MSR_LD_CNT, 2); 5308 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 5309 test_vmx_invalid_controls(); 5310 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 5311 test_vmx_valid_controls(); 5312 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 5313 test_vmx_valid_controls(); 5314 } 5315 5316 static struct vmx_state_area_test_data { 5317 u32 msr; 5318 u64 exp; 5319 bool enabled; 5320 } vmx_state_area_test_data; 5321 5322 static void guest_state_test_main(void) 5323 { 5324 u64 obs; 5325 struct vmx_state_area_test_data *data = &vmx_state_area_test_data; 5326 5327 while (1) { 5328 if (vmx_get_test_stage() == 2) 5329 break; 5330 5331 if (data->enabled) { 5332 obs = rdmsr(data->msr); 5333 report(data->exp == obs, 5334 "Guest state is 0x%lx (expected 0x%lx)", 5335 obs, data->exp); 5336 } 5337 5338 vmcall(); 5339 } 5340 5341 asm volatile("fnop"); 5342 } 5343 5344 static void test_guest_state(const char *test, bool xfail, u64 field, 5345 const char * field_name) 5346 { 5347 struct vmentry_result result; 5348 u8 abort_flags; 5349 5350 abort_flags = ABORT_ON_EARLY_VMENTRY_FAIL; 5351 if (!xfail) 5352 abort_flags = ABORT_ON_INVALID_GUEST_STATE; 5353 5354 __enter_guest(abort_flags, &result); 5355 5356 report(result.exit_reason.failed_vmentry == xfail && 5357 ((xfail && result.exit_reason.basic == VMX_FAIL_STATE) || 5358 (!xfail && result.exit_reason.basic == VMX_VMCALL)) && 5359 (!xfail || vmcs_read(EXI_QUALIFICATION) == ENTRY_FAIL_DEFAULT), 5360 "%s, %s = %lx", test, field_name, field); 5361 5362 if (!result.exit_reason.failed_vmentry) 5363 skip_exit_insn(); 5364 } 5365 5366 /* 5367 * Tests for VM-entry control fields 5368 */ 5369 static void test_vm_entry_ctls(void) 5370 { 5371 test_invalid_event_injection(); 5372 test_entry_msr_load(); 5373 } 5374 5375 /* 5376 * The following checks are performed for the VM-exit MSR-store address if 5377 * the VM-exit MSR-store count field is non-zero: 5378 * 5379 * - The lower 4 bits of the VM-exit MSR-store address must be 0. 5380 * The address should not set any bits beyond the processor's 5381 * physical-address width. 5382 * 5383 * - The address of the last byte in the VM-exit MSR-store area 5384 * should not set any bits beyond the processor's physical-address 5385 * width. The address of this last byte is VM-exit MSR-store address 5386 * + (MSR count * 16) - 1. (The arithmetic used for the computation 5387 * uses more bits than the processor's physical-address width.) 5388 * 5389 * If IA32_VMX_BASIC[48] is read as 1, neither address should set any bits 5390 * in the range 63:32. 5391 * 5392 * [Intel SDM] 5393 */ 5394 static void test_exit_msr_store(void) 5395 { 5396 exit_msr_store = alloc_page(); 5397 u64 tmp; 5398 u32 exit_msr_st_cnt = 1; 5399 int i; 5400 u32 addr_len = 64; 5401 5402 vmcs_write(EXI_MSR_ST_CNT, exit_msr_st_cnt); 5403 5404 /* Check first 4 bits of VM-exit MSR-store address */ 5405 for (i = 0; i < 4; i++) { 5406 tmp = (u64)exit_msr_store | 1ull << i; 5407 vmcs_write(EXIT_MSR_ST_ADDR, tmp); 5408 report_prefix_pushf("VM-exit MSR-store addr [4:0] %lx", 5409 tmp & 0xf); 5410 test_vmx_invalid_controls(); 5411 report_prefix_pop(); 5412 } 5413 5414 if (basic.val & (1ul << 48)) 5415 addr_len = 32; 5416 5417 test_vmcs_addr_values("VM-exit-MSR-store address", 5418 EXIT_MSR_ST_ADDR, 16, false, false, 5419 4, addr_len - 1); 5420 5421 /* 5422 * Check last byte of VM-exit MSR-store address 5423 */ 5424 exit_msr_store = (struct vmx_msr_entry *)((u64)exit_msr_store & ~0xf); 5425 5426 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 5427 i < 64; i++) { 5428 tmp = ((u64)exit_msr_store + exit_msr_st_cnt * 16 - 1) | 5429 1ul << i; 5430 vmcs_write(EXIT_MSR_ST_ADDR, 5431 tmp - (exit_msr_st_cnt * 16 - 1)); 5432 test_vmx_invalid_controls(); 5433 } 5434 5435 vmcs_write(EXI_MSR_ST_CNT, 2); 5436 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 5437 test_vmx_invalid_controls(); 5438 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 5439 test_vmx_valid_controls(); 5440 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 5441 test_vmx_valid_controls(); 5442 } 5443 5444 /* 5445 * Tests for VM-exit controls 5446 */ 5447 static void test_vm_exit_ctls(void) 5448 { 5449 test_exit_msr_store(); 5450 } 5451 5452 /* 5453 * Check that the virtual CPU checks all of the VMX controls as 5454 * documented in the Intel SDM. 5455 */ 5456 static void vmx_controls_test(void) 5457 { 5458 /* 5459 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 5460 * fail due to invalid guest state, should we make it that 5461 * far. 5462 */ 5463 vmcs_write(GUEST_RFLAGS, 0); 5464 5465 test_vm_execution_ctls(); 5466 test_vm_exit_ctls(); 5467 test_vm_entry_ctls(); 5468 } 5469 5470 struct apic_reg_virt_config { 5471 bool apic_register_virtualization; 5472 bool use_tpr_shadow; 5473 bool virtualize_apic_accesses; 5474 bool virtualize_x2apic_mode; 5475 bool activate_secondary_controls; 5476 }; 5477 5478 struct apic_reg_test { 5479 const char *name; 5480 struct apic_reg_virt_config apic_reg_virt_config; 5481 }; 5482 5483 struct apic_reg_virt_expectation { 5484 enum Reason rd_exit_reason; 5485 enum Reason wr_exit_reason; 5486 u32 val; 5487 u32 (*virt_fn)(u32); 5488 5489 /* 5490 * If false, accessing the APIC access address from L2 is treated as a 5491 * normal memory operation, rather than triggering virtualization. 5492 */ 5493 bool virtualize_apic_accesses; 5494 }; 5495 5496 static u32 apic_virt_identity(u32 val) 5497 { 5498 return val; 5499 } 5500 5501 static u32 apic_virt_nibble1(u32 val) 5502 { 5503 return val & 0xf0; 5504 } 5505 5506 static u32 apic_virt_byte3(u32 val) 5507 { 5508 return val & (0xff << 24); 5509 } 5510 5511 static bool apic_reg_virt_exit_expectation( 5512 u32 reg, struct apic_reg_virt_config *config, 5513 struct apic_reg_virt_expectation *expectation) 5514 { 5515 /* Good configs, where some L2 APIC accesses are virtualized. */ 5516 bool virtualize_apic_accesses_only = 5517 config->virtualize_apic_accesses && 5518 !config->use_tpr_shadow && 5519 !config->apic_register_virtualization && 5520 !config->virtualize_x2apic_mode && 5521 config->activate_secondary_controls; 5522 bool virtualize_apic_accesses_and_use_tpr_shadow = 5523 config->virtualize_apic_accesses && 5524 config->use_tpr_shadow && 5525 !config->apic_register_virtualization && 5526 !config->virtualize_x2apic_mode && 5527 config->activate_secondary_controls; 5528 bool apic_register_virtualization = 5529 config->virtualize_apic_accesses && 5530 config->use_tpr_shadow && 5531 config->apic_register_virtualization && 5532 !config->virtualize_x2apic_mode && 5533 config->activate_secondary_controls; 5534 5535 expectation->val = MAGIC_VAL_1; 5536 expectation->virt_fn = apic_virt_identity; 5537 expectation->virtualize_apic_accesses = 5538 config->virtualize_apic_accesses && 5539 config->activate_secondary_controls; 5540 if (virtualize_apic_accesses_only) { 5541 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5542 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5543 } else if (virtualize_apic_accesses_and_use_tpr_shadow) { 5544 switch (reg) { 5545 case APIC_TASKPRI: 5546 expectation->rd_exit_reason = VMX_VMCALL; 5547 expectation->wr_exit_reason = VMX_VMCALL; 5548 expectation->virt_fn = apic_virt_nibble1; 5549 break; 5550 default: 5551 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5552 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5553 } 5554 } else if (apic_register_virtualization) { 5555 expectation->rd_exit_reason = VMX_VMCALL; 5556 5557 switch (reg) { 5558 case APIC_ID: 5559 case APIC_EOI: 5560 case APIC_LDR: 5561 case APIC_DFR: 5562 case APIC_SPIV: 5563 case APIC_ESR: 5564 case APIC_ICR: 5565 case APIC_LVTT: 5566 case APIC_LVTTHMR: 5567 case APIC_LVTPC: 5568 case APIC_LVT0: 5569 case APIC_LVT1: 5570 case APIC_LVTERR: 5571 case APIC_TMICT: 5572 case APIC_TDCR: 5573 expectation->wr_exit_reason = VMX_APIC_WRITE; 5574 break; 5575 case APIC_LVR: 5576 case APIC_ISR ... APIC_ISR + 0x70: 5577 case APIC_TMR ... APIC_TMR + 0x70: 5578 case APIC_IRR ... APIC_IRR + 0x70: 5579 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5580 break; 5581 case APIC_TASKPRI: 5582 expectation->wr_exit_reason = VMX_VMCALL; 5583 expectation->virt_fn = apic_virt_nibble1; 5584 break; 5585 case APIC_ICR2: 5586 expectation->wr_exit_reason = VMX_VMCALL; 5587 expectation->virt_fn = apic_virt_byte3; 5588 break; 5589 default: 5590 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5591 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5592 } 5593 } else if (!expectation->virtualize_apic_accesses) { 5594 /* 5595 * No APIC registers are directly virtualized. This includes 5596 * VTPR, which can be virtualized through MOV to/from CR8 via 5597 * the use TPR shadow control, but not through directly 5598 * accessing VTPR. 5599 */ 5600 expectation->rd_exit_reason = VMX_VMCALL; 5601 expectation->wr_exit_reason = VMX_VMCALL; 5602 } else { 5603 printf("Cannot parse APIC register virtualization config:\n" 5604 "\tvirtualize_apic_accesses: %d\n" 5605 "\tuse_tpr_shadow: %d\n" 5606 "\tapic_register_virtualization: %d\n" 5607 "\tvirtualize_x2apic_mode: %d\n" 5608 "\tactivate_secondary_controls: %d\n", 5609 config->virtualize_apic_accesses, 5610 config->use_tpr_shadow, 5611 config->apic_register_virtualization, 5612 config->virtualize_x2apic_mode, 5613 config->activate_secondary_controls); 5614 5615 return false; 5616 } 5617 5618 return true; 5619 } 5620 5621 struct apic_reg_test apic_reg_tests[] = { 5622 /* Good configs, where some L2 APIC accesses are virtualized. */ 5623 { 5624 .name = "Virtualize APIC accesses", 5625 .apic_reg_virt_config = { 5626 .virtualize_apic_accesses = true, 5627 .use_tpr_shadow = false, 5628 .apic_register_virtualization = false, 5629 .virtualize_x2apic_mode = false, 5630 .activate_secondary_controls = true, 5631 }, 5632 }, 5633 { 5634 .name = "Virtualize APIC accesses + Use TPR shadow", 5635 .apic_reg_virt_config = { 5636 .virtualize_apic_accesses = true, 5637 .use_tpr_shadow = true, 5638 .apic_register_virtualization = false, 5639 .virtualize_x2apic_mode = false, 5640 .activate_secondary_controls = true, 5641 }, 5642 }, 5643 { 5644 .name = "APIC-register virtualization", 5645 .apic_reg_virt_config = { 5646 .virtualize_apic_accesses = true, 5647 .use_tpr_shadow = true, 5648 .apic_register_virtualization = true, 5649 .virtualize_x2apic_mode = false, 5650 .activate_secondary_controls = true, 5651 }, 5652 }, 5653 5654 /* 5655 * Test that the secondary processor-based VM-execution controls are 5656 * correctly ignored when "activate secondary controls" is disabled. 5657 */ 5658 { 5659 .name = "Activate secondary controls off", 5660 .apic_reg_virt_config = { 5661 .virtualize_apic_accesses = true, 5662 .use_tpr_shadow = false, 5663 .apic_register_virtualization = true, 5664 .virtualize_x2apic_mode = true, 5665 .activate_secondary_controls = false, 5666 }, 5667 }, 5668 { 5669 .name = "Activate secondary controls off + Use TPR shadow", 5670 .apic_reg_virt_config = { 5671 .virtualize_apic_accesses = true, 5672 .use_tpr_shadow = true, 5673 .apic_register_virtualization = true, 5674 .virtualize_x2apic_mode = true, 5675 .activate_secondary_controls = false, 5676 }, 5677 }, 5678 5679 /* 5680 * Test that the APIC access address is treated like an arbitrary memory 5681 * address when "virtualize APIC accesses" is disabled. 5682 */ 5683 { 5684 .name = "Virtualize APIC accesses off + Use TPR shadow", 5685 .apic_reg_virt_config = { 5686 .virtualize_apic_accesses = false, 5687 .use_tpr_shadow = true, 5688 .apic_register_virtualization = true, 5689 .virtualize_x2apic_mode = true, 5690 .activate_secondary_controls = true, 5691 }, 5692 }, 5693 5694 /* 5695 * Test that VM entry fails due to invalid controls when 5696 * "APIC-register virtualization" is enabled while "use TPR shadow" is 5697 * disabled. 5698 */ 5699 { 5700 .name = "APIC-register virtualization + Use TPR shadow off", 5701 .apic_reg_virt_config = { 5702 .virtualize_apic_accesses = true, 5703 .use_tpr_shadow = false, 5704 .apic_register_virtualization = true, 5705 .virtualize_x2apic_mode = false, 5706 .activate_secondary_controls = true, 5707 }, 5708 }, 5709 5710 /* 5711 * Test that VM entry fails due to invalid controls when 5712 * "Virtualize x2APIC mode" is enabled while "use TPR shadow" is 5713 * disabled. 5714 */ 5715 { 5716 .name = "Virtualize x2APIC mode + Use TPR shadow off", 5717 .apic_reg_virt_config = { 5718 .virtualize_apic_accesses = false, 5719 .use_tpr_shadow = false, 5720 .apic_register_virtualization = false, 5721 .virtualize_x2apic_mode = true, 5722 .activate_secondary_controls = true, 5723 }, 5724 }, 5725 { 5726 .name = "Virtualize x2APIC mode + Use TPR shadow off v2", 5727 .apic_reg_virt_config = { 5728 .virtualize_apic_accesses = false, 5729 .use_tpr_shadow = false, 5730 .apic_register_virtualization = true, 5731 .virtualize_x2apic_mode = true, 5732 .activate_secondary_controls = true, 5733 }, 5734 }, 5735 5736 /* 5737 * Test that VM entry fails due to invalid controls when 5738 * "virtualize x2APIC mode" is enabled while "virtualize APIC accesses" 5739 * is enabled. 5740 */ 5741 { 5742 .name = "Virtualize x2APIC mode + Virtualize APIC accesses", 5743 .apic_reg_virt_config = { 5744 .virtualize_apic_accesses = true, 5745 .use_tpr_shadow = true, 5746 .apic_register_virtualization = false, 5747 .virtualize_x2apic_mode = true, 5748 .activate_secondary_controls = true, 5749 }, 5750 }, 5751 { 5752 .name = "Virtualize x2APIC mode + Virtualize APIC accesses v2", 5753 .apic_reg_virt_config = { 5754 .virtualize_apic_accesses = true, 5755 .use_tpr_shadow = true, 5756 .apic_register_virtualization = true, 5757 .virtualize_x2apic_mode = true, 5758 .activate_secondary_controls = true, 5759 }, 5760 }, 5761 }; 5762 5763 enum Apic_op { 5764 APIC_OP_XAPIC_RD, 5765 APIC_OP_XAPIC_WR, 5766 TERMINATE, 5767 }; 5768 5769 static u32 vmx_xapic_read(u32 *apic_access_address, u32 reg) 5770 { 5771 return *(volatile u32 *)((uintptr_t)apic_access_address + reg); 5772 } 5773 5774 static void vmx_xapic_write(u32 *apic_access_address, u32 reg, u32 val) 5775 { 5776 *(volatile u32 *)((uintptr_t)apic_access_address + reg) = val; 5777 } 5778 5779 struct apic_reg_virt_guest_args { 5780 enum Apic_op op; 5781 u32 *apic_access_address; 5782 u32 reg; 5783 u32 val; 5784 bool check_rd; 5785 u32 (*virt_fn)(u32); 5786 } apic_reg_virt_guest_args; 5787 5788 static void apic_reg_virt_guest(void) 5789 { 5790 volatile struct apic_reg_virt_guest_args *args = 5791 &apic_reg_virt_guest_args; 5792 5793 for (;;) { 5794 enum Apic_op op = args->op; 5795 u32 *apic_access_address = args->apic_access_address; 5796 u32 reg = args->reg; 5797 u32 val = args->val; 5798 bool check_rd = args->check_rd; 5799 u32 (*virt_fn)(u32) = args->virt_fn; 5800 5801 if (op == TERMINATE) 5802 break; 5803 5804 if (op == APIC_OP_XAPIC_RD) { 5805 u32 ret = vmx_xapic_read(apic_access_address, reg); 5806 5807 if (check_rd) { 5808 u32 want = virt_fn(val); 5809 u32 got = virt_fn(ret); 5810 5811 report(got == want, 5812 "read 0x%x, expected 0x%x.", got, want); 5813 } 5814 } else if (op == APIC_OP_XAPIC_WR) { 5815 vmx_xapic_write(apic_access_address, reg, val); 5816 } 5817 5818 /* 5819 * The L1 should always execute a vmcall after it's done testing 5820 * an individual APIC operation. This helps to validate that the 5821 * L1 and L2 are in sync with each other, as expected. 5822 */ 5823 vmcall(); 5824 } 5825 } 5826 5827 static void test_xapic_rd( 5828 u32 reg, struct apic_reg_virt_expectation *expectation, 5829 u32 *apic_access_address, u32 *virtual_apic_page) 5830 { 5831 u32 val = expectation->val; 5832 u32 exit_reason_want = expectation->rd_exit_reason; 5833 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 5834 5835 report_prefix_pushf("xapic - reading 0x%03x", reg); 5836 5837 /* Configure guest to do an xapic read */ 5838 args->op = APIC_OP_XAPIC_RD; 5839 args->apic_access_address = apic_access_address; 5840 args->reg = reg; 5841 args->val = val; 5842 args->check_rd = exit_reason_want == VMX_VMCALL; 5843 args->virt_fn = expectation->virt_fn; 5844 5845 /* Setup virtual APIC page */ 5846 if (!expectation->virtualize_apic_accesses) { 5847 apic_access_address[apic_reg_index(reg)] = val; 5848 virtual_apic_page[apic_reg_index(reg)] = 0; 5849 } else if (exit_reason_want == VMX_VMCALL) { 5850 apic_access_address[apic_reg_index(reg)] = 0; 5851 virtual_apic_page[apic_reg_index(reg)] = val; 5852 } 5853 5854 /* Enter guest */ 5855 enter_guest(); 5856 5857 /* 5858 * Validate the behavior and 5859 * pass a magic value back to the guest. 5860 */ 5861 if (exit_reason_want == VMX_APIC_ACCESS) { 5862 u32 apic_page_offset = vmcs_read(EXI_QUALIFICATION) & 0xfff; 5863 5864 assert_exit_reason(exit_reason_want); 5865 report(apic_page_offset == reg, 5866 "got APIC access exit @ page offset 0x%03x, want 0x%03x", 5867 apic_page_offset, reg); 5868 skip_exit_insn(); 5869 5870 /* Reenter guest so it can consume/check rcx and exit again. */ 5871 enter_guest(); 5872 } else if (exit_reason_want != VMX_VMCALL) { 5873 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 5874 } 5875 5876 skip_exit_vmcall(); 5877 report_prefix_pop(); 5878 } 5879 5880 static void test_xapic_wr( 5881 u32 reg, struct apic_reg_virt_expectation *expectation, 5882 u32 *apic_access_address, u32 *virtual_apic_page) 5883 { 5884 u32 val = expectation->val; 5885 u32 exit_reason_want = expectation->wr_exit_reason; 5886 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 5887 bool virtualized = 5888 expectation->virtualize_apic_accesses && 5889 (exit_reason_want == VMX_APIC_WRITE || 5890 exit_reason_want == VMX_VMCALL); 5891 bool checked = false; 5892 5893 report_prefix_pushf("xapic - writing 0x%x to 0x%03x", val, reg); 5894 5895 /* Configure guest to do an xapic read */ 5896 args->op = APIC_OP_XAPIC_WR; 5897 args->apic_access_address = apic_access_address; 5898 args->reg = reg; 5899 args->val = val; 5900 5901 /* Setup virtual APIC page */ 5902 if (virtualized || !expectation->virtualize_apic_accesses) { 5903 apic_access_address[apic_reg_index(reg)] = 0; 5904 virtual_apic_page[apic_reg_index(reg)] = 0; 5905 } 5906 5907 /* Enter guest */ 5908 enter_guest(); 5909 5910 /* 5911 * Validate the behavior and 5912 * pass a magic value back to the guest. 5913 */ 5914 if (exit_reason_want == VMX_APIC_ACCESS) { 5915 u32 apic_page_offset = vmcs_read(EXI_QUALIFICATION) & 0xfff; 5916 5917 assert_exit_reason(exit_reason_want); 5918 report(apic_page_offset == reg, 5919 "got APIC access exit @ page offset 0x%03x, want 0x%03x", 5920 apic_page_offset, reg); 5921 skip_exit_insn(); 5922 5923 /* Reenter guest so it can consume/check rcx and exit again. */ 5924 enter_guest(); 5925 } else if (exit_reason_want == VMX_APIC_WRITE) { 5926 assert_exit_reason(exit_reason_want); 5927 report(virtual_apic_page[apic_reg_index(reg)] == val, 5928 "got APIC write exit @ page offset 0x%03x; val is 0x%x, want 0x%x", 5929 apic_reg_index(reg), 5930 virtual_apic_page[apic_reg_index(reg)], val); 5931 checked = true; 5932 5933 /* Reenter guest so it can consume/check rcx and exit again. */ 5934 enter_guest(); 5935 } else if (exit_reason_want != VMX_VMCALL) { 5936 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 5937 } 5938 5939 assert_exit_reason(VMX_VMCALL); 5940 if (virtualized && !checked) { 5941 u32 want = expectation->virt_fn(val); 5942 u32 got = virtual_apic_page[apic_reg_index(reg)]; 5943 got = expectation->virt_fn(got); 5944 5945 report(got == want, "exitless write; val is 0x%x, want 0x%x", 5946 got, want); 5947 } else if (!expectation->virtualize_apic_accesses && !checked) { 5948 u32 got = apic_access_address[apic_reg_index(reg)]; 5949 5950 report(got == val, 5951 "non-virtualized write; val is 0x%x, want 0x%x", got, 5952 val); 5953 } else if (!expectation->virtualize_apic_accesses && checked) { 5954 report_fail("Non-virtualized write was prematurely checked!"); 5955 } 5956 5957 skip_exit_vmcall(); 5958 report_prefix_pop(); 5959 } 5960 5961 enum Config_type { 5962 CONFIG_TYPE_GOOD, 5963 CONFIG_TYPE_UNSUPPORTED, 5964 CONFIG_TYPE_VMENTRY_FAILS_EARLY, 5965 }; 5966 5967 static enum Config_type configure_apic_reg_virt_test( 5968 struct apic_reg_virt_config *apic_reg_virt_config) 5969 { 5970 u32 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 5971 u32 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 5972 /* Configs where L2 entry fails early, due to invalid controls. */ 5973 bool use_tpr_shadow_incorrectly_off = 5974 !apic_reg_virt_config->use_tpr_shadow && 5975 (apic_reg_virt_config->apic_register_virtualization || 5976 apic_reg_virt_config->virtualize_x2apic_mode) && 5977 apic_reg_virt_config->activate_secondary_controls; 5978 bool virtualize_apic_accesses_incorrectly_on = 5979 apic_reg_virt_config->virtualize_apic_accesses && 5980 apic_reg_virt_config->virtualize_x2apic_mode && 5981 apic_reg_virt_config->activate_secondary_controls; 5982 bool vmentry_fails_early = 5983 use_tpr_shadow_incorrectly_off || 5984 virtualize_apic_accesses_incorrectly_on; 5985 5986 if (apic_reg_virt_config->activate_secondary_controls) { 5987 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 5988 printf("VM-execution control \"activate secondary controls\" NOT supported.\n"); 5989 return CONFIG_TYPE_UNSUPPORTED; 5990 } 5991 cpu_exec_ctrl0 |= CPU_SECONDARY; 5992 } else { 5993 cpu_exec_ctrl0 &= ~CPU_SECONDARY; 5994 } 5995 5996 if (apic_reg_virt_config->virtualize_apic_accesses) { 5997 if (!(ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES)) { 5998 printf("VM-execution control \"virtualize APIC accesses\" NOT supported.\n"); 5999 return CONFIG_TYPE_UNSUPPORTED; 6000 } 6001 cpu_exec_ctrl1 |= CPU_VIRT_APIC_ACCESSES; 6002 } else { 6003 cpu_exec_ctrl1 &= ~CPU_VIRT_APIC_ACCESSES; 6004 } 6005 6006 if (apic_reg_virt_config->use_tpr_shadow) { 6007 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) { 6008 printf("VM-execution control \"use TPR shadow\" NOT supported.\n"); 6009 return CONFIG_TYPE_UNSUPPORTED; 6010 } 6011 cpu_exec_ctrl0 |= CPU_TPR_SHADOW; 6012 } else { 6013 cpu_exec_ctrl0 &= ~CPU_TPR_SHADOW; 6014 } 6015 6016 if (apic_reg_virt_config->apic_register_virtualization) { 6017 if (!(ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT)) { 6018 printf("VM-execution control \"APIC-register virtualization\" NOT supported.\n"); 6019 return CONFIG_TYPE_UNSUPPORTED; 6020 } 6021 cpu_exec_ctrl1 |= CPU_APIC_REG_VIRT; 6022 } else { 6023 cpu_exec_ctrl1 &= ~CPU_APIC_REG_VIRT; 6024 } 6025 6026 if (apic_reg_virt_config->virtualize_x2apic_mode) { 6027 if (!(ctrl_cpu_rev[1].clr & CPU_VIRT_X2APIC)) { 6028 printf("VM-execution control \"virtualize x2APIC mode\" NOT supported.\n"); 6029 return CONFIG_TYPE_UNSUPPORTED; 6030 } 6031 cpu_exec_ctrl1 |= CPU_VIRT_X2APIC; 6032 } else { 6033 cpu_exec_ctrl1 &= ~CPU_VIRT_X2APIC; 6034 } 6035 6036 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6037 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6038 6039 if (vmentry_fails_early) 6040 return CONFIG_TYPE_VMENTRY_FAILS_EARLY; 6041 6042 return CONFIG_TYPE_GOOD; 6043 } 6044 6045 static bool cpu_has_apicv(void) 6046 { 6047 return ((ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT) && 6048 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 6049 (ctrl_pin_rev.clr & PIN_POST_INTR)); 6050 } 6051 6052 /* Validates APIC register access across valid virtualization configurations. */ 6053 static void apic_reg_virt_test(void) 6054 { 6055 u32 *apic_access_address; 6056 u32 *virtual_apic_page; 6057 u64 control; 6058 u64 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6059 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6060 int i; 6061 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 6062 6063 if (!cpu_has_apicv()) { 6064 report_skip("%s : Not all required APICv bits supported", __func__); 6065 return; 6066 } 6067 6068 control = cpu_exec_ctrl1; 6069 control &= ~CPU_VINTD; 6070 vmcs_write(CPU_EXEC_CTRL1, control); 6071 6072 test_set_guest(apic_reg_virt_guest); 6073 6074 /* 6075 * From the SDM: The 1-setting of the "virtualize APIC accesses" 6076 * VM-execution is guaranteed to apply only if translations to the 6077 * APIC-access address use a 4-KByte page. 6078 */ 6079 apic_access_address = alloc_page(); 6080 force_4k_page(apic_access_address); 6081 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_address)); 6082 6083 virtual_apic_page = alloc_page(); 6084 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 6085 6086 for (i = 0; i < ARRAY_SIZE(apic_reg_tests); i++) { 6087 struct apic_reg_test *apic_reg_test = &apic_reg_tests[i]; 6088 struct apic_reg_virt_config *apic_reg_virt_config = 6089 &apic_reg_test->apic_reg_virt_config; 6090 enum Config_type config_type; 6091 u32 reg; 6092 6093 printf("--- %s test ---\n", apic_reg_test->name); 6094 config_type = 6095 configure_apic_reg_virt_test(apic_reg_virt_config); 6096 if (config_type == CONFIG_TYPE_UNSUPPORTED) { 6097 printf("Skip because of missing features.\n"); 6098 continue; 6099 } 6100 6101 if (config_type == CONFIG_TYPE_VMENTRY_FAILS_EARLY) { 6102 enter_guest_with_bad_controls(); 6103 continue; 6104 } 6105 6106 for (reg = 0; reg < PAGE_SIZE / sizeof(u32); reg += 0x10) { 6107 struct apic_reg_virt_expectation expectation = {}; 6108 bool ok; 6109 6110 ok = apic_reg_virt_exit_expectation( 6111 reg, apic_reg_virt_config, &expectation); 6112 if (!ok) { 6113 report_fail("Malformed test."); 6114 break; 6115 } 6116 6117 test_xapic_rd(reg, &expectation, apic_access_address, 6118 virtual_apic_page); 6119 test_xapic_wr(reg, &expectation, apic_access_address, 6120 virtual_apic_page); 6121 } 6122 } 6123 6124 /* Terminate the guest */ 6125 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6126 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6127 args->op = TERMINATE; 6128 enter_guest(); 6129 assert_exit_reason(VMX_VMCALL); 6130 } 6131 6132 struct virt_x2apic_mode_config { 6133 struct apic_reg_virt_config apic_reg_virt_config; 6134 bool virtual_interrupt_delivery; 6135 bool use_msr_bitmaps; 6136 bool disable_x2apic_msr_intercepts; 6137 bool disable_x2apic; 6138 }; 6139 6140 struct virt_x2apic_mode_test_case { 6141 const char *name; 6142 struct virt_x2apic_mode_config virt_x2apic_mode_config; 6143 }; 6144 6145 enum Virt_x2apic_mode_behavior_type { 6146 X2APIC_ACCESS_VIRTUALIZED, 6147 X2APIC_ACCESS_PASSED_THROUGH, 6148 X2APIC_ACCESS_TRIGGERS_GP, 6149 }; 6150 6151 struct virt_x2apic_mode_expectation { 6152 enum Reason rd_exit_reason; 6153 enum Reason wr_exit_reason; 6154 6155 /* 6156 * RDMSR and WRMSR handle 64-bit values. However, except for ICR, all of 6157 * the x2APIC registers are 32 bits. Notice: 6158 * 1. vmx_x2apic_read() clears the upper 32 bits for 32-bit registers. 6159 * 2. vmx_x2apic_write() expects the val arg to be well-formed. 6160 */ 6161 u64 rd_val; 6162 u64 wr_val; 6163 6164 /* 6165 * Compares input to virtualized output; 6166 * 1st arg is pointer to return expected virtualization output. 6167 */ 6168 u64 (*virt_fn)(u64); 6169 6170 enum Virt_x2apic_mode_behavior_type rd_behavior; 6171 enum Virt_x2apic_mode_behavior_type wr_behavior; 6172 bool wr_only; 6173 }; 6174 6175 static u64 virt_x2apic_mode_identity(u64 val) 6176 { 6177 return val; 6178 } 6179 6180 static u64 virt_x2apic_mode_nibble1(u64 val) 6181 { 6182 return val & 0xf0; 6183 } 6184 6185 static void virt_x2apic_mode_rd_expectation( 6186 u32 reg, bool virt_x2apic_mode_on, bool disable_x2apic, 6187 bool apic_register_virtualization, bool virtual_interrupt_delivery, 6188 struct virt_x2apic_mode_expectation *expectation) 6189 { 6190 enum x2apic_reg_semantics semantics = get_x2apic_reg_semantics(reg); 6191 6192 expectation->rd_exit_reason = VMX_VMCALL; 6193 expectation->virt_fn = virt_x2apic_mode_identity; 6194 if (virt_x2apic_mode_on && apic_register_virtualization) { 6195 expectation->rd_val = MAGIC_VAL_1; 6196 if (reg == APIC_PROCPRI && virtual_interrupt_delivery) 6197 expectation->virt_fn = virt_x2apic_mode_nibble1; 6198 else if (reg == APIC_TASKPRI) 6199 expectation->virt_fn = virt_x2apic_mode_nibble1; 6200 expectation->rd_behavior = X2APIC_ACCESS_VIRTUALIZED; 6201 } else if (virt_x2apic_mode_on && !apic_register_virtualization && 6202 reg == APIC_TASKPRI) { 6203 expectation->rd_val = MAGIC_VAL_1; 6204 expectation->virt_fn = virt_x2apic_mode_nibble1; 6205 expectation->rd_behavior = X2APIC_ACCESS_VIRTUALIZED; 6206 } else if (!disable_x2apic && (semantics & X2APIC_READABLE)) { 6207 expectation->rd_val = apic_read(reg); 6208 expectation->rd_behavior = X2APIC_ACCESS_PASSED_THROUGH; 6209 } else { 6210 expectation->rd_behavior = X2APIC_ACCESS_TRIGGERS_GP; 6211 } 6212 } 6213 6214 /* 6215 * get_x2apic_wr_val() creates an innocuous write value for an x2APIC register. 6216 * 6217 * For writable registers, get_x2apic_wr_val() deposits the write value into the 6218 * val pointer arg and returns true. For non-writable registers, val is not 6219 * modified and get_x2apic_wr_val() returns false. 6220 */ 6221 static bool get_x2apic_wr_val(u32 reg, u64 *val) 6222 { 6223 switch (reg) { 6224 case APIC_TASKPRI: 6225 /* Bits 31:8 are reserved. */ 6226 *val &= 0xff; 6227 break; 6228 case APIC_EOI: 6229 case APIC_ESR: 6230 case APIC_TMICT: 6231 /* 6232 * EOI, ESR: WRMSR of a non-zero value causes #GP(0). 6233 * TMICT: A write of 0 to the initial-count register effectively 6234 * stops the local APIC timer, in both one-shot and 6235 * periodic mode. 6236 */ 6237 *val = 0; 6238 break; 6239 case APIC_SPIV: 6240 case APIC_LVTT: 6241 case APIC_LVTTHMR: 6242 case APIC_LVTPC: 6243 case APIC_LVT0: 6244 case APIC_LVT1: 6245 case APIC_LVTERR: 6246 case APIC_TDCR: 6247 /* 6248 * To avoid writing a 1 to a reserved bit or causing some other 6249 * unintended side effect, read the current value and use it as 6250 * the write value. 6251 */ 6252 *val = apic_read(reg); 6253 break; 6254 case APIC_CMCI: 6255 if (!apic_lvt_entry_supported(6)) 6256 return false; 6257 *val = apic_read(reg); 6258 break; 6259 case APIC_ICR: 6260 *val = 0x40000 | 0xf1; 6261 break; 6262 case APIC_SELF_IPI: 6263 /* 6264 * With special processing (i.e., virtualize x2APIC mode + 6265 * virtual interrupt delivery), writing zero causes an 6266 * APIC-write VM exit. We plan to add a test for enabling 6267 * "virtual-interrupt delivery" in VMCS12, and that's where we 6268 * will test a self IPI with special processing. 6269 */ 6270 *val = 0x0; 6271 break; 6272 default: 6273 return false; 6274 } 6275 6276 return true; 6277 } 6278 6279 static bool special_processing_applies(u32 reg, u64 *val, 6280 bool virt_int_delivery) 6281 { 6282 bool special_processing = 6283 (reg == APIC_TASKPRI) || 6284 (virt_int_delivery && 6285 (reg == APIC_EOI || reg == APIC_SELF_IPI)); 6286 6287 if (special_processing) { 6288 TEST_ASSERT(get_x2apic_wr_val(reg, val)); 6289 return true; 6290 } 6291 6292 return false; 6293 } 6294 6295 static void virt_x2apic_mode_wr_expectation( 6296 u32 reg, bool virt_x2apic_mode_on, bool disable_x2apic, 6297 bool virt_int_delivery, 6298 struct virt_x2apic_mode_expectation *expectation) 6299 { 6300 expectation->wr_exit_reason = VMX_VMCALL; 6301 expectation->wr_val = MAGIC_VAL_1; 6302 expectation->wr_only = false; 6303 6304 if (virt_x2apic_mode_on && 6305 special_processing_applies(reg, &expectation->wr_val, 6306 virt_int_delivery)) { 6307 expectation->wr_behavior = X2APIC_ACCESS_VIRTUALIZED; 6308 if (reg == APIC_SELF_IPI) 6309 expectation->wr_exit_reason = VMX_APIC_WRITE; 6310 } else if (!disable_x2apic && 6311 get_x2apic_wr_val(reg, &expectation->wr_val)) { 6312 expectation->wr_behavior = X2APIC_ACCESS_PASSED_THROUGH; 6313 if (reg == APIC_EOI || reg == APIC_SELF_IPI) 6314 expectation->wr_only = true; 6315 if (reg == APIC_ICR) 6316 expectation->wr_exit_reason = VMX_EXTINT; 6317 } else { 6318 expectation->wr_behavior = X2APIC_ACCESS_TRIGGERS_GP; 6319 /* 6320 * Writing 1 to a reserved bit triggers a #GP. 6321 * Thus, set the write value to 0, which seems 6322 * the most likely to detect a missed #GP. 6323 */ 6324 expectation->wr_val = 0; 6325 } 6326 } 6327 6328 static void virt_x2apic_mode_exit_expectation( 6329 u32 reg, struct virt_x2apic_mode_config *config, 6330 struct virt_x2apic_mode_expectation *expectation) 6331 { 6332 struct apic_reg_virt_config *base_config = 6333 &config->apic_reg_virt_config; 6334 bool virt_x2apic_mode_on = 6335 base_config->virtualize_x2apic_mode && 6336 config->use_msr_bitmaps && 6337 config->disable_x2apic_msr_intercepts && 6338 base_config->activate_secondary_controls; 6339 6340 virt_x2apic_mode_wr_expectation( 6341 reg, virt_x2apic_mode_on, config->disable_x2apic, 6342 config->virtual_interrupt_delivery, expectation); 6343 virt_x2apic_mode_rd_expectation( 6344 reg, virt_x2apic_mode_on, config->disable_x2apic, 6345 base_config->apic_register_virtualization, 6346 config->virtual_interrupt_delivery, expectation); 6347 } 6348 6349 struct virt_x2apic_mode_test_case virt_x2apic_mode_tests[] = { 6350 /* 6351 * Baseline "virtualize x2APIC mode" configuration: 6352 * - virtualize x2APIC mode 6353 * - virtual-interrupt delivery 6354 * - APIC-register virtualization 6355 * - x2APIC MSR intercepts disabled 6356 * 6357 * Reads come from virtual APIC page, special processing applies to 6358 * VTPR, EOI, and SELF IPI, and all other writes pass through to L1 6359 * APIC. 6360 */ 6361 { 6362 .name = "Baseline", 6363 .virt_x2apic_mode_config = { 6364 .virtual_interrupt_delivery = true, 6365 .use_msr_bitmaps = true, 6366 .disable_x2apic_msr_intercepts = true, 6367 .disable_x2apic = false, 6368 .apic_reg_virt_config = { 6369 .apic_register_virtualization = true, 6370 .use_tpr_shadow = true, 6371 .virtualize_apic_accesses = false, 6372 .virtualize_x2apic_mode = true, 6373 .activate_secondary_controls = true, 6374 }, 6375 }, 6376 }, 6377 { 6378 .name = "Baseline w/ x2apic disabled", 6379 .virt_x2apic_mode_config = { 6380 .virtual_interrupt_delivery = true, 6381 .use_msr_bitmaps = true, 6382 .disable_x2apic_msr_intercepts = true, 6383 .disable_x2apic = true, 6384 .apic_reg_virt_config = { 6385 .apic_register_virtualization = true, 6386 .use_tpr_shadow = true, 6387 .virtualize_apic_accesses = false, 6388 .virtualize_x2apic_mode = true, 6389 .activate_secondary_controls = true, 6390 }, 6391 }, 6392 }, 6393 6394 /* 6395 * Baseline, minus virtual-interrupt delivery. Reads come from virtual 6396 * APIC page, special processing applies to VTPR, and all other writes 6397 * pass through to L1 APIC. 6398 */ 6399 { 6400 .name = "Baseline - virtual interrupt delivery", 6401 .virt_x2apic_mode_config = { 6402 .virtual_interrupt_delivery = false, 6403 .use_msr_bitmaps = true, 6404 .disable_x2apic_msr_intercepts = true, 6405 .disable_x2apic = false, 6406 .apic_reg_virt_config = { 6407 .apic_register_virtualization = true, 6408 .use_tpr_shadow = true, 6409 .virtualize_apic_accesses = false, 6410 .virtualize_x2apic_mode = true, 6411 .activate_secondary_controls = true, 6412 }, 6413 }, 6414 }, 6415 6416 /* 6417 * Baseline, minus APIC-register virtualization. x2APIC reads pass 6418 * through to L1's APIC, unless reading VTPR 6419 */ 6420 { 6421 .name = "Virtualize x2APIC mode, no APIC reg virt", 6422 .virt_x2apic_mode_config = { 6423 .virtual_interrupt_delivery = true, 6424 .use_msr_bitmaps = true, 6425 .disable_x2apic_msr_intercepts = true, 6426 .disable_x2apic = false, 6427 .apic_reg_virt_config = { 6428 .apic_register_virtualization = false, 6429 .use_tpr_shadow = true, 6430 .virtualize_apic_accesses = false, 6431 .virtualize_x2apic_mode = true, 6432 .activate_secondary_controls = true, 6433 }, 6434 }, 6435 }, 6436 { 6437 .name = "Virtualize x2APIC mode, no APIC reg virt, x2APIC off", 6438 .virt_x2apic_mode_config = { 6439 .virtual_interrupt_delivery = true, 6440 .use_msr_bitmaps = true, 6441 .disable_x2apic_msr_intercepts = true, 6442 .disable_x2apic = true, 6443 .apic_reg_virt_config = { 6444 .apic_register_virtualization = false, 6445 .use_tpr_shadow = true, 6446 .virtualize_apic_accesses = false, 6447 .virtualize_x2apic_mode = true, 6448 .activate_secondary_controls = true, 6449 }, 6450 }, 6451 }, 6452 6453 /* 6454 * Enable "virtualize x2APIC mode" and "APIC-register virtualization", 6455 * and disable intercepts for the x2APIC MSRs, but fail to enable 6456 * "activate secondary controls" (i.e. L2 gets access to L1's x2APIC 6457 * MSRs). 6458 */ 6459 { 6460 .name = "Fail to enable activate secondary controls", 6461 .virt_x2apic_mode_config = { 6462 .virtual_interrupt_delivery = true, 6463 .use_msr_bitmaps = true, 6464 .disable_x2apic_msr_intercepts = true, 6465 .disable_x2apic = false, 6466 .apic_reg_virt_config = { 6467 .apic_register_virtualization = true, 6468 .use_tpr_shadow = true, 6469 .virtualize_apic_accesses = false, 6470 .virtualize_x2apic_mode = true, 6471 .activate_secondary_controls = false, 6472 }, 6473 }, 6474 }, 6475 6476 /* 6477 * Enable "APIC-register virtualization" and enable "activate secondary 6478 * controls" and disable intercepts for the x2APIC MSRs, but do not 6479 * enable the "virtualize x2APIC mode" VM-execution control (i.e. L2 6480 * gets access to L1's x2APIC MSRs). 6481 */ 6482 { 6483 .name = "Fail to enable virtualize x2APIC mode", 6484 .virt_x2apic_mode_config = { 6485 .virtual_interrupt_delivery = true, 6486 .use_msr_bitmaps = true, 6487 .disable_x2apic_msr_intercepts = true, 6488 .disable_x2apic = false, 6489 .apic_reg_virt_config = { 6490 .apic_register_virtualization = true, 6491 .use_tpr_shadow = true, 6492 .virtualize_apic_accesses = false, 6493 .virtualize_x2apic_mode = false, 6494 .activate_secondary_controls = true, 6495 }, 6496 }, 6497 }, 6498 6499 /* 6500 * Disable "Virtualize x2APIC mode", disable x2APIC MSR intercepts, and 6501 * enable "APIC-register virtualization" --> L2 gets L1's x2APIC MSRs. 6502 */ 6503 { 6504 .name = "Baseline", 6505 .virt_x2apic_mode_config = { 6506 .virtual_interrupt_delivery = true, 6507 .use_msr_bitmaps = true, 6508 .disable_x2apic_msr_intercepts = true, 6509 .disable_x2apic = false, 6510 .apic_reg_virt_config = { 6511 .apic_register_virtualization = true, 6512 .use_tpr_shadow = true, 6513 .virtualize_apic_accesses = false, 6514 .virtualize_x2apic_mode = false, 6515 .activate_secondary_controls = true, 6516 }, 6517 }, 6518 }, 6519 }; 6520 6521 enum X2apic_op { 6522 X2APIC_OP_RD, 6523 X2APIC_OP_WR, 6524 X2APIC_TERMINATE, 6525 }; 6526 6527 static u64 vmx_x2apic_read(u32 reg) 6528 { 6529 u32 msr_addr = x2apic_msr(reg); 6530 u64 val; 6531 6532 val = rdmsr(msr_addr); 6533 6534 return val; 6535 } 6536 6537 static void vmx_x2apic_write(u32 reg, u64 val) 6538 { 6539 u32 msr_addr = x2apic_msr(reg); 6540 6541 wrmsr(msr_addr, val); 6542 } 6543 6544 struct virt_x2apic_mode_guest_args { 6545 enum X2apic_op op; 6546 u32 reg; 6547 u64 val; 6548 bool should_gp; 6549 u64 (*virt_fn)(u64); 6550 } virt_x2apic_mode_guest_args; 6551 6552 static volatile bool handle_x2apic_gp_ran; 6553 static volatile u32 handle_x2apic_gp_insn_len; 6554 static void handle_x2apic_gp(struct ex_regs *regs) 6555 { 6556 handle_x2apic_gp_ran = true; 6557 regs->rip += handle_x2apic_gp_insn_len; 6558 } 6559 6560 static handler setup_x2apic_gp_handler(void) 6561 { 6562 handler old_handler; 6563 6564 old_handler = handle_exception(GP_VECTOR, handle_x2apic_gp); 6565 /* RDMSR and WRMSR are both 2 bytes, assuming no prefixes. */ 6566 handle_x2apic_gp_insn_len = 2; 6567 6568 return old_handler; 6569 } 6570 6571 static void teardown_x2apic_gp_handler(handler old_handler) 6572 { 6573 handle_exception(GP_VECTOR, old_handler); 6574 6575 /* 6576 * Defensively reset instruction length, so that if the handler is 6577 * incorrectly used, it will loop infinitely, rather than run off into 6578 * la la land. 6579 */ 6580 handle_x2apic_gp_insn_len = 0; 6581 handle_x2apic_gp_ran = false; 6582 } 6583 6584 static void virt_x2apic_mode_guest(void) 6585 { 6586 volatile struct virt_x2apic_mode_guest_args *args = 6587 &virt_x2apic_mode_guest_args; 6588 6589 for (;;) { 6590 enum X2apic_op op = args->op; 6591 u32 reg = args->reg; 6592 u64 val = args->val; 6593 bool should_gp = args->should_gp; 6594 u64 (*virt_fn)(u64) = args->virt_fn; 6595 handler old_handler; 6596 6597 if (op == X2APIC_TERMINATE) 6598 break; 6599 6600 if (should_gp) { 6601 TEST_ASSERT(!handle_x2apic_gp_ran); 6602 old_handler = setup_x2apic_gp_handler(); 6603 } 6604 6605 if (op == X2APIC_OP_RD) { 6606 u64 ret = vmx_x2apic_read(reg); 6607 6608 if (!should_gp) { 6609 u64 want = virt_fn(val); 6610 u64 got = virt_fn(ret); 6611 6612 report(got == want, 6613 "APIC read; got 0x%lx, want 0x%lx.", 6614 got, want); 6615 } 6616 } else if (op == X2APIC_OP_WR) { 6617 vmx_x2apic_write(reg, val); 6618 } 6619 6620 if (should_gp) { 6621 report(handle_x2apic_gp_ran, 6622 "x2APIC op triggered GP."); 6623 teardown_x2apic_gp_handler(old_handler); 6624 } 6625 6626 /* 6627 * The L1 should always execute a vmcall after it's done testing 6628 * an individual APIC operation. This helps to validate that the 6629 * L1 and L2 are in sync with each other, as expected. 6630 */ 6631 vmcall(); 6632 } 6633 } 6634 6635 static void test_x2apic_rd( 6636 u32 reg, struct virt_x2apic_mode_expectation *expectation, 6637 u32 *virtual_apic_page) 6638 { 6639 u64 val = expectation->rd_val; 6640 u32 exit_reason_want = expectation->rd_exit_reason; 6641 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6642 6643 report_prefix_pushf("x2apic - reading 0x%03x", reg); 6644 6645 /* Configure guest to do an x2apic read */ 6646 args->op = X2APIC_OP_RD; 6647 args->reg = reg; 6648 args->val = val; 6649 args->should_gp = expectation->rd_behavior == X2APIC_ACCESS_TRIGGERS_GP; 6650 args->virt_fn = expectation->virt_fn; 6651 6652 /* Setup virtual APIC page */ 6653 if (expectation->rd_behavior == X2APIC_ACCESS_VIRTUALIZED) 6654 virtual_apic_page[apic_reg_index(reg)] = (u32)val; 6655 6656 /* Enter guest */ 6657 enter_guest(); 6658 6659 if (exit_reason_want != VMX_VMCALL) { 6660 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 6661 } 6662 6663 skip_exit_vmcall(); 6664 report_prefix_pop(); 6665 } 6666 6667 static volatile bool handle_x2apic_ipi_ran; 6668 static void handle_x2apic_ipi(isr_regs_t *regs) 6669 { 6670 handle_x2apic_ipi_ran = true; 6671 eoi(); 6672 } 6673 6674 static void test_x2apic_wr( 6675 u32 reg, struct virt_x2apic_mode_expectation *expectation, 6676 u32 *virtual_apic_page) 6677 { 6678 u64 val = expectation->wr_val; 6679 u32 exit_reason_want = expectation->wr_exit_reason; 6680 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6681 int ipi_vector = 0xf1; 6682 u32 restore_val = 0; 6683 6684 report_prefix_pushf("x2apic - writing 0x%lx to 0x%03x", val, reg); 6685 6686 /* Configure guest to do an x2apic read */ 6687 args->op = X2APIC_OP_WR; 6688 args->reg = reg; 6689 args->val = val; 6690 args->should_gp = expectation->wr_behavior == X2APIC_ACCESS_TRIGGERS_GP; 6691 6692 /* Setup virtual APIC page */ 6693 if (expectation->wr_behavior == X2APIC_ACCESS_VIRTUALIZED) 6694 virtual_apic_page[apic_reg_index(reg)] = 0; 6695 if (expectation->wr_behavior == X2APIC_ACCESS_PASSED_THROUGH && !expectation->wr_only) 6696 restore_val = apic_read(reg); 6697 6698 /* Setup IPI handler */ 6699 handle_x2apic_ipi_ran = false; 6700 handle_irq(ipi_vector, handle_x2apic_ipi); 6701 6702 /* Enter guest */ 6703 enter_guest(); 6704 6705 /* 6706 * Validate the behavior and 6707 * pass a magic value back to the guest. 6708 */ 6709 if (exit_reason_want == VMX_EXTINT) { 6710 assert_exit_reason(exit_reason_want); 6711 6712 /* Clear the external interrupt. */ 6713 sti_nop_cli(); 6714 report(handle_x2apic_ipi_ran, 6715 "Got pending interrupt after IRQ enabled."); 6716 6717 enter_guest(); 6718 } else if (exit_reason_want == VMX_APIC_WRITE) { 6719 assert_exit_reason(exit_reason_want); 6720 report(virtual_apic_page[apic_reg_index(reg)] == val, 6721 "got APIC write exit @ page offset 0x%03x; val is 0x%x, want 0x%lx", 6722 apic_reg_index(reg), 6723 virtual_apic_page[apic_reg_index(reg)], val); 6724 6725 /* Reenter guest so it can consume/check rcx and exit again. */ 6726 enter_guest(); 6727 } else if (exit_reason_want != VMX_VMCALL) { 6728 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 6729 } 6730 6731 assert_exit_reason(VMX_VMCALL); 6732 if (expectation->wr_behavior == X2APIC_ACCESS_VIRTUALIZED) { 6733 u64 want = val; 6734 u32 got = virtual_apic_page[apic_reg_index(reg)]; 6735 6736 report(got == want, "x2APIC write; got 0x%x, want 0x%lx", got, 6737 want); 6738 } else if (expectation->wr_behavior == X2APIC_ACCESS_PASSED_THROUGH) { 6739 if (!expectation->wr_only) { 6740 u32 got = apic_read(reg); 6741 bool ok; 6742 6743 /* 6744 * When L1's TPR is passed through to L2, the lower 6745 * nibble can be lost. For example, if L2 executes 6746 * WRMSR(0x808, 0x78), then, L1 might read 0x70. 6747 * 6748 * Here's how the lower nibble can get lost: 6749 * 1. L2 executes WRMSR(0x808, 0x78). 6750 * 2. L2 exits to L0 with a WRMSR exit. 6751 * 3. L0 emulates WRMSR, by writing L1's TPR. 6752 * 4. L0 re-enters L2. 6753 * 5. L2 exits to L0 (reason doesn't matter). 6754 * 6. L0 reflects L2's exit to L1. 6755 * 7. Before entering L1, L0 exits to user-space 6756 * (e.g., to satisfy TPR access reporting). 6757 * 8. User-space executes KVM_SET_REGS ioctl, which 6758 * clears the lower nibble of L1's TPR. 6759 */ 6760 if (reg == APIC_TASKPRI) { 6761 got = apic_virt_nibble1(got); 6762 val = apic_virt_nibble1(val); 6763 } 6764 6765 ok = got == val; 6766 report(ok, 6767 "non-virtualized write; val is 0x%x, want 0x%lx", 6768 got, val); 6769 apic_write(reg, restore_val); 6770 } else { 6771 report_pass("non-virtualized and write-only OK"); 6772 } 6773 } 6774 skip_exit_insn(); 6775 6776 report_prefix_pop(); 6777 } 6778 6779 static enum Config_type configure_virt_x2apic_mode_test( 6780 struct virt_x2apic_mode_config *virt_x2apic_mode_config, 6781 u8 *msr_bitmap_page) 6782 { 6783 int msr; 6784 u32 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6785 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6786 6787 /* x2apic-specific VMCS config */ 6788 if (virt_x2apic_mode_config->use_msr_bitmaps) { 6789 /* virt_x2apic_mode_test() checks for MSR bitmaps support */ 6790 cpu_exec_ctrl0 |= CPU_MSR_BITMAP; 6791 } else { 6792 cpu_exec_ctrl0 &= ~CPU_MSR_BITMAP; 6793 } 6794 6795 if (virt_x2apic_mode_config->virtual_interrupt_delivery) { 6796 if (!(ctrl_cpu_rev[1].clr & CPU_VINTD)) { 6797 report_skip("%s : \"virtual-interrupt delivery\" exec control not supported", __func__); 6798 return CONFIG_TYPE_UNSUPPORTED; 6799 } 6800 cpu_exec_ctrl1 |= CPU_VINTD; 6801 } else { 6802 cpu_exec_ctrl1 &= ~CPU_VINTD; 6803 } 6804 6805 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6806 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6807 6808 /* x2APIC MSR intercepts are usually off for "Virtualize x2APIC mode" */ 6809 for (msr = 0x800; msr <= 0x8ff; msr++) { 6810 if (virt_x2apic_mode_config->disable_x2apic_msr_intercepts) { 6811 clear_bit(msr, msr_bitmap_page + 0x000); 6812 clear_bit(msr, msr_bitmap_page + 0x800); 6813 } else { 6814 set_bit(msr, msr_bitmap_page + 0x000); 6815 set_bit(msr, msr_bitmap_page + 0x800); 6816 } 6817 } 6818 6819 /* x2APIC mode can impact virtualization */ 6820 reset_apic(); 6821 if (!virt_x2apic_mode_config->disable_x2apic) 6822 enable_x2apic(); 6823 6824 return configure_apic_reg_virt_test( 6825 &virt_x2apic_mode_config->apic_reg_virt_config); 6826 } 6827 6828 static void virt_x2apic_mode_test(void) 6829 { 6830 u32 *virtual_apic_page; 6831 u8 *msr_bitmap_page; 6832 u64 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6833 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6834 int i; 6835 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6836 6837 if (!cpu_has_apicv()) { 6838 report_skip("%s : Not all required APICv bits supported", __func__); 6839 return; 6840 } 6841 6842 /* 6843 * This is to exercise an issue in KVM's logic to merge L0's and L1's 6844 * MSR bitmaps. Previously, an L1 could get at L0's x2APIC MSRs by 6845 * writing the IA32_SPEC_CTRL MSR or the IA32_PRED_CMD MSRs. KVM would 6846 * then proceed to manipulate the MSR bitmaps, as if VMCS12 had the 6847 * "Virtualize x2APIC mod" control set, even when it didn't. 6848 */ 6849 if (this_cpu_has(X86_FEATURE_SPEC_CTRL)) 6850 wrmsr(MSR_IA32_SPEC_CTRL, 1); 6851 6852 /* 6853 * Check that VMCS12 supports: 6854 * - "Virtual-APIC address", indicated by "use TPR shadow" 6855 * - "MSR-bitmap address", indicated by "use MSR bitmaps" 6856 */ 6857 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) { 6858 report_skip("%s : \"Use TPR shadow\" exec control not supported", __func__); 6859 return; 6860 } else if (!(ctrl_cpu_rev[0].clr & CPU_MSR_BITMAP)) { 6861 report_skip("%s : \"Use MSR bitmaps\" exec control not supported", __func__); 6862 return; 6863 } 6864 6865 test_set_guest(virt_x2apic_mode_guest); 6866 6867 virtual_apic_page = alloc_page(); 6868 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 6869 6870 msr_bitmap_page = alloc_page(); 6871 memset(msr_bitmap_page, 0xff, PAGE_SIZE); 6872 vmcs_write(MSR_BITMAP, virt_to_phys(msr_bitmap_page)); 6873 6874 for (i = 0; i < ARRAY_SIZE(virt_x2apic_mode_tests); i++) { 6875 struct virt_x2apic_mode_test_case *virt_x2apic_mode_test_case = 6876 &virt_x2apic_mode_tests[i]; 6877 struct virt_x2apic_mode_config *virt_x2apic_mode_config = 6878 &virt_x2apic_mode_test_case->virt_x2apic_mode_config; 6879 enum Config_type config_type; 6880 u32 reg; 6881 6882 printf("--- %s test ---\n", virt_x2apic_mode_test_case->name); 6883 config_type = 6884 configure_virt_x2apic_mode_test(virt_x2apic_mode_config, 6885 msr_bitmap_page); 6886 if (config_type == CONFIG_TYPE_UNSUPPORTED) { 6887 report_skip("Skip because of missing features."); 6888 continue; 6889 } else if (config_type == CONFIG_TYPE_VMENTRY_FAILS_EARLY) { 6890 enter_guest_with_bad_controls(); 6891 continue; 6892 } 6893 6894 for (reg = 0; reg < PAGE_SIZE / sizeof(u32); reg += 0x10) { 6895 struct virt_x2apic_mode_expectation expectation; 6896 6897 virt_x2apic_mode_exit_expectation( 6898 reg, virt_x2apic_mode_config, &expectation); 6899 6900 test_x2apic_rd(reg, &expectation, virtual_apic_page); 6901 test_x2apic_wr(reg, &expectation, virtual_apic_page); 6902 } 6903 } 6904 6905 6906 /* Terminate the guest */ 6907 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6908 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6909 args->op = X2APIC_TERMINATE; 6910 enter_guest(); 6911 assert_exit_reason(VMX_VMCALL); 6912 } 6913 6914 static void test_ctl_reg(const char *cr_name, u64 cr, u64 fixed0, u64 fixed1) 6915 { 6916 u64 val; 6917 u64 cr_saved = vmcs_read(cr); 6918 int i; 6919 6920 val = fixed0 & fixed1; 6921 if (cr == HOST_CR4) 6922 vmcs_write(cr, val | X86_CR4_PAE); 6923 else 6924 vmcs_write(cr, val); 6925 report_prefix_pushf("%s %lx", cr_name, val); 6926 if (val == fixed0) 6927 test_vmx_vmlaunch(0); 6928 else 6929 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 6930 report_prefix_pop(); 6931 6932 for (i = 0; i < 64; i++) { 6933 6934 /* Set a bit when the corresponding bit in fixed1 is 0 */ 6935 if ((fixed1 & (1ull << i)) == 0) { 6936 if (cr == HOST_CR4 && ((1ull << i) & X86_CR4_SMEP || 6937 (1ull << i) & X86_CR4_SMAP)) 6938 continue; 6939 6940 vmcs_write(cr, cr_saved | (1ull << i)); 6941 report_prefix_pushf("%s %llx", cr_name, 6942 cr_saved | (1ull << i)); 6943 test_vmx_vmlaunch( 6944 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 6945 report_prefix_pop(); 6946 } 6947 6948 /* Unset a bit when the corresponding bit in fixed0 is 1 */ 6949 if (fixed0 & (1ull << i)) { 6950 vmcs_write(cr, cr_saved & ~(1ull << i)); 6951 report_prefix_pushf("%s %llx", cr_name, 6952 cr_saved & ~(1ull << i)); 6953 test_vmx_vmlaunch( 6954 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 6955 report_prefix_pop(); 6956 } 6957 } 6958 6959 vmcs_write(cr, cr_saved); 6960 } 6961 6962 /* 6963 * 1. The CR0 field must not set any bit to a value not supported in VMX 6964 * operation. 6965 * 2. The CR4 field must not set any bit to a value not supported in VMX 6966 * operation. 6967 * 3. On processors that support Intel 64 architecture, the CR3 field must 6968 * be such that bits 63:52 and bits in the range 51:32 beyond the 6969 * processor's physical-address width must be 0. 6970 * 6971 * [Intel SDM] 6972 */ 6973 static void test_host_ctl_regs(void) 6974 { 6975 u64 fixed0, fixed1, cr3, cr3_saved; 6976 int i; 6977 6978 /* Test CR0 */ 6979 fixed0 = rdmsr(MSR_IA32_VMX_CR0_FIXED0); 6980 fixed1 = rdmsr(MSR_IA32_VMX_CR0_FIXED1); 6981 test_ctl_reg("HOST_CR0", HOST_CR0, fixed0, fixed1); 6982 6983 /* Test CR4 */ 6984 fixed0 = rdmsr(MSR_IA32_VMX_CR4_FIXED0); 6985 fixed1 = rdmsr(MSR_IA32_VMX_CR4_FIXED1) & 6986 ~(X86_CR4_SMEP | X86_CR4_SMAP); 6987 test_ctl_reg("HOST_CR4", HOST_CR4, fixed0, fixed1); 6988 6989 /* Test CR3 */ 6990 cr3_saved = vmcs_read(HOST_CR3); 6991 for (i = cpuid_maxphyaddr(); i < 64; i++) { 6992 cr3 = cr3_saved | (1ul << i); 6993 vmcs_write(HOST_CR3, cr3); 6994 report_prefix_pushf("HOST_CR3 %lx", cr3); 6995 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 6996 report_prefix_pop(); 6997 } 6998 6999 vmcs_write(HOST_CR3, cr3_saved); 7000 } 7001 7002 static void test_efer_vmlaunch(u32 fld, bool ok) 7003 { 7004 if (fld == HOST_EFER) { 7005 if (ok) 7006 test_vmx_vmlaunch(0); 7007 else 7008 test_vmx_vmlaunch2(VMXERR_ENTRY_INVALID_CONTROL_FIELD, 7009 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7010 } else { 7011 test_guest_state("EFER test", !ok, GUEST_EFER, "GUEST_EFER"); 7012 } 7013 } 7014 7015 static void test_efer_one(u32 fld, const char * fld_name, u64 efer, 7016 u32 ctrl_fld, u64 ctrl, 7017 int i, const char *efer_bit_name) 7018 { 7019 bool ok; 7020 7021 ok = true; 7022 if (ctrl_fld == EXI_CONTROLS && (ctrl & EXI_LOAD_EFER)) { 7023 if (!!(efer & EFER_LMA) != !!(ctrl & EXI_HOST_64)) 7024 ok = false; 7025 if (!!(efer & EFER_LME) != !!(ctrl & EXI_HOST_64)) 7026 ok = false; 7027 } 7028 if (ctrl_fld == ENT_CONTROLS && (ctrl & ENT_LOAD_EFER)) { 7029 /* Check LMA too since CR0.PG is set. */ 7030 if (!!(efer & EFER_LMA) != !!(ctrl & ENT_GUEST_64)) 7031 ok = false; 7032 if (!!(efer & EFER_LME) != !!(ctrl & ENT_GUEST_64)) 7033 ok = false; 7034 } 7035 7036 /* 7037 * Skip the test if it would enter the guest in 32-bit mode. 7038 * Perhaps write the test in assembly and make sure it 7039 * can be run in either mode? 7040 */ 7041 if (fld == GUEST_EFER && ok && !(ctrl & ENT_GUEST_64)) 7042 return; 7043 7044 vmcs_write(ctrl_fld, ctrl); 7045 vmcs_write(fld, efer); 7046 report_prefix_pushf("%s %s bit turned %s, controls %s", 7047 fld_name, efer_bit_name, 7048 (i & 1) ? "on" : "off", 7049 (i & 2) ? "on" : "off"); 7050 7051 test_efer_vmlaunch(fld, ok); 7052 report_prefix_pop(); 7053 } 7054 7055 static void test_efer_bit(u32 fld, const char * fld_name, 7056 u32 ctrl_fld, u64 ctrl_bit, u64 efer_bit, 7057 const char *efer_bit_name) 7058 { 7059 u64 efer_saved = vmcs_read(fld); 7060 u32 ctrl_saved = vmcs_read(ctrl_fld); 7061 int i; 7062 7063 for (i = 0; i < 4; i++) { 7064 u64 efer = efer_saved & ~efer_bit; 7065 u64 ctrl = ctrl_saved & ~ctrl_bit; 7066 7067 if (i & 1) 7068 efer |= efer_bit; 7069 if (i & 2) 7070 ctrl |= ctrl_bit; 7071 7072 test_efer_one(fld, fld_name, efer, ctrl_fld, ctrl, 7073 i, efer_bit_name); 7074 } 7075 7076 vmcs_write(ctrl_fld, ctrl_saved); 7077 vmcs_write(fld, efer_saved); 7078 } 7079 7080 static void test_efer(u32 fld, const char * fld_name, u32 ctrl_fld, 7081 u64 ctrl_bit1, u64 ctrl_bit2) 7082 { 7083 u64 efer_saved = vmcs_read(fld); 7084 u32 ctrl_saved = vmcs_read(ctrl_fld); 7085 u64 efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 7086 u64 i; 7087 u64 efer; 7088 7089 if (this_cpu_has(X86_FEATURE_NX)) 7090 efer_reserved_bits &= ~EFER_NX; 7091 7092 if (!ctrl_bit1) { 7093 report_skip("%s : \"Load-IA32-EFER\" exit control not supported", __func__); 7094 goto test_entry_exit_mode; 7095 } 7096 7097 report_prefix_pushf("%s %lx", fld_name, efer_saved); 7098 test_efer_vmlaunch(fld, true); 7099 report_prefix_pop(); 7100 7101 /* 7102 * Check reserved bits 7103 */ 7104 vmcs_write(ctrl_fld, ctrl_saved & ~ctrl_bit1); 7105 for (i = 0; i < 64; i++) { 7106 if ((1ull << i) & efer_reserved_bits) { 7107 efer = efer_saved | (1ull << i); 7108 vmcs_write(fld, efer); 7109 report_prefix_pushf("%s %lx", fld_name, efer); 7110 test_efer_vmlaunch(fld, true); 7111 report_prefix_pop(); 7112 } 7113 } 7114 7115 vmcs_write(ctrl_fld, ctrl_saved | ctrl_bit1); 7116 for (i = 0; i < 64; i++) { 7117 if ((1ull << i) & efer_reserved_bits) { 7118 efer = efer_saved | (1ull << i); 7119 vmcs_write(fld, efer); 7120 report_prefix_pushf("%s %lx", fld_name, efer); 7121 test_efer_vmlaunch(fld, false); 7122 report_prefix_pop(); 7123 } 7124 } 7125 7126 vmcs_write(ctrl_fld, ctrl_saved); 7127 vmcs_write(fld, efer_saved); 7128 7129 /* 7130 * Check LMA and LME bits 7131 */ 7132 test_efer_bit(fld, fld_name, 7133 ctrl_fld, ctrl_bit1, 7134 EFER_LMA, 7135 "EFER_LMA"); 7136 test_efer_bit(fld, fld_name, 7137 ctrl_fld, ctrl_bit1, 7138 EFER_LME, 7139 "EFER_LME"); 7140 7141 test_entry_exit_mode: 7142 test_efer_bit(fld, fld_name, 7143 ctrl_fld, ctrl_bit2, 7144 EFER_LMA, 7145 "EFER_LMA"); 7146 test_efer_bit(fld, fld_name, 7147 ctrl_fld, ctrl_bit2, 7148 EFER_LME, 7149 "EFER_LME"); 7150 } 7151 7152 /* 7153 * If the 'load IA32_EFER' VM-exit control is 1, bits reserved in the 7154 * IA32_EFER MSR must be 0 in the field for that register. In addition, 7155 * the values of the LMA and LME bits in the field must each be that of 7156 * the 'host address-space size' VM-exit control. 7157 * 7158 * [Intel SDM] 7159 */ 7160 static void test_host_efer(void) 7161 { 7162 test_efer(HOST_EFER, "HOST_EFER", EXI_CONTROLS, 7163 ctrl_exit_rev.clr & EXI_LOAD_EFER, 7164 EXI_HOST_64); 7165 } 7166 7167 /* 7168 * If the 'load IA32_EFER' VM-enter control is 1, bits reserved in the 7169 * IA32_EFER MSR must be 0 in the field for that register. In addition, 7170 * the values of the LMA and LME bits in the field must each be that of 7171 * the 'IA32e-mode guest' VM-exit control. 7172 */ 7173 static void test_guest_efer(void) 7174 { 7175 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) { 7176 report_skip("%s : \"Load-IA32-EFER\" entry control not supported", __func__); 7177 return; 7178 } 7179 7180 vmcs_write(GUEST_EFER, rdmsr(MSR_EFER)); 7181 test_efer(GUEST_EFER, "GUEST_EFER", ENT_CONTROLS, 7182 ctrl_enter_rev.clr & ENT_LOAD_EFER, 7183 ENT_GUEST_64); 7184 } 7185 7186 /* 7187 * PAT values higher than 8 are uninteresting since they're likely lumped 7188 * in with "8". We only test values above 8 one bit at a time, 7189 * in order to reduce the number of VM-Entries and keep the runtime reasonable. 7190 */ 7191 #define PAT_VAL_LIMIT 8 7192 7193 static void test_pat(u32 field, const char * field_name, u32 ctrl_field, 7194 u64 ctrl_bit) 7195 { 7196 u32 ctrl_saved = vmcs_read(ctrl_field); 7197 u64 pat_saved = vmcs_read(field); 7198 u64 i, val; 7199 u32 j; 7200 int error; 7201 7202 vmcs_clear_bits(ctrl_field, ctrl_bit); 7203 7204 for (i = 0; i < 256; i = (i < PAT_VAL_LIMIT) ? i + 1 : i * 2) { 7205 /* Test PAT0..PAT7 fields */ 7206 for (j = 0; j < (i ? 8 : 1); j++) { 7207 val = i << j * 8; 7208 vmcs_write(field, val); 7209 if (field == HOST_PAT) { 7210 report_prefix_pushf("%s %lx", field_name, val); 7211 test_vmx_vmlaunch(0); 7212 report_prefix_pop(); 7213 7214 } else { // GUEST_PAT 7215 test_guest_state("ENT_LOAD_PAT enabled", false, 7216 val, "GUEST_PAT"); 7217 } 7218 } 7219 } 7220 7221 vmcs_set_bits(ctrl_field, ctrl_bit); 7222 for (i = 0; i < 256; i = (i < PAT_VAL_LIMIT) ? i + 1 : i * 2) { 7223 /* Test PAT0..PAT7 fields */ 7224 for (j = 0; j < (i ? 8 : 1); j++) { 7225 val = i << j * 8; 7226 vmcs_write(field, val); 7227 7228 if (field == HOST_PAT) { 7229 report_prefix_pushf("%s %lx", field_name, val); 7230 if (i == 0x2 || i == 0x3 || i >= 0x8) 7231 error = 7232 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD; 7233 else 7234 error = 0; 7235 7236 test_vmx_vmlaunch(error); 7237 report_prefix_pop(); 7238 7239 } else { // GUEST_PAT 7240 error = (i == 0x2 || i == 0x3 || i >= 0x8); 7241 test_guest_state("ENT_LOAD_PAT enabled", !!error, 7242 val, "GUEST_PAT"); 7243 } 7244 7245 } 7246 } 7247 7248 vmcs_write(ctrl_field, ctrl_saved); 7249 vmcs_write(field, pat_saved); 7250 } 7251 7252 /* 7253 * If the "load IA32_PAT" VM-exit control is 1, the value of the field 7254 * for the IA32_PAT MSR must be one that could be written by WRMSR 7255 * without fault at CPL 0. Specifically, each of the 8 bytes in the 7256 * field must have one of the values 0 (UC), 1 (WC), 4 (WT), 5 (WP), 7257 * 6 (WB), or 7 (UC-). 7258 * 7259 * [Intel SDM] 7260 */ 7261 static void test_load_host_pat(void) 7262 { 7263 /* 7264 * "load IA32_PAT" VM-exit control 7265 */ 7266 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) { 7267 report_skip("%s : \"Load-IA32-PAT\" exit control not supported", __func__); 7268 return; 7269 } 7270 7271 test_pat(HOST_PAT, "HOST_PAT", EXI_CONTROLS, EXI_LOAD_PAT); 7272 } 7273 7274 union cpuidA_eax { 7275 struct { 7276 unsigned int version_id:8; 7277 unsigned int num_counters_gp:8; 7278 unsigned int bit_width:8; 7279 unsigned int mask_length:8; 7280 } split; 7281 unsigned int full; 7282 }; 7283 7284 union cpuidA_edx { 7285 struct { 7286 unsigned int num_counters_fixed:5; 7287 unsigned int bit_width_fixed:8; 7288 unsigned int reserved:9; 7289 } split; 7290 unsigned int full; 7291 }; 7292 7293 static bool valid_pgc(u64 val) 7294 { 7295 struct cpuid id; 7296 union cpuidA_eax eax; 7297 union cpuidA_edx edx; 7298 u64 mask; 7299 7300 id = cpuid(0xA); 7301 eax.full = id.a; 7302 edx.full = id.d; 7303 mask = ~(((1ull << eax.split.num_counters_gp) - 1) | 7304 (((1ull << edx.split.num_counters_fixed) - 1) << 32)); 7305 7306 return !(val & mask); 7307 } 7308 7309 static void test_pgc_vmlaunch(u32 xerror, u32 xreason, bool xfail, bool host) 7310 { 7311 u32 inst_err; 7312 u64 obs; 7313 bool success; 7314 struct vmx_state_area_test_data *data = &vmx_state_area_test_data; 7315 7316 if (host) { 7317 success = vmlaunch_succeeds(); 7318 obs = rdmsr(data->msr); 7319 if (!success) { 7320 inst_err = vmcs_read(VMX_INST_ERROR); 7321 report(xerror == inst_err, "vmlaunch failed, " 7322 "VMX Inst Error is %d (expected %d)", 7323 inst_err, xerror); 7324 } else { 7325 report(!data->enabled || data->exp == obs, 7326 "Host state is 0x%lx (expected 0x%lx)", 7327 obs, data->exp); 7328 report(success != xfail, "vmlaunch succeeded"); 7329 } 7330 } else { 7331 test_guest_state("load GUEST_PERF_GLOBAL_CTRL", xfail, 7332 GUEST_PERF_GLOBAL_CTRL, 7333 "GUEST_PERF_GLOBAL_CTRL"); 7334 } 7335 } 7336 7337 /* 7338 * test_load_perf_global_ctrl is a generic function for testing the 7339 * "load IA32_PERF_GLOBAL_CTRL" VM-{Entry,Exit} controls. This test function 7340 * tests the provided ctrl_val when disabled and enabled. 7341 * 7342 * @nr: VMCS field number corresponding to the host/guest state field 7343 * @name: Name of the above VMCS field for printing in test report 7344 * @ctrl_nr: VMCS field number corresponding to the VM-{Entry,Exit} control 7345 * @ctrl_val: Bit to set on the ctrl_field 7346 */ 7347 static void test_perf_global_ctrl(u32 nr, const char *name, u32 ctrl_nr, 7348 const char *ctrl_name, u64 ctrl_val) 7349 { 7350 u64 ctrl_saved = vmcs_read(ctrl_nr); 7351 u64 pgc_saved = vmcs_read(nr); 7352 u64 i, val; 7353 bool host = nr == HOST_PERF_GLOBAL_CTRL; 7354 struct vmx_state_area_test_data *data = &vmx_state_area_test_data; 7355 7356 data->msr = MSR_CORE_PERF_GLOBAL_CTRL; 7357 msr_bmp_init(); 7358 vmcs_write(ctrl_nr, ctrl_saved & ~ctrl_val); 7359 data->enabled = false; 7360 report_prefix_pushf("\"load IA32_PERF_GLOBAL_CTRL\"=0 on %s", 7361 ctrl_name); 7362 7363 for (i = 0; i < 64; i++) { 7364 val = 1ull << i; 7365 vmcs_write(nr, val); 7366 report_prefix_pushf("%s = 0x%lx", name, val); 7367 test_pgc_vmlaunch(0, VMX_VMCALL, false, host); 7368 report_prefix_pop(); 7369 } 7370 report_prefix_pop(); 7371 7372 vmcs_write(ctrl_nr, ctrl_saved | ctrl_val); 7373 data->enabled = true; 7374 report_prefix_pushf("\"load IA32_PERF_GLOBAL_CTRL\"=1 on %s", 7375 ctrl_name); 7376 for (i = 0; i < 64; i++) { 7377 val = 1ull << i; 7378 data->exp = val; 7379 vmcs_write(nr, val); 7380 report_prefix_pushf("%s = 0x%lx", name, val); 7381 if (valid_pgc(val)) { 7382 test_pgc_vmlaunch(0, VMX_VMCALL, false, host); 7383 } else { 7384 if (host) 7385 test_pgc_vmlaunch( 7386 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, 7387 0, 7388 true, 7389 host); 7390 else 7391 test_pgc_vmlaunch( 7392 0, 7393 VMX_ENTRY_FAILURE | VMX_FAIL_STATE, 7394 true, 7395 host); 7396 } 7397 report_prefix_pop(); 7398 } 7399 7400 data->enabled = false; 7401 report_prefix_pop(); 7402 vmcs_write(ctrl_nr, ctrl_saved); 7403 vmcs_write(nr, pgc_saved); 7404 } 7405 7406 static void test_load_host_perf_global_ctrl(void) 7407 { 7408 if (!this_cpu_has_perf_global_ctrl()) { 7409 report_skip("%s : \"IA32_PERF_GLOBAL_CTRL\" MSR not supported", __func__); 7410 return; 7411 } 7412 7413 if (!(ctrl_exit_rev.clr & EXI_LOAD_PERF)) { 7414 report_skip("%s : \"Load IA32_PERF_GLOBAL_CTRL\" exit control not supported", __func__); 7415 return; 7416 } 7417 7418 test_perf_global_ctrl(HOST_PERF_GLOBAL_CTRL, "HOST_PERF_GLOBAL_CTRL", 7419 EXI_CONTROLS, "EXI_CONTROLS", EXI_LOAD_PERF); 7420 } 7421 7422 7423 static void test_load_guest_perf_global_ctrl(void) 7424 { 7425 if (!this_cpu_has_perf_global_ctrl()) { 7426 report_skip("%s : \"IA32_PERF_GLOBAL_CTRL\" MSR not supported", __func__); 7427 return; 7428 } 7429 7430 if (!(ctrl_enter_rev.clr & ENT_LOAD_PERF)) { 7431 report_skip("%s : \"Load IA32_PERF_GLOBAL_CTRL\" entry control not supported", __func__); 7432 return; 7433 } 7434 7435 test_perf_global_ctrl(GUEST_PERF_GLOBAL_CTRL, "GUEST_PERF_GLOBAL_CTRL", 7436 ENT_CONTROLS, "ENT_CONTROLS", ENT_LOAD_PERF); 7437 } 7438 7439 7440 /* 7441 * test_vmcs_field - test a value for the given VMCS field 7442 * @field: VMCS field 7443 * @field_name: string name of VMCS field 7444 * @bit_start: starting bit 7445 * @bit_end: ending bit 7446 * @val: value that the bit range must or must not contain 7447 * @valid_val: whether value given in 'val' must be valid or not 7448 * @error: expected VMCS error when vmentry fails for an invalid value 7449 */ 7450 static void test_vmcs_field(u64 field, const char *field_name, u32 bit_start, 7451 u32 bit_end, u64 val, bool valid_val, u32 error) 7452 { 7453 u64 field_saved = vmcs_read(field); 7454 u32 i; 7455 u64 tmp; 7456 u32 bit_on; 7457 u64 mask = ~0ull; 7458 7459 mask = (mask >> bit_end) << bit_end; 7460 mask = mask | ((1 << bit_start) - 1); 7461 tmp = (field_saved & mask) | (val << bit_start); 7462 7463 vmcs_write(field, tmp); 7464 report_prefix_pushf("%s %lx", field_name, tmp); 7465 if (valid_val) 7466 test_vmx_vmlaunch(0); 7467 else 7468 test_vmx_vmlaunch(error); 7469 report_prefix_pop(); 7470 7471 for (i = bit_start; i <= bit_end; i = i + 2) { 7472 bit_on = ((1ull < i) & (val << bit_start)) ? 0 : 1; 7473 if (bit_on) 7474 tmp = field_saved | (1ull << i); 7475 else 7476 tmp = field_saved & ~(1ull << i); 7477 vmcs_write(field, tmp); 7478 report_prefix_pushf("%s %lx", field_name, tmp); 7479 if (valid_val) 7480 test_vmx_vmlaunch(error); 7481 else 7482 test_vmx_vmlaunch(0); 7483 report_prefix_pop(); 7484 } 7485 7486 vmcs_write(field, field_saved); 7487 } 7488 7489 static void test_canonical(u64 field, const char * field_name, bool host) 7490 { 7491 u64 addr_saved = vmcs_read(field); 7492 7493 /* 7494 * Use the existing value if possible. Writing a random canonical 7495 * value is not an option as doing so would corrupt the field being 7496 * tested and likely hose the test. 7497 */ 7498 if (is_canonical(addr_saved)) { 7499 if (host) { 7500 report_prefix_pushf("%s %lx", field_name, addr_saved); 7501 test_vmx_vmlaunch(0); 7502 report_prefix_pop(); 7503 } else { 7504 test_guest_state("Test canonical address", false, 7505 addr_saved, field_name); 7506 } 7507 } 7508 7509 vmcs_write(field, NONCANONICAL); 7510 7511 if (host) { 7512 report_prefix_pushf("%s %llx", field_name, NONCANONICAL); 7513 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7514 report_prefix_pop(); 7515 } else { 7516 test_guest_state("Test non-canonical address", true, 7517 NONCANONICAL, field_name); 7518 } 7519 7520 vmcs_write(field, addr_saved); 7521 } 7522 7523 #define TEST_RPL_TI_FLAGS(reg, name) \ 7524 test_vmcs_field(reg, name, 0, 2, 0x0, true, \ 7525 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7526 7527 #define TEST_CS_TR_FLAGS(reg, name) \ 7528 test_vmcs_field(reg, name, 3, 15, 0x0000, false, \ 7529 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7530 7531 /* 7532 * 1. In the selector field for each of CS, SS, DS, ES, FS, GS and TR, the 7533 * RPL (bits 1:0) and the TI flag (bit 2) must be 0. 7534 * 2. The selector fields for CS and TR cannot be 0000H. 7535 * 3. The selector field for SS cannot be 0000H if the "host address-space 7536 * size" VM-exit control is 0. 7537 * 4. On processors that support Intel 64 architecture, the base-address 7538 * fields for FS, GS and TR must contain canonical addresses. 7539 */ 7540 static void test_host_segment_regs(void) 7541 { 7542 u16 selector_saved; 7543 7544 /* 7545 * Test RPL and TI flags 7546 */ 7547 TEST_RPL_TI_FLAGS(HOST_SEL_CS, "HOST_SEL_CS"); 7548 TEST_RPL_TI_FLAGS(HOST_SEL_SS, "HOST_SEL_SS"); 7549 TEST_RPL_TI_FLAGS(HOST_SEL_DS, "HOST_SEL_DS"); 7550 TEST_RPL_TI_FLAGS(HOST_SEL_ES, "HOST_SEL_ES"); 7551 TEST_RPL_TI_FLAGS(HOST_SEL_FS, "HOST_SEL_FS"); 7552 TEST_RPL_TI_FLAGS(HOST_SEL_GS, "HOST_SEL_GS"); 7553 TEST_RPL_TI_FLAGS(HOST_SEL_TR, "HOST_SEL_TR"); 7554 7555 /* 7556 * Test that CS and TR fields can not be 0x0000 7557 */ 7558 TEST_CS_TR_FLAGS(HOST_SEL_CS, "HOST_SEL_CS"); 7559 TEST_CS_TR_FLAGS(HOST_SEL_TR, "HOST_SEL_TR"); 7560 7561 /* 7562 * SS field can not be 0x0000 if "host address-space size" VM-exit 7563 * control is 0 7564 */ 7565 selector_saved = vmcs_read(HOST_SEL_SS); 7566 vmcs_write(HOST_SEL_SS, 0); 7567 report_prefix_pushf("HOST_SEL_SS 0"); 7568 if (vmcs_read(EXI_CONTROLS) & EXI_HOST_64) { 7569 test_vmx_vmlaunch(0); 7570 } else { 7571 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7572 } 7573 report_prefix_pop(); 7574 7575 vmcs_write(HOST_SEL_SS, selector_saved); 7576 7577 /* 7578 * Base address for FS, GS and TR must be canonical 7579 */ 7580 test_canonical(HOST_BASE_FS, "HOST_BASE_FS", true); 7581 test_canonical(HOST_BASE_GS, "HOST_BASE_GS", true); 7582 test_canonical(HOST_BASE_TR, "HOST_BASE_TR", true); 7583 } 7584 7585 /* 7586 * On processors that support Intel 64 architecture, the base-address 7587 * fields for GDTR and IDTR must contain canonical addresses. 7588 */ 7589 static void test_host_desc_tables(void) 7590 { 7591 test_canonical(HOST_BASE_GDTR, "HOST_BASE_GDTR", true); 7592 test_canonical(HOST_BASE_IDTR, "HOST_BASE_IDTR", true); 7593 } 7594 7595 /* 7596 * If the "host address-space size" VM-exit control is 0, the following must 7597 * hold: 7598 * - The "IA-32e mode guest" VM-entry control is 0. 7599 * - Bit 17 of the CR4 field (corresponding to CR4.PCIDE) is 0. 7600 * - Bits 63:32 in the RIP field are 0. 7601 * 7602 * If the "host address-space size" VM-exit control is 1, the following must 7603 * hold: 7604 * - Bit 5 of the CR4 field (corresponding to CR4.PAE) is 1. 7605 * - The RIP field contains a canonical address. 7606 * 7607 */ 7608 static void test_host_addr_size(void) 7609 { 7610 u64 cr4_saved = vmcs_read(HOST_CR4); 7611 u64 rip_saved = vmcs_read(HOST_RIP); 7612 u64 entry_ctrl_saved = vmcs_read(ENT_CONTROLS); 7613 int i; 7614 u64 tmp; 7615 7616 if (vmcs_read(EXI_CONTROLS) & EXI_HOST_64) { 7617 vmcs_write(ENT_CONTROLS, entry_ctrl_saved | ENT_GUEST_64); 7618 report_prefix_pushf("\"IA-32e mode guest\" enabled"); 7619 test_vmx_vmlaunch(0); 7620 report_prefix_pop(); 7621 7622 vmcs_write(HOST_CR4, cr4_saved | X86_CR4_PCIDE); 7623 report_prefix_pushf("\"CR4.PCIDE\" set"); 7624 test_vmx_vmlaunch(0); 7625 report_prefix_pop(); 7626 7627 for (i = 32; i <= 63; i = i + 4) { 7628 tmp = rip_saved | 1ull << i; 7629 vmcs_write(HOST_RIP, tmp); 7630 report_prefix_pushf("HOST_RIP %lx", tmp); 7631 test_vmx_vmlaunch(0); 7632 report_prefix_pop(); 7633 } 7634 7635 if (cr4_saved & X86_CR4_PAE) { 7636 vmcs_write(HOST_CR4, cr4_saved & ~X86_CR4_PAE); 7637 report_prefix_pushf("\"CR4.PAE\" unset"); 7638 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7639 } else { 7640 report_prefix_pushf("\"CR4.PAE\" set"); 7641 test_vmx_vmlaunch(0); 7642 } 7643 report_prefix_pop(); 7644 7645 vmcs_write(HOST_RIP, NONCANONICAL); 7646 report_prefix_pushf("HOST_RIP %llx", NONCANONICAL); 7647 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7648 report_prefix_pop(); 7649 7650 vmcs_write(ENT_CONTROLS, entry_ctrl_saved | ENT_GUEST_64); 7651 vmcs_write(HOST_RIP, rip_saved); 7652 vmcs_write(HOST_CR4, cr4_saved); 7653 7654 /* Restore host's active RIP and CR4 values. */ 7655 report_prefix_pushf("restore host state"); 7656 test_vmx_vmlaunch(0); 7657 report_prefix_pop(); 7658 } 7659 } 7660 7661 /* 7662 * Check that the virtual CPU checks the VMX Host State Area as 7663 * documented in the Intel SDM. 7664 */ 7665 static void vmx_host_state_area_test(void) 7666 { 7667 /* 7668 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 7669 * fail due to invalid guest state, should we make it that 7670 * far. 7671 */ 7672 vmcs_write(GUEST_RFLAGS, 0); 7673 7674 test_host_ctl_regs(); 7675 7676 test_canonical(HOST_SYSENTER_ESP, "HOST_SYSENTER_ESP", true); 7677 test_canonical(HOST_SYSENTER_EIP, "HOST_SYSENTER_EIP", true); 7678 7679 test_host_efer(); 7680 test_load_host_pat(); 7681 test_host_segment_regs(); 7682 test_host_desc_tables(); 7683 test_host_addr_size(); 7684 test_load_host_perf_global_ctrl(); 7685 } 7686 7687 /* 7688 * If the "load debug controls" VM-entry control is 1, bits 63:32 in 7689 * the DR7 field must be 0. 7690 * 7691 * [Intel SDM] 7692 */ 7693 static void test_guest_dr7(void) 7694 { 7695 u32 ent_saved = vmcs_read(ENT_CONTROLS); 7696 u64 dr7_saved = vmcs_read(GUEST_DR7); 7697 u64 val; 7698 int i; 7699 7700 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS) { 7701 vmcs_clear_bits(ENT_CONTROLS, ENT_LOAD_DBGCTLS); 7702 for (i = 0; i < 64; i++) { 7703 val = 1ull << i; 7704 vmcs_write(GUEST_DR7, val); 7705 test_guest_state("ENT_LOAD_DBGCTLS disabled", false, 7706 val, "GUEST_DR7"); 7707 } 7708 } 7709 if (ctrl_enter_rev.clr & ENT_LOAD_DBGCTLS) { 7710 vmcs_set_bits(ENT_CONTROLS, ENT_LOAD_DBGCTLS); 7711 for (i = 0; i < 64; i++) { 7712 val = 1ull << i; 7713 vmcs_write(GUEST_DR7, val); 7714 test_guest_state("ENT_LOAD_DBGCTLS enabled", i >= 32, 7715 val, "GUEST_DR7"); 7716 } 7717 } 7718 vmcs_write(GUEST_DR7, dr7_saved); 7719 vmcs_write(ENT_CONTROLS, ent_saved); 7720 } 7721 7722 /* 7723 * If the "load IA32_PAT" VM-entry control is 1, the value of the field 7724 * for the IA32_PAT MSR must be one that could be written by WRMSR 7725 * without fault at CPL 0. Specifically, each of the 8 bytes in the 7726 * field must have one of the values 0 (UC), 1 (WC), 4 (WT), 5 (WP), 7727 * 6 (WB), or 7 (UC-). 7728 * 7729 * [Intel SDM] 7730 */ 7731 static void test_load_guest_pat(void) 7732 { 7733 /* 7734 * "load IA32_PAT" VM-entry control 7735 */ 7736 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 7737 report_skip("%s : \"Load-IA32-PAT\" entry control not supported", __func__); 7738 return; 7739 } 7740 7741 test_pat(GUEST_PAT, "GUEST_PAT", ENT_CONTROLS, ENT_LOAD_PAT); 7742 } 7743 7744 #define MSR_IA32_BNDCFGS_RSVD_MASK 0x00000ffc 7745 7746 /* 7747 * If the "load IA32_BNDCFGS" VM-entry control is 1, the following 7748 * checks are performed on the field for the IA32_BNDCFGS MSR: 7749 * 7750 * - Bits reserved in the IA32_BNDCFGS MSR must be 0. 7751 * - The linear address in bits 63:12 must be canonical. 7752 * 7753 * [Intel SDM] 7754 */ 7755 static void test_load_guest_bndcfgs(void) 7756 { 7757 u64 bndcfgs_saved = vmcs_read(GUEST_BNDCFGS); 7758 u64 bndcfgs; 7759 7760 if (!(ctrl_enter_rev.clr & ENT_LOAD_BNDCFGS)) { 7761 report_skip("%s : \"Load-IA32-BNDCFGS\" entry control not supported", __func__); 7762 return; 7763 } 7764 7765 vmcs_clear_bits(ENT_CONTROLS, ENT_LOAD_BNDCFGS); 7766 7767 vmcs_write(GUEST_BNDCFGS, NONCANONICAL); 7768 test_guest_state("ENT_LOAD_BNDCFGS disabled", false, 7769 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7770 bndcfgs = bndcfgs_saved | MSR_IA32_BNDCFGS_RSVD_MASK; 7771 vmcs_write(GUEST_BNDCFGS, bndcfgs); 7772 test_guest_state("ENT_LOAD_BNDCFGS disabled", false, 7773 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7774 7775 vmcs_set_bits(ENT_CONTROLS, ENT_LOAD_BNDCFGS); 7776 7777 vmcs_write(GUEST_BNDCFGS, NONCANONICAL); 7778 test_guest_state("ENT_LOAD_BNDCFGS enabled", true, 7779 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7780 bndcfgs = bndcfgs_saved | MSR_IA32_BNDCFGS_RSVD_MASK; 7781 vmcs_write(GUEST_BNDCFGS, bndcfgs); 7782 test_guest_state("ENT_LOAD_BNDCFGS enabled", true, 7783 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7784 7785 vmcs_write(GUEST_BNDCFGS, bndcfgs_saved); 7786 } 7787 7788 #define GUEST_SEG_UNUSABLE_MASK (1u << 16) 7789 #define GUEST_SEG_SEL_TI_MASK (1u << 2) 7790 7791 7792 #define TEST_SEGMENT_SEL(test, xfail, sel, val) \ 7793 do { \ 7794 vmcs_write(sel, val); \ 7795 test_guest_state(test " segment", xfail, val, xstr(sel)); \ 7796 } while (0) 7797 7798 #define TEST_INVALID_SEG_SEL(sel, val) \ 7799 TEST_SEGMENT_SEL("Invalid: " xstr(val), true, sel, val); 7800 7801 #define TEST_VALID_SEG_SEL(sel, val) \ 7802 TEST_SEGMENT_SEL("Valid: " xstr(val), false, sel, val); 7803 7804 /* 7805 * The following checks are done on the Selector field of the Guest Segment 7806 * Registers: 7807 * - TR. The TI flag (bit 2) must be 0. 7808 * - LDTR. If LDTR is usable, the TI flag (bit 2) must be 0. 7809 * - SS. If the guest will not be virtual-8086 and the "unrestricted 7810 * guest" VM-execution control is 0, the RPL (bits 1:0) must equal 7811 * the RPL of the selector field for CS. 7812 * 7813 * [Intel SDM] 7814 */ 7815 static void test_guest_segment_sel_fields(void) 7816 { 7817 u16 sel_saved; 7818 u32 ar_saved; 7819 u32 cpu_ctrl0_saved; 7820 u32 cpu_ctrl1_saved; 7821 u16 cs_rpl_bits; 7822 7823 /* 7824 * Test for GUEST_SEL_TR 7825 */ 7826 sel_saved = vmcs_read(GUEST_SEL_TR); 7827 TEST_INVALID_SEG_SEL(GUEST_SEL_TR, sel_saved | GUEST_SEG_SEL_TI_MASK); 7828 vmcs_write(GUEST_SEL_TR, sel_saved); 7829 7830 /* 7831 * Test for GUEST_SEL_LDTR 7832 */ 7833 sel_saved = vmcs_read(GUEST_SEL_LDTR); 7834 ar_saved = vmcs_read(GUEST_AR_LDTR); 7835 /* LDTR is set unusable */ 7836 vmcs_write(GUEST_AR_LDTR, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7837 TEST_VALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved | GUEST_SEG_SEL_TI_MASK); 7838 TEST_VALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved & ~GUEST_SEG_SEL_TI_MASK); 7839 /* LDTR is set usable */ 7840 vmcs_write(GUEST_AR_LDTR, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7841 TEST_INVALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved | GUEST_SEG_SEL_TI_MASK); 7842 7843 TEST_VALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved & ~GUEST_SEG_SEL_TI_MASK); 7844 7845 vmcs_write(GUEST_AR_LDTR, ar_saved); 7846 vmcs_write(GUEST_SEL_LDTR, sel_saved); 7847 7848 /* 7849 * Test for GUEST_SEL_SS 7850 */ 7851 cpu_ctrl0_saved = vmcs_read(CPU_EXEC_CTRL0); 7852 cpu_ctrl1_saved = vmcs_read(CPU_EXEC_CTRL1); 7853 ar_saved = vmcs_read(GUEST_AR_SS); 7854 /* Turn off "unrestricted guest" vm-execution control */ 7855 vmcs_write(CPU_EXEC_CTRL1, cpu_ctrl1_saved & ~CPU_URG); 7856 cs_rpl_bits = vmcs_read(GUEST_SEL_CS) & 0x3; 7857 sel_saved = vmcs_read(GUEST_SEL_SS); 7858 TEST_INVALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 7859 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 7860 /* Make SS usable if it's unusable or vice-versa */ 7861 if (ar_saved & GUEST_SEG_UNUSABLE_MASK) 7862 vmcs_write(GUEST_AR_SS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7863 else 7864 vmcs_write(GUEST_AR_SS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7865 TEST_INVALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 7866 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 7867 7868 /* Need a valid EPTP as the passing case fully enters the guest. */ 7869 if (enable_unrestricted_guest(true)) 7870 goto skip_ss_tests; 7871 7872 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 7873 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 7874 7875 /* Make SS usable if it's unusable or vice-versa */ 7876 if (vmcs_read(GUEST_AR_SS) & GUEST_SEG_UNUSABLE_MASK) 7877 vmcs_write(GUEST_AR_SS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7878 else 7879 vmcs_write(GUEST_AR_SS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7880 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 7881 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 7882 skip_ss_tests: 7883 7884 vmcs_write(GUEST_AR_SS, ar_saved); 7885 vmcs_write(GUEST_SEL_SS, sel_saved); 7886 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrl0_saved); 7887 vmcs_write(CPU_EXEC_CTRL1, cpu_ctrl1_saved); 7888 } 7889 7890 #define TEST_SEGMENT_BASE_ADDR_UPPER_BITS(xfail, seg_base) \ 7891 do { \ 7892 addr_saved = vmcs_read(seg_base); \ 7893 for (i = 32; i < 63; i = i + 4) { \ 7894 addr = addr_saved | 1ull << i; \ 7895 vmcs_write(seg_base, addr); \ 7896 test_guest_state("seg.BASE[63:32] != 0, usable = " xstr(xfail), \ 7897 xfail, addr, xstr(seg_base)); \ 7898 } \ 7899 vmcs_write(seg_base, addr_saved); \ 7900 } while (0) 7901 7902 #define TEST_SEGMENT_BASE_ADDR_CANONICAL(xfail, seg_base) \ 7903 do { \ 7904 addr_saved = vmcs_read(seg_base); \ 7905 vmcs_write(seg_base, NONCANONICAL); \ 7906 test_guest_state("seg.BASE non-canonical, usable = " xstr(xfail), \ 7907 xfail, NONCANONICAL, xstr(seg_base)); \ 7908 vmcs_write(seg_base, addr_saved); \ 7909 } while (0) 7910 7911 /* 7912 * The following checks are done on the Base Address field of the Guest 7913 * Segment Registers on processors that support Intel 64 architecture: 7914 * - TR, FS, GS : The address must be canonical. 7915 * - LDTR : If LDTR is usable, the address must be canonical. 7916 * - CS : Bits 63:32 of the address must be zero. 7917 * - SS, DS, ES : If the register is usable, bits 63:32 of the address 7918 * must be zero. 7919 * 7920 * [Intel SDM] 7921 */ 7922 static void test_guest_segment_base_addr_fields(void) 7923 { 7924 u64 addr_saved; 7925 u64 addr; 7926 u32 ar_saved; 7927 int i; 7928 7929 /* 7930 * The address of TR, FS, GS and LDTR must be canonical. 7931 */ 7932 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_TR); 7933 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_FS); 7934 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_GS); 7935 ar_saved = vmcs_read(GUEST_AR_LDTR); 7936 /* Make LDTR unusable */ 7937 vmcs_write(GUEST_AR_LDTR, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7938 TEST_SEGMENT_BASE_ADDR_CANONICAL(false, GUEST_BASE_LDTR); 7939 /* Make LDTR usable */ 7940 vmcs_write(GUEST_AR_LDTR, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7941 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_LDTR); 7942 7943 vmcs_write(GUEST_AR_LDTR, ar_saved); 7944 7945 /* 7946 * Bits 63:32 in CS, SS, DS and ES base address must be zero 7947 */ 7948 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_CS); 7949 ar_saved = vmcs_read(GUEST_AR_SS); 7950 /* Make SS unusable */ 7951 vmcs_write(GUEST_AR_SS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7952 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(false, GUEST_BASE_SS); 7953 /* Make SS usable */ 7954 vmcs_write(GUEST_AR_SS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7955 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_SS); 7956 vmcs_write(GUEST_AR_SS, ar_saved); 7957 7958 ar_saved = vmcs_read(GUEST_AR_DS); 7959 /* Make DS unusable */ 7960 vmcs_write(GUEST_AR_DS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7961 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(false, GUEST_BASE_DS); 7962 /* Make DS usable */ 7963 vmcs_write(GUEST_AR_DS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7964 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_DS); 7965 vmcs_write(GUEST_AR_DS, ar_saved); 7966 7967 ar_saved = vmcs_read(GUEST_AR_ES); 7968 /* Make ES unusable */ 7969 vmcs_write(GUEST_AR_ES, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7970 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(false, GUEST_BASE_ES); 7971 /* Make ES usable */ 7972 vmcs_write(GUEST_AR_ES, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7973 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_ES); 7974 vmcs_write(GUEST_AR_ES, ar_saved); 7975 } 7976 7977 /* 7978 * Check that the virtual CPU checks the VMX Guest State Area as 7979 * documented in the Intel SDM. 7980 */ 7981 static void vmx_guest_state_area_test(void) 7982 { 7983 vmx_set_test_stage(1); 7984 test_set_guest(guest_state_test_main); 7985 7986 /* 7987 * The IA32_SYSENTER_ESP field and the IA32_SYSENTER_EIP field 7988 * must each contain a canonical address. 7989 */ 7990 test_canonical(GUEST_SYSENTER_ESP, "GUEST_SYSENTER_ESP", false); 7991 test_canonical(GUEST_SYSENTER_EIP, "GUEST_SYSENTER_EIP", false); 7992 7993 test_guest_dr7(); 7994 test_load_guest_pat(); 7995 test_guest_efer(); 7996 test_load_guest_perf_global_ctrl(); 7997 test_load_guest_bndcfgs(); 7998 7999 test_guest_segment_sel_fields(); 8000 test_guest_segment_base_addr_fields(); 8001 8002 test_canonical(GUEST_BASE_GDTR, "GUEST_BASE_GDTR", false); 8003 test_canonical(GUEST_BASE_IDTR, "GUEST_BASE_IDTR", false); 8004 8005 u32 guest_desc_limit_saved = vmcs_read(GUEST_LIMIT_GDTR); 8006 int i; 8007 for (i = 16; i <= 31; i++) { 8008 u32 tmp = guest_desc_limit_saved | (1ull << i); 8009 vmcs_write(GUEST_LIMIT_GDTR, tmp); 8010 test_guest_state("GDT.limit > 0xffff", true, tmp, "GUEST_LIMIT_GDTR"); 8011 } 8012 vmcs_write(GUEST_LIMIT_GDTR, guest_desc_limit_saved); 8013 8014 guest_desc_limit_saved = vmcs_read(GUEST_LIMIT_IDTR); 8015 for (i = 16; i <= 31; i++) { 8016 u32 tmp = guest_desc_limit_saved | (1ull << i); 8017 vmcs_write(GUEST_LIMIT_IDTR, tmp); 8018 test_guest_state("IDT.limit > 0xffff", true, tmp, "GUEST_LIMIT_IDTR"); 8019 } 8020 vmcs_write(GUEST_LIMIT_IDTR, guest_desc_limit_saved); 8021 8022 /* 8023 * Let the guest finish execution 8024 */ 8025 vmx_set_test_stage(2); 8026 enter_guest(); 8027 } 8028 8029 extern void unrestricted_guest_main(void); 8030 asm (".code32\n" 8031 "unrestricted_guest_main:\n" 8032 "vmcall\n" 8033 "nop\n" 8034 "mov $1, %edi\n" 8035 "call hypercall\n" 8036 ".code64\n"); 8037 8038 static void setup_unrestricted_guest(void) 8039 { 8040 vmcs_write(GUEST_CR0, vmcs_read(GUEST_CR0) & ~(X86_CR0_PG)); 8041 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) & ~ENT_GUEST_64); 8042 vmcs_write(GUEST_EFER, vmcs_read(GUEST_EFER) & ~EFER_LMA); 8043 vmcs_write(GUEST_RIP, virt_to_phys(unrestricted_guest_main)); 8044 } 8045 8046 static void unsetup_unrestricted_guest(void) 8047 { 8048 vmcs_write(GUEST_CR0, vmcs_read(GUEST_CR0) | X86_CR0_PG); 8049 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) | ENT_GUEST_64); 8050 vmcs_write(GUEST_EFER, vmcs_read(GUEST_EFER) | EFER_LMA); 8051 vmcs_write(GUEST_RIP, (u64) phys_to_virt(vmcs_read(GUEST_RIP))); 8052 vmcs_write(GUEST_RSP, (u64) phys_to_virt(vmcs_read(GUEST_RSP))); 8053 } 8054 8055 /* 8056 * If "unrestricted guest" secondary VM-execution control is set, guests 8057 * can run in unpaged protected mode. 8058 */ 8059 static void vmentry_unrestricted_guest_test(void) 8060 { 8061 if (enable_unrestricted_guest(true)) { 8062 report_skip("%s: \"Unrestricted guest\" exec control not supported", __func__); 8063 return; 8064 } 8065 8066 test_set_guest(unrestricted_guest_main); 8067 setup_unrestricted_guest(); 8068 test_guest_state("Unrestricted guest test", false, CPU_URG, "CPU_URG"); 8069 8070 /* 8071 * Let the guest finish execution as a regular guest 8072 */ 8073 unsetup_unrestricted_guest(); 8074 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) & ~CPU_URG); 8075 enter_guest(); 8076 } 8077 8078 static bool valid_vmcs_for_vmentry(void) 8079 { 8080 struct vmcs *current_vmcs = NULL; 8081 8082 if (vmcs_save(¤t_vmcs)) 8083 return false; 8084 8085 return current_vmcs && !current_vmcs->hdr.shadow_vmcs; 8086 } 8087 8088 static void try_vmentry_in_movss_shadow(void) 8089 { 8090 u32 vm_inst_err; 8091 u32 flags; 8092 bool early_failure = false; 8093 u32 expected_flags = X86_EFLAGS_FIXED; 8094 bool valid_vmcs = valid_vmcs_for_vmentry(); 8095 8096 expected_flags |= valid_vmcs ? X86_EFLAGS_ZF : X86_EFLAGS_CF; 8097 8098 /* 8099 * Indirectly set VM_INST_ERR to 12 ("VMREAD/VMWRITE from/to 8100 * unsupported VMCS component"). 8101 */ 8102 vmcs_write(~0u, 0); 8103 8104 __asm__ __volatile__ ("mov %[host_rsp], %%edx;" 8105 "vmwrite %%rsp, %%rdx;" 8106 "mov 0f, %%rax;" 8107 "mov %[host_rip], %%edx;" 8108 "vmwrite %%rax, %%rdx;" 8109 "mov $-1, %%ah;" 8110 "sahf;" 8111 "mov %%ss, %%ax;" 8112 "mov %%ax, %%ss;" 8113 "vmlaunch;" 8114 "mov $1, %[early_failure];" 8115 "0: lahf;" 8116 "movzbl %%ah, %[flags]" 8117 : [early_failure] "+r" (early_failure), 8118 [flags] "=&a" (flags) 8119 : [host_rsp] "i" (HOST_RSP), 8120 [host_rip] "i" (HOST_RIP) 8121 : "rdx", "cc", "memory"); 8122 vm_inst_err = vmcs_read(VMX_INST_ERROR); 8123 8124 report(early_failure, "Early VM-entry failure"); 8125 report(flags == expected_flags, "RFLAGS[8:0] is %x (actual %x)", 8126 expected_flags, flags); 8127 if (valid_vmcs) 8128 report(vm_inst_err == VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, 8129 "VM-instruction error is %d (actual %d)", 8130 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, vm_inst_err); 8131 } 8132 8133 static void vmentry_movss_shadow_test(void) 8134 { 8135 struct vmcs *orig_vmcs; 8136 8137 TEST_ASSERT(!vmcs_save(&orig_vmcs)); 8138 8139 /* 8140 * Set the launched flag on the current VMCS to verify the correct 8141 * error priority, below. 8142 */ 8143 test_set_guest(v2_null_test_guest); 8144 enter_guest(); 8145 8146 /* 8147 * With bit 1 of the guest's RFLAGS clear, VM-entry should 8148 * fail due to invalid guest state (if we make it that far). 8149 */ 8150 vmcs_write(GUEST_RFLAGS, 0); 8151 8152 /* 8153 * "VM entry with events blocked by MOV SS" takes precedence over 8154 * "VMLAUNCH with non-clear VMCS." 8155 */ 8156 report_prefix_push("valid current-VMCS"); 8157 try_vmentry_in_movss_shadow(); 8158 report_prefix_pop(); 8159 8160 /* 8161 * VMfailInvalid takes precedence over "VM entry with events 8162 * blocked by MOV SS." 8163 */ 8164 TEST_ASSERT(!vmcs_clear(orig_vmcs)); 8165 report_prefix_push("no current-VMCS"); 8166 try_vmentry_in_movss_shadow(); 8167 report_prefix_pop(); 8168 8169 TEST_ASSERT(!make_vmcs_current(orig_vmcs)); 8170 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 8171 } 8172 8173 static void vmx_ldtr_test_guest(void) 8174 { 8175 u16 ldtr = sldt(); 8176 8177 report(ldtr == NP_SEL, "Expected %x for L2 LDTR selector (got %x)", 8178 NP_SEL, ldtr); 8179 } 8180 8181 /* 8182 * Ensure that the L1 LDTR is set to 0 on VM-exit. 8183 */ 8184 static void vmx_ldtr_test(void) 8185 { 8186 const u8 ldt_ar = 0x82; /* Present LDT */ 8187 u16 sel = FIRST_SPARE_SEL; 8188 8189 /* Set up a non-zero L1 LDTR prior to VM-entry. */ 8190 set_gdt_entry(sel, 0, 0, ldt_ar, 0); 8191 lldt(sel); 8192 8193 test_set_guest(vmx_ldtr_test_guest); 8194 /* 8195 * Set up a different LDTR for L2. The actual GDT contents are 8196 * irrelevant, since we stuff the hidden descriptor state 8197 * straight into the VMCS rather than reading it from the GDT. 8198 */ 8199 vmcs_write(GUEST_SEL_LDTR, NP_SEL); 8200 vmcs_write(GUEST_AR_LDTR, ldt_ar); 8201 enter_guest(); 8202 8203 /* 8204 * VM-exit should clear LDTR (and make it unusable, but we 8205 * won't verify that here). 8206 */ 8207 sel = sldt(); 8208 report(!sel, "Expected 0 for L1 LDTR selector (got %x)", sel); 8209 } 8210 8211 static void vmx_single_vmcall_guest(void) 8212 { 8213 vmcall(); 8214 } 8215 8216 static void vmx_cr_load_test(void) 8217 { 8218 unsigned long cr3, cr4, orig_cr3, orig_cr4; 8219 u32 ctrls[2] = {0}; 8220 pgd_t *pml5; 8221 8222 orig_cr4 = read_cr4(); 8223 orig_cr3 = read_cr3(); 8224 8225 if (!this_cpu_has(X86_FEATURE_PCID)) { 8226 report_skip("%s : PCID not detected", __func__); 8227 return; 8228 } 8229 if (!this_cpu_has(X86_FEATURE_MCE)) { 8230 report_skip("%s : MCE not detected", __func__); 8231 return; 8232 } 8233 8234 TEST_ASSERT(!(orig_cr3 & X86_CR3_PCID_MASK)); 8235 8236 /* Enable PCID for L1. */ 8237 cr4 = orig_cr4 | X86_CR4_PCIDE; 8238 cr3 = orig_cr3 | 0x1; 8239 TEST_ASSERT(!write_cr4_safe(cr4)); 8240 write_cr3(cr3); 8241 8242 test_set_guest(vmx_single_vmcall_guest); 8243 vmcs_write(HOST_CR4, cr4); 8244 vmcs_write(HOST_CR3, cr3); 8245 enter_guest(); 8246 8247 /* 8248 * No exception is expected. 8249 * 8250 * NB. KVM loads the last guest write to CR4 into CR4 read 8251 * shadow. In order to trigger an exit to KVM, we can toggle a 8252 * bit that is owned by KVM. We use CR4.MCE, which shall 8253 * have no side effect because normally no guest MCE (e.g., as the 8254 * result of bad memory) would happen during this test. 8255 */ 8256 TEST_ASSERT(!write_cr4_safe(cr4 ^ X86_CR4_MCE)); 8257 8258 /* Cleanup L1 state. */ 8259 write_cr3(orig_cr3); 8260 TEST_ASSERT(!write_cr4_safe(orig_cr4)); 8261 8262 if (!this_cpu_has(X86_FEATURE_LA57)) 8263 goto done; 8264 8265 /* 8266 * Allocate a full page for PML5 to guarantee alignment, though only 8267 * the first entry needs to be filled (the test's virtual addresses 8268 * most definitely do not have any of bits 56:48 set). 8269 */ 8270 pml5 = alloc_page(); 8271 *pml5 = orig_cr3 | PT_PRESENT_MASK | PT_WRITABLE_MASK; 8272 8273 /* 8274 * Transition to/from 5-level paging in the host via VM-Exit. CR4.LA57 8275 * can't be toggled while long is active via MOV CR4, but there are no 8276 * such restrictions on VM-Exit. 8277 */ 8278 lol_5level: 8279 vmcs_write(HOST_CR4, orig_cr4 | X86_CR4_LA57); 8280 vmcs_write(HOST_CR3, virt_to_phys(pml5)); 8281 enter_guest(); 8282 8283 /* 8284 * VMREAD with a memory operand to verify KVM detects the LA57 change, 8285 * e.g. uses the correct guest root level in gva_to_gpa(). 8286 */ 8287 TEST_ASSERT(vmcs_readm(HOST_CR3) == virt_to_phys(pml5)); 8288 TEST_ASSERT(vmcs_readm(HOST_CR4) == (orig_cr4 | X86_CR4_LA57)); 8289 8290 vmcs_write(HOST_CR4, orig_cr4); 8291 vmcs_write(HOST_CR3, orig_cr3); 8292 enter_guest(); 8293 8294 TEST_ASSERT(vmcs_readm(HOST_CR3) == orig_cr3); 8295 TEST_ASSERT(vmcs_readm(HOST_CR4) == orig_cr4); 8296 8297 /* 8298 * And now do the same LA57 shenanigans with EPT enabled. KVM uses 8299 * two separate MMUs when L1 uses TDP, whereas the above shadow paging 8300 * version shares an MMU between L1 and L2. 8301 * 8302 * If the saved execution controls are non-zero then the EPT version 8303 * has already run. In that case, restore the old controls. If EPT 8304 * setup fails, e.g. EPT isn't supported, fall through and finish up. 8305 */ 8306 if (ctrls[0]) { 8307 vmcs_write(CPU_EXEC_CTRL0, ctrls[0]); 8308 vmcs_write(CPU_EXEC_CTRL1, ctrls[1]); 8309 } else if (!setup_ept(false)) { 8310 ctrls[0] = vmcs_read(CPU_EXEC_CTRL0); 8311 ctrls[1] = vmcs_read(CPU_EXEC_CTRL1); 8312 goto lol_5level; 8313 } 8314 8315 free_page(pml5); 8316 8317 done: 8318 skip_exit_vmcall(); 8319 enter_guest(); 8320 } 8321 8322 static void vmx_cr4_osxsave_test_guest(void) 8323 { 8324 write_cr4(read_cr4() & ~X86_CR4_OSXSAVE); 8325 } 8326 8327 /* 8328 * Ensure that kvm recalculates the L1 guest's CPUID.01H:ECX.OSXSAVE 8329 * after VM-exit from an L2 guest that sets CR4.OSXSAVE to a different 8330 * value than in L1. 8331 */ 8332 static void vmx_cr4_osxsave_test(void) 8333 { 8334 if (!this_cpu_has(X86_FEATURE_XSAVE)) { 8335 report_skip("%s : XSAVE not detected", __func__); 8336 return; 8337 } 8338 8339 if (!(read_cr4() & X86_CR4_OSXSAVE)) { 8340 unsigned long cr4 = read_cr4() | X86_CR4_OSXSAVE; 8341 8342 write_cr4(cr4); 8343 vmcs_write(GUEST_CR4, cr4); 8344 vmcs_write(HOST_CR4, cr4); 8345 } 8346 8347 TEST_ASSERT(this_cpu_has(X86_FEATURE_OSXSAVE)); 8348 8349 test_set_guest(vmx_cr4_osxsave_test_guest); 8350 enter_guest(); 8351 8352 TEST_ASSERT(this_cpu_has(X86_FEATURE_OSXSAVE)); 8353 } 8354 8355 /* 8356 * FNOP with both CR0.TS and CR0.EM clear should not generate #NM, and the L2 8357 * guest should exit normally. 8358 */ 8359 static void vmx_no_nm_test(void) 8360 { 8361 test_set_guest(fnop); 8362 vmcs_write(GUEST_CR0, read_cr0() & ~(X86_CR0_TS | X86_CR0_EM)); 8363 enter_guest(); 8364 } 8365 8366 bool vmx_pending_event_ipi_fired; 8367 static void vmx_pending_event_ipi_isr(isr_regs_t *regs) 8368 { 8369 vmx_pending_event_ipi_fired = true; 8370 eoi(); 8371 } 8372 8373 bool vmx_pending_event_guest_run; 8374 static void vmx_pending_event_guest(void) 8375 { 8376 vmcall(); 8377 vmx_pending_event_guest_run = true; 8378 } 8379 8380 static void vmx_pending_event_test_core(bool guest_hlt) 8381 { 8382 int ipi_vector = 0xf1; 8383 8384 vmx_pending_event_ipi_fired = false; 8385 handle_irq(ipi_vector, vmx_pending_event_ipi_isr); 8386 8387 vmx_pending_event_guest_run = false; 8388 test_set_guest(vmx_pending_event_guest); 8389 8390 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 8391 8392 enter_guest(); 8393 skip_exit_vmcall(); 8394 8395 if (guest_hlt) 8396 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8397 8398 cli(); 8399 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | 8400 APIC_DM_FIXED | ipi_vector, 8401 0); 8402 8403 enter_guest(); 8404 8405 assert_exit_reason(VMX_EXTINT); 8406 report(!vmx_pending_event_guest_run, 8407 "Guest did not run before host received IPI"); 8408 8409 sti_nop_cli(); 8410 report(vmx_pending_event_ipi_fired, 8411 "Got pending interrupt after IRQ enabled"); 8412 8413 if (guest_hlt) 8414 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 8415 8416 enter_guest(); 8417 report(vmx_pending_event_guest_run, 8418 "Guest finished running when no interrupt"); 8419 } 8420 8421 static void vmx_pending_event_test(void) 8422 { 8423 vmx_pending_event_test_core(false); 8424 } 8425 8426 static void vmx_pending_event_hlt_test(void) 8427 { 8428 vmx_pending_event_test_core(true); 8429 } 8430 8431 static int vmx_window_test_db_count; 8432 8433 static void vmx_window_test_db_handler(struct ex_regs *regs) 8434 { 8435 vmx_window_test_db_count++; 8436 } 8437 8438 static void vmx_nmi_window_test_guest(void) 8439 { 8440 handle_exception(DB_VECTOR, vmx_window_test_db_handler); 8441 8442 asm volatile("vmcall\n\t" 8443 "nop\n\t"); 8444 8445 handle_exception(DB_VECTOR, NULL); 8446 } 8447 8448 static void verify_nmi_window_exit(u64 rip) 8449 { 8450 u32 exit_reason = vmcs_read(EXI_REASON); 8451 8452 report(exit_reason == VMX_NMI_WINDOW, 8453 "Exit reason (%d) is 'NMI window'", exit_reason); 8454 report(vmcs_read(GUEST_RIP) == rip, "RIP (%#lx) is %#lx", 8455 vmcs_read(GUEST_RIP), rip); 8456 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 8457 } 8458 8459 static void vmx_nmi_window_test(void) 8460 { 8461 u64 nop_addr; 8462 void *db_fault_addr = get_idt_addr(&boot_idt[DB_VECTOR]); 8463 8464 if (!(ctrl_pin_rev.clr & PIN_VIRT_NMI)) { 8465 report_skip("%s : \"Virtual NMIs\" exec control not supported", __func__); 8466 return; 8467 } 8468 8469 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 8470 report_skip("%s : \"NMI-window exiting\" exec control not supported", __func__); 8471 return; 8472 } 8473 8474 vmx_window_test_db_count = 0; 8475 8476 report_prefix_push("NMI-window"); 8477 test_set_guest(vmx_nmi_window_test_guest); 8478 vmcs_set_bits(PIN_CONTROLS, PIN_VIRT_NMI); 8479 enter_guest(); 8480 skip_exit_vmcall(); 8481 nop_addr = vmcs_read(GUEST_RIP); 8482 8483 /* 8484 * Ask for "NMI-window exiting," and expect an immediate VM-exit. 8485 * RIP will not advance. 8486 */ 8487 report_prefix_push("active, no blocking"); 8488 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 8489 enter_guest(); 8490 verify_nmi_window_exit(nop_addr); 8491 report_prefix_pop(); 8492 8493 /* 8494 * Ask for "NMI-window exiting" in a MOV-SS shadow, and expect 8495 * a VM-exit on the next instruction after the nop. (The nop 8496 * is one byte.) 8497 */ 8498 report_prefix_push("active, blocking by MOV-SS"); 8499 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 8500 enter_guest(); 8501 verify_nmi_window_exit(nop_addr + 1); 8502 report_prefix_pop(); 8503 8504 /* 8505 * Ask for "NMI-window exiting" (with event injection), and 8506 * expect a VM-exit after the event is injected. (RIP should 8507 * be at the address specified in the IDT entry for #DB.) 8508 */ 8509 report_prefix_push("active, no blocking, injecting #DB"); 8510 vmcs_write(ENT_INTR_INFO, 8511 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 8512 enter_guest(); 8513 verify_nmi_window_exit((u64)db_fault_addr); 8514 report_prefix_pop(); 8515 8516 /* 8517 * Ask for "NMI-window exiting" with NMI blocking, and expect 8518 * a VM-exit after the next IRET (i.e. after the #DB handler 8519 * returns). So, RIP should be back at one byte past the nop. 8520 */ 8521 report_prefix_push("active, blocking by NMI"); 8522 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_NMI); 8523 enter_guest(); 8524 verify_nmi_window_exit(nop_addr + 1); 8525 report(vmx_window_test_db_count == 1, 8526 "#DB handler executed once (actual %d times)", 8527 vmx_window_test_db_count); 8528 report_prefix_pop(); 8529 8530 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 8531 report_skip("CPU does not support activity state HLT."); 8532 } else { 8533 /* 8534 * Ask for "NMI-window exiting" when entering activity 8535 * state HLT, and expect an immediate VM-exit. RIP is 8536 * still one byte past the nop. 8537 */ 8538 report_prefix_push("halted, no blocking"); 8539 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8540 enter_guest(); 8541 verify_nmi_window_exit(nop_addr + 1); 8542 report_prefix_pop(); 8543 8544 /* 8545 * Ask for "NMI-window exiting" when entering activity 8546 * state HLT (with event injection), and expect a 8547 * VM-exit after the event is injected. (RIP should be 8548 * at the address specified in the IDT entry for #DB.) 8549 */ 8550 report_prefix_push("halted, no blocking, injecting #DB"); 8551 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8552 vmcs_write(ENT_INTR_INFO, 8553 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 8554 DB_VECTOR); 8555 enter_guest(); 8556 verify_nmi_window_exit((u64)db_fault_addr); 8557 report_prefix_pop(); 8558 } 8559 8560 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 8561 enter_guest(); 8562 report_prefix_pop(); 8563 } 8564 8565 static void vmx_intr_window_test_guest(void) 8566 { 8567 handle_exception(DB_VECTOR, vmx_window_test_db_handler); 8568 8569 /* 8570 * The two consecutive STIs are to ensure that only the first 8571 * one has a shadow. Note that NOP and STI are one byte 8572 * instructions. 8573 */ 8574 asm volatile("vmcall\n\t" 8575 "nop\n\t" 8576 "sti\n\t" 8577 "sti\n\t"); 8578 8579 handle_exception(DB_VECTOR, NULL); 8580 } 8581 8582 static void verify_intr_window_exit(u64 rip) 8583 { 8584 u32 exit_reason = vmcs_read(EXI_REASON); 8585 8586 report(exit_reason == VMX_INTR_WINDOW, 8587 "Exit reason (%d) is 'interrupt window'", exit_reason); 8588 report(vmcs_read(GUEST_RIP) == rip, "RIP (%#lx) is %#lx", 8589 vmcs_read(GUEST_RIP), rip); 8590 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 8591 } 8592 8593 static void vmx_intr_window_test(void) 8594 { 8595 u64 vmcall_addr; 8596 u64 nop_addr; 8597 unsigned int orig_db_gate_type; 8598 void *db_fault_addr = get_idt_addr(&boot_idt[DB_VECTOR]); 8599 8600 if (!(ctrl_cpu_rev[0].clr & CPU_INTR_WINDOW)) { 8601 report_skip("%s : \"Interrupt-window exiting\" exec control not supported", __func__); 8602 return; 8603 } 8604 8605 /* 8606 * Change the IDT entry for #DB from interrupt gate to trap gate, 8607 * so that it won't clear RFLAGS.IF. We don't want interrupts to 8608 * be disabled after vectoring a #DB. 8609 */ 8610 orig_db_gate_type = boot_idt[DB_VECTOR].type; 8611 boot_idt[DB_VECTOR].type = 15; 8612 8613 report_prefix_push("interrupt-window"); 8614 test_set_guest(vmx_intr_window_test_guest); 8615 enter_guest(); 8616 assert_exit_reason(VMX_VMCALL); 8617 vmcall_addr = vmcs_read(GUEST_RIP); 8618 8619 /* 8620 * Ask for "interrupt-window exiting" with RFLAGS.IF set and 8621 * no blocking; expect an immediate VM-exit. Note that we have 8622 * not advanced past the vmcall instruction yet, so RIP should 8623 * point to the vmcall instruction. 8624 */ 8625 report_prefix_push("active, no blocking, RFLAGS.IF=1"); 8626 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8627 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_IF); 8628 enter_guest(); 8629 verify_intr_window_exit(vmcall_addr); 8630 report_prefix_pop(); 8631 8632 /* 8633 * Ask for "interrupt-window exiting" (with event injection) 8634 * with RFLAGS.IF set and no blocking; expect a VM-exit after 8635 * the event is injected. That is, RIP should should be at the 8636 * address specified in the IDT entry for #DB. 8637 */ 8638 report_prefix_push("active, no blocking, RFLAGS.IF=1, injecting #DB"); 8639 vmcs_write(ENT_INTR_INFO, 8640 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 8641 vmcall_addr = vmcs_read(GUEST_RIP); 8642 enter_guest(); 8643 verify_intr_window_exit((u64)db_fault_addr); 8644 report_prefix_pop(); 8645 8646 /* 8647 * Let the L2 guest run through the IRET, back to the VMCALL. 8648 * We have to clear the "interrupt-window exiting" 8649 * VM-execution control, or it would just keep causing 8650 * VM-exits. Then, advance past the VMCALL and set the 8651 * "interrupt-window exiting" VM-execution control again. 8652 */ 8653 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8654 enter_guest(); 8655 skip_exit_vmcall(); 8656 nop_addr = vmcs_read(GUEST_RIP); 8657 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8658 8659 /* 8660 * Ask for "interrupt-window exiting" in a MOV-SS shadow with 8661 * RFLAGS.IF set, and expect a VM-exit on the next 8662 * instruction. (NOP is one byte.) 8663 */ 8664 report_prefix_push("active, blocking by MOV-SS, RFLAGS.IF=1"); 8665 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 8666 enter_guest(); 8667 verify_intr_window_exit(nop_addr + 1); 8668 report_prefix_pop(); 8669 8670 /* 8671 * Back up to the NOP and ask for "interrupt-window exiting" 8672 * in an STI shadow with RFLAGS.IF set, and expect a VM-exit 8673 * on the next instruction. (NOP is one byte.) 8674 */ 8675 report_prefix_push("active, blocking by STI, RFLAGS.IF=1"); 8676 vmcs_write(GUEST_RIP, nop_addr); 8677 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_STI); 8678 enter_guest(); 8679 verify_intr_window_exit(nop_addr + 1); 8680 report_prefix_pop(); 8681 8682 /* 8683 * Ask for "interrupt-window exiting" with RFLAGS.IF clear, 8684 * and expect a VM-exit on the instruction following the STI 8685 * shadow. Only the first STI (which is one byte past the NOP) 8686 * should have a shadow. The second STI (which is two bytes 8687 * past the NOP) has no shadow. Therefore, the interrupt 8688 * window opens at three bytes past the NOP. 8689 */ 8690 report_prefix_push("active, RFLAGS.IF = 0"); 8691 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 8692 enter_guest(); 8693 verify_intr_window_exit(nop_addr + 3); 8694 report_prefix_pop(); 8695 8696 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 8697 report_skip("CPU does not support activity state HLT."); 8698 } else { 8699 /* 8700 * Ask for "interrupt-window exiting" when entering 8701 * activity state HLT, and expect an immediate 8702 * VM-exit. RIP is still three bytes past the nop. 8703 */ 8704 report_prefix_push("halted, no blocking"); 8705 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8706 enter_guest(); 8707 verify_intr_window_exit(nop_addr + 3); 8708 report_prefix_pop(); 8709 8710 /* 8711 * Ask for "interrupt-window exiting" when entering 8712 * activity state HLT (with event injection), and 8713 * expect a VM-exit after the event is injected. That 8714 * is, RIP should should be at the address specified 8715 * in the IDT entry for #DB. 8716 */ 8717 report_prefix_push("halted, no blocking, injecting #DB"); 8718 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8719 vmcs_write(ENT_INTR_INFO, 8720 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 8721 DB_VECTOR); 8722 enter_guest(); 8723 verify_intr_window_exit((u64)db_fault_addr); 8724 report_prefix_pop(); 8725 } 8726 8727 boot_idt[DB_VECTOR].type = orig_db_gate_type; 8728 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8729 enter_guest(); 8730 report_prefix_pop(); 8731 } 8732 8733 #define GUEST_TSC_OFFSET (1u << 30) 8734 8735 static u64 guest_tsc; 8736 8737 static void vmx_store_tsc_test_guest(void) 8738 { 8739 guest_tsc = rdtsc(); 8740 } 8741 8742 /* 8743 * This test ensures that when IA32_TSC is in the VM-exit MSR-store 8744 * list, the value saved is not subject to the TSC offset that is 8745 * applied to RDTSC/RDTSCP/RDMSR(IA32_TSC) in guest execution. 8746 */ 8747 static void vmx_store_tsc_test(void) 8748 { 8749 struct vmx_msr_entry msr_entry = { .index = MSR_IA32_TSC }; 8750 u64 low, high; 8751 8752 if (!(ctrl_cpu_rev[0].clr & CPU_USE_TSC_OFFSET)) { 8753 report_skip("%s : \"Use TSC offsetting\" exec control not supported", __func__); 8754 return; 8755 } 8756 8757 test_set_guest(vmx_store_tsc_test_guest); 8758 8759 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_USE_TSC_OFFSET); 8760 vmcs_write(EXI_MSR_ST_CNT, 1); 8761 vmcs_write(EXIT_MSR_ST_ADDR, virt_to_phys(&msr_entry)); 8762 vmcs_write(TSC_OFFSET, GUEST_TSC_OFFSET); 8763 8764 low = rdtsc(); 8765 enter_guest(); 8766 high = rdtsc(); 8767 8768 report(low + GUEST_TSC_OFFSET <= guest_tsc && 8769 guest_tsc <= high + GUEST_TSC_OFFSET, 8770 "RDTSC value in the guest (%lu) is in range [%lu, %lu]", 8771 guest_tsc, low + GUEST_TSC_OFFSET, high + GUEST_TSC_OFFSET); 8772 report(low <= msr_entry.value && msr_entry.value <= high, 8773 "IA32_TSC value saved in the VM-exit MSR-store list (%lu) is in range [%lu, %lu]", 8774 msr_entry.value, low, high); 8775 } 8776 8777 static void vmx_preemption_timer_zero_test_db_handler(struct ex_regs *regs) 8778 { 8779 } 8780 8781 static void vmx_preemption_timer_zero_test_guest(void) 8782 { 8783 while (vmx_get_test_stage() < 3) 8784 vmcall(); 8785 } 8786 8787 static void vmx_preemption_timer_zero_activate_preemption_timer(void) 8788 { 8789 vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT); 8790 vmcs_write(PREEMPT_TIMER_VALUE, 0); 8791 } 8792 8793 static void vmx_preemption_timer_zero_advance_past_vmcall(void) 8794 { 8795 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 8796 enter_guest(); 8797 skip_exit_vmcall(); 8798 } 8799 8800 static void vmx_preemption_timer_zero_inject_db(bool intercept_db) 8801 { 8802 vmx_preemption_timer_zero_activate_preemption_timer(); 8803 vmcs_write(ENT_INTR_INFO, INTR_INFO_VALID_MASK | 8804 INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 8805 vmcs_write(EXC_BITMAP, intercept_db ? 1 << DB_VECTOR : 0); 8806 enter_guest(); 8807 } 8808 8809 static void vmx_preemption_timer_zero_set_pending_dbg(u32 exception_bitmap) 8810 { 8811 vmx_preemption_timer_zero_activate_preemption_timer(); 8812 vmcs_write(GUEST_PENDING_DEBUG, PENDING_DBG_TRAP | DR6_TRAP1); 8813 vmcs_write(EXC_BITMAP, exception_bitmap); 8814 enter_guest(); 8815 } 8816 8817 static void vmx_preemption_timer_zero_expect_preempt_at_rip(u64 expected_rip) 8818 { 8819 u32 reason = (u32)vmcs_read(EXI_REASON); 8820 u64 guest_rip = vmcs_read(GUEST_RIP); 8821 8822 report(reason == VMX_PREEMPT && guest_rip == expected_rip, 8823 "Exit reason is 0x%x (expected 0x%x) and guest RIP is %lx (0x%lx expected).", 8824 reason, VMX_PREEMPT, guest_rip, expected_rip); 8825 } 8826 8827 /* 8828 * This test ensures that when the VMX preemption timer is zero at 8829 * VM-entry, a VM-exit occurs after any event injection and after any 8830 * pending debug exceptions are raised, but before execution of any 8831 * guest instructions. 8832 */ 8833 static void vmx_preemption_timer_zero_test(void) 8834 { 8835 u64 db_fault_address = (u64)get_idt_addr(&boot_idt[DB_VECTOR]); 8836 handler old_db; 8837 u32 reason; 8838 8839 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 8840 report_skip("%s : \"Activate VMX-preemption timer\" pin control not supported", __func__); 8841 return; 8842 } 8843 8844 /* 8845 * Install a custom #DB handler that doesn't abort. 8846 */ 8847 old_db = handle_exception(DB_VECTOR, 8848 vmx_preemption_timer_zero_test_db_handler); 8849 8850 test_set_guest(vmx_preemption_timer_zero_test_guest); 8851 8852 /* 8853 * VMX-preemption timer should fire after event injection. 8854 */ 8855 vmx_set_test_stage(0); 8856 vmx_preemption_timer_zero_inject_db(0); 8857 vmx_preemption_timer_zero_expect_preempt_at_rip(db_fault_address); 8858 vmx_preemption_timer_zero_advance_past_vmcall(); 8859 8860 /* 8861 * VMX-preemption timer should fire after event injection. 8862 * Exception bitmap is irrelevant, since you can't intercept 8863 * an event that you injected. 8864 */ 8865 vmx_set_test_stage(1); 8866 vmx_preemption_timer_zero_inject_db(true); 8867 vmx_preemption_timer_zero_expect_preempt_at_rip(db_fault_address); 8868 vmx_preemption_timer_zero_advance_past_vmcall(); 8869 8870 /* 8871 * VMX-preemption timer should fire after pending debug exceptions 8872 * have delivered a #DB trap. 8873 */ 8874 vmx_set_test_stage(2); 8875 vmx_preemption_timer_zero_set_pending_dbg(0); 8876 vmx_preemption_timer_zero_expect_preempt_at_rip(db_fault_address); 8877 vmx_preemption_timer_zero_advance_past_vmcall(); 8878 8879 /* 8880 * VMX-preemption timer would fire after pending debug exceptions 8881 * have delivered a #DB trap, but in this case, the #DB trap is 8882 * intercepted. 8883 */ 8884 vmx_set_test_stage(3); 8885 vmx_preemption_timer_zero_set_pending_dbg(1 << DB_VECTOR); 8886 reason = (u32)vmcs_read(EXI_REASON); 8887 report(reason == VMX_EXC_NMI, "Exit reason is 0x%x (expected 0x%x)", 8888 reason, VMX_EXC_NMI); 8889 8890 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 8891 enter_guest(); 8892 8893 handle_exception(DB_VECTOR, old_db); 8894 } 8895 8896 static u64 vmx_preemption_timer_tf_test_prev_rip; 8897 8898 static void vmx_preemption_timer_tf_test_db_handler(struct ex_regs *regs) 8899 { 8900 extern char vmx_preemption_timer_tf_test_endloop; 8901 8902 if (vmx_get_test_stage() == 2) { 8903 /* 8904 * Stage 2 means that we're done, one way or another. 8905 * Arrange for the iret to drop us out of the wbinvd 8906 * loop and stop single-stepping. 8907 */ 8908 regs->rip = (u64)&vmx_preemption_timer_tf_test_endloop; 8909 regs->rflags &= ~X86_EFLAGS_TF; 8910 } else if (regs->rip == vmx_preemption_timer_tf_test_prev_rip) { 8911 /* 8912 * The RIP should alternate between the wbinvd and the 8913 * jmp instruction in the code below. If we ever see 8914 * the same instruction twice in a row, that means a 8915 * single-step trap has been dropped. Let the 8916 * hypervisor know about the failure by executing a 8917 * VMCALL. 8918 */ 8919 vmcall(); 8920 } 8921 vmx_preemption_timer_tf_test_prev_rip = regs->rip; 8922 } 8923 8924 static void vmx_preemption_timer_tf_test_guest(void) 8925 { 8926 /* 8927 * The hypervisor doesn't intercept WBINVD, so the loop below 8928 * shouldn't be a problem--it's just two instructions 8929 * executing in VMX non-root mode. However, when the 8930 * hypervisor is running in a virtual environment, the parent 8931 * hypervisor might intercept WBINVD and emulate it. If the 8932 * parent hypervisor is broken, the single-step trap after the 8933 * WBINVD might be lost. 8934 */ 8935 asm volatile("vmcall\n\t" 8936 "0: wbinvd\n\t" 8937 "1: jmp 0b\n\t" 8938 "vmx_preemption_timer_tf_test_endloop:"); 8939 } 8940 8941 /* 8942 * Ensure that the delivery of a "VMX-preemption timer expired" 8943 * VM-exit doesn't disrupt single-stepping in the guest. Note that 8944 * passing this test doesn't ensure correctness, because the test will 8945 * only fail if the VMX-preemtion timer fires at the right time (or 8946 * the wrong time, as it were). 8947 */ 8948 static void vmx_preemption_timer_tf_test(void) 8949 { 8950 handler old_db; 8951 u32 reason; 8952 int i; 8953 8954 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 8955 report_skip("%s : \"Activate VMX-preemption timer\" pin control not supported", __func__); 8956 return; 8957 } 8958 8959 old_db = handle_exception(DB_VECTOR, 8960 vmx_preemption_timer_tf_test_db_handler); 8961 8962 test_set_guest(vmx_preemption_timer_tf_test_guest); 8963 8964 enter_guest(); 8965 skip_exit_vmcall(); 8966 8967 vmx_set_test_stage(1); 8968 vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT); 8969 vmcs_write(PREEMPT_TIMER_VALUE, 50000); 8970 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_TF); 8971 8972 /* 8973 * The only exit we should see is "VMX-preemption timer 8974 * expired." If we get a VMCALL exit, that means the #DB 8975 * handler has detected a missing single-step trap. It doesn't 8976 * matter where the guest RIP is when the VMX-preemption timer 8977 * expires (whether it's in the WBINVD loop or in the #DB 8978 * handler)--a single-step trap should never be discarded. 8979 */ 8980 for (i = 0; i < 10000; i++) { 8981 enter_guest(); 8982 reason = (u32)vmcs_read(EXI_REASON); 8983 if (reason == VMX_PREEMPT) 8984 continue; 8985 TEST_ASSERT(reason == VMX_VMCALL); 8986 skip_exit_insn(); 8987 break; 8988 } 8989 8990 report(reason == VMX_PREEMPT, "No single-step traps skipped"); 8991 8992 vmx_set_test_stage(2); 8993 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 8994 enter_guest(); 8995 8996 handle_exception(DB_VECTOR, old_db); 8997 } 8998 8999 #define VMX_PREEMPTION_TIMER_EXPIRY_CYCLES 1000000 9000 9001 static u64 vmx_preemption_timer_expiry_start; 9002 static u64 vmx_preemption_timer_expiry_finish; 9003 9004 static void vmx_preemption_timer_expiry_test_guest(void) 9005 { 9006 vmcall(); 9007 vmx_preemption_timer_expiry_start = fenced_rdtsc(); 9008 9009 while (vmx_get_test_stage() == 0) 9010 vmx_preemption_timer_expiry_finish = fenced_rdtsc(); 9011 } 9012 9013 /* 9014 * Test that the VMX-preemption timer is not excessively delayed. 9015 * 9016 * Per the SDM, volume 3, VM-entry starts the VMX-preemption timer 9017 * with the unsigned value in the VMX-preemption timer-value field, 9018 * and the VMX-preemption timer counts down by 1 every time bit X in 9019 * the TSC changes due to a TSC increment (where X is 9020 * IA32_VMX_MISC[4:0]). If the timer counts down to zero in any state 9021 * other than the wait-for-SIPI state, the logical processor 9022 * transitions to the C0 C-state and causes a VM-exit. 9023 * 9024 * The guest code above reads the starting TSC after VM-entry. At this 9025 * point, the VMX-preemption timer has already been activated. Next, 9026 * the guest code reads the current TSC in a loop, storing the value 9027 * read to memory. 9028 * 9029 * If the RDTSC in the loop reads a value past the VMX-preemption 9030 * timer deadline, then the VMX-preemption timer VM-exit must be 9031 * delivered before the next instruction retires. Even if a higher 9032 * priority SMI is delivered first, the VMX-preemption timer VM-exit 9033 * must be delivered before the next instruction retires. Hence, a TSC 9034 * value past the VMX-preemption timer deadline might be read, but it 9035 * cannot be stored. If a TSC value past the deadline *is* stored, 9036 * then the architectural specification has been violated. 9037 */ 9038 static void vmx_preemption_timer_expiry_test(void) 9039 { 9040 u32 preemption_timer_value; 9041 union vmx_misc misc; 9042 u64 tsc_deadline; 9043 u32 reason; 9044 9045 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 9046 report_skip("%s : \"Activate VMX-preemption timer\" pin control not supported", __func__); 9047 return; 9048 } 9049 9050 test_set_guest(vmx_preemption_timer_expiry_test_guest); 9051 9052 enter_guest(); 9053 skip_exit_vmcall(); 9054 9055 misc.val = rdmsr(MSR_IA32_VMX_MISC); 9056 preemption_timer_value = 9057 VMX_PREEMPTION_TIMER_EXPIRY_CYCLES >> misc.pt_bit; 9058 9059 vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT); 9060 vmcs_write(PREEMPT_TIMER_VALUE, preemption_timer_value); 9061 vmx_set_test_stage(0); 9062 9063 enter_guest(); 9064 reason = (u32)vmcs_read(EXI_REASON); 9065 TEST_ASSERT(reason == VMX_PREEMPT); 9066 9067 tsc_deadline = ((vmx_preemption_timer_expiry_start >> misc.pt_bit) << 9068 misc.pt_bit) + (preemption_timer_value << misc.pt_bit); 9069 9070 report(vmx_preemption_timer_expiry_finish < tsc_deadline, 9071 "Last stored guest TSC (%lu) < TSC deadline (%lu)", 9072 vmx_preemption_timer_expiry_finish, tsc_deadline); 9073 9074 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 9075 vmx_set_test_stage(1); 9076 enter_guest(); 9077 } 9078 9079 static void vmx_db_test_guest(void) 9080 { 9081 /* 9082 * For a hardware generated single-step #DB. 9083 */ 9084 asm volatile("vmcall;" 9085 "nop;" 9086 ".Lpost_nop:"); 9087 /* 9088 * ...in a MOVSS shadow, with pending debug exceptions. 9089 */ 9090 asm volatile("vmcall;" 9091 "nop;" 9092 ".Lpost_movss_nop:"); 9093 /* 9094 * For an L0 synthesized single-step #DB. (L0 intercepts WBINVD and 9095 * emulates it in software.) 9096 */ 9097 asm volatile("vmcall;" 9098 "wbinvd;" 9099 ".Lpost_wbinvd:"); 9100 /* 9101 * ...in a MOVSS shadow, with pending debug exceptions. 9102 */ 9103 asm volatile("vmcall;" 9104 "wbinvd;" 9105 ".Lpost_movss_wbinvd:"); 9106 /* 9107 * For a hardware generated single-step #DB in a transactional region. 9108 */ 9109 asm volatile("vmcall;" 9110 ".Lxbegin: xbegin .Lskip_rtm;" 9111 "xend;" 9112 ".Lskip_rtm:"); 9113 } 9114 9115 /* 9116 * Clear the pending debug exceptions and RFLAGS.TF and re-enter 9117 * L2. No #DB is delivered and L2 continues to the next point of 9118 * interest. 9119 */ 9120 static void dismiss_db(void) 9121 { 9122 vmcs_write(GUEST_PENDING_DEBUG, 0); 9123 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 9124 enter_guest(); 9125 } 9126 9127 /* 9128 * Check a variety of VMCS fields relevant to an intercepted #DB exception. 9129 * Then throw away the #DB exception and resume L2. 9130 */ 9131 static void check_db_exit(bool xfail_qual, bool xfail_dr6, bool xfail_pdbg, 9132 void *expected_rip, u64 expected_exit_qual, 9133 u64 expected_dr6) 9134 { 9135 u32 reason = vmcs_read(EXI_REASON); 9136 u32 intr_info = vmcs_read(EXI_INTR_INFO); 9137 u64 exit_qual = vmcs_read(EXI_QUALIFICATION); 9138 u64 guest_rip = vmcs_read(GUEST_RIP); 9139 u64 guest_pending_dbg = vmcs_read(GUEST_PENDING_DEBUG); 9140 u64 dr6 = read_dr6(); 9141 const u32 expected_intr_info = INTR_INFO_VALID_MASK | 9142 INTR_TYPE_HARD_EXCEPTION | DB_VECTOR; 9143 9144 report(reason == VMX_EXC_NMI && intr_info == expected_intr_info, 9145 "Expected #DB VM-exit"); 9146 report((u64)expected_rip == guest_rip, "Expected RIP %p (actual %lx)", 9147 expected_rip, guest_rip); 9148 report_xfail(xfail_pdbg, 0 == guest_pending_dbg, 9149 "Expected pending debug exceptions 0 (actual %lx)", 9150 guest_pending_dbg); 9151 report_xfail(xfail_qual, expected_exit_qual == exit_qual, 9152 "Expected exit qualification %lx (actual %lx)", 9153 expected_exit_qual, exit_qual); 9154 report_xfail(xfail_dr6, expected_dr6 == dr6, 9155 "Expected DR6 %lx (actual %lx)", expected_dr6, dr6); 9156 dismiss_db(); 9157 } 9158 9159 /* 9160 * Assuming the guest has just exited on a VMCALL instruction, skip 9161 * over the vmcall, and set the guest's RFLAGS.TF in the VMCS. If 9162 * pending debug exceptions are non-zero, set the VMCS up as if the 9163 * previous instruction was a MOVSS that generated the indicated 9164 * pending debug exceptions. Then enter L2. 9165 */ 9166 static void single_step_guest(const char *test_name, u64 starting_dr6, 9167 u64 pending_debug_exceptions) 9168 { 9169 printf("\n%s\n", test_name); 9170 skip_exit_vmcall(); 9171 write_dr6(starting_dr6); 9172 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_TF); 9173 if (pending_debug_exceptions) { 9174 vmcs_write(GUEST_PENDING_DEBUG, pending_debug_exceptions); 9175 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 9176 } 9177 enter_guest(); 9178 } 9179 9180 /* 9181 * When L1 intercepts #DB, verify that a single-step trap clears 9182 * pending debug exceptions, populates the exit qualification field 9183 * properly, and that DR6 is not prematurely clobbered. In a 9184 * (simulated) MOVSS shadow, make sure that the pending debug 9185 * exception bits are properly accumulated into the exit qualification 9186 * field. 9187 */ 9188 static void vmx_db_test(void) 9189 { 9190 /* 9191 * We are going to set a few arbitrary bits in DR6 to verify that 9192 * (a) DR6 is not modified by an intercepted #DB, and 9193 * (b) stale bits in DR6 (DR6.BD, in particular) don't leak into 9194 * the exit qualification field for a subsequent #DB exception. 9195 */ 9196 const u64 starting_dr6 = DR6_ACTIVE_LOW | DR6_BS | DR6_TRAP3 | DR6_TRAP1; 9197 extern char post_nop asm(".Lpost_nop"); 9198 extern char post_movss_nop asm(".Lpost_movss_nop"); 9199 extern char post_wbinvd asm(".Lpost_wbinvd"); 9200 extern char post_movss_wbinvd asm(".Lpost_movss_wbinvd"); 9201 extern char xbegin asm(".Lxbegin"); 9202 extern char skip_rtm asm(".Lskip_rtm"); 9203 9204 /* 9205 * L1 wants to intercept #DB exceptions encountered in L2. 9206 */ 9207 vmcs_write(EXC_BITMAP, BIT(DB_VECTOR)); 9208 9209 /* 9210 * Start L2 and run it up to the first point of interest. 9211 */ 9212 test_set_guest(vmx_db_test_guest); 9213 enter_guest(); 9214 9215 /* 9216 * Hardware-delivered #DB trap for single-step sets the 9217 * standard that L0 has to follow for emulated instructions. 9218 */ 9219 single_step_guest("Hardware delivered single-step", starting_dr6, 0); 9220 check_db_exit(false, false, false, &post_nop, DR6_BS, starting_dr6); 9221 9222 /* 9223 * Hardware-delivered #DB trap for single-step in MOVSS shadow 9224 * also sets the standard that L0 has to follow for emulated 9225 * instructions. Here, we establish the VMCS pending debug 9226 * exceptions to indicate that the simulated MOVSS triggered a 9227 * data breakpoint as well as the single-step trap. 9228 */ 9229 single_step_guest("Hardware delivered single-step in MOVSS shadow", 9230 starting_dr6, DR6_BS | PENDING_DBG_TRAP | DR6_TRAP0); 9231 check_db_exit(false, false, false, &post_movss_nop, DR6_BS | DR6_TRAP0, 9232 starting_dr6); 9233 9234 /* 9235 * L0 synthesized #DB trap for single-step is buggy, because 9236 * kvm (a) clobbers DR6 too early, and (b) tries its best to 9237 * reconstitute the exit qualification from the prematurely 9238 * modified DR6, but fails miserably. 9239 */ 9240 single_step_guest("Software synthesized single-step", starting_dr6, 0); 9241 check_db_exit(false, false, false, &post_wbinvd, DR6_BS, starting_dr6); 9242 9243 /* 9244 * L0 synthesized #DB trap for single-step in MOVSS shadow is 9245 * even worse, because L0 also leaves the pending debug 9246 * exceptions in the VMCS instead of accumulating them into 9247 * the exit qualification field for the #DB exception. 9248 */ 9249 single_step_guest("Software synthesized single-step in MOVSS shadow", 9250 starting_dr6, DR6_BS | PENDING_DBG_TRAP | DR6_TRAP0); 9251 check_db_exit(true, false, true, &post_movss_wbinvd, DR6_BS | DR6_TRAP0, 9252 starting_dr6); 9253 9254 /* 9255 * Optional RTM test for hardware that supports RTM, to 9256 * demonstrate that the current volume 3 of the SDM 9257 * (325384-067US), table 27-1 is incorrect. Bit 16 of the exit 9258 * qualification for debug exceptions is not reserved. It is 9259 * set to 1 if a debug exception (#DB) or a breakpoint 9260 * exception (#BP) occurs inside an RTM region while advanced 9261 * debugging of RTM transactional regions is enabled. 9262 */ 9263 if (this_cpu_has(X86_FEATURE_RTM)) { 9264 vmcs_write(ENT_CONTROLS, 9265 vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 9266 /* 9267 * Set DR7.RTM[bit 11] and IA32_DEBUGCTL.RTM[bit 15] 9268 * in the guest to enable advanced debugging of RTM 9269 * transactional regions. 9270 */ 9271 vmcs_write(GUEST_DR7, BIT(11)); 9272 vmcs_write(GUEST_DEBUGCTL, BIT(15)); 9273 single_step_guest("Hardware delivered single-step in " 9274 "transactional region", starting_dr6, 0); 9275 check_db_exit(false, false, false, &xbegin, BIT(16), 9276 starting_dr6); 9277 } else { 9278 vmcs_write(GUEST_RIP, (u64)&skip_rtm); 9279 enter_guest(); 9280 } 9281 } 9282 9283 static void enable_vid(void) 9284 { 9285 void *virtual_apic_page; 9286 9287 assert(cpu_has_apicv()); 9288 9289 disable_intercept_for_x2apic_msrs(); 9290 9291 virtual_apic_page = alloc_page(); 9292 vmcs_write(APIC_VIRT_ADDR, (u64)virtual_apic_page); 9293 9294 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 9295 9296 vmcs_write(EOI_EXIT_BITMAP0, 0x0); 9297 vmcs_write(EOI_EXIT_BITMAP1, 0x0); 9298 vmcs_write(EOI_EXIT_BITMAP2, 0x0); 9299 vmcs_write(EOI_EXIT_BITMAP3, 0x0); 9300 9301 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY | CPU_TPR_SHADOW); 9302 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_VINTD | CPU_VIRT_X2APIC); 9303 } 9304 9305 static void trigger_ioapic_scan_thread(void *data) 9306 { 9307 /* Wait until other CPU entered L2 */ 9308 while (vmx_get_test_stage() != 1) 9309 ; 9310 9311 /* Trigger ioapic scan */ 9312 ioapic_set_redir(0xf, 0x79, TRIGGER_LEVEL); 9313 vmx_set_test_stage(2); 9314 } 9315 9316 static void irq_79_handler_guest(isr_regs_t *regs) 9317 { 9318 eoi(); 9319 9320 /* L1 expects vmexit on VMX_VMCALL and not VMX_EOI_INDUCED */ 9321 vmcall(); 9322 } 9323 9324 /* 9325 * Constant for num of busy-loop iterations after which 9326 * a timer interrupt should have happened in host 9327 */ 9328 #define TIMER_INTERRUPT_DELAY 100000000 9329 9330 static void vmx_eoi_bitmap_ioapic_scan_test_guest(void) 9331 { 9332 handle_irq(0x79, irq_79_handler_guest); 9333 sti(); 9334 9335 /* Signal to L1 CPU to trigger ioapic scan */ 9336 vmx_set_test_stage(1); 9337 /* Wait until L1 CPU to trigger ioapic scan */ 9338 while (vmx_get_test_stage() != 2) 9339 ; 9340 9341 /* 9342 * Wait for L0 timer interrupt to be raised while we run in L2 9343 * such that L0 will process the IOAPIC scan request before 9344 * resuming L2 9345 */ 9346 delay(TIMER_INTERRUPT_DELAY); 9347 9348 asm volatile ("int $0x79"); 9349 } 9350 9351 static void vmx_eoi_bitmap_ioapic_scan_test(void) 9352 { 9353 if (!cpu_has_apicv() || (cpu_count() < 2)) { 9354 report_skip("%s : Not all required APICv bits supported or CPU count < 2", __func__); 9355 return; 9356 } 9357 9358 enable_vid(); 9359 9360 on_cpu_async(1, trigger_ioapic_scan_thread, NULL); 9361 test_set_guest(vmx_eoi_bitmap_ioapic_scan_test_guest); 9362 9363 /* 9364 * Launch L2. 9365 * We expect the exit reason to be VMX_VMCALL (and not EOI INDUCED). 9366 * In case the reason isn't VMX_VMCALL, the asserion inside 9367 * skip_exit_vmcall() will fail. 9368 */ 9369 enter_guest(); 9370 skip_exit_vmcall(); 9371 9372 /* Let L2 finish */ 9373 enter_guest(); 9374 report_pass(__func__); 9375 } 9376 9377 #define HLT_WITH_RVI_VECTOR (0xf1) 9378 9379 bool vmx_hlt_with_rvi_guest_isr_fired; 9380 static void vmx_hlt_with_rvi_guest_isr(isr_regs_t *regs) 9381 { 9382 vmx_hlt_with_rvi_guest_isr_fired = true; 9383 eoi(); 9384 } 9385 9386 static void vmx_hlt_with_rvi_guest(void) 9387 { 9388 handle_irq(HLT_WITH_RVI_VECTOR, vmx_hlt_with_rvi_guest_isr); 9389 9390 sti_nop(); 9391 asm volatile ("nop"); 9392 9393 vmcall(); 9394 } 9395 9396 static void vmx_hlt_with_rvi_test(void) 9397 { 9398 if (!cpu_has_apicv()) { 9399 report_skip("%s : Not all required APICv bits supported", __func__); 9400 return; 9401 } 9402 9403 enable_vid(); 9404 9405 vmx_hlt_with_rvi_guest_isr_fired = false; 9406 test_set_guest(vmx_hlt_with_rvi_guest); 9407 9408 enter_guest(); 9409 skip_exit_vmcall(); 9410 9411 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 9412 vmcs_write(GUEST_INT_STATUS, HLT_WITH_RVI_VECTOR); 9413 enter_guest(); 9414 9415 report(vmx_hlt_with_rvi_guest_isr_fired, "Interrupt raised in guest"); 9416 } 9417 9418 static void set_irq_line_thread(void *data) 9419 { 9420 /* Wait until other CPU entered L2 */ 9421 while (vmx_get_test_stage() != 1) 9422 ; 9423 9424 /* Set irq-line 0xf to raise vector 0x78 for vCPU 0 */ 9425 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 9426 vmx_set_test_stage(2); 9427 } 9428 9429 static bool irq_78_handler_vmcall_before_eoi; 9430 static void irq_78_handler_guest(isr_regs_t *regs) 9431 { 9432 set_irq_line(0xf, 0); 9433 if (irq_78_handler_vmcall_before_eoi) 9434 vmcall(); 9435 eoi(); 9436 vmcall(); 9437 } 9438 9439 static void vmx_apic_passthrough_guest(void) 9440 { 9441 handle_irq(0x78, irq_78_handler_guest); 9442 sti(); 9443 9444 /* If requested, wait for other CPU to trigger ioapic scan */ 9445 if (vmx_get_test_stage() < 1) { 9446 vmx_set_test_stage(1); 9447 while (vmx_get_test_stage() != 2) 9448 ; 9449 } 9450 9451 set_irq_line(0xf, 1); 9452 } 9453 9454 static void vmx_apic_passthrough(bool set_irq_line_from_thread) 9455 { 9456 if (set_irq_line_from_thread && (cpu_count() < 2)) { 9457 report_skip("%s : CPU count < 2", __func__); 9458 return; 9459 } 9460 9461 /* Test device is required for generating IRQs */ 9462 if (!test_device_enabled()) { 9463 report_skip("%s : No test device enabled", __func__); 9464 return; 9465 } 9466 u64 cpu_ctrl_0 = CPU_SECONDARY; 9467 u64 cpu_ctrl_1 = 0; 9468 9469 disable_intercept_for_x2apic_msrs(); 9470 9471 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 9472 9473 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 9474 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 9475 9476 if (set_irq_line_from_thread) { 9477 irq_78_handler_vmcall_before_eoi = false; 9478 on_cpu_async(1, set_irq_line_thread, NULL); 9479 } else { 9480 irq_78_handler_vmcall_before_eoi = true; 9481 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 9482 vmx_set_test_stage(2); 9483 } 9484 test_set_guest(vmx_apic_passthrough_guest); 9485 9486 if (irq_78_handler_vmcall_before_eoi) { 9487 /* Before EOI remote_irr should still be set */ 9488 enter_guest(); 9489 skip_exit_vmcall(); 9490 TEST_ASSERT_EQ_MSG(1, (int)ioapic_read_redir(0xf).remote_irr, 9491 "IOAPIC pass-through: remote_irr=1 before EOI"); 9492 } 9493 9494 /* After EOI remote_irr should be cleared */ 9495 enter_guest(); 9496 skip_exit_vmcall(); 9497 TEST_ASSERT_EQ_MSG(0, (int)ioapic_read_redir(0xf).remote_irr, 9498 "IOAPIC pass-through: remote_irr=0 after EOI"); 9499 9500 /* Let L2 finish */ 9501 enter_guest(); 9502 report_pass(__func__); 9503 } 9504 9505 static void vmx_apic_passthrough_test(void) 9506 { 9507 vmx_apic_passthrough(false); 9508 } 9509 9510 static void vmx_apic_passthrough_thread_test(void) 9511 { 9512 vmx_apic_passthrough(true); 9513 } 9514 9515 static void vmx_apic_passthrough_tpr_threshold_guest(void) 9516 { 9517 cli(); 9518 apic_set_tpr(0); 9519 } 9520 9521 static bool vmx_apic_passthrough_tpr_threshold_ipi_isr_fired; 9522 static void vmx_apic_passthrough_tpr_threshold_ipi_isr(isr_regs_t *regs) 9523 { 9524 vmx_apic_passthrough_tpr_threshold_ipi_isr_fired = true; 9525 eoi(); 9526 } 9527 9528 static void vmx_apic_passthrough_tpr_threshold_test(void) 9529 { 9530 int ipi_vector = 0xe1; 9531 9532 disable_intercept_for_x2apic_msrs(); 9533 vmcs_clear_bits(PIN_CONTROLS, PIN_EXTINT); 9534 9535 /* Raise L0 TPR-threshold by queueing vector in LAPIC IRR */ 9536 cli(); 9537 apic_set_tpr((ipi_vector >> 4) + 1); 9538 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | 9539 APIC_DM_FIXED | ipi_vector, 9540 0); 9541 9542 test_set_guest(vmx_apic_passthrough_tpr_threshold_guest); 9543 enter_guest(); 9544 9545 report(apic_get_tpr() == 0, "TPR was zero by guest"); 9546 9547 /* Clean pending self-IPI */ 9548 vmx_apic_passthrough_tpr_threshold_ipi_isr_fired = false; 9549 handle_irq(ipi_vector, vmx_apic_passthrough_tpr_threshold_ipi_isr); 9550 sti_nop(); 9551 report(vmx_apic_passthrough_tpr_threshold_ipi_isr_fired, "self-IPI fired"); 9552 9553 report_pass(__func__); 9554 } 9555 9556 static u64 init_signal_test_exit_reason; 9557 static bool init_signal_test_thread_continued; 9558 9559 static void init_signal_test_thread(void *data) 9560 { 9561 struct vmcs *test_vmcs = data; 9562 9563 /* Enter VMX operation (i.e. exec VMXON) */ 9564 u64 *ap_vmxon_region = alloc_page(); 9565 enable_vmx(); 9566 init_vmx(ap_vmxon_region); 9567 TEST_ASSERT(!__vmxon_safe(ap_vmxon_region)); 9568 9569 /* Signal CPU have entered VMX operation */ 9570 vmx_set_test_stage(1); 9571 9572 /* Wait for BSP CPU to send INIT signal */ 9573 while (vmx_get_test_stage() != 2) 9574 ; 9575 9576 /* 9577 * Signal that we continue as usual as INIT signal 9578 * should be blocked while CPU is in VMX operation 9579 */ 9580 vmx_set_test_stage(3); 9581 9582 /* Wait for signal to enter VMX non-root mode */ 9583 while (vmx_get_test_stage() != 4) 9584 ; 9585 9586 /* Enter VMX non-root mode */ 9587 test_set_guest(v2_null_test_guest); 9588 make_vmcs_current(test_vmcs); 9589 enter_guest(); 9590 /* Save exit reason for BSP CPU to compare to expected result */ 9591 init_signal_test_exit_reason = vmcs_read(EXI_REASON); 9592 /* VMCLEAR test-vmcs so it could be loaded by BSP CPU */ 9593 vmcs_clear(test_vmcs); 9594 launched = false; 9595 /* Signal that CPU exited to VMX root mode */ 9596 vmx_set_test_stage(5); 9597 9598 /* Wait for BSP CPU to signal to exit VMX operation */ 9599 while (vmx_get_test_stage() != 6) 9600 ; 9601 9602 /* Exit VMX operation (i.e. exec VMXOFF) */ 9603 vmx_off(); 9604 9605 /* 9606 * Signal to BSP CPU that we continue as usual as INIT signal 9607 * should have been consumed by VMX_INIT exit from guest 9608 */ 9609 vmx_set_test_stage(7); 9610 9611 /* Wait for BSP CPU to signal to enter VMX operation */ 9612 while (vmx_get_test_stage() != 8) 9613 ; 9614 /* Enter VMX operation (i.e. exec VMXON) */ 9615 TEST_ASSERT(!__vmxon_safe(ap_vmxon_region)); 9616 /* Signal to BSP we are in VMX operation */ 9617 vmx_set_test_stage(9); 9618 9619 /* Wait for BSP CPU to send INIT signal */ 9620 while (vmx_get_test_stage() != 10) 9621 ; 9622 9623 /* Exit VMX operation (i.e. exec VMXOFF) */ 9624 vmx_off(); 9625 9626 /* 9627 * Exiting VMX operation should result in latched 9628 * INIT signal being processed. Therefore, we should 9629 * never reach the below code. Thus, signal to BSP 9630 * CPU if we have reached here so it is able to 9631 * report an issue if it happens. 9632 */ 9633 init_signal_test_thread_continued = true; 9634 } 9635 9636 #define INIT_SIGNAL_TEST_DELAY 100000000ULL 9637 9638 static void vmx_init_signal_test(void) 9639 { 9640 struct vmcs *test_vmcs; 9641 9642 if (cpu_count() < 2) { 9643 report_skip("%s : CPU count < 2", __func__); 9644 return; 9645 } 9646 9647 /* VMCLEAR test-vmcs so it could be loaded by other CPU */ 9648 vmcs_save(&test_vmcs); 9649 vmcs_clear(test_vmcs); 9650 9651 vmx_set_test_stage(0); 9652 on_cpu_async(1, init_signal_test_thread, test_vmcs); 9653 9654 /* Wait for other CPU to enter VMX operation */ 9655 while (vmx_get_test_stage() != 1) 9656 ; 9657 9658 /* Send INIT signal to other CPU */ 9659 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_INIT | APIC_INT_ASSERT, 9660 id_map[1]); 9661 /* Signal other CPU we have sent INIT signal */ 9662 vmx_set_test_stage(2); 9663 9664 /* 9665 * Wait reasonable amount of time for INIT signal to 9666 * be received on other CPU and verify that other CPU 9667 * have proceed as usual to next test stage as INIT 9668 * signal should be blocked while other CPU in 9669 * VMX operation 9670 */ 9671 delay(INIT_SIGNAL_TEST_DELAY); 9672 report(vmx_get_test_stage() == 3, 9673 "INIT signal blocked when CPU in VMX operation"); 9674 /* No point to continue if we failed at this point */ 9675 if (vmx_get_test_stage() != 3) 9676 return; 9677 9678 /* Signal other CPU to enter VMX non-root mode */ 9679 init_signal_test_exit_reason = -1ull; 9680 vmx_set_test_stage(4); 9681 /* 9682 * Wait reasonable amont of time for other CPU 9683 * to exit to VMX root mode 9684 */ 9685 delay(INIT_SIGNAL_TEST_DELAY); 9686 if (vmx_get_test_stage() != 5) { 9687 report_fail("Pending INIT signal didn't result in VMX exit"); 9688 return; 9689 } 9690 report(init_signal_test_exit_reason == VMX_INIT, 9691 "INIT signal during VMX non-root mode result in exit-reason %s (%lu)", 9692 exit_reason_description(init_signal_test_exit_reason), 9693 init_signal_test_exit_reason); 9694 9695 /* Run guest to completion */ 9696 make_vmcs_current(test_vmcs); 9697 enter_guest(); 9698 9699 /* Signal other CPU to exit VMX operation */ 9700 init_signal_test_thread_continued = false; 9701 vmx_set_test_stage(6); 9702 9703 /* Wait reasonable amount of time for other CPU to exit VMX operation */ 9704 delay(INIT_SIGNAL_TEST_DELAY); 9705 report(vmx_get_test_stage() == 7, 9706 "INIT signal consumed on VMX_INIT exit"); 9707 /* No point to continue if we failed at this point */ 9708 if (vmx_get_test_stage() != 7) 9709 return; 9710 9711 /* Signal other CPU to enter VMX operation */ 9712 vmx_set_test_stage(8); 9713 /* Wait for other CPU to enter VMX operation */ 9714 while (vmx_get_test_stage() != 9) 9715 ; 9716 9717 /* Send INIT signal to other CPU */ 9718 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_INIT | APIC_INT_ASSERT, 9719 id_map[1]); 9720 /* Signal other CPU we have sent INIT signal */ 9721 vmx_set_test_stage(10); 9722 9723 /* 9724 * Wait reasonable amount of time for other CPU 9725 * to exit VMX operation and process INIT signal 9726 */ 9727 delay(INIT_SIGNAL_TEST_DELAY); 9728 report(!init_signal_test_thread_continued, 9729 "INIT signal processed after exit VMX operation"); 9730 9731 /* 9732 * TODO: Send SIPI to other CPU to sipi_entry (See x86/cstart64.S) 9733 * to re-init it to kvm-unit-tests standard environment. 9734 * Somehow (?) verify that SIPI was indeed received. 9735 */ 9736 } 9737 9738 #define SIPI_SIGNAL_TEST_DELAY 100000000ULL 9739 9740 static void vmx_sipi_test_guest(void) 9741 { 9742 if (apic_id() == 0) { 9743 /* wait AP enter guest with activity=WAIT_SIPI */ 9744 while (vmx_get_test_stage() != 1) 9745 ; 9746 delay(SIPI_SIGNAL_TEST_DELAY); 9747 9748 /* First SIPI signal */ 9749 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_STARTUP | APIC_INT_ASSERT, id_map[1]); 9750 report_pass("BSP(L2): Send first SIPI to cpu[%d]", id_map[1]); 9751 9752 /* wait AP enter guest */ 9753 while (vmx_get_test_stage() != 2) 9754 ; 9755 delay(SIPI_SIGNAL_TEST_DELAY); 9756 9757 /* Second SIPI signal should be ignored since AP is not in WAIT_SIPI state */ 9758 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_STARTUP | APIC_INT_ASSERT, id_map[1]); 9759 report_pass("BSP(L2): Send second SIPI to cpu[%d]", id_map[1]); 9760 9761 /* Delay a while to check whether second SIPI would cause VMExit */ 9762 delay(SIPI_SIGNAL_TEST_DELAY); 9763 9764 /* Test is done, notify AP to exit test */ 9765 vmx_set_test_stage(3); 9766 9767 /* wait AP exit non-root mode */ 9768 while (vmx_get_test_stage() != 5) 9769 ; 9770 } else { 9771 /* wait BSP notify test is done */ 9772 while (vmx_get_test_stage() != 3) 9773 ; 9774 9775 /* AP exit guest */ 9776 vmx_set_test_stage(4); 9777 } 9778 } 9779 9780 static void sipi_test_ap_thread(void *data) 9781 { 9782 struct vmcs *ap_vmcs; 9783 u64 *ap_vmxon_region; 9784 void *ap_stack, *ap_syscall_stack; 9785 u64 cpu_ctrl_0 = CPU_SECONDARY; 9786 u64 cpu_ctrl_1 = 0; 9787 9788 /* Enter VMX operation (i.e. exec VMXON) */ 9789 ap_vmxon_region = alloc_page(); 9790 enable_vmx(); 9791 init_vmx(ap_vmxon_region); 9792 TEST_ASSERT(!__vmxon_safe(ap_vmxon_region)); 9793 init_vmcs(&ap_vmcs); 9794 make_vmcs_current(ap_vmcs); 9795 9796 /* Set stack for AP */ 9797 ap_stack = alloc_page(); 9798 ap_syscall_stack = alloc_page(); 9799 vmcs_write(GUEST_RSP, (u64)(ap_stack + PAGE_SIZE - 1)); 9800 vmcs_write(GUEST_SYSENTER_ESP, (u64)(ap_syscall_stack + PAGE_SIZE - 1)); 9801 9802 /* passthrough lapic to L2 */ 9803 disable_intercept_for_x2apic_msrs(); 9804 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 9805 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 9806 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 9807 9808 /* Set guest activity state to wait-for-SIPI state */ 9809 vmcs_write(GUEST_ACTV_STATE, ACTV_WAIT_SIPI); 9810 9811 vmx_set_test_stage(1); 9812 9813 /* AP enter guest */ 9814 enter_guest(); 9815 9816 if (vmcs_read(EXI_REASON) == VMX_SIPI) { 9817 report_pass("AP: Handle SIPI VMExit"); 9818 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 9819 vmx_set_test_stage(2); 9820 } else { 9821 report_fail("AP: Unexpected VMExit, reason=%ld", vmcs_read(EXI_REASON)); 9822 vmx_off(); 9823 return; 9824 } 9825 9826 /* AP enter guest */ 9827 enter_guest(); 9828 9829 report(vmcs_read(EXI_REASON) != VMX_SIPI, 9830 "AP: should no SIPI VMExit since activity is not in WAIT_SIPI state"); 9831 9832 /* notify BSP that AP is already exit from non-root mode */ 9833 vmx_set_test_stage(5); 9834 9835 /* Leave VMX operation */ 9836 vmx_off(); 9837 } 9838 9839 static void vmx_sipi_signal_test(void) 9840 { 9841 if (!(rdmsr(MSR_IA32_VMX_MISC) & MSR_IA32_VMX_MISC_ACTIVITY_WAIT_SIPI)) { 9842 report_skip("%s : \"ACTIVITY_WAIT_SIPI state\" not supported", __func__); 9843 return; 9844 } 9845 9846 if (cpu_count() < 2) { 9847 report_skip("%s : CPU count < 2", __func__); 9848 return; 9849 } 9850 9851 u64 cpu_ctrl_0 = CPU_SECONDARY; 9852 u64 cpu_ctrl_1 = 0; 9853 9854 /* passthrough lapic to L2 */ 9855 disable_intercept_for_x2apic_msrs(); 9856 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 9857 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 9858 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 9859 9860 test_set_guest(vmx_sipi_test_guest); 9861 9862 /* update CR3 on AP */ 9863 on_cpu(1, update_cr3, (void *)read_cr3()); 9864 9865 /* start AP */ 9866 on_cpu_async(1, sipi_test_ap_thread, NULL); 9867 9868 vmx_set_test_stage(0); 9869 9870 /* BSP enter guest */ 9871 enter_guest(); 9872 } 9873 9874 9875 enum vmcs_access { 9876 ACCESS_VMREAD, 9877 ACCESS_VMWRITE, 9878 ACCESS_NONE, 9879 }; 9880 9881 struct vmcs_shadow_test_common { 9882 enum vmcs_access op; 9883 enum Reason reason; 9884 u64 field; 9885 u64 value; 9886 u64 flags; 9887 u64 time; 9888 } l1_l2_common; 9889 9890 static inline u64 vmread_flags(u64 field, u64 *val) 9891 { 9892 u64 flags; 9893 9894 asm volatile ("vmread %2, %1; pushf; pop %0" 9895 : "=r" (flags), "=rm" (*val) : "r" (field) : "cc"); 9896 return flags & X86_EFLAGS_ALU; 9897 } 9898 9899 static inline u64 vmwrite_flags(u64 field, u64 val) 9900 { 9901 u64 flags; 9902 9903 asm volatile ("vmwrite %1, %2; pushf; pop %0" 9904 : "=r"(flags) : "rm" (val), "r" (field) : "cc"); 9905 return flags & X86_EFLAGS_ALU; 9906 } 9907 9908 static void vmx_vmcs_shadow_test_guest(void) 9909 { 9910 struct vmcs_shadow_test_common *c = &l1_l2_common; 9911 u64 start; 9912 9913 while (c->op != ACCESS_NONE) { 9914 start = rdtsc(); 9915 switch (c->op) { 9916 default: 9917 c->flags = -1ull; 9918 break; 9919 case ACCESS_VMREAD: 9920 c->flags = vmread_flags(c->field, &c->value); 9921 break; 9922 case ACCESS_VMWRITE: 9923 c->flags = vmwrite_flags(c->field, 0); 9924 break; 9925 } 9926 c->time = rdtsc() - start; 9927 vmcall(); 9928 } 9929 } 9930 9931 static u64 vmread_from_shadow(u64 field) 9932 { 9933 struct vmcs *primary; 9934 struct vmcs *shadow; 9935 u64 value; 9936 9937 TEST_ASSERT(!vmcs_save(&primary)); 9938 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 9939 TEST_ASSERT(!make_vmcs_current(shadow)); 9940 value = vmcs_read(field); 9941 TEST_ASSERT(!make_vmcs_current(primary)); 9942 return value; 9943 } 9944 9945 static u64 vmwrite_to_shadow(u64 field, u64 value) 9946 { 9947 struct vmcs *primary; 9948 struct vmcs *shadow; 9949 9950 TEST_ASSERT(!vmcs_save(&primary)); 9951 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 9952 TEST_ASSERT(!make_vmcs_current(shadow)); 9953 vmcs_write(field, value); 9954 value = vmcs_read(field); 9955 TEST_ASSERT(!make_vmcs_current(primary)); 9956 return value; 9957 } 9958 9959 static void vmcs_shadow_test_access(u8 *bitmap[2], enum vmcs_access access) 9960 { 9961 struct vmcs_shadow_test_common *c = &l1_l2_common; 9962 9963 c->op = access; 9964 vmcs_write(VMX_INST_ERROR, 0); 9965 enter_guest(); 9966 c->reason = vmcs_read(EXI_REASON) & 0xffff; 9967 if (c->reason != VMX_VMCALL) { 9968 skip_exit_insn(); 9969 enter_guest(); 9970 } 9971 skip_exit_vmcall(); 9972 } 9973 9974 static void vmcs_shadow_test_field(u8 *bitmap[2], u64 field) 9975 { 9976 struct vmcs_shadow_test_common *c = &l1_l2_common; 9977 struct vmcs *shadow; 9978 u64 value; 9979 uintptr_t flags[2]; 9980 bool good_shadow; 9981 u32 vmx_inst_error; 9982 9983 report_prefix_pushf("field %lx", field); 9984 c->field = field; 9985 9986 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 9987 if (shadow != (struct vmcs *)-1ull) { 9988 flags[ACCESS_VMREAD] = vmread_flags(field, &value); 9989 flags[ACCESS_VMWRITE] = vmwrite_flags(field, value); 9990 good_shadow = !flags[ACCESS_VMREAD] && !flags[ACCESS_VMWRITE]; 9991 } else { 9992 /* 9993 * When VMCS link pointer is -1ull, VMWRITE/VMREAD on 9994 * shadowed-fields should fail with setting RFLAGS.CF. 9995 */ 9996 flags[ACCESS_VMREAD] = X86_EFLAGS_CF; 9997 flags[ACCESS_VMWRITE] = X86_EFLAGS_CF; 9998 good_shadow = false; 9999 } 10000 10001 /* Intercept both VMREAD and VMWRITE. */ 10002 report_prefix_push("no VMREAD/VMWRITE permission"); 10003 /* VMWRITE/VMREAD done on reserved-bit should always intercept */ 10004 if (!(field >> VMCS_FIELD_RESERVED_SHIFT)) { 10005 set_bit(field, bitmap[ACCESS_VMREAD]); 10006 set_bit(field, bitmap[ACCESS_VMWRITE]); 10007 } 10008 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10009 report(c->reason == VMX_VMWRITE, "not shadowed for VMWRITE"); 10010 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10011 report(c->reason == VMX_VMREAD, "not shadowed for VMREAD"); 10012 report_prefix_pop(); 10013 10014 if (field >> VMCS_FIELD_RESERVED_SHIFT) 10015 goto out; 10016 10017 /* Permit shadowed VMREAD. */ 10018 report_prefix_push("VMREAD permission only"); 10019 clear_bit(field, bitmap[ACCESS_VMREAD]); 10020 set_bit(field, bitmap[ACCESS_VMWRITE]); 10021 if (good_shadow) 10022 value = vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 10023 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10024 report(c->reason == VMX_VMWRITE, "not shadowed for VMWRITE"); 10025 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10026 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10027 report(c->reason == VMX_VMCALL, "shadowed for VMREAD (in %ld cycles)", 10028 c->time); 10029 report(c->flags == flags[ACCESS_VMREAD], 10030 "ALU flags after VMREAD (%lx) are as expected (%lx)", 10031 c->flags, flags[ACCESS_VMREAD]); 10032 if (good_shadow) 10033 report(c->value == value, 10034 "value read from shadow (%lx) is as expected (%lx)", 10035 c->value, value); 10036 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 10037 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10038 "VMX_INST_ERROR (%d) is as expected (%d)", 10039 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10040 report_prefix_pop(); 10041 10042 /* Permit shadowed VMWRITE. */ 10043 report_prefix_push("VMWRITE permission only"); 10044 set_bit(field, bitmap[ACCESS_VMREAD]); 10045 clear_bit(field, bitmap[ACCESS_VMWRITE]); 10046 if (good_shadow) 10047 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 10048 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10049 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10050 report(c->reason == VMX_VMCALL, 10051 "shadowed for VMWRITE (in %ld cycles)", 10052 c->time); 10053 report(c->flags == flags[ACCESS_VMREAD], 10054 "ALU flags after VMWRITE (%lx) are as expected (%lx)", 10055 c->flags, flags[ACCESS_VMREAD]); 10056 if (good_shadow) { 10057 value = vmread_from_shadow(field); 10058 report(value == 0, 10059 "shadow VMCS value (%lx) is as expected (%lx)", value, 10060 0ul); 10061 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 10062 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10063 "VMX_INST_ERROR (%d) is as expected (%d)", 10064 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10065 } 10066 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10067 report(c->reason == VMX_VMREAD, "not shadowed for VMREAD"); 10068 report_prefix_pop(); 10069 10070 /* Permit shadowed VMREAD and VMWRITE. */ 10071 report_prefix_push("VMREAD and VMWRITE permission"); 10072 clear_bit(field, bitmap[ACCESS_VMREAD]); 10073 clear_bit(field, bitmap[ACCESS_VMWRITE]); 10074 if (good_shadow) 10075 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 10076 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10077 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10078 report(c->reason == VMX_VMCALL, 10079 "shadowed for VMWRITE (in %ld cycles)", 10080 c->time); 10081 report(c->flags == flags[ACCESS_VMREAD], 10082 "ALU flags after VMWRITE (%lx) are as expected (%lx)", 10083 c->flags, flags[ACCESS_VMREAD]); 10084 if (good_shadow) { 10085 value = vmread_from_shadow(field); 10086 report(value == 0, 10087 "shadow VMCS value (%lx) is as expected (%lx)", value, 10088 0ul); 10089 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 10090 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10091 "VMX_INST_ERROR (%d) is as expected (%d)", 10092 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10093 } 10094 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10095 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10096 report(c->reason == VMX_VMCALL, "shadowed for VMREAD (in %ld cycles)", 10097 c->time); 10098 report(c->flags == flags[ACCESS_VMREAD], 10099 "ALU flags after VMREAD (%lx) are as expected (%lx)", 10100 c->flags, flags[ACCESS_VMREAD]); 10101 if (good_shadow) 10102 report(c->value == 0, 10103 "value read from shadow (%lx) is as expected (%lx)", 10104 c->value, 0ul); 10105 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 10106 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10107 "VMX_INST_ERROR (%d) is as expected (%d)", 10108 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10109 report_prefix_pop(); 10110 10111 out: 10112 report_prefix_pop(); 10113 } 10114 10115 static void vmx_vmcs_shadow_test_body(u8 *bitmap[2]) 10116 { 10117 unsigned base; 10118 unsigned index; 10119 unsigned bit; 10120 unsigned highest_index = rdmsr(MSR_IA32_VMX_VMCS_ENUM); 10121 10122 /* Run test on all possible valid VMCS fields */ 10123 for (base = 0; 10124 base < (1 << VMCS_FIELD_RESERVED_SHIFT); 10125 base += (1 << VMCS_FIELD_TYPE_SHIFT)) 10126 for (index = 0; index <= highest_index; index++) 10127 vmcs_shadow_test_field(bitmap, base + index); 10128 10129 /* 10130 * Run tests on some invalid VMCS fields 10131 * (Have reserved bit set). 10132 */ 10133 for (bit = VMCS_FIELD_RESERVED_SHIFT; bit < VMCS_FIELD_BIT_SIZE; bit++) 10134 vmcs_shadow_test_field(bitmap, (1ull << bit)); 10135 } 10136 10137 static void vmx_vmcs_shadow_test(void) 10138 { 10139 u8 *bitmap[2]; 10140 struct vmcs *shadow; 10141 10142 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 10143 report_skip("%s : \"Activate secondary controls\" not supported", __func__); 10144 return; 10145 } 10146 10147 if (!(ctrl_cpu_rev[1].clr & CPU_SHADOW_VMCS)) { 10148 report_skip("%s : \"VMCS shadowing\" not supported", __func__); 10149 return; 10150 } 10151 10152 if (!(rdmsr(MSR_IA32_VMX_MISC) & 10153 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS)) { 10154 report_skip("%s : VMWRITE can't modify VM-exit information fields.", __func__); 10155 return; 10156 } 10157 10158 test_set_guest(vmx_vmcs_shadow_test_guest); 10159 10160 bitmap[ACCESS_VMREAD] = alloc_page(); 10161 bitmap[ACCESS_VMWRITE] = alloc_page(); 10162 10163 vmcs_write(VMREAD_BITMAP, virt_to_phys(bitmap[ACCESS_VMREAD])); 10164 vmcs_write(VMWRITE_BITMAP, virt_to_phys(bitmap[ACCESS_VMWRITE])); 10165 10166 shadow = alloc_page(); 10167 shadow->hdr.revision_id = basic.revision; 10168 shadow->hdr.shadow_vmcs = 1; 10169 TEST_ASSERT(!vmcs_clear(shadow)); 10170 10171 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_RDTSC); 10172 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY); 10173 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_SHADOW_VMCS); 10174 10175 vmcs_write(VMCS_LINK_PTR, virt_to_phys(shadow)); 10176 report_prefix_push("valid link pointer"); 10177 vmx_vmcs_shadow_test_body(bitmap); 10178 report_prefix_pop(); 10179 10180 vmcs_write(VMCS_LINK_PTR, -1ull); 10181 report_prefix_push("invalid link pointer"); 10182 vmx_vmcs_shadow_test_body(bitmap); 10183 report_prefix_pop(); 10184 10185 l1_l2_common.op = ACCESS_NONE; 10186 enter_guest(); 10187 } 10188 10189 /* 10190 * This test monitors the difference between a guest RDTSC instruction 10191 * and the IA32_TIME_STAMP_COUNTER MSR value stored in the VMCS12 10192 * VM-exit MSR-store list when taking a VM-exit on the instruction 10193 * following RDTSC. 10194 */ 10195 #define RDTSC_DIFF_ITERS 100000 10196 #define RDTSC_DIFF_FAILS 100 10197 #define HOST_CAPTURED_GUEST_TSC_DIFF_THRESHOLD 750 10198 10199 /* 10200 * Set 'use TSC offsetting' and set the guest offset to the 10201 * inverse of the host's current TSC value, so that the guest starts running 10202 * with an effective TSC value of 0. 10203 */ 10204 static void reset_guest_tsc_to_zero(void) 10205 { 10206 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_USE_TSC_OFFSET); 10207 vmcs_write(TSC_OFFSET, -rdtsc()); 10208 } 10209 10210 static void rdtsc_vmexit_diff_test_guest(void) 10211 { 10212 int i; 10213 10214 for (i = 0; i < RDTSC_DIFF_ITERS; i++) 10215 /* Ensure rdtsc is the last instruction before the vmcall. */ 10216 asm volatile("rdtsc; vmcall" : : : "eax", "edx"); 10217 } 10218 10219 /* 10220 * This function only considers the "use TSC offsetting" VM-execution 10221 * control. It does not handle "use TSC scaling" (because the latter 10222 * isn't available to the host today.) 10223 */ 10224 static unsigned long long host_time_to_guest_time(unsigned long long t) 10225 { 10226 TEST_ASSERT(!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 10227 !(vmcs_read(CPU_EXEC_CTRL1) & CPU_USE_TSC_SCALING)); 10228 10229 if (vmcs_read(CPU_EXEC_CTRL0) & CPU_USE_TSC_OFFSET) 10230 t += vmcs_read(TSC_OFFSET); 10231 10232 return t; 10233 } 10234 10235 static unsigned long long rdtsc_vmexit_diff_test_iteration(void) 10236 { 10237 unsigned long long guest_tsc, host_to_guest_tsc; 10238 10239 enter_guest(); 10240 skip_exit_vmcall(); 10241 guest_tsc = (u32) regs.rax + (regs.rdx << 32); 10242 host_to_guest_tsc = host_time_to_guest_time(exit_msr_store[0].value); 10243 10244 return host_to_guest_tsc - guest_tsc; 10245 } 10246 10247 static void rdtsc_vmexit_diff_test(void) 10248 { 10249 unsigned long long delta; 10250 int fail = 0; 10251 int i; 10252 10253 if (!(ctrl_cpu_rev[0].clr & CPU_USE_TSC_OFFSET)) 10254 test_skip("CPU doesn't support the 'use TSC offsetting' processor-based VM-execution control.\n"); 10255 10256 test_set_guest(rdtsc_vmexit_diff_test_guest); 10257 10258 reset_guest_tsc_to_zero(); 10259 10260 /* 10261 * Set up the VMCS12 VM-exit MSR-store list to store just one 10262 * MSR: IA32_TIME_STAMP_COUNTER. Note that the value stored is 10263 * in the host time domain (i.e., it is not adjusted according 10264 * to the TSC multiplier and TSC offset fields in the VMCS12, 10265 * as a guest RDTSC would be.) 10266 */ 10267 exit_msr_store = alloc_page(); 10268 exit_msr_store[0].index = MSR_IA32_TSC; 10269 vmcs_write(EXI_MSR_ST_CNT, 1); 10270 vmcs_write(EXIT_MSR_ST_ADDR, virt_to_phys(exit_msr_store)); 10271 10272 for (i = 0; i < RDTSC_DIFF_ITERS && fail < RDTSC_DIFF_FAILS; i++) { 10273 delta = rdtsc_vmexit_diff_test_iteration(); 10274 if (delta >= HOST_CAPTURED_GUEST_TSC_DIFF_THRESHOLD) 10275 fail++; 10276 } 10277 10278 enter_guest(); 10279 10280 report(fail < RDTSC_DIFF_FAILS, 10281 "RDTSC to VM-exit delta too high in %d of %d iterations, last = %llu", 10282 fail, i, delta); 10283 } 10284 10285 static int invalid_msr_init(struct vmcs *vmcs) 10286 { 10287 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 10288 printf("\tPreemption timer is not supported\n"); 10289 return VMX_TEST_EXIT; 10290 } 10291 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 10292 preempt_val = 10000000; 10293 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 10294 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 10295 10296 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 10297 printf("\tSave preemption value is not supported\n"); 10298 10299 vmcs_write(ENT_MSR_LD_CNT, 1); 10300 vmcs_write(ENTER_MSR_LD_ADDR, (u64)0x13370000); 10301 10302 return VMX_TEST_START; 10303 } 10304 10305 10306 static void invalid_msr_main(void) 10307 { 10308 report_fail("Invalid MSR load"); 10309 } 10310 10311 static int invalid_msr_exit_handler(union exit_reason exit_reason) 10312 { 10313 report_fail("Invalid MSR load"); 10314 print_vmexit_info(exit_reason); 10315 return VMX_TEST_EXIT; 10316 } 10317 10318 static int invalid_msr_entry_failure(struct vmentry_result *result) 10319 { 10320 report(result->exit_reason.failed_vmentry && 10321 result->exit_reason.basic == VMX_FAIL_MSR, "Invalid MSR load"); 10322 return VMX_TEST_VMEXIT; 10323 } 10324 10325 /* 10326 * The max number of MSRs in an atomic switch MSR list is: 10327 * (111B + 1) * 512 = 4096 10328 * 10329 * Each list entry consumes: 10330 * 4-byte MSR index + 4 bytes reserved + 8-byte data = 16 bytes 10331 * 10332 * Allocate 128 kB to cover max_msr_list_size (i.e., 64 kB) and then some. 10333 */ 10334 static const u32 msr_list_page_order = 5; 10335 10336 static void atomic_switch_msr_limit_test_guest(void) 10337 { 10338 vmcall(); 10339 } 10340 10341 static void populate_msr_list(struct vmx_msr_entry *msr_list, 10342 size_t byte_capacity, int count) 10343 { 10344 int i; 10345 10346 for (i = 0; i < count; i++) { 10347 msr_list[i].index = MSR_IA32_TSC; 10348 msr_list[i].reserved = 0; 10349 msr_list[i].value = 0x1234567890abcdef; 10350 } 10351 10352 memset(msr_list + count, 0xff, 10353 byte_capacity - count * sizeof(*msr_list)); 10354 } 10355 10356 static int max_msr_list_size(void) 10357 { 10358 u32 vmx_misc = rdmsr(MSR_IA32_VMX_MISC); 10359 u32 factor = ((vmx_misc & GENMASK(27, 25)) >> 25) + 1; 10360 10361 return factor * 512; 10362 } 10363 10364 static void atomic_switch_msrs_test(int count) 10365 { 10366 struct vmx_msr_entry *vm_enter_load; 10367 struct vmx_msr_entry *vm_exit_load; 10368 struct vmx_msr_entry *vm_exit_store; 10369 int max_allowed = max_msr_list_size(); 10370 int byte_capacity = 1ul << (msr_list_page_order + PAGE_SHIFT); 10371 /* Exceeding the max MSR list size at exit triggers KVM to abort. */ 10372 int exit_count = count > max_allowed ? max_allowed : count; 10373 int cleanup_count = count > max_allowed ? 2 : 1; 10374 int i; 10375 10376 /* 10377 * Check for the IA32_TSC MSR, 10378 * available with the "TSC flag" and used to populate the MSR lists. 10379 */ 10380 if (!(cpuid(1).d & (1 << 4))) { 10381 report_skip("%s : \"Time Stamp Counter\" not supported", __func__); 10382 return; 10383 } 10384 10385 /* Set L2 guest. */ 10386 test_set_guest(atomic_switch_msr_limit_test_guest); 10387 10388 /* Setup atomic MSR switch lists. */ 10389 vm_enter_load = alloc_pages(msr_list_page_order); 10390 vm_exit_load = alloc_pages(msr_list_page_order); 10391 vm_exit_store = alloc_pages(msr_list_page_order); 10392 10393 vmcs_write(ENTER_MSR_LD_ADDR, (u64)vm_enter_load); 10394 vmcs_write(EXIT_MSR_LD_ADDR, (u64)vm_exit_load); 10395 vmcs_write(EXIT_MSR_ST_ADDR, (u64)vm_exit_store); 10396 10397 /* 10398 * VM-Enter should succeed up to the max number of MSRs per list, and 10399 * should not consume junk beyond the last entry. 10400 */ 10401 populate_msr_list(vm_enter_load, byte_capacity, count); 10402 populate_msr_list(vm_exit_load, byte_capacity, exit_count); 10403 populate_msr_list(vm_exit_store, byte_capacity, exit_count); 10404 10405 vmcs_write(ENT_MSR_LD_CNT, count); 10406 vmcs_write(EXI_MSR_LD_CNT, exit_count); 10407 vmcs_write(EXI_MSR_ST_CNT, exit_count); 10408 10409 if (count <= max_allowed) { 10410 enter_guest(); 10411 assert_exit_reason(VMX_VMCALL); 10412 skip_exit_vmcall(); 10413 } else { 10414 u32 exit_qual; 10415 10416 test_guest_state("Invalid MSR Load Count", true, count, 10417 "ENT_MSR_LD_CNT"); 10418 10419 exit_qual = vmcs_read(EXI_QUALIFICATION); 10420 report(exit_qual == max_allowed + 1, "exit_qual, %u, is %u.", 10421 exit_qual, max_allowed + 1); 10422 } 10423 10424 /* Cleanup. */ 10425 vmcs_write(ENT_MSR_LD_CNT, 0); 10426 vmcs_write(EXI_MSR_LD_CNT, 0); 10427 vmcs_write(EXI_MSR_ST_CNT, 0); 10428 for (i = 0; i < cleanup_count; i++) { 10429 enter_guest(); 10430 skip_exit_vmcall(); 10431 } 10432 free_pages_by_order(vm_enter_load, msr_list_page_order); 10433 free_pages_by_order(vm_exit_load, msr_list_page_order); 10434 free_pages_by_order(vm_exit_store, msr_list_page_order); 10435 } 10436 10437 static void atomic_switch_max_msrs_test(void) 10438 { 10439 atomic_switch_msrs_test(max_msr_list_size()); 10440 } 10441 10442 static void atomic_switch_overflow_msrs_test(void) 10443 { 10444 if (test_device_enabled()) 10445 atomic_switch_msrs_test(max_msr_list_size() + 1); 10446 else 10447 test_skip("Test is only supported on KVM"); 10448 } 10449 10450 static void vmx_pf_exception_test_guest(void) 10451 { 10452 ac_test_run(PT_LEVEL_PML4, false); 10453 } 10454 10455 static void vmx_pf_exception_forced_emulation_test_guest(void) 10456 { 10457 ac_test_run(PT_LEVEL_PML4, true); 10458 } 10459 10460 typedef void (*invalidate_tlb_t)(void *data); 10461 typedef void (*pf_exception_test_guest_t)(void); 10462 10463 10464 static void __vmx_pf_exception_test(invalidate_tlb_t inv_fn, void *data, 10465 pf_exception_test_guest_t guest_fn) 10466 { 10467 u64 efer; 10468 struct cpuid cpuid; 10469 10470 test_set_guest(guest_fn); 10471 10472 /* Intercept INVLPG when to perform TLB invalidation from L1 (this). */ 10473 if (inv_fn) 10474 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INVLPG); 10475 else 10476 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INVLPG); 10477 10478 enter_guest(); 10479 10480 while (vmcs_read(EXI_REASON) != VMX_VMCALL) { 10481 switch (vmcs_read(EXI_REASON)) { 10482 case VMX_RDMSR: 10483 assert(regs.rcx == MSR_EFER); 10484 efer = vmcs_read(GUEST_EFER); 10485 regs.rdx = efer >> 32; 10486 regs.rax = efer & 0xffffffff; 10487 break; 10488 case VMX_WRMSR: 10489 assert(regs.rcx == MSR_EFER); 10490 efer = regs.rdx << 32 | (regs.rax & 0xffffffff); 10491 vmcs_write(GUEST_EFER, efer); 10492 break; 10493 case VMX_CPUID: 10494 cpuid = (struct cpuid) {0, 0, 0, 0}; 10495 cpuid = raw_cpuid(regs.rax, regs.rcx); 10496 regs.rax = cpuid.a; 10497 regs.rbx = cpuid.b; 10498 regs.rcx = cpuid.c; 10499 regs.rdx = cpuid.d; 10500 break; 10501 case VMX_INVLPG: 10502 inv_fn(data); 10503 break; 10504 default: 10505 assert_msg(false, 10506 "Unexpected exit to L1, exit_reason: %s (0x%lx)", 10507 exit_reason_description(vmcs_read(EXI_REASON)), 10508 vmcs_read(EXI_REASON)); 10509 } 10510 skip_exit_insn(); 10511 enter_guest(); 10512 } 10513 10514 assert_exit_reason(VMX_VMCALL); 10515 } 10516 10517 static void vmx_pf_exception_test(void) 10518 { 10519 __vmx_pf_exception_test(NULL, NULL, vmx_pf_exception_test_guest); 10520 } 10521 10522 static void vmx_pf_exception_forced_emulation_test(void) 10523 { 10524 __vmx_pf_exception_test(NULL, NULL, vmx_pf_exception_forced_emulation_test_guest); 10525 } 10526 10527 static void invalidate_tlb_no_vpid(void *data) 10528 { 10529 /* If VPID is disabled, the TLB is flushed on VM-Enter and VM-Exit. */ 10530 } 10531 10532 static void vmx_pf_no_vpid_test(void) 10533 { 10534 if (is_vpid_supported()) 10535 vmcs_clear_bits(CPU_EXEC_CTRL1, CPU_VPID); 10536 10537 __vmx_pf_exception_test(invalidate_tlb_no_vpid, NULL, 10538 vmx_pf_exception_test_guest); 10539 } 10540 10541 static void invalidate_tlb_invvpid_addr(void *data) 10542 { 10543 invvpid(INVVPID_ALL, *(u16 *)data, vmcs_read(EXI_QUALIFICATION)); 10544 } 10545 10546 static void invalidate_tlb_new_vpid(void *data) 10547 { 10548 u16 *vpid = data; 10549 10550 /* 10551 * Bump VPID to effectively flush L2's TLB from L0's perspective. 10552 * Invalidate all VPIDs when the VPID wraps to zero as hardware/KVM is 10553 * architecturally allowed to keep TLB entries indefinitely. 10554 */ 10555 ++(*vpid); 10556 if (*vpid == 0) { 10557 ++(*vpid); 10558 invvpid(INVVPID_ALL, 0, 0); 10559 } 10560 vmcs_write(VPID, *vpid); 10561 } 10562 10563 static void __vmx_pf_vpid_test(invalidate_tlb_t inv_fn, u16 vpid) 10564 { 10565 if (!is_vpid_supported()) 10566 test_skip("VPID unsupported"); 10567 10568 if (!is_invvpid_supported()) 10569 test_skip("INVVPID unsupported"); 10570 10571 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY); 10572 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_VPID); 10573 vmcs_write(VPID, vpid); 10574 10575 __vmx_pf_exception_test(inv_fn, &vpid, vmx_pf_exception_test_guest); 10576 } 10577 10578 static void vmx_pf_invvpid_test(void) 10579 { 10580 if (!is_invvpid_type_supported(INVVPID_ADDR)) 10581 test_skip("INVVPID ADDR unsupported"); 10582 10583 __vmx_pf_vpid_test(invalidate_tlb_invvpid_addr, 0xaaaa); 10584 } 10585 10586 static void vmx_pf_vpid_test(void) 10587 { 10588 /* Need INVVPID(ALL) to flush VPIDs upon wrap/reuse. */ 10589 if (!is_invvpid_type_supported(INVVPID_ALL)) 10590 test_skip("INVVPID ALL unsupported"); 10591 10592 __vmx_pf_vpid_test(invalidate_tlb_new_vpid, 1); 10593 } 10594 10595 static void vmx_l2_ac_test(void) 10596 { 10597 bool hit_ac = false; 10598 10599 write_cr0(read_cr0() | X86_CR0_AM); 10600 write_rflags(read_rflags() | X86_EFLAGS_AC); 10601 10602 run_in_user(generate_usermode_ac, AC_VECTOR, 0, 0, 0, 0, &hit_ac); 10603 report(hit_ac, "Usermode #AC handled in L2"); 10604 vmcall(); 10605 } 10606 10607 struct vmx_exception_test { 10608 u8 vector; 10609 void (*guest_code)(void); 10610 }; 10611 10612 struct vmx_exception_test vmx_exception_tests[] = { 10613 { GP_VECTOR, generate_non_canonical_gp }, 10614 { UD_VECTOR, generate_ud }, 10615 { DE_VECTOR, generate_de }, 10616 { DB_VECTOR, generate_single_step_db }, 10617 { BP_VECTOR, generate_bp }, 10618 { AC_VECTOR, vmx_l2_ac_test }, 10619 { OF_VECTOR, generate_of }, 10620 { NM_VECTOR, generate_cr0_ts_nm }, 10621 { NM_VECTOR, generate_cr0_em_nm }, 10622 }; 10623 10624 static u8 vmx_exception_test_vector; 10625 10626 static void vmx_exception_handler(struct ex_regs *regs) 10627 { 10628 report(regs->vector == vmx_exception_test_vector, 10629 "Handling %s in L2's exception handler", 10630 exception_mnemonic(vmx_exception_test_vector)); 10631 vmcall(); 10632 } 10633 10634 static void handle_exception_in_l2(u8 vector) 10635 { 10636 handler old_handler = handle_exception(vector, vmx_exception_handler); 10637 10638 vmx_exception_test_vector = vector; 10639 10640 enter_guest(); 10641 report(vmcs_read(EXI_REASON) == VMX_VMCALL, 10642 "%s handled by L2", exception_mnemonic(vector)); 10643 10644 handle_exception(vector, old_handler); 10645 } 10646 10647 static void handle_exception_in_l1(u32 vector) 10648 { 10649 u32 old_eb = vmcs_read(EXC_BITMAP); 10650 u32 intr_type; 10651 u32 intr_info; 10652 10653 vmcs_write(EXC_BITMAP, old_eb | (1u << vector)); 10654 10655 enter_guest(); 10656 10657 if (vector == BP_VECTOR || vector == OF_VECTOR) 10658 intr_type = VMX_INTR_TYPE_SOFT_EXCEPTION; 10659 else 10660 intr_type = VMX_INTR_TYPE_HARD_EXCEPTION; 10661 10662 intr_info = vmcs_read(EXI_INTR_INFO); 10663 report((vmcs_read(EXI_REASON) == VMX_EXC_NMI) && 10664 (intr_info & INTR_INFO_VALID_MASK) && 10665 (intr_info & INTR_INFO_VECTOR_MASK) == vector && 10666 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> INTR_INFO_INTR_TYPE_SHIFT) == intr_type, 10667 "%s correctly routed to L1", exception_mnemonic(vector)); 10668 10669 vmcs_write(EXC_BITMAP, old_eb); 10670 } 10671 10672 static void vmx_exception_test(void) 10673 { 10674 struct vmx_exception_test *t; 10675 int i; 10676 10677 for (i = 0; i < ARRAY_SIZE(vmx_exception_tests); i++) { 10678 t = &vmx_exception_tests[i]; 10679 10680 /* 10681 * Override the guest code before each run even though it's the 10682 * same code, the VMCS guest state needs to be reinitialized. 10683 */ 10684 test_override_guest(t->guest_code); 10685 handle_exception_in_l2(t->vector); 10686 10687 test_override_guest(t->guest_code); 10688 handle_exception_in_l1(t->vector); 10689 } 10690 10691 test_set_guest_finished(); 10692 } 10693 10694 #define TEST(name) { #name, .v2 = name } 10695 10696 /* name/init/guest_main/exit_handler/syscall_handler/guest_regs */ 10697 struct vmx_test vmx_tests[] = { 10698 { "null", NULL, basic_guest_main, basic_exit_handler, NULL, {0} }, 10699 { "vmenter", NULL, vmenter_main, vmenter_exit_handler, NULL, {0} }, 10700 { "preemption timer", preemption_timer_init, preemption_timer_main, 10701 preemption_timer_exit_handler, NULL, {0} }, 10702 { "control field PAT", test_ctrl_pat_init, test_ctrl_pat_main, 10703 test_ctrl_pat_exit_handler, NULL, {0} }, 10704 { "control field EFER", test_ctrl_efer_init, test_ctrl_efer_main, 10705 test_ctrl_efer_exit_handler, NULL, {0} }, 10706 { "CR shadowing", NULL, cr_shadowing_main, 10707 cr_shadowing_exit_handler, NULL, {0} }, 10708 { "I/O bitmap", iobmp_init, iobmp_main, iobmp_exit_handler, 10709 NULL, {0} }, 10710 { "instruction intercept", insn_intercept_init, insn_intercept_main, 10711 insn_intercept_exit_handler, NULL, {0} }, 10712 { "EPT A/D disabled", ept_init, ept_main, ept_exit_handler, NULL, {0} }, 10713 { "EPT A/D enabled", eptad_init, eptad_main, eptad_exit_handler, NULL, {0} }, 10714 { "PML", pml_init, pml_main, pml_exit_handler, NULL, {0} }, 10715 { "interrupt", interrupt_init, interrupt_main, 10716 interrupt_exit_handler, NULL, {0} }, 10717 { "nmi_hlt", nmi_hlt_init, nmi_hlt_main, 10718 nmi_hlt_exit_handler, NULL, {0} }, 10719 { "debug controls", dbgctls_init, dbgctls_main, dbgctls_exit_handler, 10720 NULL, {0} }, 10721 { "MSR switch", msr_switch_init, msr_switch_main, 10722 msr_switch_exit_handler, NULL, {0}, msr_switch_entry_failure }, 10723 { "vmmcall", vmmcall_init, vmmcall_main, vmmcall_exit_handler, NULL, {0} }, 10724 { "disable RDTSCP", disable_rdtscp_init, disable_rdtscp_main, 10725 disable_rdtscp_exit_handler, NULL, {0} }, 10726 { "exit_monitor_from_l2_test", NULL, exit_monitor_from_l2_main, 10727 exit_monitor_from_l2_handler, NULL, {0} }, 10728 { "invalid_msr", invalid_msr_init, invalid_msr_main, 10729 invalid_msr_exit_handler, NULL, {0}, invalid_msr_entry_failure}, 10730 /* Basic V2 tests. */ 10731 TEST(v2_null_test), 10732 TEST(v2_multiple_entries_test), 10733 TEST(fixture_test_case1), 10734 TEST(fixture_test_case2), 10735 /* Opcode tests. */ 10736 TEST(invvpid_test), 10737 /* VM-entry tests */ 10738 TEST(vmx_controls_test), 10739 TEST(vmx_host_state_area_test), 10740 TEST(vmx_guest_state_area_test), 10741 TEST(vmentry_movss_shadow_test), 10742 TEST(vmentry_unrestricted_guest_test), 10743 /* APICv tests */ 10744 TEST(vmx_eoi_bitmap_ioapic_scan_test), 10745 TEST(vmx_hlt_with_rvi_test), 10746 TEST(apic_reg_virt_test), 10747 TEST(virt_x2apic_mode_test), 10748 /* APIC pass-through tests */ 10749 TEST(vmx_apic_passthrough_test), 10750 TEST(vmx_apic_passthrough_thread_test), 10751 TEST(vmx_apic_passthrough_tpr_threshold_test), 10752 TEST(vmx_init_signal_test), 10753 TEST(vmx_sipi_signal_test), 10754 /* VMCS Shadowing tests */ 10755 TEST(vmx_vmcs_shadow_test), 10756 /* Regression tests */ 10757 TEST(vmx_ldtr_test), 10758 TEST(vmx_cr_load_test), 10759 TEST(vmx_cr4_osxsave_test), 10760 TEST(vmx_no_nm_test), 10761 TEST(vmx_db_test), 10762 TEST(vmx_nmi_window_test), 10763 TEST(vmx_intr_window_test), 10764 TEST(vmx_pending_event_test), 10765 TEST(vmx_pending_event_hlt_test), 10766 TEST(vmx_store_tsc_test), 10767 TEST(vmx_preemption_timer_zero_test), 10768 TEST(vmx_preemption_timer_tf_test), 10769 TEST(vmx_preemption_timer_expiry_test), 10770 /* EPT access tests. */ 10771 TEST(ept_access_test_not_present), 10772 TEST(ept_access_test_read_only), 10773 TEST(ept_access_test_write_only), 10774 TEST(ept_access_test_read_write), 10775 TEST(ept_access_test_execute_only), 10776 TEST(ept_access_test_read_execute), 10777 TEST(ept_access_test_write_execute), 10778 TEST(ept_access_test_read_write_execute), 10779 TEST(ept_access_test_reserved_bits), 10780 TEST(ept_access_test_ignored_bits), 10781 TEST(ept_access_test_paddr_not_present_ad_disabled), 10782 TEST(ept_access_test_paddr_not_present_ad_enabled), 10783 TEST(ept_access_test_paddr_read_only_ad_disabled), 10784 TEST(ept_access_test_paddr_read_only_ad_enabled), 10785 TEST(ept_access_test_paddr_read_write), 10786 TEST(ept_access_test_paddr_read_write_execute), 10787 TEST(ept_access_test_paddr_read_execute_ad_disabled), 10788 TEST(ept_access_test_paddr_read_execute_ad_enabled), 10789 TEST(ept_access_test_paddr_not_present_page_fault), 10790 TEST(ept_access_test_force_2m_page), 10791 /* Atomic MSR switch tests. */ 10792 TEST(atomic_switch_max_msrs_test), 10793 TEST(atomic_switch_overflow_msrs_test), 10794 TEST(rdtsc_vmexit_diff_test), 10795 TEST(vmx_mtf_test), 10796 TEST(vmx_mtf_pdpte_test), 10797 TEST(vmx_pf_exception_test), 10798 TEST(vmx_pf_exception_forced_emulation_test), 10799 TEST(vmx_pf_no_vpid_test), 10800 TEST(vmx_pf_invvpid_test), 10801 TEST(vmx_pf_vpid_test), 10802 TEST(vmx_exception_test), 10803 { NULL, NULL, NULL, NULL, NULL, {0} }, 10804 }; 10805