1 /* 2 * All test cases of nested virtualization should be in this file 3 * 4 * Author : Arthur Chunqi Li <yzt356@gmail.com> 5 */ 6 7 #include <asm/debugreg.h> 8 9 #include "vmx.h" 10 #include "msr.h" 11 #include "processor.h" 12 #include "vm.h" 13 #include "pci.h" 14 #include "fwcfg.h" 15 #include "isr.h" 16 #include "desc.h" 17 #include "apic.h" 18 #include "types.h" 19 #include "vmalloc.h" 20 #include "alloc_page.h" 21 #include "smp.h" 22 #include "delay.h" 23 24 #define NONCANONICAL 0xaaaaaaaaaaaaaaaaull 25 26 #define VPID_CAP_INVVPID_TYPES_SHIFT 40 27 28 u64 ia32_pat; 29 u64 ia32_efer; 30 void *io_bitmap_a, *io_bitmap_b; 31 u16 ioport; 32 33 unsigned long *pml4; 34 u64 eptp; 35 void *data_page1, *data_page2; 36 37 phys_addr_t pci_physaddr; 38 39 void *pml_log; 40 #define PML_INDEX 512 41 42 static inline unsigned ffs(unsigned x) 43 { 44 int pos = -1; 45 46 __asm__ __volatile__("bsf %1, %%eax; cmovnz %%eax, %0" 47 : "+r"(pos) : "rm"(x) : "eax"); 48 return pos + 1; 49 } 50 51 static inline void vmcall(void) 52 { 53 asm volatile("vmcall"); 54 } 55 56 static void basic_guest_main(void) 57 { 58 report("Basic VMX test", 1); 59 } 60 61 static int basic_exit_handler(void) 62 { 63 report("Basic VMX test", 0); 64 print_vmexit_info(); 65 return VMX_TEST_EXIT; 66 } 67 68 static void vmenter_main(void) 69 { 70 u64 rax; 71 u64 rsp, resume_rsp; 72 73 report("test vmlaunch", 1); 74 75 asm volatile( 76 "mov %%rsp, %0\n\t" 77 "mov %3, %%rax\n\t" 78 "vmcall\n\t" 79 "mov %%rax, %1\n\t" 80 "mov %%rsp, %2\n\t" 81 : "=r"(rsp), "=r"(rax), "=r"(resume_rsp) 82 : "g"(0xABCD)); 83 report("test vmresume", (rax == 0xFFFF) && (rsp == resume_rsp)); 84 } 85 86 static int vmenter_exit_handler(void) 87 { 88 u64 guest_rip; 89 ulong reason; 90 91 guest_rip = vmcs_read(GUEST_RIP); 92 reason = vmcs_read(EXI_REASON) & 0xff; 93 switch (reason) { 94 case VMX_VMCALL: 95 if (regs.rax != 0xABCD) { 96 report("test vmresume", 0); 97 return VMX_TEST_VMEXIT; 98 } 99 regs.rax = 0xFFFF; 100 vmcs_write(GUEST_RIP, guest_rip + 3); 101 return VMX_TEST_RESUME; 102 default: 103 report("test vmresume", 0); 104 print_vmexit_info(); 105 } 106 return VMX_TEST_VMEXIT; 107 } 108 109 u32 preempt_scale; 110 volatile unsigned long long tsc_val; 111 volatile u32 preempt_val; 112 u64 saved_rip; 113 114 static int preemption_timer_init(struct vmcs *vmcs) 115 { 116 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 117 printf("\tPreemption timer is not supported\n"); 118 return VMX_TEST_EXIT; 119 } 120 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 121 preempt_val = 10000000; 122 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 123 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 124 125 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 126 printf("\tSave preemption value is not supported\n"); 127 128 return VMX_TEST_START; 129 } 130 131 static void preemption_timer_main(void) 132 { 133 tsc_val = rdtsc(); 134 if (ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) { 135 vmx_set_test_stage(0); 136 vmcall(); 137 if (vmx_get_test_stage() == 1) 138 vmcall(); 139 } 140 vmx_set_test_stage(1); 141 while (vmx_get_test_stage() == 1) { 142 if (((rdtsc() - tsc_val) >> preempt_scale) 143 > 10 * preempt_val) { 144 vmx_set_test_stage(2); 145 vmcall(); 146 } 147 } 148 tsc_val = rdtsc(); 149 asm volatile ("hlt"); 150 vmcall(); 151 vmx_set_test_stage(5); 152 vmcall(); 153 } 154 155 static int preemption_timer_exit_handler(void) 156 { 157 bool guest_halted; 158 u64 guest_rip; 159 ulong reason; 160 u32 insn_len; 161 u32 ctrl_exit; 162 163 guest_rip = vmcs_read(GUEST_RIP); 164 reason = vmcs_read(EXI_REASON) & 0xff; 165 insn_len = vmcs_read(EXI_INST_LEN); 166 switch (reason) { 167 case VMX_PREEMPT: 168 switch (vmx_get_test_stage()) { 169 case 1: 170 case 2: 171 report("busy-wait for preemption timer", 172 ((rdtsc() - tsc_val) >> preempt_scale) >= 173 preempt_val); 174 vmx_set_test_stage(3); 175 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 176 return VMX_TEST_RESUME; 177 case 3: 178 guest_halted = 179 (vmcs_read(GUEST_ACTV_STATE) == ACTV_HLT); 180 report("preemption timer during hlt", 181 ((rdtsc() - tsc_val) >> preempt_scale) >= 182 preempt_val && guest_halted); 183 vmx_set_test_stage(4); 184 vmcs_write(PIN_CONTROLS, 185 vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 186 vmcs_write(EXI_CONTROLS, 187 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_PREEMPT); 188 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 189 return VMX_TEST_RESUME; 190 case 4: 191 report("preemption timer with 0 value", 192 saved_rip == guest_rip); 193 break; 194 default: 195 report("Invalid stage.", false); 196 print_vmexit_info(); 197 break; 198 } 199 break; 200 case VMX_VMCALL: 201 vmcs_write(GUEST_RIP, guest_rip + insn_len); 202 switch (vmx_get_test_stage()) { 203 case 0: 204 report("Keep preemption value", 205 vmcs_read(PREEMPT_TIMER_VALUE) == preempt_val); 206 vmx_set_test_stage(1); 207 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 208 ctrl_exit = (vmcs_read(EXI_CONTROLS) | 209 EXI_SAVE_PREEMPT) & ctrl_exit_rev.clr; 210 vmcs_write(EXI_CONTROLS, ctrl_exit); 211 return VMX_TEST_RESUME; 212 case 1: 213 report("Save preemption value", 214 vmcs_read(PREEMPT_TIMER_VALUE) < preempt_val); 215 return VMX_TEST_RESUME; 216 case 2: 217 report("busy-wait for preemption timer", 0); 218 vmx_set_test_stage(3); 219 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 220 return VMX_TEST_RESUME; 221 case 3: 222 report("preemption timer during hlt", 0); 223 vmx_set_test_stage(4); 224 /* fall through */ 225 case 4: 226 vmcs_write(PIN_CONTROLS, 227 vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 228 vmcs_write(PREEMPT_TIMER_VALUE, 0); 229 saved_rip = guest_rip + insn_len; 230 return VMX_TEST_RESUME; 231 case 5: 232 report("preemption timer with 0 value (vmcall stage 5)", 0); 233 break; 234 default: 235 // Should not reach here 236 report("unexpected stage, %d", false, 237 vmx_get_test_stage()); 238 print_vmexit_info(); 239 return VMX_TEST_VMEXIT; 240 } 241 break; 242 default: 243 report("Unknown exit reason, %ld", false, reason); 244 print_vmexit_info(); 245 } 246 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 247 return VMX_TEST_VMEXIT; 248 } 249 250 static void msr_bmp_init(void) 251 { 252 void *msr_bitmap; 253 u32 ctrl_cpu0; 254 255 msr_bitmap = alloc_page(); 256 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 257 ctrl_cpu0 |= CPU_MSR_BITMAP; 258 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 259 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 260 } 261 262 static void *get_msr_bitmap(void) 263 { 264 void *msr_bitmap; 265 266 if (vmcs_read(CPU_EXEC_CTRL0) & CPU_MSR_BITMAP) { 267 msr_bitmap = (void *)vmcs_read(MSR_BITMAP); 268 } else { 269 msr_bitmap = alloc_page(); 270 memset(msr_bitmap, 0xff, PAGE_SIZE); 271 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 272 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_MSR_BITMAP); 273 } 274 275 return msr_bitmap; 276 } 277 278 static void disable_intercept_for_x2apic_msrs(void) 279 { 280 unsigned long *msr_bitmap = (unsigned long *)get_msr_bitmap(); 281 u32 msr; 282 283 for (msr = APIC_BASE_MSR; 284 msr < (APIC_BASE_MSR+0xff); 285 msr += BITS_PER_LONG) { 286 unsigned int word = msr / BITS_PER_LONG; 287 288 msr_bitmap[word] = 0; 289 msr_bitmap[word + (0x800 / sizeof(long))] = 0; 290 } 291 } 292 293 static int test_ctrl_pat_init(struct vmcs *vmcs) 294 { 295 u64 ctrl_ent; 296 u64 ctrl_exi; 297 298 msr_bmp_init(); 299 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT) && 300 !(ctrl_exit_rev.clr & EXI_LOAD_PAT) && 301 !(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 302 printf("\tSave/load PAT is not supported\n"); 303 return 1; 304 } 305 306 ctrl_ent = vmcs_read(ENT_CONTROLS); 307 ctrl_exi = vmcs_read(EXI_CONTROLS); 308 ctrl_ent |= ctrl_enter_rev.clr & ENT_LOAD_PAT; 309 ctrl_exi |= ctrl_exit_rev.clr & (EXI_SAVE_PAT | EXI_LOAD_PAT); 310 vmcs_write(ENT_CONTROLS, ctrl_ent); 311 vmcs_write(EXI_CONTROLS, ctrl_exi); 312 ia32_pat = rdmsr(MSR_IA32_CR_PAT); 313 vmcs_write(GUEST_PAT, 0x0); 314 vmcs_write(HOST_PAT, ia32_pat); 315 return VMX_TEST_START; 316 } 317 318 static void test_ctrl_pat_main(void) 319 { 320 u64 guest_ia32_pat; 321 322 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 323 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) 324 printf("\tENT_LOAD_PAT is not supported.\n"); 325 else { 326 if (guest_ia32_pat != 0) { 327 report("Entry load PAT", 0); 328 return; 329 } 330 } 331 wrmsr(MSR_IA32_CR_PAT, 0x6); 332 vmcall(); 333 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 334 if (ctrl_enter_rev.clr & ENT_LOAD_PAT) 335 report("Entry load PAT", guest_ia32_pat == ia32_pat); 336 } 337 338 static int test_ctrl_pat_exit_handler(void) 339 { 340 u64 guest_rip; 341 ulong reason; 342 u64 guest_pat; 343 344 guest_rip = vmcs_read(GUEST_RIP); 345 reason = vmcs_read(EXI_REASON) & 0xff; 346 switch (reason) { 347 case VMX_VMCALL: 348 guest_pat = vmcs_read(GUEST_PAT); 349 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT)) { 350 printf("\tEXI_SAVE_PAT is not supported\n"); 351 vmcs_write(GUEST_PAT, 0x6); 352 } else { 353 report("Exit save PAT", guest_pat == 0x6); 354 } 355 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) 356 printf("\tEXI_LOAD_PAT is not supported\n"); 357 else 358 report("Exit load PAT", rdmsr(MSR_IA32_CR_PAT) == ia32_pat); 359 vmcs_write(GUEST_PAT, ia32_pat); 360 vmcs_write(GUEST_RIP, guest_rip + 3); 361 return VMX_TEST_RESUME; 362 default: 363 printf("ERROR : Undefined exit reason, reason = %ld.\n", reason); 364 break; 365 } 366 return VMX_TEST_VMEXIT; 367 } 368 369 static int test_ctrl_efer_init(struct vmcs *vmcs) 370 { 371 u64 ctrl_ent; 372 u64 ctrl_exi; 373 374 msr_bmp_init(); 375 ctrl_ent = vmcs_read(ENT_CONTROLS) | ENT_LOAD_EFER; 376 ctrl_exi = vmcs_read(EXI_CONTROLS) | EXI_SAVE_EFER | EXI_LOAD_EFER; 377 vmcs_write(ENT_CONTROLS, ctrl_ent & ctrl_enter_rev.clr); 378 vmcs_write(EXI_CONTROLS, ctrl_exi & ctrl_exit_rev.clr); 379 ia32_efer = rdmsr(MSR_EFER); 380 vmcs_write(GUEST_EFER, ia32_efer ^ EFER_NX); 381 vmcs_write(HOST_EFER, ia32_efer ^ EFER_NX); 382 return VMX_TEST_START; 383 } 384 385 static void test_ctrl_efer_main(void) 386 { 387 u64 guest_ia32_efer; 388 389 guest_ia32_efer = rdmsr(MSR_EFER); 390 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) 391 printf("\tENT_LOAD_EFER is not supported.\n"); 392 else { 393 if (guest_ia32_efer != (ia32_efer ^ EFER_NX)) { 394 report("Entry load EFER", 0); 395 return; 396 } 397 } 398 wrmsr(MSR_EFER, ia32_efer); 399 vmcall(); 400 guest_ia32_efer = rdmsr(MSR_EFER); 401 if (ctrl_enter_rev.clr & ENT_LOAD_EFER) 402 report("Entry load EFER", guest_ia32_efer == ia32_efer); 403 } 404 405 static int test_ctrl_efer_exit_handler(void) 406 { 407 u64 guest_rip; 408 ulong reason; 409 u64 guest_efer; 410 411 guest_rip = vmcs_read(GUEST_RIP); 412 reason = vmcs_read(EXI_REASON) & 0xff; 413 switch (reason) { 414 case VMX_VMCALL: 415 guest_efer = vmcs_read(GUEST_EFER); 416 if (!(ctrl_exit_rev.clr & EXI_SAVE_EFER)) { 417 printf("\tEXI_SAVE_EFER is not supported\n"); 418 vmcs_write(GUEST_EFER, ia32_efer); 419 } else { 420 report("Exit save EFER", guest_efer == ia32_efer); 421 } 422 if (!(ctrl_exit_rev.clr & EXI_LOAD_EFER)) { 423 printf("\tEXI_LOAD_EFER is not supported\n"); 424 wrmsr(MSR_EFER, ia32_efer ^ EFER_NX); 425 } else { 426 report("Exit load EFER", rdmsr(MSR_EFER) == (ia32_efer ^ EFER_NX)); 427 } 428 vmcs_write(GUEST_PAT, ia32_efer); 429 vmcs_write(GUEST_RIP, guest_rip + 3); 430 return VMX_TEST_RESUME; 431 default: 432 printf("ERROR : Undefined exit reason, reason = %ld.\n", reason); 433 break; 434 } 435 return VMX_TEST_VMEXIT; 436 } 437 438 u32 guest_cr0, guest_cr4; 439 440 static void cr_shadowing_main(void) 441 { 442 u32 cr0, cr4, tmp; 443 444 // Test read through 445 vmx_set_test_stage(0); 446 guest_cr0 = read_cr0(); 447 if (vmx_get_test_stage() == 1) 448 report("Read through CR0", 0); 449 else 450 vmcall(); 451 vmx_set_test_stage(1); 452 guest_cr4 = read_cr4(); 453 if (vmx_get_test_stage() == 2) 454 report("Read through CR4", 0); 455 else 456 vmcall(); 457 // Test write through 458 guest_cr0 = guest_cr0 ^ (X86_CR0_TS | X86_CR0_MP); 459 guest_cr4 = guest_cr4 ^ (X86_CR4_TSD | X86_CR4_DE); 460 vmx_set_test_stage(2); 461 write_cr0(guest_cr0); 462 if (vmx_get_test_stage() == 3) 463 report("Write throuth CR0", 0); 464 else 465 vmcall(); 466 vmx_set_test_stage(3); 467 write_cr4(guest_cr4); 468 if (vmx_get_test_stage() == 4) 469 report("Write through CR4", 0); 470 else 471 vmcall(); 472 // Test read shadow 473 vmx_set_test_stage(4); 474 vmcall(); 475 cr0 = read_cr0(); 476 if (vmx_get_test_stage() != 5) 477 report("Read shadowing CR0", cr0 == guest_cr0); 478 vmx_set_test_stage(5); 479 cr4 = read_cr4(); 480 if (vmx_get_test_stage() != 6) 481 report("Read shadowing CR4", cr4 == guest_cr4); 482 // Test write shadow (same value with shadow) 483 vmx_set_test_stage(6); 484 write_cr0(guest_cr0); 485 if (vmx_get_test_stage() == 7) 486 report("Write shadowing CR0 (same value with shadow)", 0); 487 else 488 vmcall(); 489 vmx_set_test_stage(7); 490 write_cr4(guest_cr4); 491 if (vmx_get_test_stage() == 8) 492 report("Write shadowing CR4 (same value with shadow)", 0); 493 else 494 vmcall(); 495 // Test write shadow (different value) 496 vmx_set_test_stage(8); 497 tmp = guest_cr0 ^ X86_CR0_TS; 498 asm volatile("mov %0, %%rsi\n\t" 499 "mov %%rsi, %%cr0\n\t" 500 ::"m"(tmp) 501 :"rsi", "memory", "cc"); 502 report("Write shadowing different X86_CR0_TS", vmx_get_test_stage() == 9); 503 vmx_set_test_stage(9); 504 tmp = guest_cr0 ^ X86_CR0_MP; 505 asm volatile("mov %0, %%rsi\n\t" 506 "mov %%rsi, %%cr0\n\t" 507 ::"m"(tmp) 508 :"rsi", "memory", "cc"); 509 report("Write shadowing different X86_CR0_MP", vmx_get_test_stage() == 10); 510 vmx_set_test_stage(10); 511 tmp = guest_cr4 ^ X86_CR4_TSD; 512 asm volatile("mov %0, %%rsi\n\t" 513 "mov %%rsi, %%cr4\n\t" 514 ::"m"(tmp) 515 :"rsi", "memory", "cc"); 516 report("Write shadowing different X86_CR4_TSD", vmx_get_test_stage() == 11); 517 vmx_set_test_stage(11); 518 tmp = guest_cr4 ^ X86_CR4_DE; 519 asm volatile("mov %0, %%rsi\n\t" 520 "mov %%rsi, %%cr4\n\t" 521 ::"m"(tmp) 522 :"rsi", "memory", "cc"); 523 report("Write shadowing different X86_CR4_DE", vmx_get_test_stage() == 12); 524 } 525 526 static int cr_shadowing_exit_handler(void) 527 { 528 u64 guest_rip; 529 ulong reason; 530 u32 insn_len; 531 u32 exit_qual; 532 533 guest_rip = vmcs_read(GUEST_RIP); 534 reason = vmcs_read(EXI_REASON) & 0xff; 535 insn_len = vmcs_read(EXI_INST_LEN); 536 exit_qual = vmcs_read(EXI_QUALIFICATION); 537 switch (reason) { 538 case VMX_VMCALL: 539 switch (vmx_get_test_stage()) { 540 case 0: 541 report("Read through CR0", guest_cr0 == vmcs_read(GUEST_CR0)); 542 break; 543 case 1: 544 report("Read through CR4", guest_cr4 == vmcs_read(GUEST_CR4)); 545 break; 546 case 2: 547 report("Write through CR0", guest_cr0 == vmcs_read(GUEST_CR0)); 548 break; 549 case 3: 550 report("Write through CR4", guest_cr4 == vmcs_read(GUEST_CR4)); 551 break; 552 case 4: 553 guest_cr0 = vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP); 554 guest_cr4 = vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE); 555 vmcs_write(CR0_MASK, X86_CR0_TS | X86_CR0_MP); 556 vmcs_write(CR0_READ_SHADOW, guest_cr0 & (X86_CR0_TS | X86_CR0_MP)); 557 vmcs_write(CR4_MASK, X86_CR4_TSD | X86_CR4_DE); 558 vmcs_write(CR4_READ_SHADOW, guest_cr4 & (X86_CR4_TSD | X86_CR4_DE)); 559 break; 560 case 6: 561 report("Write shadowing CR0 (same value)", 562 guest_cr0 == (vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP))); 563 break; 564 case 7: 565 report("Write shadowing CR4 (same value)", 566 guest_cr4 == (vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE))); 567 break; 568 default: 569 // Should not reach here 570 report("unexpected stage, %d", false, 571 vmx_get_test_stage()); 572 print_vmexit_info(); 573 return VMX_TEST_VMEXIT; 574 } 575 vmcs_write(GUEST_RIP, guest_rip + insn_len); 576 return VMX_TEST_RESUME; 577 case VMX_CR: 578 switch (vmx_get_test_stage()) { 579 case 4: 580 report("Read shadowing CR0", 0); 581 vmx_inc_test_stage(); 582 break; 583 case 5: 584 report("Read shadowing CR4", 0); 585 vmx_inc_test_stage(); 586 break; 587 case 6: 588 report("Write shadowing CR0 (same value)", 0); 589 vmx_inc_test_stage(); 590 break; 591 case 7: 592 report("Write shadowing CR4 (same value)", 0); 593 vmx_inc_test_stage(); 594 break; 595 case 8: 596 case 9: 597 // 0x600 encodes "mov %esi, %cr0" 598 if (exit_qual == 0x600) 599 vmx_inc_test_stage(); 600 break; 601 case 10: 602 case 11: 603 // 0x604 encodes "mov %esi, %cr4" 604 if (exit_qual == 0x604) 605 vmx_inc_test_stage(); 606 break; 607 default: 608 // Should not reach here 609 report("unexpected stage, %d", false, 610 vmx_get_test_stage()); 611 print_vmexit_info(); 612 return VMX_TEST_VMEXIT; 613 } 614 vmcs_write(GUEST_RIP, guest_rip + insn_len); 615 return VMX_TEST_RESUME; 616 default: 617 report("Unknown exit reason, %ld", false, reason); 618 print_vmexit_info(); 619 } 620 return VMX_TEST_VMEXIT; 621 } 622 623 static int iobmp_init(struct vmcs *vmcs) 624 { 625 u32 ctrl_cpu0; 626 627 io_bitmap_a = alloc_page(); 628 io_bitmap_b = alloc_page(); 629 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 630 ctrl_cpu0 |= CPU_IO_BITMAP; 631 ctrl_cpu0 &= (~CPU_IO); 632 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 633 vmcs_write(IO_BITMAP_A, (u64)io_bitmap_a); 634 vmcs_write(IO_BITMAP_B, (u64)io_bitmap_b); 635 return VMX_TEST_START; 636 } 637 638 static void iobmp_main(void) 639 { 640 // stage 0, test IO pass 641 vmx_set_test_stage(0); 642 inb(0x5000); 643 outb(0x0, 0x5000); 644 report("I/O bitmap - I/O pass", vmx_get_test_stage() == 0); 645 // test IO width, in/out 646 ((u8 *)io_bitmap_a)[0] = 0xFF; 647 vmx_set_test_stage(2); 648 inb(0x0); 649 report("I/O bitmap - trap in", vmx_get_test_stage() == 3); 650 vmx_set_test_stage(3); 651 outw(0x0, 0x0); 652 report("I/O bitmap - trap out", vmx_get_test_stage() == 4); 653 vmx_set_test_stage(4); 654 inl(0x0); 655 report("I/O bitmap - I/O width, long", vmx_get_test_stage() == 5); 656 // test low/high IO port 657 vmx_set_test_stage(5); 658 ((u8 *)io_bitmap_a)[0x5000 / 8] = (1 << (0x5000 % 8)); 659 inb(0x5000); 660 report("I/O bitmap - I/O port, low part", vmx_get_test_stage() == 6); 661 vmx_set_test_stage(6); 662 ((u8 *)io_bitmap_b)[0x1000 / 8] = (1 << (0x1000 % 8)); 663 inb(0x9000); 664 report("I/O bitmap - I/O port, high part", vmx_get_test_stage() == 7); 665 // test partial pass 666 vmx_set_test_stage(7); 667 inl(0x4FFF); 668 report("I/O bitmap - partial pass", vmx_get_test_stage() == 8); 669 // test overrun 670 vmx_set_test_stage(8); 671 memset(io_bitmap_a, 0x0, PAGE_SIZE); 672 memset(io_bitmap_b, 0x0, PAGE_SIZE); 673 inl(0xFFFF); 674 report("I/O bitmap - overrun", vmx_get_test_stage() == 9); 675 vmx_set_test_stage(9); 676 vmcall(); 677 outb(0x0, 0x0); 678 report("I/O bitmap - ignore unconditional exiting", 679 vmx_get_test_stage() == 9); 680 vmx_set_test_stage(10); 681 vmcall(); 682 outb(0x0, 0x0); 683 report("I/O bitmap - unconditional exiting", 684 vmx_get_test_stage() == 11); 685 } 686 687 static int iobmp_exit_handler(void) 688 { 689 u64 guest_rip; 690 ulong reason, exit_qual; 691 u32 insn_len, ctrl_cpu0; 692 693 guest_rip = vmcs_read(GUEST_RIP); 694 reason = vmcs_read(EXI_REASON) & 0xff; 695 exit_qual = vmcs_read(EXI_QUALIFICATION); 696 insn_len = vmcs_read(EXI_INST_LEN); 697 switch (reason) { 698 case VMX_IO: 699 switch (vmx_get_test_stage()) { 700 case 0: 701 case 1: 702 vmx_inc_test_stage(); 703 break; 704 case 2: 705 report("I/O bitmap - I/O width, byte", 706 (exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_BYTE); 707 report("I/O bitmap - I/O direction, in", exit_qual & VMX_IO_IN); 708 vmx_inc_test_stage(); 709 break; 710 case 3: 711 report("I/O bitmap - I/O width, word", 712 (exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_WORD); 713 report("I/O bitmap - I/O direction, out", 714 !(exit_qual & VMX_IO_IN)); 715 vmx_inc_test_stage(); 716 break; 717 case 4: 718 report("I/O bitmap - I/O width, long", 719 (exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_LONG); 720 vmx_inc_test_stage(); 721 break; 722 case 5: 723 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x5000) 724 vmx_inc_test_stage(); 725 break; 726 case 6: 727 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x9000) 728 vmx_inc_test_stage(); 729 break; 730 case 7: 731 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x4FFF) 732 vmx_inc_test_stage(); 733 break; 734 case 8: 735 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0xFFFF) 736 vmx_inc_test_stage(); 737 break; 738 case 9: 739 case 10: 740 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 741 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0 & ~CPU_IO); 742 vmx_inc_test_stage(); 743 break; 744 default: 745 // Should not reach here 746 report("unexpected stage, %d", false, 747 vmx_get_test_stage()); 748 print_vmexit_info(); 749 return VMX_TEST_VMEXIT; 750 } 751 vmcs_write(GUEST_RIP, guest_rip + insn_len); 752 return VMX_TEST_RESUME; 753 case VMX_VMCALL: 754 switch (vmx_get_test_stage()) { 755 case 9: 756 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 757 ctrl_cpu0 |= CPU_IO | CPU_IO_BITMAP; 758 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 759 break; 760 case 10: 761 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 762 ctrl_cpu0 = (ctrl_cpu0 & ~CPU_IO_BITMAP) | CPU_IO; 763 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 764 break; 765 default: 766 // Should not reach here 767 report("unexpected stage, %d", false, 768 vmx_get_test_stage()); 769 print_vmexit_info(); 770 return VMX_TEST_VMEXIT; 771 } 772 vmcs_write(GUEST_RIP, guest_rip + insn_len); 773 return VMX_TEST_RESUME; 774 default: 775 printf("guest_rip = %#lx\n", guest_rip); 776 printf("\tERROR : Undefined exit reason, reason = %ld.\n", reason); 777 break; 778 } 779 return VMX_TEST_VMEXIT; 780 } 781 782 #define INSN_CPU0 0 783 #define INSN_CPU1 1 784 #define INSN_ALWAYS_TRAP 2 785 786 #define FIELD_EXIT_QUAL (1 << 0) 787 #define FIELD_INSN_INFO (1 << 1) 788 789 asm( 790 "insn_hlt: hlt;ret\n\t" 791 "insn_invlpg: invlpg 0x12345678;ret\n\t" 792 "insn_mwait: xor %eax, %eax; xor %ecx, %ecx; mwait;ret\n\t" 793 "insn_rdpmc: xor %ecx, %ecx; rdpmc;ret\n\t" 794 "insn_rdtsc: rdtsc;ret\n\t" 795 "insn_cr3_load: mov cr3,%rax; mov %rax,%cr3;ret\n\t" 796 "insn_cr3_store: mov %cr3,%rax;ret\n\t" 797 #ifdef __x86_64__ 798 "insn_cr8_load: xor %eax, %eax; mov %rax,%cr8;ret\n\t" 799 "insn_cr8_store: mov %cr8,%rax;ret\n\t" 800 #endif 801 "insn_monitor: xor %eax, %eax; xor %ecx, %ecx; xor %edx, %edx; monitor;ret\n\t" 802 "insn_pause: pause;ret\n\t" 803 "insn_wbinvd: wbinvd;ret\n\t" 804 "insn_cpuid: mov $10, %eax; cpuid;ret\n\t" 805 "insn_invd: invd;ret\n\t" 806 "insn_sgdt: sgdt gdt64_desc;ret\n\t" 807 "insn_lgdt: lgdt gdt64_desc;ret\n\t" 808 "insn_sidt: sidt idt_descr;ret\n\t" 809 "insn_lidt: lidt idt_descr;ret\n\t" 810 "insn_sldt: sldt %ax;ret\n\t" 811 "insn_lldt: xor %eax, %eax; lldt %ax;ret\n\t" 812 "insn_str: str %ax;ret\n\t" 813 "insn_rdrand: rdrand %rax;ret\n\t" 814 "insn_rdseed: rdseed %rax;ret\n\t" 815 ); 816 extern void insn_hlt(void); 817 extern void insn_invlpg(void); 818 extern void insn_mwait(void); 819 extern void insn_rdpmc(void); 820 extern void insn_rdtsc(void); 821 extern void insn_cr3_load(void); 822 extern void insn_cr3_store(void); 823 #ifdef __x86_64__ 824 extern void insn_cr8_load(void); 825 extern void insn_cr8_store(void); 826 #endif 827 extern void insn_monitor(void); 828 extern void insn_pause(void); 829 extern void insn_wbinvd(void); 830 extern void insn_sgdt(void); 831 extern void insn_lgdt(void); 832 extern void insn_sidt(void); 833 extern void insn_lidt(void); 834 extern void insn_sldt(void); 835 extern void insn_lldt(void); 836 extern void insn_str(void); 837 extern void insn_cpuid(void); 838 extern void insn_invd(void); 839 extern void insn_rdrand(void); 840 extern void insn_rdseed(void); 841 842 u32 cur_insn; 843 u64 cr3; 844 845 #define X86_FEATURE_MONITOR (1 << 3) 846 847 typedef bool (*supported_fn)(void); 848 849 static bool monitor_supported(void) 850 { 851 return this_cpu_has(X86_FEATURE_MWAIT); 852 } 853 854 struct insn_table { 855 const char *name; 856 u32 flag; 857 void (*insn_func)(void); 858 u32 type; 859 u32 reason; 860 ulong exit_qual; 861 u32 insn_info; 862 // Use FIELD_EXIT_QUAL and FIELD_INSN_INFO to define 863 // which field need to be tested, reason is always tested 864 u32 test_field; 865 const supported_fn supported_fn; 866 u8 disabled; 867 }; 868 869 /* 870 * Add more test cases of instruction intercept here. Elements in this 871 * table is: 872 * name/control flag/insn function/type/exit reason/exit qulification/ 873 * instruction info/field to test 874 * The last field defines which fields (exit_qual and insn_info) need to be 875 * tested in exit handler. If set to 0, only "reason" is checked. 876 */ 877 static struct insn_table insn_table[] = { 878 // Flags for Primary Processor-Based VM-Execution Controls 879 {"HLT", CPU_HLT, insn_hlt, INSN_CPU0, 12, 0, 0, 0}, 880 {"INVLPG", CPU_INVLPG, insn_invlpg, INSN_CPU0, 14, 881 0x12345678, 0, FIELD_EXIT_QUAL}, 882 {"MWAIT", CPU_MWAIT, insn_mwait, INSN_CPU0, 36, 0, 0, 0, &monitor_supported}, 883 {"RDPMC", CPU_RDPMC, insn_rdpmc, INSN_CPU0, 15, 0, 0, 0}, 884 {"RDTSC", CPU_RDTSC, insn_rdtsc, INSN_CPU0, 16, 0, 0, 0}, 885 {"CR3 load", CPU_CR3_LOAD, insn_cr3_load, INSN_CPU0, 28, 0x3, 0, 886 FIELD_EXIT_QUAL}, 887 {"CR3 store", CPU_CR3_STORE, insn_cr3_store, INSN_CPU0, 28, 0x13, 0, 888 FIELD_EXIT_QUAL}, 889 #ifdef __x86_64__ 890 {"CR8 load", CPU_CR8_LOAD, insn_cr8_load, INSN_CPU0, 28, 0x8, 0, 891 FIELD_EXIT_QUAL}, 892 {"CR8 store", CPU_CR8_STORE, insn_cr8_store, INSN_CPU0, 28, 0x18, 0, 893 FIELD_EXIT_QUAL}, 894 #endif 895 {"MONITOR", CPU_MONITOR, insn_monitor, INSN_CPU0, 39, 0, 0, 0, &monitor_supported}, 896 {"PAUSE", CPU_PAUSE, insn_pause, INSN_CPU0, 40, 0, 0, 0}, 897 // Flags for Secondary Processor-Based VM-Execution Controls 898 {"WBINVD", CPU_WBINVD, insn_wbinvd, INSN_CPU1, 54, 0, 0, 0}, 899 {"DESC_TABLE (SGDT)", CPU_DESC_TABLE, insn_sgdt, INSN_CPU1, 46, 0, 0, 0}, 900 {"DESC_TABLE (LGDT)", CPU_DESC_TABLE, insn_lgdt, INSN_CPU1, 46, 0, 0, 0}, 901 {"DESC_TABLE (SIDT)", CPU_DESC_TABLE, insn_sidt, INSN_CPU1, 46, 0, 0, 0}, 902 {"DESC_TABLE (LIDT)", CPU_DESC_TABLE, insn_lidt, INSN_CPU1, 46, 0, 0, 0}, 903 {"DESC_TABLE (SLDT)", CPU_DESC_TABLE, insn_sldt, INSN_CPU1, 47, 0, 0, 0}, 904 {"DESC_TABLE (LLDT)", CPU_DESC_TABLE, insn_lldt, INSN_CPU1, 47, 0, 0, 0}, 905 {"DESC_TABLE (STR)", CPU_DESC_TABLE, insn_str, INSN_CPU1, 47, 0, 0, 0}, 906 /* LTR causes a #GP if done with a busy selector, so it is not tested. */ 907 {"RDRAND", CPU_RDRAND, insn_rdrand, INSN_CPU1, VMX_RDRAND, 0, 0, 0}, 908 {"RDSEED", CPU_RDSEED, insn_rdseed, INSN_CPU1, VMX_RDSEED, 0, 0, 0}, 909 // Instructions always trap 910 {"CPUID", 0, insn_cpuid, INSN_ALWAYS_TRAP, 10, 0, 0, 0}, 911 {"INVD", 0, insn_invd, INSN_ALWAYS_TRAP, 13, 0, 0, 0}, 912 // Instructions never trap 913 {NULL}, 914 }; 915 916 static int insn_intercept_init(struct vmcs *vmcs) 917 { 918 u32 ctrl_cpu, cur_insn; 919 920 ctrl_cpu = ctrl_cpu_rev[0].set | CPU_SECONDARY; 921 ctrl_cpu &= ctrl_cpu_rev[0].clr; 922 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu); 923 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu_rev[1].set); 924 cr3 = read_cr3(); 925 926 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 927 if (insn_table[cur_insn].supported_fn == NULL) 928 continue; 929 insn_table[cur_insn].disabled = !insn_table[cur_insn].supported_fn(); 930 } 931 return VMX_TEST_START; 932 } 933 934 static void insn_intercept_main(void) 935 { 936 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 937 vmx_set_test_stage(cur_insn * 2); 938 if ((insn_table[cur_insn].type == INSN_CPU0 && 939 !(ctrl_cpu_rev[0].clr & insn_table[cur_insn].flag)) || 940 (insn_table[cur_insn].type == INSN_CPU1 && 941 !(ctrl_cpu_rev[1].clr & insn_table[cur_insn].flag))) { 942 printf("\tCPU_CTRL%d.CPU_%s is not supported.\n", 943 insn_table[cur_insn].type - INSN_CPU0, 944 insn_table[cur_insn].name); 945 continue; 946 } 947 948 if (insn_table[cur_insn].disabled) { 949 printf("\tFeature required for %s is not supported.\n", 950 insn_table[cur_insn].name); 951 continue; 952 } 953 954 if ((insn_table[cur_insn].type == INSN_CPU0 && 955 !(ctrl_cpu_rev[0].set & insn_table[cur_insn].flag)) || 956 (insn_table[cur_insn].type == INSN_CPU1 && 957 !(ctrl_cpu_rev[1].set & insn_table[cur_insn].flag))) { 958 /* skip hlt, it stalls the guest and is tested below */ 959 if (insn_table[cur_insn].insn_func != insn_hlt) 960 insn_table[cur_insn].insn_func(); 961 report("execute %s", vmx_get_test_stage() == cur_insn * 2, 962 insn_table[cur_insn].name); 963 } else if (insn_table[cur_insn].type != INSN_ALWAYS_TRAP) 964 printf("\tCPU_CTRL%d.CPU_%s always traps.\n", 965 insn_table[cur_insn].type - INSN_CPU0, 966 insn_table[cur_insn].name); 967 968 vmcall(); 969 970 insn_table[cur_insn].insn_func(); 971 report("intercept %s", vmx_get_test_stage() == cur_insn * 2 + 1, 972 insn_table[cur_insn].name); 973 974 vmx_set_test_stage(cur_insn * 2 + 1); 975 vmcall(); 976 } 977 } 978 979 static int insn_intercept_exit_handler(void) 980 { 981 u64 guest_rip; 982 u32 reason; 983 ulong exit_qual; 984 u32 insn_len; 985 u32 insn_info; 986 bool pass; 987 988 guest_rip = vmcs_read(GUEST_RIP); 989 reason = vmcs_read(EXI_REASON) & 0xff; 990 exit_qual = vmcs_read(EXI_QUALIFICATION); 991 insn_len = vmcs_read(EXI_INST_LEN); 992 insn_info = vmcs_read(EXI_INST_INFO); 993 994 if (reason == VMX_VMCALL) { 995 u32 val = 0; 996 997 if (insn_table[cur_insn].type == INSN_CPU0) 998 val = vmcs_read(CPU_EXEC_CTRL0); 999 else if (insn_table[cur_insn].type == INSN_CPU1) 1000 val = vmcs_read(CPU_EXEC_CTRL1); 1001 1002 if (vmx_get_test_stage() & 1) 1003 val &= ~insn_table[cur_insn].flag; 1004 else 1005 val |= insn_table[cur_insn].flag; 1006 1007 if (insn_table[cur_insn].type == INSN_CPU0) 1008 vmcs_write(CPU_EXEC_CTRL0, val | ctrl_cpu_rev[0].set); 1009 else if (insn_table[cur_insn].type == INSN_CPU1) 1010 vmcs_write(CPU_EXEC_CTRL1, val | ctrl_cpu_rev[1].set); 1011 } else { 1012 pass = (cur_insn * 2 == vmx_get_test_stage()) && 1013 insn_table[cur_insn].reason == reason; 1014 if (insn_table[cur_insn].test_field & FIELD_EXIT_QUAL && 1015 insn_table[cur_insn].exit_qual != exit_qual) 1016 pass = false; 1017 if (insn_table[cur_insn].test_field & FIELD_INSN_INFO && 1018 insn_table[cur_insn].insn_info != insn_info) 1019 pass = false; 1020 if (pass) 1021 vmx_inc_test_stage(); 1022 } 1023 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1024 return VMX_TEST_RESUME; 1025 } 1026 1027 /** 1028 * __setup_ept - Setup the VMCS fields to enable Extended Page Tables (EPT) 1029 * @hpa: Host physical address of the top-level, a.k.a. root, EPT table 1030 * @enable_ad: Whether or not to enable Access/Dirty bits for EPT entries 1031 * 1032 * Returns 0 on success, 1 on failure. 1033 * 1034 * Note that @hpa doesn't need to point at actual memory if VM-Launch is 1035 * expected to fail, e.g. setup_dummy_ept() arbitrarily passes '0' to satisfy 1036 * the various EPTP consistency checks, but doesn't ensure backing for HPA '0'. 1037 */ 1038 static int __setup_ept(u64 hpa, bool enable_ad) 1039 { 1040 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1041 !(ctrl_cpu_rev[1].clr & CPU_EPT)) { 1042 printf("\tEPT is not supported"); 1043 return 1; 1044 } 1045 if (!(ept_vpid.val & EPT_CAP_WB)) { 1046 printf("WB memtype for EPT walks not supported\n"); 1047 return 1; 1048 } 1049 if (!(ept_vpid.val & EPT_CAP_PWL4)) { 1050 printf("\tPWL4 is not supported\n"); 1051 return 1; 1052 } 1053 1054 eptp = EPT_MEM_TYPE_WB; 1055 eptp |= (3 << EPTP_PG_WALK_LEN_SHIFT); 1056 eptp |= hpa; 1057 if (enable_ad) 1058 eptp |= EPTP_AD_FLAG; 1059 1060 vmcs_write(EPTP, eptp); 1061 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0)| CPU_SECONDARY); 1062 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1)| CPU_EPT); 1063 1064 return 0; 1065 } 1066 1067 /** 1068 * setup_ept - Enable Extended Page Tables (EPT) and setup an identity map 1069 * @enable_ad: Whether or not to enable Access/Dirty bits for EPT entries 1070 * 1071 * Returns 0 on success, 1 on failure. 1072 * 1073 * This is the "real" function for setting up EPT tables, i.e. use this for 1074 * tests that need to run code in the guest with EPT enabled. 1075 */ 1076 static int setup_ept(bool enable_ad) 1077 { 1078 unsigned long end_of_memory; 1079 1080 pml4 = alloc_page(); 1081 1082 if (__setup_ept(virt_to_phys(pml4), enable_ad)) 1083 return 1; 1084 1085 end_of_memory = fwcfg_get_u64(FW_CFG_RAM_SIZE); 1086 if (end_of_memory < (1ul << 32)) 1087 end_of_memory = (1ul << 32); 1088 /* Cannot use large EPT pages if we need to track EPT 1089 * accessed/dirty bits at 4K granularity. 1090 */ 1091 setup_ept_range(pml4, 0, end_of_memory, 0, 1092 !enable_ad && ept_2m_supported(), 1093 EPT_WA | EPT_RA | EPT_EA); 1094 return 0; 1095 } 1096 1097 /** 1098 * setup_dummy_ept - Enable Extended Page Tables (EPT) with a dummy root HPA 1099 * 1100 * Setup EPT using a semi-arbitrary dummy root HPA. This function is intended 1101 * for use by tests that need EPT enabled to verify dependent VMCS controls 1102 * but never expect to fully enter the guest, i.e. don't need setup the actual 1103 * EPT tables. 1104 */ 1105 static void setup_dummy_ept(void) 1106 { 1107 if (__setup_ept(0, false)) 1108 report_abort("EPT setup unexpectedly failed"); 1109 } 1110 1111 static int enable_unrestricted_guest(void) 1112 { 1113 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1114 !(ctrl_cpu_rev[1].clr & CPU_URG) || 1115 !(ctrl_cpu_rev[1].clr & CPU_EPT)) 1116 return 1; 1117 1118 setup_dummy_ept(); 1119 1120 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 1121 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | CPU_URG); 1122 1123 return 0; 1124 } 1125 1126 static void ept_enable_ad_bits(void) 1127 { 1128 eptp |= EPTP_AD_FLAG; 1129 vmcs_write(EPTP, eptp); 1130 } 1131 1132 static void ept_disable_ad_bits(void) 1133 { 1134 eptp &= ~EPTP_AD_FLAG; 1135 vmcs_write(EPTP, eptp); 1136 } 1137 1138 static void ept_enable_ad_bits_or_skip_test(void) 1139 { 1140 if (!ept_ad_bits_supported()) 1141 test_skip("EPT AD bits not supported."); 1142 ept_enable_ad_bits(); 1143 } 1144 1145 static int apic_version; 1146 1147 static int ept_init_common(bool have_ad) 1148 { 1149 int ret; 1150 struct pci_dev pcidev; 1151 1152 if (setup_ept(have_ad)) 1153 return VMX_TEST_EXIT; 1154 data_page1 = alloc_page(); 1155 data_page2 = alloc_page(); 1156 *((u32 *)data_page1) = MAGIC_VAL_1; 1157 *((u32 *)data_page2) = MAGIC_VAL_2; 1158 install_ept(pml4, (unsigned long)data_page1, (unsigned long)data_page2, 1159 EPT_RA | EPT_WA | EPT_EA); 1160 1161 apic_version = apic_read(APIC_LVR); 1162 1163 ret = pci_find_dev(PCI_VENDOR_ID_REDHAT, PCI_DEVICE_ID_REDHAT_TEST); 1164 if (ret != PCIDEVADDR_INVALID) { 1165 pci_dev_init(&pcidev, ret); 1166 pci_physaddr = pcidev.resource[PCI_TESTDEV_BAR_MEM]; 1167 } 1168 1169 return VMX_TEST_START; 1170 } 1171 1172 static int ept_init(struct vmcs *vmcs) 1173 { 1174 return ept_init_common(false); 1175 } 1176 1177 static void ept_common(void) 1178 { 1179 vmx_set_test_stage(0); 1180 if (*((u32 *)data_page2) != MAGIC_VAL_1 || 1181 *((u32 *)data_page1) != MAGIC_VAL_1) 1182 report("EPT basic framework - read", 0); 1183 else { 1184 *((u32 *)data_page2) = MAGIC_VAL_3; 1185 vmcall(); 1186 if (vmx_get_test_stage() == 1) { 1187 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1188 *((u32 *)data_page2) == MAGIC_VAL_2) 1189 report("EPT basic framework", 1); 1190 else 1191 report("EPT basic framework - remap", 1); 1192 } 1193 } 1194 // Test EPT Misconfigurations 1195 vmx_set_test_stage(1); 1196 vmcall(); 1197 *((u32 *)data_page1) = MAGIC_VAL_1; 1198 if (vmx_get_test_stage() != 2) { 1199 report("EPT misconfigurations", 0); 1200 goto t1; 1201 } 1202 vmx_set_test_stage(2); 1203 vmcall(); 1204 *((u32 *)data_page1) = MAGIC_VAL_1; 1205 report("EPT misconfigurations", vmx_get_test_stage() == 3); 1206 t1: 1207 // Test EPT violation 1208 vmx_set_test_stage(3); 1209 vmcall(); 1210 *((u32 *)data_page1) = MAGIC_VAL_1; 1211 report("EPT violation - page permission", vmx_get_test_stage() == 4); 1212 // Violation caused by EPT paging structure 1213 vmx_set_test_stage(4); 1214 vmcall(); 1215 *((u32 *)data_page1) = MAGIC_VAL_2; 1216 report("EPT violation - paging structure", vmx_get_test_stage() == 5); 1217 1218 // MMIO Read/Write 1219 vmx_set_test_stage(5); 1220 vmcall(); 1221 1222 *(u32 volatile *)pci_physaddr; 1223 report("MMIO EPT violation - read", vmx_get_test_stage() == 6); 1224 1225 *(u32 volatile *)pci_physaddr = MAGIC_VAL_1; 1226 report("MMIO EPT violation - write", vmx_get_test_stage() == 7); 1227 } 1228 1229 static void ept_main(void) 1230 { 1231 ept_common(); 1232 1233 // Test EPT access to L1 MMIO 1234 vmx_set_test_stage(7); 1235 report("EPT - MMIO access", *((u32 *)0xfee00030UL) == apic_version); 1236 1237 // Test invalid operand for INVEPT 1238 vmcall(); 1239 report("EPT - unsupported INVEPT", vmx_get_test_stage() == 8); 1240 } 1241 1242 static bool invept_test(int type, u64 eptp) 1243 { 1244 bool ret, supported; 1245 1246 supported = ept_vpid.val & (EPT_CAP_INVEPT_SINGLE >> INVEPT_SINGLE << type); 1247 ret = invept(type, eptp); 1248 1249 if (ret == !supported) 1250 return false; 1251 1252 if (!supported) 1253 printf("WARNING: unsupported invept passed!\n"); 1254 else 1255 printf("WARNING: invept failed!\n"); 1256 1257 return true; 1258 } 1259 1260 static int pml_exit_handler(void) 1261 { 1262 u16 index, count; 1263 ulong reason = vmcs_read(EXI_REASON) & 0xff; 1264 u64 *pmlbuf = pml_log; 1265 u64 guest_rip = vmcs_read(GUEST_RIP);; 1266 u64 guest_cr3 = vmcs_read(GUEST_CR3); 1267 u32 insn_len = vmcs_read(EXI_INST_LEN); 1268 1269 switch (reason) { 1270 case VMX_VMCALL: 1271 switch (vmx_get_test_stage()) { 1272 case 0: 1273 index = vmcs_read(GUEST_PML_INDEX); 1274 for (count = index + 1; count < PML_INDEX; count++) { 1275 if (pmlbuf[count] == (u64)data_page2) { 1276 vmx_inc_test_stage(); 1277 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1278 break; 1279 } 1280 } 1281 break; 1282 case 1: 1283 index = vmcs_read(GUEST_PML_INDEX); 1284 /* Keep clearing the dirty bit till a overflow */ 1285 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1286 break; 1287 default: 1288 report("unexpected stage, %d.", false, 1289 vmx_get_test_stage()); 1290 print_vmexit_info(); 1291 return VMX_TEST_VMEXIT; 1292 } 1293 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1294 return VMX_TEST_RESUME; 1295 case VMX_PML_FULL: 1296 vmx_inc_test_stage(); 1297 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1298 return VMX_TEST_RESUME; 1299 default: 1300 report("Unknown exit reason, %ld", false, reason); 1301 print_vmexit_info(); 1302 } 1303 return VMX_TEST_VMEXIT; 1304 } 1305 1306 static int ept_exit_handler_common(bool have_ad) 1307 { 1308 u64 guest_rip; 1309 u64 guest_cr3; 1310 ulong reason; 1311 u32 insn_len; 1312 u32 exit_qual; 1313 static unsigned long data_page1_pte, data_page1_pte_pte, memaddr_pte; 1314 1315 guest_rip = vmcs_read(GUEST_RIP); 1316 guest_cr3 = vmcs_read(GUEST_CR3); 1317 reason = vmcs_read(EXI_REASON) & 0xff; 1318 insn_len = vmcs_read(EXI_INST_LEN); 1319 exit_qual = vmcs_read(EXI_QUALIFICATION); 1320 switch (reason) { 1321 case VMX_VMCALL: 1322 switch (vmx_get_test_stage()) { 1323 case 0: 1324 check_ept_ad(pml4, guest_cr3, 1325 (unsigned long)data_page1, 1326 have_ad ? EPT_ACCESS_FLAG : 0, 1327 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1328 check_ept_ad(pml4, guest_cr3, 1329 (unsigned long)data_page2, 1330 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0, 1331 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1332 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1333 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1334 if (have_ad) 1335 ept_sync(INVEPT_SINGLE, eptp);; 1336 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1337 *((u32 *)data_page2) == MAGIC_VAL_2) { 1338 vmx_inc_test_stage(); 1339 install_ept(pml4, (unsigned long)data_page2, 1340 (unsigned long)data_page2, 1341 EPT_RA | EPT_WA | EPT_EA); 1342 } else 1343 report("EPT basic framework - write", 0); 1344 break; 1345 case 1: 1346 install_ept(pml4, (unsigned long)data_page1, 1347 (unsigned long)data_page1, EPT_WA); 1348 ept_sync(INVEPT_SINGLE, eptp); 1349 break; 1350 case 2: 1351 install_ept(pml4, (unsigned long)data_page1, 1352 (unsigned long)data_page1, 1353 EPT_RA | EPT_WA | EPT_EA | 1354 (2 << EPT_MEM_TYPE_SHIFT)); 1355 ept_sync(INVEPT_SINGLE, eptp); 1356 break; 1357 case 3: 1358 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1359 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)data_page1, 1360 1, &data_page1_pte)); 1361 set_ept_pte(pml4, (unsigned long)data_page1, 1362 1, data_page1_pte & ~EPT_PRESENT); 1363 ept_sync(INVEPT_SINGLE, eptp); 1364 break; 1365 case 4: 1366 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)data_page1, 1367 2, &data_page1_pte)); 1368 data_page1_pte &= PAGE_MASK; 1369 TEST_ASSERT(get_ept_pte(pml4, data_page1_pte, 1370 2, &data_page1_pte_pte)); 1371 set_ept_pte(pml4, data_page1_pte, 2, 1372 data_page1_pte_pte & ~EPT_PRESENT); 1373 ept_sync(INVEPT_SINGLE, eptp); 1374 break; 1375 case 5: 1376 install_ept(pml4, (unsigned long)pci_physaddr, 1377 (unsigned long)pci_physaddr, 0); 1378 ept_sync(INVEPT_SINGLE, eptp); 1379 break; 1380 case 7: 1381 if (!invept_test(0, eptp)) 1382 vmx_inc_test_stage(); 1383 break; 1384 // Should not reach here 1385 default: 1386 report("ERROR - unexpected stage, %d.", false, 1387 vmx_get_test_stage()); 1388 print_vmexit_info(); 1389 return VMX_TEST_VMEXIT; 1390 } 1391 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1392 return VMX_TEST_RESUME; 1393 case VMX_EPT_MISCONFIG: 1394 switch (vmx_get_test_stage()) { 1395 case 1: 1396 case 2: 1397 vmx_inc_test_stage(); 1398 install_ept(pml4, (unsigned long)data_page1, 1399 (unsigned long)data_page1, 1400 EPT_RA | EPT_WA | EPT_EA); 1401 ept_sync(INVEPT_SINGLE, eptp); 1402 break; 1403 // Should not reach here 1404 default: 1405 report("ERROR - unexpected stage, %d.", false, 1406 vmx_get_test_stage()); 1407 print_vmexit_info(); 1408 return VMX_TEST_VMEXIT; 1409 } 1410 return VMX_TEST_RESUME; 1411 case VMX_EPT_VIOLATION: 1412 switch(vmx_get_test_stage()) { 1413 case 3: 1414 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1415 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1416 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1417 if (exit_qual == (EPT_VLT_WR | EPT_VLT_LADDR_VLD | 1418 EPT_VLT_PADDR)) 1419 vmx_inc_test_stage(); 1420 set_ept_pte(pml4, (unsigned long)data_page1, 1421 1, data_page1_pte | (EPT_PRESENT)); 1422 ept_sync(INVEPT_SINGLE, eptp); 1423 break; 1424 case 4: 1425 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1426 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1427 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1428 if (exit_qual == (EPT_VLT_RD | 1429 (have_ad ? EPT_VLT_WR : 0) | 1430 EPT_VLT_LADDR_VLD)) 1431 vmx_inc_test_stage(); 1432 set_ept_pte(pml4, data_page1_pte, 2, 1433 data_page1_pte_pte | (EPT_PRESENT)); 1434 ept_sync(INVEPT_SINGLE, eptp); 1435 break; 1436 case 5: 1437 if (exit_qual & EPT_VLT_RD) 1438 vmx_inc_test_stage(); 1439 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1440 1, &memaddr_pte)); 1441 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA); 1442 ept_sync(INVEPT_SINGLE, eptp); 1443 break; 1444 case 6: 1445 if (exit_qual & EPT_VLT_WR) 1446 vmx_inc_test_stage(); 1447 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1448 1, &memaddr_pte)); 1449 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA | EPT_WA); 1450 ept_sync(INVEPT_SINGLE, eptp); 1451 break; 1452 default: 1453 // Should not reach here 1454 report("ERROR : unexpected stage, %d", false, 1455 vmx_get_test_stage()); 1456 print_vmexit_info(); 1457 return VMX_TEST_VMEXIT; 1458 } 1459 return VMX_TEST_RESUME; 1460 default: 1461 report("Unknown exit reason, %ld", false, reason); 1462 print_vmexit_info(); 1463 } 1464 return VMX_TEST_VMEXIT; 1465 } 1466 1467 static int ept_exit_handler(void) 1468 { 1469 return ept_exit_handler_common(false); 1470 } 1471 1472 static int eptad_init(struct vmcs *vmcs) 1473 { 1474 int r = ept_init_common(true); 1475 1476 if (r == VMX_TEST_EXIT) 1477 return r; 1478 1479 if ((rdmsr(MSR_IA32_VMX_EPT_VPID_CAP) & EPT_CAP_AD_FLAG) == 0) { 1480 printf("\tEPT A/D bits are not supported"); 1481 return VMX_TEST_EXIT; 1482 } 1483 1484 return r; 1485 } 1486 1487 static int pml_init(struct vmcs *vmcs) 1488 { 1489 u32 ctrl_cpu; 1490 int r = eptad_init(vmcs); 1491 1492 if (r == VMX_TEST_EXIT) 1493 return r; 1494 1495 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1496 !(ctrl_cpu_rev[1].clr & CPU_PML)) { 1497 printf("\tPML is not supported"); 1498 return VMX_TEST_EXIT; 1499 } 1500 1501 pml_log = alloc_page(); 1502 vmcs_write(PMLADDR, (u64)pml_log); 1503 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1504 1505 ctrl_cpu = vmcs_read(CPU_EXEC_CTRL1) | CPU_PML; 1506 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu); 1507 1508 return VMX_TEST_START; 1509 } 1510 1511 static void pml_main(void) 1512 { 1513 int count = 0; 1514 1515 vmx_set_test_stage(0); 1516 *((u32 *)data_page2) = 0x1; 1517 vmcall(); 1518 report("PML - Dirty GPA Logging", vmx_get_test_stage() == 1); 1519 1520 while (vmx_get_test_stage() == 1) { 1521 vmcall(); 1522 *((u32 *)data_page2) = 0x1; 1523 if (count++ > PML_INDEX) 1524 break; 1525 } 1526 report("PML Full Event", vmx_get_test_stage() == 2); 1527 } 1528 1529 static void eptad_main(void) 1530 { 1531 ept_common(); 1532 } 1533 1534 static int eptad_exit_handler(void) 1535 { 1536 return ept_exit_handler_common(true); 1537 } 1538 1539 static bool invvpid_test(int type, u16 vpid) 1540 { 1541 bool ret, supported; 1542 1543 supported = ept_vpid.val & 1544 (VPID_CAP_INVVPID_ADDR >> INVVPID_ADDR << type); 1545 ret = invvpid(type, vpid, 0); 1546 1547 if (ret == !supported) 1548 return false; 1549 1550 if (!supported) 1551 printf("WARNING: unsupported invvpid passed!\n"); 1552 else 1553 printf("WARNING: invvpid failed!\n"); 1554 1555 return true; 1556 } 1557 1558 static int vpid_init(struct vmcs *vmcs) 1559 { 1560 u32 ctrl_cpu1; 1561 1562 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1563 !(ctrl_cpu_rev[1].clr & CPU_VPID)) { 1564 printf("\tVPID is not supported"); 1565 return VMX_TEST_EXIT; 1566 } 1567 1568 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 1569 ctrl_cpu1 |= CPU_VPID; 1570 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 1571 return VMX_TEST_START; 1572 } 1573 1574 static void vpid_main(void) 1575 { 1576 vmx_set_test_stage(0); 1577 vmcall(); 1578 report("INVVPID SINGLE ADDRESS", vmx_get_test_stage() == 1); 1579 vmx_set_test_stage(2); 1580 vmcall(); 1581 report("INVVPID SINGLE", vmx_get_test_stage() == 3); 1582 vmx_set_test_stage(4); 1583 vmcall(); 1584 report("INVVPID ALL", vmx_get_test_stage() == 5); 1585 } 1586 1587 static int vpid_exit_handler(void) 1588 { 1589 u64 guest_rip; 1590 ulong reason; 1591 u32 insn_len; 1592 1593 guest_rip = vmcs_read(GUEST_RIP); 1594 reason = vmcs_read(EXI_REASON) & 0xff; 1595 insn_len = vmcs_read(EXI_INST_LEN); 1596 1597 switch (reason) { 1598 case VMX_VMCALL: 1599 switch(vmx_get_test_stage()) { 1600 case 0: 1601 if (!invvpid_test(INVVPID_ADDR, 1)) 1602 vmx_inc_test_stage(); 1603 break; 1604 case 2: 1605 if (!invvpid_test(INVVPID_CONTEXT_GLOBAL, 1)) 1606 vmx_inc_test_stage(); 1607 break; 1608 case 4: 1609 if (!invvpid_test(INVVPID_ALL, 1)) 1610 vmx_inc_test_stage(); 1611 break; 1612 default: 1613 report("ERROR: unexpected stage, %d", false, 1614 vmx_get_test_stage()); 1615 print_vmexit_info(); 1616 return VMX_TEST_VMEXIT; 1617 } 1618 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1619 return VMX_TEST_RESUME; 1620 default: 1621 report("Unknown exit reason, %ld", false, reason); 1622 print_vmexit_info(); 1623 } 1624 return VMX_TEST_VMEXIT; 1625 } 1626 1627 #define TIMER_VECTOR 222 1628 1629 static volatile bool timer_fired; 1630 1631 static void timer_isr(isr_regs_t *regs) 1632 { 1633 timer_fired = true; 1634 apic_write(APIC_EOI, 0); 1635 } 1636 1637 static int interrupt_init(struct vmcs *vmcs) 1638 { 1639 msr_bmp_init(); 1640 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1641 handle_irq(TIMER_VECTOR, timer_isr); 1642 return VMX_TEST_START; 1643 } 1644 1645 static void interrupt_main(void) 1646 { 1647 long long start, loops; 1648 1649 vmx_set_test_stage(0); 1650 1651 apic_write(APIC_LVTT, TIMER_VECTOR); 1652 irq_enable(); 1653 1654 apic_write(APIC_TMICT, 1); 1655 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1656 asm volatile ("nop"); 1657 report("direct interrupt while running guest", timer_fired); 1658 1659 apic_write(APIC_TMICT, 0); 1660 irq_disable(); 1661 vmcall(); 1662 timer_fired = false; 1663 apic_write(APIC_TMICT, 1); 1664 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1665 asm volatile ("nop"); 1666 report("intercepted interrupt while running guest", timer_fired); 1667 1668 irq_enable(); 1669 apic_write(APIC_TMICT, 0); 1670 irq_disable(); 1671 vmcall(); 1672 timer_fired = false; 1673 start = rdtsc(); 1674 apic_write(APIC_TMICT, 1000000); 1675 1676 asm volatile ("sti; hlt"); 1677 1678 report("direct interrupt + hlt", 1679 rdtsc() - start > 1000000 && timer_fired); 1680 1681 apic_write(APIC_TMICT, 0); 1682 irq_disable(); 1683 vmcall(); 1684 timer_fired = false; 1685 start = rdtsc(); 1686 apic_write(APIC_TMICT, 1000000); 1687 1688 asm volatile ("sti; hlt"); 1689 1690 report("intercepted interrupt + hlt", 1691 rdtsc() - start > 10000 && timer_fired); 1692 1693 apic_write(APIC_TMICT, 0); 1694 irq_disable(); 1695 vmcall(); 1696 timer_fired = false; 1697 start = rdtsc(); 1698 apic_write(APIC_TMICT, 1000000); 1699 1700 irq_enable(); 1701 asm volatile ("nop"); 1702 vmcall(); 1703 1704 report("direct interrupt + activity state hlt", 1705 rdtsc() - start > 10000 && timer_fired); 1706 1707 apic_write(APIC_TMICT, 0); 1708 irq_disable(); 1709 vmcall(); 1710 timer_fired = false; 1711 start = rdtsc(); 1712 apic_write(APIC_TMICT, 1000000); 1713 1714 irq_enable(); 1715 asm volatile ("nop"); 1716 vmcall(); 1717 1718 report("intercepted interrupt + activity state hlt", 1719 rdtsc() - start > 10000 && timer_fired); 1720 1721 apic_write(APIC_TMICT, 0); 1722 irq_disable(); 1723 vmx_set_test_stage(7); 1724 vmcall(); 1725 timer_fired = false; 1726 apic_write(APIC_TMICT, 1); 1727 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1728 asm volatile ("nop"); 1729 report("running a guest with interrupt acknowledgement set", timer_fired); 1730 1731 apic_write(APIC_TMICT, 0); 1732 irq_enable(); 1733 timer_fired = false; 1734 vmcall(); 1735 report("Inject an event to a halted guest", timer_fired); 1736 } 1737 1738 static int interrupt_exit_handler(void) 1739 { 1740 u64 guest_rip = vmcs_read(GUEST_RIP); 1741 ulong reason = vmcs_read(EXI_REASON) & 0xff; 1742 u32 insn_len = vmcs_read(EXI_INST_LEN); 1743 1744 switch (reason) { 1745 case VMX_VMCALL: 1746 switch (vmx_get_test_stage()) { 1747 case 0: 1748 case 2: 1749 case 5: 1750 vmcs_write(PIN_CONTROLS, 1751 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1752 break; 1753 case 7: 1754 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_INTA); 1755 vmcs_write(PIN_CONTROLS, 1756 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1757 break; 1758 case 1: 1759 case 3: 1760 vmcs_write(PIN_CONTROLS, 1761 vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1762 break; 1763 case 4: 1764 case 6: 1765 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1766 break; 1767 1768 case 8: 1769 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1770 vmcs_write(ENT_INTR_INFO, 1771 TIMER_VECTOR | 1772 (VMX_INTR_TYPE_EXT_INTR << INTR_INFO_INTR_TYPE_SHIFT) | 1773 INTR_INFO_VALID_MASK); 1774 break; 1775 } 1776 vmx_inc_test_stage(); 1777 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1778 return VMX_TEST_RESUME; 1779 case VMX_EXTINT: 1780 if (vmcs_read(EXI_CONTROLS) & EXI_INTA) { 1781 int vector = vmcs_read(EXI_INTR_INFO) & 0xff; 1782 handle_external_interrupt(vector); 1783 } else { 1784 irq_enable(); 1785 asm volatile ("nop"); 1786 irq_disable(); 1787 } 1788 if (vmx_get_test_stage() >= 2) 1789 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 1790 return VMX_TEST_RESUME; 1791 default: 1792 report("Unknown exit reason, %ld", false, reason); 1793 print_vmexit_info(); 1794 } 1795 1796 return VMX_TEST_VMEXIT; 1797 } 1798 1799 static int dbgctls_init(struct vmcs *vmcs) 1800 { 1801 u64 dr7 = 0x402; 1802 u64 zero = 0; 1803 1804 msr_bmp_init(); 1805 asm volatile( 1806 "mov %0,%%dr0\n\t" 1807 "mov %0,%%dr1\n\t" 1808 "mov %0,%%dr2\n\t" 1809 "mov %1,%%dr7\n\t" 1810 : : "r" (zero), "r" (dr7)); 1811 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1812 vmcs_write(GUEST_DR7, 0x404); 1813 vmcs_write(GUEST_DEBUGCTL, 0x2); 1814 1815 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 1816 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_SAVE_DBGCTLS); 1817 1818 return VMX_TEST_START; 1819 } 1820 1821 static void dbgctls_main(void) 1822 { 1823 u64 dr7, debugctl; 1824 1825 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1826 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1827 /* Commented out: KVM does not support DEBUGCTL so far */ 1828 (void)debugctl; 1829 report("Load debug controls", dr7 == 0x404 /* && debugctl == 0x2 */); 1830 1831 dr7 = 0x408; 1832 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1833 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1834 1835 vmx_set_test_stage(0); 1836 vmcall(); 1837 report("Save debug controls", vmx_get_test_stage() == 1); 1838 1839 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS || 1840 ctrl_exit_rev.set & EXI_SAVE_DBGCTLS) { 1841 printf("\tDebug controls are always loaded/saved\n"); 1842 return; 1843 } 1844 vmx_set_test_stage(2); 1845 vmcall(); 1846 1847 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1848 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1849 /* Commented out: KVM does not support DEBUGCTL so far */ 1850 (void)debugctl; 1851 report("Guest=host debug controls", dr7 == 0x402 /* && debugctl == 0x1 */); 1852 1853 dr7 = 0x408; 1854 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1855 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1856 1857 vmx_set_test_stage(3); 1858 vmcall(); 1859 report("Don't save debug controls", vmx_get_test_stage() == 4); 1860 } 1861 1862 static int dbgctls_exit_handler(void) 1863 { 1864 unsigned int reason = vmcs_read(EXI_REASON) & 0xff; 1865 u32 insn_len = vmcs_read(EXI_INST_LEN); 1866 u64 guest_rip = vmcs_read(GUEST_RIP); 1867 u64 dr7, debugctl; 1868 1869 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1870 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1871 1872 switch (reason) { 1873 case VMX_VMCALL: 1874 switch (vmx_get_test_stage()) { 1875 case 0: 1876 if (dr7 == 0x400 && debugctl == 0 && 1877 vmcs_read(GUEST_DR7) == 0x408 /* && 1878 Commented out: KVM does not support DEBUGCTL so far 1879 vmcs_read(GUEST_DEBUGCTL) == 0x3 */) 1880 vmx_inc_test_stage(); 1881 break; 1882 case 2: 1883 dr7 = 0x402; 1884 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1885 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1886 vmcs_write(GUEST_DR7, 0x404); 1887 vmcs_write(GUEST_DEBUGCTL, 0x2); 1888 1889 vmcs_write(ENT_CONTROLS, 1890 vmcs_read(ENT_CONTROLS) & ~ENT_LOAD_DBGCTLS); 1891 vmcs_write(EXI_CONTROLS, 1892 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_DBGCTLS); 1893 break; 1894 case 3: 1895 if (dr7 == 0x400 && debugctl == 0 && 1896 vmcs_read(GUEST_DR7) == 0x404 /* && 1897 Commented out: KVM does not support DEBUGCTL so far 1898 vmcs_read(GUEST_DEBUGCTL) == 0x2 */) 1899 vmx_inc_test_stage(); 1900 break; 1901 } 1902 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1903 return VMX_TEST_RESUME; 1904 default: 1905 report("Unknown exit reason, %d", false, reason); 1906 print_vmexit_info(); 1907 } 1908 return VMX_TEST_VMEXIT; 1909 } 1910 1911 struct vmx_msr_entry { 1912 u32 index; 1913 u32 reserved; 1914 u64 value; 1915 } __attribute__((packed)); 1916 1917 #define MSR_MAGIC 0x31415926 1918 struct vmx_msr_entry *exit_msr_store, *entry_msr_load, *exit_msr_load; 1919 1920 static int msr_switch_init(struct vmcs *vmcs) 1921 { 1922 msr_bmp_init(); 1923 exit_msr_store = alloc_page(); 1924 exit_msr_load = alloc_page(); 1925 entry_msr_load = alloc_page(); 1926 entry_msr_load[0].index = MSR_KERNEL_GS_BASE; 1927 entry_msr_load[0].value = MSR_MAGIC; 1928 1929 vmx_set_test_stage(1); 1930 vmcs_write(ENT_MSR_LD_CNT, 1); 1931 vmcs_write(ENTER_MSR_LD_ADDR, (u64)entry_msr_load); 1932 vmcs_write(EXI_MSR_ST_CNT, 1); 1933 vmcs_write(EXIT_MSR_ST_ADDR, (u64)exit_msr_store); 1934 vmcs_write(EXI_MSR_LD_CNT, 1); 1935 vmcs_write(EXIT_MSR_LD_ADDR, (u64)exit_msr_load); 1936 return VMX_TEST_START; 1937 } 1938 1939 static void msr_switch_main(void) 1940 { 1941 if (vmx_get_test_stage() == 1) { 1942 report("VM entry MSR load", 1943 rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC); 1944 vmx_set_test_stage(2); 1945 wrmsr(MSR_KERNEL_GS_BASE, MSR_MAGIC + 1); 1946 exit_msr_store[0].index = MSR_KERNEL_GS_BASE; 1947 exit_msr_load[0].index = MSR_KERNEL_GS_BASE; 1948 exit_msr_load[0].value = MSR_MAGIC + 2; 1949 } 1950 vmcall(); 1951 } 1952 1953 static int msr_switch_exit_handler(void) 1954 { 1955 ulong reason; 1956 1957 reason = vmcs_read(EXI_REASON); 1958 if (reason == VMX_VMCALL && vmx_get_test_stage() == 2) { 1959 report("VM exit MSR store", 1960 exit_msr_store[0].value == MSR_MAGIC + 1); 1961 report("VM exit MSR load", 1962 rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC + 2); 1963 vmx_set_test_stage(3); 1964 entry_msr_load[0].index = MSR_FS_BASE; 1965 return VMX_TEST_RESUME; 1966 } 1967 printf("ERROR %s: unexpected stage=%u or reason=%lu\n", 1968 __func__, vmx_get_test_stage(), reason); 1969 return VMX_TEST_EXIT; 1970 } 1971 1972 static int msr_switch_entry_failure(struct vmentry_failure *failure) 1973 { 1974 ulong reason; 1975 1976 if (failure->early) { 1977 printf("ERROR %s: early exit\n", __func__); 1978 return VMX_TEST_EXIT; 1979 } 1980 1981 reason = vmcs_read(EXI_REASON); 1982 if (reason == (VMX_ENTRY_FAILURE | VMX_FAIL_MSR) && 1983 vmx_get_test_stage() == 3) { 1984 report("VM entry MSR load: try to load FS_BASE", 1985 vmcs_read(EXI_QUALIFICATION) == 1); 1986 return VMX_TEST_VMEXIT; 1987 } 1988 printf("ERROR %s: unexpected stage=%u or reason=%lu\n", 1989 __func__, vmx_get_test_stage(), reason); 1990 return VMX_TEST_EXIT; 1991 } 1992 1993 static int vmmcall_init(struct vmcs *vmcs) 1994 { 1995 vmcs_write(EXC_BITMAP, 1 << UD_VECTOR); 1996 return VMX_TEST_START; 1997 } 1998 1999 static void vmmcall_main(void) 2000 { 2001 asm volatile( 2002 "mov $0xABCD, %%rax\n\t" 2003 "vmmcall\n\t" 2004 ::: "rax"); 2005 2006 report("VMMCALL", 0); 2007 } 2008 2009 static int vmmcall_exit_handler(void) 2010 { 2011 ulong reason; 2012 2013 reason = vmcs_read(EXI_REASON); 2014 switch (reason) { 2015 case VMX_VMCALL: 2016 printf("here\n"); 2017 report("VMMCALL triggers #UD", 0); 2018 break; 2019 case VMX_EXC_NMI: 2020 report("VMMCALL triggers #UD", 2021 (vmcs_read(EXI_INTR_INFO) & 0xff) == UD_VECTOR); 2022 break; 2023 default: 2024 report("Unknown exit reason, %ld", false, reason); 2025 print_vmexit_info(); 2026 } 2027 2028 return VMX_TEST_VMEXIT; 2029 } 2030 2031 static int disable_rdtscp_init(struct vmcs *vmcs) 2032 { 2033 u32 ctrl_cpu1; 2034 2035 if (ctrl_cpu_rev[0].clr & CPU_SECONDARY) { 2036 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 2037 ctrl_cpu1 &= ~CPU_RDTSCP; 2038 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 2039 } 2040 2041 return VMX_TEST_START; 2042 } 2043 2044 static void disable_rdtscp_ud_handler(struct ex_regs *regs) 2045 { 2046 switch (vmx_get_test_stage()) { 2047 case 0: 2048 report("RDTSCP triggers #UD", true); 2049 vmx_inc_test_stage(); 2050 regs->rip += 3; 2051 break; 2052 case 2: 2053 report("RDPID triggers #UD", true); 2054 vmx_inc_test_stage(); 2055 regs->rip += 4; 2056 break; 2057 } 2058 return; 2059 2060 } 2061 2062 static void disable_rdtscp_main(void) 2063 { 2064 /* Test that #UD is properly injected in L2. */ 2065 handle_exception(UD_VECTOR, disable_rdtscp_ud_handler); 2066 2067 vmx_set_test_stage(0); 2068 asm volatile("rdtscp" : : : "eax", "ecx", "edx"); 2069 vmcall(); 2070 asm volatile(".byte 0xf3, 0x0f, 0xc7, 0xf8" : : : "eax"); 2071 2072 handle_exception(UD_VECTOR, 0); 2073 vmcall(); 2074 } 2075 2076 static int disable_rdtscp_exit_handler(void) 2077 { 2078 unsigned int reason = vmcs_read(EXI_REASON) & 0xff; 2079 2080 switch (reason) { 2081 case VMX_VMCALL: 2082 switch (vmx_get_test_stage()) { 2083 case 0: 2084 report("RDTSCP triggers #UD", false); 2085 vmx_inc_test_stage(); 2086 /* fallthrough */ 2087 case 1: 2088 vmx_inc_test_stage(); 2089 vmcs_write(GUEST_RIP, vmcs_read(GUEST_RIP) + 3); 2090 return VMX_TEST_RESUME; 2091 case 2: 2092 report("RDPID triggers #UD", false); 2093 break; 2094 } 2095 break; 2096 2097 default: 2098 report("Unknown exit reason, %d", false, reason); 2099 print_vmexit_info(); 2100 } 2101 return VMX_TEST_VMEXIT; 2102 } 2103 2104 static int int3_init(struct vmcs *vmcs) 2105 { 2106 vmcs_write(EXC_BITMAP, ~0u); 2107 return VMX_TEST_START; 2108 } 2109 2110 static void int3_guest_main(void) 2111 { 2112 asm volatile ("int3"); 2113 } 2114 2115 static int int3_exit_handler(void) 2116 { 2117 u32 reason = vmcs_read(EXI_REASON); 2118 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2119 2120 report("L1 intercepts #BP", reason == VMX_EXC_NMI && 2121 (intr_info & INTR_INFO_VALID_MASK) && 2122 (intr_info & INTR_INFO_VECTOR_MASK) == BP_VECTOR && 2123 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2124 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION); 2125 2126 return VMX_TEST_VMEXIT; 2127 } 2128 2129 static int into_init(struct vmcs *vmcs) 2130 { 2131 vmcs_write(EXC_BITMAP, ~0u); 2132 return VMX_TEST_START; 2133 } 2134 2135 static void into_guest_main(void) 2136 { 2137 struct far_pointer32 fp = { 2138 .offset = (uintptr_t)&&into, 2139 .selector = KERNEL_CS32, 2140 }; 2141 register uintptr_t rsp asm("rsp"); 2142 2143 if (fp.offset != (uintptr_t)&&into) { 2144 printf("Code address too high.\n"); 2145 return; 2146 } 2147 if ((u32)rsp != rsp) { 2148 printf("Stack address too high.\n"); 2149 return; 2150 } 2151 2152 asm goto ("lcall *%0" : : "m" (fp) : "rax" : into); 2153 return; 2154 into: 2155 asm volatile (".code32;" 2156 "movl $0x7fffffff, %eax;" 2157 "addl %eax, %eax;" 2158 "into;" 2159 "lret;" 2160 ".code64"); 2161 __builtin_unreachable(); 2162 } 2163 2164 static int into_exit_handler(void) 2165 { 2166 u32 reason = vmcs_read(EXI_REASON); 2167 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2168 2169 report("L1 intercepts #OF", reason == VMX_EXC_NMI && 2170 (intr_info & INTR_INFO_VALID_MASK) && 2171 (intr_info & INTR_INFO_VECTOR_MASK) == OF_VECTOR && 2172 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2173 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION); 2174 2175 return VMX_TEST_VMEXIT; 2176 } 2177 2178 static void exit_monitor_from_l2_main(void) 2179 { 2180 printf("Calling exit(0) from l2...\n"); 2181 exit(0); 2182 } 2183 2184 static int exit_monitor_from_l2_handler(void) 2185 { 2186 report("The guest should have killed the VMM", false); 2187 return VMX_TEST_EXIT; 2188 } 2189 2190 static void assert_exit_reason(u64 expected) 2191 { 2192 u64 actual = vmcs_read(EXI_REASON); 2193 2194 TEST_ASSERT_EQ_MSG(expected, actual, "Expected %s, got %s.", 2195 exit_reason_description(expected), 2196 exit_reason_description(actual)); 2197 } 2198 2199 static void skip_exit_insn(void) 2200 { 2201 u64 guest_rip = vmcs_read(GUEST_RIP); 2202 u32 insn_len = vmcs_read(EXI_INST_LEN); 2203 vmcs_write(GUEST_RIP, guest_rip + insn_len); 2204 } 2205 2206 static void skip_exit_vmcall(void) 2207 { 2208 assert_exit_reason(VMX_VMCALL); 2209 skip_exit_insn(); 2210 } 2211 2212 static void v2_null_test_guest(void) 2213 { 2214 } 2215 2216 static void v2_null_test(void) 2217 { 2218 test_set_guest(v2_null_test_guest); 2219 enter_guest(); 2220 report(__func__, 1); 2221 } 2222 2223 static void v2_multiple_entries_test_guest(void) 2224 { 2225 vmx_set_test_stage(1); 2226 vmcall(); 2227 vmx_set_test_stage(2); 2228 } 2229 2230 static void v2_multiple_entries_test(void) 2231 { 2232 test_set_guest(v2_multiple_entries_test_guest); 2233 enter_guest(); 2234 TEST_ASSERT_EQ(vmx_get_test_stage(), 1); 2235 skip_exit_vmcall(); 2236 enter_guest(); 2237 TEST_ASSERT_EQ(vmx_get_test_stage(), 2); 2238 report(__func__, 1); 2239 } 2240 2241 static int fixture_test_data = 1; 2242 2243 static void fixture_test_teardown(void *data) 2244 { 2245 *((int *) data) = 1; 2246 } 2247 2248 static void fixture_test_guest(void) 2249 { 2250 fixture_test_data++; 2251 } 2252 2253 2254 static void fixture_test_setup(void) 2255 { 2256 TEST_ASSERT_EQ_MSG(1, fixture_test_data, 2257 "fixture_test_teardown didn't run?!"); 2258 fixture_test_data = 2; 2259 test_add_teardown(fixture_test_teardown, &fixture_test_data); 2260 test_set_guest(fixture_test_guest); 2261 } 2262 2263 static void fixture_test_case1(void) 2264 { 2265 fixture_test_setup(); 2266 TEST_ASSERT_EQ(2, fixture_test_data); 2267 enter_guest(); 2268 TEST_ASSERT_EQ(3, fixture_test_data); 2269 report(__func__, 1); 2270 } 2271 2272 static void fixture_test_case2(void) 2273 { 2274 fixture_test_setup(); 2275 TEST_ASSERT_EQ(2, fixture_test_data); 2276 enter_guest(); 2277 TEST_ASSERT_EQ(3, fixture_test_data); 2278 report(__func__, 1); 2279 } 2280 2281 enum ept_access_op { 2282 OP_READ, 2283 OP_WRITE, 2284 OP_EXEC, 2285 OP_FLUSH_TLB, 2286 OP_EXIT, 2287 }; 2288 2289 static struct ept_access_test_data { 2290 unsigned long gpa; 2291 unsigned long *gva; 2292 unsigned long hpa; 2293 unsigned long *hva; 2294 enum ept_access_op op; 2295 } ept_access_test_data; 2296 2297 extern unsigned char ret42_start; 2298 extern unsigned char ret42_end; 2299 2300 /* Returns 42. */ 2301 asm( 2302 ".align 64\n" 2303 "ret42_start:\n" 2304 "mov $42, %eax\n" 2305 "ret\n" 2306 "ret42_end:\n" 2307 ); 2308 2309 static void 2310 diagnose_ept_violation_qual(u64 expected, u64 actual) 2311 { 2312 2313 #define DIAGNOSE(flag) \ 2314 do { \ 2315 if ((expected & flag) != (actual & flag)) \ 2316 printf(#flag " %sexpected\n", \ 2317 (expected & flag) ? "" : "un"); \ 2318 } while (0) 2319 2320 DIAGNOSE(EPT_VLT_RD); 2321 DIAGNOSE(EPT_VLT_WR); 2322 DIAGNOSE(EPT_VLT_FETCH); 2323 DIAGNOSE(EPT_VLT_PERM_RD); 2324 DIAGNOSE(EPT_VLT_PERM_WR); 2325 DIAGNOSE(EPT_VLT_PERM_EX); 2326 DIAGNOSE(EPT_VLT_LADDR_VLD); 2327 DIAGNOSE(EPT_VLT_PADDR); 2328 2329 #undef DIAGNOSE 2330 } 2331 2332 static void do_ept_access_op(enum ept_access_op op) 2333 { 2334 ept_access_test_data.op = op; 2335 enter_guest(); 2336 } 2337 2338 /* 2339 * Force the guest to flush its TLB (i.e., flush gva -> gpa mappings). Only 2340 * needed by tests that modify guest PTEs. 2341 */ 2342 static void ept_access_test_guest_flush_tlb(void) 2343 { 2344 do_ept_access_op(OP_FLUSH_TLB); 2345 skip_exit_vmcall(); 2346 } 2347 2348 /* 2349 * Modifies the EPT entry at @level in the mapping of @gpa. First clears the 2350 * bits in @clear then sets the bits in @set. @mkhuge transforms the entry into 2351 * a huge page. 2352 */ 2353 static unsigned long ept_twiddle(unsigned long gpa, bool mkhuge, int level, 2354 unsigned long clear, unsigned long set) 2355 { 2356 struct ept_access_test_data *data = &ept_access_test_data; 2357 unsigned long orig_pte; 2358 unsigned long pte; 2359 2360 /* Screw with the mapping at the requested level. */ 2361 TEST_ASSERT(get_ept_pte(pml4, gpa, level, &orig_pte)); 2362 pte = orig_pte; 2363 if (mkhuge) 2364 pte = (orig_pte & ~EPT_ADDR_MASK) | data->hpa | EPT_LARGE_PAGE; 2365 else 2366 pte = orig_pte; 2367 pte = (pte & ~clear) | set; 2368 set_ept_pte(pml4, gpa, level, pte); 2369 ept_sync(INVEPT_SINGLE, eptp); 2370 2371 return orig_pte; 2372 } 2373 2374 static void ept_untwiddle(unsigned long gpa, int level, unsigned long orig_pte) 2375 { 2376 set_ept_pte(pml4, gpa, level, orig_pte); 2377 ept_sync(INVEPT_SINGLE, eptp); 2378 } 2379 2380 static void do_ept_violation(bool leaf, enum ept_access_op op, 2381 u64 expected_qual, u64 expected_paddr) 2382 { 2383 u64 qual; 2384 2385 /* Try the access and observe the violation. */ 2386 do_ept_access_op(op); 2387 2388 assert_exit_reason(VMX_EPT_VIOLATION); 2389 2390 qual = vmcs_read(EXI_QUALIFICATION); 2391 2392 /* Mask undefined bits (which may later be defined in certain cases). */ 2393 qual &= ~(EPT_VLT_GUEST_USER | EPT_VLT_GUEST_RW | EPT_VLT_GUEST_EX | 2394 EPT_VLT_PERM_USER_EX); 2395 2396 diagnose_ept_violation_qual(expected_qual, qual); 2397 TEST_EXPECT_EQ(expected_qual, qual); 2398 2399 #if 0 2400 /* Disable for now otherwise every test will fail */ 2401 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2402 (unsigned long) ( 2403 op == OP_EXEC ? data->gva + 1 : data->gva)); 2404 #endif 2405 /* 2406 * TODO: tests that probe expected_paddr in pages other than the one at 2407 * the beginning of the 1g region. 2408 */ 2409 TEST_EXPECT_EQ(vmcs_read(INFO_PHYS_ADDR), expected_paddr); 2410 } 2411 2412 static void 2413 ept_violation_at_level_mkhuge(bool mkhuge, int level, unsigned long clear, 2414 unsigned long set, enum ept_access_op op, 2415 u64 expected_qual) 2416 { 2417 struct ept_access_test_data *data = &ept_access_test_data; 2418 unsigned long orig_pte; 2419 2420 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2421 2422 do_ept_violation(level == 1 || mkhuge, op, expected_qual, 2423 op == OP_EXEC ? data->gpa + sizeof(unsigned long) : 2424 data->gpa); 2425 2426 /* Fix the violation and resume the op loop. */ 2427 ept_untwiddle(data->gpa, level, orig_pte); 2428 enter_guest(); 2429 skip_exit_vmcall(); 2430 } 2431 2432 static void 2433 ept_violation_at_level(int level, unsigned long clear, unsigned long set, 2434 enum ept_access_op op, u64 expected_qual) 2435 { 2436 ept_violation_at_level_mkhuge(false, level, clear, set, op, 2437 expected_qual); 2438 if (ept_huge_pages_supported(level)) 2439 ept_violation_at_level_mkhuge(true, level, clear, set, op, 2440 expected_qual); 2441 } 2442 2443 static void ept_violation(unsigned long clear, unsigned long set, 2444 enum ept_access_op op, u64 expected_qual) 2445 { 2446 ept_violation_at_level(1, clear, set, op, expected_qual); 2447 ept_violation_at_level(2, clear, set, op, expected_qual); 2448 ept_violation_at_level(3, clear, set, op, expected_qual); 2449 ept_violation_at_level(4, clear, set, op, expected_qual); 2450 } 2451 2452 static void ept_access_violation(unsigned long access, enum ept_access_op op, 2453 u64 expected_qual) 2454 { 2455 ept_violation(EPT_PRESENT, access, op, 2456 expected_qual | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2457 } 2458 2459 /* 2460 * For translations that don't involve a GVA, that is physical address (paddr) 2461 * accesses, EPT violations don't set the flag EPT_VLT_PADDR. For a typical 2462 * guest memory access, the hardware does GVA -> GPA -> HPA. However, certain 2463 * translations don't involve GVAs, such as when the hardware does the guest 2464 * page table walk. For example, in translating GVA_1 -> GPA_1, the guest MMU 2465 * might try to set an A bit on a guest PTE. If the GPA_2 that the PTE resides 2466 * on isn't present in the EPT, then the EPT violation will be for GPA_2 and 2467 * the EPT_VLT_PADDR bit will be clear in the exit qualification. 2468 * 2469 * Note that paddr violations can also be triggered by loading PAE page tables 2470 * with wonky addresses. We don't test that yet. 2471 * 2472 * This function modifies the EPT entry that maps the GPA that the guest page 2473 * table entry mapping ept_access_test_data.gva resides on. 2474 * 2475 * @ept_access EPT permissions to set. Other permissions are cleared. 2476 * 2477 * @pte_ad Set the A/D bits on the guest PTE accordingly. 2478 * 2479 * @op Guest operation to perform with 2480 * ept_access_test_data.gva. 2481 * 2482 * @expect_violation 2483 * Is a violation expected during the paddr access? 2484 * 2485 * @expected_qual Expected qualification for the EPT violation. 2486 * EPT_VLT_PADDR should be clear. 2487 */ 2488 static void ept_access_paddr(unsigned long ept_access, unsigned long pte_ad, 2489 enum ept_access_op op, bool expect_violation, 2490 u64 expected_qual) 2491 { 2492 struct ept_access_test_data *data = &ept_access_test_data; 2493 unsigned long *ptep; 2494 unsigned long gpa; 2495 unsigned long orig_epte; 2496 2497 /* Modify the guest PTE mapping data->gva according to @pte_ad. */ 2498 ptep = get_pte_level(current_page_table(), data->gva, /*level=*/1); 2499 TEST_ASSERT(ptep); 2500 TEST_ASSERT_EQ(*ptep & PT_ADDR_MASK, data->gpa); 2501 *ptep = (*ptep & ~PT_AD_MASK) | pte_ad; 2502 ept_access_test_guest_flush_tlb(); 2503 2504 /* 2505 * Now modify the access bits on the EPT entry for the GPA that the 2506 * guest PTE resides on. Note that by modifying a single EPT entry, 2507 * we're potentially affecting 512 guest PTEs. However, we've carefully 2508 * constructed our test such that those other 511 PTEs aren't used by 2509 * the guest: data->gva is at the beginning of a 1G huge page, thus the 2510 * PTE we're modifying is at the beginning of a 4K page and the 2511 * following 511 entires are also under our control (and not touched by 2512 * the guest). 2513 */ 2514 gpa = virt_to_phys(ptep); 2515 TEST_ASSERT_EQ(gpa & ~PAGE_MASK, 0); 2516 /* 2517 * Make sure the guest page table page is mapped with a 4K EPT entry, 2518 * otherwise our level=1 twiddling below will fail. We use the 2519 * identity map (gpa = gpa) since page tables are shared with the host. 2520 */ 2521 install_ept(pml4, gpa, gpa, EPT_PRESENT); 2522 orig_epte = ept_twiddle(gpa, /*mkhuge=*/0, /*level=*/1, 2523 /*clear=*/EPT_PRESENT, /*set=*/ept_access); 2524 2525 if (expect_violation) { 2526 do_ept_violation(/*leaf=*/true, op, 2527 expected_qual | EPT_VLT_LADDR_VLD, gpa); 2528 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2529 do_ept_access_op(op); 2530 } else { 2531 do_ept_access_op(op); 2532 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2533 } 2534 2535 TEST_ASSERT(*ptep & PT_ACCESSED_MASK); 2536 if ((pte_ad & PT_DIRTY_MASK) || op == OP_WRITE) 2537 TEST_ASSERT(*ptep & PT_DIRTY_MASK); 2538 2539 skip_exit_vmcall(); 2540 } 2541 2542 static void ept_access_allowed_paddr(unsigned long ept_access, 2543 unsigned long pte_ad, 2544 enum ept_access_op op) 2545 { 2546 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/false, 2547 /*expected_qual=*/-1); 2548 } 2549 2550 static void ept_access_violation_paddr(unsigned long ept_access, 2551 unsigned long pte_ad, 2552 enum ept_access_op op, 2553 u64 expected_qual) 2554 { 2555 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/true, 2556 expected_qual); 2557 } 2558 2559 2560 static void ept_allowed_at_level_mkhuge(bool mkhuge, int level, 2561 unsigned long clear, 2562 unsigned long set, 2563 enum ept_access_op op) 2564 { 2565 struct ept_access_test_data *data = &ept_access_test_data; 2566 unsigned long orig_pte; 2567 2568 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2569 2570 /* No violation. Should proceed to vmcall. */ 2571 do_ept_access_op(op); 2572 skip_exit_vmcall(); 2573 2574 ept_untwiddle(data->gpa, level, orig_pte); 2575 } 2576 2577 static void ept_allowed_at_level(int level, unsigned long clear, 2578 unsigned long set, enum ept_access_op op) 2579 { 2580 ept_allowed_at_level_mkhuge(false, level, clear, set, op); 2581 if (ept_huge_pages_supported(level)) 2582 ept_allowed_at_level_mkhuge(true, level, clear, set, op); 2583 } 2584 2585 static void ept_allowed(unsigned long clear, unsigned long set, 2586 enum ept_access_op op) 2587 { 2588 ept_allowed_at_level(1, clear, set, op); 2589 ept_allowed_at_level(2, clear, set, op); 2590 ept_allowed_at_level(3, clear, set, op); 2591 ept_allowed_at_level(4, clear, set, op); 2592 } 2593 2594 static void ept_ignored_bit(int bit) 2595 { 2596 /* Set the bit. */ 2597 ept_allowed(0, 1ul << bit, OP_READ); 2598 ept_allowed(0, 1ul << bit, OP_WRITE); 2599 ept_allowed(0, 1ul << bit, OP_EXEC); 2600 2601 /* Clear the bit. */ 2602 ept_allowed(1ul << bit, 0, OP_READ); 2603 ept_allowed(1ul << bit, 0, OP_WRITE); 2604 ept_allowed(1ul << bit, 0, OP_EXEC); 2605 } 2606 2607 static void ept_access_allowed(unsigned long access, enum ept_access_op op) 2608 { 2609 ept_allowed(EPT_PRESENT, access, op); 2610 } 2611 2612 2613 static void ept_misconfig_at_level_mkhuge_op(bool mkhuge, int level, 2614 unsigned long clear, 2615 unsigned long set, 2616 enum ept_access_op op) 2617 { 2618 struct ept_access_test_data *data = &ept_access_test_data; 2619 unsigned long orig_pte; 2620 2621 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2622 2623 do_ept_access_op(op); 2624 assert_exit_reason(VMX_EPT_MISCONFIG); 2625 2626 /* Intel 27.2.1, "For all other VM exits, this field is cleared." */ 2627 #if 0 2628 /* broken: */ 2629 TEST_EXPECT_EQ_MSG(vmcs_read(EXI_QUALIFICATION), 0); 2630 #endif 2631 #if 0 2632 /* 2633 * broken: 2634 * According to description of exit qual for EPT violation, 2635 * EPT_VLT_LADDR_VLD indicates if GUEST_LINEAR_ADDRESS is valid. 2636 * However, I can't find anything that says GUEST_LINEAR_ADDRESS ought 2637 * to be set for msiconfig. 2638 */ 2639 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2640 (unsigned long) ( 2641 op == OP_EXEC ? data->gva + 1 : data->gva)); 2642 #endif 2643 2644 /* Fix the violation and resume the op loop. */ 2645 ept_untwiddle(data->gpa, level, orig_pte); 2646 enter_guest(); 2647 skip_exit_vmcall(); 2648 } 2649 2650 static void ept_misconfig_at_level_mkhuge(bool mkhuge, int level, 2651 unsigned long clear, 2652 unsigned long set) 2653 { 2654 /* The op shouldn't matter (read, write, exec), so try them all! */ 2655 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_READ); 2656 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_WRITE); 2657 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_EXEC); 2658 } 2659 2660 static void ept_misconfig_at_level(int level, unsigned long clear, 2661 unsigned long set) 2662 { 2663 ept_misconfig_at_level_mkhuge(false, level, clear, set); 2664 if (ept_huge_pages_supported(level)) 2665 ept_misconfig_at_level_mkhuge(true, level, clear, set); 2666 } 2667 2668 static void ept_misconfig(unsigned long clear, unsigned long set) 2669 { 2670 ept_misconfig_at_level(1, clear, set); 2671 ept_misconfig_at_level(2, clear, set); 2672 ept_misconfig_at_level(3, clear, set); 2673 ept_misconfig_at_level(4, clear, set); 2674 } 2675 2676 static void ept_access_misconfig(unsigned long access) 2677 { 2678 ept_misconfig(EPT_PRESENT, access); 2679 } 2680 2681 static void ept_reserved_bit_at_level_nohuge(int level, int bit) 2682 { 2683 /* Setting the bit causes a misconfig. */ 2684 ept_misconfig_at_level_mkhuge(false, level, 0, 1ul << bit); 2685 2686 /* Making the entry non-present turns reserved bits into ignored. */ 2687 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2688 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2689 } 2690 2691 static void ept_reserved_bit_at_level_huge(int level, int bit) 2692 { 2693 /* Setting the bit causes a misconfig. */ 2694 ept_misconfig_at_level_mkhuge(true, level, 0, 1ul << bit); 2695 2696 /* Making the entry non-present turns reserved bits into ignored. */ 2697 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2698 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2699 } 2700 2701 static void ept_reserved_bit_at_level(int level, int bit) 2702 { 2703 /* Setting the bit causes a misconfig. */ 2704 ept_misconfig_at_level(level, 0, 1ul << bit); 2705 2706 /* Making the entry non-present turns reserved bits into ignored. */ 2707 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2708 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2709 } 2710 2711 static void ept_reserved_bit(int bit) 2712 { 2713 ept_reserved_bit_at_level(1, bit); 2714 ept_reserved_bit_at_level(2, bit); 2715 ept_reserved_bit_at_level(3, bit); 2716 ept_reserved_bit_at_level(4, bit); 2717 } 2718 2719 #define PAGE_2M_ORDER 9 2720 #define PAGE_1G_ORDER 18 2721 2722 static void *get_1g_page(void) 2723 { 2724 static void *alloc; 2725 2726 if (!alloc) 2727 alloc = alloc_pages(PAGE_1G_ORDER); 2728 return alloc; 2729 } 2730 2731 static void ept_access_test_teardown(void *unused) 2732 { 2733 /* Exit the guest cleanly. */ 2734 do_ept_access_op(OP_EXIT); 2735 } 2736 2737 static void ept_access_test_guest(void) 2738 { 2739 struct ept_access_test_data *data = &ept_access_test_data; 2740 int (*code)(void) = (int (*)(void)) &data->gva[1]; 2741 2742 while (true) { 2743 switch (data->op) { 2744 case OP_READ: 2745 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_1); 2746 break; 2747 case OP_WRITE: 2748 *data->gva = MAGIC_VAL_2; 2749 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_2); 2750 *data->gva = MAGIC_VAL_1; 2751 break; 2752 case OP_EXEC: 2753 TEST_ASSERT_EQ(42, code()); 2754 break; 2755 case OP_FLUSH_TLB: 2756 write_cr3(read_cr3()); 2757 break; 2758 case OP_EXIT: 2759 return; 2760 default: 2761 TEST_ASSERT_MSG(false, "Unknown op %d", data->op); 2762 } 2763 vmcall(); 2764 } 2765 } 2766 2767 static void ept_access_test_setup(void) 2768 { 2769 struct ept_access_test_data *data = &ept_access_test_data; 2770 unsigned long npages = 1ul << PAGE_1G_ORDER; 2771 unsigned long size = npages * PAGE_SIZE; 2772 unsigned long *page_table = current_page_table(); 2773 unsigned long pte; 2774 2775 if (setup_ept(false)) 2776 test_skip("EPT not supported"); 2777 2778 /* We use data->gpa = 1 << 39 so that test data has a separate pml4 entry */ 2779 if (cpuid_maxphyaddr() < 40) 2780 test_skip("Test needs MAXPHYADDR >= 40"); 2781 2782 test_set_guest(ept_access_test_guest); 2783 test_add_teardown(ept_access_test_teardown, NULL); 2784 2785 data->hva = get_1g_page(); 2786 TEST_ASSERT(data->hva); 2787 data->hpa = virt_to_phys(data->hva); 2788 2789 data->gpa = 1ul << 39; 2790 data->gva = (void *) ALIGN((unsigned long) alloc_vpages(npages * 2), 2791 size); 2792 TEST_ASSERT(!any_present_pages(page_table, data->gva, size)); 2793 install_pages(page_table, data->gpa, size, data->gva); 2794 2795 /* 2796 * Make sure nothing's mapped here so the tests that screw with the 2797 * pml4 entry don't inadvertently break something. 2798 */ 2799 TEST_ASSERT(get_ept_pte(pml4, data->gpa, 4, &pte) && pte == 0); 2800 TEST_ASSERT(get_ept_pte(pml4, data->gpa + size - 1, 4, &pte) && pte == 0); 2801 install_ept(pml4, data->hpa, data->gpa, EPT_PRESENT); 2802 2803 data->hva[0] = MAGIC_VAL_1; 2804 memcpy(&data->hva[1], &ret42_start, &ret42_end - &ret42_start); 2805 } 2806 2807 static void ept_access_test_not_present(void) 2808 { 2809 ept_access_test_setup(); 2810 /* --- */ 2811 ept_access_violation(0, OP_READ, EPT_VLT_RD); 2812 ept_access_violation(0, OP_WRITE, EPT_VLT_WR); 2813 ept_access_violation(0, OP_EXEC, EPT_VLT_FETCH); 2814 } 2815 2816 static void ept_access_test_read_only(void) 2817 { 2818 ept_access_test_setup(); 2819 2820 /* r-- */ 2821 ept_access_allowed(EPT_RA, OP_READ); 2822 ept_access_violation(EPT_RA, OP_WRITE, EPT_VLT_WR | EPT_VLT_PERM_RD); 2823 ept_access_violation(EPT_RA, OP_EXEC, EPT_VLT_FETCH | EPT_VLT_PERM_RD); 2824 } 2825 2826 static void ept_access_test_write_only(void) 2827 { 2828 ept_access_test_setup(); 2829 /* -w- */ 2830 ept_access_misconfig(EPT_WA); 2831 } 2832 2833 static void ept_access_test_read_write(void) 2834 { 2835 ept_access_test_setup(); 2836 /* rw- */ 2837 ept_access_allowed(EPT_RA | EPT_WA, OP_READ); 2838 ept_access_allowed(EPT_RA | EPT_WA, OP_WRITE); 2839 ept_access_violation(EPT_RA | EPT_WA, OP_EXEC, 2840 EPT_VLT_FETCH | EPT_VLT_PERM_RD | EPT_VLT_PERM_WR); 2841 } 2842 2843 2844 static void ept_access_test_execute_only(void) 2845 { 2846 ept_access_test_setup(); 2847 /* --x */ 2848 if (ept_execute_only_supported()) { 2849 ept_access_violation(EPT_EA, OP_READ, 2850 EPT_VLT_RD | EPT_VLT_PERM_EX); 2851 ept_access_violation(EPT_EA, OP_WRITE, 2852 EPT_VLT_WR | EPT_VLT_PERM_EX); 2853 ept_access_allowed(EPT_EA, OP_EXEC); 2854 } else { 2855 ept_access_misconfig(EPT_EA); 2856 } 2857 } 2858 2859 static void ept_access_test_read_execute(void) 2860 { 2861 ept_access_test_setup(); 2862 /* r-x */ 2863 ept_access_allowed(EPT_RA | EPT_EA, OP_READ); 2864 ept_access_violation(EPT_RA | EPT_EA, OP_WRITE, 2865 EPT_VLT_WR | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX); 2866 ept_access_allowed(EPT_RA | EPT_EA, OP_EXEC); 2867 } 2868 2869 static void ept_access_test_write_execute(void) 2870 { 2871 ept_access_test_setup(); 2872 /* -wx */ 2873 ept_access_misconfig(EPT_WA | EPT_EA); 2874 } 2875 2876 static void ept_access_test_read_write_execute(void) 2877 { 2878 ept_access_test_setup(); 2879 /* rwx */ 2880 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_READ); 2881 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_WRITE); 2882 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_EXEC); 2883 } 2884 2885 static void ept_access_test_reserved_bits(void) 2886 { 2887 int i; 2888 int maxphyaddr; 2889 2890 ept_access_test_setup(); 2891 2892 /* Reserved bits above maxphyaddr. */ 2893 maxphyaddr = cpuid_maxphyaddr(); 2894 for (i = maxphyaddr; i <= 51; i++) { 2895 report_prefix_pushf("reserved_bit=%d", i); 2896 ept_reserved_bit(i); 2897 report_prefix_pop(); 2898 } 2899 2900 /* Level-specific reserved bits. */ 2901 ept_reserved_bit_at_level_nohuge(2, 3); 2902 ept_reserved_bit_at_level_nohuge(2, 4); 2903 ept_reserved_bit_at_level_nohuge(2, 5); 2904 ept_reserved_bit_at_level_nohuge(2, 6); 2905 /* 2M alignment. */ 2906 for (i = 12; i < 20; i++) { 2907 report_prefix_pushf("reserved_bit=%d", i); 2908 ept_reserved_bit_at_level_huge(2, i); 2909 report_prefix_pop(); 2910 } 2911 ept_reserved_bit_at_level_nohuge(3, 3); 2912 ept_reserved_bit_at_level_nohuge(3, 4); 2913 ept_reserved_bit_at_level_nohuge(3, 5); 2914 ept_reserved_bit_at_level_nohuge(3, 6); 2915 /* 1G alignment. */ 2916 for (i = 12; i < 29; i++) { 2917 report_prefix_pushf("reserved_bit=%d", i); 2918 ept_reserved_bit_at_level_huge(3, i); 2919 report_prefix_pop(); 2920 } 2921 ept_reserved_bit_at_level(4, 3); 2922 ept_reserved_bit_at_level(4, 4); 2923 ept_reserved_bit_at_level(4, 5); 2924 ept_reserved_bit_at_level(4, 6); 2925 ept_reserved_bit_at_level(4, 7); 2926 } 2927 2928 static void ept_access_test_ignored_bits(void) 2929 { 2930 ept_access_test_setup(); 2931 /* 2932 * Bits ignored at every level. Bits 8 and 9 (A and D) are ignored as 2933 * far as translation is concerned even if AD bits are enabled in the 2934 * EPTP. Bit 63 is ignored because "EPT-violation #VE" VM-execution 2935 * control is 0. 2936 */ 2937 ept_ignored_bit(8); 2938 ept_ignored_bit(9); 2939 ept_ignored_bit(10); 2940 ept_ignored_bit(11); 2941 ept_ignored_bit(52); 2942 ept_ignored_bit(53); 2943 ept_ignored_bit(54); 2944 ept_ignored_bit(55); 2945 ept_ignored_bit(56); 2946 ept_ignored_bit(57); 2947 ept_ignored_bit(58); 2948 ept_ignored_bit(59); 2949 ept_ignored_bit(60); 2950 ept_ignored_bit(61); 2951 ept_ignored_bit(62); 2952 ept_ignored_bit(63); 2953 } 2954 2955 static void ept_access_test_paddr_not_present_ad_disabled(void) 2956 { 2957 ept_access_test_setup(); 2958 ept_disable_ad_bits(); 2959 2960 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, EPT_VLT_RD); 2961 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, EPT_VLT_RD); 2962 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, EPT_VLT_RD); 2963 } 2964 2965 static void ept_access_test_paddr_not_present_ad_enabled(void) 2966 { 2967 u64 qual = EPT_VLT_RD | EPT_VLT_WR; 2968 2969 ept_access_test_setup(); 2970 ept_enable_ad_bits_or_skip_test(); 2971 2972 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, qual); 2973 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, qual); 2974 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, qual); 2975 } 2976 2977 static void ept_access_test_paddr_read_only_ad_disabled(void) 2978 { 2979 /* 2980 * When EPT AD bits are disabled, all accesses to guest paging 2981 * structures are reported separately as a read and (after 2982 * translation of the GPA to host physical address) a read+write 2983 * if the A/D bits have to be set. 2984 */ 2985 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 2986 2987 ept_access_test_setup(); 2988 ept_disable_ad_bits(); 2989 2990 /* Can't update A bit, so all accesses fail. */ 2991 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 2992 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 2993 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 2994 /* AD bits disabled, so only writes try to update the D bit. */ 2995 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ); 2996 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 2997 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC); 2998 /* Both A and D already set, so read-only is OK. */ 2999 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_READ); 3000 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_WRITE); 3001 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_EXEC); 3002 } 3003 3004 static void ept_access_test_paddr_read_only_ad_enabled(void) 3005 { 3006 /* 3007 * When EPT AD bits are enabled, all accesses to guest paging 3008 * structures are considered writes as far as EPT translation 3009 * is concerned. 3010 */ 3011 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 3012 3013 ept_access_test_setup(); 3014 ept_enable_ad_bits_or_skip_test(); 3015 3016 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 3017 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 3018 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 3019 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ, qual); 3020 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 3021 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC, qual); 3022 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_READ, qual); 3023 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_WRITE, qual); 3024 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_EXEC, qual); 3025 } 3026 3027 static void ept_access_test_paddr_read_write(void) 3028 { 3029 ept_access_test_setup(); 3030 /* Read-write access to paging structure. */ 3031 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_READ); 3032 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_WRITE); 3033 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_EXEC); 3034 } 3035 3036 static void ept_access_test_paddr_read_write_execute(void) 3037 { 3038 ept_access_test_setup(); 3039 /* RWX access to paging structure. */ 3040 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_READ); 3041 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_WRITE); 3042 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_EXEC); 3043 } 3044 3045 static void ept_access_test_paddr_read_execute_ad_disabled(void) 3046 { 3047 /* 3048 * When EPT AD bits are disabled, all accesses to guest paging 3049 * structures are reported separately as a read and (after 3050 * translation of the GPA to host physical address) a read+write 3051 * if the A/D bits have to be set. 3052 */ 3053 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3054 3055 ept_access_test_setup(); 3056 ept_disable_ad_bits(); 3057 3058 /* Can't update A bit, so all accesses fail. */ 3059 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3060 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3061 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3062 /* AD bits disabled, so only writes try to update the D bit. */ 3063 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ); 3064 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3065 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC); 3066 /* Both A and D already set, so read-only is OK. */ 3067 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ); 3068 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE); 3069 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC); 3070 } 3071 3072 static void ept_access_test_paddr_read_execute_ad_enabled(void) 3073 { 3074 /* 3075 * When EPT AD bits are enabled, all accesses to guest paging 3076 * structures are considered writes as far as EPT translation 3077 * is concerned. 3078 */ 3079 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3080 3081 ept_access_test_setup(); 3082 ept_enable_ad_bits_or_skip_test(); 3083 3084 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3085 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3086 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3087 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ, qual); 3088 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3089 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC, qual); 3090 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ, qual); 3091 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE, qual); 3092 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC, qual); 3093 } 3094 3095 static void ept_access_test_paddr_not_present_page_fault(void) 3096 { 3097 ept_access_test_setup(); 3098 /* 3099 * TODO: test no EPT violation as long as guest PF occurs. e.g., GPA is 3100 * page is read-only in EPT but GVA is also mapped read only in PT. 3101 * Thus guest page fault before host takes EPT violation for trying to 3102 * update A bit. 3103 */ 3104 } 3105 3106 static void ept_access_test_force_2m_page(void) 3107 { 3108 ept_access_test_setup(); 3109 3110 TEST_ASSERT_EQ(ept_2m_supported(), true); 3111 ept_allowed_at_level_mkhuge(true, 2, 0, 0, OP_READ); 3112 ept_violation_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_RA, OP_WRITE, 3113 EPT_VLT_WR | EPT_VLT_PERM_RD | 3114 EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 3115 ept_misconfig_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_WA); 3116 } 3117 3118 static bool invvpid_valid(u64 type, u64 vpid, u64 gla) 3119 { 3120 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3121 3122 TEST_ASSERT(msr & VPID_CAP_INVVPID); 3123 3124 if (type < INVVPID_ADDR || type > INVVPID_CONTEXT_LOCAL) 3125 return false; 3126 3127 if (!(msr & (1ull << (type + VPID_CAP_INVVPID_TYPES_SHIFT)))) 3128 return false; 3129 3130 if (vpid >> 16) 3131 return false; 3132 3133 if (type != INVVPID_ALL && !vpid) 3134 return false; 3135 3136 if (type == INVVPID_ADDR && !is_canonical(gla)) 3137 return false; 3138 3139 return true; 3140 } 3141 3142 static void try_invvpid(u64 type, u64 vpid, u64 gla) 3143 { 3144 int rc; 3145 bool valid = invvpid_valid(type, vpid, gla); 3146 u64 expected = valid ? VMXERR_UNSUPPORTED_VMCS_COMPONENT 3147 : VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID; 3148 /* 3149 * Set VMX_INST_ERROR to VMXERR_UNVALID_VMCS_COMPONENT, so 3150 * that we can tell if it is updated by INVVPID. 3151 */ 3152 vmcs_read(~0); 3153 rc = invvpid(type, vpid, gla); 3154 report("INVVPID type %ld VPID %lx GLA %lx %s", 3155 !rc == valid, type, vpid, gla, 3156 valid ? "passes" : "fails"); 3157 report("After %s INVVPID, VMX_INST_ERR is %ld (actual %ld)", 3158 vmcs_read(VMX_INST_ERROR) == expected, 3159 rc ? "failed" : "successful", 3160 expected, vmcs_read(VMX_INST_ERROR)); 3161 } 3162 3163 static void ds_invvpid(void *data) 3164 { 3165 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3166 u64 type = ffs(msr >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 3167 3168 TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 3169 asm volatile("invvpid %0, %1" 3170 : 3171 : "m"(*(struct invvpid_operand *)data), 3172 "r"(type)); 3173 } 3174 3175 /* 3176 * The SS override is ignored in 64-bit mode, so we use an addressing 3177 * mode with %rsp as the base register to generate an implicit SS 3178 * reference. 3179 */ 3180 static void ss_invvpid(void *data) 3181 { 3182 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3183 u64 type = ffs(msr >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 3184 3185 TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 3186 asm volatile("sub %%rsp,%0; invvpid (%%rsp,%0,1), %1" 3187 : "+r"(data) 3188 : "r"(type)); 3189 } 3190 3191 static void invvpid_test_gp(void) 3192 { 3193 bool fault; 3194 3195 fault = test_for_exception(GP_VECTOR, &ds_invvpid, 3196 (void *)NONCANONICAL); 3197 report("INVVPID with non-canonical DS operand raises #GP", fault); 3198 } 3199 3200 static void invvpid_test_ss(void) 3201 { 3202 bool fault; 3203 3204 fault = test_for_exception(SS_VECTOR, &ss_invvpid, 3205 (void *)NONCANONICAL); 3206 report("INVVPID with non-canonical SS operand raises #SS", fault); 3207 } 3208 3209 static void invvpid_test_pf(void) 3210 { 3211 void *vpage = alloc_vpage(); 3212 bool fault; 3213 3214 fault = test_for_exception(PF_VECTOR, &ds_invvpid, vpage); 3215 report("INVVPID with unmapped operand raises #PF", fault); 3216 } 3217 3218 static void try_compat_invvpid(void *unused) 3219 { 3220 struct far_pointer32 fp = { 3221 .offset = (uintptr_t)&&invvpid, 3222 .selector = KERNEL_CS32, 3223 }; 3224 register uintptr_t rsp asm("rsp"); 3225 3226 TEST_ASSERT_MSG(fp.offset == (uintptr_t)&&invvpid, 3227 "Code address too high."); 3228 TEST_ASSERT_MSG(rsp == (u32)rsp, "Stack address too high."); 3229 3230 asm goto ("lcall *%0" : : "m" (fp) : "rax" : invvpid); 3231 return; 3232 invvpid: 3233 asm volatile (".code32;" 3234 "invvpid (%eax), %eax;" 3235 "lret;" 3236 ".code64"); 3237 __builtin_unreachable(); 3238 } 3239 3240 static void invvpid_test_compatibility_mode(void) 3241 { 3242 bool fault; 3243 3244 fault = test_for_exception(UD_VECTOR, &try_compat_invvpid, NULL); 3245 report("Compatibility mode INVVPID raises #UD", fault); 3246 } 3247 3248 static void invvpid_test_not_in_vmx_operation(void) 3249 { 3250 bool fault; 3251 3252 TEST_ASSERT(!vmx_off()); 3253 fault = test_for_exception(UD_VECTOR, &ds_invvpid, NULL); 3254 report("INVVPID outside of VMX operation raises #UD", fault); 3255 TEST_ASSERT(!vmx_on()); 3256 } 3257 3258 /* 3259 * This does not test real-address mode, virtual-8086 mode, protected mode, 3260 * or CPL > 0. 3261 */ 3262 static void invvpid_test_v2(void) 3263 { 3264 u64 msr; 3265 int i; 3266 unsigned types = 0; 3267 unsigned type; 3268 3269 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 3270 !(ctrl_cpu_rev[1].clr & CPU_VPID)) 3271 test_skip("VPID not supported"); 3272 3273 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3274 3275 if (!(msr & VPID_CAP_INVVPID)) 3276 test_skip("INVVPID not supported.\n"); 3277 3278 if (msr & VPID_CAP_INVVPID_ADDR) 3279 types |= 1u << INVVPID_ADDR; 3280 if (msr & VPID_CAP_INVVPID_CXTGLB) 3281 types |= 1u << INVVPID_CONTEXT_GLOBAL; 3282 if (msr & VPID_CAP_INVVPID_ALL) 3283 types |= 1u << INVVPID_ALL; 3284 if (msr & VPID_CAP_INVVPID_CXTLOC) 3285 types |= 1u << INVVPID_CONTEXT_LOCAL; 3286 3287 if (!types) 3288 test_skip("No INVVPID types supported.\n"); 3289 3290 for (i = -127; i < 128; i++) 3291 try_invvpid(i, 0xffff, 0); 3292 3293 /* 3294 * VPID must not be more than 16 bits. 3295 */ 3296 for (i = 0; i < 64; i++) 3297 for (type = 0; type < 4; type++) 3298 if (types & (1u << type)) 3299 try_invvpid(type, 1ul << i, 0); 3300 3301 /* 3302 * VPID must not be zero, except for "all contexts." 3303 */ 3304 for (type = 0; type < 4; type++) 3305 if (types & (1u << type)) 3306 try_invvpid(type, 0, 0); 3307 3308 /* 3309 * The gla operand is only validated for single-address INVVPID. 3310 */ 3311 if (types & (1u << INVVPID_ADDR)) 3312 try_invvpid(INVVPID_ADDR, 0xffff, NONCANONICAL); 3313 3314 invvpid_test_gp(); 3315 invvpid_test_ss(); 3316 invvpid_test_pf(); 3317 invvpid_test_compatibility_mode(); 3318 invvpid_test_not_in_vmx_operation(); 3319 } 3320 3321 /* 3322 * Test for early VMLAUNCH failure. Returns true if VMLAUNCH makes it 3323 * at least as far as the guest-state checks. Returns false if the 3324 * VMLAUNCH fails early and execution falls through to the next 3325 * instruction. 3326 */ 3327 static bool vmlaunch_succeeds(void) 3328 { 3329 u32 exit_reason; 3330 3331 /* 3332 * Indirectly set VMX_INST_ERR to 12 ("VMREAD/VMWRITE from/to 3333 * unsupported VMCS component"). The caller can then check 3334 * to see if a failed VM-entry sets VMX_INST_ERR as expected. 3335 */ 3336 vmcs_write(~0u, 0); 3337 3338 vmcs_write(HOST_RIP, (uintptr_t)&&success); 3339 __asm__ __volatile__ goto ("vmwrite %%rsp, %0; vmlaunch" 3340 : 3341 : "r" ((u64)HOST_RSP) 3342 : "cc", "memory" 3343 : success); 3344 return false; 3345 success: 3346 exit_reason = vmcs_read(EXI_REASON); 3347 TEST_ASSERT(exit_reason == (VMX_FAIL_STATE | VMX_ENTRY_FAILURE) || 3348 exit_reason == (VMX_FAIL_MSR | VMX_ENTRY_FAILURE)); 3349 return true; 3350 } 3351 3352 /* 3353 * Try to launch the current VMCS. 3354 */ 3355 static void test_vmx_vmlaunch(u32 xerror) 3356 { 3357 bool success = vmlaunch_succeeds(); 3358 u32 vmx_inst_err; 3359 3360 report("vmlaunch %s", success == !xerror, 3361 !xerror ? "succeeds" : "fails"); 3362 if (!success && xerror) { 3363 vmx_inst_err = vmcs_read(VMX_INST_ERROR); 3364 report("VMX inst error is %d (actual %d)", 3365 vmx_inst_err == xerror, xerror, vmx_inst_err); 3366 } 3367 } 3368 3369 static void test_vmx_invalid_controls(void) 3370 { 3371 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_CONTROL_FIELD); 3372 } 3373 3374 static void test_vmx_valid_controls(void) 3375 { 3376 test_vmx_vmlaunch(0); 3377 } 3378 3379 /* 3380 * Test a particular value of a VM-execution control bit, if the value 3381 * is required or if the value is zero. 3382 */ 3383 static void test_rsvd_ctl_bit_value(const char *name, union vmx_ctrl_msr msr, 3384 enum Encoding encoding, unsigned bit, 3385 unsigned val) 3386 { 3387 u32 mask = 1u << bit; 3388 bool expected; 3389 u32 controls; 3390 3391 if (msr.set & mask) 3392 TEST_ASSERT(msr.clr & mask); 3393 3394 /* 3395 * We can't arbitrarily turn on a control bit, because it may 3396 * introduce dependencies on other VMCS fields. So, we only 3397 * test turning on bits that have a required setting. 3398 */ 3399 if (val && (msr.clr & mask) && !(msr.set & mask)) 3400 return; 3401 3402 report_prefix_pushf("%s %s bit %d", 3403 val ? "Set" : "Clear", name, bit); 3404 3405 controls = vmcs_read(encoding); 3406 if (val) { 3407 vmcs_write(encoding, msr.set | mask); 3408 expected = (msr.clr & mask); 3409 } else { 3410 vmcs_write(encoding, msr.set & ~mask); 3411 expected = !(msr.set & mask); 3412 } 3413 if (expected) 3414 test_vmx_valid_controls(); 3415 else 3416 test_vmx_invalid_controls(); 3417 vmcs_write(encoding, controls); 3418 report_prefix_pop(); 3419 } 3420 3421 /* 3422 * Test reserved values of a VM-execution control bit, based on the 3423 * allowed bit settings from the corresponding VMX capability MSR. 3424 */ 3425 static void test_rsvd_ctl_bit(const char *name, union vmx_ctrl_msr msr, 3426 enum Encoding encoding, unsigned bit) 3427 { 3428 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 0); 3429 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 1); 3430 } 3431 3432 /* 3433 * Reserved bits in the pin-based VM-execution controls must be set 3434 * properly. Software may consult the VMX capability MSRs to determine 3435 * the proper settings. 3436 * [Intel SDM] 3437 */ 3438 static void test_pin_based_ctls(void) 3439 { 3440 unsigned bit; 3441 3442 printf("%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PIN" : 3443 "MSR_IA32_VMX_PINBASED_CTLS", ctrl_pin_rev.val); 3444 for (bit = 0; bit < 32; bit++) 3445 test_rsvd_ctl_bit("pin-based controls", 3446 ctrl_pin_rev, PIN_CONTROLS, bit); 3447 } 3448 3449 /* 3450 * Reserved bits in the primary processor-based VM-execution controls 3451 * must be set properly. Software may consult the VMX capability MSRs 3452 * to determine the proper settings. 3453 * [Intel SDM] 3454 */ 3455 static void test_primary_processor_based_ctls(void) 3456 { 3457 unsigned bit; 3458 3459 printf("\n%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PROC" : 3460 "MSR_IA32_VMX_PROCBASED_CTLS", ctrl_cpu_rev[0].val); 3461 for (bit = 0; bit < 32; bit++) 3462 test_rsvd_ctl_bit("primary processor-based controls", 3463 ctrl_cpu_rev[0], CPU_EXEC_CTRL0, bit); 3464 } 3465 3466 /* 3467 * If the "activate secondary controls" primary processor-based 3468 * VM-execution control is 1, reserved bits in the secondary 3469 * processor-based VM-execution controls must be cleared. Software may 3470 * consult the VMX capability MSRs to determine which bits are 3471 * reserved. 3472 * If the "activate secondary controls" primary processor-based 3473 * VM-execution control is 0 (or if the processor does not support the 3474 * 1-setting of that control), no checks are performed on the 3475 * secondary processor-based VM-execution controls. 3476 * [Intel SDM] 3477 */ 3478 static void test_secondary_processor_based_ctls(void) 3479 { 3480 u32 primary; 3481 u32 secondary; 3482 unsigned bit; 3483 3484 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) 3485 return; 3486 3487 primary = vmcs_read(CPU_EXEC_CTRL0); 3488 secondary = vmcs_read(CPU_EXEC_CTRL1); 3489 3490 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3491 printf("\nMSR_IA32_VMX_PROCBASED_CTLS2: %lx\n", ctrl_cpu_rev[1].val); 3492 for (bit = 0; bit < 32; bit++) 3493 test_rsvd_ctl_bit("secondary processor-based controls", 3494 ctrl_cpu_rev[1], CPU_EXEC_CTRL1, bit); 3495 3496 /* 3497 * When the "activate secondary controls" VM-execution control 3498 * is clear, there are no checks on the secondary controls. 3499 */ 3500 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3501 vmcs_write(CPU_EXEC_CTRL1, ~0); 3502 report("Secondary processor-based controls ignored", 3503 vmlaunch_succeeds()); 3504 vmcs_write(CPU_EXEC_CTRL1, secondary); 3505 vmcs_write(CPU_EXEC_CTRL0, primary); 3506 } 3507 3508 static void try_cr3_target_count(unsigned i, unsigned max) 3509 { 3510 report_prefix_pushf("CR3 target count 0x%x", i); 3511 vmcs_write(CR3_TARGET_COUNT, i); 3512 if (i <= max) 3513 test_vmx_valid_controls(); 3514 else 3515 test_vmx_invalid_controls(); 3516 report_prefix_pop(); 3517 } 3518 3519 /* 3520 * The CR3-target count must not be greater than 4. Future processors 3521 * may support a different number of CR3-target values. Software 3522 * should read the VMX capability MSR IA32_VMX_MISC to determine the 3523 * number of values supported. 3524 * [Intel SDM] 3525 */ 3526 static void test_cr3_targets(void) 3527 { 3528 unsigned supported_targets = (rdmsr(MSR_IA32_VMX_MISC) >> 16) & 0x1ff; 3529 u32 cr3_targets = vmcs_read(CR3_TARGET_COUNT); 3530 unsigned i; 3531 3532 printf("\nSupported CR3 targets: %d\n", supported_targets); 3533 TEST_ASSERT(supported_targets <= 256); 3534 3535 try_cr3_target_count(-1u, supported_targets); 3536 try_cr3_target_count(0x80000000, supported_targets); 3537 try_cr3_target_count(0x7fffffff, supported_targets); 3538 for (i = 0; i <= supported_targets + 1; i++) 3539 try_cr3_target_count(i, supported_targets); 3540 vmcs_write(CR3_TARGET_COUNT, cr3_targets); 3541 } 3542 3543 /* 3544 * Test a particular address setting in the VMCS 3545 */ 3546 static void test_vmcs_addr(const char *name, 3547 enum Encoding encoding, 3548 u64 align, 3549 bool ignored, 3550 bool skip_beyond_mapped_ram, 3551 u64 addr) 3552 { 3553 report_prefix_pushf("%s = %lx", name, addr); 3554 vmcs_write(encoding, addr); 3555 if (skip_beyond_mapped_ram && 3556 addr > fwcfg_get_u64(FW_CFG_RAM_SIZE) - align && 3557 addr < (1ul << cpuid_maxphyaddr())) 3558 printf("Skipping physical address beyond mapped RAM\n"); 3559 else if (ignored || (IS_ALIGNED(addr, align) && 3560 addr < (1ul << cpuid_maxphyaddr()))) 3561 test_vmx_valid_controls(); 3562 else 3563 test_vmx_invalid_controls(); 3564 report_prefix_pop(); 3565 } 3566 3567 /* 3568 * Test interesting values for a VMCS address 3569 */ 3570 static void test_vmcs_addr_values(const char *name, 3571 enum Encoding encoding, 3572 u64 align, 3573 bool ignored, 3574 bool skip_beyond_mapped_ram, 3575 u32 bit_start, u32 bit_end) 3576 { 3577 unsigned i; 3578 u64 orig_val = vmcs_read(encoding); 3579 3580 for (i = bit_start; i <= bit_end; i++) 3581 test_vmcs_addr(name, encoding, align, ignored, 3582 skip_beyond_mapped_ram, 1ul << i); 3583 3584 test_vmcs_addr(name, encoding, align, ignored, 3585 skip_beyond_mapped_ram, PAGE_SIZE - 1); 3586 test_vmcs_addr(name, encoding, align, ignored, 3587 skip_beyond_mapped_ram, PAGE_SIZE); 3588 test_vmcs_addr(name, encoding, align, ignored, 3589 skip_beyond_mapped_ram, 3590 (1ul << cpuid_maxphyaddr()) - PAGE_SIZE); 3591 test_vmcs_addr(name, encoding, align, ignored, 3592 skip_beyond_mapped_ram, -1ul); 3593 3594 vmcs_write(encoding, orig_val); 3595 } 3596 3597 /* 3598 * Test a physical address reference in the VMCS, when the corresponding 3599 * feature is enabled and when the corresponding feature is disabled. 3600 */ 3601 static void test_vmcs_addr_reference(u32 control_bit, enum Encoding field, 3602 const char *field_name, 3603 const char *control_name, u64 align, 3604 bool skip_beyond_mapped_ram, 3605 bool control_primary) 3606 { 3607 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 3608 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 3609 u64 page_addr; 3610 3611 if (control_primary) { 3612 if (!(ctrl_cpu_rev[0].clr & control_bit)) 3613 return; 3614 } else { 3615 if (!(ctrl_cpu_rev[1].clr & control_bit)) 3616 return; 3617 } 3618 3619 page_addr = vmcs_read(field); 3620 3621 report_prefix_pushf("%s enabled", control_name); 3622 if (control_primary) { 3623 vmcs_write(CPU_EXEC_CTRL0, primary | control_bit); 3624 } else { 3625 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3626 vmcs_write(CPU_EXEC_CTRL1, secondary | control_bit); 3627 } 3628 3629 test_vmcs_addr_values(field_name, field, align, false, 3630 skip_beyond_mapped_ram, 0, 63); 3631 report_prefix_pop(); 3632 3633 report_prefix_pushf("%s disabled", control_name); 3634 if (control_primary) { 3635 vmcs_write(CPU_EXEC_CTRL0, primary & ~control_bit); 3636 } else { 3637 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3638 vmcs_write(CPU_EXEC_CTRL1, secondary & ~control_bit); 3639 } 3640 3641 test_vmcs_addr_values(field_name, field, align, true, false, 0, 63); 3642 report_prefix_pop(); 3643 3644 vmcs_write(field, page_addr); 3645 vmcs_write(CPU_EXEC_CTRL0, primary); 3646 vmcs_write(CPU_EXEC_CTRL1, secondary); 3647 } 3648 3649 /* 3650 * If the "use I/O bitmaps" VM-execution control is 1, bits 11:0 of 3651 * each I/O-bitmap address must be 0. Neither address should set any 3652 * bits beyond the processor's physical-address width. 3653 * [Intel SDM] 3654 */ 3655 static void test_io_bitmaps(void) 3656 { 3657 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_A, 3658 "I/O bitmap A", "Use I/O bitmaps", 3659 PAGE_SIZE, false, true); 3660 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_B, 3661 "I/O bitmap B", "Use I/O bitmaps", 3662 PAGE_SIZE, false, true); 3663 } 3664 3665 /* 3666 * If the "use MSR bitmaps" VM-execution control is 1, bits 11:0 of 3667 * the MSR-bitmap address must be 0. The address should not set any 3668 * bits beyond the processor's physical-address width. 3669 * [Intel SDM] 3670 */ 3671 static void test_msr_bitmap(void) 3672 { 3673 test_vmcs_addr_reference(CPU_MSR_BITMAP, MSR_BITMAP, 3674 "MSR bitmap", "Use MSR bitmaps", 3675 PAGE_SIZE, false, true); 3676 } 3677 3678 /* 3679 * If the "use TPR shadow" VM-execution control is 1, the virtual-APIC 3680 * address must satisfy the following checks: 3681 * - Bits 11:0 of the address must be 0. 3682 * - The address should not set any bits beyond the processor's 3683 * physical-address width. 3684 * [Intel SDM] 3685 */ 3686 static void test_apic_virt_addr(void) 3687 { 3688 /* 3689 * Ensure the processor will never use the virtual-APIC page, since 3690 * we will point it to invalid RAM. Otherwise KVM is puzzled about 3691 * what we're trying to achieve and fails vmentry. 3692 */ 3693 u32 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 3694 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0 | CPU_CR8_LOAD | CPU_CR8_STORE); 3695 test_vmcs_addr_reference(CPU_TPR_SHADOW, APIC_VIRT_ADDR, 3696 "virtual-APIC address", "Use TPR shadow", 3697 PAGE_SIZE, false, true); 3698 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 3699 } 3700 3701 /* 3702 * If the "virtualize APIC-accesses" VM-execution control is 1, the 3703 * APIC-access address must satisfy the following checks: 3704 * - Bits 11:0 of the address must be 0. 3705 * - The address should not set any bits beyond the processor's 3706 * physical-address width. 3707 * [Intel SDM] 3708 */ 3709 static void test_apic_access_addr(void) 3710 { 3711 void *apic_access_page = alloc_page(); 3712 3713 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_page)); 3714 3715 test_vmcs_addr_reference(CPU_VIRT_APIC_ACCESSES, APIC_ACCS_ADDR, 3716 "APIC-access address", 3717 "virtualize APIC-accesses", PAGE_SIZE, 3718 true, false); 3719 } 3720 3721 static bool set_bit_pattern(u8 mask, u32 *secondary) 3722 { 3723 u8 i; 3724 bool flag = false; 3725 u32 test_bits[3] = { 3726 CPU_VIRT_X2APIC, 3727 CPU_APIC_REG_VIRT, 3728 CPU_VINTD 3729 }; 3730 3731 for (i = 0; i < ARRAY_SIZE(test_bits); i++) { 3732 if ((mask & (1u << i)) && 3733 (ctrl_cpu_rev[1].clr & test_bits[i])) { 3734 *secondary |= test_bits[i]; 3735 flag = true; 3736 } 3737 } 3738 3739 return (flag); 3740 } 3741 3742 /* 3743 * If the "use TPR shadow" VM-execution control is 0, the following 3744 * VM-execution controls must also be 0: 3745 * - virtualize x2APIC mode 3746 * - APIC-register virtualization 3747 * - virtual-interrupt delivery 3748 * [Intel SDM] 3749 * 3750 * 2. If the "virtualize x2APIC mode" VM-execution control is 1, the 3751 * "virtualize APIC accesses" VM-execution control must be 0. 3752 * [Intel SDM] 3753 */ 3754 static void test_apic_virtual_ctls(void) 3755 { 3756 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3757 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3758 u32 primary = saved_primary; 3759 u32 secondary = saved_secondary; 3760 bool ctrl = false; 3761 char str[10] = "disabled"; 3762 u8 i = 0, j; 3763 3764 /* 3765 * First test 3766 */ 3767 if (!((ctrl_cpu_rev[0].clr & (CPU_SECONDARY | CPU_TPR_SHADOW)) == 3768 (CPU_SECONDARY | CPU_TPR_SHADOW))) 3769 return; 3770 3771 primary |= CPU_SECONDARY; 3772 primary &= ~CPU_TPR_SHADOW; 3773 vmcs_write(CPU_EXEC_CTRL0, primary); 3774 3775 while (1) { 3776 for (j = 1; j < 8; j++) { 3777 secondary &= ~(CPU_VIRT_X2APIC | CPU_APIC_REG_VIRT | CPU_VINTD); 3778 if (primary & CPU_TPR_SHADOW) { 3779 ctrl = true; 3780 } else { 3781 if (! set_bit_pattern(j, &secondary)) 3782 ctrl = true; 3783 else 3784 ctrl = false; 3785 } 3786 3787 vmcs_write(CPU_EXEC_CTRL1, secondary); 3788 report_prefix_pushf("Use TPR shadow %s, virtualize x2APIC mode %s, APIC-register virtualization %s, virtual-interrupt delivery %s", 3789 str, (secondary & CPU_VIRT_X2APIC) ? "enabled" : "disabled", (secondary & CPU_APIC_REG_VIRT) ? "enabled" : "disabled", (secondary & CPU_VINTD) ? "enabled" : "disabled"); 3790 if (ctrl) 3791 test_vmx_valid_controls(); 3792 else 3793 test_vmx_invalid_controls(); 3794 report_prefix_pop(); 3795 } 3796 3797 if (i == 1) 3798 break; 3799 i++; 3800 3801 primary |= CPU_TPR_SHADOW; 3802 vmcs_write(CPU_EXEC_CTRL0, primary); 3803 strcpy(str, "enabled"); 3804 } 3805 3806 /* 3807 * Second test 3808 */ 3809 u32 apic_virt_ctls = (CPU_VIRT_X2APIC | CPU_VIRT_APIC_ACCESSES); 3810 3811 primary = saved_primary; 3812 secondary = saved_secondary; 3813 if (!((ctrl_cpu_rev[1].clr & apic_virt_ctls) == apic_virt_ctls)) 3814 return; 3815 3816 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3817 secondary &= ~CPU_VIRT_APIC_ACCESSES; 3818 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_X2APIC); 3819 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access disabled"); 3820 test_vmx_valid_controls(); 3821 report_prefix_pop(); 3822 3823 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_APIC_ACCESSES); 3824 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access enabled"); 3825 test_vmx_valid_controls(); 3826 report_prefix_pop(); 3827 3828 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_X2APIC); 3829 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access enabled"); 3830 test_vmx_invalid_controls(); 3831 report_prefix_pop(); 3832 3833 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_APIC_ACCESSES); 3834 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access disabled"); 3835 test_vmx_valid_controls(); 3836 report_prefix_pop(); 3837 3838 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3839 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3840 } 3841 3842 /* 3843 * If the "virtual-interrupt delivery" VM-execution control is 1, the 3844 * "external-interrupt exiting" VM-execution control must be 1. 3845 * [Intel SDM] 3846 */ 3847 static void test_virtual_intr_ctls(void) 3848 { 3849 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3850 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3851 u32 saved_pin = vmcs_read(PIN_CONTROLS); 3852 u32 primary = saved_primary; 3853 u32 secondary = saved_secondary; 3854 u32 pin = saved_pin; 3855 3856 if (!((ctrl_cpu_rev[1].clr & CPU_VINTD) && 3857 (ctrl_pin_rev.clr & PIN_EXTINT))) 3858 return; 3859 3860 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 3861 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VINTD); 3862 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 3863 report_prefix_pushf("Virtualize interrupt-delivery disabled; external-interrupt exiting disabled"); 3864 test_vmx_valid_controls(); 3865 report_prefix_pop(); 3866 3867 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VINTD); 3868 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 3869 test_vmx_invalid_controls(); 3870 report_prefix_pop(); 3871 3872 vmcs_write(PIN_CONTROLS, pin | PIN_EXTINT); 3873 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting enabled"); 3874 test_vmx_valid_controls(); 3875 report_prefix_pop(); 3876 3877 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 3878 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 3879 test_vmx_invalid_controls(); 3880 report_prefix_pop(); 3881 3882 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3883 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3884 vmcs_write(PIN_CONTROLS, saved_pin); 3885 } 3886 3887 static void test_pi_desc_addr(u64 addr, bool ctrl) 3888 { 3889 vmcs_write(POSTED_INTR_DESC_ADDR, addr); 3890 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-descriptor-address 0x%lx", addr); 3891 if (ctrl) 3892 test_vmx_valid_controls(); 3893 else 3894 test_vmx_invalid_controls(); 3895 report_prefix_pop(); 3896 } 3897 3898 /* 3899 * If the “process posted interrupts†VM-execution control is 1, the 3900 * following must be true: 3901 * 3902 * - The “virtual-interrupt delivery†VM-execution control is 1. 3903 * - The “acknowledge interrupt on exit†VM-exit control is 1. 3904 * - The posted-interrupt notification vector has a value in the 3905 * - range 0–255 (bits 15:8 are all 0). 3906 * - Bits 5:0 of the posted-interrupt descriptor address are all 0. 3907 * - The posted-interrupt descriptor address does not set any bits 3908 * beyond the processor's physical-address width. 3909 * [Intel SDM] 3910 */ 3911 static void test_posted_intr(void) 3912 { 3913 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3914 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3915 u32 saved_pin = vmcs_read(PIN_CONTROLS); 3916 u32 exit_ctl_saved = vmcs_read(EXI_CONTROLS); 3917 u32 primary = saved_primary; 3918 u32 secondary = saved_secondary; 3919 u32 pin = saved_pin; 3920 u32 exit_ctl = exit_ctl_saved; 3921 u16 vec; 3922 int i; 3923 3924 if (!((ctrl_pin_rev.clr & PIN_POST_INTR) && 3925 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 3926 (ctrl_exit_rev.clr & EXI_INTA))) 3927 return; 3928 3929 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 3930 3931 /* 3932 * Test virtual-interrupt-delivery and acknowledge-interrupt-on-exit 3933 */ 3934 pin |= PIN_POST_INTR; 3935 vmcs_write(PIN_CONTROLS, pin); 3936 secondary &= ~CPU_VINTD; 3937 vmcs_write(CPU_EXEC_CTRL1, secondary); 3938 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled"); 3939 test_vmx_invalid_controls(); 3940 report_prefix_pop(); 3941 3942 secondary |= CPU_VINTD; 3943 vmcs_write(CPU_EXEC_CTRL1, secondary); 3944 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled"); 3945 test_vmx_invalid_controls(); 3946 report_prefix_pop(); 3947 3948 exit_ctl &= ~EXI_INTA; 3949 vmcs_write(EXI_CONTROLS, exit_ctl); 3950 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit disabled"); 3951 test_vmx_invalid_controls(); 3952 report_prefix_pop(); 3953 3954 exit_ctl |= EXI_INTA; 3955 vmcs_write(EXI_CONTROLS, exit_ctl); 3956 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 3957 test_vmx_valid_controls(); 3958 report_prefix_pop(); 3959 3960 secondary &= ~CPU_VINTD; 3961 vmcs_write(CPU_EXEC_CTRL1, secondary); 3962 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled; acknowledge-interrupt-on-exit enabled"); 3963 test_vmx_invalid_controls(); 3964 report_prefix_pop(); 3965 3966 secondary |= CPU_VINTD; 3967 vmcs_write(CPU_EXEC_CTRL1, secondary); 3968 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 3969 test_vmx_valid_controls(); 3970 report_prefix_pop(); 3971 3972 /* 3973 * Test posted-interrupt notification vector 3974 */ 3975 for (i = 0; i < 8; i++) { 3976 vec = (1ul << i); 3977 vmcs_write(PINV, vec); 3978 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 3979 test_vmx_valid_controls(); 3980 report_prefix_pop(); 3981 } 3982 for (i = 8; i < 16; i++) { 3983 vec = (1ul << i); 3984 vmcs_write(PINV, vec); 3985 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 3986 test_vmx_invalid_controls(); 3987 report_prefix_pop(); 3988 } 3989 3990 vec &= ~(0xff << 8); 3991 vmcs_write(PINV, vec); 3992 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 3993 test_vmx_valid_controls(); 3994 report_prefix_pop(); 3995 3996 /* 3997 * Test posted-interrupt descriptor addresss 3998 */ 3999 for (i = 0; i < 6; i++) { 4000 test_pi_desc_addr(1ul << i, false); 4001 } 4002 4003 test_pi_desc_addr(0xf0, false); 4004 test_pi_desc_addr(0xff, false); 4005 test_pi_desc_addr(0x0f, false); 4006 test_pi_desc_addr(0x8000, true); 4007 test_pi_desc_addr(0x00, true); 4008 test_pi_desc_addr(0xc000, true); 4009 4010 test_vmcs_addr_values("process-posted interrupts", 4011 POSTED_INTR_DESC_ADDR, 64, 4012 false, false, 0, 63); 4013 4014 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 4015 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 4016 vmcs_write(PIN_CONTROLS, saved_pin); 4017 } 4018 4019 static void test_apic_ctls(void) 4020 { 4021 test_apic_virt_addr(); 4022 test_apic_access_addr(); 4023 test_apic_virtual_ctls(); 4024 test_virtual_intr_ctls(); 4025 test_posted_intr(); 4026 } 4027 4028 /* 4029 * If the “enable VPID†VM-execution control is 1, the value of the 4030 * of the VPID VM-execution control field must not be 0000H. 4031 * [Intel SDM] 4032 */ 4033 static void test_vpid(void) 4034 { 4035 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 4036 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 4037 u16 vpid = 0x0000; 4038 int i; 4039 4040 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4041 (ctrl_cpu_rev[1].clr & CPU_VPID))) { 4042 printf("Secondary controls and/or VPID not supported\n"); 4043 return; 4044 } 4045 4046 vmcs_write(CPU_EXEC_CTRL0, saved_primary | CPU_SECONDARY); 4047 vmcs_write(CPU_EXEC_CTRL1, saved_secondary & ~CPU_VPID); 4048 vmcs_write(VPID, vpid); 4049 report_prefix_pushf("VPID disabled; VPID value %x", vpid); 4050 test_vmx_valid_controls(); 4051 report_prefix_pop(); 4052 4053 vmcs_write(CPU_EXEC_CTRL1, saved_secondary | CPU_VPID); 4054 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 4055 test_vmx_invalid_controls(); 4056 report_prefix_pop(); 4057 4058 for (i = 0; i < 16; i++) { 4059 vpid = (short)1 << i;; 4060 vmcs_write(VPID, vpid); 4061 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 4062 test_vmx_valid_controls(); 4063 report_prefix_pop(); 4064 } 4065 4066 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 4067 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 4068 } 4069 4070 static void set_vtpr(unsigned vtpr) 4071 { 4072 *(u32 *)phys_to_virt(vmcs_read(APIC_VIRT_ADDR) + APIC_TASKPRI) = vtpr; 4073 } 4074 4075 static void try_tpr_threshold_and_vtpr(unsigned threshold, unsigned vtpr) 4076 { 4077 bool valid = true; 4078 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4079 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4080 4081 if ((primary & CPU_TPR_SHADOW) && 4082 (!(primary & CPU_SECONDARY) || 4083 !(secondary & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 4084 valid = (threshold & 0xf) <= ((vtpr >> 4) & 0xf); 4085 4086 set_vtpr(vtpr); 4087 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0x%x", 4088 threshold, (vtpr >> 4) & 0xf); 4089 if (valid) 4090 test_vmx_valid_controls(); 4091 else 4092 test_vmx_invalid_controls(); 4093 report_prefix_pop(); 4094 } 4095 4096 static void test_invalid_event_injection(void) 4097 { 4098 u32 ent_intr_info_save = vmcs_read(ENT_INTR_INFO); 4099 u32 ent_intr_error_save = vmcs_read(ENT_INTR_ERROR); 4100 u32 ent_inst_len_save = vmcs_read(ENT_INST_LEN); 4101 u32 primary_save = vmcs_read(CPU_EXEC_CTRL0); 4102 u32 secondary_save = vmcs_read(CPU_EXEC_CTRL1); 4103 u64 guest_cr0_save = vmcs_read(GUEST_CR0); 4104 u32 ent_intr_info_base = INTR_INFO_VALID_MASK; 4105 u32 ent_intr_info, ent_intr_err, ent_intr_len; 4106 u32 cnt; 4107 4108 /* Setup */ 4109 report_prefix_push("invalid event injection"); 4110 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4111 vmcs_write(ENT_INST_LEN, 0x00000001); 4112 4113 /* The field’s interruption type is not set to a reserved value. */ 4114 ent_intr_info = ent_intr_info_base | INTR_TYPE_RESERVED | DE_VECTOR; 4115 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4116 "RESERVED interruption type invalid [-]", 4117 ent_intr_info); 4118 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4119 test_vmx_invalid_controls(); 4120 report_prefix_pop(); 4121 4122 ent_intr_info = ent_intr_info_base | INTR_TYPE_EXT_INTR | 4123 DE_VECTOR; 4124 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4125 "RESERVED interruption type invalid [+]", 4126 ent_intr_info); 4127 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4128 test_vmx_valid_controls(); 4129 report_prefix_pop(); 4130 4131 /* If the interruption type is other event, the vector is 0. */ 4132 ent_intr_info = ent_intr_info_base | INTR_TYPE_OTHER_EVENT | DB_VECTOR; 4133 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4134 "(OTHER EVENT && vector != 0) invalid [-]", 4135 ent_intr_info); 4136 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4137 test_vmx_invalid_controls(); 4138 report_prefix_pop(); 4139 4140 /* If the interruption type is NMI, the vector is 2 (negative case). */ 4141 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | DE_VECTOR; 4142 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4143 "(NMI && vector != 2) invalid [-]", ent_intr_info); 4144 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4145 test_vmx_invalid_controls(); 4146 report_prefix_pop(); 4147 4148 /* If the interruption type is NMI, the vector is 2 (positive case). */ 4149 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | NMI_VECTOR; 4150 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4151 "(NMI && vector == 2) valid [+]", ent_intr_info); 4152 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4153 test_vmx_valid_controls(); 4154 report_prefix_pop(); 4155 4156 /* 4157 * If the interruption type 4158 * is HW exception, the vector is at most 31. 4159 */ 4160 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 0x20; 4161 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4162 "(HW exception && vector > 31) invalid [-]", 4163 ent_intr_info); 4164 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4165 test_vmx_invalid_controls(); 4166 report_prefix_pop(); 4167 4168 /* 4169 * deliver-error-code is 1 iff either 4170 * (a) the "unrestricted guest" VM-execution control is 0 4171 * (b) CR0.PE is set. 4172 */ 4173 4174 /* Assert that unrestricted guest is disabled or unsupported */ 4175 assert(!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 4176 !(secondary_save & CPU_URG)); 4177 4178 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4179 GP_VECTOR; 4180 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4181 "error code <-> (!URG || prot_mode) [-]", 4182 ent_intr_info); 4183 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4184 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4185 test_vmx_invalid_controls(); 4186 report_prefix_pop(); 4187 4188 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4189 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4190 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4191 "error code <-> (!URG || prot_mode) [+]", 4192 ent_intr_info); 4193 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4194 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4195 test_vmx_valid_controls(); 4196 report_prefix_pop(); 4197 4198 if (enable_unrestricted_guest()) 4199 goto skip_unrestricted_guest; 4200 4201 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4202 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4203 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4204 "error code <-> (!URG || prot_mode) [-]", 4205 ent_intr_info); 4206 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4207 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4208 test_vmx_invalid_controls(); 4209 report_prefix_pop(); 4210 4211 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4212 GP_VECTOR; 4213 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4214 "error code <-> (!URG || prot_mode) [-]", 4215 ent_intr_info); 4216 vmcs_write(GUEST_CR0, guest_cr0_save | X86_CR0_PE); 4217 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4218 test_vmx_invalid_controls(); 4219 report_prefix_pop(); 4220 4221 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4222 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4223 4224 skip_unrestricted_guest: 4225 vmcs_write(GUEST_CR0, guest_cr0_save); 4226 4227 /* deliver-error-code is 1 iff the interruption type is HW exception */ 4228 report_prefix_push("error code <-> HW exception"); 4229 for (cnt = 0; cnt < 8; cnt++) { 4230 u32 exception_type_mask = cnt << 8; 4231 u32 deliver_error_code_mask = 4232 exception_type_mask != INTR_TYPE_HARD_EXCEPTION ? 4233 INTR_INFO_DELIVER_CODE_MASK : 0; 4234 4235 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4236 exception_type_mask | GP_VECTOR; 4237 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4238 ent_intr_info); 4239 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4240 test_vmx_invalid_controls(); 4241 report_prefix_pop(); 4242 } 4243 report_prefix_pop(); 4244 4245 /* 4246 * deliver-error-code is 1 iff the the vector 4247 * indicates an exception that would normally deliver an error code 4248 */ 4249 report_prefix_push("error code <-> vector delivers error code"); 4250 for (cnt = 0; cnt < 32; cnt++) { 4251 bool has_error_code = false; 4252 u32 deliver_error_code_mask; 4253 4254 switch (cnt) { 4255 case DF_VECTOR: 4256 case TS_VECTOR: 4257 case NP_VECTOR: 4258 case SS_VECTOR: 4259 case GP_VECTOR: 4260 case PF_VECTOR: 4261 case AC_VECTOR: 4262 has_error_code = true; 4263 } 4264 4265 /* Negative case */ 4266 deliver_error_code_mask = has_error_code ? 4267 0 : 4268 INTR_INFO_DELIVER_CODE_MASK; 4269 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4270 INTR_TYPE_HARD_EXCEPTION | cnt; 4271 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4272 ent_intr_info); 4273 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4274 test_vmx_invalid_controls(); 4275 report_prefix_pop(); 4276 4277 /* Positive case */ 4278 deliver_error_code_mask = has_error_code ? 4279 INTR_INFO_DELIVER_CODE_MASK : 4280 0; 4281 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4282 INTR_TYPE_HARD_EXCEPTION | cnt; 4283 report_prefix_pushf("VM-entry intr info=0x%x [+]", 4284 ent_intr_info); 4285 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4286 test_vmx_valid_controls(); 4287 report_prefix_pop(); 4288 } 4289 report_prefix_pop(); 4290 4291 /* Reserved bits in the field (30:12) are 0. */ 4292 report_prefix_push("reserved bits clear"); 4293 for (cnt = 12; cnt <= 30; cnt++) { 4294 ent_intr_info = ent_intr_info_base | 4295 INTR_INFO_DELIVER_CODE_MASK | 4296 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR | 4297 (1U << cnt); 4298 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4299 ent_intr_info); 4300 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4301 test_vmx_invalid_controls(); 4302 report_prefix_pop(); 4303 } 4304 report_prefix_pop(); 4305 4306 /* 4307 * If deliver-error-code is 1 4308 * bits 31:16 of the VM-entry exception error-code field are 0. 4309 */ 4310 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4311 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4312 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4313 "VM-entry exception error code[31:16] clear", 4314 ent_intr_info); 4315 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4316 for (cnt = 16; cnt <= 31; cnt++) { 4317 ent_intr_err = 1U << cnt; 4318 report_prefix_pushf("VM-entry intr error=0x%x [-]", 4319 ent_intr_err); 4320 vmcs_write(ENT_INTR_ERROR, ent_intr_err); 4321 test_vmx_invalid_controls(); 4322 report_prefix_pop(); 4323 } 4324 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4325 report_prefix_pop(); 4326 4327 /* 4328 * If the interruption type is software interrupt, software exception, 4329 * or privileged software exception, the VM-entry instruction-length 4330 * field is in the range 0–15. 4331 */ 4332 4333 for (cnt = 0; cnt < 3; cnt++) { 4334 switch (cnt) { 4335 case 0: 4336 ent_intr_info = ent_intr_info_base | 4337 INTR_TYPE_SOFT_INTR; 4338 break; 4339 case 1: 4340 ent_intr_info = ent_intr_info_base | 4341 INTR_TYPE_SOFT_EXCEPTION; 4342 break; 4343 case 2: 4344 ent_intr_info = ent_intr_info_base | 4345 INTR_TYPE_PRIV_SW_EXCEPTION; 4346 break; 4347 } 4348 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4349 "VM-entry instruction-length check", 4350 ent_intr_info); 4351 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4352 4353 /* Instruction length set to -1 (0xFFFFFFFF) should fail */ 4354 ent_intr_len = -1; 4355 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4356 ent_intr_len); 4357 vmcs_write(ENT_INST_LEN, ent_intr_len); 4358 test_vmx_invalid_controls(); 4359 report_prefix_pop(); 4360 4361 /* Instruction length set to 16 should fail */ 4362 ent_intr_len = 0x00000010; 4363 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4364 ent_intr_len); 4365 vmcs_write(ENT_INST_LEN, 0x00000010); 4366 test_vmx_invalid_controls(); 4367 report_prefix_pop(); 4368 4369 report_prefix_pop(); 4370 } 4371 4372 /* Cleanup */ 4373 vmcs_write(ENT_INTR_INFO, ent_intr_info_save); 4374 vmcs_write(ENT_INTR_ERROR, ent_intr_error_save); 4375 vmcs_write(ENT_INST_LEN, ent_inst_len_save); 4376 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4377 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4378 vmcs_write(GUEST_CR0, guest_cr0_save); 4379 report_prefix_pop(); 4380 } 4381 4382 /* 4383 * Test interesting vTPR values for a given TPR threshold. 4384 */ 4385 static void test_vtpr_values(unsigned threshold) 4386 { 4387 try_tpr_threshold_and_vtpr(threshold, (threshold - 1) << 4); 4388 try_tpr_threshold_and_vtpr(threshold, threshold << 4); 4389 try_tpr_threshold_and_vtpr(threshold, (threshold + 1) << 4); 4390 } 4391 4392 static void try_tpr_threshold(unsigned threshold) 4393 { 4394 bool valid = true; 4395 4396 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4397 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4398 4399 if ((primary & CPU_TPR_SHADOW) && !((primary & CPU_SECONDARY) && 4400 (secondary & CPU_VINTD))) 4401 valid = !(threshold >> 4); 4402 4403 set_vtpr(-1); 4404 vmcs_write(TPR_THRESHOLD, threshold); 4405 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0xf", threshold); 4406 if (valid) 4407 test_vmx_valid_controls(); 4408 else 4409 test_vmx_invalid_controls(); 4410 report_prefix_pop(); 4411 4412 if (valid) 4413 test_vtpr_values(threshold); 4414 } 4415 4416 /* 4417 * Test interesting TPR threshold values. 4418 */ 4419 static void test_tpr_threshold_values(void) 4420 { 4421 unsigned i; 4422 4423 for (i = 0; i < 0x10; i++) 4424 try_tpr_threshold(i); 4425 for (i = 4; i < 32; i++) 4426 try_tpr_threshold(1u << i); 4427 try_tpr_threshold(-1u); 4428 try_tpr_threshold(0x7fffffff); 4429 } 4430 4431 /* 4432 * This test covers the following two VM entry checks: 4433 * 4434 * i) If the "use TPR shadow" VM-execution control is 1 and the 4435 * "virtual-interrupt delivery" VM-execution control is 0, bits 4436 * 31:4 of the TPR threshold VM-execution control field must 4437 be 0. 4438 * [Intel SDM] 4439 * 4440 * ii) If the "use TPR shadow" VM-execution control is 1, the 4441 * "virtual-interrupt delivery" VM-execution control is 0 4442 * and the "virtualize APIC accesses" VM-execution control 4443 * is 0, the value of bits 3:0 of the TPR threshold VM-execution 4444 * control field must not be greater than the value of bits 4445 * 7:4 of VTPR. 4446 * [Intel SDM] 4447 */ 4448 static void test_tpr_threshold(void) 4449 { 4450 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4451 u64 apic_virt_addr = vmcs_read(APIC_VIRT_ADDR); 4452 u64 threshold = vmcs_read(TPR_THRESHOLD); 4453 void *virtual_apic_page; 4454 4455 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) 4456 return; 4457 4458 virtual_apic_page = alloc_page(); 4459 memset(virtual_apic_page, 0xff, PAGE_SIZE); 4460 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 4461 4462 vmcs_write(CPU_EXEC_CTRL0, primary & ~(CPU_TPR_SHADOW | CPU_SECONDARY)); 4463 report_prefix_pushf("Use TPR shadow disabled, secondary controls disabled"); 4464 test_tpr_threshold_values(); 4465 report_prefix_pop(); 4466 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_TPR_SHADOW); 4467 report_prefix_pushf("Use TPR shadow enabled, secondary controls disabled"); 4468 test_tpr_threshold_values(); 4469 report_prefix_pop(); 4470 4471 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4472 (ctrl_cpu_rev[1].clr & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 4473 goto out; 4474 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4475 4476 if (ctrl_cpu_rev[1].clr & CPU_VINTD) { 4477 vmcs_write(CPU_EXEC_CTRL1, CPU_VINTD); 4478 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4479 test_tpr_threshold_values(); 4480 report_prefix_pop(); 4481 4482 vmcs_write(CPU_EXEC_CTRL0, 4483 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4484 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4485 test_tpr_threshold_values(); 4486 report_prefix_pop(); 4487 } 4488 4489 if (ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES) { 4490 vmcs_write(CPU_EXEC_CTRL0, 4491 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4492 vmcs_write(CPU_EXEC_CTRL1, CPU_VIRT_APIC_ACCESSES); 4493 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4494 test_tpr_threshold_values(); 4495 report_prefix_pop(); 4496 4497 vmcs_write(CPU_EXEC_CTRL0, 4498 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4499 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4500 test_tpr_threshold_values(); 4501 report_prefix_pop(); 4502 } 4503 4504 if ((ctrl_cpu_rev[1].clr & 4505 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) == 4506 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) { 4507 vmcs_write(CPU_EXEC_CTRL0, 4508 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4509 vmcs_write(CPU_EXEC_CTRL1, 4510 CPU_VINTD | CPU_VIRT_APIC_ACCESSES); 4511 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4512 test_tpr_threshold_values(); 4513 report_prefix_pop(); 4514 4515 vmcs_write(CPU_EXEC_CTRL0, 4516 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4517 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4518 test_tpr_threshold_values(); 4519 report_prefix_pop(); 4520 } 4521 4522 vmcs_write(CPU_EXEC_CTRL1, secondary); 4523 out: 4524 vmcs_write(TPR_THRESHOLD, threshold); 4525 vmcs_write(APIC_VIRT_ADDR, apic_virt_addr); 4526 vmcs_write(CPU_EXEC_CTRL0, primary); 4527 } 4528 4529 /* 4530 * This test verifies the following two vmentry checks: 4531 * 4532 * If the "NMI exiting" VM-execution control is 0, "Virtual NMIs" 4533 * VM-execution control must be 0. 4534 * [Intel SDM] 4535 * 4536 * If the “virtual NMIs” VM-execution control is 0, the “NMI-window 4537 * exiting” VM-execution control must be 0. 4538 * [Intel SDM] 4539 */ 4540 static void test_nmi_ctrls(void) 4541 { 4542 u32 pin_ctrls, cpu_ctrls0, test_pin_ctrls, test_cpu_ctrls0; 4543 4544 if ((ctrl_pin_rev.clr & (PIN_NMI | PIN_VIRT_NMI)) != 4545 (PIN_NMI | PIN_VIRT_NMI)) { 4546 printf("NMI exiting and Virtual NMIs are not supported !\n"); 4547 return; 4548 } 4549 4550 /* Save the controls so that we can restore them after our tests */ 4551 pin_ctrls = vmcs_read(PIN_CONTROLS); 4552 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 4553 4554 test_pin_ctrls = pin_ctrls & ~(PIN_NMI | PIN_VIRT_NMI); 4555 test_cpu_ctrls0 = cpu_ctrls0 & ~CPU_NMI_WINDOW; 4556 4557 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4558 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs disabled"); 4559 test_vmx_valid_controls(); 4560 report_prefix_pop(); 4561 4562 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_VIRT_NMI); 4563 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs enabled"); 4564 test_vmx_invalid_controls(); 4565 report_prefix_pop(); 4566 4567 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4568 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs enabled"); 4569 test_vmx_valid_controls(); 4570 report_prefix_pop(); 4571 4572 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_NMI); 4573 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs disabled"); 4574 test_vmx_valid_controls(); 4575 report_prefix_pop(); 4576 4577 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 4578 report_info("NMI-window exiting is not supported, skipping..."); 4579 goto done; 4580 } 4581 4582 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4583 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4584 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting enabled"); 4585 test_vmx_invalid_controls(); 4586 report_prefix_pop(); 4587 4588 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4589 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4590 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting disabled"); 4591 test_vmx_valid_controls(); 4592 report_prefix_pop(); 4593 4594 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4595 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4596 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting enabled"); 4597 test_vmx_valid_controls(); 4598 report_prefix_pop(); 4599 4600 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4601 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4602 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting disabled"); 4603 test_vmx_valid_controls(); 4604 report_prefix_pop(); 4605 4606 /* Restore the controls to their original values */ 4607 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 4608 done: 4609 vmcs_write(PIN_CONTROLS, pin_ctrls); 4610 } 4611 4612 static void test_eptp_ad_bit(u64 eptp, bool ctrl) 4613 { 4614 vmcs_write(EPTP, eptp); 4615 report_prefix_pushf("Enable-EPT enabled; EPT accessed and dirty flag %s", 4616 (eptp & EPTP_AD_FLAG) ? "1": "0"); 4617 if (ctrl) 4618 test_vmx_valid_controls(); 4619 else 4620 test_vmx_invalid_controls(); 4621 report_prefix_pop(); 4622 4623 } 4624 4625 /* 4626 * 1. If the "enable EPT" VM-execution control is 1, the "EPTP VM-execution" 4627 * control field must satisfy the following checks: 4628 * 4629 * - The EPT memory type (bits 2:0) must be a value supported by the 4630 * processor as indicated in the IA32_VMX_EPT_VPID_CAP MSR. 4631 * - Bits 5:3 (1 less than the EPT page-walk length) must be 3, 4632 * indicating an EPT page-walk length of 4. 4633 * - Bit 6 (enable bit for accessed and dirty flags for EPT) must be 4634 * 0 if bit 21 of the IA32_VMX_EPT_VPID_CAP MSR is read as 0, 4635 * indicating that the processor does not support accessed and dirty 4636 * dirty flags for EPT. 4637 * - Reserved bits 11:7 and 63:N (where N is the processor's 4638 * physical-address width) must all be 0. 4639 * 4640 * 2. If the "unrestricted guest" VM-execution control is 1, the 4641 * "enable EPT" VM-execution control must also be 1. 4642 */ 4643 static void test_ept_eptp(void) 4644 { 4645 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4646 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4647 u64 eptp_saved = vmcs_read(EPTP); 4648 u32 primary = primary_saved; 4649 u32 secondary = secondary_saved; 4650 u64 msr, eptp = eptp_saved; 4651 bool un_cache = false; 4652 bool wr_bk = false; 4653 bool ctrl; 4654 u32 i, maxphysaddr; 4655 u64 j, resv_bits_mask = 0; 4656 4657 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4658 (ctrl_cpu_rev[1].clr & CPU_EPT))) { 4659 printf("\"CPU secondary\" and/or \"enable EPT\" execution controls are not supported !\n"); 4660 return; 4661 } 4662 4663 /* 4664 * Memory type (bits 2:0) 4665 */ 4666 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 4667 if (msr & EPT_CAP_UC) 4668 un_cache = true; 4669 if (msr & EPT_CAP_WB) 4670 wr_bk = true; 4671 4672 primary |= CPU_SECONDARY; 4673 vmcs_write(CPU_EXEC_CTRL0, primary); 4674 secondary |= CPU_EPT; 4675 vmcs_write(CPU_EXEC_CTRL1, secondary); 4676 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4677 (3ul << EPTP_PG_WALK_LEN_SHIFT); 4678 vmcs_write(EPTP, eptp); 4679 4680 for (i = 0; i < 8; i++) { 4681 if (i == 0) { 4682 if (un_cache) { 4683 report_info("EPT paging structure memory-type is Un-cacheable\n"); 4684 ctrl = true; 4685 } else { 4686 ctrl = false; 4687 } 4688 } else if (i == 6) { 4689 if (wr_bk) { 4690 report_info("EPT paging structure memory-type is Write-back\n"); 4691 ctrl = true; 4692 } else { 4693 ctrl = false; 4694 } 4695 } else { 4696 ctrl = false; 4697 } 4698 4699 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | i; 4700 vmcs_write(EPTP, eptp); 4701 report_prefix_pushf("Enable-EPT enabled; EPT memory type %lu", 4702 eptp & EPT_MEM_TYPE_MASK); 4703 if (ctrl) 4704 test_vmx_valid_controls(); 4705 else 4706 test_vmx_invalid_controls(); 4707 report_prefix_pop(); 4708 } 4709 4710 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | 6ul; 4711 4712 /* 4713 * Page walk length (bits 5:3) 4714 */ 4715 for (i = 0; i < 8; i++) { 4716 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4717 (i << EPTP_PG_WALK_LEN_SHIFT); 4718 if (i == 3) 4719 ctrl = true; 4720 else 4721 ctrl = false; 4722 4723 vmcs_write(EPTP, eptp); 4724 report_prefix_pushf("Enable-EPT enabled; EPT page walk length %lu", 4725 eptp & EPTP_PG_WALK_LEN_MASK); 4726 if (ctrl) 4727 test_vmx_valid_controls(); 4728 else 4729 test_vmx_invalid_controls(); 4730 report_prefix_pop(); 4731 } 4732 4733 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4734 3ul << EPTP_PG_WALK_LEN_SHIFT; 4735 4736 /* 4737 * Accessed and dirty flag (bit 6) 4738 */ 4739 if (msr & EPT_CAP_AD_FLAG) { 4740 report_info("Processor supports accessed and dirty flag"); 4741 eptp &= ~EPTP_AD_FLAG; 4742 test_eptp_ad_bit(eptp, true); 4743 4744 eptp |= EPTP_AD_FLAG; 4745 test_eptp_ad_bit(eptp, true); 4746 } else { 4747 report_info("Processor does not supports accessed and dirty flag"); 4748 eptp &= ~EPTP_AD_FLAG; 4749 test_eptp_ad_bit(eptp, true); 4750 4751 eptp |= EPTP_AD_FLAG; 4752 test_eptp_ad_bit(eptp, false); 4753 } 4754 4755 /* 4756 * Reserved bits [11:7] and [63:N] 4757 */ 4758 for (i = 0; i < 32; i++) { 4759 eptp = (eptp & 4760 ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)) | 4761 (i << EPTP_RESERV_BITS_SHIFT); 4762 vmcs_write(EPTP, eptp); 4763 report_prefix_pushf("Enable-EPT enabled; reserved bits [11:7] %lu", 4764 (eptp >> EPTP_RESERV_BITS_SHIFT) & 4765 EPTP_RESERV_BITS_MASK); 4766 if (i == 0) 4767 test_vmx_valid_controls(); 4768 else 4769 test_vmx_invalid_controls(); 4770 report_prefix_pop(); 4771 } 4772 4773 eptp = (eptp & ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)); 4774 4775 maxphysaddr = cpuid_maxphyaddr(); 4776 for (i = 0; i < (63 - maxphysaddr + 1); i++) { 4777 resv_bits_mask |= 1ul << i; 4778 } 4779 4780 for (j = maxphysaddr - 1; j <= 63; j++) { 4781 eptp = (eptp & ~(resv_bits_mask << maxphysaddr)) | 4782 (j < maxphysaddr ? 0 : 1ul << j); 4783 vmcs_write(EPTP, eptp); 4784 report_prefix_pushf("Enable-EPT enabled; reserved bits [63:N] %lu", 4785 (eptp >> maxphysaddr) & resv_bits_mask); 4786 if (j < maxphysaddr) 4787 test_vmx_valid_controls(); 4788 else 4789 test_vmx_invalid_controls(); 4790 report_prefix_pop(); 4791 } 4792 4793 secondary &= ~(CPU_EPT | CPU_URG); 4794 vmcs_write(CPU_EXEC_CTRL1, secondary); 4795 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest disabled"); 4796 test_vmx_valid_controls(); 4797 report_prefix_pop(); 4798 4799 if (!(ctrl_cpu_rev[1].clr & CPU_URG)) 4800 goto skip_unrestricted_guest; 4801 4802 secondary |= CPU_URG; 4803 vmcs_write(CPU_EXEC_CTRL1, secondary); 4804 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest enabled"); 4805 test_vmx_invalid_controls(); 4806 report_prefix_pop(); 4807 4808 secondary |= CPU_EPT; 4809 setup_dummy_ept(); 4810 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest enabled"); 4811 test_vmx_valid_controls(); 4812 report_prefix_pop(); 4813 4814 skip_unrestricted_guest: 4815 secondary &= ~CPU_URG; 4816 vmcs_write(CPU_EXEC_CTRL1, secondary); 4817 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest disabled"); 4818 test_vmx_valid_controls(); 4819 report_prefix_pop(); 4820 4821 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4822 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4823 vmcs_write(EPTP, eptp_saved); 4824 } 4825 4826 /* 4827 * If the 'enable PML' VM-execution control is 1, the 'enable EPT' 4828 * VM-execution control must also be 1. In addition, the PML address 4829 * must satisfy the following checks: 4830 * 4831 * * Bits 11:0 of the address must be 0. 4832 * * The address should not set any bits beyond the processor's 4833 * physical-address width. 4834 * 4835 * [Intel SDM] 4836 */ 4837 static void test_pml(void) 4838 { 4839 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4840 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4841 u32 primary = primary_saved; 4842 u32 secondary = secondary_saved; 4843 4844 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4845 (ctrl_cpu_rev[1].clr & CPU_EPT) && (ctrl_cpu_rev[1].clr & CPU_PML))) { 4846 printf("\"Secondary execution\" control or \"enable EPT\" control or \"enable PML\" control is not supported !\n"); 4847 return; 4848 } 4849 4850 primary |= CPU_SECONDARY; 4851 vmcs_write(CPU_EXEC_CTRL0, primary); 4852 secondary &= ~(CPU_PML | CPU_EPT); 4853 vmcs_write(CPU_EXEC_CTRL1, secondary); 4854 report_prefix_pushf("enable-PML disabled, enable-EPT disabled"); 4855 test_vmx_valid_controls(); 4856 report_prefix_pop(); 4857 4858 secondary |= CPU_PML; 4859 vmcs_write(CPU_EXEC_CTRL1, secondary); 4860 report_prefix_pushf("enable-PML enabled, enable-EPT disabled"); 4861 test_vmx_invalid_controls(); 4862 report_prefix_pop(); 4863 4864 secondary |= CPU_EPT; 4865 setup_dummy_ept(); 4866 report_prefix_pushf("enable-PML enabled, enable-EPT enabled"); 4867 test_vmx_valid_controls(); 4868 report_prefix_pop(); 4869 4870 secondary &= ~CPU_PML; 4871 vmcs_write(CPU_EXEC_CTRL1, secondary); 4872 report_prefix_pushf("enable-PML disabled, enable EPT enabled"); 4873 test_vmx_valid_controls(); 4874 report_prefix_pop(); 4875 4876 test_vmcs_addr_reference(CPU_PML, PMLADDR, "PML address", "PML", 4877 PAGE_SIZE, false, false); 4878 4879 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4880 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4881 } 4882 4883 /* 4884 * If the "activate VMX-preemption timer" VM-execution control is 0, the 4885 * the "save VMX-preemption timer value" VM-exit control must also be 0. 4886 * 4887 * [Intel SDM] 4888 */ 4889 static void test_vmx_preemption_timer(void) 4890 { 4891 u32 saved_pin = vmcs_read(PIN_CONTROLS); 4892 u32 saved_exit = vmcs_read(EXI_CONTROLS); 4893 u32 pin = saved_pin; 4894 u32 exit = saved_exit; 4895 4896 if (!((ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) || 4897 (ctrl_pin_rev.clr & PIN_PREEMPT))) { 4898 printf("\"Save-VMX-preemption-timer\" control and/or \"Enable-VMX-preemption-timer\" control is not supported\n"); 4899 return; 4900 } 4901 4902 pin |= PIN_PREEMPT; 4903 vmcs_write(PIN_CONTROLS, pin); 4904 exit &= ~EXI_SAVE_PREEMPT; 4905 vmcs_write(EXI_CONTROLS, exit); 4906 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer disabled"); 4907 test_vmx_valid_controls(); 4908 report_prefix_pop(); 4909 4910 exit |= EXI_SAVE_PREEMPT; 4911 vmcs_write(EXI_CONTROLS, exit); 4912 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer enabled"); 4913 test_vmx_valid_controls(); 4914 report_prefix_pop(); 4915 4916 pin &= ~PIN_PREEMPT; 4917 vmcs_write(PIN_CONTROLS, pin); 4918 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer enabled"); 4919 test_vmx_invalid_controls(); 4920 report_prefix_pop(); 4921 4922 exit &= ~EXI_SAVE_PREEMPT; 4923 vmcs_write(EXI_CONTROLS, exit); 4924 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer disabled"); 4925 test_vmx_valid_controls(); 4926 report_prefix_pop(); 4927 4928 vmcs_write(PIN_CONTROLS, saved_pin); 4929 vmcs_write(EXI_CONTROLS, saved_exit); 4930 } 4931 4932 /* 4933 * Tests for VM-execution control fields 4934 */ 4935 static void test_vm_execution_ctls(void) 4936 { 4937 test_pin_based_ctls(); 4938 test_primary_processor_based_ctls(); 4939 test_secondary_processor_based_ctls(); 4940 test_cr3_targets(); 4941 test_io_bitmaps(); 4942 test_msr_bitmap(); 4943 test_apic_ctls(); 4944 test_tpr_threshold(); 4945 test_nmi_ctrls(); 4946 test_pml(); 4947 test_vpid(); 4948 test_ept_eptp(); 4949 test_vmx_preemption_timer(); 4950 } 4951 4952 /* 4953 * The following checks are performed for the VM-entry MSR-load address if 4954 * the VM-entry MSR-load count field is non-zero: 4955 * 4956 * - The lower 4 bits of the VM-entry MSR-load address must be 0. 4957 * The address should not set any bits beyond the processor’s 4958 * physical-address width. 4959 * 4960 * - The address of the last byte in the VM-entry MSR-load area 4961 * should not set any bits beyond the processor’s physical-address 4962 * width. The address of this last byte is VM-entry MSR-load address 4963 * + (MSR count * 16) - 1. (The arithmetic used for the computation 4964 * uses more bits than the processor’s physical-address width.) 4965 * 4966 * 4967 * [Intel SDM] 4968 */ 4969 static void test_entry_msr_load(void) 4970 { 4971 entry_msr_load = alloc_page(); 4972 u64 tmp; 4973 u32 entry_msr_ld_cnt = 1; 4974 int i; 4975 u32 addr_len = 64; 4976 4977 vmcs_write(ENT_MSR_LD_CNT, entry_msr_ld_cnt); 4978 4979 /* Check first 4 bits of VM-entry MSR-load address */ 4980 for (i = 0; i < 4; i++) { 4981 tmp = (u64)entry_msr_load | 1ull << i; 4982 vmcs_write(ENTER_MSR_LD_ADDR, tmp); 4983 report_prefix_pushf("VM-entry MSR-load addr [4:0] %lx", 4984 tmp & 0xf); 4985 test_vmx_invalid_controls(); 4986 report_prefix_pop(); 4987 } 4988 4989 if (basic.val & (1ul << 48)) 4990 addr_len = 32; 4991 4992 test_vmcs_addr_values("VM-entry-MSR-load address", 4993 ENTER_MSR_LD_ADDR, 16, false, false, 4994 4, addr_len - 1); 4995 4996 /* 4997 * Check last byte of VM-entry MSR-load address 4998 */ 4999 entry_msr_load = (struct vmx_msr_entry *)((u64)entry_msr_load & ~0xf); 5000 5001 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 5002 i < 64; i++) { 5003 tmp = ((u64)entry_msr_load + entry_msr_ld_cnt * 16 - 1) | 5004 1ul << i; 5005 vmcs_write(ENTER_MSR_LD_ADDR, 5006 tmp - (entry_msr_ld_cnt * 16 - 1)); 5007 test_vmx_invalid_controls(); 5008 } 5009 5010 vmcs_write(ENT_MSR_LD_CNT, 2); 5011 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 5012 test_vmx_invalid_controls(); 5013 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 5014 test_vmx_valid_controls(); 5015 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 5016 test_vmx_valid_controls(); 5017 } 5018 5019 static void guest_state_test_main(void) 5020 { 5021 while (1) { 5022 if (vmx_get_test_stage() != 2) 5023 vmcall(); 5024 else 5025 break; 5026 } 5027 5028 asm volatile("fnop"); 5029 } 5030 5031 static void advance_guest_state_test(void) 5032 { 5033 u32 reason = vmcs_read(EXI_REASON); 5034 if (! (reason & 0x80000000)) { 5035 u64 guest_rip = vmcs_read(GUEST_RIP); 5036 u32 insn_len = vmcs_read(EXI_INST_LEN); 5037 vmcs_write(GUEST_RIP, guest_rip + insn_len); 5038 } 5039 } 5040 5041 static void report_guest_state_test(const char *test, u32 xreason, 5042 u64 field, const char * field_name) 5043 { 5044 u32 reason = vmcs_read(EXI_REASON); 5045 5046 report("%s, %s %lx", reason == xreason, test, field_name, field); 5047 advance_guest_state_test(); 5048 } 5049 5050 /* 5051 * Tests for VM-entry control fields 5052 */ 5053 static void test_vm_entry_ctls(void) 5054 { 5055 test_invalid_event_injection(); 5056 test_entry_msr_load(); 5057 } 5058 5059 /* 5060 * The following checks are performed for the VM-exit MSR-store address if 5061 * the VM-exit MSR-store count field is non-zero: 5062 * 5063 * - The lower 4 bits of the VM-exit MSR-store address must be 0. 5064 * The address should not set any bits beyond the processor’s 5065 * physical-address width. 5066 * 5067 * - The address of the last byte in the VM-exit MSR-store area 5068 * should not set any bits beyond the processor’s physical-address 5069 * width. The address of this last byte is VM-exit MSR-store address 5070 * + (MSR count * 16) - 1. (The arithmetic used for the computation 5071 * uses more bits than the processor’s physical-address width.) 5072 * 5073 * If IA32_VMX_BASIC[48] is read as 1, neither address should set any bits 5074 * in the range 63:32. 5075 * 5076 * [Intel SDM] 5077 */ 5078 static void test_exit_msr_store(void) 5079 { 5080 exit_msr_store = alloc_page(); 5081 u64 tmp; 5082 u32 exit_msr_st_cnt = 1; 5083 int i; 5084 u32 addr_len = 64; 5085 5086 vmcs_write(EXI_MSR_ST_CNT, exit_msr_st_cnt); 5087 5088 /* Check first 4 bits of VM-exit MSR-store address */ 5089 for (i = 0; i < 4; i++) { 5090 tmp = (u64)exit_msr_store | 1ull << i; 5091 vmcs_write(EXIT_MSR_ST_ADDR, tmp); 5092 report_prefix_pushf("VM-exit MSR-store addr [4:0] %lx", 5093 tmp & 0xf); 5094 test_vmx_invalid_controls(); 5095 report_prefix_pop(); 5096 } 5097 5098 if (basic.val & (1ul << 48)) 5099 addr_len = 32; 5100 5101 test_vmcs_addr_values("VM-exit-MSR-store address", 5102 EXIT_MSR_ST_ADDR, 16, false, false, 5103 4, addr_len - 1); 5104 5105 /* 5106 * Check last byte of VM-exit MSR-store address 5107 */ 5108 exit_msr_store = (struct vmx_msr_entry *)((u64)exit_msr_store & ~0xf); 5109 5110 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 5111 i < 64; i++) { 5112 tmp = ((u64)exit_msr_store + exit_msr_st_cnt * 16 - 1) | 5113 1ul << i; 5114 vmcs_write(EXIT_MSR_ST_ADDR, 5115 tmp - (exit_msr_st_cnt * 16 - 1)); 5116 test_vmx_invalid_controls(); 5117 } 5118 5119 vmcs_write(EXI_MSR_ST_CNT, 2); 5120 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 5121 test_vmx_invalid_controls(); 5122 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 5123 test_vmx_valid_controls(); 5124 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 5125 test_vmx_valid_controls(); 5126 } 5127 5128 /* 5129 * Tests for VM-exit controls 5130 */ 5131 static void test_vm_exit_ctls(void) 5132 { 5133 test_exit_msr_store(); 5134 } 5135 5136 /* 5137 * Check that the virtual CPU checks all of the VMX controls as 5138 * documented in the Intel SDM. 5139 */ 5140 static void vmx_controls_test(void) 5141 { 5142 /* 5143 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 5144 * fail due to invalid guest state, should we make it that 5145 * far. 5146 */ 5147 vmcs_write(GUEST_RFLAGS, 0); 5148 5149 test_vm_execution_ctls(); 5150 test_vm_exit_ctls(); 5151 test_vm_entry_ctls(); 5152 } 5153 5154 struct apic_reg_virt_config { 5155 bool apic_register_virtualization; 5156 bool use_tpr_shadow; 5157 bool virtualize_apic_accesses; 5158 bool virtualize_x2apic_mode; 5159 bool activate_secondary_controls; 5160 }; 5161 5162 struct apic_reg_test { 5163 const char *name; 5164 struct apic_reg_virt_config apic_reg_virt_config; 5165 }; 5166 5167 struct apic_reg_virt_expectation { 5168 enum Reason rd_exit_reason; 5169 enum Reason wr_exit_reason; 5170 u32 val; 5171 u32 (*virt_fn)(u32); 5172 5173 /* 5174 * If false, accessing the APIC access address from L2 is treated as a 5175 * normal memory operation, rather than triggering virtualization. 5176 */ 5177 bool virtualize_apic_accesses; 5178 }; 5179 5180 static u32 apic_virt_identity(u32 val) 5181 { 5182 return val; 5183 } 5184 5185 static u32 apic_virt_nibble1(u32 val) 5186 { 5187 return val & 0xf0; 5188 } 5189 5190 static u32 apic_virt_byte3(u32 val) 5191 { 5192 return val & (0xff << 24); 5193 } 5194 5195 static bool apic_reg_virt_exit_expectation( 5196 u32 reg, struct apic_reg_virt_config *config, 5197 struct apic_reg_virt_expectation *expectation) 5198 { 5199 /* Good configs, where some L2 APIC accesses are virtualized. */ 5200 bool virtualize_apic_accesses_only = 5201 config->virtualize_apic_accesses && 5202 !config->use_tpr_shadow && 5203 !config->apic_register_virtualization && 5204 !config->virtualize_x2apic_mode && 5205 config->activate_secondary_controls; 5206 bool virtualize_apic_accesses_and_use_tpr_shadow = 5207 config->virtualize_apic_accesses && 5208 config->use_tpr_shadow && 5209 !config->apic_register_virtualization && 5210 !config->virtualize_x2apic_mode && 5211 config->activate_secondary_controls; 5212 bool apic_register_virtualization = 5213 config->virtualize_apic_accesses && 5214 config->use_tpr_shadow && 5215 config->apic_register_virtualization && 5216 !config->virtualize_x2apic_mode && 5217 config->activate_secondary_controls; 5218 5219 expectation->val = MAGIC_VAL_1; 5220 expectation->virt_fn = apic_virt_identity; 5221 expectation->virtualize_apic_accesses = 5222 config->virtualize_apic_accesses && 5223 config->activate_secondary_controls; 5224 if (virtualize_apic_accesses_only) { 5225 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5226 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5227 } else if (virtualize_apic_accesses_and_use_tpr_shadow) { 5228 switch (reg) { 5229 case APIC_TASKPRI: 5230 expectation->rd_exit_reason = VMX_VMCALL; 5231 expectation->wr_exit_reason = VMX_VMCALL; 5232 expectation->virt_fn = apic_virt_nibble1; 5233 break; 5234 default: 5235 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5236 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5237 } 5238 } else if (apic_register_virtualization) { 5239 expectation->rd_exit_reason = VMX_VMCALL; 5240 5241 switch (reg) { 5242 case APIC_ID: 5243 case APIC_EOI: 5244 case APIC_LDR: 5245 case APIC_DFR: 5246 case APIC_SPIV: 5247 case APIC_ESR: 5248 case APIC_ICR: 5249 case APIC_LVTT: 5250 case APIC_LVTTHMR: 5251 case APIC_LVTPC: 5252 case APIC_LVT0: 5253 case APIC_LVT1: 5254 case APIC_LVTERR: 5255 case APIC_TMICT: 5256 case APIC_TDCR: 5257 expectation->wr_exit_reason = VMX_APIC_WRITE; 5258 break; 5259 case APIC_LVR: 5260 case APIC_ISR ... APIC_ISR + 0x70: 5261 case APIC_TMR ... APIC_TMR + 0x70: 5262 case APIC_IRR ... APIC_IRR + 0x70: 5263 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5264 break; 5265 case APIC_TASKPRI: 5266 expectation->wr_exit_reason = VMX_VMCALL; 5267 expectation->virt_fn = apic_virt_nibble1; 5268 break; 5269 case APIC_ICR2: 5270 expectation->wr_exit_reason = VMX_VMCALL; 5271 expectation->virt_fn = apic_virt_byte3; 5272 break; 5273 default: 5274 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5275 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5276 } 5277 } else if (!expectation->virtualize_apic_accesses) { 5278 /* 5279 * No APIC registers are directly virtualized. This includes 5280 * VTPR, which can be virtualized through MOV to/from CR8 via 5281 * the use TPR shadow control, but not through directly 5282 * accessing VTPR. 5283 */ 5284 expectation->rd_exit_reason = VMX_VMCALL; 5285 expectation->wr_exit_reason = VMX_VMCALL; 5286 } else { 5287 printf("Cannot parse APIC register virtualization config:\n" 5288 "\tvirtualize_apic_accesses: %d\n" 5289 "\tuse_tpr_shadow: %d\n" 5290 "\tapic_register_virtualization: %d\n" 5291 "\tvirtualize_x2apic_mode: %d\n" 5292 "\tactivate_secondary_controls: %d\n", 5293 config->virtualize_apic_accesses, 5294 config->use_tpr_shadow, 5295 config->apic_register_virtualization, 5296 config->virtualize_x2apic_mode, 5297 config->activate_secondary_controls); 5298 5299 return false; 5300 } 5301 5302 return true; 5303 } 5304 5305 struct apic_reg_test apic_reg_tests[] = { 5306 /* Good configs, where some L2 APIC accesses are virtualized. */ 5307 { 5308 .name = "Virtualize APIC accesses", 5309 .apic_reg_virt_config = { 5310 .virtualize_apic_accesses = true, 5311 .use_tpr_shadow = false, 5312 .apic_register_virtualization = false, 5313 .virtualize_x2apic_mode = false, 5314 .activate_secondary_controls = true, 5315 }, 5316 }, 5317 { 5318 .name = "Virtualize APIC accesses + Use TPR shadow", 5319 .apic_reg_virt_config = { 5320 .virtualize_apic_accesses = true, 5321 .use_tpr_shadow = true, 5322 .apic_register_virtualization = false, 5323 .virtualize_x2apic_mode = false, 5324 .activate_secondary_controls = true, 5325 }, 5326 }, 5327 { 5328 .name = "APIC-register virtualization", 5329 .apic_reg_virt_config = { 5330 .virtualize_apic_accesses = true, 5331 .use_tpr_shadow = true, 5332 .apic_register_virtualization = true, 5333 .virtualize_x2apic_mode = false, 5334 .activate_secondary_controls = true, 5335 }, 5336 }, 5337 5338 /* 5339 * Test that the secondary processor-based VM-execution controls are 5340 * correctly ignored when "activate secondary controls" is disabled. 5341 */ 5342 { 5343 .name = "Activate secondary controls off", 5344 .apic_reg_virt_config = { 5345 .virtualize_apic_accesses = true, 5346 .use_tpr_shadow = false, 5347 .apic_register_virtualization = true, 5348 .virtualize_x2apic_mode = true, 5349 .activate_secondary_controls = false, 5350 }, 5351 }, 5352 { 5353 .name = "Activate secondary controls off + Use TPR shadow", 5354 .apic_reg_virt_config = { 5355 .virtualize_apic_accesses = true, 5356 .use_tpr_shadow = true, 5357 .apic_register_virtualization = true, 5358 .virtualize_x2apic_mode = true, 5359 .activate_secondary_controls = false, 5360 }, 5361 }, 5362 5363 /* 5364 * Test that the APIC access address is treated like an arbitrary memory 5365 * address when "virtualize APIC accesses" is disabled. 5366 */ 5367 { 5368 .name = "Virtualize APIC accesses off + Use TPR shadow", 5369 .apic_reg_virt_config = { 5370 .virtualize_apic_accesses = false, 5371 .use_tpr_shadow = true, 5372 .apic_register_virtualization = true, 5373 .virtualize_x2apic_mode = true, 5374 .activate_secondary_controls = true, 5375 }, 5376 }, 5377 5378 /* 5379 * Test that VM entry fails due to invalid controls when 5380 * "APIC-register virtualization" is enabled while "use TPR shadow" is 5381 * disabled. 5382 */ 5383 { 5384 .name = "APIC-register virtualization + Use TPR shadow off", 5385 .apic_reg_virt_config = { 5386 .virtualize_apic_accesses = true, 5387 .use_tpr_shadow = false, 5388 .apic_register_virtualization = true, 5389 .virtualize_x2apic_mode = false, 5390 .activate_secondary_controls = true, 5391 }, 5392 }, 5393 5394 /* 5395 * Test that VM entry fails due to invalid controls when 5396 * "Virtualize x2APIC mode" is enabled while "use TPR shadow" is 5397 * disabled. 5398 */ 5399 { 5400 .name = "Virtualize x2APIC mode + Use TPR shadow off", 5401 .apic_reg_virt_config = { 5402 .virtualize_apic_accesses = false, 5403 .use_tpr_shadow = false, 5404 .apic_register_virtualization = false, 5405 .virtualize_x2apic_mode = true, 5406 .activate_secondary_controls = true, 5407 }, 5408 }, 5409 { 5410 .name = "Virtualize x2APIC mode + Use TPR shadow off v2", 5411 .apic_reg_virt_config = { 5412 .virtualize_apic_accesses = false, 5413 .use_tpr_shadow = false, 5414 .apic_register_virtualization = true, 5415 .virtualize_x2apic_mode = true, 5416 .activate_secondary_controls = true, 5417 }, 5418 }, 5419 5420 /* 5421 * Test that VM entry fails due to invalid controls when 5422 * "virtualize x2APIC mode" is enabled while "virtualize APIC accesses" 5423 * is enabled. 5424 */ 5425 { 5426 .name = "Virtualize x2APIC mode + Virtualize APIC accesses", 5427 .apic_reg_virt_config = { 5428 .virtualize_apic_accesses = true, 5429 .use_tpr_shadow = true, 5430 .apic_register_virtualization = false, 5431 .virtualize_x2apic_mode = true, 5432 .activate_secondary_controls = true, 5433 }, 5434 }, 5435 { 5436 .name = "Virtualize x2APIC mode + Virtualize APIC accesses v2", 5437 .apic_reg_virt_config = { 5438 .virtualize_apic_accesses = true, 5439 .use_tpr_shadow = true, 5440 .apic_register_virtualization = true, 5441 .virtualize_x2apic_mode = true, 5442 .activate_secondary_controls = true, 5443 }, 5444 }, 5445 }; 5446 5447 enum Apic_op { 5448 APIC_OP_XAPIC_RD, 5449 APIC_OP_XAPIC_WR, 5450 TERMINATE, 5451 }; 5452 5453 static u32 vmx_xapic_read(u32 *apic_access_address, u32 reg) 5454 { 5455 return *(volatile u32 *)((uintptr_t)apic_access_address + reg); 5456 } 5457 5458 static void vmx_xapic_write(u32 *apic_access_address, u32 reg, u32 val) 5459 { 5460 *(volatile u32 *)((uintptr_t)apic_access_address + reg) = val; 5461 } 5462 5463 struct apic_reg_virt_guest_args { 5464 enum Apic_op op; 5465 u32 *apic_access_address; 5466 u32 reg; 5467 u32 val; 5468 bool check_rd; 5469 u32 (*virt_fn)(u32); 5470 } apic_reg_virt_guest_args; 5471 5472 static void apic_reg_virt_guest(void) 5473 { 5474 volatile struct apic_reg_virt_guest_args *args = 5475 &apic_reg_virt_guest_args; 5476 5477 for (;;) { 5478 enum Apic_op op = args->op; 5479 u32 *apic_access_address = args->apic_access_address; 5480 u32 reg = args->reg; 5481 u32 val = args->val; 5482 bool check_rd = args->check_rd; 5483 u32 (*virt_fn)(u32) = args->virt_fn; 5484 5485 if (op == TERMINATE) 5486 break; 5487 5488 if (op == APIC_OP_XAPIC_RD) { 5489 u32 ret = vmx_xapic_read(apic_access_address, reg); 5490 5491 if (check_rd) { 5492 u32 want = virt_fn(val); 5493 u32 got = virt_fn(ret); 5494 5495 report("read 0x%x, expected 0x%x.", 5496 got == want, got, want); 5497 } 5498 } else if (op == APIC_OP_XAPIC_WR) { 5499 vmx_xapic_write(apic_access_address, reg, val); 5500 } 5501 5502 /* 5503 * The L1 should always execute a vmcall after it's done testing 5504 * an individual APIC operation. This helps to validate that the 5505 * L1 and L2 are in sync with each other, as expected. 5506 */ 5507 vmcall(); 5508 } 5509 } 5510 5511 static void test_xapic_rd( 5512 u32 reg, struct apic_reg_virt_expectation *expectation, 5513 u32 *apic_access_address, u32 *virtual_apic_page) 5514 { 5515 u32 val = expectation->val; 5516 u32 exit_reason_want = expectation->rd_exit_reason; 5517 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 5518 5519 report_prefix_pushf("xapic - reading 0x%03x", reg); 5520 5521 /* Configure guest to do an xapic read */ 5522 args->op = APIC_OP_XAPIC_RD; 5523 args->apic_access_address = apic_access_address; 5524 args->reg = reg; 5525 args->val = val; 5526 args->check_rd = exit_reason_want == VMX_VMCALL; 5527 args->virt_fn = expectation->virt_fn; 5528 5529 /* Setup virtual APIC page */ 5530 if (!expectation->virtualize_apic_accesses) { 5531 apic_access_address[apic_reg_index(reg)] = val; 5532 virtual_apic_page[apic_reg_index(reg)] = 0; 5533 } else if (exit_reason_want == VMX_VMCALL) { 5534 apic_access_address[apic_reg_index(reg)] = 0; 5535 virtual_apic_page[apic_reg_index(reg)] = val; 5536 } 5537 5538 /* Enter guest */ 5539 enter_guest(); 5540 5541 /* 5542 * Validate the behavior and 5543 * pass a magic value back to the guest. 5544 */ 5545 if (exit_reason_want == VMX_APIC_ACCESS) { 5546 u32 apic_page_offset = vmcs_read(EXI_QUALIFICATION) & 0xfff; 5547 5548 assert_exit_reason(exit_reason_want); 5549 report("got APIC access exit @ page offset 0x%03x, want 0x%03x", 5550 apic_page_offset == reg, apic_page_offset, reg); 5551 skip_exit_insn(); 5552 5553 /* Reenter guest so it can consume/check rcx and exit again. */ 5554 enter_guest(); 5555 } else if (exit_reason_want != VMX_VMCALL) { 5556 report("Oops, bad exit expectation: %u.", false, 5557 exit_reason_want); 5558 } 5559 5560 skip_exit_vmcall(); 5561 report_prefix_pop(); 5562 } 5563 5564 static void test_xapic_wr( 5565 u32 reg, struct apic_reg_virt_expectation *expectation, 5566 u32 *apic_access_address, u32 *virtual_apic_page) 5567 { 5568 u32 val = expectation->val; 5569 u32 exit_reason_want = expectation->wr_exit_reason; 5570 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 5571 bool virtualized = 5572 expectation->virtualize_apic_accesses && 5573 (exit_reason_want == VMX_APIC_WRITE || 5574 exit_reason_want == VMX_VMCALL); 5575 bool checked = false; 5576 5577 report_prefix_pushf("xapic - writing 0x%x to 0x%03x", val, reg); 5578 5579 /* Configure guest to do an xapic read */ 5580 args->op = APIC_OP_XAPIC_WR; 5581 args->apic_access_address = apic_access_address; 5582 args->reg = reg; 5583 args->val = val; 5584 5585 /* Setup virtual APIC page */ 5586 if (virtualized || !expectation->virtualize_apic_accesses) { 5587 apic_access_address[apic_reg_index(reg)] = 0; 5588 virtual_apic_page[apic_reg_index(reg)] = 0; 5589 } 5590 5591 /* Enter guest */ 5592 enter_guest(); 5593 5594 /* 5595 * Validate the behavior and 5596 * pass a magic value back to the guest. 5597 */ 5598 if (exit_reason_want == VMX_APIC_ACCESS) { 5599 u32 apic_page_offset = vmcs_read(EXI_QUALIFICATION) & 0xfff; 5600 5601 assert_exit_reason(exit_reason_want); 5602 report("got APIC access exit @ page offset 0x%03x, want 0x%03x", 5603 apic_page_offset == reg, apic_page_offset, reg); 5604 skip_exit_insn(); 5605 5606 /* Reenter guest so it can consume/check rcx and exit again. */ 5607 enter_guest(); 5608 } else if (exit_reason_want == VMX_APIC_WRITE) { 5609 assert_exit_reason(exit_reason_want); 5610 report("got APIC write exit @ page offset 0x%03x; val is 0x%x, want 0x%x", 5611 virtual_apic_page[apic_reg_index(reg)] == val, 5612 apic_reg_index(reg), 5613 virtual_apic_page[apic_reg_index(reg)], val); 5614 checked = true; 5615 5616 /* Reenter guest so it can consume/check rcx and exit again. */ 5617 enter_guest(); 5618 } else if (exit_reason_want != VMX_VMCALL) { 5619 report("Oops, bad exit expectation: %u.", false, 5620 exit_reason_want); 5621 } 5622 5623 assert_exit_reason(VMX_VMCALL); 5624 if (virtualized && !checked) { 5625 u32 want = expectation->virt_fn(val); 5626 u32 got = virtual_apic_page[apic_reg_index(reg)]; 5627 got = expectation->virt_fn(got); 5628 5629 report("exitless write; val is 0x%x, want 0x%x", 5630 got == want, got, want); 5631 } else if (!expectation->virtualize_apic_accesses && !checked) { 5632 u32 got = apic_access_address[apic_reg_index(reg)]; 5633 5634 report("non-virtualized write; val is 0x%x, want 0x%x", 5635 got == val, got, val); 5636 } else if (!expectation->virtualize_apic_accesses && checked) { 5637 report("Non-virtualized write was prematurely checked!", false); 5638 } 5639 5640 skip_exit_vmcall(); 5641 report_prefix_pop(); 5642 } 5643 5644 enum Config_type { 5645 CONFIG_TYPE_GOOD, 5646 CONFIG_TYPE_UNSUPPORTED, 5647 CONFIG_TYPE_VMENTRY_FAILS_EARLY, 5648 }; 5649 5650 static enum Config_type configure_apic_reg_virt_test( 5651 struct apic_reg_virt_config *apic_reg_virt_config) 5652 { 5653 u32 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 5654 u32 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 5655 /* Configs where L2 entry fails early, due to invalid controls. */ 5656 bool use_tpr_shadow_incorrectly_off = 5657 !apic_reg_virt_config->use_tpr_shadow && 5658 (apic_reg_virt_config->apic_register_virtualization || 5659 apic_reg_virt_config->virtualize_x2apic_mode) && 5660 apic_reg_virt_config->activate_secondary_controls; 5661 bool virtualize_apic_accesses_incorrectly_on = 5662 apic_reg_virt_config->virtualize_apic_accesses && 5663 apic_reg_virt_config->virtualize_x2apic_mode && 5664 apic_reg_virt_config->activate_secondary_controls; 5665 bool vmentry_fails_early = 5666 use_tpr_shadow_incorrectly_off || 5667 virtualize_apic_accesses_incorrectly_on; 5668 5669 if (apic_reg_virt_config->activate_secondary_controls) { 5670 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 5671 printf("VM-execution control \"activate secondary controls\" NOT supported.\n"); 5672 return CONFIG_TYPE_UNSUPPORTED; 5673 } 5674 cpu_exec_ctrl0 |= CPU_SECONDARY; 5675 } else { 5676 cpu_exec_ctrl0 &= ~CPU_SECONDARY; 5677 } 5678 5679 if (apic_reg_virt_config->virtualize_apic_accesses) { 5680 if (!(ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES)) { 5681 printf("VM-execution control \"virtualize APIC accesses\" NOT supported.\n"); 5682 return CONFIG_TYPE_UNSUPPORTED; 5683 } 5684 cpu_exec_ctrl1 |= CPU_VIRT_APIC_ACCESSES; 5685 } else { 5686 cpu_exec_ctrl1 &= ~CPU_VIRT_APIC_ACCESSES; 5687 } 5688 5689 if (apic_reg_virt_config->use_tpr_shadow) { 5690 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) { 5691 printf("VM-execution control \"use TPR shadow\" NOT supported.\n"); 5692 return CONFIG_TYPE_UNSUPPORTED; 5693 } 5694 cpu_exec_ctrl0 |= CPU_TPR_SHADOW; 5695 } else { 5696 cpu_exec_ctrl0 &= ~CPU_TPR_SHADOW; 5697 } 5698 5699 if (apic_reg_virt_config->apic_register_virtualization) { 5700 if (!(ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT)) { 5701 printf("VM-execution control \"APIC-register virtualization\" NOT supported.\n"); 5702 return CONFIG_TYPE_UNSUPPORTED; 5703 } 5704 cpu_exec_ctrl1 |= CPU_APIC_REG_VIRT; 5705 } else { 5706 cpu_exec_ctrl1 &= ~CPU_APIC_REG_VIRT; 5707 } 5708 5709 if (apic_reg_virt_config->virtualize_x2apic_mode) { 5710 if (!(ctrl_cpu_rev[1].clr & CPU_VIRT_X2APIC)) { 5711 printf("VM-execution control \"virtualize x2APIC mode\" NOT supported.\n"); 5712 return CONFIG_TYPE_UNSUPPORTED; 5713 } 5714 cpu_exec_ctrl1 |= CPU_VIRT_X2APIC; 5715 } else { 5716 cpu_exec_ctrl1 &= ~CPU_VIRT_X2APIC; 5717 } 5718 5719 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 5720 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 5721 5722 if (vmentry_fails_early) 5723 return CONFIG_TYPE_VMENTRY_FAILS_EARLY; 5724 5725 return CONFIG_TYPE_GOOD; 5726 } 5727 5728 static bool cpu_has_apicv(void) 5729 { 5730 return ((ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT) && 5731 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 5732 (ctrl_pin_rev.clr & PIN_POST_INTR)); 5733 } 5734 5735 /* Validates APIC register access across valid virtualization configurations. */ 5736 static void apic_reg_virt_test(void) 5737 { 5738 u32 *apic_access_address; 5739 u32 *virtual_apic_page; 5740 u64 control; 5741 u64 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 5742 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 5743 int i; 5744 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 5745 5746 if (!cpu_has_apicv()) { 5747 report_skip(__func__); 5748 return; 5749 } 5750 5751 control = cpu_exec_ctrl1; 5752 control &= ~CPU_VINTD; 5753 vmcs_write(CPU_EXEC_CTRL1, control); 5754 5755 test_set_guest(apic_reg_virt_guest); 5756 5757 /* 5758 * From the SDM: The 1-setting of the "virtualize APIC accesses" 5759 * VM-execution is guaranteed to apply only if translations to the 5760 * APIC-access address use a 4-KByte page. 5761 */ 5762 apic_access_address = alloc_page(); 5763 force_4k_page(apic_access_address); 5764 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_address)); 5765 5766 virtual_apic_page = alloc_page(); 5767 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 5768 5769 for (i = 0; i < ARRAY_SIZE(apic_reg_tests); i++) { 5770 struct apic_reg_test *apic_reg_test = &apic_reg_tests[i]; 5771 struct apic_reg_virt_config *apic_reg_virt_config = 5772 &apic_reg_test->apic_reg_virt_config; 5773 enum Config_type config_type; 5774 u32 reg; 5775 5776 printf("--- %s test ---\n", apic_reg_test->name); 5777 config_type = 5778 configure_apic_reg_virt_test(apic_reg_virt_config); 5779 if (config_type == CONFIG_TYPE_UNSUPPORTED) { 5780 printf("Skip because of missing features.\n"); 5781 continue; 5782 } 5783 5784 if (config_type == CONFIG_TYPE_VMENTRY_FAILS_EARLY) { 5785 enter_guest_with_bad_controls(); 5786 continue; 5787 } 5788 5789 for (reg = 0; reg < PAGE_SIZE / sizeof(u32); reg += 0x10) { 5790 struct apic_reg_virt_expectation expectation = {}; 5791 bool ok; 5792 5793 ok = apic_reg_virt_exit_expectation( 5794 reg, apic_reg_virt_config, &expectation); 5795 if (!ok) { 5796 report("Malformed test.", false); 5797 break; 5798 } 5799 5800 test_xapic_rd(reg, &expectation, apic_access_address, 5801 virtual_apic_page); 5802 test_xapic_wr(reg, &expectation, apic_access_address, 5803 virtual_apic_page); 5804 } 5805 } 5806 5807 /* Terminate the guest */ 5808 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 5809 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 5810 args->op = TERMINATE; 5811 enter_guest(); 5812 assert_exit_reason(VMX_VMCALL); 5813 } 5814 5815 struct virt_x2apic_mode_config { 5816 struct apic_reg_virt_config apic_reg_virt_config; 5817 bool virtual_interrupt_delivery; 5818 bool use_msr_bitmaps; 5819 bool disable_x2apic_msr_intercepts; 5820 bool disable_x2apic; 5821 }; 5822 5823 struct virt_x2apic_mode_test_case { 5824 const char *name; 5825 struct virt_x2apic_mode_config virt_x2apic_mode_config; 5826 }; 5827 5828 enum Virt_x2apic_mode_behavior_type { 5829 X2APIC_ACCESS_VIRTUALIZED, 5830 X2APIC_ACCESS_PASSED_THROUGH, 5831 X2APIC_ACCESS_TRIGGERS_GP, 5832 }; 5833 5834 struct virt_x2apic_mode_expectation { 5835 enum Reason rd_exit_reason; 5836 enum Reason wr_exit_reason; 5837 5838 /* 5839 * RDMSR and WRMSR handle 64-bit values. However, except for ICR, all of 5840 * the x2APIC registers are 32 bits. Notice: 5841 * 1. vmx_x2apic_read() clears the upper 32 bits for 32-bit registers. 5842 * 2. vmx_x2apic_write() expects the val arg to be well-formed. 5843 */ 5844 u64 rd_val; 5845 u64 wr_val; 5846 5847 /* 5848 * Compares input to virtualized output; 5849 * 1st arg is pointer to return expected virtualization output. 5850 */ 5851 u64 (*virt_fn)(u64); 5852 5853 enum Virt_x2apic_mode_behavior_type rd_behavior; 5854 enum Virt_x2apic_mode_behavior_type wr_behavior; 5855 bool wr_only; 5856 }; 5857 5858 static u64 virt_x2apic_mode_identity(u64 val) 5859 { 5860 return val; 5861 } 5862 5863 static u64 virt_x2apic_mode_nibble1(u64 val) 5864 { 5865 return val & 0xf0; 5866 } 5867 5868 static bool is_cmci_enabled(void) 5869 { 5870 return rdmsr(MSR_IA32_MCG_CAP) & BIT_ULL(10); 5871 } 5872 5873 static void virt_x2apic_mode_rd_expectation( 5874 u32 reg, bool virt_x2apic_mode_on, bool disable_x2apic, 5875 bool apic_register_virtualization, bool virtual_interrupt_delivery, 5876 struct virt_x2apic_mode_expectation *expectation) 5877 { 5878 bool readable = 5879 !x2apic_reg_reserved(reg) && 5880 reg != APIC_EOI; 5881 5882 if (reg == APIC_CMCI && !is_cmci_enabled()) 5883 readable = false; 5884 5885 expectation->rd_exit_reason = VMX_VMCALL; 5886 expectation->virt_fn = virt_x2apic_mode_identity; 5887 if (virt_x2apic_mode_on && apic_register_virtualization) { 5888 expectation->rd_val = MAGIC_VAL_1; 5889 if (reg == APIC_PROCPRI && virtual_interrupt_delivery) 5890 expectation->virt_fn = virt_x2apic_mode_nibble1; 5891 else if (reg == APIC_TASKPRI) 5892 expectation->virt_fn = virt_x2apic_mode_nibble1; 5893 expectation->rd_behavior = X2APIC_ACCESS_VIRTUALIZED; 5894 } else if (virt_x2apic_mode_on && !apic_register_virtualization && 5895 reg == APIC_TASKPRI) { 5896 expectation->rd_val = MAGIC_VAL_1; 5897 expectation->virt_fn = virt_x2apic_mode_nibble1; 5898 expectation->rd_behavior = X2APIC_ACCESS_VIRTUALIZED; 5899 } else if (!disable_x2apic && readable) { 5900 expectation->rd_val = apic_read(reg); 5901 expectation->rd_behavior = X2APIC_ACCESS_PASSED_THROUGH; 5902 } else { 5903 expectation->rd_behavior = X2APIC_ACCESS_TRIGGERS_GP; 5904 } 5905 } 5906 5907 /* 5908 * get_x2apic_wr_val() creates an innocuous write value for an x2APIC register. 5909 * 5910 * For writable registers, get_x2apic_wr_val() deposits the write value into the 5911 * val pointer arg and returns true. For non-writable registers, val is not 5912 * modified and get_x2apic_wr_val() returns false. 5913 */ 5914 static bool get_x2apic_wr_val(u32 reg, u64 *val) 5915 { 5916 switch (reg) { 5917 case APIC_TASKPRI: 5918 /* Bits 31:8 are reserved. */ 5919 *val &= 0xff; 5920 break; 5921 case APIC_EOI: 5922 case APIC_ESR: 5923 case APIC_TMICT: 5924 /* 5925 * EOI, ESR: WRMSR of a non-zero value causes #GP(0). 5926 * TMICT: A write of 0 to the initial-count register effectively 5927 * stops the local APIC timer, in both one-shot and 5928 * periodic mode. 5929 */ 5930 *val = 0; 5931 break; 5932 case APIC_SPIV: 5933 case APIC_LVTT: 5934 case APIC_LVTTHMR: 5935 case APIC_LVTPC: 5936 case APIC_LVT0: 5937 case APIC_LVT1: 5938 case APIC_LVTERR: 5939 case APIC_TDCR: 5940 /* 5941 * To avoid writing a 1 to a reserved bit or causing some other 5942 * unintended side effect, read the current value and use it as 5943 * the write value. 5944 */ 5945 *val = apic_read(reg); 5946 break; 5947 case APIC_CMCI: 5948 if (!is_cmci_enabled()) 5949 return false; 5950 *val = apic_read(reg); 5951 break; 5952 case APIC_ICR: 5953 *val = 0x40000 | 0xf1; 5954 break; 5955 case APIC_SELF_IPI: 5956 /* 5957 * With special processing (i.e., virtualize x2APIC mode + 5958 * virtual interrupt delivery), writing zero causes an 5959 * APIC-write VM exit. We plan to add a test for enabling 5960 * "virtual-interrupt delivery" in VMCS12, and that's where we 5961 * will test a self IPI with special processing. 5962 */ 5963 *val = 0x0; 5964 break; 5965 default: 5966 return false; 5967 } 5968 5969 return true; 5970 } 5971 5972 static bool special_processing_applies(u32 reg, u64 *val, 5973 bool virt_int_delivery) 5974 { 5975 bool special_processing = 5976 (reg == APIC_TASKPRI) || 5977 (virt_int_delivery && 5978 (reg == APIC_EOI || reg == APIC_SELF_IPI)); 5979 5980 if (special_processing) { 5981 TEST_ASSERT(get_x2apic_wr_val(reg, val)); 5982 return true; 5983 } 5984 5985 return false; 5986 } 5987 5988 static void virt_x2apic_mode_wr_expectation( 5989 u32 reg, bool virt_x2apic_mode_on, bool disable_x2apic, 5990 bool virt_int_delivery, 5991 struct virt_x2apic_mode_expectation *expectation) 5992 { 5993 expectation->wr_exit_reason = VMX_VMCALL; 5994 expectation->wr_val = MAGIC_VAL_1; 5995 expectation->wr_only = false; 5996 5997 if (virt_x2apic_mode_on && 5998 special_processing_applies(reg, &expectation->wr_val, 5999 virt_int_delivery)) { 6000 expectation->wr_behavior = X2APIC_ACCESS_VIRTUALIZED; 6001 if (reg == APIC_SELF_IPI) 6002 expectation->wr_exit_reason = VMX_APIC_WRITE; 6003 } else if (!disable_x2apic && 6004 get_x2apic_wr_val(reg, &expectation->wr_val)) { 6005 expectation->wr_behavior = X2APIC_ACCESS_PASSED_THROUGH; 6006 if (reg == APIC_EOI || reg == APIC_SELF_IPI) 6007 expectation->wr_only = true; 6008 if (reg == APIC_ICR) 6009 expectation->wr_exit_reason = VMX_EXTINT; 6010 } else { 6011 expectation->wr_behavior = X2APIC_ACCESS_TRIGGERS_GP; 6012 /* 6013 * Writing 1 to a reserved bit triggers a #GP. 6014 * Thus, set the write value to 0, which seems 6015 * the most likely to detect a missed #GP. 6016 */ 6017 expectation->wr_val = 0; 6018 } 6019 } 6020 6021 static void virt_x2apic_mode_exit_expectation( 6022 u32 reg, struct virt_x2apic_mode_config *config, 6023 struct virt_x2apic_mode_expectation *expectation) 6024 { 6025 struct apic_reg_virt_config *base_config = 6026 &config->apic_reg_virt_config; 6027 bool virt_x2apic_mode_on = 6028 base_config->virtualize_x2apic_mode && 6029 config->use_msr_bitmaps && 6030 config->disable_x2apic_msr_intercepts && 6031 base_config->activate_secondary_controls; 6032 6033 virt_x2apic_mode_wr_expectation( 6034 reg, virt_x2apic_mode_on, config->disable_x2apic, 6035 config->virtual_interrupt_delivery, expectation); 6036 virt_x2apic_mode_rd_expectation( 6037 reg, virt_x2apic_mode_on, config->disable_x2apic, 6038 base_config->apic_register_virtualization, 6039 config->virtual_interrupt_delivery, expectation); 6040 } 6041 6042 struct virt_x2apic_mode_test_case virt_x2apic_mode_tests[] = { 6043 /* 6044 * Baseline "virtualize x2APIC mode" configuration: 6045 * - virtualize x2APIC mode 6046 * - virtual-interrupt delivery 6047 * - APIC-register virtualization 6048 * - x2APIC MSR intercepts disabled 6049 * 6050 * Reads come from virtual APIC page, special processing applies to 6051 * VTPR, EOI, and SELF IPI, and all other writes pass through to L1 6052 * APIC. 6053 */ 6054 { 6055 .name = "Baseline", 6056 .virt_x2apic_mode_config = { 6057 .virtual_interrupt_delivery = true, 6058 .use_msr_bitmaps = true, 6059 .disable_x2apic_msr_intercepts = true, 6060 .disable_x2apic = false, 6061 .apic_reg_virt_config = { 6062 .apic_register_virtualization = true, 6063 .use_tpr_shadow = true, 6064 .virtualize_apic_accesses = false, 6065 .virtualize_x2apic_mode = true, 6066 .activate_secondary_controls = true, 6067 }, 6068 }, 6069 }, 6070 { 6071 .name = "Baseline w/ x2apic disabled", 6072 .virt_x2apic_mode_config = { 6073 .virtual_interrupt_delivery = true, 6074 .use_msr_bitmaps = true, 6075 .disable_x2apic_msr_intercepts = true, 6076 .disable_x2apic = true, 6077 .apic_reg_virt_config = { 6078 .apic_register_virtualization = true, 6079 .use_tpr_shadow = true, 6080 .virtualize_apic_accesses = false, 6081 .virtualize_x2apic_mode = true, 6082 .activate_secondary_controls = true, 6083 }, 6084 }, 6085 }, 6086 6087 /* 6088 * Baseline, minus virtual-interrupt delivery. Reads come from virtual 6089 * APIC page, special processing applies to VTPR, and all other writes 6090 * pass through to L1 APIC. 6091 */ 6092 { 6093 .name = "Baseline - virtual interrupt delivery", 6094 .virt_x2apic_mode_config = { 6095 .virtual_interrupt_delivery = false, 6096 .use_msr_bitmaps = true, 6097 .disable_x2apic_msr_intercepts = true, 6098 .disable_x2apic = false, 6099 .apic_reg_virt_config = { 6100 .apic_register_virtualization = true, 6101 .use_tpr_shadow = true, 6102 .virtualize_apic_accesses = false, 6103 .virtualize_x2apic_mode = true, 6104 .activate_secondary_controls = true, 6105 }, 6106 }, 6107 }, 6108 6109 /* 6110 * Baseline, minus APIC-register virtualization. x2APIC reads pass 6111 * through to L1's APIC, unless reading VTPR 6112 */ 6113 { 6114 .name = "Virtualize x2APIC mode, no APIC reg virt", 6115 .virt_x2apic_mode_config = { 6116 .virtual_interrupt_delivery = true, 6117 .use_msr_bitmaps = true, 6118 .disable_x2apic_msr_intercepts = true, 6119 .disable_x2apic = false, 6120 .apic_reg_virt_config = { 6121 .apic_register_virtualization = false, 6122 .use_tpr_shadow = true, 6123 .virtualize_apic_accesses = false, 6124 .virtualize_x2apic_mode = true, 6125 .activate_secondary_controls = true, 6126 }, 6127 }, 6128 }, 6129 { 6130 .name = "Virtualize x2APIC mode, no APIC reg virt, x2APIC off", 6131 .virt_x2apic_mode_config = { 6132 .virtual_interrupt_delivery = true, 6133 .use_msr_bitmaps = true, 6134 .disable_x2apic_msr_intercepts = true, 6135 .disable_x2apic = true, 6136 .apic_reg_virt_config = { 6137 .apic_register_virtualization = false, 6138 .use_tpr_shadow = true, 6139 .virtualize_apic_accesses = false, 6140 .virtualize_x2apic_mode = true, 6141 .activate_secondary_controls = true, 6142 }, 6143 }, 6144 }, 6145 6146 /* 6147 * Enable "virtualize x2APIC mode" and "APIC-register virtualization", 6148 * and disable intercepts for the x2APIC MSRs, but fail to enable 6149 * "activate secondary controls" (i.e. L2 gets access to L1's x2APIC 6150 * MSRs). 6151 */ 6152 { 6153 .name = "Fail to enable activate secondary controls", 6154 .virt_x2apic_mode_config = { 6155 .virtual_interrupt_delivery = true, 6156 .use_msr_bitmaps = true, 6157 .disable_x2apic_msr_intercepts = true, 6158 .disable_x2apic = false, 6159 .apic_reg_virt_config = { 6160 .apic_register_virtualization = true, 6161 .use_tpr_shadow = true, 6162 .virtualize_apic_accesses = false, 6163 .virtualize_x2apic_mode = true, 6164 .activate_secondary_controls = false, 6165 }, 6166 }, 6167 }, 6168 6169 /* 6170 * Enable "APIC-register virtualization" and enable "activate secondary 6171 * controls" and disable intercepts for the x2APIC MSRs, but do not 6172 * enable the "virtualize x2APIC mode" VM-execution control (i.e. L2 6173 * gets access to L1's x2APIC MSRs). 6174 */ 6175 { 6176 .name = "Fail to enable virtualize x2APIC mode", 6177 .virt_x2apic_mode_config = { 6178 .virtual_interrupt_delivery = true, 6179 .use_msr_bitmaps = true, 6180 .disable_x2apic_msr_intercepts = true, 6181 .disable_x2apic = false, 6182 .apic_reg_virt_config = { 6183 .apic_register_virtualization = true, 6184 .use_tpr_shadow = true, 6185 .virtualize_apic_accesses = false, 6186 .virtualize_x2apic_mode = false, 6187 .activate_secondary_controls = true, 6188 }, 6189 }, 6190 }, 6191 6192 /* 6193 * Disable "Virtualize x2APIC mode", disable x2APIC MSR intercepts, and 6194 * enable "APIC-register virtualization" --> L2 gets L1's x2APIC MSRs. 6195 */ 6196 { 6197 .name = "Baseline", 6198 .virt_x2apic_mode_config = { 6199 .virtual_interrupt_delivery = true, 6200 .use_msr_bitmaps = true, 6201 .disable_x2apic_msr_intercepts = true, 6202 .disable_x2apic = false, 6203 .apic_reg_virt_config = { 6204 .apic_register_virtualization = true, 6205 .use_tpr_shadow = true, 6206 .virtualize_apic_accesses = false, 6207 .virtualize_x2apic_mode = false, 6208 .activate_secondary_controls = true, 6209 }, 6210 }, 6211 }, 6212 }; 6213 6214 enum X2apic_op { 6215 X2APIC_OP_RD, 6216 X2APIC_OP_WR, 6217 X2APIC_TERMINATE, 6218 }; 6219 6220 static u64 vmx_x2apic_read(u32 reg) 6221 { 6222 u32 msr_addr = x2apic_msr(reg); 6223 u64 val; 6224 6225 val = rdmsr(msr_addr); 6226 6227 return val; 6228 } 6229 6230 static void vmx_x2apic_write(u32 reg, u64 val) 6231 { 6232 u32 msr_addr = x2apic_msr(reg); 6233 6234 wrmsr(msr_addr, val); 6235 } 6236 6237 struct virt_x2apic_mode_guest_args { 6238 enum X2apic_op op; 6239 u32 reg; 6240 u64 val; 6241 bool should_gp; 6242 u64 (*virt_fn)(u64); 6243 } virt_x2apic_mode_guest_args; 6244 6245 static volatile bool handle_x2apic_gp_ran; 6246 static volatile u32 handle_x2apic_gp_insn_len; 6247 static void handle_x2apic_gp(struct ex_regs *regs) 6248 { 6249 handle_x2apic_gp_ran = true; 6250 regs->rip += handle_x2apic_gp_insn_len; 6251 } 6252 6253 static handler setup_x2apic_gp_handler(void) 6254 { 6255 handler old_handler; 6256 6257 old_handler = handle_exception(GP_VECTOR, handle_x2apic_gp); 6258 /* RDMSR and WRMSR are both 2 bytes, assuming no prefixes. */ 6259 handle_x2apic_gp_insn_len = 2; 6260 6261 return old_handler; 6262 } 6263 6264 static void teardown_x2apic_gp_handler(handler old_handler) 6265 { 6266 handle_exception(GP_VECTOR, old_handler); 6267 6268 /* 6269 * Defensively reset instruction length, so that if the handler is 6270 * incorrectly used, it will loop infinitely, rather than run off into 6271 * la la land. 6272 */ 6273 handle_x2apic_gp_insn_len = 0; 6274 handle_x2apic_gp_ran = false; 6275 } 6276 6277 static void virt_x2apic_mode_guest(void) 6278 { 6279 volatile struct virt_x2apic_mode_guest_args *args = 6280 &virt_x2apic_mode_guest_args; 6281 6282 for (;;) { 6283 enum X2apic_op op = args->op; 6284 u32 reg = args->reg; 6285 u64 val = args->val; 6286 bool should_gp = args->should_gp; 6287 u64 (*virt_fn)(u64) = args->virt_fn; 6288 handler old_handler; 6289 6290 if (op == X2APIC_TERMINATE) 6291 break; 6292 6293 if (should_gp) { 6294 TEST_ASSERT(!handle_x2apic_gp_ran); 6295 old_handler = setup_x2apic_gp_handler(); 6296 } 6297 6298 if (op == X2APIC_OP_RD) { 6299 u64 ret = vmx_x2apic_read(reg); 6300 6301 if (!should_gp) { 6302 u64 want = virt_fn(val); 6303 u64 got = virt_fn(ret); 6304 6305 report("APIC read; got 0x%lx, want 0x%lx.", 6306 got == want, got, want); 6307 } 6308 } else if (op == X2APIC_OP_WR) { 6309 vmx_x2apic_write(reg, val); 6310 } 6311 6312 if (should_gp) { 6313 report("x2APIC op triggered GP.", 6314 handle_x2apic_gp_ran); 6315 teardown_x2apic_gp_handler(old_handler); 6316 } 6317 6318 /* 6319 * The L1 should always execute a vmcall after it's done testing 6320 * an individual APIC operation. This helps to validate that the 6321 * L1 and L2 are in sync with each other, as expected. 6322 */ 6323 vmcall(); 6324 } 6325 } 6326 6327 static void test_x2apic_rd( 6328 u32 reg, struct virt_x2apic_mode_expectation *expectation, 6329 u32 *virtual_apic_page) 6330 { 6331 u64 val = expectation->rd_val; 6332 u32 exit_reason_want = expectation->rd_exit_reason; 6333 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6334 6335 report_prefix_pushf("x2apic - reading 0x%03x", reg); 6336 6337 /* Configure guest to do an x2apic read */ 6338 args->op = X2APIC_OP_RD; 6339 args->reg = reg; 6340 args->val = val; 6341 args->should_gp = expectation->rd_behavior == X2APIC_ACCESS_TRIGGERS_GP; 6342 args->virt_fn = expectation->virt_fn; 6343 6344 /* Setup virtual APIC page */ 6345 if (expectation->rd_behavior == X2APIC_ACCESS_VIRTUALIZED) 6346 virtual_apic_page[apic_reg_index(reg)] = (u32)val; 6347 6348 /* Enter guest */ 6349 enter_guest(); 6350 6351 if (exit_reason_want != VMX_VMCALL) { 6352 report("Oops, bad exit expectation: %u.", false, 6353 exit_reason_want); 6354 } 6355 6356 skip_exit_vmcall(); 6357 report_prefix_pop(); 6358 } 6359 6360 static volatile bool handle_x2apic_ipi_ran; 6361 static void handle_x2apic_ipi(isr_regs_t *regs) 6362 { 6363 handle_x2apic_ipi_ran = true; 6364 eoi(); 6365 } 6366 6367 static void test_x2apic_wr( 6368 u32 reg, struct virt_x2apic_mode_expectation *expectation, 6369 u32 *virtual_apic_page) 6370 { 6371 u64 val = expectation->wr_val; 6372 u32 exit_reason_want = expectation->wr_exit_reason; 6373 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6374 int ipi_vector = 0xf1; 6375 u32 restore_val = 0; 6376 6377 report_prefix_pushf("x2apic - writing 0x%lx to 0x%03x", val, reg); 6378 6379 /* Configure guest to do an x2apic read */ 6380 args->op = X2APIC_OP_WR; 6381 args->reg = reg; 6382 args->val = val; 6383 args->should_gp = expectation->wr_behavior == X2APIC_ACCESS_TRIGGERS_GP; 6384 6385 /* Setup virtual APIC page */ 6386 if (expectation->wr_behavior == X2APIC_ACCESS_VIRTUALIZED) 6387 virtual_apic_page[apic_reg_index(reg)] = 0; 6388 if (expectation->wr_behavior == X2APIC_ACCESS_PASSED_THROUGH && !expectation->wr_only) 6389 restore_val = apic_read(reg); 6390 6391 /* Setup IPI handler */ 6392 handle_x2apic_ipi_ran = false; 6393 handle_irq(ipi_vector, handle_x2apic_ipi); 6394 6395 /* Enter guest */ 6396 enter_guest(); 6397 6398 /* 6399 * Validate the behavior and 6400 * pass a magic value back to the guest. 6401 */ 6402 if (exit_reason_want == VMX_EXTINT) { 6403 assert_exit_reason(exit_reason_want); 6404 6405 /* Clear the external interrupt. */ 6406 irq_enable(); 6407 asm volatile ("nop"); 6408 irq_disable(); 6409 report("Got pending interrupt after IRQ enabled.", 6410 handle_x2apic_ipi_ran); 6411 6412 enter_guest(); 6413 } else if (exit_reason_want == VMX_APIC_WRITE) { 6414 assert_exit_reason(exit_reason_want); 6415 report("got APIC write exit @ page offset 0x%03x; val is 0x%x, want 0x%lx", 6416 virtual_apic_page[apic_reg_index(reg)] == val, 6417 apic_reg_index(reg), 6418 virtual_apic_page[apic_reg_index(reg)], val); 6419 6420 /* Reenter guest so it can consume/check rcx and exit again. */ 6421 enter_guest(); 6422 } else if (exit_reason_want != VMX_VMCALL) { 6423 report("Oops, bad exit expectation: %u.", false, 6424 exit_reason_want); 6425 } 6426 6427 assert_exit_reason(VMX_VMCALL); 6428 if (expectation->wr_behavior == X2APIC_ACCESS_VIRTUALIZED) { 6429 u64 want = val; 6430 u32 got = virtual_apic_page[apic_reg_index(reg)]; 6431 6432 report("x2APIC write; got 0x%x, want 0x%lx", 6433 got == want, got, want); 6434 } else if (expectation->wr_behavior == X2APIC_ACCESS_PASSED_THROUGH) { 6435 if (!expectation->wr_only) { 6436 u32 got = apic_read(reg); 6437 bool ok; 6438 6439 /* 6440 * When L1's TPR is passed through to L2, the lower 6441 * nibble can be lost. For example, if L2 executes 6442 * WRMSR(0x808, 0x78), then, L1 might read 0x70. 6443 * 6444 * Here's how the lower nibble can get lost: 6445 * 1. L2 executes WRMSR(0x808, 0x78). 6446 * 2. L2 exits to L0 with a WRMSR exit. 6447 * 3. L0 emulates WRMSR, by writing L1's TPR. 6448 * 4. L0 re-enters L2. 6449 * 5. L2 exits to L0 (reason doesn't matter). 6450 * 6. L0 reflects L2's exit to L1. 6451 * 7. Before entering L1, L0 exits to user-space 6452 * (e.g., to satisfy TPR access reporting). 6453 * 8. User-space executes KVM_SET_REGS ioctl, which 6454 * clears the lower nibble of L1's TPR. 6455 */ 6456 if (reg == APIC_TASKPRI) { 6457 got = apic_virt_nibble1(got); 6458 val = apic_virt_nibble1(val); 6459 } 6460 6461 ok = got == val; 6462 report("non-virtualized write; val is 0x%x, want 0x%lx", 6463 ok, got, val); 6464 apic_write(reg, restore_val); 6465 } else { 6466 report("non-virtualized and write-only OK", true); 6467 } 6468 } 6469 skip_exit_insn(); 6470 6471 report_prefix_pop(); 6472 } 6473 6474 static enum Config_type configure_virt_x2apic_mode_test( 6475 struct virt_x2apic_mode_config *virt_x2apic_mode_config, 6476 u8 *msr_bitmap_page) 6477 { 6478 int msr; 6479 u32 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6480 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6481 6482 /* x2apic-specific VMCS config */ 6483 if (virt_x2apic_mode_config->use_msr_bitmaps) { 6484 /* virt_x2apic_mode_test() checks for MSR bitmaps support */ 6485 cpu_exec_ctrl0 |= CPU_MSR_BITMAP; 6486 } else { 6487 cpu_exec_ctrl0 &= ~CPU_MSR_BITMAP; 6488 } 6489 6490 if (virt_x2apic_mode_config->virtual_interrupt_delivery) { 6491 if (!(ctrl_cpu_rev[1].clr & CPU_VINTD)) { 6492 report_skip("VM-execution control \"virtual-interrupt delivery\" NOT supported.\n"); 6493 return CONFIG_TYPE_UNSUPPORTED; 6494 } 6495 cpu_exec_ctrl1 |= CPU_VINTD; 6496 } else { 6497 cpu_exec_ctrl1 &= ~CPU_VINTD; 6498 } 6499 6500 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6501 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6502 6503 /* x2APIC MSR intercepts are usually off for "Virtualize x2APIC mode" */ 6504 for (msr = 0x800; msr <= 0x8ff; msr++) { 6505 if (virt_x2apic_mode_config->disable_x2apic_msr_intercepts) { 6506 clear_bit(msr, msr_bitmap_page + 0x000); 6507 clear_bit(msr, msr_bitmap_page + 0x800); 6508 } else { 6509 set_bit(msr, msr_bitmap_page + 0x000); 6510 set_bit(msr, msr_bitmap_page + 0x800); 6511 } 6512 } 6513 6514 /* x2APIC mode can impact virtualization */ 6515 reset_apic(); 6516 if (!virt_x2apic_mode_config->disable_x2apic) 6517 enable_x2apic(); 6518 6519 return configure_apic_reg_virt_test( 6520 &virt_x2apic_mode_config->apic_reg_virt_config); 6521 } 6522 6523 static void virt_x2apic_mode_test(void) 6524 { 6525 u32 *virtual_apic_page; 6526 u8 *msr_bitmap_page; 6527 u64 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6528 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6529 int i; 6530 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6531 6532 if (!cpu_has_apicv()) { 6533 report_skip(__func__); 6534 return; 6535 } 6536 6537 /* 6538 * This is to exercise an issue in KVM's logic to merge L0's and L1's 6539 * MSR bitmaps. Previously, an L1 could get at L0's x2APIC MSRs by 6540 * writing the IA32_SPEC_CTRL MSR or the IA32_PRED_CMD MSRs. KVM would 6541 * then proceed to manipulate the MSR bitmaps, as if VMCS12 had the 6542 * "Virtualize x2APIC mod" control set, even when it didn't. 6543 */ 6544 if (has_spec_ctrl()) 6545 wrmsr(MSR_IA32_SPEC_CTRL, 1); 6546 6547 /* 6548 * Check that VMCS12 supports: 6549 * - "Virtual-APIC address", indicated by "use TPR shadow" 6550 * - "MSR-bitmap address", indicated by "use MSR bitmaps" 6551 */ 6552 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) { 6553 report_skip("VM-execution control \"use TPR shadow\" NOT supported.\n"); 6554 return; 6555 } else if (!(ctrl_cpu_rev[0].clr & CPU_MSR_BITMAP)) { 6556 report_skip("VM-execution control \"use MSR bitmaps\" NOT supported.\n"); 6557 return; 6558 } 6559 6560 test_set_guest(virt_x2apic_mode_guest); 6561 6562 virtual_apic_page = alloc_page(); 6563 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 6564 6565 msr_bitmap_page = alloc_page(); 6566 memset(msr_bitmap_page, 0xff, PAGE_SIZE); 6567 vmcs_write(MSR_BITMAP, virt_to_phys(msr_bitmap_page)); 6568 6569 for (i = 0; i < ARRAY_SIZE(virt_x2apic_mode_tests); i++) { 6570 struct virt_x2apic_mode_test_case *virt_x2apic_mode_test_case = 6571 &virt_x2apic_mode_tests[i]; 6572 struct virt_x2apic_mode_config *virt_x2apic_mode_config = 6573 &virt_x2apic_mode_test_case->virt_x2apic_mode_config; 6574 enum Config_type config_type; 6575 u32 reg; 6576 6577 printf("--- %s test ---\n", virt_x2apic_mode_test_case->name); 6578 config_type = 6579 configure_virt_x2apic_mode_test(virt_x2apic_mode_config, 6580 msr_bitmap_page); 6581 if (config_type == CONFIG_TYPE_UNSUPPORTED) { 6582 report_skip("Skip because of missing features.\n"); 6583 continue; 6584 } else if (config_type == CONFIG_TYPE_VMENTRY_FAILS_EARLY) { 6585 enter_guest_with_bad_controls(); 6586 continue; 6587 } 6588 6589 for (reg = 0; reg < PAGE_SIZE / sizeof(u32); reg += 0x10) { 6590 struct virt_x2apic_mode_expectation expectation; 6591 6592 virt_x2apic_mode_exit_expectation( 6593 reg, virt_x2apic_mode_config, &expectation); 6594 6595 test_x2apic_rd(reg, &expectation, virtual_apic_page); 6596 test_x2apic_wr(reg, &expectation, virtual_apic_page); 6597 } 6598 } 6599 6600 6601 /* Terminate the guest */ 6602 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6603 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6604 args->op = X2APIC_TERMINATE; 6605 enter_guest(); 6606 assert_exit_reason(VMX_VMCALL); 6607 } 6608 6609 /* 6610 * On processors that support Intel 64 architecture, the IA32_SYSENTER_ESP 6611 * field and the IA32_SYSENTER_EIP field must each contain a canonical 6612 * address. 6613 * 6614 * [Intel SDM] 6615 */ 6616 static void test_sysenter_field(u32 field, const char *name) 6617 { 6618 u64 addr_saved = vmcs_read(field); 6619 6620 vmcs_write(field, NONCANONICAL); 6621 report_prefix_pushf("%s non-canonical", name); 6622 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 6623 report_prefix_pop(); 6624 6625 vmcs_write(field, 0xffffffff); 6626 report_prefix_pushf("%s canonical", name); 6627 test_vmx_vmlaunch(0); 6628 report_prefix_pop(); 6629 6630 vmcs_write(field, addr_saved); 6631 } 6632 6633 static void test_ctl_reg(const char *cr_name, u64 cr, u64 fixed0, u64 fixed1) 6634 { 6635 u64 val; 6636 u64 cr_saved = vmcs_read(cr); 6637 int i; 6638 6639 val = fixed0 & fixed1; 6640 if (cr == HOST_CR4) 6641 vmcs_write(cr, val | X86_CR4_PAE); 6642 else 6643 vmcs_write(cr, val); 6644 report_prefix_pushf("%s %lx", cr_name, val); 6645 if (val == fixed0) 6646 test_vmx_vmlaunch(0); 6647 else 6648 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 6649 report_prefix_pop(); 6650 6651 for (i = 0; i < 64; i++) { 6652 6653 /* Set a bit when the corresponding bit in fixed1 is 0 */ 6654 if ((fixed1 & (1ull << i)) == 0) { 6655 if (cr == HOST_CR4 && ((1ull << i) & X86_CR4_SMEP || 6656 (1ull << i) & X86_CR4_SMAP)) 6657 continue; 6658 6659 vmcs_write(cr, cr_saved | (1ull << i)); 6660 report_prefix_pushf("%s %llx", cr_name, 6661 cr_saved | (1ull << i)); 6662 test_vmx_vmlaunch( 6663 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 6664 report_prefix_pop(); 6665 } 6666 6667 /* Unset a bit when the corresponding bit in fixed0 is 1 */ 6668 if (fixed0 & (1ull << i)) { 6669 vmcs_write(cr, cr_saved & ~(1ull << i)); 6670 report_prefix_pushf("%s %llx", cr_name, 6671 cr_saved & ~(1ull << i)); 6672 test_vmx_vmlaunch( 6673 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 6674 report_prefix_pop(); 6675 } 6676 } 6677 6678 vmcs_write(cr, cr_saved); 6679 } 6680 6681 /* 6682 * 1. The CR0 field must not set any bit to a value not supported in VMX 6683 * operation. 6684 * 2. The CR4 field must not set any bit to a value not supported in VMX 6685 * operation. 6686 * 3. On processors that support Intel 64 architecture, the CR3 field must 6687 * be such that bits 63:52 and bits in the range 51:32 beyond the 6688 * processor’s physical-address width must be 0. 6689 * 6690 * [Intel SDM] 6691 */ 6692 static void test_host_ctl_regs(void) 6693 { 6694 u64 fixed0, fixed1, cr3, cr3_saved; 6695 int i; 6696 6697 /* Test CR0 */ 6698 fixed0 = rdmsr(MSR_IA32_VMX_CR0_FIXED0); 6699 fixed1 = rdmsr(MSR_IA32_VMX_CR0_FIXED1); 6700 test_ctl_reg("HOST_CR0", HOST_CR0, fixed0, fixed1); 6701 6702 /* Test CR4 */ 6703 fixed0 = rdmsr(MSR_IA32_VMX_CR4_FIXED0); 6704 fixed1 = rdmsr(MSR_IA32_VMX_CR4_FIXED1) & 6705 ~(X86_CR4_SMEP | X86_CR4_SMAP); 6706 test_ctl_reg("HOST_CR4", HOST_CR4, fixed0, fixed1); 6707 6708 /* Test CR3 */ 6709 cr3_saved = vmcs_read(HOST_CR3); 6710 for (i = cpuid_maxphyaddr(); i < 64; i++) { 6711 cr3 = cr3_saved | (1ul << i); 6712 vmcs_write(HOST_CR3, cr3); 6713 report_prefix_pushf("HOST_CR3 %lx", cr3); 6714 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 6715 report_prefix_pop(); 6716 } 6717 6718 vmcs_write(HOST_CR3, cr3_saved); 6719 } 6720 6721 static void test_efer_vmlaunch(u32 fld, bool ok) 6722 { 6723 if (fld == HOST_EFER) { 6724 if (ok) 6725 test_vmx_vmlaunch(0); 6726 else 6727 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 6728 } else { 6729 if (ok) { 6730 enter_guest(); 6731 report("vmlaunch succeeds", vmcs_read(EXI_REASON) == VMX_VMCALL); 6732 } else { 6733 enter_guest_with_invalid_guest_state(); 6734 report("vmlaunch fails", vmcs_read(EXI_REASON) == (VMX_ENTRY_FAILURE | VMX_FAIL_STATE)); 6735 } 6736 advance_guest_state_test(); 6737 } 6738 } 6739 6740 static void test_efer_one(u32 fld, const char * fld_name, u64 efer, 6741 u32 ctrl_fld, u64 ctrl, 6742 int i, const char *efer_bit_name) 6743 { 6744 bool ok; 6745 6746 ok = true; 6747 if (ctrl_fld == EXI_CONTROLS && (ctrl & EXI_LOAD_EFER)) { 6748 if (!!(efer & EFER_LMA) != !!(ctrl & EXI_HOST_64)) 6749 ok = false; 6750 if (!!(efer & EFER_LME) != !!(ctrl & EXI_HOST_64)) 6751 ok = false; 6752 } 6753 if (ctrl_fld == ENT_CONTROLS && (ctrl & ENT_LOAD_EFER)) { 6754 /* Check LMA too since CR0.PG is set. */ 6755 if (!!(efer & EFER_LMA) != !!(ctrl & ENT_GUEST_64)) 6756 ok = false; 6757 if (!!(efer & EFER_LME) != !!(ctrl & ENT_GUEST_64)) 6758 ok = false; 6759 } 6760 6761 /* 6762 * Skip the test if it would enter the guest in 32-bit mode. 6763 * Perhaps write the test in assembly and make sure it 6764 * can be run in either mode? 6765 */ 6766 if (fld == GUEST_EFER && ok && !(ctrl & ENT_GUEST_64)) 6767 return; 6768 6769 vmcs_write(ctrl_fld, ctrl); 6770 vmcs_write(fld, efer); 6771 report_prefix_pushf("%s %s bit turned %s, controls %s", 6772 fld_name, efer_bit_name, 6773 (i & 1) ? "on" : "off", 6774 (i & 2) ? "on" : "off"); 6775 6776 test_efer_vmlaunch(fld, ok); 6777 report_prefix_pop(); 6778 } 6779 6780 static void test_efer_bit(u32 fld, const char * fld_name, 6781 u32 ctrl_fld, u64 ctrl_bit, u64 efer_bit, 6782 const char *efer_bit_name) 6783 { 6784 u64 efer_saved = vmcs_read(fld); 6785 u32 ctrl_saved = vmcs_read(ctrl_fld); 6786 int i; 6787 6788 for (i = 0; i < 4; i++) { 6789 u64 efer = efer_saved & ~efer_bit; 6790 u64 ctrl = ctrl_saved & ~ctrl_bit; 6791 6792 if (i & 1) 6793 efer |= efer_bit; 6794 if (i & 2) 6795 ctrl |= ctrl_bit; 6796 6797 test_efer_one(fld, fld_name, efer, ctrl_fld, ctrl, 6798 i, efer_bit_name); 6799 } 6800 6801 vmcs_write(ctrl_fld, ctrl_saved); 6802 vmcs_write(fld, efer_saved); 6803 } 6804 6805 static void test_efer(u32 fld, const char * fld_name, u32 ctrl_fld, 6806 u64 ctrl_bit1, u64 ctrl_bit2) 6807 { 6808 u64 efer_saved = vmcs_read(fld); 6809 u32 ctrl_saved = vmcs_read(ctrl_fld); 6810 u64 efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 6811 u64 i; 6812 u64 efer; 6813 6814 if (cpu_has_efer_nx()) 6815 efer_reserved_bits &= ~EFER_NX; 6816 6817 if (!ctrl_bit1) { 6818 printf("\"Load-IA32-EFER\" exit control not supported\n"); 6819 goto test_entry_exit_mode; 6820 } 6821 6822 report_prefix_pushf("%s %lx", fld_name, efer_saved); 6823 test_efer_vmlaunch(fld, true); 6824 report_prefix_pop(); 6825 6826 /* 6827 * Check reserved bits 6828 */ 6829 vmcs_write(ctrl_fld, ctrl_saved & ~ctrl_bit1); 6830 for (i = 0; i < 64; i++) { 6831 if ((1ull << i) & efer_reserved_bits) { 6832 efer = efer_saved | (1ull << i); 6833 vmcs_write(fld, efer); 6834 report_prefix_pushf("%s %lx", fld_name, efer); 6835 test_efer_vmlaunch(fld, true); 6836 report_prefix_pop(); 6837 } 6838 } 6839 6840 vmcs_write(ctrl_fld, ctrl_saved | ctrl_bit1); 6841 for (i = 0; i < 64; i++) { 6842 if ((1ull << i) & efer_reserved_bits) { 6843 efer = efer_saved | (1ull << i); 6844 vmcs_write(fld, efer); 6845 report_prefix_pushf("%s %lx", fld_name, efer); 6846 test_efer_vmlaunch(fld, false); 6847 report_prefix_pop(); 6848 } 6849 } 6850 6851 vmcs_write(ctrl_fld, ctrl_saved); 6852 vmcs_write(fld, efer_saved); 6853 6854 /* 6855 * Check LMA and LME bits 6856 */ 6857 test_efer_bit(fld, fld_name, 6858 ctrl_fld, ctrl_bit1, 6859 EFER_LMA, 6860 "EFER_LMA"); 6861 test_efer_bit(fld, fld_name, 6862 ctrl_fld, ctrl_bit1, 6863 EFER_LME, 6864 "EFER_LME"); 6865 6866 test_entry_exit_mode: 6867 test_efer_bit(fld, fld_name, 6868 ctrl_fld, ctrl_bit2, 6869 EFER_LMA, 6870 "EFER_LMA"); 6871 test_efer_bit(fld, fld_name, 6872 ctrl_fld, ctrl_bit2, 6873 EFER_LME, 6874 "EFER_LME"); 6875 } 6876 6877 /* 6878 * If the 'load IA32_EFER' VM-exit control is 1, bits reserved in the 6879 * IA32_EFER MSR must be 0 in the field for that register. In addition, 6880 * the values of the LMA and LME bits in the field must each be that of 6881 * the 'host address-space size' VM-exit control. 6882 * 6883 * [Intel SDM] 6884 */ 6885 static void test_host_efer(void) 6886 { 6887 test_efer(HOST_EFER, "HOST_EFER", EXI_CONTROLS, 6888 ctrl_exit_rev.clr & EXI_LOAD_EFER, 6889 EXI_HOST_64); 6890 } 6891 6892 /* 6893 * If the 'load IA32_EFER' VM-enter control is 1, bits reserved in the 6894 * IA32_EFER MSR must be 0 in the field for that register. In addition, 6895 * the values of the LMA and LME bits in the field must each be that of 6896 * the 'IA32e-mode guest' VM-exit control. 6897 */ 6898 static void test_guest_efer(void) 6899 { 6900 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) { 6901 printf("\"Load-IA32-EFER\" entry control not supported\n"); 6902 return; 6903 } 6904 6905 vmcs_write(GUEST_EFER, rdmsr(MSR_EFER)); 6906 test_efer(GUEST_EFER, "GUEST_EFER", ENT_CONTROLS, 6907 ctrl_enter_rev.clr & ENT_LOAD_EFER, 6908 ENT_GUEST_64); 6909 } 6910 6911 /* 6912 * PAT values higher than 8 are uninteresting since they're likely lumped 6913 * in with "8". We only test values above 8 one bit at a time, 6914 * in order to reduce the number of VM-Entries and keep the runtime reasonable. 6915 */ 6916 #define PAT_VAL_LIMIT 8 6917 6918 static void test_pat(u32 field, const char * field_name, u32 ctrl_field, 6919 u64 ctrl_bit) 6920 { 6921 u32 ctrl_saved = vmcs_read(ctrl_field); 6922 u64 pat_saved = vmcs_read(field); 6923 u64 i, val; 6924 u32 j; 6925 int error; 6926 6927 vmcs_clear_bits(ctrl_field, ctrl_bit); 6928 6929 for (i = 0; i < 256; i = (i < PAT_VAL_LIMIT) ? i + 1 : i * 2) { 6930 /* Test PAT0..PAT7 fields */ 6931 for (j = 0; j < (i ? 8 : 1); j++) { 6932 val = i << j * 8; 6933 vmcs_write(field, val); 6934 if (field == HOST_PAT) { 6935 report_prefix_pushf("%s %lx", field_name, val); 6936 test_vmx_vmlaunch(0); 6937 report_prefix_pop(); 6938 6939 } else { // GUEST_PAT 6940 enter_guest(); 6941 report_guest_state_test("ENT_LOAD_PAT enabled", 6942 VMX_VMCALL, val, 6943 "GUEST_PAT"); 6944 } 6945 } 6946 } 6947 6948 vmcs_set_bits(ctrl_field, ctrl_bit); 6949 for (i = 0; i < 256; i = (i < PAT_VAL_LIMIT) ? i + 1 : i * 2) { 6950 /* Test PAT0..PAT7 fields */ 6951 for (j = 0; j < (i ? 8 : 1); j++) { 6952 val = i << j * 8; 6953 vmcs_write(field, val); 6954 6955 if (field == HOST_PAT) { 6956 report_prefix_pushf("%s %lx", field_name, val); 6957 if (i == 0x2 || i == 0x3 || i >= 0x8) 6958 error = 6959 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD; 6960 else 6961 error = 0; 6962 6963 test_vmx_vmlaunch(error); 6964 report_prefix_pop(); 6965 6966 } else { // GUEST_PAT 6967 if (i == 0x2 || i == 0x3 || i >= 0x8) { 6968 enter_guest_with_invalid_guest_state(); 6969 report_guest_state_test("ENT_LOAD_PAT " 6970 "enabled", 6971 VMX_FAIL_STATE | VMX_ENTRY_FAILURE, 6972 val, 6973 "GUEST_PAT"); 6974 } else { 6975 enter_guest(); 6976 report_guest_state_test("ENT_LOAD_PAT " 6977 "enabled", 6978 VMX_VMCALL, 6979 val, 6980 "GUEST_PAT"); 6981 } 6982 } 6983 6984 } 6985 } 6986 6987 vmcs_write(ctrl_field, ctrl_saved); 6988 vmcs_write(field, pat_saved); 6989 } 6990 6991 /* 6992 * If the "load IA32_PAT" VM-exit control is 1, the value of the field 6993 * for the IA32_PAT MSR must be one that could be written by WRMSR 6994 * without fault at CPL 0. Specifically, each of the 8 bytes in the 6995 * field must have one of the values 0 (UC), 1 (WC), 4 (WT), 5 (WP), 6996 * 6 (WB), or 7 (UC-). 6997 * 6998 * [Intel SDM] 6999 */ 7000 static void test_load_host_pat(void) 7001 { 7002 /* 7003 * "load IA32_PAT" VM-exit control 7004 */ 7005 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) { 7006 printf("\"Load-IA32-PAT\" exit control not supported\n"); 7007 return; 7008 } 7009 7010 test_pat(HOST_PAT, "HOST_PAT", EXI_CONTROLS, EXI_LOAD_PAT); 7011 } 7012 7013 /* 7014 * test_vmcs_field - test a value for the given VMCS field 7015 * @field: VMCS field 7016 * @field_name: string name of VMCS field 7017 * @bit_start: starting bit 7018 * @bit_end: ending bit 7019 * @val: value that the bit range must or must not contain 7020 * @valid_val: whether value given in 'val' must be valid or not 7021 * @error: expected VMCS error when vmentry fails for an invalid value 7022 */ 7023 static void test_vmcs_field(u64 field, const char *field_name, u32 bit_start, 7024 u32 bit_end, u64 val, bool valid_val, u32 error) 7025 { 7026 u64 field_saved = vmcs_read(field); 7027 u32 i; 7028 u64 tmp; 7029 u32 bit_on; 7030 u64 mask = ~0ull; 7031 7032 mask = (mask >> bit_end) << bit_end; 7033 mask = mask | ((1 << bit_start) - 1); 7034 tmp = (field_saved & mask) | (val << bit_start); 7035 7036 vmcs_write(field, tmp); 7037 report_prefix_pushf("%s %lx", field_name, tmp); 7038 if (valid_val) 7039 test_vmx_vmlaunch(0); 7040 else 7041 test_vmx_vmlaunch(error); 7042 report_prefix_pop(); 7043 7044 for (i = bit_start; i <= bit_end; i = i + 2) { 7045 bit_on = ((1ull < i) & (val << bit_start)) ? 0 : 1; 7046 if (bit_on) 7047 tmp = field_saved | (1ull << i); 7048 else 7049 tmp = field_saved & ~(1ull << i); 7050 vmcs_write(field, tmp); 7051 report_prefix_pushf("%s %lx", field_name, tmp); 7052 if (valid_val) 7053 test_vmx_vmlaunch(error); 7054 else 7055 test_vmx_vmlaunch(0); 7056 report_prefix_pop(); 7057 } 7058 7059 vmcs_write(field, field_saved); 7060 } 7061 7062 static void test_canonical(u64 field, const char * field_name) 7063 { 7064 u64 addr_saved = vmcs_read(field); 7065 7066 report_prefix_pushf("%s %lx", field_name, addr_saved); 7067 if (is_canonical(addr_saved)) { 7068 test_vmx_vmlaunch(0); 7069 report_prefix_pop(); 7070 7071 vmcs_write(field, NONCANONICAL); 7072 report_prefix_pushf("%s %llx", field_name, NONCANONICAL); 7073 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7074 7075 vmcs_write(field, addr_saved); 7076 } else { 7077 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7078 } 7079 report_prefix_pop(); 7080 } 7081 7082 #define TEST_RPL_TI_FLAGS(reg, name) \ 7083 test_vmcs_field(reg, name, 0, 2, 0x0, true, \ 7084 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7085 7086 #define TEST_CS_TR_FLAGS(reg, name) \ 7087 test_vmcs_field(reg, name, 3, 15, 0x0000, false, \ 7088 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7089 7090 /* 7091 * 1. In the selector field for each of CS, SS, DS, ES, FS, GS and TR, the 7092 * RPL (bits 1:0) and the TI flag (bit 2) must be 0. 7093 * 2. The selector fields for CS and TR cannot be 0000H. 7094 * 3. The selector field for SS cannot be 0000H if the "host address-space 7095 * size" VM-exit control is 0. 7096 * 4. On processors that support Intel 64 architecture, the base-address 7097 * fields for FS, GS and TR must contain canonical addresses. 7098 */ 7099 static void test_host_segment_regs(void) 7100 { 7101 u16 selector_saved; 7102 7103 /* 7104 * Test RPL and TI flags 7105 */ 7106 TEST_RPL_TI_FLAGS(HOST_SEL_CS, "HOST_SEL_CS"); 7107 TEST_RPL_TI_FLAGS(HOST_SEL_SS, "HOST_SEL_SS"); 7108 TEST_RPL_TI_FLAGS(HOST_SEL_DS, "HOST_SEL_DS"); 7109 TEST_RPL_TI_FLAGS(HOST_SEL_ES, "HOST_SEL_ES"); 7110 TEST_RPL_TI_FLAGS(HOST_SEL_FS, "HOST_SEL_FS"); 7111 TEST_RPL_TI_FLAGS(HOST_SEL_GS, "HOST_SEL_GS"); 7112 TEST_RPL_TI_FLAGS(HOST_SEL_TR, "HOST_SEL_TR"); 7113 7114 /* 7115 * Test that CS and TR fields can not be 0x0000 7116 */ 7117 TEST_CS_TR_FLAGS(HOST_SEL_CS, "HOST_SEL_CS"); 7118 TEST_CS_TR_FLAGS(HOST_SEL_TR, "HOST_SEL_TR"); 7119 7120 /* 7121 * SS field can not be 0x0000 if "host address-space size" VM-exit 7122 * control is 0 7123 */ 7124 selector_saved = vmcs_read(HOST_SEL_SS); 7125 vmcs_write(HOST_SEL_SS, 0); 7126 report_prefix_pushf("HOST_SEL_SS 0"); 7127 if (vmcs_read(EXI_CONTROLS) & EXI_HOST_64) { 7128 test_vmx_vmlaunch(0); 7129 } else { 7130 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7131 } 7132 report_prefix_pop(); 7133 7134 vmcs_write(HOST_SEL_SS, selector_saved); 7135 7136 #ifdef __x86_64__ 7137 /* 7138 * Base address for FS, GS and TR must be canonical 7139 */ 7140 test_canonical(HOST_BASE_FS, "HOST_BASE_FS"); 7141 test_canonical(HOST_BASE_GS, "HOST_BASE_GS"); 7142 test_canonical(HOST_BASE_TR, "HOST_BASE_TR"); 7143 #endif 7144 } 7145 7146 /* 7147 * On processors that support Intel 64 architecture, the base-address 7148 * fields for GDTR and IDTR must contain canonical addresses. 7149 */ 7150 static void test_host_desc_tables(void) 7151 { 7152 #ifdef __x86_64__ 7153 test_canonical(HOST_BASE_GDTR, "HOST_BASE_GDTR"); 7154 test_canonical(HOST_BASE_IDTR, "HOST_BASE_IDTR"); 7155 #endif 7156 } 7157 7158 /* 7159 * If the "host address-space size" VM-exit control is 0, the following must 7160 * hold: 7161 * - The "IA-32e mode guest" VM-entry control is 0. 7162 * - Bit 17 of the CR4 field (corresponding to CR4.PCIDE) is 0. 7163 * - Bits 63:32 in the RIP field are 0. 7164 * 7165 * If the "host address-space size" VM-exit control is 1, the following must 7166 * hold: 7167 * - Bit 5 of the CR4 field (corresponding to CR4.PAE) is 1. 7168 * - The RIP field contains a canonical address. 7169 * 7170 */ 7171 static void test_host_addr_size(void) 7172 { 7173 u64 cr4_saved = vmcs_read(HOST_CR4); 7174 u64 rip_saved = vmcs_read(HOST_RIP); 7175 u64 entry_ctrl_saved = vmcs_read(ENT_CONTROLS); 7176 int i; 7177 u64 tmp; 7178 7179 if (vmcs_read(EXI_CONTROLS) & EXI_HOST_64) { 7180 vmcs_write(ENT_CONTROLS, entry_ctrl_saved | ENT_GUEST_64); 7181 report_prefix_pushf("\"IA-32e mode guest\" enabled"); 7182 test_vmx_vmlaunch(0); 7183 report_prefix_pop(); 7184 7185 vmcs_write(HOST_CR4, cr4_saved | X86_CR4_PCIDE); 7186 report_prefix_pushf("\"CR4.PCIDE\" set"); 7187 test_vmx_vmlaunch(0); 7188 report_prefix_pop(); 7189 7190 for (i = 32; i <= 63; i = i + 4) { 7191 tmp = rip_saved | 1ull << i; 7192 vmcs_write(HOST_RIP, tmp); 7193 report_prefix_pushf("HOST_RIP %lx", tmp); 7194 test_vmx_vmlaunch(0); 7195 report_prefix_pop(); 7196 } 7197 7198 if (cr4_saved & X86_CR4_PAE) { 7199 vmcs_write(HOST_CR4, cr4_saved & ~X86_CR4_PAE); 7200 report_prefix_pushf("\"CR4.PAE\" unset"); 7201 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7202 } else { 7203 report_prefix_pushf("\"CR4.PAE\" set"); 7204 test_vmx_vmlaunch(0); 7205 } 7206 report_prefix_pop(); 7207 7208 vmcs_write(HOST_RIP, NONCANONICAL); 7209 report_prefix_pushf("HOST_RIP %llx", NONCANONICAL); 7210 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7211 report_prefix_pop(); 7212 7213 vmcs_write(ENT_CONTROLS, entry_ctrl_saved | ENT_GUEST_64); 7214 vmcs_write(HOST_RIP, rip_saved); 7215 vmcs_write(HOST_CR4, cr4_saved); 7216 } 7217 } 7218 7219 /* 7220 * Check that the virtual CPU checks the VMX Host State Area as 7221 * documented in the Intel SDM. 7222 */ 7223 static void vmx_host_state_area_test(void) 7224 { 7225 /* 7226 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 7227 * fail due to invalid guest state, should we make it that 7228 * far. 7229 */ 7230 vmcs_write(GUEST_RFLAGS, 0); 7231 7232 test_host_ctl_regs(); 7233 7234 test_sysenter_field(HOST_SYSENTER_ESP, "HOST_SYSENTER_ESP"); 7235 test_sysenter_field(HOST_SYSENTER_EIP, "HOST_SYSENTER_EIP"); 7236 7237 test_host_efer(); 7238 test_load_host_pat(); 7239 test_host_segment_regs(); 7240 test_host_desc_tables(); 7241 test_host_addr_size(); 7242 } 7243 7244 /* 7245 * If the "load IA32_PAT" VM-entry control is 1, the value of the field 7246 * for the IA32_PAT MSR must be one that could be written by WRMSR 7247 * without fault at CPL 0. Specifically, each of the 8 bytes in the 7248 * field must have one of the values 0 (UC), 1 (WC), 4 (WT), 5 (WP), 7249 * 6 (WB), or 7 (UC-). 7250 * 7251 * [Intel SDM] 7252 */ 7253 static void test_load_guest_pat(void) 7254 { 7255 /* 7256 * "load IA32_PAT" VM-entry control 7257 */ 7258 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 7259 printf("\"Load-IA32-PAT\" entry control not supported\n"); 7260 return; 7261 } 7262 7263 test_pat(GUEST_PAT, "GUEST_PAT", ENT_CONTROLS, ENT_LOAD_PAT); 7264 } 7265 7266 /* 7267 * Check that the virtual CPU checks the VMX Guest State Area as 7268 * documented in the Intel SDM. 7269 */ 7270 static void vmx_guest_state_area_test(void) 7271 { 7272 vmx_set_test_stage(1); 7273 test_set_guest(guest_state_test_main); 7274 7275 test_load_guest_pat(); 7276 test_guest_efer(); 7277 7278 /* 7279 * Let the guest finish execution 7280 */ 7281 vmx_set_test_stage(2); 7282 enter_guest(); 7283 } 7284 7285 static bool valid_vmcs_for_vmentry(void) 7286 { 7287 struct vmcs *current_vmcs = NULL; 7288 7289 if (vmcs_save(¤t_vmcs)) 7290 return false; 7291 7292 return current_vmcs && !current_vmcs->hdr.shadow_vmcs; 7293 } 7294 7295 static void try_vmentry_in_movss_shadow(void) 7296 { 7297 u32 vm_inst_err; 7298 u32 flags; 7299 bool early_failure = false; 7300 u32 expected_flags = X86_EFLAGS_FIXED; 7301 bool valid_vmcs = valid_vmcs_for_vmentry(); 7302 7303 expected_flags |= valid_vmcs ? X86_EFLAGS_ZF : X86_EFLAGS_CF; 7304 7305 /* 7306 * Indirectly set VM_INST_ERR to 12 ("VMREAD/VMWRITE from/to 7307 * unsupported VMCS component"). 7308 */ 7309 vmcs_write(~0u, 0); 7310 7311 __asm__ __volatile__ ("mov %[host_rsp], %%edx;" 7312 "vmwrite %%rsp, %%rdx;" 7313 "mov 0f, %%rax;" 7314 "mov %[host_rip], %%edx;" 7315 "vmwrite %%rax, %%rdx;" 7316 "mov $-1, %%ah;" 7317 "sahf;" 7318 "mov %%ss, %%ax;" 7319 "mov %%ax, %%ss;" 7320 "vmlaunch;" 7321 "mov $1, %[early_failure];" 7322 "0: lahf;" 7323 "movzbl %%ah, %[flags]" 7324 : [early_failure] "+r" (early_failure), 7325 [flags] "=&a" (flags) 7326 : [host_rsp] "i" (HOST_RSP), 7327 [host_rip] "i" (HOST_RIP) 7328 : "rdx", "cc", "memory"); 7329 vm_inst_err = vmcs_read(VMX_INST_ERROR); 7330 7331 report("Early VM-entry failure", early_failure); 7332 report("RFLAGS[8:0] is %x (actual %x)", flags == expected_flags, 7333 expected_flags, flags); 7334 if (valid_vmcs) 7335 report("VM-instruction error is %d (actual %d)", 7336 vm_inst_err == VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, 7337 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, vm_inst_err); 7338 } 7339 7340 static void vmentry_movss_shadow_test(void) 7341 { 7342 struct vmcs *orig_vmcs; 7343 7344 TEST_ASSERT(!vmcs_save(&orig_vmcs)); 7345 7346 /* 7347 * Set the launched flag on the current VMCS to verify the correct 7348 * error priority, below. 7349 */ 7350 test_set_guest(v2_null_test_guest); 7351 enter_guest(); 7352 7353 /* 7354 * With bit 1 of the guest's RFLAGS clear, VM-entry should 7355 * fail due to invalid guest state (if we make it that far). 7356 */ 7357 vmcs_write(GUEST_RFLAGS, 0); 7358 7359 /* 7360 * "VM entry with events blocked by MOV SS" takes precedence over 7361 * "VMLAUNCH with non-clear VMCS." 7362 */ 7363 report_prefix_push("valid current-VMCS"); 7364 try_vmentry_in_movss_shadow(); 7365 report_prefix_pop(); 7366 7367 /* 7368 * VMfailInvalid takes precedence over "VM entry with events 7369 * blocked by MOV SS." 7370 */ 7371 TEST_ASSERT(!vmcs_clear(orig_vmcs)); 7372 report_prefix_push("no current-VMCS"); 7373 try_vmentry_in_movss_shadow(); 7374 report_prefix_pop(); 7375 7376 TEST_ASSERT(!make_vmcs_current(orig_vmcs)); 7377 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 7378 } 7379 7380 static void vmx_cr_load_test(void) 7381 { 7382 unsigned long cr3, cr4, orig_cr3, orig_cr4; 7383 7384 orig_cr4 = read_cr4(); 7385 orig_cr3 = read_cr3(); 7386 7387 if (!this_cpu_has(X86_FEATURE_PCID)) { 7388 report_skip("PCID not detected"); 7389 return; 7390 } 7391 if (!this_cpu_has(X86_FEATURE_MCE)) { 7392 report_skip("MCE not detected"); 7393 return; 7394 } 7395 7396 TEST_ASSERT(!(orig_cr3 & X86_CR3_PCID_MASK)); 7397 7398 /* Enable PCID for L1. */ 7399 cr4 = orig_cr4 | X86_CR4_PCIDE; 7400 cr3 = orig_cr3 | 0x1; 7401 TEST_ASSERT(!write_cr4_checking(cr4)); 7402 write_cr3(cr3); 7403 7404 test_set_guest(v2_null_test_guest); 7405 vmcs_write(HOST_CR4, cr4); 7406 vmcs_write(HOST_CR3, cr3); 7407 enter_guest(); 7408 7409 /* 7410 * No exception is expected. 7411 * 7412 * NB. KVM loads the last guest write to CR4 into CR4 read 7413 * shadow. In order to trigger an exit to KVM, we can toggle a 7414 * bit that is owned by KVM. We use CR4.MCE, which shall 7415 * have no side effect because normally no guest MCE (e.g., as the 7416 * result of bad memory) would happen during this test. 7417 */ 7418 TEST_ASSERT(!write_cr4_checking(cr4 ^ X86_CR4_MCE)); 7419 7420 /* Cleanup L1 state. */ 7421 write_cr3(orig_cr3); 7422 TEST_ASSERT(!write_cr4_checking(orig_cr4)); 7423 } 7424 7425 static void vmx_nm_test_guest(void) 7426 { 7427 write_cr0(read_cr0() | X86_CR0_TS); 7428 asm volatile("fnop"); 7429 } 7430 7431 static void check_nm_exit(const char *test) 7432 { 7433 u32 reason = vmcs_read(EXI_REASON); 7434 u32 intr_info = vmcs_read(EXI_INTR_INFO); 7435 const u32 expected = INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 7436 NM_VECTOR; 7437 7438 report("%s", reason == VMX_EXC_NMI && intr_info == expected, test); 7439 } 7440 7441 /* 7442 * This test checks that: 7443 * 7444 * (a) If L2 launches with CR0.TS clear, but later sets CR0.TS, then 7445 * a subsequent #NM VM-exit is reflected to L1. 7446 * 7447 * (b) If L2 launches with CR0.TS clear and CR0.EM set, then a 7448 * subsequent #NM VM-exit is reflected to L1. 7449 */ 7450 static void vmx_nm_test(void) 7451 { 7452 unsigned long cr0 = read_cr0(); 7453 7454 test_set_guest(vmx_nm_test_guest); 7455 7456 /* 7457 * L1 wants to intercept #NM exceptions encountered in L2. 7458 */ 7459 vmcs_write(EXC_BITMAP, 1 << NM_VECTOR); 7460 7461 /* 7462 * Launch L2 with CR0.TS clear, but don't claim host ownership of 7463 * any CR0 bits. L2 will set CR0.TS and then try to execute fnop, 7464 * which will raise #NM. L0 should reflect the #NM VM-exit to L1. 7465 */ 7466 vmcs_write(CR0_MASK, 0); 7467 vmcs_write(GUEST_CR0, cr0 & ~X86_CR0_TS); 7468 enter_guest(); 7469 check_nm_exit("fnop with CR0.TS set in L2 triggers #NM VM-exit to L1"); 7470 7471 /* 7472 * Re-enter L2 at the fnop instruction, with CR0.TS clear but 7473 * CR0.EM set. The fnop will still raise #NM, and L0 should 7474 * reflect the #NM VM-exit to L1. 7475 */ 7476 vmcs_write(GUEST_CR0, (cr0 & ~X86_CR0_TS) | X86_CR0_EM); 7477 enter_guest(); 7478 check_nm_exit("fnop with CR0.EM set in L2 triggers #NM VM-exit to L1"); 7479 7480 /* 7481 * Re-enter L2 at the fnop instruction, with both CR0.TS and 7482 * CR0.EM clear. There will be no #NM, and the L2 guest should 7483 * exit normally. 7484 */ 7485 vmcs_write(GUEST_CR0, cr0 & ~(X86_CR0_TS | X86_CR0_EM)); 7486 enter_guest(); 7487 } 7488 7489 bool vmx_pending_event_ipi_fired; 7490 static void vmx_pending_event_ipi_isr(isr_regs_t *regs) 7491 { 7492 vmx_pending_event_ipi_fired = true; 7493 eoi(); 7494 } 7495 7496 bool vmx_pending_event_guest_run; 7497 static void vmx_pending_event_guest(void) 7498 { 7499 vmcall(); 7500 vmx_pending_event_guest_run = true; 7501 } 7502 7503 static void vmx_pending_event_test_core(bool guest_hlt) 7504 { 7505 int ipi_vector = 0xf1; 7506 7507 vmx_pending_event_ipi_fired = false; 7508 handle_irq(ipi_vector, vmx_pending_event_ipi_isr); 7509 7510 vmx_pending_event_guest_run = false; 7511 test_set_guest(vmx_pending_event_guest); 7512 7513 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 7514 7515 enter_guest(); 7516 skip_exit_vmcall(); 7517 7518 if (guest_hlt) 7519 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 7520 7521 irq_disable(); 7522 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | 7523 APIC_DM_FIXED | ipi_vector, 7524 0); 7525 7526 enter_guest(); 7527 7528 assert_exit_reason(VMX_EXTINT); 7529 report("Guest did not run before host received IPI", 7530 !vmx_pending_event_guest_run); 7531 7532 irq_enable(); 7533 asm volatile ("nop"); 7534 irq_disable(); 7535 report("Got pending interrupt after IRQ enabled", 7536 vmx_pending_event_ipi_fired); 7537 7538 if (guest_hlt) 7539 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 7540 7541 enter_guest(); 7542 report("Guest finished running when no interrupt", 7543 vmx_pending_event_guest_run); 7544 } 7545 7546 static void vmx_pending_event_test(void) 7547 { 7548 vmx_pending_event_test_core(false); 7549 } 7550 7551 static void vmx_pending_event_hlt_test(void) 7552 { 7553 vmx_pending_event_test_core(true); 7554 } 7555 7556 static int vmx_window_test_db_count; 7557 7558 static void vmx_window_test_db_handler(struct ex_regs *regs) 7559 { 7560 vmx_window_test_db_count++; 7561 } 7562 7563 static void vmx_nmi_window_test_guest(void) 7564 { 7565 handle_exception(DB_VECTOR, vmx_window_test_db_handler); 7566 7567 asm volatile("vmcall\n\t" 7568 "nop\n\t"); 7569 7570 handle_exception(DB_VECTOR, NULL); 7571 } 7572 7573 static void verify_nmi_window_exit(u64 rip) 7574 { 7575 u32 exit_reason = vmcs_read(EXI_REASON); 7576 7577 report("Exit reason (%d) is 'NMI window'", 7578 exit_reason == VMX_NMI_WINDOW, exit_reason); 7579 report("RIP (%#lx) is %#lx", vmcs_read(GUEST_RIP) == rip, 7580 vmcs_read(GUEST_RIP), rip); 7581 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 7582 } 7583 7584 static void vmx_nmi_window_test(void) 7585 { 7586 u64 nop_addr; 7587 void *db_fault_addr = get_idt_addr(&boot_idt[DB_VECTOR]); 7588 7589 if (!(ctrl_pin_rev.clr & PIN_VIRT_NMI)) { 7590 report_skip("CPU does not support the \"Virtual NMIs\" VM-execution control."); 7591 return; 7592 } 7593 7594 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 7595 report_skip("CPU does not support the \"NMI-window exiting\" VM-execution control."); 7596 return; 7597 } 7598 7599 vmx_window_test_db_count = 0; 7600 7601 report_prefix_push("NMI-window"); 7602 test_set_guest(vmx_nmi_window_test_guest); 7603 vmcs_set_bits(PIN_CONTROLS, PIN_VIRT_NMI); 7604 enter_guest(); 7605 skip_exit_vmcall(); 7606 nop_addr = vmcs_read(GUEST_RIP); 7607 7608 /* 7609 * Ask for "NMI-window exiting," and expect an immediate VM-exit. 7610 * RIP will not advance. 7611 */ 7612 report_prefix_push("active, no blocking"); 7613 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 7614 enter_guest(); 7615 verify_nmi_window_exit(nop_addr); 7616 report_prefix_pop(); 7617 7618 /* 7619 * Ask for "NMI-window exiting" in a MOV-SS shadow, and expect 7620 * a VM-exit on the next instruction after the nop. (The nop 7621 * is one byte.) 7622 */ 7623 report_prefix_push("active, blocking by MOV-SS"); 7624 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 7625 enter_guest(); 7626 verify_nmi_window_exit(nop_addr + 1); 7627 report_prefix_pop(); 7628 7629 /* 7630 * Ask for "NMI-window exiting" (with event injection), and 7631 * expect a VM-exit after the event is injected. (RIP should 7632 * be at the address specified in the IDT entry for #DB.) 7633 */ 7634 report_prefix_push("active, no blocking, injecting #DB"); 7635 vmcs_write(ENT_INTR_INFO, 7636 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 7637 enter_guest(); 7638 verify_nmi_window_exit((u64)db_fault_addr); 7639 report_prefix_pop(); 7640 7641 /* 7642 * Ask for "NMI-window exiting" with NMI blocking, and expect 7643 * a VM-exit after the next IRET (i.e. after the #DB handler 7644 * returns). So, RIP should be back at one byte past the nop. 7645 */ 7646 report_prefix_push("active, blocking by NMI"); 7647 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_NMI); 7648 enter_guest(); 7649 verify_nmi_window_exit(nop_addr + 1); 7650 report("#DB handler executed once (actual %d times)", 7651 vmx_window_test_db_count == 1, 7652 vmx_window_test_db_count); 7653 report_prefix_pop(); 7654 7655 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 7656 report_skip("CPU does not support activity state HLT."); 7657 } else { 7658 /* 7659 * Ask for "NMI-window exiting" when entering activity 7660 * state HLT, and expect an immediate VM-exit. RIP is 7661 * still one byte past the nop. 7662 */ 7663 report_prefix_push("halted, no blocking"); 7664 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 7665 enter_guest(); 7666 verify_nmi_window_exit(nop_addr + 1); 7667 report_prefix_pop(); 7668 7669 /* 7670 * Ask for "NMI-window exiting" when entering activity 7671 * state HLT (with event injection), and expect a 7672 * VM-exit after the event is injected. (RIP should be 7673 * at the address specified in the IDT entry for #DB.) 7674 */ 7675 report_prefix_push("halted, no blocking, injecting #DB"); 7676 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 7677 vmcs_write(ENT_INTR_INFO, 7678 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 7679 DB_VECTOR); 7680 enter_guest(); 7681 verify_nmi_window_exit((u64)db_fault_addr); 7682 report_prefix_pop(); 7683 } 7684 7685 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 7686 enter_guest(); 7687 report_prefix_pop(); 7688 } 7689 7690 static void vmx_intr_window_test_guest(void) 7691 { 7692 handle_exception(DB_VECTOR, vmx_window_test_db_handler); 7693 7694 /* 7695 * The two consecutive STIs are to ensure that only the first 7696 * one has a shadow. Note that NOP and STI are one byte 7697 * instructions. 7698 */ 7699 asm volatile("vmcall\n\t" 7700 "nop\n\t" 7701 "sti\n\t" 7702 "sti\n\t"); 7703 7704 handle_exception(DB_VECTOR, NULL); 7705 } 7706 7707 static void verify_intr_window_exit(u64 rip) 7708 { 7709 u32 exit_reason = vmcs_read(EXI_REASON); 7710 7711 report("Exit reason (%d) is 'interrupt window'", 7712 exit_reason == VMX_INTR_WINDOW, exit_reason); 7713 report("RIP (%#lx) is %#lx", vmcs_read(GUEST_RIP) == rip, 7714 vmcs_read(GUEST_RIP), rip); 7715 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 7716 } 7717 7718 static void vmx_intr_window_test(void) 7719 { 7720 u64 vmcall_addr; 7721 u64 nop_addr; 7722 unsigned int orig_db_gate_type; 7723 void *db_fault_addr = get_idt_addr(&boot_idt[DB_VECTOR]); 7724 7725 if (!(ctrl_cpu_rev[0].clr & CPU_INTR_WINDOW)) { 7726 report_skip("CPU does not support the \"interrupt-window exiting\" VM-execution control."); 7727 return; 7728 } 7729 7730 /* 7731 * Change the IDT entry for #DB from interrupt gate to trap gate, 7732 * so that it won't clear RFLAGS.IF. We don't want interrupts to 7733 * be disabled after vectoring a #DB. 7734 */ 7735 orig_db_gate_type = boot_idt[DB_VECTOR].type; 7736 boot_idt[DB_VECTOR].type = 15; 7737 7738 report_prefix_push("interrupt-window"); 7739 test_set_guest(vmx_intr_window_test_guest); 7740 enter_guest(); 7741 assert_exit_reason(VMX_VMCALL); 7742 vmcall_addr = vmcs_read(GUEST_RIP); 7743 7744 /* 7745 * Ask for "interrupt-window exiting" with RFLAGS.IF set and 7746 * no blocking; expect an immediate VM-exit. Note that we have 7747 * not advanced past the vmcall instruction yet, so RIP should 7748 * point to the vmcall instruction. 7749 */ 7750 report_prefix_push("active, no blocking, RFLAGS.IF=1"); 7751 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 7752 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_IF); 7753 enter_guest(); 7754 verify_intr_window_exit(vmcall_addr); 7755 report_prefix_pop(); 7756 7757 /* 7758 * Ask for "interrupt-window exiting" (with event injection) 7759 * with RFLAGS.IF set and no blocking; expect a VM-exit after 7760 * the event is injected. That is, RIP should should be at the 7761 * address specified in the IDT entry for #DB. 7762 */ 7763 report_prefix_push("active, no blocking, RFLAGS.IF=1, injecting #DB"); 7764 vmcs_write(ENT_INTR_INFO, 7765 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 7766 vmcall_addr = vmcs_read(GUEST_RIP); 7767 enter_guest(); 7768 verify_intr_window_exit((u64)db_fault_addr); 7769 report_prefix_pop(); 7770 7771 /* 7772 * Let the L2 guest run through the IRET, back to the VMCALL. 7773 * We have to clear the "interrupt-window exiting" 7774 * VM-execution control, or it would just keep causing 7775 * VM-exits. Then, advance past the VMCALL and set the 7776 * "interrupt-window exiting" VM-execution control again. 7777 */ 7778 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 7779 enter_guest(); 7780 skip_exit_vmcall(); 7781 nop_addr = vmcs_read(GUEST_RIP); 7782 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 7783 7784 /* 7785 * Ask for "interrupt-window exiting" in a MOV-SS shadow with 7786 * RFLAGS.IF set, and expect a VM-exit on the next 7787 * instruction. (NOP is one byte.) 7788 */ 7789 report_prefix_push("active, blocking by MOV-SS, RFLAGS.IF=1"); 7790 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 7791 enter_guest(); 7792 verify_intr_window_exit(nop_addr + 1); 7793 report_prefix_pop(); 7794 7795 /* 7796 * Back up to the NOP and ask for "interrupt-window exiting" 7797 * in an STI shadow with RFLAGS.IF set, and expect a VM-exit 7798 * on the next instruction. (NOP is one byte.) 7799 */ 7800 report_prefix_push("active, blocking by STI, RFLAGS.IF=1"); 7801 vmcs_write(GUEST_RIP, nop_addr); 7802 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_STI); 7803 enter_guest(); 7804 verify_intr_window_exit(nop_addr + 1); 7805 report_prefix_pop(); 7806 7807 /* 7808 * Ask for "interrupt-window exiting" with RFLAGS.IF clear, 7809 * and expect a VM-exit on the instruction following the STI 7810 * shadow. Only the first STI (which is one byte past the NOP) 7811 * should have a shadow. The second STI (which is two bytes 7812 * past the NOP) has no shadow. Therefore, the interrupt 7813 * window opens at three bytes past the NOP. 7814 */ 7815 report_prefix_push("active, RFLAGS.IF = 0"); 7816 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 7817 enter_guest(); 7818 verify_intr_window_exit(nop_addr + 3); 7819 report_prefix_pop(); 7820 7821 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 7822 report_skip("CPU does not support activity state HLT."); 7823 } else { 7824 /* 7825 * Ask for "interrupt-window exiting" when entering 7826 * activity state HLT, and expect an immediate 7827 * VM-exit. RIP is still three bytes past the nop. 7828 */ 7829 report_prefix_push("halted, no blocking"); 7830 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 7831 enter_guest(); 7832 verify_intr_window_exit(nop_addr + 3); 7833 report_prefix_pop(); 7834 7835 /* 7836 * Ask for "interrupt-window exiting" when entering 7837 * activity state HLT (with event injection), and 7838 * expect a VM-exit after the event is injected. That 7839 * is, RIP should should be at the address specified 7840 * in the IDT entry for #DB. 7841 */ 7842 report_prefix_push("halted, no blocking, injecting #DB"); 7843 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 7844 vmcs_write(ENT_INTR_INFO, 7845 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 7846 DB_VECTOR); 7847 enter_guest(); 7848 verify_intr_window_exit((u64)db_fault_addr); 7849 report_prefix_pop(); 7850 } 7851 7852 boot_idt[DB_VECTOR].type = orig_db_gate_type; 7853 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 7854 enter_guest(); 7855 report_prefix_pop(); 7856 } 7857 7858 #define GUEST_TSC_OFFSET (1u << 30) 7859 7860 static u64 guest_tsc; 7861 7862 static void vmx_store_tsc_test_guest(void) 7863 { 7864 guest_tsc = rdtsc(); 7865 } 7866 7867 /* 7868 * This test ensures that when IA32_TSC is in the VM-exit MSR-store 7869 * list, the value saved is not subject to the TSC offset that is 7870 * applied to RDTSC/RDTSCP/RDMSR(IA32_TSC) in guest execution. 7871 */ 7872 static void vmx_store_tsc_test(void) 7873 { 7874 struct vmx_msr_entry msr_entry = { .index = MSR_IA32_TSC }; 7875 u64 low, high; 7876 7877 if (!(ctrl_cpu_rev[0].clr & CPU_USE_TSC_OFFSET)) { 7878 report_skip("'Use TSC offsetting' not supported"); 7879 return; 7880 } 7881 7882 test_set_guest(vmx_store_tsc_test_guest); 7883 7884 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_USE_TSC_OFFSET); 7885 vmcs_write(EXI_MSR_ST_CNT, 1); 7886 vmcs_write(EXIT_MSR_ST_ADDR, virt_to_phys(&msr_entry)); 7887 vmcs_write(TSC_OFFSET, GUEST_TSC_OFFSET); 7888 7889 low = rdtsc(); 7890 enter_guest(); 7891 high = rdtsc(); 7892 7893 report("RDTSC value in the guest (%lu) is in range [%lu, %lu]", 7894 low + GUEST_TSC_OFFSET <= guest_tsc && 7895 guest_tsc <= high + GUEST_TSC_OFFSET, 7896 guest_tsc, low + GUEST_TSC_OFFSET, high + GUEST_TSC_OFFSET); 7897 report("IA32_TSC value saved in the VM-exit MSR-store list (%lu) is in range [%lu, %lu]", 7898 low <= msr_entry.value && msr_entry.value <= high, 7899 msr_entry.value, low, high); 7900 } 7901 7902 static void vmx_db_test_guest(void) 7903 { 7904 /* 7905 * For a hardware generated single-step #DB. 7906 */ 7907 asm volatile("vmcall;" 7908 "nop;" 7909 ".Lpost_nop:"); 7910 /* 7911 * ...in a MOVSS shadow, with pending debug exceptions. 7912 */ 7913 asm volatile("vmcall;" 7914 "nop;" 7915 ".Lpost_movss_nop:"); 7916 /* 7917 * For an L0 synthesized single-step #DB. (L0 intercepts WBINVD and 7918 * emulates it in software.) 7919 */ 7920 asm volatile("vmcall;" 7921 "wbinvd;" 7922 ".Lpost_wbinvd:"); 7923 /* 7924 * ...in a MOVSS shadow, with pending debug exceptions. 7925 */ 7926 asm volatile("vmcall;" 7927 "wbinvd;" 7928 ".Lpost_movss_wbinvd:"); 7929 /* 7930 * For a hardware generated single-step #DB in a transactional region. 7931 */ 7932 asm volatile("vmcall;" 7933 ".Lxbegin: xbegin .Lskip_rtm;" 7934 "xend;" 7935 ".Lskip_rtm:"); 7936 } 7937 7938 /* 7939 * Clear the pending debug exceptions and RFLAGS.TF and re-enter 7940 * L2. No #DB is delivered and L2 continues to the next point of 7941 * interest. 7942 */ 7943 static void dismiss_db(void) 7944 { 7945 vmcs_write(GUEST_PENDING_DEBUG, 0); 7946 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 7947 enter_guest(); 7948 } 7949 7950 /* 7951 * Check a variety of VMCS fields relevant to an intercepted #DB exception. 7952 * Then throw away the #DB exception and resume L2. 7953 */ 7954 static void check_db_exit(bool xfail_qual, bool xfail_dr6, bool xfail_pdbg, 7955 void *expected_rip, u64 expected_exit_qual, 7956 u64 expected_dr6) 7957 { 7958 u32 reason = vmcs_read(EXI_REASON); 7959 u32 intr_info = vmcs_read(EXI_INTR_INFO); 7960 u64 exit_qual = vmcs_read(EXI_QUALIFICATION); 7961 u64 guest_rip = vmcs_read(GUEST_RIP); 7962 u64 guest_pending_dbg = vmcs_read(GUEST_PENDING_DEBUG); 7963 u64 dr6 = read_dr6(); 7964 const u32 expected_intr_info = INTR_INFO_VALID_MASK | 7965 INTR_TYPE_HARD_EXCEPTION | DB_VECTOR; 7966 7967 report("Expected #DB VM-exit", 7968 reason == VMX_EXC_NMI && intr_info == expected_intr_info); 7969 report("Expected RIP %p (actual %lx)", (u64)expected_rip == guest_rip, 7970 expected_rip, guest_rip); 7971 report_xfail("Expected pending debug exceptions 0 (actual %lx)", 7972 xfail_pdbg, 0 == guest_pending_dbg, guest_pending_dbg); 7973 report_xfail("Expected exit qualification %lx (actual %lx)", xfail_qual, 7974 expected_exit_qual == exit_qual, 7975 expected_exit_qual, exit_qual); 7976 report_xfail("Expected DR6 %lx (actual %lx)", xfail_dr6, 7977 expected_dr6 == dr6, expected_dr6, dr6); 7978 dismiss_db(); 7979 } 7980 7981 /* 7982 * Assuming the guest has just exited on a VMCALL instruction, skip 7983 * over the vmcall, and set the guest's RFLAGS.TF in the VMCS. If 7984 * pending debug exceptions are non-zero, set the VMCS up as if the 7985 * previous instruction was a MOVSS that generated the indicated 7986 * pending debug exceptions. Then enter L2. 7987 */ 7988 static void single_step_guest(const char *test_name, u64 starting_dr6, 7989 u64 pending_debug_exceptions) 7990 { 7991 printf("\n%s\n", test_name); 7992 skip_exit_vmcall(); 7993 write_dr6(starting_dr6); 7994 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_TF); 7995 if (pending_debug_exceptions) { 7996 vmcs_write(GUEST_PENDING_DEBUG, pending_debug_exceptions); 7997 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 7998 } 7999 enter_guest(); 8000 } 8001 8002 /* 8003 * When L1 intercepts #DB, verify that a single-step trap clears 8004 * pending debug exceptions, populates the exit qualification field 8005 * properly, and that DR6 is not prematurely clobbered. In a 8006 * (simulated) MOVSS shadow, make sure that the pending debug 8007 * exception bits are properly accumulated into the exit qualification 8008 * field. 8009 */ 8010 static void vmx_db_test(void) 8011 { 8012 /* 8013 * We are going to set a few arbitrary bits in DR6 to verify that 8014 * (a) DR6 is not modified by an intercepted #DB, and 8015 * (b) stale bits in DR6 (DR6.BD, in particular) don't leak into 8016 * the exit qualification field for a subsequent #DB exception. 8017 */ 8018 const u64 starting_dr6 = DR6_RESERVED | BIT(13) | DR_TRAP3 | DR_TRAP1; 8019 extern char post_nop asm(".Lpost_nop"); 8020 extern char post_movss_nop asm(".Lpost_movss_nop"); 8021 extern char post_wbinvd asm(".Lpost_wbinvd"); 8022 extern char post_movss_wbinvd asm(".Lpost_movss_wbinvd"); 8023 extern char xbegin asm(".Lxbegin"); 8024 extern char skip_rtm asm(".Lskip_rtm"); 8025 8026 /* 8027 * L1 wants to intercept #DB exceptions encountered in L2. 8028 */ 8029 vmcs_write(EXC_BITMAP, BIT(DB_VECTOR)); 8030 8031 /* 8032 * Start L2 and run it up to the first point of interest. 8033 */ 8034 test_set_guest(vmx_db_test_guest); 8035 enter_guest(); 8036 8037 /* 8038 * Hardware-delivered #DB trap for single-step sets the 8039 * standard that L0 has to follow for emulated instructions. 8040 */ 8041 single_step_guest("Hardware delivered single-step", starting_dr6, 0); 8042 check_db_exit(false, false, false, &post_nop, DR_STEP, starting_dr6); 8043 8044 /* 8045 * Hardware-delivered #DB trap for single-step in MOVSS shadow 8046 * also sets the standard that L0 has to follow for emulated 8047 * instructions. Here, we establish the VMCS pending debug 8048 * exceptions to indicate that the simulated MOVSS triggered a 8049 * data breakpoint as well as the single-step trap. 8050 */ 8051 single_step_guest("Hardware delivered single-step in MOVSS shadow", 8052 starting_dr6, BIT(12) | DR_STEP | DR_TRAP0 ); 8053 check_db_exit(false, false, false, &post_movss_nop, DR_STEP | DR_TRAP0, 8054 starting_dr6); 8055 8056 /* 8057 * L0 synthesized #DB trap for single-step is buggy, because 8058 * kvm (a) clobbers DR6 too early, and (b) tries its best to 8059 * reconstitute the exit qualification from the prematurely 8060 * modified DR6, but fails miserably. 8061 */ 8062 single_step_guest("Software synthesized single-step", starting_dr6, 0); 8063 check_db_exit(true, true, false, &post_wbinvd, DR_STEP, starting_dr6); 8064 8065 /* 8066 * L0 synthesized #DB trap for single-step in MOVSS shadow is 8067 * even worse, because L0 also leaves the pending debug 8068 * exceptions in the VMCS instead of accumulating them into 8069 * the exit qualification field for the #DB exception. 8070 */ 8071 single_step_guest("Software synthesized single-step in MOVSS shadow", 8072 starting_dr6, BIT(12) | DR_STEP | DR_TRAP0); 8073 check_db_exit(true, true, true, &post_movss_wbinvd, DR_STEP | DR_TRAP0, 8074 starting_dr6); 8075 8076 /* 8077 * Optional RTM test for hardware that supports RTM, to 8078 * demonstrate that the current volume 3 of the SDM 8079 * (325384-067US), table 27-1 is incorrect. Bit 16 of the exit 8080 * qualification for debug exceptions is not reserved. It is 8081 * set to 1 if a debug exception (#DB) or a breakpoint 8082 * exception (#BP) occurs inside an RTM region while advanced 8083 * debugging of RTM transactional regions is enabled. 8084 */ 8085 if (this_cpu_has(X86_FEATURE_RTM)) { 8086 vmcs_write(ENT_CONTROLS, 8087 vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 8088 /* 8089 * Set DR7.RTM[bit 11] and IA32_DEBUGCTL.RTM[bit 15] 8090 * in the guest to enable advanced debugging of RTM 8091 * transactional regions. 8092 */ 8093 vmcs_write(GUEST_DR7, BIT(11)); 8094 vmcs_write(GUEST_DEBUGCTL, BIT(15)); 8095 single_step_guest("Hardware delivered single-step in " 8096 "transactional region", starting_dr6, 0); 8097 check_db_exit(false, false, false, &xbegin, BIT(16), 8098 starting_dr6); 8099 } else { 8100 vmcs_write(GUEST_RIP, (u64)&skip_rtm); 8101 enter_guest(); 8102 } 8103 } 8104 8105 static void enable_vid(void) 8106 { 8107 void *virtual_apic_page; 8108 8109 assert(cpu_has_apicv()); 8110 8111 disable_intercept_for_x2apic_msrs(); 8112 8113 virtual_apic_page = alloc_page(); 8114 vmcs_write(APIC_VIRT_ADDR, (u64)virtual_apic_page); 8115 8116 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 8117 8118 vmcs_write(EOI_EXIT_BITMAP0, 0x0); 8119 vmcs_write(EOI_EXIT_BITMAP1, 0x0); 8120 vmcs_write(EOI_EXIT_BITMAP2, 0x0); 8121 vmcs_write(EOI_EXIT_BITMAP3, 0x0); 8122 8123 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY | CPU_TPR_SHADOW); 8124 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_VINTD | CPU_VIRT_X2APIC); 8125 } 8126 8127 static void trigger_ioapic_scan_thread(void *data) 8128 { 8129 /* Wait until other CPU entered L2 */ 8130 while (vmx_get_test_stage() != 1) 8131 ; 8132 8133 /* Trigger ioapic scan */ 8134 ioapic_set_redir(0xf, 0x79, TRIGGER_LEVEL); 8135 vmx_set_test_stage(2); 8136 } 8137 8138 static void irq_79_handler_guest(isr_regs_t *regs) 8139 { 8140 eoi(); 8141 8142 /* L1 expects vmexit on VMX_VMCALL and not VMX_EOI_INDUCED */ 8143 vmcall(); 8144 } 8145 8146 /* 8147 * Constant for num of busy-loop iterations after which 8148 * a timer interrupt should have happened in host 8149 */ 8150 #define TIMER_INTERRUPT_DELAY 100000000 8151 8152 static void vmx_eoi_bitmap_ioapic_scan_test_guest(void) 8153 { 8154 handle_irq(0x79, irq_79_handler_guest); 8155 irq_enable(); 8156 8157 /* Signal to L1 CPU to trigger ioapic scan */ 8158 vmx_set_test_stage(1); 8159 /* Wait until L1 CPU to trigger ioapic scan */ 8160 while (vmx_get_test_stage() != 2) 8161 ; 8162 8163 /* 8164 * Wait for L0 timer interrupt to be raised while we run in L2 8165 * such that L0 will process the IOAPIC scan request before 8166 * resuming L2 8167 */ 8168 delay(TIMER_INTERRUPT_DELAY); 8169 8170 asm volatile ("int $0x79"); 8171 } 8172 8173 static void vmx_eoi_bitmap_ioapic_scan_test(void) 8174 { 8175 if (!cpu_has_apicv() || (cpu_count() < 2)) { 8176 report_skip(__func__); 8177 return; 8178 } 8179 8180 enable_vid(); 8181 8182 on_cpu_async(1, trigger_ioapic_scan_thread, NULL); 8183 test_set_guest(vmx_eoi_bitmap_ioapic_scan_test_guest); 8184 8185 /* 8186 * Launch L2. 8187 * We expect the exit reason to be VMX_VMCALL (and not EOI INDUCED). 8188 * In case the reason isn't VMX_VMCALL, the asserion inside 8189 * skip_exit_vmcall() will fail. 8190 */ 8191 enter_guest(); 8192 skip_exit_vmcall(); 8193 8194 /* Let L2 finish */ 8195 enter_guest(); 8196 report(__func__, 1); 8197 } 8198 8199 #define HLT_WITH_RVI_VECTOR (0xf1) 8200 8201 bool vmx_hlt_with_rvi_guest_isr_fired; 8202 static void vmx_hlt_with_rvi_guest_isr(isr_regs_t *regs) 8203 { 8204 vmx_hlt_with_rvi_guest_isr_fired = true; 8205 eoi(); 8206 } 8207 8208 static void vmx_hlt_with_rvi_guest(void) 8209 { 8210 handle_irq(HLT_WITH_RVI_VECTOR, vmx_hlt_with_rvi_guest_isr); 8211 8212 irq_enable(); 8213 asm volatile ("nop"); 8214 8215 vmcall(); 8216 } 8217 8218 static void vmx_hlt_with_rvi_test(void) 8219 { 8220 if (!cpu_has_apicv()) { 8221 report_skip(__func__); 8222 return; 8223 } 8224 8225 enable_vid(); 8226 8227 vmx_hlt_with_rvi_guest_isr_fired = false; 8228 test_set_guest(vmx_hlt_with_rvi_guest); 8229 8230 enter_guest(); 8231 skip_exit_vmcall(); 8232 8233 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8234 vmcs_write(GUEST_INT_STATUS, HLT_WITH_RVI_VECTOR); 8235 enter_guest(); 8236 8237 report("Interrupt raised in guest", vmx_hlt_with_rvi_guest_isr_fired); 8238 } 8239 8240 static void set_irq_line_thread(void *data) 8241 { 8242 /* Wait until other CPU entered L2 */ 8243 while (vmx_get_test_stage() != 1) 8244 ; 8245 8246 /* Set irq-line 0xf to raise vector 0x78 for vCPU 0 */ 8247 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 8248 vmx_set_test_stage(2); 8249 } 8250 8251 static bool irq_78_handler_vmcall_before_eoi; 8252 static void irq_78_handler_guest(isr_regs_t *regs) 8253 { 8254 set_irq_line(0xf, 0); 8255 if (irq_78_handler_vmcall_before_eoi) 8256 vmcall(); 8257 eoi(); 8258 vmcall(); 8259 } 8260 8261 static void vmx_apic_passthrough_guest(void) 8262 { 8263 handle_irq(0x78, irq_78_handler_guest); 8264 irq_enable(); 8265 8266 /* If requested, wait for other CPU to trigger ioapic scan */ 8267 if (vmx_get_test_stage() < 1) { 8268 vmx_set_test_stage(1); 8269 while (vmx_get_test_stage() != 2) 8270 ; 8271 } 8272 8273 set_irq_line(0xf, 1); 8274 } 8275 8276 static void vmx_apic_passthrough(bool set_irq_line_from_thread) 8277 { 8278 if (set_irq_line_from_thread && (cpu_count() < 2)) { 8279 report_skip(__func__); 8280 return; 8281 } 8282 8283 /* Test device is required for generating IRQs */ 8284 if (!test_device_enabled()) { 8285 report_skip(__func__); 8286 return; 8287 } 8288 u64 cpu_ctrl_0 = CPU_SECONDARY; 8289 u64 cpu_ctrl_1 = 0; 8290 8291 disable_intercept_for_x2apic_msrs(); 8292 8293 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 8294 8295 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 8296 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 8297 8298 if (set_irq_line_from_thread) { 8299 irq_78_handler_vmcall_before_eoi = false; 8300 on_cpu_async(1, set_irq_line_thread, NULL); 8301 } else { 8302 irq_78_handler_vmcall_before_eoi = true; 8303 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 8304 vmx_set_test_stage(2); 8305 } 8306 test_set_guest(vmx_apic_passthrough_guest); 8307 8308 if (irq_78_handler_vmcall_before_eoi) { 8309 /* Before EOI remote_irr should still be set */ 8310 enter_guest(); 8311 skip_exit_vmcall(); 8312 TEST_ASSERT_EQ_MSG(1, (int)ioapic_read_redir(0xf).remote_irr, 8313 "IOAPIC pass-through: remote_irr=1 before EOI"); 8314 } 8315 8316 /* After EOI remote_irr should be cleared */ 8317 enter_guest(); 8318 skip_exit_vmcall(); 8319 TEST_ASSERT_EQ_MSG(0, (int)ioapic_read_redir(0xf).remote_irr, 8320 "IOAPIC pass-through: remote_irr=0 after EOI"); 8321 8322 /* Let L2 finish */ 8323 enter_guest(); 8324 report(__func__, 1); 8325 } 8326 8327 static void vmx_apic_passthrough_test(void) 8328 { 8329 vmx_apic_passthrough(false); 8330 } 8331 8332 static void vmx_apic_passthrough_thread_test(void) 8333 { 8334 vmx_apic_passthrough(true); 8335 } 8336 8337 static u64 init_signal_test_exit_reason; 8338 static bool init_signal_test_thread_continued; 8339 8340 static void init_signal_test_thread(void *data) 8341 { 8342 struct vmcs *test_vmcs = data; 8343 8344 /* Enter VMX operation (i.e. exec VMXON) */ 8345 u64 *ap_vmxon_region = alloc_page(); 8346 enable_vmx(); 8347 init_vmx(ap_vmxon_region); 8348 _vmx_on(ap_vmxon_region); 8349 8350 /* Signal CPU have entered VMX operation */ 8351 vmx_set_test_stage(1); 8352 8353 /* Wait for BSP CPU to send INIT signal */ 8354 while (vmx_get_test_stage() != 2) 8355 ; 8356 8357 /* 8358 * Signal that we continue as usual as INIT signal 8359 * should be blocked while CPU is in VMX operation 8360 */ 8361 vmx_set_test_stage(3); 8362 8363 /* Wait for signal to enter VMX non-root mode */ 8364 while (vmx_get_test_stage() != 4) 8365 ; 8366 8367 /* Enter VMX non-root mode */ 8368 test_set_guest(v2_null_test_guest); 8369 make_vmcs_current(test_vmcs); 8370 enter_guest(); 8371 /* Save exit reason for BSP CPU to compare to expected result */ 8372 init_signal_test_exit_reason = vmcs_read(EXI_REASON); 8373 /* VMCLEAR test-vmcs so it could be loaded by BSP CPU */ 8374 vmcs_clear(test_vmcs); 8375 launched = false; 8376 /* Signal that CPU exited to VMX root mode */ 8377 vmx_set_test_stage(5); 8378 8379 /* Wait for signal to exit VMX operation */ 8380 while (vmx_get_test_stage() != 6) 8381 ; 8382 8383 /* Exit VMX operation (i.e. exec VMXOFF) */ 8384 vmx_off(); 8385 8386 /* 8387 * Exiting VMX operation should result in latched 8388 * INIT signal being processed. Therefore, we should 8389 * never reach the below code. Thus, signal to BSP 8390 * CPU if we have reached here so it is able to 8391 * report an issue if it happens. 8392 */ 8393 init_signal_test_thread_continued = true; 8394 } 8395 8396 #define INIT_SIGNAL_TEST_DELAY 100000000ULL 8397 8398 static void vmx_init_signal_test(void) 8399 { 8400 struct vmcs *test_vmcs; 8401 8402 if (cpu_count() < 2) { 8403 report_skip(__func__); 8404 return; 8405 } 8406 8407 /* VMCLEAR test-vmcs so it could be loaded by other CPU */ 8408 vmcs_save(&test_vmcs); 8409 vmcs_clear(test_vmcs); 8410 8411 vmx_set_test_stage(0); 8412 on_cpu_async(1, init_signal_test_thread, test_vmcs); 8413 8414 /* Wait for other CPU to enter VMX operation */ 8415 while (vmx_get_test_stage() != 1) 8416 ; 8417 8418 /* Send INIT signal to other CPU */ 8419 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_INIT | APIC_INT_ASSERT, 8420 id_map[1]); 8421 /* Signal other CPU we have sent INIT signal */ 8422 vmx_set_test_stage(2); 8423 8424 /* 8425 * Wait reasonable amount of time for INIT signal to 8426 * be received on other CPU and verify that other CPU 8427 * have proceed as usual to next test stage as INIT 8428 * signal should be blocked while other CPU in 8429 * VMX operation 8430 */ 8431 delay(INIT_SIGNAL_TEST_DELAY); 8432 report("INIT signal blocked when CPU in VMX operation", 8433 vmx_get_test_stage() == 3); 8434 /* No point to continue if we failed at this point */ 8435 if (vmx_get_test_stage() != 3) 8436 return; 8437 8438 /* Signal other CPU to enter VMX non-root mode */ 8439 init_signal_test_exit_reason = -1ull; 8440 vmx_set_test_stage(4); 8441 /* 8442 * Wait reasonable amont of time for other CPU 8443 * to exit to VMX root mode 8444 */ 8445 delay(INIT_SIGNAL_TEST_DELAY); 8446 if (vmx_get_test_stage() != 5) { 8447 report("Pending INIT signal didn't result in VMX exit", false); 8448 return; 8449 } 8450 report("INIT signal during VMX non-root mode result in exit-reason %s (%lu)", 8451 init_signal_test_exit_reason == VMX_INIT, 8452 exit_reason_description(init_signal_test_exit_reason), 8453 init_signal_test_exit_reason); 8454 8455 /* Run guest to completion */ 8456 make_vmcs_current(test_vmcs); 8457 enter_guest(); 8458 8459 /* Signal other CPU to exit VMX operation */ 8460 init_signal_test_thread_continued = false; 8461 vmx_set_test_stage(6); 8462 8463 /* 8464 * Wait reasonable amount of time for other CPU 8465 * to run after INIT signal was processed 8466 */ 8467 delay(INIT_SIGNAL_TEST_DELAY); 8468 report("INIT signal processed after exit VMX operation", 8469 !init_signal_test_thread_continued); 8470 8471 /* 8472 * TODO: Send SIPI to other CPU to sipi_entry (See x86/cstart64.S) 8473 * to re-init it to kvm-unit-tests standard environment. 8474 * Somehow (?) verify that SIPI was indeed received. 8475 */ 8476 } 8477 8478 enum vmcs_access { 8479 ACCESS_VMREAD, 8480 ACCESS_VMWRITE, 8481 ACCESS_NONE, 8482 }; 8483 8484 struct vmcs_shadow_test_common { 8485 enum vmcs_access op; 8486 enum Reason reason; 8487 u64 field; 8488 u64 value; 8489 u64 flags; 8490 u64 time; 8491 } l1_l2_common; 8492 8493 static inline u64 vmread_flags(u64 field, u64 *val) 8494 { 8495 u64 flags; 8496 8497 asm volatile ("vmread %2, %1; pushf; pop %0" 8498 : "=r" (flags), "=rm" (*val) : "r" (field) : "cc"); 8499 return flags & X86_EFLAGS_ALU; 8500 } 8501 8502 static inline u64 vmwrite_flags(u64 field, u64 val) 8503 { 8504 u64 flags; 8505 8506 asm volatile ("vmwrite %1, %2; pushf; pop %0" 8507 : "=r"(flags) : "rm" (val), "r" (field) : "cc"); 8508 return flags & X86_EFLAGS_ALU; 8509 } 8510 8511 static void vmx_vmcs_shadow_test_guest(void) 8512 { 8513 struct vmcs_shadow_test_common *c = &l1_l2_common; 8514 u64 start; 8515 8516 while (c->op != ACCESS_NONE) { 8517 start = rdtsc(); 8518 switch (c->op) { 8519 default: 8520 c->flags = -1ull; 8521 break; 8522 case ACCESS_VMREAD: 8523 c->flags = vmread_flags(c->field, &c->value); 8524 break; 8525 case ACCESS_VMWRITE: 8526 c->flags = vmwrite_flags(c->field, 0); 8527 break; 8528 } 8529 c->time = rdtsc() - start; 8530 vmcall(); 8531 } 8532 } 8533 8534 static u64 vmread_from_shadow(u64 field) 8535 { 8536 struct vmcs *primary; 8537 struct vmcs *shadow; 8538 u64 value; 8539 8540 TEST_ASSERT(!vmcs_save(&primary)); 8541 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 8542 TEST_ASSERT(!make_vmcs_current(shadow)); 8543 value = vmcs_read(field); 8544 TEST_ASSERT(!make_vmcs_current(primary)); 8545 return value; 8546 } 8547 8548 static u64 vmwrite_to_shadow(u64 field, u64 value) 8549 { 8550 struct vmcs *primary; 8551 struct vmcs *shadow; 8552 8553 TEST_ASSERT(!vmcs_save(&primary)); 8554 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 8555 TEST_ASSERT(!make_vmcs_current(shadow)); 8556 vmcs_write(field, value); 8557 value = vmcs_read(field); 8558 TEST_ASSERT(!make_vmcs_current(primary)); 8559 return value; 8560 } 8561 8562 static void vmcs_shadow_test_access(u8 *bitmap[2], enum vmcs_access access) 8563 { 8564 struct vmcs_shadow_test_common *c = &l1_l2_common; 8565 8566 c->op = access; 8567 vmcs_write(VMX_INST_ERROR, 0); 8568 enter_guest(); 8569 c->reason = vmcs_read(EXI_REASON) & 0xffff; 8570 if (c->reason != VMX_VMCALL) { 8571 skip_exit_insn(); 8572 enter_guest(); 8573 } 8574 skip_exit_vmcall(); 8575 } 8576 8577 static void vmcs_shadow_test_field(u8 *bitmap[2], u64 field) 8578 { 8579 struct vmcs_shadow_test_common *c = &l1_l2_common; 8580 struct vmcs *shadow; 8581 u64 value; 8582 uintptr_t flags[2]; 8583 bool good_shadow; 8584 u32 vmx_inst_error; 8585 8586 report_prefix_pushf("field %lx", field); 8587 c->field = field; 8588 8589 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 8590 if (shadow != (struct vmcs *)-1ull) { 8591 flags[ACCESS_VMREAD] = vmread_flags(field, &value); 8592 flags[ACCESS_VMWRITE] = vmwrite_flags(field, value); 8593 good_shadow = !flags[ACCESS_VMREAD] && !flags[ACCESS_VMWRITE]; 8594 } else { 8595 /* 8596 * When VMCS link pointer is -1ull, VMWRITE/VMREAD on 8597 * shadowed-fields should fail with setting RFLAGS.CF. 8598 */ 8599 flags[ACCESS_VMREAD] = X86_EFLAGS_CF; 8600 flags[ACCESS_VMWRITE] = X86_EFLAGS_CF; 8601 good_shadow = false; 8602 } 8603 8604 /* Intercept both VMREAD and VMWRITE. */ 8605 report_prefix_push("no VMREAD/VMWRITE permission"); 8606 /* VMWRITE/VMREAD done on reserved-bit should always intercept */ 8607 if (!(field >> VMCS_FIELD_RESERVED_SHIFT)) { 8608 set_bit(field, bitmap[ACCESS_VMREAD]); 8609 set_bit(field, bitmap[ACCESS_VMWRITE]); 8610 } 8611 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 8612 report("not shadowed for VMWRITE", c->reason == VMX_VMWRITE); 8613 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 8614 report("not shadowed for VMREAD", c->reason == VMX_VMREAD); 8615 report_prefix_pop(); 8616 8617 if (field >> VMCS_FIELD_RESERVED_SHIFT) 8618 goto out; 8619 8620 /* Permit shadowed VMREAD. */ 8621 report_prefix_push("VMREAD permission only"); 8622 clear_bit(field, bitmap[ACCESS_VMREAD]); 8623 set_bit(field, bitmap[ACCESS_VMWRITE]); 8624 if (good_shadow) 8625 value = vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 8626 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 8627 report("not shadowed for VMWRITE", c->reason == VMX_VMWRITE); 8628 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 8629 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 8630 report("shadowed for VMREAD (in %ld cycles)", c->reason == VMX_VMCALL, 8631 c->time); 8632 report("ALU flags after VMREAD (%lx) are as expected (%lx)", 8633 c->flags == flags[ACCESS_VMREAD], 8634 c->flags, flags[ACCESS_VMREAD]); 8635 if (good_shadow) 8636 report("value read from shadow (%lx) is as expected (%lx)", 8637 c->value == value, c->value, value); 8638 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 8639 report("VMX_INST_ERROR (%d) is as expected (%d)", 8640 vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 8641 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 8642 report_prefix_pop(); 8643 8644 /* Permit shadowed VMWRITE. */ 8645 report_prefix_push("VMWRITE permission only"); 8646 set_bit(field, bitmap[ACCESS_VMREAD]); 8647 clear_bit(field, bitmap[ACCESS_VMWRITE]); 8648 if (good_shadow) 8649 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 8650 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 8651 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 8652 report("shadowed for VMWRITE (in %ld cycles)", c->reason == VMX_VMCALL, 8653 c->time); 8654 report("ALU flags after VMWRITE (%lx) are as expected (%lx)", 8655 c->flags == flags[ACCESS_VMREAD], 8656 c->flags, flags[ACCESS_VMREAD]); 8657 if (good_shadow) { 8658 value = vmread_from_shadow(field); 8659 report("shadow VMCS value (%lx) is as expected (%lx)", 8660 value == 0, value, 0ul); 8661 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 8662 report("VMX_INST_ERROR (%d) is as expected (%d)", 8663 vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 8664 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 8665 } 8666 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 8667 report("not shadowed for VMREAD", c->reason == VMX_VMREAD); 8668 report_prefix_pop(); 8669 8670 /* Permit shadowed VMREAD and VMWRITE. */ 8671 report_prefix_push("VMREAD and VMWRITE permission"); 8672 clear_bit(field, bitmap[ACCESS_VMREAD]); 8673 clear_bit(field, bitmap[ACCESS_VMWRITE]); 8674 if (good_shadow) 8675 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 8676 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 8677 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 8678 report("shadowed for VMWRITE (in %ld cycles)", c->reason == VMX_VMCALL, 8679 c->time); 8680 report("ALU flags after VMWRITE (%lx) are as expected (%lx)", 8681 c->flags == flags[ACCESS_VMREAD], 8682 c->flags, flags[ACCESS_VMREAD]); 8683 if (good_shadow) { 8684 value = vmread_from_shadow(field); 8685 report("shadow VMCS value (%lx) is as expected (%lx)", 8686 value == 0, value, 0ul); 8687 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 8688 report("VMX_INST_ERROR (%d) is as expected (%d)", 8689 vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 8690 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 8691 } 8692 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 8693 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 8694 report("shadowed for VMREAD (in %ld cycles)", c->reason == VMX_VMCALL, 8695 c->time); 8696 report("ALU flags after VMREAD (%lx) are as expected (%lx)", 8697 c->flags == flags[ACCESS_VMREAD], 8698 c->flags, flags[ACCESS_VMREAD]); 8699 if (good_shadow) 8700 report("value read from shadow (%lx) is as expected (%lx)", 8701 c->value == 0, c->value, 0ul); 8702 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 8703 report("VMX_INST_ERROR (%d) is as expected (%d)", 8704 vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 8705 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 8706 report_prefix_pop(); 8707 8708 out: 8709 report_prefix_pop(); 8710 } 8711 8712 static void vmx_vmcs_shadow_test_body(u8 *bitmap[2]) 8713 { 8714 unsigned base; 8715 unsigned index; 8716 unsigned bit; 8717 unsigned highest_index = rdmsr(MSR_IA32_VMX_VMCS_ENUM); 8718 8719 /* Run test on all possible valid VMCS fields */ 8720 for (base = 0; 8721 base < (1 << VMCS_FIELD_RESERVED_SHIFT); 8722 base += (1 << VMCS_FIELD_TYPE_SHIFT)) 8723 for (index = 0; index <= highest_index; index++) 8724 vmcs_shadow_test_field(bitmap, base + index); 8725 8726 /* 8727 * Run tests on some invalid VMCS fields 8728 * (Have reserved bit set). 8729 */ 8730 for (bit = VMCS_FIELD_RESERVED_SHIFT; bit < VMCS_FIELD_BIT_SIZE; bit++) 8731 vmcs_shadow_test_field(bitmap, (1ull << bit)); 8732 } 8733 8734 static void vmx_vmcs_shadow_test(void) 8735 { 8736 u8 *bitmap[2]; 8737 struct vmcs *shadow; 8738 8739 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 8740 printf("\t'Activate secondary controls' not supported.\n"); 8741 return; 8742 } 8743 8744 if (!(ctrl_cpu_rev[1].clr & CPU_SHADOW_VMCS)) { 8745 printf("\t'VMCS shadowing' not supported.\n"); 8746 return; 8747 } 8748 8749 if (!(rdmsr(MSR_IA32_VMX_MISC) & 8750 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS)) { 8751 printf("\tVMWRITE can't modify VM-exit information fields.\n"); 8752 return; 8753 } 8754 8755 test_set_guest(vmx_vmcs_shadow_test_guest); 8756 8757 bitmap[ACCESS_VMREAD] = alloc_page(); 8758 bitmap[ACCESS_VMWRITE] = alloc_page(); 8759 8760 vmcs_write(VMREAD_BITMAP, virt_to_phys(bitmap[ACCESS_VMREAD])); 8761 vmcs_write(VMWRITE_BITMAP, virt_to_phys(bitmap[ACCESS_VMWRITE])); 8762 8763 shadow = alloc_page(); 8764 shadow->hdr.revision_id = basic.revision; 8765 shadow->hdr.shadow_vmcs = 1; 8766 TEST_ASSERT(!vmcs_clear(shadow)); 8767 8768 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_RDTSC); 8769 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY); 8770 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_SHADOW_VMCS); 8771 8772 vmcs_write(VMCS_LINK_PTR, virt_to_phys(shadow)); 8773 report_prefix_push("valid link pointer"); 8774 vmx_vmcs_shadow_test_body(bitmap); 8775 report_prefix_pop(); 8776 8777 vmcs_write(VMCS_LINK_PTR, -1ull); 8778 report_prefix_push("invalid link pointer"); 8779 vmx_vmcs_shadow_test_body(bitmap); 8780 report_prefix_pop(); 8781 8782 l1_l2_common.op = ACCESS_NONE; 8783 enter_guest(); 8784 } 8785 8786 8787 8788 static int invalid_msr_init(struct vmcs *vmcs) 8789 { 8790 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 8791 printf("\tPreemption timer is not supported\n"); 8792 return VMX_TEST_EXIT; 8793 } 8794 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 8795 preempt_val = 10000000; 8796 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 8797 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 8798 8799 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 8800 printf("\tSave preemption value is not supported\n"); 8801 8802 vmcs_write(ENT_MSR_LD_CNT, 1); 8803 vmcs_write(ENTER_MSR_LD_ADDR, (u64)0x13370000); 8804 8805 return VMX_TEST_START; 8806 } 8807 8808 8809 static void invalid_msr_main(void) 8810 { 8811 report("Invalid MSR load", 0); 8812 } 8813 8814 static int invalid_msr_exit_handler(void) 8815 { 8816 report("Invalid MSR load", 0); 8817 print_vmexit_info(); 8818 return VMX_TEST_EXIT; 8819 } 8820 8821 static int invalid_msr_entry_failure(struct vmentry_failure *failure) 8822 { 8823 ulong reason; 8824 8825 reason = vmcs_read(EXI_REASON); 8826 report("Invalid MSR load", reason == (0x80000000u | VMX_FAIL_MSR)); 8827 return VMX_TEST_VMEXIT; 8828 } 8829 8830 /* 8831 * The max number of MSRs in an atomic switch MSR list is: 8832 * (111B + 1) * 512 = 4096 8833 * 8834 * Each list entry consumes: 8835 * 4-byte MSR index + 4 bytes reserved + 8-byte data = 16 bytes 8836 * 8837 * Allocate 128 kB to cover max_msr_list_size (i.e., 64 kB) and then some. 8838 */ 8839 static const u32 msr_list_page_order = 5; 8840 8841 static void atomic_switch_msr_limit_test_guest(void) 8842 { 8843 vmcall(); 8844 } 8845 8846 static void populate_msr_list(struct vmx_msr_entry *msr_list, 8847 size_t byte_capacity, int count) 8848 { 8849 int i; 8850 8851 for (i = 0; i < count; i++) { 8852 msr_list[i].index = MSR_IA32_TSC; 8853 msr_list[i].reserved = 0; 8854 msr_list[i].value = 0x1234567890abcdef; 8855 } 8856 8857 memset(msr_list + count, 0xff, 8858 byte_capacity - count * sizeof(*msr_list)); 8859 } 8860 8861 static int max_msr_list_size(void) 8862 { 8863 u32 vmx_misc = rdmsr(MSR_IA32_VMX_MISC); 8864 u32 factor = ((vmx_misc & GENMASK(27, 25)) >> 25) + 1; 8865 8866 return factor * 512; 8867 } 8868 8869 static void atomic_switch_msrs_test(int count) 8870 { 8871 struct vmx_msr_entry *vm_enter_load; 8872 struct vmx_msr_entry *vm_exit_load; 8873 struct vmx_msr_entry *vm_exit_store; 8874 int max_allowed = max_msr_list_size(); 8875 int byte_capacity = 1ul << (msr_list_page_order + PAGE_SHIFT); 8876 /* Exceeding the max MSR list size at exit trigers KVM to abort. */ 8877 int exit_count = count > max_allowed ? max_allowed : count; 8878 int cleanup_count = count > max_allowed ? 2 : 1; 8879 int i; 8880 8881 /* 8882 * Check for the IA32_TSC MSR, 8883 * available with the "TSC flag" and used to populate the MSR lists. 8884 */ 8885 if (!(cpuid(1).d & (1 << 4))) { 8886 report_skip(__func__); 8887 return; 8888 } 8889 8890 /* Set L2 guest. */ 8891 test_set_guest(atomic_switch_msr_limit_test_guest); 8892 8893 /* Setup atomic MSR switch lists. */ 8894 vm_enter_load = alloc_pages(msr_list_page_order); 8895 vm_exit_load = alloc_pages(msr_list_page_order); 8896 vm_exit_store = alloc_pages(msr_list_page_order); 8897 8898 vmcs_write(ENTER_MSR_LD_ADDR, (u64)vm_enter_load); 8899 vmcs_write(EXIT_MSR_LD_ADDR, (u64)vm_exit_load); 8900 vmcs_write(EXIT_MSR_ST_ADDR, (u64)vm_exit_store); 8901 8902 /* 8903 * VM-Enter should succeed up to the max number of MSRs per list, and 8904 * should not consume junk beyond the last entry. 8905 */ 8906 populate_msr_list(vm_enter_load, byte_capacity, count); 8907 populate_msr_list(vm_exit_load, byte_capacity, exit_count); 8908 populate_msr_list(vm_exit_store, byte_capacity, exit_count); 8909 8910 vmcs_write(ENT_MSR_LD_CNT, count); 8911 vmcs_write(EXI_MSR_LD_CNT, exit_count); 8912 vmcs_write(EXI_MSR_ST_CNT, exit_count); 8913 8914 if (count <= max_allowed) { 8915 enter_guest(); 8916 assert_exit_reason(VMX_VMCALL); 8917 skip_exit_vmcall(); 8918 } else { 8919 u32 exit_reason; 8920 u32 exit_reason_want; 8921 u32 exit_qual; 8922 8923 enter_guest_with_invalid_guest_state(); 8924 8925 exit_reason = vmcs_read(EXI_REASON); 8926 exit_reason_want = VMX_FAIL_MSR | VMX_ENTRY_FAILURE; 8927 report("exit_reason, %u, is %u.", 8928 exit_reason == exit_reason_want, exit_reason, 8929 exit_reason_want); 8930 8931 exit_qual = vmcs_read(EXI_QUALIFICATION); 8932 report("exit_qual, %u, is %u.", exit_qual == max_allowed + 1, 8933 exit_qual, max_allowed + 1); 8934 } 8935 8936 /* Cleanup. */ 8937 vmcs_write(ENT_MSR_LD_CNT, 0); 8938 vmcs_write(EXI_MSR_LD_CNT, 0); 8939 vmcs_write(EXI_MSR_ST_CNT, 0); 8940 for (i = 0; i < cleanup_count; i++) { 8941 enter_guest(); 8942 skip_exit_vmcall(); 8943 } 8944 free_pages_by_order(vm_enter_load, msr_list_page_order); 8945 free_pages_by_order(vm_exit_load, msr_list_page_order); 8946 free_pages_by_order(vm_exit_store, msr_list_page_order); 8947 } 8948 8949 static void atomic_switch_max_msrs_test(void) 8950 { 8951 atomic_switch_msrs_test(max_msr_list_size()); 8952 } 8953 8954 static void atomic_switch_overflow_msrs_test(void) 8955 { 8956 atomic_switch_msrs_test(max_msr_list_size() + 1); 8957 } 8958 8959 #define TEST(name) { #name, .v2 = name } 8960 8961 /* name/init/guest_main/exit_handler/syscall_handler/guest_regs */ 8962 struct vmx_test vmx_tests[] = { 8963 { "null", NULL, basic_guest_main, basic_exit_handler, NULL, {0} }, 8964 { "vmenter", NULL, vmenter_main, vmenter_exit_handler, NULL, {0} }, 8965 { "preemption timer", preemption_timer_init, preemption_timer_main, 8966 preemption_timer_exit_handler, NULL, {0} }, 8967 { "control field PAT", test_ctrl_pat_init, test_ctrl_pat_main, 8968 test_ctrl_pat_exit_handler, NULL, {0} }, 8969 { "control field EFER", test_ctrl_efer_init, test_ctrl_efer_main, 8970 test_ctrl_efer_exit_handler, NULL, {0} }, 8971 { "CR shadowing", NULL, cr_shadowing_main, 8972 cr_shadowing_exit_handler, NULL, {0} }, 8973 { "I/O bitmap", iobmp_init, iobmp_main, iobmp_exit_handler, 8974 NULL, {0} }, 8975 { "instruction intercept", insn_intercept_init, insn_intercept_main, 8976 insn_intercept_exit_handler, NULL, {0} }, 8977 { "EPT A/D disabled", ept_init, ept_main, ept_exit_handler, NULL, {0} }, 8978 { "EPT A/D enabled", eptad_init, eptad_main, eptad_exit_handler, NULL, {0} }, 8979 { "PML", pml_init, pml_main, pml_exit_handler, NULL, {0} }, 8980 { "VPID", vpid_init, vpid_main, vpid_exit_handler, NULL, {0} }, 8981 { "interrupt", interrupt_init, interrupt_main, 8982 interrupt_exit_handler, NULL, {0} }, 8983 { "debug controls", dbgctls_init, dbgctls_main, dbgctls_exit_handler, 8984 NULL, {0} }, 8985 { "MSR switch", msr_switch_init, msr_switch_main, 8986 msr_switch_exit_handler, NULL, {0}, msr_switch_entry_failure }, 8987 { "vmmcall", vmmcall_init, vmmcall_main, vmmcall_exit_handler, NULL, {0} }, 8988 { "disable RDTSCP", disable_rdtscp_init, disable_rdtscp_main, 8989 disable_rdtscp_exit_handler, NULL, {0} }, 8990 { "int3", int3_init, int3_guest_main, int3_exit_handler, NULL, {0} }, 8991 { "into", into_init, into_guest_main, into_exit_handler, NULL, {0} }, 8992 { "exit_monitor_from_l2_test", NULL, exit_monitor_from_l2_main, 8993 exit_monitor_from_l2_handler, NULL, {0} }, 8994 { "invalid_msr", invalid_msr_init, invalid_msr_main, 8995 invalid_msr_exit_handler, NULL, {0}, invalid_msr_entry_failure}, 8996 /* Basic V2 tests. */ 8997 TEST(v2_null_test), 8998 TEST(v2_multiple_entries_test), 8999 TEST(fixture_test_case1), 9000 TEST(fixture_test_case2), 9001 /* Opcode tests. */ 9002 TEST(invvpid_test_v2), 9003 /* VM-entry tests */ 9004 TEST(vmx_controls_test), 9005 TEST(vmx_host_state_area_test), 9006 TEST(vmx_guest_state_area_test), 9007 TEST(vmentry_movss_shadow_test), 9008 /* APICv tests */ 9009 TEST(vmx_eoi_bitmap_ioapic_scan_test), 9010 TEST(vmx_hlt_with_rvi_test), 9011 TEST(apic_reg_virt_test), 9012 TEST(virt_x2apic_mode_test), 9013 /* APIC pass-through tests */ 9014 TEST(vmx_apic_passthrough_test), 9015 TEST(vmx_apic_passthrough_thread_test), 9016 TEST(vmx_init_signal_test), 9017 /* VMCS Shadowing tests */ 9018 TEST(vmx_vmcs_shadow_test), 9019 /* Regression tests */ 9020 TEST(vmx_cr_load_test), 9021 TEST(vmx_nm_test), 9022 TEST(vmx_db_test), 9023 TEST(vmx_nmi_window_test), 9024 TEST(vmx_intr_window_test), 9025 TEST(vmx_pending_event_test), 9026 TEST(vmx_pending_event_hlt_test), 9027 TEST(vmx_store_tsc_test), 9028 /* EPT access tests. */ 9029 TEST(ept_access_test_not_present), 9030 TEST(ept_access_test_read_only), 9031 TEST(ept_access_test_write_only), 9032 TEST(ept_access_test_read_write), 9033 TEST(ept_access_test_execute_only), 9034 TEST(ept_access_test_read_execute), 9035 TEST(ept_access_test_write_execute), 9036 TEST(ept_access_test_read_write_execute), 9037 TEST(ept_access_test_reserved_bits), 9038 TEST(ept_access_test_ignored_bits), 9039 TEST(ept_access_test_paddr_not_present_ad_disabled), 9040 TEST(ept_access_test_paddr_not_present_ad_enabled), 9041 TEST(ept_access_test_paddr_read_only_ad_disabled), 9042 TEST(ept_access_test_paddr_read_only_ad_enabled), 9043 TEST(ept_access_test_paddr_read_write), 9044 TEST(ept_access_test_paddr_read_write_execute), 9045 TEST(ept_access_test_paddr_read_execute_ad_disabled), 9046 TEST(ept_access_test_paddr_read_execute_ad_enabled), 9047 TEST(ept_access_test_paddr_not_present_page_fault), 9048 TEST(ept_access_test_force_2m_page), 9049 /* Atomic MSR switch tests. */ 9050 TEST(atomic_switch_max_msrs_test), 9051 TEST(atomic_switch_overflow_msrs_test), 9052 { NULL, NULL, NULL, NULL, NULL, {0} }, 9053 }; 9054