1 /* 2 * All test cases of nested virtualization should be in this file 3 * 4 * Author : Arthur Chunqi Li <yzt356@gmail.com> 5 */ 6 7 #include <asm/debugreg.h> 8 9 #include "vmx.h" 10 #include "msr.h" 11 #include "processor.h" 12 #include "vm.h" 13 #include "pci.h" 14 #include "fwcfg.h" 15 #include "isr.h" 16 #include "desc.h" 17 #include "apic.h" 18 #include "types.h" 19 #include "vmalloc.h" 20 #include "alloc_page.h" 21 #include "smp.h" 22 #include "delay.h" 23 24 #define NONCANONICAL 0xaaaaaaaaaaaaaaaaull 25 26 #define VPID_CAP_INVVPID_TYPES_SHIFT 40 27 28 u64 ia32_pat; 29 u64 ia32_efer; 30 void *io_bitmap_a, *io_bitmap_b; 31 u16 ioport; 32 33 unsigned long *pml4; 34 u64 eptp; 35 void *data_page1, *data_page2; 36 37 phys_addr_t pci_physaddr; 38 39 void *pml_log; 40 #define PML_INDEX 512 41 42 static inline unsigned ffs(unsigned x) 43 { 44 int pos = -1; 45 46 __asm__ __volatile__("bsf %1, %%eax; cmovnz %%eax, %0" 47 : "+r"(pos) : "rm"(x) : "eax"); 48 return pos + 1; 49 } 50 51 static inline void vmcall(void) 52 { 53 asm volatile("vmcall"); 54 } 55 56 static void basic_guest_main(void) 57 { 58 report("Basic VMX test", 1); 59 } 60 61 static int basic_exit_handler(void) 62 { 63 report("Basic VMX test", 0); 64 print_vmexit_info(); 65 return VMX_TEST_EXIT; 66 } 67 68 static void vmenter_main(void) 69 { 70 u64 rax; 71 u64 rsp, resume_rsp; 72 73 report("test vmlaunch", 1); 74 75 asm volatile( 76 "mov %%rsp, %0\n\t" 77 "mov %3, %%rax\n\t" 78 "vmcall\n\t" 79 "mov %%rax, %1\n\t" 80 "mov %%rsp, %2\n\t" 81 : "=r"(rsp), "=r"(rax), "=r"(resume_rsp) 82 : "g"(0xABCD)); 83 report("test vmresume", (rax == 0xFFFF) && (rsp == resume_rsp)); 84 } 85 86 static int vmenter_exit_handler(void) 87 { 88 u64 guest_rip; 89 ulong reason; 90 91 guest_rip = vmcs_read(GUEST_RIP); 92 reason = vmcs_read(EXI_REASON) & 0xff; 93 switch (reason) { 94 case VMX_VMCALL: 95 if (regs.rax != 0xABCD) { 96 report("test vmresume", 0); 97 return VMX_TEST_VMEXIT; 98 } 99 regs.rax = 0xFFFF; 100 vmcs_write(GUEST_RIP, guest_rip + 3); 101 return VMX_TEST_RESUME; 102 default: 103 report("test vmresume", 0); 104 print_vmexit_info(); 105 } 106 return VMX_TEST_VMEXIT; 107 } 108 109 u32 preempt_scale; 110 volatile unsigned long long tsc_val; 111 volatile u32 preempt_val; 112 u64 saved_rip; 113 114 static int preemption_timer_init(struct vmcs *vmcs) 115 { 116 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 117 printf("\tPreemption timer is not supported\n"); 118 return VMX_TEST_EXIT; 119 } 120 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 121 preempt_val = 10000000; 122 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 123 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 124 125 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 126 printf("\tSave preemption value is not supported\n"); 127 128 return VMX_TEST_START; 129 } 130 131 static void preemption_timer_main(void) 132 { 133 tsc_val = rdtsc(); 134 if (ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) { 135 vmx_set_test_stage(0); 136 vmcall(); 137 if (vmx_get_test_stage() == 1) 138 vmcall(); 139 } 140 vmx_set_test_stage(1); 141 while (vmx_get_test_stage() == 1) { 142 if (((rdtsc() - tsc_val) >> preempt_scale) 143 > 10 * preempt_val) { 144 vmx_set_test_stage(2); 145 vmcall(); 146 } 147 } 148 tsc_val = rdtsc(); 149 asm volatile ("hlt"); 150 vmcall(); 151 vmx_set_test_stage(5); 152 vmcall(); 153 } 154 155 static int preemption_timer_exit_handler(void) 156 { 157 bool guest_halted; 158 u64 guest_rip; 159 ulong reason; 160 u32 insn_len; 161 u32 ctrl_exit; 162 163 guest_rip = vmcs_read(GUEST_RIP); 164 reason = vmcs_read(EXI_REASON) & 0xff; 165 insn_len = vmcs_read(EXI_INST_LEN); 166 switch (reason) { 167 case VMX_PREEMPT: 168 switch (vmx_get_test_stage()) { 169 case 1: 170 case 2: 171 report("busy-wait for preemption timer", 172 ((rdtsc() - tsc_val) >> preempt_scale) >= 173 preempt_val); 174 vmx_set_test_stage(3); 175 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 176 return VMX_TEST_RESUME; 177 case 3: 178 guest_halted = 179 (vmcs_read(GUEST_ACTV_STATE) == ACTV_HLT); 180 report("preemption timer during hlt", 181 ((rdtsc() - tsc_val) >> preempt_scale) >= 182 preempt_val && guest_halted); 183 vmx_set_test_stage(4); 184 vmcs_write(PIN_CONTROLS, 185 vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 186 vmcs_write(EXI_CONTROLS, 187 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_PREEMPT); 188 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 189 return VMX_TEST_RESUME; 190 case 4: 191 report("preemption timer with 0 value", 192 saved_rip == guest_rip); 193 break; 194 default: 195 report("Invalid stage.", false); 196 print_vmexit_info(); 197 break; 198 } 199 break; 200 case VMX_VMCALL: 201 vmcs_write(GUEST_RIP, guest_rip + insn_len); 202 switch (vmx_get_test_stage()) { 203 case 0: 204 report("Keep preemption value", 205 vmcs_read(PREEMPT_TIMER_VALUE) == preempt_val); 206 vmx_set_test_stage(1); 207 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 208 ctrl_exit = (vmcs_read(EXI_CONTROLS) | 209 EXI_SAVE_PREEMPT) & ctrl_exit_rev.clr; 210 vmcs_write(EXI_CONTROLS, ctrl_exit); 211 return VMX_TEST_RESUME; 212 case 1: 213 report("Save preemption value", 214 vmcs_read(PREEMPT_TIMER_VALUE) < preempt_val); 215 return VMX_TEST_RESUME; 216 case 2: 217 report("busy-wait for preemption timer", 0); 218 vmx_set_test_stage(3); 219 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 220 return VMX_TEST_RESUME; 221 case 3: 222 report("preemption timer during hlt", 0); 223 vmx_set_test_stage(4); 224 /* fall through */ 225 case 4: 226 vmcs_write(PIN_CONTROLS, 227 vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 228 vmcs_write(PREEMPT_TIMER_VALUE, 0); 229 saved_rip = guest_rip + insn_len; 230 return VMX_TEST_RESUME; 231 case 5: 232 report("preemption timer with 0 value (vmcall stage 5)", 0); 233 break; 234 default: 235 // Should not reach here 236 report("unexpected stage, %d", false, 237 vmx_get_test_stage()); 238 print_vmexit_info(); 239 return VMX_TEST_VMEXIT; 240 } 241 break; 242 default: 243 report("Unknown exit reason, %ld", false, reason); 244 print_vmexit_info(); 245 } 246 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 247 return VMX_TEST_VMEXIT; 248 } 249 250 static void msr_bmp_init(void) 251 { 252 void *msr_bitmap; 253 u32 ctrl_cpu0; 254 255 msr_bitmap = alloc_page(); 256 memset(msr_bitmap, 0x0, PAGE_SIZE); 257 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 258 ctrl_cpu0 |= CPU_MSR_BITMAP; 259 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 260 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 261 } 262 263 static void *get_msr_bitmap(void) 264 { 265 void *msr_bitmap; 266 267 if (vmcs_read(CPU_EXEC_CTRL0) & CPU_MSR_BITMAP) { 268 msr_bitmap = (void *)vmcs_read(MSR_BITMAP); 269 } else { 270 msr_bitmap = alloc_page(); 271 memset(msr_bitmap, 0xff, PAGE_SIZE); 272 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 273 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_MSR_BITMAP); 274 } 275 276 return msr_bitmap; 277 } 278 279 static void disable_intercept_for_x2apic_msrs(void) 280 { 281 unsigned long *msr_bitmap = (unsigned long *)get_msr_bitmap(); 282 u32 msr; 283 284 for (msr = APIC_BASE_MSR; 285 msr < (APIC_BASE_MSR+0xff); 286 msr += BITS_PER_LONG) { 287 unsigned int word = msr / BITS_PER_LONG; 288 289 msr_bitmap[word] = 0; 290 msr_bitmap[word + (0x800 / sizeof(long))] = 0; 291 } 292 } 293 294 static int test_ctrl_pat_init(struct vmcs *vmcs) 295 { 296 u64 ctrl_ent; 297 u64 ctrl_exi; 298 299 msr_bmp_init(); 300 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT) && 301 !(ctrl_exit_rev.clr & EXI_LOAD_PAT) && 302 !(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 303 printf("\tSave/load PAT is not supported\n"); 304 return 1; 305 } 306 307 ctrl_ent = vmcs_read(ENT_CONTROLS); 308 ctrl_exi = vmcs_read(EXI_CONTROLS); 309 ctrl_ent |= ctrl_enter_rev.clr & ENT_LOAD_PAT; 310 ctrl_exi |= ctrl_exit_rev.clr & (EXI_SAVE_PAT | EXI_LOAD_PAT); 311 vmcs_write(ENT_CONTROLS, ctrl_ent); 312 vmcs_write(EXI_CONTROLS, ctrl_exi); 313 ia32_pat = rdmsr(MSR_IA32_CR_PAT); 314 vmcs_write(GUEST_PAT, 0x0); 315 vmcs_write(HOST_PAT, ia32_pat); 316 return VMX_TEST_START; 317 } 318 319 static void test_ctrl_pat_main(void) 320 { 321 u64 guest_ia32_pat; 322 323 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 324 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) 325 printf("\tENT_LOAD_PAT is not supported.\n"); 326 else { 327 if (guest_ia32_pat != 0) { 328 report("Entry load PAT", 0); 329 return; 330 } 331 } 332 wrmsr(MSR_IA32_CR_PAT, 0x6); 333 vmcall(); 334 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 335 if (ctrl_enter_rev.clr & ENT_LOAD_PAT) 336 report("Entry load PAT", guest_ia32_pat == ia32_pat); 337 } 338 339 static int test_ctrl_pat_exit_handler(void) 340 { 341 u64 guest_rip; 342 ulong reason; 343 u64 guest_pat; 344 345 guest_rip = vmcs_read(GUEST_RIP); 346 reason = vmcs_read(EXI_REASON) & 0xff; 347 switch (reason) { 348 case VMX_VMCALL: 349 guest_pat = vmcs_read(GUEST_PAT); 350 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT)) { 351 printf("\tEXI_SAVE_PAT is not supported\n"); 352 vmcs_write(GUEST_PAT, 0x6); 353 } else { 354 report("Exit save PAT", guest_pat == 0x6); 355 } 356 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) 357 printf("\tEXI_LOAD_PAT is not supported\n"); 358 else 359 report("Exit load PAT", rdmsr(MSR_IA32_CR_PAT) == ia32_pat); 360 vmcs_write(GUEST_PAT, ia32_pat); 361 vmcs_write(GUEST_RIP, guest_rip + 3); 362 return VMX_TEST_RESUME; 363 default: 364 printf("ERROR : Undefined exit reason, reason = %ld.\n", reason); 365 break; 366 } 367 return VMX_TEST_VMEXIT; 368 } 369 370 static int test_ctrl_efer_init(struct vmcs *vmcs) 371 { 372 u64 ctrl_ent; 373 u64 ctrl_exi; 374 375 msr_bmp_init(); 376 ctrl_ent = vmcs_read(ENT_CONTROLS) | ENT_LOAD_EFER; 377 ctrl_exi = vmcs_read(EXI_CONTROLS) | EXI_SAVE_EFER | EXI_LOAD_EFER; 378 vmcs_write(ENT_CONTROLS, ctrl_ent & ctrl_enter_rev.clr); 379 vmcs_write(EXI_CONTROLS, ctrl_exi & ctrl_exit_rev.clr); 380 ia32_efer = rdmsr(MSR_EFER); 381 vmcs_write(GUEST_EFER, ia32_efer ^ EFER_NX); 382 vmcs_write(HOST_EFER, ia32_efer ^ EFER_NX); 383 return VMX_TEST_START; 384 } 385 386 static void test_ctrl_efer_main(void) 387 { 388 u64 guest_ia32_efer; 389 390 guest_ia32_efer = rdmsr(MSR_EFER); 391 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) 392 printf("\tENT_LOAD_EFER is not supported.\n"); 393 else { 394 if (guest_ia32_efer != (ia32_efer ^ EFER_NX)) { 395 report("Entry load EFER", 0); 396 return; 397 } 398 } 399 wrmsr(MSR_EFER, ia32_efer); 400 vmcall(); 401 guest_ia32_efer = rdmsr(MSR_EFER); 402 if (ctrl_enter_rev.clr & ENT_LOAD_EFER) 403 report("Entry load EFER", guest_ia32_efer == ia32_efer); 404 } 405 406 static int test_ctrl_efer_exit_handler(void) 407 { 408 u64 guest_rip; 409 ulong reason; 410 u64 guest_efer; 411 412 guest_rip = vmcs_read(GUEST_RIP); 413 reason = vmcs_read(EXI_REASON) & 0xff; 414 switch (reason) { 415 case VMX_VMCALL: 416 guest_efer = vmcs_read(GUEST_EFER); 417 if (!(ctrl_exit_rev.clr & EXI_SAVE_EFER)) { 418 printf("\tEXI_SAVE_EFER is not supported\n"); 419 vmcs_write(GUEST_EFER, ia32_efer); 420 } else { 421 report("Exit save EFER", guest_efer == ia32_efer); 422 } 423 if (!(ctrl_exit_rev.clr & EXI_LOAD_EFER)) { 424 printf("\tEXI_LOAD_EFER is not supported\n"); 425 wrmsr(MSR_EFER, ia32_efer ^ EFER_NX); 426 } else { 427 report("Exit load EFER", rdmsr(MSR_EFER) == (ia32_efer ^ EFER_NX)); 428 } 429 vmcs_write(GUEST_PAT, ia32_efer); 430 vmcs_write(GUEST_RIP, guest_rip + 3); 431 return VMX_TEST_RESUME; 432 default: 433 printf("ERROR : Undefined exit reason, reason = %ld.\n", reason); 434 break; 435 } 436 return VMX_TEST_VMEXIT; 437 } 438 439 u32 guest_cr0, guest_cr4; 440 441 static void cr_shadowing_main(void) 442 { 443 u32 cr0, cr4, tmp; 444 445 // Test read through 446 vmx_set_test_stage(0); 447 guest_cr0 = read_cr0(); 448 if (vmx_get_test_stage() == 1) 449 report("Read through CR0", 0); 450 else 451 vmcall(); 452 vmx_set_test_stage(1); 453 guest_cr4 = read_cr4(); 454 if (vmx_get_test_stage() == 2) 455 report("Read through CR4", 0); 456 else 457 vmcall(); 458 // Test write through 459 guest_cr0 = guest_cr0 ^ (X86_CR0_TS | X86_CR0_MP); 460 guest_cr4 = guest_cr4 ^ (X86_CR4_TSD | X86_CR4_DE); 461 vmx_set_test_stage(2); 462 write_cr0(guest_cr0); 463 if (vmx_get_test_stage() == 3) 464 report("Write throuth CR0", 0); 465 else 466 vmcall(); 467 vmx_set_test_stage(3); 468 write_cr4(guest_cr4); 469 if (vmx_get_test_stage() == 4) 470 report("Write through CR4", 0); 471 else 472 vmcall(); 473 // Test read shadow 474 vmx_set_test_stage(4); 475 vmcall(); 476 cr0 = read_cr0(); 477 if (vmx_get_test_stage() != 5) 478 report("Read shadowing CR0", cr0 == guest_cr0); 479 vmx_set_test_stage(5); 480 cr4 = read_cr4(); 481 if (vmx_get_test_stage() != 6) 482 report("Read shadowing CR4", cr4 == guest_cr4); 483 // Test write shadow (same value with shadow) 484 vmx_set_test_stage(6); 485 write_cr0(guest_cr0); 486 if (vmx_get_test_stage() == 7) 487 report("Write shadowing CR0 (same value with shadow)", 0); 488 else 489 vmcall(); 490 vmx_set_test_stage(7); 491 write_cr4(guest_cr4); 492 if (vmx_get_test_stage() == 8) 493 report("Write shadowing CR4 (same value with shadow)", 0); 494 else 495 vmcall(); 496 // Test write shadow (different value) 497 vmx_set_test_stage(8); 498 tmp = guest_cr0 ^ X86_CR0_TS; 499 asm volatile("mov %0, %%rsi\n\t" 500 "mov %%rsi, %%cr0\n\t" 501 ::"m"(tmp) 502 :"rsi", "memory", "cc"); 503 report("Write shadowing different X86_CR0_TS", vmx_get_test_stage() == 9); 504 vmx_set_test_stage(9); 505 tmp = guest_cr0 ^ X86_CR0_MP; 506 asm volatile("mov %0, %%rsi\n\t" 507 "mov %%rsi, %%cr0\n\t" 508 ::"m"(tmp) 509 :"rsi", "memory", "cc"); 510 report("Write shadowing different X86_CR0_MP", vmx_get_test_stage() == 10); 511 vmx_set_test_stage(10); 512 tmp = guest_cr4 ^ X86_CR4_TSD; 513 asm volatile("mov %0, %%rsi\n\t" 514 "mov %%rsi, %%cr4\n\t" 515 ::"m"(tmp) 516 :"rsi", "memory", "cc"); 517 report("Write shadowing different X86_CR4_TSD", vmx_get_test_stage() == 11); 518 vmx_set_test_stage(11); 519 tmp = guest_cr4 ^ X86_CR4_DE; 520 asm volatile("mov %0, %%rsi\n\t" 521 "mov %%rsi, %%cr4\n\t" 522 ::"m"(tmp) 523 :"rsi", "memory", "cc"); 524 report("Write shadowing different X86_CR4_DE", vmx_get_test_stage() == 12); 525 } 526 527 static int cr_shadowing_exit_handler(void) 528 { 529 u64 guest_rip; 530 ulong reason; 531 u32 insn_len; 532 u32 exit_qual; 533 534 guest_rip = vmcs_read(GUEST_RIP); 535 reason = vmcs_read(EXI_REASON) & 0xff; 536 insn_len = vmcs_read(EXI_INST_LEN); 537 exit_qual = vmcs_read(EXI_QUALIFICATION); 538 switch (reason) { 539 case VMX_VMCALL: 540 switch (vmx_get_test_stage()) { 541 case 0: 542 report("Read through CR0", guest_cr0 == vmcs_read(GUEST_CR0)); 543 break; 544 case 1: 545 report("Read through CR4", guest_cr4 == vmcs_read(GUEST_CR4)); 546 break; 547 case 2: 548 report("Write through CR0", guest_cr0 == vmcs_read(GUEST_CR0)); 549 break; 550 case 3: 551 report("Write through CR4", guest_cr4 == vmcs_read(GUEST_CR4)); 552 break; 553 case 4: 554 guest_cr0 = vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP); 555 guest_cr4 = vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE); 556 vmcs_write(CR0_MASK, X86_CR0_TS | X86_CR0_MP); 557 vmcs_write(CR0_READ_SHADOW, guest_cr0 & (X86_CR0_TS | X86_CR0_MP)); 558 vmcs_write(CR4_MASK, X86_CR4_TSD | X86_CR4_DE); 559 vmcs_write(CR4_READ_SHADOW, guest_cr4 & (X86_CR4_TSD | X86_CR4_DE)); 560 break; 561 case 6: 562 report("Write shadowing CR0 (same value)", 563 guest_cr0 == (vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP))); 564 break; 565 case 7: 566 report("Write shadowing CR4 (same value)", 567 guest_cr4 == (vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE))); 568 break; 569 default: 570 // Should not reach here 571 report("unexpected stage, %d", false, 572 vmx_get_test_stage()); 573 print_vmexit_info(); 574 return VMX_TEST_VMEXIT; 575 } 576 vmcs_write(GUEST_RIP, guest_rip + insn_len); 577 return VMX_TEST_RESUME; 578 case VMX_CR: 579 switch (vmx_get_test_stage()) { 580 case 4: 581 report("Read shadowing CR0", 0); 582 vmx_inc_test_stage(); 583 break; 584 case 5: 585 report("Read shadowing CR4", 0); 586 vmx_inc_test_stage(); 587 break; 588 case 6: 589 report("Write shadowing CR0 (same value)", 0); 590 vmx_inc_test_stage(); 591 break; 592 case 7: 593 report("Write shadowing CR4 (same value)", 0); 594 vmx_inc_test_stage(); 595 break; 596 case 8: 597 case 9: 598 // 0x600 encodes "mov %esi, %cr0" 599 if (exit_qual == 0x600) 600 vmx_inc_test_stage(); 601 break; 602 case 10: 603 case 11: 604 // 0x604 encodes "mov %esi, %cr4" 605 if (exit_qual == 0x604) 606 vmx_inc_test_stage(); 607 break; 608 default: 609 // Should not reach here 610 report("unexpected stage, %d", false, 611 vmx_get_test_stage()); 612 print_vmexit_info(); 613 return VMX_TEST_VMEXIT; 614 } 615 vmcs_write(GUEST_RIP, guest_rip + insn_len); 616 return VMX_TEST_RESUME; 617 default: 618 report("Unknown exit reason, %ld", false, reason); 619 print_vmexit_info(); 620 } 621 return VMX_TEST_VMEXIT; 622 } 623 624 static int iobmp_init(struct vmcs *vmcs) 625 { 626 u32 ctrl_cpu0; 627 628 io_bitmap_a = alloc_page(); 629 io_bitmap_b = alloc_page(); 630 memset(io_bitmap_a, 0x0, PAGE_SIZE); 631 memset(io_bitmap_b, 0x0, PAGE_SIZE); 632 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 633 ctrl_cpu0 |= CPU_IO_BITMAP; 634 ctrl_cpu0 &= (~CPU_IO); 635 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 636 vmcs_write(IO_BITMAP_A, (u64)io_bitmap_a); 637 vmcs_write(IO_BITMAP_B, (u64)io_bitmap_b); 638 return VMX_TEST_START; 639 } 640 641 static void iobmp_main(void) 642 { 643 // stage 0, test IO pass 644 vmx_set_test_stage(0); 645 inb(0x5000); 646 outb(0x0, 0x5000); 647 report("I/O bitmap - I/O pass", vmx_get_test_stage() == 0); 648 // test IO width, in/out 649 ((u8 *)io_bitmap_a)[0] = 0xFF; 650 vmx_set_test_stage(2); 651 inb(0x0); 652 report("I/O bitmap - trap in", vmx_get_test_stage() == 3); 653 vmx_set_test_stage(3); 654 outw(0x0, 0x0); 655 report("I/O bitmap - trap out", vmx_get_test_stage() == 4); 656 vmx_set_test_stage(4); 657 inl(0x0); 658 report("I/O bitmap - I/O width, long", vmx_get_test_stage() == 5); 659 // test low/high IO port 660 vmx_set_test_stage(5); 661 ((u8 *)io_bitmap_a)[0x5000 / 8] = (1 << (0x5000 % 8)); 662 inb(0x5000); 663 report("I/O bitmap - I/O port, low part", vmx_get_test_stage() == 6); 664 vmx_set_test_stage(6); 665 ((u8 *)io_bitmap_b)[0x1000 / 8] = (1 << (0x1000 % 8)); 666 inb(0x9000); 667 report("I/O bitmap - I/O port, high part", vmx_get_test_stage() == 7); 668 // test partial pass 669 vmx_set_test_stage(7); 670 inl(0x4FFF); 671 report("I/O bitmap - partial pass", vmx_get_test_stage() == 8); 672 // test overrun 673 vmx_set_test_stage(8); 674 memset(io_bitmap_a, 0x0, PAGE_SIZE); 675 memset(io_bitmap_b, 0x0, PAGE_SIZE); 676 inl(0xFFFF); 677 report("I/O bitmap - overrun", vmx_get_test_stage() == 9); 678 vmx_set_test_stage(9); 679 vmcall(); 680 outb(0x0, 0x0); 681 report("I/O bitmap - ignore unconditional exiting", 682 vmx_get_test_stage() == 9); 683 vmx_set_test_stage(10); 684 vmcall(); 685 outb(0x0, 0x0); 686 report("I/O bitmap - unconditional exiting", 687 vmx_get_test_stage() == 11); 688 } 689 690 static int iobmp_exit_handler(void) 691 { 692 u64 guest_rip; 693 ulong reason, exit_qual; 694 u32 insn_len, ctrl_cpu0; 695 696 guest_rip = vmcs_read(GUEST_RIP); 697 reason = vmcs_read(EXI_REASON) & 0xff; 698 exit_qual = vmcs_read(EXI_QUALIFICATION); 699 insn_len = vmcs_read(EXI_INST_LEN); 700 switch (reason) { 701 case VMX_IO: 702 switch (vmx_get_test_stage()) { 703 case 0: 704 case 1: 705 vmx_inc_test_stage(); 706 break; 707 case 2: 708 report("I/O bitmap - I/O width, byte", 709 (exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_BYTE); 710 report("I/O bitmap - I/O direction, in", exit_qual & VMX_IO_IN); 711 vmx_inc_test_stage(); 712 break; 713 case 3: 714 report("I/O bitmap - I/O width, word", 715 (exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_WORD); 716 report("I/O bitmap - I/O direction, out", 717 !(exit_qual & VMX_IO_IN)); 718 vmx_inc_test_stage(); 719 break; 720 case 4: 721 report("I/O bitmap - I/O width, long", 722 (exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_LONG); 723 vmx_inc_test_stage(); 724 break; 725 case 5: 726 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x5000) 727 vmx_inc_test_stage(); 728 break; 729 case 6: 730 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x9000) 731 vmx_inc_test_stage(); 732 break; 733 case 7: 734 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x4FFF) 735 vmx_inc_test_stage(); 736 break; 737 case 8: 738 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0xFFFF) 739 vmx_inc_test_stage(); 740 break; 741 case 9: 742 case 10: 743 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 744 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0 & ~CPU_IO); 745 vmx_inc_test_stage(); 746 break; 747 default: 748 // Should not reach here 749 report("unexpected stage, %d", false, 750 vmx_get_test_stage()); 751 print_vmexit_info(); 752 return VMX_TEST_VMEXIT; 753 } 754 vmcs_write(GUEST_RIP, guest_rip + insn_len); 755 return VMX_TEST_RESUME; 756 case VMX_VMCALL: 757 switch (vmx_get_test_stage()) { 758 case 9: 759 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 760 ctrl_cpu0 |= CPU_IO | CPU_IO_BITMAP; 761 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 762 break; 763 case 10: 764 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 765 ctrl_cpu0 = (ctrl_cpu0 & ~CPU_IO_BITMAP) | CPU_IO; 766 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 767 break; 768 default: 769 // Should not reach here 770 report("unexpected stage, %d", false, 771 vmx_get_test_stage()); 772 print_vmexit_info(); 773 return VMX_TEST_VMEXIT; 774 } 775 vmcs_write(GUEST_RIP, guest_rip + insn_len); 776 return VMX_TEST_RESUME; 777 default: 778 printf("guest_rip = %#lx\n", guest_rip); 779 printf("\tERROR : Undefined exit reason, reason = %ld.\n", reason); 780 break; 781 } 782 return VMX_TEST_VMEXIT; 783 } 784 785 #define INSN_CPU0 0 786 #define INSN_CPU1 1 787 #define INSN_ALWAYS_TRAP 2 788 789 #define FIELD_EXIT_QUAL (1 << 0) 790 #define FIELD_INSN_INFO (1 << 1) 791 792 asm( 793 "insn_hlt: hlt;ret\n\t" 794 "insn_invlpg: invlpg 0x12345678;ret\n\t" 795 "insn_mwait: xor %eax, %eax; xor %ecx, %ecx; mwait;ret\n\t" 796 "insn_rdpmc: xor %ecx, %ecx; rdpmc;ret\n\t" 797 "insn_rdtsc: rdtsc;ret\n\t" 798 "insn_cr3_load: mov cr3,%rax; mov %rax,%cr3;ret\n\t" 799 "insn_cr3_store: mov %cr3,%rax;ret\n\t" 800 #ifdef __x86_64__ 801 "insn_cr8_load: xor %eax, %eax; mov %rax,%cr8;ret\n\t" 802 "insn_cr8_store: mov %cr8,%rax;ret\n\t" 803 #endif 804 "insn_monitor: xor %eax, %eax; xor %ecx, %ecx; xor %edx, %edx; monitor;ret\n\t" 805 "insn_pause: pause;ret\n\t" 806 "insn_wbinvd: wbinvd;ret\n\t" 807 "insn_cpuid: mov $10, %eax; cpuid;ret\n\t" 808 "insn_invd: invd;ret\n\t" 809 "insn_sgdt: sgdt gdt64_desc;ret\n\t" 810 "insn_lgdt: lgdt gdt64_desc;ret\n\t" 811 "insn_sidt: sidt idt_descr;ret\n\t" 812 "insn_lidt: lidt idt_descr;ret\n\t" 813 "insn_sldt: sldt %ax;ret\n\t" 814 "insn_lldt: xor %eax, %eax; lldt %ax;ret\n\t" 815 "insn_str: str %ax;ret\n\t" 816 "insn_rdrand: rdrand %rax;ret\n\t" 817 "insn_rdseed: rdseed %rax;ret\n\t" 818 ); 819 extern void insn_hlt(void); 820 extern void insn_invlpg(void); 821 extern void insn_mwait(void); 822 extern void insn_rdpmc(void); 823 extern void insn_rdtsc(void); 824 extern void insn_cr3_load(void); 825 extern void insn_cr3_store(void); 826 #ifdef __x86_64__ 827 extern void insn_cr8_load(void); 828 extern void insn_cr8_store(void); 829 #endif 830 extern void insn_monitor(void); 831 extern void insn_pause(void); 832 extern void insn_wbinvd(void); 833 extern void insn_sgdt(void); 834 extern void insn_lgdt(void); 835 extern void insn_sidt(void); 836 extern void insn_lidt(void); 837 extern void insn_sldt(void); 838 extern void insn_lldt(void); 839 extern void insn_str(void); 840 extern void insn_cpuid(void); 841 extern void insn_invd(void); 842 extern void insn_rdrand(void); 843 extern void insn_rdseed(void); 844 845 u32 cur_insn; 846 u64 cr3; 847 848 struct insn_table { 849 const char *name; 850 u32 flag; 851 void (*insn_func)(void); 852 u32 type; 853 u32 reason; 854 ulong exit_qual; 855 u32 insn_info; 856 // Use FIELD_EXIT_QUAL and FIELD_INSN_INFO to define 857 // which field need to be tested, reason is always tested 858 u32 test_field; 859 }; 860 861 /* 862 * Add more test cases of instruction intercept here. Elements in this 863 * table is: 864 * name/control flag/insn function/type/exit reason/exit qulification/ 865 * instruction info/field to test 866 * The last field defines which fields (exit_qual and insn_info) need to be 867 * tested in exit handler. If set to 0, only "reason" is checked. 868 */ 869 static struct insn_table insn_table[] = { 870 // Flags for Primary Processor-Based VM-Execution Controls 871 {"HLT", CPU_HLT, insn_hlt, INSN_CPU0, 12, 0, 0, 0}, 872 {"INVLPG", CPU_INVLPG, insn_invlpg, INSN_CPU0, 14, 873 0x12345678, 0, FIELD_EXIT_QUAL}, 874 {"MWAIT", CPU_MWAIT, insn_mwait, INSN_CPU0, 36, 0, 0, 0}, 875 {"RDPMC", CPU_RDPMC, insn_rdpmc, INSN_CPU0, 15, 0, 0, 0}, 876 {"RDTSC", CPU_RDTSC, insn_rdtsc, INSN_CPU0, 16, 0, 0, 0}, 877 {"CR3 load", CPU_CR3_LOAD, insn_cr3_load, INSN_CPU0, 28, 0x3, 0, 878 FIELD_EXIT_QUAL}, 879 {"CR3 store", CPU_CR3_STORE, insn_cr3_store, INSN_CPU0, 28, 0x13, 0, 880 FIELD_EXIT_QUAL}, 881 #ifdef __x86_64__ 882 {"CR8 load", CPU_CR8_LOAD, insn_cr8_load, INSN_CPU0, 28, 0x8, 0, 883 FIELD_EXIT_QUAL}, 884 {"CR8 store", CPU_CR8_STORE, insn_cr8_store, INSN_CPU0, 28, 0x18, 0, 885 FIELD_EXIT_QUAL}, 886 #endif 887 {"MONITOR", CPU_MONITOR, insn_monitor, INSN_CPU0, 39, 0, 0, 0}, 888 {"PAUSE", CPU_PAUSE, insn_pause, INSN_CPU0, 40, 0, 0, 0}, 889 // Flags for Secondary Processor-Based VM-Execution Controls 890 {"WBINVD", CPU_WBINVD, insn_wbinvd, INSN_CPU1, 54, 0, 0, 0}, 891 {"DESC_TABLE (SGDT)", CPU_DESC_TABLE, insn_sgdt, INSN_CPU1, 46, 0, 0, 0}, 892 {"DESC_TABLE (LGDT)", CPU_DESC_TABLE, insn_lgdt, INSN_CPU1, 46, 0, 0, 0}, 893 {"DESC_TABLE (SIDT)", CPU_DESC_TABLE, insn_sidt, INSN_CPU1, 46, 0, 0, 0}, 894 {"DESC_TABLE (LIDT)", CPU_DESC_TABLE, insn_lidt, INSN_CPU1, 46, 0, 0, 0}, 895 {"DESC_TABLE (SLDT)", CPU_DESC_TABLE, insn_sldt, INSN_CPU1, 47, 0, 0, 0}, 896 {"DESC_TABLE (LLDT)", CPU_DESC_TABLE, insn_lldt, INSN_CPU1, 47, 0, 0, 0}, 897 {"DESC_TABLE (STR)", CPU_DESC_TABLE, insn_str, INSN_CPU1, 47, 0, 0, 0}, 898 /* LTR causes a #GP if done with a busy selector, so it is not tested. */ 899 {"RDRAND", CPU_RDRAND, insn_rdrand, INSN_CPU1, VMX_RDRAND, 0, 0, 0}, 900 {"RDSEED", CPU_RDSEED, insn_rdseed, INSN_CPU1, VMX_RDSEED, 0, 0, 0}, 901 // Instructions always trap 902 {"CPUID", 0, insn_cpuid, INSN_ALWAYS_TRAP, 10, 0, 0, 0}, 903 {"INVD", 0, insn_invd, INSN_ALWAYS_TRAP, 13, 0, 0, 0}, 904 // Instructions never trap 905 {NULL}, 906 }; 907 908 static int insn_intercept_init(struct vmcs *vmcs) 909 { 910 u32 ctrl_cpu; 911 912 ctrl_cpu = ctrl_cpu_rev[0].set | CPU_SECONDARY; 913 ctrl_cpu &= ctrl_cpu_rev[0].clr; 914 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu); 915 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu_rev[1].set); 916 cr3 = read_cr3(); 917 return VMX_TEST_START; 918 } 919 920 static void insn_intercept_main(void) 921 { 922 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 923 vmx_set_test_stage(cur_insn * 2); 924 if ((insn_table[cur_insn].type == INSN_CPU0 && 925 !(ctrl_cpu_rev[0].clr & insn_table[cur_insn].flag)) || 926 (insn_table[cur_insn].type == INSN_CPU1 && 927 !(ctrl_cpu_rev[1].clr & insn_table[cur_insn].flag))) { 928 printf("\tCPU_CTRL%d.CPU_%s is not supported.\n", 929 insn_table[cur_insn].type - INSN_CPU0, 930 insn_table[cur_insn].name); 931 continue; 932 } 933 934 if ((insn_table[cur_insn].type == INSN_CPU0 && 935 !(ctrl_cpu_rev[0].set & insn_table[cur_insn].flag)) || 936 (insn_table[cur_insn].type == INSN_CPU1 && 937 !(ctrl_cpu_rev[1].set & insn_table[cur_insn].flag))) { 938 /* skip hlt, it stalls the guest and is tested below */ 939 if (insn_table[cur_insn].insn_func != insn_hlt) 940 insn_table[cur_insn].insn_func(); 941 report("execute %s", vmx_get_test_stage() == cur_insn * 2, 942 insn_table[cur_insn].name); 943 } else if (insn_table[cur_insn].type != INSN_ALWAYS_TRAP) 944 printf("\tCPU_CTRL%d.CPU_%s always traps.\n", 945 insn_table[cur_insn].type - INSN_CPU0, 946 insn_table[cur_insn].name); 947 948 vmcall(); 949 950 insn_table[cur_insn].insn_func(); 951 report("intercept %s", vmx_get_test_stage() == cur_insn * 2 + 1, 952 insn_table[cur_insn].name); 953 954 vmx_set_test_stage(cur_insn * 2 + 1); 955 vmcall(); 956 } 957 } 958 959 static int insn_intercept_exit_handler(void) 960 { 961 u64 guest_rip; 962 u32 reason; 963 ulong exit_qual; 964 u32 insn_len; 965 u32 insn_info; 966 bool pass; 967 968 guest_rip = vmcs_read(GUEST_RIP); 969 reason = vmcs_read(EXI_REASON) & 0xff; 970 exit_qual = vmcs_read(EXI_QUALIFICATION); 971 insn_len = vmcs_read(EXI_INST_LEN); 972 insn_info = vmcs_read(EXI_INST_INFO); 973 974 if (reason == VMX_VMCALL) { 975 u32 val = 0; 976 977 if (insn_table[cur_insn].type == INSN_CPU0) 978 val = vmcs_read(CPU_EXEC_CTRL0); 979 else if (insn_table[cur_insn].type == INSN_CPU1) 980 val = vmcs_read(CPU_EXEC_CTRL1); 981 982 if (vmx_get_test_stage() & 1) 983 val &= ~insn_table[cur_insn].flag; 984 else 985 val |= insn_table[cur_insn].flag; 986 987 if (insn_table[cur_insn].type == INSN_CPU0) 988 vmcs_write(CPU_EXEC_CTRL0, val | ctrl_cpu_rev[0].set); 989 else if (insn_table[cur_insn].type == INSN_CPU1) 990 vmcs_write(CPU_EXEC_CTRL1, val | ctrl_cpu_rev[1].set); 991 } else { 992 pass = (cur_insn * 2 == vmx_get_test_stage()) && 993 insn_table[cur_insn].reason == reason; 994 if (insn_table[cur_insn].test_field & FIELD_EXIT_QUAL && 995 insn_table[cur_insn].exit_qual != exit_qual) 996 pass = false; 997 if (insn_table[cur_insn].test_field & FIELD_INSN_INFO && 998 insn_table[cur_insn].insn_info != insn_info) 999 pass = false; 1000 if (pass) 1001 vmx_inc_test_stage(); 1002 } 1003 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1004 return VMX_TEST_RESUME; 1005 } 1006 1007 /** 1008 * __setup_ept - Setup the VMCS fields to enable Extended Page Tables (EPT) 1009 * @hpa: Host physical address of the top-level, a.k.a. root, EPT table 1010 * @enable_ad: Whether or not to enable Access/Dirty bits for EPT entries 1011 * 1012 * Returns 0 on success, 1 on failure. 1013 * 1014 * Note that @hpa doesn't need to point at actual memory if VM-Launch is 1015 * expected to fail, e.g. setup_dummy_ept() arbitrarily passes '0' to satisfy 1016 * the various EPTP consistency checks, but doesn't ensure backing for HPA '0'. 1017 */ 1018 static int __setup_ept(u64 hpa, bool enable_ad) 1019 { 1020 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1021 !(ctrl_cpu_rev[1].clr & CPU_EPT)) { 1022 printf("\tEPT is not supported"); 1023 return 1; 1024 } 1025 if (!(ept_vpid.val & EPT_CAP_WB)) { 1026 printf("WB memtype for EPT walks not supported\n"); 1027 return 1; 1028 } 1029 if (!(ept_vpid.val & EPT_CAP_PWL4)) { 1030 printf("\tPWL4 is not supported\n"); 1031 return 1; 1032 } 1033 1034 eptp = EPT_MEM_TYPE_WB; 1035 eptp |= (3 << EPTP_PG_WALK_LEN_SHIFT); 1036 eptp |= hpa; 1037 if (enable_ad) 1038 eptp |= EPTP_AD_FLAG; 1039 1040 vmcs_write(EPTP, eptp); 1041 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0)| CPU_SECONDARY); 1042 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1)| CPU_EPT); 1043 1044 return 0; 1045 } 1046 1047 /** 1048 * setup_ept - Enable Extended Page Tables (EPT) and setup an identity map 1049 * @enable_ad: Whether or not to enable Access/Dirty bits for EPT entries 1050 * 1051 * Returns 0 on success, 1 on failure. 1052 * 1053 * This is the "real" function for setting up EPT tables, i.e. use this for 1054 * tests that need to run code in the guest with EPT enabled. 1055 */ 1056 static int setup_ept(bool enable_ad) 1057 { 1058 unsigned long end_of_memory; 1059 1060 pml4 = alloc_page(); 1061 1062 if (__setup_ept(virt_to_phys(pml4), enable_ad)) 1063 return 1; 1064 1065 memset(pml4, 0, PAGE_SIZE); 1066 1067 end_of_memory = fwcfg_get_u64(FW_CFG_RAM_SIZE); 1068 if (end_of_memory < (1ul << 32)) 1069 end_of_memory = (1ul << 32); 1070 /* Cannot use large EPT pages if we need to track EPT 1071 * accessed/dirty bits at 4K granularity. 1072 */ 1073 setup_ept_range(pml4, 0, end_of_memory, 0, 1074 !enable_ad && ept_2m_supported(), 1075 EPT_WA | EPT_RA | EPT_EA); 1076 return 0; 1077 } 1078 1079 /** 1080 * setup_dummy_ept - Enable Extended Page Tables (EPT) with a dummy root HPA 1081 * 1082 * Setup EPT using a semi-arbitrary dummy root HPA. This function is intended 1083 * for use by tests that need EPT enabled to verify dependent VMCS controls 1084 * but never expect to fully enter the guest, i.e. don't need setup the actual 1085 * EPT tables. 1086 */ 1087 static void setup_dummy_ept(void) 1088 { 1089 if (__setup_ept(0, false)) 1090 report_abort("EPT setup unexpectedly failed"); 1091 } 1092 1093 static int enable_unrestricted_guest(void) 1094 { 1095 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1096 !(ctrl_cpu_rev[1].clr & CPU_URG) || 1097 !(ctrl_cpu_rev[1].clr & CPU_EPT)) 1098 return 1; 1099 1100 setup_dummy_ept(); 1101 1102 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 1103 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | CPU_URG); 1104 1105 return 0; 1106 } 1107 1108 static void ept_enable_ad_bits(void) 1109 { 1110 eptp |= EPTP_AD_FLAG; 1111 vmcs_write(EPTP, eptp); 1112 } 1113 1114 static void ept_disable_ad_bits(void) 1115 { 1116 eptp &= ~EPTP_AD_FLAG; 1117 vmcs_write(EPTP, eptp); 1118 } 1119 1120 static void ept_enable_ad_bits_or_skip_test(void) 1121 { 1122 if (!ept_ad_bits_supported()) 1123 test_skip("EPT AD bits not supported."); 1124 ept_enable_ad_bits(); 1125 } 1126 1127 static int apic_version; 1128 1129 static int ept_init_common(bool have_ad) 1130 { 1131 int ret; 1132 struct pci_dev pcidev; 1133 1134 if (setup_ept(have_ad)) 1135 return VMX_TEST_EXIT; 1136 data_page1 = alloc_page(); 1137 data_page2 = alloc_page(); 1138 memset(data_page1, 0x0, PAGE_SIZE); 1139 memset(data_page2, 0x0, PAGE_SIZE); 1140 *((u32 *)data_page1) = MAGIC_VAL_1; 1141 *((u32 *)data_page2) = MAGIC_VAL_2; 1142 install_ept(pml4, (unsigned long)data_page1, (unsigned long)data_page2, 1143 EPT_RA | EPT_WA | EPT_EA); 1144 1145 apic_version = apic_read(APIC_LVR); 1146 1147 ret = pci_find_dev(PCI_VENDOR_ID_REDHAT, PCI_DEVICE_ID_REDHAT_TEST); 1148 if (ret != PCIDEVADDR_INVALID) { 1149 pci_dev_init(&pcidev, ret); 1150 pci_physaddr = pcidev.resource[PCI_TESTDEV_BAR_MEM]; 1151 } 1152 1153 return VMX_TEST_START; 1154 } 1155 1156 static int ept_init(struct vmcs *vmcs) 1157 { 1158 return ept_init_common(false); 1159 } 1160 1161 static void ept_common(void) 1162 { 1163 vmx_set_test_stage(0); 1164 if (*((u32 *)data_page2) != MAGIC_VAL_1 || 1165 *((u32 *)data_page1) != MAGIC_VAL_1) 1166 report("EPT basic framework - read", 0); 1167 else { 1168 *((u32 *)data_page2) = MAGIC_VAL_3; 1169 vmcall(); 1170 if (vmx_get_test_stage() == 1) { 1171 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1172 *((u32 *)data_page2) == MAGIC_VAL_2) 1173 report("EPT basic framework", 1); 1174 else 1175 report("EPT basic framework - remap", 1); 1176 } 1177 } 1178 // Test EPT Misconfigurations 1179 vmx_set_test_stage(1); 1180 vmcall(); 1181 *((u32 *)data_page1) = MAGIC_VAL_1; 1182 if (vmx_get_test_stage() != 2) { 1183 report("EPT misconfigurations", 0); 1184 goto t1; 1185 } 1186 vmx_set_test_stage(2); 1187 vmcall(); 1188 *((u32 *)data_page1) = MAGIC_VAL_1; 1189 report("EPT misconfigurations", vmx_get_test_stage() == 3); 1190 t1: 1191 // Test EPT violation 1192 vmx_set_test_stage(3); 1193 vmcall(); 1194 *((u32 *)data_page1) = MAGIC_VAL_1; 1195 report("EPT violation - page permission", vmx_get_test_stage() == 4); 1196 // Violation caused by EPT paging structure 1197 vmx_set_test_stage(4); 1198 vmcall(); 1199 *((u32 *)data_page1) = MAGIC_VAL_2; 1200 report("EPT violation - paging structure", vmx_get_test_stage() == 5); 1201 1202 // MMIO Read/Write 1203 vmx_set_test_stage(5); 1204 vmcall(); 1205 1206 *(u32 volatile *)pci_physaddr; 1207 report("MMIO EPT violation - read", vmx_get_test_stage() == 6); 1208 1209 *(u32 volatile *)pci_physaddr = MAGIC_VAL_1; 1210 report("MMIO EPT violation - write", vmx_get_test_stage() == 7); 1211 } 1212 1213 static void ept_main(void) 1214 { 1215 ept_common(); 1216 1217 // Test EPT access to L1 MMIO 1218 vmx_set_test_stage(7); 1219 report("EPT - MMIO access", *((u32 *)0xfee00030UL) == apic_version); 1220 1221 // Test invalid operand for INVEPT 1222 vmcall(); 1223 report("EPT - unsupported INVEPT", vmx_get_test_stage() == 8); 1224 } 1225 1226 static bool invept_test(int type, u64 eptp) 1227 { 1228 bool ret, supported; 1229 1230 supported = ept_vpid.val & (EPT_CAP_INVEPT_SINGLE >> INVEPT_SINGLE << type); 1231 ret = invept(type, eptp); 1232 1233 if (ret == !supported) 1234 return false; 1235 1236 if (!supported) 1237 printf("WARNING: unsupported invept passed!\n"); 1238 else 1239 printf("WARNING: invept failed!\n"); 1240 1241 return true; 1242 } 1243 1244 static int pml_exit_handler(void) 1245 { 1246 u16 index, count; 1247 ulong reason = vmcs_read(EXI_REASON) & 0xff; 1248 u64 *pmlbuf = pml_log; 1249 u64 guest_rip = vmcs_read(GUEST_RIP);; 1250 u64 guest_cr3 = vmcs_read(GUEST_CR3); 1251 u32 insn_len = vmcs_read(EXI_INST_LEN); 1252 1253 switch (reason) { 1254 case VMX_VMCALL: 1255 switch (vmx_get_test_stage()) { 1256 case 0: 1257 index = vmcs_read(GUEST_PML_INDEX); 1258 for (count = index + 1; count < PML_INDEX; count++) { 1259 if (pmlbuf[count] == (u64)data_page2) { 1260 vmx_inc_test_stage(); 1261 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1262 break; 1263 } 1264 } 1265 break; 1266 case 1: 1267 index = vmcs_read(GUEST_PML_INDEX); 1268 /* Keep clearing the dirty bit till a overflow */ 1269 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1270 break; 1271 default: 1272 report("unexpected stage, %d.", false, 1273 vmx_get_test_stage()); 1274 print_vmexit_info(); 1275 return VMX_TEST_VMEXIT; 1276 } 1277 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1278 return VMX_TEST_RESUME; 1279 case VMX_PML_FULL: 1280 vmx_inc_test_stage(); 1281 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1282 return VMX_TEST_RESUME; 1283 default: 1284 report("Unknown exit reason, %ld", false, reason); 1285 print_vmexit_info(); 1286 } 1287 return VMX_TEST_VMEXIT; 1288 } 1289 1290 static int ept_exit_handler_common(bool have_ad) 1291 { 1292 u64 guest_rip; 1293 u64 guest_cr3; 1294 ulong reason; 1295 u32 insn_len; 1296 u32 exit_qual; 1297 static unsigned long data_page1_pte, data_page1_pte_pte, memaddr_pte; 1298 1299 guest_rip = vmcs_read(GUEST_RIP); 1300 guest_cr3 = vmcs_read(GUEST_CR3); 1301 reason = vmcs_read(EXI_REASON) & 0xff; 1302 insn_len = vmcs_read(EXI_INST_LEN); 1303 exit_qual = vmcs_read(EXI_QUALIFICATION); 1304 switch (reason) { 1305 case VMX_VMCALL: 1306 switch (vmx_get_test_stage()) { 1307 case 0: 1308 check_ept_ad(pml4, guest_cr3, 1309 (unsigned long)data_page1, 1310 have_ad ? EPT_ACCESS_FLAG : 0, 1311 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1312 check_ept_ad(pml4, guest_cr3, 1313 (unsigned long)data_page2, 1314 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0, 1315 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1316 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1317 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1318 if (have_ad) 1319 ept_sync(INVEPT_SINGLE, eptp);; 1320 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1321 *((u32 *)data_page2) == MAGIC_VAL_2) { 1322 vmx_inc_test_stage(); 1323 install_ept(pml4, (unsigned long)data_page2, 1324 (unsigned long)data_page2, 1325 EPT_RA | EPT_WA | EPT_EA); 1326 } else 1327 report("EPT basic framework - write", 0); 1328 break; 1329 case 1: 1330 install_ept(pml4, (unsigned long)data_page1, 1331 (unsigned long)data_page1, EPT_WA); 1332 ept_sync(INVEPT_SINGLE, eptp); 1333 break; 1334 case 2: 1335 install_ept(pml4, (unsigned long)data_page1, 1336 (unsigned long)data_page1, 1337 EPT_RA | EPT_WA | EPT_EA | 1338 (2 << EPT_MEM_TYPE_SHIFT)); 1339 ept_sync(INVEPT_SINGLE, eptp); 1340 break; 1341 case 3: 1342 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1343 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)data_page1, 1344 1, &data_page1_pte)); 1345 set_ept_pte(pml4, (unsigned long)data_page1, 1346 1, data_page1_pte & ~EPT_PRESENT); 1347 ept_sync(INVEPT_SINGLE, eptp); 1348 break; 1349 case 4: 1350 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)data_page1, 1351 2, &data_page1_pte)); 1352 data_page1_pte &= PAGE_MASK; 1353 TEST_ASSERT(get_ept_pte(pml4, data_page1_pte, 1354 2, &data_page1_pte_pte)); 1355 set_ept_pte(pml4, data_page1_pte, 2, 1356 data_page1_pte_pte & ~EPT_PRESENT); 1357 ept_sync(INVEPT_SINGLE, eptp); 1358 break; 1359 case 5: 1360 install_ept(pml4, (unsigned long)pci_physaddr, 1361 (unsigned long)pci_physaddr, 0); 1362 ept_sync(INVEPT_SINGLE, eptp); 1363 break; 1364 case 7: 1365 if (!invept_test(0, eptp)) 1366 vmx_inc_test_stage(); 1367 break; 1368 // Should not reach here 1369 default: 1370 report("ERROR - unexpected stage, %d.", false, 1371 vmx_get_test_stage()); 1372 print_vmexit_info(); 1373 return VMX_TEST_VMEXIT; 1374 } 1375 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1376 return VMX_TEST_RESUME; 1377 case VMX_EPT_MISCONFIG: 1378 switch (vmx_get_test_stage()) { 1379 case 1: 1380 case 2: 1381 vmx_inc_test_stage(); 1382 install_ept(pml4, (unsigned long)data_page1, 1383 (unsigned long)data_page1, 1384 EPT_RA | EPT_WA | EPT_EA); 1385 ept_sync(INVEPT_SINGLE, eptp); 1386 break; 1387 // Should not reach here 1388 default: 1389 report("ERROR - unexpected stage, %d.", false, 1390 vmx_get_test_stage()); 1391 print_vmexit_info(); 1392 return VMX_TEST_VMEXIT; 1393 } 1394 return VMX_TEST_RESUME; 1395 case VMX_EPT_VIOLATION: 1396 switch(vmx_get_test_stage()) { 1397 case 3: 1398 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1399 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1400 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1401 if (exit_qual == (EPT_VLT_WR | EPT_VLT_LADDR_VLD | 1402 EPT_VLT_PADDR)) 1403 vmx_inc_test_stage(); 1404 set_ept_pte(pml4, (unsigned long)data_page1, 1405 1, data_page1_pte | (EPT_PRESENT)); 1406 ept_sync(INVEPT_SINGLE, eptp); 1407 break; 1408 case 4: 1409 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1410 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1411 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1412 if (exit_qual == (EPT_VLT_RD | 1413 (have_ad ? EPT_VLT_WR : 0) | 1414 EPT_VLT_LADDR_VLD)) 1415 vmx_inc_test_stage(); 1416 set_ept_pte(pml4, data_page1_pte, 2, 1417 data_page1_pte_pte | (EPT_PRESENT)); 1418 ept_sync(INVEPT_SINGLE, eptp); 1419 break; 1420 case 5: 1421 if (exit_qual & EPT_VLT_RD) 1422 vmx_inc_test_stage(); 1423 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1424 1, &memaddr_pte)); 1425 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA); 1426 ept_sync(INVEPT_SINGLE, eptp); 1427 break; 1428 case 6: 1429 if (exit_qual & EPT_VLT_WR) 1430 vmx_inc_test_stage(); 1431 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1432 1, &memaddr_pte)); 1433 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA | EPT_WA); 1434 ept_sync(INVEPT_SINGLE, eptp); 1435 break; 1436 default: 1437 // Should not reach here 1438 report("ERROR : unexpected stage, %d", false, 1439 vmx_get_test_stage()); 1440 print_vmexit_info(); 1441 return VMX_TEST_VMEXIT; 1442 } 1443 return VMX_TEST_RESUME; 1444 default: 1445 report("Unknown exit reason, %ld", false, reason); 1446 print_vmexit_info(); 1447 } 1448 return VMX_TEST_VMEXIT; 1449 } 1450 1451 static int ept_exit_handler(void) 1452 { 1453 return ept_exit_handler_common(false); 1454 } 1455 1456 static int eptad_init(struct vmcs *vmcs) 1457 { 1458 int r = ept_init_common(true); 1459 1460 if (r == VMX_TEST_EXIT) 1461 return r; 1462 1463 if ((rdmsr(MSR_IA32_VMX_EPT_VPID_CAP) & EPT_CAP_AD_FLAG) == 0) { 1464 printf("\tEPT A/D bits are not supported"); 1465 return VMX_TEST_EXIT; 1466 } 1467 1468 return r; 1469 } 1470 1471 static int pml_init(struct vmcs *vmcs) 1472 { 1473 u32 ctrl_cpu; 1474 int r = eptad_init(vmcs); 1475 1476 if (r == VMX_TEST_EXIT) 1477 return r; 1478 1479 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1480 !(ctrl_cpu_rev[1].clr & CPU_PML)) { 1481 printf("\tPML is not supported"); 1482 return VMX_TEST_EXIT; 1483 } 1484 1485 pml_log = alloc_page(); 1486 memset(pml_log, 0x0, PAGE_SIZE); 1487 vmcs_write(PMLADDR, (u64)pml_log); 1488 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1489 1490 ctrl_cpu = vmcs_read(CPU_EXEC_CTRL1) | CPU_PML; 1491 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu); 1492 1493 return VMX_TEST_START; 1494 } 1495 1496 static void pml_main(void) 1497 { 1498 int count = 0; 1499 1500 vmx_set_test_stage(0); 1501 *((u32 *)data_page2) = 0x1; 1502 vmcall(); 1503 report("PML - Dirty GPA Logging", vmx_get_test_stage() == 1); 1504 1505 while (vmx_get_test_stage() == 1) { 1506 vmcall(); 1507 *((u32 *)data_page2) = 0x1; 1508 if (count++ > PML_INDEX) 1509 break; 1510 } 1511 report("PML Full Event", vmx_get_test_stage() == 2); 1512 } 1513 1514 static void eptad_main(void) 1515 { 1516 ept_common(); 1517 } 1518 1519 static int eptad_exit_handler(void) 1520 { 1521 return ept_exit_handler_common(true); 1522 } 1523 1524 static bool invvpid_test(int type, u16 vpid) 1525 { 1526 bool ret, supported; 1527 1528 supported = ept_vpid.val & 1529 (VPID_CAP_INVVPID_ADDR >> INVVPID_ADDR << type); 1530 ret = invvpid(type, vpid, 0); 1531 1532 if (ret == !supported) 1533 return false; 1534 1535 if (!supported) 1536 printf("WARNING: unsupported invvpid passed!\n"); 1537 else 1538 printf("WARNING: invvpid failed!\n"); 1539 1540 return true; 1541 } 1542 1543 static int vpid_init(struct vmcs *vmcs) 1544 { 1545 u32 ctrl_cpu1; 1546 1547 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1548 !(ctrl_cpu_rev[1].clr & CPU_VPID)) { 1549 printf("\tVPID is not supported"); 1550 return VMX_TEST_EXIT; 1551 } 1552 1553 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 1554 ctrl_cpu1 |= CPU_VPID; 1555 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 1556 return VMX_TEST_START; 1557 } 1558 1559 static void vpid_main(void) 1560 { 1561 vmx_set_test_stage(0); 1562 vmcall(); 1563 report("INVVPID SINGLE ADDRESS", vmx_get_test_stage() == 1); 1564 vmx_set_test_stage(2); 1565 vmcall(); 1566 report("INVVPID SINGLE", vmx_get_test_stage() == 3); 1567 vmx_set_test_stage(4); 1568 vmcall(); 1569 report("INVVPID ALL", vmx_get_test_stage() == 5); 1570 } 1571 1572 static int vpid_exit_handler(void) 1573 { 1574 u64 guest_rip; 1575 ulong reason; 1576 u32 insn_len; 1577 1578 guest_rip = vmcs_read(GUEST_RIP); 1579 reason = vmcs_read(EXI_REASON) & 0xff; 1580 insn_len = vmcs_read(EXI_INST_LEN); 1581 1582 switch (reason) { 1583 case VMX_VMCALL: 1584 switch(vmx_get_test_stage()) { 1585 case 0: 1586 if (!invvpid_test(INVVPID_ADDR, 1)) 1587 vmx_inc_test_stage(); 1588 break; 1589 case 2: 1590 if (!invvpid_test(INVVPID_CONTEXT_GLOBAL, 1)) 1591 vmx_inc_test_stage(); 1592 break; 1593 case 4: 1594 if (!invvpid_test(INVVPID_ALL, 1)) 1595 vmx_inc_test_stage(); 1596 break; 1597 default: 1598 report("ERROR: unexpected stage, %d", false, 1599 vmx_get_test_stage()); 1600 print_vmexit_info(); 1601 return VMX_TEST_VMEXIT; 1602 } 1603 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1604 return VMX_TEST_RESUME; 1605 default: 1606 report("Unknown exit reason, %ld", false, reason); 1607 print_vmexit_info(); 1608 } 1609 return VMX_TEST_VMEXIT; 1610 } 1611 1612 #define TIMER_VECTOR 222 1613 1614 static volatile bool timer_fired; 1615 1616 static void timer_isr(isr_regs_t *regs) 1617 { 1618 timer_fired = true; 1619 apic_write(APIC_EOI, 0); 1620 } 1621 1622 static int interrupt_init(struct vmcs *vmcs) 1623 { 1624 msr_bmp_init(); 1625 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1626 handle_irq(TIMER_VECTOR, timer_isr); 1627 return VMX_TEST_START; 1628 } 1629 1630 static void interrupt_main(void) 1631 { 1632 long long start, loops; 1633 1634 vmx_set_test_stage(0); 1635 1636 apic_write(APIC_LVTT, TIMER_VECTOR); 1637 irq_enable(); 1638 1639 apic_write(APIC_TMICT, 1); 1640 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1641 asm volatile ("nop"); 1642 report("direct interrupt while running guest", timer_fired); 1643 1644 apic_write(APIC_TMICT, 0); 1645 irq_disable(); 1646 vmcall(); 1647 timer_fired = false; 1648 apic_write(APIC_TMICT, 1); 1649 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1650 asm volatile ("nop"); 1651 report("intercepted interrupt while running guest", timer_fired); 1652 1653 irq_enable(); 1654 apic_write(APIC_TMICT, 0); 1655 irq_disable(); 1656 vmcall(); 1657 timer_fired = false; 1658 start = rdtsc(); 1659 apic_write(APIC_TMICT, 1000000); 1660 1661 asm volatile ("sti; hlt"); 1662 1663 report("direct interrupt + hlt", 1664 rdtsc() - start > 1000000 && timer_fired); 1665 1666 apic_write(APIC_TMICT, 0); 1667 irq_disable(); 1668 vmcall(); 1669 timer_fired = false; 1670 start = rdtsc(); 1671 apic_write(APIC_TMICT, 1000000); 1672 1673 asm volatile ("sti; hlt"); 1674 1675 report("intercepted interrupt + hlt", 1676 rdtsc() - start > 10000 && timer_fired); 1677 1678 apic_write(APIC_TMICT, 0); 1679 irq_disable(); 1680 vmcall(); 1681 timer_fired = false; 1682 start = rdtsc(); 1683 apic_write(APIC_TMICT, 1000000); 1684 1685 irq_enable(); 1686 asm volatile ("nop"); 1687 vmcall(); 1688 1689 report("direct interrupt + activity state hlt", 1690 rdtsc() - start > 10000 && timer_fired); 1691 1692 apic_write(APIC_TMICT, 0); 1693 irq_disable(); 1694 vmcall(); 1695 timer_fired = false; 1696 start = rdtsc(); 1697 apic_write(APIC_TMICT, 1000000); 1698 1699 irq_enable(); 1700 asm volatile ("nop"); 1701 vmcall(); 1702 1703 report("intercepted interrupt + activity state hlt", 1704 rdtsc() - start > 10000 && timer_fired); 1705 1706 apic_write(APIC_TMICT, 0); 1707 irq_disable(); 1708 vmx_set_test_stage(7); 1709 vmcall(); 1710 timer_fired = false; 1711 apic_write(APIC_TMICT, 1); 1712 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1713 asm volatile ("nop"); 1714 report("running a guest with interrupt acknowledgement set", timer_fired); 1715 1716 apic_write(APIC_TMICT, 0); 1717 irq_enable(); 1718 timer_fired = false; 1719 vmcall(); 1720 report("Inject an event to a halted guest", timer_fired); 1721 } 1722 1723 static int interrupt_exit_handler(void) 1724 { 1725 u64 guest_rip = vmcs_read(GUEST_RIP); 1726 ulong reason = vmcs_read(EXI_REASON) & 0xff; 1727 u32 insn_len = vmcs_read(EXI_INST_LEN); 1728 1729 switch (reason) { 1730 case VMX_VMCALL: 1731 switch (vmx_get_test_stage()) { 1732 case 0: 1733 case 2: 1734 case 5: 1735 vmcs_write(PIN_CONTROLS, 1736 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1737 break; 1738 case 7: 1739 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_INTA); 1740 vmcs_write(PIN_CONTROLS, 1741 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1742 break; 1743 case 1: 1744 case 3: 1745 vmcs_write(PIN_CONTROLS, 1746 vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1747 break; 1748 case 4: 1749 case 6: 1750 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1751 break; 1752 1753 case 8: 1754 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1755 vmcs_write(ENT_INTR_INFO, 1756 TIMER_VECTOR | 1757 (VMX_INTR_TYPE_EXT_INTR << INTR_INFO_INTR_TYPE_SHIFT) | 1758 INTR_INFO_VALID_MASK); 1759 break; 1760 } 1761 vmx_inc_test_stage(); 1762 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1763 return VMX_TEST_RESUME; 1764 case VMX_EXTINT: 1765 if (vmcs_read(EXI_CONTROLS) & EXI_INTA) { 1766 int vector = vmcs_read(EXI_INTR_INFO) & 0xff; 1767 handle_external_interrupt(vector); 1768 } else { 1769 irq_enable(); 1770 asm volatile ("nop"); 1771 irq_disable(); 1772 } 1773 if (vmx_get_test_stage() >= 2) 1774 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 1775 return VMX_TEST_RESUME; 1776 default: 1777 report("Unknown exit reason, %ld", false, reason); 1778 print_vmexit_info(); 1779 } 1780 1781 return VMX_TEST_VMEXIT; 1782 } 1783 1784 static int dbgctls_init(struct vmcs *vmcs) 1785 { 1786 u64 dr7 = 0x402; 1787 u64 zero = 0; 1788 1789 msr_bmp_init(); 1790 asm volatile( 1791 "mov %0,%%dr0\n\t" 1792 "mov %0,%%dr1\n\t" 1793 "mov %0,%%dr2\n\t" 1794 "mov %1,%%dr7\n\t" 1795 : : "r" (zero), "r" (dr7)); 1796 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1797 vmcs_write(GUEST_DR7, 0x404); 1798 vmcs_write(GUEST_DEBUGCTL, 0x2); 1799 1800 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 1801 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_SAVE_DBGCTLS); 1802 1803 return VMX_TEST_START; 1804 } 1805 1806 static void dbgctls_main(void) 1807 { 1808 u64 dr7, debugctl; 1809 1810 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1811 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1812 /* Commented out: KVM does not support DEBUGCTL so far */ 1813 (void)debugctl; 1814 report("Load debug controls", dr7 == 0x404 /* && debugctl == 0x2 */); 1815 1816 dr7 = 0x408; 1817 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1818 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1819 1820 vmx_set_test_stage(0); 1821 vmcall(); 1822 report("Save debug controls", vmx_get_test_stage() == 1); 1823 1824 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS || 1825 ctrl_exit_rev.set & EXI_SAVE_DBGCTLS) { 1826 printf("\tDebug controls are always loaded/saved\n"); 1827 return; 1828 } 1829 vmx_set_test_stage(2); 1830 vmcall(); 1831 1832 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1833 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1834 /* Commented out: KVM does not support DEBUGCTL so far */ 1835 (void)debugctl; 1836 report("Guest=host debug controls", dr7 == 0x402 /* && debugctl == 0x1 */); 1837 1838 dr7 = 0x408; 1839 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1840 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1841 1842 vmx_set_test_stage(3); 1843 vmcall(); 1844 report("Don't save debug controls", vmx_get_test_stage() == 4); 1845 } 1846 1847 static int dbgctls_exit_handler(void) 1848 { 1849 unsigned int reason = vmcs_read(EXI_REASON) & 0xff; 1850 u32 insn_len = vmcs_read(EXI_INST_LEN); 1851 u64 guest_rip = vmcs_read(GUEST_RIP); 1852 u64 dr7, debugctl; 1853 1854 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1855 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1856 1857 switch (reason) { 1858 case VMX_VMCALL: 1859 switch (vmx_get_test_stage()) { 1860 case 0: 1861 if (dr7 == 0x400 && debugctl == 0 && 1862 vmcs_read(GUEST_DR7) == 0x408 /* && 1863 Commented out: KVM does not support DEBUGCTL so far 1864 vmcs_read(GUEST_DEBUGCTL) == 0x3 */) 1865 vmx_inc_test_stage(); 1866 break; 1867 case 2: 1868 dr7 = 0x402; 1869 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1870 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1871 vmcs_write(GUEST_DR7, 0x404); 1872 vmcs_write(GUEST_DEBUGCTL, 0x2); 1873 1874 vmcs_write(ENT_CONTROLS, 1875 vmcs_read(ENT_CONTROLS) & ~ENT_LOAD_DBGCTLS); 1876 vmcs_write(EXI_CONTROLS, 1877 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_DBGCTLS); 1878 break; 1879 case 3: 1880 if (dr7 == 0x400 && debugctl == 0 && 1881 vmcs_read(GUEST_DR7) == 0x404 /* && 1882 Commented out: KVM does not support DEBUGCTL so far 1883 vmcs_read(GUEST_DEBUGCTL) == 0x2 */) 1884 vmx_inc_test_stage(); 1885 break; 1886 } 1887 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1888 return VMX_TEST_RESUME; 1889 default: 1890 report("Unknown exit reason, %d", false, reason); 1891 print_vmexit_info(); 1892 } 1893 return VMX_TEST_VMEXIT; 1894 } 1895 1896 struct vmx_msr_entry { 1897 u32 index; 1898 u32 reserved; 1899 u64 value; 1900 } __attribute__((packed)); 1901 1902 #define MSR_MAGIC 0x31415926 1903 struct vmx_msr_entry *exit_msr_store, *entry_msr_load, *exit_msr_load; 1904 1905 static int msr_switch_init(struct vmcs *vmcs) 1906 { 1907 msr_bmp_init(); 1908 exit_msr_store = alloc_page(); 1909 exit_msr_load = alloc_page(); 1910 entry_msr_load = alloc_page(); 1911 memset(exit_msr_store, 0, PAGE_SIZE); 1912 memset(exit_msr_load, 0, PAGE_SIZE); 1913 memset(entry_msr_load, 0, PAGE_SIZE); 1914 entry_msr_load[0].index = MSR_KERNEL_GS_BASE; 1915 entry_msr_load[0].value = MSR_MAGIC; 1916 1917 vmx_set_test_stage(1); 1918 vmcs_write(ENT_MSR_LD_CNT, 1); 1919 vmcs_write(ENTER_MSR_LD_ADDR, (u64)entry_msr_load); 1920 vmcs_write(EXI_MSR_ST_CNT, 1); 1921 vmcs_write(EXIT_MSR_ST_ADDR, (u64)exit_msr_store); 1922 vmcs_write(EXI_MSR_LD_CNT, 1); 1923 vmcs_write(EXIT_MSR_LD_ADDR, (u64)exit_msr_load); 1924 return VMX_TEST_START; 1925 } 1926 1927 static void msr_switch_main(void) 1928 { 1929 if (vmx_get_test_stage() == 1) { 1930 report("VM entry MSR load", 1931 rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC); 1932 vmx_set_test_stage(2); 1933 wrmsr(MSR_KERNEL_GS_BASE, MSR_MAGIC + 1); 1934 exit_msr_store[0].index = MSR_KERNEL_GS_BASE; 1935 exit_msr_load[0].index = MSR_KERNEL_GS_BASE; 1936 exit_msr_load[0].value = MSR_MAGIC + 2; 1937 } 1938 vmcall(); 1939 } 1940 1941 static int msr_switch_exit_handler(void) 1942 { 1943 ulong reason; 1944 1945 reason = vmcs_read(EXI_REASON); 1946 if (reason == VMX_VMCALL && vmx_get_test_stage() == 2) { 1947 report("VM exit MSR store", 1948 exit_msr_store[0].value == MSR_MAGIC + 1); 1949 report("VM exit MSR load", 1950 rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC + 2); 1951 vmx_set_test_stage(3); 1952 entry_msr_load[0].index = MSR_FS_BASE; 1953 return VMX_TEST_RESUME; 1954 } 1955 printf("ERROR %s: unexpected stage=%u or reason=%lu\n", 1956 __func__, vmx_get_test_stage(), reason); 1957 return VMX_TEST_EXIT; 1958 } 1959 1960 static int msr_switch_entry_failure(struct vmentry_failure *failure) 1961 { 1962 ulong reason; 1963 1964 if (failure->early) { 1965 printf("ERROR %s: early exit\n", __func__); 1966 return VMX_TEST_EXIT; 1967 } 1968 1969 reason = vmcs_read(EXI_REASON); 1970 if (reason == (VMX_ENTRY_FAILURE | VMX_FAIL_MSR) && 1971 vmx_get_test_stage() == 3) { 1972 report("VM entry MSR load: try to load FS_BASE", 1973 vmcs_read(EXI_QUALIFICATION) == 1); 1974 return VMX_TEST_VMEXIT; 1975 } 1976 printf("ERROR %s: unexpected stage=%u or reason=%lu\n", 1977 __func__, vmx_get_test_stage(), reason); 1978 return VMX_TEST_EXIT; 1979 } 1980 1981 static int vmmcall_init(struct vmcs *vmcs) 1982 { 1983 vmcs_write(EXC_BITMAP, 1 << UD_VECTOR); 1984 return VMX_TEST_START; 1985 } 1986 1987 static void vmmcall_main(void) 1988 { 1989 asm volatile( 1990 "mov $0xABCD, %%rax\n\t" 1991 "vmmcall\n\t" 1992 ::: "rax"); 1993 1994 report("VMMCALL", 0); 1995 } 1996 1997 static int vmmcall_exit_handler(void) 1998 { 1999 ulong reason; 2000 2001 reason = vmcs_read(EXI_REASON); 2002 switch (reason) { 2003 case VMX_VMCALL: 2004 printf("here\n"); 2005 report("VMMCALL triggers #UD", 0); 2006 break; 2007 case VMX_EXC_NMI: 2008 report("VMMCALL triggers #UD", 2009 (vmcs_read(EXI_INTR_INFO) & 0xff) == UD_VECTOR); 2010 break; 2011 default: 2012 report("Unknown exit reason, %ld", false, reason); 2013 print_vmexit_info(); 2014 } 2015 2016 return VMX_TEST_VMEXIT; 2017 } 2018 2019 static int disable_rdtscp_init(struct vmcs *vmcs) 2020 { 2021 u32 ctrl_cpu1; 2022 2023 if (ctrl_cpu_rev[0].clr & CPU_SECONDARY) { 2024 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 2025 ctrl_cpu1 &= ~CPU_RDTSCP; 2026 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 2027 } 2028 2029 return VMX_TEST_START; 2030 } 2031 2032 static void disable_rdtscp_ud_handler(struct ex_regs *regs) 2033 { 2034 switch (vmx_get_test_stage()) { 2035 case 0: 2036 report("RDTSCP triggers #UD", true); 2037 vmx_inc_test_stage(); 2038 regs->rip += 3; 2039 break; 2040 case 2: 2041 report("RDPID triggers #UD", true); 2042 vmx_inc_test_stage(); 2043 regs->rip += 4; 2044 break; 2045 } 2046 return; 2047 2048 } 2049 2050 static void disable_rdtscp_main(void) 2051 { 2052 /* Test that #UD is properly injected in L2. */ 2053 handle_exception(UD_VECTOR, disable_rdtscp_ud_handler); 2054 2055 vmx_set_test_stage(0); 2056 asm volatile("rdtscp" : : : "eax", "ecx", "edx"); 2057 vmcall(); 2058 asm volatile(".byte 0xf3, 0x0f, 0xc7, 0xf8" : : : "eax"); 2059 2060 handle_exception(UD_VECTOR, 0); 2061 vmcall(); 2062 } 2063 2064 static int disable_rdtscp_exit_handler(void) 2065 { 2066 unsigned int reason = vmcs_read(EXI_REASON) & 0xff; 2067 2068 switch (reason) { 2069 case VMX_VMCALL: 2070 switch (vmx_get_test_stage()) { 2071 case 0: 2072 report("RDTSCP triggers #UD", false); 2073 vmx_inc_test_stage(); 2074 /* fallthrough */ 2075 case 1: 2076 vmx_inc_test_stage(); 2077 vmcs_write(GUEST_RIP, vmcs_read(GUEST_RIP) + 3); 2078 return VMX_TEST_RESUME; 2079 case 2: 2080 report("RDPID triggers #UD", false); 2081 break; 2082 } 2083 break; 2084 2085 default: 2086 report("Unknown exit reason, %d", false, reason); 2087 print_vmexit_info(); 2088 } 2089 return VMX_TEST_VMEXIT; 2090 } 2091 2092 static int int3_init(struct vmcs *vmcs) 2093 { 2094 vmcs_write(EXC_BITMAP, ~0u); 2095 return VMX_TEST_START; 2096 } 2097 2098 static void int3_guest_main(void) 2099 { 2100 asm volatile ("int3"); 2101 } 2102 2103 static int int3_exit_handler(void) 2104 { 2105 u32 reason = vmcs_read(EXI_REASON); 2106 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2107 2108 report("L1 intercepts #BP", reason == VMX_EXC_NMI && 2109 (intr_info & INTR_INFO_VALID_MASK) && 2110 (intr_info & INTR_INFO_VECTOR_MASK) == BP_VECTOR && 2111 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2112 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION); 2113 2114 return VMX_TEST_VMEXIT; 2115 } 2116 2117 static int into_init(struct vmcs *vmcs) 2118 { 2119 vmcs_write(EXC_BITMAP, ~0u); 2120 return VMX_TEST_START; 2121 } 2122 2123 static void into_guest_main(void) 2124 { 2125 struct far_pointer32 fp = { 2126 .offset = (uintptr_t)&&into, 2127 .selector = KERNEL_CS32, 2128 }; 2129 register uintptr_t rsp asm("rsp"); 2130 2131 if (fp.offset != (uintptr_t)&&into) { 2132 printf("Code address too high.\n"); 2133 return; 2134 } 2135 if ((u32)rsp != rsp) { 2136 printf("Stack address too high.\n"); 2137 return; 2138 } 2139 2140 asm goto ("lcall *%0" : : "m" (fp) : "rax" : into); 2141 return; 2142 into: 2143 asm volatile (".code32;" 2144 "movl $0x7fffffff, %eax;" 2145 "addl %eax, %eax;" 2146 "into;" 2147 "lret;" 2148 ".code64"); 2149 __builtin_unreachable(); 2150 } 2151 2152 static int into_exit_handler(void) 2153 { 2154 u32 reason = vmcs_read(EXI_REASON); 2155 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2156 2157 report("L1 intercepts #OF", reason == VMX_EXC_NMI && 2158 (intr_info & INTR_INFO_VALID_MASK) && 2159 (intr_info & INTR_INFO_VECTOR_MASK) == OF_VECTOR && 2160 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2161 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION); 2162 2163 return VMX_TEST_VMEXIT; 2164 } 2165 2166 static void exit_monitor_from_l2_main(void) 2167 { 2168 printf("Calling exit(0) from l2...\n"); 2169 exit(0); 2170 } 2171 2172 static int exit_monitor_from_l2_handler(void) 2173 { 2174 report("The guest should have killed the VMM", false); 2175 return VMX_TEST_EXIT; 2176 } 2177 2178 static void assert_exit_reason(u64 expected) 2179 { 2180 u64 actual = vmcs_read(EXI_REASON); 2181 2182 TEST_ASSERT_EQ_MSG(expected, actual, "Expected %s, got %s.", 2183 exit_reason_description(expected), 2184 exit_reason_description(actual)); 2185 } 2186 2187 static void skip_exit_insn(void) 2188 { 2189 u64 guest_rip = vmcs_read(GUEST_RIP); 2190 u32 insn_len = vmcs_read(EXI_INST_LEN); 2191 vmcs_write(GUEST_RIP, guest_rip + insn_len); 2192 } 2193 2194 static void skip_exit_vmcall(void) 2195 { 2196 assert_exit_reason(VMX_VMCALL); 2197 skip_exit_insn(); 2198 } 2199 2200 static void v2_null_test_guest(void) 2201 { 2202 } 2203 2204 static void v2_null_test(void) 2205 { 2206 test_set_guest(v2_null_test_guest); 2207 enter_guest(); 2208 report(__func__, 1); 2209 } 2210 2211 static void v2_multiple_entries_test_guest(void) 2212 { 2213 vmx_set_test_stage(1); 2214 vmcall(); 2215 vmx_set_test_stage(2); 2216 } 2217 2218 static void v2_multiple_entries_test(void) 2219 { 2220 test_set_guest(v2_multiple_entries_test_guest); 2221 enter_guest(); 2222 TEST_ASSERT_EQ(vmx_get_test_stage(), 1); 2223 skip_exit_vmcall(); 2224 enter_guest(); 2225 TEST_ASSERT_EQ(vmx_get_test_stage(), 2); 2226 report(__func__, 1); 2227 } 2228 2229 static int fixture_test_data = 1; 2230 2231 static void fixture_test_teardown(void *data) 2232 { 2233 *((int *) data) = 1; 2234 } 2235 2236 static void fixture_test_guest(void) 2237 { 2238 fixture_test_data++; 2239 } 2240 2241 2242 static void fixture_test_setup(void) 2243 { 2244 TEST_ASSERT_EQ_MSG(1, fixture_test_data, 2245 "fixture_test_teardown didn't run?!"); 2246 fixture_test_data = 2; 2247 test_add_teardown(fixture_test_teardown, &fixture_test_data); 2248 test_set_guest(fixture_test_guest); 2249 } 2250 2251 static void fixture_test_case1(void) 2252 { 2253 fixture_test_setup(); 2254 TEST_ASSERT_EQ(2, fixture_test_data); 2255 enter_guest(); 2256 TEST_ASSERT_EQ(3, fixture_test_data); 2257 report(__func__, 1); 2258 } 2259 2260 static void fixture_test_case2(void) 2261 { 2262 fixture_test_setup(); 2263 TEST_ASSERT_EQ(2, fixture_test_data); 2264 enter_guest(); 2265 TEST_ASSERT_EQ(3, fixture_test_data); 2266 report(__func__, 1); 2267 } 2268 2269 enum ept_access_op { 2270 OP_READ, 2271 OP_WRITE, 2272 OP_EXEC, 2273 OP_FLUSH_TLB, 2274 OP_EXIT, 2275 }; 2276 2277 static struct ept_access_test_data { 2278 unsigned long gpa; 2279 unsigned long *gva; 2280 unsigned long hpa; 2281 unsigned long *hva; 2282 enum ept_access_op op; 2283 } ept_access_test_data; 2284 2285 extern unsigned char ret42_start; 2286 extern unsigned char ret42_end; 2287 2288 /* Returns 42. */ 2289 asm( 2290 ".align 64\n" 2291 "ret42_start:\n" 2292 "mov $42, %eax\n" 2293 "ret\n" 2294 "ret42_end:\n" 2295 ); 2296 2297 static void 2298 diagnose_ept_violation_qual(u64 expected, u64 actual) 2299 { 2300 2301 #define DIAGNOSE(flag) \ 2302 do { \ 2303 if ((expected & flag) != (actual & flag)) \ 2304 printf(#flag " %sexpected\n", \ 2305 (expected & flag) ? "" : "un"); \ 2306 } while (0) 2307 2308 DIAGNOSE(EPT_VLT_RD); 2309 DIAGNOSE(EPT_VLT_WR); 2310 DIAGNOSE(EPT_VLT_FETCH); 2311 DIAGNOSE(EPT_VLT_PERM_RD); 2312 DIAGNOSE(EPT_VLT_PERM_WR); 2313 DIAGNOSE(EPT_VLT_PERM_EX); 2314 DIAGNOSE(EPT_VLT_LADDR_VLD); 2315 DIAGNOSE(EPT_VLT_PADDR); 2316 2317 #undef DIAGNOSE 2318 } 2319 2320 static void do_ept_access_op(enum ept_access_op op) 2321 { 2322 ept_access_test_data.op = op; 2323 enter_guest(); 2324 } 2325 2326 /* 2327 * Force the guest to flush its TLB (i.e., flush gva -> gpa mappings). Only 2328 * needed by tests that modify guest PTEs. 2329 */ 2330 static void ept_access_test_guest_flush_tlb(void) 2331 { 2332 do_ept_access_op(OP_FLUSH_TLB); 2333 skip_exit_vmcall(); 2334 } 2335 2336 /* 2337 * Modifies the EPT entry at @level in the mapping of @gpa. First clears the 2338 * bits in @clear then sets the bits in @set. @mkhuge transforms the entry into 2339 * a huge page. 2340 */ 2341 static unsigned long ept_twiddle(unsigned long gpa, bool mkhuge, int level, 2342 unsigned long clear, unsigned long set) 2343 { 2344 struct ept_access_test_data *data = &ept_access_test_data; 2345 unsigned long orig_pte; 2346 unsigned long pte; 2347 2348 /* Screw with the mapping at the requested level. */ 2349 TEST_ASSERT(get_ept_pte(pml4, gpa, level, &orig_pte)); 2350 pte = orig_pte; 2351 if (mkhuge) 2352 pte = (orig_pte & ~EPT_ADDR_MASK) | data->hpa | EPT_LARGE_PAGE; 2353 else 2354 pte = orig_pte; 2355 pte = (pte & ~clear) | set; 2356 set_ept_pte(pml4, gpa, level, pte); 2357 ept_sync(INVEPT_SINGLE, eptp); 2358 2359 return orig_pte; 2360 } 2361 2362 static void ept_untwiddle(unsigned long gpa, int level, unsigned long orig_pte) 2363 { 2364 set_ept_pte(pml4, gpa, level, orig_pte); 2365 } 2366 2367 static void do_ept_violation(bool leaf, enum ept_access_op op, 2368 u64 expected_qual, u64 expected_paddr) 2369 { 2370 u64 qual; 2371 2372 /* Try the access and observe the violation. */ 2373 do_ept_access_op(op); 2374 2375 assert_exit_reason(VMX_EPT_VIOLATION); 2376 2377 qual = vmcs_read(EXI_QUALIFICATION); 2378 2379 diagnose_ept_violation_qual(expected_qual, qual); 2380 TEST_EXPECT_EQ(expected_qual, qual); 2381 2382 #if 0 2383 /* Disable for now otherwise every test will fail */ 2384 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2385 (unsigned long) ( 2386 op == OP_EXEC ? data->gva + 1 : data->gva)); 2387 #endif 2388 /* 2389 * TODO: tests that probe expected_paddr in pages other than the one at 2390 * the beginning of the 1g region. 2391 */ 2392 TEST_EXPECT_EQ(vmcs_read(INFO_PHYS_ADDR), expected_paddr); 2393 } 2394 2395 static void 2396 ept_violation_at_level_mkhuge(bool mkhuge, int level, unsigned long clear, 2397 unsigned long set, enum ept_access_op op, 2398 u64 expected_qual) 2399 { 2400 struct ept_access_test_data *data = &ept_access_test_data; 2401 unsigned long orig_pte; 2402 2403 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2404 2405 do_ept_violation(level == 1 || mkhuge, op, expected_qual, 2406 op == OP_EXEC ? data->gpa + sizeof(unsigned long) : 2407 data->gpa); 2408 2409 /* Fix the violation and resume the op loop. */ 2410 ept_untwiddle(data->gpa, level, orig_pte); 2411 enter_guest(); 2412 skip_exit_vmcall(); 2413 } 2414 2415 static void 2416 ept_violation_at_level(int level, unsigned long clear, unsigned long set, 2417 enum ept_access_op op, u64 expected_qual) 2418 { 2419 ept_violation_at_level_mkhuge(false, level, clear, set, op, 2420 expected_qual); 2421 if (ept_huge_pages_supported(level)) 2422 ept_violation_at_level_mkhuge(true, level, clear, set, op, 2423 expected_qual); 2424 } 2425 2426 static void ept_violation(unsigned long clear, unsigned long set, 2427 enum ept_access_op op, u64 expected_qual) 2428 { 2429 ept_violation_at_level(1, clear, set, op, expected_qual); 2430 ept_violation_at_level(2, clear, set, op, expected_qual); 2431 ept_violation_at_level(3, clear, set, op, expected_qual); 2432 ept_violation_at_level(4, clear, set, op, expected_qual); 2433 } 2434 2435 static void ept_access_violation(unsigned long access, enum ept_access_op op, 2436 u64 expected_qual) 2437 { 2438 ept_violation(EPT_PRESENT, access, op, 2439 expected_qual | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2440 } 2441 2442 /* 2443 * For translations that don't involve a GVA, that is physical address (paddr) 2444 * accesses, EPT violations don't set the flag EPT_VLT_PADDR. For a typical 2445 * guest memory access, the hardware does GVA -> GPA -> HPA. However, certain 2446 * translations don't involve GVAs, such as when the hardware does the guest 2447 * page table walk. For example, in translating GVA_1 -> GPA_1, the guest MMU 2448 * might try to set an A bit on a guest PTE. If the GPA_2 that the PTE resides 2449 * on isn't present in the EPT, then the EPT violation will be for GPA_2 and 2450 * the EPT_VLT_PADDR bit will be clear in the exit qualification. 2451 * 2452 * Note that paddr violations can also be triggered by loading PAE page tables 2453 * with wonky addresses. We don't test that yet. 2454 * 2455 * This function modifies the EPT entry that maps the GPA that the guest page 2456 * table entry mapping ept_access_data.gva resides on. 2457 * 2458 * @ept_access EPT permissions to set. Other permissions are cleared. 2459 * 2460 * @pte_ad Set the A/D bits on the guest PTE accordingly. 2461 * 2462 * @op Guest operation to perform with ept_access_data.gva. 2463 * 2464 * @expect_violation 2465 * Is a violation expected during the paddr access? 2466 * 2467 * @expected_qual Expected qualification for the EPT violation. 2468 * EPT_VLT_PADDR should be clear. 2469 */ 2470 static void ept_access_paddr(unsigned long ept_access, unsigned long pte_ad, 2471 enum ept_access_op op, bool expect_violation, 2472 u64 expected_qual) 2473 { 2474 struct ept_access_test_data *data = &ept_access_test_data; 2475 unsigned long *ptep; 2476 unsigned long gpa; 2477 unsigned long orig_epte; 2478 2479 /* Modify the guest PTE mapping data->gva according to @pte_ad. */ 2480 ptep = get_pte_level(current_page_table(), data->gva, /*level=*/1); 2481 TEST_ASSERT(ptep); 2482 TEST_ASSERT_EQ(*ptep & PT_ADDR_MASK, data->gpa); 2483 *ptep = (*ptep & ~PT_AD_MASK) | pte_ad; 2484 ept_access_test_guest_flush_tlb(); 2485 2486 /* 2487 * Now modify the access bits on the EPT entry for the GPA that the 2488 * guest PTE resides on. Note that by modifying a single EPT entry, 2489 * we're potentially affecting 512 guest PTEs. However, we've carefully 2490 * constructed our test such that those other 511 PTEs aren't used by 2491 * the guest: data->gva is at the beginning of a 1G huge page, thus the 2492 * PTE we're modifying is at the beginning of a 4K page and the 2493 * following 511 entires are also under our control (and not touched by 2494 * the guest). 2495 */ 2496 gpa = virt_to_phys(ptep); 2497 TEST_ASSERT_EQ(gpa & ~PAGE_MASK, 0); 2498 /* 2499 * Make sure the guest page table page is mapped with a 4K EPT entry, 2500 * otherwise our level=1 twiddling below will fail. We use the 2501 * identity map (gpa = gpa) since page tables are shared with the host. 2502 */ 2503 install_ept(pml4, gpa, gpa, EPT_PRESENT); 2504 orig_epte = ept_twiddle(gpa, /*mkhuge=*/0, /*level=*/1, 2505 /*clear=*/EPT_PRESENT, /*set=*/ept_access); 2506 2507 if (expect_violation) { 2508 do_ept_violation(/*leaf=*/true, op, 2509 expected_qual | EPT_VLT_LADDR_VLD, gpa); 2510 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2511 do_ept_access_op(op); 2512 } else { 2513 do_ept_access_op(op); 2514 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2515 } 2516 2517 TEST_ASSERT(*ptep & PT_ACCESSED_MASK); 2518 if ((pte_ad & PT_DIRTY_MASK) || op == OP_WRITE) 2519 TEST_ASSERT(*ptep & PT_DIRTY_MASK); 2520 2521 skip_exit_vmcall(); 2522 } 2523 2524 static void ept_access_allowed_paddr(unsigned long ept_access, 2525 unsigned long pte_ad, 2526 enum ept_access_op op) 2527 { 2528 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/false, 2529 /*expected_qual=*/-1); 2530 } 2531 2532 static void ept_access_violation_paddr(unsigned long ept_access, 2533 unsigned long pte_ad, 2534 enum ept_access_op op, 2535 u64 expected_qual) 2536 { 2537 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/true, 2538 expected_qual); 2539 } 2540 2541 2542 static void ept_allowed_at_level_mkhuge(bool mkhuge, int level, 2543 unsigned long clear, 2544 unsigned long set, 2545 enum ept_access_op op) 2546 { 2547 struct ept_access_test_data *data = &ept_access_test_data; 2548 unsigned long orig_pte; 2549 2550 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2551 2552 /* No violation. Should proceed to vmcall. */ 2553 do_ept_access_op(op); 2554 skip_exit_vmcall(); 2555 2556 ept_untwiddle(data->gpa, level, orig_pte); 2557 } 2558 2559 static void ept_allowed_at_level(int level, unsigned long clear, 2560 unsigned long set, enum ept_access_op op) 2561 { 2562 ept_allowed_at_level_mkhuge(false, level, clear, set, op); 2563 if (ept_huge_pages_supported(level)) 2564 ept_allowed_at_level_mkhuge(true, level, clear, set, op); 2565 } 2566 2567 static void ept_allowed(unsigned long clear, unsigned long set, 2568 enum ept_access_op op) 2569 { 2570 ept_allowed_at_level(1, clear, set, op); 2571 ept_allowed_at_level(2, clear, set, op); 2572 ept_allowed_at_level(3, clear, set, op); 2573 ept_allowed_at_level(4, clear, set, op); 2574 } 2575 2576 static void ept_ignored_bit(int bit) 2577 { 2578 /* Set the bit. */ 2579 ept_allowed(0, 1ul << bit, OP_READ); 2580 ept_allowed(0, 1ul << bit, OP_WRITE); 2581 ept_allowed(0, 1ul << bit, OP_EXEC); 2582 2583 /* Clear the bit. */ 2584 ept_allowed(1ul << bit, 0, OP_READ); 2585 ept_allowed(1ul << bit, 0, OP_WRITE); 2586 ept_allowed(1ul << bit, 0, OP_EXEC); 2587 } 2588 2589 static void ept_access_allowed(unsigned long access, enum ept_access_op op) 2590 { 2591 ept_allowed(EPT_PRESENT, access, op); 2592 } 2593 2594 2595 static void ept_misconfig_at_level_mkhuge_op(bool mkhuge, int level, 2596 unsigned long clear, 2597 unsigned long set, 2598 enum ept_access_op op) 2599 { 2600 struct ept_access_test_data *data = &ept_access_test_data; 2601 unsigned long orig_pte; 2602 2603 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2604 2605 do_ept_access_op(op); 2606 assert_exit_reason(VMX_EPT_MISCONFIG); 2607 2608 /* Intel 27.2.1, "For all other VM exits, this field is cleared." */ 2609 #if 0 2610 /* broken: */ 2611 TEST_EXPECT_EQ_MSG(vmcs_read(EXI_QUALIFICATION), 0); 2612 #endif 2613 #if 0 2614 /* 2615 * broken: 2616 * According to description of exit qual for EPT violation, 2617 * EPT_VLT_LADDR_VLD indicates if GUEST_LINEAR_ADDRESS is valid. 2618 * However, I can't find anything that says GUEST_LINEAR_ADDRESS ought 2619 * to be set for msiconfig. 2620 */ 2621 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2622 (unsigned long) ( 2623 op == OP_EXEC ? data->gva + 1 : data->gva)); 2624 #endif 2625 2626 /* Fix the violation and resume the op loop. */ 2627 ept_untwiddle(data->gpa, level, orig_pte); 2628 enter_guest(); 2629 skip_exit_vmcall(); 2630 } 2631 2632 static void ept_misconfig_at_level_mkhuge(bool mkhuge, int level, 2633 unsigned long clear, 2634 unsigned long set) 2635 { 2636 /* The op shouldn't matter (read, write, exec), so try them all! */ 2637 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_READ); 2638 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_WRITE); 2639 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_EXEC); 2640 } 2641 2642 static void ept_misconfig_at_level(int level, unsigned long clear, 2643 unsigned long set) 2644 { 2645 ept_misconfig_at_level_mkhuge(false, level, clear, set); 2646 if (ept_huge_pages_supported(level)) 2647 ept_misconfig_at_level_mkhuge(true, level, clear, set); 2648 } 2649 2650 static void ept_misconfig(unsigned long clear, unsigned long set) 2651 { 2652 ept_misconfig_at_level(1, clear, set); 2653 ept_misconfig_at_level(2, clear, set); 2654 ept_misconfig_at_level(3, clear, set); 2655 ept_misconfig_at_level(4, clear, set); 2656 } 2657 2658 static void ept_access_misconfig(unsigned long access) 2659 { 2660 ept_misconfig(EPT_PRESENT, access); 2661 } 2662 2663 static void ept_reserved_bit_at_level_nohuge(int level, int bit) 2664 { 2665 /* Setting the bit causes a misconfig. */ 2666 ept_misconfig_at_level_mkhuge(false, level, 0, 1ul << bit); 2667 2668 /* Making the entry non-present turns reserved bits into ignored. */ 2669 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2670 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2671 } 2672 2673 static void ept_reserved_bit_at_level_huge(int level, int bit) 2674 { 2675 /* Setting the bit causes a misconfig. */ 2676 ept_misconfig_at_level_mkhuge(true, level, 0, 1ul << bit); 2677 2678 /* Making the entry non-present turns reserved bits into ignored. */ 2679 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2680 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2681 } 2682 2683 static void ept_reserved_bit_at_level(int level, int bit) 2684 { 2685 /* Setting the bit causes a misconfig. */ 2686 ept_misconfig_at_level(level, 0, 1ul << bit); 2687 2688 /* Making the entry non-present turns reserved bits into ignored. */ 2689 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2690 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2691 } 2692 2693 static void ept_reserved_bit(int bit) 2694 { 2695 ept_reserved_bit_at_level(1, bit); 2696 ept_reserved_bit_at_level(2, bit); 2697 ept_reserved_bit_at_level(3, bit); 2698 ept_reserved_bit_at_level(4, bit); 2699 } 2700 2701 #define PAGE_2M_ORDER 9 2702 #define PAGE_1G_ORDER 18 2703 2704 static void *get_1g_page(void) 2705 { 2706 static void *alloc; 2707 2708 if (!alloc) 2709 alloc = alloc_pages(PAGE_1G_ORDER); 2710 return alloc; 2711 } 2712 2713 static void ept_access_test_teardown(void *unused) 2714 { 2715 /* Exit the guest cleanly. */ 2716 do_ept_access_op(OP_EXIT); 2717 } 2718 2719 static void ept_access_test_guest(void) 2720 { 2721 struct ept_access_test_data *data = &ept_access_test_data; 2722 int (*code)(void) = (int (*)(void)) &data->gva[1]; 2723 2724 while (true) { 2725 switch (data->op) { 2726 case OP_READ: 2727 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_1); 2728 break; 2729 case OP_WRITE: 2730 *data->gva = MAGIC_VAL_2; 2731 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_2); 2732 *data->gva = MAGIC_VAL_1; 2733 break; 2734 case OP_EXEC: 2735 TEST_ASSERT_EQ(42, code()); 2736 break; 2737 case OP_FLUSH_TLB: 2738 write_cr3(read_cr3()); 2739 break; 2740 case OP_EXIT: 2741 return; 2742 default: 2743 TEST_ASSERT_MSG(false, "Unknown op %d", data->op); 2744 } 2745 vmcall(); 2746 } 2747 } 2748 2749 static void ept_access_test_setup(void) 2750 { 2751 struct ept_access_test_data *data = &ept_access_test_data; 2752 unsigned long npages = 1ul << PAGE_1G_ORDER; 2753 unsigned long size = npages * PAGE_SIZE; 2754 unsigned long *page_table = current_page_table(); 2755 unsigned long pte; 2756 2757 if (setup_ept(false)) 2758 test_skip("EPT not supported"); 2759 2760 /* We use data->gpa = 1 << 39 so that test data has a separate pml4 entry */ 2761 if (cpuid_maxphyaddr() < 40) 2762 test_skip("Test needs MAXPHYADDR >= 40"); 2763 2764 test_set_guest(ept_access_test_guest); 2765 test_add_teardown(ept_access_test_teardown, NULL); 2766 2767 data->hva = get_1g_page(); 2768 TEST_ASSERT(data->hva); 2769 data->hpa = virt_to_phys(data->hva); 2770 2771 data->gpa = 1ul << 39; 2772 data->gva = (void *) ALIGN((unsigned long) alloc_vpages(npages * 2), 2773 size); 2774 TEST_ASSERT(!any_present_pages(page_table, data->gva, size)); 2775 install_pages(page_table, data->gpa, size, data->gva); 2776 2777 /* 2778 * Make sure nothing's mapped here so the tests that screw with the 2779 * pml4 entry don't inadvertently break something. 2780 */ 2781 TEST_ASSERT(get_ept_pte(pml4, data->gpa, 4, &pte) && pte == 0); 2782 TEST_ASSERT(get_ept_pte(pml4, data->gpa + size - 1, 4, &pte) && pte == 0); 2783 install_ept(pml4, data->hpa, data->gpa, EPT_PRESENT); 2784 2785 data->hva[0] = MAGIC_VAL_1; 2786 memcpy(&data->hva[1], &ret42_start, &ret42_end - &ret42_start); 2787 } 2788 2789 static void ept_access_test_not_present(void) 2790 { 2791 ept_access_test_setup(); 2792 /* --- */ 2793 ept_access_violation(0, OP_READ, EPT_VLT_RD); 2794 ept_access_violation(0, OP_WRITE, EPT_VLT_WR); 2795 ept_access_violation(0, OP_EXEC, EPT_VLT_FETCH); 2796 } 2797 2798 static void ept_access_test_read_only(void) 2799 { 2800 ept_access_test_setup(); 2801 2802 /* r-- */ 2803 ept_access_allowed(EPT_RA, OP_READ); 2804 ept_access_violation(EPT_RA, OP_WRITE, EPT_VLT_WR | EPT_VLT_PERM_RD); 2805 ept_access_violation(EPT_RA, OP_EXEC, EPT_VLT_FETCH | EPT_VLT_PERM_RD); 2806 } 2807 2808 static void ept_access_test_write_only(void) 2809 { 2810 ept_access_test_setup(); 2811 /* -w- */ 2812 ept_access_misconfig(EPT_WA); 2813 } 2814 2815 static void ept_access_test_read_write(void) 2816 { 2817 ept_access_test_setup(); 2818 /* rw- */ 2819 ept_access_allowed(EPT_RA | EPT_WA, OP_READ); 2820 ept_access_allowed(EPT_RA | EPT_WA, OP_WRITE); 2821 ept_access_violation(EPT_RA | EPT_WA, OP_EXEC, 2822 EPT_VLT_FETCH | EPT_VLT_PERM_RD | EPT_VLT_PERM_WR); 2823 } 2824 2825 2826 static void ept_access_test_execute_only(void) 2827 { 2828 ept_access_test_setup(); 2829 /* --x */ 2830 if (ept_execute_only_supported()) { 2831 ept_access_violation(EPT_EA, OP_READ, 2832 EPT_VLT_RD | EPT_VLT_PERM_EX); 2833 ept_access_violation(EPT_EA, OP_WRITE, 2834 EPT_VLT_WR | EPT_VLT_PERM_EX); 2835 ept_access_allowed(EPT_EA, OP_EXEC); 2836 } else { 2837 ept_access_misconfig(EPT_EA); 2838 } 2839 } 2840 2841 static void ept_access_test_read_execute(void) 2842 { 2843 ept_access_test_setup(); 2844 /* r-x */ 2845 ept_access_allowed(EPT_RA | EPT_EA, OP_READ); 2846 ept_access_violation(EPT_RA | EPT_EA, OP_WRITE, 2847 EPT_VLT_WR | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX); 2848 ept_access_allowed(EPT_RA | EPT_EA, OP_EXEC); 2849 } 2850 2851 static void ept_access_test_write_execute(void) 2852 { 2853 ept_access_test_setup(); 2854 /* -wx */ 2855 ept_access_misconfig(EPT_WA | EPT_EA); 2856 } 2857 2858 static void ept_access_test_read_write_execute(void) 2859 { 2860 ept_access_test_setup(); 2861 /* rwx */ 2862 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_READ); 2863 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_WRITE); 2864 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_EXEC); 2865 } 2866 2867 static void ept_access_test_reserved_bits(void) 2868 { 2869 int i; 2870 int maxphyaddr; 2871 2872 ept_access_test_setup(); 2873 2874 /* Reserved bits above maxphyaddr. */ 2875 maxphyaddr = cpuid_maxphyaddr(); 2876 for (i = maxphyaddr; i <= 51; i++) { 2877 report_prefix_pushf("reserved_bit=%d", i); 2878 ept_reserved_bit(i); 2879 report_prefix_pop(); 2880 } 2881 2882 /* Level-specific reserved bits. */ 2883 ept_reserved_bit_at_level_nohuge(2, 3); 2884 ept_reserved_bit_at_level_nohuge(2, 4); 2885 ept_reserved_bit_at_level_nohuge(2, 5); 2886 ept_reserved_bit_at_level_nohuge(2, 6); 2887 /* 2M alignment. */ 2888 for (i = 12; i < 20; i++) { 2889 report_prefix_pushf("reserved_bit=%d", i); 2890 ept_reserved_bit_at_level_huge(2, i); 2891 report_prefix_pop(); 2892 } 2893 ept_reserved_bit_at_level_nohuge(3, 3); 2894 ept_reserved_bit_at_level_nohuge(3, 4); 2895 ept_reserved_bit_at_level_nohuge(3, 5); 2896 ept_reserved_bit_at_level_nohuge(3, 6); 2897 /* 1G alignment. */ 2898 for (i = 12; i < 29; i++) { 2899 report_prefix_pushf("reserved_bit=%d", i); 2900 ept_reserved_bit_at_level_huge(3, i); 2901 report_prefix_pop(); 2902 } 2903 ept_reserved_bit_at_level(4, 3); 2904 ept_reserved_bit_at_level(4, 4); 2905 ept_reserved_bit_at_level(4, 5); 2906 ept_reserved_bit_at_level(4, 6); 2907 ept_reserved_bit_at_level(4, 7); 2908 } 2909 2910 static void ept_access_test_ignored_bits(void) 2911 { 2912 ept_access_test_setup(); 2913 /* 2914 * Bits ignored at every level. Bits 8 and 9 (A and D) are ignored as 2915 * far as translation is concerned even if AD bits are enabled in the 2916 * EPTP. Bit 63 is ignored because "EPT-violation #VE" VM-execution 2917 * control is 0. 2918 */ 2919 ept_ignored_bit(8); 2920 ept_ignored_bit(9); 2921 ept_ignored_bit(10); 2922 ept_ignored_bit(11); 2923 ept_ignored_bit(52); 2924 ept_ignored_bit(53); 2925 ept_ignored_bit(54); 2926 ept_ignored_bit(55); 2927 ept_ignored_bit(56); 2928 ept_ignored_bit(57); 2929 ept_ignored_bit(58); 2930 ept_ignored_bit(59); 2931 ept_ignored_bit(60); 2932 ept_ignored_bit(61); 2933 ept_ignored_bit(62); 2934 ept_ignored_bit(63); 2935 } 2936 2937 static void ept_access_test_paddr_not_present_ad_disabled(void) 2938 { 2939 ept_access_test_setup(); 2940 ept_disable_ad_bits(); 2941 2942 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, EPT_VLT_RD); 2943 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, EPT_VLT_RD); 2944 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, EPT_VLT_RD); 2945 } 2946 2947 static void ept_access_test_paddr_not_present_ad_enabled(void) 2948 { 2949 u64 qual = EPT_VLT_RD | EPT_VLT_WR; 2950 2951 ept_access_test_setup(); 2952 ept_enable_ad_bits_or_skip_test(); 2953 2954 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, qual); 2955 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, qual); 2956 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, qual); 2957 } 2958 2959 static void ept_access_test_paddr_read_only_ad_disabled(void) 2960 { 2961 /* 2962 * When EPT AD bits are disabled, all accesses to guest paging 2963 * structures are reported separately as a read and (after 2964 * translation of the GPA to host physical address) a read+write 2965 * if the A/D bits have to be set. 2966 */ 2967 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 2968 2969 ept_access_test_setup(); 2970 ept_disable_ad_bits(); 2971 2972 /* Can't update A bit, so all accesses fail. */ 2973 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 2974 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 2975 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 2976 /* AD bits disabled, so only writes try to update the D bit. */ 2977 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ); 2978 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 2979 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC); 2980 /* Both A and D already set, so read-only is OK. */ 2981 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_READ); 2982 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_WRITE); 2983 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_EXEC); 2984 } 2985 2986 static void ept_access_test_paddr_read_only_ad_enabled(void) 2987 { 2988 /* 2989 * When EPT AD bits are enabled, all accesses to guest paging 2990 * structures are considered writes as far as EPT translation 2991 * is concerned. 2992 */ 2993 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 2994 2995 ept_access_test_setup(); 2996 ept_enable_ad_bits_or_skip_test(); 2997 2998 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 2999 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 3000 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 3001 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ, qual); 3002 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 3003 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC, qual); 3004 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_READ, qual); 3005 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_WRITE, qual); 3006 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_EXEC, qual); 3007 } 3008 3009 static void ept_access_test_paddr_read_write(void) 3010 { 3011 ept_access_test_setup(); 3012 /* Read-write access to paging structure. */ 3013 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_READ); 3014 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_WRITE); 3015 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_EXEC); 3016 } 3017 3018 static void ept_access_test_paddr_read_write_execute(void) 3019 { 3020 ept_access_test_setup(); 3021 /* RWX access to paging structure. */ 3022 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_READ); 3023 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_WRITE); 3024 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_EXEC); 3025 } 3026 3027 static void ept_access_test_paddr_read_execute_ad_disabled(void) 3028 { 3029 /* 3030 * When EPT AD bits are disabled, all accesses to guest paging 3031 * structures are reported separately as a read and (after 3032 * translation of the GPA to host physical address) a read+write 3033 * if the A/D bits have to be set. 3034 */ 3035 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3036 3037 ept_access_test_setup(); 3038 ept_disable_ad_bits(); 3039 3040 /* Can't update A bit, so all accesses fail. */ 3041 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3042 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3043 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3044 /* AD bits disabled, so only writes try to update the D bit. */ 3045 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ); 3046 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3047 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC); 3048 /* Both A and D already set, so read-only is OK. */ 3049 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ); 3050 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE); 3051 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC); 3052 } 3053 3054 static void ept_access_test_paddr_read_execute_ad_enabled(void) 3055 { 3056 /* 3057 * When EPT AD bits are enabled, all accesses to guest paging 3058 * structures are considered writes as far as EPT translation 3059 * is concerned. 3060 */ 3061 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3062 3063 ept_access_test_setup(); 3064 ept_enable_ad_bits_or_skip_test(); 3065 3066 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3067 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3068 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3069 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ, qual); 3070 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3071 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC, qual); 3072 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ, qual); 3073 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE, qual); 3074 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC, qual); 3075 } 3076 3077 static void ept_access_test_paddr_not_present_page_fault(void) 3078 { 3079 ept_access_test_setup(); 3080 /* 3081 * TODO: test no EPT violation as long as guest PF occurs. e.g., GPA is 3082 * page is read-only in EPT but GVA is also mapped read only in PT. 3083 * Thus guest page fault before host takes EPT violation for trying to 3084 * update A bit. 3085 */ 3086 } 3087 3088 static void ept_access_test_force_2m_page(void) 3089 { 3090 ept_access_test_setup(); 3091 3092 TEST_ASSERT_EQ(ept_2m_supported(), true); 3093 ept_allowed_at_level_mkhuge(true, 2, 0, 0, OP_READ); 3094 ept_violation_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_RA, OP_WRITE, 3095 EPT_VLT_WR | EPT_VLT_PERM_RD | 3096 EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 3097 ept_misconfig_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_WA); 3098 } 3099 3100 static bool invvpid_valid(u64 type, u64 vpid, u64 gla) 3101 { 3102 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3103 3104 TEST_ASSERT(msr & VPID_CAP_INVVPID); 3105 3106 if (type < INVVPID_ADDR || type > INVVPID_CONTEXT_LOCAL) 3107 return false; 3108 3109 if (!(msr & (1ull << (type + VPID_CAP_INVVPID_TYPES_SHIFT)))) 3110 return false; 3111 3112 if (vpid >> 16) 3113 return false; 3114 3115 if (type != INVVPID_ALL && !vpid) 3116 return false; 3117 3118 if (type == INVVPID_ADDR && !is_canonical(gla)) 3119 return false; 3120 3121 return true; 3122 } 3123 3124 static void try_invvpid(u64 type, u64 vpid, u64 gla) 3125 { 3126 int rc; 3127 bool valid = invvpid_valid(type, vpid, gla); 3128 u64 expected = valid ? VMXERR_UNSUPPORTED_VMCS_COMPONENT 3129 : VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID; 3130 /* 3131 * Set VMX_INST_ERROR to VMXERR_UNVALID_VMCS_COMPONENT, so 3132 * that we can tell if it is updated by INVVPID. 3133 */ 3134 vmcs_read(~0); 3135 rc = invvpid(type, vpid, gla); 3136 report("INVVPID type %ld VPID %lx GLA %lx %s", 3137 !rc == valid, type, vpid, gla, 3138 valid ? "passes" : "fails"); 3139 report("After %s INVVPID, VMX_INST_ERR is %ld (actual %ld)", 3140 vmcs_read(VMX_INST_ERROR) == expected, 3141 rc ? "failed" : "successful", 3142 expected, vmcs_read(VMX_INST_ERROR)); 3143 } 3144 3145 static void ds_invvpid(void *data) 3146 { 3147 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3148 u64 type = ffs(msr >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 3149 3150 TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 3151 asm volatile("invvpid %0, %1" 3152 : 3153 : "m"(*(struct invvpid_operand *)data), 3154 "r"(type)); 3155 } 3156 3157 /* 3158 * The SS override is ignored in 64-bit mode, so we use an addressing 3159 * mode with %rsp as the base register to generate an implicit SS 3160 * reference. 3161 */ 3162 static void ss_invvpid(void *data) 3163 { 3164 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3165 u64 type = ffs(msr >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 3166 3167 TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 3168 asm volatile("sub %%rsp,%0; invvpid (%%rsp,%0,1), %1" 3169 : "+r"(data) 3170 : "r"(type)); 3171 } 3172 3173 static void invvpid_test_gp(void) 3174 { 3175 bool fault; 3176 3177 fault = test_for_exception(GP_VECTOR, &ds_invvpid, 3178 (void *)NONCANONICAL); 3179 report("INVVPID with non-canonical DS operand raises #GP", fault); 3180 } 3181 3182 static void invvpid_test_ss(void) 3183 { 3184 bool fault; 3185 3186 fault = test_for_exception(SS_VECTOR, &ss_invvpid, 3187 (void *)NONCANONICAL); 3188 report("INVVPID with non-canonical SS operand raises #SS", fault); 3189 } 3190 3191 static void invvpid_test_pf(void) 3192 { 3193 void *vpage = alloc_vpage(); 3194 bool fault; 3195 3196 fault = test_for_exception(PF_VECTOR, &ds_invvpid, vpage); 3197 report("INVVPID with unmapped operand raises #PF", fault); 3198 } 3199 3200 static void try_compat_invvpid(void *unused) 3201 { 3202 struct far_pointer32 fp = { 3203 .offset = (uintptr_t)&&invvpid, 3204 .selector = KERNEL_CS32, 3205 }; 3206 register uintptr_t rsp asm("rsp"); 3207 3208 TEST_ASSERT_MSG(fp.offset == (uintptr_t)&&invvpid, 3209 "Code address too high."); 3210 TEST_ASSERT_MSG(rsp == (u32)rsp, "Stack address too high."); 3211 3212 asm goto ("lcall *%0" : : "m" (fp) : "rax" : invvpid); 3213 return; 3214 invvpid: 3215 asm volatile (".code32;" 3216 "invvpid (%eax), %eax;" 3217 "lret;" 3218 ".code64"); 3219 __builtin_unreachable(); 3220 } 3221 3222 static void invvpid_test_compatibility_mode(void) 3223 { 3224 bool fault; 3225 3226 fault = test_for_exception(UD_VECTOR, &try_compat_invvpid, NULL); 3227 report("Compatibility mode INVVPID raises #UD", fault); 3228 } 3229 3230 static void invvpid_test_not_in_vmx_operation(void) 3231 { 3232 bool fault; 3233 3234 TEST_ASSERT(!vmx_off()); 3235 fault = test_for_exception(UD_VECTOR, &ds_invvpid, NULL); 3236 report("INVVPID outside of VMX operation raises #UD", fault); 3237 TEST_ASSERT(!vmx_on()); 3238 } 3239 3240 /* 3241 * This does not test real-address mode, virtual-8086 mode, protected mode, 3242 * or CPL > 0. 3243 */ 3244 static void invvpid_test_v2(void) 3245 { 3246 u64 msr; 3247 int i; 3248 unsigned types = 0; 3249 unsigned type; 3250 3251 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 3252 !(ctrl_cpu_rev[1].clr & CPU_VPID)) 3253 test_skip("VPID not supported"); 3254 3255 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3256 3257 if (!(msr & VPID_CAP_INVVPID)) 3258 test_skip("INVVPID not supported.\n"); 3259 3260 if (msr & VPID_CAP_INVVPID_ADDR) 3261 types |= 1u << INVVPID_ADDR; 3262 if (msr & VPID_CAP_INVVPID_CXTGLB) 3263 types |= 1u << INVVPID_CONTEXT_GLOBAL; 3264 if (msr & VPID_CAP_INVVPID_ALL) 3265 types |= 1u << INVVPID_ALL; 3266 if (msr & VPID_CAP_INVVPID_CXTLOC) 3267 types |= 1u << INVVPID_CONTEXT_LOCAL; 3268 3269 if (!types) 3270 test_skip("No INVVPID types supported.\n"); 3271 3272 for (i = -127; i < 128; i++) 3273 try_invvpid(i, 0xffff, 0); 3274 3275 /* 3276 * VPID must not be more than 16 bits. 3277 */ 3278 for (i = 0; i < 64; i++) 3279 for (type = 0; type < 4; type++) 3280 if (types & (1u << type)) 3281 try_invvpid(type, 1ul << i, 0); 3282 3283 /* 3284 * VPID must not be zero, except for "all contexts." 3285 */ 3286 for (type = 0; type < 4; type++) 3287 if (types & (1u << type)) 3288 try_invvpid(type, 0, 0); 3289 3290 /* 3291 * The gla operand is only validated for single-address INVVPID. 3292 */ 3293 if (types & (1u << INVVPID_ADDR)) 3294 try_invvpid(INVVPID_ADDR, 0xffff, NONCANONICAL); 3295 3296 invvpid_test_gp(); 3297 invvpid_test_ss(); 3298 invvpid_test_pf(); 3299 invvpid_test_compatibility_mode(); 3300 invvpid_test_not_in_vmx_operation(); 3301 } 3302 3303 /* 3304 * Test for early VMLAUNCH failure. Returns true if VMLAUNCH makes it 3305 * at least as far as the guest-state checks. Returns false if the 3306 * VMLAUNCH fails early and execution falls through to the next 3307 * instruction. 3308 */ 3309 static bool vmlaunch_succeeds(void) 3310 { 3311 u32 exit_reason; 3312 3313 /* 3314 * Indirectly set VMX_INST_ERR to 12 ("VMREAD/VMWRITE from/to 3315 * unsupported VMCS component"). The caller can then check 3316 * to see if a failed VM-entry sets VMX_INST_ERR as expected. 3317 */ 3318 vmcs_write(~0u, 0); 3319 3320 vmcs_write(HOST_RIP, (uintptr_t)&&success); 3321 __asm__ __volatile__ goto ("vmwrite %%rsp, %0; vmlaunch" 3322 : 3323 : "r" ((u64)HOST_RSP) 3324 : "cc", "memory" 3325 : success); 3326 return false; 3327 success: 3328 exit_reason = vmcs_read(EXI_REASON); 3329 TEST_ASSERT(exit_reason == (VMX_FAIL_STATE | VMX_ENTRY_FAILURE) || 3330 exit_reason == (VMX_FAIL_MSR | VMX_ENTRY_FAILURE)); 3331 return true; 3332 } 3333 3334 /* 3335 * Try to launch the current VMCS. 3336 */ 3337 static void test_vmx_vmlaunch(u32 xerror, bool xfail) 3338 { 3339 bool success = vmlaunch_succeeds(); 3340 u32 vmx_inst_err; 3341 3342 report_xfail("vmlaunch %s", xfail, success == !xerror, 3343 !xerror ? "succeeds" : "fails"); 3344 if (!success && xerror) { 3345 vmx_inst_err = vmcs_read(VMX_INST_ERROR); 3346 report("VMX inst error is %d (actual %d)", 3347 vmx_inst_err == xerror, xerror, vmx_inst_err); 3348 } 3349 } 3350 3351 static void test_vmx_invalid_controls(bool xfail) 3352 { 3353 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_CONTROL_FIELD, xfail); 3354 } 3355 3356 static void test_vmx_valid_controls(bool xfail) 3357 { 3358 test_vmx_vmlaunch(0, xfail); 3359 } 3360 3361 /* 3362 * Test a particular value of a VM-execution control bit, if the value 3363 * is required or if the value is zero. 3364 */ 3365 static void test_rsvd_ctl_bit_value(const char *name, union vmx_ctrl_msr msr, 3366 enum Encoding encoding, unsigned bit, 3367 unsigned val) 3368 { 3369 u32 mask = 1u << bit; 3370 bool expected; 3371 u32 controls; 3372 3373 if (msr.set & mask) 3374 TEST_ASSERT(msr.clr & mask); 3375 3376 /* 3377 * We can't arbitrarily turn on a control bit, because it may 3378 * introduce dependencies on other VMCS fields. So, we only 3379 * test turning on bits that have a required setting. 3380 */ 3381 if (val && (msr.clr & mask) && !(msr.set & mask)) 3382 return; 3383 3384 report_prefix_pushf("%s %s bit %d", 3385 val ? "Set" : "Clear", name, bit); 3386 3387 controls = vmcs_read(encoding); 3388 if (val) { 3389 vmcs_write(encoding, msr.set | mask); 3390 expected = (msr.clr & mask); 3391 } else { 3392 vmcs_write(encoding, msr.set & ~mask); 3393 expected = !(msr.set & mask); 3394 } 3395 if (expected) 3396 test_vmx_valid_controls(false); 3397 else 3398 test_vmx_invalid_controls(false); 3399 vmcs_write(encoding, controls); 3400 report_prefix_pop(); 3401 } 3402 3403 /* 3404 * Test reserved values of a VM-execution control bit, based on the 3405 * allowed bit settings from the corresponding VMX capability MSR. 3406 */ 3407 static void test_rsvd_ctl_bit(const char *name, union vmx_ctrl_msr msr, 3408 enum Encoding encoding, unsigned bit) 3409 { 3410 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 0); 3411 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 1); 3412 } 3413 3414 /* 3415 * Reserved bits in the pin-based VM-execution controls must be set 3416 * properly. Software may consult the VMX capability MSRs to determine 3417 * the proper settings. 3418 * [Intel SDM] 3419 */ 3420 static void test_pin_based_ctls(void) 3421 { 3422 unsigned bit; 3423 3424 printf("%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PIN" : 3425 "MSR_IA32_VMX_PINBASED_CTLS", ctrl_pin_rev.val); 3426 for (bit = 0; bit < 32; bit++) 3427 test_rsvd_ctl_bit("pin-based controls", 3428 ctrl_pin_rev, PIN_CONTROLS, bit); 3429 } 3430 3431 /* 3432 * Reserved bits in the primary processor-based VM-execution controls 3433 * must be set properly. Software may consult the VMX capability MSRs 3434 * to determine the proper settings. 3435 * [Intel SDM] 3436 */ 3437 static void test_primary_processor_based_ctls(void) 3438 { 3439 unsigned bit; 3440 3441 printf("\n%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PROC" : 3442 "MSR_IA32_VMX_PROCBASED_CTLS", ctrl_cpu_rev[0].val); 3443 for (bit = 0; bit < 32; bit++) 3444 test_rsvd_ctl_bit("primary processor-based controls", 3445 ctrl_cpu_rev[0], CPU_EXEC_CTRL0, bit); 3446 } 3447 3448 /* 3449 * If the "activate secondary controls" primary processor-based 3450 * VM-execution control is 1, reserved bits in the secondary 3451 * processor-based VM-execution controls must be cleared. Software may 3452 * consult the VMX capability MSRs to determine which bits are 3453 * reserved. 3454 * If the "activate secondary controls" primary processor-based 3455 * VM-execution control is 0 (or if the processor does not support the 3456 * 1-setting of that control), no checks are performed on the 3457 * secondary processor-based VM-execution controls. 3458 * [Intel SDM] 3459 */ 3460 static void test_secondary_processor_based_ctls(void) 3461 { 3462 u32 primary; 3463 u32 secondary; 3464 unsigned bit; 3465 3466 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) 3467 return; 3468 3469 primary = vmcs_read(CPU_EXEC_CTRL0); 3470 secondary = vmcs_read(CPU_EXEC_CTRL1); 3471 3472 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3473 printf("\nMSR_IA32_VMX_PROCBASED_CTLS2: %lx\n", ctrl_cpu_rev[1].val); 3474 for (bit = 0; bit < 32; bit++) 3475 test_rsvd_ctl_bit("secondary processor-based controls", 3476 ctrl_cpu_rev[1], CPU_EXEC_CTRL1, bit); 3477 3478 /* 3479 * When the "activate secondary controls" VM-execution control 3480 * is clear, there are no checks on the secondary controls. 3481 */ 3482 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3483 vmcs_write(CPU_EXEC_CTRL1, ~0); 3484 report("Secondary processor-based controls ignored", 3485 vmlaunch_succeeds()); 3486 vmcs_write(CPU_EXEC_CTRL1, secondary); 3487 vmcs_write(CPU_EXEC_CTRL0, primary); 3488 } 3489 3490 static void try_cr3_target_count(unsigned i, unsigned max) 3491 { 3492 report_prefix_pushf("CR3 target count 0x%x", i); 3493 vmcs_write(CR3_TARGET_COUNT, i); 3494 if (i <= max) 3495 test_vmx_valid_controls(false); 3496 else 3497 test_vmx_invalid_controls(false); 3498 report_prefix_pop(); 3499 } 3500 3501 /* 3502 * The CR3-target count must not be greater than 4. Future processors 3503 * may support a different number of CR3-target values. Software 3504 * should read the VMX capability MSR IA32_VMX_MISC to determine the 3505 * number of values supported. 3506 * [Intel SDM] 3507 */ 3508 static void test_cr3_targets(void) 3509 { 3510 unsigned supported_targets = (rdmsr(MSR_IA32_VMX_MISC) >> 16) & 0x1ff; 3511 u32 cr3_targets = vmcs_read(CR3_TARGET_COUNT); 3512 unsigned i; 3513 3514 printf("\nSupported CR3 targets: %d\n", supported_targets); 3515 TEST_ASSERT(supported_targets <= 256); 3516 3517 try_cr3_target_count(-1u, supported_targets); 3518 try_cr3_target_count(0x80000000, supported_targets); 3519 try_cr3_target_count(0x7fffffff, supported_targets); 3520 for (i = 0; i <= supported_targets + 1; i++) 3521 try_cr3_target_count(i, supported_targets); 3522 vmcs_write(CR3_TARGET_COUNT, cr3_targets); 3523 } 3524 3525 /* 3526 * Test a particular address setting in the VMCS 3527 */ 3528 static void test_vmcs_addr(const char *name, 3529 enum Encoding encoding, 3530 u64 align, 3531 bool ignored, 3532 bool xfail_beyond_mapped_ram, 3533 u64 addr) 3534 { 3535 bool xfail = 3536 (xfail_beyond_mapped_ram && 3537 addr > fwcfg_get_u64(FW_CFG_RAM_SIZE) - align && 3538 addr < (1ul << cpuid_maxphyaddr())); 3539 3540 report_prefix_pushf("%s = %lx", name, addr); 3541 vmcs_write(encoding, addr); 3542 if (ignored || (IS_ALIGNED(addr, align) && 3543 addr < (1ul << cpuid_maxphyaddr()))) 3544 test_vmx_valid_controls(xfail); 3545 else 3546 test_vmx_invalid_controls(xfail); 3547 report_prefix_pop(); 3548 xfail = false; 3549 } 3550 3551 /* 3552 * Test interesting values for a VMCS address 3553 */ 3554 static void test_vmcs_addr_values(const char *name, 3555 enum Encoding encoding, 3556 u64 align, 3557 bool ignored, 3558 bool xfail_beyond_mapped_ram, 3559 u32 bit_start, u32 bit_end) 3560 { 3561 unsigned i; 3562 u64 orig_val = vmcs_read(encoding); 3563 3564 for (i = bit_start; i <= bit_end; i++) 3565 test_vmcs_addr(name, encoding, align, ignored, 3566 xfail_beyond_mapped_ram, 1ul << i); 3567 3568 test_vmcs_addr(name, encoding, align, ignored, 3569 xfail_beyond_mapped_ram, PAGE_SIZE - 1); 3570 test_vmcs_addr(name, encoding, align, ignored, 3571 xfail_beyond_mapped_ram, PAGE_SIZE); 3572 test_vmcs_addr(name, encoding, align, ignored, 3573 xfail_beyond_mapped_ram, 3574 (1ul << cpuid_maxphyaddr()) - PAGE_SIZE); 3575 test_vmcs_addr(name, encoding, align, ignored, 3576 xfail_beyond_mapped_ram, -1ul); 3577 3578 vmcs_write(encoding, orig_val); 3579 } 3580 3581 /* 3582 * Test a physical address reference in the VMCS, when the corresponding 3583 * feature is enabled and when the corresponding feature is disabled. 3584 */ 3585 static void test_vmcs_addr_reference(u32 control_bit, enum Encoding field, 3586 const char *field_name, 3587 const char *control_name, u64 align, 3588 bool xfail_beyond_mapped_ram, 3589 bool control_primary) 3590 { 3591 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 3592 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 3593 u64 page_addr; 3594 3595 if (control_primary) { 3596 if (!(ctrl_cpu_rev[0].clr & control_bit)) 3597 return; 3598 } else { 3599 if (!(ctrl_cpu_rev[1].clr & control_bit)) 3600 return; 3601 } 3602 3603 page_addr = vmcs_read(field); 3604 3605 report_prefix_pushf("%s enabled", control_name); 3606 if (control_primary) { 3607 vmcs_write(CPU_EXEC_CTRL0, primary | control_bit); 3608 } else { 3609 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3610 vmcs_write(CPU_EXEC_CTRL1, secondary | control_bit); 3611 } 3612 3613 test_vmcs_addr_values(field_name, field, align, false, 3614 xfail_beyond_mapped_ram, 0, 63); 3615 report_prefix_pop(); 3616 3617 report_prefix_pushf("%s disabled", control_name); 3618 if (control_primary) { 3619 vmcs_write(CPU_EXEC_CTRL0, primary & ~control_bit); 3620 } else { 3621 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3622 vmcs_write(CPU_EXEC_CTRL1, secondary & ~control_bit); 3623 } 3624 3625 test_vmcs_addr_values(field_name, field, align, true, false, 0, 63); 3626 report_prefix_pop(); 3627 3628 vmcs_write(field, page_addr); 3629 vmcs_write(CPU_EXEC_CTRL0, primary); 3630 vmcs_write(CPU_EXEC_CTRL1, secondary); 3631 } 3632 3633 /* 3634 * If the "use I/O bitmaps" VM-execution control is 1, bits 11:0 of 3635 * each I/O-bitmap address must be 0. Neither address should set any 3636 * bits beyond the processor's physical-address width. 3637 * [Intel SDM] 3638 */ 3639 static void test_io_bitmaps(void) 3640 { 3641 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_A, 3642 "I/O bitmap A", "Use I/O bitmaps", 3643 PAGE_SIZE, false, true); 3644 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_B, 3645 "I/O bitmap B", "Use I/O bitmaps", 3646 PAGE_SIZE, false, true); 3647 } 3648 3649 /* 3650 * If the "use MSR bitmaps" VM-execution control is 1, bits 11:0 of 3651 * the MSR-bitmap address must be 0. The address should not set any 3652 * bits beyond the processor's physical-address width. 3653 * [Intel SDM] 3654 */ 3655 static void test_msr_bitmap(void) 3656 { 3657 test_vmcs_addr_reference(CPU_MSR_BITMAP, MSR_BITMAP, 3658 "MSR bitmap", "Use MSR bitmaps", 3659 PAGE_SIZE, false, true); 3660 } 3661 3662 /* 3663 * If the "use TPR shadow" VM-execution control is 1, the virtual-APIC 3664 * address must satisfy the following checks: 3665 * - Bits 11:0 of the address must be 0. 3666 * - The address should not set any bits beyond the processor's 3667 * physical-address width. 3668 * [Intel SDM] 3669 */ 3670 static void test_apic_virt_addr(void) 3671 { 3672 test_vmcs_addr_reference(CPU_TPR_SHADOW, APIC_VIRT_ADDR, 3673 "virtual-APIC address", "Use TPR shadow", 3674 PAGE_SIZE, true, true); 3675 } 3676 3677 /* 3678 * If the "virtualize APIC-accesses" VM-execution control is 1, the 3679 * APIC-access address must satisfy the following checks: 3680 * - Bits 11:0 of the address must be 0. 3681 * - The address should not set any bits beyond the processor's 3682 * physical-address width. 3683 * [Intel SDM] 3684 */ 3685 static void test_apic_access_addr(void) 3686 { 3687 void *apic_access_page = alloc_page(); 3688 3689 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_page)); 3690 3691 test_vmcs_addr_reference(CPU_VIRT_APIC_ACCESSES, APIC_ACCS_ADDR, 3692 "APIC-access address", 3693 "virtualize APIC-accesses", PAGE_SIZE, 3694 false, false); 3695 } 3696 3697 static bool set_bit_pattern(u8 mask, u32 *secondary) 3698 { 3699 u8 i; 3700 bool flag = false; 3701 u32 test_bits[3] = { 3702 CPU_VIRT_X2APIC, 3703 CPU_APIC_REG_VIRT, 3704 CPU_VINTD 3705 }; 3706 3707 for (i = 0; i < ARRAY_SIZE(test_bits); i++) { 3708 if ((mask & (1u << i)) && 3709 (ctrl_cpu_rev[1].clr & test_bits[i])) { 3710 *secondary |= test_bits[i]; 3711 flag = true; 3712 } 3713 } 3714 3715 return (flag); 3716 } 3717 3718 /* 3719 * If the "use TPR shadow" VM-execution control is 0, the following 3720 * VM-execution controls must also be 0: 3721 * - virtualize x2APIC mode 3722 * - APIC-register virtualization 3723 * - virtual-interrupt delivery 3724 * [Intel SDM] 3725 * 3726 * 2. If the "virtualize x2APIC mode" VM-execution control is 1, the 3727 * "virtualize APIC accesses" VM-execution control must be 0. 3728 * [Intel SDM] 3729 */ 3730 static void test_apic_virtual_ctls(void) 3731 { 3732 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3733 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3734 u32 primary = saved_primary; 3735 u32 secondary = saved_secondary; 3736 bool ctrl = false; 3737 char str[10] = "disabled"; 3738 u8 i = 0, j; 3739 3740 /* 3741 * First test 3742 */ 3743 if (!((ctrl_cpu_rev[0].clr & (CPU_SECONDARY | CPU_TPR_SHADOW)) == 3744 (CPU_SECONDARY | CPU_TPR_SHADOW))) 3745 return; 3746 3747 primary |= CPU_SECONDARY; 3748 primary &= ~CPU_TPR_SHADOW; 3749 vmcs_write(CPU_EXEC_CTRL0, primary); 3750 3751 while (1) { 3752 for (j = 1; j < 8; j++) { 3753 secondary &= ~(CPU_VIRT_X2APIC | CPU_APIC_REG_VIRT | CPU_VINTD); 3754 if (primary & CPU_TPR_SHADOW) { 3755 ctrl = true; 3756 } else { 3757 if (! set_bit_pattern(j, &secondary)) 3758 ctrl = true; 3759 else 3760 ctrl = false; 3761 } 3762 3763 vmcs_write(CPU_EXEC_CTRL1, secondary); 3764 report_prefix_pushf("Use TPR shadow %s, virtualize x2APIC mode %s, APIC-register virtualization %s, virtual-interrupt delivery %s", 3765 str, (secondary & CPU_VIRT_X2APIC) ? "enabled" : "disabled", (secondary & CPU_APIC_REG_VIRT) ? "enabled" : "disabled", (secondary & CPU_VINTD) ? "enabled" : "disabled"); 3766 if (ctrl) 3767 test_vmx_valid_controls(false); 3768 else 3769 test_vmx_invalid_controls(false); 3770 report_prefix_pop(); 3771 } 3772 3773 if (i == 1) 3774 break; 3775 i++; 3776 3777 primary |= CPU_TPR_SHADOW; 3778 vmcs_write(CPU_EXEC_CTRL0, primary); 3779 strcpy(str, "enabled"); 3780 } 3781 3782 /* 3783 * Second test 3784 */ 3785 u32 apic_virt_ctls = (CPU_VIRT_X2APIC | CPU_VIRT_APIC_ACCESSES); 3786 3787 primary = saved_primary; 3788 secondary = saved_secondary; 3789 if (!((ctrl_cpu_rev[1].clr & apic_virt_ctls) == apic_virt_ctls)) 3790 return; 3791 3792 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3793 secondary &= ~CPU_VIRT_APIC_ACCESSES; 3794 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_X2APIC); 3795 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access disabled"); 3796 test_vmx_valid_controls(false); 3797 report_prefix_pop(); 3798 3799 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_APIC_ACCESSES); 3800 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access enabled"); 3801 test_vmx_valid_controls(false); 3802 report_prefix_pop(); 3803 3804 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_X2APIC); 3805 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access enabled"); 3806 test_vmx_invalid_controls(false); 3807 report_prefix_pop(); 3808 3809 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_APIC_ACCESSES); 3810 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access disabled"); 3811 test_vmx_valid_controls(false); 3812 report_prefix_pop(); 3813 3814 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3815 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3816 } 3817 3818 /* 3819 * If the "virtual-interrupt delivery" VM-execution control is 1, the 3820 * "external-interrupt exiting" VM-execution control must be 1. 3821 * [Intel SDM] 3822 */ 3823 static void test_virtual_intr_ctls(void) 3824 { 3825 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3826 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3827 u32 saved_pin = vmcs_read(PIN_CONTROLS); 3828 u32 primary = saved_primary; 3829 u32 secondary = saved_secondary; 3830 u32 pin = saved_pin; 3831 3832 if (!((ctrl_cpu_rev[1].clr & CPU_VINTD) && 3833 (ctrl_pin_rev.clr & PIN_EXTINT))) 3834 return; 3835 3836 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 3837 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VINTD); 3838 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 3839 report_prefix_pushf("Virtualize interrupt-delivery disabled; external-interrupt exiting disabled"); 3840 test_vmx_valid_controls(false); 3841 report_prefix_pop(); 3842 3843 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VINTD); 3844 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 3845 test_vmx_invalid_controls(false); 3846 report_prefix_pop(); 3847 3848 vmcs_write(PIN_CONTROLS, pin | PIN_EXTINT); 3849 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting enabled"); 3850 test_vmx_valid_controls(false); 3851 report_prefix_pop(); 3852 3853 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 3854 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 3855 test_vmx_invalid_controls(false); 3856 report_prefix_pop(); 3857 3858 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3859 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3860 vmcs_write(PIN_CONTROLS, saved_pin); 3861 } 3862 3863 static void test_pi_desc_addr(u64 addr, bool ctrl) 3864 { 3865 vmcs_write(POSTED_INTR_DESC_ADDR, addr); 3866 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-descriptor-address 0x%lx", addr); 3867 if (ctrl) 3868 test_vmx_valid_controls(false); 3869 else 3870 test_vmx_invalid_controls(false); 3871 report_prefix_pop(); 3872 } 3873 3874 /* 3875 * If the “process posted interrupts†VM-execution control is 1, the 3876 * following must be true: 3877 * 3878 * - The “virtual-interrupt delivery†VM-execution control is 1. 3879 * - The “acknowledge interrupt on exit†VM-exit control is 1. 3880 * - The posted-interrupt notification vector has a value in the 3881 * - range 0–255 (bits 15:8 are all 0). 3882 * - Bits 5:0 of the posted-interrupt descriptor address are all 0. 3883 * - The posted-interrupt descriptor address does not set any bits 3884 * beyond the processor's physical-address width. 3885 * [Intel SDM] 3886 */ 3887 static void test_posted_intr(void) 3888 { 3889 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3890 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3891 u32 saved_pin = vmcs_read(PIN_CONTROLS); 3892 u32 exit_ctl_saved = vmcs_read(EXI_CONTROLS); 3893 u32 primary = saved_primary; 3894 u32 secondary = saved_secondary; 3895 u32 pin = saved_pin; 3896 u32 exit_ctl = exit_ctl_saved; 3897 u16 vec; 3898 int i; 3899 3900 if (!((ctrl_pin_rev.clr & PIN_POST_INTR) && 3901 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 3902 (ctrl_exit_rev.clr & EXI_INTA))) 3903 return; 3904 3905 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 3906 3907 /* 3908 * Test virtual-interrupt-delivery and acknowledge-interrupt-on-exit 3909 */ 3910 pin |= PIN_POST_INTR; 3911 vmcs_write(PIN_CONTROLS, pin); 3912 secondary &= ~CPU_VINTD; 3913 vmcs_write(CPU_EXEC_CTRL1, secondary); 3914 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled"); 3915 test_vmx_invalid_controls(false); 3916 report_prefix_pop(); 3917 3918 secondary |= CPU_VINTD; 3919 vmcs_write(CPU_EXEC_CTRL1, secondary); 3920 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled"); 3921 test_vmx_invalid_controls(false); 3922 report_prefix_pop(); 3923 3924 exit_ctl &= ~EXI_INTA; 3925 vmcs_write(EXI_CONTROLS, exit_ctl); 3926 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit disabled"); 3927 test_vmx_invalid_controls(false); 3928 report_prefix_pop(); 3929 3930 exit_ctl |= EXI_INTA; 3931 vmcs_write(EXI_CONTROLS, exit_ctl); 3932 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 3933 test_vmx_valid_controls(false); 3934 report_prefix_pop(); 3935 3936 secondary &= ~CPU_VINTD; 3937 vmcs_write(CPU_EXEC_CTRL1, secondary); 3938 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled; acknowledge-interrupt-on-exit enabled"); 3939 test_vmx_invalid_controls(false); 3940 report_prefix_pop(); 3941 3942 secondary |= CPU_VINTD; 3943 vmcs_write(CPU_EXEC_CTRL1, secondary); 3944 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 3945 test_vmx_valid_controls(false); 3946 report_prefix_pop(); 3947 3948 /* 3949 * Test posted-interrupt notification vector 3950 */ 3951 for (i = 0; i < 8; i++) { 3952 vec = (1ul << i); 3953 vmcs_write(PINV, vec); 3954 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 3955 test_vmx_valid_controls(false); 3956 report_prefix_pop(); 3957 } 3958 for (i = 8; i < 16; i++) { 3959 vec = (1ul << i); 3960 vmcs_write(PINV, vec); 3961 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 3962 test_vmx_invalid_controls(false); 3963 report_prefix_pop(); 3964 } 3965 3966 vec &= ~(0xff << 8); 3967 vmcs_write(PINV, vec); 3968 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 3969 test_vmx_valid_controls(false); 3970 report_prefix_pop(); 3971 3972 /* 3973 * Test posted-interrupt descriptor addresss 3974 */ 3975 for (i = 0; i < 6; i++) { 3976 test_pi_desc_addr(1ul << i, false); 3977 } 3978 3979 test_pi_desc_addr(0xf0, false); 3980 test_pi_desc_addr(0xff, false); 3981 test_pi_desc_addr(0x0f, false); 3982 test_pi_desc_addr(0x8000, true); 3983 test_pi_desc_addr(0x00, true); 3984 test_pi_desc_addr(0xc000, true); 3985 3986 test_vmcs_addr_values("process-posted interrupts", 3987 POSTED_INTR_DESC_ADDR, 64, 3988 false, false, 0, 63); 3989 3990 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3991 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3992 vmcs_write(PIN_CONTROLS, saved_pin); 3993 } 3994 3995 static void test_apic_ctls(void) 3996 { 3997 test_apic_virt_addr(); 3998 test_apic_access_addr(); 3999 test_apic_virtual_ctls(); 4000 test_virtual_intr_ctls(); 4001 test_posted_intr(); 4002 } 4003 4004 /* 4005 * If the “enable VPID†VM-execution control is 1, the value of the 4006 * of the VPID VM-execution control field must not be 0000H. 4007 * [Intel SDM] 4008 */ 4009 static void test_vpid(void) 4010 { 4011 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 4012 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 4013 u16 vpid = 0x0000; 4014 int i; 4015 4016 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4017 (ctrl_cpu_rev[1].clr & CPU_VPID))) { 4018 test_skip("Secondary controls and/or VPID not supported"); 4019 return; 4020 } 4021 4022 vmcs_write(CPU_EXEC_CTRL0, saved_primary | CPU_SECONDARY); 4023 vmcs_write(CPU_EXEC_CTRL1, saved_secondary & ~CPU_VPID); 4024 vmcs_write(VPID, vpid); 4025 report_prefix_pushf("VPID disabled; VPID value %x", vpid); 4026 test_vmx_valid_controls(false); 4027 report_prefix_pop(); 4028 4029 vmcs_write(CPU_EXEC_CTRL1, saved_secondary | CPU_VPID); 4030 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 4031 test_vmx_invalid_controls(false); 4032 report_prefix_pop(); 4033 4034 for (i = 0; i < 16; i++) { 4035 vpid = (short)1 << i;; 4036 vmcs_write(VPID, vpid); 4037 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 4038 test_vmx_valid_controls(false); 4039 report_prefix_pop(); 4040 } 4041 4042 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 4043 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 4044 } 4045 4046 static void set_vtpr(unsigned vtpr) 4047 { 4048 *(u32 *)phys_to_virt(vmcs_read(APIC_VIRT_ADDR) + APIC_TASKPRI) = vtpr; 4049 } 4050 4051 static void try_tpr_threshold_and_vtpr(unsigned threshold, unsigned vtpr) 4052 { 4053 bool valid = true; 4054 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4055 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4056 4057 if ((primary & CPU_TPR_SHADOW) && 4058 (!(primary & CPU_SECONDARY) || 4059 !(secondary & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 4060 valid = (threshold & 0xf) <= ((vtpr >> 4) & 0xf); 4061 4062 set_vtpr(vtpr); 4063 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0x%x", 4064 threshold, (vtpr >> 4) & 0xf); 4065 if (valid) 4066 test_vmx_valid_controls(false); 4067 else 4068 test_vmx_invalid_controls(false); 4069 report_prefix_pop(); 4070 } 4071 4072 static void test_invalid_event_injection(void) 4073 { 4074 u32 ent_intr_info_save = vmcs_read(ENT_INTR_INFO); 4075 u32 ent_intr_error_save = vmcs_read(ENT_INTR_ERROR); 4076 u32 ent_inst_len_save = vmcs_read(ENT_INST_LEN); 4077 u32 primary_save = vmcs_read(CPU_EXEC_CTRL0); 4078 u32 secondary_save = vmcs_read(CPU_EXEC_CTRL1); 4079 u64 guest_cr0_save = vmcs_read(GUEST_CR0); 4080 u32 ent_intr_info_base = INTR_INFO_VALID_MASK; 4081 u32 ent_intr_info, ent_intr_err, ent_intr_len; 4082 u32 cnt; 4083 4084 /* Setup */ 4085 report_prefix_push("invalid event injection"); 4086 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4087 vmcs_write(ENT_INST_LEN, 0x00000001); 4088 4089 /* The field’s interruption type is not set to a reserved value. */ 4090 ent_intr_info = ent_intr_info_base | INTR_TYPE_RESERVED | DE_VECTOR; 4091 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4092 "RESERVED interruption type invalid [-]", 4093 ent_intr_info); 4094 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4095 test_vmx_invalid_controls(false); 4096 report_prefix_pop(); 4097 4098 ent_intr_info = ent_intr_info_base | INTR_TYPE_EXT_INTR | 4099 DE_VECTOR; 4100 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4101 "RESERVED interruption type invalid [+]", 4102 ent_intr_info); 4103 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4104 test_vmx_valid_controls(false); 4105 report_prefix_pop(); 4106 4107 /* If the interruption type is other event, the vector is 0. */ 4108 ent_intr_info = ent_intr_info_base | INTR_TYPE_OTHER_EVENT | DB_VECTOR; 4109 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4110 "(OTHER EVENT && vector != 0) invalid [-]", 4111 ent_intr_info); 4112 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4113 test_vmx_invalid_controls(false); 4114 report_prefix_pop(); 4115 4116 /* If the interruption type is NMI, the vector is 2 (negative case). */ 4117 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | DE_VECTOR; 4118 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4119 "(NMI && vector != 2) invalid [-]", ent_intr_info); 4120 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4121 test_vmx_invalid_controls(false); 4122 report_prefix_pop(); 4123 4124 /* If the interruption type is NMI, the vector is 2 (positive case). */ 4125 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | NMI_VECTOR; 4126 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4127 "(NMI && vector == 2) valid [+]", ent_intr_info); 4128 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4129 test_vmx_valid_controls(false); 4130 report_prefix_pop(); 4131 4132 /* 4133 * If the interruption type 4134 * is HW exception, the vector is at most 31. 4135 */ 4136 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 0x20; 4137 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4138 "(HW exception && vector > 31) invalid [-]", 4139 ent_intr_info); 4140 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4141 test_vmx_invalid_controls(false); 4142 report_prefix_pop(); 4143 4144 /* 4145 * deliver-error-code is 1 iff either 4146 * (a) the "unrestricted guest" VM-execution control is 0 4147 * (b) CR0.PE is set. 4148 */ 4149 4150 /* Assert that unrestricted guest is disabled or unsupported */ 4151 assert(!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 4152 !(secondary_save & CPU_URG)); 4153 4154 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4155 GP_VECTOR; 4156 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4157 "error code <-> (!URG || prot_mode) [-]", 4158 ent_intr_info); 4159 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4160 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4161 test_vmx_invalid_controls(false); 4162 report_prefix_pop(); 4163 4164 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4165 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4166 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4167 "error code <-> (!URG || prot_mode) [+]", 4168 ent_intr_info); 4169 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4170 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4171 test_vmx_valid_controls(false); 4172 report_prefix_pop(); 4173 4174 if (enable_unrestricted_guest()) 4175 goto skip_unrestricted_guest; 4176 4177 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4178 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4179 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4180 "error code <-> (!URG || prot_mode) [-]", 4181 ent_intr_info); 4182 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4183 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4184 test_vmx_invalid_controls(false); 4185 report_prefix_pop(); 4186 4187 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4188 GP_VECTOR; 4189 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4190 "error code <-> (!URG || prot_mode) [-]", 4191 ent_intr_info); 4192 vmcs_write(GUEST_CR0, guest_cr0_save | X86_CR0_PE); 4193 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4194 test_vmx_invalid_controls(false); 4195 report_prefix_pop(); 4196 4197 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4198 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4199 4200 skip_unrestricted_guest: 4201 vmcs_write(GUEST_CR0, guest_cr0_save); 4202 4203 /* deliver-error-code is 1 iff the interruption type is HW exception */ 4204 report_prefix_push("error code <-> HW exception"); 4205 for (cnt = 0; cnt < 8; cnt++) { 4206 u32 exception_type_mask = cnt << 8; 4207 u32 deliver_error_code_mask = 4208 exception_type_mask != INTR_TYPE_HARD_EXCEPTION ? 4209 INTR_INFO_DELIVER_CODE_MASK : 0; 4210 4211 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4212 exception_type_mask | GP_VECTOR; 4213 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4214 ent_intr_info); 4215 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4216 test_vmx_invalid_controls(false); 4217 report_prefix_pop(); 4218 } 4219 report_prefix_pop(); 4220 4221 /* 4222 * deliver-error-code is 1 iff the the vector 4223 * indicates an exception that would normally deliver an error code 4224 */ 4225 report_prefix_push("error code <-> vector delivers error code"); 4226 for (cnt = 0; cnt < 32; cnt++) { 4227 bool has_error_code = false; 4228 u32 deliver_error_code_mask; 4229 4230 switch (cnt) { 4231 case DF_VECTOR: 4232 case TS_VECTOR: 4233 case NP_VECTOR: 4234 case SS_VECTOR: 4235 case GP_VECTOR: 4236 case PF_VECTOR: 4237 case AC_VECTOR: 4238 has_error_code = true; 4239 } 4240 4241 /* Negative case */ 4242 deliver_error_code_mask = has_error_code ? 4243 0 : 4244 INTR_INFO_DELIVER_CODE_MASK; 4245 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4246 INTR_TYPE_HARD_EXCEPTION | cnt; 4247 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4248 ent_intr_info); 4249 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4250 test_vmx_invalid_controls(false); 4251 report_prefix_pop(); 4252 4253 /* Positive case */ 4254 deliver_error_code_mask = has_error_code ? 4255 INTR_INFO_DELIVER_CODE_MASK : 4256 0; 4257 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4258 INTR_TYPE_HARD_EXCEPTION | cnt; 4259 report_prefix_pushf("VM-entry intr info=0x%x [+]", 4260 ent_intr_info); 4261 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4262 test_vmx_valid_controls(false); 4263 report_prefix_pop(); 4264 } 4265 report_prefix_pop(); 4266 4267 /* Reserved bits in the field (30:12) are 0. */ 4268 report_prefix_push("reserved bits clear"); 4269 for (cnt = 12; cnt <= 30; cnt++) { 4270 ent_intr_info = ent_intr_info_base | 4271 INTR_INFO_DELIVER_CODE_MASK | 4272 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR | 4273 (1U << cnt); 4274 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4275 ent_intr_info); 4276 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4277 test_vmx_invalid_controls(false); 4278 report_prefix_pop(); 4279 } 4280 report_prefix_pop(); 4281 4282 /* 4283 * If deliver-error-code is 1 4284 * bits 31:15 of the VM-entry exception error-code field are 0. 4285 */ 4286 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4287 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4288 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4289 "VM-entry exception error code[31:15] clear", 4290 ent_intr_info); 4291 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4292 for (cnt = 15; cnt <= 31; cnt++) { 4293 ent_intr_err = 1U << cnt; 4294 report_prefix_pushf("VM-entry intr error=0x%x [-]", 4295 ent_intr_err); 4296 vmcs_write(ENT_INTR_ERROR, ent_intr_err); 4297 test_vmx_invalid_controls(false); 4298 report_prefix_pop(); 4299 } 4300 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4301 report_prefix_pop(); 4302 4303 /* 4304 * If the interruption type is software interrupt, software exception, 4305 * or privileged software exception, the VM-entry instruction-length 4306 * field is in the range 0–15. 4307 */ 4308 4309 for (cnt = 0; cnt < 3; cnt++) { 4310 switch (cnt) { 4311 case 0: 4312 ent_intr_info = ent_intr_info_base | 4313 INTR_TYPE_SOFT_INTR; 4314 break; 4315 case 1: 4316 ent_intr_info = ent_intr_info_base | 4317 INTR_TYPE_SOFT_EXCEPTION; 4318 break; 4319 case 2: 4320 ent_intr_info = ent_intr_info_base | 4321 INTR_TYPE_PRIV_SW_EXCEPTION; 4322 break; 4323 } 4324 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4325 "VM-entry instruction-length check", 4326 ent_intr_info); 4327 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4328 4329 /* Instruction length set to -1 (0xFFFFFFFF) should fail */ 4330 ent_intr_len = -1; 4331 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4332 ent_intr_len); 4333 vmcs_write(ENT_INST_LEN, ent_intr_len); 4334 test_vmx_invalid_controls(false); 4335 report_prefix_pop(); 4336 4337 /* Instruction length set to 16 should fail */ 4338 ent_intr_len = 0x00000010; 4339 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4340 ent_intr_len); 4341 vmcs_write(ENT_INST_LEN, 0x00000010); 4342 test_vmx_invalid_controls(false); 4343 report_prefix_pop(); 4344 4345 report_prefix_pop(); 4346 } 4347 4348 /* Cleanup */ 4349 vmcs_write(ENT_INTR_INFO, ent_intr_info_save); 4350 vmcs_write(ENT_INTR_ERROR, ent_intr_error_save); 4351 vmcs_write(ENT_INST_LEN, ent_inst_len_save); 4352 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4353 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4354 vmcs_write(GUEST_CR0, guest_cr0_save); 4355 report_prefix_pop(); 4356 } 4357 4358 /* 4359 * Test interesting vTPR values for a given TPR threshold. 4360 */ 4361 static void test_vtpr_values(unsigned threshold) 4362 { 4363 try_tpr_threshold_and_vtpr(threshold, (threshold - 1) << 4); 4364 try_tpr_threshold_and_vtpr(threshold, threshold << 4); 4365 try_tpr_threshold_and_vtpr(threshold, (threshold + 1) << 4); 4366 } 4367 4368 static void try_tpr_threshold(unsigned threshold) 4369 { 4370 bool valid = true; 4371 4372 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4373 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4374 4375 if ((primary & CPU_TPR_SHADOW) && !((primary & CPU_SECONDARY) && 4376 (secondary & CPU_VINTD))) 4377 valid = !(threshold >> 4); 4378 4379 set_vtpr(-1); 4380 vmcs_write(TPR_THRESHOLD, threshold); 4381 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0xf", threshold); 4382 if (valid) 4383 test_vmx_valid_controls(false); 4384 else 4385 test_vmx_invalid_controls(false); 4386 report_prefix_pop(); 4387 4388 if (valid) 4389 test_vtpr_values(threshold); 4390 } 4391 4392 /* 4393 * Test interesting TPR threshold values. 4394 */ 4395 static void test_tpr_threshold_values(void) 4396 { 4397 unsigned i; 4398 4399 for (i = 0; i < 0x10; i++) 4400 try_tpr_threshold(i); 4401 for (i = 4; i < 32; i++) 4402 try_tpr_threshold(1u << i); 4403 try_tpr_threshold(-1u); 4404 try_tpr_threshold(0x7fffffff); 4405 } 4406 4407 /* 4408 * This test covers the following two VM entry checks: 4409 * 4410 * i) If the "use TPR shadow" VM-execution control is 1 and the 4411 * "virtual-interrupt delivery" VM-execution control is 0, bits 4412 * 31:4 of the TPR threshold VM-execution control field must 4413 be 0. 4414 * [Intel SDM] 4415 * 4416 * ii) If the "use TPR shadow" VM-execution control is 1, the 4417 * "virtual-interrupt delivery" VM-execution control is 0 4418 * and the "virtualize APIC accesses" VM-execution control 4419 * is 0, the value of bits 3:0 of the TPR threshold VM-execution 4420 * control field must not be greater than the value of bits 4421 * 7:4 of VTPR. 4422 * [Intel SDM] 4423 */ 4424 static void test_tpr_threshold(void) 4425 { 4426 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4427 void *virtual_apic_page; 4428 4429 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) 4430 return; 4431 4432 virtual_apic_page = alloc_page(); 4433 memset(virtual_apic_page, 0xff, PAGE_SIZE); 4434 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 4435 4436 vmcs_write(CPU_EXEC_CTRL0, primary & ~(CPU_TPR_SHADOW | CPU_SECONDARY)); 4437 report_prefix_pushf("Use TPR shadow disabled, secondary controls disabled"); 4438 test_tpr_threshold_values(); 4439 report_prefix_pop(); 4440 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_TPR_SHADOW); 4441 report_prefix_pushf("Use TPR shadow enabled, secondary controls disabled"); 4442 test_tpr_threshold_values(); 4443 report_prefix_pop(); 4444 4445 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4446 (ctrl_cpu_rev[1].clr & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) { 4447 vmcs_write(CPU_EXEC_CTRL0, primary); 4448 return; 4449 } 4450 4451 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4452 4453 if (ctrl_cpu_rev[1].clr & CPU_VINTD) { 4454 vmcs_write(CPU_EXEC_CTRL1, CPU_VINTD); 4455 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4456 test_tpr_threshold_values(); 4457 report_prefix_pop(); 4458 4459 vmcs_write(CPU_EXEC_CTRL0, 4460 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4461 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4462 test_tpr_threshold_values(); 4463 report_prefix_pop(); 4464 } 4465 4466 if (ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES) { 4467 vmcs_write(CPU_EXEC_CTRL0, 4468 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4469 vmcs_write(CPU_EXEC_CTRL1, CPU_VIRT_APIC_ACCESSES); 4470 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4471 test_tpr_threshold_values(); 4472 report_prefix_pop(); 4473 4474 vmcs_write(CPU_EXEC_CTRL0, 4475 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4476 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4477 test_tpr_threshold_values(); 4478 report_prefix_pop(); 4479 } 4480 4481 if ((ctrl_cpu_rev[1].clr & 4482 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) == 4483 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) { 4484 vmcs_write(CPU_EXEC_CTRL0, 4485 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4486 vmcs_write(CPU_EXEC_CTRL1, 4487 CPU_VINTD | CPU_VIRT_APIC_ACCESSES); 4488 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4489 test_tpr_threshold_values(); 4490 report_prefix_pop(); 4491 4492 vmcs_write(CPU_EXEC_CTRL0, 4493 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4494 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4495 test_tpr_threshold_values(); 4496 report_prefix_pop(); 4497 } 4498 4499 vmcs_write(CPU_EXEC_CTRL1, secondary); 4500 vmcs_write(CPU_EXEC_CTRL0, primary); 4501 } 4502 4503 /* 4504 * This test verifies the following two vmentry checks: 4505 * 4506 * If the "NMI exiting" VM-execution control is 0, "Virtual NMIs" 4507 * VM-execution control must be 0. 4508 * [Intel SDM] 4509 * 4510 * If the “virtual NMIs” VM-execution control is 0, the “NMI-window 4511 * exiting” VM-execution control must be 0. 4512 * [Intel SDM] 4513 */ 4514 static void test_nmi_ctrls(void) 4515 { 4516 u32 pin_ctrls, cpu_ctrls0, test_pin_ctrls, test_cpu_ctrls0; 4517 4518 if ((ctrl_pin_rev.clr & (PIN_NMI | PIN_VIRT_NMI)) != 4519 (PIN_NMI | PIN_VIRT_NMI)) { 4520 test_skip("NMI exiting and Virtual NMIs are not supported !"); 4521 return; 4522 } 4523 4524 /* Save the controls so that we can restore them after our tests */ 4525 pin_ctrls = vmcs_read(PIN_CONTROLS); 4526 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 4527 4528 test_pin_ctrls = pin_ctrls & ~(PIN_NMI | PIN_VIRT_NMI); 4529 test_cpu_ctrls0 = cpu_ctrls0 & ~CPU_NMI_WINDOW; 4530 4531 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4532 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs disabled"); 4533 test_vmx_valid_controls(false); 4534 report_prefix_pop(); 4535 4536 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_VIRT_NMI); 4537 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs enabled"); 4538 test_vmx_invalid_controls(false); 4539 report_prefix_pop(); 4540 4541 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4542 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs enabled"); 4543 test_vmx_valid_controls(false); 4544 report_prefix_pop(); 4545 4546 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_NMI); 4547 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs disabled"); 4548 test_vmx_valid_controls(false); 4549 report_prefix_pop(); 4550 4551 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 4552 report_info("NMI-window exiting is not supported, skipping..."); 4553 goto done; 4554 } 4555 4556 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4557 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4558 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting enabled"); 4559 test_vmx_invalid_controls(false); 4560 report_prefix_pop(); 4561 4562 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4563 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4564 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting disabled"); 4565 test_vmx_valid_controls(false); 4566 report_prefix_pop(); 4567 4568 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4569 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4570 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting enabled"); 4571 test_vmx_valid_controls(false); 4572 report_prefix_pop(); 4573 4574 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4575 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4576 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting disabled"); 4577 test_vmx_valid_controls(false); 4578 report_prefix_pop(); 4579 4580 /* Restore the controls to their original values */ 4581 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 4582 done: 4583 vmcs_write(PIN_CONTROLS, pin_ctrls); 4584 } 4585 4586 static void test_eptp_ad_bit(u64 eptp, bool ctrl) 4587 { 4588 vmcs_write(EPTP, eptp); 4589 report_prefix_pushf("Enable-EPT enabled; EPT accessed and dirty flag %s", 4590 (eptp & EPTP_AD_FLAG) ? "1": "0"); 4591 if (ctrl) 4592 test_vmx_valid_controls(false); 4593 else 4594 test_vmx_invalid_controls(false); 4595 report_prefix_pop(); 4596 4597 } 4598 4599 /* 4600 * 1. If the "enable EPT" VM-execution control is 1, the "EPTP VM-execution" 4601 * control field must satisfy the following checks: 4602 * 4603 * - The EPT memory type (bits 2:0) must be a value supported by the 4604 * processor as indicated in the IA32_VMX_EPT_VPID_CAP MSR. 4605 * - Bits 5:3 (1 less than the EPT page-walk length) must be 3, 4606 * indicating an EPT page-walk length of 4. 4607 * - Bit 6 (enable bit for accessed and dirty flags for EPT) must be 4608 * 0 if bit 21 of the IA32_VMX_EPT_VPID_CAP MSR is read as 0, 4609 * indicating that the processor does not support accessed and dirty 4610 * dirty flags for EPT. 4611 * - Reserved bits 11:7 and 63:N (where N is the processor's 4612 * physical-address width) must all be 0. 4613 * 4614 * 2. If the "unrestricted guest" VM-execution control is 1, the 4615 * "enable EPT" VM-execution control must also be 1. 4616 */ 4617 static void test_ept_eptp(void) 4618 { 4619 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4620 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4621 u64 eptp_saved = vmcs_read(EPTP); 4622 u32 primary = primary_saved; 4623 u32 secondary = secondary_saved; 4624 u64 msr, eptp = eptp_saved; 4625 bool un_cache = false; 4626 bool wr_bk = false; 4627 bool ctrl; 4628 u32 i, maxphysaddr; 4629 u64 j, resv_bits_mask = 0; 4630 4631 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4632 (ctrl_cpu_rev[1].clr & CPU_EPT))) { 4633 test_skip("\"CPU secondary\" and/or \"enable EPT\" execution controls are not supported !"); 4634 return; 4635 } 4636 4637 /* 4638 * Memory type (bits 2:0) 4639 */ 4640 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 4641 if (msr & EPT_CAP_UC) 4642 un_cache = true; 4643 if (msr & EPT_CAP_WB) 4644 wr_bk = true; 4645 4646 primary |= CPU_SECONDARY; 4647 vmcs_write(CPU_EXEC_CTRL0, primary); 4648 secondary |= CPU_EPT; 4649 vmcs_write(CPU_EXEC_CTRL1, secondary); 4650 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4651 (3ul << EPTP_PG_WALK_LEN_SHIFT); 4652 vmcs_write(EPTP, eptp); 4653 4654 for (i = 0; i < 8; i++) { 4655 if (i == 0) { 4656 if (un_cache) { 4657 report_info("EPT paging structure memory-type is Un-cacheable\n"); 4658 ctrl = true; 4659 } else { 4660 ctrl = false; 4661 } 4662 } else if (i == 6) { 4663 if (wr_bk) { 4664 report_info("EPT paging structure memory-type is Write-back\n"); 4665 ctrl = true; 4666 } else { 4667 ctrl = false; 4668 } 4669 } else { 4670 ctrl = false; 4671 } 4672 4673 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | i; 4674 vmcs_write(EPTP, eptp); 4675 report_prefix_pushf("Enable-EPT enabled; EPT memory type %lu", 4676 eptp & EPT_MEM_TYPE_MASK); 4677 if (ctrl) 4678 test_vmx_valid_controls(false); 4679 else 4680 test_vmx_invalid_controls(false); 4681 report_prefix_pop(); 4682 } 4683 4684 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | 6ul; 4685 4686 /* 4687 * Page walk length (bits 5:3) 4688 */ 4689 for (i = 0; i < 8; i++) { 4690 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4691 (i << EPTP_PG_WALK_LEN_SHIFT); 4692 if (i == 3) 4693 ctrl = true; 4694 else 4695 ctrl = false; 4696 4697 vmcs_write(EPTP, eptp); 4698 report_prefix_pushf("Enable-EPT enabled; EPT page walk length %lu", 4699 eptp & EPTP_PG_WALK_LEN_MASK); 4700 if (ctrl) 4701 test_vmx_valid_controls(false); 4702 else 4703 test_vmx_invalid_controls(false); 4704 report_prefix_pop(); 4705 } 4706 4707 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4708 3ul << EPTP_PG_WALK_LEN_SHIFT; 4709 4710 /* 4711 * Accessed and dirty flag (bit 6) 4712 */ 4713 if (msr & EPT_CAP_AD_FLAG) { 4714 report_info("Processor supports accessed and dirty flag"); 4715 eptp &= ~EPTP_AD_FLAG; 4716 test_eptp_ad_bit(eptp, true); 4717 4718 eptp |= EPTP_AD_FLAG; 4719 test_eptp_ad_bit(eptp, true); 4720 } else { 4721 report_info("Processor does not supports accessed and dirty flag"); 4722 eptp &= ~EPTP_AD_FLAG; 4723 test_eptp_ad_bit(eptp, true); 4724 4725 eptp |= EPTP_AD_FLAG; 4726 test_eptp_ad_bit(eptp, false); 4727 } 4728 4729 /* 4730 * Reserved bits [11:7] and [63:N] 4731 */ 4732 for (i = 0; i < 32; i++) { 4733 eptp = (eptp & 4734 ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)) | 4735 (i << EPTP_RESERV_BITS_SHIFT); 4736 vmcs_write(EPTP, eptp); 4737 report_prefix_pushf("Enable-EPT enabled; reserved bits [11:7] %lu", 4738 (eptp >> EPTP_RESERV_BITS_SHIFT) & 4739 EPTP_RESERV_BITS_MASK); 4740 if (i == 0) 4741 test_vmx_valid_controls(false); 4742 else 4743 test_vmx_invalid_controls(false); 4744 report_prefix_pop(); 4745 } 4746 4747 eptp = (eptp & ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)); 4748 4749 maxphysaddr = cpuid_maxphyaddr(); 4750 for (i = 0; i < (63 - maxphysaddr + 1); i++) { 4751 resv_bits_mask |= 1ul << i; 4752 } 4753 4754 for (j = maxphysaddr - 1; j <= 63; j++) { 4755 eptp = (eptp & ~(resv_bits_mask << maxphysaddr)) | 4756 (j < maxphysaddr ? 0 : 1ul << j); 4757 vmcs_write(EPTP, eptp); 4758 report_prefix_pushf("Enable-EPT enabled; reserved bits [63:N] %lu", 4759 (eptp >> maxphysaddr) & resv_bits_mask); 4760 if (j < maxphysaddr) 4761 test_vmx_valid_controls(false); 4762 else 4763 test_vmx_invalid_controls(false); 4764 report_prefix_pop(); 4765 } 4766 4767 secondary &= ~(CPU_EPT | CPU_URG); 4768 vmcs_write(CPU_EXEC_CTRL1, secondary); 4769 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest disabled"); 4770 test_vmx_valid_controls(false); 4771 report_prefix_pop(); 4772 4773 secondary |= CPU_URG; 4774 vmcs_write(CPU_EXEC_CTRL1, secondary); 4775 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest enabled"); 4776 test_vmx_invalid_controls(false); 4777 report_prefix_pop(); 4778 4779 secondary |= CPU_EPT; 4780 setup_dummy_ept(); 4781 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest enabled"); 4782 test_vmx_valid_controls(false); 4783 report_prefix_pop(); 4784 4785 secondary &= ~CPU_URG; 4786 vmcs_write(CPU_EXEC_CTRL1, secondary); 4787 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest disabled"); 4788 test_vmx_valid_controls(false); 4789 report_prefix_pop(); 4790 4791 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4792 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4793 vmcs_write(EPTP, eptp_saved); 4794 } 4795 4796 /* 4797 * If the 'enable PML' VM-execution control is 1, the 'enable EPT' 4798 * VM-execution control must also be 1. In addition, the PML address 4799 * must satisfy the following checks: 4800 * 4801 * * Bits 11:0 of the address must be 0. 4802 * * The address should not set any bits beyond the processor's 4803 * physical-address width. 4804 * 4805 * [Intel SDM] 4806 */ 4807 static void test_pml(void) 4808 { 4809 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4810 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4811 u32 primary = primary_saved; 4812 u32 secondary = secondary_saved; 4813 4814 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4815 (ctrl_cpu_rev[1].clr & CPU_EPT) && (ctrl_cpu_rev[1].clr & CPU_PML))) { 4816 test_skip("\"Secondary execution\" control or \"enable EPT\" control or \"enable PML\" control is not supported !"); 4817 return; 4818 } 4819 4820 primary |= CPU_SECONDARY; 4821 vmcs_write(CPU_EXEC_CTRL0, primary); 4822 secondary &= ~(CPU_PML | CPU_EPT); 4823 vmcs_write(CPU_EXEC_CTRL1, secondary); 4824 report_prefix_pushf("enable-PML disabled, enable-EPT disabled"); 4825 test_vmx_valid_controls(false); 4826 report_prefix_pop(); 4827 4828 secondary |= CPU_PML; 4829 vmcs_write(CPU_EXEC_CTRL1, secondary); 4830 report_prefix_pushf("enable-PML enabled, enable-EPT disabled"); 4831 test_vmx_invalid_controls(false); 4832 report_prefix_pop(); 4833 4834 secondary |= CPU_EPT; 4835 setup_dummy_ept(); 4836 report_prefix_pushf("enable-PML enabled, enable-EPT enabled"); 4837 test_vmx_valid_controls(false); 4838 report_prefix_pop(); 4839 4840 secondary &= ~CPU_PML; 4841 vmcs_write(CPU_EXEC_CTRL1, secondary); 4842 report_prefix_pushf("enable-PML disabled, enable EPT enabled"); 4843 test_vmx_valid_controls(false); 4844 report_prefix_pop(); 4845 4846 test_vmcs_addr_reference(CPU_PML, PMLADDR, "PML address", "PML", 4847 PAGE_SIZE, false, false); 4848 4849 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4850 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4851 } 4852 4853 /* 4854 * If the "activate VMX-preemption timer" VM-execution control is 0, the 4855 * the "save VMX-preemption timer value" VM-exit control must also be 0. 4856 * 4857 * [Intel SDM] 4858 */ 4859 static void test_vmx_preemption_timer(void) 4860 { 4861 u32 saved_pin = vmcs_read(PIN_CONTROLS); 4862 u32 saved_exit = vmcs_read(EXI_CONTROLS); 4863 u32 pin = saved_pin; 4864 u32 exit = saved_exit; 4865 4866 if (!((ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) || 4867 (ctrl_pin_rev.clr & PIN_PREEMPT))) { 4868 printf("\"Save-VMX-preemption-timer\" control and/or \"Enable-VMX-preemption-timer\" control is not supported\n"); 4869 return; 4870 } 4871 4872 pin |= PIN_PREEMPT; 4873 vmcs_write(PIN_CONTROLS, pin); 4874 exit &= ~EXI_SAVE_PREEMPT; 4875 vmcs_write(EXI_CONTROLS, exit); 4876 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer disabled"); 4877 test_vmx_valid_controls(false); 4878 report_prefix_pop(); 4879 4880 exit |= EXI_SAVE_PREEMPT; 4881 vmcs_write(EXI_CONTROLS, exit); 4882 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer enabled"); 4883 test_vmx_valid_controls(false); 4884 report_prefix_pop(); 4885 4886 pin &= ~PIN_PREEMPT; 4887 vmcs_write(PIN_CONTROLS, pin); 4888 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer enabled"); 4889 test_vmx_invalid_controls(false); 4890 report_prefix_pop(); 4891 4892 exit &= ~EXI_SAVE_PREEMPT; 4893 vmcs_write(EXI_CONTROLS, exit); 4894 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer disabled"); 4895 test_vmx_valid_controls(false); 4896 report_prefix_pop(); 4897 4898 vmcs_write(PIN_CONTROLS, saved_pin); 4899 vmcs_write(EXI_CONTROLS, saved_exit); 4900 } 4901 4902 /* 4903 * Tests for VM-execution control fields 4904 */ 4905 static void test_vm_execution_ctls(void) 4906 { 4907 test_pin_based_ctls(); 4908 test_primary_processor_based_ctls(); 4909 test_secondary_processor_based_ctls(); 4910 test_cr3_targets(); 4911 test_io_bitmaps(); 4912 test_msr_bitmap(); 4913 test_apic_ctls(); 4914 test_tpr_threshold(); 4915 test_nmi_ctrls(); 4916 test_pml(); 4917 test_vpid(); 4918 test_ept_eptp(); 4919 test_vmx_preemption_timer(); 4920 } 4921 4922 /* 4923 * The following checks are performed for the VM-entry MSR-load address if 4924 * the VM-entry MSR-load count field is non-zero: 4925 * 4926 * - The lower 4 bits of the VM-entry MSR-load address must be 0. 4927 * The address should not set any bits beyond the processor’s 4928 * physical-address width. 4929 * 4930 * - The address of the last byte in the VM-entry MSR-load area 4931 * should not set any bits beyond the processor’s physical-address 4932 * width. The address of this last byte is VM-entry MSR-load address 4933 * + (MSR count * 16) - 1. (The arithmetic used for the computation 4934 * uses more bits than the processor’s physical-address width.) 4935 * 4936 * 4937 * [Intel SDM] 4938 */ 4939 static void test_entry_msr_load(void) 4940 { 4941 entry_msr_load = alloc_page(); 4942 u64 tmp; 4943 u32 entry_msr_ld_cnt = 1; 4944 int i; 4945 u32 addr_len = 64; 4946 4947 vmcs_write(ENT_MSR_LD_CNT, entry_msr_ld_cnt); 4948 4949 /* Check first 4 bits of VM-entry MSR-load address */ 4950 for (i = 0; i < 4; i++) { 4951 tmp = (u64)entry_msr_load | 1ull << i; 4952 vmcs_write(ENTER_MSR_LD_ADDR, tmp); 4953 report_prefix_pushf("VM-entry MSR-load addr [4:0] %lx", 4954 tmp & 0xf); 4955 test_vmx_invalid_controls(false); 4956 report_prefix_pop(); 4957 } 4958 4959 if (basic.val & (1ul << 48)) 4960 addr_len = 32; 4961 4962 test_vmcs_addr_values("VM-entry-MSR-load address", 4963 ENTER_MSR_LD_ADDR, 16, false, false, 4964 4, addr_len - 1); 4965 4966 /* 4967 * Check last byte of VM-entry MSR-load address 4968 */ 4969 entry_msr_load = (struct vmx_msr_entry *)((u64)entry_msr_load & ~0xf); 4970 4971 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 4972 i < 64; i++) { 4973 tmp = ((u64)entry_msr_load + entry_msr_ld_cnt * 16 - 1) | 4974 1ul << i; 4975 vmcs_write(ENTER_MSR_LD_ADDR, 4976 tmp - (entry_msr_ld_cnt * 16 - 1)); 4977 test_vmx_invalid_controls(false); 4978 } 4979 4980 vmcs_write(ENT_MSR_LD_CNT, 2); 4981 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 4982 test_vmx_invalid_controls(false); 4983 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 4984 test_vmx_valid_controls(false); 4985 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 4986 test_vmx_valid_controls(false); 4987 } 4988 4989 /* 4990 * Tests for VM-entry control fields 4991 */ 4992 static void test_vm_entry_ctls(void) 4993 { 4994 test_invalid_event_injection(); 4995 test_entry_msr_load(); 4996 } 4997 4998 /* 4999 * The following checks are performed for the VM-exit MSR-store address if 5000 * the VM-exit MSR-store count field is non-zero: 5001 * 5002 * - The lower 4 bits of the VM-exit MSR-store address must be 0. 5003 * The address should not set any bits beyond the processor’s 5004 * physical-address width. 5005 * 5006 * - The address of the last byte in the VM-exit MSR-store area 5007 * should not set any bits beyond the processor’s physical-address 5008 * width. The address of this last byte is VM-exit MSR-store address 5009 * + (MSR count * 16) - 1. (The arithmetic used for the computation 5010 * uses more bits than the processor’s physical-address width.) 5011 * 5012 * If IA32_VMX_BASIC[48] is read as 1, neither address should set any bits 5013 * in the range 63:32. 5014 * 5015 * [Intel SDM] 5016 */ 5017 static void test_exit_msr_store(void) 5018 { 5019 exit_msr_store = alloc_page(); 5020 u64 tmp; 5021 u32 exit_msr_st_cnt = 1; 5022 int i; 5023 u32 addr_len = 64; 5024 5025 vmcs_write(EXI_MSR_ST_CNT, exit_msr_st_cnt); 5026 5027 /* Check first 4 bits of VM-exit MSR-store address */ 5028 for (i = 0; i < 4; i++) { 5029 tmp = (u64)exit_msr_store | 1ull << i; 5030 vmcs_write(EXIT_MSR_ST_ADDR, tmp); 5031 report_prefix_pushf("VM-exit MSR-store addr [4:0] %lx", 5032 tmp & 0xf); 5033 test_vmx_invalid_controls(false); 5034 report_prefix_pop(); 5035 } 5036 5037 if (basic.val & (1ul << 48)) 5038 addr_len = 32; 5039 5040 test_vmcs_addr_values("VM-exit-MSR-store address", 5041 EXIT_MSR_ST_ADDR, 16, false, false, 5042 4, addr_len - 1); 5043 5044 /* 5045 * Check last byte of VM-exit MSR-store address 5046 */ 5047 exit_msr_store = (struct vmx_msr_entry *)((u64)exit_msr_store & ~0xf); 5048 5049 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 5050 i < 64; i++) { 5051 tmp = ((u64)exit_msr_store + exit_msr_st_cnt * 16 - 1) | 5052 1ul << i; 5053 vmcs_write(EXIT_MSR_ST_ADDR, 5054 tmp - (exit_msr_st_cnt * 16 - 1)); 5055 test_vmx_invalid_controls(false); 5056 } 5057 5058 vmcs_write(EXI_MSR_ST_CNT, 2); 5059 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 5060 test_vmx_invalid_controls(false); 5061 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 5062 test_vmx_valid_controls(false); 5063 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 5064 test_vmx_valid_controls(false); 5065 } 5066 5067 /* 5068 * Tests for VM-exit controls 5069 */ 5070 static void test_vm_exit_ctls(void) 5071 { 5072 test_exit_msr_store(); 5073 } 5074 5075 /* 5076 * Check that the virtual CPU checks all of the VMX controls as 5077 * documented in the Intel SDM. 5078 */ 5079 static void vmx_controls_test(void) 5080 { 5081 /* 5082 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 5083 * fail due to invalid guest state, should we make it that 5084 * far. 5085 */ 5086 vmcs_write(GUEST_RFLAGS, 0); 5087 5088 test_vm_execution_ctls(); 5089 test_vm_exit_ctls(); 5090 test_vm_entry_ctls(); 5091 } 5092 5093 struct apic_reg_virt_config { 5094 bool apic_register_virtualization; 5095 bool use_tpr_shadow; 5096 bool virtualize_apic_accesses; 5097 bool virtualize_x2apic_mode; 5098 bool activate_secondary_controls; 5099 }; 5100 5101 struct apic_reg_test { 5102 const char *name; 5103 struct apic_reg_virt_config apic_reg_virt_config; 5104 }; 5105 5106 struct apic_reg_virt_expectation { 5107 enum Reason rd_exit_reason; 5108 enum Reason wr_exit_reason; 5109 u32 val; 5110 u32 (*virt_fn)(u32); 5111 5112 /* 5113 * If false, accessing the APIC access address from L2 is treated as a 5114 * normal memory operation, rather than triggering virtualization. 5115 */ 5116 bool virtualize_apic_accesses; 5117 }; 5118 5119 static u32 apic_virt_identity(u32 val) 5120 { 5121 return val; 5122 } 5123 5124 static u32 apic_virt_nibble1(u32 val) 5125 { 5126 return val & 0xf0; 5127 } 5128 5129 static u32 apic_virt_byte3(u32 val) 5130 { 5131 return val & (0xff << 24); 5132 } 5133 5134 static bool apic_reg_virt_exit_expectation( 5135 u32 reg, struct apic_reg_virt_config *config, 5136 struct apic_reg_virt_expectation *expectation) 5137 { 5138 /* Good configs, where some L2 APIC accesses are virtualized. */ 5139 bool virtualize_apic_accesses_only = 5140 config->virtualize_apic_accesses && 5141 !config->use_tpr_shadow && 5142 !config->apic_register_virtualization && 5143 !config->virtualize_x2apic_mode && 5144 config->activate_secondary_controls; 5145 bool virtualize_apic_accesses_and_use_tpr_shadow = 5146 config->virtualize_apic_accesses && 5147 config->use_tpr_shadow && 5148 !config->apic_register_virtualization && 5149 !config->virtualize_x2apic_mode && 5150 config->activate_secondary_controls; 5151 bool apic_register_virtualization = 5152 config->virtualize_apic_accesses && 5153 config->use_tpr_shadow && 5154 config->apic_register_virtualization && 5155 !config->virtualize_x2apic_mode && 5156 config->activate_secondary_controls; 5157 5158 expectation->val = MAGIC_VAL_1; 5159 expectation->virt_fn = apic_virt_identity; 5160 expectation->virtualize_apic_accesses = 5161 config->virtualize_apic_accesses && 5162 config->activate_secondary_controls; 5163 if (virtualize_apic_accesses_only) { 5164 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5165 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5166 } else if (virtualize_apic_accesses_and_use_tpr_shadow) { 5167 switch (reg) { 5168 case APIC_TASKPRI: 5169 expectation->rd_exit_reason = VMX_VMCALL; 5170 expectation->wr_exit_reason = VMX_VMCALL; 5171 expectation->virt_fn = apic_virt_nibble1; 5172 break; 5173 default: 5174 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5175 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5176 } 5177 } else if (apic_register_virtualization) { 5178 expectation->rd_exit_reason = VMX_VMCALL; 5179 5180 switch (reg) { 5181 case APIC_ID: 5182 case APIC_EOI: 5183 case APIC_LDR: 5184 case APIC_DFR: 5185 case APIC_SPIV: 5186 case APIC_ESR: 5187 case APIC_ICR: 5188 case APIC_LVTT: 5189 case APIC_LVTTHMR: 5190 case APIC_LVTPC: 5191 case APIC_LVT0: 5192 case APIC_LVT1: 5193 case APIC_LVTERR: 5194 case APIC_TMICT: 5195 case APIC_TDCR: 5196 expectation->wr_exit_reason = VMX_APIC_WRITE; 5197 break; 5198 case APIC_LVR: 5199 case APIC_ISR ... APIC_ISR + 0x70: 5200 case APIC_TMR ... APIC_TMR + 0x70: 5201 case APIC_IRR ... APIC_IRR + 0x70: 5202 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5203 break; 5204 case APIC_TASKPRI: 5205 expectation->wr_exit_reason = VMX_VMCALL; 5206 expectation->virt_fn = apic_virt_nibble1; 5207 break; 5208 case APIC_ICR2: 5209 expectation->wr_exit_reason = VMX_VMCALL; 5210 expectation->virt_fn = apic_virt_byte3; 5211 break; 5212 default: 5213 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5214 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5215 } 5216 } else if (!expectation->virtualize_apic_accesses) { 5217 /* 5218 * No APIC registers are directly virtualized. This includes 5219 * VTPR, which can be virtualized through MOV to/from CR8 via 5220 * the use TPR shadow control, but not through directly 5221 * accessing VTPR. 5222 */ 5223 expectation->rd_exit_reason = VMX_VMCALL; 5224 expectation->wr_exit_reason = VMX_VMCALL; 5225 } else { 5226 printf("Cannot parse APIC register virtualization config:\n" 5227 "\tvirtualize_apic_accesses: %d\n" 5228 "\tuse_tpr_shadow: %d\n" 5229 "\tapic_register_virtualization: %d\n" 5230 "\tvirtualize_x2apic_mode: %d\n" 5231 "\tactivate_secondary_controls: %d\n", 5232 config->virtualize_apic_accesses, 5233 config->use_tpr_shadow, 5234 config->apic_register_virtualization, 5235 config->virtualize_x2apic_mode, 5236 config->activate_secondary_controls); 5237 5238 return false; 5239 } 5240 5241 return true; 5242 } 5243 5244 struct apic_reg_test apic_reg_tests[] = { 5245 /* Good configs, where some L2 APIC accesses are virtualized. */ 5246 { 5247 .name = "Virtualize APIC accesses", 5248 .apic_reg_virt_config = { 5249 .virtualize_apic_accesses = true, 5250 .use_tpr_shadow = false, 5251 .apic_register_virtualization = false, 5252 .virtualize_x2apic_mode = false, 5253 .activate_secondary_controls = true, 5254 }, 5255 }, 5256 { 5257 .name = "Virtualize APIC accesses + Use TPR shadow", 5258 .apic_reg_virt_config = { 5259 .virtualize_apic_accesses = true, 5260 .use_tpr_shadow = true, 5261 .apic_register_virtualization = false, 5262 .virtualize_x2apic_mode = false, 5263 .activate_secondary_controls = true, 5264 }, 5265 }, 5266 { 5267 .name = "APIC-register virtualization", 5268 .apic_reg_virt_config = { 5269 .virtualize_apic_accesses = true, 5270 .use_tpr_shadow = true, 5271 .apic_register_virtualization = true, 5272 .virtualize_x2apic_mode = false, 5273 .activate_secondary_controls = true, 5274 }, 5275 }, 5276 5277 /* 5278 * Test that the secondary processor-based VM-execution controls are 5279 * correctly ignored when "activate secondary controls" is disabled. 5280 */ 5281 { 5282 .name = "Activate secondary controls off", 5283 .apic_reg_virt_config = { 5284 .virtualize_apic_accesses = true, 5285 .use_tpr_shadow = false, 5286 .apic_register_virtualization = true, 5287 .virtualize_x2apic_mode = true, 5288 .activate_secondary_controls = false, 5289 }, 5290 }, 5291 { 5292 .name = "Activate secondary controls off + Use TPR shadow", 5293 .apic_reg_virt_config = { 5294 .virtualize_apic_accesses = true, 5295 .use_tpr_shadow = true, 5296 .apic_register_virtualization = true, 5297 .virtualize_x2apic_mode = true, 5298 .activate_secondary_controls = false, 5299 }, 5300 }, 5301 5302 /* 5303 * Test that the APIC access address is treated like an arbitrary memory 5304 * address when "virtualize APIC accesses" is disabled. 5305 */ 5306 { 5307 .name = "Virtualize APIC accesses off + Use TPR shadow", 5308 .apic_reg_virt_config = { 5309 .virtualize_apic_accesses = false, 5310 .use_tpr_shadow = true, 5311 .apic_register_virtualization = true, 5312 .virtualize_x2apic_mode = true, 5313 .activate_secondary_controls = true, 5314 }, 5315 }, 5316 5317 /* 5318 * Test that VM entry fails due to invalid controls when 5319 * "APIC-register virtualization" is enabled while "use TPR shadow" is 5320 * disabled. 5321 */ 5322 { 5323 .name = "APIC-register virtualization + Use TPR shadow off", 5324 .apic_reg_virt_config = { 5325 .virtualize_apic_accesses = true, 5326 .use_tpr_shadow = false, 5327 .apic_register_virtualization = true, 5328 .virtualize_x2apic_mode = false, 5329 .activate_secondary_controls = true, 5330 }, 5331 }, 5332 5333 /* 5334 * Test that VM entry fails due to invalid controls when 5335 * "Virtualize x2APIC mode" is enabled while "use TPR shadow" is 5336 * disabled. 5337 */ 5338 { 5339 .name = "Virtualize x2APIC mode + Use TPR shadow off", 5340 .apic_reg_virt_config = { 5341 .virtualize_apic_accesses = false, 5342 .use_tpr_shadow = false, 5343 .apic_register_virtualization = false, 5344 .virtualize_x2apic_mode = true, 5345 .activate_secondary_controls = true, 5346 }, 5347 }, 5348 { 5349 .name = "Virtualize x2APIC mode + Use TPR shadow off v2", 5350 .apic_reg_virt_config = { 5351 .virtualize_apic_accesses = false, 5352 .use_tpr_shadow = false, 5353 .apic_register_virtualization = true, 5354 .virtualize_x2apic_mode = true, 5355 .activate_secondary_controls = true, 5356 }, 5357 }, 5358 5359 /* 5360 * Test that VM entry fails due to invalid controls when 5361 * "virtualize x2APIC mode" is enabled while "virtualize APIC accesses" 5362 * is enabled. 5363 */ 5364 { 5365 .name = "Virtualize x2APIC mode + Virtualize APIC accesses", 5366 .apic_reg_virt_config = { 5367 .virtualize_apic_accesses = true, 5368 .use_tpr_shadow = true, 5369 .apic_register_virtualization = false, 5370 .virtualize_x2apic_mode = true, 5371 .activate_secondary_controls = true, 5372 }, 5373 }, 5374 { 5375 .name = "Virtualize x2APIC mode + Virtualize APIC accesses v2", 5376 .apic_reg_virt_config = { 5377 .virtualize_apic_accesses = true, 5378 .use_tpr_shadow = true, 5379 .apic_register_virtualization = true, 5380 .virtualize_x2apic_mode = true, 5381 .activate_secondary_controls = true, 5382 }, 5383 }, 5384 }; 5385 5386 enum Apic_op { 5387 APIC_OP_XAPIC_RD, 5388 APIC_OP_XAPIC_WR, 5389 TERMINATE, 5390 }; 5391 5392 static u32 vmx_xapic_read(u32 *apic_access_address, u32 reg) 5393 { 5394 return *(volatile u32 *)((uintptr_t)apic_access_address + reg); 5395 } 5396 5397 static void vmx_xapic_write(u32 *apic_access_address, u32 reg, u32 val) 5398 { 5399 *(volatile u32 *)((uintptr_t)apic_access_address + reg) = val; 5400 } 5401 5402 struct apic_reg_virt_guest_args { 5403 enum Apic_op op; 5404 u32 *apic_access_address; 5405 u32 reg; 5406 u32 val; 5407 bool check_rd; 5408 u32 (*virt_fn)(u32); 5409 } apic_reg_virt_guest_args; 5410 5411 static void apic_reg_virt_guest(void) 5412 { 5413 volatile struct apic_reg_virt_guest_args *args = 5414 &apic_reg_virt_guest_args; 5415 5416 for (;;) { 5417 enum Apic_op op = args->op; 5418 u32 *apic_access_address = args->apic_access_address; 5419 u32 reg = args->reg; 5420 u32 val = args->val; 5421 bool check_rd = args->check_rd; 5422 u32 (*virt_fn)(u32) = args->virt_fn; 5423 5424 if (op == TERMINATE) 5425 break; 5426 5427 if (op == APIC_OP_XAPIC_RD) { 5428 u32 ret = vmx_xapic_read(apic_access_address, reg); 5429 5430 if (check_rd) { 5431 u32 want = virt_fn(val); 5432 u32 got = virt_fn(ret); 5433 5434 report("read 0x%x, expected 0x%x.", 5435 got == want, got, want); 5436 } 5437 } else if (op == APIC_OP_XAPIC_WR) { 5438 vmx_xapic_write(apic_access_address, reg, val); 5439 } 5440 5441 /* 5442 * The L1 should always execute a vmcall after it's done testing 5443 * an individual APIC operation. This helps to validate that the 5444 * L1 and L2 are in sync with each other, as expected. 5445 */ 5446 vmcall(); 5447 } 5448 } 5449 5450 static void test_xapic_rd( 5451 u32 reg, struct apic_reg_virt_expectation *expectation, 5452 u32 *apic_access_address, u32 *virtual_apic_page) 5453 { 5454 u32 val = expectation->val; 5455 u32 exit_reason_want = expectation->rd_exit_reason; 5456 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 5457 5458 report_prefix_pushf("xapic - reading 0x%03x", reg); 5459 5460 /* Configure guest to do an xapic read */ 5461 args->op = APIC_OP_XAPIC_RD; 5462 args->apic_access_address = apic_access_address; 5463 args->reg = reg; 5464 args->val = val; 5465 args->check_rd = exit_reason_want == VMX_VMCALL; 5466 args->virt_fn = expectation->virt_fn; 5467 5468 /* Setup virtual APIC page */ 5469 if (!expectation->virtualize_apic_accesses) { 5470 apic_access_address[apic_reg_index(reg)] = val; 5471 virtual_apic_page[apic_reg_index(reg)] = 0; 5472 } else if (exit_reason_want == VMX_VMCALL) { 5473 apic_access_address[apic_reg_index(reg)] = 0; 5474 virtual_apic_page[apic_reg_index(reg)] = val; 5475 } 5476 5477 /* Enter guest */ 5478 enter_guest(); 5479 5480 /* 5481 * Validate the behavior and 5482 * pass a magic value back to the guest. 5483 */ 5484 if (exit_reason_want == VMX_APIC_ACCESS) { 5485 u32 apic_page_offset = vmcs_read(EXI_QUALIFICATION) & 0xfff; 5486 5487 assert_exit_reason(exit_reason_want); 5488 report("got APIC access exit @ page offset 0x%03x, want 0x%03x", 5489 apic_page_offset == reg, apic_page_offset, reg); 5490 skip_exit_insn(); 5491 5492 /* Reenter guest so it can consume/check rcx and exit again. */ 5493 enter_guest(); 5494 } else if (exit_reason_want != VMX_VMCALL) { 5495 report("Oops, bad exit expectation: %u.", false, 5496 exit_reason_want); 5497 } 5498 5499 skip_exit_vmcall(); 5500 report_prefix_pop(); 5501 } 5502 5503 static void test_xapic_wr( 5504 u32 reg, struct apic_reg_virt_expectation *expectation, 5505 u32 *apic_access_address, u32 *virtual_apic_page) 5506 { 5507 u32 val = expectation->val; 5508 u32 exit_reason_want = expectation->wr_exit_reason; 5509 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 5510 bool virtualized = 5511 expectation->virtualize_apic_accesses && 5512 (exit_reason_want == VMX_APIC_WRITE || 5513 exit_reason_want == VMX_VMCALL); 5514 bool checked = false; 5515 5516 report_prefix_pushf("xapic - writing 0x%x to 0x%03x", val, reg); 5517 5518 /* Configure guest to do an xapic read */ 5519 args->op = APIC_OP_XAPIC_WR; 5520 args->apic_access_address = apic_access_address; 5521 args->reg = reg; 5522 args->val = val; 5523 5524 /* Setup virtual APIC page */ 5525 if (virtualized || !expectation->virtualize_apic_accesses) { 5526 apic_access_address[apic_reg_index(reg)] = 0; 5527 virtual_apic_page[apic_reg_index(reg)] = 0; 5528 } 5529 5530 /* Enter guest */ 5531 enter_guest(); 5532 5533 /* 5534 * Validate the behavior and 5535 * pass a magic value back to the guest. 5536 */ 5537 if (exit_reason_want == VMX_APIC_ACCESS) { 5538 u32 apic_page_offset = vmcs_read(EXI_QUALIFICATION) & 0xfff; 5539 5540 assert_exit_reason(exit_reason_want); 5541 report("got APIC access exit @ page offset 0x%03x, want 0x%03x", 5542 apic_page_offset == reg, apic_page_offset, reg); 5543 skip_exit_insn(); 5544 5545 /* Reenter guest so it can consume/check rcx and exit again. */ 5546 enter_guest(); 5547 } else if (exit_reason_want == VMX_APIC_WRITE) { 5548 assert_exit_reason(exit_reason_want); 5549 report("got APIC write exit @ page offset 0x%03x; val is 0x%x, want 0x%x", 5550 virtual_apic_page[apic_reg_index(reg)] == val, 5551 apic_reg_index(reg), 5552 virtual_apic_page[apic_reg_index(reg)], val); 5553 checked = true; 5554 5555 /* Reenter guest so it can consume/check rcx and exit again. */ 5556 enter_guest(); 5557 } else if (exit_reason_want != VMX_VMCALL) { 5558 report("Oops, bad exit expectation: %u.", false, 5559 exit_reason_want); 5560 } 5561 5562 assert_exit_reason(VMX_VMCALL); 5563 if (virtualized && !checked) { 5564 u32 want = expectation->virt_fn(val); 5565 u32 got = virtual_apic_page[apic_reg_index(reg)]; 5566 got = expectation->virt_fn(got); 5567 5568 report("exitless write; val is 0x%x, want 0x%x", 5569 got == want, got, want); 5570 } else if (!expectation->virtualize_apic_accesses && !checked) { 5571 u32 got = apic_access_address[apic_reg_index(reg)]; 5572 5573 report("non-virtualized write; val is 0x%x, want 0x%x", 5574 got == val, got, val); 5575 } else if (!expectation->virtualize_apic_accesses && checked) { 5576 report("Non-virtualized write was prematurely checked!", false); 5577 } 5578 5579 skip_exit_vmcall(); 5580 report_prefix_pop(); 5581 } 5582 5583 enum Config_type { 5584 CONFIG_TYPE_GOOD, 5585 CONFIG_TYPE_UNSUPPORTED, 5586 CONFIG_TYPE_VMENTRY_FAILS_EARLY, 5587 }; 5588 5589 static enum Config_type configure_apic_reg_virt_test( 5590 struct apic_reg_virt_config *apic_reg_virt_config) 5591 { 5592 u32 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 5593 u32 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 5594 /* Configs where L2 entry fails early, due to invalid controls. */ 5595 bool use_tpr_shadow_incorrectly_off = 5596 !apic_reg_virt_config->use_tpr_shadow && 5597 (apic_reg_virt_config->apic_register_virtualization || 5598 apic_reg_virt_config->virtualize_x2apic_mode) && 5599 apic_reg_virt_config->activate_secondary_controls; 5600 bool virtualize_apic_accesses_incorrectly_on = 5601 apic_reg_virt_config->virtualize_apic_accesses && 5602 apic_reg_virt_config->virtualize_x2apic_mode && 5603 apic_reg_virt_config->activate_secondary_controls; 5604 bool vmentry_fails_early = 5605 use_tpr_shadow_incorrectly_off || 5606 virtualize_apic_accesses_incorrectly_on; 5607 5608 if (apic_reg_virt_config->activate_secondary_controls) { 5609 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 5610 printf("VM-execution control \"activate secondary controls\" NOT supported.\n"); 5611 return CONFIG_TYPE_UNSUPPORTED; 5612 } 5613 cpu_exec_ctrl0 |= CPU_SECONDARY; 5614 } else { 5615 cpu_exec_ctrl0 &= ~CPU_SECONDARY; 5616 } 5617 5618 if (apic_reg_virt_config->virtualize_apic_accesses) { 5619 if (!(ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES)) { 5620 printf("VM-execution control \"virtualize APIC accesses\" NOT supported.\n"); 5621 return CONFIG_TYPE_UNSUPPORTED; 5622 } 5623 cpu_exec_ctrl1 |= CPU_VIRT_APIC_ACCESSES; 5624 } else { 5625 cpu_exec_ctrl1 &= ~CPU_VIRT_APIC_ACCESSES; 5626 } 5627 5628 if (apic_reg_virt_config->use_tpr_shadow) { 5629 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) { 5630 printf("VM-execution control \"use TPR shadow\" NOT supported.\n"); 5631 return CONFIG_TYPE_UNSUPPORTED; 5632 } 5633 cpu_exec_ctrl0 |= CPU_TPR_SHADOW; 5634 } else { 5635 cpu_exec_ctrl0 &= ~CPU_TPR_SHADOW; 5636 } 5637 5638 if (apic_reg_virt_config->apic_register_virtualization) { 5639 if (!(ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT)) { 5640 printf("VM-execution control \"APIC-register virtualization\" NOT supported.\n"); 5641 return CONFIG_TYPE_UNSUPPORTED; 5642 } 5643 cpu_exec_ctrl1 |= CPU_APIC_REG_VIRT; 5644 } else { 5645 cpu_exec_ctrl1 &= ~CPU_APIC_REG_VIRT; 5646 } 5647 5648 if (apic_reg_virt_config->virtualize_x2apic_mode) { 5649 if (!(ctrl_cpu_rev[1].clr & CPU_VIRT_X2APIC)) { 5650 printf("VM-execution control \"virtualize x2APIC mode\" NOT supported.\n"); 5651 return CONFIG_TYPE_UNSUPPORTED; 5652 } 5653 cpu_exec_ctrl1 |= CPU_VIRT_X2APIC; 5654 } else { 5655 cpu_exec_ctrl1 &= ~CPU_VIRT_X2APIC; 5656 } 5657 5658 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 5659 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 5660 5661 if (vmentry_fails_early) 5662 return CONFIG_TYPE_VMENTRY_FAILS_EARLY; 5663 5664 return CONFIG_TYPE_GOOD; 5665 } 5666 5667 static bool cpu_has_apicv(void) 5668 { 5669 return ((ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT) && 5670 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 5671 (ctrl_pin_rev.clr & PIN_POST_INTR)); 5672 } 5673 5674 /* Validates APIC register access across valid virtualization configurations. */ 5675 static void apic_reg_virt_test(void) 5676 { 5677 u32 *apic_access_address; 5678 u32 *virtual_apic_page; 5679 u64 control; 5680 u64 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 5681 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 5682 int i; 5683 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 5684 5685 if (!cpu_has_apicv()) { 5686 report_skip(__func__); 5687 return; 5688 } 5689 5690 control = cpu_exec_ctrl1; 5691 control &= ~CPU_VINTD; 5692 vmcs_write(CPU_EXEC_CTRL1, control); 5693 5694 test_set_guest(apic_reg_virt_guest); 5695 5696 /* 5697 * From the SDM: The 1-setting of the "virtualize APIC accesses" 5698 * VM-execution is guaranteed to apply only if translations to the 5699 * APIC-access address use a 4-KByte page. 5700 */ 5701 apic_access_address = alloc_page(); 5702 force_4k_page(apic_access_address); 5703 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_address)); 5704 5705 virtual_apic_page = alloc_page(); 5706 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 5707 5708 for (i = 0; i < ARRAY_SIZE(apic_reg_tests); i++) { 5709 struct apic_reg_test *apic_reg_test = &apic_reg_tests[i]; 5710 struct apic_reg_virt_config *apic_reg_virt_config = 5711 &apic_reg_test->apic_reg_virt_config; 5712 enum Config_type config_type; 5713 u32 reg; 5714 5715 printf("--- %s test ---\n", apic_reg_test->name); 5716 config_type = 5717 configure_apic_reg_virt_test(apic_reg_virt_config); 5718 if (config_type == CONFIG_TYPE_UNSUPPORTED) { 5719 printf("Skip because of missing features.\n"); 5720 continue; 5721 } 5722 5723 if (config_type == CONFIG_TYPE_VMENTRY_FAILS_EARLY) { 5724 enter_guest_with_bad_controls(); 5725 continue; 5726 } 5727 5728 for (reg = 0; reg < PAGE_SIZE / sizeof(u32); reg += 0x10) { 5729 struct apic_reg_virt_expectation expectation = {}; 5730 bool ok; 5731 5732 ok = apic_reg_virt_exit_expectation( 5733 reg, apic_reg_virt_config, &expectation); 5734 if (!ok) { 5735 report("Malformed test.", false); 5736 break; 5737 } 5738 5739 test_xapic_rd(reg, &expectation, apic_access_address, 5740 virtual_apic_page); 5741 test_xapic_wr(reg, &expectation, apic_access_address, 5742 virtual_apic_page); 5743 } 5744 } 5745 5746 /* Terminate the guest */ 5747 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 5748 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 5749 args->op = TERMINATE; 5750 enter_guest(); 5751 assert_exit_reason(VMX_VMCALL); 5752 } 5753 5754 struct virt_x2apic_mode_config { 5755 struct apic_reg_virt_config apic_reg_virt_config; 5756 bool virtual_interrupt_delivery; 5757 bool use_msr_bitmaps; 5758 bool disable_x2apic_msr_intercepts; 5759 bool disable_x2apic; 5760 }; 5761 5762 struct virt_x2apic_mode_test_case { 5763 const char *name; 5764 struct virt_x2apic_mode_config virt_x2apic_mode_config; 5765 }; 5766 5767 enum Virt_x2apic_mode_behavior_type { 5768 X2APIC_ACCESS_VIRTUALIZED, 5769 X2APIC_ACCESS_PASSED_THROUGH, 5770 X2APIC_ACCESS_TRIGGERS_GP, 5771 }; 5772 5773 struct virt_x2apic_mode_expectation { 5774 enum Reason rd_exit_reason; 5775 enum Reason wr_exit_reason; 5776 5777 /* 5778 * RDMSR and WRMSR handle 64-bit values. However, except for ICR, all of 5779 * the x2APIC registers are 32 bits. Notice: 5780 * 1. vmx_x2apic_read() clears the upper 32 bits for 32-bit registers. 5781 * 2. vmx_x2apic_write() expects the val arg to be well-formed. 5782 */ 5783 u64 rd_val; 5784 u64 wr_val; 5785 5786 /* 5787 * Compares input to virtualized output; 5788 * 1st arg is pointer to return expected virtualization output. 5789 */ 5790 u64 (*virt_fn)(u64); 5791 5792 enum Virt_x2apic_mode_behavior_type rd_behavior; 5793 enum Virt_x2apic_mode_behavior_type wr_behavior; 5794 bool wr_only; 5795 }; 5796 5797 static u64 virt_x2apic_mode_identity(u64 val) 5798 { 5799 return val; 5800 } 5801 5802 static u64 virt_x2apic_mode_nibble1(u64 val) 5803 { 5804 return val & 0xf0; 5805 } 5806 5807 static void virt_x2apic_mode_rd_expectation( 5808 u32 reg, bool virt_x2apic_mode_on, bool disable_x2apic, 5809 bool apic_register_virtualization, bool virtual_interrupt_delivery, 5810 struct virt_x2apic_mode_expectation *expectation) 5811 { 5812 bool readable = 5813 !x2apic_reg_reserved(reg) && 5814 reg != APIC_EOI && 5815 reg != APIC_CMCI; 5816 5817 expectation->rd_exit_reason = VMX_VMCALL; 5818 expectation->virt_fn = virt_x2apic_mode_identity; 5819 if (virt_x2apic_mode_on && apic_register_virtualization) { 5820 expectation->rd_val = MAGIC_VAL_1; 5821 if (reg == APIC_PROCPRI && virtual_interrupt_delivery) 5822 expectation->virt_fn = virt_x2apic_mode_nibble1; 5823 else if (reg == APIC_TASKPRI) 5824 expectation->virt_fn = virt_x2apic_mode_nibble1; 5825 expectation->rd_behavior = X2APIC_ACCESS_VIRTUALIZED; 5826 } else if (virt_x2apic_mode_on && !apic_register_virtualization && 5827 reg == APIC_TASKPRI) { 5828 expectation->rd_val = MAGIC_VAL_1; 5829 expectation->virt_fn = virt_x2apic_mode_nibble1; 5830 expectation->rd_behavior = X2APIC_ACCESS_VIRTUALIZED; 5831 } else if (!disable_x2apic && readable) { 5832 expectation->rd_val = apic_read(reg); 5833 expectation->rd_behavior = X2APIC_ACCESS_PASSED_THROUGH; 5834 } else { 5835 expectation->rd_behavior = X2APIC_ACCESS_TRIGGERS_GP; 5836 } 5837 } 5838 5839 /* 5840 * get_x2apic_wr_val() creates an innocuous write value for an x2APIC register. 5841 * 5842 * For writable registers, get_x2apic_wr_val() deposits the write value into the 5843 * val pointer arg and returns true. For non-writable registers, val is not 5844 * modified and get_x2apic_wr_val() returns false. 5845 * 5846 * CMCI, including the LVT CMCI register, is disabled by default. Thus, 5847 * get_x2apic_wr_val() treats this register as non-writable. 5848 */ 5849 static bool get_x2apic_wr_val(u32 reg, u64 *val) 5850 { 5851 switch (reg) { 5852 case APIC_TASKPRI: 5853 /* Bits 31:8 are reserved. */ 5854 *val &= 0xff; 5855 break; 5856 case APIC_EOI: 5857 case APIC_ESR: 5858 case APIC_TMICT: 5859 /* 5860 * EOI, ESR: WRMSR of a non-zero value causes #GP(0). 5861 * TMICT: A write of 0 to the initial-count register effectively 5862 * stops the local APIC timer, in both one-shot and 5863 * periodic mode. 5864 */ 5865 *val = 0; 5866 break; 5867 case APIC_SPIV: 5868 case APIC_LVTT: 5869 case APIC_LVTTHMR: 5870 case APIC_LVTPC: 5871 case APIC_LVT0: 5872 case APIC_LVT1: 5873 case APIC_LVTERR: 5874 case APIC_TDCR: 5875 /* 5876 * To avoid writing a 1 to a reserved bit or causing some other 5877 * unintended side effect, read the current value and use it as 5878 * the write value. 5879 */ 5880 *val = apic_read(reg); 5881 break; 5882 case APIC_ICR: 5883 *val = 0x40000 | 0xf1; 5884 break; 5885 case APIC_SELF_IPI: 5886 /* 5887 * With special processing (i.e., virtualize x2APIC mode + 5888 * virtual interrupt delivery), writing zero causes an 5889 * APIC-write VM exit. We plan to add a test for enabling 5890 * "virtual-interrupt delivery" in VMCS12, and that's where we 5891 * will test a self IPI with special processing. 5892 */ 5893 *val = 0x0; 5894 break; 5895 default: 5896 return false; 5897 } 5898 5899 return true; 5900 } 5901 5902 static bool special_processing_applies(u32 reg, u64 *val, 5903 bool virt_int_delivery) 5904 { 5905 bool special_processing = 5906 (reg == APIC_TASKPRI) || 5907 (virt_int_delivery && 5908 (reg == APIC_EOI || reg == APIC_SELF_IPI)); 5909 5910 if (special_processing) { 5911 TEST_ASSERT(get_x2apic_wr_val(reg, val)); 5912 return true; 5913 } 5914 5915 return false; 5916 } 5917 5918 static void virt_x2apic_mode_wr_expectation( 5919 u32 reg, bool virt_x2apic_mode_on, bool disable_x2apic, 5920 bool virt_int_delivery, 5921 struct virt_x2apic_mode_expectation *expectation) 5922 { 5923 expectation->wr_exit_reason = VMX_VMCALL; 5924 expectation->wr_val = MAGIC_VAL_1; 5925 expectation->wr_only = false; 5926 5927 if (virt_x2apic_mode_on && 5928 special_processing_applies(reg, &expectation->wr_val, 5929 virt_int_delivery)) { 5930 expectation->wr_behavior = X2APIC_ACCESS_VIRTUALIZED; 5931 if (reg == APIC_SELF_IPI) 5932 expectation->wr_exit_reason = VMX_APIC_WRITE; 5933 } else if (!disable_x2apic && 5934 get_x2apic_wr_val(reg, &expectation->wr_val)) { 5935 expectation->wr_behavior = X2APIC_ACCESS_PASSED_THROUGH; 5936 if (reg == APIC_EOI || reg == APIC_SELF_IPI) 5937 expectation->wr_only = true; 5938 if (reg == APIC_ICR) 5939 expectation->wr_exit_reason = VMX_EXTINT; 5940 } else { 5941 expectation->wr_behavior = X2APIC_ACCESS_TRIGGERS_GP; 5942 /* 5943 * Writing 1 to a reserved bit triggers a #GP. 5944 * Thus, set the write value to 0, which seems 5945 * the most likely to detect a missed #GP. 5946 */ 5947 expectation->wr_val = 0; 5948 } 5949 } 5950 5951 static void virt_x2apic_mode_exit_expectation( 5952 u32 reg, struct virt_x2apic_mode_config *config, 5953 struct virt_x2apic_mode_expectation *expectation) 5954 { 5955 struct apic_reg_virt_config *base_config = 5956 &config->apic_reg_virt_config; 5957 bool virt_x2apic_mode_on = 5958 base_config->virtualize_x2apic_mode && 5959 config->use_msr_bitmaps && 5960 config->disable_x2apic_msr_intercepts && 5961 base_config->activate_secondary_controls; 5962 5963 virt_x2apic_mode_wr_expectation( 5964 reg, virt_x2apic_mode_on, config->disable_x2apic, 5965 config->virtual_interrupt_delivery, expectation); 5966 virt_x2apic_mode_rd_expectation( 5967 reg, virt_x2apic_mode_on, config->disable_x2apic, 5968 base_config->apic_register_virtualization, 5969 config->virtual_interrupt_delivery, expectation); 5970 } 5971 5972 struct virt_x2apic_mode_test_case virt_x2apic_mode_tests[] = { 5973 /* 5974 * Baseline "virtualize x2APIC mode" configuration: 5975 * - virtualize x2APIC mode 5976 * - virtual-interrupt delivery 5977 * - APIC-register virtualization 5978 * - x2APIC MSR intercepts disabled 5979 * 5980 * Reads come from virtual APIC page, special processing applies to 5981 * VTPR, EOI, and SELF IPI, and all other writes pass through to L1 5982 * APIC. 5983 */ 5984 { 5985 .name = "Baseline", 5986 .virt_x2apic_mode_config = { 5987 .virtual_interrupt_delivery = true, 5988 .use_msr_bitmaps = true, 5989 .disable_x2apic_msr_intercepts = true, 5990 .disable_x2apic = false, 5991 .apic_reg_virt_config = { 5992 .apic_register_virtualization = true, 5993 .use_tpr_shadow = true, 5994 .virtualize_apic_accesses = false, 5995 .virtualize_x2apic_mode = true, 5996 .activate_secondary_controls = true, 5997 }, 5998 }, 5999 }, 6000 { 6001 .name = "Baseline w/ x2apic disabled", 6002 .virt_x2apic_mode_config = { 6003 .virtual_interrupt_delivery = true, 6004 .use_msr_bitmaps = true, 6005 .disable_x2apic_msr_intercepts = true, 6006 .disable_x2apic = true, 6007 .apic_reg_virt_config = { 6008 .apic_register_virtualization = true, 6009 .use_tpr_shadow = true, 6010 .virtualize_apic_accesses = false, 6011 .virtualize_x2apic_mode = true, 6012 .activate_secondary_controls = true, 6013 }, 6014 }, 6015 }, 6016 6017 /* 6018 * Baseline, minus virtual-interrupt delivery. Reads come from virtual 6019 * APIC page, special processing applies to VTPR, and all other writes 6020 * pass through to L1 APIC. 6021 */ 6022 { 6023 .name = "Baseline - virtual interrupt delivery", 6024 .virt_x2apic_mode_config = { 6025 .virtual_interrupt_delivery = false, 6026 .use_msr_bitmaps = true, 6027 .disable_x2apic_msr_intercepts = true, 6028 .disable_x2apic = false, 6029 .apic_reg_virt_config = { 6030 .apic_register_virtualization = true, 6031 .use_tpr_shadow = true, 6032 .virtualize_apic_accesses = false, 6033 .virtualize_x2apic_mode = true, 6034 .activate_secondary_controls = true, 6035 }, 6036 }, 6037 }, 6038 6039 /* 6040 * Baseline, minus APIC-register virtualization. x2APIC reads pass 6041 * through to L1's APIC, unless reading VTPR 6042 */ 6043 { 6044 .name = "Virtualize x2APIC mode, no APIC reg virt", 6045 .virt_x2apic_mode_config = { 6046 .virtual_interrupt_delivery = true, 6047 .use_msr_bitmaps = true, 6048 .disable_x2apic_msr_intercepts = true, 6049 .disable_x2apic = false, 6050 .apic_reg_virt_config = { 6051 .apic_register_virtualization = false, 6052 .use_tpr_shadow = true, 6053 .virtualize_apic_accesses = false, 6054 .virtualize_x2apic_mode = true, 6055 .activate_secondary_controls = true, 6056 }, 6057 }, 6058 }, 6059 { 6060 .name = "Virtualize x2APIC mode, no APIC reg virt, x2APIC off", 6061 .virt_x2apic_mode_config = { 6062 .virtual_interrupt_delivery = true, 6063 .use_msr_bitmaps = true, 6064 .disable_x2apic_msr_intercepts = true, 6065 .disable_x2apic = true, 6066 .apic_reg_virt_config = { 6067 .apic_register_virtualization = false, 6068 .use_tpr_shadow = true, 6069 .virtualize_apic_accesses = false, 6070 .virtualize_x2apic_mode = true, 6071 .activate_secondary_controls = true, 6072 }, 6073 }, 6074 }, 6075 6076 /* 6077 * Enable "virtualize x2APIC mode" and "APIC-register virtualization", 6078 * and disable intercepts for the x2APIC MSRs, but fail to enable 6079 * "activate secondary controls" (i.e. L2 gets access to L1's x2APIC 6080 * MSRs). 6081 */ 6082 { 6083 .name = "Fail to enable activate secondary controls", 6084 .virt_x2apic_mode_config = { 6085 .virtual_interrupt_delivery = true, 6086 .use_msr_bitmaps = true, 6087 .disable_x2apic_msr_intercepts = true, 6088 .disable_x2apic = false, 6089 .apic_reg_virt_config = { 6090 .apic_register_virtualization = true, 6091 .use_tpr_shadow = true, 6092 .virtualize_apic_accesses = false, 6093 .virtualize_x2apic_mode = true, 6094 .activate_secondary_controls = false, 6095 }, 6096 }, 6097 }, 6098 6099 /* 6100 * Enable "APIC-register virtualization" and enable "activate secondary 6101 * controls" and disable intercepts for the x2APIC MSRs, but do not 6102 * enable the "virtualize x2APIC mode" VM-execution control (i.e. L2 6103 * gets access to L1's x2APIC MSRs). 6104 */ 6105 { 6106 .name = "Fail to enable virtualize x2APIC mode", 6107 .virt_x2apic_mode_config = { 6108 .virtual_interrupt_delivery = true, 6109 .use_msr_bitmaps = true, 6110 .disable_x2apic_msr_intercepts = true, 6111 .disable_x2apic = false, 6112 .apic_reg_virt_config = { 6113 .apic_register_virtualization = true, 6114 .use_tpr_shadow = true, 6115 .virtualize_apic_accesses = false, 6116 .virtualize_x2apic_mode = false, 6117 .activate_secondary_controls = true, 6118 }, 6119 }, 6120 }, 6121 6122 /* 6123 * Disable "Virtualize x2APIC mode", disable x2APIC MSR intercepts, and 6124 * enable "APIC-register virtualization" --> L2 gets L1's x2APIC MSRs. 6125 */ 6126 { 6127 .name = "Baseline", 6128 .virt_x2apic_mode_config = { 6129 .virtual_interrupt_delivery = true, 6130 .use_msr_bitmaps = true, 6131 .disable_x2apic_msr_intercepts = true, 6132 .disable_x2apic = false, 6133 .apic_reg_virt_config = { 6134 .apic_register_virtualization = true, 6135 .use_tpr_shadow = true, 6136 .virtualize_apic_accesses = false, 6137 .virtualize_x2apic_mode = false, 6138 .activate_secondary_controls = true, 6139 }, 6140 }, 6141 }, 6142 }; 6143 6144 enum X2apic_op { 6145 X2APIC_OP_RD, 6146 X2APIC_OP_WR, 6147 X2APIC_TERMINATE, 6148 }; 6149 6150 static u64 vmx_x2apic_read(u32 reg) 6151 { 6152 u32 msr_addr = x2apic_msr(reg); 6153 u64 val; 6154 6155 val = rdmsr(msr_addr); 6156 6157 return val; 6158 } 6159 6160 static void vmx_x2apic_write(u32 reg, u64 val) 6161 { 6162 u32 msr_addr = x2apic_msr(reg); 6163 6164 wrmsr(msr_addr, val); 6165 } 6166 6167 struct virt_x2apic_mode_guest_args { 6168 enum X2apic_op op; 6169 u32 reg; 6170 u64 val; 6171 bool should_gp; 6172 u64 (*virt_fn)(u64); 6173 } virt_x2apic_mode_guest_args; 6174 6175 static volatile bool handle_x2apic_gp_ran; 6176 static volatile u32 handle_x2apic_gp_insn_len; 6177 static void handle_x2apic_gp(struct ex_regs *regs) 6178 { 6179 handle_x2apic_gp_ran = true; 6180 regs->rip += handle_x2apic_gp_insn_len; 6181 } 6182 6183 static handler setup_x2apic_gp_handler(void) 6184 { 6185 handler old_handler; 6186 6187 old_handler = handle_exception(GP_VECTOR, handle_x2apic_gp); 6188 /* RDMSR and WRMSR are both 2 bytes, assuming no prefixes. */ 6189 handle_x2apic_gp_insn_len = 2; 6190 6191 return old_handler; 6192 } 6193 6194 static void teardown_x2apic_gp_handler(handler old_handler) 6195 { 6196 handle_exception(GP_VECTOR, old_handler); 6197 6198 /* 6199 * Defensively reset instruction length, so that if the handler is 6200 * incorrectly used, it will loop infinitely, rather than run off into 6201 * la la land. 6202 */ 6203 handle_x2apic_gp_insn_len = 0; 6204 handle_x2apic_gp_ran = false; 6205 } 6206 6207 static void virt_x2apic_mode_guest(void) 6208 { 6209 volatile struct virt_x2apic_mode_guest_args *args = 6210 &virt_x2apic_mode_guest_args; 6211 6212 for (;;) { 6213 enum X2apic_op op = args->op; 6214 u32 reg = args->reg; 6215 u64 val = args->val; 6216 bool should_gp = args->should_gp; 6217 u64 (*virt_fn)(u64) = args->virt_fn; 6218 handler old_handler; 6219 6220 if (op == X2APIC_TERMINATE) 6221 break; 6222 6223 if (should_gp) { 6224 TEST_ASSERT(!handle_x2apic_gp_ran); 6225 old_handler = setup_x2apic_gp_handler(); 6226 } 6227 6228 if (op == X2APIC_OP_RD) { 6229 u64 ret = vmx_x2apic_read(reg); 6230 6231 if (!should_gp) { 6232 u64 want = virt_fn(val); 6233 u64 got = virt_fn(ret); 6234 6235 report("APIC read; got 0x%lx, want 0x%lx.", 6236 got == want, got, want); 6237 } 6238 } else if (op == X2APIC_OP_WR) { 6239 vmx_x2apic_write(reg, val); 6240 } 6241 6242 if (should_gp) { 6243 report("x2APIC op triggered GP.", 6244 handle_x2apic_gp_ran); 6245 teardown_x2apic_gp_handler(old_handler); 6246 } 6247 6248 /* 6249 * The L1 should always execute a vmcall after it's done testing 6250 * an individual APIC operation. This helps to validate that the 6251 * L1 and L2 are in sync with each other, as expected. 6252 */ 6253 vmcall(); 6254 } 6255 } 6256 6257 static void test_x2apic_rd( 6258 u32 reg, struct virt_x2apic_mode_expectation *expectation, 6259 u32 *virtual_apic_page) 6260 { 6261 u64 val = expectation->rd_val; 6262 u32 exit_reason_want = expectation->rd_exit_reason; 6263 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6264 6265 report_prefix_pushf("x2apic - reading 0x%03x", reg); 6266 6267 /* Configure guest to do an x2apic read */ 6268 args->op = X2APIC_OP_RD; 6269 args->reg = reg; 6270 args->val = val; 6271 args->should_gp = expectation->rd_behavior == X2APIC_ACCESS_TRIGGERS_GP; 6272 args->virt_fn = expectation->virt_fn; 6273 6274 /* Setup virtual APIC page */ 6275 if (expectation->rd_behavior == X2APIC_ACCESS_VIRTUALIZED) 6276 virtual_apic_page[apic_reg_index(reg)] = (u32)val; 6277 6278 /* Enter guest */ 6279 enter_guest(); 6280 6281 if (exit_reason_want != VMX_VMCALL) { 6282 report("Oops, bad exit expectation: %u.", false, 6283 exit_reason_want); 6284 } 6285 6286 skip_exit_vmcall(); 6287 report_prefix_pop(); 6288 } 6289 6290 static volatile bool handle_x2apic_ipi_ran; 6291 static void handle_x2apic_ipi(isr_regs_t *regs) 6292 { 6293 handle_x2apic_ipi_ran = true; 6294 eoi(); 6295 } 6296 6297 static void test_x2apic_wr( 6298 u32 reg, struct virt_x2apic_mode_expectation *expectation, 6299 u32 *virtual_apic_page) 6300 { 6301 u64 val = expectation->wr_val; 6302 u32 exit_reason_want = expectation->wr_exit_reason; 6303 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6304 int ipi_vector = 0xf1; 6305 u32 restore_val = 0; 6306 6307 report_prefix_pushf("x2apic - writing 0x%lx to 0x%03x", val, reg); 6308 6309 /* Configure guest to do an x2apic read */ 6310 args->op = X2APIC_OP_WR; 6311 args->reg = reg; 6312 args->val = val; 6313 args->should_gp = expectation->wr_behavior == X2APIC_ACCESS_TRIGGERS_GP; 6314 6315 /* Setup virtual APIC page */ 6316 if (expectation->wr_behavior == X2APIC_ACCESS_VIRTUALIZED) 6317 virtual_apic_page[apic_reg_index(reg)] = 0; 6318 if (expectation->wr_behavior == X2APIC_ACCESS_PASSED_THROUGH && !expectation->wr_only) 6319 restore_val = apic_read(reg); 6320 6321 /* Setup IPI handler */ 6322 handle_x2apic_ipi_ran = false; 6323 handle_irq(ipi_vector, handle_x2apic_ipi); 6324 6325 /* Enter guest */ 6326 enter_guest(); 6327 6328 /* 6329 * Validate the behavior and 6330 * pass a magic value back to the guest. 6331 */ 6332 if (exit_reason_want == VMX_EXTINT) { 6333 assert_exit_reason(exit_reason_want); 6334 6335 /* Clear the external interrupt. */ 6336 irq_enable(); 6337 asm volatile ("nop"); 6338 irq_disable(); 6339 report("Got pending interrupt after IRQ enabled.", 6340 handle_x2apic_ipi_ran); 6341 6342 enter_guest(); 6343 } else if (exit_reason_want == VMX_APIC_WRITE) { 6344 assert_exit_reason(exit_reason_want); 6345 report("got APIC write exit @ page offset 0x%03x; val is 0x%x, want 0x%lx", 6346 virtual_apic_page[apic_reg_index(reg)] == val, 6347 apic_reg_index(reg), 6348 virtual_apic_page[apic_reg_index(reg)], val); 6349 6350 /* Reenter guest so it can consume/check rcx and exit again. */ 6351 enter_guest(); 6352 } else if (exit_reason_want != VMX_VMCALL) { 6353 report("Oops, bad exit expectation: %u.", false, 6354 exit_reason_want); 6355 } 6356 6357 assert_exit_reason(VMX_VMCALL); 6358 if (expectation->wr_behavior == X2APIC_ACCESS_VIRTUALIZED) { 6359 u64 want = val; 6360 u32 got = virtual_apic_page[apic_reg_index(reg)]; 6361 6362 report("x2APIC write; got 0x%x, want 0x%lx", 6363 got == want, got, want); 6364 } else if (expectation->wr_behavior == X2APIC_ACCESS_PASSED_THROUGH) { 6365 if (!expectation->wr_only) { 6366 u32 got = apic_read(reg); 6367 bool ok; 6368 6369 /* 6370 * When L1's TPR is passed through to L2, the lower 6371 * nibble can be lost. For example, if L2 executes 6372 * WRMSR(0x808, 0x78), then, L1 might read 0x70. 6373 * 6374 * Here's how the lower nibble can get lost: 6375 * 1. L2 executes WRMSR(0x808, 0x78). 6376 * 2. L2 exits to L0 with a WRMSR exit. 6377 * 3. L0 emulates WRMSR, by writing L1's TPR. 6378 * 4. L0 re-enters L2. 6379 * 5. L2 exits to L0 (reason doesn't matter). 6380 * 6. L0 reflects L2's exit to L1. 6381 * 7. Before entering L1, L0 exits to user-space 6382 * (e.g., to satisfy TPR access reporting). 6383 * 8. User-space executes KVM_SET_REGS ioctl, which 6384 * clears the lower nibble of L1's TPR. 6385 */ 6386 if (reg == APIC_TASKPRI) { 6387 got = apic_virt_nibble1(got); 6388 val = apic_virt_nibble1(val); 6389 } 6390 6391 ok = got == val; 6392 report("non-virtualized write; val is 0x%x, want 0x%lx", 6393 ok, got, val); 6394 apic_write(reg, restore_val); 6395 } else { 6396 report("non-virtualized and write-only OK", true); 6397 } 6398 } 6399 skip_exit_insn(); 6400 6401 report_prefix_pop(); 6402 } 6403 6404 static enum Config_type configure_virt_x2apic_mode_test( 6405 struct virt_x2apic_mode_config *virt_x2apic_mode_config, 6406 u8 *msr_bitmap_page) 6407 { 6408 int msr; 6409 u32 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6410 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6411 6412 /* x2apic-specific VMCS config */ 6413 if (virt_x2apic_mode_config->use_msr_bitmaps) { 6414 /* virt_x2apic_mode_test() checks for MSR bitmaps support */ 6415 cpu_exec_ctrl0 |= CPU_MSR_BITMAP; 6416 } else { 6417 cpu_exec_ctrl0 &= ~CPU_MSR_BITMAP; 6418 } 6419 6420 if (virt_x2apic_mode_config->virtual_interrupt_delivery) { 6421 if (!(ctrl_cpu_rev[1].clr & CPU_VINTD)) { 6422 report_skip("VM-execution control \"virtual-interrupt delivery\" NOT supported.\n"); 6423 return CONFIG_TYPE_UNSUPPORTED; 6424 } 6425 cpu_exec_ctrl1 |= CPU_VINTD; 6426 } else { 6427 cpu_exec_ctrl1 &= ~CPU_VINTD; 6428 } 6429 6430 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6431 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6432 6433 /* x2APIC MSR intercepts are usually off for "Virtualize x2APIC mode" */ 6434 for (msr = 0x800; msr <= 0x8ff; msr++) { 6435 if (virt_x2apic_mode_config->disable_x2apic_msr_intercepts) { 6436 clear_bit(msr, msr_bitmap_page + 0x000); 6437 clear_bit(msr, msr_bitmap_page + 0x800); 6438 } else { 6439 set_bit(msr, msr_bitmap_page + 0x000); 6440 set_bit(msr, msr_bitmap_page + 0x800); 6441 } 6442 } 6443 6444 /* x2APIC mode can impact virtualization */ 6445 reset_apic(); 6446 if (!virt_x2apic_mode_config->disable_x2apic) 6447 enable_x2apic(); 6448 6449 return configure_apic_reg_virt_test( 6450 &virt_x2apic_mode_config->apic_reg_virt_config); 6451 } 6452 6453 static void virt_x2apic_mode_test(void) 6454 { 6455 u32 *virtual_apic_page; 6456 u8 *msr_bitmap_page; 6457 u64 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6458 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6459 int i; 6460 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6461 6462 if (!cpu_has_apicv()) { 6463 report_skip(__func__); 6464 return; 6465 } 6466 6467 /* 6468 * This is to exercise an issue in KVM's logic to merge L0's and L1's 6469 * MSR bitmaps. Previously, an L1 could get at L0's x2APIC MSRs by 6470 * writing the IA32_SPEC_CTRL MSR or the IA32_PRED_CMD MSRs. KVM would 6471 * then proceed to manipulate the MSR bitmaps, as if VMCS12 had the 6472 * "Virtualize x2APIC mod" control set, even when it didn't. 6473 */ 6474 if (has_spec_ctrl()) 6475 wrmsr(MSR_IA32_SPEC_CTRL, 1); 6476 6477 /* 6478 * Check that VMCS12 supports: 6479 * - "Virtual-APIC address", indicated by "use TPR shadow" 6480 * - "MSR-bitmap address", indicated by "use MSR bitmaps" 6481 */ 6482 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) { 6483 report_skip("VM-execution control \"use TPR shadow\" NOT supported.\n"); 6484 return; 6485 } else if (!(ctrl_cpu_rev[0].clr & CPU_MSR_BITMAP)) { 6486 report_skip("VM-execution control \"use MSR bitmaps\" NOT supported.\n"); 6487 return; 6488 } 6489 6490 test_set_guest(virt_x2apic_mode_guest); 6491 6492 virtual_apic_page = alloc_page(); 6493 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 6494 6495 msr_bitmap_page = alloc_page(); 6496 memset(msr_bitmap_page, 0xff, PAGE_SIZE); 6497 vmcs_write(MSR_BITMAP, virt_to_phys(msr_bitmap_page)); 6498 6499 for (i = 0; i < ARRAY_SIZE(virt_x2apic_mode_tests); i++) { 6500 struct virt_x2apic_mode_test_case *virt_x2apic_mode_test_case = 6501 &virt_x2apic_mode_tests[i]; 6502 struct virt_x2apic_mode_config *virt_x2apic_mode_config = 6503 &virt_x2apic_mode_test_case->virt_x2apic_mode_config; 6504 enum Config_type config_type; 6505 u32 reg; 6506 6507 printf("--- %s test ---\n", virt_x2apic_mode_test_case->name); 6508 config_type = 6509 configure_virt_x2apic_mode_test(virt_x2apic_mode_config, 6510 msr_bitmap_page); 6511 if (config_type == CONFIG_TYPE_UNSUPPORTED) { 6512 report_skip("Skip because of missing features.\n"); 6513 continue; 6514 } else if (config_type == CONFIG_TYPE_VMENTRY_FAILS_EARLY) { 6515 enter_guest_with_bad_controls(); 6516 continue; 6517 } 6518 6519 for (reg = 0; reg < PAGE_SIZE / sizeof(u32); reg += 0x10) { 6520 struct virt_x2apic_mode_expectation expectation; 6521 6522 virt_x2apic_mode_exit_expectation( 6523 reg, virt_x2apic_mode_config, &expectation); 6524 6525 test_x2apic_rd(reg, &expectation, virtual_apic_page); 6526 test_x2apic_wr(reg, &expectation, virtual_apic_page); 6527 } 6528 } 6529 6530 6531 /* Terminate the guest */ 6532 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6533 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6534 args->op = X2APIC_TERMINATE; 6535 enter_guest(); 6536 assert_exit_reason(VMX_VMCALL); 6537 } 6538 6539 /* 6540 * On processors that support Intel 64 architecture, the IA32_SYSENTER_ESP 6541 * field and the IA32_SYSENTER_EIP field must each contain a canonical 6542 * address. 6543 * 6544 * [Intel SDM] 6545 */ 6546 static void test_sysenter_field(u32 field, const char *name) 6547 { 6548 u64 addr_saved = vmcs_read(field); 6549 6550 vmcs_write(field, NONCANONICAL); 6551 report_prefix_pushf("%s non-canonical", name); 6552 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, false); 6553 report_prefix_pop(); 6554 6555 vmcs_write(field, 0xffffffff); 6556 report_prefix_pushf("%s canonical", name); 6557 test_vmx_vmlaunch(0, false); 6558 report_prefix_pop(); 6559 6560 vmcs_write(field, addr_saved); 6561 } 6562 6563 static void test_ctl_reg(const char *cr_name, u64 cr, u64 fixed0, u64 fixed1) 6564 { 6565 u64 val; 6566 u64 cr_saved = vmcs_read(cr); 6567 int i; 6568 6569 val = fixed0 & fixed1; 6570 if (cr == HOST_CR4) 6571 vmcs_write(cr, val | X86_CR4_PAE); 6572 else 6573 vmcs_write(cr, val); 6574 report_prefix_pushf("%s %lx", cr_name, val); 6575 if (val == fixed0) 6576 test_vmx_vmlaunch(0, false); 6577 else 6578 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, 6579 false); 6580 report_prefix_pop(); 6581 6582 for (i = 0; i < 64; i++) { 6583 6584 /* Set a bit when the corresponding bit in fixed1 is 0 */ 6585 if ((fixed1 & (1ull << i)) == 0) { 6586 if (cr == HOST_CR4 && ((1ull << i) & X86_CR4_SMEP || 6587 (1ull << i) & X86_CR4_SMAP)) 6588 continue; 6589 6590 vmcs_write(cr, cr_saved | (1ull << i)); 6591 report_prefix_pushf("%s %llx", cr_name, 6592 cr_saved | (1ull << i)); 6593 test_vmx_vmlaunch( 6594 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, 6595 false); 6596 report_prefix_pop(); 6597 } 6598 6599 /* Unset a bit when the corresponding bit in fixed0 is 1 */ 6600 if (fixed0 & (1ull << i)) { 6601 vmcs_write(cr, cr_saved & ~(1ull << i)); 6602 report_prefix_pushf("%s %llx", cr_name, 6603 cr_saved & ~(1ull << i)); 6604 test_vmx_vmlaunch( 6605 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, 6606 false); 6607 report_prefix_pop(); 6608 } 6609 } 6610 6611 vmcs_write(cr, cr_saved); 6612 } 6613 6614 /* 6615 * 1. The CR0 field must not set any bit to a value not supported in VMX 6616 * operation. 6617 * 2. The CR4 field must not set any bit to a value not supported in VMX 6618 * operation. 6619 * 3. On processors that support Intel 64 architecture, the CR3 field must 6620 * be such that bits 63:52 and bits in the range 51:32 beyond the 6621 * processor’s physical-address width must be 0. 6622 * 6623 * [Intel SDM] 6624 */ 6625 static void test_host_ctl_regs(void) 6626 { 6627 u64 fixed0, fixed1, cr3, cr3_saved; 6628 int i; 6629 6630 /* Test CR0 */ 6631 fixed0 = rdmsr(MSR_IA32_VMX_CR0_FIXED0); 6632 fixed1 = rdmsr(MSR_IA32_VMX_CR0_FIXED1); 6633 test_ctl_reg("HOST_CR0", HOST_CR0, fixed0, fixed1); 6634 6635 /* Test CR4 */ 6636 fixed0 = rdmsr(MSR_IA32_VMX_CR4_FIXED0); 6637 fixed1 = rdmsr(MSR_IA32_VMX_CR4_FIXED1) & 6638 ~(X86_CR4_SMEP | X86_CR4_SMAP); 6639 test_ctl_reg("HOST_CR4", HOST_CR4, fixed0, fixed1); 6640 6641 /* Test CR3 */ 6642 cr3_saved = vmcs_read(HOST_CR3); 6643 for (i = cpuid_maxphyaddr(); i < 64; i++) { 6644 cr3 = cr3_saved | (1ul << i); 6645 vmcs_write(HOST_CR3, cr3); 6646 report_prefix_pushf("HOST_CR3 %lx", cr3); 6647 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, 6648 false); 6649 report_prefix_pop(); 6650 } 6651 6652 vmcs_write(HOST_CR3, cr3_saved); 6653 } 6654 6655 /* 6656 * PAT values higher than 8 are uninteresting since they're likely lumped 6657 * in with "8". We only test values above 8 one bit at a time, 6658 * in order to reduce the number of VM-Entries and keep the runtime reasonable. 6659 */ 6660 #define PAT_VAL_LIMIT 8 6661 6662 static void test_pat(u32 field, const char * field_name, u32 ctrl_field, 6663 u64 ctrl_bit) 6664 { 6665 u32 ctrl_saved = vmcs_read(ctrl_field); 6666 u64 pat_saved = vmcs_read(field); 6667 u64 i, val; 6668 u32 j; 6669 int error; 6670 6671 vmcs_write(ctrl_field, ctrl_saved & ~ctrl_bit); 6672 for (i = 0; i < 256; i = (i < PAT_VAL_LIMIT) ? i + 1 : i * 2) { 6673 /* Test PAT0..PAT7 fields */ 6674 for (j = 0; j < (i ? 8 : 1); j++) { 6675 val = i << j * 8; 6676 vmcs_write(field, val); 6677 report_prefix_pushf("%s %lx", field_name, val); 6678 test_vmx_vmlaunch(0, false); 6679 report_prefix_pop(); 6680 } 6681 } 6682 6683 vmcs_write(ctrl_field, ctrl_saved | ctrl_bit); 6684 for (i = 0; i < 256; i = (i < PAT_VAL_LIMIT) ? i + 1 : i * 2) { 6685 /* Test PAT0..PAT7 fields */ 6686 for (j = 0; j < (i ? 8 : 1); j++) { 6687 val = i << j * 8; 6688 vmcs_write(field, val); 6689 report_prefix_pushf("%s %lx", field_name, val); 6690 if (i == 0x2 || i == 0x3 || i >= 0x8) 6691 error = VMXERR_ENTRY_INVALID_HOST_STATE_FIELD; 6692 else 6693 error = 0; 6694 test_vmx_vmlaunch(error, false); 6695 report_prefix_pop(); 6696 } 6697 } 6698 6699 vmcs_write(ctrl_field, ctrl_saved); 6700 vmcs_write(field, pat_saved); 6701 } 6702 6703 /* 6704 * If the "load IA32_PAT" VM-exit control is 1, the value of the field 6705 * for the IA32_PAT MSR must be one that could be written by WRMSR 6706 * without fault at CPL 0. Specifically, each of the 8 bytes in the 6707 * field must have one of the values 0 (UC), 1 (WC), 4 (WT), 5 (WP), 6708 * 6 (WB), or 7 (UC-). 6709 * 6710 * [Intel SDM] 6711 */ 6712 static void test_load_host_pat(void) 6713 { 6714 /* 6715 * "load IA32_PAT" VM-exit control 6716 */ 6717 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) { 6718 printf("\"Load-IA32-PAT\" exit control not supported\n"); 6719 return; 6720 } 6721 6722 test_pat(HOST_PAT, "HOST_PAT", EXI_CONTROLS, EXI_LOAD_PAT); 6723 } 6724 6725 /* 6726 * Check that the virtual CPU checks the VMX Host State Area as 6727 * documented in the Intel SDM. 6728 */ 6729 static void vmx_host_state_area_test(void) 6730 { 6731 /* 6732 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 6733 * fail due to invalid guest state, should we make it that 6734 * far. 6735 */ 6736 vmcs_write(GUEST_RFLAGS, 0); 6737 6738 test_host_ctl_regs(); 6739 6740 test_sysenter_field(HOST_SYSENTER_ESP, "HOST_SYSENTER_ESP"); 6741 test_sysenter_field(HOST_SYSENTER_EIP, "HOST_SYSENTER_EIP"); 6742 6743 test_load_host_pat(); 6744 } 6745 6746 static bool valid_vmcs_for_vmentry(void) 6747 { 6748 struct vmcs *current_vmcs = NULL; 6749 6750 if (vmcs_save(¤t_vmcs)) 6751 return false; 6752 6753 return current_vmcs && !current_vmcs->hdr.shadow_vmcs; 6754 } 6755 6756 static void try_vmentry_in_movss_shadow(void) 6757 { 6758 u32 vm_inst_err; 6759 u32 flags; 6760 bool early_failure = false; 6761 u32 expected_flags = X86_EFLAGS_FIXED; 6762 bool valid_vmcs = valid_vmcs_for_vmentry(); 6763 6764 expected_flags |= valid_vmcs ? X86_EFLAGS_ZF : X86_EFLAGS_CF; 6765 6766 /* 6767 * Indirectly set VM_INST_ERR to 12 ("VMREAD/VMWRITE from/to 6768 * unsupported VMCS component"). 6769 */ 6770 vmcs_write(~0u, 0); 6771 6772 __asm__ __volatile__ ("mov %[host_rsp], %%edx;" 6773 "vmwrite %%rsp, %%rdx;" 6774 "mov 0f, %%rax;" 6775 "mov %[host_rip], %%edx;" 6776 "vmwrite %%rax, %%rdx;" 6777 "mov $-1, %%ah;" 6778 "sahf;" 6779 "mov %%ss, %%ax;" 6780 "mov %%ax, %%ss;" 6781 "vmlaunch;" 6782 "mov $1, %[early_failure];" 6783 "0: lahf;" 6784 "movzbl %%ah, %[flags]" 6785 : [early_failure] "+r" (early_failure), 6786 [flags] "=&a" (flags) 6787 : [host_rsp] "i" (HOST_RSP), 6788 [host_rip] "i" (HOST_RIP) 6789 : "rdx", "cc", "memory"); 6790 vm_inst_err = vmcs_read(VMX_INST_ERROR); 6791 6792 report("Early VM-entry failure", early_failure); 6793 report("RFLAGS[8:0] is %x (actual %x)", flags == expected_flags, 6794 expected_flags, flags); 6795 if (valid_vmcs) 6796 report("VM-instruction error is %d (actual %d)", 6797 vm_inst_err == VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, 6798 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, vm_inst_err); 6799 } 6800 6801 static void vmentry_movss_shadow_test(void) 6802 { 6803 struct vmcs *orig_vmcs; 6804 6805 TEST_ASSERT(!vmcs_save(&orig_vmcs)); 6806 6807 /* 6808 * Set the launched flag on the current VMCS to verify the correct 6809 * error priority, below. 6810 */ 6811 test_set_guest(v2_null_test_guest); 6812 enter_guest(); 6813 6814 /* 6815 * With bit 1 of the guest's RFLAGS clear, VM-entry should 6816 * fail due to invalid guest state (if we make it that far). 6817 */ 6818 vmcs_write(GUEST_RFLAGS, 0); 6819 6820 /* 6821 * "VM entry with events blocked by MOV SS" takes precedence over 6822 * "VMLAUNCH with non-clear VMCS." 6823 */ 6824 report_prefix_push("valid current-VMCS"); 6825 try_vmentry_in_movss_shadow(); 6826 report_prefix_pop(); 6827 6828 /* 6829 * VMfailInvalid takes precedence over "VM entry with events 6830 * blocked by MOV SS." 6831 */ 6832 TEST_ASSERT(!vmcs_clear(orig_vmcs)); 6833 report_prefix_push("no current-VMCS"); 6834 try_vmentry_in_movss_shadow(); 6835 report_prefix_pop(); 6836 6837 TEST_ASSERT(!make_vmcs_current(orig_vmcs)); 6838 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 6839 } 6840 6841 #define X86_FEATURE_PCID (1 << 17) 6842 #define X86_FEATURE_MCE (1 << 7) 6843 6844 static int write_cr4_checking(unsigned long val) 6845 { 6846 asm volatile(ASM_TRY("1f") 6847 "mov %0, %%cr4\n\t" 6848 "1:": : "r" (val)); 6849 return exception_vector(); 6850 } 6851 6852 static void vmx_cr_load_test(void) 6853 { 6854 struct cpuid _cpuid = cpuid(1); 6855 unsigned long cr4 = read_cr4(), cr3 = read_cr3(); 6856 6857 if (!(_cpuid.c & X86_FEATURE_PCID)) { 6858 report_skip("PCID not detected"); 6859 return; 6860 } 6861 if (!(_cpuid.d & X86_FEATURE_MCE)) { 6862 report_skip("MCE not detected"); 6863 return; 6864 } 6865 6866 TEST_ASSERT(!(cr4 & (X86_CR4_PCIDE | X86_CR4_MCE))); 6867 TEST_ASSERT(!(cr3 & X86_CR3_PCID_MASK)); 6868 6869 /* Enable PCID for L1. */ 6870 cr4 |= X86_CR4_PCIDE; 6871 cr3 |= 0x1; 6872 TEST_ASSERT(!write_cr4_checking(cr4)); 6873 write_cr3(cr3); 6874 6875 test_set_guest(v2_null_test_guest); 6876 vmcs_write(HOST_CR4, cr4); 6877 vmcs_write(HOST_CR3, cr3); 6878 enter_guest(); 6879 6880 /* 6881 * No exception is expected. 6882 * 6883 * NB. KVM loads the last guest write to CR4 into CR4 read 6884 * shadow. In order to trigger an exit to KVM, we can set a 6885 * bit that was zero in the above CR4 write and is owned by 6886 * KVM. We choose to set CR4.MCE, which shall have no side 6887 * effect because normally no guest MCE (e.g., as the result 6888 * of bad memory) would happen during this test. 6889 */ 6890 TEST_ASSERT(!write_cr4_checking(cr4 | X86_CR4_MCE)); 6891 6892 /* Cleanup L1 state: disable PCID. */ 6893 write_cr3(cr3 & ~X86_CR3_PCID_MASK); 6894 TEST_ASSERT(!write_cr4_checking(cr4 & ~X86_CR4_PCIDE)); 6895 } 6896 6897 static void vmx_nm_test_guest(void) 6898 { 6899 write_cr0(read_cr0() | X86_CR0_TS); 6900 asm volatile("fnop"); 6901 } 6902 6903 static void check_nm_exit(const char *test) 6904 { 6905 u32 reason = vmcs_read(EXI_REASON); 6906 u32 intr_info = vmcs_read(EXI_INTR_INFO); 6907 const u32 expected = INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 6908 NM_VECTOR; 6909 6910 report("%s", reason == VMX_EXC_NMI && intr_info == expected, test); 6911 } 6912 6913 /* 6914 * This test checks that: 6915 * 6916 * (a) If L2 launches with CR0.TS clear, but later sets CR0.TS, then 6917 * a subsequent #NM VM-exit is reflected to L1. 6918 * 6919 * (b) If L2 launches with CR0.TS clear and CR0.EM set, then a 6920 * subsequent #NM VM-exit is reflected to L1. 6921 */ 6922 static void vmx_nm_test(void) 6923 { 6924 unsigned long cr0 = read_cr0(); 6925 6926 test_set_guest(vmx_nm_test_guest); 6927 6928 /* 6929 * L1 wants to intercept #NM exceptions encountered in L2. 6930 */ 6931 vmcs_write(EXC_BITMAP, 1 << NM_VECTOR); 6932 6933 /* 6934 * Launch L2 with CR0.TS clear, but don't claim host ownership of 6935 * any CR0 bits. L2 will set CR0.TS and then try to execute fnop, 6936 * which will raise #NM. L0 should reflect the #NM VM-exit to L1. 6937 */ 6938 vmcs_write(CR0_MASK, 0); 6939 vmcs_write(GUEST_CR0, cr0 & ~X86_CR0_TS); 6940 enter_guest(); 6941 check_nm_exit("fnop with CR0.TS set in L2 triggers #NM VM-exit to L1"); 6942 6943 /* 6944 * Re-enter L2 at the fnop instruction, with CR0.TS clear but 6945 * CR0.EM set. The fnop will still raise #NM, and L0 should 6946 * reflect the #NM VM-exit to L1. 6947 */ 6948 vmcs_write(GUEST_CR0, (cr0 & ~X86_CR0_TS) | X86_CR0_EM); 6949 enter_guest(); 6950 check_nm_exit("fnop with CR0.EM set in L2 triggers #NM VM-exit to L1"); 6951 6952 /* 6953 * Re-enter L2 at the fnop instruction, with both CR0.TS and 6954 * CR0.EM clear. There will be no #NM, and the L2 guest should 6955 * exit normally. 6956 */ 6957 vmcs_write(GUEST_CR0, cr0 & ~(X86_CR0_TS | X86_CR0_EM)); 6958 enter_guest(); 6959 } 6960 6961 bool vmx_pending_event_ipi_fired; 6962 static void vmx_pending_event_ipi_isr(isr_regs_t *regs) 6963 { 6964 vmx_pending_event_ipi_fired = true; 6965 eoi(); 6966 } 6967 6968 bool vmx_pending_event_guest_run; 6969 static void vmx_pending_event_guest(void) 6970 { 6971 vmcall(); 6972 vmx_pending_event_guest_run = true; 6973 } 6974 6975 static void vmx_pending_event_test_core(bool guest_hlt) 6976 { 6977 int ipi_vector = 0xf1; 6978 6979 vmx_pending_event_ipi_fired = false; 6980 handle_irq(ipi_vector, vmx_pending_event_ipi_isr); 6981 6982 vmx_pending_event_guest_run = false; 6983 test_set_guest(vmx_pending_event_guest); 6984 6985 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 6986 6987 enter_guest(); 6988 skip_exit_vmcall(); 6989 6990 if (guest_hlt) 6991 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 6992 6993 irq_disable(); 6994 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | 6995 APIC_DM_FIXED | ipi_vector, 6996 0); 6997 6998 enter_guest(); 6999 7000 assert_exit_reason(VMX_EXTINT); 7001 report("Guest did not run before host received IPI", 7002 !vmx_pending_event_guest_run); 7003 7004 irq_enable(); 7005 asm volatile ("nop"); 7006 irq_disable(); 7007 report("Got pending interrupt after IRQ enabled", 7008 vmx_pending_event_ipi_fired); 7009 7010 if (guest_hlt) 7011 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 7012 7013 enter_guest(); 7014 report("Guest finished running when no interrupt", 7015 vmx_pending_event_guest_run); 7016 } 7017 7018 static void vmx_pending_event_test(void) 7019 { 7020 vmx_pending_event_test_core(false); 7021 } 7022 7023 static void vmx_pending_event_hlt_test(void) 7024 { 7025 vmx_pending_event_test_core(true); 7026 } 7027 7028 static int vmx_window_test_ud_count; 7029 7030 static void vmx_window_test_ud_handler(struct ex_regs *regs) 7031 { 7032 vmx_window_test_ud_count++; 7033 } 7034 7035 static void vmx_nmi_window_test_guest(void) 7036 { 7037 handle_exception(UD_VECTOR, vmx_window_test_ud_handler); 7038 7039 asm volatile("vmcall\n\t" 7040 "nop\n\t"); 7041 7042 handle_exception(UD_VECTOR, NULL); 7043 } 7044 7045 static void verify_nmi_window_exit(u64 rip) 7046 { 7047 u32 exit_reason = vmcs_read(EXI_REASON); 7048 7049 report("Exit reason (%d) is 'NMI window'", 7050 exit_reason == VMX_NMI_WINDOW, exit_reason); 7051 report("RIP (%#lx) is %#lx", vmcs_read(GUEST_RIP) == rip, 7052 vmcs_read(GUEST_RIP), rip); 7053 report("Activity state (%ld) is 'ACTIVE'", 7054 vmcs_read(GUEST_ACTV_STATE) == ACTV_ACTIVE, 7055 vmcs_read(GUEST_ACTV_STATE)); 7056 } 7057 7058 static void vmx_nmi_window_test(void) 7059 { 7060 u64 nop_addr; 7061 void *ud_fault_addr = get_idt_addr(&boot_idt[UD_VECTOR]); 7062 7063 if (!(ctrl_pin_rev.clr & PIN_VIRT_NMI)) { 7064 report_skip("CPU does not support the \"Virtual NMIs\" VM-execution control."); 7065 return; 7066 } 7067 7068 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 7069 report_skip("CPU does not support the \"NMI-window exiting\" VM-execution control."); 7070 return; 7071 } 7072 7073 vmx_window_test_ud_count = 0; 7074 7075 report_prefix_push("NMI-window"); 7076 test_set_guest(vmx_nmi_window_test_guest); 7077 vmcs_set_bits(PIN_CONTROLS, PIN_VIRT_NMI); 7078 enter_guest(); 7079 skip_exit_vmcall(); 7080 nop_addr = vmcs_read(GUEST_RIP); 7081 7082 /* 7083 * Ask for "NMI-window exiting," and expect an immediate VM-exit. 7084 * RIP will not advance. 7085 */ 7086 report_prefix_push("active, no blocking"); 7087 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 7088 enter_guest(); 7089 verify_nmi_window_exit(nop_addr); 7090 report_prefix_pop(); 7091 7092 /* 7093 * Ask for "NMI-window exiting" in a MOV-SS shadow, and expect 7094 * a VM-exit on the next instruction after the nop. (The nop 7095 * is one byte.) 7096 */ 7097 report_prefix_push("active, blocking by MOV-SS"); 7098 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 7099 enter_guest(); 7100 verify_nmi_window_exit(nop_addr + 1); 7101 report_prefix_pop(); 7102 7103 /* 7104 * Ask for "NMI-window exiting" (with event injection), and 7105 * expect a VM-exit after the event is injected. (RIP should 7106 * be at the address specified in the IDT entry for #UD.) 7107 */ 7108 report_prefix_push("active, no blocking, injecting #UD"); 7109 vmcs_write(ENT_INTR_INFO, 7110 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | UD_VECTOR); 7111 enter_guest(); 7112 verify_nmi_window_exit((u64)ud_fault_addr); 7113 report_prefix_pop(); 7114 7115 /* 7116 * Ask for "NMI-window exiting" with NMI blocking, and expect 7117 * a VM-exit after the next IRET (i.e. after the #UD handler 7118 * returns). So, RIP should be back at one byte past the nop. 7119 */ 7120 report_prefix_push("active, blocking by NMI"); 7121 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_NMI); 7122 enter_guest(); 7123 verify_nmi_window_exit(nop_addr + 1); 7124 report("#UD handler executed once (actual %d times)", 7125 vmx_window_test_ud_count == 1, 7126 vmx_window_test_ud_count); 7127 report_prefix_pop(); 7128 7129 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 7130 report_skip("CPU does not support activity state HLT."); 7131 } else { 7132 /* 7133 * Ask for "NMI-window exiting" when entering activity 7134 * state HLT, and expect an immediate VM-exit. RIP is 7135 * still one byte past the nop. 7136 */ 7137 report_prefix_push("halted, no blocking"); 7138 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 7139 enter_guest(); 7140 verify_nmi_window_exit(nop_addr + 1); 7141 report_prefix_pop(); 7142 7143 /* 7144 * Ask for "NMI-window exiting" when entering activity 7145 * state HLT (with event injection), and expect a 7146 * VM-exit after the event is injected. (RIP should be 7147 * at the address specified in the IDT entry for #UD.) 7148 */ 7149 report_prefix_push("halted, no blocking, injecting #UD"); 7150 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 7151 vmcs_write(ENT_INTR_INFO, 7152 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 7153 UD_VECTOR); 7154 enter_guest(); 7155 verify_nmi_window_exit((u64)ud_fault_addr); 7156 report_prefix_pop(); 7157 } 7158 7159 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 7160 enter_guest(); 7161 report_prefix_pop(); 7162 } 7163 7164 static void vmx_intr_window_test_guest(void) 7165 { 7166 handle_exception(UD_VECTOR, vmx_window_test_ud_handler); 7167 7168 /* 7169 * The two consecutive STIs are to ensure that only the first 7170 * one has a shadow. Note that NOP and STI are one byte 7171 * instructions. 7172 */ 7173 asm volatile("vmcall\n\t" 7174 "nop\n\t" 7175 "sti\n\t" 7176 "sti\n\t"); 7177 7178 handle_exception(UD_VECTOR, NULL); 7179 } 7180 7181 static void verify_intr_window_exit(u64 rip) 7182 { 7183 u32 exit_reason = vmcs_read(EXI_REASON); 7184 7185 report("Exit reason (%d) is 'interrupt window'", 7186 exit_reason == VMX_INTR_WINDOW, exit_reason); 7187 report("RIP (%#lx) is %#lx", vmcs_read(GUEST_RIP) == rip, 7188 vmcs_read(GUEST_RIP), rip); 7189 report("Activity state (%ld) is 'ACTIVE'", 7190 vmcs_read(GUEST_ACTV_STATE) == ACTV_ACTIVE, 7191 vmcs_read(GUEST_ACTV_STATE)); 7192 } 7193 7194 static void vmx_intr_window_test(void) 7195 { 7196 u64 vmcall_addr; 7197 u64 nop_addr; 7198 unsigned int orig_ud_gate_type; 7199 void *ud_fault_addr = get_idt_addr(&boot_idt[UD_VECTOR]); 7200 7201 if (!(ctrl_cpu_rev[0].clr & CPU_INTR_WINDOW)) { 7202 report_skip("CPU does not support the \"interrupt-window exiting\" VM-execution control."); 7203 return; 7204 } 7205 7206 /* 7207 * Change the IDT entry for #UD from interrupt gate to trap gate, 7208 * so that it won't clear RFLAGS.IF. We don't want interrupts to 7209 * be disabled after vectoring a #UD. 7210 */ 7211 orig_ud_gate_type = boot_idt[UD_VECTOR].type; 7212 boot_idt[UD_VECTOR].type = 15; 7213 7214 report_prefix_push("interrupt-window"); 7215 test_set_guest(vmx_intr_window_test_guest); 7216 enter_guest(); 7217 assert_exit_reason(VMX_VMCALL); 7218 vmcall_addr = vmcs_read(GUEST_RIP); 7219 7220 /* 7221 * Ask for "interrupt-window exiting" with RFLAGS.IF set and 7222 * no blocking; expect an immediate VM-exit. Note that we have 7223 * not advanced past the vmcall instruction yet, so RIP should 7224 * point to the vmcall instruction. 7225 */ 7226 report_prefix_push("active, no blocking, RFLAGS.IF=1"); 7227 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 7228 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_IF); 7229 enter_guest(); 7230 verify_intr_window_exit(vmcall_addr); 7231 report_prefix_pop(); 7232 7233 /* 7234 * Ask for "interrupt-window exiting" (with event injection) 7235 * with RFLAGS.IF set and no blocking; expect a VM-exit after 7236 * the event is injected. That is, RIP should should be at the 7237 * address specified in the IDT entry for #UD. 7238 */ 7239 report_prefix_push("active, no blocking, RFLAGS.IF=1, injecting #UD"); 7240 vmcs_write(ENT_INTR_INFO, 7241 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | UD_VECTOR); 7242 vmcall_addr = vmcs_read(GUEST_RIP); 7243 enter_guest(); 7244 verify_intr_window_exit((u64)ud_fault_addr); 7245 report_prefix_pop(); 7246 7247 /* 7248 * Let the L2 guest run through the IRET, back to the VMCALL. 7249 * We have to clear the "interrupt-window exiting" 7250 * VM-execution control, or it would just keep causing 7251 * VM-exits. Then, advance past the VMCALL and set the 7252 * "interrupt-window exiting" VM-execution control again. 7253 */ 7254 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 7255 enter_guest(); 7256 skip_exit_vmcall(); 7257 nop_addr = vmcs_read(GUEST_RIP); 7258 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 7259 7260 /* 7261 * Ask for "interrupt-window exiting" in a MOV-SS shadow with 7262 * RFLAGS.IF set, and expect a VM-exit on the next 7263 * instruction. (NOP is one byte.) 7264 */ 7265 report_prefix_push("active, blocking by MOV-SS, RFLAGS.IF=1"); 7266 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 7267 enter_guest(); 7268 verify_intr_window_exit(nop_addr + 1); 7269 report_prefix_pop(); 7270 7271 /* 7272 * Back up to the NOP and ask for "interrupt-window exiting" 7273 * in an STI shadow with RFLAGS.IF set, and expect a VM-exit 7274 * on the next instruction. (NOP is one byte.) 7275 */ 7276 report_prefix_push("active, blocking by STI, RFLAGS.IF=1"); 7277 vmcs_write(GUEST_RIP, nop_addr); 7278 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_STI); 7279 enter_guest(); 7280 verify_intr_window_exit(nop_addr + 1); 7281 report_prefix_pop(); 7282 7283 /* 7284 * Ask for "interrupt-window exiting" with RFLAGS.IF clear, 7285 * and expect a VM-exit on the instruction following the STI 7286 * shadow. Only the first STI (which is one byte past the NOP) 7287 * should have a shadow. The second STI (which is two bytes 7288 * past the NOP) has no shadow. Therefore, the interrupt 7289 * window opens at three bytes past the NOP. 7290 */ 7291 report_prefix_push("active, RFLAGS.IF = 0"); 7292 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 7293 enter_guest(); 7294 verify_intr_window_exit(nop_addr + 3); 7295 report_prefix_pop(); 7296 7297 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 7298 report_skip("CPU does not support activity state HLT."); 7299 } else { 7300 /* 7301 * Ask for "interrupt-window exiting" when entering 7302 * activity state HLT, and expect an immediate 7303 * VM-exit. RIP is still three bytes past the nop. 7304 */ 7305 report_prefix_push("halted, no blocking"); 7306 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 7307 enter_guest(); 7308 verify_intr_window_exit(nop_addr + 3); 7309 report_prefix_pop(); 7310 7311 /* 7312 * Ask for "interrupt-window exiting" when entering 7313 * activity state HLT (with event injection), and 7314 * expect a VM-exit after the event is injected. That 7315 * is, RIP should should be at the address specified 7316 * in the IDT entry for #UD. 7317 */ 7318 report_prefix_push("halted, no blocking, injecting #UD"); 7319 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 7320 vmcs_write(ENT_INTR_INFO, 7321 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 7322 UD_VECTOR); 7323 enter_guest(); 7324 verify_intr_window_exit((u64)ud_fault_addr); 7325 report_prefix_pop(); 7326 } 7327 7328 boot_idt[UD_VECTOR].type = orig_ud_gate_type; 7329 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 7330 enter_guest(); 7331 report_prefix_pop(); 7332 } 7333 7334 #define GUEST_TSC_OFFSET (1u << 30) 7335 7336 static u64 guest_tsc; 7337 7338 static void vmx_store_tsc_test_guest(void) 7339 { 7340 guest_tsc = rdtsc(); 7341 } 7342 7343 /* 7344 * This test ensures that when IA32_TSC is in the VM-exit MSR-store 7345 * list, the value saved is not subject to the TSC offset that is 7346 * applied to RDTSC/RDTSCP/RDMSR(IA32_TSC) in guest execution. 7347 */ 7348 static void vmx_store_tsc_test(void) 7349 { 7350 struct vmx_msr_entry msr_entry = { .index = MSR_IA32_TSC }; 7351 u64 low, high; 7352 7353 if (!(ctrl_cpu_rev[0].clr & CPU_USE_TSC_OFFSET)) { 7354 report_skip("'Use TSC offsetting' not supported"); 7355 return; 7356 } 7357 7358 test_set_guest(vmx_store_tsc_test_guest); 7359 7360 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_USE_TSC_OFFSET); 7361 vmcs_write(EXI_MSR_ST_CNT, 1); 7362 vmcs_write(EXIT_MSR_ST_ADDR, virt_to_phys(&msr_entry)); 7363 vmcs_write(TSC_OFFSET, GUEST_TSC_OFFSET); 7364 7365 low = rdtsc(); 7366 enter_guest(); 7367 high = rdtsc(); 7368 7369 report("RDTSC value in the guest (%lu) is in range [%lu, %lu]", 7370 low + GUEST_TSC_OFFSET <= guest_tsc && 7371 guest_tsc <= high + GUEST_TSC_OFFSET, 7372 guest_tsc, low + GUEST_TSC_OFFSET, high + GUEST_TSC_OFFSET); 7373 report("IA32_TSC value saved in the VM-exit MSR-store list (%lu) is in range [%lu, %lu]", 7374 low <= msr_entry.value && msr_entry.value <= high, 7375 msr_entry.value, low, high); 7376 } 7377 7378 static void vmx_db_test_guest(void) 7379 { 7380 /* 7381 * For a hardware generated single-step #DB. 7382 */ 7383 asm volatile("vmcall;" 7384 "nop;" 7385 ".Lpost_nop:"); 7386 /* 7387 * ...in a MOVSS shadow, with pending debug exceptions. 7388 */ 7389 asm volatile("vmcall;" 7390 "nop;" 7391 ".Lpost_movss_nop:"); 7392 /* 7393 * For an L0 synthesized single-step #DB. (L0 intercepts WBINVD and 7394 * emulates it in software.) 7395 */ 7396 asm volatile("vmcall;" 7397 "wbinvd;" 7398 ".Lpost_wbinvd:"); 7399 /* 7400 * ...in a MOVSS shadow, with pending debug exceptions. 7401 */ 7402 asm volatile("vmcall;" 7403 "wbinvd;" 7404 ".Lpost_movss_wbinvd:"); 7405 /* 7406 * For a hardware generated single-step #DB in a transactional region. 7407 */ 7408 asm volatile("vmcall;" 7409 ".Lxbegin: xbegin .Lskip_rtm;" 7410 "xend;" 7411 ".Lskip_rtm:"); 7412 } 7413 7414 /* 7415 * Clear the pending debug exceptions and RFLAGS.TF and re-enter 7416 * L2. No #DB is delivered and L2 continues to the next point of 7417 * interest. 7418 */ 7419 static void dismiss_db(void) 7420 { 7421 vmcs_write(GUEST_PENDING_DEBUG, 0); 7422 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 7423 enter_guest(); 7424 } 7425 7426 /* 7427 * Check a variety of VMCS fields relevant to an intercepted #DB exception. 7428 * Then throw away the #DB exception and resume L2. 7429 */ 7430 static void check_db_exit(bool xfail_qual, bool xfail_dr6, bool xfail_pdbg, 7431 void *expected_rip, u64 expected_exit_qual, 7432 u64 expected_dr6) 7433 { 7434 u32 reason = vmcs_read(EXI_REASON); 7435 u32 intr_info = vmcs_read(EXI_INTR_INFO); 7436 u64 exit_qual = vmcs_read(EXI_QUALIFICATION); 7437 u64 guest_rip = vmcs_read(GUEST_RIP); 7438 u64 guest_pending_dbg = vmcs_read(GUEST_PENDING_DEBUG); 7439 u64 dr6 = read_dr6(); 7440 const u32 expected_intr_info = INTR_INFO_VALID_MASK | 7441 INTR_TYPE_HARD_EXCEPTION | DB_VECTOR; 7442 7443 report("Expected #DB VM-exit", 7444 reason == VMX_EXC_NMI && intr_info == expected_intr_info); 7445 report("Expected RIP %p (actual %lx)", (u64)expected_rip == guest_rip, 7446 expected_rip, guest_rip); 7447 report_xfail("Expected pending debug exceptions 0 (actual %lx)", 7448 xfail_pdbg, 0 == guest_pending_dbg, guest_pending_dbg); 7449 report_xfail("Expected exit qualification %lx (actual %lx)", xfail_qual, 7450 expected_exit_qual == exit_qual, 7451 expected_exit_qual, exit_qual); 7452 report_xfail("Expected DR6 %lx (actual %lx)", xfail_dr6, 7453 expected_dr6 == dr6, expected_dr6, dr6); 7454 dismiss_db(); 7455 } 7456 7457 /* 7458 * Assuming the guest has just exited on a VMCALL instruction, skip 7459 * over the vmcall, and set the guest's RFLAGS.TF in the VMCS. If 7460 * pending debug exceptions are non-zero, set the VMCS up as if the 7461 * previous instruction was a MOVSS that generated the indicated 7462 * pending debug exceptions. Then enter L2. 7463 */ 7464 static void single_step_guest(const char *test_name, u64 starting_dr6, 7465 u64 pending_debug_exceptions) 7466 { 7467 printf("\n%s\n", test_name); 7468 skip_exit_vmcall(); 7469 write_dr6(starting_dr6); 7470 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_TF); 7471 if (pending_debug_exceptions) { 7472 vmcs_write(GUEST_PENDING_DEBUG, pending_debug_exceptions); 7473 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 7474 } 7475 enter_guest(); 7476 } 7477 7478 /* 7479 * When L1 intercepts #DB, verify that a single-step trap clears 7480 * pending debug exceptions, populates the exit qualification field 7481 * properly, and that DR6 is not prematurely clobbered. In a 7482 * (simulated) MOVSS shadow, make sure that the pending debug 7483 * exception bits are properly accumulated into the exit qualification 7484 * field. 7485 */ 7486 static void vmx_db_test(void) 7487 { 7488 /* 7489 * We are going to set a few arbitrary bits in DR6 to verify that 7490 * (a) DR6 is not modified by an intercepted #DB, and 7491 * (b) stale bits in DR6 (DR6.BD, in particular) don't leak into 7492 * the exit qualification field for a subsequent #DB exception. 7493 */ 7494 const u64 starting_dr6 = DR6_RESERVED | BIT(13) | DR_TRAP3 | DR_TRAP1; 7495 extern char post_nop asm(".Lpost_nop"); 7496 extern char post_movss_nop asm(".Lpost_movss_nop"); 7497 extern char post_wbinvd asm(".Lpost_wbinvd"); 7498 extern char post_movss_wbinvd asm(".Lpost_movss_wbinvd"); 7499 extern char xbegin asm(".Lxbegin"); 7500 extern char skip_rtm asm(".Lskip_rtm"); 7501 7502 /* 7503 * L1 wants to intercept #DB exceptions encountered in L2. 7504 */ 7505 vmcs_write(EXC_BITMAP, BIT(DB_VECTOR)); 7506 7507 /* 7508 * Start L2 and run it up to the first point of interest. 7509 */ 7510 test_set_guest(vmx_db_test_guest); 7511 enter_guest(); 7512 7513 /* 7514 * Hardware-delivered #DB trap for single-step sets the 7515 * standard that L0 has to follow for emulated instructions. 7516 */ 7517 single_step_guest("Hardware delivered single-step", starting_dr6, 0); 7518 check_db_exit(false, false, false, &post_nop, DR_STEP, starting_dr6); 7519 7520 /* 7521 * Hardware-delivered #DB trap for single-step in MOVSS shadow 7522 * also sets the standard that L0 has to follow for emulated 7523 * instructions. Here, we establish the VMCS pending debug 7524 * exceptions to indicate that the simulated MOVSS triggered a 7525 * data breakpoint as well as the single-step trap. 7526 */ 7527 single_step_guest("Hardware delivered single-step in MOVSS shadow", 7528 starting_dr6, BIT(12) | DR_STEP | DR_TRAP0 ); 7529 check_db_exit(false, false, false, &post_movss_nop, DR_STEP | DR_TRAP0, 7530 starting_dr6); 7531 7532 /* 7533 * L0 synthesized #DB trap for single-step is buggy, because 7534 * kvm (a) clobbers DR6 too early, and (b) tries its best to 7535 * reconstitute the exit qualification from the prematurely 7536 * modified DR6, but fails miserably. 7537 */ 7538 single_step_guest("Software synthesized single-step", starting_dr6, 0); 7539 check_db_exit(true, true, false, &post_wbinvd, DR_STEP, starting_dr6); 7540 7541 /* 7542 * L0 synthesized #DB trap for single-step in MOVSS shadow is 7543 * even worse, because L0 also leaves the pending debug 7544 * exceptions in the VMCS instead of accumulating them into 7545 * the exit qualification field for the #DB exception. 7546 */ 7547 single_step_guest("Software synthesized single-step in MOVSS shadow", 7548 starting_dr6, BIT(12) | DR_STEP | DR_TRAP0); 7549 check_db_exit(true, true, true, &post_movss_wbinvd, DR_STEP | DR_TRAP0, 7550 starting_dr6); 7551 7552 /* 7553 * Optional RTM test for hardware that supports RTM, to 7554 * demonstrate that the current volume 3 of the SDM 7555 * (325384-067US), table 27-1 is incorrect. Bit 16 of the exit 7556 * qualification for debug exceptions is not reserved. It is 7557 * set to 1 if a debug exception (#DB) or a breakpoint 7558 * exception (#BP) occurs inside an RTM region while advanced 7559 * debugging of RTM transactional regions is enabled. 7560 */ 7561 if (cpuid(7).b & BIT(11)) { 7562 vmcs_write(ENT_CONTROLS, 7563 vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 7564 /* 7565 * Set DR7.RTM[bit 11] and IA32_DEBUGCTL.RTM[bit 15] 7566 * in the guest to enable advanced debugging of RTM 7567 * transactional regions. 7568 */ 7569 vmcs_write(GUEST_DR7, BIT(11)); 7570 vmcs_write(GUEST_DEBUGCTL, BIT(15)); 7571 single_step_guest("Hardware delivered single-step in " 7572 "transactional region", starting_dr6, 0); 7573 check_db_exit(false, false, false, &xbegin, BIT(16), 7574 starting_dr6); 7575 } else { 7576 vmcs_write(GUEST_RIP, (u64)&skip_rtm); 7577 enter_guest(); 7578 } 7579 } 7580 7581 static void enable_vid(void) 7582 { 7583 void *virtual_apic_page; 7584 7585 assert(cpu_has_apicv()); 7586 7587 disable_intercept_for_x2apic_msrs(); 7588 7589 virtual_apic_page = alloc_page(); 7590 vmcs_write(APIC_VIRT_ADDR, (u64)virtual_apic_page); 7591 7592 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 7593 7594 vmcs_write(EOI_EXIT_BITMAP0, 0x0); 7595 vmcs_write(EOI_EXIT_BITMAP1, 0x0); 7596 vmcs_write(EOI_EXIT_BITMAP2, 0x0); 7597 vmcs_write(EOI_EXIT_BITMAP3, 0x0); 7598 7599 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY | CPU_TPR_SHADOW); 7600 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_VINTD | CPU_VIRT_X2APIC); 7601 } 7602 7603 static void trigger_ioapic_scan_thread(void *data) 7604 { 7605 /* Wait until other CPU entered L2 */ 7606 while (vmx_get_test_stage() != 1) 7607 ; 7608 7609 /* Trigger ioapic scan */ 7610 ioapic_set_redir(0xf, 0x79, TRIGGER_LEVEL); 7611 vmx_set_test_stage(2); 7612 } 7613 7614 static void irq_79_handler_guest(isr_regs_t *regs) 7615 { 7616 eoi(); 7617 7618 /* L1 expects vmexit on VMX_VMCALL and not VMX_EOI_INDUCED */ 7619 vmcall(); 7620 } 7621 7622 /* 7623 * Constant for num of busy-loop iterations after which 7624 * a timer interrupt should have happened in host 7625 */ 7626 #define TIMER_INTERRUPT_DELAY 100000000 7627 7628 static void vmx_eoi_bitmap_ioapic_scan_test_guest(void) 7629 { 7630 handle_irq(0x79, irq_79_handler_guest); 7631 irq_enable(); 7632 7633 /* Signal to L1 CPU to trigger ioapic scan */ 7634 vmx_set_test_stage(1); 7635 /* Wait until L1 CPU to trigger ioapic scan */ 7636 while (vmx_get_test_stage() != 2) 7637 ; 7638 7639 /* 7640 * Wait for L0 timer interrupt to be raised while we run in L2 7641 * such that L0 will process the IOAPIC scan request before 7642 * resuming L2 7643 */ 7644 delay(TIMER_INTERRUPT_DELAY); 7645 7646 asm volatile ("int $0x79"); 7647 } 7648 7649 static void vmx_eoi_bitmap_ioapic_scan_test(void) 7650 { 7651 if (!cpu_has_apicv() || (cpu_count() < 2)) { 7652 report_skip(__func__); 7653 return; 7654 } 7655 7656 enable_vid(); 7657 7658 on_cpu_async(1, trigger_ioapic_scan_thread, NULL); 7659 test_set_guest(vmx_eoi_bitmap_ioapic_scan_test_guest); 7660 7661 /* 7662 * Launch L2. 7663 * We expect the exit reason to be VMX_VMCALL (and not EOI INDUCED). 7664 * In case the reason isn't VMX_VMCALL, the asserion inside 7665 * skip_exit_vmcall() will fail. 7666 */ 7667 enter_guest(); 7668 skip_exit_vmcall(); 7669 7670 /* Let L2 finish */ 7671 enter_guest(); 7672 report(__func__, 1); 7673 } 7674 7675 #define HLT_WITH_RVI_VECTOR (0xf1) 7676 7677 bool vmx_hlt_with_rvi_guest_isr_fired; 7678 static void vmx_hlt_with_rvi_guest_isr(isr_regs_t *regs) 7679 { 7680 vmx_hlt_with_rvi_guest_isr_fired = true; 7681 eoi(); 7682 } 7683 7684 static void vmx_hlt_with_rvi_guest(void) 7685 { 7686 handle_irq(HLT_WITH_RVI_VECTOR, vmx_hlt_with_rvi_guest_isr); 7687 7688 irq_enable(); 7689 asm volatile ("nop"); 7690 7691 vmcall(); 7692 } 7693 7694 static void vmx_hlt_with_rvi_test(void) 7695 { 7696 if (!cpu_has_apicv()) { 7697 report_skip(__func__); 7698 return; 7699 } 7700 7701 enable_vid(); 7702 7703 vmx_hlt_with_rvi_guest_isr_fired = false; 7704 test_set_guest(vmx_hlt_with_rvi_guest); 7705 7706 enter_guest(); 7707 skip_exit_vmcall(); 7708 7709 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 7710 vmcs_write(GUEST_INT_STATUS, HLT_WITH_RVI_VECTOR); 7711 enter_guest(); 7712 7713 report("Interrupt raised in guest", vmx_hlt_with_rvi_guest_isr_fired); 7714 } 7715 7716 static void set_irq_line_thread(void *data) 7717 { 7718 /* Wait until other CPU entered L2 */ 7719 while (vmx_get_test_stage() != 1) 7720 ; 7721 7722 /* Set irq-line 0xf to raise vector 0x78 for vCPU 0 */ 7723 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 7724 vmx_set_test_stage(2); 7725 } 7726 7727 static bool irq_78_handler_vmcall_before_eoi; 7728 static void irq_78_handler_guest(isr_regs_t *regs) 7729 { 7730 set_irq_line(0xf, 0); 7731 if (irq_78_handler_vmcall_before_eoi) 7732 vmcall(); 7733 eoi(); 7734 vmcall(); 7735 } 7736 7737 static void vmx_apic_passthrough_guest(void) 7738 { 7739 handle_irq(0x78, irq_78_handler_guest); 7740 irq_enable(); 7741 7742 /* If requested, wait for other CPU to trigger ioapic scan */ 7743 if (vmx_get_test_stage() < 1) { 7744 vmx_set_test_stage(1); 7745 while (vmx_get_test_stage() != 2) 7746 ; 7747 } 7748 7749 set_irq_line(0xf, 1); 7750 } 7751 7752 static void vmx_apic_passthrough(bool set_irq_line_from_thread) 7753 { 7754 if (set_irq_line_from_thread && (cpu_count() < 2)) { 7755 report_skip(__func__); 7756 return; 7757 } 7758 7759 u64 cpu_ctrl_0 = CPU_SECONDARY; 7760 u64 cpu_ctrl_1 = 0; 7761 7762 disable_intercept_for_x2apic_msrs(); 7763 7764 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 7765 7766 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 7767 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 7768 7769 if (set_irq_line_from_thread) { 7770 irq_78_handler_vmcall_before_eoi = false; 7771 on_cpu_async(1, set_irq_line_thread, NULL); 7772 } else { 7773 irq_78_handler_vmcall_before_eoi = true; 7774 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 7775 vmx_set_test_stage(2); 7776 } 7777 test_set_guest(vmx_apic_passthrough_guest); 7778 7779 if (irq_78_handler_vmcall_before_eoi) { 7780 /* Before EOI remote_irr should still be set */ 7781 enter_guest(); 7782 skip_exit_vmcall(); 7783 TEST_ASSERT_EQ_MSG(1, (int)ioapic_read_redir(0xf).remote_irr, 7784 "IOAPIC pass-through: remote_irr=1 before EOI"); 7785 } 7786 7787 /* After EOI remote_irr should be cleared */ 7788 enter_guest(); 7789 skip_exit_vmcall(); 7790 TEST_ASSERT_EQ_MSG(0, (int)ioapic_read_redir(0xf).remote_irr, 7791 "IOAPIC pass-through: remote_irr=0 after EOI"); 7792 7793 /* Let L2 finish */ 7794 enter_guest(); 7795 report(__func__, 1); 7796 } 7797 7798 static void vmx_apic_passthrough_test(void) 7799 { 7800 vmx_apic_passthrough(false); 7801 } 7802 7803 static void vmx_apic_passthrough_thread_test(void) 7804 { 7805 vmx_apic_passthrough(true); 7806 } 7807 7808 enum vmcs_access { 7809 ACCESS_VMREAD, 7810 ACCESS_VMWRITE, 7811 ACCESS_NONE, 7812 }; 7813 7814 struct vmcs_shadow_test_common { 7815 enum vmcs_access op; 7816 enum Reason reason; 7817 u64 field; 7818 u64 value; 7819 u64 flags; 7820 u64 time; 7821 } l1_l2_common; 7822 7823 static inline u64 vmread_flags(u64 field, u64 *val) 7824 { 7825 u64 flags; 7826 7827 asm volatile ("vmread %2, %1; pushf; pop %0" 7828 : "=r" (flags), "=rm" (*val) : "r" (field) : "cc"); 7829 return flags & X86_EFLAGS_ALU; 7830 } 7831 7832 static inline u64 vmwrite_flags(u64 field, u64 val) 7833 { 7834 u64 flags; 7835 7836 asm volatile ("vmwrite %1, %2; pushf; pop %0" 7837 : "=r"(flags) : "rm" (val), "r" (field) : "cc"); 7838 return flags & X86_EFLAGS_ALU; 7839 } 7840 7841 static void vmx_vmcs_shadow_test_guest(void) 7842 { 7843 struct vmcs_shadow_test_common *c = &l1_l2_common; 7844 u64 start; 7845 7846 while (c->op != ACCESS_NONE) { 7847 start = rdtsc(); 7848 switch (c->op) { 7849 default: 7850 c->flags = -1ull; 7851 break; 7852 case ACCESS_VMREAD: 7853 c->flags = vmread_flags(c->field, &c->value); 7854 break; 7855 case ACCESS_VMWRITE: 7856 c->flags = vmwrite_flags(c->field, 0); 7857 break; 7858 } 7859 c->time = rdtsc() - start; 7860 vmcall(); 7861 } 7862 } 7863 7864 static u64 vmread_from_shadow(u64 field) 7865 { 7866 struct vmcs *primary; 7867 struct vmcs *shadow; 7868 u64 value; 7869 7870 TEST_ASSERT(!vmcs_save(&primary)); 7871 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 7872 TEST_ASSERT(!make_vmcs_current(shadow)); 7873 value = vmcs_read(field); 7874 TEST_ASSERT(!make_vmcs_current(primary)); 7875 return value; 7876 } 7877 7878 static u64 vmwrite_to_shadow(u64 field, u64 value) 7879 { 7880 struct vmcs *primary; 7881 struct vmcs *shadow; 7882 7883 TEST_ASSERT(!vmcs_save(&primary)); 7884 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 7885 TEST_ASSERT(!make_vmcs_current(shadow)); 7886 vmcs_write(field, value); 7887 value = vmcs_read(field); 7888 TEST_ASSERT(!make_vmcs_current(primary)); 7889 return value; 7890 } 7891 7892 static void vmcs_shadow_test_access(u8 *bitmap[2], enum vmcs_access access) 7893 { 7894 struct vmcs_shadow_test_common *c = &l1_l2_common; 7895 7896 c->op = access; 7897 vmcs_write(VMX_INST_ERROR, 0); 7898 enter_guest(); 7899 c->reason = vmcs_read(EXI_REASON) & 0xffff; 7900 if (c->reason != VMX_VMCALL) { 7901 skip_exit_insn(); 7902 enter_guest(); 7903 } 7904 skip_exit_vmcall(); 7905 } 7906 7907 static void vmcs_shadow_test_field(u8 *bitmap[2], u64 field) 7908 { 7909 struct vmcs_shadow_test_common *c = &l1_l2_common; 7910 struct vmcs *shadow; 7911 u64 value; 7912 uintptr_t flags[2]; 7913 bool good_shadow; 7914 u32 vmx_inst_error; 7915 7916 report_prefix_pushf("field %lx", field); 7917 c->field = field; 7918 7919 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 7920 if (shadow != (struct vmcs *)-1ull) { 7921 flags[ACCESS_VMREAD] = vmread_flags(field, &value); 7922 flags[ACCESS_VMWRITE] = vmwrite_flags(field, value); 7923 good_shadow = !flags[ACCESS_VMREAD] && !flags[ACCESS_VMWRITE]; 7924 } else { 7925 /* 7926 * When VMCS link pointer is -1ull, VMWRITE/VMREAD on 7927 * shadowed-fields should fail with setting RFLAGS.CF. 7928 */ 7929 flags[ACCESS_VMREAD] = X86_EFLAGS_CF; 7930 flags[ACCESS_VMWRITE] = X86_EFLAGS_CF; 7931 good_shadow = false; 7932 } 7933 7934 /* Intercept both VMREAD and VMWRITE. */ 7935 report_prefix_push("no VMREAD/VMWRITE permission"); 7936 /* VMWRITE/VMREAD done on reserved-bit should always intercept */ 7937 if (!(field >> VMCS_FIELD_RESERVED_SHIFT)) { 7938 set_bit(field, bitmap[ACCESS_VMREAD]); 7939 set_bit(field, bitmap[ACCESS_VMWRITE]); 7940 } 7941 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 7942 report("not shadowed for VMWRITE", c->reason == VMX_VMWRITE); 7943 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 7944 report("not shadowed for VMREAD", c->reason == VMX_VMREAD); 7945 report_prefix_pop(); 7946 7947 if (field >> VMCS_FIELD_RESERVED_SHIFT) 7948 goto out; 7949 7950 /* Permit shadowed VMREAD. */ 7951 report_prefix_push("VMREAD permission only"); 7952 clear_bit(field, bitmap[ACCESS_VMREAD]); 7953 set_bit(field, bitmap[ACCESS_VMWRITE]); 7954 if (good_shadow) 7955 value = vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 7956 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 7957 report("not shadowed for VMWRITE", c->reason == VMX_VMWRITE); 7958 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 7959 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 7960 report("shadowed for VMREAD (in %ld cycles)", c->reason == VMX_VMCALL, 7961 c->time); 7962 report("ALU flags after VMREAD (%lx) are as expected (%lx)", 7963 c->flags == flags[ACCESS_VMREAD], 7964 c->flags, flags[ACCESS_VMREAD]); 7965 if (good_shadow) 7966 report("value read from shadow (%lx) is as expected (%lx)", 7967 c->value == value, c->value, value); 7968 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 7969 report("VMX_INST_ERROR (%d) is as expected (%d)", 7970 vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 7971 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 7972 report_prefix_pop(); 7973 7974 /* Permit shadowed VMWRITE. */ 7975 report_prefix_push("VMWRITE permission only"); 7976 set_bit(field, bitmap[ACCESS_VMREAD]); 7977 clear_bit(field, bitmap[ACCESS_VMWRITE]); 7978 if (good_shadow) 7979 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 7980 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 7981 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 7982 report("shadowed for VMWRITE (in %ld cycles)", c->reason == VMX_VMCALL, 7983 c->time); 7984 report("ALU flags after VMWRITE (%lx) are as expected (%lx)", 7985 c->flags == flags[ACCESS_VMREAD], 7986 c->flags, flags[ACCESS_VMREAD]); 7987 if (good_shadow) { 7988 value = vmread_from_shadow(field); 7989 report("shadow VMCS value (%lx) is as expected (%lx)", 7990 value == 0, value, 0ul); 7991 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 7992 report("VMX_INST_ERROR (%d) is as expected (%d)", 7993 vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 7994 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 7995 } 7996 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 7997 report("not shadowed for VMREAD", c->reason == VMX_VMREAD); 7998 report_prefix_pop(); 7999 8000 /* Permit shadowed VMREAD and VMWRITE. */ 8001 report_prefix_push("VMREAD and VMWRITE permission"); 8002 clear_bit(field, bitmap[ACCESS_VMREAD]); 8003 clear_bit(field, bitmap[ACCESS_VMWRITE]); 8004 if (good_shadow) 8005 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 8006 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 8007 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 8008 report("shadowed for VMWRITE (in %ld cycles)", c->reason == VMX_VMCALL, 8009 c->time); 8010 report("ALU flags after VMWRITE (%lx) are as expected (%lx)", 8011 c->flags == flags[ACCESS_VMREAD], 8012 c->flags, flags[ACCESS_VMREAD]); 8013 if (good_shadow) { 8014 value = vmread_from_shadow(field); 8015 report("shadow VMCS value (%lx) is as expected (%lx)", 8016 value == 0, value, 0ul); 8017 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 8018 report("VMX_INST_ERROR (%d) is as expected (%d)", 8019 vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 8020 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 8021 } 8022 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 8023 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 8024 report("shadowed for VMREAD (in %ld cycles)", c->reason == VMX_VMCALL, 8025 c->time); 8026 report("ALU flags after VMREAD (%lx) are as expected (%lx)", 8027 c->flags == flags[ACCESS_VMREAD], 8028 c->flags, flags[ACCESS_VMREAD]); 8029 if (good_shadow) 8030 report("value read from shadow (%lx) is as expected (%lx)", 8031 c->value == 0, c->value, 0ul); 8032 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 8033 report("VMX_INST_ERROR (%d) is as expected (%d)", 8034 vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 8035 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 8036 report_prefix_pop(); 8037 8038 out: 8039 report_prefix_pop(); 8040 } 8041 8042 static void vmx_vmcs_shadow_test_body(u8 *bitmap[2]) 8043 { 8044 unsigned base; 8045 unsigned index; 8046 unsigned bit; 8047 unsigned highest_index = rdmsr(MSR_IA32_VMX_VMCS_ENUM); 8048 8049 /* Run test on all possible valid VMCS fields */ 8050 for (base = 0; 8051 base < (1 << VMCS_FIELD_RESERVED_SHIFT); 8052 base += (1 << VMCS_FIELD_TYPE_SHIFT)) 8053 for (index = 0; index <= highest_index; index++) 8054 vmcs_shadow_test_field(bitmap, base + index); 8055 8056 /* 8057 * Run tests on some invalid VMCS fields 8058 * (Have reserved bit set). 8059 */ 8060 for (bit = VMCS_FIELD_RESERVED_SHIFT; bit < VMCS_FIELD_BIT_SIZE; bit++) 8061 vmcs_shadow_test_field(bitmap, (1ull << bit)); 8062 } 8063 8064 static void vmx_vmcs_shadow_test(void) 8065 { 8066 u8 *bitmap[2]; 8067 struct vmcs *shadow; 8068 8069 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 8070 printf("\t'Activate secondary controls' not supported.\n"); 8071 return; 8072 } 8073 8074 if (!(ctrl_cpu_rev[1].clr & CPU_SHADOW_VMCS)) { 8075 printf("\t'VMCS shadowing' not supported.\n"); 8076 return; 8077 } 8078 8079 if (!(rdmsr(MSR_IA32_VMX_MISC) & 8080 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS)) { 8081 printf("\tVMWRITE can't modify VM-exit information fields.\n"); 8082 return; 8083 } 8084 8085 test_set_guest(vmx_vmcs_shadow_test_guest); 8086 8087 bitmap[ACCESS_VMREAD] = alloc_page(); 8088 bitmap[ACCESS_VMWRITE] = alloc_page(); 8089 8090 vmcs_write(VMREAD_BITMAP, virt_to_phys(bitmap[ACCESS_VMREAD])); 8091 vmcs_write(VMWRITE_BITMAP, virt_to_phys(bitmap[ACCESS_VMWRITE])); 8092 8093 shadow = alloc_page(); 8094 shadow->hdr.revision_id = basic.revision; 8095 shadow->hdr.shadow_vmcs = 1; 8096 TEST_ASSERT(!vmcs_clear(shadow)); 8097 8098 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_RDTSC); 8099 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY); 8100 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_SHADOW_VMCS); 8101 8102 vmcs_write(VMCS_LINK_PTR, virt_to_phys(shadow)); 8103 report_prefix_push("valid link pointer"); 8104 vmx_vmcs_shadow_test_body(bitmap); 8105 report_prefix_pop(); 8106 8107 vmcs_write(VMCS_LINK_PTR, -1ull); 8108 report_prefix_push("invalid link pointer"); 8109 vmx_vmcs_shadow_test_body(bitmap); 8110 report_prefix_pop(); 8111 8112 l1_l2_common.op = ACCESS_NONE; 8113 enter_guest(); 8114 } 8115 8116 8117 8118 static int invalid_msr_init(struct vmcs *vmcs) 8119 { 8120 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 8121 printf("\tPreemption timer is not supported\n"); 8122 return VMX_TEST_EXIT; 8123 } 8124 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 8125 preempt_val = 10000000; 8126 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 8127 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 8128 8129 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 8130 printf("\tSave preemption value is not supported\n"); 8131 8132 vmcs_write(ENT_MSR_LD_CNT, 1); 8133 vmcs_write(ENTER_MSR_LD_ADDR, (u64)0x13370000); 8134 8135 return VMX_TEST_START; 8136 } 8137 8138 8139 static void invalid_msr_main(void) 8140 { 8141 report("Invalid MSR load", 0); 8142 } 8143 8144 static int invalid_msr_exit_handler(void) 8145 { 8146 report("Invalid MSR load", 0); 8147 print_vmexit_info(); 8148 return VMX_TEST_EXIT; 8149 } 8150 8151 static int invalid_msr_entry_failure(struct vmentry_failure *failure) 8152 { 8153 ulong reason; 8154 8155 reason = vmcs_read(EXI_REASON); 8156 report("Invalid MSR load", reason == (0x80000000u | VMX_FAIL_MSR)); 8157 return VMX_TEST_VMEXIT; 8158 } 8159 8160 8161 #define TEST(name) { #name, .v2 = name } 8162 8163 /* name/init/guest_main/exit_handler/syscall_handler/guest_regs */ 8164 struct vmx_test vmx_tests[] = { 8165 { "null", NULL, basic_guest_main, basic_exit_handler, NULL, {0} }, 8166 { "vmenter", NULL, vmenter_main, vmenter_exit_handler, NULL, {0} }, 8167 { "preemption timer", preemption_timer_init, preemption_timer_main, 8168 preemption_timer_exit_handler, NULL, {0} }, 8169 { "control field PAT", test_ctrl_pat_init, test_ctrl_pat_main, 8170 test_ctrl_pat_exit_handler, NULL, {0} }, 8171 { "control field EFER", test_ctrl_efer_init, test_ctrl_efer_main, 8172 test_ctrl_efer_exit_handler, NULL, {0} }, 8173 { "CR shadowing", NULL, cr_shadowing_main, 8174 cr_shadowing_exit_handler, NULL, {0} }, 8175 { "I/O bitmap", iobmp_init, iobmp_main, iobmp_exit_handler, 8176 NULL, {0} }, 8177 { "instruction intercept", insn_intercept_init, insn_intercept_main, 8178 insn_intercept_exit_handler, NULL, {0} }, 8179 { "EPT A/D disabled", ept_init, ept_main, ept_exit_handler, NULL, {0} }, 8180 { "EPT A/D enabled", eptad_init, eptad_main, eptad_exit_handler, NULL, {0} }, 8181 { "PML", pml_init, pml_main, pml_exit_handler, NULL, {0} }, 8182 { "VPID", vpid_init, vpid_main, vpid_exit_handler, NULL, {0} }, 8183 { "interrupt", interrupt_init, interrupt_main, 8184 interrupt_exit_handler, NULL, {0} }, 8185 { "debug controls", dbgctls_init, dbgctls_main, dbgctls_exit_handler, 8186 NULL, {0} }, 8187 { "MSR switch", msr_switch_init, msr_switch_main, 8188 msr_switch_exit_handler, NULL, {0}, msr_switch_entry_failure }, 8189 { "vmmcall", vmmcall_init, vmmcall_main, vmmcall_exit_handler, NULL, {0} }, 8190 { "disable RDTSCP", disable_rdtscp_init, disable_rdtscp_main, 8191 disable_rdtscp_exit_handler, NULL, {0} }, 8192 { "int3", int3_init, int3_guest_main, int3_exit_handler, NULL, {0} }, 8193 { "into", into_init, into_guest_main, into_exit_handler, NULL, {0} }, 8194 { "exit_monitor_from_l2_test", NULL, exit_monitor_from_l2_main, 8195 exit_monitor_from_l2_handler, NULL, {0} }, 8196 { "invalid_msr", invalid_msr_init, invalid_msr_main, 8197 invalid_msr_exit_handler, NULL, {0}, invalid_msr_entry_failure}, 8198 /* Basic V2 tests. */ 8199 TEST(v2_null_test), 8200 TEST(v2_multiple_entries_test), 8201 TEST(fixture_test_case1), 8202 TEST(fixture_test_case2), 8203 /* Opcode tests. */ 8204 TEST(invvpid_test_v2), 8205 /* VM-entry tests */ 8206 TEST(vmx_controls_test), 8207 TEST(vmx_host_state_area_test), 8208 TEST(vmentry_movss_shadow_test), 8209 /* APICv tests */ 8210 TEST(vmx_eoi_bitmap_ioapic_scan_test), 8211 TEST(vmx_hlt_with_rvi_test), 8212 TEST(apic_reg_virt_test), 8213 TEST(virt_x2apic_mode_test), 8214 /* APIC pass-through tests */ 8215 TEST(vmx_apic_passthrough_test), 8216 TEST(vmx_apic_passthrough_thread_test), 8217 /* VMCS Shadowing tests */ 8218 TEST(vmx_vmcs_shadow_test), 8219 /* Regression tests */ 8220 TEST(vmx_cr_load_test), 8221 TEST(vmx_nm_test), 8222 TEST(vmx_db_test), 8223 TEST(vmx_nmi_window_test), 8224 TEST(vmx_intr_window_test), 8225 TEST(vmx_pending_event_test), 8226 TEST(vmx_pending_event_hlt_test), 8227 TEST(vmx_store_tsc_test), 8228 /* EPT access tests. */ 8229 TEST(ept_access_test_not_present), 8230 TEST(ept_access_test_read_only), 8231 TEST(ept_access_test_write_only), 8232 TEST(ept_access_test_read_write), 8233 TEST(ept_access_test_execute_only), 8234 TEST(ept_access_test_read_execute), 8235 TEST(ept_access_test_write_execute), 8236 TEST(ept_access_test_read_write_execute), 8237 TEST(ept_access_test_reserved_bits), 8238 TEST(ept_access_test_ignored_bits), 8239 TEST(ept_access_test_paddr_not_present_ad_disabled), 8240 TEST(ept_access_test_paddr_not_present_ad_enabled), 8241 TEST(ept_access_test_paddr_read_only_ad_disabled), 8242 TEST(ept_access_test_paddr_read_only_ad_enabled), 8243 TEST(ept_access_test_paddr_read_write), 8244 TEST(ept_access_test_paddr_read_write_execute), 8245 TEST(ept_access_test_paddr_read_execute_ad_disabled), 8246 TEST(ept_access_test_paddr_read_execute_ad_enabled), 8247 TEST(ept_access_test_paddr_not_present_page_fault), 8248 TEST(ept_access_test_force_2m_page), 8249 { NULL, NULL, NULL, NULL, NULL, {0} }, 8250 }; 8251