1 /* 2 * All test cases of nested virtualization should be in this file 3 * 4 * Author : Arthur Chunqi Li <yzt356@gmail.com> 5 */ 6 7 #include <asm/debugreg.h> 8 9 #include "vmx.h" 10 #include "msr.h" 11 #include "processor.h" 12 #include "pmu.h" 13 #include "vm.h" 14 #include "pci.h" 15 #include "fwcfg.h" 16 #include "isr.h" 17 #include "desc.h" 18 #include "apic.h" 19 #include "vmalloc.h" 20 #include "alloc_page.h" 21 #include "smp.h" 22 #include "delay.h" 23 #include "access.h" 24 #include "x86/usermode.h" 25 26 /* 27 * vmcs.GUEST_PENDING_DEBUG has the same format as DR6, although some bits that 28 * are legal in DR6 are reserved in vmcs.GUEST_PENDING_DEBUG. And if any data 29 * or I/O breakpoint matches *and* was enabled, bit 12 is also set. 30 */ 31 #define PENDING_DBG_TRAP BIT(12) 32 33 #define VPID_CAP_INVVPID_TYPES_SHIFT 40 34 35 u64 ia32_pat; 36 u64 ia32_efer; 37 void *io_bitmap_a, *io_bitmap_b; 38 u16 ioport; 39 40 unsigned long *pml4; 41 u64 eptp; 42 void *data_page1, *data_page2; 43 44 phys_addr_t pci_physaddr; 45 46 void *pml_log; 47 #define PML_INDEX 512 48 49 static inline unsigned ffs(unsigned x) 50 { 51 int pos = -1; 52 53 __asm__ __volatile__("bsf %1, %%eax; cmovnz %%eax, %0" 54 : "+r"(pos) : "rm"(x) : "eax"); 55 return pos + 1; 56 } 57 58 static inline void vmcall(void) 59 { 60 asm volatile("vmcall"); 61 } 62 63 static void basic_guest_main(void) 64 { 65 report_pass("Basic VMX test"); 66 } 67 68 static int basic_exit_handler(union exit_reason exit_reason) 69 { 70 report_fail("Basic VMX test"); 71 print_vmexit_info(exit_reason); 72 return VMX_TEST_EXIT; 73 } 74 75 static void vmenter_main(void) 76 { 77 u64 rax; 78 u64 rsp, resume_rsp; 79 80 report_pass("test vmlaunch"); 81 82 asm volatile( 83 "mov %%rsp, %0\n\t" 84 "mov %3, %%rax\n\t" 85 "vmcall\n\t" 86 "mov %%rax, %1\n\t" 87 "mov %%rsp, %2\n\t" 88 : "=r"(rsp), "=r"(rax), "=r"(resume_rsp) 89 : "g"(0xABCD)); 90 report((rax == 0xFFFF) && (rsp == resume_rsp), "test vmresume"); 91 } 92 93 static int vmenter_exit_handler(union exit_reason exit_reason) 94 { 95 u64 guest_rip = vmcs_read(GUEST_RIP); 96 97 switch (exit_reason.basic) { 98 case VMX_VMCALL: 99 if (regs.rax != 0xABCD) { 100 report_fail("test vmresume"); 101 return VMX_TEST_VMEXIT; 102 } 103 regs.rax = 0xFFFF; 104 vmcs_write(GUEST_RIP, guest_rip + 3); 105 return VMX_TEST_RESUME; 106 default: 107 report_fail("test vmresume"); 108 print_vmexit_info(exit_reason); 109 } 110 return VMX_TEST_VMEXIT; 111 } 112 113 u32 preempt_scale; 114 volatile unsigned long long tsc_val; 115 volatile u32 preempt_val; 116 u64 saved_rip; 117 118 static int preemption_timer_init(struct vmcs *vmcs) 119 { 120 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 121 printf("\tPreemption timer is not supported\n"); 122 return VMX_TEST_EXIT; 123 } 124 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 125 preempt_val = 10000000; 126 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 127 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 128 129 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 130 printf("\tSave preemption value is not supported\n"); 131 132 return VMX_TEST_START; 133 } 134 135 static void preemption_timer_main(void) 136 { 137 tsc_val = rdtsc(); 138 if (ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) { 139 vmx_set_test_stage(0); 140 vmcall(); 141 if (vmx_get_test_stage() == 1) 142 vmcall(); 143 } 144 vmx_set_test_stage(1); 145 while (vmx_get_test_stage() == 1) { 146 if (((rdtsc() - tsc_val) >> preempt_scale) 147 > 10 * preempt_val) { 148 vmx_set_test_stage(2); 149 vmcall(); 150 } 151 } 152 tsc_val = rdtsc(); 153 asm volatile ("hlt"); 154 vmcall(); 155 vmx_set_test_stage(5); 156 vmcall(); 157 } 158 159 static int preemption_timer_exit_handler(union exit_reason exit_reason) 160 { 161 bool guest_halted; 162 u64 guest_rip; 163 u32 insn_len; 164 u32 ctrl_exit; 165 166 guest_rip = vmcs_read(GUEST_RIP); 167 insn_len = vmcs_read(EXI_INST_LEN); 168 switch (exit_reason.basic) { 169 case VMX_PREEMPT: 170 switch (vmx_get_test_stage()) { 171 case 1: 172 case 2: 173 report(((rdtsc() - tsc_val) >> preempt_scale) >= preempt_val, 174 "busy-wait for preemption timer"); 175 vmx_set_test_stage(3); 176 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 177 return VMX_TEST_RESUME; 178 case 3: 179 guest_halted = 180 (vmcs_read(GUEST_ACTV_STATE) == ACTV_HLT); 181 report(((rdtsc() - tsc_val) >> preempt_scale) >= preempt_val 182 && guest_halted, 183 "preemption timer during hlt"); 184 vmx_set_test_stage(4); 185 vmcs_write(PIN_CONTROLS, 186 vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 187 vmcs_write(EXI_CONTROLS, 188 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_PREEMPT); 189 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 190 return VMX_TEST_RESUME; 191 case 4: 192 report(saved_rip == guest_rip, 193 "preemption timer with 0 value"); 194 break; 195 default: 196 report_fail("Invalid stage."); 197 print_vmexit_info(exit_reason); 198 break; 199 } 200 break; 201 case VMX_VMCALL: 202 vmcs_write(GUEST_RIP, guest_rip + insn_len); 203 switch (vmx_get_test_stage()) { 204 case 0: 205 report(vmcs_read(PREEMPT_TIMER_VALUE) == preempt_val, 206 "Keep preemption value"); 207 vmx_set_test_stage(1); 208 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 209 ctrl_exit = (vmcs_read(EXI_CONTROLS) | 210 EXI_SAVE_PREEMPT) & ctrl_exit_rev.clr; 211 vmcs_write(EXI_CONTROLS, ctrl_exit); 212 return VMX_TEST_RESUME; 213 case 1: 214 report(vmcs_read(PREEMPT_TIMER_VALUE) < preempt_val, 215 "Save preemption value"); 216 return VMX_TEST_RESUME; 217 case 2: 218 report_fail("busy-wait for preemption timer"); 219 vmx_set_test_stage(3); 220 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 221 return VMX_TEST_RESUME; 222 case 3: 223 report_fail("preemption timer during hlt"); 224 vmx_set_test_stage(4); 225 /* fall through */ 226 case 4: 227 vmcs_write(PIN_CONTROLS, 228 vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 229 vmcs_write(PREEMPT_TIMER_VALUE, 0); 230 saved_rip = guest_rip + insn_len; 231 return VMX_TEST_RESUME; 232 case 5: 233 report_fail("preemption timer with 0 value (vmcall stage 5)"); 234 break; 235 default: 236 // Should not reach here 237 report_fail("unexpected stage, %d", 238 vmx_get_test_stage()); 239 print_vmexit_info(exit_reason); 240 return VMX_TEST_VMEXIT; 241 } 242 break; 243 default: 244 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 245 print_vmexit_info(exit_reason); 246 } 247 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 248 return VMX_TEST_VMEXIT; 249 } 250 251 static void msr_bmp_init(void) 252 { 253 void *msr_bitmap; 254 u32 ctrl_cpu0; 255 256 msr_bitmap = alloc_page(); 257 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 258 ctrl_cpu0 |= CPU_MSR_BITMAP; 259 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 260 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 261 } 262 263 static void *get_msr_bitmap(void) 264 { 265 void *msr_bitmap; 266 267 if (vmcs_read(CPU_EXEC_CTRL0) & CPU_MSR_BITMAP) { 268 msr_bitmap = (void *)vmcs_read(MSR_BITMAP); 269 } else { 270 msr_bitmap = alloc_page(); 271 memset(msr_bitmap, 0xff, PAGE_SIZE); 272 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 273 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_MSR_BITMAP); 274 } 275 276 return msr_bitmap; 277 } 278 279 static void disable_intercept_for_x2apic_msrs(void) 280 { 281 unsigned long *msr_bitmap = (unsigned long *)get_msr_bitmap(); 282 u32 msr; 283 284 for (msr = APIC_BASE_MSR; 285 msr < (APIC_BASE_MSR+0xff); 286 msr += BITS_PER_LONG) { 287 unsigned int word = msr / BITS_PER_LONG; 288 289 msr_bitmap[word] = 0; 290 msr_bitmap[word + (0x800 / sizeof(long))] = 0; 291 } 292 } 293 294 static int test_ctrl_pat_init(struct vmcs *vmcs) 295 { 296 u64 ctrl_ent; 297 u64 ctrl_exi; 298 299 msr_bmp_init(); 300 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT) && 301 !(ctrl_exit_rev.clr & EXI_LOAD_PAT) && 302 !(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 303 printf("\tSave/load PAT is not supported\n"); 304 return 1; 305 } 306 307 ctrl_ent = vmcs_read(ENT_CONTROLS); 308 ctrl_exi = vmcs_read(EXI_CONTROLS); 309 ctrl_ent |= ctrl_enter_rev.clr & ENT_LOAD_PAT; 310 ctrl_exi |= ctrl_exit_rev.clr & (EXI_SAVE_PAT | EXI_LOAD_PAT); 311 vmcs_write(ENT_CONTROLS, ctrl_ent); 312 vmcs_write(EXI_CONTROLS, ctrl_exi); 313 ia32_pat = rdmsr(MSR_IA32_CR_PAT); 314 vmcs_write(GUEST_PAT, 0x0); 315 vmcs_write(HOST_PAT, ia32_pat); 316 return VMX_TEST_START; 317 } 318 319 static void test_ctrl_pat_main(void) 320 { 321 u64 guest_ia32_pat; 322 323 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 324 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) 325 printf("\tENT_LOAD_PAT is not supported.\n"); 326 else { 327 if (guest_ia32_pat != 0) { 328 report_fail("Entry load PAT"); 329 return; 330 } 331 } 332 wrmsr(MSR_IA32_CR_PAT, 0x6); 333 vmcall(); 334 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 335 if (ctrl_enter_rev.clr & ENT_LOAD_PAT) 336 report(guest_ia32_pat == ia32_pat, "Entry load PAT"); 337 } 338 339 static int test_ctrl_pat_exit_handler(union exit_reason exit_reason) 340 { 341 u64 guest_rip; 342 u64 guest_pat; 343 344 guest_rip = vmcs_read(GUEST_RIP); 345 switch (exit_reason.basic) { 346 case VMX_VMCALL: 347 guest_pat = vmcs_read(GUEST_PAT); 348 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT)) { 349 printf("\tEXI_SAVE_PAT is not supported\n"); 350 vmcs_write(GUEST_PAT, 0x6); 351 } else { 352 report(guest_pat == 0x6, "Exit save PAT"); 353 } 354 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) 355 printf("\tEXI_LOAD_PAT is not supported\n"); 356 else 357 report(rdmsr(MSR_IA32_CR_PAT) == ia32_pat, 358 "Exit load PAT"); 359 vmcs_write(GUEST_PAT, ia32_pat); 360 vmcs_write(GUEST_RIP, guest_rip + 3); 361 return VMX_TEST_RESUME; 362 default: 363 printf("ERROR : Unknown exit reason, 0x%x.\n", exit_reason.full); 364 break; 365 } 366 return VMX_TEST_VMEXIT; 367 } 368 369 static int test_ctrl_efer_init(struct vmcs *vmcs) 370 { 371 u64 ctrl_ent; 372 u64 ctrl_exi; 373 374 msr_bmp_init(); 375 ctrl_ent = vmcs_read(ENT_CONTROLS) | ENT_LOAD_EFER; 376 ctrl_exi = vmcs_read(EXI_CONTROLS) | EXI_SAVE_EFER | EXI_LOAD_EFER; 377 vmcs_write(ENT_CONTROLS, ctrl_ent & ctrl_enter_rev.clr); 378 vmcs_write(EXI_CONTROLS, ctrl_exi & ctrl_exit_rev.clr); 379 ia32_efer = rdmsr(MSR_EFER); 380 vmcs_write(GUEST_EFER, ia32_efer ^ EFER_NX); 381 vmcs_write(HOST_EFER, ia32_efer ^ EFER_NX); 382 return VMX_TEST_START; 383 } 384 385 static void test_ctrl_efer_main(void) 386 { 387 u64 guest_ia32_efer; 388 389 guest_ia32_efer = rdmsr(MSR_EFER); 390 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) 391 printf("\tENT_LOAD_EFER is not supported.\n"); 392 else { 393 if (guest_ia32_efer != (ia32_efer ^ EFER_NX)) { 394 report_fail("Entry load EFER"); 395 return; 396 } 397 } 398 wrmsr(MSR_EFER, ia32_efer); 399 vmcall(); 400 guest_ia32_efer = rdmsr(MSR_EFER); 401 if (ctrl_enter_rev.clr & ENT_LOAD_EFER) 402 report(guest_ia32_efer == ia32_efer, "Entry load EFER"); 403 } 404 405 static int test_ctrl_efer_exit_handler(union exit_reason exit_reason) 406 { 407 u64 guest_rip; 408 u64 guest_efer; 409 410 guest_rip = vmcs_read(GUEST_RIP); 411 switch (exit_reason.basic) { 412 case VMX_VMCALL: 413 guest_efer = vmcs_read(GUEST_EFER); 414 if (!(ctrl_exit_rev.clr & EXI_SAVE_EFER)) { 415 printf("\tEXI_SAVE_EFER is not supported\n"); 416 vmcs_write(GUEST_EFER, ia32_efer); 417 } else { 418 report(guest_efer == ia32_efer, "Exit save EFER"); 419 } 420 if (!(ctrl_exit_rev.clr & EXI_LOAD_EFER)) { 421 printf("\tEXI_LOAD_EFER is not supported\n"); 422 wrmsr(MSR_EFER, ia32_efer ^ EFER_NX); 423 } else { 424 report(rdmsr(MSR_EFER) == (ia32_efer ^ EFER_NX), 425 "Exit load EFER"); 426 } 427 vmcs_write(GUEST_PAT, ia32_efer); 428 vmcs_write(GUEST_RIP, guest_rip + 3); 429 return VMX_TEST_RESUME; 430 default: 431 printf("ERROR : Unknown exit reason, 0x%x.\n", exit_reason.full); 432 break; 433 } 434 return VMX_TEST_VMEXIT; 435 } 436 437 u32 guest_cr0, guest_cr4; 438 439 static void cr_shadowing_main(void) 440 { 441 u32 cr0, cr4, tmp; 442 443 // Test read through 444 vmx_set_test_stage(0); 445 guest_cr0 = read_cr0(); 446 if (vmx_get_test_stage() == 1) 447 report_fail("Read through CR0"); 448 else 449 vmcall(); 450 vmx_set_test_stage(1); 451 guest_cr4 = read_cr4(); 452 if (vmx_get_test_stage() == 2) 453 report_fail("Read through CR4"); 454 else 455 vmcall(); 456 // Test write through 457 guest_cr0 = guest_cr0 ^ (X86_CR0_TS | X86_CR0_MP); 458 guest_cr4 = guest_cr4 ^ (X86_CR4_TSD | X86_CR4_DE); 459 vmx_set_test_stage(2); 460 write_cr0(guest_cr0); 461 if (vmx_get_test_stage() == 3) 462 report_fail("Write through CR0"); 463 else 464 vmcall(); 465 vmx_set_test_stage(3); 466 write_cr4(guest_cr4); 467 if (vmx_get_test_stage() == 4) 468 report_fail("Write through CR4"); 469 else 470 vmcall(); 471 // Test read shadow 472 vmx_set_test_stage(4); 473 vmcall(); 474 cr0 = read_cr0(); 475 if (vmx_get_test_stage() != 5) 476 report(cr0 == guest_cr0, "Read shadowing CR0"); 477 vmx_set_test_stage(5); 478 cr4 = read_cr4(); 479 if (vmx_get_test_stage() != 6) 480 report(cr4 == guest_cr4, "Read shadowing CR4"); 481 // Test write shadow (same value with shadow) 482 vmx_set_test_stage(6); 483 write_cr0(guest_cr0); 484 if (vmx_get_test_stage() == 7) 485 report_fail("Write shadowing CR0 (same value with shadow)"); 486 else 487 vmcall(); 488 vmx_set_test_stage(7); 489 write_cr4(guest_cr4); 490 if (vmx_get_test_stage() == 8) 491 report_fail("Write shadowing CR4 (same value with shadow)"); 492 else 493 vmcall(); 494 // Test write shadow (different value) 495 vmx_set_test_stage(8); 496 tmp = guest_cr0 ^ X86_CR0_TS; 497 asm volatile("mov %0, %%rsi\n\t" 498 "mov %%rsi, %%cr0\n\t" 499 ::"m"(tmp) 500 :"rsi", "memory", "cc"); 501 report(vmx_get_test_stage() == 9, 502 "Write shadowing different X86_CR0_TS"); 503 vmx_set_test_stage(9); 504 tmp = guest_cr0 ^ X86_CR0_MP; 505 asm volatile("mov %0, %%rsi\n\t" 506 "mov %%rsi, %%cr0\n\t" 507 ::"m"(tmp) 508 :"rsi", "memory", "cc"); 509 report(vmx_get_test_stage() == 10, 510 "Write shadowing different X86_CR0_MP"); 511 vmx_set_test_stage(10); 512 tmp = guest_cr4 ^ X86_CR4_TSD; 513 asm volatile("mov %0, %%rsi\n\t" 514 "mov %%rsi, %%cr4\n\t" 515 ::"m"(tmp) 516 :"rsi", "memory", "cc"); 517 report(vmx_get_test_stage() == 11, 518 "Write shadowing different X86_CR4_TSD"); 519 vmx_set_test_stage(11); 520 tmp = guest_cr4 ^ X86_CR4_DE; 521 asm volatile("mov %0, %%rsi\n\t" 522 "mov %%rsi, %%cr4\n\t" 523 ::"m"(tmp) 524 :"rsi", "memory", "cc"); 525 report(vmx_get_test_stage() == 12, 526 "Write shadowing different X86_CR4_DE"); 527 } 528 529 static int cr_shadowing_exit_handler(union exit_reason exit_reason) 530 { 531 u64 guest_rip; 532 u32 insn_len; 533 u32 exit_qual; 534 535 guest_rip = vmcs_read(GUEST_RIP); 536 insn_len = vmcs_read(EXI_INST_LEN); 537 exit_qual = vmcs_read(EXI_QUALIFICATION); 538 switch (exit_reason.basic) { 539 case VMX_VMCALL: 540 switch (vmx_get_test_stage()) { 541 case 0: 542 report(guest_cr0 == vmcs_read(GUEST_CR0), 543 "Read through CR0"); 544 break; 545 case 1: 546 report(guest_cr4 == vmcs_read(GUEST_CR4), 547 "Read through CR4"); 548 break; 549 case 2: 550 report(guest_cr0 == vmcs_read(GUEST_CR0), 551 "Write through CR0"); 552 break; 553 case 3: 554 report(guest_cr4 == vmcs_read(GUEST_CR4), 555 "Write through CR4"); 556 break; 557 case 4: 558 guest_cr0 = vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP); 559 guest_cr4 = vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE); 560 vmcs_write(CR0_MASK, X86_CR0_TS | X86_CR0_MP); 561 vmcs_write(CR0_READ_SHADOW, guest_cr0 & (X86_CR0_TS | X86_CR0_MP)); 562 vmcs_write(CR4_MASK, X86_CR4_TSD | X86_CR4_DE); 563 vmcs_write(CR4_READ_SHADOW, guest_cr4 & (X86_CR4_TSD | X86_CR4_DE)); 564 break; 565 case 6: 566 report(guest_cr0 == (vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP)), 567 "Write shadowing CR0 (same value)"); 568 break; 569 case 7: 570 report(guest_cr4 == (vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE)), 571 "Write shadowing CR4 (same value)"); 572 break; 573 default: 574 // Should not reach here 575 report_fail("unexpected stage, %d", 576 vmx_get_test_stage()); 577 print_vmexit_info(exit_reason); 578 return VMX_TEST_VMEXIT; 579 } 580 vmcs_write(GUEST_RIP, guest_rip + insn_len); 581 return VMX_TEST_RESUME; 582 case VMX_CR: 583 switch (vmx_get_test_stage()) { 584 case 4: 585 report_fail("Read shadowing CR0"); 586 vmx_inc_test_stage(); 587 break; 588 case 5: 589 report_fail("Read shadowing CR4"); 590 vmx_inc_test_stage(); 591 break; 592 case 6: 593 report_fail("Write shadowing CR0 (same value)"); 594 vmx_inc_test_stage(); 595 break; 596 case 7: 597 report_fail("Write shadowing CR4 (same value)"); 598 vmx_inc_test_stage(); 599 break; 600 case 8: 601 case 9: 602 // 0x600 encodes "mov %esi, %cr0" 603 if (exit_qual == 0x600) 604 vmx_inc_test_stage(); 605 break; 606 case 10: 607 case 11: 608 // 0x604 encodes "mov %esi, %cr4" 609 if (exit_qual == 0x604) 610 vmx_inc_test_stage(); 611 break; 612 default: 613 // Should not reach here 614 report_fail("unexpected stage, %d", 615 vmx_get_test_stage()); 616 print_vmexit_info(exit_reason); 617 return VMX_TEST_VMEXIT; 618 } 619 vmcs_write(GUEST_RIP, guest_rip + insn_len); 620 return VMX_TEST_RESUME; 621 default: 622 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 623 print_vmexit_info(exit_reason); 624 } 625 return VMX_TEST_VMEXIT; 626 } 627 628 static int iobmp_init(struct vmcs *vmcs) 629 { 630 u32 ctrl_cpu0; 631 632 io_bitmap_a = alloc_page(); 633 io_bitmap_b = alloc_page(); 634 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 635 ctrl_cpu0 |= CPU_IO_BITMAP; 636 ctrl_cpu0 &= (~CPU_IO); 637 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 638 vmcs_write(IO_BITMAP_A, (u64)io_bitmap_a); 639 vmcs_write(IO_BITMAP_B, (u64)io_bitmap_b); 640 return VMX_TEST_START; 641 } 642 643 static void iobmp_main(void) 644 { 645 // stage 0, test IO pass 646 vmx_set_test_stage(0); 647 inb(0x5000); 648 outb(0x0, 0x5000); 649 report(vmx_get_test_stage() == 0, "I/O bitmap - I/O pass"); 650 // test IO width, in/out 651 ((u8 *)io_bitmap_a)[0] = 0xFF; 652 vmx_set_test_stage(2); 653 inb(0x0); 654 report(vmx_get_test_stage() == 3, "I/O bitmap - trap in"); 655 vmx_set_test_stage(3); 656 outw(0x0, 0x0); 657 report(vmx_get_test_stage() == 4, "I/O bitmap - trap out"); 658 vmx_set_test_stage(4); 659 inl(0x0); 660 report(vmx_get_test_stage() == 5, "I/O bitmap - I/O width, long"); 661 // test low/high IO port 662 vmx_set_test_stage(5); 663 ((u8 *)io_bitmap_a)[0x5000 / 8] = (1 << (0x5000 % 8)); 664 inb(0x5000); 665 report(vmx_get_test_stage() == 6, "I/O bitmap - I/O port, low part"); 666 vmx_set_test_stage(6); 667 ((u8 *)io_bitmap_b)[0x1000 / 8] = (1 << (0x1000 % 8)); 668 inb(0x9000); 669 report(vmx_get_test_stage() == 7, "I/O bitmap - I/O port, high part"); 670 // test partial pass 671 vmx_set_test_stage(7); 672 inl(0x4FFF); 673 report(vmx_get_test_stage() == 8, "I/O bitmap - partial pass"); 674 // test overrun 675 vmx_set_test_stage(8); 676 memset(io_bitmap_a, 0x0, PAGE_SIZE); 677 memset(io_bitmap_b, 0x0, PAGE_SIZE); 678 inl(0xFFFF); 679 report(vmx_get_test_stage() == 9, "I/O bitmap - overrun"); 680 vmx_set_test_stage(9); 681 vmcall(); 682 outb(0x0, 0x0); 683 report(vmx_get_test_stage() == 9, 684 "I/O bitmap - ignore unconditional exiting"); 685 vmx_set_test_stage(10); 686 vmcall(); 687 outb(0x0, 0x0); 688 report(vmx_get_test_stage() == 11, 689 "I/O bitmap - unconditional exiting"); 690 } 691 692 static int iobmp_exit_handler(union exit_reason exit_reason) 693 { 694 u64 guest_rip; 695 ulong exit_qual; 696 u32 insn_len, ctrl_cpu0; 697 698 guest_rip = vmcs_read(GUEST_RIP); 699 exit_qual = vmcs_read(EXI_QUALIFICATION); 700 insn_len = vmcs_read(EXI_INST_LEN); 701 switch (exit_reason.basic) { 702 case VMX_IO: 703 switch (vmx_get_test_stage()) { 704 case 0: 705 case 1: 706 vmx_inc_test_stage(); 707 break; 708 case 2: 709 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_BYTE, 710 "I/O bitmap - I/O width, byte"); 711 report(exit_qual & VMX_IO_IN, 712 "I/O bitmap - I/O direction, in"); 713 vmx_inc_test_stage(); 714 break; 715 case 3: 716 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_WORD, 717 "I/O bitmap - I/O width, word"); 718 report(!(exit_qual & VMX_IO_IN), 719 "I/O bitmap - I/O direction, out"); 720 vmx_inc_test_stage(); 721 break; 722 case 4: 723 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_LONG, 724 "I/O bitmap - I/O width, long"); 725 vmx_inc_test_stage(); 726 break; 727 case 5: 728 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x5000) 729 vmx_inc_test_stage(); 730 break; 731 case 6: 732 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x9000) 733 vmx_inc_test_stage(); 734 break; 735 case 7: 736 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x4FFF) 737 vmx_inc_test_stage(); 738 break; 739 case 8: 740 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0xFFFF) 741 vmx_inc_test_stage(); 742 break; 743 case 9: 744 case 10: 745 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 746 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0 & ~CPU_IO); 747 vmx_inc_test_stage(); 748 break; 749 default: 750 // Should not reach here 751 report_fail("unexpected stage, %d", 752 vmx_get_test_stage()); 753 print_vmexit_info(exit_reason); 754 return VMX_TEST_VMEXIT; 755 } 756 vmcs_write(GUEST_RIP, guest_rip + insn_len); 757 return VMX_TEST_RESUME; 758 case VMX_VMCALL: 759 switch (vmx_get_test_stage()) { 760 case 9: 761 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 762 ctrl_cpu0 |= CPU_IO | CPU_IO_BITMAP; 763 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 764 break; 765 case 10: 766 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 767 ctrl_cpu0 = (ctrl_cpu0 & ~CPU_IO_BITMAP) | CPU_IO; 768 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 769 break; 770 default: 771 // Should not reach here 772 report_fail("unexpected stage, %d", 773 vmx_get_test_stage()); 774 print_vmexit_info(exit_reason); 775 return VMX_TEST_VMEXIT; 776 } 777 vmcs_write(GUEST_RIP, guest_rip + insn_len); 778 return VMX_TEST_RESUME; 779 default: 780 printf("guest_rip = %#lx\n", guest_rip); 781 printf("\tERROR : Unknown exit reason, 0x%x\n", exit_reason.full); 782 break; 783 } 784 return VMX_TEST_VMEXIT; 785 } 786 787 #define INSN_CPU0 0 788 #define INSN_CPU1 1 789 #define INSN_ALWAYS_TRAP 2 790 791 #define FIELD_EXIT_QUAL (1 << 0) 792 #define FIELD_INSN_INFO (1 << 1) 793 794 asm( 795 "insn_hlt: hlt;ret\n\t" 796 "insn_invlpg: invlpg 0x12345678;ret\n\t" 797 "insn_mwait: xor %eax, %eax; xor %ecx, %ecx; mwait;ret\n\t" 798 "insn_rdpmc: xor %ecx, %ecx; rdpmc;ret\n\t" 799 "insn_rdtsc: rdtsc;ret\n\t" 800 "insn_cr3_load: mov cr3,%rax; mov %rax,%cr3;ret\n\t" 801 "insn_cr3_store: mov %cr3,%rax;ret\n\t" 802 "insn_cr8_load: xor %eax, %eax; mov %rax,%cr8;ret\n\t" 803 "insn_cr8_store: mov %cr8,%rax;ret\n\t" 804 "insn_monitor: xor %eax, %eax; xor %ecx, %ecx; xor %edx, %edx; monitor;ret\n\t" 805 "insn_pause: pause;ret\n\t" 806 "insn_wbinvd: wbinvd;ret\n\t" 807 "insn_cpuid: mov $10, %eax; cpuid;ret\n\t" 808 "insn_invd: invd;ret\n\t" 809 "insn_sgdt: sgdt gdt_descr;ret\n\t" 810 "insn_lgdt: lgdt gdt_descr;ret\n\t" 811 "insn_sidt: sidt idt_descr;ret\n\t" 812 "insn_lidt: lidt idt_descr;ret\n\t" 813 "insn_sldt: sldt %ax;ret\n\t" 814 "insn_lldt: xor %eax, %eax; lldt %ax;ret\n\t" 815 "insn_str: str %ax;ret\n\t" 816 "insn_rdrand: rdrand %rax;ret\n\t" 817 "insn_rdseed: rdseed %rax;ret\n\t" 818 ); 819 extern void insn_hlt(void); 820 extern void insn_invlpg(void); 821 extern void insn_mwait(void); 822 extern void insn_rdpmc(void); 823 extern void insn_rdtsc(void); 824 extern void insn_cr3_load(void); 825 extern void insn_cr3_store(void); 826 extern void insn_cr8_load(void); 827 extern void insn_cr8_store(void); 828 extern void insn_monitor(void); 829 extern void insn_pause(void); 830 extern void insn_wbinvd(void); 831 extern void insn_sgdt(void); 832 extern void insn_lgdt(void); 833 extern void insn_sidt(void); 834 extern void insn_lidt(void); 835 extern void insn_sldt(void); 836 extern void insn_lldt(void); 837 extern void insn_str(void); 838 extern void insn_cpuid(void); 839 extern void insn_invd(void); 840 extern void insn_rdrand(void); 841 extern void insn_rdseed(void); 842 843 u32 cur_insn; 844 u64 cr3; 845 846 typedef bool (*supported_fn)(void); 847 848 static bool this_cpu_has_mwait(void) 849 { 850 return this_cpu_has(X86_FEATURE_MWAIT); 851 } 852 853 struct insn_table { 854 const char *name; 855 u32 flag; 856 void (*insn_func)(void); 857 u32 type; 858 u32 reason; 859 ulong exit_qual; 860 u32 insn_info; 861 // Use FIELD_EXIT_QUAL and FIELD_INSN_INFO to define 862 // which field need to be tested, reason is always tested 863 u32 test_field; 864 const supported_fn supported_fn; 865 u8 disabled; 866 }; 867 868 /* 869 * Add more test cases of instruction intercept here. Elements in this 870 * table is: 871 * name/control flag/insn function/type/exit reason/exit qulification/ 872 * instruction info/field to test 873 * The last field defines which fields (exit_qual and insn_info) need to be 874 * tested in exit handler. If set to 0, only "reason" is checked. 875 */ 876 static struct insn_table insn_table[] = { 877 // Flags for Primary Processor-Based VM-Execution Controls 878 {"HLT", CPU_HLT, insn_hlt, INSN_CPU0, 12, 0, 0, 0}, 879 {"INVLPG", CPU_INVLPG, insn_invlpg, INSN_CPU0, 14, 880 0x12345678, 0, FIELD_EXIT_QUAL}, 881 {"MWAIT", CPU_MWAIT, insn_mwait, INSN_CPU0, 36, 0, 0, 0, this_cpu_has_mwait}, 882 {"RDPMC", CPU_RDPMC, insn_rdpmc, INSN_CPU0, 15, 0, 0, 0, this_cpu_has_pmu}, 883 {"RDTSC", CPU_RDTSC, insn_rdtsc, INSN_CPU0, 16, 0, 0, 0}, 884 {"CR3 load", CPU_CR3_LOAD, insn_cr3_load, INSN_CPU0, 28, 0x3, 0, 885 FIELD_EXIT_QUAL}, 886 {"CR3 store", CPU_CR3_STORE, insn_cr3_store, INSN_CPU0, 28, 0x13, 0, 887 FIELD_EXIT_QUAL}, 888 {"CR8 load", CPU_CR8_LOAD, insn_cr8_load, INSN_CPU0, 28, 0x8, 0, 889 FIELD_EXIT_QUAL}, 890 {"CR8 store", CPU_CR8_STORE, insn_cr8_store, INSN_CPU0, 28, 0x18, 0, 891 FIELD_EXIT_QUAL}, 892 {"MONITOR", CPU_MONITOR, insn_monitor, INSN_CPU0, 39, 0, 0, 0, this_cpu_has_mwait}, 893 {"PAUSE", CPU_PAUSE, insn_pause, INSN_CPU0, 40, 0, 0, 0}, 894 // Flags for Secondary Processor-Based VM-Execution Controls 895 {"WBINVD", CPU_WBINVD, insn_wbinvd, INSN_CPU1, 54, 0, 0, 0}, 896 {"DESC_TABLE (SGDT)", CPU_DESC_TABLE, insn_sgdt, INSN_CPU1, 46, 0, 0, 0}, 897 {"DESC_TABLE (LGDT)", CPU_DESC_TABLE, insn_lgdt, INSN_CPU1, 46, 0, 0, 0}, 898 {"DESC_TABLE (SIDT)", CPU_DESC_TABLE, insn_sidt, INSN_CPU1, 46, 0, 0, 0}, 899 {"DESC_TABLE (LIDT)", CPU_DESC_TABLE, insn_lidt, INSN_CPU1, 46, 0, 0, 0}, 900 {"DESC_TABLE (SLDT)", CPU_DESC_TABLE, insn_sldt, INSN_CPU1, 47, 0, 0, 0}, 901 {"DESC_TABLE (LLDT)", CPU_DESC_TABLE, insn_lldt, INSN_CPU1, 47, 0, 0, 0}, 902 {"DESC_TABLE (STR)", CPU_DESC_TABLE, insn_str, INSN_CPU1, 47, 0, 0, 0}, 903 /* LTR causes a #GP if done with a busy selector, so it is not tested. */ 904 {"RDRAND", CPU_RDRAND, insn_rdrand, INSN_CPU1, VMX_RDRAND, 0, 0, 0}, 905 {"RDSEED", CPU_RDSEED, insn_rdseed, INSN_CPU1, VMX_RDSEED, 0, 0, 0}, 906 // Instructions always trap 907 {"CPUID", 0, insn_cpuid, INSN_ALWAYS_TRAP, 10, 0, 0, 0}, 908 {"INVD", 0, insn_invd, INSN_ALWAYS_TRAP, 13, 0, 0, 0}, 909 // Instructions never trap 910 {NULL}, 911 }; 912 913 static int insn_intercept_init(struct vmcs *vmcs) 914 { 915 u32 ctrl_cpu, cur_insn; 916 917 ctrl_cpu = ctrl_cpu_rev[0].set | CPU_SECONDARY; 918 ctrl_cpu &= ctrl_cpu_rev[0].clr; 919 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu); 920 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu_rev[1].set); 921 cr3 = read_cr3(); 922 923 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 924 if (insn_table[cur_insn].supported_fn == NULL) 925 continue; 926 insn_table[cur_insn].disabled = !insn_table[cur_insn].supported_fn(); 927 } 928 return VMX_TEST_START; 929 } 930 931 static void insn_intercept_main(void) 932 { 933 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 934 vmx_set_test_stage(cur_insn * 2); 935 if ((insn_table[cur_insn].type == INSN_CPU0 && 936 !(ctrl_cpu_rev[0].clr & insn_table[cur_insn].flag)) || 937 (insn_table[cur_insn].type == INSN_CPU1 && 938 !(ctrl_cpu_rev[1].clr & insn_table[cur_insn].flag))) { 939 printf("\tCPU_CTRL%d.CPU_%s is not supported.\n", 940 insn_table[cur_insn].type - INSN_CPU0, 941 insn_table[cur_insn].name); 942 continue; 943 } 944 945 if (insn_table[cur_insn].disabled) { 946 printf("\tFeature required for %s is not supported.\n", 947 insn_table[cur_insn].name); 948 continue; 949 } 950 951 if ((insn_table[cur_insn].type == INSN_CPU0 && 952 !(ctrl_cpu_rev[0].set & insn_table[cur_insn].flag)) || 953 (insn_table[cur_insn].type == INSN_CPU1 && 954 !(ctrl_cpu_rev[1].set & insn_table[cur_insn].flag))) { 955 /* skip hlt, it stalls the guest and is tested below */ 956 if (insn_table[cur_insn].insn_func != insn_hlt) 957 insn_table[cur_insn].insn_func(); 958 report(vmx_get_test_stage() == cur_insn * 2, 959 "execute %s", 960 insn_table[cur_insn].name); 961 } else if (insn_table[cur_insn].type != INSN_ALWAYS_TRAP) 962 printf("\tCPU_CTRL%d.CPU_%s always traps.\n", 963 insn_table[cur_insn].type - INSN_CPU0, 964 insn_table[cur_insn].name); 965 966 vmcall(); 967 968 insn_table[cur_insn].insn_func(); 969 report(vmx_get_test_stage() == cur_insn * 2 + 1, 970 "intercept %s", 971 insn_table[cur_insn].name); 972 973 vmx_set_test_stage(cur_insn * 2 + 1); 974 vmcall(); 975 } 976 } 977 978 static int insn_intercept_exit_handler(union exit_reason exit_reason) 979 { 980 u64 guest_rip; 981 ulong exit_qual; 982 u32 insn_len; 983 u32 insn_info; 984 bool pass; 985 986 guest_rip = vmcs_read(GUEST_RIP); 987 exit_qual = vmcs_read(EXI_QUALIFICATION); 988 insn_len = vmcs_read(EXI_INST_LEN); 989 insn_info = vmcs_read(EXI_INST_INFO); 990 991 if (exit_reason.basic == VMX_VMCALL) { 992 u32 val = 0; 993 994 if (insn_table[cur_insn].type == INSN_CPU0) 995 val = vmcs_read(CPU_EXEC_CTRL0); 996 else if (insn_table[cur_insn].type == INSN_CPU1) 997 val = vmcs_read(CPU_EXEC_CTRL1); 998 999 if (vmx_get_test_stage() & 1) 1000 val &= ~insn_table[cur_insn].flag; 1001 else 1002 val |= insn_table[cur_insn].flag; 1003 1004 if (insn_table[cur_insn].type == INSN_CPU0) 1005 vmcs_write(CPU_EXEC_CTRL0, val | ctrl_cpu_rev[0].set); 1006 else if (insn_table[cur_insn].type == INSN_CPU1) 1007 vmcs_write(CPU_EXEC_CTRL1, val | ctrl_cpu_rev[1].set); 1008 } else { 1009 pass = (cur_insn * 2 == vmx_get_test_stage()) && 1010 insn_table[cur_insn].reason == exit_reason.full; 1011 if (insn_table[cur_insn].test_field & FIELD_EXIT_QUAL && 1012 insn_table[cur_insn].exit_qual != exit_qual) 1013 pass = false; 1014 if (insn_table[cur_insn].test_field & FIELD_INSN_INFO && 1015 insn_table[cur_insn].insn_info != insn_info) 1016 pass = false; 1017 if (pass) 1018 vmx_inc_test_stage(); 1019 } 1020 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1021 return VMX_TEST_RESUME; 1022 } 1023 1024 /** 1025 * __setup_ept - Setup the VMCS fields to enable Extended Page Tables (EPT) 1026 * @hpa: Host physical address of the top-level, a.k.a. root, EPT table 1027 * @enable_ad: Whether or not to enable Access/Dirty bits for EPT entries 1028 * 1029 * Returns 0 on success, 1 on failure. 1030 * 1031 * Note that @hpa doesn't need to point at actual memory if VM-Launch is 1032 * expected to fail, e.g. setup_dummy_ept() arbitrarily passes '0' to satisfy 1033 * the various EPTP consistency checks, but doesn't ensure backing for HPA '0'. 1034 */ 1035 static int __setup_ept(u64 hpa, bool enable_ad) 1036 { 1037 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1038 !(ctrl_cpu_rev[1].clr & CPU_EPT)) { 1039 printf("\tEPT is not supported\n"); 1040 return 1; 1041 } 1042 if (!(ept_vpid.val & EPT_CAP_WB)) { 1043 printf("\tWB memtype for EPT walks not supported\n"); 1044 return 1; 1045 } 1046 if (!(ept_vpid.val & EPT_CAP_PWL4)) { 1047 printf("\tPWL4 is not supported\n"); 1048 return 1; 1049 } 1050 1051 eptp = EPT_MEM_TYPE_WB; 1052 eptp |= (3 << EPTP_PG_WALK_LEN_SHIFT); 1053 eptp |= hpa; 1054 if (enable_ad) 1055 eptp |= EPTP_AD_FLAG; 1056 1057 vmcs_write(EPTP, eptp); 1058 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0)| CPU_SECONDARY); 1059 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1)| CPU_EPT); 1060 1061 return 0; 1062 } 1063 1064 /** 1065 * setup_ept - Enable Extended Page Tables (EPT) and setup an identity map 1066 * @enable_ad: Whether or not to enable Access/Dirty bits for EPT entries 1067 * 1068 * Returns 0 on success, 1 on failure. 1069 * 1070 * This is the "real" function for setting up EPT tables, i.e. use this for 1071 * tests that need to run code in the guest with EPT enabled. 1072 */ 1073 static int setup_ept(bool enable_ad) 1074 { 1075 unsigned long end_of_memory; 1076 1077 pml4 = alloc_page(); 1078 1079 if (__setup_ept(virt_to_phys(pml4), enable_ad)) 1080 return 1; 1081 1082 end_of_memory = fwcfg_get_u64(FW_CFG_RAM_SIZE); 1083 if (end_of_memory < (1ul << 32)) 1084 end_of_memory = (1ul << 32); 1085 /* Cannot use large EPT pages if we need to track EPT 1086 * accessed/dirty bits at 4K granularity. 1087 */ 1088 setup_ept_range(pml4, 0, end_of_memory, 0, 1089 !enable_ad && ept_2m_supported(), 1090 EPT_WA | EPT_RA | EPT_EA); 1091 return 0; 1092 } 1093 1094 /** 1095 * setup_dummy_ept - Enable Extended Page Tables (EPT) with a dummy root HPA 1096 * 1097 * Setup EPT using a semi-arbitrary dummy root HPA. This function is intended 1098 * for use by tests that need EPT enabled to verify dependent VMCS controls 1099 * but never expect to fully enter the guest, i.e. don't need setup the actual 1100 * EPT tables. 1101 */ 1102 static void setup_dummy_ept(void) 1103 { 1104 if (__setup_ept(0, false)) 1105 report_abort("EPT setup unexpectedly failed"); 1106 } 1107 1108 static int enable_unrestricted_guest(bool need_valid_ept) 1109 { 1110 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1111 !(ctrl_cpu_rev[1].clr & CPU_URG) || 1112 !(ctrl_cpu_rev[1].clr & CPU_EPT)) 1113 return 1; 1114 1115 if (need_valid_ept) 1116 setup_ept(false); 1117 else 1118 setup_dummy_ept(); 1119 1120 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 1121 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | CPU_URG); 1122 1123 return 0; 1124 } 1125 1126 static void ept_enable_ad_bits(void) 1127 { 1128 eptp |= EPTP_AD_FLAG; 1129 vmcs_write(EPTP, eptp); 1130 } 1131 1132 static void ept_disable_ad_bits(void) 1133 { 1134 eptp &= ~EPTP_AD_FLAG; 1135 vmcs_write(EPTP, eptp); 1136 } 1137 1138 static int ept_ad_enabled(void) 1139 { 1140 return eptp & EPTP_AD_FLAG; 1141 } 1142 1143 static void ept_enable_ad_bits_or_skip_test(void) 1144 { 1145 if (!ept_ad_bits_supported()) 1146 test_skip("EPT AD bits not supported."); 1147 ept_enable_ad_bits(); 1148 } 1149 1150 static int apic_version; 1151 1152 static int ept_init_common(bool have_ad) 1153 { 1154 int ret; 1155 struct pci_dev pcidev; 1156 1157 /* INVEPT is required by the EPT violation handler. */ 1158 if (!is_invept_type_supported(INVEPT_SINGLE)) 1159 return VMX_TEST_EXIT; 1160 1161 if (setup_ept(have_ad)) 1162 return VMX_TEST_EXIT; 1163 1164 data_page1 = alloc_page(); 1165 data_page2 = alloc_page(); 1166 *((u32 *)data_page1) = MAGIC_VAL_1; 1167 *((u32 *)data_page2) = MAGIC_VAL_2; 1168 install_ept(pml4, (unsigned long)data_page1, (unsigned long)data_page2, 1169 EPT_RA | EPT_WA | EPT_EA); 1170 1171 apic_version = apic_read(APIC_LVR); 1172 1173 ret = pci_find_dev(PCI_VENDOR_ID_REDHAT, PCI_DEVICE_ID_REDHAT_TEST); 1174 if (ret != PCIDEVADDR_INVALID) { 1175 pci_dev_init(&pcidev, ret); 1176 pci_physaddr = pcidev.resource[PCI_TESTDEV_BAR_MEM]; 1177 } 1178 1179 return VMX_TEST_START; 1180 } 1181 1182 static int ept_init(struct vmcs *vmcs) 1183 { 1184 return ept_init_common(false); 1185 } 1186 1187 static void ept_common(void) 1188 { 1189 vmx_set_test_stage(0); 1190 if (*((u32 *)data_page2) != MAGIC_VAL_1 || 1191 *((u32 *)data_page1) != MAGIC_VAL_1) 1192 report_fail("EPT basic framework - read"); 1193 else { 1194 *((u32 *)data_page2) = MAGIC_VAL_3; 1195 vmcall(); 1196 if (vmx_get_test_stage() == 1) { 1197 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1198 *((u32 *)data_page2) == MAGIC_VAL_2) 1199 report_pass("EPT basic framework"); 1200 else 1201 report_pass("EPT basic framework - remap"); 1202 } 1203 } 1204 // Test EPT Misconfigurations 1205 vmx_set_test_stage(1); 1206 vmcall(); 1207 *((u32 *)data_page1) = MAGIC_VAL_1; 1208 if (vmx_get_test_stage() != 2) { 1209 report_fail("EPT misconfigurations"); 1210 goto t1; 1211 } 1212 vmx_set_test_stage(2); 1213 vmcall(); 1214 *((u32 *)data_page1) = MAGIC_VAL_1; 1215 report(vmx_get_test_stage() == 3, "EPT misconfigurations"); 1216 t1: 1217 // Test EPT violation 1218 vmx_set_test_stage(3); 1219 vmcall(); 1220 *((u32 *)data_page1) = MAGIC_VAL_1; 1221 report(vmx_get_test_stage() == 4, "EPT violation - page permission"); 1222 // Violation caused by EPT paging structure 1223 vmx_set_test_stage(4); 1224 vmcall(); 1225 *((u32 *)data_page1) = MAGIC_VAL_2; 1226 report(vmx_get_test_stage() == 5, "EPT violation - paging structure"); 1227 1228 // MMIO Read/Write 1229 vmx_set_test_stage(5); 1230 vmcall(); 1231 1232 *(u32 volatile *)pci_physaddr; 1233 report(vmx_get_test_stage() == 6, "MMIO EPT violation - read"); 1234 1235 *(u32 volatile *)pci_physaddr = MAGIC_VAL_1; 1236 report(vmx_get_test_stage() == 7, "MMIO EPT violation - write"); 1237 } 1238 1239 static void ept_main(void) 1240 { 1241 ept_common(); 1242 1243 // Test EPT access to L1 MMIO 1244 vmx_set_test_stage(7); 1245 report(*((u32 *)0xfee00030UL) == apic_version, "EPT - MMIO access"); 1246 1247 // Test invalid operand for INVEPT 1248 vmcall(); 1249 report(vmx_get_test_stage() == 8, "EPT - unsupported INVEPT"); 1250 } 1251 1252 static bool invept_test(int type, u64 eptp) 1253 { 1254 bool ret, supported; 1255 1256 supported = ept_vpid.val & (EPT_CAP_INVEPT_SINGLE >> INVEPT_SINGLE << type); 1257 ret = __invept(type, eptp); 1258 1259 if (ret == !supported) 1260 return false; 1261 1262 if (!supported) 1263 printf("WARNING: unsupported invept passed!\n"); 1264 else 1265 printf("WARNING: invept failed!\n"); 1266 1267 return true; 1268 } 1269 1270 static int pml_exit_handler(union exit_reason exit_reason) 1271 { 1272 u16 index, count; 1273 u64 *pmlbuf = pml_log; 1274 u64 guest_rip = vmcs_read(GUEST_RIP);; 1275 u64 guest_cr3 = vmcs_read(GUEST_CR3); 1276 u32 insn_len = vmcs_read(EXI_INST_LEN); 1277 1278 switch (exit_reason.basic) { 1279 case VMX_VMCALL: 1280 switch (vmx_get_test_stage()) { 1281 case 0: 1282 index = vmcs_read(GUEST_PML_INDEX); 1283 for (count = index + 1; count < PML_INDEX; count++) { 1284 if (pmlbuf[count] == (u64)data_page2) { 1285 vmx_inc_test_stage(); 1286 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1287 break; 1288 } 1289 } 1290 break; 1291 case 1: 1292 index = vmcs_read(GUEST_PML_INDEX); 1293 /* Keep clearing the dirty bit till a overflow */ 1294 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1295 break; 1296 default: 1297 report_fail("unexpected stage, %d.", 1298 vmx_get_test_stage()); 1299 print_vmexit_info(exit_reason); 1300 return VMX_TEST_VMEXIT; 1301 } 1302 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1303 return VMX_TEST_RESUME; 1304 case VMX_PML_FULL: 1305 vmx_inc_test_stage(); 1306 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1307 return VMX_TEST_RESUME; 1308 default: 1309 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 1310 print_vmexit_info(exit_reason); 1311 } 1312 return VMX_TEST_VMEXIT; 1313 } 1314 1315 static int ept_exit_handler_common(union exit_reason exit_reason, bool have_ad) 1316 { 1317 u64 guest_rip; 1318 u64 guest_cr3; 1319 u32 insn_len; 1320 u32 exit_qual; 1321 static unsigned long data_page1_pte, data_page1_pte_pte, memaddr_pte, 1322 guest_pte_addr; 1323 1324 guest_rip = vmcs_read(GUEST_RIP); 1325 guest_cr3 = vmcs_read(GUEST_CR3); 1326 insn_len = vmcs_read(EXI_INST_LEN); 1327 exit_qual = vmcs_read(EXI_QUALIFICATION); 1328 pteval_t *ptep; 1329 switch (exit_reason.basic) { 1330 case VMX_VMCALL: 1331 switch (vmx_get_test_stage()) { 1332 case 0: 1333 check_ept_ad(pml4, guest_cr3, 1334 (unsigned long)data_page1, 1335 have_ad ? EPT_ACCESS_FLAG : 0, 1336 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1337 check_ept_ad(pml4, guest_cr3, 1338 (unsigned long)data_page2, 1339 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0, 1340 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1341 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1342 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1343 if (have_ad) 1344 invept(INVEPT_SINGLE, eptp); 1345 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1346 *((u32 *)data_page2) == MAGIC_VAL_2) { 1347 vmx_inc_test_stage(); 1348 install_ept(pml4, (unsigned long)data_page2, 1349 (unsigned long)data_page2, 1350 EPT_RA | EPT_WA | EPT_EA); 1351 } else 1352 report_fail("EPT basic framework - write"); 1353 break; 1354 case 1: 1355 install_ept(pml4, (unsigned long)data_page1, 1356 (unsigned long)data_page1, EPT_WA); 1357 invept(INVEPT_SINGLE, eptp); 1358 break; 1359 case 2: 1360 install_ept(pml4, (unsigned long)data_page1, 1361 (unsigned long)data_page1, 1362 EPT_RA | EPT_WA | EPT_EA | 1363 (2 << EPT_MEM_TYPE_SHIFT)); 1364 invept(INVEPT_SINGLE, eptp); 1365 break; 1366 case 3: 1367 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1368 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)data_page1, 1369 1, &data_page1_pte)); 1370 set_ept_pte(pml4, (unsigned long)data_page1, 1371 1, data_page1_pte & ~EPT_PRESENT); 1372 invept(INVEPT_SINGLE, eptp); 1373 break; 1374 case 4: 1375 ptep = get_pte_level((pgd_t *)guest_cr3, data_page1, /*level=*/2); 1376 guest_pte_addr = virt_to_phys(ptep) & PAGE_MASK; 1377 1378 TEST_ASSERT(get_ept_pte(pml4, guest_pte_addr, 2, &data_page1_pte_pte)); 1379 set_ept_pte(pml4, guest_pte_addr, 2, 1380 data_page1_pte_pte & ~EPT_PRESENT); 1381 invept(INVEPT_SINGLE, eptp); 1382 break; 1383 case 5: 1384 install_ept(pml4, (unsigned long)pci_physaddr, 1385 (unsigned long)pci_physaddr, 0); 1386 invept(INVEPT_SINGLE, eptp); 1387 break; 1388 case 7: 1389 if (!invept_test(0, eptp)) 1390 vmx_inc_test_stage(); 1391 break; 1392 // Should not reach here 1393 default: 1394 report_fail("ERROR - unexpected stage, %d.", 1395 vmx_get_test_stage()); 1396 print_vmexit_info(exit_reason); 1397 return VMX_TEST_VMEXIT; 1398 } 1399 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1400 return VMX_TEST_RESUME; 1401 case VMX_EPT_MISCONFIG: 1402 switch (vmx_get_test_stage()) { 1403 case 1: 1404 case 2: 1405 vmx_inc_test_stage(); 1406 install_ept(pml4, (unsigned long)data_page1, 1407 (unsigned long)data_page1, 1408 EPT_RA | EPT_WA | EPT_EA); 1409 invept(INVEPT_SINGLE, eptp); 1410 break; 1411 // Should not reach here 1412 default: 1413 report_fail("ERROR - unexpected stage, %d.", 1414 vmx_get_test_stage()); 1415 print_vmexit_info(exit_reason); 1416 return VMX_TEST_VMEXIT; 1417 } 1418 return VMX_TEST_RESUME; 1419 case VMX_EPT_VIOLATION: 1420 /* 1421 * Exit-qualifications are masked not to account for advanced 1422 * VM-exit information. Once KVM supports this feature, this 1423 * masking should be removed. 1424 */ 1425 exit_qual &= ~EPT_VLT_GUEST_MASK; 1426 1427 switch(vmx_get_test_stage()) { 1428 case 3: 1429 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1430 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1431 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1432 if (exit_qual == (EPT_VLT_WR | EPT_VLT_LADDR_VLD | 1433 EPT_VLT_PADDR)) 1434 vmx_inc_test_stage(); 1435 set_ept_pte(pml4, (unsigned long)data_page1, 1436 1, data_page1_pte | (EPT_PRESENT)); 1437 invept(INVEPT_SINGLE, eptp); 1438 break; 1439 case 4: 1440 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1441 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1442 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1443 if (exit_qual == (EPT_VLT_RD | 1444 (have_ad ? EPT_VLT_WR : 0) | 1445 EPT_VLT_LADDR_VLD)) 1446 vmx_inc_test_stage(); 1447 set_ept_pte(pml4, guest_pte_addr, 2, 1448 data_page1_pte_pte | (EPT_PRESENT)); 1449 invept(INVEPT_SINGLE, eptp); 1450 break; 1451 case 5: 1452 if (exit_qual & EPT_VLT_RD) 1453 vmx_inc_test_stage(); 1454 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1455 1, &memaddr_pte)); 1456 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA); 1457 invept(INVEPT_SINGLE, eptp); 1458 break; 1459 case 6: 1460 if (exit_qual & EPT_VLT_WR) 1461 vmx_inc_test_stage(); 1462 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1463 1, &memaddr_pte)); 1464 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA | EPT_WA); 1465 invept(INVEPT_SINGLE, eptp); 1466 break; 1467 default: 1468 // Should not reach here 1469 report_fail("ERROR : unexpected stage, %d", 1470 vmx_get_test_stage()); 1471 print_vmexit_info(exit_reason); 1472 return VMX_TEST_VMEXIT; 1473 } 1474 return VMX_TEST_RESUME; 1475 default: 1476 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 1477 print_vmexit_info(exit_reason); 1478 } 1479 return VMX_TEST_VMEXIT; 1480 } 1481 1482 static int ept_exit_handler(union exit_reason exit_reason) 1483 { 1484 return ept_exit_handler_common(exit_reason, false); 1485 } 1486 1487 static int eptad_init(struct vmcs *vmcs) 1488 { 1489 int r = ept_init_common(true); 1490 1491 if (r == VMX_TEST_EXIT) 1492 return r; 1493 1494 if (!ept_ad_bits_supported()) { 1495 printf("\tEPT A/D bits are not supported"); 1496 return VMX_TEST_EXIT; 1497 } 1498 1499 return r; 1500 } 1501 1502 static int pml_init(struct vmcs *vmcs) 1503 { 1504 u32 ctrl_cpu; 1505 int r = eptad_init(vmcs); 1506 1507 if (r == VMX_TEST_EXIT) 1508 return r; 1509 1510 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1511 !(ctrl_cpu_rev[1].clr & CPU_PML)) { 1512 printf("\tPML is not supported"); 1513 return VMX_TEST_EXIT; 1514 } 1515 1516 pml_log = alloc_page(); 1517 vmcs_write(PMLADDR, (u64)pml_log); 1518 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1519 1520 ctrl_cpu = vmcs_read(CPU_EXEC_CTRL1) | CPU_PML; 1521 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu); 1522 1523 return VMX_TEST_START; 1524 } 1525 1526 static void pml_main(void) 1527 { 1528 int count = 0; 1529 1530 vmx_set_test_stage(0); 1531 *((u32 *)data_page2) = 0x1; 1532 vmcall(); 1533 report(vmx_get_test_stage() == 1, "PML - Dirty GPA Logging"); 1534 1535 while (vmx_get_test_stage() == 1) { 1536 vmcall(); 1537 *((u32 *)data_page2) = 0x1; 1538 if (count++ > PML_INDEX) 1539 break; 1540 } 1541 report(vmx_get_test_stage() == 2, "PML Full Event"); 1542 } 1543 1544 static void eptad_main(void) 1545 { 1546 ept_common(); 1547 } 1548 1549 static int eptad_exit_handler(union exit_reason exit_reason) 1550 { 1551 return ept_exit_handler_common(exit_reason, true); 1552 } 1553 1554 #define TIMER_VECTOR 222 1555 1556 static volatile bool timer_fired; 1557 1558 static void timer_isr(isr_regs_t *regs) 1559 { 1560 timer_fired = true; 1561 apic_write(APIC_EOI, 0); 1562 } 1563 1564 static int interrupt_init(struct vmcs *vmcs) 1565 { 1566 msr_bmp_init(); 1567 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1568 handle_irq(TIMER_VECTOR, timer_isr); 1569 return VMX_TEST_START; 1570 } 1571 1572 static void interrupt_main(void) 1573 { 1574 long long start, loops; 1575 1576 vmx_set_test_stage(0); 1577 1578 apic_write(APIC_LVTT, TIMER_VECTOR); 1579 sti(); 1580 1581 apic_write(APIC_TMICT, 1); 1582 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1583 asm volatile ("nop"); 1584 report(timer_fired, "direct interrupt while running guest"); 1585 1586 apic_write(APIC_TMICT, 0); 1587 cli(); 1588 vmcall(); 1589 timer_fired = false; 1590 apic_write(APIC_TMICT, 1); 1591 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1592 asm volatile ("nop"); 1593 report(timer_fired, "intercepted interrupt while running guest"); 1594 1595 sti(); 1596 apic_write(APIC_TMICT, 0); 1597 cli(); 1598 vmcall(); 1599 timer_fired = false; 1600 start = rdtsc(); 1601 apic_write(APIC_TMICT, 1000000); 1602 1603 safe_halt(); 1604 1605 report(rdtsc() - start > 1000000 && timer_fired, 1606 "direct interrupt + hlt"); 1607 1608 apic_write(APIC_TMICT, 0); 1609 cli(); 1610 vmcall(); 1611 timer_fired = false; 1612 start = rdtsc(); 1613 apic_write(APIC_TMICT, 1000000); 1614 1615 safe_halt(); 1616 1617 report(rdtsc() - start > 10000 && timer_fired, 1618 "intercepted interrupt + hlt"); 1619 1620 apic_write(APIC_TMICT, 0); 1621 cli(); 1622 vmcall(); 1623 timer_fired = false; 1624 start = rdtsc(); 1625 apic_write(APIC_TMICT, 1000000); 1626 1627 sti_nop(); 1628 vmcall(); 1629 1630 report(rdtsc() - start > 10000 && timer_fired, 1631 "direct interrupt + activity state hlt"); 1632 1633 apic_write(APIC_TMICT, 0); 1634 cli(); 1635 vmcall(); 1636 timer_fired = false; 1637 start = rdtsc(); 1638 apic_write(APIC_TMICT, 1000000); 1639 1640 sti_nop(); 1641 vmcall(); 1642 1643 report(rdtsc() - start > 10000 && timer_fired, 1644 "intercepted interrupt + activity state hlt"); 1645 1646 apic_write(APIC_TMICT, 0); 1647 cli(); 1648 vmx_set_test_stage(7); 1649 vmcall(); 1650 timer_fired = false; 1651 apic_write(APIC_TMICT, 1); 1652 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1653 asm volatile ("nop"); 1654 report(timer_fired, 1655 "running a guest with interrupt acknowledgement set"); 1656 1657 apic_write(APIC_TMICT, 0); 1658 sti(); 1659 timer_fired = false; 1660 vmcall(); 1661 report(timer_fired, "Inject an event to a halted guest"); 1662 } 1663 1664 static int interrupt_exit_handler(union exit_reason exit_reason) 1665 { 1666 u64 guest_rip = vmcs_read(GUEST_RIP); 1667 u32 insn_len = vmcs_read(EXI_INST_LEN); 1668 1669 switch (exit_reason.basic) { 1670 case VMX_VMCALL: 1671 switch (vmx_get_test_stage()) { 1672 case 0: 1673 case 2: 1674 case 5: 1675 vmcs_write(PIN_CONTROLS, 1676 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1677 break; 1678 case 7: 1679 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_INTA); 1680 vmcs_write(PIN_CONTROLS, 1681 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1682 break; 1683 case 1: 1684 case 3: 1685 vmcs_write(PIN_CONTROLS, 1686 vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1687 break; 1688 case 4: 1689 case 6: 1690 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1691 break; 1692 1693 case 8: 1694 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1695 vmcs_write(ENT_INTR_INFO, 1696 TIMER_VECTOR | 1697 (VMX_INTR_TYPE_EXT_INTR << INTR_INFO_INTR_TYPE_SHIFT) | 1698 INTR_INFO_VALID_MASK); 1699 break; 1700 } 1701 vmx_inc_test_stage(); 1702 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1703 return VMX_TEST_RESUME; 1704 case VMX_EXTINT: 1705 if (vmcs_read(EXI_CONTROLS) & EXI_INTA) { 1706 int vector = vmcs_read(EXI_INTR_INFO) & 0xff; 1707 handle_external_interrupt(vector); 1708 } else { 1709 sti_nop_cli(); 1710 } 1711 if (vmx_get_test_stage() >= 2) 1712 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 1713 return VMX_TEST_RESUME; 1714 default: 1715 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 1716 print_vmexit_info(exit_reason); 1717 } 1718 1719 return VMX_TEST_VMEXIT; 1720 } 1721 1722 1723 static volatile int nmi_fired; 1724 1725 #define NMI_DELAY 100000000ULL 1726 1727 static void nmi_isr(isr_regs_t *regs) 1728 { 1729 nmi_fired = true; 1730 } 1731 1732 static int nmi_hlt_init(struct vmcs *vmcs) 1733 { 1734 msr_bmp_init(); 1735 handle_irq(NMI_VECTOR, nmi_isr); 1736 vmcs_write(PIN_CONTROLS, 1737 vmcs_read(PIN_CONTROLS) & ~PIN_NMI); 1738 vmcs_write(PIN_CONTROLS, 1739 vmcs_read(PIN_CONTROLS) & ~PIN_VIRT_NMI); 1740 return VMX_TEST_START; 1741 } 1742 1743 static void nmi_message_thread(void *data) 1744 { 1745 while (vmx_get_test_stage() != 1) 1746 pause(); 1747 1748 delay(NMI_DELAY); 1749 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_NMI | APIC_INT_ASSERT, id_map[0]); 1750 1751 while (vmx_get_test_stage() != 2) 1752 pause(); 1753 1754 delay(NMI_DELAY); 1755 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_NMI | APIC_INT_ASSERT, id_map[0]); 1756 } 1757 1758 static void nmi_hlt_main(void) 1759 { 1760 long long start; 1761 1762 if (cpu_count() < 2) { 1763 report_skip("%s : CPU count < 2", __func__); 1764 vmx_set_test_stage(-1); 1765 return; 1766 } 1767 1768 vmx_set_test_stage(0); 1769 on_cpu_async(1, nmi_message_thread, NULL); 1770 start = rdtsc(); 1771 vmx_set_test_stage(1); 1772 asm volatile ("hlt"); 1773 report((rdtsc() - start > NMI_DELAY) && nmi_fired, 1774 "direct NMI + hlt"); 1775 if (!nmi_fired) 1776 vmx_set_test_stage(-1); 1777 nmi_fired = false; 1778 1779 vmcall(); 1780 1781 start = rdtsc(); 1782 vmx_set_test_stage(2); 1783 asm volatile ("hlt"); 1784 report((rdtsc() - start > NMI_DELAY) && !nmi_fired, 1785 "intercepted NMI + hlt"); 1786 if (nmi_fired) { 1787 report(!nmi_fired, "intercepted NMI was dispatched"); 1788 vmx_set_test_stage(-1); 1789 return; 1790 } 1791 vmx_set_test_stage(3); 1792 } 1793 1794 static int nmi_hlt_exit_handler(union exit_reason exit_reason) 1795 { 1796 u64 guest_rip = vmcs_read(GUEST_RIP); 1797 u32 insn_len = vmcs_read(EXI_INST_LEN); 1798 1799 switch (vmx_get_test_stage()) { 1800 case 1: 1801 if (exit_reason.basic != VMX_VMCALL) { 1802 report_fail("VMEXIT not due to vmcall. Exit reason 0x%x", 1803 exit_reason.full); 1804 print_vmexit_info(exit_reason); 1805 return VMX_TEST_VMEXIT; 1806 } 1807 1808 vmcs_write(PIN_CONTROLS, 1809 vmcs_read(PIN_CONTROLS) | PIN_NMI); 1810 vmcs_write(PIN_CONTROLS, 1811 vmcs_read(PIN_CONTROLS) | PIN_VIRT_NMI); 1812 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1813 break; 1814 1815 case 2: 1816 if (exit_reason.basic != VMX_EXC_NMI) { 1817 report_fail("VMEXIT not due to NMI intercept. Exit reason 0x%x", 1818 exit_reason.full); 1819 print_vmexit_info(exit_reason); 1820 return VMX_TEST_VMEXIT; 1821 } 1822 report_pass("NMI intercept while running guest"); 1823 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 1824 break; 1825 1826 case 3: 1827 break; 1828 1829 default: 1830 return VMX_TEST_VMEXIT; 1831 } 1832 1833 if (vmx_get_test_stage() == 3) 1834 return VMX_TEST_VMEXIT; 1835 1836 return VMX_TEST_RESUME; 1837 } 1838 1839 1840 static int dbgctls_init(struct vmcs *vmcs) 1841 { 1842 u64 dr7 = 0x402; 1843 u64 zero = 0; 1844 1845 msr_bmp_init(); 1846 asm volatile( 1847 "mov %0,%%dr0\n\t" 1848 "mov %0,%%dr1\n\t" 1849 "mov %0,%%dr2\n\t" 1850 "mov %1,%%dr7\n\t" 1851 : : "r" (zero), "r" (dr7)); 1852 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1853 vmcs_write(GUEST_DR7, 0x404); 1854 vmcs_write(GUEST_DEBUGCTL, 0x2); 1855 1856 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 1857 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_SAVE_DBGCTLS); 1858 1859 return VMX_TEST_START; 1860 } 1861 1862 static void dbgctls_main(void) 1863 { 1864 u64 dr7, debugctl; 1865 1866 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1867 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1868 /* Commented out: KVM does not support DEBUGCTL so far */ 1869 (void)debugctl; 1870 report(dr7 == 0x404, "Load debug controls" /* && debugctl == 0x2 */); 1871 1872 dr7 = 0x408; 1873 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1874 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1875 1876 vmx_set_test_stage(0); 1877 vmcall(); 1878 report(vmx_get_test_stage() == 1, "Save debug controls"); 1879 1880 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS || 1881 ctrl_exit_rev.set & EXI_SAVE_DBGCTLS) { 1882 printf("\tDebug controls are always loaded/saved\n"); 1883 return; 1884 } 1885 vmx_set_test_stage(2); 1886 vmcall(); 1887 1888 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1889 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1890 /* Commented out: KVM does not support DEBUGCTL so far */ 1891 (void)debugctl; 1892 report(dr7 == 0x402, 1893 "Guest=host debug controls" /* && debugctl == 0x1 */); 1894 1895 dr7 = 0x408; 1896 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1897 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1898 1899 vmx_set_test_stage(3); 1900 vmcall(); 1901 report(vmx_get_test_stage() == 4, "Don't save debug controls"); 1902 } 1903 1904 static int dbgctls_exit_handler(union exit_reason exit_reason) 1905 { 1906 u32 insn_len = vmcs_read(EXI_INST_LEN); 1907 u64 guest_rip = vmcs_read(GUEST_RIP); 1908 u64 dr7, debugctl; 1909 1910 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1911 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1912 1913 switch (exit_reason.basic) { 1914 case VMX_VMCALL: 1915 switch (vmx_get_test_stage()) { 1916 case 0: 1917 if (dr7 == 0x400 && debugctl == 0 && 1918 vmcs_read(GUEST_DR7) == 0x408 /* && 1919 Commented out: KVM does not support DEBUGCTL so far 1920 vmcs_read(GUEST_DEBUGCTL) == 0x3 */) 1921 vmx_inc_test_stage(); 1922 break; 1923 case 2: 1924 dr7 = 0x402; 1925 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1926 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1927 vmcs_write(GUEST_DR7, 0x404); 1928 vmcs_write(GUEST_DEBUGCTL, 0x2); 1929 1930 vmcs_write(ENT_CONTROLS, 1931 vmcs_read(ENT_CONTROLS) & ~ENT_LOAD_DBGCTLS); 1932 vmcs_write(EXI_CONTROLS, 1933 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_DBGCTLS); 1934 break; 1935 case 3: 1936 if (dr7 == 0x400 && debugctl == 0 && 1937 vmcs_read(GUEST_DR7) == 0x404 /* && 1938 Commented out: KVM does not support DEBUGCTL so far 1939 vmcs_read(GUEST_DEBUGCTL) == 0x2 */) 1940 vmx_inc_test_stage(); 1941 break; 1942 } 1943 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1944 return VMX_TEST_RESUME; 1945 default: 1946 report_fail("Unknown exit reason, %d", exit_reason.full); 1947 print_vmexit_info(exit_reason); 1948 } 1949 return VMX_TEST_VMEXIT; 1950 } 1951 1952 struct vmx_msr_entry { 1953 u32 index; 1954 u32 reserved; 1955 u64 value; 1956 } __attribute__((packed)); 1957 1958 #define MSR_MAGIC 0x31415926 1959 struct vmx_msr_entry *exit_msr_store, *entry_msr_load, *exit_msr_load; 1960 1961 static int msr_switch_init(struct vmcs *vmcs) 1962 { 1963 msr_bmp_init(); 1964 exit_msr_store = alloc_page(); 1965 exit_msr_load = alloc_page(); 1966 entry_msr_load = alloc_page(); 1967 entry_msr_load[0].index = MSR_KERNEL_GS_BASE; 1968 entry_msr_load[0].value = MSR_MAGIC; 1969 1970 vmx_set_test_stage(1); 1971 vmcs_write(ENT_MSR_LD_CNT, 1); 1972 vmcs_write(ENTER_MSR_LD_ADDR, (u64)entry_msr_load); 1973 vmcs_write(EXI_MSR_ST_CNT, 1); 1974 vmcs_write(EXIT_MSR_ST_ADDR, (u64)exit_msr_store); 1975 vmcs_write(EXI_MSR_LD_CNT, 1); 1976 vmcs_write(EXIT_MSR_LD_ADDR, (u64)exit_msr_load); 1977 return VMX_TEST_START; 1978 } 1979 1980 static void msr_switch_main(void) 1981 { 1982 if (vmx_get_test_stage() == 1) { 1983 report(rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC, 1984 "VM entry MSR load"); 1985 vmx_set_test_stage(2); 1986 wrmsr(MSR_KERNEL_GS_BASE, MSR_MAGIC + 1); 1987 exit_msr_store[0].index = MSR_KERNEL_GS_BASE; 1988 exit_msr_load[0].index = MSR_KERNEL_GS_BASE; 1989 exit_msr_load[0].value = MSR_MAGIC + 2; 1990 } 1991 vmcall(); 1992 } 1993 1994 static int msr_switch_exit_handler(union exit_reason exit_reason) 1995 { 1996 if (exit_reason.basic == VMX_VMCALL && vmx_get_test_stage() == 2) { 1997 report(exit_msr_store[0].value == MSR_MAGIC + 1, 1998 "VM exit MSR store"); 1999 report(rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC + 2, 2000 "VM exit MSR load"); 2001 vmx_set_test_stage(3); 2002 entry_msr_load[0].index = MSR_FS_BASE; 2003 return VMX_TEST_RESUME; 2004 } 2005 printf("ERROR %s: unexpected stage=%u or reason=0x%x\n", 2006 __func__, vmx_get_test_stage(), exit_reason.full); 2007 return VMX_TEST_EXIT; 2008 } 2009 2010 static int msr_switch_entry_failure(struct vmentry_result *result) 2011 { 2012 if (result->vm_fail) { 2013 printf("ERROR %s: VM-Fail on %s\n", __func__, result->instr); 2014 return VMX_TEST_EXIT; 2015 } 2016 2017 if (result->exit_reason.failed_vmentry && 2018 result->exit_reason.basic == VMX_FAIL_MSR && 2019 vmx_get_test_stage() == 3) { 2020 report(vmcs_read(EXI_QUALIFICATION) == 1, 2021 "VM entry MSR load: try to load FS_BASE"); 2022 return VMX_TEST_VMEXIT; 2023 } 2024 printf("ERROR %s: unexpected stage=%u or reason=%x\n", 2025 __func__, vmx_get_test_stage(), result->exit_reason.full); 2026 return VMX_TEST_EXIT; 2027 } 2028 2029 static int vmmcall_init(struct vmcs *vmcs) 2030 { 2031 vmcs_write(EXC_BITMAP, 1 << UD_VECTOR); 2032 return VMX_TEST_START; 2033 } 2034 2035 static void vmmcall_main(void) 2036 { 2037 asm volatile( 2038 "mov $0xABCD, %%rax\n\t" 2039 "vmmcall\n\t" 2040 ::: "rax"); 2041 2042 report_fail("VMMCALL"); 2043 } 2044 2045 static int vmmcall_exit_handler(union exit_reason exit_reason) 2046 { 2047 switch (exit_reason.basic) { 2048 case VMX_VMCALL: 2049 printf("here\n"); 2050 report_fail("VMMCALL triggers #UD"); 2051 break; 2052 case VMX_EXC_NMI: 2053 report((vmcs_read(EXI_INTR_INFO) & 0xff) == UD_VECTOR, 2054 "VMMCALL triggers #UD"); 2055 break; 2056 default: 2057 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 2058 print_vmexit_info(exit_reason); 2059 } 2060 2061 return VMX_TEST_VMEXIT; 2062 } 2063 2064 static int disable_rdtscp_init(struct vmcs *vmcs) 2065 { 2066 u32 ctrl_cpu1; 2067 2068 if (ctrl_cpu_rev[0].clr & CPU_SECONDARY) { 2069 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 2070 ctrl_cpu1 &= ~CPU_RDTSCP; 2071 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 2072 } 2073 2074 return VMX_TEST_START; 2075 } 2076 2077 static void disable_rdtscp_ud_handler(struct ex_regs *regs) 2078 { 2079 switch (vmx_get_test_stage()) { 2080 case 0: 2081 report_pass("RDTSCP triggers #UD"); 2082 vmx_inc_test_stage(); 2083 regs->rip += 3; 2084 break; 2085 case 2: 2086 report_pass("RDPID triggers #UD"); 2087 vmx_inc_test_stage(); 2088 regs->rip += 4; 2089 break; 2090 } 2091 return; 2092 2093 } 2094 2095 static void disable_rdtscp_main(void) 2096 { 2097 /* Test that #UD is properly injected in L2. */ 2098 handle_exception(UD_VECTOR, disable_rdtscp_ud_handler); 2099 2100 vmx_set_test_stage(0); 2101 asm volatile("rdtscp" : : : "eax", "ecx", "edx"); 2102 vmcall(); 2103 asm volatile(".byte 0xf3, 0x0f, 0xc7, 0xf8" : : : "eax"); 2104 2105 handle_exception(UD_VECTOR, 0); 2106 vmcall(); 2107 } 2108 2109 static int disable_rdtscp_exit_handler(union exit_reason exit_reason) 2110 { 2111 switch (exit_reason.basic) { 2112 case VMX_VMCALL: 2113 switch (vmx_get_test_stage()) { 2114 case 0: 2115 report_fail("RDTSCP triggers #UD"); 2116 vmx_inc_test_stage(); 2117 /* fallthrough */ 2118 case 1: 2119 vmx_inc_test_stage(); 2120 vmcs_write(GUEST_RIP, vmcs_read(GUEST_RIP) + 3); 2121 return VMX_TEST_RESUME; 2122 case 2: 2123 report_fail("RDPID triggers #UD"); 2124 break; 2125 } 2126 break; 2127 2128 default: 2129 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 2130 print_vmexit_info(exit_reason); 2131 } 2132 return VMX_TEST_VMEXIT; 2133 } 2134 2135 static void exit_monitor_from_l2_main(void) 2136 { 2137 printf("Calling exit(0) from l2...\n"); 2138 exit(0); 2139 } 2140 2141 static int exit_monitor_from_l2_handler(union exit_reason exit_reason) 2142 { 2143 report_fail("The guest should have killed the VMM"); 2144 return VMX_TEST_EXIT; 2145 } 2146 2147 static void assert_exit_reason(u64 expected) 2148 { 2149 u64 actual = vmcs_read(EXI_REASON); 2150 2151 TEST_ASSERT_EQ_MSG(expected, actual, "Expected %s, got %s.", 2152 exit_reason_description(expected), 2153 exit_reason_description(actual)); 2154 } 2155 2156 static void skip_exit_insn(void) 2157 { 2158 u64 guest_rip = vmcs_read(GUEST_RIP); 2159 u32 insn_len = vmcs_read(EXI_INST_LEN); 2160 vmcs_write(GUEST_RIP, guest_rip + insn_len); 2161 } 2162 2163 static void skip_exit_vmcall(void) 2164 { 2165 assert_exit_reason(VMX_VMCALL); 2166 skip_exit_insn(); 2167 } 2168 2169 static void v2_null_test_guest(void) 2170 { 2171 } 2172 2173 static void v2_null_test(void) 2174 { 2175 test_set_guest(v2_null_test_guest); 2176 enter_guest(); 2177 report_pass(__func__); 2178 } 2179 2180 static void v2_multiple_entries_test_guest(void) 2181 { 2182 vmx_set_test_stage(1); 2183 vmcall(); 2184 vmx_set_test_stage(2); 2185 } 2186 2187 static void v2_multiple_entries_test(void) 2188 { 2189 test_set_guest(v2_multiple_entries_test_guest); 2190 enter_guest(); 2191 TEST_ASSERT_EQ(vmx_get_test_stage(), 1); 2192 skip_exit_vmcall(); 2193 enter_guest(); 2194 TEST_ASSERT_EQ(vmx_get_test_stage(), 2); 2195 report_pass(__func__); 2196 } 2197 2198 static int fixture_test_data = 1; 2199 2200 static void fixture_test_teardown(void *data) 2201 { 2202 *((int *) data) = 1; 2203 } 2204 2205 static void fixture_test_guest(void) 2206 { 2207 fixture_test_data++; 2208 } 2209 2210 2211 static void fixture_test_setup(void) 2212 { 2213 TEST_ASSERT_EQ_MSG(1, fixture_test_data, 2214 "fixture_test_teardown didn't run?!"); 2215 fixture_test_data = 2; 2216 test_add_teardown(fixture_test_teardown, &fixture_test_data); 2217 test_set_guest(fixture_test_guest); 2218 } 2219 2220 static void fixture_test_case1(void) 2221 { 2222 fixture_test_setup(); 2223 TEST_ASSERT_EQ(2, fixture_test_data); 2224 enter_guest(); 2225 TEST_ASSERT_EQ(3, fixture_test_data); 2226 report_pass(__func__); 2227 } 2228 2229 static void fixture_test_case2(void) 2230 { 2231 fixture_test_setup(); 2232 TEST_ASSERT_EQ(2, fixture_test_data); 2233 enter_guest(); 2234 TEST_ASSERT_EQ(3, fixture_test_data); 2235 report_pass(__func__); 2236 } 2237 2238 enum ept_access_op { 2239 OP_READ, 2240 OP_WRITE, 2241 OP_EXEC, 2242 OP_FLUSH_TLB, 2243 OP_EXIT, 2244 }; 2245 2246 static struct ept_access_test_data { 2247 unsigned long gpa; 2248 unsigned long *gva; 2249 unsigned long hpa; 2250 unsigned long *hva; 2251 enum ept_access_op op; 2252 } ept_access_test_data; 2253 2254 extern unsigned char ret42_start; 2255 extern unsigned char ret42_end; 2256 2257 /* Returns 42. */ 2258 asm( 2259 ".align 64\n" 2260 "ret42_start:\n" 2261 "mov $42, %eax\n" 2262 "ret\n" 2263 "ret42_end:\n" 2264 ); 2265 2266 static void 2267 diagnose_ept_violation_qual(u64 expected, u64 actual) 2268 { 2269 2270 #define DIAGNOSE(flag) \ 2271 do { \ 2272 if ((expected & flag) != (actual & flag)) \ 2273 printf(#flag " %sexpected\n", \ 2274 (expected & flag) ? "" : "un"); \ 2275 } while (0) 2276 2277 DIAGNOSE(EPT_VLT_RD); 2278 DIAGNOSE(EPT_VLT_WR); 2279 DIAGNOSE(EPT_VLT_FETCH); 2280 DIAGNOSE(EPT_VLT_PERM_RD); 2281 DIAGNOSE(EPT_VLT_PERM_WR); 2282 DIAGNOSE(EPT_VLT_PERM_EX); 2283 DIAGNOSE(EPT_VLT_LADDR_VLD); 2284 DIAGNOSE(EPT_VLT_PADDR); 2285 2286 #undef DIAGNOSE 2287 } 2288 2289 static void do_ept_access_op(enum ept_access_op op) 2290 { 2291 ept_access_test_data.op = op; 2292 enter_guest(); 2293 } 2294 2295 /* 2296 * Force the guest to flush its TLB (i.e., flush gva -> gpa mappings). Only 2297 * needed by tests that modify guest PTEs. 2298 */ 2299 static void ept_access_test_guest_flush_tlb(void) 2300 { 2301 do_ept_access_op(OP_FLUSH_TLB); 2302 skip_exit_vmcall(); 2303 } 2304 2305 /* 2306 * Modifies the EPT entry at @level in the mapping of @gpa. First clears the 2307 * bits in @clear then sets the bits in @set. @mkhuge transforms the entry into 2308 * a huge page. 2309 */ 2310 static unsigned long ept_twiddle(unsigned long gpa, bool mkhuge, int level, 2311 unsigned long clear, unsigned long set) 2312 { 2313 struct ept_access_test_data *data = &ept_access_test_data; 2314 unsigned long orig_pte; 2315 unsigned long pte; 2316 2317 /* Screw with the mapping at the requested level. */ 2318 TEST_ASSERT(get_ept_pte(pml4, gpa, level, &orig_pte)); 2319 pte = orig_pte; 2320 if (mkhuge) 2321 pte = (orig_pte & ~EPT_ADDR_MASK) | data->hpa | EPT_LARGE_PAGE; 2322 else 2323 pte = orig_pte; 2324 pte = (pte & ~clear) | set; 2325 set_ept_pte(pml4, gpa, level, pte); 2326 invept(INVEPT_SINGLE, eptp); 2327 2328 return orig_pte; 2329 } 2330 2331 static void ept_untwiddle(unsigned long gpa, int level, unsigned long orig_pte) 2332 { 2333 set_ept_pte(pml4, gpa, level, orig_pte); 2334 invept(INVEPT_SINGLE, eptp); 2335 } 2336 2337 static void do_ept_violation(bool leaf, enum ept_access_op op, 2338 u64 expected_qual, u64 expected_paddr) 2339 { 2340 u64 qual; 2341 2342 /* Try the access and observe the violation. */ 2343 do_ept_access_op(op); 2344 2345 assert_exit_reason(VMX_EPT_VIOLATION); 2346 2347 qual = vmcs_read(EXI_QUALIFICATION); 2348 2349 /* Mask undefined bits (which may later be defined in certain cases). */ 2350 qual &= ~(EPT_VLT_GUEST_USER | EPT_VLT_GUEST_RW | EPT_VLT_GUEST_EX | 2351 EPT_VLT_PERM_USER_EX); 2352 2353 diagnose_ept_violation_qual(expected_qual, qual); 2354 TEST_EXPECT_EQ(expected_qual, qual); 2355 2356 #if 0 2357 /* Disable for now otherwise every test will fail */ 2358 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2359 (unsigned long) ( 2360 op == OP_EXEC ? data->gva + 1 : data->gva)); 2361 #endif 2362 /* 2363 * TODO: tests that probe expected_paddr in pages other than the one at 2364 * the beginning of the 1g region. 2365 */ 2366 TEST_EXPECT_EQ(vmcs_read(INFO_PHYS_ADDR), expected_paddr); 2367 } 2368 2369 static void 2370 ept_violation_at_level_mkhuge(bool mkhuge, int level, unsigned long clear, 2371 unsigned long set, enum ept_access_op op, 2372 u64 expected_qual) 2373 { 2374 struct ept_access_test_data *data = &ept_access_test_data; 2375 unsigned long orig_pte; 2376 2377 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2378 2379 do_ept_violation(level == 1 || mkhuge, op, expected_qual, 2380 op == OP_EXEC ? data->gpa + sizeof(unsigned long) : 2381 data->gpa); 2382 2383 /* Fix the violation and resume the op loop. */ 2384 ept_untwiddle(data->gpa, level, orig_pte); 2385 enter_guest(); 2386 skip_exit_vmcall(); 2387 } 2388 2389 static void 2390 ept_violation_at_level(int level, unsigned long clear, unsigned long set, 2391 enum ept_access_op op, u64 expected_qual) 2392 { 2393 ept_violation_at_level_mkhuge(false, level, clear, set, op, 2394 expected_qual); 2395 if (ept_huge_pages_supported(level)) 2396 ept_violation_at_level_mkhuge(true, level, clear, set, op, 2397 expected_qual); 2398 } 2399 2400 static void ept_violation(unsigned long clear, unsigned long set, 2401 enum ept_access_op op, u64 expected_qual) 2402 { 2403 ept_violation_at_level(1, clear, set, op, expected_qual); 2404 ept_violation_at_level(2, clear, set, op, expected_qual); 2405 ept_violation_at_level(3, clear, set, op, expected_qual); 2406 ept_violation_at_level(4, clear, set, op, expected_qual); 2407 } 2408 2409 static void ept_access_violation(unsigned long access, enum ept_access_op op, 2410 u64 expected_qual) 2411 { 2412 ept_violation(EPT_PRESENT, access, op, 2413 expected_qual | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2414 } 2415 2416 /* 2417 * For translations that don't involve a GVA, that is physical address (paddr) 2418 * accesses, EPT violations don't set the flag EPT_VLT_PADDR. For a typical 2419 * guest memory access, the hardware does GVA -> GPA -> HPA. However, certain 2420 * translations don't involve GVAs, such as when the hardware does the guest 2421 * page table walk. For example, in translating GVA_1 -> GPA_1, the guest MMU 2422 * might try to set an A bit on a guest PTE. If the GPA_2 that the PTE resides 2423 * on isn't present in the EPT, then the EPT violation will be for GPA_2 and 2424 * the EPT_VLT_PADDR bit will be clear in the exit qualification. 2425 * 2426 * Note that paddr violations can also be triggered by loading PAE page tables 2427 * with wonky addresses. We don't test that yet. 2428 * 2429 * This function modifies the EPT entry that maps the GPA that the guest page 2430 * table entry mapping ept_access_test_data.gva resides on. 2431 * 2432 * @ept_access EPT permissions to set. Other permissions are cleared. 2433 * 2434 * @pte_ad Set the A/D bits on the guest PTE accordingly. 2435 * 2436 * @op Guest operation to perform with 2437 * ept_access_test_data.gva. 2438 * 2439 * @expect_violation 2440 * Is a violation expected during the paddr access? 2441 * 2442 * @expected_qual Expected qualification for the EPT violation. 2443 * EPT_VLT_PADDR should be clear. 2444 */ 2445 static void ept_access_paddr(unsigned long ept_access, unsigned long pte_ad, 2446 enum ept_access_op op, bool expect_violation, 2447 u64 expected_qual) 2448 { 2449 struct ept_access_test_data *data = &ept_access_test_data; 2450 unsigned long *ptep; 2451 unsigned long gpa; 2452 unsigned long orig_epte; 2453 unsigned long epte; 2454 int i; 2455 2456 /* Modify the guest PTE mapping data->gva according to @pte_ad. */ 2457 ptep = get_pte_level(current_page_table(), data->gva, /*level=*/1); 2458 TEST_ASSERT(ptep); 2459 TEST_ASSERT_EQ(*ptep & PT_ADDR_MASK, data->gpa); 2460 *ptep = (*ptep & ~PT_AD_MASK) | pte_ad; 2461 ept_access_test_guest_flush_tlb(); 2462 2463 /* 2464 * Now modify the access bits on the EPT entry for the GPA that the 2465 * guest PTE resides on. Note that by modifying a single EPT entry, 2466 * we're potentially affecting 512 guest PTEs. However, we've carefully 2467 * constructed our test such that those other 511 PTEs aren't used by 2468 * the guest: data->gva is at the beginning of a 1G huge page, thus the 2469 * PTE we're modifying is at the beginning of a 4K page and the 2470 * following 511 entries are also under our control (and not touched by 2471 * the guest). 2472 */ 2473 gpa = virt_to_phys(ptep); 2474 TEST_ASSERT_EQ(gpa & ~PAGE_MASK, 0); 2475 /* 2476 * Make sure the guest page table page is mapped with a 4K EPT entry, 2477 * otherwise our level=1 twiddling below will fail. We use the 2478 * identity map (gpa = gpa) since page tables are shared with the host. 2479 */ 2480 install_ept(pml4, gpa, gpa, EPT_PRESENT); 2481 orig_epte = ept_twiddle(gpa, /*mkhuge=*/0, /*level=*/1, 2482 /*clear=*/EPT_PRESENT, /*set=*/ept_access); 2483 2484 if (expect_violation) { 2485 do_ept_violation(/*leaf=*/true, op, 2486 expected_qual | EPT_VLT_LADDR_VLD, gpa); 2487 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2488 do_ept_access_op(op); 2489 } else { 2490 do_ept_access_op(op); 2491 if (ept_ad_enabled()) { 2492 for (i = EPT_PAGE_LEVEL; i > 0; i--) { 2493 TEST_ASSERT(get_ept_pte(pml4, gpa, i, &epte)); 2494 TEST_ASSERT(epte & EPT_ACCESS_FLAG); 2495 if (i == 1) 2496 TEST_ASSERT(epte & EPT_DIRTY_FLAG); 2497 else 2498 TEST_ASSERT_EQ(epte & EPT_DIRTY_FLAG, 0); 2499 } 2500 } 2501 2502 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2503 } 2504 2505 TEST_ASSERT(*ptep & PT_ACCESSED_MASK); 2506 if ((pte_ad & PT_DIRTY_MASK) || op == OP_WRITE) 2507 TEST_ASSERT(*ptep & PT_DIRTY_MASK); 2508 2509 skip_exit_vmcall(); 2510 } 2511 2512 static void ept_access_allowed_paddr(unsigned long ept_access, 2513 unsigned long pte_ad, 2514 enum ept_access_op op) 2515 { 2516 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/false, 2517 /*expected_qual=*/-1); 2518 } 2519 2520 static void ept_access_violation_paddr(unsigned long ept_access, 2521 unsigned long pte_ad, 2522 enum ept_access_op op, 2523 u64 expected_qual) 2524 { 2525 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/true, 2526 expected_qual); 2527 } 2528 2529 2530 static void ept_allowed_at_level_mkhuge(bool mkhuge, int level, 2531 unsigned long clear, 2532 unsigned long set, 2533 enum ept_access_op op) 2534 { 2535 struct ept_access_test_data *data = &ept_access_test_data; 2536 unsigned long orig_pte; 2537 2538 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2539 2540 /* No violation. Should proceed to vmcall. */ 2541 do_ept_access_op(op); 2542 skip_exit_vmcall(); 2543 2544 ept_untwiddle(data->gpa, level, orig_pte); 2545 } 2546 2547 static void ept_allowed_at_level(int level, unsigned long clear, 2548 unsigned long set, enum ept_access_op op) 2549 { 2550 ept_allowed_at_level_mkhuge(false, level, clear, set, op); 2551 if (ept_huge_pages_supported(level)) 2552 ept_allowed_at_level_mkhuge(true, level, clear, set, op); 2553 } 2554 2555 static void ept_allowed(unsigned long clear, unsigned long set, 2556 enum ept_access_op op) 2557 { 2558 ept_allowed_at_level(1, clear, set, op); 2559 ept_allowed_at_level(2, clear, set, op); 2560 ept_allowed_at_level(3, clear, set, op); 2561 ept_allowed_at_level(4, clear, set, op); 2562 } 2563 2564 static void ept_ignored_bit(int bit) 2565 { 2566 /* Set the bit. */ 2567 ept_allowed(0, 1ul << bit, OP_READ); 2568 ept_allowed(0, 1ul << bit, OP_WRITE); 2569 ept_allowed(0, 1ul << bit, OP_EXEC); 2570 2571 /* Clear the bit. */ 2572 ept_allowed(1ul << bit, 0, OP_READ); 2573 ept_allowed(1ul << bit, 0, OP_WRITE); 2574 ept_allowed(1ul << bit, 0, OP_EXEC); 2575 } 2576 2577 static void ept_access_allowed(unsigned long access, enum ept_access_op op) 2578 { 2579 ept_allowed(EPT_PRESENT, access, op); 2580 } 2581 2582 2583 static void ept_misconfig_at_level_mkhuge_op(bool mkhuge, int level, 2584 unsigned long clear, 2585 unsigned long set, 2586 enum ept_access_op op) 2587 { 2588 struct ept_access_test_data *data = &ept_access_test_data; 2589 unsigned long orig_pte; 2590 2591 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2592 2593 do_ept_access_op(op); 2594 assert_exit_reason(VMX_EPT_MISCONFIG); 2595 2596 /* Intel 27.2.1, "For all other VM exits, this field is cleared." */ 2597 #if 0 2598 /* broken: */ 2599 TEST_EXPECT_EQ_MSG(vmcs_read(EXI_QUALIFICATION), 0); 2600 #endif 2601 #if 0 2602 /* 2603 * broken: 2604 * According to description of exit qual for EPT violation, 2605 * EPT_VLT_LADDR_VLD indicates if GUEST_LINEAR_ADDRESS is valid. 2606 * However, I can't find anything that says GUEST_LINEAR_ADDRESS ought 2607 * to be set for msiconfig. 2608 */ 2609 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2610 (unsigned long) ( 2611 op == OP_EXEC ? data->gva + 1 : data->gva)); 2612 #endif 2613 2614 /* Fix the violation and resume the op loop. */ 2615 ept_untwiddle(data->gpa, level, orig_pte); 2616 enter_guest(); 2617 skip_exit_vmcall(); 2618 } 2619 2620 static void ept_misconfig_at_level_mkhuge(bool mkhuge, int level, 2621 unsigned long clear, 2622 unsigned long set) 2623 { 2624 /* The op shouldn't matter (read, write, exec), so try them all! */ 2625 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_READ); 2626 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_WRITE); 2627 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_EXEC); 2628 } 2629 2630 static void ept_misconfig_at_level(int level, unsigned long clear, 2631 unsigned long set) 2632 { 2633 ept_misconfig_at_level_mkhuge(false, level, clear, set); 2634 if (ept_huge_pages_supported(level)) 2635 ept_misconfig_at_level_mkhuge(true, level, clear, set); 2636 } 2637 2638 static void ept_misconfig(unsigned long clear, unsigned long set) 2639 { 2640 ept_misconfig_at_level(1, clear, set); 2641 ept_misconfig_at_level(2, clear, set); 2642 ept_misconfig_at_level(3, clear, set); 2643 ept_misconfig_at_level(4, clear, set); 2644 } 2645 2646 static void ept_access_misconfig(unsigned long access) 2647 { 2648 ept_misconfig(EPT_PRESENT, access); 2649 } 2650 2651 static void ept_reserved_bit_at_level_nohuge(int level, int bit) 2652 { 2653 /* Setting the bit causes a misconfig. */ 2654 ept_misconfig_at_level_mkhuge(false, level, 0, 1ul << bit); 2655 2656 /* Making the entry non-present turns reserved bits into ignored. */ 2657 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2658 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2659 } 2660 2661 static void ept_reserved_bit_at_level_huge(int level, int bit) 2662 { 2663 /* Setting the bit causes a misconfig. */ 2664 ept_misconfig_at_level_mkhuge(true, level, 0, 1ul << bit); 2665 2666 /* Making the entry non-present turns reserved bits into ignored. */ 2667 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2668 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2669 } 2670 2671 static void ept_reserved_bit_at_level(int level, int bit) 2672 { 2673 /* Setting the bit causes a misconfig. */ 2674 ept_misconfig_at_level(level, 0, 1ul << bit); 2675 2676 /* Making the entry non-present turns reserved bits into ignored. */ 2677 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2678 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2679 } 2680 2681 static void ept_reserved_bit(int bit) 2682 { 2683 ept_reserved_bit_at_level(1, bit); 2684 ept_reserved_bit_at_level(2, bit); 2685 ept_reserved_bit_at_level(3, bit); 2686 ept_reserved_bit_at_level(4, bit); 2687 } 2688 2689 #define PAGE_2M_ORDER 9 2690 #define PAGE_1G_ORDER 18 2691 2692 static void *get_1g_page(void) 2693 { 2694 static void *alloc; 2695 2696 if (!alloc) 2697 alloc = alloc_pages(PAGE_1G_ORDER); 2698 return alloc; 2699 } 2700 2701 static void ept_access_test_teardown(void *unused) 2702 { 2703 /* Exit the guest cleanly. */ 2704 do_ept_access_op(OP_EXIT); 2705 } 2706 2707 static void ept_access_test_guest(void) 2708 { 2709 struct ept_access_test_data *data = &ept_access_test_data; 2710 int (*code)(void) = (int (*)(void)) &data->gva[1]; 2711 2712 while (true) { 2713 switch (data->op) { 2714 case OP_READ: 2715 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_1); 2716 break; 2717 case OP_WRITE: 2718 *data->gva = MAGIC_VAL_2; 2719 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_2); 2720 *data->gva = MAGIC_VAL_1; 2721 break; 2722 case OP_EXEC: 2723 TEST_ASSERT_EQ(42, code()); 2724 break; 2725 case OP_FLUSH_TLB: 2726 write_cr3(read_cr3()); 2727 break; 2728 case OP_EXIT: 2729 return; 2730 default: 2731 TEST_ASSERT_MSG(false, "Unknown op %d", data->op); 2732 } 2733 vmcall(); 2734 } 2735 } 2736 2737 static void ept_access_test_setup(void) 2738 { 2739 struct ept_access_test_data *data = &ept_access_test_data; 2740 unsigned long npages = 1ul << PAGE_1G_ORDER; 2741 unsigned long size = npages * PAGE_SIZE; 2742 unsigned long *page_table = current_page_table(); 2743 unsigned long pte; 2744 2745 if (setup_ept(false)) 2746 test_skip("EPT not supported"); 2747 2748 /* We use data->gpa = 1 << 39 so that test data has a separate pml4 entry */ 2749 if (cpuid_maxphyaddr() < 40) 2750 test_skip("Test needs MAXPHYADDR >= 40"); 2751 2752 test_set_guest(ept_access_test_guest); 2753 test_add_teardown(ept_access_test_teardown, NULL); 2754 2755 data->hva = get_1g_page(); 2756 TEST_ASSERT(data->hva); 2757 data->hpa = virt_to_phys(data->hva); 2758 2759 data->gpa = 1ul << 39; 2760 data->gva = (void *) ALIGN((unsigned long) alloc_vpages(npages * 2), 2761 size); 2762 TEST_ASSERT(!any_present_pages(page_table, data->gva, size)); 2763 install_pages(page_table, data->gpa, size, data->gva); 2764 2765 /* 2766 * Make sure nothing's mapped here so the tests that screw with the 2767 * pml4 entry don't inadvertently break something. 2768 */ 2769 TEST_ASSERT(get_ept_pte(pml4, data->gpa, 4, &pte) && pte == 0); 2770 TEST_ASSERT(get_ept_pte(pml4, data->gpa + size - 1, 4, &pte) && pte == 0); 2771 install_ept(pml4, data->hpa, data->gpa, EPT_PRESENT); 2772 2773 data->hva[0] = MAGIC_VAL_1; 2774 memcpy(&data->hva[1], &ret42_start, &ret42_end - &ret42_start); 2775 } 2776 2777 static void ept_access_test_not_present(void) 2778 { 2779 ept_access_test_setup(); 2780 /* --- */ 2781 ept_access_violation(0, OP_READ, EPT_VLT_RD); 2782 ept_access_violation(0, OP_WRITE, EPT_VLT_WR); 2783 ept_access_violation(0, OP_EXEC, EPT_VLT_FETCH); 2784 } 2785 2786 static void ept_access_test_read_only(void) 2787 { 2788 ept_access_test_setup(); 2789 2790 /* r-- */ 2791 ept_access_allowed(EPT_RA, OP_READ); 2792 ept_access_violation(EPT_RA, OP_WRITE, EPT_VLT_WR | EPT_VLT_PERM_RD); 2793 ept_access_violation(EPT_RA, OP_EXEC, EPT_VLT_FETCH | EPT_VLT_PERM_RD); 2794 } 2795 2796 static void ept_access_test_write_only(void) 2797 { 2798 ept_access_test_setup(); 2799 /* -w- */ 2800 ept_access_misconfig(EPT_WA); 2801 } 2802 2803 static void ept_access_test_read_write(void) 2804 { 2805 ept_access_test_setup(); 2806 /* rw- */ 2807 ept_access_allowed(EPT_RA | EPT_WA, OP_READ); 2808 ept_access_allowed(EPT_RA | EPT_WA, OP_WRITE); 2809 ept_access_violation(EPT_RA | EPT_WA, OP_EXEC, 2810 EPT_VLT_FETCH | EPT_VLT_PERM_RD | EPT_VLT_PERM_WR); 2811 } 2812 2813 2814 static void ept_access_test_execute_only(void) 2815 { 2816 ept_access_test_setup(); 2817 /* --x */ 2818 if (ept_execute_only_supported()) { 2819 ept_access_violation(EPT_EA, OP_READ, 2820 EPT_VLT_RD | EPT_VLT_PERM_EX); 2821 ept_access_violation(EPT_EA, OP_WRITE, 2822 EPT_VLT_WR | EPT_VLT_PERM_EX); 2823 ept_access_allowed(EPT_EA, OP_EXEC); 2824 } else { 2825 ept_access_misconfig(EPT_EA); 2826 } 2827 } 2828 2829 static void ept_access_test_read_execute(void) 2830 { 2831 ept_access_test_setup(); 2832 /* r-x */ 2833 ept_access_allowed(EPT_RA | EPT_EA, OP_READ); 2834 ept_access_violation(EPT_RA | EPT_EA, OP_WRITE, 2835 EPT_VLT_WR | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX); 2836 ept_access_allowed(EPT_RA | EPT_EA, OP_EXEC); 2837 } 2838 2839 static void ept_access_test_write_execute(void) 2840 { 2841 ept_access_test_setup(); 2842 /* -wx */ 2843 ept_access_misconfig(EPT_WA | EPT_EA); 2844 } 2845 2846 static void ept_access_test_read_write_execute(void) 2847 { 2848 ept_access_test_setup(); 2849 /* rwx */ 2850 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_READ); 2851 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_WRITE); 2852 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_EXEC); 2853 } 2854 2855 static void ept_access_test_reserved_bits(void) 2856 { 2857 int i; 2858 int maxphyaddr; 2859 2860 ept_access_test_setup(); 2861 2862 /* Reserved bits above maxphyaddr. */ 2863 maxphyaddr = cpuid_maxphyaddr(); 2864 for (i = maxphyaddr; i <= 51; i++) { 2865 report_prefix_pushf("reserved_bit=%d", i); 2866 ept_reserved_bit(i); 2867 report_prefix_pop(); 2868 } 2869 2870 /* Level-specific reserved bits. */ 2871 ept_reserved_bit_at_level_nohuge(2, 3); 2872 ept_reserved_bit_at_level_nohuge(2, 4); 2873 ept_reserved_bit_at_level_nohuge(2, 5); 2874 ept_reserved_bit_at_level_nohuge(2, 6); 2875 /* 2M alignment. */ 2876 for (i = 12; i < 20; i++) { 2877 report_prefix_pushf("reserved_bit=%d", i); 2878 ept_reserved_bit_at_level_huge(2, i); 2879 report_prefix_pop(); 2880 } 2881 ept_reserved_bit_at_level_nohuge(3, 3); 2882 ept_reserved_bit_at_level_nohuge(3, 4); 2883 ept_reserved_bit_at_level_nohuge(3, 5); 2884 ept_reserved_bit_at_level_nohuge(3, 6); 2885 /* 1G alignment. */ 2886 for (i = 12; i < 29; i++) { 2887 report_prefix_pushf("reserved_bit=%d", i); 2888 ept_reserved_bit_at_level_huge(3, i); 2889 report_prefix_pop(); 2890 } 2891 ept_reserved_bit_at_level(4, 3); 2892 ept_reserved_bit_at_level(4, 4); 2893 ept_reserved_bit_at_level(4, 5); 2894 ept_reserved_bit_at_level(4, 6); 2895 ept_reserved_bit_at_level(4, 7); 2896 } 2897 2898 static void ept_access_test_ignored_bits(void) 2899 { 2900 ept_access_test_setup(); 2901 /* 2902 * Bits ignored at every level. Bits 8 and 9 (A and D) are ignored as 2903 * far as translation is concerned even if AD bits are enabled in the 2904 * EPTP. Bit 63 is ignored because "EPT-violation #VE" VM-execution 2905 * control is 0. 2906 */ 2907 ept_ignored_bit(8); 2908 ept_ignored_bit(9); 2909 ept_ignored_bit(10); 2910 ept_ignored_bit(11); 2911 ept_ignored_bit(52); 2912 ept_ignored_bit(53); 2913 ept_ignored_bit(54); 2914 ept_ignored_bit(55); 2915 ept_ignored_bit(56); 2916 ept_ignored_bit(57); 2917 ept_ignored_bit(58); 2918 ept_ignored_bit(59); 2919 ept_ignored_bit(60); 2920 ept_ignored_bit(61); 2921 ept_ignored_bit(62); 2922 ept_ignored_bit(63); 2923 } 2924 2925 static void ept_access_test_paddr_not_present_ad_disabled(void) 2926 { 2927 ept_access_test_setup(); 2928 ept_disable_ad_bits(); 2929 2930 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, EPT_VLT_RD); 2931 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, EPT_VLT_RD); 2932 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, EPT_VLT_RD); 2933 } 2934 2935 static void ept_access_test_paddr_not_present_ad_enabled(void) 2936 { 2937 u64 qual = EPT_VLT_RD | EPT_VLT_WR; 2938 2939 ept_access_test_setup(); 2940 ept_enable_ad_bits_or_skip_test(); 2941 2942 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, qual); 2943 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, qual); 2944 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, qual); 2945 } 2946 2947 static void ept_access_test_paddr_read_only_ad_disabled(void) 2948 { 2949 /* 2950 * When EPT AD bits are disabled, all accesses to guest paging 2951 * structures are reported separately as a read and (after 2952 * translation of the GPA to host physical address) a read+write 2953 * if the A/D bits have to be set. 2954 */ 2955 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 2956 2957 ept_access_test_setup(); 2958 ept_disable_ad_bits(); 2959 2960 /* Can't update A bit, so all accesses fail. */ 2961 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 2962 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 2963 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 2964 /* AD bits disabled, so only writes try to update the D bit. */ 2965 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ); 2966 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 2967 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC); 2968 /* Both A and D already set, so read-only is OK. */ 2969 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_READ); 2970 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_WRITE); 2971 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_EXEC); 2972 } 2973 2974 static void ept_access_test_paddr_read_only_ad_enabled(void) 2975 { 2976 /* 2977 * When EPT AD bits are enabled, all accesses to guest paging 2978 * structures are considered writes as far as EPT translation 2979 * is concerned. 2980 */ 2981 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 2982 2983 ept_access_test_setup(); 2984 ept_enable_ad_bits_or_skip_test(); 2985 2986 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 2987 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 2988 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 2989 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ, qual); 2990 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 2991 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC, qual); 2992 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_READ, qual); 2993 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_WRITE, qual); 2994 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_EXEC, qual); 2995 } 2996 2997 static void ept_access_test_paddr_read_write(void) 2998 { 2999 ept_access_test_setup(); 3000 /* Read-write access to paging structure. */ 3001 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_READ); 3002 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_WRITE); 3003 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_EXEC); 3004 } 3005 3006 static void ept_access_test_paddr_read_write_execute(void) 3007 { 3008 ept_access_test_setup(); 3009 /* RWX access to paging structure. */ 3010 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_READ); 3011 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_WRITE); 3012 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_EXEC); 3013 } 3014 3015 static void ept_access_test_paddr_read_execute_ad_disabled(void) 3016 { 3017 /* 3018 * When EPT AD bits are disabled, all accesses to guest paging 3019 * structures are reported separately as a read and (after 3020 * translation of the GPA to host physical address) a read+write 3021 * if the A/D bits have to be set. 3022 */ 3023 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3024 3025 ept_access_test_setup(); 3026 ept_disable_ad_bits(); 3027 3028 /* Can't update A bit, so all accesses fail. */ 3029 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3030 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3031 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3032 /* AD bits disabled, so only writes try to update the D bit. */ 3033 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ); 3034 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3035 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC); 3036 /* Both A and D already set, so read-only is OK. */ 3037 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ); 3038 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE); 3039 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC); 3040 } 3041 3042 static void ept_access_test_paddr_read_execute_ad_enabled(void) 3043 { 3044 /* 3045 * When EPT AD bits are enabled, all accesses to guest paging 3046 * structures are considered writes as far as EPT translation 3047 * is concerned. 3048 */ 3049 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3050 3051 ept_access_test_setup(); 3052 ept_enable_ad_bits_or_skip_test(); 3053 3054 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3055 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3056 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3057 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ, qual); 3058 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3059 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC, qual); 3060 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ, qual); 3061 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE, qual); 3062 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC, qual); 3063 } 3064 3065 static void ept_access_test_paddr_not_present_page_fault(void) 3066 { 3067 ept_access_test_setup(); 3068 /* 3069 * TODO: test no EPT violation as long as guest PF occurs. e.g., GPA is 3070 * page is read-only in EPT but GVA is also mapped read only in PT. 3071 * Thus guest page fault before host takes EPT violation for trying to 3072 * update A bit. 3073 */ 3074 } 3075 3076 static void ept_access_test_force_2m_page(void) 3077 { 3078 ept_access_test_setup(); 3079 3080 TEST_ASSERT_EQ(ept_2m_supported(), true); 3081 ept_allowed_at_level_mkhuge(true, 2, 0, 0, OP_READ); 3082 ept_violation_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_RA, OP_WRITE, 3083 EPT_VLT_WR | EPT_VLT_PERM_RD | 3084 EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 3085 ept_misconfig_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_WA); 3086 } 3087 3088 static bool invvpid_valid(u64 type, u64 vpid, u64 gla) 3089 { 3090 if (!is_invvpid_type_supported(type)) 3091 return false; 3092 3093 if (vpid >> 16) 3094 return false; 3095 3096 if (type != INVVPID_ALL && !vpid) 3097 return false; 3098 3099 if (type == INVVPID_ADDR && !is_canonical(gla)) 3100 return false; 3101 3102 return true; 3103 } 3104 3105 static void try_invvpid(u64 type, u64 vpid, u64 gla) 3106 { 3107 int rc; 3108 bool valid = invvpid_valid(type, vpid, gla); 3109 u64 expected = valid ? VMXERR_UNSUPPORTED_VMCS_COMPONENT 3110 : VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID; 3111 /* 3112 * Set VMX_INST_ERROR to VMXERR_UNVALID_VMCS_COMPONENT, so 3113 * that we can tell if it is updated by INVVPID. 3114 */ 3115 vmcs_read(~0); 3116 rc = __invvpid(type, vpid, gla); 3117 report(!rc == valid, "INVVPID type %ld VPID %lx GLA %lx %s", type, 3118 vpid, gla, 3119 valid ? "passes" : "fails"); 3120 report(vmcs_read(VMX_INST_ERROR) == expected, 3121 "After %s INVVPID, VMX_INST_ERR is %ld (actual %ld)", 3122 rc ? "failed" : "successful", 3123 expected, vmcs_read(VMX_INST_ERROR)); 3124 } 3125 3126 static inline unsigned long get_first_supported_invvpid_type(void) 3127 { 3128 u64 type = ffs(ept_vpid.val >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 3129 3130 __TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 3131 return type; 3132 } 3133 3134 static void ds_invvpid(void *data) 3135 { 3136 asm volatile("invvpid %0, %1" 3137 : 3138 : "m"(*(struct invvpid_operand *)data), 3139 "r"(get_first_supported_invvpid_type())); 3140 } 3141 3142 /* 3143 * The SS override is ignored in 64-bit mode, so we use an addressing 3144 * mode with %rsp as the base register to generate an implicit SS 3145 * reference. 3146 */ 3147 static void ss_invvpid(void *data) 3148 { 3149 asm volatile("sub %%rsp,%0; invvpid (%%rsp,%0,1), %1" 3150 : "+r"(data) 3151 : "r"(get_first_supported_invvpid_type())); 3152 } 3153 3154 static void invvpid_test_gp(void) 3155 { 3156 bool fault; 3157 3158 fault = test_for_exception(GP_VECTOR, &ds_invvpid, 3159 (void *)NONCANONICAL); 3160 report(fault, "INVVPID with non-canonical DS operand raises #GP"); 3161 } 3162 3163 static void invvpid_test_ss(void) 3164 { 3165 bool fault; 3166 3167 fault = test_for_exception(SS_VECTOR, &ss_invvpid, 3168 (void *)NONCANONICAL); 3169 report(fault, "INVVPID with non-canonical SS operand raises #SS"); 3170 } 3171 3172 static void invvpid_test_pf(void) 3173 { 3174 void *vpage = alloc_vpage(); 3175 bool fault; 3176 3177 fault = test_for_exception(PF_VECTOR, &ds_invvpid, vpage); 3178 report(fault, "INVVPID with unmapped operand raises #PF"); 3179 } 3180 3181 static void try_compat_invvpid(void *unused) 3182 { 3183 struct far_pointer32 fp = { 3184 .offset = (uintptr_t)&&invvpid, 3185 .selector = KERNEL_CS32, 3186 }; 3187 uintptr_t rsp; 3188 3189 asm volatile ("mov %%rsp, %0" : "=r"(rsp)); 3190 3191 TEST_ASSERT_MSG(fp.offset == (uintptr_t)&&invvpid, 3192 "Code address too high."); 3193 TEST_ASSERT_MSG(rsp == (u32)rsp, "Stack address too high."); 3194 3195 asm goto ("lcall *%0" : : "m" (fp) : "rax" : invvpid); 3196 return; 3197 invvpid: 3198 asm volatile (".code32;" 3199 "invvpid (%eax), %eax;" 3200 "lret;" 3201 ".code64"); 3202 __builtin_unreachable(); 3203 } 3204 3205 static void invvpid_test_compatibility_mode(void) 3206 { 3207 bool fault; 3208 3209 fault = test_for_exception(UD_VECTOR, &try_compat_invvpid, NULL); 3210 report(fault, "Compatibility mode INVVPID raises #UD"); 3211 } 3212 3213 static void invvpid_test_not_in_vmx_operation(void) 3214 { 3215 bool fault; 3216 3217 TEST_ASSERT(!vmx_off()); 3218 fault = test_for_exception(UD_VECTOR, &ds_invvpid, NULL); 3219 report(fault, "INVVPID outside of VMX operation raises #UD"); 3220 TEST_ASSERT(!vmx_on()); 3221 } 3222 3223 /* 3224 * This does not test real-address mode, virtual-8086 mode, protected mode, 3225 * or CPL > 0. 3226 */ 3227 static void invvpid_test(void) 3228 { 3229 int i; 3230 unsigned types = 0; 3231 unsigned type; 3232 3233 if (!is_vpid_supported()) 3234 test_skip("VPID not supported"); 3235 3236 if (!is_invvpid_supported()) 3237 test_skip("INVVPID not supported.\n"); 3238 3239 if (is_invvpid_type_supported(INVVPID_ADDR)) 3240 types |= 1u << INVVPID_ADDR; 3241 if (is_invvpid_type_supported(INVVPID_CONTEXT_GLOBAL)) 3242 types |= 1u << INVVPID_CONTEXT_GLOBAL; 3243 if (is_invvpid_type_supported(INVVPID_ALL)) 3244 types |= 1u << INVVPID_ALL; 3245 if (is_invvpid_type_supported(INVVPID_CONTEXT_LOCAL)) 3246 types |= 1u << INVVPID_CONTEXT_LOCAL; 3247 3248 if (!types) 3249 test_skip("No INVVPID types supported.\n"); 3250 3251 for (i = -127; i < 128; i++) 3252 try_invvpid(i, 0xffff, 0); 3253 3254 /* 3255 * VPID must not be more than 16 bits. 3256 */ 3257 for (i = 0; i < 64; i++) 3258 for (type = 0; type < 4; type++) 3259 if (types & (1u << type)) 3260 try_invvpid(type, 1ul << i, 0); 3261 3262 /* 3263 * VPID must not be zero, except for "all contexts." 3264 */ 3265 for (type = 0; type < 4; type++) 3266 if (types & (1u << type)) 3267 try_invvpid(type, 0, 0); 3268 3269 /* 3270 * The gla operand is only validated for single-address INVVPID. 3271 */ 3272 if (types & (1u << INVVPID_ADDR)) 3273 try_invvpid(INVVPID_ADDR, 0xffff, NONCANONICAL); 3274 3275 invvpid_test_gp(); 3276 invvpid_test_ss(); 3277 invvpid_test_pf(); 3278 invvpid_test_compatibility_mode(); 3279 invvpid_test_not_in_vmx_operation(); 3280 } 3281 3282 static void test_assert_vmlaunch_inst_error(u32 expected_error) 3283 { 3284 u32 vmx_inst_err = vmcs_read(VMX_INST_ERROR); 3285 3286 report(vmx_inst_err == expected_error, 3287 "VMX inst error is %d (actual %d)", expected_error, vmx_inst_err); 3288 } 3289 3290 /* 3291 * This version is wildly unsafe and should _only_ be used to test VM-Fail 3292 * scenarios involving HOST_RIP. 3293 */ 3294 static void test_vmx_vmlaunch_must_fail(u32 expected_error) 3295 { 3296 /* Read the function name. */ 3297 TEST_ASSERT(expected_error); 3298 3299 /* 3300 * Don't bother with any prep work, if VMLAUNCH passes the VM-Fail 3301 * consistency checks and generates a VM-Exit, then the test is doomed 3302 * no matter what as it will jump to a garbage RIP. 3303 */ 3304 __asm__ __volatile__ ("vmlaunch"); 3305 test_assert_vmlaunch_inst_error(expected_error); 3306 } 3307 3308 /* 3309 * Test for early VMLAUNCH failure. Returns true if VMLAUNCH makes it 3310 * at least as far as the guest-state checks. Returns false if the 3311 * VMLAUNCH fails early and execution falls through to the next 3312 * instruction. 3313 */ 3314 static bool vmlaunch(void) 3315 { 3316 u32 exit_reason; 3317 3318 /* 3319 * Indirectly set VMX_INST_ERR to 12 ("VMREAD/VMWRITE from/to 3320 * unsupported VMCS component"). The caller can then check 3321 * to see if a failed VM-entry sets VMX_INST_ERR as expected. 3322 */ 3323 vmcs_write(~0u, 0); 3324 3325 vmcs_write(HOST_RIP, (uintptr_t)&&success); 3326 __asm__ __volatile__ goto ("vmwrite %%rsp, %0; vmlaunch" 3327 : 3328 : "r" ((u64)HOST_RSP) 3329 : "cc", "memory" 3330 : success); 3331 return false; 3332 success: 3333 exit_reason = vmcs_read(EXI_REASON); 3334 TEST_ASSERT(exit_reason == (VMX_FAIL_STATE | VMX_ENTRY_FAILURE) || 3335 exit_reason == (VMX_FAIL_MSR | VMX_ENTRY_FAILURE)); 3336 return true; 3337 } 3338 3339 /* 3340 * Try to launch the current VMCS. 3341 */ 3342 static void test_vmx_vmlaunch(u32 xerror) 3343 { 3344 bool success = vmlaunch(); 3345 3346 report(success == !xerror, "vmlaunch %s", 3347 !xerror ? "succeeds" : "fails"); 3348 if (!success && xerror) 3349 test_assert_vmlaunch_inst_error(xerror); 3350 } 3351 3352 /* 3353 * Try to launch the current VMCS, and expect one of two possible 3354 * errors (or success) codes. 3355 */ 3356 static void test_vmx_vmlaunch2(u32 xerror1, u32 xerror2) 3357 { 3358 bool success = vmlaunch(); 3359 u32 vmx_inst_err; 3360 3361 if (!xerror1 == !xerror2) 3362 report(success == !xerror1, "vmlaunch %s", 3363 !xerror1 ? "succeeds" : "fails"); 3364 3365 if (!success && (xerror1 || xerror2)) { 3366 vmx_inst_err = vmcs_read(VMX_INST_ERROR); 3367 report(vmx_inst_err == xerror1 || vmx_inst_err == xerror2, 3368 "VMX inst error is %d or %d (actual %d)", xerror1, 3369 xerror2, vmx_inst_err); 3370 } 3371 } 3372 3373 static void test_vmx_invalid_controls(void) 3374 { 3375 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_CONTROL_FIELD); 3376 } 3377 3378 static void test_vmx_valid_controls(void) 3379 { 3380 test_vmx_vmlaunch(0); 3381 } 3382 3383 /* 3384 * Test a particular value of a VM-execution control bit, if the value 3385 * is required or if the value is zero. 3386 */ 3387 static void test_rsvd_ctl_bit_value(const char *name, union vmx_ctrl_msr msr, 3388 enum Encoding encoding, unsigned bit, 3389 unsigned val) 3390 { 3391 u32 mask = 1u << bit; 3392 bool expected; 3393 u32 controls; 3394 3395 if (msr.set & mask) 3396 TEST_ASSERT(msr.clr & mask); 3397 3398 /* 3399 * We can't arbitrarily turn on a control bit, because it may 3400 * introduce dependencies on other VMCS fields. So, we only 3401 * test turning on bits that have a required setting. 3402 */ 3403 if (val && (msr.clr & mask) && !(msr.set & mask)) 3404 return; 3405 3406 report_prefix_pushf("%s %s bit %d", 3407 val ? "Set" : "Clear", name, bit); 3408 3409 controls = vmcs_read(encoding); 3410 if (val) { 3411 vmcs_write(encoding, msr.set | mask); 3412 expected = (msr.clr & mask); 3413 } else { 3414 vmcs_write(encoding, msr.set & ~mask); 3415 expected = !(msr.set & mask); 3416 } 3417 if (expected) 3418 test_vmx_valid_controls(); 3419 else 3420 test_vmx_invalid_controls(); 3421 vmcs_write(encoding, controls); 3422 report_prefix_pop(); 3423 } 3424 3425 /* 3426 * Test reserved values of a VM-execution control bit, based on the 3427 * allowed bit settings from the corresponding VMX capability MSR. 3428 */ 3429 static void test_rsvd_ctl_bit(const char *name, union vmx_ctrl_msr msr, 3430 enum Encoding encoding, unsigned bit) 3431 { 3432 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 0); 3433 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 1); 3434 } 3435 3436 /* 3437 * Reserved bits in the pin-based VM-execution controls must be set 3438 * properly. Software may consult the VMX capability MSRs to determine 3439 * the proper settings. 3440 * [Intel SDM] 3441 */ 3442 static void test_pin_based_ctls(void) 3443 { 3444 unsigned bit; 3445 3446 printf("%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PIN" : 3447 "MSR_IA32_VMX_PINBASED_CTLS", ctrl_pin_rev.val); 3448 for (bit = 0; bit < 32; bit++) 3449 test_rsvd_ctl_bit("pin-based controls", 3450 ctrl_pin_rev, PIN_CONTROLS, bit); 3451 } 3452 3453 /* 3454 * Reserved bits in the primary processor-based VM-execution controls 3455 * must be set properly. Software may consult the VMX capability MSRs 3456 * to determine the proper settings. 3457 * [Intel SDM] 3458 */ 3459 static void test_primary_processor_based_ctls(void) 3460 { 3461 unsigned bit; 3462 3463 printf("\n%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PROC" : 3464 "MSR_IA32_VMX_PROCBASED_CTLS", ctrl_cpu_rev[0].val); 3465 for (bit = 0; bit < 32; bit++) 3466 test_rsvd_ctl_bit("primary processor-based controls", 3467 ctrl_cpu_rev[0], CPU_EXEC_CTRL0, bit); 3468 } 3469 3470 /* 3471 * If the "activate secondary controls" primary processor-based 3472 * VM-execution control is 1, reserved bits in the secondary 3473 * processor-based VM-execution controls must be cleared. Software may 3474 * consult the VMX capability MSRs to determine which bits are 3475 * reserved. 3476 * If the "activate secondary controls" primary processor-based 3477 * VM-execution control is 0 (or if the processor does not support the 3478 * 1-setting of that control), no checks are performed on the 3479 * secondary processor-based VM-execution controls. 3480 * [Intel SDM] 3481 */ 3482 static void test_secondary_processor_based_ctls(void) 3483 { 3484 u32 primary; 3485 u32 secondary; 3486 unsigned bit; 3487 3488 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) 3489 return; 3490 3491 primary = vmcs_read(CPU_EXEC_CTRL0); 3492 secondary = vmcs_read(CPU_EXEC_CTRL1); 3493 3494 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3495 printf("\nMSR_IA32_VMX_PROCBASED_CTLS2: %lx\n", ctrl_cpu_rev[1].val); 3496 for (bit = 0; bit < 32; bit++) 3497 test_rsvd_ctl_bit("secondary processor-based controls", 3498 ctrl_cpu_rev[1], CPU_EXEC_CTRL1, bit); 3499 3500 /* 3501 * When the "activate secondary controls" VM-execution control 3502 * is clear, there are no checks on the secondary controls. 3503 */ 3504 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3505 vmcs_write(CPU_EXEC_CTRL1, ~0); 3506 report(vmlaunch(), 3507 "Secondary processor-based controls ignored"); 3508 vmcs_write(CPU_EXEC_CTRL1, secondary); 3509 vmcs_write(CPU_EXEC_CTRL0, primary); 3510 } 3511 3512 static void try_cr3_target_count(unsigned i, unsigned max) 3513 { 3514 report_prefix_pushf("CR3 target count 0x%x", i); 3515 vmcs_write(CR3_TARGET_COUNT, i); 3516 if (i <= max) 3517 test_vmx_valid_controls(); 3518 else 3519 test_vmx_invalid_controls(); 3520 report_prefix_pop(); 3521 } 3522 3523 /* 3524 * The CR3-target count must not be greater than 4. Future processors 3525 * may support a different number of CR3-target values. Software 3526 * should read the VMX capability MSR IA32_VMX_MISC to determine the 3527 * number of values supported. 3528 * [Intel SDM] 3529 */ 3530 static void test_cr3_targets(void) 3531 { 3532 unsigned supported_targets = (rdmsr(MSR_IA32_VMX_MISC) >> 16) & 0x1ff; 3533 u32 cr3_targets = vmcs_read(CR3_TARGET_COUNT); 3534 unsigned i; 3535 3536 printf("\nSupported CR3 targets: %d\n", supported_targets); 3537 TEST_ASSERT(supported_targets <= 256); 3538 3539 try_cr3_target_count(-1u, supported_targets); 3540 try_cr3_target_count(0x80000000, supported_targets); 3541 try_cr3_target_count(0x7fffffff, supported_targets); 3542 for (i = 0; i <= supported_targets + 1; i++) 3543 try_cr3_target_count(i, supported_targets); 3544 vmcs_write(CR3_TARGET_COUNT, cr3_targets); 3545 3546 /* VMWRITE to nonexistent target fields should fail. */ 3547 for (i = supported_targets; i < 256; i++) 3548 TEST_ASSERT(vmcs_write(CR3_TARGET_0 + i*2, 0)); 3549 } 3550 3551 /* 3552 * Test a particular address setting in the VMCS 3553 */ 3554 static void test_vmcs_addr(const char *name, 3555 enum Encoding encoding, 3556 u64 align, 3557 bool ignored, 3558 bool skip_beyond_mapped_ram, 3559 u64 addr) 3560 { 3561 report_prefix_pushf("%s = %lx", name, addr); 3562 vmcs_write(encoding, addr); 3563 if (skip_beyond_mapped_ram && 3564 addr > fwcfg_get_u64(FW_CFG_RAM_SIZE) - align && 3565 addr < (1ul << cpuid_maxphyaddr())) 3566 printf("Skipping physical address beyond mapped RAM\n"); 3567 else if (ignored || (IS_ALIGNED(addr, align) && 3568 addr < (1ul << cpuid_maxphyaddr()))) 3569 test_vmx_valid_controls(); 3570 else 3571 test_vmx_invalid_controls(); 3572 report_prefix_pop(); 3573 } 3574 3575 /* 3576 * Test interesting values for a VMCS address 3577 */ 3578 static void test_vmcs_addr_values(const char *name, 3579 enum Encoding encoding, 3580 u64 align, 3581 bool ignored, 3582 bool skip_beyond_mapped_ram, 3583 u32 bit_start, u32 bit_end) 3584 { 3585 unsigned i; 3586 u64 orig_val = vmcs_read(encoding); 3587 3588 for (i = bit_start; i <= bit_end; i++) 3589 test_vmcs_addr(name, encoding, align, ignored, 3590 skip_beyond_mapped_ram, 1ul << i); 3591 3592 test_vmcs_addr(name, encoding, align, ignored, 3593 skip_beyond_mapped_ram, PAGE_SIZE - 1); 3594 test_vmcs_addr(name, encoding, align, ignored, 3595 skip_beyond_mapped_ram, PAGE_SIZE); 3596 test_vmcs_addr(name, encoding, align, ignored, 3597 skip_beyond_mapped_ram, 3598 (1ul << cpuid_maxphyaddr()) - PAGE_SIZE); 3599 test_vmcs_addr(name, encoding, align, ignored, 3600 skip_beyond_mapped_ram, -1ul); 3601 3602 vmcs_write(encoding, orig_val); 3603 } 3604 3605 /* 3606 * Test a physical address reference in the VMCS, when the corresponding 3607 * feature is enabled and when the corresponding feature is disabled. 3608 */ 3609 static void test_vmcs_addr_reference(u32 control_bit, enum Encoding field, 3610 const char *field_name, 3611 const char *control_name, u64 align, 3612 bool skip_beyond_mapped_ram, 3613 bool control_primary) 3614 { 3615 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 3616 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 3617 u64 page_addr; 3618 3619 if (control_primary) { 3620 if (!(ctrl_cpu_rev[0].clr & control_bit)) 3621 return; 3622 } else { 3623 if (!(ctrl_cpu_rev[1].clr & control_bit)) 3624 return; 3625 } 3626 3627 page_addr = vmcs_read(field); 3628 3629 report_prefix_pushf("%s enabled", control_name); 3630 if (control_primary) { 3631 vmcs_write(CPU_EXEC_CTRL0, primary | control_bit); 3632 } else { 3633 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3634 vmcs_write(CPU_EXEC_CTRL1, secondary | control_bit); 3635 } 3636 3637 test_vmcs_addr_values(field_name, field, align, false, 3638 skip_beyond_mapped_ram, 0, 63); 3639 report_prefix_pop(); 3640 3641 report_prefix_pushf("%s disabled", control_name); 3642 if (control_primary) { 3643 vmcs_write(CPU_EXEC_CTRL0, primary & ~control_bit); 3644 } else { 3645 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3646 vmcs_write(CPU_EXEC_CTRL1, secondary & ~control_bit); 3647 } 3648 3649 test_vmcs_addr_values(field_name, field, align, true, false, 0, 63); 3650 report_prefix_pop(); 3651 3652 vmcs_write(field, page_addr); 3653 vmcs_write(CPU_EXEC_CTRL0, primary); 3654 vmcs_write(CPU_EXEC_CTRL1, secondary); 3655 } 3656 3657 /* 3658 * If the "use I/O bitmaps" VM-execution control is 1, bits 11:0 of 3659 * each I/O-bitmap address must be 0. Neither address should set any 3660 * bits beyond the processor's physical-address width. 3661 * [Intel SDM] 3662 */ 3663 static void test_io_bitmaps(void) 3664 { 3665 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_A, 3666 "I/O bitmap A", "Use I/O bitmaps", 3667 PAGE_SIZE, false, true); 3668 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_B, 3669 "I/O bitmap B", "Use I/O bitmaps", 3670 PAGE_SIZE, false, true); 3671 } 3672 3673 /* 3674 * If the "use MSR bitmaps" VM-execution control is 1, bits 11:0 of 3675 * the MSR-bitmap address must be 0. The address should not set any 3676 * bits beyond the processor's physical-address width. 3677 * [Intel SDM] 3678 */ 3679 static void test_msr_bitmap(void) 3680 { 3681 test_vmcs_addr_reference(CPU_MSR_BITMAP, MSR_BITMAP, 3682 "MSR bitmap", "Use MSR bitmaps", 3683 PAGE_SIZE, false, true); 3684 } 3685 3686 /* 3687 * If the "use TPR shadow" VM-execution control is 1, the virtual-APIC 3688 * address must satisfy the following checks: 3689 * - Bits 11:0 of the address must be 0. 3690 * - The address should not set any bits beyond the processor's 3691 * physical-address width. 3692 * [Intel SDM] 3693 */ 3694 static void test_apic_virt_addr(void) 3695 { 3696 /* 3697 * Ensure the processor will never use the virtual-APIC page, since 3698 * we will point it to invalid RAM. Otherwise KVM is puzzled about 3699 * what we're trying to achieve and fails vmentry. 3700 */ 3701 u32 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 3702 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0 | CPU_CR8_LOAD | CPU_CR8_STORE); 3703 test_vmcs_addr_reference(CPU_TPR_SHADOW, APIC_VIRT_ADDR, 3704 "virtual-APIC address", "Use TPR shadow", 3705 PAGE_SIZE, false, true); 3706 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 3707 } 3708 3709 /* 3710 * If the "virtualize APIC-accesses" VM-execution control is 1, the 3711 * APIC-access address must satisfy the following checks: 3712 * - Bits 11:0 of the address must be 0. 3713 * - The address should not set any bits beyond the processor's 3714 * physical-address width. 3715 * [Intel SDM] 3716 */ 3717 static void test_apic_access_addr(void) 3718 { 3719 void *apic_access_page = alloc_page(); 3720 3721 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_page)); 3722 3723 test_vmcs_addr_reference(CPU_VIRT_APIC_ACCESSES, APIC_ACCS_ADDR, 3724 "APIC-access address", 3725 "virtualize APIC-accesses", PAGE_SIZE, 3726 true, false); 3727 } 3728 3729 static bool set_bit_pattern(u8 mask, u32 *secondary) 3730 { 3731 u8 i; 3732 bool flag = false; 3733 u32 test_bits[3] = { 3734 CPU_VIRT_X2APIC, 3735 CPU_APIC_REG_VIRT, 3736 CPU_VINTD 3737 }; 3738 3739 for (i = 0; i < ARRAY_SIZE(test_bits); i++) { 3740 if ((mask & (1u << i)) && 3741 (ctrl_cpu_rev[1].clr & test_bits[i])) { 3742 *secondary |= test_bits[i]; 3743 flag = true; 3744 } 3745 } 3746 3747 return (flag); 3748 } 3749 3750 /* 3751 * If the "use TPR shadow" VM-execution control is 0, the following 3752 * VM-execution controls must also be 0: 3753 * - virtualize x2APIC mode 3754 * - APIC-register virtualization 3755 * - virtual-interrupt delivery 3756 * [Intel SDM] 3757 * 3758 * 2. If the "virtualize x2APIC mode" VM-execution control is 1, the 3759 * "virtualize APIC accesses" VM-execution control must be 0. 3760 * [Intel SDM] 3761 */ 3762 static void test_apic_virtual_ctls(void) 3763 { 3764 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3765 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3766 u32 primary = saved_primary; 3767 u32 secondary = saved_secondary; 3768 bool is_ctrl_valid = false; 3769 char str[10] = "disabled"; 3770 u8 i = 0, j; 3771 3772 /* 3773 * First test 3774 */ 3775 if (!((ctrl_cpu_rev[0].clr & (CPU_SECONDARY | CPU_TPR_SHADOW)) == 3776 (CPU_SECONDARY | CPU_TPR_SHADOW))) 3777 return; 3778 3779 primary |= CPU_SECONDARY; 3780 primary &= ~CPU_TPR_SHADOW; 3781 vmcs_write(CPU_EXEC_CTRL0, primary); 3782 3783 while (1) { 3784 for (j = 1; j < 8; j++) { 3785 secondary &= ~(CPU_VIRT_X2APIC | CPU_APIC_REG_VIRT | CPU_VINTD); 3786 if (primary & CPU_TPR_SHADOW) { 3787 is_ctrl_valid = true; 3788 } else { 3789 if (! set_bit_pattern(j, &secondary)) 3790 is_ctrl_valid = true; 3791 else 3792 is_ctrl_valid = false; 3793 } 3794 3795 vmcs_write(CPU_EXEC_CTRL1, secondary); 3796 report_prefix_pushf("Use TPR shadow %s, virtualize x2APIC mode %s, APIC-register virtualization %s, virtual-interrupt delivery %s", 3797 str, (secondary & CPU_VIRT_X2APIC) ? "enabled" : "disabled", (secondary & CPU_APIC_REG_VIRT) ? "enabled" : "disabled", (secondary & CPU_VINTD) ? "enabled" : "disabled"); 3798 if (is_ctrl_valid) 3799 test_vmx_valid_controls(); 3800 else 3801 test_vmx_invalid_controls(); 3802 report_prefix_pop(); 3803 } 3804 3805 if (i == 1) 3806 break; 3807 i++; 3808 3809 primary |= CPU_TPR_SHADOW; 3810 vmcs_write(CPU_EXEC_CTRL0, primary); 3811 strcpy(str, "enabled"); 3812 } 3813 3814 /* 3815 * Second test 3816 */ 3817 u32 apic_virt_ctls = (CPU_VIRT_X2APIC | CPU_VIRT_APIC_ACCESSES); 3818 3819 primary = saved_primary; 3820 secondary = saved_secondary; 3821 if (!((ctrl_cpu_rev[1].clr & apic_virt_ctls) == apic_virt_ctls)) 3822 return; 3823 3824 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3825 secondary &= ~CPU_VIRT_APIC_ACCESSES; 3826 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_X2APIC); 3827 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access disabled"); 3828 test_vmx_valid_controls(); 3829 report_prefix_pop(); 3830 3831 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_APIC_ACCESSES); 3832 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access enabled"); 3833 test_vmx_valid_controls(); 3834 report_prefix_pop(); 3835 3836 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_X2APIC); 3837 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access enabled"); 3838 test_vmx_invalid_controls(); 3839 report_prefix_pop(); 3840 3841 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_APIC_ACCESSES); 3842 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access disabled"); 3843 test_vmx_valid_controls(); 3844 report_prefix_pop(); 3845 3846 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3847 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3848 } 3849 3850 /* 3851 * If the "virtual-interrupt delivery" VM-execution control is 1, the 3852 * "external-interrupt exiting" VM-execution control must be 1. 3853 * [Intel SDM] 3854 */ 3855 static void test_virtual_intr_ctls(void) 3856 { 3857 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3858 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3859 u32 saved_pin = vmcs_read(PIN_CONTROLS); 3860 u32 primary = saved_primary; 3861 u32 secondary = saved_secondary; 3862 u32 pin = saved_pin; 3863 3864 if (!((ctrl_cpu_rev[1].clr & CPU_VINTD) && 3865 (ctrl_pin_rev.clr & PIN_EXTINT))) 3866 return; 3867 3868 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 3869 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VINTD); 3870 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 3871 report_prefix_pushf("Virtualize interrupt-delivery disabled; external-interrupt exiting disabled"); 3872 test_vmx_valid_controls(); 3873 report_prefix_pop(); 3874 3875 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VINTD); 3876 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 3877 test_vmx_invalid_controls(); 3878 report_prefix_pop(); 3879 3880 vmcs_write(PIN_CONTROLS, pin | PIN_EXTINT); 3881 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting enabled"); 3882 test_vmx_valid_controls(); 3883 report_prefix_pop(); 3884 3885 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 3886 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 3887 test_vmx_invalid_controls(); 3888 report_prefix_pop(); 3889 3890 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3891 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3892 vmcs_write(PIN_CONTROLS, saved_pin); 3893 } 3894 3895 static void test_pi_desc_addr(u64 addr, bool is_ctrl_valid) 3896 { 3897 vmcs_write(POSTED_INTR_DESC_ADDR, addr); 3898 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-descriptor-address 0x%lx", addr); 3899 if (is_ctrl_valid) 3900 test_vmx_valid_controls(); 3901 else 3902 test_vmx_invalid_controls(); 3903 report_prefix_pop(); 3904 } 3905 3906 /* 3907 * If the "process posted interrupts" VM-execution control is 1, the 3908 * following must be true: 3909 * 3910 * - The "virtual-interrupt delivery" VM-execution control is 1. 3911 * - The "acknowledge interrupt on exit" VM-exit control is 1. 3912 * - The posted-interrupt notification vector has a value in the 3913 * - range 0 - 255 (bits 15:8 are all 0). 3914 * - Bits 5:0 of the posted-interrupt descriptor address are all 0. 3915 * - The posted-interrupt descriptor address does not set any bits 3916 * beyond the processor's physical-address width. 3917 * [Intel SDM] 3918 */ 3919 static void test_posted_intr(void) 3920 { 3921 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3922 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3923 u32 saved_pin = vmcs_read(PIN_CONTROLS); 3924 u32 exit_ctl_saved = vmcs_read(EXI_CONTROLS); 3925 u32 primary = saved_primary; 3926 u32 secondary = saved_secondary; 3927 u32 pin = saved_pin; 3928 u32 exit_ctl = exit_ctl_saved; 3929 u16 vec; 3930 int i; 3931 3932 if (!((ctrl_pin_rev.clr & PIN_POST_INTR) && 3933 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 3934 (ctrl_exit_rev.clr & EXI_INTA))) 3935 return; 3936 3937 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 3938 3939 /* 3940 * Test virtual-interrupt-delivery and acknowledge-interrupt-on-exit 3941 */ 3942 pin |= PIN_POST_INTR; 3943 vmcs_write(PIN_CONTROLS, pin); 3944 secondary &= ~CPU_VINTD; 3945 vmcs_write(CPU_EXEC_CTRL1, secondary); 3946 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled"); 3947 test_vmx_invalid_controls(); 3948 report_prefix_pop(); 3949 3950 secondary |= CPU_VINTD; 3951 vmcs_write(CPU_EXEC_CTRL1, secondary); 3952 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled"); 3953 test_vmx_invalid_controls(); 3954 report_prefix_pop(); 3955 3956 exit_ctl &= ~EXI_INTA; 3957 vmcs_write(EXI_CONTROLS, exit_ctl); 3958 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit disabled"); 3959 test_vmx_invalid_controls(); 3960 report_prefix_pop(); 3961 3962 exit_ctl |= EXI_INTA; 3963 vmcs_write(EXI_CONTROLS, exit_ctl); 3964 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 3965 test_vmx_valid_controls(); 3966 report_prefix_pop(); 3967 3968 secondary &= ~CPU_VINTD; 3969 vmcs_write(CPU_EXEC_CTRL1, secondary); 3970 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled; acknowledge-interrupt-on-exit enabled"); 3971 test_vmx_invalid_controls(); 3972 report_prefix_pop(); 3973 3974 secondary |= CPU_VINTD; 3975 vmcs_write(CPU_EXEC_CTRL1, secondary); 3976 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 3977 test_vmx_valid_controls(); 3978 report_prefix_pop(); 3979 3980 /* 3981 * Test posted-interrupt notification vector 3982 */ 3983 for (i = 0; i < 8; i++) { 3984 vec = (1ul << i); 3985 vmcs_write(PINV, vec); 3986 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 3987 test_vmx_valid_controls(); 3988 report_prefix_pop(); 3989 } 3990 for (i = 8; i < 16; i++) { 3991 vec = (1ul << i); 3992 vmcs_write(PINV, vec); 3993 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 3994 test_vmx_invalid_controls(); 3995 report_prefix_pop(); 3996 } 3997 3998 vec &= ~(0xff << 8); 3999 vmcs_write(PINV, vec); 4000 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 4001 test_vmx_valid_controls(); 4002 report_prefix_pop(); 4003 4004 /* 4005 * Test posted-interrupt descriptor address 4006 */ 4007 for (i = 0; i < 6; i++) { 4008 test_pi_desc_addr(1ul << i, false); 4009 } 4010 4011 test_pi_desc_addr(0xf0, false); 4012 test_pi_desc_addr(0xff, false); 4013 test_pi_desc_addr(0x0f, false); 4014 test_pi_desc_addr(0x8000, true); 4015 test_pi_desc_addr(0x00, true); 4016 test_pi_desc_addr(0xc000, true); 4017 4018 test_vmcs_addr_values("process-posted interrupts", 4019 POSTED_INTR_DESC_ADDR, 64, 4020 false, false, 0, 63); 4021 4022 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 4023 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 4024 vmcs_write(PIN_CONTROLS, saved_pin); 4025 } 4026 4027 static void test_apic_ctls(void) 4028 { 4029 test_apic_virt_addr(); 4030 test_apic_access_addr(); 4031 test_apic_virtual_ctls(); 4032 test_virtual_intr_ctls(); 4033 test_posted_intr(); 4034 } 4035 4036 /* 4037 * If the "enable VPID" VM-execution control is 1, the value of the 4038 * of the VPID VM-execution control field must not be 0000H. 4039 * [Intel SDM] 4040 */ 4041 static void test_vpid(void) 4042 { 4043 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 4044 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 4045 u16 vpid = 0x0000; 4046 int i; 4047 4048 if (!is_vpid_supported()) { 4049 report_skip("%s : Secondary controls and/or VPID not supported", __func__); 4050 return; 4051 } 4052 4053 vmcs_write(CPU_EXEC_CTRL0, saved_primary | CPU_SECONDARY); 4054 vmcs_write(CPU_EXEC_CTRL1, saved_secondary & ~CPU_VPID); 4055 vmcs_write(VPID, vpid); 4056 report_prefix_pushf("VPID disabled; VPID value %x", vpid); 4057 test_vmx_valid_controls(); 4058 report_prefix_pop(); 4059 4060 vmcs_write(CPU_EXEC_CTRL1, saved_secondary | CPU_VPID); 4061 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 4062 test_vmx_invalid_controls(); 4063 report_prefix_pop(); 4064 4065 for (i = 0; i < 16; i++) { 4066 vpid = (short)1 << i;; 4067 vmcs_write(VPID, vpid); 4068 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 4069 test_vmx_valid_controls(); 4070 report_prefix_pop(); 4071 } 4072 4073 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 4074 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 4075 } 4076 4077 static void set_vtpr(unsigned vtpr) 4078 { 4079 *(u32 *)phys_to_virt(vmcs_read(APIC_VIRT_ADDR) + APIC_TASKPRI) = vtpr; 4080 } 4081 4082 static void try_tpr_threshold_and_vtpr(unsigned threshold, unsigned vtpr) 4083 { 4084 bool valid = true; 4085 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4086 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4087 4088 if ((primary & CPU_TPR_SHADOW) && 4089 (!(primary & CPU_SECONDARY) || 4090 !(secondary & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 4091 valid = (threshold & 0xf) <= ((vtpr >> 4) & 0xf); 4092 4093 set_vtpr(vtpr); 4094 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0x%x", 4095 threshold, (vtpr >> 4) & 0xf); 4096 if (valid) 4097 test_vmx_valid_controls(); 4098 else 4099 test_vmx_invalid_controls(); 4100 report_prefix_pop(); 4101 } 4102 4103 static void test_invalid_event_injection(void) 4104 { 4105 u32 ent_intr_info_save = vmcs_read(ENT_INTR_INFO); 4106 u32 ent_intr_error_save = vmcs_read(ENT_INTR_ERROR); 4107 u32 ent_inst_len_save = vmcs_read(ENT_INST_LEN); 4108 u32 primary_save = vmcs_read(CPU_EXEC_CTRL0); 4109 u32 secondary_save = vmcs_read(CPU_EXEC_CTRL1); 4110 u64 guest_cr0_save = vmcs_read(GUEST_CR0); 4111 u32 ent_intr_info_base = INTR_INFO_VALID_MASK; 4112 u32 ent_intr_info, ent_intr_err, ent_intr_len; 4113 u32 cnt; 4114 4115 /* Setup */ 4116 report_prefix_push("invalid event injection"); 4117 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4118 vmcs_write(ENT_INST_LEN, 0x00000001); 4119 4120 /* The field's interruption type is not set to a reserved value. */ 4121 ent_intr_info = ent_intr_info_base | INTR_TYPE_RESERVED | DE_VECTOR; 4122 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4123 "RESERVED interruption type invalid [-]", 4124 ent_intr_info); 4125 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4126 test_vmx_invalid_controls(); 4127 report_prefix_pop(); 4128 4129 ent_intr_info = ent_intr_info_base | INTR_TYPE_EXT_INTR | 4130 DE_VECTOR; 4131 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4132 "RESERVED interruption type invalid [+]", 4133 ent_intr_info); 4134 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4135 test_vmx_valid_controls(); 4136 report_prefix_pop(); 4137 4138 /* If the interruption type is other event, the vector is 0. */ 4139 ent_intr_info = ent_intr_info_base | INTR_TYPE_OTHER_EVENT | DB_VECTOR; 4140 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4141 "(OTHER EVENT && vector != 0) invalid [-]", 4142 ent_intr_info); 4143 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4144 test_vmx_invalid_controls(); 4145 report_prefix_pop(); 4146 4147 /* If the interruption type is NMI, the vector is 2 (negative case). */ 4148 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | DE_VECTOR; 4149 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4150 "(NMI && vector != 2) invalid [-]", ent_intr_info); 4151 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4152 test_vmx_invalid_controls(); 4153 report_prefix_pop(); 4154 4155 /* If the interruption type is NMI, the vector is 2 (positive case). */ 4156 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | NMI_VECTOR; 4157 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4158 "(NMI && vector == 2) valid [+]", ent_intr_info); 4159 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4160 test_vmx_valid_controls(); 4161 report_prefix_pop(); 4162 4163 /* 4164 * If the interruption type 4165 * is HW exception, the vector is at most 31. 4166 */ 4167 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 0x20; 4168 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4169 "(HW exception && vector > 31) invalid [-]", 4170 ent_intr_info); 4171 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4172 test_vmx_invalid_controls(); 4173 report_prefix_pop(); 4174 4175 /* 4176 * deliver-error-code is 1 iff either 4177 * (a) the "unrestricted guest" VM-execution control is 0 4178 * (b) CR0.PE is set. 4179 */ 4180 4181 /* Assert that unrestricted guest is disabled or unsupported */ 4182 assert(!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 4183 !(secondary_save & CPU_URG)); 4184 4185 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4186 GP_VECTOR; 4187 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4188 "error code <-> (!URG || prot_mode) [-]", 4189 ent_intr_info); 4190 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4191 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4192 test_vmx_invalid_controls(); 4193 report_prefix_pop(); 4194 4195 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4196 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4197 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4198 "error code <-> (!URG || prot_mode) [+]", 4199 ent_intr_info); 4200 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4201 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4202 test_vmx_valid_controls(); 4203 report_prefix_pop(); 4204 4205 if (enable_unrestricted_guest(false)) 4206 goto skip_unrestricted_guest; 4207 4208 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4209 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4210 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4211 "error code <-> (!URG || prot_mode) [-]", 4212 ent_intr_info); 4213 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4214 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4215 test_vmx_invalid_controls(); 4216 report_prefix_pop(); 4217 4218 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4219 GP_VECTOR; 4220 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4221 "error code <-> (!URG || prot_mode) [-]", 4222 ent_intr_info); 4223 vmcs_write(GUEST_CR0, guest_cr0_save | X86_CR0_PE); 4224 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4225 test_vmx_invalid_controls(); 4226 report_prefix_pop(); 4227 4228 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4229 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4230 4231 skip_unrestricted_guest: 4232 vmcs_write(GUEST_CR0, guest_cr0_save); 4233 4234 /* deliver-error-code is 1 iff the interruption type is HW exception */ 4235 report_prefix_push("error code <-> HW exception"); 4236 for (cnt = 0; cnt < 8; cnt++) { 4237 u32 exception_type_mask = cnt << 8; 4238 u32 deliver_error_code_mask = 4239 exception_type_mask != INTR_TYPE_HARD_EXCEPTION ? 4240 INTR_INFO_DELIVER_CODE_MASK : 0; 4241 4242 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4243 exception_type_mask | GP_VECTOR; 4244 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4245 ent_intr_info); 4246 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4247 test_vmx_invalid_controls(); 4248 report_prefix_pop(); 4249 } 4250 report_prefix_pop(); 4251 4252 /* 4253 * deliver-error-code is 1 iff the the vector 4254 * indicates an exception that would normally deliver an error code 4255 */ 4256 report_prefix_push("error code <-> vector delivers error code"); 4257 for (cnt = 0; cnt < 32; cnt++) { 4258 bool has_error_code = false; 4259 u32 deliver_error_code_mask; 4260 4261 switch (cnt) { 4262 case DF_VECTOR: 4263 case TS_VECTOR: 4264 case NP_VECTOR: 4265 case SS_VECTOR: 4266 case GP_VECTOR: 4267 case PF_VECTOR: 4268 case AC_VECTOR: 4269 has_error_code = true; 4270 case CP_VECTOR: 4271 /* Some CPUs have error code and some do not, skip */ 4272 continue; 4273 } 4274 4275 /* Negative case */ 4276 deliver_error_code_mask = has_error_code ? 4277 0 : 4278 INTR_INFO_DELIVER_CODE_MASK; 4279 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4280 INTR_TYPE_HARD_EXCEPTION | cnt; 4281 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4282 ent_intr_info); 4283 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4284 test_vmx_invalid_controls(); 4285 report_prefix_pop(); 4286 4287 /* Positive case */ 4288 deliver_error_code_mask = has_error_code ? 4289 INTR_INFO_DELIVER_CODE_MASK : 4290 0; 4291 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4292 INTR_TYPE_HARD_EXCEPTION | cnt; 4293 report_prefix_pushf("VM-entry intr info=0x%x [+]", 4294 ent_intr_info); 4295 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4296 test_vmx_valid_controls(); 4297 report_prefix_pop(); 4298 } 4299 report_prefix_pop(); 4300 4301 /* Reserved bits in the field (30:12) are 0. */ 4302 report_prefix_push("reserved bits clear"); 4303 for (cnt = 12; cnt <= 30; cnt++) { 4304 ent_intr_info = ent_intr_info_base | 4305 INTR_INFO_DELIVER_CODE_MASK | 4306 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR | 4307 (1U << cnt); 4308 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4309 ent_intr_info); 4310 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4311 test_vmx_invalid_controls(); 4312 report_prefix_pop(); 4313 } 4314 report_prefix_pop(); 4315 4316 /* 4317 * If deliver-error-code is 1 4318 * bits 31:16 of the VM-entry exception error-code field are 0. 4319 */ 4320 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4321 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4322 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4323 "VM-entry exception error code[31:16] clear", 4324 ent_intr_info); 4325 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4326 for (cnt = 16; cnt <= 31; cnt++) { 4327 ent_intr_err = 1U << cnt; 4328 report_prefix_pushf("VM-entry intr error=0x%x [-]", 4329 ent_intr_err); 4330 vmcs_write(ENT_INTR_ERROR, ent_intr_err); 4331 test_vmx_invalid_controls(); 4332 report_prefix_pop(); 4333 } 4334 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4335 report_prefix_pop(); 4336 4337 /* 4338 * If the interruption type is software interrupt, software exception, 4339 * or privileged software exception, the VM-entry instruction-length 4340 * field is in the range 0 - 15. 4341 */ 4342 4343 for (cnt = 0; cnt < 3; cnt++) { 4344 switch (cnt) { 4345 case 0: 4346 ent_intr_info = ent_intr_info_base | 4347 INTR_TYPE_SOFT_INTR; 4348 break; 4349 case 1: 4350 ent_intr_info = ent_intr_info_base | 4351 INTR_TYPE_SOFT_EXCEPTION; 4352 break; 4353 case 2: 4354 ent_intr_info = ent_intr_info_base | 4355 INTR_TYPE_PRIV_SW_EXCEPTION; 4356 break; 4357 } 4358 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4359 "VM-entry instruction-length check", 4360 ent_intr_info); 4361 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4362 4363 /* Instruction length set to -1 (0xFFFFFFFF) should fail */ 4364 ent_intr_len = -1; 4365 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4366 ent_intr_len); 4367 vmcs_write(ENT_INST_LEN, ent_intr_len); 4368 test_vmx_invalid_controls(); 4369 report_prefix_pop(); 4370 4371 /* Instruction length set to 16 should fail */ 4372 ent_intr_len = 0x00000010; 4373 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4374 ent_intr_len); 4375 vmcs_write(ENT_INST_LEN, 0x00000010); 4376 test_vmx_invalid_controls(); 4377 report_prefix_pop(); 4378 4379 report_prefix_pop(); 4380 } 4381 4382 /* Cleanup */ 4383 vmcs_write(ENT_INTR_INFO, ent_intr_info_save); 4384 vmcs_write(ENT_INTR_ERROR, ent_intr_error_save); 4385 vmcs_write(ENT_INST_LEN, ent_inst_len_save); 4386 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4387 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4388 vmcs_write(GUEST_CR0, guest_cr0_save); 4389 report_prefix_pop(); 4390 } 4391 4392 /* 4393 * Test interesting vTPR values for a given TPR threshold. 4394 */ 4395 static void test_vtpr_values(unsigned threshold) 4396 { 4397 try_tpr_threshold_and_vtpr(threshold, (threshold - 1) << 4); 4398 try_tpr_threshold_and_vtpr(threshold, threshold << 4); 4399 try_tpr_threshold_and_vtpr(threshold, (threshold + 1) << 4); 4400 } 4401 4402 static void try_tpr_threshold(unsigned threshold) 4403 { 4404 bool valid = true; 4405 4406 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4407 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4408 4409 if ((primary & CPU_TPR_SHADOW) && !((primary & CPU_SECONDARY) && 4410 (secondary & CPU_VINTD))) 4411 valid = !(threshold >> 4); 4412 4413 set_vtpr(-1); 4414 vmcs_write(TPR_THRESHOLD, threshold); 4415 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0xf", threshold); 4416 if (valid) 4417 test_vmx_valid_controls(); 4418 else 4419 test_vmx_invalid_controls(); 4420 report_prefix_pop(); 4421 4422 if (valid) 4423 test_vtpr_values(threshold); 4424 } 4425 4426 /* 4427 * Test interesting TPR threshold values. 4428 */ 4429 static void test_tpr_threshold_values(void) 4430 { 4431 unsigned i; 4432 4433 for (i = 0; i < 0x10; i++) 4434 try_tpr_threshold(i); 4435 for (i = 4; i < 32; i++) 4436 try_tpr_threshold(1u << i); 4437 try_tpr_threshold(-1u); 4438 try_tpr_threshold(0x7fffffff); 4439 } 4440 4441 /* 4442 * This test covers the following two VM entry checks: 4443 * 4444 * i) If the "use TPR shadow" VM-execution control is 1 and the 4445 * "virtual-interrupt delivery" VM-execution control is 0, bits 4446 * 31:4 of the TPR threshold VM-execution control field must 4447 be 0. 4448 * [Intel SDM] 4449 * 4450 * ii) If the "use TPR shadow" VM-execution control is 1, the 4451 * "virtual-interrupt delivery" VM-execution control is 0 4452 * and the "virtualize APIC accesses" VM-execution control 4453 * is 0, the value of bits 3:0 of the TPR threshold VM-execution 4454 * control field must not be greater than the value of bits 4455 * 7:4 of VTPR. 4456 * [Intel SDM] 4457 */ 4458 static void test_tpr_threshold(void) 4459 { 4460 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4461 u64 apic_virt_addr = vmcs_read(APIC_VIRT_ADDR); 4462 u64 threshold = vmcs_read(TPR_THRESHOLD); 4463 void *virtual_apic_page; 4464 4465 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) 4466 return; 4467 4468 virtual_apic_page = alloc_page(); 4469 memset(virtual_apic_page, 0xff, PAGE_SIZE); 4470 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 4471 4472 vmcs_write(CPU_EXEC_CTRL0, primary & ~(CPU_TPR_SHADOW | CPU_SECONDARY)); 4473 report_prefix_pushf("Use TPR shadow disabled, secondary controls disabled"); 4474 test_tpr_threshold_values(); 4475 report_prefix_pop(); 4476 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_TPR_SHADOW); 4477 report_prefix_pushf("Use TPR shadow enabled, secondary controls disabled"); 4478 test_tpr_threshold_values(); 4479 report_prefix_pop(); 4480 4481 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4482 (ctrl_cpu_rev[1].clr & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 4483 goto out; 4484 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4485 4486 if (ctrl_cpu_rev[1].clr & CPU_VINTD) { 4487 vmcs_write(CPU_EXEC_CTRL1, CPU_VINTD); 4488 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4489 test_tpr_threshold_values(); 4490 report_prefix_pop(); 4491 4492 vmcs_write(CPU_EXEC_CTRL0, 4493 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4494 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4495 test_tpr_threshold_values(); 4496 report_prefix_pop(); 4497 } 4498 4499 if (ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES) { 4500 vmcs_write(CPU_EXEC_CTRL0, 4501 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4502 vmcs_write(CPU_EXEC_CTRL1, CPU_VIRT_APIC_ACCESSES); 4503 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4504 test_tpr_threshold_values(); 4505 report_prefix_pop(); 4506 4507 vmcs_write(CPU_EXEC_CTRL0, 4508 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4509 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4510 test_tpr_threshold_values(); 4511 report_prefix_pop(); 4512 } 4513 4514 if ((ctrl_cpu_rev[1].clr & 4515 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) == 4516 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) { 4517 vmcs_write(CPU_EXEC_CTRL0, 4518 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4519 vmcs_write(CPU_EXEC_CTRL1, 4520 CPU_VINTD | CPU_VIRT_APIC_ACCESSES); 4521 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4522 test_tpr_threshold_values(); 4523 report_prefix_pop(); 4524 4525 vmcs_write(CPU_EXEC_CTRL0, 4526 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4527 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4528 test_tpr_threshold_values(); 4529 report_prefix_pop(); 4530 } 4531 4532 vmcs_write(CPU_EXEC_CTRL1, secondary); 4533 out: 4534 vmcs_write(TPR_THRESHOLD, threshold); 4535 vmcs_write(APIC_VIRT_ADDR, apic_virt_addr); 4536 vmcs_write(CPU_EXEC_CTRL0, primary); 4537 } 4538 4539 /* 4540 * This test verifies the following two vmentry checks: 4541 * 4542 * If the "NMI exiting" VM-execution control is 0, "Virtual NMIs" 4543 * VM-execution control must be 0. 4544 * [Intel SDM] 4545 * 4546 * If the "virtual NMIs" VM-execution control is 0, the "NMI-window 4547 * exiting" VM-execution control must be 0. 4548 * [Intel SDM] 4549 */ 4550 static void test_nmi_ctrls(void) 4551 { 4552 u32 pin_ctrls, cpu_ctrls0, test_pin_ctrls, test_cpu_ctrls0; 4553 4554 if ((ctrl_pin_rev.clr & (PIN_NMI | PIN_VIRT_NMI)) != 4555 (PIN_NMI | PIN_VIRT_NMI)) { 4556 report_skip("%s : NMI exiting and/or Virtual NMIs not supported", __func__); 4557 return; 4558 } 4559 4560 /* Save the controls so that we can restore them after our tests */ 4561 pin_ctrls = vmcs_read(PIN_CONTROLS); 4562 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 4563 4564 test_pin_ctrls = pin_ctrls & ~(PIN_NMI | PIN_VIRT_NMI); 4565 test_cpu_ctrls0 = cpu_ctrls0 & ~CPU_NMI_WINDOW; 4566 4567 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4568 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs disabled"); 4569 test_vmx_valid_controls(); 4570 report_prefix_pop(); 4571 4572 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_VIRT_NMI); 4573 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs enabled"); 4574 test_vmx_invalid_controls(); 4575 report_prefix_pop(); 4576 4577 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4578 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs enabled"); 4579 test_vmx_valid_controls(); 4580 report_prefix_pop(); 4581 4582 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_NMI); 4583 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs disabled"); 4584 test_vmx_valid_controls(); 4585 report_prefix_pop(); 4586 4587 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 4588 report_info("NMI-window exiting is not supported, skipping..."); 4589 goto done; 4590 } 4591 4592 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4593 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4594 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting enabled"); 4595 test_vmx_invalid_controls(); 4596 report_prefix_pop(); 4597 4598 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4599 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4600 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting disabled"); 4601 test_vmx_valid_controls(); 4602 report_prefix_pop(); 4603 4604 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4605 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4606 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting enabled"); 4607 test_vmx_valid_controls(); 4608 report_prefix_pop(); 4609 4610 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4611 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4612 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting disabled"); 4613 test_vmx_valid_controls(); 4614 report_prefix_pop(); 4615 4616 /* Restore the controls to their original values */ 4617 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 4618 done: 4619 vmcs_write(PIN_CONTROLS, pin_ctrls); 4620 } 4621 4622 static void test_eptp_ad_bit(u64 eptp, bool is_ctrl_valid) 4623 { 4624 vmcs_write(EPTP, eptp); 4625 report_prefix_pushf("Enable-EPT enabled; EPT accessed and dirty flag %s", 4626 (eptp & EPTP_AD_FLAG) ? "1": "0"); 4627 if (is_ctrl_valid) 4628 test_vmx_valid_controls(); 4629 else 4630 test_vmx_invalid_controls(); 4631 report_prefix_pop(); 4632 4633 } 4634 4635 /* 4636 * 1. If the "enable EPT" VM-execution control is 1, the "EPTP VM-execution" 4637 * control field must satisfy the following checks: 4638 * 4639 * - The EPT memory type (bits 2:0) must be a value supported by the 4640 * processor as indicated in the IA32_VMX_EPT_VPID_CAP MSR. 4641 * - Bits 5:3 (1 less than the EPT page-walk length) must indicate a 4642 * supported EPT page-walk length. 4643 * - Bit 6 (enable bit for accessed and dirty flags for EPT) must be 4644 * 0 if bit 21 of the IA32_VMX_EPT_VPID_CAP MSR is read as 0, 4645 * indicating that the processor does not support accessed and dirty 4646 * dirty flags for EPT. 4647 * - Reserved bits 11:7 and 63:N (where N is the processor's 4648 * physical-address width) must all be 0. 4649 * 4650 * 2. If the "unrestricted guest" VM-execution control is 1, the 4651 * "enable EPT" VM-execution control must also be 1. 4652 */ 4653 static void test_ept_eptp(void) 4654 { 4655 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4656 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4657 u64 eptp_saved = vmcs_read(EPTP); 4658 u32 primary = primary_saved; 4659 u32 secondary = secondary_saved; 4660 u64 eptp = eptp_saved; 4661 u32 i, maxphysaddr; 4662 u64 j, resv_bits_mask = 0; 4663 4664 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4665 (ctrl_cpu_rev[1].clr & CPU_EPT))) { 4666 report_skip("%s : \"CPU secondary\" and/or \"enable EPT\" exec control not supported", __func__); 4667 return; 4668 } 4669 4670 /* Support for 4-level EPT is mandatory. */ 4671 report(is_4_level_ept_supported(), "4-level EPT support check"); 4672 4673 primary |= CPU_SECONDARY; 4674 vmcs_write(CPU_EXEC_CTRL0, primary); 4675 secondary |= CPU_EPT; 4676 vmcs_write(CPU_EXEC_CTRL1, secondary); 4677 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4678 (3ul << EPTP_PG_WALK_LEN_SHIFT); 4679 vmcs_write(EPTP, eptp); 4680 4681 for (i = 0; i < 8; i++) { 4682 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | i; 4683 vmcs_write(EPTP, eptp); 4684 report_prefix_pushf("Enable-EPT enabled; EPT memory type %lu", 4685 eptp & EPT_MEM_TYPE_MASK); 4686 if (is_ept_memtype_supported(i)) 4687 test_vmx_valid_controls(); 4688 else 4689 test_vmx_invalid_controls(); 4690 report_prefix_pop(); 4691 } 4692 4693 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | 6ul; 4694 4695 /* 4696 * Page walk length (bits 5:3). Note, the value in VMCS.EPTP "is 1 4697 * less than the EPT page-walk length". 4698 */ 4699 for (i = 0; i < 8; i++) { 4700 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4701 (i << EPTP_PG_WALK_LEN_SHIFT); 4702 4703 vmcs_write(EPTP, eptp); 4704 report_prefix_pushf("Enable-EPT enabled; EPT page walk length %lu", 4705 eptp & EPTP_PG_WALK_LEN_MASK); 4706 if (i == 3 || (i == 4 && is_5_level_ept_supported())) 4707 test_vmx_valid_controls(); 4708 else 4709 test_vmx_invalid_controls(); 4710 report_prefix_pop(); 4711 } 4712 4713 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4714 3ul << EPTP_PG_WALK_LEN_SHIFT; 4715 4716 /* 4717 * Accessed and dirty flag (bit 6) 4718 */ 4719 if (ept_ad_bits_supported()) { 4720 report_info("Processor supports accessed and dirty flag"); 4721 eptp &= ~EPTP_AD_FLAG; 4722 test_eptp_ad_bit(eptp, true); 4723 4724 eptp |= EPTP_AD_FLAG; 4725 test_eptp_ad_bit(eptp, true); 4726 } else { 4727 report_info("Processor does not supports accessed and dirty flag"); 4728 eptp &= ~EPTP_AD_FLAG; 4729 test_eptp_ad_bit(eptp, true); 4730 4731 eptp |= EPTP_AD_FLAG; 4732 test_eptp_ad_bit(eptp, false); 4733 } 4734 4735 /* 4736 * Reserved bits [11:7] and [63:N] 4737 */ 4738 for (i = 0; i < 32; i++) { 4739 eptp = (eptp & 4740 ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)) | 4741 (i << EPTP_RESERV_BITS_SHIFT); 4742 vmcs_write(EPTP, eptp); 4743 report_prefix_pushf("Enable-EPT enabled; reserved bits [11:7] %lu", 4744 (eptp >> EPTP_RESERV_BITS_SHIFT) & 4745 EPTP_RESERV_BITS_MASK); 4746 if (i == 0) 4747 test_vmx_valid_controls(); 4748 else 4749 test_vmx_invalid_controls(); 4750 report_prefix_pop(); 4751 } 4752 4753 eptp = (eptp & ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)); 4754 4755 maxphysaddr = cpuid_maxphyaddr(); 4756 for (i = 0; i < (63 - maxphysaddr + 1); i++) { 4757 resv_bits_mask |= 1ul << i; 4758 } 4759 4760 for (j = maxphysaddr - 1; j <= 63; j++) { 4761 eptp = (eptp & ~(resv_bits_mask << maxphysaddr)) | 4762 (j < maxphysaddr ? 0 : 1ul << j); 4763 vmcs_write(EPTP, eptp); 4764 report_prefix_pushf("Enable-EPT enabled; reserved bits [63:N] %lu", 4765 (eptp >> maxphysaddr) & resv_bits_mask); 4766 if (j < maxphysaddr) 4767 test_vmx_valid_controls(); 4768 else 4769 test_vmx_invalid_controls(); 4770 report_prefix_pop(); 4771 } 4772 4773 secondary &= ~(CPU_EPT | CPU_URG); 4774 vmcs_write(CPU_EXEC_CTRL1, secondary); 4775 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest disabled"); 4776 test_vmx_valid_controls(); 4777 report_prefix_pop(); 4778 4779 if (!(ctrl_cpu_rev[1].clr & CPU_URG)) 4780 goto skip_unrestricted_guest; 4781 4782 secondary |= CPU_URG; 4783 vmcs_write(CPU_EXEC_CTRL1, secondary); 4784 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest enabled"); 4785 test_vmx_invalid_controls(); 4786 report_prefix_pop(); 4787 4788 secondary |= CPU_EPT; 4789 setup_dummy_ept(); 4790 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest enabled"); 4791 test_vmx_valid_controls(); 4792 report_prefix_pop(); 4793 4794 skip_unrestricted_guest: 4795 secondary &= ~CPU_URG; 4796 vmcs_write(CPU_EXEC_CTRL1, secondary); 4797 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest disabled"); 4798 test_vmx_valid_controls(); 4799 report_prefix_pop(); 4800 4801 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4802 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4803 vmcs_write(EPTP, eptp_saved); 4804 } 4805 4806 /* 4807 * If the 'enable PML' VM-execution control is 1, the 'enable EPT' 4808 * VM-execution control must also be 1. In addition, the PML address 4809 * must satisfy the following checks: 4810 * 4811 * * Bits 11:0 of the address must be 0. 4812 * * The address should not set any bits beyond the processor's 4813 * physical-address width. 4814 * 4815 * [Intel SDM] 4816 */ 4817 static void test_pml(void) 4818 { 4819 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4820 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4821 u32 primary = primary_saved; 4822 u32 secondary = secondary_saved; 4823 4824 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4825 (ctrl_cpu_rev[1].clr & CPU_EPT) && (ctrl_cpu_rev[1].clr & CPU_PML))) { 4826 report_skip("%s : \"Secondary execution\" or \"enable EPT\" or \"enable PML\" control not supported", __func__); 4827 return; 4828 } 4829 4830 primary |= CPU_SECONDARY; 4831 vmcs_write(CPU_EXEC_CTRL0, primary); 4832 secondary &= ~(CPU_PML | CPU_EPT); 4833 vmcs_write(CPU_EXEC_CTRL1, secondary); 4834 report_prefix_pushf("enable-PML disabled, enable-EPT disabled"); 4835 test_vmx_valid_controls(); 4836 report_prefix_pop(); 4837 4838 secondary |= CPU_PML; 4839 vmcs_write(CPU_EXEC_CTRL1, secondary); 4840 report_prefix_pushf("enable-PML enabled, enable-EPT disabled"); 4841 test_vmx_invalid_controls(); 4842 report_prefix_pop(); 4843 4844 secondary |= CPU_EPT; 4845 setup_dummy_ept(); 4846 report_prefix_pushf("enable-PML enabled, enable-EPT enabled"); 4847 test_vmx_valid_controls(); 4848 report_prefix_pop(); 4849 4850 secondary &= ~CPU_PML; 4851 vmcs_write(CPU_EXEC_CTRL1, secondary); 4852 report_prefix_pushf("enable-PML disabled, enable EPT enabled"); 4853 test_vmx_valid_controls(); 4854 report_prefix_pop(); 4855 4856 test_vmcs_addr_reference(CPU_PML, PMLADDR, "PML address", "PML", 4857 PAGE_SIZE, false, false); 4858 4859 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4860 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4861 } 4862 4863 /* 4864 * If the "activate VMX-preemption timer" VM-execution control is 0, the 4865 * the "save VMX-preemption timer value" VM-exit control must also be 0. 4866 * 4867 * [Intel SDM] 4868 */ 4869 static void test_vmx_preemption_timer(void) 4870 { 4871 u32 saved_pin = vmcs_read(PIN_CONTROLS); 4872 u32 saved_exit = vmcs_read(EXI_CONTROLS); 4873 u32 pin = saved_pin; 4874 u32 exit = saved_exit; 4875 4876 if (!((ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) || 4877 (ctrl_pin_rev.clr & PIN_PREEMPT))) { 4878 report_skip("%s : \"Save-VMX-preemption-timer\" and/or \"Enable-VMX-preemption-timer\" control not supported", __func__); 4879 return; 4880 } 4881 4882 pin |= PIN_PREEMPT; 4883 vmcs_write(PIN_CONTROLS, pin); 4884 exit &= ~EXI_SAVE_PREEMPT; 4885 vmcs_write(EXI_CONTROLS, exit); 4886 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer disabled"); 4887 test_vmx_valid_controls(); 4888 report_prefix_pop(); 4889 4890 exit |= EXI_SAVE_PREEMPT; 4891 vmcs_write(EXI_CONTROLS, exit); 4892 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer enabled"); 4893 test_vmx_valid_controls(); 4894 report_prefix_pop(); 4895 4896 pin &= ~PIN_PREEMPT; 4897 vmcs_write(PIN_CONTROLS, pin); 4898 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer enabled"); 4899 test_vmx_invalid_controls(); 4900 report_prefix_pop(); 4901 4902 exit &= ~EXI_SAVE_PREEMPT; 4903 vmcs_write(EXI_CONTROLS, exit); 4904 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer disabled"); 4905 test_vmx_valid_controls(); 4906 report_prefix_pop(); 4907 4908 vmcs_write(PIN_CONTROLS, saved_pin); 4909 vmcs_write(EXI_CONTROLS, saved_exit); 4910 } 4911 4912 extern unsigned char test_mtf1; 4913 extern unsigned char test_mtf2; 4914 extern unsigned char test_mtf3; 4915 extern unsigned char test_mtf4; 4916 4917 static void test_mtf_guest(void) 4918 { 4919 asm ("vmcall;\n\t" 4920 "out %al, $0x80;\n\t" 4921 "test_mtf1:\n\t" 4922 "vmcall;\n\t" 4923 "out %al, $0x80;\n\t" 4924 "test_mtf2:\n\t" 4925 /* 4926 * Prepare for the 'MOV CR3' test. Attempt to induce a 4927 * general-protection fault by moving a non-canonical address into 4928 * CR3. The 'MOV CR3' instruction does not take an imm64 operand, 4929 * so we must MOV the desired value into a register first. 4930 * 4931 * MOV RAX is done before the VMCALL such that MTF is only enabled 4932 * for the instruction under test. 4933 */ 4934 "mov $0xaaaaaaaaaaaaaaaa, %rax;\n\t" 4935 "vmcall;\n\t" 4936 "mov %rax, %cr3;\n\t" 4937 "test_mtf3:\n\t" 4938 "vmcall;\n\t" 4939 /* 4940 * ICEBP/INT1 instruction. Though the instruction is now 4941 * documented, don't rely on assemblers enumerating the 4942 * instruction. Resort to hand assembly. 4943 */ 4944 ".byte 0xf1;\n\t" 4945 "vmcall;\n\t" 4946 "test_mtf4:\n\t" 4947 "mov $0, %eax;\n\t"); 4948 } 4949 4950 static void test_mtf_gp_handler(struct ex_regs *regs) 4951 { 4952 regs->rip = (unsigned long) &test_mtf3; 4953 } 4954 4955 static void test_mtf_db_handler(struct ex_regs *regs) 4956 { 4957 } 4958 4959 static void enable_mtf(void) 4960 { 4961 u32 ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 4962 4963 vmcs_write(CPU_EXEC_CTRL0, ctrl0 | CPU_MTF); 4964 } 4965 4966 static void disable_mtf(void) 4967 { 4968 u32 ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 4969 4970 vmcs_write(CPU_EXEC_CTRL0, ctrl0 & ~CPU_MTF); 4971 } 4972 4973 static void enable_tf(void) 4974 { 4975 unsigned long rflags = vmcs_read(GUEST_RFLAGS); 4976 4977 vmcs_write(GUEST_RFLAGS, rflags | X86_EFLAGS_TF); 4978 } 4979 4980 static void disable_tf(void) 4981 { 4982 unsigned long rflags = vmcs_read(GUEST_RFLAGS); 4983 4984 vmcs_write(GUEST_RFLAGS, rflags & ~X86_EFLAGS_TF); 4985 } 4986 4987 static void report_mtf(const char *insn_name, unsigned long exp_rip) 4988 { 4989 unsigned long rip = vmcs_read(GUEST_RIP); 4990 4991 assert_exit_reason(VMX_MTF); 4992 report(rip == exp_rip, "MTF VM-exit after %s. RIP: 0x%lx (expected 0x%lx)", 4993 insn_name, rip, exp_rip); 4994 } 4995 4996 static void vmx_mtf_test(void) 4997 { 4998 unsigned long pending_dbg; 4999 handler old_gp, old_db; 5000 5001 if (!(ctrl_cpu_rev[0].clr & CPU_MTF)) { 5002 report_skip("%s : \"Monitor trap flag\" exec control not supported", __func__); 5003 return; 5004 } 5005 5006 test_set_guest(test_mtf_guest); 5007 5008 /* Expect an MTF VM-exit after OUT instruction */ 5009 enter_guest(); 5010 skip_exit_vmcall(); 5011 5012 enable_mtf(); 5013 enter_guest(); 5014 report_mtf("OUT", (unsigned long) &test_mtf1); 5015 disable_mtf(); 5016 5017 /* 5018 * Concurrent #DB trap and MTF on instruction boundary. Expect MTF 5019 * VM-exit with populated 'pending debug exceptions' VMCS field. 5020 */ 5021 enter_guest(); 5022 skip_exit_vmcall(); 5023 5024 enable_mtf(); 5025 enable_tf(); 5026 5027 enter_guest(); 5028 report_mtf("OUT", (unsigned long) &test_mtf2); 5029 pending_dbg = vmcs_read(GUEST_PENDING_DEBUG); 5030 report(pending_dbg & DR6_BS, 5031 "'pending debug exceptions' field after MTF VM-exit: 0x%lx (expected 0x%lx)", 5032 pending_dbg, (unsigned long) DR6_BS); 5033 5034 disable_mtf(); 5035 disable_tf(); 5036 vmcs_write(GUEST_PENDING_DEBUG, 0); 5037 5038 /* 5039 * #GP exception takes priority over MTF. Expect MTF VM-exit with RIP 5040 * advanced to first instruction of #GP handler. 5041 */ 5042 enter_guest(); 5043 skip_exit_vmcall(); 5044 5045 old_gp = handle_exception(GP_VECTOR, test_mtf_gp_handler); 5046 5047 enable_mtf(); 5048 enter_guest(); 5049 report_mtf("MOV CR3", (unsigned long) get_idt_addr(&boot_idt[GP_VECTOR])); 5050 disable_mtf(); 5051 5052 /* 5053 * Concurrent MTF and privileged software exception (i.e. ICEBP/INT1). 5054 * MTF should follow the delivery of #DB trap, though the SDM doesn't 5055 * provide clear indication of the relative priority. 5056 */ 5057 enter_guest(); 5058 skip_exit_vmcall(); 5059 5060 handle_exception(GP_VECTOR, old_gp); 5061 old_db = handle_exception(DB_VECTOR, test_mtf_db_handler); 5062 5063 enable_mtf(); 5064 enter_guest(); 5065 report_mtf("INT1", (unsigned long) get_idt_addr(&boot_idt[DB_VECTOR])); 5066 disable_mtf(); 5067 5068 enter_guest(); 5069 skip_exit_vmcall(); 5070 handle_exception(DB_VECTOR, old_db); 5071 vmcs_write(ENT_INTR_INFO, INTR_INFO_VALID_MASK | INTR_TYPE_OTHER_EVENT); 5072 enter_guest(); 5073 report_mtf("injected MTF", (unsigned long) &test_mtf4); 5074 enter_guest(); 5075 } 5076 5077 extern char vmx_mtf_pdpte_guest_begin; 5078 extern char vmx_mtf_pdpte_guest_end; 5079 5080 asm("vmx_mtf_pdpte_guest_begin:\n\t" 5081 "mov %cr0, %rax\n\t" /* save CR0 with PG=1 */ 5082 "vmcall\n\t" /* on return from this CR0.PG=0 */ 5083 "mov %rax, %cr0\n\t" /* restore CR0.PG=1 to enter PAE mode */ 5084 "vmcall\n\t" 5085 "retq\n\t" 5086 "vmx_mtf_pdpte_guest_end:"); 5087 5088 static void vmx_mtf_pdpte_test(void) 5089 { 5090 void *test_mtf_pdpte_guest; 5091 pteval_t *pdpt; 5092 u32 guest_ar_cs; 5093 u64 guest_efer; 5094 pteval_t *pte; 5095 u64 guest_cr0; 5096 u64 guest_cr3; 5097 u64 guest_cr4; 5098 u64 ent_ctls; 5099 int i; 5100 5101 if (setup_ept(false)) 5102 return; 5103 5104 if (!(ctrl_cpu_rev[0].clr & CPU_MTF)) { 5105 report_skip("%s : \"Monitor trap flag\" exec control not supported", __func__); 5106 return; 5107 } 5108 5109 if (!(ctrl_cpu_rev[1].clr & CPU_URG)) { 5110 report_skip("%s : \"Unrestricted guest\" exec control not supported", __func__); 5111 return; 5112 } 5113 5114 vmcs_write(EXC_BITMAP, ~0); 5115 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | CPU_URG); 5116 5117 /* 5118 * Copy the guest code to an identity-mapped page. 5119 */ 5120 test_mtf_pdpte_guest = alloc_page(); 5121 memcpy(test_mtf_pdpte_guest, &vmx_mtf_pdpte_guest_begin, 5122 &vmx_mtf_pdpte_guest_end - &vmx_mtf_pdpte_guest_begin); 5123 5124 test_set_guest(test_mtf_pdpte_guest); 5125 5126 enter_guest(); 5127 skip_exit_vmcall(); 5128 5129 /* 5130 * Put the guest in non-paged 32-bit protected mode, ready to enter 5131 * PAE mode when CR0.PG is set. CR4.PAE will already have been set 5132 * when the guest started out in long mode. 5133 */ 5134 ent_ctls = vmcs_read(ENT_CONTROLS); 5135 vmcs_write(ENT_CONTROLS, ent_ctls & ~ENT_GUEST_64); 5136 5137 guest_efer = vmcs_read(GUEST_EFER); 5138 vmcs_write(GUEST_EFER, guest_efer & ~(EFER_LMA | EFER_LME)); 5139 5140 /* 5141 * Set CS access rights bits for 32-bit protected mode: 5142 * 3:0 B execute/read/accessed 5143 * 4 1 code or data 5144 * 6:5 0 descriptor privilege level 5145 * 7 1 present 5146 * 11:8 0 reserved 5147 * 12 0 available for use by system software 5148 * 13 0 64 bit mode not active 5149 * 14 1 default operation size 32-bit segment 5150 * 15 1 page granularity: segment limit in 4K units 5151 * 16 0 segment usable 5152 * 31:17 0 reserved 5153 */ 5154 guest_ar_cs = vmcs_read(GUEST_AR_CS); 5155 vmcs_write(GUEST_AR_CS, 0xc09b); 5156 5157 guest_cr0 = vmcs_read(GUEST_CR0); 5158 vmcs_write(GUEST_CR0, guest_cr0 & ~X86_CR0_PG); 5159 5160 guest_cr4 = vmcs_read(GUEST_CR4); 5161 vmcs_write(GUEST_CR4, guest_cr4 & ~X86_CR4_PCIDE); 5162 5163 guest_cr3 = vmcs_read(GUEST_CR3); 5164 5165 /* 5166 * Turn the 4-level page table into a PAE page table by following the 0th 5167 * PML4 entry to a PDPT page, and grab the first four PDPTEs from that 5168 * page. 5169 * 5170 * Why does this work? 5171 * 5172 * PAE uses 32-bit addressing which implies: 5173 * Bits 11:0 page offset 5174 * Bits 20:12 entry into 512-entry page table 5175 * Bits 29:21 entry into a 512-entry directory table 5176 * Bits 31:30 entry into the page directory pointer table. 5177 * Bits 63:32 zero 5178 * 5179 * As only 2 bits are needed to select the PDPTEs for the entire 5180 * 32-bit address space, take the first 4 PDPTEs in the level 3 page 5181 * directory pointer table. It doesn't matter which of these PDPTEs 5182 * are present because they must cover the guest code given that it 5183 * has already run successfully. 5184 * 5185 * Get a pointer to PTE for GVA=0 in the page directory pointer table 5186 */ 5187 pte = get_pte_level( 5188 (pgd_t *)phys_to_virt(guest_cr3 & ~X86_CR3_PCID_MASK), 0, 5189 PDPT_LEVEL); 5190 5191 /* 5192 * Need some memory for the 4-entry PAE page directory pointer 5193 * table. Use the end of the identity-mapped page where the guest code 5194 * is stored. There is definitely space as the guest code is only a 5195 * few bytes. 5196 */ 5197 pdpt = test_mtf_pdpte_guest + PAGE_SIZE - 4 * sizeof(pteval_t); 5198 5199 /* 5200 * Copy the first four PDPTEs into the PAE page table with reserved 5201 * bits cleared. Note that permission bits from the PML4E and PDPTE 5202 * are not propagated. 5203 */ 5204 for (i = 0; i < 4; i++) { 5205 TEST_ASSERT_EQ_MSG(0, (pte[i] & PDPTE64_RSVD_MASK), 5206 "PDPTE has invalid reserved bits"); 5207 TEST_ASSERT_EQ_MSG(0, (pte[i] & PDPTE64_PAGE_SIZE_MASK), 5208 "Cannot use 1GB super pages for PAE"); 5209 pdpt[i] = pte[i] & ~(PAE_PDPTE_RSVD_MASK); 5210 } 5211 vmcs_write(GUEST_CR3, virt_to_phys(pdpt)); 5212 5213 enable_mtf(); 5214 enter_guest(); 5215 assert_exit_reason(VMX_MTF); 5216 disable_mtf(); 5217 5218 /* 5219 * The four PDPTEs should have been loaded into the VMCS when 5220 * the guest set CR0.PG to enter PAE mode. 5221 */ 5222 for (i = 0; i < 4; i++) { 5223 u64 pdpte = vmcs_read(GUEST_PDPTE + 2 * i); 5224 5225 report(pdpte == pdpt[i], "PDPTE%d is 0x%lx (expected 0x%lx)", 5226 i, pdpte, pdpt[i]); 5227 } 5228 5229 /* 5230 * Now, try to enter the guest in PAE mode. If the PDPTEs in the 5231 * vmcs are wrong, this will fail. 5232 */ 5233 enter_guest(); 5234 skip_exit_vmcall(); 5235 5236 /* 5237 * Return guest to 64-bit mode and wrap up. 5238 */ 5239 vmcs_write(ENT_CONTROLS, ent_ctls); 5240 vmcs_write(GUEST_EFER, guest_efer); 5241 vmcs_write(GUEST_AR_CS, guest_ar_cs); 5242 vmcs_write(GUEST_CR0, guest_cr0); 5243 vmcs_write(GUEST_CR4, guest_cr4); 5244 vmcs_write(GUEST_CR3, guest_cr3); 5245 5246 enter_guest(); 5247 } 5248 5249 /* 5250 * Tests for VM-execution control fields 5251 */ 5252 static void test_vm_execution_ctls(void) 5253 { 5254 test_pin_based_ctls(); 5255 test_primary_processor_based_ctls(); 5256 test_secondary_processor_based_ctls(); 5257 test_cr3_targets(); 5258 test_io_bitmaps(); 5259 test_msr_bitmap(); 5260 test_apic_ctls(); 5261 test_tpr_threshold(); 5262 test_nmi_ctrls(); 5263 test_pml(); 5264 test_vpid(); 5265 test_ept_eptp(); 5266 test_vmx_preemption_timer(); 5267 } 5268 5269 /* 5270 * The following checks are performed for the VM-entry MSR-load address if 5271 * the VM-entry MSR-load count field is non-zero: 5272 * 5273 * - The lower 4 bits of the VM-entry MSR-load address must be 0. 5274 * The address should not set any bits beyond the processor's 5275 * physical-address width. 5276 * 5277 * - The address of the last byte in the VM-entry MSR-load area 5278 * should not set any bits beyond the processor's physical-address 5279 * width. The address of this last byte is VM-entry MSR-load address 5280 * + (MSR count * 16) - 1. (The arithmetic used for the computation 5281 * uses more bits than the processor's physical-address width.) 5282 * 5283 * 5284 * [Intel SDM] 5285 */ 5286 static void test_entry_msr_load(void) 5287 { 5288 entry_msr_load = alloc_page(); 5289 u64 tmp; 5290 u32 entry_msr_ld_cnt = 1; 5291 int i; 5292 u32 addr_len = 64; 5293 5294 vmcs_write(ENT_MSR_LD_CNT, entry_msr_ld_cnt); 5295 5296 /* Check first 4 bits of VM-entry MSR-load address */ 5297 for (i = 0; i < 4; i++) { 5298 tmp = (u64)entry_msr_load | 1ull << i; 5299 vmcs_write(ENTER_MSR_LD_ADDR, tmp); 5300 report_prefix_pushf("VM-entry MSR-load addr [4:0] %lx", 5301 tmp & 0xf); 5302 test_vmx_invalid_controls(); 5303 report_prefix_pop(); 5304 } 5305 5306 if (basic.val & (1ul << 48)) 5307 addr_len = 32; 5308 5309 test_vmcs_addr_values("VM-entry-MSR-load address", 5310 ENTER_MSR_LD_ADDR, 16, false, false, 5311 4, addr_len - 1); 5312 5313 /* 5314 * Check last byte of VM-entry MSR-load address 5315 */ 5316 entry_msr_load = (struct vmx_msr_entry *)((u64)entry_msr_load & ~0xf); 5317 5318 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 5319 i < 64; i++) { 5320 tmp = ((u64)entry_msr_load + entry_msr_ld_cnt * 16 - 1) | 5321 1ul << i; 5322 vmcs_write(ENTER_MSR_LD_ADDR, 5323 tmp - (entry_msr_ld_cnt * 16 - 1)); 5324 test_vmx_invalid_controls(); 5325 } 5326 5327 vmcs_write(ENT_MSR_LD_CNT, 2); 5328 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 5329 test_vmx_invalid_controls(); 5330 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 5331 test_vmx_valid_controls(); 5332 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 5333 test_vmx_valid_controls(); 5334 } 5335 5336 static struct vmx_state_area_test_data { 5337 u32 msr; 5338 u64 exp; 5339 bool enabled; 5340 } vmx_state_area_test_data; 5341 5342 static void guest_state_test_main(void) 5343 { 5344 u64 obs; 5345 struct vmx_state_area_test_data *data = &vmx_state_area_test_data; 5346 5347 while (1) { 5348 if (vmx_get_test_stage() == 2) 5349 break; 5350 5351 if (data->enabled) { 5352 obs = rdmsr(data->msr); 5353 report(data->exp == obs, 5354 "Guest state is 0x%lx (expected 0x%lx)", 5355 obs, data->exp); 5356 } 5357 5358 vmcall(); 5359 } 5360 5361 asm volatile("fnop"); 5362 } 5363 5364 static void test_guest_state(const char *test, bool xfail, u64 field, 5365 const char * field_name) 5366 { 5367 struct vmentry_result result; 5368 u8 abort_flags; 5369 5370 abort_flags = ABORT_ON_EARLY_VMENTRY_FAIL; 5371 if (!xfail) 5372 abort_flags = ABORT_ON_INVALID_GUEST_STATE; 5373 5374 __enter_guest(abort_flags, &result); 5375 5376 report(result.exit_reason.failed_vmentry == xfail && 5377 ((xfail && result.exit_reason.basic == VMX_FAIL_STATE) || 5378 (!xfail && result.exit_reason.basic == VMX_VMCALL)) && 5379 (!xfail || vmcs_read(EXI_QUALIFICATION) == ENTRY_FAIL_DEFAULT), 5380 "%s, %s = %lx", test, field_name, field); 5381 5382 if (!result.exit_reason.failed_vmentry) 5383 skip_exit_insn(); 5384 } 5385 5386 /* 5387 * Tests for VM-entry control fields 5388 */ 5389 static void test_vm_entry_ctls(void) 5390 { 5391 test_invalid_event_injection(); 5392 test_entry_msr_load(); 5393 } 5394 5395 /* 5396 * The following checks are performed for the VM-exit MSR-store address if 5397 * the VM-exit MSR-store count field is non-zero: 5398 * 5399 * - The lower 4 bits of the VM-exit MSR-store address must be 0. 5400 * The address should not set any bits beyond the processor's 5401 * physical-address width. 5402 * 5403 * - The address of the last byte in the VM-exit MSR-store area 5404 * should not set any bits beyond the processor's physical-address 5405 * width. The address of this last byte is VM-exit MSR-store address 5406 * + (MSR count * 16) - 1. (The arithmetic used for the computation 5407 * uses more bits than the processor's physical-address width.) 5408 * 5409 * If IA32_VMX_BASIC[48] is read as 1, neither address should set any bits 5410 * in the range 63:32. 5411 * 5412 * [Intel SDM] 5413 */ 5414 static void test_exit_msr_store(void) 5415 { 5416 exit_msr_store = alloc_page(); 5417 u64 tmp; 5418 u32 exit_msr_st_cnt = 1; 5419 int i; 5420 u32 addr_len = 64; 5421 5422 vmcs_write(EXI_MSR_ST_CNT, exit_msr_st_cnt); 5423 5424 /* Check first 4 bits of VM-exit MSR-store address */ 5425 for (i = 0; i < 4; i++) { 5426 tmp = (u64)exit_msr_store | 1ull << i; 5427 vmcs_write(EXIT_MSR_ST_ADDR, tmp); 5428 report_prefix_pushf("VM-exit MSR-store addr [4:0] %lx", 5429 tmp & 0xf); 5430 test_vmx_invalid_controls(); 5431 report_prefix_pop(); 5432 } 5433 5434 if (basic.val & (1ul << 48)) 5435 addr_len = 32; 5436 5437 test_vmcs_addr_values("VM-exit-MSR-store address", 5438 EXIT_MSR_ST_ADDR, 16, false, false, 5439 4, addr_len - 1); 5440 5441 /* 5442 * Check last byte of VM-exit MSR-store address 5443 */ 5444 exit_msr_store = (struct vmx_msr_entry *)((u64)exit_msr_store & ~0xf); 5445 5446 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 5447 i < 64; i++) { 5448 tmp = ((u64)exit_msr_store + exit_msr_st_cnt * 16 - 1) | 5449 1ul << i; 5450 vmcs_write(EXIT_MSR_ST_ADDR, 5451 tmp - (exit_msr_st_cnt * 16 - 1)); 5452 test_vmx_invalid_controls(); 5453 } 5454 5455 vmcs_write(EXI_MSR_ST_CNT, 2); 5456 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 5457 test_vmx_invalid_controls(); 5458 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 5459 test_vmx_valid_controls(); 5460 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 5461 test_vmx_valid_controls(); 5462 } 5463 5464 /* 5465 * Tests for VM-exit controls 5466 */ 5467 static void test_vm_exit_ctls(void) 5468 { 5469 test_exit_msr_store(); 5470 } 5471 5472 /* 5473 * Check that the virtual CPU checks all of the VMX controls as 5474 * documented in the Intel SDM. 5475 */ 5476 static void vmx_controls_test(void) 5477 { 5478 /* 5479 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 5480 * fail due to invalid guest state, should we make it that 5481 * far. 5482 */ 5483 vmcs_write(GUEST_RFLAGS, 0); 5484 5485 test_vm_execution_ctls(); 5486 test_vm_exit_ctls(); 5487 test_vm_entry_ctls(); 5488 } 5489 5490 struct apic_reg_virt_config { 5491 bool apic_register_virtualization; 5492 bool use_tpr_shadow; 5493 bool virtualize_apic_accesses; 5494 bool virtualize_x2apic_mode; 5495 bool activate_secondary_controls; 5496 }; 5497 5498 struct apic_reg_test { 5499 const char *name; 5500 struct apic_reg_virt_config apic_reg_virt_config; 5501 }; 5502 5503 struct apic_reg_virt_expectation { 5504 enum Reason rd_exit_reason; 5505 enum Reason wr_exit_reason; 5506 u32 val; 5507 u32 (*virt_fn)(u32); 5508 5509 /* 5510 * If false, accessing the APIC access address from L2 is treated as a 5511 * normal memory operation, rather than triggering virtualization. 5512 */ 5513 bool virtualize_apic_accesses; 5514 }; 5515 5516 static u32 apic_virt_identity(u32 val) 5517 { 5518 return val; 5519 } 5520 5521 static u32 apic_virt_nibble1(u32 val) 5522 { 5523 return val & 0xf0; 5524 } 5525 5526 static u32 apic_virt_byte3(u32 val) 5527 { 5528 return val & (0xff << 24); 5529 } 5530 5531 static bool apic_reg_virt_exit_expectation( 5532 u32 reg, struct apic_reg_virt_config *config, 5533 struct apic_reg_virt_expectation *expectation) 5534 { 5535 /* Good configs, where some L2 APIC accesses are virtualized. */ 5536 bool virtualize_apic_accesses_only = 5537 config->virtualize_apic_accesses && 5538 !config->use_tpr_shadow && 5539 !config->apic_register_virtualization && 5540 !config->virtualize_x2apic_mode && 5541 config->activate_secondary_controls; 5542 bool virtualize_apic_accesses_and_use_tpr_shadow = 5543 config->virtualize_apic_accesses && 5544 config->use_tpr_shadow && 5545 !config->apic_register_virtualization && 5546 !config->virtualize_x2apic_mode && 5547 config->activate_secondary_controls; 5548 bool apic_register_virtualization = 5549 config->virtualize_apic_accesses && 5550 config->use_tpr_shadow && 5551 config->apic_register_virtualization && 5552 !config->virtualize_x2apic_mode && 5553 config->activate_secondary_controls; 5554 5555 expectation->val = MAGIC_VAL_1; 5556 expectation->virt_fn = apic_virt_identity; 5557 expectation->virtualize_apic_accesses = 5558 config->virtualize_apic_accesses && 5559 config->activate_secondary_controls; 5560 if (virtualize_apic_accesses_only) { 5561 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5562 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5563 } else if (virtualize_apic_accesses_and_use_tpr_shadow) { 5564 switch (reg) { 5565 case APIC_TASKPRI: 5566 expectation->rd_exit_reason = VMX_VMCALL; 5567 expectation->wr_exit_reason = VMX_VMCALL; 5568 expectation->virt_fn = apic_virt_nibble1; 5569 break; 5570 default: 5571 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5572 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5573 } 5574 } else if (apic_register_virtualization) { 5575 expectation->rd_exit_reason = VMX_VMCALL; 5576 5577 switch (reg) { 5578 case APIC_ID: 5579 case APIC_EOI: 5580 case APIC_LDR: 5581 case APIC_DFR: 5582 case APIC_SPIV: 5583 case APIC_ESR: 5584 case APIC_ICR: 5585 case APIC_LVTT: 5586 case APIC_LVTTHMR: 5587 case APIC_LVTPC: 5588 case APIC_LVT0: 5589 case APIC_LVT1: 5590 case APIC_LVTERR: 5591 case APIC_TMICT: 5592 case APIC_TDCR: 5593 expectation->wr_exit_reason = VMX_APIC_WRITE; 5594 break; 5595 case APIC_LVR: 5596 case APIC_ISR ... APIC_ISR + 0x70: 5597 case APIC_TMR ... APIC_TMR + 0x70: 5598 case APIC_IRR ... APIC_IRR + 0x70: 5599 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5600 break; 5601 case APIC_TASKPRI: 5602 expectation->wr_exit_reason = VMX_VMCALL; 5603 expectation->virt_fn = apic_virt_nibble1; 5604 break; 5605 case APIC_ICR2: 5606 expectation->wr_exit_reason = VMX_VMCALL; 5607 expectation->virt_fn = apic_virt_byte3; 5608 break; 5609 default: 5610 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5611 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5612 } 5613 } else if (!expectation->virtualize_apic_accesses) { 5614 /* 5615 * No APIC registers are directly virtualized. This includes 5616 * VTPR, which can be virtualized through MOV to/from CR8 via 5617 * the use TPR shadow control, but not through directly 5618 * accessing VTPR. 5619 */ 5620 expectation->rd_exit_reason = VMX_VMCALL; 5621 expectation->wr_exit_reason = VMX_VMCALL; 5622 } else { 5623 printf("Cannot parse APIC register virtualization config:\n" 5624 "\tvirtualize_apic_accesses: %d\n" 5625 "\tuse_tpr_shadow: %d\n" 5626 "\tapic_register_virtualization: %d\n" 5627 "\tvirtualize_x2apic_mode: %d\n" 5628 "\tactivate_secondary_controls: %d\n", 5629 config->virtualize_apic_accesses, 5630 config->use_tpr_shadow, 5631 config->apic_register_virtualization, 5632 config->virtualize_x2apic_mode, 5633 config->activate_secondary_controls); 5634 5635 return false; 5636 } 5637 5638 return true; 5639 } 5640 5641 struct apic_reg_test apic_reg_tests[] = { 5642 /* Good configs, where some L2 APIC accesses are virtualized. */ 5643 { 5644 .name = "Virtualize APIC accesses", 5645 .apic_reg_virt_config = { 5646 .virtualize_apic_accesses = true, 5647 .use_tpr_shadow = false, 5648 .apic_register_virtualization = false, 5649 .virtualize_x2apic_mode = false, 5650 .activate_secondary_controls = true, 5651 }, 5652 }, 5653 { 5654 .name = "Virtualize APIC accesses + Use TPR shadow", 5655 .apic_reg_virt_config = { 5656 .virtualize_apic_accesses = true, 5657 .use_tpr_shadow = true, 5658 .apic_register_virtualization = false, 5659 .virtualize_x2apic_mode = false, 5660 .activate_secondary_controls = true, 5661 }, 5662 }, 5663 { 5664 .name = "APIC-register virtualization", 5665 .apic_reg_virt_config = { 5666 .virtualize_apic_accesses = true, 5667 .use_tpr_shadow = true, 5668 .apic_register_virtualization = true, 5669 .virtualize_x2apic_mode = false, 5670 .activate_secondary_controls = true, 5671 }, 5672 }, 5673 5674 /* 5675 * Test that the secondary processor-based VM-execution controls are 5676 * correctly ignored when "activate secondary controls" is disabled. 5677 */ 5678 { 5679 .name = "Activate secondary controls off", 5680 .apic_reg_virt_config = { 5681 .virtualize_apic_accesses = true, 5682 .use_tpr_shadow = false, 5683 .apic_register_virtualization = true, 5684 .virtualize_x2apic_mode = true, 5685 .activate_secondary_controls = false, 5686 }, 5687 }, 5688 { 5689 .name = "Activate secondary controls off + Use TPR shadow", 5690 .apic_reg_virt_config = { 5691 .virtualize_apic_accesses = true, 5692 .use_tpr_shadow = true, 5693 .apic_register_virtualization = true, 5694 .virtualize_x2apic_mode = true, 5695 .activate_secondary_controls = false, 5696 }, 5697 }, 5698 5699 /* 5700 * Test that the APIC access address is treated like an arbitrary memory 5701 * address when "virtualize APIC accesses" is disabled. 5702 */ 5703 { 5704 .name = "Virtualize APIC accesses off + Use TPR shadow", 5705 .apic_reg_virt_config = { 5706 .virtualize_apic_accesses = false, 5707 .use_tpr_shadow = true, 5708 .apic_register_virtualization = true, 5709 .virtualize_x2apic_mode = true, 5710 .activate_secondary_controls = true, 5711 }, 5712 }, 5713 5714 /* 5715 * Test that VM entry fails due to invalid controls when 5716 * "APIC-register virtualization" is enabled while "use TPR shadow" is 5717 * disabled. 5718 */ 5719 { 5720 .name = "APIC-register virtualization + Use TPR shadow off", 5721 .apic_reg_virt_config = { 5722 .virtualize_apic_accesses = true, 5723 .use_tpr_shadow = false, 5724 .apic_register_virtualization = true, 5725 .virtualize_x2apic_mode = false, 5726 .activate_secondary_controls = true, 5727 }, 5728 }, 5729 5730 /* 5731 * Test that VM entry fails due to invalid controls when 5732 * "Virtualize x2APIC mode" is enabled while "use TPR shadow" is 5733 * disabled. 5734 */ 5735 { 5736 .name = "Virtualize x2APIC mode + Use TPR shadow off", 5737 .apic_reg_virt_config = { 5738 .virtualize_apic_accesses = false, 5739 .use_tpr_shadow = false, 5740 .apic_register_virtualization = false, 5741 .virtualize_x2apic_mode = true, 5742 .activate_secondary_controls = true, 5743 }, 5744 }, 5745 { 5746 .name = "Virtualize x2APIC mode + Use TPR shadow off v2", 5747 .apic_reg_virt_config = { 5748 .virtualize_apic_accesses = false, 5749 .use_tpr_shadow = false, 5750 .apic_register_virtualization = true, 5751 .virtualize_x2apic_mode = true, 5752 .activate_secondary_controls = true, 5753 }, 5754 }, 5755 5756 /* 5757 * Test that VM entry fails due to invalid controls when 5758 * "virtualize x2APIC mode" is enabled while "virtualize APIC accesses" 5759 * is enabled. 5760 */ 5761 { 5762 .name = "Virtualize x2APIC mode + Virtualize APIC accesses", 5763 .apic_reg_virt_config = { 5764 .virtualize_apic_accesses = true, 5765 .use_tpr_shadow = true, 5766 .apic_register_virtualization = false, 5767 .virtualize_x2apic_mode = true, 5768 .activate_secondary_controls = true, 5769 }, 5770 }, 5771 { 5772 .name = "Virtualize x2APIC mode + Virtualize APIC accesses v2", 5773 .apic_reg_virt_config = { 5774 .virtualize_apic_accesses = true, 5775 .use_tpr_shadow = true, 5776 .apic_register_virtualization = true, 5777 .virtualize_x2apic_mode = true, 5778 .activate_secondary_controls = true, 5779 }, 5780 }, 5781 }; 5782 5783 enum Apic_op { 5784 APIC_OP_XAPIC_RD, 5785 APIC_OP_XAPIC_WR, 5786 TERMINATE, 5787 }; 5788 5789 static u32 vmx_xapic_read(u32 *apic_access_address, u32 reg) 5790 { 5791 return *(volatile u32 *)((uintptr_t)apic_access_address + reg); 5792 } 5793 5794 static void vmx_xapic_write(u32 *apic_access_address, u32 reg, u32 val) 5795 { 5796 *(volatile u32 *)((uintptr_t)apic_access_address + reg) = val; 5797 } 5798 5799 struct apic_reg_virt_guest_args { 5800 enum Apic_op op; 5801 u32 *apic_access_address; 5802 u32 reg; 5803 u32 val; 5804 bool check_rd; 5805 u32 (*virt_fn)(u32); 5806 } apic_reg_virt_guest_args; 5807 5808 static void apic_reg_virt_guest(void) 5809 { 5810 volatile struct apic_reg_virt_guest_args *args = 5811 &apic_reg_virt_guest_args; 5812 5813 for (;;) { 5814 enum Apic_op op = args->op; 5815 u32 *apic_access_address = args->apic_access_address; 5816 u32 reg = args->reg; 5817 u32 val = args->val; 5818 bool check_rd = args->check_rd; 5819 u32 (*virt_fn)(u32) = args->virt_fn; 5820 5821 if (op == TERMINATE) 5822 break; 5823 5824 if (op == APIC_OP_XAPIC_RD) { 5825 u32 ret = vmx_xapic_read(apic_access_address, reg); 5826 5827 if (check_rd) { 5828 u32 want = virt_fn(val); 5829 u32 got = virt_fn(ret); 5830 5831 report(got == want, 5832 "read 0x%x, expected 0x%x.", got, want); 5833 } 5834 } else if (op == APIC_OP_XAPIC_WR) { 5835 vmx_xapic_write(apic_access_address, reg, val); 5836 } 5837 5838 /* 5839 * The L1 should always execute a vmcall after it's done testing 5840 * an individual APIC operation. This helps to validate that the 5841 * L1 and L2 are in sync with each other, as expected. 5842 */ 5843 vmcall(); 5844 } 5845 } 5846 5847 static void test_xapic_rd( 5848 u32 reg, struct apic_reg_virt_expectation *expectation, 5849 u32 *apic_access_address, u32 *virtual_apic_page) 5850 { 5851 u32 val = expectation->val; 5852 u32 exit_reason_want = expectation->rd_exit_reason; 5853 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 5854 5855 report_prefix_pushf("xapic - reading 0x%03x", reg); 5856 5857 /* Configure guest to do an xapic read */ 5858 args->op = APIC_OP_XAPIC_RD; 5859 args->apic_access_address = apic_access_address; 5860 args->reg = reg; 5861 args->val = val; 5862 args->check_rd = exit_reason_want == VMX_VMCALL; 5863 args->virt_fn = expectation->virt_fn; 5864 5865 /* Setup virtual APIC page */ 5866 if (!expectation->virtualize_apic_accesses) { 5867 apic_access_address[apic_reg_index(reg)] = val; 5868 virtual_apic_page[apic_reg_index(reg)] = 0; 5869 } else if (exit_reason_want == VMX_VMCALL) { 5870 apic_access_address[apic_reg_index(reg)] = 0; 5871 virtual_apic_page[apic_reg_index(reg)] = val; 5872 } 5873 5874 /* Enter guest */ 5875 enter_guest(); 5876 5877 /* 5878 * Validate the behavior and 5879 * pass a magic value back to the guest. 5880 */ 5881 if (exit_reason_want == VMX_APIC_ACCESS) { 5882 u32 apic_page_offset = vmcs_read(EXI_QUALIFICATION) & 0xfff; 5883 5884 assert_exit_reason(exit_reason_want); 5885 report(apic_page_offset == reg, 5886 "got APIC access exit @ page offset 0x%03x, want 0x%03x", 5887 apic_page_offset, reg); 5888 skip_exit_insn(); 5889 5890 /* Reenter guest so it can consume/check rcx and exit again. */ 5891 enter_guest(); 5892 } else if (exit_reason_want != VMX_VMCALL) { 5893 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 5894 } 5895 5896 skip_exit_vmcall(); 5897 report_prefix_pop(); 5898 } 5899 5900 static void test_xapic_wr( 5901 u32 reg, struct apic_reg_virt_expectation *expectation, 5902 u32 *apic_access_address, u32 *virtual_apic_page) 5903 { 5904 u32 val = expectation->val; 5905 u32 exit_reason_want = expectation->wr_exit_reason; 5906 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 5907 bool virtualized = 5908 expectation->virtualize_apic_accesses && 5909 (exit_reason_want == VMX_APIC_WRITE || 5910 exit_reason_want == VMX_VMCALL); 5911 bool checked = false; 5912 5913 report_prefix_pushf("xapic - writing 0x%x to 0x%03x", val, reg); 5914 5915 /* Configure guest to do an xapic read */ 5916 args->op = APIC_OP_XAPIC_WR; 5917 args->apic_access_address = apic_access_address; 5918 args->reg = reg; 5919 args->val = val; 5920 5921 /* Setup virtual APIC page */ 5922 if (virtualized || !expectation->virtualize_apic_accesses) { 5923 apic_access_address[apic_reg_index(reg)] = 0; 5924 virtual_apic_page[apic_reg_index(reg)] = 0; 5925 } 5926 5927 /* Enter guest */ 5928 enter_guest(); 5929 5930 /* 5931 * Validate the behavior and 5932 * pass a magic value back to the guest. 5933 */ 5934 if (exit_reason_want == VMX_APIC_ACCESS) { 5935 u32 apic_page_offset = vmcs_read(EXI_QUALIFICATION) & 0xfff; 5936 5937 assert_exit_reason(exit_reason_want); 5938 report(apic_page_offset == reg, 5939 "got APIC access exit @ page offset 0x%03x, want 0x%03x", 5940 apic_page_offset, reg); 5941 skip_exit_insn(); 5942 5943 /* Reenter guest so it can consume/check rcx and exit again. */ 5944 enter_guest(); 5945 } else if (exit_reason_want == VMX_APIC_WRITE) { 5946 assert_exit_reason(exit_reason_want); 5947 report(virtual_apic_page[apic_reg_index(reg)] == val, 5948 "got APIC write exit @ page offset 0x%03x; val is 0x%x, want 0x%x", 5949 apic_reg_index(reg), 5950 virtual_apic_page[apic_reg_index(reg)], val); 5951 checked = true; 5952 5953 /* Reenter guest so it can consume/check rcx and exit again. */ 5954 enter_guest(); 5955 } else if (exit_reason_want != VMX_VMCALL) { 5956 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 5957 } 5958 5959 assert_exit_reason(VMX_VMCALL); 5960 if (virtualized && !checked) { 5961 u32 want = expectation->virt_fn(val); 5962 u32 got = virtual_apic_page[apic_reg_index(reg)]; 5963 got = expectation->virt_fn(got); 5964 5965 report(got == want, "exitless write; val is 0x%x, want 0x%x", 5966 got, want); 5967 } else if (!expectation->virtualize_apic_accesses && !checked) { 5968 u32 got = apic_access_address[apic_reg_index(reg)]; 5969 5970 report(got == val, 5971 "non-virtualized write; val is 0x%x, want 0x%x", got, 5972 val); 5973 } else if (!expectation->virtualize_apic_accesses && checked) { 5974 report_fail("Non-virtualized write was prematurely checked!"); 5975 } 5976 5977 skip_exit_vmcall(); 5978 report_prefix_pop(); 5979 } 5980 5981 enum Config_type { 5982 CONFIG_TYPE_GOOD, 5983 CONFIG_TYPE_UNSUPPORTED, 5984 CONFIG_TYPE_VMENTRY_FAILS_EARLY, 5985 }; 5986 5987 static enum Config_type configure_apic_reg_virt_test( 5988 struct apic_reg_virt_config *apic_reg_virt_config) 5989 { 5990 u32 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 5991 u32 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 5992 /* Configs where L2 entry fails early, due to invalid controls. */ 5993 bool use_tpr_shadow_incorrectly_off = 5994 !apic_reg_virt_config->use_tpr_shadow && 5995 (apic_reg_virt_config->apic_register_virtualization || 5996 apic_reg_virt_config->virtualize_x2apic_mode) && 5997 apic_reg_virt_config->activate_secondary_controls; 5998 bool virtualize_apic_accesses_incorrectly_on = 5999 apic_reg_virt_config->virtualize_apic_accesses && 6000 apic_reg_virt_config->virtualize_x2apic_mode && 6001 apic_reg_virt_config->activate_secondary_controls; 6002 bool vmentry_fails_early = 6003 use_tpr_shadow_incorrectly_off || 6004 virtualize_apic_accesses_incorrectly_on; 6005 6006 if (apic_reg_virt_config->activate_secondary_controls) { 6007 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 6008 printf("VM-execution control \"activate secondary controls\" NOT supported.\n"); 6009 return CONFIG_TYPE_UNSUPPORTED; 6010 } 6011 cpu_exec_ctrl0 |= CPU_SECONDARY; 6012 } else { 6013 cpu_exec_ctrl0 &= ~CPU_SECONDARY; 6014 } 6015 6016 if (apic_reg_virt_config->virtualize_apic_accesses) { 6017 if (!(ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES)) { 6018 printf("VM-execution control \"virtualize APIC accesses\" NOT supported.\n"); 6019 return CONFIG_TYPE_UNSUPPORTED; 6020 } 6021 cpu_exec_ctrl1 |= CPU_VIRT_APIC_ACCESSES; 6022 } else { 6023 cpu_exec_ctrl1 &= ~CPU_VIRT_APIC_ACCESSES; 6024 } 6025 6026 if (apic_reg_virt_config->use_tpr_shadow) { 6027 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) { 6028 printf("VM-execution control \"use TPR shadow\" NOT supported.\n"); 6029 return CONFIG_TYPE_UNSUPPORTED; 6030 } 6031 cpu_exec_ctrl0 |= CPU_TPR_SHADOW; 6032 } else { 6033 cpu_exec_ctrl0 &= ~CPU_TPR_SHADOW; 6034 } 6035 6036 if (apic_reg_virt_config->apic_register_virtualization) { 6037 if (!(ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT)) { 6038 printf("VM-execution control \"APIC-register virtualization\" NOT supported.\n"); 6039 return CONFIG_TYPE_UNSUPPORTED; 6040 } 6041 cpu_exec_ctrl1 |= CPU_APIC_REG_VIRT; 6042 } else { 6043 cpu_exec_ctrl1 &= ~CPU_APIC_REG_VIRT; 6044 } 6045 6046 if (apic_reg_virt_config->virtualize_x2apic_mode) { 6047 if (!(ctrl_cpu_rev[1].clr & CPU_VIRT_X2APIC)) { 6048 printf("VM-execution control \"virtualize x2APIC mode\" NOT supported.\n"); 6049 return CONFIG_TYPE_UNSUPPORTED; 6050 } 6051 cpu_exec_ctrl1 |= CPU_VIRT_X2APIC; 6052 } else { 6053 cpu_exec_ctrl1 &= ~CPU_VIRT_X2APIC; 6054 } 6055 6056 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6057 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6058 6059 if (vmentry_fails_early) 6060 return CONFIG_TYPE_VMENTRY_FAILS_EARLY; 6061 6062 return CONFIG_TYPE_GOOD; 6063 } 6064 6065 static bool cpu_has_apicv(void) 6066 { 6067 return ((ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT) && 6068 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 6069 (ctrl_pin_rev.clr & PIN_POST_INTR)); 6070 } 6071 6072 /* Validates APIC register access across valid virtualization configurations. */ 6073 static void apic_reg_virt_test(void) 6074 { 6075 u32 *apic_access_address; 6076 u32 *virtual_apic_page; 6077 u64 control; 6078 u64 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6079 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6080 int i; 6081 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 6082 6083 if (!cpu_has_apicv()) { 6084 report_skip("%s : Not all required APICv bits supported", __func__); 6085 return; 6086 } 6087 6088 control = cpu_exec_ctrl1; 6089 control &= ~CPU_VINTD; 6090 vmcs_write(CPU_EXEC_CTRL1, control); 6091 6092 test_set_guest(apic_reg_virt_guest); 6093 6094 /* 6095 * From the SDM: The 1-setting of the "virtualize APIC accesses" 6096 * VM-execution is guaranteed to apply only if translations to the 6097 * APIC-access address use a 4-KByte page. 6098 */ 6099 apic_access_address = alloc_page(); 6100 force_4k_page(apic_access_address); 6101 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_address)); 6102 6103 virtual_apic_page = alloc_page(); 6104 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 6105 6106 for (i = 0; i < ARRAY_SIZE(apic_reg_tests); i++) { 6107 struct apic_reg_test *apic_reg_test = &apic_reg_tests[i]; 6108 struct apic_reg_virt_config *apic_reg_virt_config = 6109 &apic_reg_test->apic_reg_virt_config; 6110 enum Config_type config_type; 6111 u32 reg; 6112 6113 printf("--- %s test ---\n", apic_reg_test->name); 6114 config_type = 6115 configure_apic_reg_virt_test(apic_reg_virt_config); 6116 if (config_type == CONFIG_TYPE_UNSUPPORTED) { 6117 printf("Skip because of missing features.\n"); 6118 continue; 6119 } 6120 6121 if (config_type == CONFIG_TYPE_VMENTRY_FAILS_EARLY) { 6122 enter_guest_with_bad_controls(); 6123 continue; 6124 } 6125 6126 for (reg = 0; reg < PAGE_SIZE / sizeof(u32); reg += 0x10) { 6127 struct apic_reg_virt_expectation expectation = {}; 6128 bool ok; 6129 6130 ok = apic_reg_virt_exit_expectation( 6131 reg, apic_reg_virt_config, &expectation); 6132 if (!ok) { 6133 report_fail("Malformed test."); 6134 break; 6135 } 6136 6137 test_xapic_rd(reg, &expectation, apic_access_address, 6138 virtual_apic_page); 6139 test_xapic_wr(reg, &expectation, apic_access_address, 6140 virtual_apic_page); 6141 } 6142 } 6143 6144 /* Terminate the guest */ 6145 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6146 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6147 args->op = TERMINATE; 6148 enter_guest(); 6149 assert_exit_reason(VMX_VMCALL); 6150 } 6151 6152 struct virt_x2apic_mode_config { 6153 struct apic_reg_virt_config apic_reg_virt_config; 6154 bool virtual_interrupt_delivery; 6155 bool use_msr_bitmaps; 6156 bool disable_x2apic_msr_intercepts; 6157 bool disable_x2apic; 6158 }; 6159 6160 struct virt_x2apic_mode_test_case { 6161 const char *name; 6162 struct virt_x2apic_mode_config virt_x2apic_mode_config; 6163 }; 6164 6165 enum Virt_x2apic_mode_behavior_type { 6166 X2APIC_ACCESS_VIRTUALIZED, 6167 X2APIC_ACCESS_PASSED_THROUGH, 6168 X2APIC_ACCESS_TRIGGERS_GP, 6169 }; 6170 6171 struct virt_x2apic_mode_expectation { 6172 enum Reason rd_exit_reason; 6173 enum Reason wr_exit_reason; 6174 6175 /* 6176 * RDMSR and WRMSR handle 64-bit values. However, except for ICR, all of 6177 * the x2APIC registers are 32 bits. Notice: 6178 * 1. vmx_x2apic_read() clears the upper 32 bits for 32-bit registers. 6179 * 2. vmx_x2apic_write() expects the val arg to be well-formed. 6180 */ 6181 u64 rd_val; 6182 u64 wr_val; 6183 6184 /* 6185 * Compares input to virtualized output; 6186 * 1st arg is pointer to return expected virtualization output. 6187 */ 6188 u64 (*virt_fn)(u64); 6189 6190 enum Virt_x2apic_mode_behavior_type rd_behavior; 6191 enum Virt_x2apic_mode_behavior_type wr_behavior; 6192 bool wr_only; 6193 }; 6194 6195 static u64 virt_x2apic_mode_identity(u64 val) 6196 { 6197 return val; 6198 } 6199 6200 static u64 virt_x2apic_mode_nibble1(u64 val) 6201 { 6202 return val & 0xf0; 6203 } 6204 6205 static void virt_x2apic_mode_rd_expectation( 6206 u32 reg, bool virt_x2apic_mode_on, bool disable_x2apic, 6207 bool apic_register_virtualization, bool virtual_interrupt_delivery, 6208 struct virt_x2apic_mode_expectation *expectation) 6209 { 6210 enum x2apic_reg_semantics semantics = get_x2apic_reg_semantics(reg); 6211 6212 expectation->rd_exit_reason = VMX_VMCALL; 6213 expectation->virt_fn = virt_x2apic_mode_identity; 6214 if (virt_x2apic_mode_on && apic_register_virtualization) { 6215 expectation->rd_val = MAGIC_VAL_1; 6216 if (reg == APIC_PROCPRI && virtual_interrupt_delivery) 6217 expectation->virt_fn = virt_x2apic_mode_nibble1; 6218 else if (reg == APIC_TASKPRI) 6219 expectation->virt_fn = virt_x2apic_mode_nibble1; 6220 expectation->rd_behavior = X2APIC_ACCESS_VIRTUALIZED; 6221 } else if (virt_x2apic_mode_on && !apic_register_virtualization && 6222 reg == APIC_TASKPRI) { 6223 expectation->rd_val = MAGIC_VAL_1; 6224 expectation->virt_fn = virt_x2apic_mode_nibble1; 6225 expectation->rd_behavior = X2APIC_ACCESS_VIRTUALIZED; 6226 } else if (!disable_x2apic && (semantics & X2APIC_READABLE)) { 6227 expectation->rd_val = apic_read(reg); 6228 expectation->rd_behavior = X2APIC_ACCESS_PASSED_THROUGH; 6229 } else { 6230 expectation->rd_behavior = X2APIC_ACCESS_TRIGGERS_GP; 6231 } 6232 } 6233 6234 /* 6235 * get_x2apic_wr_val() creates an innocuous write value for an x2APIC register. 6236 * 6237 * For writable registers, get_x2apic_wr_val() deposits the write value into the 6238 * val pointer arg and returns true. For non-writable registers, val is not 6239 * modified and get_x2apic_wr_val() returns false. 6240 */ 6241 static bool get_x2apic_wr_val(u32 reg, u64 *val) 6242 { 6243 switch (reg) { 6244 case APIC_TASKPRI: 6245 /* Bits 31:8 are reserved. */ 6246 *val &= 0xff; 6247 break; 6248 case APIC_EOI: 6249 case APIC_ESR: 6250 case APIC_TMICT: 6251 /* 6252 * EOI, ESR: WRMSR of a non-zero value causes #GP(0). 6253 * TMICT: A write of 0 to the initial-count register effectively 6254 * stops the local APIC timer, in both one-shot and 6255 * periodic mode. 6256 */ 6257 *val = 0; 6258 break; 6259 case APIC_SPIV: 6260 case APIC_LVTT: 6261 case APIC_LVTTHMR: 6262 case APIC_LVTPC: 6263 case APIC_LVT0: 6264 case APIC_LVT1: 6265 case APIC_LVTERR: 6266 case APIC_TDCR: 6267 /* 6268 * To avoid writing a 1 to a reserved bit or causing some other 6269 * unintended side effect, read the current value and use it as 6270 * the write value. 6271 */ 6272 *val = apic_read(reg); 6273 break; 6274 case APIC_CMCI: 6275 if (!apic_lvt_entry_supported(6)) 6276 return false; 6277 *val = apic_read(reg); 6278 break; 6279 case APIC_ICR: 6280 *val = 0x40000 | 0xf1; 6281 break; 6282 case APIC_SELF_IPI: 6283 /* 6284 * With special processing (i.e., virtualize x2APIC mode + 6285 * virtual interrupt delivery), writing zero causes an 6286 * APIC-write VM exit. We plan to add a test for enabling 6287 * "virtual-interrupt delivery" in VMCS12, and that's where we 6288 * will test a self IPI with special processing. 6289 */ 6290 *val = 0x0; 6291 break; 6292 default: 6293 return false; 6294 } 6295 6296 return true; 6297 } 6298 6299 static bool special_processing_applies(u32 reg, u64 *val, 6300 bool virt_int_delivery) 6301 { 6302 bool special_processing = 6303 (reg == APIC_TASKPRI) || 6304 (virt_int_delivery && 6305 (reg == APIC_EOI || reg == APIC_SELF_IPI)); 6306 6307 if (special_processing) { 6308 TEST_ASSERT(get_x2apic_wr_val(reg, val)); 6309 return true; 6310 } 6311 6312 return false; 6313 } 6314 6315 static void virt_x2apic_mode_wr_expectation( 6316 u32 reg, bool virt_x2apic_mode_on, bool disable_x2apic, 6317 bool virt_int_delivery, 6318 struct virt_x2apic_mode_expectation *expectation) 6319 { 6320 expectation->wr_exit_reason = VMX_VMCALL; 6321 expectation->wr_val = MAGIC_VAL_1; 6322 expectation->wr_only = false; 6323 6324 if (virt_x2apic_mode_on && 6325 special_processing_applies(reg, &expectation->wr_val, 6326 virt_int_delivery)) { 6327 expectation->wr_behavior = X2APIC_ACCESS_VIRTUALIZED; 6328 if (reg == APIC_SELF_IPI) 6329 expectation->wr_exit_reason = VMX_APIC_WRITE; 6330 } else if (!disable_x2apic && 6331 get_x2apic_wr_val(reg, &expectation->wr_val)) { 6332 expectation->wr_behavior = X2APIC_ACCESS_PASSED_THROUGH; 6333 if (reg == APIC_EOI || reg == APIC_SELF_IPI) 6334 expectation->wr_only = true; 6335 if (reg == APIC_ICR) 6336 expectation->wr_exit_reason = VMX_EXTINT; 6337 } else { 6338 expectation->wr_behavior = X2APIC_ACCESS_TRIGGERS_GP; 6339 /* 6340 * Writing 1 to a reserved bit triggers a #GP. 6341 * Thus, set the write value to 0, which seems 6342 * the most likely to detect a missed #GP. 6343 */ 6344 expectation->wr_val = 0; 6345 } 6346 } 6347 6348 static void virt_x2apic_mode_exit_expectation( 6349 u32 reg, struct virt_x2apic_mode_config *config, 6350 struct virt_x2apic_mode_expectation *expectation) 6351 { 6352 struct apic_reg_virt_config *base_config = 6353 &config->apic_reg_virt_config; 6354 bool virt_x2apic_mode_on = 6355 base_config->virtualize_x2apic_mode && 6356 config->use_msr_bitmaps && 6357 config->disable_x2apic_msr_intercepts && 6358 base_config->activate_secondary_controls; 6359 6360 virt_x2apic_mode_wr_expectation( 6361 reg, virt_x2apic_mode_on, config->disable_x2apic, 6362 config->virtual_interrupt_delivery, expectation); 6363 virt_x2apic_mode_rd_expectation( 6364 reg, virt_x2apic_mode_on, config->disable_x2apic, 6365 base_config->apic_register_virtualization, 6366 config->virtual_interrupt_delivery, expectation); 6367 } 6368 6369 struct virt_x2apic_mode_test_case virt_x2apic_mode_tests[] = { 6370 /* 6371 * Baseline "virtualize x2APIC mode" configuration: 6372 * - virtualize x2APIC mode 6373 * - virtual-interrupt delivery 6374 * - APIC-register virtualization 6375 * - x2APIC MSR intercepts disabled 6376 * 6377 * Reads come from virtual APIC page, special processing applies to 6378 * VTPR, EOI, and SELF IPI, and all other writes pass through to L1 6379 * APIC. 6380 */ 6381 { 6382 .name = "Baseline", 6383 .virt_x2apic_mode_config = { 6384 .virtual_interrupt_delivery = true, 6385 .use_msr_bitmaps = true, 6386 .disable_x2apic_msr_intercepts = true, 6387 .disable_x2apic = false, 6388 .apic_reg_virt_config = { 6389 .apic_register_virtualization = true, 6390 .use_tpr_shadow = true, 6391 .virtualize_apic_accesses = false, 6392 .virtualize_x2apic_mode = true, 6393 .activate_secondary_controls = true, 6394 }, 6395 }, 6396 }, 6397 { 6398 .name = "Baseline w/ x2apic disabled", 6399 .virt_x2apic_mode_config = { 6400 .virtual_interrupt_delivery = true, 6401 .use_msr_bitmaps = true, 6402 .disable_x2apic_msr_intercepts = true, 6403 .disable_x2apic = true, 6404 .apic_reg_virt_config = { 6405 .apic_register_virtualization = true, 6406 .use_tpr_shadow = true, 6407 .virtualize_apic_accesses = false, 6408 .virtualize_x2apic_mode = true, 6409 .activate_secondary_controls = true, 6410 }, 6411 }, 6412 }, 6413 6414 /* 6415 * Baseline, minus virtual-interrupt delivery. Reads come from virtual 6416 * APIC page, special processing applies to VTPR, and all other writes 6417 * pass through to L1 APIC. 6418 */ 6419 { 6420 .name = "Baseline - virtual interrupt delivery", 6421 .virt_x2apic_mode_config = { 6422 .virtual_interrupt_delivery = false, 6423 .use_msr_bitmaps = true, 6424 .disable_x2apic_msr_intercepts = true, 6425 .disable_x2apic = false, 6426 .apic_reg_virt_config = { 6427 .apic_register_virtualization = true, 6428 .use_tpr_shadow = true, 6429 .virtualize_apic_accesses = false, 6430 .virtualize_x2apic_mode = true, 6431 .activate_secondary_controls = true, 6432 }, 6433 }, 6434 }, 6435 6436 /* 6437 * Baseline, minus APIC-register virtualization. x2APIC reads pass 6438 * through to L1's APIC, unless reading VTPR 6439 */ 6440 { 6441 .name = "Virtualize x2APIC mode, no APIC reg virt", 6442 .virt_x2apic_mode_config = { 6443 .virtual_interrupt_delivery = true, 6444 .use_msr_bitmaps = true, 6445 .disable_x2apic_msr_intercepts = true, 6446 .disable_x2apic = false, 6447 .apic_reg_virt_config = { 6448 .apic_register_virtualization = false, 6449 .use_tpr_shadow = true, 6450 .virtualize_apic_accesses = false, 6451 .virtualize_x2apic_mode = true, 6452 .activate_secondary_controls = true, 6453 }, 6454 }, 6455 }, 6456 { 6457 .name = "Virtualize x2APIC mode, no APIC reg virt, x2APIC off", 6458 .virt_x2apic_mode_config = { 6459 .virtual_interrupt_delivery = true, 6460 .use_msr_bitmaps = true, 6461 .disable_x2apic_msr_intercepts = true, 6462 .disable_x2apic = true, 6463 .apic_reg_virt_config = { 6464 .apic_register_virtualization = false, 6465 .use_tpr_shadow = true, 6466 .virtualize_apic_accesses = false, 6467 .virtualize_x2apic_mode = true, 6468 .activate_secondary_controls = true, 6469 }, 6470 }, 6471 }, 6472 6473 /* 6474 * Enable "virtualize x2APIC mode" and "APIC-register virtualization", 6475 * and disable intercepts for the x2APIC MSRs, but fail to enable 6476 * "activate secondary controls" (i.e. L2 gets access to L1's x2APIC 6477 * MSRs). 6478 */ 6479 { 6480 .name = "Fail to enable activate secondary controls", 6481 .virt_x2apic_mode_config = { 6482 .virtual_interrupt_delivery = true, 6483 .use_msr_bitmaps = true, 6484 .disable_x2apic_msr_intercepts = true, 6485 .disable_x2apic = false, 6486 .apic_reg_virt_config = { 6487 .apic_register_virtualization = true, 6488 .use_tpr_shadow = true, 6489 .virtualize_apic_accesses = false, 6490 .virtualize_x2apic_mode = true, 6491 .activate_secondary_controls = false, 6492 }, 6493 }, 6494 }, 6495 6496 /* 6497 * Enable "APIC-register virtualization" and enable "activate secondary 6498 * controls" and disable intercepts for the x2APIC MSRs, but do not 6499 * enable the "virtualize x2APIC mode" VM-execution control (i.e. L2 6500 * gets access to L1's x2APIC MSRs). 6501 */ 6502 { 6503 .name = "Fail to enable virtualize x2APIC mode", 6504 .virt_x2apic_mode_config = { 6505 .virtual_interrupt_delivery = true, 6506 .use_msr_bitmaps = true, 6507 .disable_x2apic_msr_intercepts = true, 6508 .disable_x2apic = false, 6509 .apic_reg_virt_config = { 6510 .apic_register_virtualization = true, 6511 .use_tpr_shadow = true, 6512 .virtualize_apic_accesses = false, 6513 .virtualize_x2apic_mode = false, 6514 .activate_secondary_controls = true, 6515 }, 6516 }, 6517 }, 6518 6519 /* 6520 * Disable "Virtualize x2APIC mode", disable x2APIC MSR intercepts, and 6521 * enable "APIC-register virtualization" --> L2 gets L1's x2APIC MSRs. 6522 */ 6523 { 6524 .name = "Baseline", 6525 .virt_x2apic_mode_config = { 6526 .virtual_interrupt_delivery = true, 6527 .use_msr_bitmaps = true, 6528 .disable_x2apic_msr_intercepts = true, 6529 .disable_x2apic = false, 6530 .apic_reg_virt_config = { 6531 .apic_register_virtualization = true, 6532 .use_tpr_shadow = true, 6533 .virtualize_apic_accesses = false, 6534 .virtualize_x2apic_mode = false, 6535 .activate_secondary_controls = true, 6536 }, 6537 }, 6538 }, 6539 }; 6540 6541 enum X2apic_op { 6542 X2APIC_OP_RD, 6543 X2APIC_OP_WR, 6544 X2APIC_TERMINATE, 6545 }; 6546 6547 static u64 vmx_x2apic_read(u32 reg) 6548 { 6549 u32 msr_addr = x2apic_msr(reg); 6550 u64 val; 6551 6552 val = rdmsr(msr_addr); 6553 6554 return val; 6555 } 6556 6557 static void vmx_x2apic_write(u32 reg, u64 val) 6558 { 6559 u32 msr_addr = x2apic_msr(reg); 6560 6561 wrmsr(msr_addr, val); 6562 } 6563 6564 struct virt_x2apic_mode_guest_args { 6565 enum X2apic_op op; 6566 u32 reg; 6567 u64 val; 6568 bool should_gp; 6569 u64 (*virt_fn)(u64); 6570 } virt_x2apic_mode_guest_args; 6571 6572 static volatile bool handle_x2apic_gp_ran; 6573 static volatile u32 handle_x2apic_gp_insn_len; 6574 static void handle_x2apic_gp(struct ex_regs *regs) 6575 { 6576 handle_x2apic_gp_ran = true; 6577 regs->rip += handle_x2apic_gp_insn_len; 6578 } 6579 6580 static handler setup_x2apic_gp_handler(void) 6581 { 6582 handler old_handler; 6583 6584 old_handler = handle_exception(GP_VECTOR, handle_x2apic_gp); 6585 /* RDMSR and WRMSR are both 2 bytes, assuming no prefixes. */ 6586 handle_x2apic_gp_insn_len = 2; 6587 6588 return old_handler; 6589 } 6590 6591 static void teardown_x2apic_gp_handler(handler old_handler) 6592 { 6593 handle_exception(GP_VECTOR, old_handler); 6594 6595 /* 6596 * Defensively reset instruction length, so that if the handler is 6597 * incorrectly used, it will loop infinitely, rather than run off into 6598 * la la land. 6599 */ 6600 handle_x2apic_gp_insn_len = 0; 6601 handle_x2apic_gp_ran = false; 6602 } 6603 6604 static void virt_x2apic_mode_guest(void) 6605 { 6606 volatile struct virt_x2apic_mode_guest_args *args = 6607 &virt_x2apic_mode_guest_args; 6608 6609 for (;;) { 6610 enum X2apic_op op = args->op; 6611 u32 reg = args->reg; 6612 u64 val = args->val; 6613 bool should_gp = args->should_gp; 6614 u64 (*virt_fn)(u64) = args->virt_fn; 6615 handler old_handler; 6616 6617 if (op == X2APIC_TERMINATE) 6618 break; 6619 6620 if (should_gp) { 6621 TEST_ASSERT(!handle_x2apic_gp_ran); 6622 old_handler = setup_x2apic_gp_handler(); 6623 } 6624 6625 if (op == X2APIC_OP_RD) { 6626 u64 ret = vmx_x2apic_read(reg); 6627 6628 if (!should_gp) { 6629 u64 want = virt_fn(val); 6630 u64 got = virt_fn(ret); 6631 6632 report(got == want, 6633 "APIC read; got 0x%lx, want 0x%lx.", 6634 got, want); 6635 } 6636 } else if (op == X2APIC_OP_WR) { 6637 vmx_x2apic_write(reg, val); 6638 } 6639 6640 if (should_gp) { 6641 report(handle_x2apic_gp_ran, 6642 "x2APIC op triggered GP."); 6643 teardown_x2apic_gp_handler(old_handler); 6644 } 6645 6646 /* 6647 * The L1 should always execute a vmcall after it's done testing 6648 * an individual APIC operation. This helps to validate that the 6649 * L1 and L2 are in sync with each other, as expected. 6650 */ 6651 vmcall(); 6652 } 6653 } 6654 6655 static void test_x2apic_rd( 6656 u32 reg, struct virt_x2apic_mode_expectation *expectation, 6657 u32 *virtual_apic_page) 6658 { 6659 u64 val = expectation->rd_val; 6660 u32 exit_reason_want = expectation->rd_exit_reason; 6661 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6662 6663 report_prefix_pushf("x2apic - reading 0x%03x", reg); 6664 6665 /* Configure guest to do an x2apic read */ 6666 args->op = X2APIC_OP_RD; 6667 args->reg = reg; 6668 args->val = val; 6669 args->should_gp = expectation->rd_behavior == X2APIC_ACCESS_TRIGGERS_GP; 6670 args->virt_fn = expectation->virt_fn; 6671 6672 /* Setup virtual APIC page */ 6673 if (expectation->rd_behavior == X2APIC_ACCESS_VIRTUALIZED) 6674 virtual_apic_page[apic_reg_index(reg)] = (u32)val; 6675 6676 /* Enter guest */ 6677 enter_guest(); 6678 6679 if (exit_reason_want != VMX_VMCALL) { 6680 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 6681 } 6682 6683 skip_exit_vmcall(); 6684 report_prefix_pop(); 6685 } 6686 6687 static volatile bool handle_x2apic_ipi_ran; 6688 static void handle_x2apic_ipi(isr_regs_t *regs) 6689 { 6690 handle_x2apic_ipi_ran = true; 6691 eoi(); 6692 } 6693 6694 static void test_x2apic_wr( 6695 u32 reg, struct virt_x2apic_mode_expectation *expectation, 6696 u32 *virtual_apic_page) 6697 { 6698 u64 val = expectation->wr_val; 6699 u32 exit_reason_want = expectation->wr_exit_reason; 6700 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6701 int ipi_vector = 0xf1; 6702 u32 restore_val = 0; 6703 6704 report_prefix_pushf("x2apic - writing 0x%lx to 0x%03x", val, reg); 6705 6706 /* Configure guest to do an x2apic read */ 6707 args->op = X2APIC_OP_WR; 6708 args->reg = reg; 6709 args->val = val; 6710 args->should_gp = expectation->wr_behavior == X2APIC_ACCESS_TRIGGERS_GP; 6711 6712 /* Setup virtual APIC page */ 6713 if (expectation->wr_behavior == X2APIC_ACCESS_VIRTUALIZED) 6714 virtual_apic_page[apic_reg_index(reg)] = 0; 6715 if (expectation->wr_behavior == X2APIC_ACCESS_PASSED_THROUGH && !expectation->wr_only) 6716 restore_val = apic_read(reg); 6717 6718 /* Setup IPI handler */ 6719 handle_x2apic_ipi_ran = false; 6720 handle_irq(ipi_vector, handle_x2apic_ipi); 6721 6722 /* Enter guest */ 6723 enter_guest(); 6724 6725 /* 6726 * Validate the behavior and 6727 * pass a magic value back to the guest. 6728 */ 6729 if (exit_reason_want == VMX_EXTINT) { 6730 assert_exit_reason(exit_reason_want); 6731 6732 /* Clear the external interrupt. */ 6733 sti_nop_cli(); 6734 report(handle_x2apic_ipi_ran, 6735 "Got pending interrupt after IRQ enabled."); 6736 6737 enter_guest(); 6738 } else if (exit_reason_want == VMX_APIC_WRITE) { 6739 assert_exit_reason(exit_reason_want); 6740 report(virtual_apic_page[apic_reg_index(reg)] == val, 6741 "got APIC write exit @ page offset 0x%03x; val is 0x%x, want 0x%lx", 6742 apic_reg_index(reg), 6743 virtual_apic_page[apic_reg_index(reg)], val); 6744 6745 /* Reenter guest so it can consume/check rcx and exit again. */ 6746 enter_guest(); 6747 } else if (exit_reason_want != VMX_VMCALL) { 6748 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 6749 } 6750 6751 assert_exit_reason(VMX_VMCALL); 6752 if (expectation->wr_behavior == X2APIC_ACCESS_VIRTUALIZED) { 6753 u64 want = val; 6754 u32 got = virtual_apic_page[apic_reg_index(reg)]; 6755 6756 report(got == want, "x2APIC write; got 0x%x, want 0x%lx", got, 6757 want); 6758 } else if (expectation->wr_behavior == X2APIC_ACCESS_PASSED_THROUGH) { 6759 if (!expectation->wr_only) { 6760 u32 got = apic_read(reg); 6761 bool ok; 6762 6763 /* 6764 * When L1's TPR is passed through to L2, the lower 6765 * nibble can be lost. For example, if L2 executes 6766 * WRMSR(0x808, 0x78), then, L1 might read 0x70. 6767 * 6768 * Here's how the lower nibble can get lost: 6769 * 1. L2 executes WRMSR(0x808, 0x78). 6770 * 2. L2 exits to L0 with a WRMSR exit. 6771 * 3. L0 emulates WRMSR, by writing L1's TPR. 6772 * 4. L0 re-enters L2. 6773 * 5. L2 exits to L0 (reason doesn't matter). 6774 * 6. L0 reflects L2's exit to L1. 6775 * 7. Before entering L1, L0 exits to user-space 6776 * (e.g., to satisfy TPR access reporting). 6777 * 8. User-space executes KVM_SET_REGS ioctl, which 6778 * clears the lower nibble of L1's TPR. 6779 */ 6780 if (reg == APIC_TASKPRI) { 6781 got = apic_virt_nibble1(got); 6782 val = apic_virt_nibble1(val); 6783 } 6784 6785 ok = got == val; 6786 report(ok, 6787 "non-virtualized write; val is 0x%x, want 0x%lx", 6788 got, val); 6789 apic_write(reg, restore_val); 6790 } else { 6791 report_pass("non-virtualized and write-only OK"); 6792 } 6793 } 6794 skip_exit_insn(); 6795 6796 report_prefix_pop(); 6797 } 6798 6799 static enum Config_type configure_virt_x2apic_mode_test( 6800 struct virt_x2apic_mode_config *virt_x2apic_mode_config, 6801 u8 *msr_bitmap_page) 6802 { 6803 int msr; 6804 u32 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6805 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6806 6807 /* x2apic-specific VMCS config */ 6808 if (virt_x2apic_mode_config->use_msr_bitmaps) { 6809 /* virt_x2apic_mode_test() checks for MSR bitmaps support */ 6810 cpu_exec_ctrl0 |= CPU_MSR_BITMAP; 6811 } else { 6812 cpu_exec_ctrl0 &= ~CPU_MSR_BITMAP; 6813 } 6814 6815 if (virt_x2apic_mode_config->virtual_interrupt_delivery) { 6816 if (!(ctrl_cpu_rev[1].clr & CPU_VINTD)) { 6817 report_skip("%s : \"virtual-interrupt delivery\" exec control not supported", __func__); 6818 return CONFIG_TYPE_UNSUPPORTED; 6819 } 6820 cpu_exec_ctrl1 |= CPU_VINTD; 6821 } else { 6822 cpu_exec_ctrl1 &= ~CPU_VINTD; 6823 } 6824 6825 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6826 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6827 6828 /* x2APIC MSR intercepts are usually off for "Virtualize x2APIC mode" */ 6829 for (msr = 0x800; msr <= 0x8ff; msr++) { 6830 if (virt_x2apic_mode_config->disable_x2apic_msr_intercepts) { 6831 clear_bit(msr, msr_bitmap_page + 0x000); 6832 clear_bit(msr, msr_bitmap_page + 0x800); 6833 } else { 6834 set_bit(msr, msr_bitmap_page + 0x000); 6835 set_bit(msr, msr_bitmap_page + 0x800); 6836 } 6837 } 6838 6839 /* x2APIC mode can impact virtualization */ 6840 reset_apic(); 6841 if (!virt_x2apic_mode_config->disable_x2apic) 6842 enable_x2apic(); 6843 6844 return configure_apic_reg_virt_test( 6845 &virt_x2apic_mode_config->apic_reg_virt_config); 6846 } 6847 6848 static void virt_x2apic_mode_test(void) 6849 { 6850 u32 *virtual_apic_page; 6851 u8 *msr_bitmap_page; 6852 u64 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6853 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6854 int i; 6855 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6856 6857 if (!cpu_has_apicv()) { 6858 report_skip("%s : Not all required APICv bits supported", __func__); 6859 return; 6860 } 6861 6862 /* 6863 * This is to exercise an issue in KVM's logic to merge L0's and L1's 6864 * MSR bitmaps. Previously, an L1 could get at L0's x2APIC MSRs by 6865 * writing the IA32_SPEC_CTRL MSR or the IA32_PRED_CMD MSRs. KVM would 6866 * then proceed to manipulate the MSR bitmaps, as if VMCS12 had the 6867 * "Virtualize x2APIC mod" control set, even when it didn't. 6868 */ 6869 if (this_cpu_has(X86_FEATURE_SPEC_CTRL)) 6870 wrmsr(MSR_IA32_SPEC_CTRL, 1); 6871 6872 /* 6873 * Check that VMCS12 supports: 6874 * - "Virtual-APIC address", indicated by "use TPR shadow" 6875 * - "MSR-bitmap address", indicated by "use MSR bitmaps" 6876 */ 6877 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) { 6878 report_skip("%s : \"Use TPR shadow\" exec control not supported", __func__); 6879 return; 6880 } else if (!(ctrl_cpu_rev[0].clr & CPU_MSR_BITMAP)) { 6881 report_skip("%s : \"Use MSR bitmaps\" exec control not supported", __func__); 6882 return; 6883 } 6884 6885 test_set_guest(virt_x2apic_mode_guest); 6886 6887 virtual_apic_page = alloc_page(); 6888 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 6889 6890 msr_bitmap_page = alloc_page(); 6891 memset(msr_bitmap_page, 0xff, PAGE_SIZE); 6892 vmcs_write(MSR_BITMAP, virt_to_phys(msr_bitmap_page)); 6893 6894 for (i = 0; i < ARRAY_SIZE(virt_x2apic_mode_tests); i++) { 6895 struct virt_x2apic_mode_test_case *virt_x2apic_mode_test_case = 6896 &virt_x2apic_mode_tests[i]; 6897 struct virt_x2apic_mode_config *virt_x2apic_mode_config = 6898 &virt_x2apic_mode_test_case->virt_x2apic_mode_config; 6899 enum Config_type config_type; 6900 u32 reg; 6901 6902 printf("--- %s test ---\n", virt_x2apic_mode_test_case->name); 6903 config_type = 6904 configure_virt_x2apic_mode_test(virt_x2apic_mode_config, 6905 msr_bitmap_page); 6906 if (config_type == CONFIG_TYPE_UNSUPPORTED) { 6907 report_skip("Skip because of missing features."); 6908 continue; 6909 } else if (config_type == CONFIG_TYPE_VMENTRY_FAILS_EARLY) { 6910 enter_guest_with_bad_controls(); 6911 continue; 6912 } 6913 6914 for (reg = 0; reg < PAGE_SIZE / sizeof(u32); reg += 0x10) { 6915 struct virt_x2apic_mode_expectation expectation; 6916 6917 virt_x2apic_mode_exit_expectation( 6918 reg, virt_x2apic_mode_config, &expectation); 6919 6920 test_x2apic_rd(reg, &expectation, virtual_apic_page); 6921 test_x2apic_wr(reg, &expectation, virtual_apic_page); 6922 } 6923 } 6924 6925 6926 /* Terminate the guest */ 6927 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6928 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6929 args->op = X2APIC_TERMINATE; 6930 enter_guest(); 6931 assert_exit_reason(VMX_VMCALL); 6932 } 6933 6934 static void test_ctl_reg(const char *cr_name, u64 cr, u64 fixed0, u64 fixed1) 6935 { 6936 u64 val; 6937 u64 cr_saved = vmcs_read(cr); 6938 int i; 6939 6940 val = fixed0 & fixed1; 6941 if (cr == HOST_CR4) 6942 vmcs_write(cr, val | X86_CR4_PAE); 6943 else 6944 vmcs_write(cr, val); 6945 report_prefix_pushf("%s %lx", cr_name, val); 6946 if (val == fixed0) 6947 test_vmx_vmlaunch(0); 6948 else 6949 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 6950 report_prefix_pop(); 6951 6952 for (i = 0; i < 64; i++) { 6953 6954 /* Set a bit when the corresponding bit in fixed1 is 0 */ 6955 if ((fixed1 & (1ull << i)) == 0) { 6956 if (cr == HOST_CR4 && ((1ull << i) & X86_CR4_SMEP || 6957 (1ull << i) & X86_CR4_SMAP)) 6958 continue; 6959 6960 vmcs_write(cr, cr_saved | (1ull << i)); 6961 report_prefix_pushf("%s %llx", cr_name, 6962 cr_saved | (1ull << i)); 6963 test_vmx_vmlaunch( 6964 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 6965 report_prefix_pop(); 6966 } 6967 6968 /* Unset a bit when the corresponding bit in fixed0 is 1 */ 6969 if (fixed0 & (1ull << i)) { 6970 vmcs_write(cr, cr_saved & ~(1ull << i)); 6971 report_prefix_pushf("%s %llx", cr_name, 6972 cr_saved & ~(1ull << i)); 6973 test_vmx_vmlaunch( 6974 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 6975 report_prefix_pop(); 6976 } 6977 } 6978 6979 vmcs_write(cr, cr_saved); 6980 } 6981 6982 /* 6983 * 1. The CR0 field must not set any bit to a value not supported in VMX 6984 * operation. 6985 * 2. The CR4 field must not set any bit to a value not supported in VMX 6986 * operation. 6987 * 3. On processors that support Intel 64 architecture, the CR3 field must 6988 * be such that bits 63:52 and bits in the range 51:32 beyond the 6989 * processor's physical-address width must be 0. 6990 * 6991 * [Intel SDM] 6992 */ 6993 static void test_host_ctl_regs(void) 6994 { 6995 u64 fixed0, fixed1, cr3, cr3_saved; 6996 int i; 6997 6998 /* Test CR0 */ 6999 fixed0 = rdmsr(MSR_IA32_VMX_CR0_FIXED0); 7000 fixed1 = rdmsr(MSR_IA32_VMX_CR0_FIXED1); 7001 test_ctl_reg("HOST_CR0", HOST_CR0, fixed0, fixed1); 7002 7003 /* Test CR4 */ 7004 fixed0 = rdmsr(MSR_IA32_VMX_CR4_FIXED0); 7005 fixed1 = rdmsr(MSR_IA32_VMX_CR4_FIXED1) & 7006 ~(X86_CR4_SMEP | X86_CR4_SMAP); 7007 test_ctl_reg("HOST_CR4", HOST_CR4, fixed0, fixed1); 7008 7009 /* Test CR3 */ 7010 cr3_saved = vmcs_read(HOST_CR3); 7011 for (i = cpuid_maxphyaddr(); i < 64; i++) { 7012 cr3 = cr3_saved | (1ul << i); 7013 vmcs_write(HOST_CR3, cr3); 7014 report_prefix_pushf("HOST_CR3 %lx", cr3); 7015 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7016 report_prefix_pop(); 7017 } 7018 7019 vmcs_write(HOST_CR3, cr3_saved); 7020 } 7021 7022 static void test_efer_vmlaunch(u32 fld, bool ok) 7023 { 7024 if (fld == HOST_EFER) { 7025 if (ok) 7026 test_vmx_vmlaunch(0); 7027 else 7028 test_vmx_vmlaunch2(VMXERR_ENTRY_INVALID_CONTROL_FIELD, 7029 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7030 } else { 7031 test_guest_state("EFER test", !ok, GUEST_EFER, "GUEST_EFER"); 7032 } 7033 } 7034 7035 static void test_efer_one(u32 fld, const char * fld_name, u64 efer, 7036 u32 ctrl_fld, u64 ctrl, 7037 int i, const char *efer_bit_name) 7038 { 7039 bool ok; 7040 7041 ok = true; 7042 if (ctrl_fld == EXI_CONTROLS && (ctrl & EXI_LOAD_EFER)) { 7043 if (!!(efer & EFER_LMA) != !!(ctrl & EXI_HOST_64)) 7044 ok = false; 7045 if (!!(efer & EFER_LME) != !!(ctrl & EXI_HOST_64)) 7046 ok = false; 7047 } 7048 if (ctrl_fld == ENT_CONTROLS && (ctrl & ENT_LOAD_EFER)) { 7049 /* Check LMA too since CR0.PG is set. */ 7050 if (!!(efer & EFER_LMA) != !!(ctrl & ENT_GUEST_64)) 7051 ok = false; 7052 if (!!(efer & EFER_LME) != !!(ctrl & ENT_GUEST_64)) 7053 ok = false; 7054 } 7055 7056 /* 7057 * Skip the test if it would enter the guest in 32-bit mode. 7058 * Perhaps write the test in assembly and make sure it 7059 * can be run in either mode? 7060 */ 7061 if (fld == GUEST_EFER && ok && !(ctrl & ENT_GUEST_64)) 7062 return; 7063 7064 vmcs_write(ctrl_fld, ctrl); 7065 vmcs_write(fld, efer); 7066 report_prefix_pushf("%s %s bit turned %s, controls %s", 7067 fld_name, efer_bit_name, 7068 (i & 1) ? "on" : "off", 7069 (i & 2) ? "on" : "off"); 7070 7071 test_efer_vmlaunch(fld, ok); 7072 report_prefix_pop(); 7073 } 7074 7075 static void test_efer_bit(u32 fld, const char * fld_name, 7076 u32 ctrl_fld, u64 ctrl_bit, u64 efer_bit, 7077 const char *efer_bit_name) 7078 { 7079 u64 efer_saved = vmcs_read(fld); 7080 u32 ctrl_saved = vmcs_read(ctrl_fld); 7081 int i; 7082 7083 for (i = 0; i < 4; i++) { 7084 u64 efer = efer_saved & ~efer_bit; 7085 u64 ctrl = ctrl_saved & ~ctrl_bit; 7086 7087 if (i & 1) 7088 efer |= efer_bit; 7089 if (i & 2) 7090 ctrl |= ctrl_bit; 7091 7092 test_efer_one(fld, fld_name, efer, ctrl_fld, ctrl, 7093 i, efer_bit_name); 7094 } 7095 7096 vmcs_write(ctrl_fld, ctrl_saved); 7097 vmcs_write(fld, efer_saved); 7098 } 7099 7100 static void test_efer(u32 fld, const char * fld_name, u32 ctrl_fld, 7101 u64 ctrl_bit1, u64 ctrl_bit2) 7102 { 7103 u64 efer_saved = vmcs_read(fld); 7104 u32 ctrl_saved = vmcs_read(ctrl_fld); 7105 u64 efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 7106 u64 i; 7107 u64 efer; 7108 7109 if (this_cpu_has(X86_FEATURE_NX)) 7110 efer_reserved_bits &= ~EFER_NX; 7111 7112 if (!ctrl_bit1) { 7113 report_skip("%s : \"Load-IA32-EFER\" exit control not supported", __func__); 7114 goto test_entry_exit_mode; 7115 } 7116 7117 report_prefix_pushf("%s %lx", fld_name, efer_saved); 7118 test_efer_vmlaunch(fld, true); 7119 report_prefix_pop(); 7120 7121 /* 7122 * Check reserved bits 7123 */ 7124 vmcs_write(ctrl_fld, ctrl_saved & ~ctrl_bit1); 7125 for (i = 0; i < 64; i++) { 7126 if ((1ull << i) & efer_reserved_bits) { 7127 efer = efer_saved | (1ull << i); 7128 vmcs_write(fld, efer); 7129 report_prefix_pushf("%s %lx", fld_name, efer); 7130 test_efer_vmlaunch(fld, true); 7131 report_prefix_pop(); 7132 } 7133 } 7134 7135 vmcs_write(ctrl_fld, ctrl_saved | ctrl_bit1); 7136 for (i = 0; i < 64; i++) { 7137 if ((1ull << i) & efer_reserved_bits) { 7138 efer = efer_saved | (1ull << i); 7139 vmcs_write(fld, efer); 7140 report_prefix_pushf("%s %lx", fld_name, efer); 7141 test_efer_vmlaunch(fld, false); 7142 report_prefix_pop(); 7143 } 7144 } 7145 7146 vmcs_write(ctrl_fld, ctrl_saved); 7147 vmcs_write(fld, efer_saved); 7148 7149 /* 7150 * Check LMA and LME bits 7151 */ 7152 test_efer_bit(fld, fld_name, 7153 ctrl_fld, ctrl_bit1, 7154 EFER_LMA, 7155 "EFER_LMA"); 7156 test_efer_bit(fld, fld_name, 7157 ctrl_fld, ctrl_bit1, 7158 EFER_LME, 7159 "EFER_LME"); 7160 7161 test_entry_exit_mode: 7162 test_efer_bit(fld, fld_name, 7163 ctrl_fld, ctrl_bit2, 7164 EFER_LMA, 7165 "EFER_LMA"); 7166 test_efer_bit(fld, fld_name, 7167 ctrl_fld, ctrl_bit2, 7168 EFER_LME, 7169 "EFER_LME"); 7170 } 7171 7172 /* 7173 * If the 'load IA32_EFER' VM-exit control is 1, bits reserved in the 7174 * IA32_EFER MSR must be 0 in the field for that register. In addition, 7175 * the values of the LMA and LME bits in the field must each be that of 7176 * the 'host address-space size' VM-exit control. 7177 * 7178 * [Intel SDM] 7179 */ 7180 static void test_host_efer(void) 7181 { 7182 test_efer(HOST_EFER, "HOST_EFER", EXI_CONTROLS, 7183 ctrl_exit_rev.clr & EXI_LOAD_EFER, 7184 EXI_HOST_64); 7185 } 7186 7187 /* 7188 * If the 'load IA32_EFER' VM-enter control is 1, bits reserved in the 7189 * IA32_EFER MSR must be 0 in the field for that register. In addition, 7190 * the values of the LMA and LME bits in the field must each be that of 7191 * the 'IA32e-mode guest' VM-exit control. 7192 */ 7193 static void test_guest_efer(void) 7194 { 7195 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) { 7196 report_skip("%s : \"Load-IA32-EFER\" entry control not supported", __func__); 7197 return; 7198 } 7199 7200 vmcs_write(GUEST_EFER, rdmsr(MSR_EFER)); 7201 test_efer(GUEST_EFER, "GUEST_EFER", ENT_CONTROLS, 7202 ctrl_enter_rev.clr & ENT_LOAD_EFER, 7203 ENT_GUEST_64); 7204 } 7205 7206 /* 7207 * PAT values higher than 8 are uninteresting since they're likely lumped 7208 * in with "8". We only test values above 8 one bit at a time, 7209 * in order to reduce the number of VM-Entries and keep the runtime reasonable. 7210 */ 7211 #define PAT_VAL_LIMIT 8 7212 7213 static void test_pat(u32 field, const char * field_name, u32 ctrl_field, 7214 u64 ctrl_bit) 7215 { 7216 u32 ctrl_saved = vmcs_read(ctrl_field); 7217 u64 pat_saved = vmcs_read(field); 7218 u64 i, val; 7219 u32 j; 7220 int error; 7221 7222 vmcs_clear_bits(ctrl_field, ctrl_bit); 7223 7224 for (i = 0; i < 256; i = (i < PAT_VAL_LIMIT) ? i + 1 : i * 2) { 7225 /* Test PAT0..PAT7 fields */ 7226 for (j = 0; j < (i ? 8 : 1); j++) { 7227 val = i << j * 8; 7228 vmcs_write(field, val); 7229 if (field == HOST_PAT) { 7230 report_prefix_pushf("%s %lx", field_name, val); 7231 test_vmx_vmlaunch(0); 7232 report_prefix_pop(); 7233 7234 } else { // GUEST_PAT 7235 test_guest_state("ENT_LOAD_PAT enabled", false, 7236 val, "GUEST_PAT"); 7237 } 7238 } 7239 } 7240 7241 vmcs_set_bits(ctrl_field, ctrl_bit); 7242 for (i = 0; i < 256; i = (i < PAT_VAL_LIMIT) ? i + 1 : i * 2) { 7243 /* Test PAT0..PAT7 fields */ 7244 for (j = 0; j < (i ? 8 : 1); j++) { 7245 val = i << j * 8; 7246 vmcs_write(field, val); 7247 7248 if (field == HOST_PAT) { 7249 report_prefix_pushf("%s %lx", field_name, val); 7250 if (i == 0x2 || i == 0x3 || i >= 0x8) 7251 error = 7252 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD; 7253 else 7254 error = 0; 7255 7256 test_vmx_vmlaunch(error); 7257 report_prefix_pop(); 7258 7259 } else { // GUEST_PAT 7260 error = (i == 0x2 || i == 0x3 || i >= 0x8); 7261 test_guest_state("ENT_LOAD_PAT enabled", !!error, 7262 val, "GUEST_PAT"); 7263 } 7264 7265 } 7266 } 7267 7268 vmcs_write(ctrl_field, ctrl_saved); 7269 vmcs_write(field, pat_saved); 7270 } 7271 7272 /* 7273 * If the "load IA32_PAT" VM-exit control is 1, the value of the field 7274 * for the IA32_PAT MSR must be one that could be written by WRMSR 7275 * without fault at CPL 0. Specifically, each of the 8 bytes in the 7276 * field must have one of the values 0 (UC), 1 (WC), 4 (WT), 5 (WP), 7277 * 6 (WB), or 7 (UC-). 7278 * 7279 * [Intel SDM] 7280 */ 7281 static void test_load_host_pat(void) 7282 { 7283 /* 7284 * "load IA32_PAT" VM-exit control 7285 */ 7286 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) { 7287 report_skip("%s : \"Load-IA32-PAT\" exit control not supported", __func__); 7288 return; 7289 } 7290 7291 test_pat(HOST_PAT, "HOST_PAT", EXI_CONTROLS, EXI_LOAD_PAT); 7292 } 7293 7294 union cpuidA_eax { 7295 struct { 7296 unsigned int version_id:8; 7297 unsigned int num_counters_gp:8; 7298 unsigned int bit_width:8; 7299 unsigned int mask_length:8; 7300 } split; 7301 unsigned int full; 7302 }; 7303 7304 union cpuidA_edx { 7305 struct { 7306 unsigned int num_counters_fixed:5; 7307 unsigned int bit_width_fixed:8; 7308 unsigned int reserved:9; 7309 } split; 7310 unsigned int full; 7311 }; 7312 7313 static bool valid_pgc(u64 val) 7314 { 7315 struct cpuid id; 7316 union cpuidA_eax eax; 7317 union cpuidA_edx edx; 7318 u64 mask; 7319 7320 id = cpuid(0xA); 7321 eax.full = id.a; 7322 edx.full = id.d; 7323 mask = ~(((1ull << eax.split.num_counters_gp) - 1) | 7324 (((1ull << edx.split.num_counters_fixed) - 1) << 32)); 7325 7326 return !(val & mask); 7327 } 7328 7329 static void test_pgc_vmlaunch(u32 xerror, u32 xreason, bool xfail, bool host) 7330 { 7331 u32 inst_err; 7332 u64 obs; 7333 bool success; 7334 struct vmx_state_area_test_data *data = &vmx_state_area_test_data; 7335 7336 if (host) { 7337 success = vmlaunch(); 7338 obs = rdmsr(data->msr); 7339 if (!success) { 7340 inst_err = vmcs_read(VMX_INST_ERROR); 7341 report(xerror == inst_err, "vmlaunch failed, " 7342 "VMX Inst Error is %d (expected %d)", 7343 inst_err, xerror); 7344 } else { 7345 report(!data->enabled || data->exp == obs, 7346 "Host state is 0x%lx (expected 0x%lx)", 7347 obs, data->exp); 7348 report(success != xfail, "vmlaunch succeeded"); 7349 } 7350 } else { 7351 test_guest_state("load GUEST_PERF_GLOBAL_CTRL", xfail, 7352 GUEST_PERF_GLOBAL_CTRL, 7353 "GUEST_PERF_GLOBAL_CTRL"); 7354 } 7355 } 7356 7357 /* 7358 * test_load_perf_global_ctrl is a generic function for testing the 7359 * "load IA32_PERF_GLOBAL_CTRL" VM-{Entry,Exit} controls. This test function 7360 * tests the provided ctrl_val when disabled and enabled. 7361 * 7362 * @nr: VMCS field number corresponding to the host/guest state field 7363 * @name: Name of the above VMCS field for printing in test report 7364 * @ctrl_nr: VMCS field number corresponding to the VM-{Entry,Exit} control 7365 * @ctrl_val: Bit to set on the ctrl_field 7366 */ 7367 static void test_perf_global_ctrl(u32 nr, const char *name, u32 ctrl_nr, 7368 const char *ctrl_name, u64 ctrl_val) 7369 { 7370 u64 ctrl_saved = vmcs_read(ctrl_nr); 7371 u64 pgc_saved = vmcs_read(nr); 7372 u64 i, val; 7373 bool host = nr == HOST_PERF_GLOBAL_CTRL; 7374 struct vmx_state_area_test_data *data = &vmx_state_area_test_data; 7375 7376 data->msr = MSR_CORE_PERF_GLOBAL_CTRL; 7377 msr_bmp_init(); 7378 vmcs_write(ctrl_nr, ctrl_saved & ~ctrl_val); 7379 data->enabled = false; 7380 report_prefix_pushf("\"load IA32_PERF_GLOBAL_CTRL\"=0 on %s", 7381 ctrl_name); 7382 7383 for (i = 0; i < 64; i++) { 7384 val = 1ull << i; 7385 vmcs_write(nr, val); 7386 report_prefix_pushf("%s = 0x%lx", name, val); 7387 test_pgc_vmlaunch(0, VMX_VMCALL, false, host); 7388 report_prefix_pop(); 7389 } 7390 report_prefix_pop(); 7391 7392 vmcs_write(ctrl_nr, ctrl_saved | ctrl_val); 7393 data->enabled = true; 7394 report_prefix_pushf("\"load IA32_PERF_GLOBAL_CTRL\"=1 on %s", 7395 ctrl_name); 7396 for (i = 0; i < 64; i++) { 7397 val = 1ull << i; 7398 data->exp = val; 7399 vmcs_write(nr, val); 7400 report_prefix_pushf("%s = 0x%lx", name, val); 7401 if (valid_pgc(val)) { 7402 test_pgc_vmlaunch(0, VMX_VMCALL, false, host); 7403 } else { 7404 if (host) 7405 test_pgc_vmlaunch( 7406 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, 7407 0, 7408 true, 7409 host); 7410 else 7411 test_pgc_vmlaunch( 7412 0, 7413 VMX_ENTRY_FAILURE | VMX_FAIL_STATE, 7414 true, 7415 host); 7416 } 7417 report_prefix_pop(); 7418 } 7419 7420 data->enabled = false; 7421 report_prefix_pop(); 7422 vmcs_write(ctrl_nr, ctrl_saved); 7423 vmcs_write(nr, pgc_saved); 7424 } 7425 7426 static void test_load_host_perf_global_ctrl(void) 7427 { 7428 if (!this_cpu_has_perf_global_ctrl()) { 7429 report_skip("%s : \"IA32_PERF_GLOBAL_CTRL\" MSR not supported", __func__); 7430 return; 7431 } 7432 7433 if (!(ctrl_exit_rev.clr & EXI_LOAD_PERF)) { 7434 report_skip("%s : \"Load IA32_PERF_GLOBAL_CTRL\" exit control not supported", __func__); 7435 return; 7436 } 7437 7438 test_perf_global_ctrl(HOST_PERF_GLOBAL_CTRL, "HOST_PERF_GLOBAL_CTRL", 7439 EXI_CONTROLS, "EXI_CONTROLS", EXI_LOAD_PERF); 7440 } 7441 7442 7443 static void test_load_guest_perf_global_ctrl(void) 7444 { 7445 if (!this_cpu_has_perf_global_ctrl()) { 7446 report_skip("%s : \"IA32_PERF_GLOBAL_CTRL\" MSR not supported", __func__); 7447 return; 7448 } 7449 7450 if (!(ctrl_enter_rev.clr & ENT_LOAD_PERF)) { 7451 report_skip("%s : \"Load IA32_PERF_GLOBAL_CTRL\" entry control not supported", __func__); 7452 return; 7453 } 7454 7455 test_perf_global_ctrl(GUEST_PERF_GLOBAL_CTRL, "GUEST_PERF_GLOBAL_CTRL", 7456 ENT_CONTROLS, "ENT_CONTROLS", ENT_LOAD_PERF); 7457 } 7458 7459 7460 /* 7461 * test_vmcs_field - test a value for the given VMCS field 7462 * @field: VMCS field 7463 * @field_name: string name of VMCS field 7464 * @bit_start: starting bit 7465 * @bit_end: ending bit 7466 * @val: value that the bit range must or must not contain 7467 * @valid_val: whether value given in 'val' must be valid or not 7468 * @error: expected VMCS error when vmentry fails for an invalid value 7469 */ 7470 static void test_vmcs_field(u64 field, const char *field_name, u32 bit_start, 7471 u32 bit_end, u64 val, bool valid_val, u32 error) 7472 { 7473 u64 field_saved = vmcs_read(field); 7474 u32 i; 7475 u64 tmp; 7476 u32 bit_on; 7477 u64 mask = ~0ull; 7478 7479 mask = (mask >> bit_end) << bit_end; 7480 mask = mask | ((1 << bit_start) - 1); 7481 tmp = (field_saved & mask) | (val << bit_start); 7482 7483 vmcs_write(field, tmp); 7484 report_prefix_pushf("%s %lx", field_name, tmp); 7485 if (valid_val) 7486 test_vmx_vmlaunch(0); 7487 else 7488 test_vmx_vmlaunch(error); 7489 report_prefix_pop(); 7490 7491 for (i = bit_start; i <= bit_end; i = i + 2) { 7492 bit_on = ((1ull < i) & (val << bit_start)) ? 0 : 1; 7493 if (bit_on) 7494 tmp = field_saved | (1ull << i); 7495 else 7496 tmp = field_saved & ~(1ull << i); 7497 vmcs_write(field, tmp); 7498 report_prefix_pushf("%s %lx", field_name, tmp); 7499 if (valid_val) 7500 test_vmx_vmlaunch(error); 7501 else 7502 test_vmx_vmlaunch(0); 7503 report_prefix_pop(); 7504 } 7505 7506 vmcs_write(field, field_saved); 7507 } 7508 7509 static void test_canonical(u64 field, const char * field_name, bool host) 7510 { 7511 u64 addr_saved = vmcs_read(field); 7512 7513 /* 7514 * Use the existing value if possible. Writing a random canonical 7515 * value is not an option as doing so would corrupt the field being 7516 * tested and likely hose the test. 7517 */ 7518 if (is_canonical(addr_saved)) { 7519 if (host) { 7520 report_prefix_pushf("%s %lx", field_name, addr_saved); 7521 test_vmx_vmlaunch(0); 7522 report_prefix_pop(); 7523 } else { 7524 test_guest_state("Test canonical address", false, 7525 addr_saved, field_name); 7526 } 7527 } 7528 7529 vmcs_write(field, NONCANONICAL); 7530 7531 if (host) { 7532 report_prefix_pushf("%s %llx", field_name, NONCANONICAL); 7533 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7534 report_prefix_pop(); 7535 } else { 7536 test_guest_state("Test non-canonical address", true, 7537 NONCANONICAL, field_name); 7538 } 7539 7540 vmcs_write(field, addr_saved); 7541 } 7542 7543 #define TEST_RPL_TI_FLAGS(reg, name) \ 7544 test_vmcs_field(reg, name, 0, 2, 0x0, true, \ 7545 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7546 7547 #define TEST_CS_TR_FLAGS(reg, name) \ 7548 test_vmcs_field(reg, name, 3, 15, 0x0000, false, \ 7549 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7550 7551 /* 7552 * 1. In the selector field for each of CS, SS, DS, ES, FS, GS and TR, the 7553 * RPL (bits 1:0) and the TI flag (bit 2) must be 0. 7554 * 2. The selector fields for CS and TR cannot be 0000H. 7555 * 3. The selector field for SS cannot be 0000H if the "host address-space 7556 * size" VM-exit control is 0. 7557 * 4. On processors that support Intel 64 architecture, the base-address 7558 * fields for FS, GS and TR must contain canonical addresses. 7559 */ 7560 static void test_host_segment_regs(void) 7561 { 7562 u16 selector_saved; 7563 7564 /* 7565 * Test RPL and TI flags 7566 */ 7567 TEST_RPL_TI_FLAGS(HOST_SEL_CS, "HOST_SEL_CS"); 7568 TEST_RPL_TI_FLAGS(HOST_SEL_SS, "HOST_SEL_SS"); 7569 TEST_RPL_TI_FLAGS(HOST_SEL_DS, "HOST_SEL_DS"); 7570 TEST_RPL_TI_FLAGS(HOST_SEL_ES, "HOST_SEL_ES"); 7571 TEST_RPL_TI_FLAGS(HOST_SEL_FS, "HOST_SEL_FS"); 7572 TEST_RPL_TI_FLAGS(HOST_SEL_GS, "HOST_SEL_GS"); 7573 TEST_RPL_TI_FLAGS(HOST_SEL_TR, "HOST_SEL_TR"); 7574 7575 /* 7576 * Test that CS and TR fields can not be 0x0000 7577 */ 7578 TEST_CS_TR_FLAGS(HOST_SEL_CS, "HOST_SEL_CS"); 7579 TEST_CS_TR_FLAGS(HOST_SEL_TR, "HOST_SEL_TR"); 7580 7581 /* 7582 * SS field can not be 0x0000 if "host address-space size" VM-exit 7583 * control is 0 7584 */ 7585 selector_saved = vmcs_read(HOST_SEL_SS); 7586 vmcs_write(HOST_SEL_SS, 0); 7587 report_prefix_pushf("HOST_SEL_SS 0"); 7588 if (vmcs_read(EXI_CONTROLS) & EXI_HOST_64) { 7589 test_vmx_vmlaunch(0); 7590 } else { 7591 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7592 } 7593 report_prefix_pop(); 7594 7595 vmcs_write(HOST_SEL_SS, selector_saved); 7596 7597 /* 7598 * Base address for FS, GS and TR must be canonical 7599 */ 7600 test_canonical(HOST_BASE_FS, "HOST_BASE_FS", true); 7601 test_canonical(HOST_BASE_GS, "HOST_BASE_GS", true); 7602 test_canonical(HOST_BASE_TR, "HOST_BASE_TR", true); 7603 } 7604 7605 /* 7606 * On processors that support Intel 64 architecture, the base-address 7607 * fields for GDTR and IDTR must contain canonical addresses. 7608 */ 7609 static void test_host_desc_tables(void) 7610 { 7611 test_canonical(HOST_BASE_GDTR, "HOST_BASE_GDTR", true); 7612 test_canonical(HOST_BASE_IDTR, "HOST_BASE_IDTR", true); 7613 } 7614 7615 /* 7616 * If the "host address-space size" VM-exit control is 0, the following must 7617 * hold: 7618 * - The "IA-32e mode guest" VM-entry control is 0. 7619 * - Bit 17 of the CR4 field (corresponding to CR4.PCIDE) is 0. 7620 * - Bits 63:32 in the RIP field are 0. 7621 * 7622 * If the "host address-space size" VM-exit control is 1, the following must 7623 * hold: 7624 * - Bit 5 of the CR4 field (corresponding to CR4.PAE) is 1. 7625 * - The RIP field contains a canonical address. 7626 * 7627 */ 7628 static void test_host_addr_size(void) 7629 { 7630 u64 cr4_saved = vmcs_read(HOST_CR4); 7631 u64 rip_saved = vmcs_read(HOST_RIP); 7632 u64 entry_ctrl_saved = vmcs_read(ENT_CONTROLS); 7633 7634 assert(vmcs_read(EXI_CONTROLS) & EXI_HOST_64); 7635 assert(cr4_saved & X86_CR4_PAE); 7636 7637 vmcs_write(ENT_CONTROLS, entry_ctrl_saved | ENT_GUEST_64); 7638 report_prefix_pushf("\"IA-32e mode guest\" enabled"); 7639 test_vmx_vmlaunch(0); 7640 report_prefix_pop(); 7641 7642 if (this_cpu_has(X86_FEATURE_PCID)) { 7643 vmcs_write(HOST_CR4, cr4_saved | X86_CR4_PCIDE); 7644 report_prefix_pushf("\"CR4.PCIDE\" set"); 7645 test_vmx_vmlaunch(0); 7646 report_prefix_pop(); 7647 } 7648 7649 vmcs_write(HOST_CR4, cr4_saved & ~X86_CR4_PAE); 7650 report_prefix_pushf("\"CR4.PAE\" unset"); 7651 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7652 vmcs_write(HOST_CR4, cr4_saved); 7653 report_prefix_pop(); 7654 7655 vmcs_write(HOST_RIP, NONCANONICAL); 7656 report_prefix_pushf("HOST_RIP %llx", NONCANONICAL); 7657 test_vmx_vmlaunch_must_fail(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7658 report_prefix_pop(); 7659 7660 vmcs_write(ENT_CONTROLS, entry_ctrl_saved | ENT_GUEST_64); 7661 vmcs_write(HOST_RIP, rip_saved); 7662 vmcs_write(HOST_CR4, cr4_saved); 7663 7664 /* 7665 * Restore host's active CR4 and RIP values by triggering a VM-Exit. 7666 * The original CR4 and RIP values in the VMCS are restored between 7667 * testcases as needed, but don't guarantee a VM-Exit and so the active 7668 * CR4 and RIP may still hold a test value. Running with the test CR4 7669 * and RIP values at some point is unavoidable, and the active values 7670 * are unlikely to affect VM-Enter, so the above doesn't force a VM-exit 7671 * between testcases. Note, if VM-Enter is surrounded by CALL+RET then 7672 * the active RIP will already be restored, but that's also not 7673 * guaranteed, and CR4 needs to be restored regardless. 7674 */ 7675 report_prefix_pushf("restore host state"); 7676 test_vmx_vmlaunch(0); 7677 report_prefix_pop(); 7678 } 7679 7680 /* 7681 * Check that the virtual CPU checks the VMX Host State Area as 7682 * documented in the Intel SDM. 7683 */ 7684 static void vmx_host_state_area_test(void) 7685 { 7686 /* 7687 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 7688 * fail due to invalid guest state, should we make it that 7689 * far. 7690 */ 7691 vmcs_write(GUEST_RFLAGS, 0); 7692 7693 test_host_ctl_regs(); 7694 7695 test_canonical(HOST_SYSENTER_ESP, "HOST_SYSENTER_ESP", true); 7696 test_canonical(HOST_SYSENTER_EIP, "HOST_SYSENTER_EIP", true); 7697 7698 test_host_efer(); 7699 test_load_host_pat(); 7700 test_host_segment_regs(); 7701 test_host_desc_tables(); 7702 test_host_addr_size(); 7703 test_load_host_perf_global_ctrl(); 7704 } 7705 7706 /* 7707 * If the "load debug controls" VM-entry control is 1, bits 63:32 in 7708 * the DR7 field must be 0. 7709 * 7710 * [Intel SDM] 7711 */ 7712 static void test_guest_dr7(void) 7713 { 7714 u32 ent_saved = vmcs_read(ENT_CONTROLS); 7715 u64 dr7_saved = vmcs_read(GUEST_DR7); 7716 u64 val; 7717 int i; 7718 7719 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS) { 7720 vmcs_clear_bits(ENT_CONTROLS, ENT_LOAD_DBGCTLS); 7721 for (i = 0; i < 64; i++) { 7722 val = 1ull << i; 7723 vmcs_write(GUEST_DR7, val); 7724 test_guest_state("ENT_LOAD_DBGCTLS disabled", false, 7725 val, "GUEST_DR7"); 7726 } 7727 } 7728 if (ctrl_enter_rev.clr & ENT_LOAD_DBGCTLS) { 7729 vmcs_set_bits(ENT_CONTROLS, ENT_LOAD_DBGCTLS); 7730 for (i = 0; i < 64; i++) { 7731 val = 1ull << i; 7732 vmcs_write(GUEST_DR7, val); 7733 test_guest_state("ENT_LOAD_DBGCTLS enabled", i >= 32, 7734 val, "GUEST_DR7"); 7735 } 7736 } 7737 vmcs_write(GUEST_DR7, dr7_saved); 7738 vmcs_write(ENT_CONTROLS, ent_saved); 7739 } 7740 7741 /* 7742 * If the "load IA32_PAT" VM-entry control is 1, the value of the field 7743 * for the IA32_PAT MSR must be one that could be written by WRMSR 7744 * without fault at CPL 0. Specifically, each of the 8 bytes in the 7745 * field must have one of the values 0 (UC), 1 (WC), 4 (WT), 5 (WP), 7746 * 6 (WB), or 7 (UC-). 7747 * 7748 * [Intel SDM] 7749 */ 7750 static void test_load_guest_pat(void) 7751 { 7752 /* 7753 * "load IA32_PAT" VM-entry control 7754 */ 7755 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 7756 report_skip("%s : \"Load-IA32-PAT\" entry control not supported", __func__); 7757 return; 7758 } 7759 7760 test_pat(GUEST_PAT, "GUEST_PAT", ENT_CONTROLS, ENT_LOAD_PAT); 7761 } 7762 7763 #define MSR_IA32_BNDCFGS_RSVD_MASK 0x00000ffc 7764 7765 /* 7766 * If the "load IA32_BNDCFGS" VM-entry control is 1, the following 7767 * checks are performed on the field for the IA32_BNDCFGS MSR: 7768 * 7769 * - Bits reserved in the IA32_BNDCFGS MSR must be 0. 7770 * - The linear address in bits 63:12 must be canonical. 7771 * 7772 * [Intel SDM] 7773 */ 7774 static void test_load_guest_bndcfgs(void) 7775 { 7776 u64 bndcfgs_saved = vmcs_read(GUEST_BNDCFGS); 7777 u64 bndcfgs; 7778 7779 if (!(ctrl_enter_rev.clr & ENT_LOAD_BNDCFGS)) { 7780 report_skip("%s : \"Load-IA32-BNDCFGS\" entry control not supported", __func__); 7781 return; 7782 } 7783 7784 vmcs_clear_bits(ENT_CONTROLS, ENT_LOAD_BNDCFGS); 7785 7786 vmcs_write(GUEST_BNDCFGS, NONCANONICAL); 7787 test_guest_state("ENT_LOAD_BNDCFGS disabled", false, 7788 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7789 bndcfgs = bndcfgs_saved | MSR_IA32_BNDCFGS_RSVD_MASK; 7790 vmcs_write(GUEST_BNDCFGS, bndcfgs); 7791 test_guest_state("ENT_LOAD_BNDCFGS disabled", false, 7792 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7793 7794 vmcs_set_bits(ENT_CONTROLS, ENT_LOAD_BNDCFGS); 7795 7796 vmcs_write(GUEST_BNDCFGS, NONCANONICAL); 7797 test_guest_state("ENT_LOAD_BNDCFGS enabled", true, 7798 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7799 bndcfgs = bndcfgs_saved | MSR_IA32_BNDCFGS_RSVD_MASK; 7800 vmcs_write(GUEST_BNDCFGS, bndcfgs); 7801 test_guest_state("ENT_LOAD_BNDCFGS enabled", true, 7802 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7803 7804 vmcs_write(GUEST_BNDCFGS, bndcfgs_saved); 7805 } 7806 7807 #define GUEST_SEG_UNUSABLE_MASK (1u << 16) 7808 #define GUEST_SEG_SEL_TI_MASK (1u << 2) 7809 7810 7811 #define TEST_SEGMENT_SEL(test, xfail, sel, val) \ 7812 do { \ 7813 vmcs_write(sel, val); \ 7814 test_guest_state(test " segment", xfail, val, xstr(sel)); \ 7815 } while (0) 7816 7817 #define TEST_INVALID_SEG_SEL(sel, val) \ 7818 TEST_SEGMENT_SEL("Invalid: " xstr(val), true, sel, val); 7819 7820 #define TEST_VALID_SEG_SEL(sel, val) \ 7821 TEST_SEGMENT_SEL("Valid: " xstr(val), false, sel, val); 7822 7823 /* 7824 * The following checks are done on the Selector field of the Guest Segment 7825 * Registers: 7826 * - TR. The TI flag (bit 2) must be 0. 7827 * - LDTR. If LDTR is usable, the TI flag (bit 2) must be 0. 7828 * - SS. If the guest will not be virtual-8086 and the "unrestricted 7829 * guest" VM-execution control is 0, the RPL (bits 1:0) must equal 7830 * the RPL of the selector field for CS. 7831 * 7832 * [Intel SDM] 7833 */ 7834 static void test_guest_segment_sel_fields(void) 7835 { 7836 u16 sel_saved; 7837 u32 ar_saved; 7838 u32 cpu_ctrl0_saved; 7839 u32 cpu_ctrl1_saved; 7840 u16 cs_rpl_bits; 7841 7842 /* 7843 * Test for GUEST_SEL_TR 7844 */ 7845 sel_saved = vmcs_read(GUEST_SEL_TR); 7846 TEST_INVALID_SEG_SEL(GUEST_SEL_TR, sel_saved | GUEST_SEG_SEL_TI_MASK); 7847 vmcs_write(GUEST_SEL_TR, sel_saved); 7848 7849 /* 7850 * Test for GUEST_SEL_LDTR 7851 */ 7852 sel_saved = vmcs_read(GUEST_SEL_LDTR); 7853 ar_saved = vmcs_read(GUEST_AR_LDTR); 7854 /* LDTR is set unusable */ 7855 vmcs_write(GUEST_AR_LDTR, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7856 TEST_VALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved | GUEST_SEG_SEL_TI_MASK); 7857 TEST_VALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved & ~GUEST_SEG_SEL_TI_MASK); 7858 /* LDTR is set usable */ 7859 vmcs_write(GUEST_AR_LDTR, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7860 TEST_INVALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved | GUEST_SEG_SEL_TI_MASK); 7861 7862 TEST_VALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved & ~GUEST_SEG_SEL_TI_MASK); 7863 7864 vmcs_write(GUEST_AR_LDTR, ar_saved); 7865 vmcs_write(GUEST_SEL_LDTR, sel_saved); 7866 7867 /* 7868 * Test for GUEST_SEL_SS 7869 */ 7870 cpu_ctrl0_saved = vmcs_read(CPU_EXEC_CTRL0); 7871 cpu_ctrl1_saved = vmcs_read(CPU_EXEC_CTRL1); 7872 ar_saved = vmcs_read(GUEST_AR_SS); 7873 /* Turn off "unrestricted guest" vm-execution control */ 7874 vmcs_write(CPU_EXEC_CTRL1, cpu_ctrl1_saved & ~CPU_URG); 7875 cs_rpl_bits = vmcs_read(GUEST_SEL_CS) & 0x3; 7876 sel_saved = vmcs_read(GUEST_SEL_SS); 7877 TEST_INVALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 7878 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 7879 /* Make SS usable if it's unusable or vice-versa */ 7880 if (ar_saved & GUEST_SEG_UNUSABLE_MASK) 7881 vmcs_write(GUEST_AR_SS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7882 else 7883 vmcs_write(GUEST_AR_SS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7884 TEST_INVALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 7885 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 7886 7887 /* Need a valid EPTP as the passing case fully enters the guest. */ 7888 if (enable_unrestricted_guest(true)) 7889 goto skip_ss_tests; 7890 7891 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 7892 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 7893 7894 /* Make SS usable if it's unusable or vice-versa */ 7895 if (vmcs_read(GUEST_AR_SS) & GUEST_SEG_UNUSABLE_MASK) 7896 vmcs_write(GUEST_AR_SS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7897 else 7898 vmcs_write(GUEST_AR_SS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7899 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 7900 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 7901 skip_ss_tests: 7902 7903 vmcs_write(GUEST_AR_SS, ar_saved); 7904 vmcs_write(GUEST_SEL_SS, sel_saved); 7905 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrl0_saved); 7906 vmcs_write(CPU_EXEC_CTRL1, cpu_ctrl1_saved); 7907 } 7908 7909 #define TEST_SEGMENT_BASE_ADDR_UPPER_BITS(xfail, seg_base) \ 7910 do { \ 7911 addr_saved = vmcs_read(seg_base); \ 7912 for (i = 32; i < 63; i = i + 4) { \ 7913 addr = addr_saved | 1ull << i; \ 7914 vmcs_write(seg_base, addr); \ 7915 test_guest_state("seg.BASE[63:32] != 0, usable = " xstr(xfail), \ 7916 xfail, addr, xstr(seg_base)); \ 7917 } \ 7918 vmcs_write(seg_base, addr_saved); \ 7919 } while (0) 7920 7921 #define TEST_SEGMENT_BASE_ADDR_CANONICAL(xfail, seg_base) \ 7922 do { \ 7923 addr_saved = vmcs_read(seg_base); \ 7924 vmcs_write(seg_base, NONCANONICAL); \ 7925 test_guest_state("seg.BASE non-canonical, usable = " xstr(xfail), \ 7926 xfail, NONCANONICAL, xstr(seg_base)); \ 7927 vmcs_write(seg_base, addr_saved); \ 7928 } while (0) 7929 7930 /* 7931 * The following checks are done on the Base Address field of the Guest 7932 * Segment Registers on processors that support Intel 64 architecture: 7933 * - TR, FS, GS : The address must be canonical. 7934 * - LDTR : If LDTR is usable, the address must be canonical. 7935 * - CS : Bits 63:32 of the address must be zero. 7936 * - SS, DS, ES : If the register is usable, bits 63:32 of the address 7937 * must be zero. 7938 * 7939 * [Intel SDM] 7940 */ 7941 static void test_guest_segment_base_addr_fields(void) 7942 { 7943 u64 addr_saved; 7944 u64 addr; 7945 u32 ar_saved; 7946 int i; 7947 7948 /* 7949 * The address of TR, FS, GS and LDTR must be canonical. 7950 */ 7951 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_TR); 7952 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_FS); 7953 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_GS); 7954 ar_saved = vmcs_read(GUEST_AR_LDTR); 7955 /* Make LDTR unusable */ 7956 vmcs_write(GUEST_AR_LDTR, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7957 TEST_SEGMENT_BASE_ADDR_CANONICAL(false, GUEST_BASE_LDTR); 7958 /* Make LDTR usable */ 7959 vmcs_write(GUEST_AR_LDTR, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7960 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_LDTR); 7961 7962 vmcs_write(GUEST_AR_LDTR, ar_saved); 7963 7964 /* 7965 * Bits 63:32 in CS, SS, DS and ES base address must be zero 7966 */ 7967 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_CS); 7968 ar_saved = vmcs_read(GUEST_AR_SS); 7969 /* Make SS unusable */ 7970 vmcs_write(GUEST_AR_SS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7971 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(false, GUEST_BASE_SS); 7972 /* Make SS usable */ 7973 vmcs_write(GUEST_AR_SS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7974 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_SS); 7975 vmcs_write(GUEST_AR_SS, ar_saved); 7976 7977 ar_saved = vmcs_read(GUEST_AR_DS); 7978 /* Make DS unusable */ 7979 vmcs_write(GUEST_AR_DS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7980 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(false, GUEST_BASE_DS); 7981 /* Make DS usable */ 7982 vmcs_write(GUEST_AR_DS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7983 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_DS); 7984 vmcs_write(GUEST_AR_DS, ar_saved); 7985 7986 ar_saved = vmcs_read(GUEST_AR_ES); 7987 /* Make ES unusable */ 7988 vmcs_write(GUEST_AR_ES, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7989 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(false, GUEST_BASE_ES); 7990 /* Make ES usable */ 7991 vmcs_write(GUEST_AR_ES, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7992 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_ES); 7993 vmcs_write(GUEST_AR_ES, ar_saved); 7994 } 7995 7996 /* 7997 * Check that the virtual CPU checks the VMX Guest State Area as 7998 * documented in the Intel SDM. 7999 */ 8000 static void vmx_guest_state_area_test(void) 8001 { 8002 vmx_set_test_stage(1); 8003 test_set_guest(guest_state_test_main); 8004 8005 /* 8006 * The IA32_SYSENTER_ESP field and the IA32_SYSENTER_EIP field 8007 * must each contain a canonical address. 8008 */ 8009 test_canonical(GUEST_SYSENTER_ESP, "GUEST_SYSENTER_ESP", false); 8010 test_canonical(GUEST_SYSENTER_EIP, "GUEST_SYSENTER_EIP", false); 8011 8012 test_guest_dr7(); 8013 test_load_guest_pat(); 8014 test_guest_efer(); 8015 test_load_guest_perf_global_ctrl(); 8016 test_load_guest_bndcfgs(); 8017 8018 test_guest_segment_sel_fields(); 8019 test_guest_segment_base_addr_fields(); 8020 8021 test_canonical(GUEST_BASE_GDTR, "GUEST_BASE_GDTR", false); 8022 test_canonical(GUEST_BASE_IDTR, "GUEST_BASE_IDTR", false); 8023 8024 u32 guest_desc_limit_saved = vmcs_read(GUEST_LIMIT_GDTR); 8025 int i; 8026 for (i = 16; i <= 31; i++) { 8027 u32 tmp = guest_desc_limit_saved | (1ull << i); 8028 vmcs_write(GUEST_LIMIT_GDTR, tmp); 8029 test_guest_state("GDT.limit > 0xffff", true, tmp, "GUEST_LIMIT_GDTR"); 8030 } 8031 vmcs_write(GUEST_LIMIT_GDTR, guest_desc_limit_saved); 8032 8033 guest_desc_limit_saved = vmcs_read(GUEST_LIMIT_IDTR); 8034 for (i = 16; i <= 31; i++) { 8035 u32 tmp = guest_desc_limit_saved | (1ull << i); 8036 vmcs_write(GUEST_LIMIT_IDTR, tmp); 8037 test_guest_state("IDT.limit > 0xffff", true, tmp, "GUEST_LIMIT_IDTR"); 8038 } 8039 vmcs_write(GUEST_LIMIT_IDTR, guest_desc_limit_saved); 8040 8041 /* 8042 * Let the guest finish execution 8043 */ 8044 vmx_set_test_stage(2); 8045 enter_guest(); 8046 } 8047 8048 extern void unrestricted_guest_main(void); 8049 asm (".code32\n" 8050 "unrestricted_guest_main:\n" 8051 "vmcall\n" 8052 "nop\n" 8053 "mov $1, %edi\n" 8054 "call hypercall\n" 8055 ".code64\n"); 8056 8057 static void setup_unrestricted_guest(void) 8058 { 8059 vmcs_write(GUEST_CR0, vmcs_read(GUEST_CR0) & ~(X86_CR0_PG)); 8060 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) & ~ENT_GUEST_64); 8061 vmcs_write(GUEST_EFER, vmcs_read(GUEST_EFER) & ~EFER_LMA); 8062 vmcs_write(GUEST_RIP, virt_to_phys(unrestricted_guest_main)); 8063 } 8064 8065 static void unsetup_unrestricted_guest(void) 8066 { 8067 vmcs_write(GUEST_CR0, vmcs_read(GUEST_CR0) | X86_CR0_PG); 8068 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) | ENT_GUEST_64); 8069 vmcs_write(GUEST_EFER, vmcs_read(GUEST_EFER) | EFER_LMA); 8070 vmcs_write(GUEST_RIP, (u64) phys_to_virt(vmcs_read(GUEST_RIP))); 8071 vmcs_write(GUEST_RSP, (u64) phys_to_virt(vmcs_read(GUEST_RSP))); 8072 } 8073 8074 /* 8075 * If "unrestricted guest" secondary VM-execution control is set, guests 8076 * can run in unpaged protected mode. 8077 */ 8078 static void vmentry_unrestricted_guest_test(void) 8079 { 8080 if (enable_unrestricted_guest(true)) { 8081 report_skip("%s: \"Unrestricted guest\" exec control not supported", __func__); 8082 return; 8083 } 8084 8085 test_set_guest(unrestricted_guest_main); 8086 setup_unrestricted_guest(); 8087 test_guest_state("Unrestricted guest test", false, CPU_URG, "CPU_URG"); 8088 8089 /* 8090 * Let the guest finish execution as a regular guest 8091 */ 8092 unsetup_unrestricted_guest(); 8093 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) & ~CPU_URG); 8094 enter_guest(); 8095 } 8096 8097 static bool valid_vmcs_for_vmentry(void) 8098 { 8099 struct vmcs *current_vmcs = NULL; 8100 8101 if (vmcs_save(¤t_vmcs)) 8102 return false; 8103 8104 return current_vmcs && !current_vmcs->hdr.shadow_vmcs; 8105 } 8106 8107 static void try_vmentry_in_movss_shadow(void) 8108 { 8109 u32 vm_inst_err; 8110 u32 flags; 8111 bool early_failure = false; 8112 u32 expected_flags = X86_EFLAGS_FIXED; 8113 bool valid_vmcs = valid_vmcs_for_vmentry(); 8114 8115 expected_flags |= valid_vmcs ? X86_EFLAGS_ZF : X86_EFLAGS_CF; 8116 8117 /* 8118 * Indirectly set VM_INST_ERR to 12 ("VMREAD/VMWRITE from/to 8119 * unsupported VMCS component"). 8120 */ 8121 vmcs_write(~0u, 0); 8122 8123 __asm__ __volatile__ ("mov %[host_rsp], %%edx;" 8124 "vmwrite %%rsp, %%rdx;" 8125 "mov 0f, %%rax;" 8126 "mov %[host_rip], %%edx;" 8127 "vmwrite %%rax, %%rdx;" 8128 "mov $-1, %%ah;" 8129 "sahf;" 8130 "mov %%ss, %%ax;" 8131 "mov %%ax, %%ss;" 8132 "vmlaunch;" 8133 "mov $1, %[early_failure];" 8134 "0: lahf;" 8135 "movzbl %%ah, %[flags]" 8136 : [early_failure] "+r" (early_failure), 8137 [flags] "=&a" (flags) 8138 : [host_rsp] "i" (HOST_RSP), 8139 [host_rip] "i" (HOST_RIP) 8140 : "rdx", "cc", "memory"); 8141 vm_inst_err = vmcs_read(VMX_INST_ERROR); 8142 8143 report(early_failure, "Early VM-entry failure"); 8144 report(flags == expected_flags, "RFLAGS[8:0] is %x (actual %x)", 8145 expected_flags, flags); 8146 if (valid_vmcs) 8147 report(vm_inst_err == VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, 8148 "VM-instruction error is %d (actual %d)", 8149 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, vm_inst_err); 8150 } 8151 8152 static void vmentry_movss_shadow_test(void) 8153 { 8154 struct vmcs *orig_vmcs; 8155 8156 TEST_ASSERT(!vmcs_save(&orig_vmcs)); 8157 8158 /* 8159 * Set the launched flag on the current VMCS to verify the correct 8160 * error priority, below. 8161 */ 8162 test_set_guest(v2_null_test_guest); 8163 enter_guest(); 8164 8165 /* 8166 * With bit 1 of the guest's RFLAGS clear, VM-entry should 8167 * fail due to invalid guest state (if we make it that far). 8168 */ 8169 vmcs_write(GUEST_RFLAGS, 0); 8170 8171 /* 8172 * "VM entry with events blocked by MOV SS" takes precedence over 8173 * "VMLAUNCH with non-clear VMCS." 8174 */ 8175 report_prefix_push("valid current-VMCS"); 8176 try_vmentry_in_movss_shadow(); 8177 report_prefix_pop(); 8178 8179 /* 8180 * VMfailInvalid takes precedence over "VM entry with events 8181 * blocked by MOV SS." 8182 */ 8183 TEST_ASSERT(!vmcs_clear(orig_vmcs)); 8184 report_prefix_push("no current-VMCS"); 8185 try_vmentry_in_movss_shadow(); 8186 report_prefix_pop(); 8187 8188 TEST_ASSERT(!make_vmcs_current(orig_vmcs)); 8189 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 8190 } 8191 8192 static void vmx_ldtr_test_guest(void) 8193 { 8194 u16 ldtr = sldt(); 8195 8196 report(ldtr == NP_SEL, "Expected %x for L2 LDTR selector (got %x)", 8197 NP_SEL, ldtr); 8198 } 8199 8200 /* 8201 * Ensure that the L1 LDTR is set to 0 on VM-exit. 8202 */ 8203 static void vmx_ldtr_test(void) 8204 { 8205 const u8 ldt_ar = 0x82; /* Present LDT */ 8206 u16 sel = FIRST_SPARE_SEL; 8207 8208 /* Set up a non-zero L1 LDTR prior to VM-entry. */ 8209 set_gdt_entry(sel, 0, 0, ldt_ar, 0); 8210 lldt(sel); 8211 8212 test_set_guest(vmx_ldtr_test_guest); 8213 /* 8214 * Set up a different LDTR for L2. The actual GDT contents are 8215 * irrelevant, since we stuff the hidden descriptor state 8216 * straight into the VMCS rather than reading it from the GDT. 8217 */ 8218 vmcs_write(GUEST_SEL_LDTR, NP_SEL); 8219 vmcs_write(GUEST_AR_LDTR, ldt_ar); 8220 enter_guest(); 8221 8222 /* 8223 * VM-exit should clear LDTR (and make it unusable, but we 8224 * won't verify that here). 8225 */ 8226 sel = sldt(); 8227 report(!sel, "Expected 0 for L1 LDTR selector (got %x)", sel); 8228 } 8229 8230 static void vmx_single_vmcall_guest(void) 8231 { 8232 vmcall(); 8233 } 8234 8235 static void vmx_cr_load_test(void) 8236 { 8237 unsigned long cr3, cr4, orig_cr3, orig_cr4; 8238 u32 ctrls[2] = {0}; 8239 pgd_t *pml5; 8240 8241 orig_cr4 = read_cr4(); 8242 orig_cr3 = read_cr3(); 8243 8244 if (!this_cpu_has(X86_FEATURE_PCID)) { 8245 report_skip("%s : PCID not detected", __func__); 8246 return; 8247 } 8248 if (!this_cpu_has(X86_FEATURE_MCE)) { 8249 report_skip("%s : MCE not detected", __func__); 8250 return; 8251 } 8252 8253 TEST_ASSERT(!(orig_cr3 & X86_CR3_PCID_MASK)); 8254 8255 /* Enable PCID for L1. */ 8256 cr4 = orig_cr4 | X86_CR4_PCIDE; 8257 cr3 = orig_cr3 | 0x1; 8258 TEST_ASSERT(!write_cr4_safe(cr4)); 8259 write_cr3(cr3); 8260 8261 test_set_guest(vmx_single_vmcall_guest); 8262 vmcs_write(HOST_CR4, cr4); 8263 vmcs_write(HOST_CR3, cr3); 8264 enter_guest(); 8265 8266 /* 8267 * No exception is expected. 8268 * 8269 * NB. KVM loads the last guest write to CR4 into CR4 read 8270 * shadow. In order to trigger an exit to KVM, we can toggle a 8271 * bit that is owned by KVM. We use CR4.MCE, which shall 8272 * have no side effect because normally no guest MCE (e.g., as the 8273 * result of bad memory) would happen during this test. 8274 */ 8275 TEST_ASSERT(!write_cr4_safe(cr4 ^ X86_CR4_MCE)); 8276 8277 /* Cleanup L1 state. */ 8278 write_cr3(orig_cr3); 8279 TEST_ASSERT(!write_cr4_safe(orig_cr4)); 8280 8281 if (!this_cpu_has(X86_FEATURE_LA57)) 8282 goto done; 8283 8284 /* 8285 * Allocate a full page for PML5 to guarantee alignment, though only 8286 * the first entry needs to be filled (the test's virtual addresses 8287 * most definitely do not have any of bits 56:48 set). 8288 */ 8289 pml5 = alloc_page(); 8290 *pml5 = orig_cr3 | PT_PRESENT_MASK | PT_WRITABLE_MASK; 8291 8292 /* 8293 * Transition to/from 5-level paging in the host via VM-Exit. CR4.LA57 8294 * can't be toggled while long is active via MOV CR4, but there are no 8295 * such restrictions on VM-Exit. 8296 */ 8297 lol_5level: 8298 vmcs_write(HOST_CR4, orig_cr4 | X86_CR4_LA57); 8299 vmcs_write(HOST_CR3, virt_to_phys(pml5)); 8300 enter_guest(); 8301 8302 /* 8303 * VMREAD with a memory operand to verify KVM detects the LA57 change, 8304 * e.g. uses the correct guest root level in gva_to_gpa(). 8305 */ 8306 TEST_ASSERT(vmcs_readm(HOST_CR3) == virt_to_phys(pml5)); 8307 TEST_ASSERT(vmcs_readm(HOST_CR4) == (orig_cr4 | X86_CR4_LA57)); 8308 8309 vmcs_write(HOST_CR4, orig_cr4); 8310 vmcs_write(HOST_CR3, orig_cr3); 8311 enter_guest(); 8312 8313 TEST_ASSERT(vmcs_readm(HOST_CR3) == orig_cr3); 8314 TEST_ASSERT(vmcs_readm(HOST_CR4) == orig_cr4); 8315 8316 /* 8317 * And now do the same LA57 shenanigans with EPT enabled. KVM uses 8318 * two separate MMUs when L1 uses TDP, whereas the above shadow paging 8319 * version shares an MMU between L1 and L2. 8320 * 8321 * If the saved execution controls are non-zero then the EPT version 8322 * has already run. In that case, restore the old controls. If EPT 8323 * setup fails, e.g. EPT isn't supported, fall through and finish up. 8324 */ 8325 if (ctrls[0]) { 8326 vmcs_write(CPU_EXEC_CTRL0, ctrls[0]); 8327 vmcs_write(CPU_EXEC_CTRL1, ctrls[1]); 8328 } else if (!setup_ept(false)) { 8329 ctrls[0] = vmcs_read(CPU_EXEC_CTRL0); 8330 ctrls[1] = vmcs_read(CPU_EXEC_CTRL1); 8331 goto lol_5level; 8332 } 8333 8334 free_page(pml5); 8335 8336 done: 8337 skip_exit_vmcall(); 8338 enter_guest(); 8339 } 8340 8341 static void vmx_cr4_osxsave_test_guest(void) 8342 { 8343 write_cr4(read_cr4() & ~X86_CR4_OSXSAVE); 8344 } 8345 8346 /* 8347 * Ensure that kvm recalculates the L1 guest's CPUID.01H:ECX.OSXSAVE 8348 * after VM-exit from an L2 guest that sets CR4.OSXSAVE to a different 8349 * value than in L1. 8350 */ 8351 static void vmx_cr4_osxsave_test(void) 8352 { 8353 if (!this_cpu_has(X86_FEATURE_XSAVE)) { 8354 report_skip("%s : XSAVE not detected", __func__); 8355 return; 8356 } 8357 8358 if (!(read_cr4() & X86_CR4_OSXSAVE)) { 8359 unsigned long cr4 = read_cr4() | X86_CR4_OSXSAVE; 8360 8361 write_cr4(cr4); 8362 vmcs_write(GUEST_CR4, cr4); 8363 vmcs_write(HOST_CR4, cr4); 8364 } 8365 8366 TEST_ASSERT(this_cpu_has(X86_FEATURE_OSXSAVE)); 8367 8368 test_set_guest(vmx_cr4_osxsave_test_guest); 8369 enter_guest(); 8370 8371 TEST_ASSERT(this_cpu_has(X86_FEATURE_OSXSAVE)); 8372 } 8373 8374 /* 8375 * FNOP with both CR0.TS and CR0.EM clear should not generate #NM, and the L2 8376 * guest should exit normally. 8377 */ 8378 static void vmx_no_nm_test(void) 8379 { 8380 test_set_guest(fnop); 8381 vmcs_write(GUEST_CR0, read_cr0() & ~(X86_CR0_TS | X86_CR0_EM)); 8382 enter_guest(); 8383 } 8384 8385 bool vmx_pending_event_ipi_fired; 8386 static void vmx_pending_event_ipi_isr(isr_regs_t *regs) 8387 { 8388 vmx_pending_event_ipi_fired = true; 8389 eoi(); 8390 } 8391 8392 bool vmx_pending_event_guest_run; 8393 static void vmx_pending_event_guest(void) 8394 { 8395 vmcall(); 8396 vmx_pending_event_guest_run = true; 8397 } 8398 8399 static void vmx_pending_event_test_core(bool guest_hlt) 8400 { 8401 int ipi_vector = 0xf1; 8402 8403 vmx_pending_event_ipi_fired = false; 8404 handle_irq(ipi_vector, vmx_pending_event_ipi_isr); 8405 8406 vmx_pending_event_guest_run = false; 8407 test_set_guest(vmx_pending_event_guest); 8408 8409 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 8410 8411 enter_guest(); 8412 skip_exit_vmcall(); 8413 8414 if (guest_hlt) 8415 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8416 8417 cli(); 8418 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | 8419 APIC_DM_FIXED | ipi_vector, 8420 0); 8421 8422 enter_guest(); 8423 8424 assert_exit_reason(VMX_EXTINT); 8425 report(!vmx_pending_event_guest_run, 8426 "Guest did not run before host received IPI"); 8427 8428 sti_nop_cli(); 8429 report(vmx_pending_event_ipi_fired, 8430 "Got pending interrupt after IRQ enabled"); 8431 8432 if (guest_hlt) 8433 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 8434 8435 enter_guest(); 8436 report(vmx_pending_event_guest_run, 8437 "Guest finished running when no interrupt"); 8438 } 8439 8440 static void vmx_pending_event_test(void) 8441 { 8442 vmx_pending_event_test_core(false); 8443 } 8444 8445 static void vmx_pending_event_hlt_test(void) 8446 { 8447 vmx_pending_event_test_core(true); 8448 } 8449 8450 static int vmx_window_test_db_count; 8451 8452 static void vmx_window_test_db_handler(struct ex_regs *regs) 8453 { 8454 vmx_window_test_db_count++; 8455 } 8456 8457 static void vmx_nmi_window_test_guest(void) 8458 { 8459 handle_exception(DB_VECTOR, vmx_window_test_db_handler); 8460 8461 asm volatile("vmcall\n\t" 8462 "nop\n\t"); 8463 8464 handle_exception(DB_VECTOR, NULL); 8465 } 8466 8467 static void verify_nmi_window_exit(u64 rip) 8468 { 8469 u32 exit_reason = vmcs_read(EXI_REASON); 8470 8471 report(exit_reason == VMX_NMI_WINDOW, 8472 "Exit reason (%d) is 'NMI window'", exit_reason); 8473 report(vmcs_read(GUEST_RIP) == rip, "RIP (%#lx) is %#lx", 8474 vmcs_read(GUEST_RIP), rip); 8475 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 8476 } 8477 8478 static void vmx_nmi_window_test(void) 8479 { 8480 u64 nop_addr; 8481 void *db_fault_addr = get_idt_addr(&boot_idt[DB_VECTOR]); 8482 8483 if (!(ctrl_pin_rev.clr & PIN_VIRT_NMI)) { 8484 report_skip("%s : \"Virtual NMIs\" exec control not supported", __func__); 8485 return; 8486 } 8487 8488 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 8489 report_skip("%s : \"NMI-window exiting\" exec control not supported", __func__); 8490 return; 8491 } 8492 8493 vmx_window_test_db_count = 0; 8494 8495 report_prefix_push("NMI-window"); 8496 test_set_guest(vmx_nmi_window_test_guest); 8497 vmcs_set_bits(PIN_CONTROLS, PIN_VIRT_NMI); 8498 enter_guest(); 8499 skip_exit_vmcall(); 8500 nop_addr = vmcs_read(GUEST_RIP); 8501 8502 /* 8503 * Ask for "NMI-window exiting," and expect an immediate VM-exit. 8504 * RIP will not advance. 8505 */ 8506 report_prefix_push("active, no blocking"); 8507 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 8508 enter_guest(); 8509 verify_nmi_window_exit(nop_addr); 8510 report_prefix_pop(); 8511 8512 /* 8513 * Ask for "NMI-window exiting" in a MOV-SS shadow, and expect 8514 * a VM-exit on the next instruction after the nop. (The nop 8515 * is one byte.) 8516 */ 8517 report_prefix_push("active, blocking by MOV-SS"); 8518 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 8519 enter_guest(); 8520 verify_nmi_window_exit(nop_addr + 1); 8521 report_prefix_pop(); 8522 8523 /* 8524 * Ask for "NMI-window exiting" (with event injection), and 8525 * expect a VM-exit after the event is injected. (RIP should 8526 * be at the address specified in the IDT entry for #DB.) 8527 */ 8528 report_prefix_push("active, no blocking, injecting #DB"); 8529 vmcs_write(ENT_INTR_INFO, 8530 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 8531 enter_guest(); 8532 verify_nmi_window_exit((u64)db_fault_addr); 8533 report_prefix_pop(); 8534 8535 /* 8536 * Ask for "NMI-window exiting" with NMI blocking, and expect 8537 * a VM-exit after the next IRET (i.e. after the #DB handler 8538 * returns). So, RIP should be back at one byte past the nop. 8539 */ 8540 report_prefix_push("active, blocking by NMI"); 8541 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_NMI); 8542 enter_guest(); 8543 verify_nmi_window_exit(nop_addr + 1); 8544 report(vmx_window_test_db_count == 1, 8545 "#DB handler executed once (actual %d times)", 8546 vmx_window_test_db_count); 8547 report_prefix_pop(); 8548 8549 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 8550 report_skip("CPU does not support activity state HLT."); 8551 } else { 8552 /* 8553 * Ask for "NMI-window exiting" when entering activity 8554 * state HLT, and expect an immediate VM-exit. RIP is 8555 * still one byte past the nop. 8556 */ 8557 report_prefix_push("halted, no blocking"); 8558 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8559 enter_guest(); 8560 verify_nmi_window_exit(nop_addr + 1); 8561 report_prefix_pop(); 8562 8563 /* 8564 * Ask for "NMI-window exiting" when entering activity 8565 * state HLT (with event injection), and expect a 8566 * VM-exit after the event is injected. (RIP should be 8567 * at the address specified in the IDT entry for #DB.) 8568 */ 8569 report_prefix_push("halted, no blocking, injecting #DB"); 8570 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8571 vmcs_write(ENT_INTR_INFO, 8572 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 8573 DB_VECTOR); 8574 enter_guest(); 8575 verify_nmi_window_exit((u64)db_fault_addr); 8576 report_prefix_pop(); 8577 } 8578 8579 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 8580 enter_guest(); 8581 report_prefix_pop(); 8582 } 8583 8584 static void vmx_intr_window_test_guest(void) 8585 { 8586 handle_exception(DB_VECTOR, vmx_window_test_db_handler); 8587 8588 /* 8589 * The two consecutive STIs are to ensure that only the first 8590 * one has a shadow. Note that NOP and STI are one byte 8591 * instructions. 8592 */ 8593 asm volatile("vmcall\n\t" 8594 "nop\n\t" 8595 "sti\n\t" 8596 "sti\n\t"); 8597 8598 handle_exception(DB_VECTOR, NULL); 8599 } 8600 8601 static void verify_intr_window_exit(u64 rip) 8602 { 8603 u32 exit_reason = vmcs_read(EXI_REASON); 8604 8605 report(exit_reason == VMX_INTR_WINDOW, 8606 "Exit reason (%d) is 'interrupt window'", exit_reason); 8607 report(vmcs_read(GUEST_RIP) == rip, "RIP (%#lx) is %#lx", 8608 vmcs_read(GUEST_RIP), rip); 8609 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 8610 } 8611 8612 static void vmx_intr_window_test(void) 8613 { 8614 u64 vmcall_addr; 8615 u64 nop_addr; 8616 unsigned int orig_db_gate_type; 8617 void *db_fault_addr = get_idt_addr(&boot_idt[DB_VECTOR]); 8618 8619 if (!(ctrl_cpu_rev[0].clr & CPU_INTR_WINDOW)) { 8620 report_skip("%s : \"Interrupt-window exiting\" exec control not supported", __func__); 8621 return; 8622 } 8623 8624 /* 8625 * Change the IDT entry for #DB from interrupt gate to trap gate, 8626 * so that it won't clear RFLAGS.IF. We don't want interrupts to 8627 * be disabled after vectoring a #DB. 8628 */ 8629 orig_db_gate_type = boot_idt[DB_VECTOR].type; 8630 boot_idt[DB_VECTOR].type = 15; 8631 8632 report_prefix_push("interrupt-window"); 8633 test_set_guest(vmx_intr_window_test_guest); 8634 enter_guest(); 8635 assert_exit_reason(VMX_VMCALL); 8636 vmcall_addr = vmcs_read(GUEST_RIP); 8637 8638 /* 8639 * Ask for "interrupt-window exiting" with RFLAGS.IF set and 8640 * no blocking; expect an immediate VM-exit. Note that we have 8641 * not advanced past the vmcall instruction yet, so RIP should 8642 * point to the vmcall instruction. 8643 */ 8644 report_prefix_push("active, no blocking, RFLAGS.IF=1"); 8645 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8646 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_IF); 8647 enter_guest(); 8648 verify_intr_window_exit(vmcall_addr); 8649 report_prefix_pop(); 8650 8651 /* 8652 * Ask for "interrupt-window exiting" (with event injection) 8653 * with RFLAGS.IF set and no blocking; expect a VM-exit after 8654 * the event is injected. That is, RIP should should be at the 8655 * address specified in the IDT entry for #DB. 8656 */ 8657 report_prefix_push("active, no blocking, RFLAGS.IF=1, injecting #DB"); 8658 vmcs_write(ENT_INTR_INFO, 8659 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 8660 vmcall_addr = vmcs_read(GUEST_RIP); 8661 enter_guest(); 8662 verify_intr_window_exit((u64)db_fault_addr); 8663 report_prefix_pop(); 8664 8665 /* 8666 * Let the L2 guest run through the IRET, back to the VMCALL. 8667 * We have to clear the "interrupt-window exiting" 8668 * VM-execution control, or it would just keep causing 8669 * VM-exits. Then, advance past the VMCALL and set the 8670 * "interrupt-window exiting" VM-execution control again. 8671 */ 8672 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8673 enter_guest(); 8674 skip_exit_vmcall(); 8675 nop_addr = vmcs_read(GUEST_RIP); 8676 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8677 8678 /* 8679 * Ask for "interrupt-window exiting" in a MOV-SS shadow with 8680 * RFLAGS.IF set, and expect a VM-exit on the next 8681 * instruction. (NOP is one byte.) 8682 */ 8683 report_prefix_push("active, blocking by MOV-SS, RFLAGS.IF=1"); 8684 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 8685 enter_guest(); 8686 verify_intr_window_exit(nop_addr + 1); 8687 report_prefix_pop(); 8688 8689 /* 8690 * Back up to the NOP and ask for "interrupt-window exiting" 8691 * in an STI shadow with RFLAGS.IF set, and expect a VM-exit 8692 * on the next instruction. (NOP is one byte.) 8693 */ 8694 report_prefix_push("active, blocking by STI, RFLAGS.IF=1"); 8695 vmcs_write(GUEST_RIP, nop_addr); 8696 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_STI); 8697 enter_guest(); 8698 verify_intr_window_exit(nop_addr + 1); 8699 report_prefix_pop(); 8700 8701 /* 8702 * Ask for "interrupt-window exiting" with RFLAGS.IF clear, 8703 * and expect a VM-exit on the instruction following the STI 8704 * shadow. Only the first STI (which is one byte past the NOP) 8705 * should have a shadow. The second STI (which is two bytes 8706 * past the NOP) has no shadow. Therefore, the interrupt 8707 * window opens at three bytes past the NOP. 8708 */ 8709 report_prefix_push("active, RFLAGS.IF = 0"); 8710 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 8711 enter_guest(); 8712 verify_intr_window_exit(nop_addr + 3); 8713 report_prefix_pop(); 8714 8715 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 8716 report_skip("CPU does not support activity state HLT."); 8717 } else { 8718 /* 8719 * Ask for "interrupt-window exiting" when entering 8720 * activity state HLT, and expect an immediate 8721 * VM-exit. RIP is still three bytes past the nop. 8722 */ 8723 report_prefix_push("halted, no blocking"); 8724 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8725 enter_guest(); 8726 verify_intr_window_exit(nop_addr + 3); 8727 report_prefix_pop(); 8728 8729 /* 8730 * Ask for "interrupt-window exiting" when entering 8731 * activity state HLT (with event injection), and 8732 * expect a VM-exit after the event is injected. That 8733 * is, RIP should should be at the address specified 8734 * in the IDT entry for #DB. 8735 */ 8736 report_prefix_push("halted, no blocking, injecting #DB"); 8737 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8738 vmcs_write(ENT_INTR_INFO, 8739 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 8740 DB_VECTOR); 8741 enter_guest(); 8742 verify_intr_window_exit((u64)db_fault_addr); 8743 report_prefix_pop(); 8744 } 8745 8746 boot_idt[DB_VECTOR].type = orig_db_gate_type; 8747 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8748 enter_guest(); 8749 report_prefix_pop(); 8750 } 8751 8752 #define GUEST_TSC_OFFSET (1u << 30) 8753 8754 static u64 guest_tsc; 8755 8756 static void vmx_store_tsc_test_guest(void) 8757 { 8758 guest_tsc = rdtsc(); 8759 } 8760 8761 /* 8762 * This test ensures that when IA32_TSC is in the VM-exit MSR-store 8763 * list, the value saved is not subject to the TSC offset that is 8764 * applied to RDTSC/RDTSCP/RDMSR(IA32_TSC) in guest execution. 8765 */ 8766 static void vmx_store_tsc_test(void) 8767 { 8768 struct vmx_msr_entry msr_entry = { .index = MSR_IA32_TSC }; 8769 u64 low, high; 8770 8771 if (!(ctrl_cpu_rev[0].clr & CPU_USE_TSC_OFFSET)) { 8772 report_skip("%s : \"Use TSC offsetting\" exec control not supported", __func__); 8773 return; 8774 } 8775 8776 test_set_guest(vmx_store_tsc_test_guest); 8777 8778 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_USE_TSC_OFFSET); 8779 vmcs_write(EXI_MSR_ST_CNT, 1); 8780 vmcs_write(EXIT_MSR_ST_ADDR, virt_to_phys(&msr_entry)); 8781 vmcs_write(TSC_OFFSET, GUEST_TSC_OFFSET); 8782 8783 low = rdtsc(); 8784 enter_guest(); 8785 high = rdtsc(); 8786 8787 report(low + GUEST_TSC_OFFSET <= guest_tsc && 8788 guest_tsc <= high + GUEST_TSC_OFFSET, 8789 "RDTSC value in the guest (%lu) is in range [%lu, %lu]", 8790 guest_tsc, low + GUEST_TSC_OFFSET, high + GUEST_TSC_OFFSET); 8791 report(low <= msr_entry.value && msr_entry.value <= high, 8792 "IA32_TSC value saved in the VM-exit MSR-store list (%lu) is in range [%lu, %lu]", 8793 msr_entry.value, low, high); 8794 } 8795 8796 static void vmx_preemption_timer_zero_test_db_handler(struct ex_regs *regs) 8797 { 8798 } 8799 8800 static void vmx_preemption_timer_zero_test_guest(void) 8801 { 8802 while (vmx_get_test_stage() < 3) 8803 vmcall(); 8804 } 8805 8806 static void vmx_preemption_timer_zero_activate_preemption_timer(void) 8807 { 8808 vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT); 8809 vmcs_write(PREEMPT_TIMER_VALUE, 0); 8810 } 8811 8812 static void vmx_preemption_timer_zero_advance_past_vmcall(void) 8813 { 8814 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 8815 enter_guest(); 8816 skip_exit_vmcall(); 8817 } 8818 8819 static void vmx_preemption_timer_zero_inject_db(bool intercept_db) 8820 { 8821 vmx_preemption_timer_zero_activate_preemption_timer(); 8822 vmcs_write(ENT_INTR_INFO, INTR_INFO_VALID_MASK | 8823 INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 8824 vmcs_write(EXC_BITMAP, intercept_db ? 1 << DB_VECTOR : 0); 8825 enter_guest(); 8826 } 8827 8828 static void vmx_preemption_timer_zero_set_pending_dbg(u32 exception_bitmap) 8829 { 8830 vmx_preemption_timer_zero_activate_preemption_timer(); 8831 vmcs_write(GUEST_PENDING_DEBUG, PENDING_DBG_TRAP | DR6_TRAP1); 8832 vmcs_write(EXC_BITMAP, exception_bitmap); 8833 enter_guest(); 8834 } 8835 8836 static void vmx_preemption_timer_zero_expect_preempt_at_rip(u64 expected_rip) 8837 { 8838 u32 reason = (u32)vmcs_read(EXI_REASON); 8839 u64 guest_rip = vmcs_read(GUEST_RIP); 8840 8841 report(reason == VMX_PREEMPT && guest_rip == expected_rip, 8842 "Exit reason is 0x%x (expected 0x%x) and guest RIP is %lx (0x%lx expected).", 8843 reason, VMX_PREEMPT, guest_rip, expected_rip); 8844 } 8845 8846 /* 8847 * This test ensures that when the VMX preemption timer is zero at 8848 * VM-entry, a VM-exit occurs after any event injection and after any 8849 * pending debug exceptions are raised, but before execution of any 8850 * guest instructions. 8851 */ 8852 static void vmx_preemption_timer_zero_test(void) 8853 { 8854 u64 db_fault_address = (u64)get_idt_addr(&boot_idt[DB_VECTOR]); 8855 handler old_db; 8856 u32 reason; 8857 8858 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 8859 report_skip("%s : \"Activate VMX-preemption timer\" pin control not supported", __func__); 8860 return; 8861 } 8862 8863 /* 8864 * Install a custom #DB handler that doesn't abort. 8865 */ 8866 old_db = handle_exception(DB_VECTOR, 8867 vmx_preemption_timer_zero_test_db_handler); 8868 8869 test_set_guest(vmx_preemption_timer_zero_test_guest); 8870 8871 /* 8872 * VMX-preemption timer should fire after event injection. 8873 */ 8874 vmx_set_test_stage(0); 8875 vmx_preemption_timer_zero_inject_db(0); 8876 vmx_preemption_timer_zero_expect_preempt_at_rip(db_fault_address); 8877 vmx_preemption_timer_zero_advance_past_vmcall(); 8878 8879 /* 8880 * VMX-preemption timer should fire after event injection. 8881 * Exception bitmap is irrelevant, since you can't intercept 8882 * an event that you injected. 8883 */ 8884 vmx_set_test_stage(1); 8885 vmx_preemption_timer_zero_inject_db(true); 8886 vmx_preemption_timer_zero_expect_preempt_at_rip(db_fault_address); 8887 vmx_preemption_timer_zero_advance_past_vmcall(); 8888 8889 /* 8890 * VMX-preemption timer should fire after pending debug exceptions 8891 * have delivered a #DB trap. 8892 */ 8893 vmx_set_test_stage(2); 8894 vmx_preemption_timer_zero_set_pending_dbg(0); 8895 vmx_preemption_timer_zero_expect_preempt_at_rip(db_fault_address); 8896 vmx_preemption_timer_zero_advance_past_vmcall(); 8897 8898 /* 8899 * VMX-preemption timer would fire after pending debug exceptions 8900 * have delivered a #DB trap, but in this case, the #DB trap is 8901 * intercepted. 8902 */ 8903 vmx_set_test_stage(3); 8904 vmx_preemption_timer_zero_set_pending_dbg(1 << DB_VECTOR); 8905 reason = (u32)vmcs_read(EXI_REASON); 8906 report(reason == VMX_EXC_NMI, "Exit reason is 0x%x (expected 0x%x)", 8907 reason, VMX_EXC_NMI); 8908 8909 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 8910 enter_guest(); 8911 8912 handle_exception(DB_VECTOR, old_db); 8913 } 8914 8915 static u64 vmx_preemption_timer_tf_test_prev_rip; 8916 8917 static void vmx_preemption_timer_tf_test_db_handler(struct ex_regs *regs) 8918 { 8919 extern char vmx_preemption_timer_tf_test_endloop; 8920 8921 if (vmx_get_test_stage() == 2) { 8922 /* 8923 * Stage 2 means that we're done, one way or another. 8924 * Arrange for the iret to drop us out of the wbinvd 8925 * loop and stop single-stepping. 8926 */ 8927 regs->rip = (u64)&vmx_preemption_timer_tf_test_endloop; 8928 regs->rflags &= ~X86_EFLAGS_TF; 8929 } else if (regs->rip == vmx_preemption_timer_tf_test_prev_rip) { 8930 /* 8931 * The RIP should alternate between the wbinvd and the 8932 * jmp instruction in the code below. If we ever see 8933 * the same instruction twice in a row, that means a 8934 * single-step trap has been dropped. Let the 8935 * hypervisor know about the failure by executing a 8936 * VMCALL. 8937 */ 8938 vmcall(); 8939 } 8940 vmx_preemption_timer_tf_test_prev_rip = regs->rip; 8941 } 8942 8943 static void vmx_preemption_timer_tf_test_guest(void) 8944 { 8945 /* 8946 * The hypervisor doesn't intercept WBINVD, so the loop below 8947 * shouldn't be a problem--it's just two instructions 8948 * executing in VMX non-root mode. However, when the 8949 * hypervisor is running in a virtual environment, the parent 8950 * hypervisor might intercept WBINVD and emulate it. If the 8951 * parent hypervisor is broken, the single-step trap after the 8952 * WBINVD might be lost. 8953 */ 8954 asm volatile("vmcall\n\t" 8955 "0: wbinvd\n\t" 8956 "1: jmp 0b\n\t" 8957 "vmx_preemption_timer_tf_test_endloop:"); 8958 } 8959 8960 /* 8961 * Ensure that the delivery of a "VMX-preemption timer expired" 8962 * VM-exit doesn't disrupt single-stepping in the guest. Note that 8963 * passing this test doesn't ensure correctness, because the test will 8964 * only fail if the VMX-preemtion timer fires at the right time (or 8965 * the wrong time, as it were). 8966 */ 8967 static void vmx_preemption_timer_tf_test(void) 8968 { 8969 handler old_db; 8970 u32 reason; 8971 int i; 8972 8973 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 8974 report_skip("%s : \"Activate VMX-preemption timer\" pin control not supported", __func__); 8975 return; 8976 } 8977 8978 old_db = handle_exception(DB_VECTOR, 8979 vmx_preemption_timer_tf_test_db_handler); 8980 8981 test_set_guest(vmx_preemption_timer_tf_test_guest); 8982 8983 enter_guest(); 8984 skip_exit_vmcall(); 8985 8986 vmx_set_test_stage(1); 8987 vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT); 8988 vmcs_write(PREEMPT_TIMER_VALUE, 50000); 8989 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_TF); 8990 8991 /* 8992 * The only exit we should see is "VMX-preemption timer 8993 * expired." If we get a VMCALL exit, that means the #DB 8994 * handler has detected a missing single-step trap. It doesn't 8995 * matter where the guest RIP is when the VMX-preemption timer 8996 * expires (whether it's in the WBINVD loop or in the #DB 8997 * handler)--a single-step trap should never be discarded. 8998 */ 8999 for (i = 0; i < 10000; i++) { 9000 enter_guest(); 9001 reason = (u32)vmcs_read(EXI_REASON); 9002 if (reason == VMX_PREEMPT) 9003 continue; 9004 TEST_ASSERT(reason == VMX_VMCALL); 9005 skip_exit_insn(); 9006 break; 9007 } 9008 9009 report(reason == VMX_PREEMPT, "No single-step traps skipped"); 9010 9011 vmx_set_test_stage(2); 9012 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 9013 enter_guest(); 9014 9015 handle_exception(DB_VECTOR, old_db); 9016 } 9017 9018 #define VMX_PREEMPTION_TIMER_EXPIRY_CYCLES 1000000 9019 9020 static u64 vmx_preemption_timer_expiry_start; 9021 static u64 vmx_preemption_timer_expiry_finish; 9022 9023 static void vmx_preemption_timer_expiry_test_guest(void) 9024 { 9025 vmcall(); 9026 vmx_preemption_timer_expiry_start = fenced_rdtsc(); 9027 9028 while (vmx_get_test_stage() == 0) 9029 vmx_preemption_timer_expiry_finish = fenced_rdtsc(); 9030 } 9031 9032 /* 9033 * Test that the VMX-preemption timer is not excessively delayed. 9034 * 9035 * Per the SDM, volume 3, VM-entry starts the VMX-preemption timer 9036 * with the unsigned value in the VMX-preemption timer-value field, 9037 * and the VMX-preemption timer counts down by 1 every time bit X in 9038 * the TSC changes due to a TSC increment (where X is 9039 * IA32_VMX_MISC[4:0]). If the timer counts down to zero in any state 9040 * other than the wait-for-SIPI state, the logical processor 9041 * transitions to the C0 C-state and causes a VM-exit. 9042 * 9043 * The guest code above reads the starting TSC after VM-entry. At this 9044 * point, the VMX-preemption timer has already been activated. Next, 9045 * the guest code reads the current TSC in a loop, storing the value 9046 * read to memory. 9047 * 9048 * If the RDTSC in the loop reads a value past the VMX-preemption 9049 * timer deadline, then the VMX-preemption timer VM-exit must be 9050 * delivered before the next instruction retires. Even if a higher 9051 * priority SMI is delivered first, the VMX-preemption timer VM-exit 9052 * must be delivered before the next instruction retires. Hence, a TSC 9053 * value past the VMX-preemption timer deadline might be read, but it 9054 * cannot be stored. If a TSC value past the deadline *is* stored, 9055 * then the architectural specification has been violated. 9056 */ 9057 static void vmx_preemption_timer_expiry_test(void) 9058 { 9059 u32 preemption_timer_value; 9060 union vmx_misc misc; 9061 u64 tsc_deadline; 9062 u32 reason; 9063 9064 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 9065 report_skip("%s : \"Activate VMX-preemption timer\" pin control not supported", __func__); 9066 return; 9067 } 9068 9069 test_set_guest(vmx_preemption_timer_expiry_test_guest); 9070 9071 enter_guest(); 9072 skip_exit_vmcall(); 9073 9074 misc.val = rdmsr(MSR_IA32_VMX_MISC); 9075 preemption_timer_value = 9076 VMX_PREEMPTION_TIMER_EXPIRY_CYCLES >> misc.pt_bit; 9077 9078 vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT); 9079 vmcs_write(PREEMPT_TIMER_VALUE, preemption_timer_value); 9080 vmx_set_test_stage(0); 9081 9082 enter_guest(); 9083 reason = (u32)vmcs_read(EXI_REASON); 9084 TEST_ASSERT(reason == VMX_PREEMPT); 9085 9086 tsc_deadline = ((vmx_preemption_timer_expiry_start >> misc.pt_bit) << 9087 misc.pt_bit) + (preemption_timer_value << misc.pt_bit); 9088 9089 report(vmx_preemption_timer_expiry_finish < tsc_deadline, 9090 "Last stored guest TSC (%lu) < TSC deadline (%lu)", 9091 vmx_preemption_timer_expiry_finish, tsc_deadline); 9092 9093 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 9094 vmx_set_test_stage(1); 9095 enter_guest(); 9096 } 9097 9098 static void vmx_db_test_guest(void) 9099 { 9100 /* 9101 * For a hardware generated single-step #DB. 9102 */ 9103 asm volatile("vmcall;" 9104 "nop;" 9105 ".Lpost_nop:"); 9106 /* 9107 * ...in a MOVSS shadow, with pending debug exceptions. 9108 */ 9109 asm volatile("vmcall;" 9110 "nop;" 9111 ".Lpost_movss_nop:"); 9112 /* 9113 * For an L0 synthesized single-step #DB. (L0 intercepts WBINVD and 9114 * emulates it in software.) 9115 */ 9116 asm volatile("vmcall;" 9117 "wbinvd;" 9118 ".Lpost_wbinvd:"); 9119 /* 9120 * ...in a MOVSS shadow, with pending debug exceptions. 9121 */ 9122 asm volatile("vmcall;" 9123 "wbinvd;" 9124 ".Lpost_movss_wbinvd:"); 9125 /* 9126 * For a hardware generated single-step #DB in a transactional region. 9127 */ 9128 asm volatile("vmcall;" 9129 ".Lxbegin: xbegin .Lskip_rtm;" 9130 "xend;" 9131 ".Lskip_rtm:"); 9132 } 9133 9134 /* 9135 * Clear the pending debug exceptions and RFLAGS.TF and re-enter 9136 * L2. No #DB is delivered and L2 continues to the next point of 9137 * interest. 9138 */ 9139 static void dismiss_db(void) 9140 { 9141 vmcs_write(GUEST_PENDING_DEBUG, 0); 9142 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 9143 enter_guest(); 9144 } 9145 9146 /* 9147 * Check a variety of VMCS fields relevant to an intercepted #DB exception. 9148 * Then throw away the #DB exception and resume L2. 9149 */ 9150 static void check_db_exit(bool xfail_qual, bool xfail_dr6, bool xfail_pdbg, 9151 void *expected_rip, u64 expected_exit_qual, 9152 u64 expected_dr6) 9153 { 9154 u32 reason = vmcs_read(EXI_REASON); 9155 u32 intr_info = vmcs_read(EXI_INTR_INFO); 9156 u64 exit_qual = vmcs_read(EXI_QUALIFICATION); 9157 u64 guest_rip = vmcs_read(GUEST_RIP); 9158 u64 guest_pending_dbg = vmcs_read(GUEST_PENDING_DEBUG); 9159 u64 dr6 = read_dr6(); 9160 const u32 expected_intr_info = INTR_INFO_VALID_MASK | 9161 INTR_TYPE_HARD_EXCEPTION | DB_VECTOR; 9162 9163 report(reason == VMX_EXC_NMI && intr_info == expected_intr_info, 9164 "Expected #DB VM-exit"); 9165 report((u64)expected_rip == guest_rip, "Expected RIP %p (actual %lx)", 9166 expected_rip, guest_rip); 9167 report_xfail(xfail_pdbg, 0 == guest_pending_dbg, 9168 "Expected pending debug exceptions 0 (actual %lx)", 9169 guest_pending_dbg); 9170 report_xfail(xfail_qual, expected_exit_qual == exit_qual, 9171 "Expected exit qualification %lx (actual %lx)", 9172 expected_exit_qual, exit_qual); 9173 report_xfail(xfail_dr6, expected_dr6 == dr6, 9174 "Expected DR6 %lx (actual %lx)", expected_dr6, dr6); 9175 dismiss_db(); 9176 } 9177 9178 /* 9179 * Assuming the guest has just exited on a VMCALL instruction, skip 9180 * over the vmcall, and set the guest's RFLAGS.TF in the VMCS. If 9181 * pending debug exceptions are non-zero, set the VMCS up as if the 9182 * previous instruction was a MOVSS that generated the indicated 9183 * pending debug exceptions. Then enter L2. 9184 */ 9185 static void single_step_guest(const char *test_name, u64 starting_dr6, 9186 u64 pending_debug_exceptions) 9187 { 9188 printf("\n%s\n", test_name); 9189 skip_exit_vmcall(); 9190 write_dr6(starting_dr6); 9191 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_TF); 9192 if (pending_debug_exceptions) { 9193 vmcs_write(GUEST_PENDING_DEBUG, pending_debug_exceptions); 9194 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 9195 } 9196 enter_guest(); 9197 } 9198 9199 /* 9200 * When L1 intercepts #DB, verify that a single-step trap clears 9201 * pending debug exceptions, populates the exit qualification field 9202 * properly, and that DR6 is not prematurely clobbered. In a 9203 * (simulated) MOVSS shadow, make sure that the pending debug 9204 * exception bits are properly accumulated into the exit qualification 9205 * field. 9206 */ 9207 static void vmx_db_test(void) 9208 { 9209 /* 9210 * We are going to set a few arbitrary bits in DR6 to verify that 9211 * (a) DR6 is not modified by an intercepted #DB, and 9212 * (b) stale bits in DR6 (DR6.BD, in particular) don't leak into 9213 * the exit qualification field for a subsequent #DB exception. 9214 */ 9215 const u64 starting_dr6 = DR6_ACTIVE_LOW | DR6_BS | DR6_TRAP3 | DR6_TRAP1; 9216 extern char post_nop asm(".Lpost_nop"); 9217 extern char post_movss_nop asm(".Lpost_movss_nop"); 9218 extern char post_wbinvd asm(".Lpost_wbinvd"); 9219 extern char post_movss_wbinvd asm(".Lpost_movss_wbinvd"); 9220 extern char xbegin asm(".Lxbegin"); 9221 extern char skip_rtm asm(".Lskip_rtm"); 9222 9223 /* 9224 * L1 wants to intercept #DB exceptions encountered in L2. 9225 */ 9226 vmcs_write(EXC_BITMAP, BIT(DB_VECTOR)); 9227 9228 /* 9229 * Start L2 and run it up to the first point of interest. 9230 */ 9231 test_set_guest(vmx_db_test_guest); 9232 enter_guest(); 9233 9234 /* 9235 * Hardware-delivered #DB trap for single-step sets the 9236 * standard that L0 has to follow for emulated instructions. 9237 */ 9238 single_step_guest("Hardware delivered single-step", starting_dr6, 0); 9239 check_db_exit(false, false, false, &post_nop, DR6_BS, starting_dr6); 9240 9241 /* 9242 * Hardware-delivered #DB trap for single-step in MOVSS shadow 9243 * also sets the standard that L0 has to follow for emulated 9244 * instructions. Here, we establish the VMCS pending debug 9245 * exceptions to indicate that the simulated MOVSS triggered a 9246 * data breakpoint as well as the single-step trap. 9247 */ 9248 single_step_guest("Hardware delivered single-step in MOVSS shadow", 9249 starting_dr6, DR6_BS | PENDING_DBG_TRAP | DR6_TRAP0); 9250 check_db_exit(false, false, false, &post_movss_nop, DR6_BS | DR6_TRAP0, 9251 starting_dr6); 9252 9253 /* 9254 * L0 synthesized #DB trap for single-step is buggy, because 9255 * kvm (a) clobbers DR6 too early, and (b) tries its best to 9256 * reconstitute the exit qualification from the prematurely 9257 * modified DR6, but fails miserably. 9258 */ 9259 single_step_guest("Software synthesized single-step", starting_dr6, 0); 9260 check_db_exit(false, false, false, &post_wbinvd, DR6_BS, starting_dr6); 9261 9262 /* 9263 * L0 synthesized #DB trap for single-step in MOVSS shadow is 9264 * even worse, because L0 also leaves the pending debug 9265 * exceptions in the VMCS instead of accumulating them into 9266 * the exit qualification field for the #DB exception. 9267 */ 9268 single_step_guest("Software synthesized single-step in MOVSS shadow", 9269 starting_dr6, DR6_BS | PENDING_DBG_TRAP | DR6_TRAP0); 9270 check_db_exit(true, false, true, &post_movss_wbinvd, DR6_BS | DR6_TRAP0, 9271 starting_dr6); 9272 9273 /* 9274 * Optional RTM test for hardware that supports RTM, to 9275 * demonstrate that the current volume 3 of the SDM 9276 * (325384-067US), table 27-1 is incorrect. Bit 16 of the exit 9277 * qualification for debug exceptions is not reserved. It is 9278 * set to 1 if a debug exception (#DB) or a breakpoint 9279 * exception (#BP) occurs inside an RTM region while advanced 9280 * debugging of RTM transactional regions is enabled. 9281 */ 9282 if (this_cpu_has(X86_FEATURE_RTM)) { 9283 vmcs_write(ENT_CONTROLS, 9284 vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 9285 /* 9286 * Set DR7.RTM[bit 11] and IA32_DEBUGCTL.RTM[bit 15] 9287 * in the guest to enable advanced debugging of RTM 9288 * transactional regions. 9289 */ 9290 vmcs_write(GUEST_DR7, BIT(11)); 9291 vmcs_write(GUEST_DEBUGCTL, BIT(15)); 9292 single_step_guest("Hardware delivered single-step in " 9293 "transactional region", starting_dr6, 0); 9294 check_db_exit(false, false, false, &xbegin, BIT(16), 9295 starting_dr6); 9296 } else { 9297 vmcs_write(GUEST_RIP, (u64)&skip_rtm); 9298 enter_guest(); 9299 } 9300 } 9301 9302 static void enable_vid(void) 9303 { 9304 void *virtual_apic_page; 9305 9306 assert(cpu_has_apicv()); 9307 9308 disable_intercept_for_x2apic_msrs(); 9309 9310 virtual_apic_page = alloc_page(); 9311 vmcs_write(APIC_VIRT_ADDR, (u64)virtual_apic_page); 9312 9313 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 9314 9315 vmcs_write(EOI_EXIT_BITMAP0, 0x0); 9316 vmcs_write(EOI_EXIT_BITMAP1, 0x0); 9317 vmcs_write(EOI_EXIT_BITMAP2, 0x0); 9318 vmcs_write(EOI_EXIT_BITMAP3, 0x0); 9319 9320 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY | CPU_TPR_SHADOW); 9321 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_VINTD | CPU_VIRT_X2APIC); 9322 } 9323 9324 static void trigger_ioapic_scan_thread(void *data) 9325 { 9326 /* Wait until other CPU entered L2 */ 9327 while (vmx_get_test_stage() != 1) 9328 ; 9329 9330 /* Trigger ioapic scan */ 9331 ioapic_set_redir(0xf, 0x79, TRIGGER_LEVEL); 9332 vmx_set_test_stage(2); 9333 } 9334 9335 static void irq_79_handler_guest(isr_regs_t *regs) 9336 { 9337 eoi(); 9338 9339 /* L1 expects vmexit on VMX_VMCALL and not VMX_EOI_INDUCED */ 9340 vmcall(); 9341 } 9342 9343 /* 9344 * Constant for num of busy-loop iterations after which 9345 * a timer interrupt should have happened in host 9346 */ 9347 #define TIMER_INTERRUPT_DELAY 100000000 9348 9349 static void vmx_eoi_bitmap_ioapic_scan_test_guest(void) 9350 { 9351 handle_irq(0x79, irq_79_handler_guest); 9352 sti(); 9353 9354 /* Signal to L1 CPU to trigger ioapic scan */ 9355 vmx_set_test_stage(1); 9356 /* Wait until L1 CPU to trigger ioapic scan */ 9357 while (vmx_get_test_stage() != 2) 9358 ; 9359 9360 /* 9361 * Wait for L0 timer interrupt to be raised while we run in L2 9362 * such that L0 will process the IOAPIC scan request before 9363 * resuming L2 9364 */ 9365 delay(TIMER_INTERRUPT_DELAY); 9366 9367 asm volatile ("int $0x79"); 9368 } 9369 9370 static void vmx_eoi_bitmap_ioapic_scan_test(void) 9371 { 9372 if (!cpu_has_apicv() || (cpu_count() < 2)) { 9373 report_skip("%s : Not all required APICv bits supported or CPU count < 2", __func__); 9374 return; 9375 } 9376 9377 enable_vid(); 9378 9379 on_cpu_async(1, trigger_ioapic_scan_thread, NULL); 9380 test_set_guest(vmx_eoi_bitmap_ioapic_scan_test_guest); 9381 9382 /* 9383 * Launch L2. 9384 * We expect the exit reason to be VMX_VMCALL (and not EOI INDUCED). 9385 * In case the reason isn't VMX_VMCALL, the assertion inside 9386 * skip_exit_vmcall() will fail. 9387 */ 9388 enter_guest(); 9389 skip_exit_vmcall(); 9390 9391 /* Let L2 finish */ 9392 enter_guest(); 9393 report_pass(__func__); 9394 } 9395 9396 #define HLT_WITH_RVI_VECTOR (0xf1) 9397 9398 bool vmx_hlt_with_rvi_guest_isr_fired; 9399 static void vmx_hlt_with_rvi_guest_isr(isr_regs_t *regs) 9400 { 9401 vmx_hlt_with_rvi_guest_isr_fired = true; 9402 eoi(); 9403 } 9404 9405 static void vmx_hlt_with_rvi_guest(void) 9406 { 9407 handle_irq(HLT_WITH_RVI_VECTOR, vmx_hlt_with_rvi_guest_isr); 9408 9409 sti_nop(); 9410 asm volatile ("nop"); 9411 9412 vmcall(); 9413 } 9414 9415 static void vmx_hlt_with_rvi_test(void) 9416 { 9417 if (!cpu_has_apicv()) { 9418 report_skip("%s : Not all required APICv bits supported", __func__); 9419 return; 9420 } 9421 9422 enable_vid(); 9423 9424 vmx_hlt_with_rvi_guest_isr_fired = false; 9425 test_set_guest(vmx_hlt_with_rvi_guest); 9426 9427 enter_guest(); 9428 skip_exit_vmcall(); 9429 9430 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 9431 vmcs_write(GUEST_INT_STATUS, HLT_WITH_RVI_VECTOR); 9432 enter_guest(); 9433 9434 report(vmx_hlt_with_rvi_guest_isr_fired, "Interrupt raised in guest"); 9435 } 9436 9437 static void set_irq_line_thread(void *data) 9438 { 9439 /* Wait until other CPU entered L2 */ 9440 while (vmx_get_test_stage() != 1) 9441 ; 9442 9443 /* Set irq-line 0xf to raise vector 0x78 for vCPU 0 */ 9444 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 9445 vmx_set_test_stage(2); 9446 } 9447 9448 static bool irq_78_handler_vmcall_before_eoi; 9449 static void irq_78_handler_guest(isr_regs_t *regs) 9450 { 9451 set_irq_line(0xf, 0); 9452 if (irq_78_handler_vmcall_before_eoi) 9453 vmcall(); 9454 eoi(); 9455 vmcall(); 9456 } 9457 9458 static void vmx_apic_passthrough_guest(void) 9459 { 9460 handle_irq(0x78, irq_78_handler_guest); 9461 sti(); 9462 9463 /* If requested, wait for other CPU to trigger ioapic scan */ 9464 if (vmx_get_test_stage() < 1) { 9465 vmx_set_test_stage(1); 9466 while (vmx_get_test_stage() != 2) 9467 ; 9468 } 9469 9470 set_irq_line(0xf, 1); 9471 } 9472 9473 static void vmx_apic_passthrough(bool set_irq_line_from_thread) 9474 { 9475 if (set_irq_line_from_thread && (cpu_count() < 2)) { 9476 report_skip("%s : CPU count < 2", __func__); 9477 return; 9478 } 9479 9480 /* Test device is required for generating IRQs */ 9481 if (!test_device_enabled()) { 9482 report_skip("%s : No test device enabled", __func__); 9483 return; 9484 } 9485 u64 cpu_ctrl_0 = CPU_SECONDARY; 9486 u64 cpu_ctrl_1 = 0; 9487 9488 disable_intercept_for_x2apic_msrs(); 9489 9490 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 9491 9492 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 9493 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 9494 9495 if (set_irq_line_from_thread) { 9496 irq_78_handler_vmcall_before_eoi = false; 9497 on_cpu_async(1, set_irq_line_thread, NULL); 9498 } else { 9499 irq_78_handler_vmcall_before_eoi = true; 9500 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 9501 vmx_set_test_stage(2); 9502 } 9503 test_set_guest(vmx_apic_passthrough_guest); 9504 9505 if (irq_78_handler_vmcall_before_eoi) { 9506 /* Before EOI remote_irr should still be set */ 9507 enter_guest(); 9508 skip_exit_vmcall(); 9509 TEST_ASSERT_EQ_MSG(1, (int)ioapic_read_redir(0xf).remote_irr, 9510 "IOAPIC pass-through: remote_irr=1 before EOI"); 9511 } 9512 9513 /* After EOI remote_irr should be cleared */ 9514 enter_guest(); 9515 skip_exit_vmcall(); 9516 TEST_ASSERT_EQ_MSG(0, (int)ioapic_read_redir(0xf).remote_irr, 9517 "IOAPIC pass-through: remote_irr=0 after EOI"); 9518 9519 /* Let L2 finish */ 9520 enter_guest(); 9521 report_pass(__func__); 9522 } 9523 9524 static void vmx_apic_passthrough_test(void) 9525 { 9526 vmx_apic_passthrough(false); 9527 } 9528 9529 static void vmx_apic_passthrough_thread_test(void) 9530 { 9531 vmx_apic_passthrough(true); 9532 } 9533 9534 static void vmx_apic_passthrough_tpr_threshold_guest(void) 9535 { 9536 cli(); 9537 apic_set_tpr(0); 9538 } 9539 9540 static bool vmx_apic_passthrough_tpr_threshold_ipi_isr_fired; 9541 static void vmx_apic_passthrough_tpr_threshold_ipi_isr(isr_regs_t *regs) 9542 { 9543 vmx_apic_passthrough_tpr_threshold_ipi_isr_fired = true; 9544 eoi(); 9545 } 9546 9547 static void vmx_apic_passthrough_tpr_threshold_test(void) 9548 { 9549 int ipi_vector = 0xe1; 9550 9551 disable_intercept_for_x2apic_msrs(); 9552 vmcs_clear_bits(PIN_CONTROLS, PIN_EXTINT); 9553 9554 /* Raise L0 TPR-threshold by queueing vector in LAPIC IRR */ 9555 cli(); 9556 apic_set_tpr((ipi_vector >> 4) + 1); 9557 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | 9558 APIC_DM_FIXED | ipi_vector, 9559 0); 9560 9561 test_set_guest(vmx_apic_passthrough_tpr_threshold_guest); 9562 enter_guest(); 9563 9564 report(apic_get_tpr() == 0, "TPR was zero by guest"); 9565 9566 /* Clean pending self-IPI */ 9567 vmx_apic_passthrough_tpr_threshold_ipi_isr_fired = false; 9568 handle_irq(ipi_vector, vmx_apic_passthrough_tpr_threshold_ipi_isr); 9569 sti_nop(); 9570 report(vmx_apic_passthrough_tpr_threshold_ipi_isr_fired, "self-IPI fired"); 9571 9572 report_pass(__func__); 9573 } 9574 9575 static u64 init_signal_test_exit_reason; 9576 static bool init_signal_test_thread_continued; 9577 9578 static void init_signal_test_thread(void *data) 9579 { 9580 struct vmcs *test_vmcs = data; 9581 9582 /* Enter VMX operation (i.e. exec VMXON) */ 9583 u64 *ap_vmxon_region = alloc_page(); 9584 enable_vmx(); 9585 init_vmx(ap_vmxon_region); 9586 TEST_ASSERT(!__vmxon_safe(ap_vmxon_region)); 9587 9588 /* Signal CPU have entered VMX operation */ 9589 vmx_set_test_stage(1); 9590 9591 /* Wait for BSP CPU to send INIT signal */ 9592 while (vmx_get_test_stage() != 2) 9593 ; 9594 9595 /* 9596 * Signal that we continue as usual as INIT signal 9597 * should be blocked while CPU is in VMX operation 9598 */ 9599 vmx_set_test_stage(3); 9600 9601 /* Wait for signal to enter VMX non-root mode */ 9602 while (vmx_get_test_stage() != 4) 9603 ; 9604 9605 /* Enter VMX non-root mode */ 9606 test_set_guest(v2_null_test_guest); 9607 make_vmcs_current(test_vmcs); 9608 enter_guest(); 9609 /* Save exit reason for BSP CPU to compare to expected result */ 9610 init_signal_test_exit_reason = vmcs_read(EXI_REASON); 9611 /* VMCLEAR test-vmcs so it could be loaded by BSP CPU */ 9612 vmcs_clear(test_vmcs); 9613 launched = false; 9614 /* Signal that CPU exited to VMX root mode */ 9615 vmx_set_test_stage(5); 9616 9617 /* Wait for BSP CPU to signal to exit VMX operation */ 9618 while (vmx_get_test_stage() != 6) 9619 ; 9620 9621 /* Exit VMX operation (i.e. exec VMXOFF) */ 9622 vmx_off(); 9623 9624 /* 9625 * Signal to BSP CPU that we continue as usual as INIT signal 9626 * should have been consumed by VMX_INIT exit from guest 9627 */ 9628 vmx_set_test_stage(7); 9629 9630 /* Wait for BSP CPU to signal to enter VMX operation */ 9631 while (vmx_get_test_stage() != 8) 9632 ; 9633 /* Enter VMX operation (i.e. exec VMXON) */ 9634 TEST_ASSERT(!__vmxon_safe(ap_vmxon_region)); 9635 /* Signal to BSP we are in VMX operation */ 9636 vmx_set_test_stage(9); 9637 9638 /* Wait for BSP CPU to send INIT signal */ 9639 while (vmx_get_test_stage() != 10) 9640 ; 9641 9642 /* Exit VMX operation (i.e. exec VMXOFF) */ 9643 vmx_off(); 9644 9645 /* 9646 * Exiting VMX operation should result in latched 9647 * INIT signal being processed. Therefore, we should 9648 * never reach the below code. Thus, signal to BSP 9649 * CPU if we have reached here so it is able to 9650 * report an issue if it happens. 9651 */ 9652 init_signal_test_thread_continued = true; 9653 } 9654 9655 #define INIT_SIGNAL_TEST_DELAY 100000000ULL 9656 9657 static void vmx_init_signal_test(void) 9658 { 9659 struct vmcs *test_vmcs; 9660 9661 if (cpu_count() < 2) { 9662 report_skip("%s : CPU count < 2", __func__); 9663 return; 9664 } 9665 9666 /* VMCLEAR test-vmcs so it could be loaded by other CPU */ 9667 vmcs_save(&test_vmcs); 9668 vmcs_clear(test_vmcs); 9669 9670 vmx_set_test_stage(0); 9671 on_cpu_async(1, init_signal_test_thread, test_vmcs); 9672 9673 /* Wait for other CPU to enter VMX operation */ 9674 while (vmx_get_test_stage() != 1) 9675 ; 9676 9677 /* Send INIT signal to other CPU */ 9678 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_INIT | APIC_INT_ASSERT, 9679 id_map[1]); 9680 /* Signal other CPU we have sent INIT signal */ 9681 vmx_set_test_stage(2); 9682 9683 /* 9684 * Wait reasonable amount of time for INIT signal to 9685 * be received on other CPU and verify that other CPU 9686 * have proceed as usual to next test stage as INIT 9687 * signal should be blocked while other CPU in 9688 * VMX operation 9689 */ 9690 delay(INIT_SIGNAL_TEST_DELAY); 9691 report(vmx_get_test_stage() == 3, 9692 "INIT signal blocked when CPU in VMX operation"); 9693 /* No point to continue if we failed at this point */ 9694 if (vmx_get_test_stage() != 3) 9695 return; 9696 9697 /* Signal other CPU to enter VMX non-root mode */ 9698 init_signal_test_exit_reason = -1ull; 9699 vmx_set_test_stage(4); 9700 /* 9701 * Wait reasonable amount of time for other CPU 9702 * to exit to VMX root mode 9703 */ 9704 delay(INIT_SIGNAL_TEST_DELAY); 9705 if (vmx_get_test_stage() != 5) { 9706 report_fail("Pending INIT signal didn't result in VMX exit"); 9707 return; 9708 } 9709 report(init_signal_test_exit_reason == VMX_INIT, 9710 "INIT signal during VMX non-root mode result in exit-reason %s (%lu)", 9711 exit_reason_description(init_signal_test_exit_reason), 9712 init_signal_test_exit_reason); 9713 9714 /* Run guest to completion */ 9715 make_vmcs_current(test_vmcs); 9716 enter_guest(); 9717 9718 /* Signal other CPU to exit VMX operation */ 9719 init_signal_test_thread_continued = false; 9720 vmx_set_test_stage(6); 9721 9722 /* Wait reasonable amount of time for other CPU to exit VMX operation */ 9723 delay(INIT_SIGNAL_TEST_DELAY); 9724 report(vmx_get_test_stage() == 7, 9725 "INIT signal consumed on VMX_INIT exit"); 9726 /* No point to continue if we failed at this point */ 9727 if (vmx_get_test_stage() != 7) 9728 return; 9729 9730 /* Signal other CPU to enter VMX operation */ 9731 vmx_set_test_stage(8); 9732 /* Wait for other CPU to enter VMX operation */ 9733 while (vmx_get_test_stage() != 9) 9734 ; 9735 9736 /* Send INIT signal to other CPU */ 9737 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_INIT | APIC_INT_ASSERT, 9738 id_map[1]); 9739 /* Signal other CPU we have sent INIT signal */ 9740 vmx_set_test_stage(10); 9741 9742 /* 9743 * Wait reasonable amount of time for other CPU 9744 * to exit VMX operation and process INIT signal 9745 */ 9746 delay(INIT_SIGNAL_TEST_DELAY); 9747 report(!init_signal_test_thread_continued, 9748 "INIT signal processed after exit VMX operation"); 9749 9750 /* 9751 * TODO: Send SIPI to other CPU to sipi_entry (See x86/cstart64.S) 9752 * to re-init it to kvm-unit-tests standard environment. 9753 * Somehow (?) verify that SIPI was indeed received. 9754 */ 9755 } 9756 9757 #define SIPI_SIGNAL_TEST_DELAY 100000000ULL 9758 9759 static void vmx_sipi_test_guest(void) 9760 { 9761 if (apic_id() == 0) { 9762 /* wait AP enter guest with activity=WAIT_SIPI */ 9763 while (vmx_get_test_stage() != 1) 9764 ; 9765 delay(SIPI_SIGNAL_TEST_DELAY); 9766 9767 /* First SIPI signal */ 9768 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_STARTUP | APIC_INT_ASSERT, id_map[1]); 9769 report_pass("BSP(L2): Send first SIPI to cpu[%d]", id_map[1]); 9770 9771 /* wait AP enter guest */ 9772 while (vmx_get_test_stage() != 2) 9773 ; 9774 delay(SIPI_SIGNAL_TEST_DELAY); 9775 9776 /* Second SIPI signal should be ignored since AP is not in WAIT_SIPI state */ 9777 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_STARTUP | APIC_INT_ASSERT, id_map[1]); 9778 report_pass("BSP(L2): Send second SIPI to cpu[%d]", id_map[1]); 9779 9780 /* Delay a while to check whether second SIPI would cause VMExit */ 9781 delay(SIPI_SIGNAL_TEST_DELAY); 9782 9783 /* Test is done, notify AP to exit test */ 9784 vmx_set_test_stage(3); 9785 9786 /* wait AP exit non-root mode */ 9787 while (vmx_get_test_stage() != 5) 9788 ; 9789 } else { 9790 /* wait BSP notify test is done */ 9791 while (vmx_get_test_stage() != 3) 9792 ; 9793 9794 /* AP exit guest */ 9795 vmx_set_test_stage(4); 9796 } 9797 } 9798 9799 static void sipi_test_ap_thread(void *data) 9800 { 9801 struct vmcs *ap_vmcs; 9802 u64 *ap_vmxon_region; 9803 void *ap_stack, *ap_syscall_stack; 9804 u64 cpu_ctrl_0 = CPU_SECONDARY; 9805 u64 cpu_ctrl_1 = 0; 9806 9807 /* Enter VMX operation (i.e. exec VMXON) */ 9808 ap_vmxon_region = alloc_page(); 9809 enable_vmx(); 9810 init_vmx(ap_vmxon_region); 9811 TEST_ASSERT(!__vmxon_safe(ap_vmxon_region)); 9812 init_vmcs(&ap_vmcs); 9813 make_vmcs_current(ap_vmcs); 9814 9815 /* Set stack for AP */ 9816 ap_stack = alloc_page(); 9817 ap_syscall_stack = alloc_page(); 9818 vmcs_write(GUEST_RSP, (u64)(ap_stack + PAGE_SIZE - 1)); 9819 vmcs_write(GUEST_SYSENTER_ESP, (u64)(ap_syscall_stack + PAGE_SIZE - 1)); 9820 9821 /* passthrough lapic to L2 */ 9822 disable_intercept_for_x2apic_msrs(); 9823 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 9824 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 9825 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 9826 9827 /* Set guest activity state to wait-for-SIPI state */ 9828 vmcs_write(GUEST_ACTV_STATE, ACTV_WAIT_SIPI); 9829 9830 vmx_set_test_stage(1); 9831 9832 /* AP enter guest */ 9833 enter_guest(); 9834 9835 if (vmcs_read(EXI_REASON) == VMX_SIPI) { 9836 report_pass("AP: Handle SIPI VMExit"); 9837 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 9838 vmx_set_test_stage(2); 9839 } else { 9840 report_fail("AP: Unexpected VMExit, reason=%ld", vmcs_read(EXI_REASON)); 9841 vmx_off(); 9842 return; 9843 } 9844 9845 /* AP enter guest */ 9846 enter_guest(); 9847 9848 report(vmcs_read(EXI_REASON) != VMX_SIPI, 9849 "AP: should no SIPI VMExit since activity is not in WAIT_SIPI state"); 9850 9851 /* notify BSP that AP is already exit from non-root mode */ 9852 vmx_set_test_stage(5); 9853 9854 /* Leave VMX operation */ 9855 vmx_off(); 9856 } 9857 9858 static void vmx_sipi_signal_test(void) 9859 { 9860 if (!(rdmsr(MSR_IA32_VMX_MISC) & MSR_IA32_VMX_MISC_ACTIVITY_WAIT_SIPI)) { 9861 report_skip("%s : \"ACTIVITY_WAIT_SIPI state\" not supported", __func__); 9862 return; 9863 } 9864 9865 if (cpu_count() < 2) { 9866 report_skip("%s : CPU count < 2", __func__); 9867 return; 9868 } 9869 9870 u64 cpu_ctrl_0 = CPU_SECONDARY; 9871 u64 cpu_ctrl_1 = 0; 9872 9873 /* passthrough lapic to L2 */ 9874 disable_intercept_for_x2apic_msrs(); 9875 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 9876 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 9877 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 9878 9879 test_set_guest(vmx_sipi_test_guest); 9880 9881 /* update CR3 on AP */ 9882 on_cpu(1, update_cr3, (void *)read_cr3()); 9883 9884 /* start AP */ 9885 on_cpu_async(1, sipi_test_ap_thread, NULL); 9886 9887 vmx_set_test_stage(0); 9888 9889 /* BSP enter guest */ 9890 enter_guest(); 9891 } 9892 9893 9894 enum vmcs_access { 9895 ACCESS_VMREAD, 9896 ACCESS_VMWRITE, 9897 ACCESS_NONE, 9898 }; 9899 9900 struct vmcs_shadow_test_common { 9901 enum vmcs_access op; 9902 enum Reason reason; 9903 u64 field; 9904 u64 value; 9905 u64 flags; 9906 u64 time; 9907 } l1_l2_common; 9908 9909 static inline u64 vmread_flags(u64 field, u64 *val) 9910 { 9911 u64 flags; 9912 9913 asm volatile ("vmread %2, %1; pushf; pop %0" 9914 : "=r" (flags), "=rm" (*val) : "r" (field) : "cc"); 9915 return flags & X86_EFLAGS_ALU; 9916 } 9917 9918 static inline u64 vmwrite_flags(u64 field, u64 val) 9919 { 9920 u64 flags; 9921 9922 asm volatile ("vmwrite %1, %2; pushf; pop %0" 9923 : "=r"(flags) : "rm" (val), "r" (field) : "cc"); 9924 return flags & X86_EFLAGS_ALU; 9925 } 9926 9927 static void vmx_vmcs_shadow_test_guest(void) 9928 { 9929 struct vmcs_shadow_test_common *c = &l1_l2_common; 9930 u64 start; 9931 9932 while (c->op != ACCESS_NONE) { 9933 start = rdtsc(); 9934 switch (c->op) { 9935 default: 9936 c->flags = -1ull; 9937 break; 9938 case ACCESS_VMREAD: 9939 c->flags = vmread_flags(c->field, &c->value); 9940 break; 9941 case ACCESS_VMWRITE: 9942 c->flags = vmwrite_flags(c->field, 0); 9943 break; 9944 } 9945 c->time = rdtsc() - start; 9946 vmcall(); 9947 } 9948 } 9949 9950 static u64 vmread_from_shadow(u64 field) 9951 { 9952 struct vmcs *primary; 9953 struct vmcs *shadow; 9954 u64 value; 9955 9956 TEST_ASSERT(!vmcs_save(&primary)); 9957 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 9958 TEST_ASSERT(!make_vmcs_current(shadow)); 9959 value = vmcs_read(field); 9960 TEST_ASSERT(!make_vmcs_current(primary)); 9961 return value; 9962 } 9963 9964 static u64 vmwrite_to_shadow(u64 field, u64 value) 9965 { 9966 struct vmcs *primary; 9967 struct vmcs *shadow; 9968 9969 TEST_ASSERT(!vmcs_save(&primary)); 9970 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 9971 TEST_ASSERT(!make_vmcs_current(shadow)); 9972 vmcs_write(field, value); 9973 value = vmcs_read(field); 9974 TEST_ASSERT(!make_vmcs_current(primary)); 9975 return value; 9976 } 9977 9978 static void vmcs_shadow_test_access(u8 *bitmap[2], enum vmcs_access access) 9979 { 9980 struct vmcs_shadow_test_common *c = &l1_l2_common; 9981 9982 c->op = access; 9983 vmcs_write(VMX_INST_ERROR, 0); 9984 enter_guest(); 9985 c->reason = vmcs_read(EXI_REASON) & 0xffff; 9986 if (c->reason != VMX_VMCALL) { 9987 skip_exit_insn(); 9988 enter_guest(); 9989 } 9990 skip_exit_vmcall(); 9991 } 9992 9993 static void vmcs_shadow_test_field(u8 *bitmap[2], u64 field) 9994 { 9995 struct vmcs_shadow_test_common *c = &l1_l2_common; 9996 struct vmcs *shadow; 9997 u64 value; 9998 uintptr_t flags[2]; 9999 bool good_shadow; 10000 u32 vmx_inst_error; 10001 10002 report_prefix_pushf("field %lx", field); 10003 c->field = field; 10004 10005 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 10006 if (shadow != (struct vmcs *)-1ull) { 10007 flags[ACCESS_VMREAD] = vmread_flags(field, &value); 10008 flags[ACCESS_VMWRITE] = vmwrite_flags(field, value); 10009 good_shadow = !flags[ACCESS_VMREAD] && !flags[ACCESS_VMWRITE]; 10010 } else { 10011 /* 10012 * When VMCS link pointer is -1ull, VMWRITE/VMREAD on 10013 * shadowed-fields should fail with setting RFLAGS.CF. 10014 */ 10015 flags[ACCESS_VMREAD] = X86_EFLAGS_CF; 10016 flags[ACCESS_VMWRITE] = X86_EFLAGS_CF; 10017 good_shadow = false; 10018 } 10019 10020 /* Intercept both VMREAD and VMWRITE. */ 10021 report_prefix_push("no VMREAD/VMWRITE permission"); 10022 /* VMWRITE/VMREAD done on reserved-bit should always intercept */ 10023 if (!(field >> VMCS_FIELD_RESERVED_SHIFT)) { 10024 set_bit(field, bitmap[ACCESS_VMREAD]); 10025 set_bit(field, bitmap[ACCESS_VMWRITE]); 10026 } 10027 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10028 report(c->reason == VMX_VMWRITE, "not shadowed for VMWRITE"); 10029 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10030 report(c->reason == VMX_VMREAD, "not shadowed for VMREAD"); 10031 report_prefix_pop(); 10032 10033 if (field >> VMCS_FIELD_RESERVED_SHIFT) 10034 goto out; 10035 10036 /* Permit shadowed VMREAD. */ 10037 report_prefix_push("VMREAD permission only"); 10038 clear_bit(field, bitmap[ACCESS_VMREAD]); 10039 set_bit(field, bitmap[ACCESS_VMWRITE]); 10040 if (good_shadow) 10041 value = vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 10042 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10043 report(c->reason == VMX_VMWRITE, "not shadowed for VMWRITE"); 10044 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10045 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10046 report(c->reason == VMX_VMCALL, "shadowed for VMREAD (in %ld cycles)", 10047 c->time); 10048 report(c->flags == flags[ACCESS_VMREAD], 10049 "ALU flags after VMREAD (%lx) are as expected (%lx)", 10050 c->flags, flags[ACCESS_VMREAD]); 10051 if (good_shadow) 10052 report(c->value == value, 10053 "value read from shadow (%lx) is as expected (%lx)", 10054 c->value, value); 10055 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 10056 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10057 "VMX_INST_ERROR (%d) is as expected (%d)", 10058 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10059 report_prefix_pop(); 10060 10061 /* Permit shadowed VMWRITE. */ 10062 report_prefix_push("VMWRITE permission only"); 10063 set_bit(field, bitmap[ACCESS_VMREAD]); 10064 clear_bit(field, bitmap[ACCESS_VMWRITE]); 10065 if (good_shadow) 10066 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 10067 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10068 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10069 report(c->reason == VMX_VMCALL, 10070 "shadowed for VMWRITE (in %ld cycles)", 10071 c->time); 10072 report(c->flags == flags[ACCESS_VMREAD], 10073 "ALU flags after VMWRITE (%lx) are as expected (%lx)", 10074 c->flags, flags[ACCESS_VMREAD]); 10075 if (good_shadow) { 10076 value = vmread_from_shadow(field); 10077 report(value == 0, 10078 "shadow VMCS value (%lx) is as expected (%lx)", value, 10079 0ul); 10080 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 10081 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10082 "VMX_INST_ERROR (%d) is as expected (%d)", 10083 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10084 } 10085 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10086 report(c->reason == VMX_VMREAD, "not shadowed for VMREAD"); 10087 report_prefix_pop(); 10088 10089 /* Permit shadowed VMREAD and VMWRITE. */ 10090 report_prefix_push("VMREAD and VMWRITE permission"); 10091 clear_bit(field, bitmap[ACCESS_VMREAD]); 10092 clear_bit(field, bitmap[ACCESS_VMWRITE]); 10093 if (good_shadow) 10094 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 10095 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10096 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10097 report(c->reason == VMX_VMCALL, 10098 "shadowed for VMWRITE (in %ld cycles)", 10099 c->time); 10100 report(c->flags == flags[ACCESS_VMREAD], 10101 "ALU flags after VMWRITE (%lx) are as expected (%lx)", 10102 c->flags, flags[ACCESS_VMREAD]); 10103 if (good_shadow) { 10104 value = vmread_from_shadow(field); 10105 report(value == 0, 10106 "shadow VMCS value (%lx) is as expected (%lx)", value, 10107 0ul); 10108 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 10109 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10110 "VMX_INST_ERROR (%d) is as expected (%d)", 10111 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10112 } 10113 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10114 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10115 report(c->reason == VMX_VMCALL, "shadowed for VMREAD (in %ld cycles)", 10116 c->time); 10117 report(c->flags == flags[ACCESS_VMREAD], 10118 "ALU flags after VMREAD (%lx) are as expected (%lx)", 10119 c->flags, flags[ACCESS_VMREAD]); 10120 if (good_shadow) 10121 report(c->value == 0, 10122 "value read from shadow (%lx) is as expected (%lx)", 10123 c->value, 0ul); 10124 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 10125 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10126 "VMX_INST_ERROR (%d) is as expected (%d)", 10127 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10128 report_prefix_pop(); 10129 10130 out: 10131 report_prefix_pop(); 10132 } 10133 10134 static void vmx_vmcs_shadow_test_body(u8 *bitmap[2]) 10135 { 10136 unsigned base; 10137 unsigned index; 10138 unsigned bit; 10139 unsigned highest_index = rdmsr(MSR_IA32_VMX_VMCS_ENUM); 10140 10141 /* Run test on all possible valid VMCS fields */ 10142 for (base = 0; 10143 base < (1 << VMCS_FIELD_RESERVED_SHIFT); 10144 base += (1 << VMCS_FIELD_TYPE_SHIFT)) 10145 for (index = 0; index <= highest_index; index++) 10146 vmcs_shadow_test_field(bitmap, base + index); 10147 10148 /* 10149 * Run tests on some invalid VMCS fields 10150 * (Have reserved bit set). 10151 */ 10152 for (bit = VMCS_FIELD_RESERVED_SHIFT; bit < VMCS_FIELD_BIT_SIZE; bit++) 10153 vmcs_shadow_test_field(bitmap, (1ull << bit)); 10154 } 10155 10156 static void vmx_vmcs_shadow_test(void) 10157 { 10158 u8 *bitmap[2]; 10159 struct vmcs *shadow; 10160 10161 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 10162 report_skip("%s : \"Activate secondary controls\" not supported", __func__); 10163 return; 10164 } 10165 10166 if (!(ctrl_cpu_rev[1].clr & CPU_SHADOW_VMCS)) { 10167 report_skip("%s : \"VMCS shadowing\" not supported", __func__); 10168 return; 10169 } 10170 10171 if (!(rdmsr(MSR_IA32_VMX_MISC) & 10172 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS)) { 10173 report_skip("%s : VMWRITE can't modify VM-exit information fields.", __func__); 10174 return; 10175 } 10176 10177 test_set_guest(vmx_vmcs_shadow_test_guest); 10178 10179 bitmap[ACCESS_VMREAD] = alloc_page(); 10180 bitmap[ACCESS_VMWRITE] = alloc_page(); 10181 10182 vmcs_write(VMREAD_BITMAP, virt_to_phys(bitmap[ACCESS_VMREAD])); 10183 vmcs_write(VMWRITE_BITMAP, virt_to_phys(bitmap[ACCESS_VMWRITE])); 10184 10185 shadow = alloc_page(); 10186 shadow->hdr.revision_id = basic.revision; 10187 shadow->hdr.shadow_vmcs = 1; 10188 TEST_ASSERT(!vmcs_clear(shadow)); 10189 10190 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_RDTSC); 10191 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY); 10192 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_SHADOW_VMCS); 10193 10194 vmcs_write(VMCS_LINK_PTR, virt_to_phys(shadow)); 10195 report_prefix_push("valid link pointer"); 10196 vmx_vmcs_shadow_test_body(bitmap); 10197 report_prefix_pop(); 10198 10199 vmcs_write(VMCS_LINK_PTR, -1ull); 10200 report_prefix_push("invalid link pointer"); 10201 vmx_vmcs_shadow_test_body(bitmap); 10202 report_prefix_pop(); 10203 10204 l1_l2_common.op = ACCESS_NONE; 10205 enter_guest(); 10206 } 10207 10208 /* 10209 * This test monitors the difference between a guest RDTSC instruction 10210 * and the IA32_TIME_STAMP_COUNTER MSR value stored in the VMCS12 10211 * VM-exit MSR-store list when taking a VM-exit on the instruction 10212 * following RDTSC. 10213 */ 10214 #define RDTSC_DIFF_ITERS 100000 10215 #define RDTSC_DIFF_FAILS 100 10216 #define HOST_CAPTURED_GUEST_TSC_DIFF_THRESHOLD 750 10217 10218 /* 10219 * Set 'use TSC offsetting' and set the guest offset to the 10220 * inverse of the host's current TSC value, so that the guest starts running 10221 * with an effective TSC value of 0. 10222 */ 10223 static void reset_guest_tsc_to_zero(void) 10224 { 10225 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_USE_TSC_OFFSET); 10226 vmcs_write(TSC_OFFSET, -rdtsc()); 10227 } 10228 10229 static void rdtsc_vmexit_diff_test_guest(void) 10230 { 10231 int i; 10232 10233 for (i = 0; i < RDTSC_DIFF_ITERS; i++) 10234 /* Ensure rdtsc is the last instruction before the vmcall. */ 10235 asm volatile("rdtsc; vmcall" : : : "eax", "edx"); 10236 } 10237 10238 /* 10239 * This function only considers the "use TSC offsetting" VM-execution 10240 * control. It does not handle "use TSC scaling" (because the latter 10241 * isn't available to the host today.) 10242 */ 10243 static unsigned long long host_time_to_guest_time(unsigned long long t) 10244 { 10245 TEST_ASSERT(!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 10246 !(vmcs_read(CPU_EXEC_CTRL1) & CPU_USE_TSC_SCALING)); 10247 10248 if (vmcs_read(CPU_EXEC_CTRL0) & CPU_USE_TSC_OFFSET) 10249 t += vmcs_read(TSC_OFFSET); 10250 10251 return t; 10252 } 10253 10254 static unsigned long long rdtsc_vmexit_diff_test_iteration(void) 10255 { 10256 unsigned long long guest_tsc, host_to_guest_tsc; 10257 10258 enter_guest(); 10259 skip_exit_vmcall(); 10260 guest_tsc = (u32) regs.rax + (regs.rdx << 32); 10261 host_to_guest_tsc = host_time_to_guest_time(exit_msr_store[0].value); 10262 10263 return host_to_guest_tsc - guest_tsc; 10264 } 10265 10266 static void rdtsc_vmexit_diff_test(void) 10267 { 10268 unsigned long long delta; 10269 int fail = 0; 10270 int i; 10271 10272 if (!(ctrl_cpu_rev[0].clr & CPU_USE_TSC_OFFSET)) 10273 test_skip("CPU doesn't support the 'use TSC offsetting' processor-based VM-execution control.\n"); 10274 10275 test_set_guest(rdtsc_vmexit_diff_test_guest); 10276 10277 reset_guest_tsc_to_zero(); 10278 10279 /* 10280 * Set up the VMCS12 VM-exit MSR-store list to store just one 10281 * MSR: IA32_TIME_STAMP_COUNTER. Note that the value stored is 10282 * in the host time domain (i.e., it is not adjusted according 10283 * to the TSC multiplier and TSC offset fields in the VMCS12, 10284 * as a guest RDTSC would be.) 10285 */ 10286 exit_msr_store = alloc_page(); 10287 exit_msr_store[0].index = MSR_IA32_TSC; 10288 vmcs_write(EXI_MSR_ST_CNT, 1); 10289 vmcs_write(EXIT_MSR_ST_ADDR, virt_to_phys(exit_msr_store)); 10290 10291 for (i = 0; i < RDTSC_DIFF_ITERS && fail < RDTSC_DIFF_FAILS; i++) { 10292 delta = rdtsc_vmexit_diff_test_iteration(); 10293 if (delta >= HOST_CAPTURED_GUEST_TSC_DIFF_THRESHOLD) 10294 fail++; 10295 } 10296 10297 enter_guest(); 10298 10299 report(fail < RDTSC_DIFF_FAILS, 10300 "RDTSC to VM-exit delta too high in %d of %d iterations, last = %llu", 10301 fail, i, delta); 10302 } 10303 10304 static int invalid_msr_init(struct vmcs *vmcs) 10305 { 10306 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 10307 printf("\tPreemption timer is not supported\n"); 10308 return VMX_TEST_EXIT; 10309 } 10310 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 10311 preempt_val = 10000000; 10312 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 10313 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 10314 10315 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 10316 printf("\tSave preemption value is not supported\n"); 10317 10318 vmcs_write(ENT_MSR_LD_CNT, 1); 10319 vmcs_write(ENTER_MSR_LD_ADDR, (u64)0x13370000); 10320 10321 return VMX_TEST_START; 10322 } 10323 10324 10325 static void invalid_msr_main(void) 10326 { 10327 report_fail("Invalid MSR load"); 10328 } 10329 10330 static int invalid_msr_exit_handler(union exit_reason exit_reason) 10331 { 10332 report_fail("Invalid MSR load"); 10333 print_vmexit_info(exit_reason); 10334 return VMX_TEST_EXIT; 10335 } 10336 10337 static int invalid_msr_entry_failure(struct vmentry_result *result) 10338 { 10339 report(result->exit_reason.failed_vmentry && 10340 result->exit_reason.basic == VMX_FAIL_MSR, "Invalid MSR load"); 10341 return VMX_TEST_VMEXIT; 10342 } 10343 10344 /* 10345 * The max number of MSRs in an atomic switch MSR list is: 10346 * (111B + 1) * 512 = 4096 10347 * 10348 * Each list entry consumes: 10349 * 4-byte MSR index + 4 bytes reserved + 8-byte data = 16 bytes 10350 * 10351 * Allocate 128 kB to cover max_msr_list_size (i.e., 64 kB) and then some. 10352 */ 10353 static const u32 msr_list_page_order = 5; 10354 10355 static void atomic_switch_msr_limit_test_guest(void) 10356 { 10357 vmcall(); 10358 } 10359 10360 static void populate_msr_list(struct vmx_msr_entry *msr_list, 10361 size_t byte_capacity, int count) 10362 { 10363 int i; 10364 10365 for (i = 0; i < count; i++) { 10366 msr_list[i].index = MSR_IA32_TSC; 10367 msr_list[i].reserved = 0; 10368 msr_list[i].value = 0x1234567890abcdef; 10369 } 10370 10371 memset(msr_list + count, 0xff, 10372 byte_capacity - count * sizeof(*msr_list)); 10373 } 10374 10375 static int max_msr_list_size(void) 10376 { 10377 u32 vmx_misc = rdmsr(MSR_IA32_VMX_MISC); 10378 u32 factor = ((vmx_misc & GENMASK(27, 25)) >> 25) + 1; 10379 10380 return factor * 512; 10381 } 10382 10383 static void atomic_switch_msrs_test(int count) 10384 { 10385 struct vmx_msr_entry *vm_enter_load; 10386 struct vmx_msr_entry *vm_exit_load; 10387 struct vmx_msr_entry *vm_exit_store; 10388 int max_allowed = max_msr_list_size(); 10389 int byte_capacity = 1ul << (msr_list_page_order + PAGE_SHIFT); 10390 /* Exceeding the max MSR list size at exit triggers KVM to abort. */ 10391 int exit_count = count > max_allowed ? max_allowed : count; 10392 int cleanup_count = count > max_allowed ? 2 : 1; 10393 int i; 10394 10395 /* 10396 * Check for the IA32_TSC MSR, 10397 * available with the "TSC flag" and used to populate the MSR lists. 10398 */ 10399 if (!(cpuid(1).d & (1 << 4))) { 10400 report_skip("%s : \"Time Stamp Counter\" not supported", __func__); 10401 return; 10402 } 10403 10404 /* Set L2 guest. */ 10405 test_set_guest(atomic_switch_msr_limit_test_guest); 10406 10407 /* Setup atomic MSR switch lists. */ 10408 vm_enter_load = alloc_pages(msr_list_page_order); 10409 vm_exit_load = alloc_pages(msr_list_page_order); 10410 vm_exit_store = alloc_pages(msr_list_page_order); 10411 10412 vmcs_write(ENTER_MSR_LD_ADDR, (u64)vm_enter_load); 10413 vmcs_write(EXIT_MSR_LD_ADDR, (u64)vm_exit_load); 10414 vmcs_write(EXIT_MSR_ST_ADDR, (u64)vm_exit_store); 10415 10416 /* 10417 * VM-Enter should succeed up to the max number of MSRs per list, and 10418 * should not consume junk beyond the last entry. 10419 */ 10420 populate_msr_list(vm_enter_load, byte_capacity, count); 10421 populate_msr_list(vm_exit_load, byte_capacity, exit_count); 10422 populate_msr_list(vm_exit_store, byte_capacity, exit_count); 10423 10424 vmcs_write(ENT_MSR_LD_CNT, count); 10425 vmcs_write(EXI_MSR_LD_CNT, exit_count); 10426 vmcs_write(EXI_MSR_ST_CNT, exit_count); 10427 10428 if (count <= max_allowed) { 10429 enter_guest(); 10430 assert_exit_reason(VMX_VMCALL); 10431 skip_exit_vmcall(); 10432 } else { 10433 u32 exit_qual; 10434 10435 test_guest_state("Invalid MSR Load Count", true, count, 10436 "ENT_MSR_LD_CNT"); 10437 10438 exit_qual = vmcs_read(EXI_QUALIFICATION); 10439 report(exit_qual == max_allowed + 1, "exit_qual, %u, is %u.", 10440 exit_qual, max_allowed + 1); 10441 } 10442 10443 /* Cleanup. */ 10444 vmcs_write(ENT_MSR_LD_CNT, 0); 10445 vmcs_write(EXI_MSR_LD_CNT, 0); 10446 vmcs_write(EXI_MSR_ST_CNT, 0); 10447 for (i = 0; i < cleanup_count; i++) { 10448 enter_guest(); 10449 skip_exit_vmcall(); 10450 } 10451 free_pages_by_order(vm_enter_load, msr_list_page_order); 10452 free_pages_by_order(vm_exit_load, msr_list_page_order); 10453 free_pages_by_order(vm_exit_store, msr_list_page_order); 10454 } 10455 10456 static void atomic_switch_max_msrs_test(void) 10457 { 10458 atomic_switch_msrs_test(max_msr_list_size()); 10459 } 10460 10461 static void atomic_switch_overflow_msrs_test(void) 10462 { 10463 if (test_device_enabled()) 10464 atomic_switch_msrs_test(max_msr_list_size() + 1); 10465 else 10466 test_skip("Test is only supported on KVM"); 10467 } 10468 10469 static void vmx_pf_exception_test_guest(void) 10470 { 10471 ac_test_run(PT_LEVEL_PML4, false); 10472 } 10473 10474 static void vmx_pf_exception_forced_emulation_test_guest(void) 10475 { 10476 ac_test_run(PT_LEVEL_PML4, true); 10477 } 10478 10479 typedef void (*invalidate_tlb_t)(void *data); 10480 typedef void (*pf_exception_test_guest_t)(void); 10481 10482 10483 static void __vmx_pf_exception_test(invalidate_tlb_t inv_fn, void *data, 10484 pf_exception_test_guest_t guest_fn) 10485 { 10486 u64 efer; 10487 struct cpuid cpuid; 10488 10489 test_set_guest(guest_fn); 10490 10491 /* Intercept INVLPG when to perform TLB invalidation from L1 (this). */ 10492 if (inv_fn) 10493 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INVLPG); 10494 else 10495 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INVLPG); 10496 10497 enter_guest(); 10498 10499 while (vmcs_read(EXI_REASON) != VMX_VMCALL) { 10500 switch (vmcs_read(EXI_REASON)) { 10501 case VMX_RDMSR: 10502 assert(regs.rcx == MSR_EFER); 10503 efer = vmcs_read(GUEST_EFER); 10504 regs.rdx = efer >> 32; 10505 regs.rax = efer & 0xffffffff; 10506 break; 10507 case VMX_WRMSR: 10508 assert(regs.rcx == MSR_EFER); 10509 efer = regs.rdx << 32 | (regs.rax & 0xffffffff); 10510 vmcs_write(GUEST_EFER, efer); 10511 break; 10512 case VMX_CPUID: 10513 cpuid = (struct cpuid) {0, 0, 0, 0}; 10514 cpuid = raw_cpuid(regs.rax, regs.rcx); 10515 regs.rax = cpuid.a; 10516 regs.rbx = cpuid.b; 10517 regs.rcx = cpuid.c; 10518 regs.rdx = cpuid.d; 10519 break; 10520 case VMX_INVLPG: 10521 inv_fn(data); 10522 break; 10523 default: 10524 assert_msg(false, 10525 "Unexpected exit to L1, exit_reason: %s (0x%lx)", 10526 exit_reason_description(vmcs_read(EXI_REASON)), 10527 vmcs_read(EXI_REASON)); 10528 } 10529 skip_exit_insn(); 10530 enter_guest(); 10531 } 10532 10533 assert_exit_reason(VMX_VMCALL); 10534 } 10535 10536 static void vmx_pf_exception_test(void) 10537 { 10538 __vmx_pf_exception_test(NULL, NULL, vmx_pf_exception_test_guest); 10539 } 10540 10541 static void vmx_pf_exception_forced_emulation_test(void) 10542 { 10543 __vmx_pf_exception_test(NULL, NULL, vmx_pf_exception_forced_emulation_test_guest); 10544 } 10545 10546 static void invalidate_tlb_no_vpid(void *data) 10547 { 10548 /* If VPID is disabled, the TLB is flushed on VM-Enter and VM-Exit. */ 10549 } 10550 10551 static void vmx_pf_no_vpid_test(void) 10552 { 10553 if (is_vpid_supported()) 10554 vmcs_clear_bits(CPU_EXEC_CTRL1, CPU_VPID); 10555 10556 __vmx_pf_exception_test(invalidate_tlb_no_vpid, NULL, 10557 vmx_pf_exception_test_guest); 10558 } 10559 10560 static void invalidate_tlb_invvpid_addr(void *data) 10561 { 10562 invvpid(INVVPID_ALL, *(u16 *)data, vmcs_read(EXI_QUALIFICATION)); 10563 } 10564 10565 static void invalidate_tlb_new_vpid(void *data) 10566 { 10567 u16 *vpid = data; 10568 10569 /* 10570 * Bump VPID to effectively flush L2's TLB from L0's perspective. 10571 * Invalidate all VPIDs when the VPID wraps to zero as hardware/KVM is 10572 * architecturally allowed to keep TLB entries indefinitely. 10573 */ 10574 ++(*vpid); 10575 if (*vpid == 0) { 10576 ++(*vpid); 10577 invvpid(INVVPID_ALL, 0, 0); 10578 } 10579 vmcs_write(VPID, *vpid); 10580 } 10581 10582 static void __vmx_pf_vpid_test(invalidate_tlb_t inv_fn, u16 vpid) 10583 { 10584 if (!is_vpid_supported()) 10585 test_skip("VPID unsupported"); 10586 10587 if (!is_invvpid_supported()) 10588 test_skip("INVVPID unsupported"); 10589 10590 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY); 10591 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_VPID); 10592 vmcs_write(VPID, vpid); 10593 10594 __vmx_pf_exception_test(inv_fn, &vpid, vmx_pf_exception_test_guest); 10595 } 10596 10597 static void vmx_pf_invvpid_test(void) 10598 { 10599 if (!is_invvpid_type_supported(INVVPID_ADDR)) 10600 test_skip("INVVPID ADDR unsupported"); 10601 10602 __vmx_pf_vpid_test(invalidate_tlb_invvpid_addr, 0xaaaa); 10603 } 10604 10605 static void vmx_pf_vpid_test(void) 10606 { 10607 /* Need INVVPID(ALL) to flush VPIDs upon wrap/reuse. */ 10608 if (!is_invvpid_type_supported(INVVPID_ALL)) 10609 test_skip("INVVPID ALL unsupported"); 10610 10611 __vmx_pf_vpid_test(invalidate_tlb_new_vpid, 1); 10612 } 10613 10614 static void vmx_l2_ac_test(void) 10615 { 10616 bool hit_ac = false; 10617 10618 write_cr0(read_cr0() | X86_CR0_AM); 10619 write_rflags(read_rflags() | X86_EFLAGS_AC); 10620 10621 run_in_user(generate_usermode_ac, AC_VECTOR, 0, 0, 0, 0, &hit_ac); 10622 report(hit_ac, "Usermode #AC handled in L2"); 10623 vmcall(); 10624 } 10625 10626 struct vmx_exception_test { 10627 u8 vector; 10628 void (*guest_code)(void); 10629 }; 10630 10631 struct vmx_exception_test vmx_exception_tests[] = { 10632 { GP_VECTOR, generate_non_canonical_gp }, 10633 { UD_VECTOR, generate_ud }, 10634 { DE_VECTOR, generate_de }, 10635 { DB_VECTOR, generate_single_step_db }, 10636 { BP_VECTOR, generate_bp }, 10637 { AC_VECTOR, vmx_l2_ac_test }, 10638 { OF_VECTOR, generate_of }, 10639 { NM_VECTOR, generate_cr0_ts_nm }, 10640 { NM_VECTOR, generate_cr0_em_nm }, 10641 }; 10642 10643 static u8 vmx_exception_test_vector; 10644 10645 static void vmx_exception_handler(struct ex_regs *regs) 10646 { 10647 report(regs->vector == vmx_exception_test_vector, 10648 "Handling %s in L2's exception handler", 10649 exception_mnemonic(vmx_exception_test_vector)); 10650 vmcall(); 10651 } 10652 10653 static void handle_exception_in_l2(u8 vector) 10654 { 10655 handler old_handler = handle_exception(vector, vmx_exception_handler); 10656 10657 vmx_exception_test_vector = vector; 10658 10659 enter_guest(); 10660 report(vmcs_read(EXI_REASON) == VMX_VMCALL, 10661 "%s handled by L2", exception_mnemonic(vector)); 10662 10663 handle_exception(vector, old_handler); 10664 } 10665 10666 static void handle_exception_in_l1(u32 vector) 10667 { 10668 u32 old_eb = vmcs_read(EXC_BITMAP); 10669 u32 intr_type; 10670 u32 intr_info; 10671 10672 vmcs_write(EXC_BITMAP, old_eb | (1u << vector)); 10673 10674 enter_guest(); 10675 10676 if (vector == BP_VECTOR || vector == OF_VECTOR) 10677 intr_type = VMX_INTR_TYPE_SOFT_EXCEPTION; 10678 else 10679 intr_type = VMX_INTR_TYPE_HARD_EXCEPTION; 10680 10681 intr_info = vmcs_read(EXI_INTR_INFO); 10682 report((vmcs_read(EXI_REASON) == VMX_EXC_NMI) && 10683 (intr_info & INTR_INFO_VALID_MASK) && 10684 (intr_info & INTR_INFO_VECTOR_MASK) == vector && 10685 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> INTR_INFO_INTR_TYPE_SHIFT) == intr_type, 10686 "%s correctly routed to L1", exception_mnemonic(vector)); 10687 10688 vmcs_write(EXC_BITMAP, old_eb); 10689 } 10690 10691 static void vmx_exception_test(void) 10692 { 10693 struct vmx_exception_test *t; 10694 int i; 10695 10696 for (i = 0; i < ARRAY_SIZE(vmx_exception_tests); i++) { 10697 t = &vmx_exception_tests[i]; 10698 10699 /* 10700 * Override the guest code before each run even though it's the 10701 * same code, the VMCS guest state needs to be reinitialized. 10702 */ 10703 test_override_guest(t->guest_code); 10704 handle_exception_in_l2(t->vector); 10705 10706 test_override_guest(t->guest_code); 10707 handle_exception_in_l1(t->vector); 10708 } 10709 10710 test_set_guest_finished(); 10711 } 10712 10713 #define TEST(name) { #name, .v2 = name } 10714 10715 /* name/init/guest_main/exit_handler/syscall_handler/guest_regs */ 10716 struct vmx_test vmx_tests[] = { 10717 { "null", NULL, basic_guest_main, basic_exit_handler, NULL, {0} }, 10718 { "vmenter", NULL, vmenter_main, vmenter_exit_handler, NULL, {0} }, 10719 { "preemption timer", preemption_timer_init, preemption_timer_main, 10720 preemption_timer_exit_handler, NULL, {0} }, 10721 { "control field PAT", test_ctrl_pat_init, test_ctrl_pat_main, 10722 test_ctrl_pat_exit_handler, NULL, {0} }, 10723 { "control field EFER", test_ctrl_efer_init, test_ctrl_efer_main, 10724 test_ctrl_efer_exit_handler, NULL, {0} }, 10725 { "CR shadowing", NULL, cr_shadowing_main, 10726 cr_shadowing_exit_handler, NULL, {0} }, 10727 { "I/O bitmap", iobmp_init, iobmp_main, iobmp_exit_handler, 10728 NULL, {0} }, 10729 { "instruction intercept", insn_intercept_init, insn_intercept_main, 10730 insn_intercept_exit_handler, NULL, {0} }, 10731 { "EPT A/D disabled", ept_init, ept_main, ept_exit_handler, NULL, {0} }, 10732 { "EPT A/D enabled", eptad_init, eptad_main, eptad_exit_handler, NULL, {0} }, 10733 { "PML", pml_init, pml_main, pml_exit_handler, NULL, {0} }, 10734 { "interrupt", interrupt_init, interrupt_main, 10735 interrupt_exit_handler, NULL, {0} }, 10736 { "nmi_hlt", nmi_hlt_init, nmi_hlt_main, 10737 nmi_hlt_exit_handler, NULL, {0} }, 10738 { "debug controls", dbgctls_init, dbgctls_main, dbgctls_exit_handler, 10739 NULL, {0} }, 10740 { "MSR switch", msr_switch_init, msr_switch_main, 10741 msr_switch_exit_handler, NULL, {0}, msr_switch_entry_failure }, 10742 { "vmmcall", vmmcall_init, vmmcall_main, vmmcall_exit_handler, NULL, {0} }, 10743 { "disable RDTSCP", disable_rdtscp_init, disable_rdtscp_main, 10744 disable_rdtscp_exit_handler, NULL, {0} }, 10745 { "exit_monitor_from_l2_test", NULL, exit_monitor_from_l2_main, 10746 exit_monitor_from_l2_handler, NULL, {0} }, 10747 { "invalid_msr", invalid_msr_init, invalid_msr_main, 10748 invalid_msr_exit_handler, NULL, {0}, invalid_msr_entry_failure}, 10749 /* Basic V2 tests. */ 10750 TEST(v2_null_test), 10751 TEST(v2_multiple_entries_test), 10752 TEST(fixture_test_case1), 10753 TEST(fixture_test_case2), 10754 /* Opcode tests. */ 10755 TEST(invvpid_test), 10756 /* VM-entry tests */ 10757 TEST(vmx_controls_test), 10758 TEST(vmx_host_state_area_test), 10759 TEST(vmx_guest_state_area_test), 10760 TEST(vmentry_movss_shadow_test), 10761 TEST(vmentry_unrestricted_guest_test), 10762 /* APICv tests */ 10763 TEST(vmx_eoi_bitmap_ioapic_scan_test), 10764 TEST(vmx_hlt_with_rvi_test), 10765 TEST(apic_reg_virt_test), 10766 TEST(virt_x2apic_mode_test), 10767 /* APIC pass-through tests */ 10768 TEST(vmx_apic_passthrough_test), 10769 TEST(vmx_apic_passthrough_thread_test), 10770 TEST(vmx_apic_passthrough_tpr_threshold_test), 10771 TEST(vmx_init_signal_test), 10772 TEST(vmx_sipi_signal_test), 10773 /* VMCS Shadowing tests */ 10774 TEST(vmx_vmcs_shadow_test), 10775 /* Regression tests */ 10776 TEST(vmx_ldtr_test), 10777 TEST(vmx_cr_load_test), 10778 TEST(vmx_cr4_osxsave_test), 10779 TEST(vmx_no_nm_test), 10780 TEST(vmx_db_test), 10781 TEST(vmx_nmi_window_test), 10782 TEST(vmx_intr_window_test), 10783 TEST(vmx_pending_event_test), 10784 TEST(vmx_pending_event_hlt_test), 10785 TEST(vmx_store_tsc_test), 10786 TEST(vmx_preemption_timer_zero_test), 10787 TEST(vmx_preemption_timer_tf_test), 10788 TEST(vmx_preemption_timer_expiry_test), 10789 /* EPT access tests. */ 10790 TEST(ept_access_test_not_present), 10791 TEST(ept_access_test_read_only), 10792 TEST(ept_access_test_write_only), 10793 TEST(ept_access_test_read_write), 10794 TEST(ept_access_test_execute_only), 10795 TEST(ept_access_test_read_execute), 10796 TEST(ept_access_test_write_execute), 10797 TEST(ept_access_test_read_write_execute), 10798 TEST(ept_access_test_reserved_bits), 10799 TEST(ept_access_test_ignored_bits), 10800 TEST(ept_access_test_paddr_not_present_ad_disabled), 10801 TEST(ept_access_test_paddr_not_present_ad_enabled), 10802 TEST(ept_access_test_paddr_read_only_ad_disabled), 10803 TEST(ept_access_test_paddr_read_only_ad_enabled), 10804 TEST(ept_access_test_paddr_read_write), 10805 TEST(ept_access_test_paddr_read_write_execute), 10806 TEST(ept_access_test_paddr_read_execute_ad_disabled), 10807 TEST(ept_access_test_paddr_read_execute_ad_enabled), 10808 TEST(ept_access_test_paddr_not_present_page_fault), 10809 TEST(ept_access_test_force_2m_page), 10810 /* Atomic MSR switch tests. */ 10811 TEST(atomic_switch_max_msrs_test), 10812 TEST(atomic_switch_overflow_msrs_test), 10813 TEST(rdtsc_vmexit_diff_test), 10814 TEST(vmx_mtf_test), 10815 TEST(vmx_mtf_pdpte_test), 10816 TEST(vmx_pf_exception_test), 10817 TEST(vmx_pf_exception_forced_emulation_test), 10818 TEST(vmx_pf_no_vpid_test), 10819 TEST(vmx_pf_invvpid_test), 10820 TEST(vmx_pf_vpid_test), 10821 TEST(vmx_exception_test), 10822 { NULL, NULL, NULL, NULL, NULL, {0} }, 10823 }; 10824