1 /* 2 * All test cases of nested virtualization should be in this file 3 * 4 * Author : Arthur Chunqi Li <yzt356@gmail.com> 5 */ 6 #include "vmx.h" 7 #include "msr.h" 8 #include "processor.h" 9 #include "vm.h" 10 #include "fwcfg.h" 11 #include "isr.h" 12 #include "desc.h" 13 #include "apic.h" 14 #include "types.h" 15 16 u64 ia32_pat; 17 u64 ia32_efer; 18 void *io_bitmap_a, *io_bitmap_b; 19 u16 ioport; 20 21 unsigned long *pml4; 22 u64 eptp; 23 void *data_page1, *data_page2; 24 25 static inline void vmcall() 26 { 27 asm volatile("vmcall"); 28 } 29 30 void basic_guest_main() 31 { 32 } 33 34 int basic_exit_handler() 35 { 36 report("Basic VMX test", 0); 37 print_vmexit_info(); 38 return VMX_TEST_EXIT; 39 } 40 41 void vmenter_main() 42 { 43 u64 rax; 44 u64 rsp, resume_rsp; 45 46 report("test vmlaunch", 1); 47 48 asm volatile( 49 "mov %%rsp, %0\n\t" 50 "mov %3, %%rax\n\t" 51 "vmcall\n\t" 52 "mov %%rax, %1\n\t" 53 "mov %%rsp, %2\n\t" 54 : "=r"(rsp), "=r"(rax), "=r"(resume_rsp) 55 : "g"(0xABCD)); 56 report("test vmresume", (rax == 0xFFFF) && (rsp == resume_rsp)); 57 } 58 59 int vmenter_exit_handler() 60 { 61 u64 guest_rip; 62 ulong reason; 63 64 guest_rip = vmcs_read(GUEST_RIP); 65 reason = vmcs_read(EXI_REASON) & 0xff; 66 switch (reason) { 67 case VMX_VMCALL: 68 if (regs.rax != 0xABCD) { 69 report("test vmresume", 0); 70 return VMX_TEST_VMEXIT; 71 } 72 regs.rax = 0xFFFF; 73 vmcs_write(GUEST_RIP, guest_rip + 3); 74 return VMX_TEST_RESUME; 75 default: 76 report("test vmresume", 0); 77 print_vmexit_info(); 78 } 79 return VMX_TEST_VMEXIT; 80 } 81 82 u32 preempt_scale; 83 volatile unsigned long long tsc_val; 84 volatile u32 preempt_val; 85 u64 saved_rip; 86 87 int preemption_timer_init() 88 { 89 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 90 printf("\tPreemption timer is not supported\n"); 91 return VMX_TEST_EXIT; 92 } 93 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 94 preempt_val = 10000000; 95 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 96 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 97 98 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 99 printf("\tSave preemption value is not supported\n"); 100 101 return VMX_TEST_START; 102 } 103 104 void preemption_timer_main() 105 { 106 tsc_val = rdtsc(); 107 if (ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) { 108 vmx_set_test_stage(0); 109 vmcall(); 110 if (vmx_get_test_stage() == 1) 111 vmcall(); 112 } 113 vmx_set_test_stage(1); 114 while (vmx_get_test_stage() == 1) { 115 if (((rdtsc() - tsc_val) >> preempt_scale) 116 > 10 * preempt_val) { 117 vmx_set_test_stage(2); 118 vmcall(); 119 } 120 } 121 tsc_val = rdtsc(); 122 asm volatile ("hlt"); 123 vmcall(); 124 vmx_set_test_stage(5); 125 vmcall(); 126 } 127 128 int preemption_timer_exit_handler() 129 { 130 bool guest_halted; 131 u64 guest_rip; 132 ulong reason; 133 u32 insn_len; 134 u32 ctrl_exit; 135 136 guest_rip = vmcs_read(GUEST_RIP); 137 reason = vmcs_read(EXI_REASON) & 0xff; 138 insn_len = vmcs_read(EXI_INST_LEN); 139 switch (reason) { 140 case VMX_PREEMPT: 141 switch (vmx_get_test_stage()) { 142 case 1: 143 case 2: 144 report("busy-wait for preemption timer", 145 ((rdtsc() - tsc_val) >> preempt_scale) >= 146 preempt_val); 147 vmx_set_test_stage(3); 148 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 149 return VMX_TEST_RESUME; 150 case 3: 151 guest_halted = 152 (vmcs_read(GUEST_ACTV_STATE) == ACTV_HLT); 153 report("preemption timer during hlt", 154 ((rdtsc() - tsc_val) >> preempt_scale) >= 155 preempt_val && guest_halted); 156 vmx_set_test_stage(4); 157 vmcs_write(PIN_CONTROLS, 158 vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 159 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 160 return VMX_TEST_RESUME; 161 case 4: 162 report("preemption timer with 0 value", 163 saved_rip == guest_rip); 164 break; 165 default: 166 printf("Invalid stage.\n"); 167 print_vmexit_info(); 168 break; 169 } 170 break; 171 case VMX_VMCALL: 172 vmcs_write(GUEST_RIP, guest_rip + insn_len); 173 switch (vmx_get_test_stage()) { 174 case 0: 175 report("Keep preemption value", 176 vmcs_read(PREEMPT_TIMER_VALUE) == preempt_val); 177 vmx_set_test_stage(1); 178 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 179 ctrl_exit = (vmcs_read(EXI_CONTROLS) | 180 EXI_SAVE_PREEMPT) & ctrl_exit_rev.clr; 181 vmcs_write(EXI_CONTROLS, ctrl_exit); 182 return VMX_TEST_RESUME; 183 case 1: 184 report("Save preemption value", 185 vmcs_read(PREEMPT_TIMER_VALUE) < preempt_val); 186 return VMX_TEST_RESUME; 187 case 2: 188 report("busy-wait for preemption timer", 0); 189 vmx_set_test_stage(3); 190 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 191 return VMX_TEST_RESUME; 192 case 3: 193 report("preemption timer during hlt", 0); 194 vmx_set_test_stage(4); 195 /* fall through */ 196 case 4: 197 vmcs_write(PIN_CONTROLS, 198 vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 199 vmcs_write(PREEMPT_TIMER_VALUE, 0); 200 saved_rip = guest_rip + insn_len; 201 return VMX_TEST_RESUME; 202 case 5: 203 report("preemption timer with 0 value (vmcall stage 5)", 0); 204 break; 205 default: 206 // Should not reach here 207 printf("ERROR : unexpected stage, %d\n", 208 vmx_get_test_stage()); 209 print_vmexit_info(); 210 return VMX_TEST_VMEXIT; 211 } 212 break; 213 default: 214 printf("Unknown exit reason, %ld\n", reason); 215 print_vmexit_info(); 216 } 217 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 218 return VMX_TEST_VMEXIT; 219 } 220 221 void msr_bmp_init() 222 { 223 void *msr_bitmap; 224 u32 ctrl_cpu0; 225 226 msr_bitmap = alloc_page(); 227 memset(msr_bitmap, 0x0, PAGE_SIZE); 228 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 229 ctrl_cpu0 |= CPU_MSR_BITMAP; 230 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 231 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 232 } 233 234 static int test_ctrl_pat_init() 235 { 236 u64 ctrl_ent; 237 u64 ctrl_exi; 238 239 msr_bmp_init(); 240 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT) && 241 !(ctrl_exit_rev.clr & EXI_LOAD_PAT) && 242 !(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 243 printf("\tSave/load PAT is not supported\n"); 244 return 1; 245 } 246 247 ctrl_ent = vmcs_read(ENT_CONTROLS); 248 ctrl_exi = vmcs_read(EXI_CONTROLS); 249 ctrl_ent |= ctrl_enter_rev.clr & ENT_LOAD_PAT; 250 ctrl_exi |= ctrl_exit_rev.clr & (EXI_SAVE_PAT | EXI_LOAD_PAT); 251 vmcs_write(ENT_CONTROLS, ctrl_ent); 252 vmcs_write(EXI_CONTROLS, ctrl_exi); 253 ia32_pat = rdmsr(MSR_IA32_CR_PAT); 254 vmcs_write(GUEST_PAT, 0x0); 255 vmcs_write(HOST_PAT, ia32_pat); 256 return VMX_TEST_START; 257 } 258 259 static void test_ctrl_pat_main() 260 { 261 u64 guest_ia32_pat; 262 263 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 264 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) 265 printf("\tENT_LOAD_PAT is not supported.\n"); 266 else { 267 if (guest_ia32_pat != 0) { 268 report("Entry load PAT", 0); 269 return; 270 } 271 } 272 wrmsr(MSR_IA32_CR_PAT, 0x6); 273 vmcall(); 274 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 275 if (ctrl_enter_rev.clr & ENT_LOAD_PAT) 276 report("Entry load PAT", guest_ia32_pat == ia32_pat); 277 } 278 279 static int test_ctrl_pat_exit_handler() 280 { 281 u64 guest_rip; 282 ulong reason; 283 u64 guest_pat; 284 285 guest_rip = vmcs_read(GUEST_RIP); 286 reason = vmcs_read(EXI_REASON) & 0xff; 287 switch (reason) { 288 case VMX_VMCALL: 289 guest_pat = vmcs_read(GUEST_PAT); 290 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT)) { 291 printf("\tEXI_SAVE_PAT is not supported\n"); 292 vmcs_write(GUEST_PAT, 0x6); 293 } else { 294 report("Exit save PAT", guest_pat == 0x6); 295 } 296 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) 297 printf("\tEXI_LOAD_PAT is not supported\n"); 298 else 299 report("Exit load PAT", rdmsr(MSR_IA32_CR_PAT) == ia32_pat); 300 vmcs_write(GUEST_PAT, ia32_pat); 301 vmcs_write(GUEST_RIP, guest_rip + 3); 302 return VMX_TEST_RESUME; 303 default: 304 printf("ERROR : Undefined exit reason, reason = %ld.\n", reason); 305 break; 306 } 307 return VMX_TEST_VMEXIT; 308 } 309 310 static int test_ctrl_efer_init() 311 { 312 u64 ctrl_ent; 313 u64 ctrl_exi; 314 315 msr_bmp_init(); 316 ctrl_ent = vmcs_read(ENT_CONTROLS) | ENT_LOAD_EFER; 317 ctrl_exi = vmcs_read(EXI_CONTROLS) | EXI_SAVE_EFER | EXI_LOAD_EFER; 318 vmcs_write(ENT_CONTROLS, ctrl_ent & ctrl_enter_rev.clr); 319 vmcs_write(EXI_CONTROLS, ctrl_exi & ctrl_exit_rev.clr); 320 ia32_efer = rdmsr(MSR_EFER); 321 vmcs_write(GUEST_EFER, ia32_efer ^ EFER_NX); 322 vmcs_write(HOST_EFER, ia32_efer ^ EFER_NX); 323 return VMX_TEST_START; 324 } 325 326 static void test_ctrl_efer_main() 327 { 328 u64 guest_ia32_efer; 329 330 guest_ia32_efer = rdmsr(MSR_EFER); 331 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) 332 printf("\tENT_LOAD_EFER is not supported.\n"); 333 else { 334 if (guest_ia32_efer != (ia32_efer ^ EFER_NX)) { 335 report("Entry load EFER", 0); 336 return; 337 } 338 } 339 wrmsr(MSR_EFER, ia32_efer); 340 vmcall(); 341 guest_ia32_efer = rdmsr(MSR_EFER); 342 if (ctrl_enter_rev.clr & ENT_LOAD_EFER) 343 report("Entry load EFER", guest_ia32_efer == ia32_efer); 344 } 345 346 static int test_ctrl_efer_exit_handler() 347 { 348 u64 guest_rip; 349 ulong reason; 350 u64 guest_efer; 351 352 guest_rip = vmcs_read(GUEST_RIP); 353 reason = vmcs_read(EXI_REASON) & 0xff; 354 switch (reason) { 355 case VMX_VMCALL: 356 guest_efer = vmcs_read(GUEST_EFER); 357 if (!(ctrl_exit_rev.clr & EXI_SAVE_EFER)) { 358 printf("\tEXI_SAVE_EFER is not supported\n"); 359 vmcs_write(GUEST_EFER, ia32_efer); 360 } else { 361 report("Exit save EFER", guest_efer == ia32_efer); 362 } 363 if (!(ctrl_exit_rev.clr & EXI_LOAD_EFER)) { 364 printf("\tEXI_LOAD_EFER is not supported\n"); 365 wrmsr(MSR_EFER, ia32_efer ^ EFER_NX); 366 } else { 367 report("Exit load EFER", rdmsr(MSR_EFER) == (ia32_efer ^ EFER_NX)); 368 } 369 vmcs_write(GUEST_PAT, ia32_efer); 370 vmcs_write(GUEST_RIP, guest_rip + 3); 371 return VMX_TEST_RESUME; 372 default: 373 printf("ERROR : Undefined exit reason, reason = %ld.\n", reason); 374 break; 375 } 376 return VMX_TEST_VMEXIT; 377 } 378 379 u32 guest_cr0, guest_cr4; 380 381 static void cr_shadowing_main() 382 { 383 u32 cr0, cr4, tmp; 384 385 // Test read through 386 vmx_set_test_stage(0); 387 guest_cr0 = read_cr0(); 388 if (vmx_get_test_stage() == 1) 389 report("Read through CR0", 0); 390 else 391 vmcall(); 392 vmx_set_test_stage(1); 393 guest_cr4 = read_cr4(); 394 if (vmx_get_test_stage() == 2) 395 report("Read through CR4", 0); 396 else 397 vmcall(); 398 // Test write through 399 guest_cr0 = guest_cr0 ^ (X86_CR0_TS | X86_CR0_MP); 400 guest_cr4 = guest_cr4 ^ (X86_CR4_TSD | X86_CR4_DE); 401 vmx_set_test_stage(2); 402 write_cr0(guest_cr0); 403 if (vmx_get_test_stage() == 3) 404 report("Write throuth CR0", 0); 405 else 406 vmcall(); 407 vmx_set_test_stage(3); 408 write_cr4(guest_cr4); 409 if (vmx_get_test_stage() == 4) 410 report("Write through CR4", 0); 411 else 412 vmcall(); 413 // Test read shadow 414 vmx_set_test_stage(4); 415 vmcall(); 416 cr0 = read_cr0(); 417 if (vmx_get_test_stage() != 5) 418 report("Read shadowing CR0", cr0 == guest_cr0); 419 vmx_set_test_stage(5); 420 cr4 = read_cr4(); 421 if (vmx_get_test_stage() != 6) 422 report("Read shadowing CR4", cr4 == guest_cr4); 423 // Test write shadow (same value with shadow) 424 vmx_set_test_stage(6); 425 write_cr0(guest_cr0); 426 if (vmx_get_test_stage() == 7) 427 report("Write shadowing CR0 (same value with shadow)", 0); 428 else 429 vmcall(); 430 vmx_set_test_stage(7); 431 write_cr4(guest_cr4); 432 if (vmx_get_test_stage() == 8) 433 report("Write shadowing CR4 (same value with shadow)", 0); 434 else 435 vmcall(); 436 // Test write shadow (different value) 437 vmx_set_test_stage(8); 438 tmp = guest_cr0 ^ X86_CR0_TS; 439 asm volatile("mov %0, %%rsi\n\t" 440 "mov %%rsi, %%cr0\n\t" 441 ::"m"(tmp) 442 :"rsi", "memory", "cc"); 443 report("Write shadowing different X86_CR0_TS", vmx_get_test_stage() == 9); 444 vmx_set_test_stage(9); 445 tmp = guest_cr0 ^ X86_CR0_MP; 446 asm volatile("mov %0, %%rsi\n\t" 447 "mov %%rsi, %%cr0\n\t" 448 ::"m"(tmp) 449 :"rsi", "memory", "cc"); 450 report("Write shadowing different X86_CR0_MP", vmx_get_test_stage() == 10); 451 vmx_set_test_stage(10); 452 tmp = guest_cr4 ^ X86_CR4_TSD; 453 asm volatile("mov %0, %%rsi\n\t" 454 "mov %%rsi, %%cr4\n\t" 455 ::"m"(tmp) 456 :"rsi", "memory", "cc"); 457 report("Write shadowing different X86_CR4_TSD", vmx_get_test_stage() == 11); 458 vmx_set_test_stage(11); 459 tmp = guest_cr4 ^ X86_CR4_DE; 460 asm volatile("mov %0, %%rsi\n\t" 461 "mov %%rsi, %%cr4\n\t" 462 ::"m"(tmp) 463 :"rsi", "memory", "cc"); 464 report("Write shadowing different X86_CR4_DE", vmx_get_test_stage() == 12); 465 } 466 467 static int cr_shadowing_exit_handler() 468 { 469 u64 guest_rip; 470 ulong reason; 471 u32 insn_len; 472 u32 exit_qual; 473 474 guest_rip = vmcs_read(GUEST_RIP); 475 reason = vmcs_read(EXI_REASON) & 0xff; 476 insn_len = vmcs_read(EXI_INST_LEN); 477 exit_qual = vmcs_read(EXI_QUALIFICATION); 478 switch (reason) { 479 case VMX_VMCALL: 480 switch (vmx_get_test_stage()) { 481 case 0: 482 report("Read through CR0", guest_cr0 == vmcs_read(GUEST_CR0)); 483 break; 484 case 1: 485 report("Read through CR4", guest_cr4 == vmcs_read(GUEST_CR4)); 486 break; 487 case 2: 488 report("Write through CR0", guest_cr0 == vmcs_read(GUEST_CR0)); 489 break; 490 case 3: 491 report("Write through CR4", guest_cr4 == vmcs_read(GUEST_CR4)); 492 break; 493 case 4: 494 guest_cr0 = vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP); 495 guest_cr4 = vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE); 496 vmcs_write(CR0_MASK, X86_CR0_TS | X86_CR0_MP); 497 vmcs_write(CR0_READ_SHADOW, guest_cr0 & (X86_CR0_TS | X86_CR0_MP)); 498 vmcs_write(CR4_MASK, X86_CR4_TSD | X86_CR4_DE); 499 vmcs_write(CR4_READ_SHADOW, guest_cr4 & (X86_CR4_TSD | X86_CR4_DE)); 500 break; 501 case 6: 502 report("Write shadowing CR0 (same value)", 503 guest_cr0 == (vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP))); 504 break; 505 case 7: 506 report("Write shadowing CR4 (same value)", 507 guest_cr4 == (vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE))); 508 break; 509 default: 510 // Should not reach here 511 printf("ERROR : unexpected stage, %d\n", 512 vmx_get_test_stage()); 513 print_vmexit_info(); 514 return VMX_TEST_VMEXIT; 515 } 516 vmcs_write(GUEST_RIP, guest_rip + insn_len); 517 return VMX_TEST_RESUME; 518 case VMX_CR: 519 switch (vmx_get_test_stage()) { 520 case 4: 521 report("Read shadowing CR0", 0); 522 vmx_inc_test_stage(); 523 break; 524 case 5: 525 report("Read shadowing CR4", 0); 526 vmx_inc_test_stage(); 527 break; 528 case 6: 529 report("Write shadowing CR0 (same value)", 0); 530 vmx_inc_test_stage(); 531 break; 532 case 7: 533 report("Write shadowing CR4 (same value)", 0); 534 vmx_inc_test_stage(); 535 break; 536 case 8: 537 case 9: 538 // 0x600 encodes "mov %esi, %cr0" 539 if (exit_qual == 0x600) 540 vmx_inc_test_stage(); 541 break; 542 case 10: 543 case 11: 544 // 0x604 encodes "mov %esi, %cr4" 545 if (exit_qual == 0x604) 546 vmx_inc_test_stage(); 547 break; 548 default: 549 // Should not reach here 550 printf("ERROR : unexpected stage, %d\n", 551 vmx_get_test_stage()); 552 print_vmexit_info(); 553 return VMX_TEST_VMEXIT; 554 } 555 vmcs_write(GUEST_RIP, guest_rip + insn_len); 556 return VMX_TEST_RESUME; 557 default: 558 printf("Unknown exit reason, %ld\n", reason); 559 print_vmexit_info(); 560 } 561 return VMX_TEST_VMEXIT; 562 } 563 564 static int iobmp_init() 565 { 566 u32 ctrl_cpu0; 567 568 io_bitmap_a = alloc_page(); 569 io_bitmap_b = alloc_page(); 570 memset(io_bitmap_a, 0x0, PAGE_SIZE); 571 memset(io_bitmap_b, 0x0, PAGE_SIZE); 572 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 573 ctrl_cpu0 |= CPU_IO_BITMAP; 574 ctrl_cpu0 &= (~CPU_IO); 575 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 576 vmcs_write(IO_BITMAP_A, (u64)io_bitmap_a); 577 vmcs_write(IO_BITMAP_B, (u64)io_bitmap_b); 578 return VMX_TEST_START; 579 } 580 581 static void iobmp_main() 582 { 583 // stage 0, test IO pass 584 vmx_set_test_stage(0); 585 inb(0x5000); 586 outb(0x0, 0x5000); 587 report("I/O bitmap - I/O pass", vmx_get_test_stage() == 0); 588 // test IO width, in/out 589 ((u8 *)io_bitmap_a)[0] = 0xFF; 590 vmx_set_test_stage(2); 591 inb(0x0); 592 report("I/O bitmap - trap in", vmx_get_test_stage() == 3); 593 vmx_set_test_stage(3); 594 outw(0x0, 0x0); 595 report("I/O bitmap - trap out", vmx_get_test_stage() == 4); 596 vmx_set_test_stage(4); 597 inl(0x0); 598 report("I/O bitmap - I/O width, long", vmx_get_test_stage() == 5); 599 // test low/high IO port 600 vmx_set_test_stage(5); 601 ((u8 *)io_bitmap_a)[0x5000 / 8] = (1 << (0x5000 % 8)); 602 inb(0x5000); 603 report("I/O bitmap - I/O port, low part", vmx_get_test_stage() == 6); 604 vmx_set_test_stage(6); 605 ((u8 *)io_bitmap_b)[0x1000 / 8] = (1 << (0x1000 % 8)); 606 inb(0x9000); 607 report("I/O bitmap - I/O port, high part", vmx_get_test_stage() == 7); 608 // test partial pass 609 vmx_set_test_stage(7); 610 inl(0x4FFF); 611 report("I/O bitmap - partial pass", vmx_get_test_stage() == 8); 612 // test overrun 613 vmx_set_test_stage(8); 614 memset(io_bitmap_a, 0x0, PAGE_SIZE); 615 memset(io_bitmap_b, 0x0, PAGE_SIZE); 616 inl(0xFFFF); 617 report("I/O bitmap - overrun", vmx_get_test_stage() == 9); 618 vmx_set_test_stage(9); 619 vmcall(); 620 outb(0x0, 0x0); 621 report("I/O bitmap - ignore unconditional exiting", 622 vmx_get_test_stage() == 9); 623 vmx_set_test_stage(10); 624 vmcall(); 625 outb(0x0, 0x0); 626 report("I/O bitmap - unconditional exiting", 627 vmx_get_test_stage() == 11); 628 } 629 630 static int iobmp_exit_handler() 631 { 632 u64 guest_rip; 633 ulong reason, exit_qual; 634 u32 insn_len, ctrl_cpu0; 635 636 guest_rip = vmcs_read(GUEST_RIP); 637 reason = vmcs_read(EXI_REASON) & 0xff; 638 exit_qual = vmcs_read(EXI_QUALIFICATION); 639 insn_len = vmcs_read(EXI_INST_LEN); 640 switch (reason) { 641 case VMX_IO: 642 switch (vmx_get_test_stage()) { 643 case 0: 644 case 1: 645 vmx_inc_test_stage(); 646 break; 647 case 2: 648 report("I/O bitmap - I/O width, byte", 649 (exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_BYTE); 650 report("I/O bitmap - I/O direction, in", exit_qual & VMX_IO_IN); 651 vmx_inc_test_stage(); 652 break; 653 case 3: 654 report("I/O bitmap - I/O width, word", 655 (exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_WORD); 656 report("I/O bitmap - I/O direction, out", 657 !(exit_qual & VMX_IO_IN)); 658 vmx_inc_test_stage(); 659 break; 660 case 4: 661 report("I/O bitmap - I/O width, long", 662 (exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_LONG); 663 vmx_inc_test_stage(); 664 break; 665 case 5: 666 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x5000) 667 vmx_inc_test_stage(); 668 break; 669 case 6: 670 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x9000) 671 vmx_inc_test_stage(); 672 break; 673 case 7: 674 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x4FFF) 675 vmx_inc_test_stage(); 676 break; 677 case 8: 678 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0xFFFF) 679 vmx_inc_test_stage(); 680 break; 681 case 9: 682 case 10: 683 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 684 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0 & ~CPU_IO); 685 vmx_inc_test_stage(); 686 break; 687 default: 688 // Should not reach here 689 printf("ERROR : unexpected stage, %d\n", 690 vmx_get_test_stage()); 691 print_vmexit_info(); 692 return VMX_TEST_VMEXIT; 693 } 694 vmcs_write(GUEST_RIP, guest_rip + insn_len); 695 return VMX_TEST_RESUME; 696 case VMX_VMCALL: 697 switch (vmx_get_test_stage()) { 698 case 9: 699 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 700 ctrl_cpu0 |= CPU_IO | CPU_IO_BITMAP; 701 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 702 break; 703 case 10: 704 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 705 ctrl_cpu0 = (ctrl_cpu0 & ~CPU_IO_BITMAP) | CPU_IO; 706 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 707 break; 708 default: 709 // Should not reach here 710 printf("ERROR : unexpected stage, %d\n", 711 vmx_get_test_stage()); 712 print_vmexit_info(); 713 return VMX_TEST_VMEXIT; 714 } 715 vmcs_write(GUEST_RIP, guest_rip + insn_len); 716 return VMX_TEST_RESUME; 717 default: 718 printf("guest_rip = 0x%lx\n", guest_rip); 719 printf("\tERROR : Undefined exit reason, reason = %ld.\n", reason); 720 break; 721 } 722 return VMX_TEST_VMEXIT; 723 } 724 725 #define INSN_CPU0 0 726 #define INSN_CPU1 1 727 #define INSN_ALWAYS_TRAP 2 728 729 #define FIELD_EXIT_QUAL (1 << 0) 730 #define FIELD_INSN_INFO (1 << 1) 731 732 asm( 733 "insn_hlt: hlt;ret\n\t" 734 "insn_invlpg: invlpg 0x12345678;ret\n\t" 735 "insn_mwait: mwait;ret\n\t" 736 "insn_rdpmc: xor %ecx, %ecx; rdpmc;ret\n\t" 737 "insn_rdtsc: rdtsc;ret\n\t" 738 "insn_cr3_load: mov cr3,%rax; mov %rax,%cr3;ret\n\t" 739 "insn_cr3_store: mov %cr3,%rax;ret\n\t" 740 #ifdef __x86_64__ 741 "insn_cr8_load: mov %rax,%cr8;ret\n\t" 742 "insn_cr8_store: mov %cr8,%rax;ret\n\t" 743 #endif 744 "insn_monitor: monitor;ret\n\t" 745 "insn_pause: pause;ret\n\t" 746 "insn_wbinvd: wbinvd;ret\n\t" 747 "insn_cpuid: mov $10, %eax; cpuid;ret\n\t" 748 "insn_invd: invd;ret\n\t" 749 "insn_sgdt: sgdt gdt64_desc;ret\n\t" 750 "insn_lgdt: lgdt gdt64_desc;ret\n\t" 751 "insn_sidt: sidt idt_descr;ret\n\t" 752 "insn_lidt: lidt idt_descr;ret\n\t" 753 "insn_sldt: sldt %ax;ret\n\t" 754 "insn_lldt: xor %eax, %eax; lldt %ax;ret\n\t" 755 "insn_str: str %ax;ret\n\t" 756 ); 757 extern void insn_hlt(); 758 extern void insn_invlpg(); 759 extern void insn_mwait(); 760 extern void insn_rdpmc(); 761 extern void insn_rdtsc(); 762 extern void insn_cr3_load(); 763 extern void insn_cr3_store(); 764 #ifdef __x86_64__ 765 extern void insn_cr8_load(); 766 extern void insn_cr8_store(); 767 #endif 768 extern void insn_monitor(); 769 extern void insn_pause(); 770 extern void insn_wbinvd(); 771 extern void insn_sgdt(); 772 extern void insn_lgdt(); 773 extern void insn_sidt(); 774 extern void insn_lidt(); 775 extern void insn_sldt(); 776 extern void insn_lldt(); 777 extern void insn_str(); 778 extern void insn_cpuid(); 779 extern void insn_invd(); 780 781 u32 cur_insn; 782 u64 cr3; 783 784 struct insn_table { 785 const char *name; 786 u32 flag; 787 void (*insn_func)(); 788 u32 type; 789 u32 reason; 790 ulong exit_qual; 791 u32 insn_info; 792 // Use FIELD_EXIT_QUAL and FIELD_INSN_INFO to define 793 // which field need to be tested, reason is always tested 794 u32 test_field; 795 }; 796 797 /* 798 * Add more test cases of instruction intercept here. Elements in this 799 * table is: 800 * name/control flag/insn function/type/exit reason/exit qulification/ 801 * instruction info/field to test 802 * The last field defines which fields (exit_qual and insn_info) need to be 803 * tested in exit handler. If set to 0, only "reason" is checked. 804 */ 805 static struct insn_table insn_table[] = { 806 // Flags for Primary Processor-Based VM-Execution Controls 807 {"HLT", CPU_HLT, insn_hlt, INSN_CPU0, 12, 0, 0, 0}, 808 {"INVLPG", CPU_INVLPG, insn_invlpg, INSN_CPU0, 14, 809 0x12345678, 0, FIELD_EXIT_QUAL}, 810 {"MWAIT", CPU_MWAIT, insn_mwait, INSN_CPU0, 36, 0, 0, 0}, 811 {"RDPMC", CPU_RDPMC, insn_rdpmc, INSN_CPU0, 15, 0, 0, 0}, 812 {"RDTSC", CPU_RDTSC, insn_rdtsc, INSN_CPU0, 16, 0, 0, 0}, 813 {"CR3 load", CPU_CR3_LOAD, insn_cr3_load, INSN_CPU0, 28, 0x3, 0, 814 FIELD_EXIT_QUAL}, 815 {"CR3 store", CPU_CR3_STORE, insn_cr3_store, INSN_CPU0, 28, 0x13, 0, 816 FIELD_EXIT_QUAL}, 817 #ifdef __x86_64__ 818 {"CR8 load", CPU_CR8_LOAD, insn_cr8_load, INSN_CPU0, 28, 0x8, 0, 819 FIELD_EXIT_QUAL}, 820 {"CR8 store", CPU_CR8_STORE, insn_cr8_store, INSN_CPU0, 28, 0x18, 0, 821 FIELD_EXIT_QUAL}, 822 #endif 823 {"MONITOR", CPU_MONITOR, insn_monitor, INSN_CPU0, 39, 0, 0, 0}, 824 {"PAUSE", CPU_PAUSE, insn_pause, INSN_CPU0, 40, 0, 0, 0}, 825 // Flags for Secondary Processor-Based VM-Execution Controls 826 {"WBINVD", CPU_WBINVD, insn_wbinvd, INSN_CPU1, 54, 0, 0, 0}, 827 {"DESC_TABLE (SGDT)", CPU_DESC_TABLE, insn_sgdt, INSN_CPU1, 46, 0, 0, 0}, 828 {"DESC_TABLE (LGDT)", CPU_DESC_TABLE, insn_lgdt, INSN_CPU1, 46, 0, 0, 0}, 829 {"DESC_TABLE (SIDT)", CPU_DESC_TABLE, insn_sidt, INSN_CPU1, 46, 0, 0, 0}, 830 {"DESC_TABLE (LIDT)", CPU_DESC_TABLE, insn_lidt, INSN_CPU1, 46, 0, 0, 0}, 831 {"DESC_TABLE (SLDT)", CPU_DESC_TABLE, insn_sldt, INSN_CPU1, 47, 0, 0, 0}, 832 {"DESC_TABLE (LLDT)", CPU_DESC_TABLE, insn_lldt, INSN_CPU1, 47, 0, 0, 0}, 833 {"DESC_TABLE (STR)", CPU_DESC_TABLE, insn_str, INSN_CPU1, 47, 0, 0, 0}, 834 /* LTR causes a #GP if done with a busy selector, so it is not tested. */ 835 // Instructions always trap 836 {"CPUID", 0, insn_cpuid, INSN_ALWAYS_TRAP, 10, 0, 0, 0}, 837 {"INVD", 0, insn_invd, INSN_ALWAYS_TRAP, 13, 0, 0, 0}, 838 // Instructions never trap 839 {NULL}, 840 }; 841 842 static int insn_intercept_init() 843 { 844 u32 ctrl_cpu; 845 846 ctrl_cpu = ctrl_cpu_rev[0].set | CPU_SECONDARY; 847 ctrl_cpu &= ctrl_cpu_rev[0].clr; 848 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu); 849 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu_rev[1].set); 850 cr3 = read_cr3(); 851 return VMX_TEST_START; 852 } 853 854 static void insn_intercept_main() 855 { 856 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 857 vmx_set_test_stage(cur_insn * 2); 858 if ((insn_table[cur_insn].type == INSN_CPU0 && 859 !(ctrl_cpu_rev[0].clr & insn_table[cur_insn].flag)) || 860 (insn_table[cur_insn].type == INSN_CPU1 && 861 !(ctrl_cpu_rev[1].clr & insn_table[cur_insn].flag))) { 862 printf("\tCPU_CTRL%d.CPU_%s is not supported.\n", 863 insn_table[cur_insn].type - INSN_CPU0, 864 insn_table[cur_insn].name); 865 continue; 866 } 867 868 if ((insn_table[cur_insn].type == INSN_CPU0 && 869 !(ctrl_cpu_rev[0].set & insn_table[cur_insn].flag)) || 870 (insn_table[cur_insn].type == INSN_CPU1 && 871 !(ctrl_cpu_rev[1].set & insn_table[cur_insn].flag))) { 872 /* skip hlt, it stalls the guest and is tested below */ 873 if (insn_table[cur_insn].insn_func != insn_hlt) 874 insn_table[cur_insn].insn_func(); 875 report("execute %s", vmx_get_test_stage() == cur_insn * 2, 876 insn_table[cur_insn].name); 877 } else if (insn_table[cur_insn].type != INSN_ALWAYS_TRAP) 878 printf("\tCPU_CTRL%d.CPU_%s always traps.\n", 879 insn_table[cur_insn].type - INSN_CPU0, 880 insn_table[cur_insn].name); 881 882 vmcall(); 883 884 insn_table[cur_insn].insn_func(); 885 report("intercept %s", vmx_get_test_stage() == cur_insn * 2 + 1, 886 insn_table[cur_insn].name); 887 888 vmx_set_test_stage(cur_insn * 2 + 1); 889 vmcall(); 890 } 891 } 892 893 static int insn_intercept_exit_handler() 894 { 895 u64 guest_rip; 896 u32 reason; 897 ulong exit_qual; 898 u32 insn_len; 899 u32 insn_info; 900 bool pass; 901 902 guest_rip = vmcs_read(GUEST_RIP); 903 reason = vmcs_read(EXI_REASON) & 0xff; 904 exit_qual = vmcs_read(EXI_QUALIFICATION); 905 insn_len = vmcs_read(EXI_INST_LEN); 906 insn_info = vmcs_read(EXI_INST_INFO); 907 908 if (reason == VMX_VMCALL) { 909 u32 val = 0; 910 911 if (insn_table[cur_insn].type == INSN_CPU0) 912 val = vmcs_read(CPU_EXEC_CTRL0); 913 else if (insn_table[cur_insn].type == INSN_CPU1) 914 val = vmcs_read(CPU_EXEC_CTRL1); 915 916 if (vmx_get_test_stage() & 1) 917 val &= ~insn_table[cur_insn].flag; 918 else 919 val |= insn_table[cur_insn].flag; 920 921 if (insn_table[cur_insn].type == INSN_CPU0) 922 vmcs_write(CPU_EXEC_CTRL0, val | ctrl_cpu_rev[0].set); 923 else if (insn_table[cur_insn].type == INSN_CPU1) 924 vmcs_write(CPU_EXEC_CTRL1, val | ctrl_cpu_rev[1].set); 925 } else { 926 pass = (cur_insn * 2 == vmx_get_test_stage()) && 927 insn_table[cur_insn].reason == reason; 928 if (insn_table[cur_insn].test_field & FIELD_EXIT_QUAL && 929 insn_table[cur_insn].exit_qual != exit_qual) 930 pass = false; 931 if (insn_table[cur_insn].test_field & FIELD_INSN_INFO && 932 insn_table[cur_insn].insn_info != insn_info) 933 pass = false; 934 if (pass) 935 vmx_inc_test_stage(); 936 } 937 vmcs_write(GUEST_RIP, guest_rip + insn_len); 938 return VMX_TEST_RESUME; 939 } 940 941 942 static int setup_ept() 943 { 944 int support_2m; 945 unsigned long end_of_memory; 946 947 if (!(ept_vpid.val & EPT_CAP_UC) && 948 !(ept_vpid.val & EPT_CAP_WB)) { 949 printf("\tEPT paging-structure memory type " 950 "UC&WB are not supported\n"); 951 return 1; 952 } 953 if (ept_vpid.val & EPT_CAP_UC) 954 eptp = EPT_MEM_TYPE_UC; 955 else 956 eptp = EPT_MEM_TYPE_WB; 957 if (!(ept_vpid.val & EPT_CAP_PWL4)) { 958 printf("\tPWL4 is not supported\n"); 959 return 1; 960 } 961 eptp |= (3 << EPTP_PG_WALK_LEN_SHIFT); 962 pml4 = alloc_page(); 963 memset(pml4, 0, PAGE_SIZE); 964 eptp |= virt_to_phys(pml4); 965 vmcs_write(EPTP, eptp); 966 support_2m = !!(ept_vpid.val & EPT_CAP_2M_PAGE); 967 end_of_memory = fwcfg_get_u64(FW_CFG_RAM_SIZE); 968 if (end_of_memory < (1ul << 32)) 969 end_of_memory = (1ul << 32); 970 setup_ept_range(pml4, 0, end_of_memory, 0, support_2m, 971 EPT_WA | EPT_RA | EPT_EA); 972 return 0; 973 } 974 975 static int apic_version; 976 977 static int ept_init() 978 { 979 u32 ctrl_cpu[2]; 980 981 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 982 !(ctrl_cpu_rev[1].clr & CPU_EPT)) { 983 printf("\tEPT is not supported"); 984 return VMX_TEST_EXIT; 985 } 986 987 ctrl_cpu[0] = vmcs_read(CPU_EXEC_CTRL0); 988 ctrl_cpu[1] = vmcs_read(CPU_EXEC_CTRL1); 989 ctrl_cpu[0] = (ctrl_cpu[0] | CPU_SECONDARY) 990 & ctrl_cpu_rev[0].clr; 991 ctrl_cpu[1] = (ctrl_cpu[1] | CPU_EPT) 992 & ctrl_cpu_rev[1].clr; 993 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu[0]); 994 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu[1]); 995 if (setup_ept()) 996 return VMX_TEST_EXIT; 997 data_page1 = alloc_page(); 998 data_page2 = alloc_page(); 999 memset(data_page1, 0x0, PAGE_SIZE); 1000 memset(data_page2, 0x0, PAGE_SIZE); 1001 *((u32 *)data_page1) = MAGIC_VAL_1; 1002 *((u32 *)data_page2) = MAGIC_VAL_2; 1003 install_ept(pml4, (unsigned long)data_page1, (unsigned long)data_page2, 1004 EPT_RA | EPT_WA | EPT_EA); 1005 1006 apic_version = *((u32 *)0xfee00030UL); 1007 return VMX_TEST_START; 1008 } 1009 1010 static void ept_main() 1011 { 1012 vmx_set_test_stage(0); 1013 if (*((u32 *)data_page2) != MAGIC_VAL_1 || 1014 *((u32 *)data_page1) != MAGIC_VAL_1) 1015 report("EPT basic framework - read", 0); 1016 else { 1017 *((u32 *)data_page2) = MAGIC_VAL_3; 1018 vmcall(); 1019 if (vmx_get_test_stage() == 1) { 1020 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1021 *((u32 *)data_page2) == MAGIC_VAL_2) 1022 report("EPT basic framework", 1); 1023 else 1024 report("EPT basic framework - remap", 1); 1025 } 1026 } 1027 // Test EPT Misconfigurations 1028 vmx_set_test_stage(1); 1029 vmcall(); 1030 *((u32 *)data_page1) = MAGIC_VAL_1; 1031 if (vmx_get_test_stage() != 2) { 1032 report("EPT misconfigurations", 0); 1033 goto t1; 1034 } 1035 vmx_set_test_stage(2); 1036 vmcall(); 1037 *((u32 *)data_page1) = MAGIC_VAL_1; 1038 report("EPT misconfigurations", vmx_get_test_stage() == 3); 1039 t1: 1040 // Test EPT violation 1041 vmx_set_test_stage(3); 1042 vmcall(); 1043 *((u32 *)data_page1) = MAGIC_VAL_1; 1044 report("EPT violation - page permission", vmx_get_test_stage() == 4); 1045 // Violation caused by EPT paging structure 1046 vmx_set_test_stage(4); 1047 vmcall(); 1048 *((u32 *)data_page1) = MAGIC_VAL_2; 1049 report("EPT violation - paging structure", vmx_get_test_stage() == 5); 1050 1051 // Test EPT access to L1 MMIO 1052 vmx_set_test_stage(6); 1053 report("EPT - MMIO access", *((u32 *)0xfee00030UL) == apic_version); 1054 1055 // Test invalid operand for INVEPT 1056 vmcall(); 1057 report("EPT - unsupported INVEPT", vmx_get_test_stage() == 7); 1058 } 1059 1060 bool invept_test(int type, u64 eptp) 1061 { 1062 bool ret, supported; 1063 1064 supported = ept_vpid.val & (EPT_CAP_INVEPT_SINGLE >> INVEPT_SINGLE << type); 1065 ret = invept(type, eptp); 1066 1067 if (ret == !supported) 1068 return false; 1069 1070 if (!supported) 1071 printf("WARNING: unsupported invept passed!\n"); 1072 else 1073 printf("WARNING: invept failed!\n"); 1074 1075 return true; 1076 } 1077 1078 static int ept_exit_handler() 1079 { 1080 u64 guest_rip; 1081 ulong reason; 1082 u32 insn_len; 1083 u32 exit_qual; 1084 static unsigned long data_page1_pte, data_page1_pte_pte; 1085 1086 guest_rip = vmcs_read(GUEST_RIP); 1087 reason = vmcs_read(EXI_REASON) & 0xff; 1088 insn_len = vmcs_read(EXI_INST_LEN); 1089 exit_qual = vmcs_read(EXI_QUALIFICATION); 1090 switch (reason) { 1091 case VMX_VMCALL: 1092 switch (vmx_get_test_stage()) { 1093 case 0: 1094 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1095 *((u32 *)data_page2) == MAGIC_VAL_2) { 1096 vmx_inc_test_stage(); 1097 install_ept(pml4, (unsigned long)data_page2, 1098 (unsigned long)data_page2, 1099 EPT_RA | EPT_WA | EPT_EA); 1100 } else 1101 report("EPT basic framework - write", 0); 1102 break; 1103 case 1: 1104 install_ept(pml4, (unsigned long)data_page1, 1105 (unsigned long)data_page1, EPT_WA); 1106 ept_sync(INVEPT_SINGLE, eptp); 1107 break; 1108 case 2: 1109 install_ept(pml4, (unsigned long)data_page1, 1110 (unsigned long)data_page1, 1111 EPT_RA | EPT_WA | EPT_EA | 1112 (2 << EPT_MEM_TYPE_SHIFT)); 1113 ept_sync(INVEPT_SINGLE, eptp); 1114 break; 1115 case 3: 1116 data_page1_pte = get_ept_pte(pml4, 1117 (unsigned long)data_page1, 1); 1118 set_ept_pte(pml4, (unsigned long)data_page1, 1119 1, data_page1_pte & (~EPT_PRESENT)); 1120 ept_sync(INVEPT_SINGLE, eptp); 1121 break; 1122 case 4: 1123 data_page1_pte = get_ept_pte(pml4, 1124 (unsigned long)data_page1, 2); 1125 data_page1_pte &= PAGE_MASK; 1126 data_page1_pte_pte = get_ept_pte(pml4, data_page1_pte, 2); 1127 set_ept_pte(pml4, data_page1_pte, 2, 1128 data_page1_pte_pte & (~EPT_PRESENT)); 1129 ept_sync(INVEPT_SINGLE, eptp); 1130 break; 1131 case 6: 1132 if (!invept_test(0, eptp)) 1133 vmx_inc_test_stage(); 1134 break; 1135 // Should not reach here 1136 default: 1137 printf("ERROR - unexpected stage, %d.\n", 1138 vmx_get_test_stage()); 1139 print_vmexit_info(); 1140 return VMX_TEST_VMEXIT; 1141 } 1142 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1143 return VMX_TEST_RESUME; 1144 case VMX_EPT_MISCONFIG: 1145 switch (vmx_get_test_stage()) { 1146 case 1: 1147 case 2: 1148 vmx_inc_test_stage(); 1149 install_ept(pml4, (unsigned long)data_page1, 1150 (unsigned long)data_page1, 1151 EPT_RA | EPT_WA | EPT_EA); 1152 ept_sync(INVEPT_SINGLE, eptp); 1153 break; 1154 // Should not reach here 1155 default: 1156 printf("ERROR - unexpected stage, %d.\n", 1157 vmx_get_test_stage()); 1158 print_vmexit_info(); 1159 return VMX_TEST_VMEXIT; 1160 } 1161 return VMX_TEST_RESUME; 1162 case VMX_EPT_VIOLATION: 1163 switch(vmx_get_test_stage()) { 1164 case 3: 1165 if (exit_qual == (EPT_VLT_WR | EPT_VLT_LADDR_VLD | 1166 EPT_VLT_PADDR)) 1167 vmx_inc_test_stage(); 1168 set_ept_pte(pml4, (unsigned long)data_page1, 1169 1, data_page1_pte | (EPT_PRESENT)); 1170 ept_sync(INVEPT_SINGLE, eptp); 1171 break; 1172 case 4: 1173 if (exit_qual == (EPT_VLT_RD | EPT_VLT_LADDR_VLD)) 1174 vmx_inc_test_stage(); 1175 set_ept_pte(pml4, data_page1_pte, 2, 1176 data_page1_pte_pte | (EPT_PRESENT)); 1177 ept_sync(INVEPT_SINGLE, eptp); 1178 break; 1179 default: 1180 // Should not reach here 1181 printf("ERROR : unexpected stage, %d\n", 1182 vmx_get_test_stage()); 1183 print_vmexit_info(); 1184 return VMX_TEST_VMEXIT; 1185 } 1186 return VMX_TEST_RESUME; 1187 default: 1188 printf("Unknown exit reason, %ld\n", reason); 1189 print_vmexit_info(); 1190 } 1191 return VMX_TEST_VMEXIT; 1192 } 1193 1194 bool invvpid_test(int type, u16 vpid) 1195 { 1196 bool ret, supported; 1197 1198 supported = ept_vpid.val & (VPID_CAP_INVVPID_SINGLE >> INVVPID_SINGLE << type); 1199 ret = invvpid(type, vpid, 0); 1200 1201 if (ret == !supported) 1202 return false; 1203 1204 if (!supported) 1205 printf("WARNING: unsupported invvpid passed!\n"); 1206 else 1207 printf("WARNING: invvpid failed!\n"); 1208 1209 return true; 1210 } 1211 1212 static int vpid_init() 1213 { 1214 u32 ctrl_cpu1; 1215 1216 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1217 !(ctrl_cpu_rev[1].clr & CPU_VPID)) { 1218 printf("\tVPID is not supported"); 1219 return VMX_TEST_EXIT; 1220 } 1221 1222 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 1223 ctrl_cpu1 |= CPU_VPID; 1224 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 1225 return VMX_TEST_START; 1226 } 1227 1228 static void vpid_main() 1229 { 1230 vmx_set_test_stage(0); 1231 vmcall(); 1232 report("INVVPID SINGLE ADDRESS", vmx_get_test_stage() == 1); 1233 vmx_set_test_stage(2); 1234 vmcall(); 1235 report("INVVPID SINGLE", vmx_get_test_stage() == 3); 1236 vmx_set_test_stage(4); 1237 vmcall(); 1238 report("INVVPID ALL", vmx_get_test_stage() == 5); 1239 } 1240 1241 static int vpid_exit_handler() 1242 { 1243 u64 guest_rip; 1244 ulong reason; 1245 u32 insn_len; 1246 1247 guest_rip = vmcs_read(GUEST_RIP); 1248 reason = vmcs_read(EXI_REASON) & 0xff; 1249 insn_len = vmcs_read(EXI_INST_LEN); 1250 1251 switch (reason) { 1252 case VMX_VMCALL: 1253 switch(vmx_get_test_stage()) { 1254 case 0: 1255 if (!invvpid_test(INVVPID_SINGLE_ADDRESS, 1)) 1256 vmx_inc_test_stage(); 1257 break; 1258 case 2: 1259 if (!invvpid_test(INVVPID_SINGLE, 1)) 1260 vmx_inc_test_stage(); 1261 break; 1262 case 4: 1263 if (!invvpid_test(INVVPID_ALL, 1)) 1264 vmx_inc_test_stage(); 1265 break; 1266 default: 1267 printf("ERROR: unexpected stage, %d\n", 1268 vmx_get_test_stage()); 1269 print_vmexit_info(); 1270 return VMX_TEST_VMEXIT; 1271 } 1272 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1273 return VMX_TEST_RESUME; 1274 default: 1275 printf("Unknown exit reason, %ld\n", reason); 1276 print_vmexit_info(); 1277 } 1278 return VMX_TEST_VMEXIT; 1279 } 1280 1281 #define TIMER_VECTOR 222 1282 1283 static volatile bool timer_fired; 1284 1285 static void timer_isr(isr_regs_t *regs) 1286 { 1287 timer_fired = true; 1288 apic_write(APIC_EOI, 0); 1289 } 1290 1291 static int interrupt_init(struct vmcs *vmcs) 1292 { 1293 msr_bmp_init(); 1294 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1295 handle_irq(TIMER_VECTOR, timer_isr); 1296 return VMX_TEST_START; 1297 } 1298 1299 static void interrupt_main(void) 1300 { 1301 long long start, loops; 1302 1303 vmx_set_test_stage(0); 1304 1305 apic_write(APIC_LVTT, TIMER_VECTOR); 1306 irq_enable(); 1307 1308 apic_write(APIC_TMICT, 1); 1309 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1310 asm volatile ("nop"); 1311 report("direct interrupt while running guest", timer_fired); 1312 1313 apic_write(APIC_TMICT, 0); 1314 irq_disable(); 1315 vmcall(); 1316 timer_fired = false; 1317 apic_write(APIC_TMICT, 1); 1318 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1319 asm volatile ("nop"); 1320 report("intercepted interrupt while running guest", timer_fired); 1321 1322 irq_enable(); 1323 apic_write(APIC_TMICT, 0); 1324 irq_disable(); 1325 vmcall(); 1326 timer_fired = false; 1327 start = rdtsc(); 1328 apic_write(APIC_TMICT, 1000000); 1329 1330 asm volatile ("sti; hlt"); 1331 1332 report("direct interrupt + hlt", 1333 rdtsc() - start > 1000000 && timer_fired); 1334 1335 apic_write(APIC_TMICT, 0); 1336 irq_disable(); 1337 vmcall(); 1338 timer_fired = false; 1339 start = rdtsc(); 1340 apic_write(APIC_TMICT, 1000000); 1341 1342 asm volatile ("sti; hlt"); 1343 1344 report("intercepted interrupt + hlt", 1345 rdtsc() - start > 10000 && timer_fired); 1346 1347 apic_write(APIC_TMICT, 0); 1348 irq_disable(); 1349 vmcall(); 1350 timer_fired = false; 1351 start = rdtsc(); 1352 apic_write(APIC_TMICT, 1000000); 1353 1354 irq_enable(); 1355 asm volatile ("nop"); 1356 vmcall(); 1357 1358 report("direct interrupt + activity state hlt", 1359 rdtsc() - start > 10000 && timer_fired); 1360 1361 apic_write(APIC_TMICT, 0); 1362 irq_disable(); 1363 vmcall(); 1364 timer_fired = false; 1365 start = rdtsc(); 1366 apic_write(APIC_TMICT, 1000000); 1367 1368 irq_enable(); 1369 asm volatile ("nop"); 1370 vmcall(); 1371 1372 report("intercepted interrupt + activity state hlt", 1373 rdtsc() - start > 10000 && timer_fired); 1374 1375 apic_write(APIC_TMICT, 0); 1376 irq_disable(); 1377 vmx_set_test_stage(7); 1378 vmcall(); 1379 timer_fired = false; 1380 apic_write(APIC_TMICT, 1); 1381 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1382 asm volatile ("nop"); 1383 report("running a guest with interrupt acknowledgement set", timer_fired); 1384 } 1385 1386 static int interrupt_exit_handler(void) 1387 { 1388 u64 guest_rip = vmcs_read(GUEST_RIP); 1389 ulong reason = vmcs_read(EXI_REASON) & 0xff; 1390 u32 insn_len = vmcs_read(EXI_INST_LEN); 1391 1392 switch (reason) { 1393 case VMX_VMCALL: 1394 switch (vmx_get_test_stage()) { 1395 case 0: 1396 case 2: 1397 case 5: 1398 vmcs_write(PIN_CONTROLS, 1399 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1400 break; 1401 case 7: 1402 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_INTA); 1403 vmcs_write(PIN_CONTROLS, 1404 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1405 break; 1406 case 1: 1407 case 3: 1408 vmcs_write(PIN_CONTROLS, 1409 vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1410 break; 1411 case 4: 1412 case 6: 1413 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1414 break; 1415 } 1416 vmx_inc_test_stage(); 1417 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1418 return VMX_TEST_RESUME; 1419 case VMX_EXTINT: 1420 if (vmcs_read(EXI_CONTROLS) & EXI_INTA) { 1421 int vector = vmcs_read(EXI_INTR_INFO) & 0xff; 1422 handle_external_interrupt(vector); 1423 } else { 1424 irq_enable(); 1425 asm volatile ("nop"); 1426 irq_disable(); 1427 } 1428 if (vmx_get_test_stage() >= 2) 1429 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 1430 return VMX_TEST_RESUME; 1431 default: 1432 printf("Unknown exit reason, %ld\n", reason); 1433 print_vmexit_info(); 1434 } 1435 1436 return VMX_TEST_VMEXIT; 1437 } 1438 1439 static int dbgctls_init(struct vmcs *vmcs) 1440 { 1441 u64 dr7 = 0x402; 1442 u64 zero = 0; 1443 1444 msr_bmp_init(); 1445 asm volatile( 1446 "mov %0,%%dr0\n\t" 1447 "mov %0,%%dr1\n\t" 1448 "mov %0,%%dr2\n\t" 1449 "mov %1,%%dr7\n\t" 1450 : : "r" (zero), "r" (dr7)); 1451 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1452 vmcs_write(GUEST_DR7, 0x404); 1453 vmcs_write(GUEST_DEBUGCTL, 0x2); 1454 1455 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 1456 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_SAVE_DBGCTLS); 1457 1458 return VMX_TEST_START; 1459 } 1460 1461 static void dbgctls_main(void) 1462 { 1463 u64 dr7, debugctl; 1464 1465 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1466 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1467 /* Commented out: KVM does not support DEBUGCTL so far */ 1468 (void)debugctl; 1469 report("Load debug controls", dr7 == 0x404 /* && debugctl == 0x2 */); 1470 1471 dr7 = 0x408; 1472 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1473 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1474 1475 vmx_set_test_stage(0); 1476 vmcall(); 1477 report("Save debug controls", vmx_get_test_stage() == 1); 1478 1479 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS || 1480 ctrl_exit_rev.set & EXI_SAVE_DBGCTLS) { 1481 printf("\tDebug controls are always loaded/saved\n"); 1482 return; 1483 } 1484 vmx_set_test_stage(2); 1485 vmcall(); 1486 1487 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1488 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1489 /* Commented out: KVM does not support DEBUGCTL so far */ 1490 (void)debugctl; 1491 report("Guest=host debug controls", dr7 == 0x402 /* && debugctl == 0x1 */); 1492 1493 dr7 = 0x408; 1494 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1495 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1496 1497 vmx_set_test_stage(3); 1498 vmcall(); 1499 report("Don't save debug controls", vmx_get_test_stage() == 4); 1500 } 1501 1502 static int dbgctls_exit_handler(void) 1503 { 1504 unsigned int reason = vmcs_read(EXI_REASON) & 0xff; 1505 u32 insn_len = vmcs_read(EXI_INST_LEN); 1506 u64 guest_rip = vmcs_read(GUEST_RIP); 1507 u64 dr7, debugctl; 1508 1509 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1510 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1511 1512 switch (reason) { 1513 case VMX_VMCALL: 1514 switch (vmx_get_test_stage()) { 1515 case 0: 1516 if (dr7 == 0x400 && debugctl == 0 && 1517 vmcs_read(GUEST_DR7) == 0x408 /* && 1518 Commented out: KVM does not support DEBUGCTL so far 1519 vmcs_read(GUEST_DEBUGCTL) == 0x3 */) 1520 vmx_inc_test_stage(); 1521 break; 1522 case 2: 1523 dr7 = 0x402; 1524 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1525 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1526 vmcs_write(GUEST_DR7, 0x404); 1527 vmcs_write(GUEST_DEBUGCTL, 0x2); 1528 1529 vmcs_write(ENT_CONTROLS, 1530 vmcs_read(ENT_CONTROLS) & ~ENT_LOAD_DBGCTLS); 1531 vmcs_write(EXI_CONTROLS, 1532 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_DBGCTLS); 1533 break; 1534 case 3: 1535 if (dr7 == 0x400 && debugctl == 0 && 1536 vmcs_read(GUEST_DR7) == 0x404 /* && 1537 Commented out: KVM does not support DEBUGCTL so far 1538 vmcs_read(GUEST_DEBUGCTL) == 0x2 */) 1539 vmx_inc_test_stage(); 1540 break; 1541 } 1542 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1543 return VMX_TEST_RESUME; 1544 default: 1545 printf("Unknown exit reason, %d\n", reason); 1546 print_vmexit_info(); 1547 } 1548 return VMX_TEST_VMEXIT; 1549 } 1550 1551 struct vmx_msr_entry { 1552 u32 index; 1553 u32 reserved; 1554 u64 value; 1555 } __attribute__((packed)); 1556 1557 #define MSR_MAGIC 0x31415926 1558 struct vmx_msr_entry *exit_msr_store, *entry_msr_load, *exit_msr_load; 1559 1560 static int msr_switch_init(struct vmcs *vmcs) 1561 { 1562 msr_bmp_init(); 1563 exit_msr_store = alloc_page(); 1564 exit_msr_load = alloc_page(); 1565 entry_msr_load = alloc_page(); 1566 memset(exit_msr_store, 0, PAGE_SIZE); 1567 memset(exit_msr_load, 0, PAGE_SIZE); 1568 memset(entry_msr_load, 0, PAGE_SIZE); 1569 entry_msr_load[0].index = MSR_KERNEL_GS_BASE; 1570 entry_msr_load[0].value = MSR_MAGIC; 1571 1572 vmx_set_test_stage(1); 1573 vmcs_write(ENT_MSR_LD_CNT, 1); 1574 vmcs_write(ENTER_MSR_LD_ADDR, (u64)entry_msr_load); 1575 vmcs_write(EXI_MSR_ST_CNT, 1); 1576 vmcs_write(EXIT_MSR_ST_ADDR, (u64)exit_msr_store); 1577 vmcs_write(EXI_MSR_LD_CNT, 1); 1578 vmcs_write(EXIT_MSR_LD_ADDR, (u64)exit_msr_load); 1579 return VMX_TEST_START; 1580 } 1581 1582 static void msr_switch_main() 1583 { 1584 if (vmx_get_test_stage() == 1) { 1585 report("VM entry MSR load", 1586 rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC); 1587 vmx_set_test_stage(2); 1588 wrmsr(MSR_KERNEL_GS_BASE, MSR_MAGIC + 1); 1589 exit_msr_store[0].index = MSR_KERNEL_GS_BASE; 1590 exit_msr_load[0].index = MSR_KERNEL_GS_BASE; 1591 exit_msr_load[0].value = MSR_MAGIC + 2; 1592 } 1593 vmcall(); 1594 } 1595 1596 static int msr_switch_exit_handler() 1597 { 1598 ulong reason; 1599 1600 reason = vmcs_read(EXI_REASON); 1601 if (reason == VMX_VMCALL && vmx_get_test_stage() == 2) { 1602 report("VM exit MSR store", 1603 exit_msr_store[0].value == MSR_MAGIC + 1); 1604 report("VM exit MSR load", 1605 rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC + 2); 1606 vmx_set_test_stage(3); 1607 entry_msr_load[0].index = MSR_FS_BASE; 1608 return VMX_TEST_RESUME; 1609 } 1610 printf("ERROR %s: unexpected stage=%u or reason=%lu\n", 1611 __func__, vmx_get_test_stage(), reason); 1612 return VMX_TEST_EXIT; 1613 } 1614 1615 static int msr_switch_entry_failure(struct vmentry_failure *failure) 1616 { 1617 ulong reason; 1618 1619 if (failure->early) { 1620 printf("ERROR %s: early exit\n", __func__); 1621 return VMX_TEST_EXIT; 1622 } 1623 1624 reason = vmcs_read(EXI_REASON); 1625 if (reason == (VMX_ENTRY_FAILURE | VMX_FAIL_MSR) && 1626 vmx_get_test_stage() == 3) { 1627 report("VM entry MSR load: try to load FS_BASE", 1628 vmcs_read(EXI_QUALIFICATION) == 1); 1629 return VMX_TEST_VMEXIT; 1630 } 1631 printf("ERROR %s: unexpected stage=%u or reason=%lu\n", 1632 __func__, vmx_get_test_stage(), reason); 1633 return VMX_TEST_EXIT; 1634 } 1635 1636 static int vmmcall_init(struct vmcs *vmcs ) 1637 { 1638 vmcs_write(EXC_BITMAP, 1 << UD_VECTOR); 1639 return VMX_TEST_START; 1640 } 1641 1642 static void vmmcall_main(void) 1643 { 1644 asm volatile( 1645 "mov $0xABCD, %%rax\n\t" 1646 "vmmcall\n\t" 1647 ::: "rax"); 1648 1649 report("VMMCALL", 0); 1650 } 1651 1652 static int vmmcall_exit_handler() 1653 { 1654 ulong reason; 1655 1656 reason = vmcs_read(EXI_REASON); 1657 switch (reason) { 1658 case VMX_VMCALL: 1659 printf("here\n"); 1660 report("VMMCALL triggers #UD", 0); 1661 break; 1662 case VMX_EXC_NMI: 1663 report("VMMCALL triggers #UD", 1664 (vmcs_read(EXI_INTR_INFO) & 0xff) == UD_VECTOR); 1665 break; 1666 default: 1667 printf("Unknown exit reason, %ld\n", reason); 1668 print_vmexit_info(); 1669 } 1670 1671 return VMX_TEST_VMEXIT; 1672 } 1673 1674 static int disable_rdtscp_init(struct vmcs *vmcs) 1675 { 1676 u32 ctrl_cpu1; 1677 1678 if (ctrl_cpu_rev[0].clr & CPU_SECONDARY) { 1679 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 1680 ctrl_cpu1 &= ~CPU_RDTSCP; 1681 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 1682 } 1683 1684 return VMX_TEST_START; 1685 } 1686 1687 static void disable_rdtscp_ud_handler(struct ex_regs *regs) 1688 { 1689 switch (vmx_get_test_stage()) { 1690 case 0: 1691 report("RDTSCP triggers #UD", true); 1692 vmx_inc_test_stage(); 1693 regs->rip += 3; 1694 break; 1695 case 2: 1696 report("RDPID triggers #UD", true); 1697 vmx_inc_test_stage(); 1698 regs->rip += 4; 1699 break; 1700 } 1701 return; 1702 1703 } 1704 1705 static void disable_rdtscp_main(void) 1706 { 1707 /* Test that #UD is properly injected in L2. */ 1708 handle_exception(UD_VECTOR, disable_rdtscp_ud_handler); 1709 1710 vmx_set_test_stage(0); 1711 asm volatile("rdtscp" : : : "eax", "ecx", "edx"); 1712 vmcall(); 1713 asm volatile(".byte 0xf3, 0x0f, 0xc7, 0xf8" : : : "eax"); 1714 vmcall(); 1715 } 1716 1717 static int disable_rdtscp_exit_handler(void) 1718 { 1719 unsigned int reason = vmcs_read(EXI_REASON) & 0xff; 1720 1721 switch (reason) { 1722 case VMX_VMCALL: 1723 switch (vmx_get_test_stage()) { 1724 case 0: 1725 report("RDTSCP triggers #UD", false); 1726 vmx_inc_test_stage(); 1727 /* fallthrough */ 1728 case 1: 1729 vmx_inc_test_stage(); 1730 vmcs_write(GUEST_RIP, vmcs_read(GUEST_RIP) + 3); 1731 return VMX_TEST_RESUME; 1732 case 2: 1733 report("RDPID triggers #UD", false); 1734 break; 1735 } 1736 break; 1737 1738 default: 1739 printf("Unknown exit reason, %d\n", reason); 1740 print_vmexit_info(); 1741 } 1742 return VMX_TEST_VMEXIT; 1743 } 1744 1745 int int3_init() 1746 { 1747 vmcs_write(EXC_BITMAP, ~0u); 1748 return VMX_TEST_START; 1749 } 1750 1751 void int3_guest_main() 1752 { 1753 asm volatile ("int3"); 1754 } 1755 1756 int int3_exit_handler() 1757 { 1758 u32 reason = vmcs_read(EXI_REASON); 1759 u32 intr_info = vmcs_read(EXI_INTR_INFO); 1760 1761 report("L1 intercepts #BP", reason == VMX_EXC_NMI && 1762 (intr_info & INTR_INFO_VALID_MASK) && 1763 (intr_info & INTR_INFO_VECTOR_MASK) == BP_VECTOR && 1764 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 1765 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION); 1766 1767 return VMX_TEST_VMEXIT; 1768 } 1769 1770 int into_init() 1771 { 1772 vmcs_write(EXC_BITMAP, ~0u); 1773 return VMX_TEST_START; 1774 } 1775 1776 void into_guest_main() 1777 { 1778 struct far_pointer32 fp = { 1779 .offset = (uintptr_t)&&into, 1780 .selector = KERNEL_CS32, 1781 }; 1782 register uintptr_t rsp asm("rsp"); 1783 1784 if (fp.offset != (uintptr_t)&&into) { 1785 printf("Code address too high.\n"); 1786 return; 1787 } 1788 if ((u32)rsp != rsp) { 1789 printf("Stack address too high.\n"); 1790 return; 1791 } 1792 1793 asm goto ("lcall *%0" : : "m" (fp) : "rax" : into); 1794 return; 1795 into: 1796 asm volatile (".code32;" 1797 "movl $0x7fffffff, %eax;" 1798 "addl %eax, %eax;" 1799 "into;" 1800 "lret;" 1801 ".code64"); 1802 __builtin_unreachable(); 1803 } 1804 1805 int into_exit_handler() 1806 { 1807 u32 reason = vmcs_read(EXI_REASON); 1808 u32 intr_info = vmcs_read(EXI_INTR_INFO); 1809 1810 report("L1 intercepts #OF", reason == VMX_EXC_NMI && 1811 (intr_info & INTR_INFO_VALID_MASK) && 1812 (intr_info & INTR_INFO_VECTOR_MASK) == OF_VECTOR && 1813 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 1814 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION); 1815 1816 return VMX_TEST_VMEXIT; 1817 } 1818 1819 /* name/init/guest_main/exit_handler/syscall_handler/guest_regs */ 1820 struct vmx_test vmx_tests[] = { 1821 { "null", NULL, basic_guest_main, basic_exit_handler, NULL, {0} }, 1822 { "vmenter", NULL, vmenter_main, vmenter_exit_handler, NULL, {0} }, 1823 { "preemption timer", preemption_timer_init, preemption_timer_main, 1824 preemption_timer_exit_handler, NULL, {0} }, 1825 { "control field PAT", test_ctrl_pat_init, test_ctrl_pat_main, 1826 test_ctrl_pat_exit_handler, NULL, {0} }, 1827 { "control field EFER", test_ctrl_efer_init, test_ctrl_efer_main, 1828 test_ctrl_efer_exit_handler, NULL, {0} }, 1829 { "CR shadowing", NULL, cr_shadowing_main, 1830 cr_shadowing_exit_handler, NULL, {0} }, 1831 { "I/O bitmap", iobmp_init, iobmp_main, iobmp_exit_handler, 1832 NULL, {0} }, 1833 { "instruction intercept", insn_intercept_init, insn_intercept_main, 1834 insn_intercept_exit_handler, NULL, {0} }, 1835 { "EPT framework", ept_init, ept_main, ept_exit_handler, NULL, {0} }, 1836 { "VPID", vpid_init, vpid_main, vpid_exit_handler, NULL, {0} }, 1837 { "interrupt", interrupt_init, interrupt_main, 1838 interrupt_exit_handler, NULL, {0} }, 1839 { "debug controls", dbgctls_init, dbgctls_main, dbgctls_exit_handler, 1840 NULL, {0} }, 1841 { "MSR switch", msr_switch_init, msr_switch_main, 1842 msr_switch_exit_handler, NULL, {0}, msr_switch_entry_failure }, 1843 { "vmmcall", vmmcall_init, vmmcall_main, vmmcall_exit_handler, NULL, {0} }, 1844 { "disable RDTSCP", disable_rdtscp_init, disable_rdtscp_main, 1845 disable_rdtscp_exit_handler, NULL, {0} }, 1846 { "int3", int3_init, int3_guest_main, int3_exit_handler, NULL, {0} }, 1847 { "into", into_init, into_guest_main, into_exit_handler, NULL, {0} }, 1848 { NULL, NULL, NULL, NULL, NULL, {0} }, 1849 }; 1850