1 /* 2 * All test cases of nested virtualization should be in this file 3 * 4 * Author : Arthur Chunqi Li <yzt356@gmail.com> 5 */ 6 7 #include <asm/debugreg.h> 8 9 #include "vmx.h" 10 #include "msr.h" 11 #include "processor.h" 12 #include "vm.h" 13 #include "pci.h" 14 #include "fwcfg.h" 15 #include "isr.h" 16 #include "desc.h" 17 #include "apic.h" 18 #include "types.h" 19 #include "vmalloc.h" 20 #include "alloc_page.h" 21 #include "smp.h" 22 #include "delay.h" 23 24 #define NONCANONICAL 0xaaaaaaaaaaaaaaaaull 25 26 #define VPID_CAP_INVVPID_TYPES_SHIFT 40 27 28 u64 ia32_pat; 29 u64 ia32_efer; 30 void *io_bitmap_a, *io_bitmap_b; 31 u16 ioport; 32 33 unsigned long *pml4; 34 u64 eptp; 35 void *data_page1, *data_page2; 36 37 phys_addr_t pci_physaddr; 38 39 void *pml_log; 40 #define PML_INDEX 512 41 42 static inline unsigned ffs(unsigned x) 43 { 44 int pos = -1; 45 46 __asm__ __volatile__("bsf %1, %%eax; cmovnz %%eax, %0" 47 : "+r"(pos) : "rm"(x) : "eax"); 48 return pos + 1; 49 } 50 51 static inline void vmcall(void) 52 { 53 asm volatile("vmcall"); 54 } 55 56 static void basic_guest_main(void) 57 { 58 report("Basic VMX test", 1); 59 } 60 61 static int basic_exit_handler(void) 62 { 63 report("Basic VMX test", 0); 64 print_vmexit_info(); 65 return VMX_TEST_EXIT; 66 } 67 68 static void vmenter_main(void) 69 { 70 u64 rax; 71 u64 rsp, resume_rsp; 72 73 report("test vmlaunch", 1); 74 75 asm volatile( 76 "mov %%rsp, %0\n\t" 77 "mov %3, %%rax\n\t" 78 "vmcall\n\t" 79 "mov %%rax, %1\n\t" 80 "mov %%rsp, %2\n\t" 81 : "=r"(rsp), "=r"(rax), "=r"(resume_rsp) 82 : "g"(0xABCD)); 83 report("test vmresume", (rax == 0xFFFF) && (rsp == resume_rsp)); 84 } 85 86 static int vmenter_exit_handler(void) 87 { 88 u64 guest_rip; 89 ulong reason; 90 91 guest_rip = vmcs_read(GUEST_RIP); 92 reason = vmcs_read(EXI_REASON) & 0xff; 93 switch (reason) { 94 case VMX_VMCALL: 95 if (regs.rax != 0xABCD) { 96 report("test vmresume", 0); 97 return VMX_TEST_VMEXIT; 98 } 99 regs.rax = 0xFFFF; 100 vmcs_write(GUEST_RIP, guest_rip + 3); 101 return VMX_TEST_RESUME; 102 default: 103 report("test vmresume", 0); 104 print_vmexit_info(); 105 } 106 return VMX_TEST_VMEXIT; 107 } 108 109 u32 preempt_scale; 110 volatile unsigned long long tsc_val; 111 volatile u32 preempt_val; 112 u64 saved_rip; 113 114 static int preemption_timer_init(struct vmcs *vmcs) 115 { 116 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 117 printf("\tPreemption timer is not supported\n"); 118 return VMX_TEST_EXIT; 119 } 120 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 121 preempt_val = 10000000; 122 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 123 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 124 125 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 126 printf("\tSave preemption value is not supported\n"); 127 128 return VMX_TEST_START; 129 } 130 131 static void preemption_timer_main(void) 132 { 133 tsc_val = rdtsc(); 134 if (ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) { 135 vmx_set_test_stage(0); 136 vmcall(); 137 if (vmx_get_test_stage() == 1) 138 vmcall(); 139 } 140 vmx_set_test_stage(1); 141 while (vmx_get_test_stage() == 1) { 142 if (((rdtsc() - tsc_val) >> preempt_scale) 143 > 10 * preempt_val) { 144 vmx_set_test_stage(2); 145 vmcall(); 146 } 147 } 148 tsc_val = rdtsc(); 149 asm volatile ("hlt"); 150 vmcall(); 151 vmx_set_test_stage(5); 152 vmcall(); 153 } 154 155 static int preemption_timer_exit_handler(void) 156 { 157 bool guest_halted; 158 u64 guest_rip; 159 ulong reason; 160 u32 insn_len; 161 u32 ctrl_exit; 162 163 guest_rip = vmcs_read(GUEST_RIP); 164 reason = vmcs_read(EXI_REASON) & 0xff; 165 insn_len = vmcs_read(EXI_INST_LEN); 166 switch (reason) { 167 case VMX_PREEMPT: 168 switch (vmx_get_test_stage()) { 169 case 1: 170 case 2: 171 report("busy-wait for preemption timer", 172 ((rdtsc() - tsc_val) >> preempt_scale) >= 173 preempt_val); 174 vmx_set_test_stage(3); 175 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 176 return VMX_TEST_RESUME; 177 case 3: 178 guest_halted = 179 (vmcs_read(GUEST_ACTV_STATE) == ACTV_HLT); 180 report("preemption timer during hlt", 181 ((rdtsc() - tsc_val) >> preempt_scale) >= 182 preempt_val && guest_halted); 183 vmx_set_test_stage(4); 184 vmcs_write(PIN_CONTROLS, 185 vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 186 vmcs_write(EXI_CONTROLS, 187 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_PREEMPT); 188 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 189 return VMX_TEST_RESUME; 190 case 4: 191 report("preemption timer with 0 value", 192 saved_rip == guest_rip); 193 break; 194 default: 195 report("Invalid stage.", false); 196 print_vmexit_info(); 197 break; 198 } 199 break; 200 case VMX_VMCALL: 201 vmcs_write(GUEST_RIP, guest_rip + insn_len); 202 switch (vmx_get_test_stage()) { 203 case 0: 204 report("Keep preemption value", 205 vmcs_read(PREEMPT_TIMER_VALUE) == preempt_val); 206 vmx_set_test_stage(1); 207 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 208 ctrl_exit = (vmcs_read(EXI_CONTROLS) | 209 EXI_SAVE_PREEMPT) & ctrl_exit_rev.clr; 210 vmcs_write(EXI_CONTROLS, ctrl_exit); 211 return VMX_TEST_RESUME; 212 case 1: 213 report("Save preemption value", 214 vmcs_read(PREEMPT_TIMER_VALUE) < preempt_val); 215 return VMX_TEST_RESUME; 216 case 2: 217 report("busy-wait for preemption timer", 0); 218 vmx_set_test_stage(3); 219 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 220 return VMX_TEST_RESUME; 221 case 3: 222 report("preemption timer during hlt", 0); 223 vmx_set_test_stage(4); 224 /* fall through */ 225 case 4: 226 vmcs_write(PIN_CONTROLS, 227 vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 228 vmcs_write(PREEMPT_TIMER_VALUE, 0); 229 saved_rip = guest_rip + insn_len; 230 return VMX_TEST_RESUME; 231 case 5: 232 report("preemption timer with 0 value (vmcall stage 5)", 0); 233 break; 234 default: 235 // Should not reach here 236 report("unexpected stage, %d", false, 237 vmx_get_test_stage()); 238 print_vmexit_info(); 239 return VMX_TEST_VMEXIT; 240 } 241 break; 242 default: 243 report("Unknown exit reason, %ld", false, reason); 244 print_vmexit_info(); 245 } 246 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 247 return VMX_TEST_VMEXIT; 248 } 249 250 static void msr_bmp_init(void) 251 { 252 void *msr_bitmap; 253 u32 ctrl_cpu0; 254 255 msr_bitmap = alloc_page(); 256 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 257 ctrl_cpu0 |= CPU_MSR_BITMAP; 258 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 259 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 260 } 261 262 static void *get_msr_bitmap(void) 263 { 264 void *msr_bitmap; 265 266 if (vmcs_read(CPU_EXEC_CTRL0) & CPU_MSR_BITMAP) { 267 msr_bitmap = (void *)vmcs_read(MSR_BITMAP); 268 } else { 269 msr_bitmap = alloc_page(); 270 memset(msr_bitmap, 0xff, PAGE_SIZE); 271 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 272 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_MSR_BITMAP); 273 } 274 275 return msr_bitmap; 276 } 277 278 static void disable_intercept_for_x2apic_msrs(void) 279 { 280 unsigned long *msr_bitmap = (unsigned long *)get_msr_bitmap(); 281 u32 msr; 282 283 for (msr = APIC_BASE_MSR; 284 msr < (APIC_BASE_MSR+0xff); 285 msr += BITS_PER_LONG) { 286 unsigned int word = msr / BITS_PER_LONG; 287 288 msr_bitmap[word] = 0; 289 msr_bitmap[word + (0x800 / sizeof(long))] = 0; 290 } 291 } 292 293 static int test_ctrl_pat_init(struct vmcs *vmcs) 294 { 295 u64 ctrl_ent; 296 u64 ctrl_exi; 297 298 msr_bmp_init(); 299 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT) && 300 !(ctrl_exit_rev.clr & EXI_LOAD_PAT) && 301 !(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 302 printf("\tSave/load PAT is not supported\n"); 303 return 1; 304 } 305 306 ctrl_ent = vmcs_read(ENT_CONTROLS); 307 ctrl_exi = vmcs_read(EXI_CONTROLS); 308 ctrl_ent |= ctrl_enter_rev.clr & ENT_LOAD_PAT; 309 ctrl_exi |= ctrl_exit_rev.clr & (EXI_SAVE_PAT | EXI_LOAD_PAT); 310 vmcs_write(ENT_CONTROLS, ctrl_ent); 311 vmcs_write(EXI_CONTROLS, ctrl_exi); 312 ia32_pat = rdmsr(MSR_IA32_CR_PAT); 313 vmcs_write(GUEST_PAT, 0x0); 314 vmcs_write(HOST_PAT, ia32_pat); 315 return VMX_TEST_START; 316 } 317 318 static void test_ctrl_pat_main(void) 319 { 320 u64 guest_ia32_pat; 321 322 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 323 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) 324 printf("\tENT_LOAD_PAT is not supported.\n"); 325 else { 326 if (guest_ia32_pat != 0) { 327 report("Entry load PAT", 0); 328 return; 329 } 330 } 331 wrmsr(MSR_IA32_CR_PAT, 0x6); 332 vmcall(); 333 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 334 if (ctrl_enter_rev.clr & ENT_LOAD_PAT) 335 report("Entry load PAT", guest_ia32_pat == ia32_pat); 336 } 337 338 static int test_ctrl_pat_exit_handler(void) 339 { 340 u64 guest_rip; 341 ulong reason; 342 u64 guest_pat; 343 344 guest_rip = vmcs_read(GUEST_RIP); 345 reason = vmcs_read(EXI_REASON) & 0xff; 346 switch (reason) { 347 case VMX_VMCALL: 348 guest_pat = vmcs_read(GUEST_PAT); 349 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT)) { 350 printf("\tEXI_SAVE_PAT is not supported\n"); 351 vmcs_write(GUEST_PAT, 0x6); 352 } else { 353 report("Exit save PAT", guest_pat == 0x6); 354 } 355 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) 356 printf("\tEXI_LOAD_PAT is not supported\n"); 357 else 358 report("Exit load PAT", rdmsr(MSR_IA32_CR_PAT) == ia32_pat); 359 vmcs_write(GUEST_PAT, ia32_pat); 360 vmcs_write(GUEST_RIP, guest_rip + 3); 361 return VMX_TEST_RESUME; 362 default: 363 printf("ERROR : Undefined exit reason, reason = %ld.\n", reason); 364 break; 365 } 366 return VMX_TEST_VMEXIT; 367 } 368 369 static int test_ctrl_efer_init(struct vmcs *vmcs) 370 { 371 u64 ctrl_ent; 372 u64 ctrl_exi; 373 374 msr_bmp_init(); 375 ctrl_ent = vmcs_read(ENT_CONTROLS) | ENT_LOAD_EFER; 376 ctrl_exi = vmcs_read(EXI_CONTROLS) | EXI_SAVE_EFER | EXI_LOAD_EFER; 377 vmcs_write(ENT_CONTROLS, ctrl_ent & ctrl_enter_rev.clr); 378 vmcs_write(EXI_CONTROLS, ctrl_exi & ctrl_exit_rev.clr); 379 ia32_efer = rdmsr(MSR_EFER); 380 vmcs_write(GUEST_EFER, ia32_efer ^ EFER_NX); 381 vmcs_write(HOST_EFER, ia32_efer ^ EFER_NX); 382 return VMX_TEST_START; 383 } 384 385 static void test_ctrl_efer_main(void) 386 { 387 u64 guest_ia32_efer; 388 389 guest_ia32_efer = rdmsr(MSR_EFER); 390 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) 391 printf("\tENT_LOAD_EFER is not supported.\n"); 392 else { 393 if (guest_ia32_efer != (ia32_efer ^ EFER_NX)) { 394 report("Entry load EFER", 0); 395 return; 396 } 397 } 398 wrmsr(MSR_EFER, ia32_efer); 399 vmcall(); 400 guest_ia32_efer = rdmsr(MSR_EFER); 401 if (ctrl_enter_rev.clr & ENT_LOAD_EFER) 402 report("Entry load EFER", guest_ia32_efer == ia32_efer); 403 } 404 405 static int test_ctrl_efer_exit_handler(void) 406 { 407 u64 guest_rip; 408 ulong reason; 409 u64 guest_efer; 410 411 guest_rip = vmcs_read(GUEST_RIP); 412 reason = vmcs_read(EXI_REASON) & 0xff; 413 switch (reason) { 414 case VMX_VMCALL: 415 guest_efer = vmcs_read(GUEST_EFER); 416 if (!(ctrl_exit_rev.clr & EXI_SAVE_EFER)) { 417 printf("\tEXI_SAVE_EFER is not supported\n"); 418 vmcs_write(GUEST_EFER, ia32_efer); 419 } else { 420 report("Exit save EFER", guest_efer == ia32_efer); 421 } 422 if (!(ctrl_exit_rev.clr & EXI_LOAD_EFER)) { 423 printf("\tEXI_LOAD_EFER is not supported\n"); 424 wrmsr(MSR_EFER, ia32_efer ^ EFER_NX); 425 } else { 426 report("Exit load EFER", rdmsr(MSR_EFER) == (ia32_efer ^ EFER_NX)); 427 } 428 vmcs_write(GUEST_PAT, ia32_efer); 429 vmcs_write(GUEST_RIP, guest_rip + 3); 430 return VMX_TEST_RESUME; 431 default: 432 printf("ERROR : Undefined exit reason, reason = %ld.\n", reason); 433 break; 434 } 435 return VMX_TEST_VMEXIT; 436 } 437 438 u32 guest_cr0, guest_cr4; 439 440 static void cr_shadowing_main(void) 441 { 442 u32 cr0, cr4, tmp; 443 444 // Test read through 445 vmx_set_test_stage(0); 446 guest_cr0 = read_cr0(); 447 if (vmx_get_test_stage() == 1) 448 report("Read through CR0", 0); 449 else 450 vmcall(); 451 vmx_set_test_stage(1); 452 guest_cr4 = read_cr4(); 453 if (vmx_get_test_stage() == 2) 454 report("Read through CR4", 0); 455 else 456 vmcall(); 457 // Test write through 458 guest_cr0 = guest_cr0 ^ (X86_CR0_TS | X86_CR0_MP); 459 guest_cr4 = guest_cr4 ^ (X86_CR4_TSD | X86_CR4_DE); 460 vmx_set_test_stage(2); 461 write_cr0(guest_cr0); 462 if (vmx_get_test_stage() == 3) 463 report("Write throuth CR0", 0); 464 else 465 vmcall(); 466 vmx_set_test_stage(3); 467 write_cr4(guest_cr4); 468 if (vmx_get_test_stage() == 4) 469 report("Write through CR4", 0); 470 else 471 vmcall(); 472 // Test read shadow 473 vmx_set_test_stage(4); 474 vmcall(); 475 cr0 = read_cr0(); 476 if (vmx_get_test_stage() != 5) 477 report("Read shadowing CR0", cr0 == guest_cr0); 478 vmx_set_test_stage(5); 479 cr4 = read_cr4(); 480 if (vmx_get_test_stage() != 6) 481 report("Read shadowing CR4", cr4 == guest_cr4); 482 // Test write shadow (same value with shadow) 483 vmx_set_test_stage(6); 484 write_cr0(guest_cr0); 485 if (vmx_get_test_stage() == 7) 486 report("Write shadowing CR0 (same value with shadow)", 0); 487 else 488 vmcall(); 489 vmx_set_test_stage(7); 490 write_cr4(guest_cr4); 491 if (vmx_get_test_stage() == 8) 492 report("Write shadowing CR4 (same value with shadow)", 0); 493 else 494 vmcall(); 495 // Test write shadow (different value) 496 vmx_set_test_stage(8); 497 tmp = guest_cr0 ^ X86_CR0_TS; 498 asm volatile("mov %0, %%rsi\n\t" 499 "mov %%rsi, %%cr0\n\t" 500 ::"m"(tmp) 501 :"rsi", "memory", "cc"); 502 report("Write shadowing different X86_CR0_TS", vmx_get_test_stage() == 9); 503 vmx_set_test_stage(9); 504 tmp = guest_cr0 ^ X86_CR0_MP; 505 asm volatile("mov %0, %%rsi\n\t" 506 "mov %%rsi, %%cr0\n\t" 507 ::"m"(tmp) 508 :"rsi", "memory", "cc"); 509 report("Write shadowing different X86_CR0_MP", vmx_get_test_stage() == 10); 510 vmx_set_test_stage(10); 511 tmp = guest_cr4 ^ X86_CR4_TSD; 512 asm volatile("mov %0, %%rsi\n\t" 513 "mov %%rsi, %%cr4\n\t" 514 ::"m"(tmp) 515 :"rsi", "memory", "cc"); 516 report("Write shadowing different X86_CR4_TSD", vmx_get_test_stage() == 11); 517 vmx_set_test_stage(11); 518 tmp = guest_cr4 ^ X86_CR4_DE; 519 asm volatile("mov %0, %%rsi\n\t" 520 "mov %%rsi, %%cr4\n\t" 521 ::"m"(tmp) 522 :"rsi", "memory", "cc"); 523 report("Write shadowing different X86_CR4_DE", vmx_get_test_stage() == 12); 524 } 525 526 static int cr_shadowing_exit_handler(void) 527 { 528 u64 guest_rip; 529 ulong reason; 530 u32 insn_len; 531 u32 exit_qual; 532 533 guest_rip = vmcs_read(GUEST_RIP); 534 reason = vmcs_read(EXI_REASON) & 0xff; 535 insn_len = vmcs_read(EXI_INST_LEN); 536 exit_qual = vmcs_read(EXI_QUALIFICATION); 537 switch (reason) { 538 case VMX_VMCALL: 539 switch (vmx_get_test_stage()) { 540 case 0: 541 report("Read through CR0", guest_cr0 == vmcs_read(GUEST_CR0)); 542 break; 543 case 1: 544 report("Read through CR4", guest_cr4 == vmcs_read(GUEST_CR4)); 545 break; 546 case 2: 547 report("Write through CR0", guest_cr0 == vmcs_read(GUEST_CR0)); 548 break; 549 case 3: 550 report("Write through CR4", guest_cr4 == vmcs_read(GUEST_CR4)); 551 break; 552 case 4: 553 guest_cr0 = vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP); 554 guest_cr4 = vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE); 555 vmcs_write(CR0_MASK, X86_CR0_TS | X86_CR0_MP); 556 vmcs_write(CR0_READ_SHADOW, guest_cr0 & (X86_CR0_TS | X86_CR0_MP)); 557 vmcs_write(CR4_MASK, X86_CR4_TSD | X86_CR4_DE); 558 vmcs_write(CR4_READ_SHADOW, guest_cr4 & (X86_CR4_TSD | X86_CR4_DE)); 559 break; 560 case 6: 561 report("Write shadowing CR0 (same value)", 562 guest_cr0 == (vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP))); 563 break; 564 case 7: 565 report("Write shadowing CR4 (same value)", 566 guest_cr4 == (vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE))); 567 break; 568 default: 569 // Should not reach here 570 report("unexpected stage, %d", false, 571 vmx_get_test_stage()); 572 print_vmexit_info(); 573 return VMX_TEST_VMEXIT; 574 } 575 vmcs_write(GUEST_RIP, guest_rip + insn_len); 576 return VMX_TEST_RESUME; 577 case VMX_CR: 578 switch (vmx_get_test_stage()) { 579 case 4: 580 report("Read shadowing CR0", 0); 581 vmx_inc_test_stage(); 582 break; 583 case 5: 584 report("Read shadowing CR4", 0); 585 vmx_inc_test_stage(); 586 break; 587 case 6: 588 report("Write shadowing CR0 (same value)", 0); 589 vmx_inc_test_stage(); 590 break; 591 case 7: 592 report("Write shadowing CR4 (same value)", 0); 593 vmx_inc_test_stage(); 594 break; 595 case 8: 596 case 9: 597 // 0x600 encodes "mov %esi, %cr0" 598 if (exit_qual == 0x600) 599 vmx_inc_test_stage(); 600 break; 601 case 10: 602 case 11: 603 // 0x604 encodes "mov %esi, %cr4" 604 if (exit_qual == 0x604) 605 vmx_inc_test_stage(); 606 break; 607 default: 608 // Should not reach here 609 report("unexpected stage, %d", false, 610 vmx_get_test_stage()); 611 print_vmexit_info(); 612 return VMX_TEST_VMEXIT; 613 } 614 vmcs_write(GUEST_RIP, guest_rip + insn_len); 615 return VMX_TEST_RESUME; 616 default: 617 report("Unknown exit reason, %ld", false, reason); 618 print_vmexit_info(); 619 } 620 return VMX_TEST_VMEXIT; 621 } 622 623 static int iobmp_init(struct vmcs *vmcs) 624 { 625 u32 ctrl_cpu0; 626 627 io_bitmap_a = alloc_page(); 628 io_bitmap_b = alloc_page(); 629 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 630 ctrl_cpu0 |= CPU_IO_BITMAP; 631 ctrl_cpu0 &= (~CPU_IO); 632 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 633 vmcs_write(IO_BITMAP_A, (u64)io_bitmap_a); 634 vmcs_write(IO_BITMAP_B, (u64)io_bitmap_b); 635 return VMX_TEST_START; 636 } 637 638 static void iobmp_main(void) 639 { 640 // stage 0, test IO pass 641 vmx_set_test_stage(0); 642 inb(0x5000); 643 outb(0x0, 0x5000); 644 report("I/O bitmap - I/O pass", vmx_get_test_stage() == 0); 645 // test IO width, in/out 646 ((u8 *)io_bitmap_a)[0] = 0xFF; 647 vmx_set_test_stage(2); 648 inb(0x0); 649 report("I/O bitmap - trap in", vmx_get_test_stage() == 3); 650 vmx_set_test_stage(3); 651 outw(0x0, 0x0); 652 report("I/O bitmap - trap out", vmx_get_test_stage() == 4); 653 vmx_set_test_stage(4); 654 inl(0x0); 655 report("I/O bitmap - I/O width, long", vmx_get_test_stage() == 5); 656 // test low/high IO port 657 vmx_set_test_stage(5); 658 ((u8 *)io_bitmap_a)[0x5000 / 8] = (1 << (0x5000 % 8)); 659 inb(0x5000); 660 report("I/O bitmap - I/O port, low part", vmx_get_test_stage() == 6); 661 vmx_set_test_stage(6); 662 ((u8 *)io_bitmap_b)[0x1000 / 8] = (1 << (0x1000 % 8)); 663 inb(0x9000); 664 report("I/O bitmap - I/O port, high part", vmx_get_test_stage() == 7); 665 // test partial pass 666 vmx_set_test_stage(7); 667 inl(0x4FFF); 668 report("I/O bitmap - partial pass", vmx_get_test_stage() == 8); 669 // test overrun 670 vmx_set_test_stage(8); 671 memset(io_bitmap_a, 0x0, PAGE_SIZE); 672 memset(io_bitmap_b, 0x0, PAGE_SIZE); 673 inl(0xFFFF); 674 report("I/O bitmap - overrun", vmx_get_test_stage() == 9); 675 vmx_set_test_stage(9); 676 vmcall(); 677 outb(0x0, 0x0); 678 report("I/O bitmap - ignore unconditional exiting", 679 vmx_get_test_stage() == 9); 680 vmx_set_test_stage(10); 681 vmcall(); 682 outb(0x0, 0x0); 683 report("I/O bitmap - unconditional exiting", 684 vmx_get_test_stage() == 11); 685 } 686 687 static int iobmp_exit_handler(void) 688 { 689 u64 guest_rip; 690 ulong reason, exit_qual; 691 u32 insn_len, ctrl_cpu0; 692 693 guest_rip = vmcs_read(GUEST_RIP); 694 reason = vmcs_read(EXI_REASON) & 0xff; 695 exit_qual = vmcs_read(EXI_QUALIFICATION); 696 insn_len = vmcs_read(EXI_INST_LEN); 697 switch (reason) { 698 case VMX_IO: 699 switch (vmx_get_test_stage()) { 700 case 0: 701 case 1: 702 vmx_inc_test_stage(); 703 break; 704 case 2: 705 report("I/O bitmap - I/O width, byte", 706 (exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_BYTE); 707 report("I/O bitmap - I/O direction, in", exit_qual & VMX_IO_IN); 708 vmx_inc_test_stage(); 709 break; 710 case 3: 711 report("I/O bitmap - I/O width, word", 712 (exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_WORD); 713 report("I/O bitmap - I/O direction, out", 714 !(exit_qual & VMX_IO_IN)); 715 vmx_inc_test_stage(); 716 break; 717 case 4: 718 report("I/O bitmap - I/O width, long", 719 (exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_LONG); 720 vmx_inc_test_stage(); 721 break; 722 case 5: 723 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x5000) 724 vmx_inc_test_stage(); 725 break; 726 case 6: 727 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x9000) 728 vmx_inc_test_stage(); 729 break; 730 case 7: 731 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x4FFF) 732 vmx_inc_test_stage(); 733 break; 734 case 8: 735 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0xFFFF) 736 vmx_inc_test_stage(); 737 break; 738 case 9: 739 case 10: 740 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 741 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0 & ~CPU_IO); 742 vmx_inc_test_stage(); 743 break; 744 default: 745 // Should not reach here 746 report("unexpected stage, %d", false, 747 vmx_get_test_stage()); 748 print_vmexit_info(); 749 return VMX_TEST_VMEXIT; 750 } 751 vmcs_write(GUEST_RIP, guest_rip + insn_len); 752 return VMX_TEST_RESUME; 753 case VMX_VMCALL: 754 switch (vmx_get_test_stage()) { 755 case 9: 756 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 757 ctrl_cpu0 |= CPU_IO | CPU_IO_BITMAP; 758 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 759 break; 760 case 10: 761 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 762 ctrl_cpu0 = (ctrl_cpu0 & ~CPU_IO_BITMAP) | CPU_IO; 763 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 764 break; 765 default: 766 // Should not reach here 767 report("unexpected stage, %d", false, 768 vmx_get_test_stage()); 769 print_vmexit_info(); 770 return VMX_TEST_VMEXIT; 771 } 772 vmcs_write(GUEST_RIP, guest_rip + insn_len); 773 return VMX_TEST_RESUME; 774 default: 775 printf("guest_rip = %#lx\n", guest_rip); 776 printf("\tERROR : Undefined exit reason, reason = %ld.\n", reason); 777 break; 778 } 779 return VMX_TEST_VMEXIT; 780 } 781 782 #define INSN_CPU0 0 783 #define INSN_CPU1 1 784 #define INSN_ALWAYS_TRAP 2 785 786 #define FIELD_EXIT_QUAL (1 << 0) 787 #define FIELD_INSN_INFO (1 << 1) 788 789 asm( 790 "insn_hlt: hlt;ret\n\t" 791 "insn_invlpg: invlpg 0x12345678;ret\n\t" 792 "insn_mwait: xor %eax, %eax; xor %ecx, %ecx; mwait;ret\n\t" 793 "insn_rdpmc: xor %ecx, %ecx; rdpmc;ret\n\t" 794 "insn_rdtsc: rdtsc;ret\n\t" 795 "insn_cr3_load: mov cr3,%rax; mov %rax,%cr3;ret\n\t" 796 "insn_cr3_store: mov %cr3,%rax;ret\n\t" 797 #ifdef __x86_64__ 798 "insn_cr8_load: xor %eax, %eax; mov %rax,%cr8;ret\n\t" 799 "insn_cr8_store: mov %cr8,%rax;ret\n\t" 800 #endif 801 "insn_monitor: xor %eax, %eax; xor %ecx, %ecx; xor %edx, %edx; monitor;ret\n\t" 802 "insn_pause: pause;ret\n\t" 803 "insn_wbinvd: wbinvd;ret\n\t" 804 "insn_cpuid: mov $10, %eax; cpuid;ret\n\t" 805 "insn_invd: invd;ret\n\t" 806 "insn_sgdt: sgdt gdt64_desc;ret\n\t" 807 "insn_lgdt: lgdt gdt64_desc;ret\n\t" 808 "insn_sidt: sidt idt_descr;ret\n\t" 809 "insn_lidt: lidt idt_descr;ret\n\t" 810 "insn_sldt: sldt %ax;ret\n\t" 811 "insn_lldt: xor %eax, %eax; lldt %ax;ret\n\t" 812 "insn_str: str %ax;ret\n\t" 813 "insn_rdrand: rdrand %rax;ret\n\t" 814 "insn_rdseed: rdseed %rax;ret\n\t" 815 ); 816 extern void insn_hlt(void); 817 extern void insn_invlpg(void); 818 extern void insn_mwait(void); 819 extern void insn_rdpmc(void); 820 extern void insn_rdtsc(void); 821 extern void insn_cr3_load(void); 822 extern void insn_cr3_store(void); 823 #ifdef __x86_64__ 824 extern void insn_cr8_load(void); 825 extern void insn_cr8_store(void); 826 #endif 827 extern void insn_monitor(void); 828 extern void insn_pause(void); 829 extern void insn_wbinvd(void); 830 extern void insn_sgdt(void); 831 extern void insn_lgdt(void); 832 extern void insn_sidt(void); 833 extern void insn_lidt(void); 834 extern void insn_sldt(void); 835 extern void insn_lldt(void); 836 extern void insn_str(void); 837 extern void insn_cpuid(void); 838 extern void insn_invd(void); 839 extern void insn_rdrand(void); 840 extern void insn_rdseed(void); 841 842 u32 cur_insn; 843 u64 cr3; 844 845 #define X86_FEATURE_MONITOR (1 << 3) 846 847 typedef bool (*supported_fn)(void); 848 849 static bool monitor_supported(void) 850 { 851 return this_cpu_has(X86_FEATURE_MWAIT); 852 } 853 854 struct insn_table { 855 const char *name; 856 u32 flag; 857 void (*insn_func)(void); 858 u32 type; 859 u32 reason; 860 ulong exit_qual; 861 u32 insn_info; 862 // Use FIELD_EXIT_QUAL and FIELD_INSN_INFO to define 863 // which field need to be tested, reason is always tested 864 u32 test_field; 865 const supported_fn supported_fn; 866 u8 disabled; 867 }; 868 869 /* 870 * Add more test cases of instruction intercept here. Elements in this 871 * table is: 872 * name/control flag/insn function/type/exit reason/exit qulification/ 873 * instruction info/field to test 874 * The last field defines which fields (exit_qual and insn_info) need to be 875 * tested in exit handler. If set to 0, only "reason" is checked. 876 */ 877 static struct insn_table insn_table[] = { 878 // Flags for Primary Processor-Based VM-Execution Controls 879 {"HLT", CPU_HLT, insn_hlt, INSN_CPU0, 12, 0, 0, 0}, 880 {"INVLPG", CPU_INVLPG, insn_invlpg, INSN_CPU0, 14, 881 0x12345678, 0, FIELD_EXIT_QUAL}, 882 {"MWAIT", CPU_MWAIT, insn_mwait, INSN_CPU0, 36, 0, 0, 0, &monitor_supported}, 883 {"RDPMC", CPU_RDPMC, insn_rdpmc, INSN_CPU0, 15, 0, 0, 0}, 884 {"RDTSC", CPU_RDTSC, insn_rdtsc, INSN_CPU0, 16, 0, 0, 0}, 885 {"CR3 load", CPU_CR3_LOAD, insn_cr3_load, INSN_CPU0, 28, 0x3, 0, 886 FIELD_EXIT_QUAL}, 887 {"CR3 store", CPU_CR3_STORE, insn_cr3_store, INSN_CPU0, 28, 0x13, 0, 888 FIELD_EXIT_QUAL}, 889 #ifdef __x86_64__ 890 {"CR8 load", CPU_CR8_LOAD, insn_cr8_load, INSN_CPU0, 28, 0x8, 0, 891 FIELD_EXIT_QUAL}, 892 {"CR8 store", CPU_CR8_STORE, insn_cr8_store, INSN_CPU0, 28, 0x18, 0, 893 FIELD_EXIT_QUAL}, 894 #endif 895 {"MONITOR", CPU_MONITOR, insn_monitor, INSN_CPU0, 39, 0, 0, 0, &monitor_supported}, 896 {"PAUSE", CPU_PAUSE, insn_pause, INSN_CPU0, 40, 0, 0, 0}, 897 // Flags for Secondary Processor-Based VM-Execution Controls 898 {"WBINVD", CPU_WBINVD, insn_wbinvd, INSN_CPU1, 54, 0, 0, 0}, 899 {"DESC_TABLE (SGDT)", CPU_DESC_TABLE, insn_sgdt, INSN_CPU1, 46, 0, 0, 0}, 900 {"DESC_TABLE (LGDT)", CPU_DESC_TABLE, insn_lgdt, INSN_CPU1, 46, 0, 0, 0}, 901 {"DESC_TABLE (SIDT)", CPU_DESC_TABLE, insn_sidt, INSN_CPU1, 46, 0, 0, 0}, 902 {"DESC_TABLE (LIDT)", CPU_DESC_TABLE, insn_lidt, INSN_CPU1, 46, 0, 0, 0}, 903 {"DESC_TABLE (SLDT)", CPU_DESC_TABLE, insn_sldt, INSN_CPU1, 47, 0, 0, 0}, 904 {"DESC_TABLE (LLDT)", CPU_DESC_TABLE, insn_lldt, INSN_CPU1, 47, 0, 0, 0}, 905 {"DESC_TABLE (STR)", CPU_DESC_TABLE, insn_str, INSN_CPU1, 47, 0, 0, 0}, 906 /* LTR causes a #GP if done with a busy selector, so it is not tested. */ 907 {"RDRAND", CPU_RDRAND, insn_rdrand, INSN_CPU1, VMX_RDRAND, 0, 0, 0}, 908 {"RDSEED", CPU_RDSEED, insn_rdseed, INSN_CPU1, VMX_RDSEED, 0, 0, 0}, 909 // Instructions always trap 910 {"CPUID", 0, insn_cpuid, INSN_ALWAYS_TRAP, 10, 0, 0, 0}, 911 {"INVD", 0, insn_invd, INSN_ALWAYS_TRAP, 13, 0, 0, 0}, 912 // Instructions never trap 913 {NULL}, 914 }; 915 916 static int insn_intercept_init(struct vmcs *vmcs) 917 { 918 u32 ctrl_cpu, cur_insn; 919 920 ctrl_cpu = ctrl_cpu_rev[0].set | CPU_SECONDARY; 921 ctrl_cpu &= ctrl_cpu_rev[0].clr; 922 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu); 923 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu_rev[1].set); 924 cr3 = read_cr3(); 925 926 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 927 if (insn_table[cur_insn].supported_fn == NULL) 928 continue; 929 insn_table[cur_insn].disabled = !insn_table[cur_insn].supported_fn(); 930 } 931 return VMX_TEST_START; 932 } 933 934 static void insn_intercept_main(void) 935 { 936 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 937 vmx_set_test_stage(cur_insn * 2); 938 if ((insn_table[cur_insn].type == INSN_CPU0 && 939 !(ctrl_cpu_rev[0].clr & insn_table[cur_insn].flag)) || 940 (insn_table[cur_insn].type == INSN_CPU1 && 941 !(ctrl_cpu_rev[1].clr & insn_table[cur_insn].flag))) { 942 printf("\tCPU_CTRL%d.CPU_%s is not supported.\n", 943 insn_table[cur_insn].type - INSN_CPU0, 944 insn_table[cur_insn].name); 945 continue; 946 } 947 948 if (insn_table[cur_insn].disabled) { 949 printf("\tFeature required for %s is not supported.\n", 950 insn_table[cur_insn].name); 951 continue; 952 } 953 954 if ((insn_table[cur_insn].type == INSN_CPU0 && 955 !(ctrl_cpu_rev[0].set & insn_table[cur_insn].flag)) || 956 (insn_table[cur_insn].type == INSN_CPU1 && 957 !(ctrl_cpu_rev[1].set & insn_table[cur_insn].flag))) { 958 /* skip hlt, it stalls the guest and is tested below */ 959 if (insn_table[cur_insn].insn_func != insn_hlt) 960 insn_table[cur_insn].insn_func(); 961 report("execute %s", vmx_get_test_stage() == cur_insn * 2, 962 insn_table[cur_insn].name); 963 } else if (insn_table[cur_insn].type != INSN_ALWAYS_TRAP) 964 printf("\tCPU_CTRL%d.CPU_%s always traps.\n", 965 insn_table[cur_insn].type - INSN_CPU0, 966 insn_table[cur_insn].name); 967 968 vmcall(); 969 970 insn_table[cur_insn].insn_func(); 971 report("intercept %s", vmx_get_test_stage() == cur_insn * 2 + 1, 972 insn_table[cur_insn].name); 973 974 vmx_set_test_stage(cur_insn * 2 + 1); 975 vmcall(); 976 } 977 } 978 979 static int insn_intercept_exit_handler(void) 980 { 981 u64 guest_rip; 982 u32 reason; 983 ulong exit_qual; 984 u32 insn_len; 985 u32 insn_info; 986 bool pass; 987 988 guest_rip = vmcs_read(GUEST_RIP); 989 reason = vmcs_read(EXI_REASON) & 0xff; 990 exit_qual = vmcs_read(EXI_QUALIFICATION); 991 insn_len = vmcs_read(EXI_INST_LEN); 992 insn_info = vmcs_read(EXI_INST_INFO); 993 994 if (reason == VMX_VMCALL) { 995 u32 val = 0; 996 997 if (insn_table[cur_insn].type == INSN_CPU0) 998 val = vmcs_read(CPU_EXEC_CTRL0); 999 else if (insn_table[cur_insn].type == INSN_CPU1) 1000 val = vmcs_read(CPU_EXEC_CTRL1); 1001 1002 if (vmx_get_test_stage() & 1) 1003 val &= ~insn_table[cur_insn].flag; 1004 else 1005 val |= insn_table[cur_insn].flag; 1006 1007 if (insn_table[cur_insn].type == INSN_CPU0) 1008 vmcs_write(CPU_EXEC_CTRL0, val | ctrl_cpu_rev[0].set); 1009 else if (insn_table[cur_insn].type == INSN_CPU1) 1010 vmcs_write(CPU_EXEC_CTRL1, val | ctrl_cpu_rev[1].set); 1011 } else { 1012 pass = (cur_insn * 2 == vmx_get_test_stage()) && 1013 insn_table[cur_insn].reason == reason; 1014 if (insn_table[cur_insn].test_field & FIELD_EXIT_QUAL && 1015 insn_table[cur_insn].exit_qual != exit_qual) 1016 pass = false; 1017 if (insn_table[cur_insn].test_field & FIELD_INSN_INFO && 1018 insn_table[cur_insn].insn_info != insn_info) 1019 pass = false; 1020 if (pass) 1021 vmx_inc_test_stage(); 1022 } 1023 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1024 return VMX_TEST_RESUME; 1025 } 1026 1027 /** 1028 * __setup_ept - Setup the VMCS fields to enable Extended Page Tables (EPT) 1029 * @hpa: Host physical address of the top-level, a.k.a. root, EPT table 1030 * @enable_ad: Whether or not to enable Access/Dirty bits for EPT entries 1031 * 1032 * Returns 0 on success, 1 on failure. 1033 * 1034 * Note that @hpa doesn't need to point at actual memory if VM-Launch is 1035 * expected to fail, e.g. setup_dummy_ept() arbitrarily passes '0' to satisfy 1036 * the various EPTP consistency checks, but doesn't ensure backing for HPA '0'. 1037 */ 1038 static int __setup_ept(u64 hpa, bool enable_ad) 1039 { 1040 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1041 !(ctrl_cpu_rev[1].clr & CPU_EPT)) { 1042 printf("\tEPT is not supported"); 1043 return 1; 1044 } 1045 if (!(ept_vpid.val & EPT_CAP_WB)) { 1046 printf("WB memtype for EPT walks not supported\n"); 1047 return 1; 1048 } 1049 if (!(ept_vpid.val & EPT_CAP_PWL4)) { 1050 printf("\tPWL4 is not supported\n"); 1051 return 1; 1052 } 1053 1054 eptp = EPT_MEM_TYPE_WB; 1055 eptp |= (3 << EPTP_PG_WALK_LEN_SHIFT); 1056 eptp |= hpa; 1057 if (enable_ad) 1058 eptp |= EPTP_AD_FLAG; 1059 1060 vmcs_write(EPTP, eptp); 1061 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0)| CPU_SECONDARY); 1062 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1)| CPU_EPT); 1063 1064 return 0; 1065 } 1066 1067 /** 1068 * setup_ept - Enable Extended Page Tables (EPT) and setup an identity map 1069 * @enable_ad: Whether or not to enable Access/Dirty bits for EPT entries 1070 * 1071 * Returns 0 on success, 1 on failure. 1072 * 1073 * This is the "real" function for setting up EPT tables, i.e. use this for 1074 * tests that need to run code in the guest with EPT enabled. 1075 */ 1076 static int setup_ept(bool enable_ad) 1077 { 1078 unsigned long end_of_memory; 1079 1080 pml4 = alloc_page(); 1081 1082 if (__setup_ept(virt_to_phys(pml4), enable_ad)) 1083 return 1; 1084 1085 end_of_memory = fwcfg_get_u64(FW_CFG_RAM_SIZE); 1086 if (end_of_memory < (1ul << 32)) 1087 end_of_memory = (1ul << 32); 1088 /* Cannot use large EPT pages if we need to track EPT 1089 * accessed/dirty bits at 4K granularity. 1090 */ 1091 setup_ept_range(pml4, 0, end_of_memory, 0, 1092 !enable_ad && ept_2m_supported(), 1093 EPT_WA | EPT_RA | EPT_EA); 1094 return 0; 1095 } 1096 1097 /** 1098 * setup_dummy_ept - Enable Extended Page Tables (EPT) with a dummy root HPA 1099 * 1100 * Setup EPT using a semi-arbitrary dummy root HPA. This function is intended 1101 * for use by tests that need EPT enabled to verify dependent VMCS controls 1102 * but never expect to fully enter the guest, i.e. don't need setup the actual 1103 * EPT tables. 1104 */ 1105 static void setup_dummy_ept(void) 1106 { 1107 if (__setup_ept(0, false)) 1108 report_abort("EPT setup unexpectedly failed"); 1109 } 1110 1111 static int enable_unrestricted_guest(void) 1112 { 1113 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1114 !(ctrl_cpu_rev[1].clr & CPU_URG) || 1115 !(ctrl_cpu_rev[1].clr & CPU_EPT)) 1116 return 1; 1117 1118 setup_dummy_ept(); 1119 1120 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 1121 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | CPU_URG); 1122 1123 return 0; 1124 } 1125 1126 static void ept_enable_ad_bits(void) 1127 { 1128 eptp |= EPTP_AD_FLAG; 1129 vmcs_write(EPTP, eptp); 1130 } 1131 1132 static void ept_disable_ad_bits(void) 1133 { 1134 eptp &= ~EPTP_AD_FLAG; 1135 vmcs_write(EPTP, eptp); 1136 } 1137 1138 static void ept_enable_ad_bits_or_skip_test(void) 1139 { 1140 if (!ept_ad_bits_supported()) 1141 test_skip("EPT AD bits not supported."); 1142 ept_enable_ad_bits(); 1143 } 1144 1145 static int apic_version; 1146 1147 static int ept_init_common(bool have_ad) 1148 { 1149 int ret; 1150 struct pci_dev pcidev; 1151 1152 if (setup_ept(have_ad)) 1153 return VMX_TEST_EXIT; 1154 data_page1 = alloc_page(); 1155 data_page2 = alloc_page(); 1156 *((u32 *)data_page1) = MAGIC_VAL_1; 1157 *((u32 *)data_page2) = MAGIC_VAL_2; 1158 install_ept(pml4, (unsigned long)data_page1, (unsigned long)data_page2, 1159 EPT_RA | EPT_WA | EPT_EA); 1160 1161 apic_version = apic_read(APIC_LVR); 1162 1163 ret = pci_find_dev(PCI_VENDOR_ID_REDHAT, PCI_DEVICE_ID_REDHAT_TEST); 1164 if (ret != PCIDEVADDR_INVALID) { 1165 pci_dev_init(&pcidev, ret); 1166 pci_physaddr = pcidev.resource[PCI_TESTDEV_BAR_MEM]; 1167 } 1168 1169 return VMX_TEST_START; 1170 } 1171 1172 static int ept_init(struct vmcs *vmcs) 1173 { 1174 return ept_init_common(false); 1175 } 1176 1177 static void ept_common(void) 1178 { 1179 vmx_set_test_stage(0); 1180 if (*((u32 *)data_page2) != MAGIC_VAL_1 || 1181 *((u32 *)data_page1) != MAGIC_VAL_1) 1182 report("EPT basic framework - read", 0); 1183 else { 1184 *((u32 *)data_page2) = MAGIC_VAL_3; 1185 vmcall(); 1186 if (vmx_get_test_stage() == 1) { 1187 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1188 *((u32 *)data_page2) == MAGIC_VAL_2) 1189 report("EPT basic framework", 1); 1190 else 1191 report("EPT basic framework - remap", 1); 1192 } 1193 } 1194 // Test EPT Misconfigurations 1195 vmx_set_test_stage(1); 1196 vmcall(); 1197 *((u32 *)data_page1) = MAGIC_VAL_1; 1198 if (vmx_get_test_stage() != 2) { 1199 report("EPT misconfigurations", 0); 1200 goto t1; 1201 } 1202 vmx_set_test_stage(2); 1203 vmcall(); 1204 *((u32 *)data_page1) = MAGIC_VAL_1; 1205 report("EPT misconfigurations", vmx_get_test_stage() == 3); 1206 t1: 1207 // Test EPT violation 1208 vmx_set_test_stage(3); 1209 vmcall(); 1210 *((u32 *)data_page1) = MAGIC_VAL_1; 1211 report("EPT violation - page permission", vmx_get_test_stage() == 4); 1212 // Violation caused by EPT paging structure 1213 vmx_set_test_stage(4); 1214 vmcall(); 1215 *((u32 *)data_page1) = MAGIC_VAL_2; 1216 report("EPT violation - paging structure", vmx_get_test_stage() == 5); 1217 1218 // MMIO Read/Write 1219 vmx_set_test_stage(5); 1220 vmcall(); 1221 1222 *(u32 volatile *)pci_physaddr; 1223 report("MMIO EPT violation - read", vmx_get_test_stage() == 6); 1224 1225 *(u32 volatile *)pci_physaddr = MAGIC_VAL_1; 1226 report("MMIO EPT violation - write", vmx_get_test_stage() == 7); 1227 } 1228 1229 static void ept_main(void) 1230 { 1231 ept_common(); 1232 1233 // Test EPT access to L1 MMIO 1234 vmx_set_test_stage(7); 1235 report("EPT - MMIO access", *((u32 *)0xfee00030UL) == apic_version); 1236 1237 // Test invalid operand for INVEPT 1238 vmcall(); 1239 report("EPT - unsupported INVEPT", vmx_get_test_stage() == 8); 1240 } 1241 1242 static bool invept_test(int type, u64 eptp) 1243 { 1244 bool ret, supported; 1245 1246 supported = ept_vpid.val & (EPT_CAP_INVEPT_SINGLE >> INVEPT_SINGLE << type); 1247 ret = invept(type, eptp); 1248 1249 if (ret == !supported) 1250 return false; 1251 1252 if (!supported) 1253 printf("WARNING: unsupported invept passed!\n"); 1254 else 1255 printf("WARNING: invept failed!\n"); 1256 1257 return true; 1258 } 1259 1260 static int pml_exit_handler(void) 1261 { 1262 u16 index, count; 1263 ulong reason = vmcs_read(EXI_REASON) & 0xff; 1264 u64 *pmlbuf = pml_log; 1265 u64 guest_rip = vmcs_read(GUEST_RIP);; 1266 u64 guest_cr3 = vmcs_read(GUEST_CR3); 1267 u32 insn_len = vmcs_read(EXI_INST_LEN); 1268 1269 switch (reason) { 1270 case VMX_VMCALL: 1271 switch (vmx_get_test_stage()) { 1272 case 0: 1273 index = vmcs_read(GUEST_PML_INDEX); 1274 for (count = index + 1; count < PML_INDEX; count++) { 1275 if (pmlbuf[count] == (u64)data_page2) { 1276 vmx_inc_test_stage(); 1277 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1278 break; 1279 } 1280 } 1281 break; 1282 case 1: 1283 index = vmcs_read(GUEST_PML_INDEX); 1284 /* Keep clearing the dirty bit till a overflow */ 1285 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1286 break; 1287 default: 1288 report("unexpected stage, %d.", false, 1289 vmx_get_test_stage()); 1290 print_vmexit_info(); 1291 return VMX_TEST_VMEXIT; 1292 } 1293 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1294 return VMX_TEST_RESUME; 1295 case VMX_PML_FULL: 1296 vmx_inc_test_stage(); 1297 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1298 return VMX_TEST_RESUME; 1299 default: 1300 report("Unknown exit reason, %ld", false, reason); 1301 print_vmexit_info(); 1302 } 1303 return VMX_TEST_VMEXIT; 1304 } 1305 1306 static int ept_exit_handler_common(bool have_ad) 1307 { 1308 u64 guest_rip; 1309 u64 guest_cr3; 1310 ulong reason; 1311 u32 insn_len; 1312 u32 exit_qual; 1313 static unsigned long data_page1_pte, data_page1_pte_pte, memaddr_pte; 1314 1315 guest_rip = vmcs_read(GUEST_RIP); 1316 guest_cr3 = vmcs_read(GUEST_CR3); 1317 reason = vmcs_read(EXI_REASON) & 0xff; 1318 insn_len = vmcs_read(EXI_INST_LEN); 1319 exit_qual = vmcs_read(EXI_QUALIFICATION); 1320 switch (reason) { 1321 case VMX_VMCALL: 1322 switch (vmx_get_test_stage()) { 1323 case 0: 1324 check_ept_ad(pml4, guest_cr3, 1325 (unsigned long)data_page1, 1326 have_ad ? EPT_ACCESS_FLAG : 0, 1327 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1328 check_ept_ad(pml4, guest_cr3, 1329 (unsigned long)data_page2, 1330 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0, 1331 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1332 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1333 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1334 if (have_ad) 1335 ept_sync(INVEPT_SINGLE, eptp);; 1336 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1337 *((u32 *)data_page2) == MAGIC_VAL_2) { 1338 vmx_inc_test_stage(); 1339 install_ept(pml4, (unsigned long)data_page2, 1340 (unsigned long)data_page2, 1341 EPT_RA | EPT_WA | EPT_EA); 1342 } else 1343 report("EPT basic framework - write", 0); 1344 break; 1345 case 1: 1346 install_ept(pml4, (unsigned long)data_page1, 1347 (unsigned long)data_page1, EPT_WA); 1348 ept_sync(INVEPT_SINGLE, eptp); 1349 break; 1350 case 2: 1351 install_ept(pml4, (unsigned long)data_page1, 1352 (unsigned long)data_page1, 1353 EPT_RA | EPT_WA | EPT_EA | 1354 (2 << EPT_MEM_TYPE_SHIFT)); 1355 ept_sync(INVEPT_SINGLE, eptp); 1356 break; 1357 case 3: 1358 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1359 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)data_page1, 1360 1, &data_page1_pte)); 1361 set_ept_pte(pml4, (unsigned long)data_page1, 1362 1, data_page1_pte & ~EPT_PRESENT); 1363 ept_sync(INVEPT_SINGLE, eptp); 1364 break; 1365 case 4: 1366 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)data_page1, 1367 2, &data_page1_pte)); 1368 data_page1_pte &= PAGE_MASK; 1369 TEST_ASSERT(get_ept_pte(pml4, data_page1_pte, 1370 2, &data_page1_pte_pte)); 1371 set_ept_pte(pml4, data_page1_pte, 2, 1372 data_page1_pte_pte & ~EPT_PRESENT); 1373 ept_sync(INVEPT_SINGLE, eptp); 1374 break; 1375 case 5: 1376 install_ept(pml4, (unsigned long)pci_physaddr, 1377 (unsigned long)pci_physaddr, 0); 1378 ept_sync(INVEPT_SINGLE, eptp); 1379 break; 1380 case 7: 1381 if (!invept_test(0, eptp)) 1382 vmx_inc_test_stage(); 1383 break; 1384 // Should not reach here 1385 default: 1386 report("ERROR - unexpected stage, %d.", false, 1387 vmx_get_test_stage()); 1388 print_vmexit_info(); 1389 return VMX_TEST_VMEXIT; 1390 } 1391 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1392 return VMX_TEST_RESUME; 1393 case VMX_EPT_MISCONFIG: 1394 switch (vmx_get_test_stage()) { 1395 case 1: 1396 case 2: 1397 vmx_inc_test_stage(); 1398 install_ept(pml4, (unsigned long)data_page1, 1399 (unsigned long)data_page1, 1400 EPT_RA | EPT_WA | EPT_EA); 1401 ept_sync(INVEPT_SINGLE, eptp); 1402 break; 1403 // Should not reach here 1404 default: 1405 report("ERROR - unexpected stage, %d.", false, 1406 vmx_get_test_stage()); 1407 print_vmexit_info(); 1408 return VMX_TEST_VMEXIT; 1409 } 1410 return VMX_TEST_RESUME; 1411 case VMX_EPT_VIOLATION: 1412 switch(vmx_get_test_stage()) { 1413 case 3: 1414 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1415 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1416 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1417 if (exit_qual == (EPT_VLT_WR | EPT_VLT_LADDR_VLD | 1418 EPT_VLT_PADDR)) 1419 vmx_inc_test_stage(); 1420 set_ept_pte(pml4, (unsigned long)data_page1, 1421 1, data_page1_pte | (EPT_PRESENT)); 1422 ept_sync(INVEPT_SINGLE, eptp); 1423 break; 1424 case 4: 1425 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1426 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1427 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1428 if (exit_qual == (EPT_VLT_RD | 1429 (have_ad ? EPT_VLT_WR : 0) | 1430 EPT_VLT_LADDR_VLD)) 1431 vmx_inc_test_stage(); 1432 set_ept_pte(pml4, data_page1_pte, 2, 1433 data_page1_pte_pte | (EPT_PRESENT)); 1434 ept_sync(INVEPT_SINGLE, eptp); 1435 break; 1436 case 5: 1437 if (exit_qual & EPT_VLT_RD) 1438 vmx_inc_test_stage(); 1439 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1440 1, &memaddr_pte)); 1441 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA); 1442 ept_sync(INVEPT_SINGLE, eptp); 1443 break; 1444 case 6: 1445 if (exit_qual & EPT_VLT_WR) 1446 vmx_inc_test_stage(); 1447 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1448 1, &memaddr_pte)); 1449 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA | EPT_WA); 1450 ept_sync(INVEPT_SINGLE, eptp); 1451 break; 1452 default: 1453 // Should not reach here 1454 report("ERROR : unexpected stage, %d", false, 1455 vmx_get_test_stage()); 1456 print_vmexit_info(); 1457 return VMX_TEST_VMEXIT; 1458 } 1459 return VMX_TEST_RESUME; 1460 default: 1461 report("Unknown exit reason, %ld", false, reason); 1462 print_vmexit_info(); 1463 } 1464 return VMX_TEST_VMEXIT; 1465 } 1466 1467 static int ept_exit_handler(void) 1468 { 1469 return ept_exit_handler_common(false); 1470 } 1471 1472 static int eptad_init(struct vmcs *vmcs) 1473 { 1474 int r = ept_init_common(true); 1475 1476 if (r == VMX_TEST_EXIT) 1477 return r; 1478 1479 if ((rdmsr(MSR_IA32_VMX_EPT_VPID_CAP) & EPT_CAP_AD_FLAG) == 0) { 1480 printf("\tEPT A/D bits are not supported"); 1481 return VMX_TEST_EXIT; 1482 } 1483 1484 return r; 1485 } 1486 1487 static int pml_init(struct vmcs *vmcs) 1488 { 1489 u32 ctrl_cpu; 1490 int r = eptad_init(vmcs); 1491 1492 if (r == VMX_TEST_EXIT) 1493 return r; 1494 1495 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1496 !(ctrl_cpu_rev[1].clr & CPU_PML)) { 1497 printf("\tPML is not supported"); 1498 return VMX_TEST_EXIT; 1499 } 1500 1501 pml_log = alloc_page(); 1502 vmcs_write(PMLADDR, (u64)pml_log); 1503 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1504 1505 ctrl_cpu = vmcs_read(CPU_EXEC_CTRL1) | CPU_PML; 1506 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu); 1507 1508 return VMX_TEST_START; 1509 } 1510 1511 static void pml_main(void) 1512 { 1513 int count = 0; 1514 1515 vmx_set_test_stage(0); 1516 *((u32 *)data_page2) = 0x1; 1517 vmcall(); 1518 report("PML - Dirty GPA Logging", vmx_get_test_stage() == 1); 1519 1520 while (vmx_get_test_stage() == 1) { 1521 vmcall(); 1522 *((u32 *)data_page2) = 0x1; 1523 if (count++ > PML_INDEX) 1524 break; 1525 } 1526 report("PML Full Event", vmx_get_test_stage() == 2); 1527 } 1528 1529 static void eptad_main(void) 1530 { 1531 ept_common(); 1532 } 1533 1534 static int eptad_exit_handler(void) 1535 { 1536 return ept_exit_handler_common(true); 1537 } 1538 1539 static bool invvpid_test(int type, u16 vpid) 1540 { 1541 bool ret, supported; 1542 1543 supported = ept_vpid.val & 1544 (VPID_CAP_INVVPID_ADDR >> INVVPID_ADDR << type); 1545 ret = invvpid(type, vpid, 0); 1546 1547 if (ret == !supported) 1548 return false; 1549 1550 if (!supported) 1551 printf("WARNING: unsupported invvpid passed!\n"); 1552 else 1553 printf("WARNING: invvpid failed!\n"); 1554 1555 return true; 1556 } 1557 1558 static int vpid_init(struct vmcs *vmcs) 1559 { 1560 u32 ctrl_cpu1; 1561 1562 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1563 !(ctrl_cpu_rev[1].clr & CPU_VPID)) { 1564 printf("\tVPID is not supported"); 1565 return VMX_TEST_EXIT; 1566 } 1567 1568 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 1569 ctrl_cpu1 |= CPU_VPID; 1570 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 1571 return VMX_TEST_START; 1572 } 1573 1574 static void vpid_main(void) 1575 { 1576 vmx_set_test_stage(0); 1577 vmcall(); 1578 report("INVVPID SINGLE ADDRESS", vmx_get_test_stage() == 1); 1579 vmx_set_test_stage(2); 1580 vmcall(); 1581 report("INVVPID SINGLE", vmx_get_test_stage() == 3); 1582 vmx_set_test_stage(4); 1583 vmcall(); 1584 report("INVVPID ALL", vmx_get_test_stage() == 5); 1585 } 1586 1587 static int vpid_exit_handler(void) 1588 { 1589 u64 guest_rip; 1590 ulong reason; 1591 u32 insn_len; 1592 1593 guest_rip = vmcs_read(GUEST_RIP); 1594 reason = vmcs_read(EXI_REASON) & 0xff; 1595 insn_len = vmcs_read(EXI_INST_LEN); 1596 1597 switch (reason) { 1598 case VMX_VMCALL: 1599 switch(vmx_get_test_stage()) { 1600 case 0: 1601 if (!invvpid_test(INVVPID_ADDR, 1)) 1602 vmx_inc_test_stage(); 1603 break; 1604 case 2: 1605 if (!invvpid_test(INVVPID_CONTEXT_GLOBAL, 1)) 1606 vmx_inc_test_stage(); 1607 break; 1608 case 4: 1609 if (!invvpid_test(INVVPID_ALL, 1)) 1610 vmx_inc_test_stage(); 1611 break; 1612 default: 1613 report("ERROR: unexpected stage, %d", false, 1614 vmx_get_test_stage()); 1615 print_vmexit_info(); 1616 return VMX_TEST_VMEXIT; 1617 } 1618 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1619 return VMX_TEST_RESUME; 1620 default: 1621 report("Unknown exit reason, %ld", false, reason); 1622 print_vmexit_info(); 1623 } 1624 return VMX_TEST_VMEXIT; 1625 } 1626 1627 #define TIMER_VECTOR 222 1628 1629 static volatile bool timer_fired; 1630 1631 static void timer_isr(isr_regs_t *regs) 1632 { 1633 timer_fired = true; 1634 apic_write(APIC_EOI, 0); 1635 } 1636 1637 static int interrupt_init(struct vmcs *vmcs) 1638 { 1639 msr_bmp_init(); 1640 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1641 handle_irq(TIMER_VECTOR, timer_isr); 1642 return VMX_TEST_START; 1643 } 1644 1645 static void interrupt_main(void) 1646 { 1647 long long start, loops; 1648 1649 vmx_set_test_stage(0); 1650 1651 apic_write(APIC_LVTT, TIMER_VECTOR); 1652 irq_enable(); 1653 1654 apic_write(APIC_TMICT, 1); 1655 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1656 asm volatile ("nop"); 1657 report("direct interrupt while running guest", timer_fired); 1658 1659 apic_write(APIC_TMICT, 0); 1660 irq_disable(); 1661 vmcall(); 1662 timer_fired = false; 1663 apic_write(APIC_TMICT, 1); 1664 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1665 asm volatile ("nop"); 1666 report("intercepted interrupt while running guest", timer_fired); 1667 1668 irq_enable(); 1669 apic_write(APIC_TMICT, 0); 1670 irq_disable(); 1671 vmcall(); 1672 timer_fired = false; 1673 start = rdtsc(); 1674 apic_write(APIC_TMICT, 1000000); 1675 1676 asm volatile ("sti; hlt"); 1677 1678 report("direct interrupt + hlt", 1679 rdtsc() - start > 1000000 && timer_fired); 1680 1681 apic_write(APIC_TMICT, 0); 1682 irq_disable(); 1683 vmcall(); 1684 timer_fired = false; 1685 start = rdtsc(); 1686 apic_write(APIC_TMICT, 1000000); 1687 1688 asm volatile ("sti; hlt"); 1689 1690 report("intercepted interrupt + hlt", 1691 rdtsc() - start > 10000 && timer_fired); 1692 1693 apic_write(APIC_TMICT, 0); 1694 irq_disable(); 1695 vmcall(); 1696 timer_fired = false; 1697 start = rdtsc(); 1698 apic_write(APIC_TMICT, 1000000); 1699 1700 irq_enable(); 1701 asm volatile ("nop"); 1702 vmcall(); 1703 1704 report("direct interrupt + activity state hlt", 1705 rdtsc() - start > 10000 && timer_fired); 1706 1707 apic_write(APIC_TMICT, 0); 1708 irq_disable(); 1709 vmcall(); 1710 timer_fired = false; 1711 start = rdtsc(); 1712 apic_write(APIC_TMICT, 1000000); 1713 1714 irq_enable(); 1715 asm volatile ("nop"); 1716 vmcall(); 1717 1718 report("intercepted interrupt + activity state hlt", 1719 rdtsc() - start > 10000 && timer_fired); 1720 1721 apic_write(APIC_TMICT, 0); 1722 irq_disable(); 1723 vmx_set_test_stage(7); 1724 vmcall(); 1725 timer_fired = false; 1726 apic_write(APIC_TMICT, 1); 1727 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1728 asm volatile ("nop"); 1729 report("running a guest with interrupt acknowledgement set", timer_fired); 1730 1731 apic_write(APIC_TMICT, 0); 1732 irq_enable(); 1733 timer_fired = false; 1734 vmcall(); 1735 report("Inject an event to a halted guest", timer_fired); 1736 } 1737 1738 static int interrupt_exit_handler(void) 1739 { 1740 u64 guest_rip = vmcs_read(GUEST_RIP); 1741 ulong reason = vmcs_read(EXI_REASON) & 0xff; 1742 u32 insn_len = vmcs_read(EXI_INST_LEN); 1743 1744 switch (reason) { 1745 case VMX_VMCALL: 1746 switch (vmx_get_test_stage()) { 1747 case 0: 1748 case 2: 1749 case 5: 1750 vmcs_write(PIN_CONTROLS, 1751 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1752 break; 1753 case 7: 1754 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_INTA); 1755 vmcs_write(PIN_CONTROLS, 1756 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1757 break; 1758 case 1: 1759 case 3: 1760 vmcs_write(PIN_CONTROLS, 1761 vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1762 break; 1763 case 4: 1764 case 6: 1765 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1766 break; 1767 1768 case 8: 1769 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1770 vmcs_write(ENT_INTR_INFO, 1771 TIMER_VECTOR | 1772 (VMX_INTR_TYPE_EXT_INTR << INTR_INFO_INTR_TYPE_SHIFT) | 1773 INTR_INFO_VALID_MASK); 1774 break; 1775 } 1776 vmx_inc_test_stage(); 1777 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1778 return VMX_TEST_RESUME; 1779 case VMX_EXTINT: 1780 if (vmcs_read(EXI_CONTROLS) & EXI_INTA) { 1781 int vector = vmcs_read(EXI_INTR_INFO) & 0xff; 1782 handle_external_interrupt(vector); 1783 } else { 1784 irq_enable(); 1785 asm volatile ("nop"); 1786 irq_disable(); 1787 } 1788 if (vmx_get_test_stage() >= 2) 1789 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 1790 return VMX_TEST_RESUME; 1791 default: 1792 report("Unknown exit reason, %ld", false, reason); 1793 print_vmexit_info(); 1794 } 1795 1796 return VMX_TEST_VMEXIT; 1797 } 1798 1799 static int dbgctls_init(struct vmcs *vmcs) 1800 { 1801 u64 dr7 = 0x402; 1802 u64 zero = 0; 1803 1804 msr_bmp_init(); 1805 asm volatile( 1806 "mov %0,%%dr0\n\t" 1807 "mov %0,%%dr1\n\t" 1808 "mov %0,%%dr2\n\t" 1809 "mov %1,%%dr7\n\t" 1810 : : "r" (zero), "r" (dr7)); 1811 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1812 vmcs_write(GUEST_DR7, 0x404); 1813 vmcs_write(GUEST_DEBUGCTL, 0x2); 1814 1815 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 1816 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_SAVE_DBGCTLS); 1817 1818 return VMX_TEST_START; 1819 } 1820 1821 static void dbgctls_main(void) 1822 { 1823 u64 dr7, debugctl; 1824 1825 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1826 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1827 /* Commented out: KVM does not support DEBUGCTL so far */ 1828 (void)debugctl; 1829 report("Load debug controls", dr7 == 0x404 /* && debugctl == 0x2 */); 1830 1831 dr7 = 0x408; 1832 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1833 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1834 1835 vmx_set_test_stage(0); 1836 vmcall(); 1837 report("Save debug controls", vmx_get_test_stage() == 1); 1838 1839 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS || 1840 ctrl_exit_rev.set & EXI_SAVE_DBGCTLS) { 1841 printf("\tDebug controls are always loaded/saved\n"); 1842 return; 1843 } 1844 vmx_set_test_stage(2); 1845 vmcall(); 1846 1847 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1848 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1849 /* Commented out: KVM does not support DEBUGCTL so far */ 1850 (void)debugctl; 1851 report("Guest=host debug controls", dr7 == 0x402 /* && debugctl == 0x1 */); 1852 1853 dr7 = 0x408; 1854 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1855 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1856 1857 vmx_set_test_stage(3); 1858 vmcall(); 1859 report("Don't save debug controls", vmx_get_test_stage() == 4); 1860 } 1861 1862 static int dbgctls_exit_handler(void) 1863 { 1864 unsigned int reason = vmcs_read(EXI_REASON) & 0xff; 1865 u32 insn_len = vmcs_read(EXI_INST_LEN); 1866 u64 guest_rip = vmcs_read(GUEST_RIP); 1867 u64 dr7, debugctl; 1868 1869 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1870 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1871 1872 switch (reason) { 1873 case VMX_VMCALL: 1874 switch (vmx_get_test_stage()) { 1875 case 0: 1876 if (dr7 == 0x400 && debugctl == 0 && 1877 vmcs_read(GUEST_DR7) == 0x408 /* && 1878 Commented out: KVM does not support DEBUGCTL so far 1879 vmcs_read(GUEST_DEBUGCTL) == 0x3 */) 1880 vmx_inc_test_stage(); 1881 break; 1882 case 2: 1883 dr7 = 0x402; 1884 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1885 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1886 vmcs_write(GUEST_DR7, 0x404); 1887 vmcs_write(GUEST_DEBUGCTL, 0x2); 1888 1889 vmcs_write(ENT_CONTROLS, 1890 vmcs_read(ENT_CONTROLS) & ~ENT_LOAD_DBGCTLS); 1891 vmcs_write(EXI_CONTROLS, 1892 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_DBGCTLS); 1893 break; 1894 case 3: 1895 if (dr7 == 0x400 && debugctl == 0 && 1896 vmcs_read(GUEST_DR7) == 0x404 /* && 1897 Commented out: KVM does not support DEBUGCTL so far 1898 vmcs_read(GUEST_DEBUGCTL) == 0x2 */) 1899 vmx_inc_test_stage(); 1900 break; 1901 } 1902 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1903 return VMX_TEST_RESUME; 1904 default: 1905 report("Unknown exit reason, %d", false, reason); 1906 print_vmexit_info(); 1907 } 1908 return VMX_TEST_VMEXIT; 1909 } 1910 1911 struct vmx_msr_entry { 1912 u32 index; 1913 u32 reserved; 1914 u64 value; 1915 } __attribute__((packed)); 1916 1917 #define MSR_MAGIC 0x31415926 1918 struct vmx_msr_entry *exit_msr_store, *entry_msr_load, *exit_msr_load; 1919 1920 static int msr_switch_init(struct vmcs *vmcs) 1921 { 1922 msr_bmp_init(); 1923 exit_msr_store = alloc_page(); 1924 exit_msr_load = alloc_page(); 1925 entry_msr_load = alloc_page(); 1926 entry_msr_load[0].index = MSR_KERNEL_GS_BASE; 1927 entry_msr_load[0].value = MSR_MAGIC; 1928 1929 vmx_set_test_stage(1); 1930 vmcs_write(ENT_MSR_LD_CNT, 1); 1931 vmcs_write(ENTER_MSR_LD_ADDR, (u64)entry_msr_load); 1932 vmcs_write(EXI_MSR_ST_CNT, 1); 1933 vmcs_write(EXIT_MSR_ST_ADDR, (u64)exit_msr_store); 1934 vmcs_write(EXI_MSR_LD_CNT, 1); 1935 vmcs_write(EXIT_MSR_LD_ADDR, (u64)exit_msr_load); 1936 return VMX_TEST_START; 1937 } 1938 1939 static void msr_switch_main(void) 1940 { 1941 if (vmx_get_test_stage() == 1) { 1942 report("VM entry MSR load", 1943 rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC); 1944 vmx_set_test_stage(2); 1945 wrmsr(MSR_KERNEL_GS_BASE, MSR_MAGIC + 1); 1946 exit_msr_store[0].index = MSR_KERNEL_GS_BASE; 1947 exit_msr_load[0].index = MSR_KERNEL_GS_BASE; 1948 exit_msr_load[0].value = MSR_MAGIC + 2; 1949 } 1950 vmcall(); 1951 } 1952 1953 static int msr_switch_exit_handler(void) 1954 { 1955 ulong reason; 1956 1957 reason = vmcs_read(EXI_REASON); 1958 if (reason == VMX_VMCALL && vmx_get_test_stage() == 2) { 1959 report("VM exit MSR store", 1960 exit_msr_store[0].value == MSR_MAGIC + 1); 1961 report("VM exit MSR load", 1962 rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC + 2); 1963 vmx_set_test_stage(3); 1964 entry_msr_load[0].index = MSR_FS_BASE; 1965 return VMX_TEST_RESUME; 1966 } 1967 printf("ERROR %s: unexpected stage=%u or reason=%lu\n", 1968 __func__, vmx_get_test_stage(), reason); 1969 return VMX_TEST_EXIT; 1970 } 1971 1972 static int msr_switch_entry_failure(struct vmentry_failure *failure) 1973 { 1974 ulong reason; 1975 1976 if (failure->early) { 1977 printf("ERROR %s: early exit\n", __func__); 1978 return VMX_TEST_EXIT; 1979 } 1980 1981 reason = vmcs_read(EXI_REASON); 1982 if (reason == (VMX_ENTRY_FAILURE | VMX_FAIL_MSR) && 1983 vmx_get_test_stage() == 3) { 1984 report("VM entry MSR load: try to load FS_BASE", 1985 vmcs_read(EXI_QUALIFICATION) == 1); 1986 return VMX_TEST_VMEXIT; 1987 } 1988 printf("ERROR %s: unexpected stage=%u or reason=%lu\n", 1989 __func__, vmx_get_test_stage(), reason); 1990 return VMX_TEST_EXIT; 1991 } 1992 1993 static int vmmcall_init(struct vmcs *vmcs) 1994 { 1995 vmcs_write(EXC_BITMAP, 1 << UD_VECTOR); 1996 return VMX_TEST_START; 1997 } 1998 1999 static void vmmcall_main(void) 2000 { 2001 asm volatile( 2002 "mov $0xABCD, %%rax\n\t" 2003 "vmmcall\n\t" 2004 ::: "rax"); 2005 2006 report("VMMCALL", 0); 2007 } 2008 2009 static int vmmcall_exit_handler(void) 2010 { 2011 ulong reason; 2012 2013 reason = vmcs_read(EXI_REASON); 2014 switch (reason) { 2015 case VMX_VMCALL: 2016 printf("here\n"); 2017 report("VMMCALL triggers #UD", 0); 2018 break; 2019 case VMX_EXC_NMI: 2020 report("VMMCALL triggers #UD", 2021 (vmcs_read(EXI_INTR_INFO) & 0xff) == UD_VECTOR); 2022 break; 2023 default: 2024 report("Unknown exit reason, %ld", false, reason); 2025 print_vmexit_info(); 2026 } 2027 2028 return VMX_TEST_VMEXIT; 2029 } 2030 2031 static int disable_rdtscp_init(struct vmcs *vmcs) 2032 { 2033 u32 ctrl_cpu1; 2034 2035 if (ctrl_cpu_rev[0].clr & CPU_SECONDARY) { 2036 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 2037 ctrl_cpu1 &= ~CPU_RDTSCP; 2038 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 2039 } 2040 2041 return VMX_TEST_START; 2042 } 2043 2044 static void disable_rdtscp_ud_handler(struct ex_regs *regs) 2045 { 2046 switch (vmx_get_test_stage()) { 2047 case 0: 2048 report("RDTSCP triggers #UD", true); 2049 vmx_inc_test_stage(); 2050 regs->rip += 3; 2051 break; 2052 case 2: 2053 report("RDPID triggers #UD", true); 2054 vmx_inc_test_stage(); 2055 regs->rip += 4; 2056 break; 2057 } 2058 return; 2059 2060 } 2061 2062 static void disable_rdtscp_main(void) 2063 { 2064 /* Test that #UD is properly injected in L2. */ 2065 handle_exception(UD_VECTOR, disable_rdtscp_ud_handler); 2066 2067 vmx_set_test_stage(0); 2068 asm volatile("rdtscp" : : : "eax", "ecx", "edx"); 2069 vmcall(); 2070 asm volatile(".byte 0xf3, 0x0f, 0xc7, 0xf8" : : : "eax"); 2071 2072 handle_exception(UD_VECTOR, 0); 2073 vmcall(); 2074 } 2075 2076 static int disable_rdtscp_exit_handler(void) 2077 { 2078 unsigned int reason = vmcs_read(EXI_REASON) & 0xff; 2079 2080 switch (reason) { 2081 case VMX_VMCALL: 2082 switch (vmx_get_test_stage()) { 2083 case 0: 2084 report("RDTSCP triggers #UD", false); 2085 vmx_inc_test_stage(); 2086 /* fallthrough */ 2087 case 1: 2088 vmx_inc_test_stage(); 2089 vmcs_write(GUEST_RIP, vmcs_read(GUEST_RIP) + 3); 2090 return VMX_TEST_RESUME; 2091 case 2: 2092 report("RDPID triggers #UD", false); 2093 break; 2094 } 2095 break; 2096 2097 default: 2098 report("Unknown exit reason, %d", false, reason); 2099 print_vmexit_info(); 2100 } 2101 return VMX_TEST_VMEXIT; 2102 } 2103 2104 static int int3_init(struct vmcs *vmcs) 2105 { 2106 vmcs_write(EXC_BITMAP, ~0u); 2107 return VMX_TEST_START; 2108 } 2109 2110 static void int3_guest_main(void) 2111 { 2112 asm volatile ("int3"); 2113 } 2114 2115 static int int3_exit_handler(void) 2116 { 2117 u32 reason = vmcs_read(EXI_REASON); 2118 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2119 2120 report("L1 intercepts #BP", reason == VMX_EXC_NMI && 2121 (intr_info & INTR_INFO_VALID_MASK) && 2122 (intr_info & INTR_INFO_VECTOR_MASK) == BP_VECTOR && 2123 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2124 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION); 2125 2126 return VMX_TEST_VMEXIT; 2127 } 2128 2129 static int into_init(struct vmcs *vmcs) 2130 { 2131 vmcs_write(EXC_BITMAP, ~0u); 2132 return VMX_TEST_START; 2133 } 2134 2135 static void into_guest_main(void) 2136 { 2137 struct far_pointer32 fp = { 2138 .offset = (uintptr_t)&&into, 2139 .selector = KERNEL_CS32, 2140 }; 2141 register uintptr_t rsp asm("rsp"); 2142 2143 if (fp.offset != (uintptr_t)&&into) { 2144 printf("Code address too high.\n"); 2145 return; 2146 } 2147 if ((u32)rsp != rsp) { 2148 printf("Stack address too high.\n"); 2149 return; 2150 } 2151 2152 asm goto ("lcall *%0" : : "m" (fp) : "rax" : into); 2153 return; 2154 into: 2155 asm volatile (".code32;" 2156 "movl $0x7fffffff, %eax;" 2157 "addl %eax, %eax;" 2158 "into;" 2159 "lret;" 2160 ".code64"); 2161 __builtin_unreachable(); 2162 } 2163 2164 static int into_exit_handler(void) 2165 { 2166 u32 reason = vmcs_read(EXI_REASON); 2167 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2168 2169 report("L1 intercepts #OF", reason == VMX_EXC_NMI && 2170 (intr_info & INTR_INFO_VALID_MASK) && 2171 (intr_info & INTR_INFO_VECTOR_MASK) == OF_VECTOR && 2172 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2173 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION); 2174 2175 return VMX_TEST_VMEXIT; 2176 } 2177 2178 static void exit_monitor_from_l2_main(void) 2179 { 2180 printf("Calling exit(0) from l2...\n"); 2181 exit(0); 2182 } 2183 2184 static int exit_monitor_from_l2_handler(void) 2185 { 2186 report("The guest should have killed the VMM", false); 2187 return VMX_TEST_EXIT; 2188 } 2189 2190 static void assert_exit_reason(u64 expected) 2191 { 2192 u64 actual = vmcs_read(EXI_REASON); 2193 2194 TEST_ASSERT_EQ_MSG(expected, actual, "Expected %s, got %s.", 2195 exit_reason_description(expected), 2196 exit_reason_description(actual)); 2197 } 2198 2199 static void skip_exit_insn(void) 2200 { 2201 u64 guest_rip = vmcs_read(GUEST_RIP); 2202 u32 insn_len = vmcs_read(EXI_INST_LEN); 2203 vmcs_write(GUEST_RIP, guest_rip + insn_len); 2204 } 2205 2206 static void skip_exit_vmcall(void) 2207 { 2208 assert_exit_reason(VMX_VMCALL); 2209 skip_exit_insn(); 2210 } 2211 2212 static void v2_null_test_guest(void) 2213 { 2214 } 2215 2216 static void v2_null_test(void) 2217 { 2218 test_set_guest(v2_null_test_guest); 2219 enter_guest(); 2220 report(__func__, 1); 2221 } 2222 2223 static void v2_multiple_entries_test_guest(void) 2224 { 2225 vmx_set_test_stage(1); 2226 vmcall(); 2227 vmx_set_test_stage(2); 2228 } 2229 2230 static void v2_multiple_entries_test(void) 2231 { 2232 test_set_guest(v2_multiple_entries_test_guest); 2233 enter_guest(); 2234 TEST_ASSERT_EQ(vmx_get_test_stage(), 1); 2235 skip_exit_vmcall(); 2236 enter_guest(); 2237 TEST_ASSERT_EQ(vmx_get_test_stage(), 2); 2238 report(__func__, 1); 2239 } 2240 2241 static int fixture_test_data = 1; 2242 2243 static void fixture_test_teardown(void *data) 2244 { 2245 *((int *) data) = 1; 2246 } 2247 2248 static void fixture_test_guest(void) 2249 { 2250 fixture_test_data++; 2251 } 2252 2253 2254 static void fixture_test_setup(void) 2255 { 2256 TEST_ASSERT_EQ_MSG(1, fixture_test_data, 2257 "fixture_test_teardown didn't run?!"); 2258 fixture_test_data = 2; 2259 test_add_teardown(fixture_test_teardown, &fixture_test_data); 2260 test_set_guest(fixture_test_guest); 2261 } 2262 2263 static void fixture_test_case1(void) 2264 { 2265 fixture_test_setup(); 2266 TEST_ASSERT_EQ(2, fixture_test_data); 2267 enter_guest(); 2268 TEST_ASSERT_EQ(3, fixture_test_data); 2269 report(__func__, 1); 2270 } 2271 2272 static void fixture_test_case2(void) 2273 { 2274 fixture_test_setup(); 2275 TEST_ASSERT_EQ(2, fixture_test_data); 2276 enter_guest(); 2277 TEST_ASSERT_EQ(3, fixture_test_data); 2278 report(__func__, 1); 2279 } 2280 2281 enum ept_access_op { 2282 OP_READ, 2283 OP_WRITE, 2284 OP_EXEC, 2285 OP_FLUSH_TLB, 2286 OP_EXIT, 2287 }; 2288 2289 static struct ept_access_test_data { 2290 unsigned long gpa; 2291 unsigned long *gva; 2292 unsigned long hpa; 2293 unsigned long *hva; 2294 enum ept_access_op op; 2295 } ept_access_test_data; 2296 2297 extern unsigned char ret42_start; 2298 extern unsigned char ret42_end; 2299 2300 /* Returns 42. */ 2301 asm( 2302 ".align 64\n" 2303 "ret42_start:\n" 2304 "mov $42, %eax\n" 2305 "ret\n" 2306 "ret42_end:\n" 2307 ); 2308 2309 static void 2310 diagnose_ept_violation_qual(u64 expected, u64 actual) 2311 { 2312 2313 #define DIAGNOSE(flag) \ 2314 do { \ 2315 if ((expected & flag) != (actual & flag)) \ 2316 printf(#flag " %sexpected\n", \ 2317 (expected & flag) ? "" : "un"); \ 2318 } while (0) 2319 2320 DIAGNOSE(EPT_VLT_RD); 2321 DIAGNOSE(EPT_VLT_WR); 2322 DIAGNOSE(EPT_VLT_FETCH); 2323 DIAGNOSE(EPT_VLT_PERM_RD); 2324 DIAGNOSE(EPT_VLT_PERM_WR); 2325 DIAGNOSE(EPT_VLT_PERM_EX); 2326 DIAGNOSE(EPT_VLT_LADDR_VLD); 2327 DIAGNOSE(EPT_VLT_PADDR); 2328 2329 #undef DIAGNOSE 2330 } 2331 2332 static void do_ept_access_op(enum ept_access_op op) 2333 { 2334 ept_access_test_data.op = op; 2335 enter_guest(); 2336 } 2337 2338 /* 2339 * Force the guest to flush its TLB (i.e., flush gva -> gpa mappings). Only 2340 * needed by tests that modify guest PTEs. 2341 */ 2342 static void ept_access_test_guest_flush_tlb(void) 2343 { 2344 do_ept_access_op(OP_FLUSH_TLB); 2345 skip_exit_vmcall(); 2346 } 2347 2348 /* 2349 * Modifies the EPT entry at @level in the mapping of @gpa. First clears the 2350 * bits in @clear then sets the bits in @set. @mkhuge transforms the entry into 2351 * a huge page. 2352 */ 2353 static unsigned long ept_twiddle(unsigned long gpa, bool mkhuge, int level, 2354 unsigned long clear, unsigned long set) 2355 { 2356 struct ept_access_test_data *data = &ept_access_test_data; 2357 unsigned long orig_pte; 2358 unsigned long pte; 2359 2360 /* Screw with the mapping at the requested level. */ 2361 TEST_ASSERT(get_ept_pte(pml4, gpa, level, &orig_pte)); 2362 pte = orig_pte; 2363 if (mkhuge) 2364 pte = (orig_pte & ~EPT_ADDR_MASK) | data->hpa | EPT_LARGE_PAGE; 2365 else 2366 pte = orig_pte; 2367 pte = (pte & ~clear) | set; 2368 set_ept_pte(pml4, gpa, level, pte); 2369 ept_sync(INVEPT_SINGLE, eptp); 2370 2371 return orig_pte; 2372 } 2373 2374 static void ept_untwiddle(unsigned long gpa, int level, unsigned long orig_pte) 2375 { 2376 set_ept_pte(pml4, gpa, level, orig_pte); 2377 } 2378 2379 static void do_ept_violation(bool leaf, enum ept_access_op op, 2380 u64 expected_qual, u64 expected_paddr) 2381 { 2382 u64 qual; 2383 2384 /* Try the access and observe the violation. */ 2385 do_ept_access_op(op); 2386 2387 assert_exit_reason(VMX_EPT_VIOLATION); 2388 2389 qual = vmcs_read(EXI_QUALIFICATION); 2390 2391 /* Mask undefined bits (which may later be defined in certain cases). */ 2392 qual &= ~(EPT_VLT_GUEST_USER | EPT_VLT_GUEST_RW | EPT_VLT_GUEST_EX | 2393 EPT_VLT_PERM_USER_EX); 2394 2395 diagnose_ept_violation_qual(expected_qual, qual); 2396 TEST_EXPECT_EQ(expected_qual, qual); 2397 2398 #if 0 2399 /* Disable for now otherwise every test will fail */ 2400 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2401 (unsigned long) ( 2402 op == OP_EXEC ? data->gva + 1 : data->gva)); 2403 #endif 2404 /* 2405 * TODO: tests that probe expected_paddr in pages other than the one at 2406 * the beginning of the 1g region. 2407 */ 2408 TEST_EXPECT_EQ(vmcs_read(INFO_PHYS_ADDR), expected_paddr); 2409 } 2410 2411 static void 2412 ept_violation_at_level_mkhuge(bool mkhuge, int level, unsigned long clear, 2413 unsigned long set, enum ept_access_op op, 2414 u64 expected_qual) 2415 { 2416 struct ept_access_test_data *data = &ept_access_test_data; 2417 unsigned long orig_pte; 2418 2419 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2420 2421 do_ept_violation(level == 1 || mkhuge, op, expected_qual, 2422 op == OP_EXEC ? data->gpa + sizeof(unsigned long) : 2423 data->gpa); 2424 2425 /* Fix the violation and resume the op loop. */ 2426 ept_untwiddle(data->gpa, level, orig_pte); 2427 enter_guest(); 2428 skip_exit_vmcall(); 2429 } 2430 2431 static void 2432 ept_violation_at_level(int level, unsigned long clear, unsigned long set, 2433 enum ept_access_op op, u64 expected_qual) 2434 { 2435 ept_violation_at_level_mkhuge(false, level, clear, set, op, 2436 expected_qual); 2437 if (ept_huge_pages_supported(level)) 2438 ept_violation_at_level_mkhuge(true, level, clear, set, op, 2439 expected_qual); 2440 } 2441 2442 static void ept_violation(unsigned long clear, unsigned long set, 2443 enum ept_access_op op, u64 expected_qual) 2444 { 2445 ept_violation_at_level(1, clear, set, op, expected_qual); 2446 ept_violation_at_level(2, clear, set, op, expected_qual); 2447 ept_violation_at_level(3, clear, set, op, expected_qual); 2448 ept_violation_at_level(4, clear, set, op, expected_qual); 2449 } 2450 2451 static void ept_access_violation(unsigned long access, enum ept_access_op op, 2452 u64 expected_qual) 2453 { 2454 ept_violation(EPT_PRESENT, access, op, 2455 expected_qual | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2456 } 2457 2458 /* 2459 * For translations that don't involve a GVA, that is physical address (paddr) 2460 * accesses, EPT violations don't set the flag EPT_VLT_PADDR. For a typical 2461 * guest memory access, the hardware does GVA -> GPA -> HPA. However, certain 2462 * translations don't involve GVAs, such as when the hardware does the guest 2463 * page table walk. For example, in translating GVA_1 -> GPA_1, the guest MMU 2464 * might try to set an A bit on a guest PTE. If the GPA_2 that the PTE resides 2465 * on isn't present in the EPT, then the EPT violation will be for GPA_2 and 2466 * the EPT_VLT_PADDR bit will be clear in the exit qualification. 2467 * 2468 * Note that paddr violations can also be triggered by loading PAE page tables 2469 * with wonky addresses. We don't test that yet. 2470 * 2471 * This function modifies the EPT entry that maps the GPA that the guest page 2472 * table entry mapping ept_access_data.gva resides on. 2473 * 2474 * @ept_access EPT permissions to set. Other permissions are cleared. 2475 * 2476 * @pte_ad Set the A/D bits on the guest PTE accordingly. 2477 * 2478 * @op Guest operation to perform with ept_access_data.gva. 2479 * 2480 * @expect_violation 2481 * Is a violation expected during the paddr access? 2482 * 2483 * @expected_qual Expected qualification for the EPT violation. 2484 * EPT_VLT_PADDR should be clear. 2485 */ 2486 static void ept_access_paddr(unsigned long ept_access, unsigned long pte_ad, 2487 enum ept_access_op op, bool expect_violation, 2488 u64 expected_qual) 2489 { 2490 struct ept_access_test_data *data = &ept_access_test_data; 2491 unsigned long *ptep; 2492 unsigned long gpa; 2493 unsigned long orig_epte; 2494 2495 /* Modify the guest PTE mapping data->gva according to @pte_ad. */ 2496 ptep = get_pte_level(current_page_table(), data->gva, /*level=*/1); 2497 TEST_ASSERT(ptep); 2498 TEST_ASSERT_EQ(*ptep & PT_ADDR_MASK, data->gpa); 2499 *ptep = (*ptep & ~PT_AD_MASK) | pte_ad; 2500 ept_access_test_guest_flush_tlb(); 2501 2502 /* 2503 * Now modify the access bits on the EPT entry for the GPA that the 2504 * guest PTE resides on. Note that by modifying a single EPT entry, 2505 * we're potentially affecting 512 guest PTEs. However, we've carefully 2506 * constructed our test such that those other 511 PTEs aren't used by 2507 * the guest: data->gva is at the beginning of a 1G huge page, thus the 2508 * PTE we're modifying is at the beginning of a 4K page and the 2509 * following 511 entires are also under our control (and not touched by 2510 * the guest). 2511 */ 2512 gpa = virt_to_phys(ptep); 2513 TEST_ASSERT_EQ(gpa & ~PAGE_MASK, 0); 2514 /* 2515 * Make sure the guest page table page is mapped with a 4K EPT entry, 2516 * otherwise our level=1 twiddling below will fail. We use the 2517 * identity map (gpa = gpa) since page tables are shared with the host. 2518 */ 2519 install_ept(pml4, gpa, gpa, EPT_PRESENT); 2520 orig_epte = ept_twiddle(gpa, /*mkhuge=*/0, /*level=*/1, 2521 /*clear=*/EPT_PRESENT, /*set=*/ept_access); 2522 2523 if (expect_violation) { 2524 do_ept_violation(/*leaf=*/true, op, 2525 expected_qual | EPT_VLT_LADDR_VLD, gpa); 2526 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2527 do_ept_access_op(op); 2528 } else { 2529 do_ept_access_op(op); 2530 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2531 } 2532 2533 TEST_ASSERT(*ptep & PT_ACCESSED_MASK); 2534 if ((pte_ad & PT_DIRTY_MASK) || op == OP_WRITE) 2535 TEST_ASSERT(*ptep & PT_DIRTY_MASK); 2536 2537 skip_exit_vmcall(); 2538 } 2539 2540 static void ept_access_allowed_paddr(unsigned long ept_access, 2541 unsigned long pte_ad, 2542 enum ept_access_op op) 2543 { 2544 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/false, 2545 /*expected_qual=*/-1); 2546 } 2547 2548 static void ept_access_violation_paddr(unsigned long ept_access, 2549 unsigned long pte_ad, 2550 enum ept_access_op op, 2551 u64 expected_qual) 2552 { 2553 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/true, 2554 expected_qual); 2555 } 2556 2557 2558 static void ept_allowed_at_level_mkhuge(bool mkhuge, int level, 2559 unsigned long clear, 2560 unsigned long set, 2561 enum ept_access_op op) 2562 { 2563 struct ept_access_test_data *data = &ept_access_test_data; 2564 unsigned long orig_pte; 2565 2566 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2567 2568 /* No violation. Should proceed to vmcall. */ 2569 do_ept_access_op(op); 2570 skip_exit_vmcall(); 2571 2572 ept_untwiddle(data->gpa, level, orig_pte); 2573 } 2574 2575 static void ept_allowed_at_level(int level, unsigned long clear, 2576 unsigned long set, enum ept_access_op op) 2577 { 2578 ept_allowed_at_level_mkhuge(false, level, clear, set, op); 2579 if (ept_huge_pages_supported(level)) 2580 ept_allowed_at_level_mkhuge(true, level, clear, set, op); 2581 } 2582 2583 static void ept_allowed(unsigned long clear, unsigned long set, 2584 enum ept_access_op op) 2585 { 2586 ept_allowed_at_level(1, clear, set, op); 2587 ept_allowed_at_level(2, clear, set, op); 2588 ept_allowed_at_level(3, clear, set, op); 2589 ept_allowed_at_level(4, clear, set, op); 2590 } 2591 2592 static void ept_ignored_bit(int bit) 2593 { 2594 /* Set the bit. */ 2595 ept_allowed(0, 1ul << bit, OP_READ); 2596 ept_allowed(0, 1ul << bit, OP_WRITE); 2597 ept_allowed(0, 1ul << bit, OP_EXEC); 2598 2599 /* Clear the bit. */ 2600 ept_allowed(1ul << bit, 0, OP_READ); 2601 ept_allowed(1ul << bit, 0, OP_WRITE); 2602 ept_allowed(1ul << bit, 0, OP_EXEC); 2603 } 2604 2605 static void ept_access_allowed(unsigned long access, enum ept_access_op op) 2606 { 2607 ept_allowed(EPT_PRESENT, access, op); 2608 } 2609 2610 2611 static void ept_misconfig_at_level_mkhuge_op(bool mkhuge, int level, 2612 unsigned long clear, 2613 unsigned long set, 2614 enum ept_access_op op) 2615 { 2616 struct ept_access_test_data *data = &ept_access_test_data; 2617 unsigned long orig_pte; 2618 2619 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2620 2621 do_ept_access_op(op); 2622 assert_exit_reason(VMX_EPT_MISCONFIG); 2623 2624 /* Intel 27.2.1, "For all other VM exits, this field is cleared." */ 2625 #if 0 2626 /* broken: */ 2627 TEST_EXPECT_EQ_MSG(vmcs_read(EXI_QUALIFICATION), 0); 2628 #endif 2629 #if 0 2630 /* 2631 * broken: 2632 * According to description of exit qual for EPT violation, 2633 * EPT_VLT_LADDR_VLD indicates if GUEST_LINEAR_ADDRESS is valid. 2634 * However, I can't find anything that says GUEST_LINEAR_ADDRESS ought 2635 * to be set for msiconfig. 2636 */ 2637 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2638 (unsigned long) ( 2639 op == OP_EXEC ? data->gva + 1 : data->gva)); 2640 #endif 2641 2642 /* Fix the violation and resume the op loop. */ 2643 ept_untwiddle(data->gpa, level, orig_pte); 2644 enter_guest(); 2645 skip_exit_vmcall(); 2646 } 2647 2648 static void ept_misconfig_at_level_mkhuge(bool mkhuge, int level, 2649 unsigned long clear, 2650 unsigned long set) 2651 { 2652 /* The op shouldn't matter (read, write, exec), so try them all! */ 2653 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_READ); 2654 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_WRITE); 2655 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_EXEC); 2656 } 2657 2658 static void ept_misconfig_at_level(int level, unsigned long clear, 2659 unsigned long set) 2660 { 2661 ept_misconfig_at_level_mkhuge(false, level, clear, set); 2662 if (ept_huge_pages_supported(level)) 2663 ept_misconfig_at_level_mkhuge(true, level, clear, set); 2664 } 2665 2666 static void ept_misconfig(unsigned long clear, unsigned long set) 2667 { 2668 ept_misconfig_at_level(1, clear, set); 2669 ept_misconfig_at_level(2, clear, set); 2670 ept_misconfig_at_level(3, clear, set); 2671 ept_misconfig_at_level(4, clear, set); 2672 } 2673 2674 static void ept_access_misconfig(unsigned long access) 2675 { 2676 ept_misconfig(EPT_PRESENT, access); 2677 } 2678 2679 static void ept_reserved_bit_at_level_nohuge(int level, int bit) 2680 { 2681 /* Setting the bit causes a misconfig. */ 2682 ept_misconfig_at_level_mkhuge(false, level, 0, 1ul << bit); 2683 2684 /* Making the entry non-present turns reserved bits into ignored. */ 2685 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2686 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2687 } 2688 2689 static void ept_reserved_bit_at_level_huge(int level, int bit) 2690 { 2691 /* Setting the bit causes a misconfig. */ 2692 ept_misconfig_at_level_mkhuge(true, level, 0, 1ul << bit); 2693 2694 /* Making the entry non-present turns reserved bits into ignored. */ 2695 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2696 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2697 } 2698 2699 static void ept_reserved_bit_at_level(int level, int bit) 2700 { 2701 /* Setting the bit causes a misconfig. */ 2702 ept_misconfig_at_level(level, 0, 1ul << bit); 2703 2704 /* Making the entry non-present turns reserved bits into ignored. */ 2705 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2706 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2707 } 2708 2709 static void ept_reserved_bit(int bit) 2710 { 2711 ept_reserved_bit_at_level(1, bit); 2712 ept_reserved_bit_at_level(2, bit); 2713 ept_reserved_bit_at_level(3, bit); 2714 ept_reserved_bit_at_level(4, bit); 2715 } 2716 2717 #define PAGE_2M_ORDER 9 2718 #define PAGE_1G_ORDER 18 2719 2720 static void *get_1g_page(void) 2721 { 2722 static void *alloc; 2723 2724 if (!alloc) 2725 alloc = alloc_pages(PAGE_1G_ORDER); 2726 return alloc; 2727 } 2728 2729 static void ept_access_test_teardown(void *unused) 2730 { 2731 /* Exit the guest cleanly. */ 2732 do_ept_access_op(OP_EXIT); 2733 } 2734 2735 static void ept_access_test_guest(void) 2736 { 2737 struct ept_access_test_data *data = &ept_access_test_data; 2738 int (*code)(void) = (int (*)(void)) &data->gva[1]; 2739 2740 while (true) { 2741 switch (data->op) { 2742 case OP_READ: 2743 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_1); 2744 break; 2745 case OP_WRITE: 2746 *data->gva = MAGIC_VAL_2; 2747 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_2); 2748 *data->gva = MAGIC_VAL_1; 2749 break; 2750 case OP_EXEC: 2751 TEST_ASSERT_EQ(42, code()); 2752 break; 2753 case OP_FLUSH_TLB: 2754 write_cr3(read_cr3()); 2755 break; 2756 case OP_EXIT: 2757 return; 2758 default: 2759 TEST_ASSERT_MSG(false, "Unknown op %d", data->op); 2760 } 2761 vmcall(); 2762 } 2763 } 2764 2765 static void ept_access_test_setup(void) 2766 { 2767 struct ept_access_test_data *data = &ept_access_test_data; 2768 unsigned long npages = 1ul << PAGE_1G_ORDER; 2769 unsigned long size = npages * PAGE_SIZE; 2770 unsigned long *page_table = current_page_table(); 2771 unsigned long pte; 2772 2773 if (setup_ept(false)) 2774 test_skip("EPT not supported"); 2775 2776 /* We use data->gpa = 1 << 39 so that test data has a separate pml4 entry */ 2777 if (cpuid_maxphyaddr() < 40) 2778 test_skip("Test needs MAXPHYADDR >= 40"); 2779 2780 test_set_guest(ept_access_test_guest); 2781 test_add_teardown(ept_access_test_teardown, NULL); 2782 2783 data->hva = get_1g_page(); 2784 TEST_ASSERT(data->hva); 2785 data->hpa = virt_to_phys(data->hva); 2786 2787 data->gpa = 1ul << 39; 2788 data->gva = (void *) ALIGN((unsigned long) alloc_vpages(npages * 2), 2789 size); 2790 TEST_ASSERT(!any_present_pages(page_table, data->gva, size)); 2791 install_pages(page_table, data->gpa, size, data->gva); 2792 2793 /* 2794 * Make sure nothing's mapped here so the tests that screw with the 2795 * pml4 entry don't inadvertently break something. 2796 */ 2797 TEST_ASSERT(get_ept_pte(pml4, data->gpa, 4, &pte) && pte == 0); 2798 TEST_ASSERT(get_ept_pte(pml4, data->gpa + size - 1, 4, &pte) && pte == 0); 2799 install_ept(pml4, data->hpa, data->gpa, EPT_PRESENT); 2800 2801 data->hva[0] = MAGIC_VAL_1; 2802 memcpy(&data->hva[1], &ret42_start, &ret42_end - &ret42_start); 2803 } 2804 2805 static void ept_access_test_not_present(void) 2806 { 2807 ept_access_test_setup(); 2808 /* --- */ 2809 ept_access_violation(0, OP_READ, EPT_VLT_RD); 2810 ept_access_violation(0, OP_WRITE, EPT_VLT_WR); 2811 ept_access_violation(0, OP_EXEC, EPT_VLT_FETCH); 2812 } 2813 2814 static void ept_access_test_read_only(void) 2815 { 2816 ept_access_test_setup(); 2817 2818 /* r-- */ 2819 ept_access_allowed(EPT_RA, OP_READ); 2820 ept_access_violation(EPT_RA, OP_WRITE, EPT_VLT_WR | EPT_VLT_PERM_RD); 2821 ept_access_violation(EPT_RA, OP_EXEC, EPT_VLT_FETCH | EPT_VLT_PERM_RD); 2822 } 2823 2824 static void ept_access_test_write_only(void) 2825 { 2826 ept_access_test_setup(); 2827 /* -w- */ 2828 ept_access_misconfig(EPT_WA); 2829 } 2830 2831 static void ept_access_test_read_write(void) 2832 { 2833 ept_access_test_setup(); 2834 /* rw- */ 2835 ept_access_allowed(EPT_RA | EPT_WA, OP_READ); 2836 ept_access_allowed(EPT_RA | EPT_WA, OP_WRITE); 2837 ept_access_violation(EPT_RA | EPT_WA, OP_EXEC, 2838 EPT_VLT_FETCH | EPT_VLT_PERM_RD | EPT_VLT_PERM_WR); 2839 } 2840 2841 2842 static void ept_access_test_execute_only(void) 2843 { 2844 ept_access_test_setup(); 2845 /* --x */ 2846 if (ept_execute_only_supported()) { 2847 ept_access_violation(EPT_EA, OP_READ, 2848 EPT_VLT_RD | EPT_VLT_PERM_EX); 2849 ept_access_violation(EPT_EA, OP_WRITE, 2850 EPT_VLT_WR | EPT_VLT_PERM_EX); 2851 ept_access_allowed(EPT_EA, OP_EXEC); 2852 } else { 2853 ept_access_misconfig(EPT_EA); 2854 } 2855 } 2856 2857 static void ept_access_test_read_execute(void) 2858 { 2859 ept_access_test_setup(); 2860 /* r-x */ 2861 ept_access_allowed(EPT_RA | EPT_EA, OP_READ); 2862 ept_access_violation(EPT_RA | EPT_EA, OP_WRITE, 2863 EPT_VLT_WR | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX); 2864 ept_access_allowed(EPT_RA | EPT_EA, OP_EXEC); 2865 } 2866 2867 static void ept_access_test_write_execute(void) 2868 { 2869 ept_access_test_setup(); 2870 /* -wx */ 2871 ept_access_misconfig(EPT_WA | EPT_EA); 2872 } 2873 2874 static void ept_access_test_read_write_execute(void) 2875 { 2876 ept_access_test_setup(); 2877 /* rwx */ 2878 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_READ); 2879 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_WRITE); 2880 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_EXEC); 2881 } 2882 2883 static void ept_access_test_reserved_bits(void) 2884 { 2885 int i; 2886 int maxphyaddr; 2887 2888 ept_access_test_setup(); 2889 2890 /* Reserved bits above maxphyaddr. */ 2891 maxphyaddr = cpuid_maxphyaddr(); 2892 for (i = maxphyaddr; i <= 51; i++) { 2893 report_prefix_pushf("reserved_bit=%d", i); 2894 ept_reserved_bit(i); 2895 report_prefix_pop(); 2896 } 2897 2898 /* Level-specific reserved bits. */ 2899 ept_reserved_bit_at_level_nohuge(2, 3); 2900 ept_reserved_bit_at_level_nohuge(2, 4); 2901 ept_reserved_bit_at_level_nohuge(2, 5); 2902 ept_reserved_bit_at_level_nohuge(2, 6); 2903 /* 2M alignment. */ 2904 for (i = 12; i < 20; i++) { 2905 report_prefix_pushf("reserved_bit=%d", i); 2906 ept_reserved_bit_at_level_huge(2, i); 2907 report_prefix_pop(); 2908 } 2909 ept_reserved_bit_at_level_nohuge(3, 3); 2910 ept_reserved_bit_at_level_nohuge(3, 4); 2911 ept_reserved_bit_at_level_nohuge(3, 5); 2912 ept_reserved_bit_at_level_nohuge(3, 6); 2913 /* 1G alignment. */ 2914 for (i = 12; i < 29; i++) { 2915 report_prefix_pushf("reserved_bit=%d", i); 2916 ept_reserved_bit_at_level_huge(3, i); 2917 report_prefix_pop(); 2918 } 2919 ept_reserved_bit_at_level(4, 3); 2920 ept_reserved_bit_at_level(4, 4); 2921 ept_reserved_bit_at_level(4, 5); 2922 ept_reserved_bit_at_level(4, 6); 2923 ept_reserved_bit_at_level(4, 7); 2924 } 2925 2926 static void ept_access_test_ignored_bits(void) 2927 { 2928 ept_access_test_setup(); 2929 /* 2930 * Bits ignored at every level. Bits 8 and 9 (A and D) are ignored as 2931 * far as translation is concerned even if AD bits are enabled in the 2932 * EPTP. Bit 63 is ignored because "EPT-violation #VE" VM-execution 2933 * control is 0. 2934 */ 2935 ept_ignored_bit(8); 2936 ept_ignored_bit(9); 2937 ept_ignored_bit(10); 2938 ept_ignored_bit(11); 2939 ept_ignored_bit(52); 2940 ept_ignored_bit(53); 2941 ept_ignored_bit(54); 2942 ept_ignored_bit(55); 2943 ept_ignored_bit(56); 2944 ept_ignored_bit(57); 2945 ept_ignored_bit(58); 2946 ept_ignored_bit(59); 2947 ept_ignored_bit(60); 2948 ept_ignored_bit(61); 2949 ept_ignored_bit(62); 2950 ept_ignored_bit(63); 2951 } 2952 2953 static void ept_access_test_paddr_not_present_ad_disabled(void) 2954 { 2955 ept_access_test_setup(); 2956 ept_disable_ad_bits(); 2957 2958 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, EPT_VLT_RD); 2959 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, EPT_VLT_RD); 2960 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, EPT_VLT_RD); 2961 } 2962 2963 static void ept_access_test_paddr_not_present_ad_enabled(void) 2964 { 2965 u64 qual = EPT_VLT_RD | EPT_VLT_WR; 2966 2967 ept_access_test_setup(); 2968 ept_enable_ad_bits_or_skip_test(); 2969 2970 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, qual); 2971 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, qual); 2972 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, qual); 2973 } 2974 2975 static void ept_access_test_paddr_read_only_ad_disabled(void) 2976 { 2977 /* 2978 * When EPT AD bits are disabled, all accesses to guest paging 2979 * structures are reported separately as a read and (after 2980 * translation of the GPA to host physical address) a read+write 2981 * if the A/D bits have to be set. 2982 */ 2983 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 2984 2985 ept_access_test_setup(); 2986 ept_disable_ad_bits(); 2987 2988 /* Can't update A bit, so all accesses fail. */ 2989 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 2990 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 2991 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 2992 /* AD bits disabled, so only writes try to update the D bit. */ 2993 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ); 2994 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 2995 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC); 2996 /* Both A and D already set, so read-only is OK. */ 2997 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_READ); 2998 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_WRITE); 2999 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_EXEC); 3000 } 3001 3002 static void ept_access_test_paddr_read_only_ad_enabled(void) 3003 { 3004 /* 3005 * When EPT AD bits are enabled, all accesses to guest paging 3006 * structures are considered writes as far as EPT translation 3007 * is concerned. 3008 */ 3009 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 3010 3011 ept_access_test_setup(); 3012 ept_enable_ad_bits_or_skip_test(); 3013 3014 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 3015 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 3016 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 3017 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ, qual); 3018 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 3019 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC, qual); 3020 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_READ, qual); 3021 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_WRITE, qual); 3022 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_EXEC, qual); 3023 } 3024 3025 static void ept_access_test_paddr_read_write(void) 3026 { 3027 ept_access_test_setup(); 3028 /* Read-write access to paging structure. */ 3029 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_READ); 3030 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_WRITE); 3031 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_EXEC); 3032 } 3033 3034 static void ept_access_test_paddr_read_write_execute(void) 3035 { 3036 ept_access_test_setup(); 3037 /* RWX access to paging structure. */ 3038 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_READ); 3039 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_WRITE); 3040 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_EXEC); 3041 } 3042 3043 static void ept_access_test_paddr_read_execute_ad_disabled(void) 3044 { 3045 /* 3046 * When EPT AD bits are disabled, all accesses to guest paging 3047 * structures are reported separately as a read and (after 3048 * translation of the GPA to host physical address) a read+write 3049 * if the A/D bits have to be set. 3050 */ 3051 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3052 3053 ept_access_test_setup(); 3054 ept_disable_ad_bits(); 3055 3056 /* Can't update A bit, so all accesses fail. */ 3057 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3058 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3059 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3060 /* AD bits disabled, so only writes try to update the D bit. */ 3061 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ); 3062 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3063 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC); 3064 /* Both A and D already set, so read-only is OK. */ 3065 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ); 3066 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE); 3067 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC); 3068 } 3069 3070 static void ept_access_test_paddr_read_execute_ad_enabled(void) 3071 { 3072 /* 3073 * When EPT AD bits are enabled, all accesses to guest paging 3074 * structures are considered writes as far as EPT translation 3075 * is concerned. 3076 */ 3077 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3078 3079 ept_access_test_setup(); 3080 ept_enable_ad_bits_or_skip_test(); 3081 3082 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3083 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3084 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3085 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ, qual); 3086 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3087 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC, qual); 3088 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ, qual); 3089 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE, qual); 3090 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC, qual); 3091 } 3092 3093 static void ept_access_test_paddr_not_present_page_fault(void) 3094 { 3095 ept_access_test_setup(); 3096 /* 3097 * TODO: test no EPT violation as long as guest PF occurs. e.g., GPA is 3098 * page is read-only in EPT but GVA is also mapped read only in PT. 3099 * Thus guest page fault before host takes EPT violation for trying to 3100 * update A bit. 3101 */ 3102 } 3103 3104 static void ept_access_test_force_2m_page(void) 3105 { 3106 ept_access_test_setup(); 3107 3108 TEST_ASSERT_EQ(ept_2m_supported(), true); 3109 ept_allowed_at_level_mkhuge(true, 2, 0, 0, OP_READ); 3110 ept_violation_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_RA, OP_WRITE, 3111 EPT_VLT_WR | EPT_VLT_PERM_RD | 3112 EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 3113 ept_misconfig_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_WA); 3114 } 3115 3116 static bool invvpid_valid(u64 type, u64 vpid, u64 gla) 3117 { 3118 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3119 3120 TEST_ASSERT(msr & VPID_CAP_INVVPID); 3121 3122 if (type < INVVPID_ADDR || type > INVVPID_CONTEXT_LOCAL) 3123 return false; 3124 3125 if (!(msr & (1ull << (type + VPID_CAP_INVVPID_TYPES_SHIFT)))) 3126 return false; 3127 3128 if (vpid >> 16) 3129 return false; 3130 3131 if (type != INVVPID_ALL && !vpid) 3132 return false; 3133 3134 if (type == INVVPID_ADDR && !is_canonical(gla)) 3135 return false; 3136 3137 return true; 3138 } 3139 3140 static void try_invvpid(u64 type, u64 vpid, u64 gla) 3141 { 3142 int rc; 3143 bool valid = invvpid_valid(type, vpid, gla); 3144 u64 expected = valid ? VMXERR_UNSUPPORTED_VMCS_COMPONENT 3145 : VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID; 3146 /* 3147 * Set VMX_INST_ERROR to VMXERR_UNVALID_VMCS_COMPONENT, so 3148 * that we can tell if it is updated by INVVPID. 3149 */ 3150 vmcs_read(~0); 3151 rc = invvpid(type, vpid, gla); 3152 report("INVVPID type %ld VPID %lx GLA %lx %s", 3153 !rc == valid, type, vpid, gla, 3154 valid ? "passes" : "fails"); 3155 report("After %s INVVPID, VMX_INST_ERR is %ld (actual %ld)", 3156 vmcs_read(VMX_INST_ERROR) == expected, 3157 rc ? "failed" : "successful", 3158 expected, vmcs_read(VMX_INST_ERROR)); 3159 } 3160 3161 static void ds_invvpid(void *data) 3162 { 3163 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3164 u64 type = ffs(msr >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 3165 3166 TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 3167 asm volatile("invvpid %0, %1" 3168 : 3169 : "m"(*(struct invvpid_operand *)data), 3170 "r"(type)); 3171 } 3172 3173 /* 3174 * The SS override is ignored in 64-bit mode, so we use an addressing 3175 * mode with %rsp as the base register to generate an implicit SS 3176 * reference. 3177 */ 3178 static void ss_invvpid(void *data) 3179 { 3180 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3181 u64 type = ffs(msr >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 3182 3183 TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 3184 asm volatile("sub %%rsp,%0; invvpid (%%rsp,%0,1), %1" 3185 : "+r"(data) 3186 : "r"(type)); 3187 } 3188 3189 static void invvpid_test_gp(void) 3190 { 3191 bool fault; 3192 3193 fault = test_for_exception(GP_VECTOR, &ds_invvpid, 3194 (void *)NONCANONICAL); 3195 report("INVVPID with non-canonical DS operand raises #GP", fault); 3196 } 3197 3198 static void invvpid_test_ss(void) 3199 { 3200 bool fault; 3201 3202 fault = test_for_exception(SS_VECTOR, &ss_invvpid, 3203 (void *)NONCANONICAL); 3204 report("INVVPID with non-canonical SS operand raises #SS", fault); 3205 } 3206 3207 static void invvpid_test_pf(void) 3208 { 3209 void *vpage = alloc_vpage(); 3210 bool fault; 3211 3212 fault = test_for_exception(PF_VECTOR, &ds_invvpid, vpage); 3213 report("INVVPID with unmapped operand raises #PF", fault); 3214 } 3215 3216 static void try_compat_invvpid(void *unused) 3217 { 3218 struct far_pointer32 fp = { 3219 .offset = (uintptr_t)&&invvpid, 3220 .selector = KERNEL_CS32, 3221 }; 3222 register uintptr_t rsp asm("rsp"); 3223 3224 TEST_ASSERT_MSG(fp.offset == (uintptr_t)&&invvpid, 3225 "Code address too high."); 3226 TEST_ASSERT_MSG(rsp == (u32)rsp, "Stack address too high."); 3227 3228 asm goto ("lcall *%0" : : "m" (fp) : "rax" : invvpid); 3229 return; 3230 invvpid: 3231 asm volatile (".code32;" 3232 "invvpid (%eax), %eax;" 3233 "lret;" 3234 ".code64"); 3235 __builtin_unreachable(); 3236 } 3237 3238 static void invvpid_test_compatibility_mode(void) 3239 { 3240 bool fault; 3241 3242 fault = test_for_exception(UD_VECTOR, &try_compat_invvpid, NULL); 3243 report("Compatibility mode INVVPID raises #UD", fault); 3244 } 3245 3246 static void invvpid_test_not_in_vmx_operation(void) 3247 { 3248 bool fault; 3249 3250 TEST_ASSERT(!vmx_off()); 3251 fault = test_for_exception(UD_VECTOR, &ds_invvpid, NULL); 3252 report("INVVPID outside of VMX operation raises #UD", fault); 3253 TEST_ASSERT(!vmx_on()); 3254 } 3255 3256 /* 3257 * This does not test real-address mode, virtual-8086 mode, protected mode, 3258 * or CPL > 0. 3259 */ 3260 static void invvpid_test_v2(void) 3261 { 3262 u64 msr; 3263 int i; 3264 unsigned types = 0; 3265 unsigned type; 3266 3267 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 3268 !(ctrl_cpu_rev[1].clr & CPU_VPID)) 3269 test_skip("VPID not supported"); 3270 3271 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3272 3273 if (!(msr & VPID_CAP_INVVPID)) 3274 test_skip("INVVPID not supported.\n"); 3275 3276 if (msr & VPID_CAP_INVVPID_ADDR) 3277 types |= 1u << INVVPID_ADDR; 3278 if (msr & VPID_CAP_INVVPID_CXTGLB) 3279 types |= 1u << INVVPID_CONTEXT_GLOBAL; 3280 if (msr & VPID_CAP_INVVPID_ALL) 3281 types |= 1u << INVVPID_ALL; 3282 if (msr & VPID_CAP_INVVPID_CXTLOC) 3283 types |= 1u << INVVPID_CONTEXT_LOCAL; 3284 3285 if (!types) 3286 test_skip("No INVVPID types supported.\n"); 3287 3288 for (i = -127; i < 128; i++) 3289 try_invvpid(i, 0xffff, 0); 3290 3291 /* 3292 * VPID must not be more than 16 bits. 3293 */ 3294 for (i = 0; i < 64; i++) 3295 for (type = 0; type < 4; type++) 3296 if (types & (1u << type)) 3297 try_invvpid(type, 1ul << i, 0); 3298 3299 /* 3300 * VPID must not be zero, except for "all contexts." 3301 */ 3302 for (type = 0; type < 4; type++) 3303 if (types & (1u << type)) 3304 try_invvpid(type, 0, 0); 3305 3306 /* 3307 * The gla operand is only validated for single-address INVVPID. 3308 */ 3309 if (types & (1u << INVVPID_ADDR)) 3310 try_invvpid(INVVPID_ADDR, 0xffff, NONCANONICAL); 3311 3312 invvpid_test_gp(); 3313 invvpid_test_ss(); 3314 invvpid_test_pf(); 3315 invvpid_test_compatibility_mode(); 3316 invvpid_test_not_in_vmx_operation(); 3317 } 3318 3319 /* 3320 * Test for early VMLAUNCH failure. Returns true if VMLAUNCH makes it 3321 * at least as far as the guest-state checks. Returns false if the 3322 * VMLAUNCH fails early and execution falls through to the next 3323 * instruction. 3324 */ 3325 static bool vmlaunch_succeeds(void) 3326 { 3327 u32 exit_reason; 3328 3329 /* 3330 * Indirectly set VMX_INST_ERR to 12 ("VMREAD/VMWRITE from/to 3331 * unsupported VMCS component"). The caller can then check 3332 * to see if a failed VM-entry sets VMX_INST_ERR as expected. 3333 */ 3334 vmcs_write(~0u, 0); 3335 3336 vmcs_write(HOST_RIP, (uintptr_t)&&success); 3337 __asm__ __volatile__ goto ("vmwrite %%rsp, %0; vmlaunch" 3338 : 3339 : "r" ((u64)HOST_RSP) 3340 : "cc", "memory" 3341 : success); 3342 return false; 3343 success: 3344 exit_reason = vmcs_read(EXI_REASON); 3345 TEST_ASSERT(exit_reason == (VMX_FAIL_STATE | VMX_ENTRY_FAILURE) || 3346 exit_reason == (VMX_FAIL_MSR | VMX_ENTRY_FAILURE)); 3347 return true; 3348 } 3349 3350 /* 3351 * Try to launch the current VMCS. 3352 */ 3353 static void test_vmx_vmlaunch(u32 xerror, bool xfail) 3354 { 3355 bool success = vmlaunch_succeeds(); 3356 u32 vmx_inst_err; 3357 3358 report_xfail("vmlaunch %s", xfail, success == !xerror, 3359 !xerror ? "succeeds" : "fails"); 3360 if (!success && xerror) { 3361 vmx_inst_err = vmcs_read(VMX_INST_ERROR); 3362 report("VMX inst error is %d (actual %d)", 3363 vmx_inst_err == xerror, xerror, vmx_inst_err); 3364 } 3365 } 3366 3367 static void test_vmx_invalid_controls(bool xfail) 3368 { 3369 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_CONTROL_FIELD, xfail); 3370 } 3371 3372 static void test_vmx_valid_controls(bool xfail) 3373 { 3374 test_vmx_vmlaunch(0, xfail); 3375 } 3376 3377 /* 3378 * Test a particular value of a VM-execution control bit, if the value 3379 * is required or if the value is zero. 3380 */ 3381 static void test_rsvd_ctl_bit_value(const char *name, union vmx_ctrl_msr msr, 3382 enum Encoding encoding, unsigned bit, 3383 unsigned val) 3384 { 3385 u32 mask = 1u << bit; 3386 bool expected; 3387 u32 controls; 3388 3389 if (msr.set & mask) 3390 TEST_ASSERT(msr.clr & mask); 3391 3392 /* 3393 * We can't arbitrarily turn on a control bit, because it may 3394 * introduce dependencies on other VMCS fields. So, we only 3395 * test turning on bits that have a required setting. 3396 */ 3397 if (val && (msr.clr & mask) && !(msr.set & mask)) 3398 return; 3399 3400 report_prefix_pushf("%s %s bit %d", 3401 val ? "Set" : "Clear", name, bit); 3402 3403 controls = vmcs_read(encoding); 3404 if (val) { 3405 vmcs_write(encoding, msr.set | mask); 3406 expected = (msr.clr & mask); 3407 } else { 3408 vmcs_write(encoding, msr.set & ~mask); 3409 expected = !(msr.set & mask); 3410 } 3411 if (expected) 3412 test_vmx_valid_controls(false); 3413 else 3414 test_vmx_invalid_controls(false); 3415 vmcs_write(encoding, controls); 3416 report_prefix_pop(); 3417 } 3418 3419 /* 3420 * Test reserved values of a VM-execution control bit, based on the 3421 * allowed bit settings from the corresponding VMX capability MSR. 3422 */ 3423 static void test_rsvd_ctl_bit(const char *name, union vmx_ctrl_msr msr, 3424 enum Encoding encoding, unsigned bit) 3425 { 3426 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 0); 3427 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 1); 3428 } 3429 3430 /* 3431 * Reserved bits in the pin-based VM-execution controls must be set 3432 * properly. Software may consult the VMX capability MSRs to determine 3433 * the proper settings. 3434 * [Intel SDM] 3435 */ 3436 static void test_pin_based_ctls(void) 3437 { 3438 unsigned bit; 3439 3440 printf("%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PIN" : 3441 "MSR_IA32_VMX_PINBASED_CTLS", ctrl_pin_rev.val); 3442 for (bit = 0; bit < 32; bit++) 3443 test_rsvd_ctl_bit("pin-based controls", 3444 ctrl_pin_rev, PIN_CONTROLS, bit); 3445 } 3446 3447 /* 3448 * Reserved bits in the primary processor-based VM-execution controls 3449 * must be set properly. Software may consult the VMX capability MSRs 3450 * to determine the proper settings. 3451 * [Intel SDM] 3452 */ 3453 static void test_primary_processor_based_ctls(void) 3454 { 3455 unsigned bit; 3456 3457 printf("\n%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PROC" : 3458 "MSR_IA32_VMX_PROCBASED_CTLS", ctrl_cpu_rev[0].val); 3459 for (bit = 0; bit < 32; bit++) 3460 test_rsvd_ctl_bit("primary processor-based controls", 3461 ctrl_cpu_rev[0], CPU_EXEC_CTRL0, bit); 3462 } 3463 3464 /* 3465 * If the "activate secondary controls" primary processor-based 3466 * VM-execution control is 1, reserved bits in the secondary 3467 * processor-based VM-execution controls must be cleared. Software may 3468 * consult the VMX capability MSRs to determine which bits are 3469 * reserved. 3470 * If the "activate secondary controls" primary processor-based 3471 * VM-execution control is 0 (or if the processor does not support the 3472 * 1-setting of that control), no checks are performed on the 3473 * secondary processor-based VM-execution controls. 3474 * [Intel SDM] 3475 */ 3476 static void test_secondary_processor_based_ctls(void) 3477 { 3478 u32 primary; 3479 u32 secondary; 3480 unsigned bit; 3481 3482 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) 3483 return; 3484 3485 primary = vmcs_read(CPU_EXEC_CTRL0); 3486 secondary = vmcs_read(CPU_EXEC_CTRL1); 3487 3488 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3489 printf("\nMSR_IA32_VMX_PROCBASED_CTLS2: %lx\n", ctrl_cpu_rev[1].val); 3490 for (bit = 0; bit < 32; bit++) 3491 test_rsvd_ctl_bit("secondary processor-based controls", 3492 ctrl_cpu_rev[1], CPU_EXEC_CTRL1, bit); 3493 3494 /* 3495 * When the "activate secondary controls" VM-execution control 3496 * is clear, there are no checks on the secondary controls. 3497 */ 3498 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3499 vmcs_write(CPU_EXEC_CTRL1, ~0); 3500 report("Secondary processor-based controls ignored", 3501 vmlaunch_succeeds()); 3502 vmcs_write(CPU_EXEC_CTRL1, secondary); 3503 vmcs_write(CPU_EXEC_CTRL0, primary); 3504 } 3505 3506 static void try_cr3_target_count(unsigned i, unsigned max) 3507 { 3508 report_prefix_pushf("CR3 target count 0x%x", i); 3509 vmcs_write(CR3_TARGET_COUNT, i); 3510 if (i <= max) 3511 test_vmx_valid_controls(false); 3512 else 3513 test_vmx_invalid_controls(false); 3514 report_prefix_pop(); 3515 } 3516 3517 /* 3518 * The CR3-target count must not be greater than 4. Future processors 3519 * may support a different number of CR3-target values. Software 3520 * should read the VMX capability MSR IA32_VMX_MISC to determine the 3521 * number of values supported. 3522 * [Intel SDM] 3523 */ 3524 static void test_cr3_targets(void) 3525 { 3526 unsigned supported_targets = (rdmsr(MSR_IA32_VMX_MISC) >> 16) & 0x1ff; 3527 u32 cr3_targets = vmcs_read(CR3_TARGET_COUNT); 3528 unsigned i; 3529 3530 printf("\nSupported CR3 targets: %d\n", supported_targets); 3531 TEST_ASSERT(supported_targets <= 256); 3532 3533 try_cr3_target_count(-1u, supported_targets); 3534 try_cr3_target_count(0x80000000, supported_targets); 3535 try_cr3_target_count(0x7fffffff, supported_targets); 3536 for (i = 0; i <= supported_targets + 1; i++) 3537 try_cr3_target_count(i, supported_targets); 3538 vmcs_write(CR3_TARGET_COUNT, cr3_targets); 3539 } 3540 3541 /* 3542 * Test a particular address setting in the VMCS 3543 */ 3544 static void test_vmcs_addr(const char *name, 3545 enum Encoding encoding, 3546 u64 align, 3547 bool ignored, 3548 bool xfail_beyond_mapped_ram, 3549 u64 addr) 3550 { 3551 bool xfail = 3552 (xfail_beyond_mapped_ram && 3553 addr > fwcfg_get_u64(FW_CFG_RAM_SIZE) - align && 3554 addr < (1ul << cpuid_maxphyaddr())); 3555 3556 report_prefix_pushf("%s = %lx", name, addr); 3557 vmcs_write(encoding, addr); 3558 if (ignored || (IS_ALIGNED(addr, align) && 3559 addr < (1ul << cpuid_maxphyaddr()))) 3560 test_vmx_valid_controls(xfail); 3561 else 3562 test_vmx_invalid_controls(xfail); 3563 report_prefix_pop(); 3564 xfail = false; 3565 } 3566 3567 /* 3568 * Test interesting values for a VMCS address 3569 */ 3570 static void test_vmcs_addr_values(const char *name, 3571 enum Encoding encoding, 3572 u64 align, 3573 bool ignored, 3574 bool xfail_beyond_mapped_ram, 3575 u32 bit_start, u32 bit_end) 3576 { 3577 unsigned i; 3578 u64 orig_val = vmcs_read(encoding); 3579 3580 for (i = bit_start; i <= bit_end; i++) 3581 test_vmcs_addr(name, encoding, align, ignored, 3582 xfail_beyond_mapped_ram, 1ul << i); 3583 3584 test_vmcs_addr(name, encoding, align, ignored, 3585 xfail_beyond_mapped_ram, PAGE_SIZE - 1); 3586 test_vmcs_addr(name, encoding, align, ignored, 3587 xfail_beyond_mapped_ram, PAGE_SIZE); 3588 test_vmcs_addr(name, encoding, align, ignored, 3589 xfail_beyond_mapped_ram, 3590 (1ul << cpuid_maxphyaddr()) - PAGE_SIZE); 3591 test_vmcs_addr(name, encoding, align, ignored, 3592 xfail_beyond_mapped_ram, -1ul); 3593 3594 vmcs_write(encoding, orig_val); 3595 } 3596 3597 /* 3598 * Test a physical address reference in the VMCS, when the corresponding 3599 * feature is enabled and when the corresponding feature is disabled. 3600 */ 3601 static void test_vmcs_addr_reference(u32 control_bit, enum Encoding field, 3602 const char *field_name, 3603 const char *control_name, u64 align, 3604 bool xfail_beyond_mapped_ram, 3605 bool control_primary) 3606 { 3607 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 3608 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 3609 u64 page_addr; 3610 3611 if (control_primary) { 3612 if (!(ctrl_cpu_rev[0].clr & control_bit)) 3613 return; 3614 } else { 3615 if (!(ctrl_cpu_rev[1].clr & control_bit)) 3616 return; 3617 } 3618 3619 page_addr = vmcs_read(field); 3620 3621 report_prefix_pushf("%s enabled", control_name); 3622 if (control_primary) { 3623 vmcs_write(CPU_EXEC_CTRL0, primary | control_bit); 3624 } else { 3625 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3626 vmcs_write(CPU_EXEC_CTRL1, secondary | control_bit); 3627 } 3628 3629 test_vmcs_addr_values(field_name, field, align, false, 3630 xfail_beyond_mapped_ram, 0, 63); 3631 report_prefix_pop(); 3632 3633 report_prefix_pushf("%s disabled", control_name); 3634 if (control_primary) { 3635 vmcs_write(CPU_EXEC_CTRL0, primary & ~control_bit); 3636 } else { 3637 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3638 vmcs_write(CPU_EXEC_CTRL1, secondary & ~control_bit); 3639 } 3640 3641 test_vmcs_addr_values(field_name, field, align, true, false, 0, 63); 3642 report_prefix_pop(); 3643 3644 vmcs_write(field, page_addr); 3645 vmcs_write(CPU_EXEC_CTRL0, primary); 3646 vmcs_write(CPU_EXEC_CTRL1, secondary); 3647 } 3648 3649 /* 3650 * If the "use I/O bitmaps" VM-execution control is 1, bits 11:0 of 3651 * each I/O-bitmap address must be 0. Neither address should set any 3652 * bits beyond the processor's physical-address width. 3653 * [Intel SDM] 3654 */ 3655 static void test_io_bitmaps(void) 3656 { 3657 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_A, 3658 "I/O bitmap A", "Use I/O bitmaps", 3659 PAGE_SIZE, false, true); 3660 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_B, 3661 "I/O bitmap B", "Use I/O bitmaps", 3662 PAGE_SIZE, false, true); 3663 } 3664 3665 /* 3666 * If the "use MSR bitmaps" VM-execution control is 1, bits 11:0 of 3667 * the MSR-bitmap address must be 0. The address should not set any 3668 * bits beyond the processor's physical-address width. 3669 * [Intel SDM] 3670 */ 3671 static void test_msr_bitmap(void) 3672 { 3673 test_vmcs_addr_reference(CPU_MSR_BITMAP, MSR_BITMAP, 3674 "MSR bitmap", "Use MSR bitmaps", 3675 PAGE_SIZE, false, true); 3676 } 3677 3678 /* 3679 * If the "use TPR shadow" VM-execution control is 1, the virtual-APIC 3680 * address must satisfy the following checks: 3681 * - Bits 11:0 of the address must be 0. 3682 * - The address should not set any bits beyond the processor's 3683 * physical-address width. 3684 * [Intel SDM] 3685 */ 3686 static void test_apic_virt_addr(void) 3687 { 3688 /* 3689 * Ensure the processor will never use the virtual-APIC page, since 3690 * we will point it to invalid RAM. Otherwise KVM is puzzled about 3691 * what we're trying to achieve and fails vmentry. 3692 */ 3693 u32 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 3694 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0 | CPU_CR8_LOAD | CPU_CR8_STORE); 3695 test_vmcs_addr_reference(CPU_TPR_SHADOW, APIC_VIRT_ADDR, 3696 "virtual-APIC address", "Use TPR shadow", 3697 PAGE_SIZE, false, true); 3698 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 3699 } 3700 3701 /* 3702 * If the "virtualize APIC-accesses" VM-execution control is 1, the 3703 * APIC-access address must satisfy the following checks: 3704 * - Bits 11:0 of the address must be 0. 3705 * - The address should not set any bits beyond the processor's 3706 * physical-address width. 3707 * [Intel SDM] 3708 */ 3709 static void test_apic_access_addr(void) 3710 { 3711 void *apic_access_page = alloc_page(); 3712 3713 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_page)); 3714 3715 test_vmcs_addr_reference(CPU_VIRT_APIC_ACCESSES, APIC_ACCS_ADDR, 3716 "APIC-access address", 3717 "virtualize APIC-accesses", PAGE_SIZE, 3718 false, false); 3719 } 3720 3721 static bool set_bit_pattern(u8 mask, u32 *secondary) 3722 { 3723 u8 i; 3724 bool flag = false; 3725 u32 test_bits[3] = { 3726 CPU_VIRT_X2APIC, 3727 CPU_APIC_REG_VIRT, 3728 CPU_VINTD 3729 }; 3730 3731 for (i = 0; i < ARRAY_SIZE(test_bits); i++) { 3732 if ((mask & (1u << i)) && 3733 (ctrl_cpu_rev[1].clr & test_bits[i])) { 3734 *secondary |= test_bits[i]; 3735 flag = true; 3736 } 3737 } 3738 3739 return (flag); 3740 } 3741 3742 /* 3743 * If the "use TPR shadow" VM-execution control is 0, the following 3744 * VM-execution controls must also be 0: 3745 * - virtualize x2APIC mode 3746 * - APIC-register virtualization 3747 * - virtual-interrupt delivery 3748 * [Intel SDM] 3749 * 3750 * 2. If the "virtualize x2APIC mode" VM-execution control is 1, the 3751 * "virtualize APIC accesses" VM-execution control must be 0. 3752 * [Intel SDM] 3753 */ 3754 static void test_apic_virtual_ctls(void) 3755 { 3756 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3757 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3758 u32 primary = saved_primary; 3759 u32 secondary = saved_secondary; 3760 bool ctrl = false; 3761 char str[10] = "disabled"; 3762 u8 i = 0, j; 3763 3764 /* 3765 * First test 3766 */ 3767 if (!((ctrl_cpu_rev[0].clr & (CPU_SECONDARY | CPU_TPR_SHADOW)) == 3768 (CPU_SECONDARY | CPU_TPR_SHADOW))) 3769 return; 3770 3771 primary |= CPU_SECONDARY; 3772 primary &= ~CPU_TPR_SHADOW; 3773 vmcs_write(CPU_EXEC_CTRL0, primary); 3774 3775 while (1) { 3776 for (j = 1; j < 8; j++) { 3777 secondary &= ~(CPU_VIRT_X2APIC | CPU_APIC_REG_VIRT | CPU_VINTD); 3778 if (primary & CPU_TPR_SHADOW) { 3779 ctrl = true; 3780 } else { 3781 if (! set_bit_pattern(j, &secondary)) 3782 ctrl = true; 3783 else 3784 ctrl = false; 3785 } 3786 3787 vmcs_write(CPU_EXEC_CTRL1, secondary); 3788 report_prefix_pushf("Use TPR shadow %s, virtualize x2APIC mode %s, APIC-register virtualization %s, virtual-interrupt delivery %s", 3789 str, (secondary & CPU_VIRT_X2APIC) ? "enabled" : "disabled", (secondary & CPU_APIC_REG_VIRT) ? "enabled" : "disabled", (secondary & CPU_VINTD) ? "enabled" : "disabled"); 3790 if (ctrl) 3791 test_vmx_valid_controls(false); 3792 else 3793 test_vmx_invalid_controls(false); 3794 report_prefix_pop(); 3795 } 3796 3797 if (i == 1) 3798 break; 3799 i++; 3800 3801 primary |= CPU_TPR_SHADOW; 3802 vmcs_write(CPU_EXEC_CTRL0, primary); 3803 strcpy(str, "enabled"); 3804 } 3805 3806 /* 3807 * Second test 3808 */ 3809 u32 apic_virt_ctls = (CPU_VIRT_X2APIC | CPU_VIRT_APIC_ACCESSES); 3810 3811 primary = saved_primary; 3812 secondary = saved_secondary; 3813 if (!((ctrl_cpu_rev[1].clr & apic_virt_ctls) == apic_virt_ctls)) 3814 return; 3815 3816 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3817 secondary &= ~CPU_VIRT_APIC_ACCESSES; 3818 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_X2APIC); 3819 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access disabled"); 3820 test_vmx_valid_controls(false); 3821 report_prefix_pop(); 3822 3823 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_APIC_ACCESSES); 3824 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access enabled"); 3825 test_vmx_valid_controls(false); 3826 report_prefix_pop(); 3827 3828 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_X2APIC); 3829 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access enabled"); 3830 test_vmx_invalid_controls(false); 3831 report_prefix_pop(); 3832 3833 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_APIC_ACCESSES); 3834 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access disabled"); 3835 test_vmx_valid_controls(false); 3836 report_prefix_pop(); 3837 3838 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3839 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3840 } 3841 3842 /* 3843 * If the "virtual-interrupt delivery" VM-execution control is 1, the 3844 * "external-interrupt exiting" VM-execution control must be 1. 3845 * [Intel SDM] 3846 */ 3847 static void test_virtual_intr_ctls(void) 3848 { 3849 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3850 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3851 u32 saved_pin = vmcs_read(PIN_CONTROLS); 3852 u32 primary = saved_primary; 3853 u32 secondary = saved_secondary; 3854 u32 pin = saved_pin; 3855 3856 if (!((ctrl_cpu_rev[1].clr & CPU_VINTD) && 3857 (ctrl_pin_rev.clr & PIN_EXTINT))) 3858 return; 3859 3860 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 3861 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VINTD); 3862 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 3863 report_prefix_pushf("Virtualize interrupt-delivery disabled; external-interrupt exiting disabled"); 3864 test_vmx_valid_controls(false); 3865 report_prefix_pop(); 3866 3867 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VINTD); 3868 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 3869 test_vmx_invalid_controls(false); 3870 report_prefix_pop(); 3871 3872 vmcs_write(PIN_CONTROLS, pin | PIN_EXTINT); 3873 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting enabled"); 3874 test_vmx_valid_controls(false); 3875 report_prefix_pop(); 3876 3877 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 3878 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 3879 test_vmx_invalid_controls(false); 3880 report_prefix_pop(); 3881 3882 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3883 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3884 vmcs_write(PIN_CONTROLS, saved_pin); 3885 } 3886 3887 static void test_pi_desc_addr(u64 addr, bool ctrl) 3888 { 3889 vmcs_write(POSTED_INTR_DESC_ADDR, addr); 3890 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-descriptor-address 0x%lx", addr); 3891 if (ctrl) 3892 test_vmx_valid_controls(false); 3893 else 3894 test_vmx_invalid_controls(false); 3895 report_prefix_pop(); 3896 } 3897 3898 /* 3899 * If the “process posted interrupts†VM-execution control is 1, the 3900 * following must be true: 3901 * 3902 * - The “virtual-interrupt delivery†VM-execution control is 1. 3903 * - The “acknowledge interrupt on exit†VM-exit control is 1. 3904 * - The posted-interrupt notification vector has a value in the 3905 * - range 0–255 (bits 15:8 are all 0). 3906 * - Bits 5:0 of the posted-interrupt descriptor address are all 0. 3907 * - The posted-interrupt descriptor address does not set any bits 3908 * beyond the processor's physical-address width. 3909 * [Intel SDM] 3910 */ 3911 static void test_posted_intr(void) 3912 { 3913 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3914 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3915 u32 saved_pin = vmcs_read(PIN_CONTROLS); 3916 u32 exit_ctl_saved = vmcs_read(EXI_CONTROLS); 3917 u32 primary = saved_primary; 3918 u32 secondary = saved_secondary; 3919 u32 pin = saved_pin; 3920 u32 exit_ctl = exit_ctl_saved; 3921 u16 vec; 3922 int i; 3923 3924 if (!((ctrl_pin_rev.clr & PIN_POST_INTR) && 3925 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 3926 (ctrl_exit_rev.clr & EXI_INTA))) 3927 return; 3928 3929 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 3930 3931 /* 3932 * Test virtual-interrupt-delivery and acknowledge-interrupt-on-exit 3933 */ 3934 pin |= PIN_POST_INTR; 3935 vmcs_write(PIN_CONTROLS, pin); 3936 secondary &= ~CPU_VINTD; 3937 vmcs_write(CPU_EXEC_CTRL1, secondary); 3938 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled"); 3939 test_vmx_invalid_controls(false); 3940 report_prefix_pop(); 3941 3942 secondary |= CPU_VINTD; 3943 vmcs_write(CPU_EXEC_CTRL1, secondary); 3944 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled"); 3945 test_vmx_invalid_controls(false); 3946 report_prefix_pop(); 3947 3948 exit_ctl &= ~EXI_INTA; 3949 vmcs_write(EXI_CONTROLS, exit_ctl); 3950 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit disabled"); 3951 test_vmx_invalid_controls(false); 3952 report_prefix_pop(); 3953 3954 exit_ctl |= EXI_INTA; 3955 vmcs_write(EXI_CONTROLS, exit_ctl); 3956 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 3957 test_vmx_valid_controls(false); 3958 report_prefix_pop(); 3959 3960 secondary &= ~CPU_VINTD; 3961 vmcs_write(CPU_EXEC_CTRL1, secondary); 3962 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled; acknowledge-interrupt-on-exit enabled"); 3963 test_vmx_invalid_controls(false); 3964 report_prefix_pop(); 3965 3966 secondary |= CPU_VINTD; 3967 vmcs_write(CPU_EXEC_CTRL1, secondary); 3968 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 3969 test_vmx_valid_controls(false); 3970 report_prefix_pop(); 3971 3972 /* 3973 * Test posted-interrupt notification vector 3974 */ 3975 for (i = 0; i < 8; i++) { 3976 vec = (1ul << i); 3977 vmcs_write(PINV, vec); 3978 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 3979 test_vmx_valid_controls(false); 3980 report_prefix_pop(); 3981 } 3982 for (i = 8; i < 16; i++) { 3983 vec = (1ul << i); 3984 vmcs_write(PINV, vec); 3985 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 3986 test_vmx_invalid_controls(false); 3987 report_prefix_pop(); 3988 } 3989 3990 vec &= ~(0xff << 8); 3991 vmcs_write(PINV, vec); 3992 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 3993 test_vmx_valid_controls(false); 3994 report_prefix_pop(); 3995 3996 /* 3997 * Test posted-interrupt descriptor addresss 3998 */ 3999 for (i = 0; i < 6; i++) { 4000 test_pi_desc_addr(1ul << i, false); 4001 } 4002 4003 test_pi_desc_addr(0xf0, false); 4004 test_pi_desc_addr(0xff, false); 4005 test_pi_desc_addr(0x0f, false); 4006 test_pi_desc_addr(0x8000, true); 4007 test_pi_desc_addr(0x00, true); 4008 test_pi_desc_addr(0xc000, true); 4009 4010 test_vmcs_addr_values("process-posted interrupts", 4011 POSTED_INTR_DESC_ADDR, 64, 4012 false, false, 0, 63); 4013 4014 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 4015 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 4016 vmcs_write(PIN_CONTROLS, saved_pin); 4017 } 4018 4019 static void test_apic_ctls(void) 4020 { 4021 test_apic_virt_addr(); 4022 test_apic_access_addr(); 4023 test_apic_virtual_ctls(); 4024 test_virtual_intr_ctls(); 4025 test_posted_intr(); 4026 } 4027 4028 /* 4029 * If the “enable VPID†VM-execution control is 1, the value of the 4030 * of the VPID VM-execution control field must not be 0000H. 4031 * [Intel SDM] 4032 */ 4033 static void test_vpid(void) 4034 { 4035 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 4036 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 4037 u16 vpid = 0x0000; 4038 int i; 4039 4040 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4041 (ctrl_cpu_rev[1].clr & CPU_VPID))) { 4042 test_skip("Secondary controls and/or VPID not supported"); 4043 return; 4044 } 4045 4046 vmcs_write(CPU_EXEC_CTRL0, saved_primary | CPU_SECONDARY); 4047 vmcs_write(CPU_EXEC_CTRL1, saved_secondary & ~CPU_VPID); 4048 vmcs_write(VPID, vpid); 4049 report_prefix_pushf("VPID disabled; VPID value %x", vpid); 4050 test_vmx_valid_controls(false); 4051 report_prefix_pop(); 4052 4053 vmcs_write(CPU_EXEC_CTRL1, saved_secondary | CPU_VPID); 4054 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 4055 test_vmx_invalid_controls(false); 4056 report_prefix_pop(); 4057 4058 for (i = 0; i < 16; i++) { 4059 vpid = (short)1 << i;; 4060 vmcs_write(VPID, vpid); 4061 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 4062 test_vmx_valid_controls(false); 4063 report_prefix_pop(); 4064 } 4065 4066 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 4067 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 4068 } 4069 4070 static void set_vtpr(unsigned vtpr) 4071 { 4072 *(u32 *)phys_to_virt(vmcs_read(APIC_VIRT_ADDR) + APIC_TASKPRI) = vtpr; 4073 } 4074 4075 static void try_tpr_threshold_and_vtpr(unsigned threshold, unsigned vtpr) 4076 { 4077 bool valid = true; 4078 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4079 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4080 4081 if ((primary & CPU_TPR_SHADOW) && 4082 (!(primary & CPU_SECONDARY) || 4083 !(secondary & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 4084 valid = (threshold & 0xf) <= ((vtpr >> 4) & 0xf); 4085 4086 set_vtpr(vtpr); 4087 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0x%x", 4088 threshold, (vtpr >> 4) & 0xf); 4089 if (valid) 4090 test_vmx_valid_controls(false); 4091 else 4092 test_vmx_invalid_controls(false); 4093 report_prefix_pop(); 4094 } 4095 4096 static void test_invalid_event_injection(void) 4097 { 4098 u32 ent_intr_info_save = vmcs_read(ENT_INTR_INFO); 4099 u32 ent_intr_error_save = vmcs_read(ENT_INTR_ERROR); 4100 u32 ent_inst_len_save = vmcs_read(ENT_INST_LEN); 4101 u32 primary_save = vmcs_read(CPU_EXEC_CTRL0); 4102 u32 secondary_save = vmcs_read(CPU_EXEC_CTRL1); 4103 u64 guest_cr0_save = vmcs_read(GUEST_CR0); 4104 u32 ent_intr_info_base = INTR_INFO_VALID_MASK; 4105 u32 ent_intr_info, ent_intr_err, ent_intr_len; 4106 u32 cnt; 4107 4108 /* Setup */ 4109 report_prefix_push("invalid event injection"); 4110 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4111 vmcs_write(ENT_INST_LEN, 0x00000001); 4112 4113 /* The field’s interruption type is not set to a reserved value. */ 4114 ent_intr_info = ent_intr_info_base | INTR_TYPE_RESERVED | DE_VECTOR; 4115 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4116 "RESERVED interruption type invalid [-]", 4117 ent_intr_info); 4118 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4119 test_vmx_invalid_controls(false); 4120 report_prefix_pop(); 4121 4122 ent_intr_info = ent_intr_info_base | INTR_TYPE_EXT_INTR | 4123 DE_VECTOR; 4124 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4125 "RESERVED interruption type invalid [+]", 4126 ent_intr_info); 4127 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4128 test_vmx_valid_controls(false); 4129 report_prefix_pop(); 4130 4131 /* If the interruption type is other event, the vector is 0. */ 4132 ent_intr_info = ent_intr_info_base | INTR_TYPE_OTHER_EVENT | DB_VECTOR; 4133 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4134 "(OTHER EVENT && vector != 0) invalid [-]", 4135 ent_intr_info); 4136 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4137 test_vmx_invalid_controls(false); 4138 report_prefix_pop(); 4139 4140 /* If the interruption type is NMI, the vector is 2 (negative case). */ 4141 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | DE_VECTOR; 4142 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4143 "(NMI && vector != 2) invalid [-]", ent_intr_info); 4144 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4145 test_vmx_invalid_controls(false); 4146 report_prefix_pop(); 4147 4148 /* If the interruption type is NMI, the vector is 2 (positive case). */ 4149 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | NMI_VECTOR; 4150 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4151 "(NMI && vector == 2) valid [+]", ent_intr_info); 4152 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4153 test_vmx_valid_controls(false); 4154 report_prefix_pop(); 4155 4156 /* 4157 * If the interruption type 4158 * is HW exception, the vector is at most 31. 4159 */ 4160 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 0x20; 4161 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4162 "(HW exception && vector > 31) invalid [-]", 4163 ent_intr_info); 4164 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4165 test_vmx_invalid_controls(false); 4166 report_prefix_pop(); 4167 4168 /* 4169 * deliver-error-code is 1 iff either 4170 * (a) the "unrestricted guest" VM-execution control is 0 4171 * (b) CR0.PE is set. 4172 */ 4173 4174 /* Assert that unrestricted guest is disabled or unsupported */ 4175 assert(!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 4176 !(secondary_save & CPU_URG)); 4177 4178 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4179 GP_VECTOR; 4180 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4181 "error code <-> (!URG || prot_mode) [-]", 4182 ent_intr_info); 4183 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4184 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4185 test_vmx_invalid_controls(false); 4186 report_prefix_pop(); 4187 4188 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4189 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4190 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4191 "error code <-> (!URG || prot_mode) [+]", 4192 ent_intr_info); 4193 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4194 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4195 test_vmx_valid_controls(false); 4196 report_prefix_pop(); 4197 4198 if (enable_unrestricted_guest()) 4199 goto skip_unrestricted_guest; 4200 4201 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4202 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4203 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4204 "error code <-> (!URG || prot_mode) [-]", 4205 ent_intr_info); 4206 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4207 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4208 test_vmx_invalid_controls(false); 4209 report_prefix_pop(); 4210 4211 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4212 GP_VECTOR; 4213 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4214 "error code <-> (!URG || prot_mode) [-]", 4215 ent_intr_info); 4216 vmcs_write(GUEST_CR0, guest_cr0_save | X86_CR0_PE); 4217 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4218 test_vmx_invalid_controls(false); 4219 report_prefix_pop(); 4220 4221 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4222 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4223 4224 skip_unrestricted_guest: 4225 vmcs_write(GUEST_CR0, guest_cr0_save); 4226 4227 /* deliver-error-code is 1 iff the interruption type is HW exception */ 4228 report_prefix_push("error code <-> HW exception"); 4229 for (cnt = 0; cnt < 8; cnt++) { 4230 u32 exception_type_mask = cnt << 8; 4231 u32 deliver_error_code_mask = 4232 exception_type_mask != INTR_TYPE_HARD_EXCEPTION ? 4233 INTR_INFO_DELIVER_CODE_MASK : 0; 4234 4235 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4236 exception_type_mask | GP_VECTOR; 4237 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4238 ent_intr_info); 4239 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4240 test_vmx_invalid_controls(false); 4241 report_prefix_pop(); 4242 } 4243 report_prefix_pop(); 4244 4245 /* 4246 * deliver-error-code is 1 iff the the vector 4247 * indicates an exception that would normally deliver an error code 4248 */ 4249 report_prefix_push("error code <-> vector delivers error code"); 4250 for (cnt = 0; cnt < 32; cnt++) { 4251 bool has_error_code = false; 4252 u32 deliver_error_code_mask; 4253 4254 switch (cnt) { 4255 case DF_VECTOR: 4256 case TS_VECTOR: 4257 case NP_VECTOR: 4258 case SS_VECTOR: 4259 case GP_VECTOR: 4260 case PF_VECTOR: 4261 case AC_VECTOR: 4262 has_error_code = true; 4263 } 4264 4265 /* Negative case */ 4266 deliver_error_code_mask = has_error_code ? 4267 0 : 4268 INTR_INFO_DELIVER_CODE_MASK; 4269 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4270 INTR_TYPE_HARD_EXCEPTION | cnt; 4271 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4272 ent_intr_info); 4273 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4274 test_vmx_invalid_controls(false); 4275 report_prefix_pop(); 4276 4277 /* Positive case */ 4278 deliver_error_code_mask = has_error_code ? 4279 INTR_INFO_DELIVER_CODE_MASK : 4280 0; 4281 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4282 INTR_TYPE_HARD_EXCEPTION | cnt; 4283 report_prefix_pushf("VM-entry intr info=0x%x [+]", 4284 ent_intr_info); 4285 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4286 test_vmx_valid_controls(false); 4287 report_prefix_pop(); 4288 } 4289 report_prefix_pop(); 4290 4291 /* Reserved bits in the field (30:12) are 0. */ 4292 report_prefix_push("reserved bits clear"); 4293 for (cnt = 12; cnt <= 30; cnt++) { 4294 ent_intr_info = ent_intr_info_base | 4295 INTR_INFO_DELIVER_CODE_MASK | 4296 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR | 4297 (1U << cnt); 4298 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4299 ent_intr_info); 4300 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4301 test_vmx_invalid_controls(false); 4302 report_prefix_pop(); 4303 } 4304 report_prefix_pop(); 4305 4306 /* 4307 * If deliver-error-code is 1 4308 * bits 31:15 of the VM-entry exception error-code field are 0. 4309 */ 4310 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4311 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4312 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4313 "VM-entry exception error code[31:15] clear", 4314 ent_intr_info); 4315 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4316 for (cnt = 15; cnt <= 31; cnt++) { 4317 ent_intr_err = 1U << cnt; 4318 report_prefix_pushf("VM-entry intr error=0x%x [-]", 4319 ent_intr_err); 4320 vmcs_write(ENT_INTR_ERROR, ent_intr_err); 4321 test_vmx_invalid_controls(false); 4322 report_prefix_pop(); 4323 } 4324 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4325 report_prefix_pop(); 4326 4327 /* 4328 * If the interruption type is software interrupt, software exception, 4329 * or privileged software exception, the VM-entry instruction-length 4330 * field is in the range 0–15. 4331 */ 4332 4333 for (cnt = 0; cnt < 3; cnt++) { 4334 switch (cnt) { 4335 case 0: 4336 ent_intr_info = ent_intr_info_base | 4337 INTR_TYPE_SOFT_INTR; 4338 break; 4339 case 1: 4340 ent_intr_info = ent_intr_info_base | 4341 INTR_TYPE_SOFT_EXCEPTION; 4342 break; 4343 case 2: 4344 ent_intr_info = ent_intr_info_base | 4345 INTR_TYPE_PRIV_SW_EXCEPTION; 4346 break; 4347 } 4348 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4349 "VM-entry instruction-length check", 4350 ent_intr_info); 4351 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4352 4353 /* Instruction length set to -1 (0xFFFFFFFF) should fail */ 4354 ent_intr_len = -1; 4355 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4356 ent_intr_len); 4357 vmcs_write(ENT_INST_LEN, ent_intr_len); 4358 test_vmx_invalid_controls(false); 4359 report_prefix_pop(); 4360 4361 /* Instruction length set to 16 should fail */ 4362 ent_intr_len = 0x00000010; 4363 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4364 ent_intr_len); 4365 vmcs_write(ENT_INST_LEN, 0x00000010); 4366 test_vmx_invalid_controls(false); 4367 report_prefix_pop(); 4368 4369 report_prefix_pop(); 4370 } 4371 4372 /* Cleanup */ 4373 vmcs_write(ENT_INTR_INFO, ent_intr_info_save); 4374 vmcs_write(ENT_INTR_ERROR, ent_intr_error_save); 4375 vmcs_write(ENT_INST_LEN, ent_inst_len_save); 4376 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4377 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4378 vmcs_write(GUEST_CR0, guest_cr0_save); 4379 report_prefix_pop(); 4380 } 4381 4382 /* 4383 * Test interesting vTPR values for a given TPR threshold. 4384 */ 4385 static void test_vtpr_values(unsigned threshold) 4386 { 4387 try_tpr_threshold_and_vtpr(threshold, (threshold - 1) << 4); 4388 try_tpr_threshold_and_vtpr(threshold, threshold << 4); 4389 try_tpr_threshold_and_vtpr(threshold, (threshold + 1) << 4); 4390 } 4391 4392 static void try_tpr_threshold(unsigned threshold) 4393 { 4394 bool valid = true; 4395 4396 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4397 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4398 4399 if ((primary & CPU_TPR_SHADOW) && !((primary & CPU_SECONDARY) && 4400 (secondary & CPU_VINTD))) 4401 valid = !(threshold >> 4); 4402 4403 set_vtpr(-1); 4404 vmcs_write(TPR_THRESHOLD, threshold); 4405 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0xf", threshold); 4406 if (valid) 4407 test_vmx_valid_controls(false); 4408 else 4409 test_vmx_invalid_controls(false); 4410 report_prefix_pop(); 4411 4412 if (valid) 4413 test_vtpr_values(threshold); 4414 } 4415 4416 /* 4417 * Test interesting TPR threshold values. 4418 */ 4419 static void test_tpr_threshold_values(void) 4420 { 4421 unsigned i; 4422 4423 for (i = 0; i < 0x10; i++) 4424 try_tpr_threshold(i); 4425 for (i = 4; i < 32; i++) 4426 try_tpr_threshold(1u << i); 4427 try_tpr_threshold(-1u); 4428 try_tpr_threshold(0x7fffffff); 4429 } 4430 4431 /* 4432 * This test covers the following two VM entry checks: 4433 * 4434 * i) If the "use TPR shadow" VM-execution control is 1 and the 4435 * "virtual-interrupt delivery" VM-execution control is 0, bits 4436 * 31:4 of the TPR threshold VM-execution control field must 4437 be 0. 4438 * [Intel SDM] 4439 * 4440 * ii) If the "use TPR shadow" VM-execution control is 1, the 4441 * "virtual-interrupt delivery" VM-execution control is 0 4442 * and the "virtualize APIC accesses" VM-execution control 4443 * is 0, the value of bits 3:0 of the TPR threshold VM-execution 4444 * control field must not be greater than the value of bits 4445 * 7:4 of VTPR. 4446 * [Intel SDM] 4447 */ 4448 static void test_tpr_threshold(void) 4449 { 4450 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4451 u64 apic_virt_addr = vmcs_read(APIC_VIRT_ADDR); 4452 u64 threshold = vmcs_read(TPR_THRESHOLD); 4453 void *virtual_apic_page; 4454 4455 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) 4456 return; 4457 4458 virtual_apic_page = alloc_page(); 4459 memset(virtual_apic_page, 0xff, PAGE_SIZE); 4460 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 4461 4462 vmcs_write(CPU_EXEC_CTRL0, primary & ~(CPU_TPR_SHADOW | CPU_SECONDARY)); 4463 report_prefix_pushf("Use TPR shadow disabled, secondary controls disabled"); 4464 test_tpr_threshold_values(); 4465 report_prefix_pop(); 4466 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_TPR_SHADOW); 4467 report_prefix_pushf("Use TPR shadow enabled, secondary controls disabled"); 4468 test_tpr_threshold_values(); 4469 report_prefix_pop(); 4470 4471 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4472 (ctrl_cpu_rev[1].clr & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 4473 goto out; 4474 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4475 4476 if (ctrl_cpu_rev[1].clr & CPU_VINTD) { 4477 vmcs_write(CPU_EXEC_CTRL1, CPU_VINTD); 4478 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4479 test_tpr_threshold_values(); 4480 report_prefix_pop(); 4481 4482 vmcs_write(CPU_EXEC_CTRL0, 4483 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4484 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4485 test_tpr_threshold_values(); 4486 report_prefix_pop(); 4487 } 4488 4489 if (ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES) { 4490 vmcs_write(CPU_EXEC_CTRL0, 4491 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4492 vmcs_write(CPU_EXEC_CTRL1, CPU_VIRT_APIC_ACCESSES); 4493 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4494 test_tpr_threshold_values(); 4495 report_prefix_pop(); 4496 4497 vmcs_write(CPU_EXEC_CTRL0, 4498 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4499 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4500 test_tpr_threshold_values(); 4501 report_prefix_pop(); 4502 } 4503 4504 if ((ctrl_cpu_rev[1].clr & 4505 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) == 4506 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) { 4507 vmcs_write(CPU_EXEC_CTRL0, 4508 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4509 vmcs_write(CPU_EXEC_CTRL1, 4510 CPU_VINTD | CPU_VIRT_APIC_ACCESSES); 4511 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4512 test_tpr_threshold_values(); 4513 report_prefix_pop(); 4514 4515 vmcs_write(CPU_EXEC_CTRL0, 4516 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4517 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4518 test_tpr_threshold_values(); 4519 report_prefix_pop(); 4520 } 4521 4522 vmcs_write(CPU_EXEC_CTRL1, secondary); 4523 out: 4524 vmcs_write(TPR_THRESHOLD, threshold); 4525 vmcs_write(APIC_VIRT_ADDR, apic_virt_addr); 4526 vmcs_write(CPU_EXEC_CTRL0, primary); 4527 } 4528 4529 /* 4530 * This test verifies the following two vmentry checks: 4531 * 4532 * If the "NMI exiting" VM-execution control is 0, "Virtual NMIs" 4533 * VM-execution control must be 0. 4534 * [Intel SDM] 4535 * 4536 * If the “virtual NMIs” VM-execution control is 0, the “NMI-window 4537 * exiting” VM-execution control must be 0. 4538 * [Intel SDM] 4539 */ 4540 static void test_nmi_ctrls(void) 4541 { 4542 u32 pin_ctrls, cpu_ctrls0, test_pin_ctrls, test_cpu_ctrls0; 4543 4544 if ((ctrl_pin_rev.clr & (PIN_NMI | PIN_VIRT_NMI)) != 4545 (PIN_NMI | PIN_VIRT_NMI)) { 4546 test_skip("NMI exiting and Virtual NMIs are not supported !"); 4547 return; 4548 } 4549 4550 /* Save the controls so that we can restore them after our tests */ 4551 pin_ctrls = vmcs_read(PIN_CONTROLS); 4552 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 4553 4554 test_pin_ctrls = pin_ctrls & ~(PIN_NMI | PIN_VIRT_NMI); 4555 test_cpu_ctrls0 = cpu_ctrls0 & ~CPU_NMI_WINDOW; 4556 4557 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4558 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs disabled"); 4559 test_vmx_valid_controls(false); 4560 report_prefix_pop(); 4561 4562 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_VIRT_NMI); 4563 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs enabled"); 4564 test_vmx_invalid_controls(false); 4565 report_prefix_pop(); 4566 4567 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4568 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs enabled"); 4569 test_vmx_valid_controls(false); 4570 report_prefix_pop(); 4571 4572 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_NMI); 4573 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs disabled"); 4574 test_vmx_valid_controls(false); 4575 report_prefix_pop(); 4576 4577 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 4578 report_info("NMI-window exiting is not supported, skipping..."); 4579 goto done; 4580 } 4581 4582 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4583 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4584 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting enabled"); 4585 test_vmx_invalid_controls(false); 4586 report_prefix_pop(); 4587 4588 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4589 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4590 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting disabled"); 4591 test_vmx_valid_controls(false); 4592 report_prefix_pop(); 4593 4594 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4595 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4596 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting enabled"); 4597 test_vmx_valid_controls(false); 4598 report_prefix_pop(); 4599 4600 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4601 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4602 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting disabled"); 4603 test_vmx_valid_controls(false); 4604 report_prefix_pop(); 4605 4606 /* Restore the controls to their original values */ 4607 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 4608 done: 4609 vmcs_write(PIN_CONTROLS, pin_ctrls); 4610 } 4611 4612 static void test_eptp_ad_bit(u64 eptp, bool ctrl) 4613 { 4614 vmcs_write(EPTP, eptp); 4615 report_prefix_pushf("Enable-EPT enabled; EPT accessed and dirty flag %s", 4616 (eptp & EPTP_AD_FLAG) ? "1": "0"); 4617 if (ctrl) 4618 test_vmx_valid_controls(false); 4619 else 4620 test_vmx_invalid_controls(false); 4621 report_prefix_pop(); 4622 4623 } 4624 4625 /* 4626 * 1. If the "enable EPT" VM-execution control is 1, the "EPTP VM-execution" 4627 * control field must satisfy the following checks: 4628 * 4629 * - The EPT memory type (bits 2:0) must be a value supported by the 4630 * processor as indicated in the IA32_VMX_EPT_VPID_CAP MSR. 4631 * - Bits 5:3 (1 less than the EPT page-walk length) must be 3, 4632 * indicating an EPT page-walk length of 4. 4633 * - Bit 6 (enable bit for accessed and dirty flags for EPT) must be 4634 * 0 if bit 21 of the IA32_VMX_EPT_VPID_CAP MSR is read as 0, 4635 * indicating that the processor does not support accessed and dirty 4636 * dirty flags for EPT. 4637 * - Reserved bits 11:7 and 63:N (where N is the processor's 4638 * physical-address width) must all be 0. 4639 * 4640 * 2. If the "unrestricted guest" VM-execution control is 1, the 4641 * "enable EPT" VM-execution control must also be 1. 4642 */ 4643 static void test_ept_eptp(void) 4644 { 4645 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4646 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4647 u64 eptp_saved = vmcs_read(EPTP); 4648 u32 primary = primary_saved; 4649 u32 secondary = secondary_saved; 4650 u64 msr, eptp = eptp_saved; 4651 bool un_cache = false; 4652 bool wr_bk = false; 4653 bool ctrl; 4654 u32 i, maxphysaddr; 4655 u64 j, resv_bits_mask = 0; 4656 4657 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4658 (ctrl_cpu_rev[1].clr & CPU_EPT))) { 4659 test_skip("\"CPU secondary\" and/or \"enable EPT\" execution controls are not supported !"); 4660 return; 4661 } 4662 4663 /* 4664 * Memory type (bits 2:0) 4665 */ 4666 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 4667 if (msr & EPT_CAP_UC) 4668 un_cache = true; 4669 if (msr & EPT_CAP_WB) 4670 wr_bk = true; 4671 4672 primary |= CPU_SECONDARY; 4673 vmcs_write(CPU_EXEC_CTRL0, primary); 4674 secondary |= CPU_EPT; 4675 vmcs_write(CPU_EXEC_CTRL1, secondary); 4676 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4677 (3ul << EPTP_PG_WALK_LEN_SHIFT); 4678 vmcs_write(EPTP, eptp); 4679 4680 for (i = 0; i < 8; i++) { 4681 if (i == 0) { 4682 if (un_cache) { 4683 report_info("EPT paging structure memory-type is Un-cacheable\n"); 4684 ctrl = true; 4685 } else { 4686 ctrl = false; 4687 } 4688 } else if (i == 6) { 4689 if (wr_bk) { 4690 report_info("EPT paging structure memory-type is Write-back\n"); 4691 ctrl = true; 4692 } else { 4693 ctrl = false; 4694 } 4695 } else { 4696 ctrl = false; 4697 } 4698 4699 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | i; 4700 vmcs_write(EPTP, eptp); 4701 report_prefix_pushf("Enable-EPT enabled; EPT memory type %lu", 4702 eptp & EPT_MEM_TYPE_MASK); 4703 if (ctrl) 4704 test_vmx_valid_controls(false); 4705 else 4706 test_vmx_invalid_controls(false); 4707 report_prefix_pop(); 4708 } 4709 4710 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | 6ul; 4711 4712 /* 4713 * Page walk length (bits 5:3) 4714 */ 4715 for (i = 0; i < 8; i++) { 4716 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4717 (i << EPTP_PG_WALK_LEN_SHIFT); 4718 if (i == 3) 4719 ctrl = true; 4720 else 4721 ctrl = false; 4722 4723 vmcs_write(EPTP, eptp); 4724 report_prefix_pushf("Enable-EPT enabled; EPT page walk length %lu", 4725 eptp & EPTP_PG_WALK_LEN_MASK); 4726 if (ctrl) 4727 test_vmx_valid_controls(false); 4728 else 4729 test_vmx_invalid_controls(false); 4730 report_prefix_pop(); 4731 } 4732 4733 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4734 3ul << EPTP_PG_WALK_LEN_SHIFT; 4735 4736 /* 4737 * Accessed and dirty flag (bit 6) 4738 */ 4739 if (msr & EPT_CAP_AD_FLAG) { 4740 report_info("Processor supports accessed and dirty flag"); 4741 eptp &= ~EPTP_AD_FLAG; 4742 test_eptp_ad_bit(eptp, true); 4743 4744 eptp |= EPTP_AD_FLAG; 4745 test_eptp_ad_bit(eptp, true); 4746 } else { 4747 report_info("Processor does not supports accessed and dirty flag"); 4748 eptp &= ~EPTP_AD_FLAG; 4749 test_eptp_ad_bit(eptp, true); 4750 4751 eptp |= EPTP_AD_FLAG; 4752 test_eptp_ad_bit(eptp, false); 4753 } 4754 4755 /* 4756 * Reserved bits [11:7] and [63:N] 4757 */ 4758 for (i = 0; i < 32; i++) { 4759 eptp = (eptp & 4760 ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)) | 4761 (i << EPTP_RESERV_BITS_SHIFT); 4762 vmcs_write(EPTP, eptp); 4763 report_prefix_pushf("Enable-EPT enabled; reserved bits [11:7] %lu", 4764 (eptp >> EPTP_RESERV_BITS_SHIFT) & 4765 EPTP_RESERV_BITS_MASK); 4766 if (i == 0) 4767 test_vmx_valid_controls(false); 4768 else 4769 test_vmx_invalid_controls(false); 4770 report_prefix_pop(); 4771 } 4772 4773 eptp = (eptp & ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)); 4774 4775 maxphysaddr = cpuid_maxphyaddr(); 4776 for (i = 0; i < (63 - maxphysaddr + 1); i++) { 4777 resv_bits_mask |= 1ul << i; 4778 } 4779 4780 for (j = maxphysaddr - 1; j <= 63; j++) { 4781 eptp = (eptp & ~(resv_bits_mask << maxphysaddr)) | 4782 (j < maxphysaddr ? 0 : 1ul << j); 4783 vmcs_write(EPTP, eptp); 4784 report_prefix_pushf("Enable-EPT enabled; reserved bits [63:N] %lu", 4785 (eptp >> maxphysaddr) & resv_bits_mask); 4786 if (j < maxphysaddr) 4787 test_vmx_valid_controls(false); 4788 else 4789 test_vmx_invalid_controls(false); 4790 report_prefix_pop(); 4791 } 4792 4793 secondary &= ~(CPU_EPT | CPU_URG); 4794 vmcs_write(CPU_EXEC_CTRL1, secondary); 4795 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest disabled"); 4796 test_vmx_valid_controls(false); 4797 report_prefix_pop(); 4798 4799 secondary |= CPU_URG; 4800 vmcs_write(CPU_EXEC_CTRL1, secondary); 4801 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest enabled"); 4802 test_vmx_invalid_controls(false); 4803 report_prefix_pop(); 4804 4805 secondary |= CPU_EPT; 4806 setup_dummy_ept(); 4807 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest enabled"); 4808 test_vmx_valid_controls(false); 4809 report_prefix_pop(); 4810 4811 secondary &= ~CPU_URG; 4812 vmcs_write(CPU_EXEC_CTRL1, secondary); 4813 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest disabled"); 4814 test_vmx_valid_controls(false); 4815 report_prefix_pop(); 4816 4817 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4818 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4819 vmcs_write(EPTP, eptp_saved); 4820 } 4821 4822 /* 4823 * If the 'enable PML' VM-execution control is 1, the 'enable EPT' 4824 * VM-execution control must also be 1. In addition, the PML address 4825 * must satisfy the following checks: 4826 * 4827 * * Bits 11:0 of the address must be 0. 4828 * * The address should not set any bits beyond the processor's 4829 * physical-address width. 4830 * 4831 * [Intel SDM] 4832 */ 4833 static void test_pml(void) 4834 { 4835 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4836 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4837 u32 primary = primary_saved; 4838 u32 secondary = secondary_saved; 4839 4840 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4841 (ctrl_cpu_rev[1].clr & CPU_EPT) && (ctrl_cpu_rev[1].clr & CPU_PML))) { 4842 test_skip("\"Secondary execution\" control or \"enable EPT\" control or \"enable PML\" control is not supported !"); 4843 return; 4844 } 4845 4846 primary |= CPU_SECONDARY; 4847 vmcs_write(CPU_EXEC_CTRL0, primary); 4848 secondary &= ~(CPU_PML | CPU_EPT); 4849 vmcs_write(CPU_EXEC_CTRL1, secondary); 4850 report_prefix_pushf("enable-PML disabled, enable-EPT disabled"); 4851 test_vmx_valid_controls(false); 4852 report_prefix_pop(); 4853 4854 secondary |= CPU_PML; 4855 vmcs_write(CPU_EXEC_CTRL1, secondary); 4856 report_prefix_pushf("enable-PML enabled, enable-EPT disabled"); 4857 test_vmx_invalid_controls(false); 4858 report_prefix_pop(); 4859 4860 secondary |= CPU_EPT; 4861 setup_dummy_ept(); 4862 report_prefix_pushf("enable-PML enabled, enable-EPT enabled"); 4863 test_vmx_valid_controls(false); 4864 report_prefix_pop(); 4865 4866 secondary &= ~CPU_PML; 4867 vmcs_write(CPU_EXEC_CTRL1, secondary); 4868 report_prefix_pushf("enable-PML disabled, enable EPT enabled"); 4869 test_vmx_valid_controls(false); 4870 report_prefix_pop(); 4871 4872 test_vmcs_addr_reference(CPU_PML, PMLADDR, "PML address", "PML", 4873 PAGE_SIZE, false, false); 4874 4875 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4876 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4877 } 4878 4879 /* 4880 * If the "activate VMX-preemption timer" VM-execution control is 0, the 4881 * the "save VMX-preemption timer value" VM-exit control must also be 0. 4882 * 4883 * [Intel SDM] 4884 */ 4885 static void test_vmx_preemption_timer(void) 4886 { 4887 u32 saved_pin = vmcs_read(PIN_CONTROLS); 4888 u32 saved_exit = vmcs_read(EXI_CONTROLS); 4889 u32 pin = saved_pin; 4890 u32 exit = saved_exit; 4891 4892 if (!((ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) || 4893 (ctrl_pin_rev.clr & PIN_PREEMPT))) { 4894 printf("\"Save-VMX-preemption-timer\" control and/or \"Enable-VMX-preemption-timer\" control is not supported\n"); 4895 return; 4896 } 4897 4898 pin |= PIN_PREEMPT; 4899 vmcs_write(PIN_CONTROLS, pin); 4900 exit &= ~EXI_SAVE_PREEMPT; 4901 vmcs_write(EXI_CONTROLS, exit); 4902 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer disabled"); 4903 test_vmx_valid_controls(false); 4904 report_prefix_pop(); 4905 4906 exit |= EXI_SAVE_PREEMPT; 4907 vmcs_write(EXI_CONTROLS, exit); 4908 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer enabled"); 4909 test_vmx_valid_controls(false); 4910 report_prefix_pop(); 4911 4912 pin &= ~PIN_PREEMPT; 4913 vmcs_write(PIN_CONTROLS, pin); 4914 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer enabled"); 4915 test_vmx_invalid_controls(false); 4916 report_prefix_pop(); 4917 4918 exit &= ~EXI_SAVE_PREEMPT; 4919 vmcs_write(EXI_CONTROLS, exit); 4920 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer disabled"); 4921 test_vmx_valid_controls(false); 4922 report_prefix_pop(); 4923 4924 vmcs_write(PIN_CONTROLS, saved_pin); 4925 vmcs_write(EXI_CONTROLS, saved_exit); 4926 } 4927 4928 /* 4929 * Tests for VM-execution control fields 4930 */ 4931 static void test_vm_execution_ctls(void) 4932 { 4933 test_pin_based_ctls(); 4934 test_primary_processor_based_ctls(); 4935 test_secondary_processor_based_ctls(); 4936 test_cr3_targets(); 4937 test_io_bitmaps(); 4938 test_msr_bitmap(); 4939 test_apic_ctls(); 4940 test_tpr_threshold(); 4941 test_nmi_ctrls(); 4942 test_pml(); 4943 test_vpid(); 4944 test_ept_eptp(); 4945 test_vmx_preemption_timer(); 4946 } 4947 4948 /* 4949 * The following checks are performed for the VM-entry MSR-load address if 4950 * the VM-entry MSR-load count field is non-zero: 4951 * 4952 * - The lower 4 bits of the VM-entry MSR-load address must be 0. 4953 * The address should not set any bits beyond the processor’s 4954 * physical-address width. 4955 * 4956 * - The address of the last byte in the VM-entry MSR-load area 4957 * should not set any bits beyond the processor’s physical-address 4958 * width. The address of this last byte is VM-entry MSR-load address 4959 * + (MSR count * 16) - 1. (The arithmetic used for the computation 4960 * uses more bits than the processor’s physical-address width.) 4961 * 4962 * 4963 * [Intel SDM] 4964 */ 4965 static void test_entry_msr_load(void) 4966 { 4967 entry_msr_load = alloc_page(); 4968 u64 tmp; 4969 u32 entry_msr_ld_cnt = 1; 4970 int i; 4971 u32 addr_len = 64; 4972 4973 vmcs_write(ENT_MSR_LD_CNT, entry_msr_ld_cnt); 4974 4975 /* Check first 4 bits of VM-entry MSR-load address */ 4976 for (i = 0; i < 4; i++) { 4977 tmp = (u64)entry_msr_load | 1ull << i; 4978 vmcs_write(ENTER_MSR_LD_ADDR, tmp); 4979 report_prefix_pushf("VM-entry MSR-load addr [4:0] %lx", 4980 tmp & 0xf); 4981 test_vmx_invalid_controls(false); 4982 report_prefix_pop(); 4983 } 4984 4985 if (basic.val & (1ul << 48)) 4986 addr_len = 32; 4987 4988 test_vmcs_addr_values("VM-entry-MSR-load address", 4989 ENTER_MSR_LD_ADDR, 16, false, false, 4990 4, addr_len - 1); 4991 4992 /* 4993 * Check last byte of VM-entry MSR-load address 4994 */ 4995 entry_msr_load = (struct vmx_msr_entry *)((u64)entry_msr_load & ~0xf); 4996 4997 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 4998 i < 64; i++) { 4999 tmp = ((u64)entry_msr_load + entry_msr_ld_cnt * 16 - 1) | 5000 1ul << i; 5001 vmcs_write(ENTER_MSR_LD_ADDR, 5002 tmp - (entry_msr_ld_cnt * 16 - 1)); 5003 test_vmx_invalid_controls(false); 5004 } 5005 5006 vmcs_write(ENT_MSR_LD_CNT, 2); 5007 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 5008 test_vmx_invalid_controls(false); 5009 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 5010 test_vmx_valid_controls(false); 5011 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 5012 test_vmx_valid_controls(false); 5013 } 5014 5015 static void guest_state_test_main(void) 5016 { 5017 while (1) { 5018 if (vmx_get_test_stage() != 2) 5019 vmcall(); 5020 else 5021 break; 5022 } 5023 5024 asm volatile("fnop"); 5025 } 5026 5027 static void report_guest_state_test(const char *test, u32 xreason, 5028 u64 field, const char * field_name) 5029 { 5030 u32 reason = vmcs_read(EXI_REASON); 5031 u64 guest_rip; 5032 u32 insn_len; 5033 5034 report("%s, %s %lx", reason == xreason, test, field_name, field); 5035 5036 guest_rip = vmcs_read(GUEST_RIP); 5037 insn_len = vmcs_read(EXI_INST_LEN); 5038 if (! (reason & 0x80000021)) 5039 vmcs_write(GUEST_RIP, guest_rip + insn_len); 5040 } 5041 5042 /* 5043 * Tests for VM-entry control fields 5044 */ 5045 static void test_vm_entry_ctls(void) 5046 { 5047 test_invalid_event_injection(); 5048 test_entry_msr_load(); 5049 } 5050 5051 /* 5052 * The following checks are performed for the VM-exit MSR-store address if 5053 * the VM-exit MSR-store count field is non-zero: 5054 * 5055 * - The lower 4 bits of the VM-exit MSR-store address must be 0. 5056 * The address should not set any bits beyond the processor’s 5057 * physical-address width. 5058 * 5059 * - The address of the last byte in the VM-exit MSR-store area 5060 * should not set any bits beyond the processor’s physical-address 5061 * width. The address of this last byte is VM-exit MSR-store address 5062 * + (MSR count * 16) - 1. (The arithmetic used for the computation 5063 * uses more bits than the processor’s physical-address width.) 5064 * 5065 * If IA32_VMX_BASIC[48] is read as 1, neither address should set any bits 5066 * in the range 63:32. 5067 * 5068 * [Intel SDM] 5069 */ 5070 static void test_exit_msr_store(void) 5071 { 5072 exit_msr_store = alloc_page(); 5073 u64 tmp; 5074 u32 exit_msr_st_cnt = 1; 5075 int i; 5076 u32 addr_len = 64; 5077 5078 vmcs_write(EXI_MSR_ST_CNT, exit_msr_st_cnt); 5079 5080 /* Check first 4 bits of VM-exit MSR-store address */ 5081 for (i = 0; i < 4; i++) { 5082 tmp = (u64)exit_msr_store | 1ull << i; 5083 vmcs_write(EXIT_MSR_ST_ADDR, tmp); 5084 report_prefix_pushf("VM-exit MSR-store addr [4:0] %lx", 5085 tmp & 0xf); 5086 test_vmx_invalid_controls(false); 5087 report_prefix_pop(); 5088 } 5089 5090 if (basic.val & (1ul << 48)) 5091 addr_len = 32; 5092 5093 test_vmcs_addr_values("VM-exit-MSR-store address", 5094 EXIT_MSR_ST_ADDR, 16, false, false, 5095 4, addr_len - 1); 5096 5097 /* 5098 * Check last byte of VM-exit MSR-store address 5099 */ 5100 exit_msr_store = (struct vmx_msr_entry *)((u64)exit_msr_store & ~0xf); 5101 5102 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 5103 i < 64; i++) { 5104 tmp = ((u64)exit_msr_store + exit_msr_st_cnt * 16 - 1) | 5105 1ul << i; 5106 vmcs_write(EXIT_MSR_ST_ADDR, 5107 tmp - (exit_msr_st_cnt * 16 - 1)); 5108 test_vmx_invalid_controls(false); 5109 } 5110 5111 vmcs_write(EXI_MSR_ST_CNT, 2); 5112 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 5113 test_vmx_invalid_controls(false); 5114 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 5115 test_vmx_valid_controls(false); 5116 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 5117 test_vmx_valid_controls(false); 5118 } 5119 5120 /* 5121 * Tests for VM-exit controls 5122 */ 5123 static void test_vm_exit_ctls(void) 5124 { 5125 test_exit_msr_store(); 5126 } 5127 5128 /* 5129 * Check that the virtual CPU checks all of the VMX controls as 5130 * documented in the Intel SDM. 5131 */ 5132 static void vmx_controls_test(void) 5133 { 5134 /* 5135 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 5136 * fail due to invalid guest state, should we make it that 5137 * far. 5138 */ 5139 vmcs_write(GUEST_RFLAGS, 0); 5140 5141 test_vm_execution_ctls(); 5142 test_vm_exit_ctls(); 5143 test_vm_entry_ctls(); 5144 } 5145 5146 struct apic_reg_virt_config { 5147 bool apic_register_virtualization; 5148 bool use_tpr_shadow; 5149 bool virtualize_apic_accesses; 5150 bool virtualize_x2apic_mode; 5151 bool activate_secondary_controls; 5152 }; 5153 5154 struct apic_reg_test { 5155 const char *name; 5156 struct apic_reg_virt_config apic_reg_virt_config; 5157 }; 5158 5159 struct apic_reg_virt_expectation { 5160 enum Reason rd_exit_reason; 5161 enum Reason wr_exit_reason; 5162 u32 val; 5163 u32 (*virt_fn)(u32); 5164 5165 /* 5166 * If false, accessing the APIC access address from L2 is treated as a 5167 * normal memory operation, rather than triggering virtualization. 5168 */ 5169 bool virtualize_apic_accesses; 5170 }; 5171 5172 static u32 apic_virt_identity(u32 val) 5173 { 5174 return val; 5175 } 5176 5177 static u32 apic_virt_nibble1(u32 val) 5178 { 5179 return val & 0xf0; 5180 } 5181 5182 static u32 apic_virt_byte3(u32 val) 5183 { 5184 return val & (0xff << 24); 5185 } 5186 5187 static bool apic_reg_virt_exit_expectation( 5188 u32 reg, struct apic_reg_virt_config *config, 5189 struct apic_reg_virt_expectation *expectation) 5190 { 5191 /* Good configs, where some L2 APIC accesses are virtualized. */ 5192 bool virtualize_apic_accesses_only = 5193 config->virtualize_apic_accesses && 5194 !config->use_tpr_shadow && 5195 !config->apic_register_virtualization && 5196 !config->virtualize_x2apic_mode && 5197 config->activate_secondary_controls; 5198 bool virtualize_apic_accesses_and_use_tpr_shadow = 5199 config->virtualize_apic_accesses && 5200 config->use_tpr_shadow && 5201 !config->apic_register_virtualization && 5202 !config->virtualize_x2apic_mode && 5203 config->activate_secondary_controls; 5204 bool apic_register_virtualization = 5205 config->virtualize_apic_accesses && 5206 config->use_tpr_shadow && 5207 config->apic_register_virtualization && 5208 !config->virtualize_x2apic_mode && 5209 config->activate_secondary_controls; 5210 5211 expectation->val = MAGIC_VAL_1; 5212 expectation->virt_fn = apic_virt_identity; 5213 expectation->virtualize_apic_accesses = 5214 config->virtualize_apic_accesses && 5215 config->activate_secondary_controls; 5216 if (virtualize_apic_accesses_only) { 5217 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5218 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5219 } else if (virtualize_apic_accesses_and_use_tpr_shadow) { 5220 switch (reg) { 5221 case APIC_TASKPRI: 5222 expectation->rd_exit_reason = VMX_VMCALL; 5223 expectation->wr_exit_reason = VMX_VMCALL; 5224 expectation->virt_fn = apic_virt_nibble1; 5225 break; 5226 default: 5227 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5228 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5229 } 5230 } else if (apic_register_virtualization) { 5231 expectation->rd_exit_reason = VMX_VMCALL; 5232 5233 switch (reg) { 5234 case APIC_ID: 5235 case APIC_EOI: 5236 case APIC_LDR: 5237 case APIC_DFR: 5238 case APIC_SPIV: 5239 case APIC_ESR: 5240 case APIC_ICR: 5241 case APIC_LVTT: 5242 case APIC_LVTTHMR: 5243 case APIC_LVTPC: 5244 case APIC_LVT0: 5245 case APIC_LVT1: 5246 case APIC_LVTERR: 5247 case APIC_TMICT: 5248 case APIC_TDCR: 5249 expectation->wr_exit_reason = VMX_APIC_WRITE; 5250 break; 5251 case APIC_LVR: 5252 case APIC_ISR ... APIC_ISR + 0x70: 5253 case APIC_TMR ... APIC_TMR + 0x70: 5254 case APIC_IRR ... APIC_IRR + 0x70: 5255 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5256 break; 5257 case APIC_TASKPRI: 5258 expectation->wr_exit_reason = VMX_VMCALL; 5259 expectation->virt_fn = apic_virt_nibble1; 5260 break; 5261 case APIC_ICR2: 5262 expectation->wr_exit_reason = VMX_VMCALL; 5263 expectation->virt_fn = apic_virt_byte3; 5264 break; 5265 default: 5266 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5267 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5268 } 5269 } else if (!expectation->virtualize_apic_accesses) { 5270 /* 5271 * No APIC registers are directly virtualized. This includes 5272 * VTPR, which can be virtualized through MOV to/from CR8 via 5273 * the use TPR shadow control, but not through directly 5274 * accessing VTPR. 5275 */ 5276 expectation->rd_exit_reason = VMX_VMCALL; 5277 expectation->wr_exit_reason = VMX_VMCALL; 5278 } else { 5279 printf("Cannot parse APIC register virtualization config:\n" 5280 "\tvirtualize_apic_accesses: %d\n" 5281 "\tuse_tpr_shadow: %d\n" 5282 "\tapic_register_virtualization: %d\n" 5283 "\tvirtualize_x2apic_mode: %d\n" 5284 "\tactivate_secondary_controls: %d\n", 5285 config->virtualize_apic_accesses, 5286 config->use_tpr_shadow, 5287 config->apic_register_virtualization, 5288 config->virtualize_x2apic_mode, 5289 config->activate_secondary_controls); 5290 5291 return false; 5292 } 5293 5294 return true; 5295 } 5296 5297 struct apic_reg_test apic_reg_tests[] = { 5298 /* Good configs, where some L2 APIC accesses are virtualized. */ 5299 { 5300 .name = "Virtualize APIC accesses", 5301 .apic_reg_virt_config = { 5302 .virtualize_apic_accesses = true, 5303 .use_tpr_shadow = false, 5304 .apic_register_virtualization = false, 5305 .virtualize_x2apic_mode = false, 5306 .activate_secondary_controls = true, 5307 }, 5308 }, 5309 { 5310 .name = "Virtualize APIC accesses + Use TPR shadow", 5311 .apic_reg_virt_config = { 5312 .virtualize_apic_accesses = true, 5313 .use_tpr_shadow = true, 5314 .apic_register_virtualization = false, 5315 .virtualize_x2apic_mode = false, 5316 .activate_secondary_controls = true, 5317 }, 5318 }, 5319 { 5320 .name = "APIC-register virtualization", 5321 .apic_reg_virt_config = { 5322 .virtualize_apic_accesses = true, 5323 .use_tpr_shadow = true, 5324 .apic_register_virtualization = true, 5325 .virtualize_x2apic_mode = false, 5326 .activate_secondary_controls = true, 5327 }, 5328 }, 5329 5330 /* 5331 * Test that the secondary processor-based VM-execution controls are 5332 * correctly ignored when "activate secondary controls" is disabled. 5333 */ 5334 { 5335 .name = "Activate secondary controls off", 5336 .apic_reg_virt_config = { 5337 .virtualize_apic_accesses = true, 5338 .use_tpr_shadow = false, 5339 .apic_register_virtualization = true, 5340 .virtualize_x2apic_mode = true, 5341 .activate_secondary_controls = false, 5342 }, 5343 }, 5344 { 5345 .name = "Activate secondary controls off + Use TPR shadow", 5346 .apic_reg_virt_config = { 5347 .virtualize_apic_accesses = true, 5348 .use_tpr_shadow = true, 5349 .apic_register_virtualization = true, 5350 .virtualize_x2apic_mode = true, 5351 .activate_secondary_controls = false, 5352 }, 5353 }, 5354 5355 /* 5356 * Test that the APIC access address is treated like an arbitrary memory 5357 * address when "virtualize APIC accesses" is disabled. 5358 */ 5359 { 5360 .name = "Virtualize APIC accesses off + Use TPR shadow", 5361 .apic_reg_virt_config = { 5362 .virtualize_apic_accesses = false, 5363 .use_tpr_shadow = true, 5364 .apic_register_virtualization = true, 5365 .virtualize_x2apic_mode = true, 5366 .activate_secondary_controls = true, 5367 }, 5368 }, 5369 5370 /* 5371 * Test that VM entry fails due to invalid controls when 5372 * "APIC-register virtualization" is enabled while "use TPR shadow" is 5373 * disabled. 5374 */ 5375 { 5376 .name = "APIC-register virtualization + Use TPR shadow off", 5377 .apic_reg_virt_config = { 5378 .virtualize_apic_accesses = true, 5379 .use_tpr_shadow = false, 5380 .apic_register_virtualization = true, 5381 .virtualize_x2apic_mode = false, 5382 .activate_secondary_controls = true, 5383 }, 5384 }, 5385 5386 /* 5387 * Test that VM entry fails due to invalid controls when 5388 * "Virtualize x2APIC mode" is enabled while "use TPR shadow" is 5389 * disabled. 5390 */ 5391 { 5392 .name = "Virtualize x2APIC mode + Use TPR shadow off", 5393 .apic_reg_virt_config = { 5394 .virtualize_apic_accesses = false, 5395 .use_tpr_shadow = false, 5396 .apic_register_virtualization = false, 5397 .virtualize_x2apic_mode = true, 5398 .activate_secondary_controls = true, 5399 }, 5400 }, 5401 { 5402 .name = "Virtualize x2APIC mode + Use TPR shadow off v2", 5403 .apic_reg_virt_config = { 5404 .virtualize_apic_accesses = false, 5405 .use_tpr_shadow = false, 5406 .apic_register_virtualization = true, 5407 .virtualize_x2apic_mode = true, 5408 .activate_secondary_controls = true, 5409 }, 5410 }, 5411 5412 /* 5413 * Test that VM entry fails due to invalid controls when 5414 * "virtualize x2APIC mode" is enabled while "virtualize APIC accesses" 5415 * is enabled. 5416 */ 5417 { 5418 .name = "Virtualize x2APIC mode + Virtualize APIC accesses", 5419 .apic_reg_virt_config = { 5420 .virtualize_apic_accesses = true, 5421 .use_tpr_shadow = true, 5422 .apic_register_virtualization = false, 5423 .virtualize_x2apic_mode = true, 5424 .activate_secondary_controls = true, 5425 }, 5426 }, 5427 { 5428 .name = "Virtualize x2APIC mode + Virtualize APIC accesses v2", 5429 .apic_reg_virt_config = { 5430 .virtualize_apic_accesses = true, 5431 .use_tpr_shadow = true, 5432 .apic_register_virtualization = true, 5433 .virtualize_x2apic_mode = true, 5434 .activate_secondary_controls = true, 5435 }, 5436 }, 5437 }; 5438 5439 enum Apic_op { 5440 APIC_OP_XAPIC_RD, 5441 APIC_OP_XAPIC_WR, 5442 TERMINATE, 5443 }; 5444 5445 static u32 vmx_xapic_read(u32 *apic_access_address, u32 reg) 5446 { 5447 return *(volatile u32 *)((uintptr_t)apic_access_address + reg); 5448 } 5449 5450 static void vmx_xapic_write(u32 *apic_access_address, u32 reg, u32 val) 5451 { 5452 *(volatile u32 *)((uintptr_t)apic_access_address + reg) = val; 5453 } 5454 5455 struct apic_reg_virt_guest_args { 5456 enum Apic_op op; 5457 u32 *apic_access_address; 5458 u32 reg; 5459 u32 val; 5460 bool check_rd; 5461 u32 (*virt_fn)(u32); 5462 } apic_reg_virt_guest_args; 5463 5464 static void apic_reg_virt_guest(void) 5465 { 5466 volatile struct apic_reg_virt_guest_args *args = 5467 &apic_reg_virt_guest_args; 5468 5469 for (;;) { 5470 enum Apic_op op = args->op; 5471 u32 *apic_access_address = args->apic_access_address; 5472 u32 reg = args->reg; 5473 u32 val = args->val; 5474 bool check_rd = args->check_rd; 5475 u32 (*virt_fn)(u32) = args->virt_fn; 5476 5477 if (op == TERMINATE) 5478 break; 5479 5480 if (op == APIC_OP_XAPIC_RD) { 5481 u32 ret = vmx_xapic_read(apic_access_address, reg); 5482 5483 if (check_rd) { 5484 u32 want = virt_fn(val); 5485 u32 got = virt_fn(ret); 5486 5487 report("read 0x%x, expected 0x%x.", 5488 got == want, got, want); 5489 } 5490 } else if (op == APIC_OP_XAPIC_WR) { 5491 vmx_xapic_write(apic_access_address, reg, val); 5492 } 5493 5494 /* 5495 * The L1 should always execute a vmcall after it's done testing 5496 * an individual APIC operation. This helps to validate that the 5497 * L1 and L2 are in sync with each other, as expected. 5498 */ 5499 vmcall(); 5500 } 5501 } 5502 5503 static void test_xapic_rd( 5504 u32 reg, struct apic_reg_virt_expectation *expectation, 5505 u32 *apic_access_address, u32 *virtual_apic_page) 5506 { 5507 u32 val = expectation->val; 5508 u32 exit_reason_want = expectation->rd_exit_reason; 5509 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 5510 5511 report_prefix_pushf("xapic - reading 0x%03x", reg); 5512 5513 /* Configure guest to do an xapic read */ 5514 args->op = APIC_OP_XAPIC_RD; 5515 args->apic_access_address = apic_access_address; 5516 args->reg = reg; 5517 args->val = val; 5518 args->check_rd = exit_reason_want == VMX_VMCALL; 5519 args->virt_fn = expectation->virt_fn; 5520 5521 /* Setup virtual APIC page */ 5522 if (!expectation->virtualize_apic_accesses) { 5523 apic_access_address[apic_reg_index(reg)] = val; 5524 virtual_apic_page[apic_reg_index(reg)] = 0; 5525 } else if (exit_reason_want == VMX_VMCALL) { 5526 apic_access_address[apic_reg_index(reg)] = 0; 5527 virtual_apic_page[apic_reg_index(reg)] = val; 5528 } 5529 5530 /* Enter guest */ 5531 enter_guest(); 5532 5533 /* 5534 * Validate the behavior and 5535 * pass a magic value back to the guest. 5536 */ 5537 if (exit_reason_want == VMX_APIC_ACCESS) { 5538 u32 apic_page_offset = vmcs_read(EXI_QUALIFICATION) & 0xfff; 5539 5540 assert_exit_reason(exit_reason_want); 5541 report("got APIC access exit @ page offset 0x%03x, want 0x%03x", 5542 apic_page_offset == reg, apic_page_offset, reg); 5543 skip_exit_insn(); 5544 5545 /* Reenter guest so it can consume/check rcx and exit again. */ 5546 enter_guest(); 5547 } else if (exit_reason_want != VMX_VMCALL) { 5548 report("Oops, bad exit expectation: %u.", false, 5549 exit_reason_want); 5550 } 5551 5552 skip_exit_vmcall(); 5553 report_prefix_pop(); 5554 } 5555 5556 static void test_xapic_wr( 5557 u32 reg, struct apic_reg_virt_expectation *expectation, 5558 u32 *apic_access_address, u32 *virtual_apic_page) 5559 { 5560 u32 val = expectation->val; 5561 u32 exit_reason_want = expectation->wr_exit_reason; 5562 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 5563 bool virtualized = 5564 expectation->virtualize_apic_accesses && 5565 (exit_reason_want == VMX_APIC_WRITE || 5566 exit_reason_want == VMX_VMCALL); 5567 bool checked = false; 5568 5569 report_prefix_pushf("xapic - writing 0x%x to 0x%03x", val, reg); 5570 5571 /* Configure guest to do an xapic read */ 5572 args->op = APIC_OP_XAPIC_WR; 5573 args->apic_access_address = apic_access_address; 5574 args->reg = reg; 5575 args->val = val; 5576 5577 /* Setup virtual APIC page */ 5578 if (virtualized || !expectation->virtualize_apic_accesses) { 5579 apic_access_address[apic_reg_index(reg)] = 0; 5580 virtual_apic_page[apic_reg_index(reg)] = 0; 5581 } 5582 5583 /* Enter guest */ 5584 enter_guest(); 5585 5586 /* 5587 * Validate the behavior and 5588 * pass a magic value back to the guest. 5589 */ 5590 if (exit_reason_want == VMX_APIC_ACCESS) { 5591 u32 apic_page_offset = vmcs_read(EXI_QUALIFICATION) & 0xfff; 5592 5593 assert_exit_reason(exit_reason_want); 5594 report("got APIC access exit @ page offset 0x%03x, want 0x%03x", 5595 apic_page_offset == reg, apic_page_offset, reg); 5596 skip_exit_insn(); 5597 5598 /* Reenter guest so it can consume/check rcx and exit again. */ 5599 enter_guest(); 5600 } else if (exit_reason_want == VMX_APIC_WRITE) { 5601 assert_exit_reason(exit_reason_want); 5602 report("got APIC write exit @ page offset 0x%03x; val is 0x%x, want 0x%x", 5603 virtual_apic_page[apic_reg_index(reg)] == val, 5604 apic_reg_index(reg), 5605 virtual_apic_page[apic_reg_index(reg)], val); 5606 checked = true; 5607 5608 /* Reenter guest so it can consume/check rcx and exit again. */ 5609 enter_guest(); 5610 } else if (exit_reason_want != VMX_VMCALL) { 5611 report("Oops, bad exit expectation: %u.", false, 5612 exit_reason_want); 5613 } 5614 5615 assert_exit_reason(VMX_VMCALL); 5616 if (virtualized && !checked) { 5617 u32 want = expectation->virt_fn(val); 5618 u32 got = virtual_apic_page[apic_reg_index(reg)]; 5619 got = expectation->virt_fn(got); 5620 5621 report("exitless write; val is 0x%x, want 0x%x", 5622 got == want, got, want); 5623 } else if (!expectation->virtualize_apic_accesses && !checked) { 5624 u32 got = apic_access_address[apic_reg_index(reg)]; 5625 5626 report("non-virtualized write; val is 0x%x, want 0x%x", 5627 got == val, got, val); 5628 } else if (!expectation->virtualize_apic_accesses && checked) { 5629 report("Non-virtualized write was prematurely checked!", false); 5630 } 5631 5632 skip_exit_vmcall(); 5633 report_prefix_pop(); 5634 } 5635 5636 enum Config_type { 5637 CONFIG_TYPE_GOOD, 5638 CONFIG_TYPE_UNSUPPORTED, 5639 CONFIG_TYPE_VMENTRY_FAILS_EARLY, 5640 }; 5641 5642 static enum Config_type configure_apic_reg_virt_test( 5643 struct apic_reg_virt_config *apic_reg_virt_config) 5644 { 5645 u32 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 5646 u32 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 5647 /* Configs where L2 entry fails early, due to invalid controls. */ 5648 bool use_tpr_shadow_incorrectly_off = 5649 !apic_reg_virt_config->use_tpr_shadow && 5650 (apic_reg_virt_config->apic_register_virtualization || 5651 apic_reg_virt_config->virtualize_x2apic_mode) && 5652 apic_reg_virt_config->activate_secondary_controls; 5653 bool virtualize_apic_accesses_incorrectly_on = 5654 apic_reg_virt_config->virtualize_apic_accesses && 5655 apic_reg_virt_config->virtualize_x2apic_mode && 5656 apic_reg_virt_config->activate_secondary_controls; 5657 bool vmentry_fails_early = 5658 use_tpr_shadow_incorrectly_off || 5659 virtualize_apic_accesses_incorrectly_on; 5660 5661 if (apic_reg_virt_config->activate_secondary_controls) { 5662 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 5663 printf("VM-execution control \"activate secondary controls\" NOT supported.\n"); 5664 return CONFIG_TYPE_UNSUPPORTED; 5665 } 5666 cpu_exec_ctrl0 |= CPU_SECONDARY; 5667 } else { 5668 cpu_exec_ctrl0 &= ~CPU_SECONDARY; 5669 } 5670 5671 if (apic_reg_virt_config->virtualize_apic_accesses) { 5672 if (!(ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES)) { 5673 printf("VM-execution control \"virtualize APIC accesses\" NOT supported.\n"); 5674 return CONFIG_TYPE_UNSUPPORTED; 5675 } 5676 cpu_exec_ctrl1 |= CPU_VIRT_APIC_ACCESSES; 5677 } else { 5678 cpu_exec_ctrl1 &= ~CPU_VIRT_APIC_ACCESSES; 5679 } 5680 5681 if (apic_reg_virt_config->use_tpr_shadow) { 5682 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) { 5683 printf("VM-execution control \"use TPR shadow\" NOT supported.\n"); 5684 return CONFIG_TYPE_UNSUPPORTED; 5685 } 5686 cpu_exec_ctrl0 |= CPU_TPR_SHADOW; 5687 } else { 5688 cpu_exec_ctrl0 &= ~CPU_TPR_SHADOW; 5689 } 5690 5691 if (apic_reg_virt_config->apic_register_virtualization) { 5692 if (!(ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT)) { 5693 printf("VM-execution control \"APIC-register virtualization\" NOT supported.\n"); 5694 return CONFIG_TYPE_UNSUPPORTED; 5695 } 5696 cpu_exec_ctrl1 |= CPU_APIC_REG_VIRT; 5697 } else { 5698 cpu_exec_ctrl1 &= ~CPU_APIC_REG_VIRT; 5699 } 5700 5701 if (apic_reg_virt_config->virtualize_x2apic_mode) { 5702 if (!(ctrl_cpu_rev[1].clr & CPU_VIRT_X2APIC)) { 5703 printf("VM-execution control \"virtualize x2APIC mode\" NOT supported.\n"); 5704 return CONFIG_TYPE_UNSUPPORTED; 5705 } 5706 cpu_exec_ctrl1 |= CPU_VIRT_X2APIC; 5707 } else { 5708 cpu_exec_ctrl1 &= ~CPU_VIRT_X2APIC; 5709 } 5710 5711 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 5712 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 5713 5714 if (vmentry_fails_early) 5715 return CONFIG_TYPE_VMENTRY_FAILS_EARLY; 5716 5717 return CONFIG_TYPE_GOOD; 5718 } 5719 5720 static bool cpu_has_apicv(void) 5721 { 5722 return ((ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT) && 5723 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 5724 (ctrl_pin_rev.clr & PIN_POST_INTR)); 5725 } 5726 5727 /* Validates APIC register access across valid virtualization configurations. */ 5728 static void apic_reg_virt_test(void) 5729 { 5730 u32 *apic_access_address; 5731 u32 *virtual_apic_page; 5732 u64 control; 5733 u64 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 5734 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 5735 int i; 5736 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 5737 5738 if (!cpu_has_apicv()) { 5739 report_skip(__func__); 5740 return; 5741 } 5742 5743 control = cpu_exec_ctrl1; 5744 control &= ~CPU_VINTD; 5745 vmcs_write(CPU_EXEC_CTRL1, control); 5746 5747 test_set_guest(apic_reg_virt_guest); 5748 5749 /* 5750 * From the SDM: The 1-setting of the "virtualize APIC accesses" 5751 * VM-execution is guaranteed to apply only if translations to the 5752 * APIC-access address use a 4-KByte page. 5753 */ 5754 apic_access_address = alloc_page(); 5755 force_4k_page(apic_access_address); 5756 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_address)); 5757 5758 virtual_apic_page = alloc_page(); 5759 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 5760 5761 for (i = 0; i < ARRAY_SIZE(apic_reg_tests); i++) { 5762 struct apic_reg_test *apic_reg_test = &apic_reg_tests[i]; 5763 struct apic_reg_virt_config *apic_reg_virt_config = 5764 &apic_reg_test->apic_reg_virt_config; 5765 enum Config_type config_type; 5766 u32 reg; 5767 5768 printf("--- %s test ---\n", apic_reg_test->name); 5769 config_type = 5770 configure_apic_reg_virt_test(apic_reg_virt_config); 5771 if (config_type == CONFIG_TYPE_UNSUPPORTED) { 5772 printf("Skip because of missing features.\n"); 5773 continue; 5774 } 5775 5776 if (config_type == CONFIG_TYPE_VMENTRY_FAILS_EARLY) { 5777 enter_guest_with_bad_controls(); 5778 continue; 5779 } 5780 5781 for (reg = 0; reg < PAGE_SIZE / sizeof(u32); reg += 0x10) { 5782 struct apic_reg_virt_expectation expectation = {}; 5783 bool ok; 5784 5785 ok = apic_reg_virt_exit_expectation( 5786 reg, apic_reg_virt_config, &expectation); 5787 if (!ok) { 5788 report("Malformed test.", false); 5789 break; 5790 } 5791 5792 test_xapic_rd(reg, &expectation, apic_access_address, 5793 virtual_apic_page); 5794 test_xapic_wr(reg, &expectation, apic_access_address, 5795 virtual_apic_page); 5796 } 5797 } 5798 5799 /* Terminate the guest */ 5800 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 5801 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 5802 args->op = TERMINATE; 5803 enter_guest(); 5804 assert_exit_reason(VMX_VMCALL); 5805 } 5806 5807 struct virt_x2apic_mode_config { 5808 struct apic_reg_virt_config apic_reg_virt_config; 5809 bool virtual_interrupt_delivery; 5810 bool use_msr_bitmaps; 5811 bool disable_x2apic_msr_intercepts; 5812 bool disable_x2apic; 5813 }; 5814 5815 struct virt_x2apic_mode_test_case { 5816 const char *name; 5817 struct virt_x2apic_mode_config virt_x2apic_mode_config; 5818 }; 5819 5820 enum Virt_x2apic_mode_behavior_type { 5821 X2APIC_ACCESS_VIRTUALIZED, 5822 X2APIC_ACCESS_PASSED_THROUGH, 5823 X2APIC_ACCESS_TRIGGERS_GP, 5824 }; 5825 5826 struct virt_x2apic_mode_expectation { 5827 enum Reason rd_exit_reason; 5828 enum Reason wr_exit_reason; 5829 5830 /* 5831 * RDMSR and WRMSR handle 64-bit values. However, except for ICR, all of 5832 * the x2APIC registers are 32 bits. Notice: 5833 * 1. vmx_x2apic_read() clears the upper 32 bits for 32-bit registers. 5834 * 2. vmx_x2apic_write() expects the val arg to be well-formed. 5835 */ 5836 u64 rd_val; 5837 u64 wr_val; 5838 5839 /* 5840 * Compares input to virtualized output; 5841 * 1st arg is pointer to return expected virtualization output. 5842 */ 5843 u64 (*virt_fn)(u64); 5844 5845 enum Virt_x2apic_mode_behavior_type rd_behavior; 5846 enum Virt_x2apic_mode_behavior_type wr_behavior; 5847 bool wr_only; 5848 }; 5849 5850 static u64 virt_x2apic_mode_identity(u64 val) 5851 { 5852 return val; 5853 } 5854 5855 static u64 virt_x2apic_mode_nibble1(u64 val) 5856 { 5857 return val & 0xf0; 5858 } 5859 5860 static bool is_cmci_enabled(void) 5861 { 5862 return rdmsr(MSR_IA32_MCG_CAP) & BIT_ULL(10); 5863 } 5864 5865 static void virt_x2apic_mode_rd_expectation( 5866 u32 reg, bool virt_x2apic_mode_on, bool disable_x2apic, 5867 bool apic_register_virtualization, bool virtual_interrupt_delivery, 5868 struct virt_x2apic_mode_expectation *expectation) 5869 { 5870 bool readable = 5871 !x2apic_reg_reserved(reg) && 5872 reg != APIC_EOI; 5873 5874 if (reg == APIC_CMCI && !is_cmci_enabled()) 5875 readable = false; 5876 5877 expectation->rd_exit_reason = VMX_VMCALL; 5878 expectation->virt_fn = virt_x2apic_mode_identity; 5879 if (virt_x2apic_mode_on && apic_register_virtualization) { 5880 expectation->rd_val = MAGIC_VAL_1; 5881 if (reg == APIC_PROCPRI && virtual_interrupt_delivery) 5882 expectation->virt_fn = virt_x2apic_mode_nibble1; 5883 else if (reg == APIC_TASKPRI) 5884 expectation->virt_fn = virt_x2apic_mode_nibble1; 5885 expectation->rd_behavior = X2APIC_ACCESS_VIRTUALIZED; 5886 } else if (virt_x2apic_mode_on && !apic_register_virtualization && 5887 reg == APIC_TASKPRI) { 5888 expectation->rd_val = MAGIC_VAL_1; 5889 expectation->virt_fn = virt_x2apic_mode_nibble1; 5890 expectation->rd_behavior = X2APIC_ACCESS_VIRTUALIZED; 5891 } else if (!disable_x2apic && readable) { 5892 expectation->rd_val = apic_read(reg); 5893 expectation->rd_behavior = X2APIC_ACCESS_PASSED_THROUGH; 5894 } else { 5895 expectation->rd_behavior = X2APIC_ACCESS_TRIGGERS_GP; 5896 } 5897 } 5898 5899 /* 5900 * get_x2apic_wr_val() creates an innocuous write value for an x2APIC register. 5901 * 5902 * For writable registers, get_x2apic_wr_val() deposits the write value into the 5903 * val pointer arg and returns true. For non-writable registers, val is not 5904 * modified and get_x2apic_wr_val() returns false. 5905 */ 5906 static bool get_x2apic_wr_val(u32 reg, u64 *val) 5907 { 5908 switch (reg) { 5909 case APIC_TASKPRI: 5910 /* Bits 31:8 are reserved. */ 5911 *val &= 0xff; 5912 break; 5913 case APIC_EOI: 5914 case APIC_ESR: 5915 case APIC_TMICT: 5916 /* 5917 * EOI, ESR: WRMSR of a non-zero value causes #GP(0). 5918 * TMICT: A write of 0 to the initial-count register effectively 5919 * stops the local APIC timer, in both one-shot and 5920 * periodic mode. 5921 */ 5922 *val = 0; 5923 break; 5924 case APIC_SPIV: 5925 case APIC_LVTT: 5926 case APIC_LVTTHMR: 5927 case APIC_LVTPC: 5928 case APIC_LVT0: 5929 case APIC_LVT1: 5930 case APIC_LVTERR: 5931 case APIC_TDCR: 5932 /* 5933 * To avoid writing a 1 to a reserved bit or causing some other 5934 * unintended side effect, read the current value and use it as 5935 * the write value. 5936 */ 5937 *val = apic_read(reg); 5938 break; 5939 case APIC_CMCI: 5940 if (!is_cmci_enabled()) 5941 return false; 5942 *val = apic_read(reg); 5943 break; 5944 case APIC_ICR: 5945 *val = 0x40000 | 0xf1; 5946 break; 5947 case APIC_SELF_IPI: 5948 /* 5949 * With special processing (i.e., virtualize x2APIC mode + 5950 * virtual interrupt delivery), writing zero causes an 5951 * APIC-write VM exit. We plan to add a test for enabling 5952 * "virtual-interrupt delivery" in VMCS12, and that's where we 5953 * will test a self IPI with special processing. 5954 */ 5955 *val = 0x0; 5956 break; 5957 default: 5958 return false; 5959 } 5960 5961 return true; 5962 } 5963 5964 static bool special_processing_applies(u32 reg, u64 *val, 5965 bool virt_int_delivery) 5966 { 5967 bool special_processing = 5968 (reg == APIC_TASKPRI) || 5969 (virt_int_delivery && 5970 (reg == APIC_EOI || reg == APIC_SELF_IPI)); 5971 5972 if (special_processing) { 5973 TEST_ASSERT(get_x2apic_wr_val(reg, val)); 5974 return true; 5975 } 5976 5977 return false; 5978 } 5979 5980 static void virt_x2apic_mode_wr_expectation( 5981 u32 reg, bool virt_x2apic_mode_on, bool disable_x2apic, 5982 bool virt_int_delivery, 5983 struct virt_x2apic_mode_expectation *expectation) 5984 { 5985 expectation->wr_exit_reason = VMX_VMCALL; 5986 expectation->wr_val = MAGIC_VAL_1; 5987 expectation->wr_only = false; 5988 5989 if (virt_x2apic_mode_on && 5990 special_processing_applies(reg, &expectation->wr_val, 5991 virt_int_delivery)) { 5992 expectation->wr_behavior = X2APIC_ACCESS_VIRTUALIZED; 5993 if (reg == APIC_SELF_IPI) 5994 expectation->wr_exit_reason = VMX_APIC_WRITE; 5995 } else if (!disable_x2apic && 5996 get_x2apic_wr_val(reg, &expectation->wr_val)) { 5997 expectation->wr_behavior = X2APIC_ACCESS_PASSED_THROUGH; 5998 if (reg == APIC_EOI || reg == APIC_SELF_IPI) 5999 expectation->wr_only = true; 6000 if (reg == APIC_ICR) 6001 expectation->wr_exit_reason = VMX_EXTINT; 6002 } else { 6003 expectation->wr_behavior = X2APIC_ACCESS_TRIGGERS_GP; 6004 /* 6005 * Writing 1 to a reserved bit triggers a #GP. 6006 * Thus, set the write value to 0, which seems 6007 * the most likely to detect a missed #GP. 6008 */ 6009 expectation->wr_val = 0; 6010 } 6011 } 6012 6013 static void virt_x2apic_mode_exit_expectation( 6014 u32 reg, struct virt_x2apic_mode_config *config, 6015 struct virt_x2apic_mode_expectation *expectation) 6016 { 6017 struct apic_reg_virt_config *base_config = 6018 &config->apic_reg_virt_config; 6019 bool virt_x2apic_mode_on = 6020 base_config->virtualize_x2apic_mode && 6021 config->use_msr_bitmaps && 6022 config->disable_x2apic_msr_intercepts && 6023 base_config->activate_secondary_controls; 6024 6025 virt_x2apic_mode_wr_expectation( 6026 reg, virt_x2apic_mode_on, config->disable_x2apic, 6027 config->virtual_interrupt_delivery, expectation); 6028 virt_x2apic_mode_rd_expectation( 6029 reg, virt_x2apic_mode_on, config->disable_x2apic, 6030 base_config->apic_register_virtualization, 6031 config->virtual_interrupt_delivery, expectation); 6032 } 6033 6034 struct virt_x2apic_mode_test_case virt_x2apic_mode_tests[] = { 6035 /* 6036 * Baseline "virtualize x2APIC mode" configuration: 6037 * - virtualize x2APIC mode 6038 * - virtual-interrupt delivery 6039 * - APIC-register virtualization 6040 * - x2APIC MSR intercepts disabled 6041 * 6042 * Reads come from virtual APIC page, special processing applies to 6043 * VTPR, EOI, and SELF IPI, and all other writes pass through to L1 6044 * APIC. 6045 */ 6046 { 6047 .name = "Baseline", 6048 .virt_x2apic_mode_config = { 6049 .virtual_interrupt_delivery = true, 6050 .use_msr_bitmaps = true, 6051 .disable_x2apic_msr_intercepts = true, 6052 .disable_x2apic = false, 6053 .apic_reg_virt_config = { 6054 .apic_register_virtualization = true, 6055 .use_tpr_shadow = true, 6056 .virtualize_apic_accesses = false, 6057 .virtualize_x2apic_mode = true, 6058 .activate_secondary_controls = true, 6059 }, 6060 }, 6061 }, 6062 { 6063 .name = "Baseline w/ x2apic disabled", 6064 .virt_x2apic_mode_config = { 6065 .virtual_interrupt_delivery = true, 6066 .use_msr_bitmaps = true, 6067 .disable_x2apic_msr_intercepts = true, 6068 .disable_x2apic = true, 6069 .apic_reg_virt_config = { 6070 .apic_register_virtualization = true, 6071 .use_tpr_shadow = true, 6072 .virtualize_apic_accesses = false, 6073 .virtualize_x2apic_mode = true, 6074 .activate_secondary_controls = true, 6075 }, 6076 }, 6077 }, 6078 6079 /* 6080 * Baseline, minus virtual-interrupt delivery. Reads come from virtual 6081 * APIC page, special processing applies to VTPR, and all other writes 6082 * pass through to L1 APIC. 6083 */ 6084 { 6085 .name = "Baseline - virtual interrupt delivery", 6086 .virt_x2apic_mode_config = { 6087 .virtual_interrupt_delivery = false, 6088 .use_msr_bitmaps = true, 6089 .disable_x2apic_msr_intercepts = true, 6090 .disable_x2apic = false, 6091 .apic_reg_virt_config = { 6092 .apic_register_virtualization = true, 6093 .use_tpr_shadow = true, 6094 .virtualize_apic_accesses = false, 6095 .virtualize_x2apic_mode = true, 6096 .activate_secondary_controls = true, 6097 }, 6098 }, 6099 }, 6100 6101 /* 6102 * Baseline, minus APIC-register virtualization. x2APIC reads pass 6103 * through to L1's APIC, unless reading VTPR 6104 */ 6105 { 6106 .name = "Virtualize x2APIC mode, no APIC reg virt", 6107 .virt_x2apic_mode_config = { 6108 .virtual_interrupt_delivery = true, 6109 .use_msr_bitmaps = true, 6110 .disable_x2apic_msr_intercepts = true, 6111 .disable_x2apic = false, 6112 .apic_reg_virt_config = { 6113 .apic_register_virtualization = false, 6114 .use_tpr_shadow = true, 6115 .virtualize_apic_accesses = false, 6116 .virtualize_x2apic_mode = true, 6117 .activate_secondary_controls = true, 6118 }, 6119 }, 6120 }, 6121 { 6122 .name = "Virtualize x2APIC mode, no APIC reg virt, x2APIC off", 6123 .virt_x2apic_mode_config = { 6124 .virtual_interrupt_delivery = true, 6125 .use_msr_bitmaps = true, 6126 .disable_x2apic_msr_intercepts = true, 6127 .disable_x2apic = true, 6128 .apic_reg_virt_config = { 6129 .apic_register_virtualization = false, 6130 .use_tpr_shadow = true, 6131 .virtualize_apic_accesses = false, 6132 .virtualize_x2apic_mode = true, 6133 .activate_secondary_controls = true, 6134 }, 6135 }, 6136 }, 6137 6138 /* 6139 * Enable "virtualize x2APIC mode" and "APIC-register virtualization", 6140 * and disable intercepts for the x2APIC MSRs, but fail to enable 6141 * "activate secondary controls" (i.e. L2 gets access to L1's x2APIC 6142 * MSRs). 6143 */ 6144 { 6145 .name = "Fail to enable activate secondary controls", 6146 .virt_x2apic_mode_config = { 6147 .virtual_interrupt_delivery = true, 6148 .use_msr_bitmaps = true, 6149 .disable_x2apic_msr_intercepts = true, 6150 .disable_x2apic = false, 6151 .apic_reg_virt_config = { 6152 .apic_register_virtualization = true, 6153 .use_tpr_shadow = true, 6154 .virtualize_apic_accesses = false, 6155 .virtualize_x2apic_mode = true, 6156 .activate_secondary_controls = false, 6157 }, 6158 }, 6159 }, 6160 6161 /* 6162 * Enable "APIC-register virtualization" and enable "activate secondary 6163 * controls" and disable intercepts for the x2APIC MSRs, but do not 6164 * enable the "virtualize x2APIC mode" VM-execution control (i.e. L2 6165 * gets access to L1's x2APIC MSRs). 6166 */ 6167 { 6168 .name = "Fail to enable virtualize x2APIC mode", 6169 .virt_x2apic_mode_config = { 6170 .virtual_interrupt_delivery = true, 6171 .use_msr_bitmaps = true, 6172 .disable_x2apic_msr_intercepts = true, 6173 .disable_x2apic = false, 6174 .apic_reg_virt_config = { 6175 .apic_register_virtualization = true, 6176 .use_tpr_shadow = true, 6177 .virtualize_apic_accesses = false, 6178 .virtualize_x2apic_mode = false, 6179 .activate_secondary_controls = true, 6180 }, 6181 }, 6182 }, 6183 6184 /* 6185 * Disable "Virtualize x2APIC mode", disable x2APIC MSR intercepts, and 6186 * enable "APIC-register virtualization" --> L2 gets L1's x2APIC MSRs. 6187 */ 6188 { 6189 .name = "Baseline", 6190 .virt_x2apic_mode_config = { 6191 .virtual_interrupt_delivery = true, 6192 .use_msr_bitmaps = true, 6193 .disable_x2apic_msr_intercepts = true, 6194 .disable_x2apic = false, 6195 .apic_reg_virt_config = { 6196 .apic_register_virtualization = true, 6197 .use_tpr_shadow = true, 6198 .virtualize_apic_accesses = false, 6199 .virtualize_x2apic_mode = false, 6200 .activate_secondary_controls = true, 6201 }, 6202 }, 6203 }, 6204 }; 6205 6206 enum X2apic_op { 6207 X2APIC_OP_RD, 6208 X2APIC_OP_WR, 6209 X2APIC_TERMINATE, 6210 }; 6211 6212 static u64 vmx_x2apic_read(u32 reg) 6213 { 6214 u32 msr_addr = x2apic_msr(reg); 6215 u64 val; 6216 6217 val = rdmsr(msr_addr); 6218 6219 return val; 6220 } 6221 6222 static void vmx_x2apic_write(u32 reg, u64 val) 6223 { 6224 u32 msr_addr = x2apic_msr(reg); 6225 6226 wrmsr(msr_addr, val); 6227 } 6228 6229 struct virt_x2apic_mode_guest_args { 6230 enum X2apic_op op; 6231 u32 reg; 6232 u64 val; 6233 bool should_gp; 6234 u64 (*virt_fn)(u64); 6235 } virt_x2apic_mode_guest_args; 6236 6237 static volatile bool handle_x2apic_gp_ran; 6238 static volatile u32 handle_x2apic_gp_insn_len; 6239 static void handle_x2apic_gp(struct ex_regs *regs) 6240 { 6241 handle_x2apic_gp_ran = true; 6242 regs->rip += handle_x2apic_gp_insn_len; 6243 } 6244 6245 static handler setup_x2apic_gp_handler(void) 6246 { 6247 handler old_handler; 6248 6249 old_handler = handle_exception(GP_VECTOR, handle_x2apic_gp); 6250 /* RDMSR and WRMSR are both 2 bytes, assuming no prefixes. */ 6251 handle_x2apic_gp_insn_len = 2; 6252 6253 return old_handler; 6254 } 6255 6256 static void teardown_x2apic_gp_handler(handler old_handler) 6257 { 6258 handle_exception(GP_VECTOR, old_handler); 6259 6260 /* 6261 * Defensively reset instruction length, so that if the handler is 6262 * incorrectly used, it will loop infinitely, rather than run off into 6263 * la la land. 6264 */ 6265 handle_x2apic_gp_insn_len = 0; 6266 handle_x2apic_gp_ran = false; 6267 } 6268 6269 static void virt_x2apic_mode_guest(void) 6270 { 6271 volatile struct virt_x2apic_mode_guest_args *args = 6272 &virt_x2apic_mode_guest_args; 6273 6274 for (;;) { 6275 enum X2apic_op op = args->op; 6276 u32 reg = args->reg; 6277 u64 val = args->val; 6278 bool should_gp = args->should_gp; 6279 u64 (*virt_fn)(u64) = args->virt_fn; 6280 handler old_handler; 6281 6282 if (op == X2APIC_TERMINATE) 6283 break; 6284 6285 if (should_gp) { 6286 TEST_ASSERT(!handle_x2apic_gp_ran); 6287 old_handler = setup_x2apic_gp_handler(); 6288 } 6289 6290 if (op == X2APIC_OP_RD) { 6291 u64 ret = vmx_x2apic_read(reg); 6292 6293 if (!should_gp) { 6294 u64 want = virt_fn(val); 6295 u64 got = virt_fn(ret); 6296 6297 report("APIC read; got 0x%lx, want 0x%lx.", 6298 got == want, got, want); 6299 } 6300 } else if (op == X2APIC_OP_WR) { 6301 vmx_x2apic_write(reg, val); 6302 } 6303 6304 if (should_gp) { 6305 report("x2APIC op triggered GP.", 6306 handle_x2apic_gp_ran); 6307 teardown_x2apic_gp_handler(old_handler); 6308 } 6309 6310 /* 6311 * The L1 should always execute a vmcall after it's done testing 6312 * an individual APIC operation. This helps to validate that the 6313 * L1 and L2 are in sync with each other, as expected. 6314 */ 6315 vmcall(); 6316 } 6317 } 6318 6319 static void test_x2apic_rd( 6320 u32 reg, struct virt_x2apic_mode_expectation *expectation, 6321 u32 *virtual_apic_page) 6322 { 6323 u64 val = expectation->rd_val; 6324 u32 exit_reason_want = expectation->rd_exit_reason; 6325 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6326 6327 report_prefix_pushf("x2apic - reading 0x%03x", reg); 6328 6329 /* Configure guest to do an x2apic read */ 6330 args->op = X2APIC_OP_RD; 6331 args->reg = reg; 6332 args->val = val; 6333 args->should_gp = expectation->rd_behavior == X2APIC_ACCESS_TRIGGERS_GP; 6334 args->virt_fn = expectation->virt_fn; 6335 6336 /* Setup virtual APIC page */ 6337 if (expectation->rd_behavior == X2APIC_ACCESS_VIRTUALIZED) 6338 virtual_apic_page[apic_reg_index(reg)] = (u32)val; 6339 6340 /* Enter guest */ 6341 enter_guest(); 6342 6343 if (exit_reason_want != VMX_VMCALL) { 6344 report("Oops, bad exit expectation: %u.", false, 6345 exit_reason_want); 6346 } 6347 6348 skip_exit_vmcall(); 6349 report_prefix_pop(); 6350 } 6351 6352 static volatile bool handle_x2apic_ipi_ran; 6353 static void handle_x2apic_ipi(isr_regs_t *regs) 6354 { 6355 handle_x2apic_ipi_ran = true; 6356 eoi(); 6357 } 6358 6359 static void test_x2apic_wr( 6360 u32 reg, struct virt_x2apic_mode_expectation *expectation, 6361 u32 *virtual_apic_page) 6362 { 6363 u64 val = expectation->wr_val; 6364 u32 exit_reason_want = expectation->wr_exit_reason; 6365 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6366 int ipi_vector = 0xf1; 6367 u32 restore_val = 0; 6368 6369 report_prefix_pushf("x2apic - writing 0x%lx to 0x%03x", val, reg); 6370 6371 /* Configure guest to do an x2apic read */ 6372 args->op = X2APIC_OP_WR; 6373 args->reg = reg; 6374 args->val = val; 6375 args->should_gp = expectation->wr_behavior == X2APIC_ACCESS_TRIGGERS_GP; 6376 6377 /* Setup virtual APIC page */ 6378 if (expectation->wr_behavior == X2APIC_ACCESS_VIRTUALIZED) 6379 virtual_apic_page[apic_reg_index(reg)] = 0; 6380 if (expectation->wr_behavior == X2APIC_ACCESS_PASSED_THROUGH && !expectation->wr_only) 6381 restore_val = apic_read(reg); 6382 6383 /* Setup IPI handler */ 6384 handle_x2apic_ipi_ran = false; 6385 handle_irq(ipi_vector, handle_x2apic_ipi); 6386 6387 /* Enter guest */ 6388 enter_guest(); 6389 6390 /* 6391 * Validate the behavior and 6392 * pass a magic value back to the guest. 6393 */ 6394 if (exit_reason_want == VMX_EXTINT) { 6395 assert_exit_reason(exit_reason_want); 6396 6397 /* Clear the external interrupt. */ 6398 irq_enable(); 6399 asm volatile ("nop"); 6400 irq_disable(); 6401 report("Got pending interrupt after IRQ enabled.", 6402 handle_x2apic_ipi_ran); 6403 6404 enter_guest(); 6405 } else if (exit_reason_want == VMX_APIC_WRITE) { 6406 assert_exit_reason(exit_reason_want); 6407 report("got APIC write exit @ page offset 0x%03x; val is 0x%x, want 0x%lx", 6408 virtual_apic_page[apic_reg_index(reg)] == val, 6409 apic_reg_index(reg), 6410 virtual_apic_page[apic_reg_index(reg)], val); 6411 6412 /* Reenter guest so it can consume/check rcx and exit again. */ 6413 enter_guest(); 6414 } else if (exit_reason_want != VMX_VMCALL) { 6415 report("Oops, bad exit expectation: %u.", false, 6416 exit_reason_want); 6417 } 6418 6419 assert_exit_reason(VMX_VMCALL); 6420 if (expectation->wr_behavior == X2APIC_ACCESS_VIRTUALIZED) { 6421 u64 want = val; 6422 u32 got = virtual_apic_page[apic_reg_index(reg)]; 6423 6424 report("x2APIC write; got 0x%x, want 0x%lx", 6425 got == want, got, want); 6426 } else if (expectation->wr_behavior == X2APIC_ACCESS_PASSED_THROUGH) { 6427 if (!expectation->wr_only) { 6428 u32 got = apic_read(reg); 6429 bool ok; 6430 6431 /* 6432 * When L1's TPR is passed through to L2, the lower 6433 * nibble can be lost. For example, if L2 executes 6434 * WRMSR(0x808, 0x78), then, L1 might read 0x70. 6435 * 6436 * Here's how the lower nibble can get lost: 6437 * 1. L2 executes WRMSR(0x808, 0x78). 6438 * 2. L2 exits to L0 with a WRMSR exit. 6439 * 3. L0 emulates WRMSR, by writing L1's TPR. 6440 * 4. L0 re-enters L2. 6441 * 5. L2 exits to L0 (reason doesn't matter). 6442 * 6. L0 reflects L2's exit to L1. 6443 * 7. Before entering L1, L0 exits to user-space 6444 * (e.g., to satisfy TPR access reporting). 6445 * 8. User-space executes KVM_SET_REGS ioctl, which 6446 * clears the lower nibble of L1's TPR. 6447 */ 6448 if (reg == APIC_TASKPRI) { 6449 got = apic_virt_nibble1(got); 6450 val = apic_virt_nibble1(val); 6451 } 6452 6453 ok = got == val; 6454 report("non-virtualized write; val is 0x%x, want 0x%lx", 6455 ok, got, val); 6456 apic_write(reg, restore_val); 6457 } else { 6458 report("non-virtualized and write-only OK", true); 6459 } 6460 } 6461 skip_exit_insn(); 6462 6463 report_prefix_pop(); 6464 } 6465 6466 static enum Config_type configure_virt_x2apic_mode_test( 6467 struct virt_x2apic_mode_config *virt_x2apic_mode_config, 6468 u8 *msr_bitmap_page) 6469 { 6470 int msr; 6471 u32 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6472 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6473 6474 /* x2apic-specific VMCS config */ 6475 if (virt_x2apic_mode_config->use_msr_bitmaps) { 6476 /* virt_x2apic_mode_test() checks for MSR bitmaps support */ 6477 cpu_exec_ctrl0 |= CPU_MSR_BITMAP; 6478 } else { 6479 cpu_exec_ctrl0 &= ~CPU_MSR_BITMAP; 6480 } 6481 6482 if (virt_x2apic_mode_config->virtual_interrupt_delivery) { 6483 if (!(ctrl_cpu_rev[1].clr & CPU_VINTD)) { 6484 report_skip("VM-execution control \"virtual-interrupt delivery\" NOT supported.\n"); 6485 return CONFIG_TYPE_UNSUPPORTED; 6486 } 6487 cpu_exec_ctrl1 |= CPU_VINTD; 6488 } else { 6489 cpu_exec_ctrl1 &= ~CPU_VINTD; 6490 } 6491 6492 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6493 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6494 6495 /* x2APIC MSR intercepts are usually off for "Virtualize x2APIC mode" */ 6496 for (msr = 0x800; msr <= 0x8ff; msr++) { 6497 if (virt_x2apic_mode_config->disable_x2apic_msr_intercepts) { 6498 clear_bit(msr, msr_bitmap_page + 0x000); 6499 clear_bit(msr, msr_bitmap_page + 0x800); 6500 } else { 6501 set_bit(msr, msr_bitmap_page + 0x000); 6502 set_bit(msr, msr_bitmap_page + 0x800); 6503 } 6504 } 6505 6506 /* x2APIC mode can impact virtualization */ 6507 reset_apic(); 6508 if (!virt_x2apic_mode_config->disable_x2apic) 6509 enable_x2apic(); 6510 6511 return configure_apic_reg_virt_test( 6512 &virt_x2apic_mode_config->apic_reg_virt_config); 6513 } 6514 6515 static void virt_x2apic_mode_test(void) 6516 { 6517 u32 *virtual_apic_page; 6518 u8 *msr_bitmap_page; 6519 u64 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6520 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6521 int i; 6522 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6523 6524 if (!cpu_has_apicv()) { 6525 report_skip(__func__); 6526 return; 6527 } 6528 6529 /* 6530 * This is to exercise an issue in KVM's logic to merge L0's and L1's 6531 * MSR bitmaps. Previously, an L1 could get at L0's x2APIC MSRs by 6532 * writing the IA32_SPEC_CTRL MSR or the IA32_PRED_CMD MSRs. KVM would 6533 * then proceed to manipulate the MSR bitmaps, as if VMCS12 had the 6534 * "Virtualize x2APIC mod" control set, even when it didn't. 6535 */ 6536 if (has_spec_ctrl()) 6537 wrmsr(MSR_IA32_SPEC_CTRL, 1); 6538 6539 /* 6540 * Check that VMCS12 supports: 6541 * - "Virtual-APIC address", indicated by "use TPR shadow" 6542 * - "MSR-bitmap address", indicated by "use MSR bitmaps" 6543 */ 6544 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) { 6545 report_skip("VM-execution control \"use TPR shadow\" NOT supported.\n"); 6546 return; 6547 } else if (!(ctrl_cpu_rev[0].clr & CPU_MSR_BITMAP)) { 6548 report_skip("VM-execution control \"use MSR bitmaps\" NOT supported.\n"); 6549 return; 6550 } 6551 6552 test_set_guest(virt_x2apic_mode_guest); 6553 6554 virtual_apic_page = alloc_page(); 6555 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 6556 6557 msr_bitmap_page = alloc_page(); 6558 memset(msr_bitmap_page, 0xff, PAGE_SIZE); 6559 vmcs_write(MSR_BITMAP, virt_to_phys(msr_bitmap_page)); 6560 6561 for (i = 0; i < ARRAY_SIZE(virt_x2apic_mode_tests); i++) { 6562 struct virt_x2apic_mode_test_case *virt_x2apic_mode_test_case = 6563 &virt_x2apic_mode_tests[i]; 6564 struct virt_x2apic_mode_config *virt_x2apic_mode_config = 6565 &virt_x2apic_mode_test_case->virt_x2apic_mode_config; 6566 enum Config_type config_type; 6567 u32 reg; 6568 6569 printf("--- %s test ---\n", virt_x2apic_mode_test_case->name); 6570 config_type = 6571 configure_virt_x2apic_mode_test(virt_x2apic_mode_config, 6572 msr_bitmap_page); 6573 if (config_type == CONFIG_TYPE_UNSUPPORTED) { 6574 report_skip("Skip because of missing features.\n"); 6575 continue; 6576 } else if (config_type == CONFIG_TYPE_VMENTRY_FAILS_EARLY) { 6577 enter_guest_with_bad_controls(); 6578 continue; 6579 } 6580 6581 for (reg = 0; reg < PAGE_SIZE / sizeof(u32); reg += 0x10) { 6582 struct virt_x2apic_mode_expectation expectation; 6583 6584 virt_x2apic_mode_exit_expectation( 6585 reg, virt_x2apic_mode_config, &expectation); 6586 6587 test_x2apic_rd(reg, &expectation, virtual_apic_page); 6588 test_x2apic_wr(reg, &expectation, virtual_apic_page); 6589 } 6590 } 6591 6592 6593 /* Terminate the guest */ 6594 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6595 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6596 args->op = X2APIC_TERMINATE; 6597 enter_guest(); 6598 assert_exit_reason(VMX_VMCALL); 6599 } 6600 6601 /* 6602 * On processors that support Intel 64 architecture, the IA32_SYSENTER_ESP 6603 * field and the IA32_SYSENTER_EIP field must each contain a canonical 6604 * address. 6605 * 6606 * [Intel SDM] 6607 */ 6608 static void test_sysenter_field(u32 field, const char *name) 6609 { 6610 u64 addr_saved = vmcs_read(field); 6611 6612 vmcs_write(field, NONCANONICAL); 6613 report_prefix_pushf("%s non-canonical", name); 6614 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, false); 6615 report_prefix_pop(); 6616 6617 vmcs_write(field, 0xffffffff); 6618 report_prefix_pushf("%s canonical", name); 6619 test_vmx_vmlaunch(0, false); 6620 report_prefix_pop(); 6621 6622 vmcs_write(field, addr_saved); 6623 } 6624 6625 static void test_ctl_reg(const char *cr_name, u64 cr, u64 fixed0, u64 fixed1) 6626 { 6627 u64 val; 6628 u64 cr_saved = vmcs_read(cr); 6629 int i; 6630 6631 val = fixed0 & fixed1; 6632 if (cr == HOST_CR4) 6633 vmcs_write(cr, val | X86_CR4_PAE); 6634 else 6635 vmcs_write(cr, val); 6636 report_prefix_pushf("%s %lx", cr_name, val); 6637 if (val == fixed0) 6638 test_vmx_vmlaunch(0, false); 6639 else 6640 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, 6641 false); 6642 report_prefix_pop(); 6643 6644 for (i = 0; i < 64; i++) { 6645 6646 /* Set a bit when the corresponding bit in fixed1 is 0 */ 6647 if ((fixed1 & (1ull << i)) == 0) { 6648 if (cr == HOST_CR4 && ((1ull << i) & X86_CR4_SMEP || 6649 (1ull << i) & X86_CR4_SMAP)) 6650 continue; 6651 6652 vmcs_write(cr, cr_saved | (1ull << i)); 6653 report_prefix_pushf("%s %llx", cr_name, 6654 cr_saved | (1ull << i)); 6655 test_vmx_vmlaunch( 6656 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, 6657 false); 6658 report_prefix_pop(); 6659 } 6660 6661 /* Unset a bit when the corresponding bit in fixed0 is 1 */ 6662 if (fixed0 & (1ull << i)) { 6663 vmcs_write(cr, cr_saved & ~(1ull << i)); 6664 report_prefix_pushf("%s %llx", cr_name, 6665 cr_saved & ~(1ull << i)); 6666 test_vmx_vmlaunch( 6667 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, 6668 false); 6669 report_prefix_pop(); 6670 } 6671 } 6672 6673 vmcs_write(cr, cr_saved); 6674 } 6675 6676 /* 6677 * 1. The CR0 field must not set any bit to a value not supported in VMX 6678 * operation. 6679 * 2. The CR4 field must not set any bit to a value not supported in VMX 6680 * operation. 6681 * 3. On processors that support Intel 64 architecture, the CR3 field must 6682 * be such that bits 63:52 and bits in the range 51:32 beyond the 6683 * processor’s physical-address width must be 0. 6684 * 6685 * [Intel SDM] 6686 */ 6687 static void test_host_ctl_regs(void) 6688 { 6689 u64 fixed0, fixed1, cr3, cr3_saved; 6690 int i; 6691 6692 /* Test CR0 */ 6693 fixed0 = rdmsr(MSR_IA32_VMX_CR0_FIXED0); 6694 fixed1 = rdmsr(MSR_IA32_VMX_CR0_FIXED1); 6695 test_ctl_reg("HOST_CR0", HOST_CR0, fixed0, fixed1); 6696 6697 /* Test CR4 */ 6698 fixed0 = rdmsr(MSR_IA32_VMX_CR4_FIXED0); 6699 fixed1 = rdmsr(MSR_IA32_VMX_CR4_FIXED1) & 6700 ~(X86_CR4_SMEP | X86_CR4_SMAP); 6701 test_ctl_reg("HOST_CR4", HOST_CR4, fixed0, fixed1); 6702 6703 /* Test CR3 */ 6704 cr3_saved = vmcs_read(HOST_CR3); 6705 for (i = cpuid_maxphyaddr(); i < 64; i++) { 6706 cr3 = cr3_saved | (1ul << i); 6707 vmcs_write(HOST_CR3, cr3); 6708 report_prefix_pushf("HOST_CR3 %lx", cr3); 6709 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, 6710 false); 6711 report_prefix_pop(); 6712 } 6713 6714 vmcs_write(HOST_CR3, cr3_saved); 6715 } 6716 6717 static void test_efer_bit(u32 fld, const char * fld_name, u32 ctrl_fld, 6718 u64 ctrl_bit, u64 efer_bit, 6719 const char *efer_bit_name) 6720 { 6721 u64 efer_saved = vmcs_read(fld); 6722 u32 ctrl_saved = vmcs_read(ctrl_fld); 6723 u64 host_addr_size = ctrl_saved & EXI_HOST_64; 6724 u64 efer; 6725 6726 vmcs_write(ctrl_fld, ctrl_saved & ~ctrl_bit); 6727 efer = efer_saved & ~efer_bit; 6728 vmcs_write(fld, efer); 6729 report_prefix_pushf("%s bit turned off, %s %lx", efer_bit_name, 6730 fld_name, efer); 6731 test_vmx_vmlaunch(0, false); 6732 report_prefix_pop(); 6733 6734 efer = efer_saved | efer_bit; 6735 vmcs_write(fld, efer); 6736 report_prefix_pushf("%s bit turned on, %s %lx", efer_bit_name, 6737 fld_name, efer); 6738 test_vmx_vmlaunch(0, false); 6739 report_prefix_pop(); 6740 6741 vmcs_write(ctrl_fld, ctrl_saved | ctrl_bit); 6742 efer = efer_saved & ~efer_bit; 6743 vmcs_write(fld, efer); 6744 report_prefix_pushf("%s bit turned off, %s %lx", efer_bit_name, 6745 fld_name, efer); 6746 if (host_addr_size) 6747 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, 6748 false); 6749 else 6750 test_vmx_vmlaunch(0, false); 6751 report_prefix_pop(); 6752 6753 efer = efer_saved | efer_bit; 6754 vmcs_write(fld, efer); 6755 report_prefix_pushf("%s bit turned on, %s %lx", efer_bit_name, 6756 fld_name, efer); 6757 if (host_addr_size) 6758 test_vmx_vmlaunch(0, false); 6759 else 6760 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, 6761 false); 6762 report_prefix_pop(); 6763 6764 vmcs_write(ctrl_fld, ctrl_saved); 6765 vmcs_write(fld, efer_saved); 6766 } 6767 6768 static void test_efer(u32 fld, const char * fld_name, u32 ctrl_fld, 6769 u64 ctrl_bit) 6770 { 6771 u64 efer_saved = vmcs_read(fld); 6772 u32 ctrl_saved = vmcs_read(ctrl_fld); 6773 u64 efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 6774 u64 i; 6775 u64 efer; 6776 6777 if (cpu_has_efer_nx()) 6778 efer_reserved_bits &= ~EFER_NX; 6779 6780 /* 6781 * Check reserved bits 6782 */ 6783 vmcs_write(ctrl_fld, ctrl_saved & ~ctrl_bit); 6784 for (i = 0; i < 64; i++) { 6785 if ((1ull << i) & efer_reserved_bits) { 6786 efer = efer_saved | (1ull << i); 6787 vmcs_write(fld, efer); 6788 report_prefix_pushf("%s %lx", fld_name, efer); 6789 test_vmx_vmlaunch(0, false); 6790 report_prefix_pop(); 6791 } 6792 } 6793 6794 vmcs_write(ctrl_fld, ctrl_saved | ctrl_bit); 6795 for (i = 0; i < 64; i++) { 6796 if ((1ull << i) & efer_reserved_bits) { 6797 efer = efer_saved | (1ull << i); 6798 vmcs_write(fld, efer); 6799 report_prefix_pushf("%s %lx", fld_name, efer); 6800 test_vmx_vmlaunch( 6801 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, 6802 false); 6803 report_prefix_pop(); 6804 } 6805 } 6806 6807 vmcs_write(ctrl_fld, ctrl_saved); 6808 vmcs_write(fld, efer_saved); 6809 6810 /* 6811 * Check LMA and LME bits 6812 */ 6813 test_efer_bit(fld, fld_name, ctrl_fld, ctrl_bit, EFER_LMA, 6814 "EFER_LMA"); 6815 test_efer_bit(fld, fld_name, ctrl_fld, ctrl_bit, EFER_LME, 6816 "EFER_LME"); 6817 } 6818 6819 /* 6820 * If the “load IA32_EFER†VM-exit control is 1, bits reserved in the 6821 * IA32_EFER MSR must be 0 in the field for that register. In addition, 6822 * the values of the LMA and LME bits in the field must each be that of 6823 * the “host address-space size†VM-exit control. 6824 * 6825 * [Intel SDM] 6826 */ 6827 static void test_host_efer(void) 6828 { 6829 if (!(ctrl_exit_rev.clr & EXI_LOAD_EFER)) { 6830 printf("\"Load-IA32-EFER\" exit control not supported\n"); 6831 return; 6832 } 6833 6834 test_efer(HOST_EFER, "HOST_EFER", EXI_CONTROLS, EXI_LOAD_EFER); 6835 } 6836 6837 /* 6838 * PAT values higher than 8 are uninteresting since they're likely lumped 6839 * in with "8". We only test values above 8 one bit at a time, 6840 * in order to reduce the number of VM-Entries and keep the runtime reasonable. 6841 */ 6842 #define PAT_VAL_LIMIT 8 6843 6844 static void test_pat(u32 field, const char * field_name, u32 ctrl_field, 6845 u64 ctrl_bit) 6846 { 6847 u32 ctrl_saved = vmcs_read(ctrl_field); 6848 u64 pat_saved = vmcs_read(field); 6849 u64 i, val; 6850 u32 j; 6851 int error; 6852 6853 vmcs_clear_bits(ctrl_field, ctrl_bit); 6854 if (field == GUEST_PAT) { 6855 vmx_set_test_stage(1); 6856 test_set_guest(guest_state_test_main); 6857 } 6858 6859 for (i = 0; i < 256; i = (i < PAT_VAL_LIMIT) ? i + 1 : i * 2) { 6860 /* Test PAT0..PAT7 fields */ 6861 for (j = 0; j < (i ? 8 : 1); j++) { 6862 val = i << j * 8; 6863 vmcs_write(field, val); 6864 if (field == HOST_PAT) { 6865 report_prefix_pushf("%s %lx", field_name, val); 6866 test_vmx_vmlaunch(0, false); 6867 report_prefix_pop(); 6868 6869 } else { // GUEST_PAT 6870 enter_guest(); 6871 report_guest_state_test("ENT_LOAD_PAT enabled", 6872 VMX_VMCALL, val, 6873 "GUEST_PAT"); 6874 } 6875 } 6876 } 6877 6878 vmcs_set_bits(ctrl_field, ctrl_bit); 6879 for (i = 0; i < 256; i = (i < PAT_VAL_LIMIT) ? i + 1 : i * 2) { 6880 /* Test PAT0..PAT7 fields */ 6881 for (j = 0; j < (i ? 8 : 1); j++) { 6882 val = i << j * 8; 6883 vmcs_write(field, val); 6884 6885 if (field == HOST_PAT) { 6886 report_prefix_pushf("%s %lx", field_name, val); 6887 if (i == 0x2 || i == 0x3 || i >= 0x8) 6888 error = 6889 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD; 6890 else 6891 error = 0; 6892 6893 test_vmx_vmlaunch(error, false); 6894 report_prefix_pop(); 6895 6896 } else { // GUEST_PAT 6897 if (i == 0x2 || i == 0x3 || i >= 0x8) { 6898 enter_guest_with_invalid_guest_state(); 6899 report_guest_state_test("ENT_LOAD_PAT " 6900 "enabled", 6901 VMX_FAIL_STATE | VMX_ENTRY_FAILURE, 6902 val, 6903 "GUEST_PAT"); 6904 } else { 6905 enter_guest(); 6906 report_guest_state_test("ENT_LOAD_PAT " 6907 "enabled", 6908 VMX_VMCALL, 6909 val, 6910 "GUEST_PAT"); 6911 } 6912 } 6913 6914 } 6915 } 6916 6917 if (field == GUEST_PAT) { 6918 /* 6919 * Let the guest finish execution 6920 */ 6921 vmx_set_test_stage(2); 6922 vmcs_write(field, pat_saved); 6923 enter_guest(); 6924 } 6925 6926 vmcs_write(ctrl_field, ctrl_saved); 6927 vmcs_write(field, pat_saved); 6928 } 6929 6930 /* 6931 * If the "load IA32_PAT" VM-exit control is 1, the value of the field 6932 * for the IA32_PAT MSR must be one that could be written by WRMSR 6933 * without fault at CPL 0. Specifically, each of the 8 bytes in the 6934 * field must have one of the values 0 (UC), 1 (WC), 4 (WT), 5 (WP), 6935 * 6 (WB), or 7 (UC-). 6936 * 6937 * [Intel SDM] 6938 */ 6939 static void test_load_host_pat(void) 6940 { 6941 /* 6942 * "load IA32_PAT" VM-exit control 6943 */ 6944 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) { 6945 printf("\"Load-IA32-PAT\" exit control not supported\n"); 6946 return; 6947 } 6948 6949 test_pat(HOST_PAT, "HOST_PAT", EXI_CONTROLS, EXI_LOAD_PAT); 6950 } 6951 6952 /* 6953 * Test a value for the given VMCS field. 6954 * 6955 * "field" - VMCS field 6956 * "field_name" - string name of VMCS field 6957 * "bit_start" - starting bit 6958 * "bit_end" - ending bit 6959 * "val" - value that the bit range must or must not contain 6960 * "valid_val" - whether value given in 'val' must be valid or not 6961 * "error" - expected VMCS error when vmentry fails for an invalid value 6962 */ 6963 static void test_vmcs_field(u64 field, const char *field_name, u32 bit_start, 6964 u32 bit_end, u64 val, bool valid_val, u32 error) 6965 { 6966 u64 field_saved = vmcs_read(field); 6967 u32 i; 6968 u64 tmp; 6969 u32 bit_on; 6970 u64 mask = ~0ull; 6971 6972 mask = (mask >> bit_end) << bit_end; 6973 mask = mask | ((1 << bit_start) - 1); 6974 tmp = (field_saved & mask) | (val << bit_start); 6975 6976 vmcs_write(field, tmp); 6977 report_prefix_pushf("%s %lx", field_name, tmp); 6978 if (valid_val) 6979 test_vmx_vmlaunch(0, false); 6980 else 6981 test_vmx_vmlaunch(error, false); 6982 report_prefix_pop(); 6983 6984 for (i = bit_start; i <= bit_end; i = i + 2) { 6985 bit_on = ((1ull < i) & (val << bit_start)) ? 0 : 1; 6986 if (bit_on) 6987 tmp = field_saved | (1ull << i); 6988 else 6989 tmp = field_saved & ~(1ull << i); 6990 vmcs_write(field, tmp); 6991 report_prefix_pushf("%s %lx", field_name, tmp); 6992 if (valid_val) 6993 test_vmx_vmlaunch(error, false); 6994 else 6995 test_vmx_vmlaunch(0, false); 6996 report_prefix_pop(); 6997 } 6998 6999 vmcs_write(field, field_saved); 7000 } 7001 7002 static void test_canonical(u64 field, const char * field_name) 7003 { 7004 u64 addr_saved = vmcs_read(field); 7005 u64 addr = addr_saved; 7006 7007 report_prefix_pushf("%s %lx", field_name, addr); 7008 if (is_canonical(addr)) { 7009 test_vmx_vmlaunch(0, false); 7010 report_prefix_pop(); 7011 7012 addr = make_non_canonical(addr); 7013 vmcs_write(field, addr); 7014 report_prefix_pushf("%s %lx", field_name, addr); 7015 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, 7016 false); 7017 7018 vmcs_write(field, addr_saved); 7019 } else { 7020 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, 7021 false); 7022 } 7023 report_prefix_pop(); 7024 } 7025 7026 /* 7027 * 1. In the selector field for each of CS, SS, DS, ES, FS, GS and TR, the 7028 * RPL (bits 1:0) and the TI flag (bit 2) must be 0. 7029 * 2. The selector fields for CS and TR cannot be 0000H. 7030 * 3. The selector field for SS cannot be 0000H if the "host address-space 7031 * size" VM-exit control is 0. 7032 * 4. On processors that support Intel 64 architecture, the base-address 7033 * fields for FS, GS and TR must contain canonical addresses. 7034 */ 7035 static void test_host_segment_regs(void) 7036 { 7037 u32 exit_ctrl_saved = vmcs_read(EXI_CONTROLS); 7038 u16 selector_saved; 7039 7040 /* 7041 * Test RPL and TI flags 7042 */ 7043 test_vmcs_field(HOST_SEL_CS, "HOST_SEL_CS", 0, 2, 0x0, true, 7044 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7045 test_vmcs_field(HOST_SEL_SS, "HOST_SEL_SS", 0, 2, 0x0, true, 7046 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7047 test_vmcs_field(HOST_SEL_DS, "HOST_SEL_DS", 0, 2, 0x0, true, 7048 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7049 test_vmcs_field(HOST_SEL_ES, "HOST_SEL_ES", 0, 2, 0x0, true, 7050 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7051 test_vmcs_field(HOST_SEL_FS, "HOST_SEL_FS", 0, 2, 0x0, true, 7052 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7053 test_vmcs_field(HOST_SEL_GS, "HOST_SEL_GS", 0, 2, 0x0, true, 7054 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7055 test_vmcs_field(HOST_SEL_TR, "HOST_SEL_TR", 0, 2, 0x0, true, 7056 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7057 7058 /* 7059 * Test that CS and TR fields can not be 0x0000 7060 */ 7061 test_vmcs_field(HOST_SEL_CS, "HOST_SEL_CS", 3, 15, 0x0000, false, 7062 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7063 test_vmcs_field(HOST_SEL_TR, "HOST_SEL_TR", 3, 15, 0x0000, false, 7064 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7065 7066 /* 7067 * SS field can not be 0x0000 if "host address-space size" VM-exit 7068 * control is 0 7069 */ 7070 selector_saved = vmcs_read(HOST_SEL_SS); 7071 vmcs_write(HOST_SEL_SS, 0); 7072 if (exit_ctrl_saved & EXI_HOST_64) { 7073 report_prefix_pushf("HOST_SEL_SS 0"); 7074 test_vmx_vmlaunch(0, false); 7075 report_prefix_pop(); 7076 7077 vmcs_write(EXI_CONTROLS, exit_ctrl_saved & ~EXI_HOST_64); 7078 } 7079 7080 report_prefix_pushf("HOST_SEL_SS 0"); 7081 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, false); 7082 report_prefix_pop(); 7083 7084 vmcs_write(HOST_SEL_SS, selector_saved); 7085 vmcs_write(EXI_CONTROLS, exit_ctrl_saved); 7086 7087 #ifdef __x86_64__ 7088 /* 7089 * Base address for FS, GS and TR must be canonical 7090 */ 7091 test_canonical(HOST_BASE_FS, "HOST_BASE_FS"); 7092 test_canonical(HOST_BASE_GS, "HOST_BASE_GS"); 7093 test_canonical(HOST_BASE_TR, "HOST_BASE_TR"); 7094 #endif 7095 } 7096 7097 /* 7098 * On processors that support Intel 64 architecture, the base-address 7099 * fields for GDTR and IDTR must contain canonical addresses. 7100 */ 7101 static void test_host_desc_tables(void) 7102 { 7103 #ifdef __x86_64__ 7104 test_canonical(HOST_BASE_GDTR, "HOST_BASE_GDTR"); 7105 test_canonical(HOST_BASE_IDTR, "HOST_BASE_IDTR"); 7106 #endif 7107 } 7108 7109 /* 7110 * Check that the virtual CPU checks the VMX Host State Area as 7111 * documented in the Intel SDM. 7112 */ 7113 static void vmx_host_state_area_test(void) 7114 { 7115 /* 7116 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 7117 * fail due to invalid guest state, should we make it that 7118 * far. 7119 */ 7120 vmcs_write(GUEST_RFLAGS, 0); 7121 7122 test_host_ctl_regs(); 7123 7124 test_sysenter_field(HOST_SYSENTER_ESP, "HOST_SYSENTER_ESP"); 7125 test_sysenter_field(HOST_SYSENTER_EIP, "HOST_SYSENTER_EIP"); 7126 7127 test_host_efer(); 7128 test_load_host_pat(); 7129 test_host_segment_regs(); 7130 test_host_desc_tables(); 7131 } 7132 7133 /* 7134 * If the "load IA32_PAT" VM-entry control is 1, the value of the field 7135 * for the IA32_PAT MSR must be one that could be written by WRMSR 7136 * without fault at CPL 0. Specifically, each of the 8 bytes in the 7137 * field must have one of the values 0 (UC), 1 (WC), 4 (WT), 5 (WP), 7138 * 6 (WB), or 7 (UC-). 7139 * 7140 * [Intel SDM] 7141 */ 7142 static void test_load_guest_pat(void) 7143 { 7144 /* 7145 * "load IA32_PAT" VM-entry control 7146 */ 7147 if (!(ctrl_exit_rev.clr & ENT_LOAD_PAT)) { 7148 printf("\"Load-IA32-PAT\" entry control not supported\n"); 7149 return; 7150 } 7151 7152 test_pat(GUEST_PAT, "GUEST_PAT", ENT_CONTROLS, ENT_LOAD_PAT); 7153 } 7154 7155 /* 7156 * Check that the virtual CPU checks the VMX Guest State Area as 7157 * documented in the Intel SDM. 7158 */ 7159 static void vmx_guest_state_area_test(void) 7160 { 7161 test_load_guest_pat(); 7162 } 7163 7164 static bool valid_vmcs_for_vmentry(void) 7165 { 7166 struct vmcs *current_vmcs = NULL; 7167 7168 if (vmcs_save(¤t_vmcs)) 7169 return false; 7170 7171 return current_vmcs && !current_vmcs->hdr.shadow_vmcs; 7172 } 7173 7174 static void try_vmentry_in_movss_shadow(void) 7175 { 7176 u32 vm_inst_err; 7177 u32 flags; 7178 bool early_failure = false; 7179 u32 expected_flags = X86_EFLAGS_FIXED; 7180 bool valid_vmcs = valid_vmcs_for_vmentry(); 7181 7182 expected_flags |= valid_vmcs ? X86_EFLAGS_ZF : X86_EFLAGS_CF; 7183 7184 /* 7185 * Indirectly set VM_INST_ERR to 12 ("VMREAD/VMWRITE from/to 7186 * unsupported VMCS component"). 7187 */ 7188 vmcs_write(~0u, 0); 7189 7190 __asm__ __volatile__ ("mov %[host_rsp], %%edx;" 7191 "vmwrite %%rsp, %%rdx;" 7192 "mov 0f, %%rax;" 7193 "mov %[host_rip], %%edx;" 7194 "vmwrite %%rax, %%rdx;" 7195 "mov $-1, %%ah;" 7196 "sahf;" 7197 "mov %%ss, %%ax;" 7198 "mov %%ax, %%ss;" 7199 "vmlaunch;" 7200 "mov $1, %[early_failure];" 7201 "0: lahf;" 7202 "movzbl %%ah, %[flags]" 7203 : [early_failure] "+r" (early_failure), 7204 [flags] "=&a" (flags) 7205 : [host_rsp] "i" (HOST_RSP), 7206 [host_rip] "i" (HOST_RIP) 7207 : "rdx", "cc", "memory"); 7208 vm_inst_err = vmcs_read(VMX_INST_ERROR); 7209 7210 report("Early VM-entry failure", early_failure); 7211 report("RFLAGS[8:0] is %x (actual %x)", flags == expected_flags, 7212 expected_flags, flags); 7213 if (valid_vmcs) 7214 report("VM-instruction error is %d (actual %d)", 7215 vm_inst_err == VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, 7216 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, vm_inst_err); 7217 } 7218 7219 static void vmentry_movss_shadow_test(void) 7220 { 7221 struct vmcs *orig_vmcs; 7222 7223 TEST_ASSERT(!vmcs_save(&orig_vmcs)); 7224 7225 /* 7226 * Set the launched flag on the current VMCS to verify the correct 7227 * error priority, below. 7228 */ 7229 test_set_guest(v2_null_test_guest); 7230 enter_guest(); 7231 7232 /* 7233 * With bit 1 of the guest's RFLAGS clear, VM-entry should 7234 * fail due to invalid guest state (if we make it that far). 7235 */ 7236 vmcs_write(GUEST_RFLAGS, 0); 7237 7238 /* 7239 * "VM entry with events blocked by MOV SS" takes precedence over 7240 * "VMLAUNCH with non-clear VMCS." 7241 */ 7242 report_prefix_push("valid current-VMCS"); 7243 try_vmentry_in_movss_shadow(); 7244 report_prefix_pop(); 7245 7246 /* 7247 * VMfailInvalid takes precedence over "VM entry with events 7248 * blocked by MOV SS." 7249 */ 7250 TEST_ASSERT(!vmcs_clear(orig_vmcs)); 7251 report_prefix_push("no current-VMCS"); 7252 try_vmentry_in_movss_shadow(); 7253 report_prefix_pop(); 7254 7255 TEST_ASSERT(!make_vmcs_current(orig_vmcs)); 7256 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 7257 } 7258 7259 static void vmx_cr_load_test(void) 7260 { 7261 unsigned long cr3, cr4, orig_cr3, orig_cr4; 7262 7263 orig_cr4 = read_cr4(); 7264 orig_cr3 = read_cr3(); 7265 7266 if (!this_cpu_has(X86_FEATURE_PCID)) { 7267 report_skip("PCID not detected"); 7268 return; 7269 } 7270 if (!this_cpu_has(X86_FEATURE_MCE)) { 7271 report_skip("MCE not detected"); 7272 return; 7273 } 7274 7275 TEST_ASSERT(!(orig_cr3 & X86_CR3_PCID_MASK)); 7276 7277 /* Enable PCID for L1. */ 7278 cr4 = orig_cr4 | X86_CR4_PCIDE; 7279 cr3 = orig_cr3 | 0x1; 7280 TEST_ASSERT(!write_cr4_checking(cr4)); 7281 write_cr3(cr3); 7282 7283 test_set_guest(v2_null_test_guest); 7284 vmcs_write(HOST_CR4, cr4); 7285 vmcs_write(HOST_CR3, cr3); 7286 enter_guest(); 7287 7288 /* 7289 * No exception is expected. 7290 * 7291 * NB. KVM loads the last guest write to CR4 into CR4 read 7292 * shadow. In order to trigger an exit to KVM, we can toggle a 7293 * bit that is owned by KVM. We use CR4.MCE, which shall 7294 * have no side effect because normally no guest MCE (e.g., as the 7295 * result of bad memory) would happen during this test. 7296 */ 7297 TEST_ASSERT(!write_cr4_checking(cr4 ^ X86_CR4_MCE)); 7298 7299 /* Cleanup L1 state. */ 7300 write_cr3(orig_cr3); 7301 TEST_ASSERT(!write_cr4_checking(orig_cr4)); 7302 } 7303 7304 static void vmx_nm_test_guest(void) 7305 { 7306 write_cr0(read_cr0() | X86_CR0_TS); 7307 asm volatile("fnop"); 7308 } 7309 7310 static void check_nm_exit(const char *test) 7311 { 7312 u32 reason = vmcs_read(EXI_REASON); 7313 u32 intr_info = vmcs_read(EXI_INTR_INFO); 7314 const u32 expected = INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 7315 NM_VECTOR; 7316 7317 report("%s", reason == VMX_EXC_NMI && intr_info == expected, test); 7318 } 7319 7320 /* 7321 * This test checks that: 7322 * 7323 * (a) If L2 launches with CR0.TS clear, but later sets CR0.TS, then 7324 * a subsequent #NM VM-exit is reflected to L1. 7325 * 7326 * (b) If L2 launches with CR0.TS clear and CR0.EM set, then a 7327 * subsequent #NM VM-exit is reflected to L1. 7328 */ 7329 static void vmx_nm_test(void) 7330 { 7331 unsigned long cr0 = read_cr0(); 7332 7333 test_set_guest(vmx_nm_test_guest); 7334 7335 /* 7336 * L1 wants to intercept #NM exceptions encountered in L2. 7337 */ 7338 vmcs_write(EXC_BITMAP, 1 << NM_VECTOR); 7339 7340 /* 7341 * Launch L2 with CR0.TS clear, but don't claim host ownership of 7342 * any CR0 bits. L2 will set CR0.TS and then try to execute fnop, 7343 * which will raise #NM. L0 should reflect the #NM VM-exit to L1. 7344 */ 7345 vmcs_write(CR0_MASK, 0); 7346 vmcs_write(GUEST_CR0, cr0 & ~X86_CR0_TS); 7347 enter_guest(); 7348 check_nm_exit("fnop with CR0.TS set in L2 triggers #NM VM-exit to L1"); 7349 7350 /* 7351 * Re-enter L2 at the fnop instruction, with CR0.TS clear but 7352 * CR0.EM set. The fnop will still raise #NM, and L0 should 7353 * reflect the #NM VM-exit to L1. 7354 */ 7355 vmcs_write(GUEST_CR0, (cr0 & ~X86_CR0_TS) | X86_CR0_EM); 7356 enter_guest(); 7357 check_nm_exit("fnop with CR0.EM set in L2 triggers #NM VM-exit to L1"); 7358 7359 /* 7360 * Re-enter L2 at the fnop instruction, with both CR0.TS and 7361 * CR0.EM clear. There will be no #NM, and the L2 guest should 7362 * exit normally. 7363 */ 7364 vmcs_write(GUEST_CR0, cr0 & ~(X86_CR0_TS | X86_CR0_EM)); 7365 enter_guest(); 7366 } 7367 7368 bool vmx_pending_event_ipi_fired; 7369 static void vmx_pending_event_ipi_isr(isr_regs_t *regs) 7370 { 7371 vmx_pending_event_ipi_fired = true; 7372 eoi(); 7373 } 7374 7375 bool vmx_pending_event_guest_run; 7376 static void vmx_pending_event_guest(void) 7377 { 7378 vmcall(); 7379 vmx_pending_event_guest_run = true; 7380 } 7381 7382 static void vmx_pending_event_test_core(bool guest_hlt) 7383 { 7384 int ipi_vector = 0xf1; 7385 7386 vmx_pending_event_ipi_fired = false; 7387 handle_irq(ipi_vector, vmx_pending_event_ipi_isr); 7388 7389 vmx_pending_event_guest_run = false; 7390 test_set_guest(vmx_pending_event_guest); 7391 7392 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 7393 7394 enter_guest(); 7395 skip_exit_vmcall(); 7396 7397 if (guest_hlt) 7398 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 7399 7400 irq_disable(); 7401 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | 7402 APIC_DM_FIXED | ipi_vector, 7403 0); 7404 7405 enter_guest(); 7406 7407 assert_exit_reason(VMX_EXTINT); 7408 report("Guest did not run before host received IPI", 7409 !vmx_pending_event_guest_run); 7410 7411 irq_enable(); 7412 asm volatile ("nop"); 7413 irq_disable(); 7414 report("Got pending interrupt after IRQ enabled", 7415 vmx_pending_event_ipi_fired); 7416 7417 if (guest_hlt) 7418 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 7419 7420 enter_guest(); 7421 report("Guest finished running when no interrupt", 7422 vmx_pending_event_guest_run); 7423 } 7424 7425 static void vmx_pending_event_test(void) 7426 { 7427 vmx_pending_event_test_core(false); 7428 } 7429 7430 static void vmx_pending_event_hlt_test(void) 7431 { 7432 vmx_pending_event_test_core(true); 7433 } 7434 7435 static int vmx_window_test_db_count; 7436 7437 static void vmx_window_test_db_handler(struct ex_regs *regs) 7438 { 7439 vmx_window_test_db_count++; 7440 } 7441 7442 static void vmx_nmi_window_test_guest(void) 7443 { 7444 handle_exception(DB_VECTOR, vmx_window_test_db_handler); 7445 7446 asm volatile("vmcall\n\t" 7447 "nop\n\t"); 7448 7449 handle_exception(DB_VECTOR, NULL); 7450 } 7451 7452 static void verify_nmi_window_exit(u64 rip) 7453 { 7454 u32 exit_reason = vmcs_read(EXI_REASON); 7455 7456 report("Exit reason (%d) is 'NMI window'", 7457 exit_reason == VMX_NMI_WINDOW, exit_reason); 7458 report("RIP (%#lx) is %#lx", vmcs_read(GUEST_RIP) == rip, 7459 vmcs_read(GUEST_RIP), rip); 7460 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 7461 } 7462 7463 static void vmx_nmi_window_test(void) 7464 { 7465 u64 nop_addr; 7466 void *db_fault_addr = get_idt_addr(&boot_idt[DB_VECTOR]); 7467 7468 if (!(ctrl_pin_rev.clr & PIN_VIRT_NMI)) { 7469 report_skip("CPU does not support the \"Virtual NMIs\" VM-execution control."); 7470 return; 7471 } 7472 7473 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 7474 report_skip("CPU does not support the \"NMI-window exiting\" VM-execution control."); 7475 return; 7476 } 7477 7478 vmx_window_test_db_count = 0; 7479 7480 report_prefix_push("NMI-window"); 7481 test_set_guest(vmx_nmi_window_test_guest); 7482 vmcs_set_bits(PIN_CONTROLS, PIN_VIRT_NMI); 7483 enter_guest(); 7484 skip_exit_vmcall(); 7485 nop_addr = vmcs_read(GUEST_RIP); 7486 7487 /* 7488 * Ask for "NMI-window exiting," and expect an immediate VM-exit. 7489 * RIP will not advance. 7490 */ 7491 report_prefix_push("active, no blocking"); 7492 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 7493 enter_guest(); 7494 verify_nmi_window_exit(nop_addr); 7495 report_prefix_pop(); 7496 7497 /* 7498 * Ask for "NMI-window exiting" in a MOV-SS shadow, and expect 7499 * a VM-exit on the next instruction after the nop. (The nop 7500 * is one byte.) 7501 */ 7502 report_prefix_push("active, blocking by MOV-SS"); 7503 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 7504 enter_guest(); 7505 verify_nmi_window_exit(nop_addr + 1); 7506 report_prefix_pop(); 7507 7508 /* 7509 * Ask for "NMI-window exiting" (with event injection), and 7510 * expect a VM-exit after the event is injected. (RIP should 7511 * be at the address specified in the IDT entry for #DB.) 7512 */ 7513 report_prefix_push("active, no blocking, injecting #DB"); 7514 vmcs_write(ENT_INTR_INFO, 7515 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 7516 enter_guest(); 7517 verify_nmi_window_exit((u64)db_fault_addr); 7518 report_prefix_pop(); 7519 7520 /* 7521 * Ask for "NMI-window exiting" with NMI blocking, and expect 7522 * a VM-exit after the next IRET (i.e. after the #DB handler 7523 * returns). So, RIP should be back at one byte past the nop. 7524 */ 7525 report_prefix_push("active, blocking by NMI"); 7526 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_NMI); 7527 enter_guest(); 7528 verify_nmi_window_exit(nop_addr + 1); 7529 report("#DB handler executed once (actual %d times)", 7530 vmx_window_test_db_count == 1, 7531 vmx_window_test_db_count); 7532 report_prefix_pop(); 7533 7534 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 7535 report_skip("CPU does not support activity state HLT."); 7536 } else { 7537 /* 7538 * Ask for "NMI-window exiting" when entering activity 7539 * state HLT, and expect an immediate VM-exit. RIP is 7540 * still one byte past the nop. 7541 */ 7542 report_prefix_push("halted, no blocking"); 7543 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 7544 enter_guest(); 7545 verify_nmi_window_exit(nop_addr + 1); 7546 report_prefix_pop(); 7547 7548 /* 7549 * Ask for "NMI-window exiting" when entering activity 7550 * state HLT (with event injection), and expect a 7551 * VM-exit after the event is injected. (RIP should be 7552 * at the address specified in the IDT entry for #DB.) 7553 */ 7554 report_prefix_push("halted, no blocking, injecting #DB"); 7555 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 7556 vmcs_write(ENT_INTR_INFO, 7557 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 7558 DB_VECTOR); 7559 enter_guest(); 7560 verify_nmi_window_exit((u64)db_fault_addr); 7561 report_prefix_pop(); 7562 } 7563 7564 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 7565 enter_guest(); 7566 report_prefix_pop(); 7567 } 7568 7569 static void vmx_intr_window_test_guest(void) 7570 { 7571 handle_exception(DB_VECTOR, vmx_window_test_db_handler); 7572 7573 /* 7574 * The two consecutive STIs are to ensure that only the first 7575 * one has a shadow. Note that NOP and STI are one byte 7576 * instructions. 7577 */ 7578 asm volatile("vmcall\n\t" 7579 "nop\n\t" 7580 "sti\n\t" 7581 "sti\n\t"); 7582 7583 handle_exception(DB_VECTOR, NULL); 7584 } 7585 7586 static void verify_intr_window_exit(u64 rip) 7587 { 7588 u32 exit_reason = vmcs_read(EXI_REASON); 7589 7590 report("Exit reason (%d) is 'interrupt window'", 7591 exit_reason == VMX_INTR_WINDOW, exit_reason); 7592 report("RIP (%#lx) is %#lx", vmcs_read(GUEST_RIP) == rip, 7593 vmcs_read(GUEST_RIP), rip); 7594 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 7595 } 7596 7597 static void vmx_intr_window_test(void) 7598 { 7599 u64 vmcall_addr; 7600 u64 nop_addr; 7601 unsigned int orig_db_gate_type; 7602 void *db_fault_addr = get_idt_addr(&boot_idt[DB_VECTOR]); 7603 7604 if (!(ctrl_cpu_rev[0].clr & CPU_INTR_WINDOW)) { 7605 report_skip("CPU does not support the \"interrupt-window exiting\" VM-execution control."); 7606 return; 7607 } 7608 7609 /* 7610 * Change the IDT entry for #DB from interrupt gate to trap gate, 7611 * so that it won't clear RFLAGS.IF. We don't want interrupts to 7612 * be disabled after vectoring a #DB. 7613 */ 7614 orig_db_gate_type = boot_idt[DB_VECTOR].type; 7615 boot_idt[DB_VECTOR].type = 15; 7616 7617 report_prefix_push("interrupt-window"); 7618 test_set_guest(vmx_intr_window_test_guest); 7619 enter_guest(); 7620 assert_exit_reason(VMX_VMCALL); 7621 vmcall_addr = vmcs_read(GUEST_RIP); 7622 7623 /* 7624 * Ask for "interrupt-window exiting" with RFLAGS.IF set and 7625 * no blocking; expect an immediate VM-exit. Note that we have 7626 * not advanced past the vmcall instruction yet, so RIP should 7627 * point to the vmcall instruction. 7628 */ 7629 report_prefix_push("active, no blocking, RFLAGS.IF=1"); 7630 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 7631 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_IF); 7632 enter_guest(); 7633 verify_intr_window_exit(vmcall_addr); 7634 report_prefix_pop(); 7635 7636 /* 7637 * Ask for "interrupt-window exiting" (with event injection) 7638 * with RFLAGS.IF set and no blocking; expect a VM-exit after 7639 * the event is injected. That is, RIP should should be at the 7640 * address specified in the IDT entry for #DB. 7641 */ 7642 report_prefix_push("active, no blocking, RFLAGS.IF=1, injecting #DB"); 7643 vmcs_write(ENT_INTR_INFO, 7644 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 7645 vmcall_addr = vmcs_read(GUEST_RIP); 7646 enter_guest(); 7647 verify_intr_window_exit((u64)db_fault_addr); 7648 report_prefix_pop(); 7649 7650 /* 7651 * Let the L2 guest run through the IRET, back to the VMCALL. 7652 * We have to clear the "interrupt-window exiting" 7653 * VM-execution control, or it would just keep causing 7654 * VM-exits. Then, advance past the VMCALL and set the 7655 * "interrupt-window exiting" VM-execution control again. 7656 */ 7657 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 7658 enter_guest(); 7659 skip_exit_vmcall(); 7660 nop_addr = vmcs_read(GUEST_RIP); 7661 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 7662 7663 /* 7664 * Ask for "interrupt-window exiting" in a MOV-SS shadow with 7665 * RFLAGS.IF set, and expect a VM-exit on the next 7666 * instruction. (NOP is one byte.) 7667 */ 7668 report_prefix_push("active, blocking by MOV-SS, RFLAGS.IF=1"); 7669 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 7670 enter_guest(); 7671 verify_intr_window_exit(nop_addr + 1); 7672 report_prefix_pop(); 7673 7674 /* 7675 * Back up to the NOP and ask for "interrupt-window exiting" 7676 * in an STI shadow with RFLAGS.IF set, and expect a VM-exit 7677 * on the next instruction. (NOP is one byte.) 7678 */ 7679 report_prefix_push("active, blocking by STI, RFLAGS.IF=1"); 7680 vmcs_write(GUEST_RIP, nop_addr); 7681 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_STI); 7682 enter_guest(); 7683 verify_intr_window_exit(nop_addr + 1); 7684 report_prefix_pop(); 7685 7686 /* 7687 * Ask for "interrupt-window exiting" with RFLAGS.IF clear, 7688 * and expect a VM-exit on the instruction following the STI 7689 * shadow. Only the first STI (which is one byte past the NOP) 7690 * should have a shadow. The second STI (which is two bytes 7691 * past the NOP) has no shadow. Therefore, the interrupt 7692 * window opens at three bytes past the NOP. 7693 */ 7694 report_prefix_push("active, RFLAGS.IF = 0"); 7695 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 7696 enter_guest(); 7697 verify_intr_window_exit(nop_addr + 3); 7698 report_prefix_pop(); 7699 7700 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 7701 report_skip("CPU does not support activity state HLT."); 7702 } else { 7703 /* 7704 * Ask for "interrupt-window exiting" when entering 7705 * activity state HLT, and expect an immediate 7706 * VM-exit. RIP is still three bytes past the nop. 7707 */ 7708 report_prefix_push("halted, no blocking"); 7709 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 7710 enter_guest(); 7711 verify_intr_window_exit(nop_addr + 3); 7712 report_prefix_pop(); 7713 7714 /* 7715 * Ask for "interrupt-window exiting" when entering 7716 * activity state HLT (with event injection), and 7717 * expect a VM-exit after the event is injected. That 7718 * is, RIP should should be at the address specified 7719 * in the IDT entry for #DB. 7720 */ 7721 report_prefix_push("halted, no blocking, injecting #DB"); 7722 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 7723 vmcs_write(ENT_INTR_INFO, 7724 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 7725 DB_VECTOR); 7726 enter_guest(); 7727 verify_intr_window_exit((u64)db_fault_addr); 7728 report_prefix_pop(); 7729 } 7730 7731 boot_idt[DB_VECTOR].type = orig_db_gate_type; 7732 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 7733 enter_guest(); 7734 report_prefix_pop(); 7735 } 7736 7737 #define GUEST_TSC_OFFSET (1u << 30) 7738 7739 static u64 guest_tsc; 7740 7741 static void vmx_store_tsc_test_guest(void) 7742 { 7743 guest_tsc = rdtsc(); 7744 } 7745 7746 /* 7747 * This test ensures that when IA32_TSC is in the VM-exit MSR-store 7748 * list, the value saved is not subject to the TSC offset that is 7749 * applied to RDTSC/RDTSCP/RDMSR(IA32_TSC) in guest execution. 7750 */ 7751 static void vmx_store_tsc_test(void) 7752 { 7753 struct vmx_msr_entry msr_entry = { .index = MSR_IA32_TSC }; 7754 u64 low, high; 7755 7756 if (!(ctrl_cpu_rev[0].clr & CPU_USE_TSC_OFFSET)) { 7757 report_skip("'Use TSC offsetting' not supported"); 7758 return; 7759 } 7760 7761 test_set_guest(vmx_store_tsc_test_guest); 7762 7763 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_USE_TSC_OFFSET); 7764 vmcs_write(EXI_MSR_ST_CNT, 1); 7765 vmcs_write(EXIT_MSR_ST_ADDR, virt_to_phys(&msr_entry)); 7766 vmcs_write(TSC_OFFSET, GUEST_TSC_OFFSET); 7767 7768 low = rdtsc(); 7769 enter_guest(); 7770 high = rdtsc(); 7771 7772 report("RDTSC value in the guest (%lu) is in range [%lu, %lu]", 7773 low + GUEST_TSC_OFFSET <= guest_tsc && 7774 guest_tsc <= high + GUEST_TSC_OFFSET, 7775 guest_tsc, low + GUEST_TSC_OFFSET, high + GUEST_TSC_OFFSET); 7776 report("IA32_TSC value saved in the VM-exit MSR-store list (%lu) is in range [%lu, %lu]", 7777 low <= msr_entry.value && msr_entry.value <= high, 7778 msr_entry.value, low, high); 7779 } 7780 7781 static void vmx_db_test_guest(void) 7782 { 7783 /* 7784 * For a hardware generated single-step #DB. 7785 */ 7786 asm volatile("vmcall;" 7787 "nop;" 7788 ".Lpost_nop:"); 7789 /* 7790 * ...in a MOVSS shadow, with pending debug exceptions. 7791 */ 7792 asm volatile("vmcall;" 7793 "nop;" 7794 ".Lpost_movss_nop:"); 7795 /* 7796 * For an L0 synthesized single-step #DB. (L0 intercepts WBINVD and 7797 * emulates it in software.) 7798 */ 7799 asm volatile("vmcall;" 7800 "wbinvd;" 7801 ".Lpost_wbinvd:"); 7802 /* 7803 * ...in a MOVSS shadow, with pending debug exceptions. 7804 */ 7805 asm volatile("vmcall;" 7806 "wbinvd;" 7807 ".Lpost_movss_wbinvd:"); 7808 /* 7809 * For a hardware generated single-step #DB in a transactional region. 7810 */ 7811 asm volatile("vmcall;" 7812 ".Lxbegin: xbegin .Lskip_rtm;" 7813 "xend;" 7814 ".Lskip_rtm:"); 7815 } 7816 7817 /* 7818 * Clear the pending debug exceptions and RFLAGS.TF and re-enter 7819 * L2. No #DB is delivered and L2 continues to the next point of 7820 * interest. 7821 */ 7822 static void dismiss_db(void) 7823 { 7824 vmcs_write(GUEST_PENDING_DEBUG, 0); 7825 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 7826 enter_guest(); 7827 } 7828 7829 /* 7830 * Check a variety of VMCS fields relevant to an intercepted #DB exception. 7831 * Then throw away the #DB exception and resume L2. 7832 */ 7833 static void check_db_exit(bool xfail_qual, bool xfail_dr6, bool xfail_pdbg, 7834 void *expected_rip, u64 expected_exit_qual, 7835 u64 expected_dr6) 7836 { 7837 u32 reason = vmcs_read(EXI_REASON); 7838 u32 intr_info = vmcs_read(EXI_INTR_INFO); 7839 u64 exit_qual = vmcs_read(EXI_QUALIFICATION); 7840 u64 guest_rip = vmcs_read(GUEST_RIP); 7841 u64 guest_pending_dbg = vmcs_read(GUEST_PENDING_DEBUG); 7842 u64 dr6 = read_dr6(); 7843 const u32 expected_intr_info = INTR_INFO_VALID_MASK | 7844 INTR_TYPE_HARD_EXCEPTION | DB_VECTOR; 7845 7846 report("Expected #DB VM-exit", 7847 reason == VMX_EXC_NMI && intr_info == expected_intr_info); 7848 report("Expected RIP %p (actual %lx)", (u64)expected_rip == guest_rip, 7849 expected_rip, guest_rip); 7850 report_xfail("Expected pending debug exceptions 0 (actual %lx)", 7851 xfail_pdbg, 0 == guest_pending_dbg, guest_pending_dbg); 7852 report_xfail("Expected exit qualification %lx (actual %lx)", xfail_qual, 7853 expected_exit_qual == exit_qual, 7854 expected_exit_qual, exit_qual); 7855 report_xfail("Expected DR6 %lx (actual %lx)", xfail_dr6, 7856 expected_dr6 == dr6, expected_dr6, dr6); 7857 dismiss_db(); 7858 } 7859 7860 /* 7861 * Assuming the guest has just exited on a VMCALL instruction, skip 7862 * over the vmcall, and set the guest's RFLAGS.TF in the VMCS. If 7863 * pending debug exceptions are non-zero, set the VMCS up as if the 7864 * previous instruction was a MOVSS that generated the indicated 7865 * pending debug exceptions. Then enter L2. 7866 */ 7867 static void single_step_guest(const char *test_name, u64 starting_dr6, 7868 u64 pending_debug_exceptions) 7869 { 7870 printf("\n%s\n", test_name); 7871 skip_exit_vmcall(); 7872 write_dr6(starting_dr6); 7873 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_TF); 7874 if (pending_debug_exceptions) { 7875 vmcs_write(GUEST_PENDING_DEBUG, pending_debug_exceptions); 7876 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 7877 } 7878 enter_guest(); 7879 } 7880 7881 /* 7882 * When L1 intercepts #DB, verify that a single-step trap clears 7883 * pending debug exceptions, populates the exit qualification field 7884 * properly, and that DR6 is not prematurely clobbered. In a 7885 * (simulated) MOVSS shadow, make sure that the pending debug 7886 * exception bits are properly accumulated into the exit qualification 7887 * field. 7888 */ 7889 static void vmx_db_test(void) 7890 { 7891 /* 7892 * We are going to set a few arbitrary bits in DR6 to verify that 7893 * (a) DR6 is not modified by an intercepted #DB, and 7894 * (b) stale bits in DR6 (DR6.BD, in particular) don't leak into 7895 * the exit qualification field for a subsequent #DB exception. 7896 */ 7897 const u64 starting_dr6 = DR6_RESERVED | BIT(13) | DR_TRAP3 | DR_TRAP1; 7898 extern char post_nop asm(".Lpost_nop"); 7899 extern char post_movss_nop asm(".Lpost_movss_nop"); 7900 extern char post_wbinvd asm(".Lpost_wbinvd"); 7901 extern char post_movss_wbinvd asm(".Lpost_movss_wbinvd"); 7902 extern char xbegin asm(".Lxbegin"); 7903 extern char skip_rtm asm(".Lskip_rtm"); 7904 7905 /* 7906 * L1 wants to intercept #DB exceptions encountered in L2. 7907 */ 7908 vmcs_write(EXC_BITMAP, BIT(DB_VECTOR)); 7909 7910 /* 7911 * Start L2 and run it up to the first point of interest. 7912 */ 7913 test_set_guest(vmx_db_test_guest); 7914 enter_guest(); 7915 7916 /* 7917 * Hardware-delivered #DB trap for single-step sets the 7918 * standard that L0 has to follow for emulated instructions. 7919 */ 7920 single_step_guest("Hardware delivered single-step", starting_dr6, 0); 7921 check_db_exit(false, false, false, &post_nop, DR_STEP, starting_dr6); 7922 7923 /* 7924 * Hardware-delivered #DB trap for single-step in MOVSS shadow 7925 * also sets the standard that L0 has to follow for emulated 7926 * instructions. Here, we establish the VMCS pending debug 7927 * exceptions to indicate that the simulated MOVSS triggered a 7928 * data breakpoint as well as the single-step trap. 7929 */ 7930 single_step_guest("Hardware delivered single-step in MOVSS shadow", 7931 starting_dr6, BIT(12) | DR_STEP | DR_TRAP0 ); 7932 check_db_exit(false, false, false, &post_movss_nop, DR_STEP | DR_TRAP0, 7933 starting_dr6); 7934 7935 /* 7936 * L0 synthesized #DB trap for single-step is buggy, because 7937 * kvm (a) clobbers DR6 too early, and (b) tries its best to 7938 * reconstitute the exit qualification from the prematurely 7939 * modified DR6, but fails miserably. 7940 */ 7941 single_step_guest("Software synthesized single-step", starting_dr6, 0); 7942 check_db_exit(true, true, false, &post_wbinvd, DR_STEP, starting_dr6); 7943 7944 /* 7945 * L0 synthesized #DB trap for single-step in MOVSS shadow is 7946 * even worse, because L0 also leaves the pending debug 7947 * exceptions in the VMCS instead of accumulating them into 7948 * the exit qualification field for the #DB exception. 7949 */ 7950 single_step_guest("Software synthesized single-step in MOVSS shadow", 7951 starting_dr6, BIT(12) | DR_STEP | DR_TRAP0); 7952 check_db_exit(true, true, true, &post_movss_wbinvd, DR_STEP | DR_TRAP0, 7953 starting_dr6); 7954 7955 /* 7956 * Optional RTM test for hardware that supports RTM, to 7957 * demonstrate that the current volume 3 of the SDM 7958 * (325384-067US), table 27-1 is incorrect. Bit 16 of the exit 7959 * qualification for debug exceptions is not reserved. It is 7960 * set to 1 if a debug exception (#DB) or a breakpoint 7961 * exception (#BP) occurs inside an RTM region while advanced 7962 * debugging of RTM transactional regions is enabled. 7963 */ 7964 if (this_cpu_has(X86_FEATURE_RTM)) { 7965 vmcs_write(ENT_CONTROLS, 7966 vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 7967 /* 7968 * Set DR7.RTM[bit 11] and IA32_DEBUGCTL.RTM[bit 15] 7969 * in the guest to enable advanced debugging of RTM 7970 * transactional regions. 7971 */ 7972 vmcs_write(GUEST_DR7, BIT(11)); 7973 vmcs_write(GUEST_DEBUGCTL, BIT(15)); 7974 single_step_guest("Hardware delivered single-step in " 7975 "transactional region", starting_dr6, 0); 7976 check_db_exit(false, false, false, &xbegin, BIT(16), 7977 starting_dr6); 7978 } else { 7979 vmcs_write(GUEST_RIP, (u64)&skip_rtm); 7980 enter_guest(); 7981 } 7982 } 7983 7984 static void enable_vid(void) 7985 { 7986 void *virtual_apic_page; 7987 7988 assert(cpu_has_apicv()); 7989 7990 disable_intercept_for_x2apic_msrs(); 7991 7992 virtual_apic_page = alloc_page(); 7993 vmcs_write(APIC_VIRT_ADDR, (u64)virtual_apic_page); 7994 7995 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 7996 7997 vmcs_write(EOI_EXIT_BITMAP0, 0x0); 7998 vmcs_write(EOI_EXIT_BITMAP1, 0x0); 7999 vmcs_write(EOI_EXIT_BITMAP2, 0x0); 8000 vmcs_write(EOI_EXIT_BITMAP3, 0x0); 8001 8002 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY | CPU_TPR_SHADOW); 8003 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_VINTD | CPU_VIRT_X2APIC); 8004 } 8005 8006 static void trigger_ioapic_scan_thread(void *data) 8007 { 8008 /* Wait until other CPU entered L2 */ 8009 while (vmx_get_test_stage() != 1) 8010 ; 8011 8012 /* Trigger ioapic scan */ 8013 ioapic_set_redir(0xf, 0x79, TRIGGER_LEVEL); 8014 vmx_set_test_stage(2); 8015 } 8016 8017 static void irq_79_handler_guest(isr_regs_t *regs) 8018 { 8019 eoi(); 8020 8021 /* L1 expects vmexit on VMX_VMCALL and not VMX_EOI_INDUCED */ 8022 vmcall(); 8023 } 8024 8025 /* 8026 * Constant for num of busy-loop iterations after which 8027 * a timer interrupt should have happened in host 8028 */ 8029 #define TIMER_INTERRUPT_DELAY 100000000 8030 8031 static void vmx_eoi_bitmap_ioapic_scan_test_guest(void) 8032 { 8033 handle_irq(0x79, irq_79_handler_guest); 8034 irq_enable(); 8035 8036 /* Signal to L1 CPU to trigger ioapic scan */ 8037 vmx_set_test_stage(1); 8038 /* Wait until L1 CPU to trigger ioapic scan */ 8039 while (vmx_get_test_stage() != 2) 8040 ; 8041 8042 /* 8043 * Wait for L0 timer interrupt to be raised while we run in L2 8044 * such that L0 will process the IOAPIC scan request before 8045 * resuming L2 8046 */ 8047 delay(TIMER_INTERRUPT_DELAY); 8048 8049 asm volatile ("int $0x79"); 8050 } 8051 8052 static void vmx_eoi_bitmap_ioapic_scan_test(void) 8053 { 8054 if (!cpu_has_apicv() || (cpu_count() < 2)) { 8055 report_skip(__func__); 8056 return; 8057 } 8058 8059 enable_vid(); 8060 8061 on_cpu_async(1, trigger_ioapic_scan_thread, NULL); 8062 test_set_guest(vmx_eoi_bitmap_ioapic_scan_test_guest); 8063 8064 /* 8065 * Launch L2. 8066 * We expect the exit reason to be VMX_VMCALL (and not EOI INDUCED). 8067 * In case the reason isn't VMX_VMCALL, the asserion inside 8068 * skip_exit_vmcall() will fail. 8069 */ 8070 enter_guest(); 8071 skip_exit_vmcall(); 8072 8073 /* Let L2 finish */ 8074 enter_guest(); 8075 report(__func__, 1); 8076 } 8077 8078 #define HLT_WITH_RVI_VECTOR (0xf1) 8079 8080 bool vmx_hlt_with_rvi_guest_isr_fired; 8081 static void vmx_hlt_with_rvi_guest_isr(isr_regs_t *regs) 8082 { 8083 vmx_hlt_with_rvi_guest_isr_fired = true; 8084 eoi(); 8085 } 8086 8087 static void vmx_hlt_with_rvi_guest(void) 8088 { 8089 handle_irq(HLT_WITH_RVI_VECTOR, vmx_hlt_with_rvi_guest_isr); 8090 8091 irq_enable(); 8092 asm volatile ("nop"); 8093 8094 vmcall(); 8095 } 8096 8097 static void vmx_hlt_with_rvi_test(void) 8098 { 8099 if (!cpu_has_apicv()) { 8100 report_skip(__func__); 8101 return; 8102 } 8103 8104 enable_vid(); 8105 8106 vmx_hlt_with_rvi_guest_isr_fired = false; 8107 test_set_guest(vmx_hlt_with_rvi_guest); 8108 8109 enter_guest(); 8110 skip_exit_vmcall(); 8111 8112 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8113 vmcs_write(GUEST_INT_STATUS, HLT_WITH_RVI_VECTOR); 8114 enter_guest(); 8115 8116 report("Interrupt raised in guest", vmx_hlt_with_rvi_guest_isr_fired); 8117 } 8118 8119 static void set_irq_line_thread(void *data) 8120 { 8121 /* Wait until other CPU entered L2 */ 8122 while (vmx_get_test_stage() != 1) 8123 ; 8124 8125 /* Set irq-line 0xf to raise vector 0x78 for vCPU 0 */ 8126 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 8127 vmx_set_test_stage(2); 8128 } 8129 8130 static bool irq_78_handler_vmcall_before_eoi; 8131 static void irq_78_handler_guest(isr_regs_t *regs) 8132 { 8133 set_irq_line(0xf, 0); 8134 if (irq_78_handler_vmcall_before_eoi) 8135 vmcall(); 8136 eoi(); 8137 vmcall(); 8138 } 8139 8140 static void vmx_apic_passthrough_guest(void) 8141 { 8142 handle_irq(0x78, irq_78_handler_guest); 8143 irq_enable(); 8144 8145 /* If requested, wait for other CPU to trigger ioapic scan */ 8146 if (vmx_get_test_stage() < 1) { 8147 vmx_set_test_stage(1); 8148 while (vmx_get_test_stage() != 2) 8149 ; 8150 } 8151 8152 set_irq_line(0xf, 1); 8153 } 8154 8155 static void vmx_apic_passthrough(bool set_irq_line_from_thread) 8156 { 8157 if (set_irq_line_from_thread && (cpu_count() < 2)) { 8158 report_skip(__func__); 8159 return; 8160 } 8161 8162 u64 cpu_ctrl_0 = CPU_SECONDARY; 8163 u64 cpu_ctrl_1 = 0; 8164 8165 disable_intercept_for_x2apic_msrs(); 8166 8167 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 8168 8169 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 8170 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 8171 8172 if (set_irq_line_from_thread) { 8173 irq_78_handler_vmcall_before_eoi = false; 8174 on_cpu_async(1, set_irq_line_thread, NULL); 8175 } else { 8176 irq_78_handler_vmcall_before_eoi = true; 8177 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 8178 vmx_set_test_stage(2); 8179 } 8180 test_set_guest(vmx_apic_passthrough_guest); 8181 8182 if (irq_78_handler_vmcall_before_eoi) { 8183 /* Before EOI remote_irr should still be set */ 8184 enter_guest(); 8185 skip_exit_vmcall(); 8186 TEST_ASSERT_EQ_MSG(1, (int)ioapic_read_redir(0xf).remote_irr, 8187 "IOAPIC pass-through: remote_irr=1 before EOI"); 8188 } 8189 8190 /* After EOI remote_irr should be cleared */ 8191 enter_guest(); 8192 skip_exit_vmcall(); 8193 TEST_ASSERT_EQ_MSG(0, (int)ioapic_read_redir(0xf).remote_irr, 8194 "IOAPIC pass-through: remote_irr=0 after EOI"); 8195 8196 /* Let L2 finish */ 8197 enter_guest(); 8198 report(__func__, 1); 8199 } 8200 8201 static void vmx_apic_passthrough_test(void) 8202 { 8203 vmx_apic_passthrough(false); 8204 } 8205 8206 static void vmx_apic_passthrough_thread_test(void) 8207 { 8208 vmx_apic_passthrough(true); 8209 } 8210 8211 enum vmcs_access { 8212 ACCESS_VMREAD, 8213 ACCESS_VMWRITE, 8214 ACCESS_NONE, 8215 }; 8216 8217 struct vmcs_shadow_test_common { 8218 enum vmcs_access op; 8219 enum Reason reason; 8220 u64 field; 8221 u64 value; 8222 u64 flags; 8223 u64 time; 8224 } l1_l2_common; 8225 8226 static inline u64 vmread_flags(u64 field, u64 *val) 8227 { 8228 u64 flags; 8229 8230 asm volatile ("vmread %2, %1; pushf; pop %0" 8231 : "=r" (flags), "=rm" (*val) : "r" (field) : "cc"); 8232 return flags & X86_EFLAGS_ALU; 8233 } 8234 8235 static inline u64 vmwrite_flags(u64 field, u64 val) 8236 { 8237 u64 flags; 8238 8239 asm volatile ("vmwrite %1, %2; pushf; pop %0" 8240 : "=r"(flags) : "rm" (val), "r" (field) : "cc"); 8241 return flags & X86_EFLAGS_ALU; 8242 } 8243 8244 static void vmx_vmcs_shadow_test_guest(void) 8245 { 8246 struct vmcs_shadow_test_common *c = &l1_l2_common; 8247 u64 start; 8248 8249 while (c->op != ACCESS_NONE) { 8250 start = rdtsc(); 8251 switch (c->op) { 8252 default: 8253 c->flags = -1ull; 8254 break; 8255 case ACCESS_VMREAD: 8256 c->flags = vmread_flags(c->field, &c->value); 8257 break; 8258 case ACCESS_VMWRITE: 8259 c->flags = vmwrite_flags(c->field, 0); 8260 break; 8261 } 8262 c->time = rdtsc() - start; 8263 vmcall(); 8264 } 8265 } 8266 8267 static u64 vmread_from_shadow(u64 field) 8268 { 8269 struct vmcs *primary; 8270 struct vmcs *shadow; 8271 u64 value; 8272 8273 TEST_ASSERT(!vmcs_save(&primary)); 8274 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 8275 TEST_ASSERT(!make_vmcs_current(shadow)); 8276 value = vmcs_read(field); 8277 TEST_ASSERT(!make_vmcs_current(primary)); 8278 return value; 8279 } 8280 8281 static u64 vmwrite_to_shadow(u64 field, u64 value) 8282 { 8283 struct vmcs *primary; 8284 struct vmcs *shadow; 8285 8286 TEST_ASSERT(!vmcs_save(&primary)); 8287 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 8288 TEST_ASSERT(!make_vmcs_current(shadow)); 8289 vmcs_write(field, value); 8290 value = vmcs_read(field); 8291 TEST_ASSERT(!make_vmcs_current(primary)); 8292 return value; 8293 } 8294 8295 static void vmcs_shadow_test_access(u8 *bitmap[2], enum vmcs_access access) 8296 { 8297 struct vmcs_shadow_test_common *c = &l1_l2_common; 8298 8299 c->op = access; 8300 vmcs_write(VMX_INST_ERROR, 0); 8301 enter_guest(); 8302 c->reason = vmcs_read(EXI_REASON) & 0xffff; 8303 if (c->reason != VMX_VMCALL) { 8304 skip_exit_insn(); 8305 enter_guest(); 8306 } 8307 skip_exit_vmcall(); 8308 } 8309 8310 static void vmcs_shadow_test_field(u8 *bitmap[2], u64 field) 8311 { 8312 struct vmcs_shadow_test_common *c = &l1_l2_common; 8313 struct vmcs *shadow; 8314 u64 value; 8315 uintptr_t flags[2]; 8316 bool good_shadow; 8317 u32 vmx_inst_error; 8318 8319 report_prefix_pushf("field %lx", field); 8320 c->field = field; 8321 8322 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 8323 if (shadow != (struct vmcs *)-1ull) { 8324 flags[ACCESS_VMREAD] = vmread_flags(field, &value); 8325 flags[ACCESS_VMWRITE] = vmwrite_flags(field, value); 8326 good_shadow = !flags[ACCESS_VMREAD] && !flags[ACCESS_VMWRITE]; 8327 } else { 8328 /* 8329 * When VMCS link pointer is -1ull, VMWRITE/VMREAD on 8330 * shadowed-fields should fail with setting RFLAGS.CF. 8331 */ 8332 flags[ACCESS_VMREAD] = X86_EFLAGS_CF; 8333 flags[ACCESS_VMWRITE] = X86_EFLAGS_CF; 8334 good_shadow = false; 8335 } 8336 8337 /* Intercept both VMREAD and VMWRITE. */ 8338 report_prefix_push("no VMREAD/VMWRITE permission"); 8339 /* VMWRITE/VMREAD done on reserved-bit should always intercept */ 8340 if (!(field >> VMCS_FIELD_RESERVED_SHIFT)) { 8341 set_bit(field, bitmap[ACCESS_VMREAD]); 8342 set_bit(field, bitmap[ACCESS_VMWRITE]); 8343 } 8344 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 8345 report("not shadowed for VMWRITE", c->reason == VMX_VMWRITE); 8346 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 8347 report("not shadowed for VMREAD", c->reason == VMX_VMREAD); 8348 report_prefix_pop(); 8349 8350 if (field >> VMCS_FIELD_RESERVED_SHIFT) 8351 goto out; 8352 8353 /* Permit shadowed VMREAD. */ 8354 report_prefix_push("VMREAD permission only"); 8355 clear_bit(field, bitmap[ACCESS_VMREAD]); 8356 set_bit(field, bitmap[ACCESS_VMWRITE]); 8357 if (good_shadow) 8358 value = vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 8359 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 8360 report("not shadowed for VMWRITE", c->reason == VMX_VMWRITE); 8361 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 8362 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 8363 report("shadowed for VMREAD (in %ld cycles)", c->reason == VMX_VMCALL, 8364 c->time); 8365 report("ALU flags after VMREAD (%lx) are as expected (%lx)", 8366 c->flags == flags[ACCESS_VMREAD], 8367 c->flags, flags[ACCESS_VMREAD]); 8368 if (good_shadow) 8369 report("value read from shadow (%lx) is as expected (%lx)", 8370 c->value == value, c->value, value); 8371 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 8372 report("VMX_INST_ERROR (%d) is as expected (%d)", 8373 vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 8374 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 8375 report_prefix_pop(); 8376 8377 /* Permit shadowed VMWRITE. */ 8378 report_prefix_push("VMWRITE permission only"); 8379 set_bit(field, bitmap[ACCESS_VMREAD]); 8380 clear_bit(field, bitmap[ACCESS_VMWRITE]); 8381 if (good_shadow) 8382 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 8383 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 8384 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 8385 report("shadowed for VMWRITE (in %ld cycles)", c->reason == VMX_VMCALL, 8386 c->time); 8387 report("ALU flags after VMWRITE (%lx) are as expected (%lx)", 8388 c->flags == flags[ACCESS_VMREAD], 8389 c->flags, flags[ACCESS_VMREAD]); 8390 if (good_shadow) { 8391 value = vmread_from_shadow(field); 8392 report("shadow VMCS value (%lx) is as expected (%lx)", 8393 value == 0, value, 0ul); 8394 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 8395 report("VMX_INST_ERROR (%d) is as expected (%d)", 8396 vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 8397 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 8398 } 8399 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 8400 report("not shadowed for VMREAD", c->reason == VMX_VMREAD); 8401 report_prefix_pop(); 8402 8403 /* Permit shadowed VMREAD and VMWRITE. */ 8404 report_prefix_push("VMREAD and VMWRITE permission"); 8405 clear_bit(field, bitmap[ACCESS_VMREAD]); 8406 clear_bit(field, bitmap[ACCESS_VMWRITE]); 8407 if (good_shadow) 8408 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 8409 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 8410 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 8411 report("shadowed for VMWRITE (in %ld cycles)", c->reason == VMX_VMCALL, 8412 c->time); 8413 report("ALU flags after VMWRITE (%lx) are as expected (%lx)", 8414 c->flags == flags[ACCESS_VMREAD], 8415 c->flags, flags[ACCESS_VMREAD]); 8416 if (good_shadow) { 8417 value = vmread_from_shadow(field); 8418 report("shadow VMCS value (%lx) is as expected (%lx)", 8419 value == 0, value, 0ul); 8420 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 8421 report("VMX_INST_ERROR (%d) is as expected (%d)", 8422 vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 8423 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 8424 } 8425 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 8426 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 8427 report("shadowed for VMREAD (in %ld cycles)", c->reason == VMX_VMCALL, 8428 c->time); 8429 report("ALU flags after VMREAD (%lx) are as expected (%lx)", 8430 c->flags == flags[ACCESS_VMREAD], 8431 c->flags, flags[ACCESS_VMREAD]); 8432 if (good_shadow) 8433 report("value read from shadow (%lx) is as expected (%lx)", 8434 c->value == 0, c->value, 0ul); 8435 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 8436 report("VMX_INST_ERROR (%d) is as expected (%d)", 8437 vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 8438 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 8439 report_prefix_pop(); 8440 8441 out: 8442 report_prefix_pop(); 8443 } 8444 8445 static void vmx_vmcs_shadow_test_body(u8 *bitmap[2]) 8446 { 8447 unsigned base; 8448 unsigned index; 8449 unsigned bit; 8450 unsigned highest_index = rdmsr(MSR_IA32_VMX_VMCS_ENUM); 8451 8452 /* Run test on all possible valid VMCS fields */ 8453 for (base = 0; 8454 base < (1 << VMCS_FIELD_RESERVED_SHIFT); 8455 base += (1 << VMCS_FIELD_TYPE_SHIFT)) 8456 for (index = 0; index <= highest_index; index++) 8457 vmcs_shadow_test_field(bitmap, base + index); 8458 8459 /* 8460 * Run tests on some invalid VMCS fields 8461 * (Have reserved bit set). 8462 */ 8463 for (bit = VMCS_FIELD_RESERVED_SHIFT; bit < VMCS_FIELD_BIT_SIZE; bit++) 8464 vmcs_shadow_test_field(bitmap, (1ull << bit)); 8465 } 8466 8467 static void vmx_vmcs_shadow_test(void) 8468 { 8469 u8 *bitmap[2]; 8470 struct vmcs *shadow; 8471 8472 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 8473 printf("\t'Activate secondary controls' not supported.\n"); 8474 return; 8475 } 8476 8477 if (!(ctrl_cpu_rev[1].clr & CPU_SHADOW_VMCS)) { 8478 printf("\t'VMCS shadowing' not supported.\n"); 8479 return; 8480 } 8481 8482 if (!(rdmsr(MSR_IA32_VMX_MISC) & 8483 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS)) { 8484 printf("\tVMWRITE can't modify VM-exit information fields.\n"); 8485 return; 8486 } 8487 8488 test_set_guest(vmx_vmcs_shadow_test_guest); 8489 8490 bitmap[ACCESS_VMREAD] = alloc_page(); 8491 bitmap[ACCESS_VMWRITE] = alloc_page(); 8492 8493 vmcs_write(VMREAD_BITMAP, virt_to_phys(bitmap[ACCESS_VMREAD])); 8494 vmcs_write(VMWRITE_BITMAP, virt_to_phys(bitmap[ACCESS_VMWRITE])); 8495 8496 shadow = alloc_page(); 8497 shadow->hdr.revision_id = basic.revision; 8498 shadow->hdr.shadow_vmcs = 1; 8499 TEST_ASSERT(!vmcs_clear(shadow)); 8500 8501 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_RDTSC); 8502 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY); 8503 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_SHADOW_VMCS); 8504 8505 vmcs_write(VMCS_LINK_PTR, virt_to_phys(shadow)); 8506 report_prefix_push("valid link pointer"); 8507 vmx_vmcs_shadow_test_body(bitmap); 8508 report_prefix_pop(); 8509 8510 vmcs_write(VMCS_LINK_PTR, -1ull); 8511 report_prefix_push("invalid link pointer"); 8512 vmx_vmcs_shadow_test_body(bitmap); 8513 report_prefix_pop(); 8514 8515 l1_l2_common.op = ACCESS_NONE; 8516 enter_guest(); 8517 } 8518 8519 8520 8521 static int invalid_msr_init(struct vmcs *vmcs) 8522 { 8523 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 8524 printf("\tPreemption timer is not supported\n"); 8525 return VMX_TEST_EXIT; 8526 } 8527 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 8528 preempt_val = 10000000; 8529 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 8530 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 8531 8532 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 8533 printf("\tSave preemption value is not supported\n"); 8534 8535 vmcs_write(ENT_MSR_LD_CNT, 1); 8536 vmcs_write(ENTER_MSR_LD_ADDR, (u64)0x13370000); 8537 8538 return VMX_TEST_START; 8539 } 8540 8541 8542 static void invalid_msr_main(void) 8543 { 8544 report("Invalid MSR load", 0); 8545 } 8546 8547 static int invalid_msr_exit_handler(void) 8548 { 8549 report("Invalid MSR load", 0); 8550 print_vmexit_info(); 8551 return VMX_TEST_EXIT; 8552 } 8553 8554 static int invalid_msr_entry_failure(struct vmentry_failure *failure) 8555 { 8556 ulong reason; 8557 8558 reason = vmcs_read(EXI_REASON); 8559 report("Invalid MSR load", reason == (0x80000000u | VMX_FAIL_MSR)); 8560 return VMX_TEST_VMEXIT; 8561 } 8562 8563 8564 #define TEST(name) { #name, .v2 = name } 8565 8566 /* name/init/guest_main/exit_handler/syscall_handler/guest_regs */ 8567 struct vmx_test vmx_tests[] = { 8568 { "null", NULL, basic_guest_main, basic_exit_handler, NULL, {0} }, 8569 { "vmenter", NULL, vmenter_main, vmenter_exit_handler, NULL, {0} }, 8570 { "preemption timer", preemption_timer_init, preemption_timer_main, 8571 preemption_timer_exit_handler, NULL, {0} }, 8572 { "control field PAT", test_ctrl_pat_init, test_ctrl_pat_main, 8573 test_ctrl_pat_exit_handler, NULL, {0} }, 8574 { "control field EFER", test_ctrl_efer_init, test_ctrl_efer_main, 8575 test_ctrl_efer_exit_handler, NULL, {0} }, 8576 { "CR shadowing", NULL, cr_shadowing_main, 8577 cr_shadowing_exit_handler, NULL, {0} }, 8578 { "I/O bitmap", iobmp_init, iobmp_main, iobmp_exit_handler, 8579 NULL, {0} }, 8580 { "instruction intercept", insn_intercept_init, insn_intercept_main, 8581 insn_intercept_exit_handler, NULL, {0} }, 8582 { "EPT A/D disabled", ept_init, ept_main, ept_exit_handler, NULL, {0} }, 8583 { "EPT A/D enabled", eptad_init, eptad_main, eptad_exit_handler, NULL, {0} }, 8584 { "PML", pml_init, pml_main, pml_exit_handler, NULL, {0} }, 8585 { "VPID", vpid_init, vpid_main, vpid_exit_handler, NULL, {0} }, 8586 { "interrupt", interrupt_init, interrupt_main, 8587 interrupt_exit_handler, NULL, {0} }, 8588 { "debug controls", dbgctls_init, dbgctls_main, dbgctls_exit_handler, 8589 NULL, {0} }, 8590 { "MSR switch", msr_switch_init, msr_switch_main, 8591 msr_switch_exit_handler, NULL, {0}, msr_switch_entry_failure }, 8592 { "vmmcall", vmmcall_init, vmmcall_main, vmmcall_exit_handler, NULL, {0} }, 8593 { "disable RDTSCP", disable_rdtscp_init, disable_rdtscp_main, 8594 disable_rdtscp_exit_handler, NULL, {0} }, 8595 { "int3", int3_init, int3_guest_main, int3_exit_handler, NULL, {0} }, 8596 { "into", into_init, into_guest_main, into_exit_handler, NULL, {0} }, 8597 { "exit_monitor_from_l2_test", NULL, exit_monitor_from_l2_main, 8598 exit_monitor_from_l2_handler, NULL, {0} }, 8599 { "invalid_msr", invalid_msr_init, invalid_msr_main, 8600 invalid_msr_exit_handler, NULL, {0}, invalid_msr_entry_failure}, 8601 /* Basic V2 tests. */ 8602 TEST(v2_null_test), 8603 TEST(v2_multiple_entries_test), 8604 TEST(fixture_test_case1), 8605 TEST(fixture_test_case2), 8606 /* Opcode tests. */ 8607 TEST(invvpid_test_v2), 8608 /* VM-entry tests */ 8609 TEST(vmx_controls_test), 8610 TEST(vmx_host_state_area_test), 8611 TEST(vmx_guest_state_area_test), 8612 TEST(vmentry_movss_shadow_test), 8613 /* APICv tests */ 8614 TEST(vmx_eoi_bitmap_ioapic_scan_test), 8615 TEST(vmx_hlt_with_rvi_test), 8616 TEST(apic_reg_virt_test), 8617 TEST(virt_x2apic_mode_test), 8618 /* APIC pass-through tests */ 8619 TEST(vmx_apic_passthrough_test), 8620 TEST(vmx_apic_passthrough_thread_test), 8621 /* VMCS Shadowing tests */ 8622 TEST(vmx_vmcs_shadow_test), 8623 /* Regression tests */ 8624 TEST(vmx_cr_load_test), 8625 TEST(vmx_nm_test), 8626 TEST(vmx_db_test), 8627 TEST(vmx_nmi_window_test), 8628 TEST(vmx_intr_window_test), 8629 TEST(vmx_pending_event_test), 8630 TEST(vmx_pending_event_hlt_test), 8631 TEST(vmx_store_tsc_test), 8632 /* EPT access tests. */ 8633 TEST(ept_access_test_not_present), 8634 TEST(ept_access_test_read_only), 8635 TEST(ept_access_test_write_only), 8636 TEST(ept_access_test_read_write), 8637 TEST(ept_access_test_execute_only), 8638 TEST(ept_access_test_read_execute), 8639 TEST(ept_access_test_write_execute), 8640 TEST(ept_access_test_read_write_execute), 8641 TEST(ept_access_test_reserved_bits), 8642 TEST(ept_access_test_ignored_bits), 8643 TEST(ept_access_test_paddr_not_present_ad_disabled), 8644 TEST(ept_access_test_paddr_not_present_ad_enabled), 8645 TEST(ept_access_test_paddr_read_only_ad_disabled), 8646 TEST(ept_access_test_paddr_read_only_ad_enabled), 8647 TEST(ept_access_test_paddr_read_write), 8648 TEST(ept_access_test_paddr_read_write_execute), 8649 TEST(ept_access_test_paddr_read_execute_ad_disabled), 8650 TEST(ept_access_test_paddr_read_execute_ad_enabled), 8651 TEST(ept_access_test_paddr_not_present_page_fault), 8652 TEST(ept_access_test_force_2m_page), 8653 { NULL, NULL, NULL, NULL, NULL, {0} }, 8654 }; 8655