1 /* 2 * All test cases of nested virtualization should be in this file 3 * 4 * Author : Arthur Chunqi Li <yzt356@gmail.com> 5 */ 6 7 #include <asm/debugreg.h> 8 9 #include "vmx.h" 10 #include "msr.h" 11 #include "processor.h" 12 #include "vm.h" 13 #include "pci.h" 14 #include "fwcfg.h" 15 #include "isr.h" 16 #include "desc.h" 17 #include "apic.h" 18 #include "types.h" 19 #include "vmalloc.h" 20 #include "alloc_page.h" 21 #include "smp.h" 22 #include "delay.h" 23 #include "access.h" 24 #include "x86/usermode.h" 25 26 #define VPID_CAP_INVVPID_TYPES_SHIFT 40 27 28 u64 ia32_pat; 29 u64 ia32_efer; 30 void *io_bitmap_a, *io_bitmap_b; 31 u16 ioport; 32 33 unsigned long *pml4; 34 u64 eptp; 35 void *data_page1, *data_page2; 36 37 phys_addr_t pci_physaddr; 38 39 void *pml_log; 40 #define PML_INDEX 512 41 42 static inline unsigned ffs(unsigned x) 43 { 44 int pos = -1; 45 46 __asm__ __volatile__("bsf %1, %%eax; cmovnz %%eax, %0" 47 : "+r"(pos) : "rm"(x) : "eax"); 48 return pos + 1; 49 } 50 51 static inline void vmcall(void) 52 { 53 asm volatile("vmcall"); 54 } 55 56 static void basic_guest_main(void) 57 { 58 report_pass("Basic VMX test"); 59 } 60 61 static int basic_exit_handler(union exit_reason exit_reason) 62 { 63 report_fail("Basic VMX test"); 64 print_vmexit_info(exit_reason); 65 return VMX_TEST_EXIT; 66 } 67 68 static void vmenter_main(void) 69 { 70 u64 rax; 71 u64 rsp, resume_rsp; 72 73 report_pass("test vmlaunch"); 74 75 asm volatile( 76 "mov %%rsp, %0\n\t" 77 "mov %3, %%rax\n\t" 78 "vmcall\n\t" 79 "mov %%rax, %1\n\t" 80 "mov %%rsp, %2\n\t" 81 : "=r"(rsp), "=r"(rax), "=r"(resume_rsp) 82 : "g"(0xABCD)); 83 report((rax == 0xFFFF) && (rsp == resume_rsp), "test vmresume"); 84 } 85 86 static int vmenter_exit_handler(union exit_reason exit_reason) 87 { 88 u64 guest_rip = vmcs_read(GUEST_RIP); 89 90 switch (exit_reason.basic) { 91 case VMX_VMCALL: 92 if (regs.rax != 0xABCD) { 93 report_fail("test vmresume"); 94 return VMX_TEST_VMEXIT; 95 } 96 regs.rax = 0xFFFF; 97 vmcs_write(GUEST_RIP, guest_rip + 3); 98 return VMX_TEST_RESUME; 99 default: 100 report_fail("test vmresume"); 101 print_vmexit_info(exit_reason); 102 } 103 return VMX_TEST_VMEXIT; 104 } 105 106 u32 preempt_scale; 107 volatile unsigned long long tsc_val; 108 volatile u32 preempt_val; 109 u64 saved_rip; 110 111 static int preemption_timer_init(struct vmcs *vmcs) 112 { 113 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 114 printf("\tPreemption timer is not supported\n"); 115 return VMX_TEST_EXIT; 116 } 117 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 118 preempt_val = 10000000; 119 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 120 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 121 122 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 123 printf("\tSave preemption value is not supported\n"); 124 125 return VMX_TEST_START; 126 } 127 128 static void preemption_timer_main(void) 129 { 130 tsc_val = rdtsc(); 131 if (ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) { 132 vmx_set_test_stage(0); 133 vmcall(); 134 if (vmx_get_test_stage() == 1) 135 vmcall(); 136 } 137 vmx_set_test_stage(1); 138 while (vmx_get_test_stage() == 1) { 139 if (((rdtsc() - tsc_val) >> preempt_scale) 140 > 10 * preempt_val) { 141 vmx_set_test_stage(2); 142 vmcall(); 143 } 144 } 145 tsc_val = rdtsc(); 146 asm volatile ("hlt"); 147 vmcall(); 148 vmx_set_test_stage(5); 149 vmcall(); 150 } 151 152 static int preemption_timer_exit_handler(union exit_reason exit_reason) 153 { 154 bool guest_halted; 155 u64 guest_rip; 156 u32 insn_len; 157 u32 ctrl_exit; 158 159 guest_rip = vmcs_read(GUEST_RIP); 160 insn_len = vmcs_read(EXI_INST_LEN); 161 switch (exit_reason.basic) { 162 case VMX_PREEMPT: 163 switch (vmx_get_test_stage()) { 164 case 1: 165 case 2: 166 report(((rdtsc() - tsc_val) >> preempt_scale) >= preempt_val, 167 "busy-wait for preemption timer"); 168 vmx_set_test_stage(3); 169 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 170 return VMX_TEST_RESUME; 171 case 3: 172 guest_halted = 173 (vmcs_read(GUEST_ACTV_STATE) == ACTV_HLT); 174 report(((rdtsc() - tsc_val) >> preempt_scale) >= preempt_val 175 && guest_halted, 176 "preemption timer during hlt"); 177 vmx_set_test_stage(4); 178 vmcs_write(PIN_CONTROLS, 179 vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 180 vmcs_write(EXI_CONTROLS, 181 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_PREEMPT); 182 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 183 return VMX_TEST_RESUME; 184 case 4: 185 report(saved_rip == guest_rip, 186 "preemption timer with 0 value"); 187 break; 188 default: 189 report_fail("Invalid stage."); 190 print_vmexit_info(exit_reason); 191 break; 192 } 193 break; 194 case VMX_VMCALL: 195 vmcs_write(GUEST_RIP, guest_rip + insn_len); 196 switch (vmx_get_test_stage()) { 197 case 0: 198 report(vmcs_read(PREEMPT_TIMER_VALUE) == preempt_val, 199 "Keep preemption value"); 200 vmx_set_test_stage(1); 201 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 202 ctrl_exit = (vmcs_read(EXI_CONTROLS) | 203 EXI_SAVE_PREEMPT) & ctrl_exit_rev.clr; 204 vmcs_write(EXI_CONTROLS, ctrl_exit); 205 return VMX_TEST_RESUME; 206 case 1: 207 report(vmcs_read(PREEMPT_TIMER_VALUE) < preempt_val, 208 "Save preemption value"); 209 return VMX_TEST_RESUME; 210 case 2: 211 report_fail("busy-wait for preemption timer"); 212 vmx_set_test_stage(3); 213 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 214 return VMX_TEST_RESUME; 215 case 3: 216 report_fail("preemption timer during hlt"); 217 vmx_set_test_stage(4); 218 /* fall through */ 219 case 4: 220 vmcs_write(PIN_CONTROLS, 221 vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 222 vmcs_write(PREEMPT_TIMER_VALUE, 0); 223 saved_rip = guest_rip + insn_len; 224 return VMX_TEST_RESUME; 225 case 5: 226 report_fail("preemption timer with 0 value (vmcall stage 5)"); 227 break; 228 default: 229 // Should not reach here 230 report_fail("unexpected stage, %d", 231 vmx_get_test_stage()); 232 print_vmexit_info(exit_reason); 233 return VMX_TEST_VMEXIT; 234 } 235 break; 236 default: 237 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 238 print_vmexit_info(exit_reason); 239 } 240 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 241 return VMX_TEST_VMEXIT; 242 } 243 244 static void msr_bmp_init(void) 245 { 246 void *msr_bitmap; 247 u32 ctrl_cpu0; 248 249 msr_bitmap = alloc_page(); 250 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 251 ctrl_cpu0 |= CPU_MSR_BITMAP; 252 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 253 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 254 } 255 256 static void *get_msr_bitmap(void) 257 { 258 void *msr_bitmap; 259 260 if (vmcs_read(CPU_EXEC_CTRL0) & CPU_MSR_BITMAP) { 261 msr_bitmap = (void *)vmcs_read(MSR_BITMAP); 262 } else { 263 msr_bitmap = alloc_page(); 264 memset(msr_bitmap, 0xff, PAGE_SIZE); 265 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 266 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_MSR_BITMAP); 267 } 268 269 return msr_bitmap; 270 } 271 272 static void disable_intercept_for_x2apic_msrs(void) 273 { 274 unsigned long *msr_bitmap = (unsigned long *)get_msr_bitmap(); 275 u32 msr; 276 277 for (msr = APIC_BASE_MSR; 278 msr < (APIC_BASE_MSR+0xff); 279 msr += BITS_PER_LONG) { 280 unsigned int word = msr / BITS_PER_LONG; 281 282 msr_bitmap[word] = 0; 283 msr_bitmap[word + (0x800 / sizeof(long))] = 0; 284 } 285 } 286 287 static int test_ctrl_pat_init(struct vmcs *vmcs) 288 { 289 u64 ctrl_ent; 290 u64 ctrl_exi; 291 292 msr_bmp_init(); 293 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT) && 294 !(ctrl_exit_rev.clr & EXI_LOAD_PAT) && 295 !(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 296 printf("\tSave/load PAT is not supported\n"); 297 return 1; 298 } 299 300 ctrl_ent = vmcs_read(ENT_CONTROLS); 301 ctrl_exi = vmcs_read(EXI_CONTROLS); 302 ctrl_ent |= ctrl_enter_rev.clr & ENT_LOAD_PAT; 303 ctrl_exi |= ctrl_exit_rev.clr & (EXI_SAVE_PAT | EXI_LOAD_PAT); 304 vmcs_write(ENT_CONTROLS, ctrl_ent); 305 vmcs_write(EXI_CONTROLS, ctrl_exi); 306 ia32_pat = rdmsr(MSR_IA32_CR_PAT); 307 vmcs_write(GUEST_PAT, 0x0); 308 vmcs_write(HOST_PAT, ia32_pat); 309 return VMX_TEST_START; 310 } 311 312 static void test_ctrl_pat_main(void) 313 { 314 u64 guest_ia32_pat; 315 316 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 317 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) 318 printf("\tENT_LOAD_PAT is not supported.\n"); 319 else { 320 if (guest_ia32_pat != 0) { 321 report_fail("Entry load PAT"); 322 return; 323 } 324 } 325 wrmsr(MSR_IA32_CR_PAT, 0x6); 326 vmcall(); 327 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 328 if (ctrl_enter_rev.clr & ENT_LOAD_PAT) 329 report(guest_ia32_pat == ia32_pat, "Entry load PAT"); 330 } 331 332 static int test_ctrl_pat_exit_handler(union exit_reason exit_reason) 333 { 334 u64 guest_rip; 335 u64 guest_pat; 336 337 guest_rip = vmcs_read(GUEST_RIP); 338 switch (exit_reason.basic) { 339 case VMX_VMCALL: 340 guest_pat = vmcs_read(GUEST_PAT); 341 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT)) { 342 printf("\tEXI_SAVE_PAT is not supported\n"); 343 vmcs_write(GUEST_PAT, 0x6); 344 } else { 345 report(guest_pat == 0x6, "Exit save PAT"); 346 } 347 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) 348 printf("\tEXI_LOAD_PAT is not supported\n"); 349 else 350 report(rdmsr(MSR_IA32_CR_PAT) == ia32_pat, 351 "Exit load PAT"); 352 vmcs_write(GUEST_PAT, ia32_pat); 353 vmcs_write(GUEST_RIP, guest_rip + 3); 354 return VMX_TEST_RESUME; 355 default: 356 printf("ERROR : Unknown exit reason, 0x%x.\n", exit_reason.full); 357 break; 358 } 359 return VMX_TEST_VMEXIT; 360 } 361 362 static int test_ctrl_efer_init(struct vmcs *vmcs) 363 { 364 u64 ctrl_ent; 365 u64 ctrl_exi; 366 367 msr_bmp_init(); 368 ctrl_ent = vmcs_read(ENT_CONTROLS) | ENT_LOAD_EFER; 369 ctrl_exi = vmcs_read(EXI_CONTROLS) | EXI_SAVE_EFER | EXI_LOAD_EFER; 370 vmcs_write(ENT_CONTROLS, ctrl_ent & ctrl_enter_rev.clr); 371 vmcs_write(EXI_CONTROLS, ctrl_exi & ctrl_exit_rev.clr); 372 ia32_efer = rdmsr(MSR_EFER); 373 vmcs_write(GUEST_EFER, ia32_efer ^ EFER_NX); 374 vmcs_write(HOST_EFER, ia32_efer ^ EFER_NX); 375 return VMX_TEST_START; 376 } 377 378 static void test_ctrl_efer_main(void) 379 { 380 u64 guest_ia32_efer; 381 382 guest_ia32_efer = rdmsr(MSR_EFER); 383 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) 384 printf("\tENT_LOAD_EFER is not supported.\n"); 385 else { 386 if (guest_ia32_efer != (ia32_efer ^ EFER_NX)) { 387 report_fail("Entry load EFER"); 388 return; 389 } 390 } 391 wrmsr(MSR_EFER, ia32_efer); 392 vmcall(); 393 guest_ia32_efer = rdmsr(MSR_EFER); 394 if (ctrl_enter_rev.clr & ENT_LOAD_EFER) 395 report(guest_ia32_efer == ia32_efer, "Entry load EFER"); 396 } 397 398 static int test_ctrl_efer_exit_handler(union exit_reason exit_reason) 399 { 400 u64 guest_rip; 401 u64 guest_efer; 402 403 guest_rip = vmcs_read(GUEST_RIP); 404 switch (exit_reason.basic) { 405 case VMX_VMCALL: 406 guest_efer = vmcs_read(GUEST_EFER); 407 if (!(ctrl_exit_rev.clr & EXI_SAVE_EFER)) { 408 printf("\tEXI_SAVE_EFER is not supported\n"); 409 vmcs_write(GUEST_EFER, ia32_efer); 410 } else { 411 report(guest_efer == ia32_efer, "Exit save EFER"); 412 } 413 if (!(ctrl_exit_rev.clr & EXI_LOAD_EFER)) { 414 printf("\tEXI_LOAD_EFER is not supported\n"); 415 wrmsr(MSR_EFER, ia32_efer ^ EFER_NX); 416 } else { 417 report(rdmsr(MSR_EFER) == (ia32_efer ^ EFER_NX), 418 "Exit load EFER"); 419 } 420 vmcs_write(GUEST_PAT, ia32_efer); 421 vmcs_write(GUEST_RIP, guest_rip + 3); 422 return VMX_TEST_RESUME; 423 default: 424 printf("ERROR : Unknown exit reason, 0x%x.\n", exit_reason.full); 425 break; 426 } 427 return VMX_TEST_VMEXIT; 428 } 429 430 u32 guest_cr0, guest_cr4; 431 432 static void cr_shadowing_main(void) 433 { 434 u32 cr0, cr4, tmp; 435 436 // Test read through 437 vmx_set_test_stage(0); 438 guest_cr0 = read_cr0(); 439 if (vmx_get_test_stage() == 1) 440 report_fail("Read through CR0"); 441 else 442 vmcall(); 443 vmx_set_test_stage(1); 444 guest_cr4 = read_cr4(); 445 if (vmx_get_test_stage() == 2) 446 report_fail("Read through CR4"); 447 else 448 vmcall(); 449 // Test write through 450 guest_cr0 = guest_cr0 ^ (X86_CR0_TS | X86_CR0_MP); 451 guest_cr4 = guest_cr4 ^ (X86_CR4_TSD | X86_CR4_DE); 452 vmx_set_test_stage(2); 453 write_cr0(guest_cr0); 454 if (vmx_get_test_stage() == 3) 455 report_fail("Write throuth CR0"); 456 else 457 vmcall(); 458 vmx_set_test_stage(3); 459 write_cr4(guest_cr4); 460 if (vmx_get_test_stage() == 4) 461 report_fail("Write through CR4"); 462 else 463 vmcall(); 464 // Test read shadow 465 vmx_set_test_stage(4); 466 vmcall(); 467 cr0 = read_cr0(); 468 if (vmx_get_test_stage() != 5) 469 report(cr0 == guest_cr0, "Read shadowing CR0"); 470 vmx_set_test_stage(5); 471 cr4 = read_cr4(); 472 if (vmx_get_test_stage() != 6) 473 report(cr4 == guest_cr4, "Read shadowing CR4"); 474 // Test write shadow (same value with shadow) 475 vmx_set_test_stage(6); 476 write_cr0(guest_cr0); 477 if (vmx_get_test_stage() == 7) 478 report_fail("Write shadowing CR0 (same value with shadow)"); 479 else 480 vmcall(); 481 vmx_set_test_stage(7); 482 write_cr4(guest_cr4); 483 if (vmx_get_test_stage() == 8) 484 report_fail("Write shadowing CR4 (same value with shadow)"); 485 else 486 vmcall(); 487 // Test write shadow (different value) 488 vmx_set_test_stage(8); 489 tmp = guest_cr0 ^ X86_CR0_TS; 490 asm volatile("mov %0, %%rsi\n\t" 491 "mov %%rsi, %%cr0\n\t" 492 ::"m"(tmp) 493 :"rsi", "memory", "cc"); 494 report(vmx_get_test_stage() == 9, 495 "Write shadowing different X86_CR0_TS"); 496 vmx_set_test_stage(9); 497 tmp = guest_cr0 ^ X86_CR0_MP; 498 asm volatile("mov %0, %%rsi\n\t" 499 "mov %%rsi, %%cr0\n\t" 500 ::"m"(tmp) 501 :"rsi", "memory", "cc"); 502 report(vmx_get_test_stage() == 10, 503 "Write shadowing different X86_CR0_MP"); 504 vmx_set_test_stage(10); 505 tmp = guest_cr4 ^ X86_CR4_TSD; 506 asm volatile("mov %0, %%rsi\n\t" 507 "mov %%rsi, %%cr4\n\t" 508 ::"m"(tmp) 509 :"rsi", "memory", "cc"); 510 report(vmx_get_test_stage() == 11, 511 "Write shadowing different X86_CR4_TSD"); 512 vmx_set_test_stage(11); 513 tmp = guest_cr4 ^ X86_CR4_DE; 514 asm volatile("mov %0, %%rsi\n\t" 515 "mov %%rsi, %%cr4\n\t" 516 ::"m"(tmp) 517 :"rsi", "memory", "cc"); 518 report(vmx_get_test_stage() == 12, 519 "Write shadowing different X86_CR4_DE"); 520 } 521 522 static int cr_shadowing_exit_handler(union exit_reason exit_reason) 523 { 524 u64 guest_rip; 525 u32 insn_len; 526 u32 exit_qual; 527 528 guest_rip = vmcs_read(GUEST_RIP); 529 insn_len = vmcs_read(EXI_INST_LEN); 530 exit_qual = vmcs_read(EXI_QUALIFICATION); 531 switch (exit_reason.basic) { 532 case VMX_VMCALL: 533 switch (vmx_get_test_stage()) { 534 case 0: 535 report(guest_cr0 == vmcs_read(GUEST_CR0), 536 "Read through CR0"); 537 break; 538 case 1: 539 report(guest_cr4 == vmcs_read(GUEST_CR4), 540 "Read through CR4"); 541 break; 542 case 2: 543 report(guest_cr0 == vmcs_read(GUEST_CR0), 544 "Write through CR0"); 545 break; 546 case 3: 547 report(guest_cr4 == vmcs_read(GUEST_CR4), 548 "Write through CR4"); 549 break; 550 case 4: 551 guest_cr0 = vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP); 552 guest_cr4 = vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE); 553 vmcs_write(CR0_MASK, X86_CR0_TS | X86_CR0_MP); 554 vmcs_write(CR0_READ_SHADOW, guest_cr0 & (X86_CR0_TS | X86_CR0_MP)); 555 vmcs_write(CR4_MASK, X86_CR4_TSD | X86_CR4_DE); 556 vmcs_write(CR4_READ_SHADOW, guest_cr4 & (X86_CR4_TSD | X86_CR4_DE)); 557 break; 558 case 6: 559 report(guest_cr0 == (vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP)), 560 "Write shadowing CR0 (same value)"); 561 break; 562 case 7: 563 report(guest_cr4 == (vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE)), 564 "Write shadowing CR4 (same value)"); 565 break; 566 default: 567 // Should not reach here 568 report_fail("unexpected stage, %d", 569 vmx_get_test_stage()); 570 print_vmexit_info(exit_reason); 571 return VMX_TEST_VMEXIT; 572 } 573 vmcs_write(GUEST_RIP, guest_rip + insn_len); 574 return VMX_TEST_RESUME; 575 case VMX_CR: 576 switch (vmx_get_test_stage()) { 577 case 4: 578 report_fail("Read shadowing CR0"); 579 vmx_inc_test_stage(); 580 break; 581 case 5: 582 report_fail("Read shadowing CR4"); 583 vmx_inc_test_stage(); 584 break; 585 case 6: 586 report_fail("Write shadowing CR0 (same value)"); 587 vmx_inc_test_stage(); 588 break; 589 case 7: 590 report_fail("Write shadowing CR4 (same value)"); 591 vmx_inc_test_stage(); 592 break; 593 case 8: 594 case 9: 595 // 0x600 encodes "mov %esi, %cr0" 596 if (exit_qual == 0x600) 597 vmx_inc_test_stage(); 598 break; 599 case 10: 600 case 11: 601 // 0x604 encodes "mov %esi, %cr4" 602 if (exit_qual == 0x604) 603 vmx_inc_test_stage(); 604 break; 605 default: 606 // Should not reach here 607 report_fail("unexpected stage, %d", 608 vmx_get_test_stage()); 609 print_vmexit_info(exit_reason); 610 return VMX_TEST_VMEXIT; 611 } 612 vmcs_write(GUEST_RIP, guest_rip + insn_len); 613 return VMX_TEST_RESUME; 614 default: 615 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 616 print_vmexit_info(exit_reason); 617 } 618 return VMX_TEST_VMEXIT; 619 } 620 621 static int iobmp_init(struct vmcs *vmcs) 622 { 623 u32 ctrl_cpu0; 624 625 io_bitmap_a = alloc_page(); 626 io_bitmap_b = alloc_page(); 627 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 628 ctrl_cpu0 |= CPU_IO_BITMAP; 629 ctrl_cpu0 &= (~CPU_IO); 630 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 631 vmcs_write(IO_BITMAP_A, (u64)io_bitmap_a); 632 vmcs_write(IO_BITMAP_B, (u64)io_bitmap_b); 633 return VMX_TEST_START; 634 } 635 636 static void iobmp_main(void) 637 { 638 // stage 0, test IO pass 639 vmx_set_test_stage(0); 640 inb(0x5000); 641 outb(0x0, 0x5000); 642 report(vmx_get_test_stage() == 0, "I/O bitmap - I/O pass"); 643 // test IO width, in/out 644 ((u8 *)io_bitmap_a)[0] = 0xFF; 645 vmx_set_test_stage(2); 646 inb(0x0); 647 report(vmx_get_test_stage() == 3, "I/O bitmap - trap in"); 648 vmx_set_test_stage(3); 649 outw(0x0, 0x0); 650 report(vmx_get_test_stage() == 4, "I/O bitmap - trap out"); 651 vmx_set_test_stage(4); 652 inl(0x0); 653 report(vmx_get_test_stage() == 5, "I/O bitmap - I/O width, long"); 654 // test low/high IO port 655 vmx_set_test_stage(5); 656 ((u8 *)io_bitmap_a)[0x5000 / 8] = (1 << (0x5000 % 8)); 657 inb(0x5000); 658 report(vmx_get_test_stage() == 6, "I/O bitmap - I/O port, low part"); 659 vmx_set_test_stage(6); 660 ((u8 *)io_bitmap_b)[0x1000 / 8] = (1 << (0x1000 % 8)); 661 inb(0x9000); 662 report(vmx_get_test_stage() == 7, "I/O bitmap - I/O port, high part"); 663 // test partial pass 664 vmx_set_test_stage(7); 665 inl(0x4FFF); 666 report(vmx_get_test_stage() == 8, "I/O bitmap - partial pass"); 667 // test overrun 668 vmx_set_test_stage(8); 669 memset(io_bitmap_a, 0x0, PAGE_SIZE); 670 memset(io_bitmap_b, 0x0, PAGE_SIZE); 671 inl(0xFFFF); 672 report(vmx_get_test_stage() == 9, "I/O bitmap - overrun"); 673 vmx_set_test_stage(9); 674 vmcall(); 675 outb(0x0, 0x0); 676 report(vmx_get_test_stage() == 9, 677 "I/O bitmap - ignore unconditional exiting"); 678 vmx_set_test_stage(10); 679 vmcall(); 680 outb(0x0, 0x0); 681 report(vmx_get_test_stage() == 11, 682 "I/O bitmap - unconditional exiting"); 683 } 684 685 static int iobmp_exit_handler(union exit_reason exit_reason) 686 { 687 u64 guest_rip; 688 ulong exit_qual; 689 u32 insn_len, ctrl_cpu0; 690 691 guest_rip = vmcs_read(GUEST_RIP); 692 exit_qual = vmcs_read(EXI_QUALIFICATION); 693 insn_len = vmcs_read(EXI_INST_LEN); 694 switch (exit_reason.basic) { 695 case VMX_IO: 696 switch (vmx_get_test_stage()) { 697 case 0: 698 case 1: 699 vmx_inc_test_stage(); 700 break; 701 case 2: 702 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_BYTE, 703 "I/O bitmap - I/O width, byte"); 704 report(exit_qual & VMX_IO_IN, 705 "I/O bitmap - I/O direction, in"); 706 vmx_inc_test_stage(); 707 break; 708 case 3: 709 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_WORD, 710 "I/O bitmap - I/O width, word"); 711 report(!(exit_qual & VMX_IO_IN), 712 "I/O bitmap - I/O direction, out"); 713 vmx_inc_test_stage(); 714 break; 715 case 4: 716 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_LONG, 717 "I/O bitmap - I/O width, long"); 718 vmx_inc_test_stage(); 719 break; 720 case 5: 721 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x5000) 722 vmx_inc_test_stage(); 723 break; 724 case 6: 725 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x9000) 726 vmx_inc_test_stage(); 727 break; 728 case 7: 729 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x4FFF) 730 vmx_inc_test_stage(); 731 break; 732 case 8: 733 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0xFFFF) 734 vmx_inc_test_stage(); 735 break; 736 case 9: 737 case 10: 738 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 739 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0 & ~CPU_IO); 740 vmx_inc_test_stage(); 741 break; 742 default: 743 // Should not reach here 744 report_fail("unexpected stage, %d", 745 vmx_get_test_stage()); 746 print_vmexit_info(exit_reason); 747 return VMX_TEST_VMEXIT; 748 } 749 vmcs_write(GUEST_RIP, guest_rip + insn_len); 750 return VMX_TEST_RESUME; 751 case VMX_VMCALL: 752 switch (vmx_get_test_stage()) { 753 case 9: 754 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 755 ctrl_cpu0 |= CPU_IO | CPU_IO_BITMAP; 756 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 757 break; 758 case 10: 759 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 760 ctrl_cpu0 = (ctrl_cpu0 & ~CPU_IO_BITMAP) | CPU_IO; 761 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 762 break; 763 default: 764 // Should not reach here 765 report_fail("unexpected stage, %d", 766 vmx_get_test_stage()); 767 print_vmexit_info(exit_reason); 768 return VMX_TEST_VMEXIT; 769 } 770 vmcs_write(GUEST_RIP, guest_rip + insn_len); 771 return VMX_TEST_RESUME; 772 default: 773 printf("guest_rip = %#lx\n", guest_rip); 774 printf("\tERROR : Unknown exit reason, 0x%x\n", exit_reason.full); 775 break; 776 } 777 return VMX_TEST_VMEXIT; 778 } 779 780 #define INSN_CPU0 0 781 #define INSN_CPU1 1 782 #define INSN_ALWAYS_TRAP 2 783 784 #define FIELD_EXIT_QUAL (1 << 0) 785 #define FIELD_INSN_INFO (1 << 1) 786 787 asm( 788 "insn_hlt: hlt;ret\n\t" 789 "insn_invlpg: invlpg 0x12345678;ret\n\t" 790 "insn_mwait: xor %eax, %eax; xor %ecx, %ecx; mwait;ret\n\t" 791 "insn_rdpmc: xor %ecx, %ecx; rdpmc;ret\n\t" 792 "insn_rdtsc: rdtsc;ret\n\t" 793 "insn_cr3_load: mov cr3,%rax; mov %rax,%cr3;ret\n\t" 794 "insn_cr3_store: mov %cr3,%rax;ret\n\t" 795 "insn_cr8_load: xor %eax, %eax; mov %rax,%cr8;ret\n\t" 796 "insn_cr8_store: mov %cr8,%rax;ret\n\t" 797 "insn_monitor: xor %eax, %eax; xor %ecx, %ecx; xor %edx, %edx; monitor;ret\n\t" 798 "insn_pause: pause;ret\n\t" 799 "insn_wbinvd: wbinvd;ret\n\t" 800 "insn_cpuid: mov $10, %eax; cpuid;ret\n\t" 801 "insn_invd: invd;ret\n\t" 802 "insn_sgdt: sgdt gdt_descr;ret\n\t" 803 "insn_lgdt: lgdt gdt_descr;ret\n\t" 804 "insn_sidt: sidt idt_descr;ret\n\t" 805 "insn_lidt: lidt idt_descr;ret\n\t" 806 "insn_sldt: sldt %ax;ret\n\t" 807 "insn_lldt: xor %eax, %eax; lldt %ax;ret\n\t" 808 "insn_str: str %ax;ret\n\t" 809 "insn_rdrand: rdrand %rax;ret\n\t" 810 "insn_rdseed: rdseed %rax;ret\n\t" 811 ); 812 extern void insn_hlt(void); 813 extern void insn_invlpg(void); 814 extern void insn_mwait(void); 815 extern void insn_rdpmc(void); 816 extern void insn_rdtsc(void); 817 extern void insn_cr3_load(void); 818 extern void insn_cr3_store(void); 819 extern void insn_cr8_load(void); 820 extern void insn_cr8_store(void); 821 extern void insn_monitor(void); 822 extern void insn_pause(void); 823 extern void insn_wbinvd(void); 824 extern void insn_sgdt(void); 825 extern void insn_lgdt(void); 826 extern void insn_sidt(void); 827 extern void insn_lidt(void); 828 extern void insn_sldt(void); 829 extern void insn_lldt(void); 830 extern void insn_str(void); 831 extern void insn_cpuid(void); 832 extern void insn_invd(void); 833 extern void insn_rdrand(void); 834 extern void insn_rdseed(void); 835 836 u32 cur_insn; 837 u64 cr3; 838 839 #define X86_FEATURE_MONITOR (1 << 3) 840 841 typedef bool (*supported_fn)(void); 842 843 static bool monitor_supported(void) 844 { 845 return this_cpu_has(X86_FEATURE_MWAIT); 846 } 847 848 struct insn_table { 849 const char *name; 850 u32 flag; 851 void (*insn_func)(void); 852 u32 type; 853 u32 reason; 854 ulong exit_qual; 855 u32 insn_info; 856 // Use FIELD_EXIT_QUAL and FIELD_INSN_INFO to define 857 // which field need to be tested, reason is always tested 858 u32 test_field; 859 const supported_fn supported_fn; 860 u8 disabled; 861 }; 862 863 /* 864 * Add more test cases of instruction intercept here. Elements in this 865 * table is: 866 * name/control flag/insn function/type/exit reason/exit qulification/ 867 * instruction info/field to test 868 * The last field defines which fields (exit_qual and insn_info) need to be 869 * tested in exit handler. If set to 0, only "reason" is checked. 870 */ 871 static struct insn_table insn_table[] = { 872 // Flags for Primary Processor-Based VM-Execution Controls 873 {"HLT", CPU_HLT, insn_hlt, INSN_CPU0, 12, 0, 0, 0}, 874 {"INVLPG", CPU_INVLPG, insn_invlpg, INSN_CPU0, 14, 875 0x12345678, 0, FIELD_EXIT_QUAL}, 876 {"MWAIT", CPU_MWAIT, insn_mwait, INSN_CPU0, 36, 0, 0, 0, &monitor_supported}, 877 {"RDPMC", CPU_RDPMC, insn_rdpmc, INSN_CPU0, 15, 0, 0, 0}, 878 {"RDTSC", CPU_RDTSC, insn_rdtsc, INSN_CPU0, 16, 0, 0, 0}, 879 {"CR3 load", CPU_CR3_LOAD, insn_cr3_load, INSN_CPU0, 28, 0x3, 0, 880 FIELD_EXIT_QUAL}, 881 {"CR3 store", CPU_CR3_STORE, insn_cr3_store, INSN_CPU0, 28, 0x13, 0, 882 FIELD_EXIT_QUAL}, 883 {"CR8 load", CPU_CR8_LOAD, insn_cr8_load, INSN_CPU0, 28, 0x8, 0, 884 FIELD_EXIT_QUAL}, 885 {"CR8 store", CPU_CR8_STORE, insn_cr8_store, INSN_CPU0, 28, 0x18, 0, 886 FIELD_EXIT_QUAL}, 887 {"MONITOR", CPU_MONITOR, insn_monitor, INSN_CPU0, 39, 0, 0, 0, &monitor_supported}, 888 {"PAUSE", CPU_PAUSE, insn_pause, INSN_CPU0, 40, 0, 0, 0}, 889 // Flags for Secondary Processor-Based VM-Execution Controls 890 {"WBINVD", CPU_WBINVD, insn_wbinvd, INSN_CPU1, 54, 0, 0, 0}, 891 {"DESC_TABLE (SGDT)", CPU_DESC_TABLE, insn_sgdt, INSN_CPU1, 46, 0, 0, 0}, 892 {"DESC_TABLE (LGDT)", CPU_DESC_TABLE, insn_lgdt, INSN_CPU1, 46, 0, 0, 0}, 893 {"DESC_TABLE (SIDT)", CPU_DESC_TABLE, insn_sidt, INSN_CPU1, 46, 0, 0, 0}, 894 {"DESC_TABLE (LIDT)", CPU_DESC_TABLE, insn_lidt, INSN_CPU1, 46, 0, 0, 0}, 895 {"DESC_TABLE (SLDT)", CPU_DESC_TABLE, insn_sldt, INSN_CPU1, 47, 0, 0, 0}, 896 {"DESC_TABLE (LLDT)", CPU_DESC_TABLE, insn_lldt, INSN_CPU1, 47, 0, 0, 0}, 897 {"DESC_TABLE (STR)", CPU_DESC_TABLE, insn_str, INSN_CPU1, 47, 0, 0, 0}, 898 /* LTR causes a #GP if done with a busy selector, so it is not tested. */ 899 {"RDRAND", CPU_RDRAND, insn_rdrand, INSN_CPU1, VMX_RDRAND, 0, 0, 0}, 900 {"RDSEED", CPU_RDSEED, insn_rdseed, INSN_CPU1, VMX_RDSEED, 0, 0, 0}, 901 // Instructions always trap 902 {"CPUID", 0, insn_cpuid, INSN_ALWAYS_TRAP, 10, 0, 0, 0}, 903 {"INVD", 0, insn_invd, INSN_ALWAYS_TRAP, 13, 0, 0, 0}, 904 // Instructions never trap 905 {NULL}, 906 }; 907 908 static int insn_intercept_init(struct vmcs *vmcs) 909 { 910 u32 ctrl_cpu, cur_insn; 911 912 ctrl_cpu = ctrl_cpu_rev[0].set | CPU_SECONDARY; 913 ctrl_cpu &= ctrl_cpu_rev[0].clr; 914 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu); 915 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu_rev[1].set); 916 cr3 = read_cr3(); 917 918 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 919 if (insn_table[cur_insn].supported_fn == NULL) 920 continue; 921 insn_table[cur_insn].disabled = !insn_table[cur_insn].supported_fn(); 922 } 923 return VMX_TEST_START; 924 } 925 926 static void insn_intercept_main(void) 927 { 928 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 929 vmx_set_test_stage(cur_insn * 2); 930 if ((insn_table[cur_insn].type == INSN_CPU0 && 931 !(ctrl_cpu_rev[0].clr & insn_table[cur_insn].flag)) || 932 (insn_table[cur_insn].type == INSN_CPU1 && 933 !(ctrl_cpu_rev[1].clr & insn_table[cur_insn].flag))) { 934 printf("\tCPU_CTRL%d.CPU_%s is not supported.\n", 935 insn_table[cur_insn].type - INSN_CPU0, 936 insn_table[cur_insn].name); 937 continue; 938 } 939 940 if (insn_table[cur_insn].disabled) { 941 printf("\tFeature required for %s is not supported.\n", 942 insn_table[cur_insn].name); 943 continue; 944 } 945 946 if ((insn_table[cur_insn].type == INSN_CPU0 && 947 !(ctrl_cpu_rev[0].set & insn_table[cur_insn].flag)) || 948 (insn_table[cur_insn].type == INSN_CPU1 && 949 !(ctrl_cpu_rev[1].set & insn_table[cur_insn].flag))) { 950 /* skip hlt, it stalls the guest and is tested below */ 951 if (insn_table[cur_insn].insn_func != insn_hlt) 952 insn_table[cur_insn].insn_func(); 953 report(vmx_get_test_stage() == cur_insn * 2, 954 "execute %s", 955 insn_table[cur_insn].name); 956 } else if (insn_table[cur_insn].type != INSN_ALWAYS_TRAP) 957 printf("\tCPU_CTRL%d.CPU_%s always traps.\n", 958 insn_table[cur_insn].type - INSN_CPU0, 959 insn_table[cur_insn].name); 960 961 vmcall(); 962 963 insn_table[cur_insn].insn_func(); 964 report(vmx_get_test_stage() == cur_insn * 2 + 1, 965 "intercept %s", 966 insn_table[cur_insn].name); 967 968 vmx_set_test_stage(cur_insn * 2 + 1); 969 vmcall(); 970 } 971 } 972 973 static int insn_intercept_exit_handler(union exit_reason exit_reason) 974 { 975 u64 guest_rip; 976 ulong exit_qual; 977 u32 insn_len; 978 u32 insn_info; 979 bool pass; 980 981 guest_rip = vmcs_read(GUEST_RIP); 982 exit_qual = vmcs_read(EXI_QUALIFICATION); 983 insn_len = vmcs_read(EXI_INST_LEN); 984 insn_info = vmcs_read(EXI_INST_INFO); 985 986 if (exit_reason.basic == VMX_VMCALL) { 987 u32 val = 0; 988 989 if (insn_table[cur_insn].type == INSN_CPU0) 990 val = vmcs_read(CPU_EXEC_CTRL0); 991 else if (insn_table[cur_insn].type == INSN_CPU1) 992 val = vmcs_read(CPU_EXEC_CTRL1); 993 994 if (vmx_get_test_stage() & 1) 995 val &= ~insn_table[cur_insn].flag; 996 else 997 val |= insn_table[cur_insn].flag; 998 999 if (insn_table[cur_insn].type == INSN_CPU0) 1000 vmcs_write(CPU_EXEC_CTRL0, val | ctrl_cpu_rev[0].set); 1001 else if (insn_table[cur_insn].type == INSN_CPU1) 1002 vmcs_write(CPU_EXEC_CTRL1, val | ctrl_cpu_rev[1].set); 1003 } else { 1004 pass = (cur_insn * 2 == vmx_get_test_stage()) && 1005 insn_table[cur_insn].reason == exit_reason.full; 1006 if (insn_table[cur_insn].test_field & FIELD_EXIT_QUAL && 1007 insn_table[cur_insn].exit_qual != exit_qual) 1008 pass = false; 1009 if (insn_table[cur_insn].test_field & FIELD_INSN_INFO && 1010 insn_table[cur_insn].insn_info != insn_info) 1011 pass = false; 1012 if (pass) 1013 vmx_inc_test_stage(); 1014 } 1015 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1016 return VMX_TEST_RESUME; 1017 } 1018 1019 /** 1020 * __setup_ept - Setup the VMCS fields to enable Extended Page Tables (EPT) 1021 * @hpa: Host physical address of the top-level, a.k.a. root, EPT table 1022 * @enable_ad: Whether or not to enable Access/Dirty bits for EPT entries 1023 * 1024 * Returns 0 on success, 1 on failure. 1025 * 1026 * Note that @hpa doesn't need to point at actual memory if VM-Launch is 1027 * expected to fail, e.g. setup_dummy_ept() arbitrarily passes '0' to satisfy 1028 * the various EPTP consistency checks, but doesn't ensure backing for HPA '0'. 1029 */ 1030 static int __setup_ept(u64 hpa, bool enable_ad) 1031 { 1032 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1033 !(ctrl_cpu_rev[1].clr & CPU_EPT)) { 1034 printf("\tEPT is not supported\n"); 1035 return 1; 1036 } 1037 if (!(ept_vpid.val & EPT_CAP_WB)) { 1038 printf("\tWB memtype for EPT walks not supported\n"); 1039 return 1; 1040 } 1041 if (!(ept_vpid.val & EPT_CAP_PWL4)) { 1042 printf("\tPWL4 is not supported\n"); 1043 return 1; 1044 } 1045 1046 eptp = EPT_MEM_TYPE_WB; 1047 eptp |= (3 << EPTP_PG_WALK_LEN_SHIFT); 1048 eptp |= hpa; 1049 if (enable_ad) 1050 eptp |= EPTP_AD_FLAG; 1051 1052 vmcs_write(EPTP, eptp); 1053 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0)| CPU_SECONDARY); 1054 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1)| CPU_EPT); 1055 1056 return 0; 1057 } 1058 1059 /** 1060 * setup_ept - Enable Extended Page Tables (EPT) and setup an identity map 1061 * @enable_ad: Whether or not to enable Access/Dirty bits for EPT entries 1062 * 1063 * Returns 0 on success, 1 on failure. 1064 * 1065 * This is the "real" function for setting up EPT tables, i.e. use this for 1066 * tests that need to run code in the guest with EPT enabled. 1067 */ 1068 static int setup_ept(bool enable_ad) 1069 { 1070 unsigned long end_of_memory; 1071 1072 pml4 = alloc_page(); 1073 1074 if (__setup_ept(virt_to_phys(pml4), enable_ad)) 1075 return 1; 1076 1077 end_of_memory = fwcfg_get_u64(FW_CFG_RAM_SIZE); 1078 if (end_of_memory < (1ul << 32)) 1079 end_of_memory = (1ul << 32); 1080 /* Cannot use large EPT pages if we need to track EPT 1081 * accessed/dirty bits at 4K granularity. 1082 */ 1083 setup_ept_range(pml4, 0, end_of_memory, 0, 1084 !enable_ad && ept_2m_supported(), 1085 EPT_WA | EPT_RA | EPT_EA); 1086 return 0; 1087 } 1088 1089 /** 1090 * setup_dummy_ept - Enable Extended Page Tables (EPT) with a dummy root HPA 1091 * 1092 * Setup EPT using a semi-arbitrary dummy root HPA. This function is intended 1093 * for use by tests that need EPT enabled to verify dependent VMCS controls 1094 * but never expect to fully enter the guest, i.e. don't need setup the actual 1095 * EPT tables. 1096 */ 1097 static void setup_dummy_ept(void) 1098 { 1099 if (__setup_ept(0, false)) 1100 report_abort("EPT setup unexpectedly failed"); 1101 } 1102 1103 static int enable_unrestricted_guest(bool need_valid_ept) 1104 { 1105 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1106 !(ctrl_cpu_rev[1].clr & CPU_URG) || 1107 !(ctrl_cpu_rev[1].clr & CPU_EPT)) 1108 return 1; 1109 1110 if (need_valid_ept) 1111 setup_ept(false); 1112 else 1113 setup_dummy_ept(); 1114 1115 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 1116 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | CPU_URG); 1117 1118 return 0; 1119 } 1120 1121 static void ept_enable_ad_bits(void) 1122 { 1123 eptp |= EPTP_AD_FLAG; 1124 vmcs_write(EPTP, eptp); 1125 } 1126 1127 static void ept_disable_ad_bits(void) 1128 { 1129 eptp &= ~EPTP_AD_FLAG; 1130 vmcs_write(EPTP, eptp); 1131 } 1132 1133 static int ept_ad_enabled(void) 1134 { 1135 return eptp & EPTP_AD_FLAG; 1136 } 1137 1138 static void ept_enable_ad_bits_or_skip_test(void) 1139 { 1140 if (!ept_ad_bits_supported()) 1141 test_skip("EPT AD bits not supported."); 1142 ept_enable_ad_bits(); 1143 } 1144 1145 static int apic_version; 1146 1147 static int ept_init_common(bool have_ad) 1148 { 1149 int ret; 1150 struct pci_dev pcidev; 1151 1152 /* INVEPT is required by the EPT violation handler. */ 1153 if (!is_invept_type_supported(INVEPT_SINGLE)) 1154 return VMX_TEST_EXIT; 1155 1156 if (setup_ept(have_ad)) 1157 return VMX_TEST_EXIT; 1158 1159 data_page1 = alloc_page(); 1160 data_page2 = alloc_page(); 1161 *((u32 *)data_page1) = MAGIC_VAL_1; 1162 *((u32 *)data_page2) = MAGIC_VAL_2; 1163 install_ept(pml4, (unsigned long)data_page1, (unsigned long)data_page2, 1164 EPT_RA | EPT_WA | EPT_EA); 1165 1166 apic_version = apic_read(APIC_LVR); 1167 1168 ret = pci_find_dev(PCI_VENDOR_ID_REDHAT, PCI_DEVICE_ID_REDHAT_TEST); 1169 if (ret != PCIDEVADDR_INVALID) { 1170 pci_dev_init(&pcidev, ret); 1171 pci_physaddr = pcidev.resource[PCI_TESTDEV_BAR_MEM]; 1172 } 1173 1174 return VMX_TEST_START; 1175 } 1176 1177 static int ept_init(struct vmcs *vmcs) 1178 { 1179 return ept_init_common(false); 1180 } 1181 1182 static void ept_common(void) 1183 { 1184 vmx_set_test_stage(0); 1185 if (*((u32 *)data_page2) != MAGIC_VAL_1 || 1186 *((u32 *)data_page1) != MAGIC_VAL_1) 1187 report_fail("EPT basic framework - read"); 1188 else { 1189 *((u32 *)data_page2) = MAGIC_VAL_3; 1190 vmcall(); 1191 if (vmx_get_test_stage() == 1) { 1192 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1193 *((u32 *)data_page2) == MAGIC_VAL_2) 1194 report_pass("EPT basic framework"); 1195 else 1196 report_pass("EPT basic framework - remap"); 1197 } 1198 } 1199 // Test EPT Misconfigurations 1200 vmx_set_test_stage(1); 1201 vmcall(); 1202 *((u32 *)data_page1) = MAGIC_VAL_1; 1203 if (vmx_get_test_stage() != 2) { 1204 report_fail("EPT misconfigurations"); 1205 goto t1; 1206 } 1207 vmx_set_test_stage(2); 1208 vmcall(); 1209 *((u32 *)data_page1) = MAGIC_VAL_1; 1210 report(vmx_get_test_stage() == 3, "EPT misconfigurations"); 1211 t1: 1212 // Test EPT violation 1213 vmx_set_test_stage(3); 1214 vmcall(); 1215 *((u32 *)data_page1) = MAGIC_VAL_1; 1216 report(vmx_get_test_stage() == 4, "EPT violation - page permission"); 1217 // Violation caused by EPT paging structure 1218 vmx_set_test_stage(4); 1219 vmcall(); 1220 *((u32 *)data_page1) = MAGIC_VAL_2; 1221 report(vmx_get_test_stage() == 5, "EPT violation - paging structure"); 1222 1223 // MMIO Read/Write 1224 vmx_set_test_stage(5); 1225 vmcall(); 1226 1227 *(u32 volatile *)pci_physaddr; 1228 report(vmx_get_test_stage() == 6, "MMIO EPT violation - read"); 1229 1230 *(u32 volatile *)pci_physaddr = MAGIC_VAL_1; 1231 report(vmx_get_test_stage() == 7, "MMIO EPT violation - write"); 1232 } 1233 1234 static void ept_main(void) 1235 { 1236 ept_common(); 1237 1238 // Test EPT access to L1 MMIO 1239 vmx_set_test_stage(7); 1240 report(*((u32 *)0xfee00030UL) == apic_version, "EPT - MMIO access"); 1241 1242 // Test invalid operand for INVEPT 1243 vmcall(); 1244 report(vmx_get_test_stage() == 8, "EPT - unsupported INVEPT"); 1245 } 1246 1247 static bool invept_test(int type, u64 eptp) 1248 { 1249 bool ret, supported; 1250 1251 supported = ept_vpid.val & (EPT_CAP_INVEPT_SINGLE >> INVEPT_SINGLE << type); 1252 ret = __invept(type, eptp); 1253 1254 if (ret == !supported) 1255 return false; 1256 1257 if (!supported) 1258 printf("WARNING: unsupported invept passed!\n"); 1259 else 1260 printf("WARNING: invept failed!\n"); 1261 1262 return true; 1263 } 1264 1265 static int pml_exit_handler(union exit_reason exit_reason) 1266 { 1267 u16 index, count; 1268 u64 *pmlbuf = pml_log; 1269 u64 guest_rip = vmcs_read(GUEST_RIP);; 1270 u64 guest_cr3 = vmcs_read(GUEST_CR3); 1271 u32 insn_len = vmcs_read(EXI_INST_LEN); 1272 1273 switch (exit_reason.basic) { 1274 case VMX_VMCALL: 1275 switch (vmx_get_test_stage()) { 1276 case 0: 1277 index = vmcs_read(GUEST_PML_INDEX); 1278 for (count = index + 1; count < PML_INDEX; count++) { 1279 if (pmlbuf[count] == (u64)data_page2) { 1280 vmx_inc_test_stage(); 1281 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1282 break; 1283 } 1284 } 1285 break; 1286 case 1: 1287 index = vmcs_read(GUEST_PML_INDEX); 1288 /* Keep clearing the dirty bit till a overflow */ 1289 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1290 break; 1291 default: 1292 report_fail("unexpected stage, %d.", 1293 vmx_get_test_stage()); 1294 print_vmexit_info(exit_reason); 1295 return VMX_TEST_VMEXIT; 1296 } 1297 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1298 return VMX_TEST_RESUME; 1299 case VMX_PML_FULL: 1300 vmx_inc_test_stage(); 1301 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1302 return VMX_TEST_RESUME; 1303 default: 1304 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 1305 print_vmexit_info(exit_reason); 1306 } 1307 return VMX_TEST_VMEXIT; 1308 } 1309 1310 static int ept_exit_handler_common(union exit_reason exit_reason, bool have_ad) 1311 { 1312 u64 guest_rip; 1313 u64 guest_cr3; 1314 u32 insn_len; 1315 u32 exit_qual; 1316 static unsigned long data_page1_pte, data_page1_pte_pte, memaddr_pte, 1317 guest_pte_addr; 1318 1319 guest_rip = vmcs_read(GUEST_RIP); 1320 guest_cr3 = vmcs_read(GUEST_CR3); 1321 insn_len = vmcs_read(EXI_INST_LEN); 1322 exit_qual = vmcs_read(EXI_QUALIFICATION); 1323 pteval_t *ptep; 1324 switch (exit_reason.basic) { 1325 case VMX_VMCALL: 1326 switch (vmx_get_test_stage()) { 1327 case 0: 1328 check_ept_ad(pml4, guest_cr3, 1329 (unsigned long)data_page1, 1330 have_ad ? EPT_ACCESS_FLAG : 0, 1331 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1332 check_ept_ad(pml4, guest_cr3, 1333 (unsigned long)data_page2, 1334 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0, 1335 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1336 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1337 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1338 if (have_ad) 1339 invept(INVEPT_SINGLE, eptp); 1340 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1341 *((u32 *)data_page2) == MAGIC_VAL_2) { 1342 vmx_inc_test_stage(); 1343 install_ept(pml4, (unsigned long)data_page2, 1344 (unsigned long)data_page2, 1345 EPT_RA | EPT_WA | EPT_EA); 1346 } else 1347 report_fail("EPT basic framework - write"); 1348 break; 1349 case 1: 1350 install_ept(pml4, (unsigned long)data_page1, 1351 (unsigned long)data_page1, EPT_WA); 1352 invept(INVEPT_SINGLE, eptp); 1353 break; 1354 case 2: 1355 install_ept(pml4, (unsigned long)data_page1, 1356 (unsigned long)data_page1, 1357 EPT_RA | EPT_WA | EPT_EA | 1358 (2 << EPT_MEM_TYPE_SHIFT)); 1359 invept(INVEPT_SINGLE, eptp); 1360 break; 1361 case 3: 1362 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1363 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)data_page1, 1364 1, &data_page1_pte)); 1365 set_ept_pte(pml4, (unsigned long)data_page1, 1366 1, data_page1_pte & ~EPT_PRESENT); 1367 invept(INVEPT_SINGLE, eptp); 1368 break; 1369 case 4: 1370 ptep = get_pte_level((pgd_t *)guest_cr3, data_page1, /*level=*/2); 1371 guest_pte_addr = virt_to_phys(ptep) & PAGE_MASK; 1372 1373 TEST_ASSERT(get_ept_pte(pml4, guest_pte_addr, 2, &data_page1_pte_pte)); 1374 set_ept_pte(pml4, guest_pte_addr, 2, 1375 data_page1_pte_pte & ~EPT_PRESENT); 1376 invept(INVEPT_SINGLE, eptp); 1377 break; 1378 case 5: 1379 install_ept(pml4, (unsigned long)pci_physaddr, 1380 (unsigned long)pci_physaddr, 0); 1381 invept(INVEPT_SINGLE, eptp); 1382 break; 1383 case 7: 1384 if (!invept_test(0, eptp)) 1385 vmx_inc_test_stage(); 1386 break; 1387 // Should not reach here 1388 default: 1389 report_fail("ERROR - unexpected stage, %d.", 1390 vmx_get_test_stage()); 1391 print_vmexit_info(exit_reason); 1392 return VMX_TEST_VMEXIT; 1393 } 1394 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1395 return VMX_TEST_RESUME; 1396 case VMX_EPT_MISCONFIG: 1397 switch (vmx_get_test_stage()) { 1398 case 1: 1399 case 2: 1400 vmx_inc_test_stage(); 1401 install_ept(pml4, (unsigned long)data_page1, 1402 (unsigned long)data_page1, 1403 EPT_RA | EPT_WA | EPT_EA); 1404 invept(INVEPT_SINGLE, eptp); 1405 break; 1406 // Should not reach here 1407 default: 1408 report_fail("ERROR - unexpected stage, %d.", 1409 vmx_get_test_stage()); 1410 print_vmexit_info(exit_reason); 1411 return VMX_TEST_VMEXIT; 1412 } 1413 return VMX_TEST_RESUME; 1414 case VMX_EPT_VIOLATION: 1415 /* 1416 * Exit-qualifications are masked not to account for advanced 1417 * VM-exit information. Once KVM supports this feature, this 1418 * masking should be removed. 1419 */ 1420 exit_qual &= ~EPT_VLT_GUEST_MASK; 1421 1422 switch(vmx_get_test_stage()) { 1423 case 3: 1424 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1425 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1426 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1427 if (exit_qual == (EPT_VLT_WR | EPT_VLT_LADDR_VLD | 1428 EPT_VLT_PADDR)) 1429 vmx_inc_test_stage(); 1430 set_ept_pte(pml4, (unsigned long)data_page1, 1431 1, data_page1_pte | (EPT_PRESENT)); 1432 invept(INVEPT_SINGLE, eptp); 1433 break; 1434 case 4: 1435 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1436 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1437 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1438 if (exit_qual == (EPT_VLT_RD | 1439 (have_ad ? EPT_VLT_WR : 0) | 1440 EPT_VLT_LADDR_VLD)) 1441 vmx_inc_test_stage(); 1442 set_ept_pte(pml4, guest_pte_addr, 2, 1443 data_page1_pte_pte | (EPT_PRESENT)); 1444 invept(INVEPT_SINGLE, eptp); 1445 break; 1446 case 5: 1447 if (exit_qual & EPT_VLT_RD) 1448 vmx_inc_test_stage(); 1449 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1450 1, &memaddr_pte)); 1451 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA); 1452 invept(INVEPT_SINGLE, eptp); 1453 break; 1454 case 6: 1455 if (exit_qual & EPT_VLT_WR) 1456 vmx_inc_test_stage(); 1457 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1458 1, &memaddr_pte)); 1459 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA | EPT_WA); 1460 invept(INVEPT_SINGLE, eptp); 1461 break; 1462 default: 1463 // Should not reach here 1464 report_fail("ERROR : unexpected stage, %d", 1465 vmx_get_test_stage()); 1466 print_vmexit_info(exit_reason); 1467 return VMX_TEST_VMEXIT; 1468 } 1469 return VMX_TEST_RESUME; 1470 default: 1471 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 1472 print_vmexit_info(exit_reason); 1473 } 1474 return VMX_TEST_VMEXIT; 1475 } 1476 1477 static int ept_exit_handler(union exit_reason exit_reason) 1478 { 1479 return ept_exit_handler_common(exit_reason, false); 1480 } 1481 1482 static int eptad_init(struct vmcs *vmcs) 1483 { 1484 int r = ept_init_common(true); 1485 1486 if (r == VMX_TEST_EXIT) 1487 return r; 1488 1489 if (!ept_ad_bits_supported()) { 1490 printf("\tEPT A/D bits are not supported"); 1491 return VMX_TEST_EXIT; 1492 } 1493 1494 return r; 1495 } 1496 1497 static int pml_init(struct vmcs *vmcs) 1498 { 1499 u32 ctrl_cpu; 1500 int r = eptad_init(vmcs); 1501 1502 if (r == VMX_TEST_EXIT) 1503 return r; 1504 1505 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1506 !(ctrl_cpu_rev[1].clr & CPU_PML)) { 1507 printf("\tPML is not supported"); 1508 return VMX_TEST_EXIT; 1509 } 1510 1511 pml_log = alloc_page(); 1512 vmcs_write(PMLADDR, (u64)pml_log); 1513 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1514 1515 ctrl_cpu = vmcs_read(CPU_EXEC_CTRL1) | CPU_PML; 1516 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu); 1517 1518 return VMX_TEST_START; 1519 } 1520 1521 static void pml_main(void) 1522 { 1523 int count = 0; 1524 1525 vmx_set_test_stage(0); 1526 *((u32 *)data_page2) = 0x1; 1527 vmcall(); 1528 report(vmx_get_test_stage() == 1, "PML - Dirty GPA Logging"); 1529 1530 while (vmx_get_test_stage() == 1) { 1531 vmcall(); 1532 *((u32 *)data_page2) = 0x1; 1533 if (count++ > PML_INDEX) 1534 break; 1535 } 1536 report(vmx_get_test_stage() == 2, "PML Full Event"); 1537 } 1538 1539 static void eptad_main(void) 1540 { 1541 ept_common(); 1542 } 1543 1544 static int eptad_exit_handler(union exit_reason exit_reason) 1545 { 1546 return ept_exit_handler_common(exit_reason, true); 1547 } 1548 1549 #define TIMER_VECTOR 222 1550 1551 static volatile bool timer_fired; 1552 1553 static void timer_isr(isr_regs_t *regs) 1554 { 1555 timer_fired = true; 1556 apic_write(APIC_EOI, 0); 1557 } 1558 1559 static int interrupt_init(struct vmcs *vmcs) 1560 { 1561 msr_bmp_init(); 1562 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1563 handle_irq(TIMER_VECTOR, timer_isr); 1564 return VMX_TEST_START; 1565 } 1566 1567 static void interrupt_main(void) 1568 { 1569 long long start, loops; 1570 1571 vmx_set_test_stage(0); 1572 1573 apic_write(APIC_LVTT, TIMER_VECTOR); 1574 irq_enable(); 1575 1576 apic_write(APIC_TMICT, 1); 1577 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1578 asm volatile ("nop"); 1579 report(timer_fired, "direct interrupt while running guest"); 1580 1581 apic_write(APIC_TMICT, 0); 1582 irq_disable(); 1583 vmcall(); 1584 timer_fired = false; 1585 apic_write(APIC_TMICT, 1); 1586 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1587 asm volatile ("nop"); 1588 report(timer_fired, "intercepted interrupt while running guest"); 1589 1590 irq_enable(); 1591 apic_write(APIC_TMICT, 0); 1592 irq_disable(); 1593 vmcall(); 1594 timer_fired = false; 1595 start = rdtsc(); 1596 apic_write(APIC_TMICT, 1000000); 1597 1598 safe_halt(); 1599 1600 report(rdtsc() - start > 1000000 && timer_fired, 1601 "direct interrupt + hlt"); 1602 1603 apic_write(APIC_TMICT, 0); 1604 irq_disable(); 1605 vmcall(); 1606 timer_fired = false; 1607 start = rdtsc(); 1608 apic_write(APIC_TMICT, 1000000); 1609 1610 safe_halt(); 1611 1612 report(rdtsc() - start > 10000 && timer_fired, 1613 "intercepted interrupt + hlt"); 1614 1615 apic_write(APIC_TMICT, 0); 1616 irq_disable(); 1617 vmcall(); 1618 timer_fired = false; 1619 start = rdtsc(); 1620 apic_write(APIC_TMICT, 1000000); 1621 1622 irq_enable(); 1623 asm volatile ("nop"); 1624 vmcall(); 1625 1626 report(rdtsc() - start > 10000 && timer_fired, 1627 "direct interrupt + activity state hlt"); 1628 1629 apic_write(APIC_TMICT, 0); 1630 irq_disable(); 1631 vmcall(); 1632 timer_fired = false; 1633 start = rdtsc(); 1634 apic_write(APIC_TMICT, 1000000); 1635 1636 irq_enable(); 1637 asm volatile ("nop"); 1638 vmcall(); 1639 1640 report(rdtsc() - start > 10000 && timer_fired, 1641 "intercepted interrupt + activity state hlt"); 1642 1643 apic_write(APIC_TMICT, 0); 1644 irq_disable(); 1645 vmx_set_test_stage(7); 1646 vmcall(); 1647 timer_fired = false; 1648 apic_write(APIC_TMICT, 1); 1649 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1650 asm volatile ("nop"); 1651 report(timer_fired, 1652 "running a guest with interrupt acknowledgement set"); 1653 1654 apic_write(APIC_TMICT, 0); 1655 irq_enable(); 1656 timer_fired = false; 1657 vmcall(); 1658 report(timer_fired, "Inject an event to a halted guest"); 1659 } 1660 1661 static int interrupt_exit_handler(union exit_reason exit_reason) 1662 { 1663 u64 guest_rip = vmcs_read(GUEST_RIP); 1664 u32 insn_len = vmcs_read(EXI_INST_LEN); 1665 1666 switch (exit_reason.basic) { 1667 case VMX_VMCALL: 1668 switch (vmx_get_test_stage()) { 1669 case 0: 1670 case 2: 1671 case 5: 1672 vmcs_write(PIN_CONTROLS, 1673 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1674 break; 1675 case 7: 1676 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_INTA); 1677 vmcs_write(PIN_CONTROLS, 1678 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1679 break; 1680 case 1: 1681 case 3: 1682 vmcs_write(PIN_CONTROLS, 1683 vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1684 break; 1685 case 4: 1686 case 6: 1687 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1688 break; 1689 1690 case 8: 1691 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1692 vmcs_write(ENT_INTR_INFO, 1693 TIMER_VECTOR | 1694 (VMX_INTR_TYPE_EXT_INTR << INTR_INFO_INTR_TYPE_SHIFT) | 1695 INTR_INFO_VALID_MASK); 1696 break; 1697 } 1698 vmx_inc_test_stage(); 1699 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1700 return VMX_TEST_RESUME; 1701 case VMX_EXTINT: 1702 if (vmcs_read(EXI_CONTROLS) & EXI_INTA) { 1703 int vector = vmcs_read(EXI_INTR_INFO) & 0xff; 1704 handle_external_interrupt(vector); 1705 } else { 1706 irq_enable(); 1707 asm volatile ("nop"); 1708 irq_disable(); 1709 } 1710 if (vmx_get_test_stage() >= 2) 1711 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 1712 return VMX_TEST_RESUME; 1713 default: 1714 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 1715 print_vmexit_info(exit_reason); 1716 } 1717 1718 return VMX_TEST_VMEXIT; 1719 } 1720 1721 1722 static volatile int nmi_fired; 1723 1724 #define NMI_DELAY 100000000ULL 1725 1726 static void nmi_isr(isr_regs_t *regs) 1727 { 1728 nmi_fired = true; 1729 } 1730 1731 static int nmi_hlt_init(struct vmcs *vmcs) 1732 { 1733 msr_bmp_init(); 1734 handle_irq(NMI_VECTOR, nmi_isr); 1735 vmcs_write(PIN_CONTROLS, 1736 vmcs_read(PIN_CONTROLS) & ~PIN_NMI); 1737 vmcs_write(PIN_CONTROLS, 1738 vmcs_read(PIN_CONTROLS) & ~PIN_VIRT_NMI); 1739 return VMX_TEST_START; 1740 } 1741 1742 static void nmi_message_thread(void *data) 1743 { 1744 while (vmx_get_test_stage() != 1) 1745 pause(); 1746 1747 delay(NMI_DELAY); 1748 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_NMI | APIC_INT_ASSERT, id_map[0]); 1749 1750 while (vmx_get_test_stage() != 2) 1751 pause(); 1752 1753 delay(NMI_DELAY); 1754 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_NMI | APIC_INT_ASSERT, id_map[0]); 1755 } 1756 1757 static void nmi_hlt_main(void) 1758 { 1759 long long start; 1760 1761 if (cpu_count() < 2) { 1762 report_skip(__func__); 1763 vmx_set_test_stage(-1); 1764 return; 1765 } 1766 1767 vmx_set_test_stage(0); 1768 on_cpu_async(1, nmi_message_thread, NULL); 1769 start = rdtsc(); 1770 vmx_set_test_stage(1); 1771 asm volatile ("hlt"); 1772 report((rdtsc() - start > NMI_DELAY) && nmi_fired, 1773 "direct NMI + hlt"); 1774 if (!nmi_fired) 1775 vmx_set_test_stage(-1); 1776 nmi_fired = false; 1777 1778 vmcall(); 1779 1780 start = rdtsc(); 1781 vmx_set_test_stage(2); 1782 asm volatile ("hlt"); 1783 report((rdtsc() - start > NMI_DELAY) && !nmi_fired, 1784 "intercepted NMI + hlt"); 1785 if (nmi_fired) { 1786 report(!nmi_fired, "intercepted NMI was dispatched"); 1787 vmx_set_test_stage(-1); 1788 return; 1789 } 1790 vmx_set_test_stage(3); 1791 } 1792 1793 static int nmi_hlt_exit_handler(union exit_reason exit_reason) 1794 { 1795 u64 guest_rip = vmcs_read(GUEST_RIP); 1796 u32 insn_len = vmcs_read(EXI_INST_LEN); 1797 1798 switch (vmx_get_test_stage()) { 1799 case 1: 1800 if (exit_reason.basic != VMX_VMCALL) { 1801 report_fail("VMEXIT not due to vmcall. Exit reason 0x%x", 1802 exit_reason.full); 1803 print_vmexit_info(exit_reason); 1804 return VMX_TEST_VMEXIT; 1805 } 1806 1807 vmcs_write(PIN_CONTROLS, 1808 vmcs_read(PIN_CONTROLS) | PIN_NMI); 1809 vmcs_write(PIN_CONTROLS, 1810 vmcs_read(PIN_CONTROLS) | PIN_VIRT_NMI); 1811 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1812 break; 1813 1814 case 2: 1815 if (exit_reason.basic != VMX_EXC_NMI) { 1816 report_fail("VMEXIT not due to NMI intercept. Exit reason 0x%x", 1817 exit_reason.full); 1818 print_vmexit_info(exit_reason); 1819 return VMX_TEST_VMEXIT; 1820 } 1821 report_pass("NMI intercept while running guest"); 1822 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 1823 break; 1824 1825 case 3: 1826 break; 1827 1828 default: 1829 return VMX_TEST_VMEXIT; 1830 } 1831 1832 if (vmx_get_test_stage() == 3) 1833 return VMX_TEST_VMEXIT; 1834 1835 return VMX_TEST_RESUME; 1836 } 1837 1838 1839 static int dbgctls_init(struct vmcs *vmcs) 1840 { 1841 u64 dr7 = 0x402; 1842 u64 zero = 0; 1843 1844 msr_bmp_init(); 1845 asm volatile( 1846 "mov %0,%%dr0\n\t" 1847 "mov %0,%%dr1\n\t" 1848 "mov %0,%%dr2\n\t" 1849 "mov %1,%%dr7\n\t" 1850 : : "r" (zero), "r" (dr7)); 1851 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1852 vmcs_write(GUEST_DR7, 0x404); 1853 vmcs_write(GUEST_DEBUGCTL, 0x2); 1854 1855 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 1856 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_SAVE_DBGCTLS); 1857 1858 return VMX_TEST_START; 1859 } 1860 1861 static void dbgctls_main(void) 1862 { 1863 u64 dr7, debugctl; 1864 1865 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1866 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1867 /* Commented out: KVM does not support DEBUGCTL so far */ 1868 (void)debugctl; 1869 report(dr7 == 0x404, "Load debug controls" /* && debugctl == 0x2 */); 1870 1871 dr7 = 0x408; 1872 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1873 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1874 1875 vmx_set_test_stage(0); 1876 vmcall(); 1877 report(vmx_get_test_stage() == 1, "Save debug controls"); 1878 1879 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS || 1880 ctrl_exit_rev.set & EXI_SAVE_DBGCTLS) { 1881 printf("\tDebug controls are always loaded/saved\n"); 1882 return; 1883 } 1884 vmx_set_test_stage(2); 1885 vmcall(); 1886 1887 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1888 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1889 /* Commented out: KVM does not support DEBUGCTL so far */ 1890 (void)debugctl; 1891 report(dr7 == 0x402, 1892 "Guest=host debug controls" /* && debugctl == 0x1 */); 1893 1894 dr7 = 0x408; 1895 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1896 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1897 1898 vmx_set_test_stage(3); 1899 vmcall(); 1900 report(vmx_get_test_stage() == 4, "Don't save debug controls"); 1901 } 1902 1903 static int dbgctls_exit_handler(union exit_reason exit_reason) 1904 { 1905 u32 insn_len = vmcs_read(EXI_INST_LEN); 1906 u64 guest_rip = vmcs_read(GUEST_RIP); 1907 u64 dr7, debugctl; 1908 1909 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1910 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1911 1912 switch (exit_reason.basic) { 1913 case VMX_VMCALL: 1914 switch (vmx_get_test_stage()) { 1915 case 0: 1916 if (dr7 == 0x400 && debugctl == 0 && 1917 vmcs_read(GUEST_DR7) == 0x408 /* && 1918 Commented out: KVM does not support DEBUGCTL so far 1919 vmcs_read(GUEST_DEBUGCTL) == 0x3 */) 1920 vmx_inc_test_stage(); 1921 break; 1922 case 2: 1923 dr7 = 0x402; 1924 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1925 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1926 vmcs_write(GUEST_DR7, 0x404); 1927 vmcs_write(GUEST_DEBUGCTL, 0x2); 1928 1929 vmcs_write(ENT_CONTROLS, 1930 vmcs_read(ENT_CONTROLS) & ~ENT_LOAD_DBGCTLS); 1931 vmcs_write(EXI_CONTROLS, 1932 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_DBGCTLS); 1933 break; 1934 case 3: 1935 if (dr7 == 0x400 && debugctl == 0 && 1936 vmcs_read(GUEST_DR7) == 0x404 /* && 1937 Commented out: KVM does not support DEBUGCTL so far 1938 vmcs_read(GUEST_DEBUGCTL) == 0x2 */) 1939 vmx_inc_test_stage(); 1940 break; 1941 } 1942 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1943 return VMX_TEST_RESUME; 1944 default: 1945 report_fail("Unknown exit reason, %d", exit_reason.full); 1946 print_vmexit_info(exit_reason); 1947 } 1948 return VMX_TEST_VMEXIT; 1949 } 1950 1951 struct vmx_msr_entry { 1952 u32 index; 1953 u32 reserved; 1954 u64 value; 1955 } __attribute__((packed)); 1956 1957 #define MSR_MAGIC 0x31415926 1958 struct vmx_msr_entry *exit_msr_store, *entry_msr_load, *exit_msr_load; 1959 1960 static int msr_switch_init(struct vmcs *vmcs) 1961 { 1962 msr_bmp_init(); 1963 exit_msr_store = alloc_page(); 1964 exit_msr_load = alloc_page(); 1965 entry_msr_load = alloc_page(); 1966 entry_msr_load[0].index = MSR_KERNEL_GS_BASE; 1967 entry_msr_load[0].value = MSR_MAGIC; 1968 1969 vmx_set_test_stage(1); 1970 vmcs_write(ENT_MSR_LD_CNT, 1); 1971 vmcs_write(ENTER_MSR_LD_ADDR, (u64)entry_msr_load); 1972 vmcs_write(EXI_MSR_ST_CNT, 1); 1973 vmcs_write(EXIT_MSR_ST_ADDR, (u64)exit_msr_store); 1974 vmcs_write(EXI_MSR_LD_CNT, 1); 1975 vmcs_write(EXIT_MSR_LD_ADDR, (u64)exit_msr_load); 1976 return VMX_TEST_START; 1977 } 1978 1979 static void msr_switch_main(void) 1980 { 1981 if (vmx_get_test_stage() == 1) { 1982 report(rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC, 1983 "VM entry MSR load"); 1984 vmx_set_test_stage(2); 1985 wrmsr(MSR_KERNEL_GS_BASE, MSR_MAGIC + 1); 1986 exit_msr_store[0].index = MSR_KERNEL_GS_BASE; 1987 exit_msr_load[0].index = MSR_KERNEL_GS_BASE; 1988 exit_msr_load[0].value = MSR_MAGIC + 2; 1989 } 1990 vmcall(); 1991 } 1992 1993 static int msr_switch_exit_handler(union exit_reason exit_reason) 1994 { 1995 if (exit_reason.basic == VMX_VMCALL && vmx_get_test_stage() == 2) { 1996 report(exit_msr_store[0].value == MSR_MAGIC + 1, 1997 "VM exit MSR store"); 1998 report(rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC + 2, 1999 "VM exit MSR load"); 2000 vmx_set_test_stage(3); 2001 entry_msr_load[0].index = MSR_FS_BASE; 2002 return VMX_TEST_RESUME; 2003 } 2004 printf("ERROR %s: unexpected stage=%u or reason=0x%x\n", 2005 __func__, vmx_get_test_stage(), exit_reason.full); 2006 return VMX_TEST_EXIT; 2007 } 2008 2009 static int msr_switch_entry_failure(struct vmentry_result *result) 2010 { 2011 if (result->vm_fail) { 2012 printf("ERROR %s: VM-Fail on %s\n", __func__, result->instr); 2013 return VMX_TEST_EXIT; 2014 } 2015 2016 if (result->exit_reason.failed_vmentry && 2017 result->exit_reason.basic == VMX_FAIL_MSR && 2018 vmx_get_test_stage() == 3) { 2019 report(vmcs_read(EXI_QUALIFICATION) == 1, 2020 "VM entry MSR load: try to load FS_BASE"); 2021 return VMX_TEST_VMEXIT; 2022 } 2023 printf("ERROR %s: unexpected stage=%u or reason=%x\n", 2024 __func__, vmx_get_test_stage(), result->exit_reason.full); 2025 return VMX_TEST_EXIT; 2026 } 2027 2028 static int vmmcall_init(struct vmcs *vmcs) 2029 { 2030 vmcs_write(EXC_BITMAP, 1 << UD_VECTOR); 2031 return VMX_TEST_START; 2032 } 2033 2034 static void vmmcall_main(void) 2035 { 2036 asm volatile( 2037 "mov $0xABCD, %%rax\n\t" 2038 "vmmcall\n\t" 2039 ::: "rax"); 2040 2041 report_fail("VMMCALL"); 2042 } 2043 2044 static int vmmcall_exit_handler(union exit_reason exit_reason) 2045 { 2046 switch (exit_reason.basic) { 2047 case VMX_VMCALL: 2048 printf("here\n"); 2049 report_fail("VMMCALL triggers #UD"); 2050 break; 2051 case VMX_EXC_NMI: 2052 report((vmcs_read(EXI_INTR_INFO) & 0xff) == UD_VECTOR, 2053 "VMMCALL triggers #UD"); 2054 break; 2055 default: 2056 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 2057 print_vmexit_info(exit_reason); 2058 } 2059 2060 return VMX_TEST_VMEXIT; 2061 } 2062 2063 static int disable_rdtscp_init(struct vmcs *vmcs) 2064 { 2065 u32 ctrl_cpu1; 2066 2067 if (ctrl_cpu_rev[0].clr & CPU_SECONDARY) { 2068 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 2069 ctrl_cpu1 &= ~CPU_RDTSCP; 2070 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 2071 } 2072 2073 return VMX_TEST_START; 2074 } 2075 2076 static void disable_rdtscp_ud_handler(struct ex_regs *regs) 2077 { 2078 switch (vmx_get_test_stage()) { 2079 case 0: 2080 report_pass("RDTSCP triggers #UD"); 2081 vmx_inc_test_stage(); 2082 regs->rip += 3; 2083 break; 2084 case 2: 2085 report_pass("RDPID triggers #UD"); 2086 vmx_inc_test_stage(); 2087 regs->rip += 4; 2088 break; 2089 } 2090 return; 2091 2092 } 2093 2094 static void disable_rdtscp_main(void) 2095 { 2096 /* Test that #UD is properly injected in L2. */ 2097 handle_exception(UD_VECTOR, disable_rdtscp_ud_handler); 2098 2099 vmx_set_test_stage(0); 2100 asm volatile("rdtscp" : : : "eax", "ecx", "edx"); 2101 vmcall(); 2102 asm volatile(".byte 0xf3, 0x0f, 0xc7, 0xf8" : : : "eax"); 2103 2104 handle_exception(UD_VECTOR, 0); 2105 vmcall(); 2106 } 2107 2108 static int disable_rdtscp_exit_handler(union exit_reason exit_reason) 2109 { 2110 switch (exit_reason.basic) { 2111 case VMX_VMCALL: 2112 switch (vmx_get_test_stage()) { 2113 case 0: 2114 report_fail("RDTSCP triggers #UD"); 2115 vmx_inc_test_stage(); 2116 /* fallthrough */ 2117 case 1: 2118 vmx_inc_test_stage(); 2119 vmcs_write(GUEST_RIP, vmcs_read(GUEST_RIP) + 3); 2120 return VMX_TEST_RESUME; 2121 case 2: 2122 report_fail("RDPID triggers #UD"); 2123 break; 2124 } 2125 break; 2126 2127 default: 2128 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 2129 print_vmexit_info(exit_reason); 2130 } 2131 return VMX_TEST_VMEXIT; 2132 } 2133 2134 static int int3_init(struct vmcs *vmcs) 2135 { 2136 vmcs_write(EXC_BITMAP, ~0u); 2137 return VMX_TEST_START; 2138 } 2139 2140 static void int3_guest_main(void) 2141 { 2142 asm volatile ("int3"); 2143 } 2144 2145 static int int3_exit_handler(union exit_reason exit_reason) 2146 { 2147 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2148 2149 report(exit_reason.basic == VMX_EXC_NMI && 2150 (intr_info & INTR_INFO_VALID_MASK) && 2151 (intr_info & INTR_INFO_VECTOR_MASK) == BP_VECTOR && 2152 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2153 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION, 2154 "L1 intercepts #BP"); 2155 2156 return VMX_TEST_VMEXIT; 2157 } 2158 2159 static int into_init(struct vmcs *vmcs) 2160 { 2161 vmcs_write(EXC_BITMAP, ~0u); 2162 return VMX_TEST_START; 2163 } 2164 2165 static void into_guest_main(void) 2166 { 2167 struct far_pointer32 fp = { 2168 .offset = (uintptr_t)&&into, 2169 .selector = KERNEL_CS32, 2170 }; 2171 uintptr_t rsp; 2172 2173 asm volatile ("mov %%rsp, %0" : "=r"(rsp)); 2174 2175 if (fp.offset != (uintptr_t)&&into) { 2176 printf("Code address too high.\n"); 2177 return; 2178 } 2179 if ((u32)rsp != rsp) { 2180 printf("Stack address too high.\n"); 2181 return; 2182 } 2183 2184 asm goto ("lcall *%0" : : "m" (fp) : "rax" : into); 2185 return; 2186 into: 2187 asm volatile (".code32;" 2188 "movl $0x7fffffff, %eax;" 2189 "addl %eax, %eax;" 2190 "into;" 2191 "lret;" 2192 ".code64"); 2193 __builtin_unreachable(); 2194 } 2195 2196 static int into_exit_handler(union exit_reason exit_reason) 2197 { 2198 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2199 2200 report(exit_reason.basic == VMX_EXC_NMI && 2201 (intr_info & INTR_INFO_VALID_MASK) && 2202 (intr_info & INTR_INFO_VECTOR_MASK) == OF_VECTOR && 2203 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2204 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION, 2205 "L1 intercepts #OF"); 2206 2207 return VMX_TEST_VMEXIT; 2208 } 2209 2210 static void exit_monitor_from_l2_main(void) 2211 { 2212 printf("Calling exit(0) from l2...\n"); 2213 exit(0); 2214 } 2215 2216 static int exit_monitor_from_l2_handler(union exit_reason exit_reason) 2217 { 2218 report_fail("The guest should have killed the VMM"); 2219 return VMX_TEST_EXIT; 2220 } 2221 2222 static void assert_exit_reason(u64 expected) 2223 { 2224 u64 actual = vmcs_read(EXI_REASON); 2225 2226 TEST_ASSERT_EQ_MSG(expected, actual, "Expected %s, got %s.", 2227 exit_reason_description(expected), 2228 exit_reason_description(actual)); 2229 } 2230 2231 static void skip_exit_insn(void) 2232 { 2233 u64 guest_rip = vmcs_read(GUEST_RIP); 2234 u32 insn_len = vmcs_read(EXI_INST_LEN); 2235 vmcs_write(GUEST_RIP, guest_rip + insn_len); 2236 } 2237 2238 static void skip_exit_vmcall(void) 2239 { 2240 assert_exit_reason(VMX_VMCALL); 2241 skip_exit_insn(); 2242 } 2243 2244 static void v2_null_test_guest(void) 2245 { 2246 } 2247 2248 static void v2_null_test(void) 2249 { 2250 test_set_guest(v2_null_test_guest); 2251 enter_guest(); 2252 report_pass(__func__); 2253 } 2254 2255 static void v2_multiple_entries_test_guest(void) 2256 { 2257 vmx_set_test_stage(1); 2258 vmcall(); 2259 vmx_set_test_stage(2); 2260 } 2261 2262 static void v2_multiple_entries_test(void) 2263 { 2264 test_set_guest(v2_multiple_entries_test_guest); 2265 enter_guest(); 2266 TEST_ASSERT_EQ(vmx_get_test_stage(), 1); 2267 skip_exit_vmcall(); 2268 enter_guest(); 2269 TEST_ASSERT_EQ(vmx_get_test_stage(), 2); 2270 report_pass(__func__); 2271 } 2272 2273 static int fixture_test_data = 1; 2274 2275 static void fixture_test_teardown(void *data) 2276 { 2277 *((int *) data) = 1; 2278 } 2279 2280 static void fixture_test_guest(void) 2281 { 2282 fixture_test_data++; 2283 } 2284 2285 2286 static void fixture_test_setup(void) 2287 { 2288 TEST_ASSERT_EQ_MSG(1, fixture_test_data, 2289 "fixture_test_teardown didn't run?!"); 2290 fixture_test_data = 2; 2291 test_add_teardown(fixture_test_teardown, &fixture_test_data); 2292 test_set_guest(fixture_test_guest); 2293 } 2294 2295 static void fixture_test_case1(void) 2296 { 2297 fixture_test_setup(); 2298 TEST_ASSERT_EQ(2, fixture_test_data); 2299 enter_guest(); 2300 TEST_ASSERT_EQ(3, fixture_test_data); 2301 report_pass(__func__); 2302 } 2303 2304 static void fixture_test_case2(void) 2305 { 2306 fixture_test_setup(); 2307 TEST_ASSERT_EQ(2, fixture_test_data); 2308 enter_guest(); 2309 TEST_ASSERT_EQ(3, fixture_test_data); 2310 report_pass(__func__); 2311 } 2312 2313 enum ept_access_op { 2314 OP_READ, 2315 OP_WRITE, 2316 OP_EXEC, 2317 OP_FLUSH_TLB, 2318 OP_EXIT, 2319 }; 2320 2321 static struct ept_access_test_data { 2322 unsigned long gpa; 2323 unsigned long *gva; 2324 unsigned long hpa; 2325 unsigned long *hva; 2326 enum ept_access_op op; 2327 } ept_access_test_data; 2328 2329 extern unsigned char ret42_start; 2330 extern unsigned char ret42_end; 2331 2332 /* Returns 42. */ 2333 asm( 2334 ".align 64\n" 2335 "ret42_start:\n" 2336 "mov $42, %eax\n" 2337 "ret\n" 2338 "ret42_end:\n" 2339 ); 2340 2341 static void 2342 diagnose_ept_violation_qual(u64 expected, u64 actual) 2343 { 2344 2345 #define DIAGNOSE(flag) \ 2346 do { \ 2347 if ((expected & flag) != (actual & flag)) \ 2348 printf(#flag " %sexpected\n", \ 2349 (expected & flag) ? "" : "un"); \ 2350 } while (0) 2351 2352 DIAGNOSE(EPT_VLT_RD); 2353 DIAGNOSE(EPT_VLT_WR); 2354 DIAGNOSE(EPT_VLT_FETCH); 2355 DIAGNOSE(EPT_VLT_PERM_RD); 2356 DIAGNOSE(EPT_VLT_PERM_WR); 2357 DIAGNOSE(EPT_VLT_PERM_EX); 2358 DIAGNOSE(EPT_VLT_LADDR_VLD); 2359 DIAGNOSE(EPT_VLT_PADDR); 2360 2361 #undef DIAGNOSE 2362 } 2363 2364 static void do_ept_access_op(enum ept_access_op op) 2365 { 2366 ept_access_test_data.op = op; 2367 enter_guest(); 2368 } 2369 2370 /* 2371 * Force the guest to flush its TLB (i.e., flush gva -> gpa mappings). Only 2372 * needed by tests that modify guest PTEs. 2373 */ 2374 static void ept_access_test_guest_flush_tlb(void) 2375 { 2376 do_ept_access_op(OP_FLUSH_TLB); 2377 skip_exit_vmcall(); 2378 } 2379 2380 /* 2381 * Modifies the EPT entry at @level in the mapping of @gpa. First clears the 2382 * bits in @clear then sets the bits in @set. @mkhuge transforms the entry into 2383 * a huge page. 2384 */ 2385 static unsigned long ept_twiddle(unsigned long gpa, bool mkhuge, int level, 2386 unsigned long clear, unsigned long set) 2387 { 2388 struct ept_access_test_data *data = &ept_access_test_data; 2389 unsigned long orig_pte; 2390 unsigned long pte; 2391 2392 /* Screw with the mapping at the requested level. */ 2393 TEST_ASSERT(get_ept_pte(pml4, gpa, level, &orig_pte)); 2394 pte = orig_pte; 2395 if (mkhuge) 2396 pte = (orig_pte & ~EPT_ADDR_MASK) | data->hpa | EPT_LARGE_PAGE; 2397 else 2398 pte = orig_pte; 2399 pte = (pte & ~clear) | set; 2400 set_ept_pte(pml4, gpa, level, pte); 2401 invept(INVEPT_SINGLE, eptp); 2402 2403 return orig_pte; 2404 } 2405 2406 static void ept_untwiddle(unsigned long gpa, int level, unsigned long orig_pte) 2407 { 2408 set_ept_pte(pml4, gpa, level, orig_pte); 2409 invept(INVEPT_SINGLE, eptp); 2410 } 2411 2412 static void do_ept_violation(bool leaf, enum ept_access_op op, 2413 u64 expected_qual, u64 expected_paddr) 2414 { 2415 u64 qual; 2416 2417 /* Try the access and observe the violation. */ 2418 do_ept_access_op(op); 2419 2420 assert_exit_reason(VMX_EPT_VIOLATION); 2421 2422 qual = vmcs_read(EXI_QUALIFICATION); 2423 2424 /* Mask undefined bits (which may later be defined in certain cases). */ 2425 qual &= ~(EPT_VLT_GUEST_USER | EPT_VLT_GUEST_RW | EPT_VLT_GUEST_EX | 2426 EPT_VLT_PERM_USER_EX); 2427 2428 diagnose_ept_violation_qual(expected_qual, qual); 2429 TEST_EXPECT_EQ(expected_qual, qual); 2430 2431 #if 0 2432 /* Disable for now otherwise every test will fail */ 2433 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2434 (unsigned long) ( 2435 op == OP_EXEC ? data->gva + 1 : data->gva)); 2436 #endif 2437 /* 2438 * TODO: tests that probe expected_paddr in pages other than the one at 2439 * the beginning of the 1g region. 2440 */ 2441 TEST_EXPECT_EQ(vmcs_read(INFO_PHYS_ADDR), expected_paddr); 2442 } 2443 2444 static void 2445 ept_violation_at_level_mkhuge(bool mkhuge, int level, unsigned long clear, 2446 unsigned long set, enum ept_access_op op, 2447 u64 expected_qual) 2448 { 2449 struct ept_access_test_data *data = &ept_access_test_data; 2450 unsigned long orig_pte; 2451 2452 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2453 2454 do_ept_violation(level == 1 || mkhuge, op, expected_qual, 2455 op == OP_EXEC ? data->gpa + sizeof(unsigned long) : 2456 data->gpa); 2457 2458 /* Fix the violation and resume the op loop. */ 2459 ept_untwiddle(data->gpa, level, orig_pte); 2460 enter_guest(); 2461 skip_exit_vmcall(); 2462 } 2463 2464 static void 2465 ept_violation_at_level(int level, unsigned long clear, unsigned long set, 2466 enum ept_access_op op, u64 expected_qual) 2467 { 2468 ept_violation_at_level_mkhuge(false, level, clear, set, op, 2469 expected_qual); 2470 if (ept_huge_pages_supported(level)) 2471 ept_violation_at_level_mkhuge(true, level, clear, set, op, 2472 expected_qual); 2473 } 2474 2475 static void ept_violation(unsigned long clear, unsigned long set, 2476 enum ept_access_op op, u64 expected_qual) 2477 { 2478 ept_violation_at_level(1, clear, set, op, expected_qual); 2479 ept_violation_at_level(2, clear, set, op, expected_qual); 2480 ept_violation_at_level(3, clear, set, op, expected_qual); 2481 ept_violation_at_level(4, clear, set, op, expected_qual); 2482 } 2483 2484 static void ept_access_violation(unsigned long access, enum ept_access_op op, 2485 u64 expected_qual) 2486 { 2487 ept_violation(EPT_PRESENT, access, op, 2488 expected_qual | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2489 } 2490 2491 /* 2492 * For translations that don't involve a GVA, that is physical address (paddr) 2493 * accesses, EPT violations don't set the flag EPT_VLT_PADDR. For a typical 2494 * guest memory access, the hardware does GVA -> GPA -> HPA. However, certain 2495 * translations don't involve GVAs, such as when the hardware does the guest 2496 * page table walk. For example, in translating GVA_1 -> GPA_1, the guest MMU 2497 * might try to set an A bit on a guest PTE. If the GPA_2 that the PTE resides 2498 * on isn't present in the EPT, then the EPT violation will be for GPA_2 and 2499 * the EPT_VLT_PADDR bit will be clear in the exit qualification. 2500 * 2501 * Note that paddr violations can also be triggered by loading PAE page tables 2502 * with wonky addresses. We don't test that yet. 2503 * 2504 * This function modifies the EPT entry that maps the GPA that the guest page 2505 * table entry mapping ept_access_test_data.gva resides on. 2506 * 2507 * @ept_access EPT permissions to set. Other permissions are cleared. 2508 * 2509 * @pte_ad Set the A/D bits on the guest PTE accordingly. 2510 * 2511 * @op Guest operation to perform with 2512 * ept_access_test_data.gva. 2513 * 2514 * @expect_violation 2515 * Is a violation expected during the paddr access? 2516 * 2517 * @expected_qual Expected qualification for the EPT violation. 2518 * EPT_VLT_PADDR should be clear. 2519 */ 2520 static void ept_access_paddr(unsigned long ept_access, unsigned long pte_ad, 2521 enum ept_access_op op, bool expect_violation, 2522 u64 expected_qual) 2523 { 2524 struct ept_access_test_data *data = &ept_access_test_data; 2525 unsigned long *ptep; 2526 unsigned long gpa; 2527 unsigned long orig_epte; 2528 unsigned long epte; 2529 int i; 2530 2531 /* Modify the guest PTE mapping data->gva according to @pte_ad. */ 2532 ptep = get_pte_level(current_page_table(), data->gva, /*level=*/1); 2533 TEST_ASSERT(ptep); 2534 TEST_ASSERT_EQ(*ptep & PT_ADDR_MASK, data->gpa); 2535 *ptep = (*ptep & ~PT_AD_MASK) | pte_ad; 2536 ept_access_test_guest_flush_tlb(); 2537 2538 /* 2539 * Now modify the access bits on the EPT entry for the GPA that the 2540 * guest PTE resides on. Note that by modifying a single EPT entry, 2541 * we're potentially affecting 512 guest PTEs. However, we've carefully 2542 * constructed our test such that those other 511 PTEs aren't used by 2543 * the guest: data->gva is at the beginning of a 1G huge page, thus the 2544 * PTE we're modifying is at the beginning of a 4K page and the 2545 * following 511 entires are also under our control (and not touched by 2546 * the guest). 2547 */ 2548 gpa = virt_to_phys(ptep); 2549 TEST_ASSERT_EQ(gpa & ~PAGE_MASK, 0); 2550 /* 2551 * Make sure the guest page table page is mapped with a 4K EPT entry, 2552 * otherwise our level=1 twiddling below will fail. We use the 2553 * identity map (gpa = gpa) since page tables are shared with the host. 2554 */ 2555 install_ept(pml4, gpa, gpa, EPT_PRESENT); 2556 orig_epte = ept_twiddle(gpa, /*mkhuge=*/0, /*level=*/1, 2557 /*clear=*/EPT_PRESENT, /*set=*/ept_access); 2558 2559 if (expect_violation) { 2560 do_ept_violation(/*leaf=*/true, op, 2561 expected_qual | EPT_VLT_LADDR_VLD, gpa); 2562 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2563 do_ept_access_op(op); 2564 } else { 2565 do_ept_access_op(op); 2566 if (ept_ad_enabled()) { 2567 for (i = EPT_PAGE_LEVEL; i > 0; i--) { 2568 TEST_ASSERT(get_ept_pte(pml4, gpa, i, &epte)); 2569 TEST_ASSERT(epte & EPT_ACCESS_FLAG); 2570 if (i == 1) 2571 TEST_ASSERT(epte & EPT_DIRTY_FLAG); 2572 else 2573 TEST_ASSERT_EQ(epte & EPT_DIRTY_FLAG, 0); 2574 } 2575 } 2576 2577 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2578 } 2579 2580 TEST_ASSERT(*ptep & PT_ACCESSED_MASK); 2581 if ((pte_ad & PT_DIRTY_MASK) || op == OP_WRITE) 2582 TEST_ASSERT(*ptep & PT_DIRTY_MASK); 2583 2584 skip_exit_vmcall(); 2585 } 2586 2587 static void ept_access_allowed_paddr(unsigned long ept_access, 2588 unsigned long pte_ad, 2589 enum ept_access_op op) 2590 { 2591 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/false, 2592 /*expected_qual=*/-1); 2593 } 2594 2595 static void ept_access_violation_paddr(unsigned long ept_access, 2596 unsigned long pte_ad, 2597 enum ept_access_op op, 2598 u64 expected_qual) 2599 { 2600 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/true, 2601 expected_qual); 2602 } 2603 2604 2605 static void ept_allowed_at_level_mkhuge(bool mkhuge, int level, 2606 unsigned long clear, 2607 unsigned long set, 2608 enum ept_access_op op) 2609 { 2610 struct ept_access_test_data *data = &ept_access_test_data; 2611 unsigned long orig_pte; 2612 2613 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2614 2615 /* No violation. Should proceed to vmcall. */ 2616 do_ept_access_op(op); 2617 skip_exit_vmcall(); 2618 2619 ept_untwiddle(data->gpa, level, orig_pte); 2620 } 2621 2622 static void ept_allowed_at_level(int level, unsigned long clear, 2623 unsigned long set, enum ept_access_op op) 2624 { 2625 ept_allowed_at_level_mkhuge(false, level, clear, set, op); 2626 if (ept_huge_pages_supported(level)) 2627 ept_allowed_at_level_mkhuge(true, level, clear, set, op); 2628 } 2629 2630 static void ept_allowed(unsigned long clear, unsigned long set, 2631 enum ept_access_op op) 2632 { 2633 ept_allowed_at_level(1, clear, set, op); 2634 ept_allowed_at_level(2, clear, set, op); 2635 ept_allowed_at_level(3, clear, set, op); 2636 ept_allowed_at_level(4, clear, set, op); 2637 } 2638 2639 static void ept_ignored_bit(int bit) 2640 { 2641 /* Set the bit. */ 2642 ept_allowed(0, 1ul << bit, OP_READ); 2643 ept_allowed(0, 1ul << bit, OP_WRITE); 2644 ept_allowed(0, 1ul << bit, OP_EXEC); 2645 2646 /* Clear the bit. */ 2647 ept_allowed(1ul << bit, 0, OP_READ); 2648 ept_allowed(1ul << bit, 0, OP_WRITE); 2649 ept_allowed(1ul << bit, 0, OP_EXEC); 2650 } 2651 2652 static void ept_access_allowed(unsigned long access, enum ept_access_op op) 2653 { 2654 ept_allowed(EPT_PRESENT, access, op); 2655 } 2656 2657 2658 static void ept_misconfig_at_level_mkhuge_op(bool mkhuge, int level, 2659 unsigned long clear, 2660 unsigned long set, 2661 enum ept_access_op op) 2662 { 2663 struct ept_access_test_data *data = &ept_access_test_data; 2664 unsigned long orig_pte; 2665 2666 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2667 2668 do_ept_access_op(op); 2669 assert_exit_reason(VMX_EPT_MISCONFIG); 2670 2671 /* Intel 27.2.1, "For all other VM exits, this field is cleared." */ 2672 #if 0 2673 /* broken: */ 2674 TEST_EXPECT_EQ_MSG(vmcs_read(EXI_QUALIFICATION), 0); 2675 #endif 2676 #if 0 2677 /* 2678 * broken: 2679 * According to description of exit qual for EPT violation, 2680 * EPT_VLT_LADDR_VLD indicates if GUEST_LINEAR_ADDRESS is valid. 2681 * However, I can't find anything that says GUEST_LINEAR_ADDRESS ought 2682 * to be set for msiconfig. 2683 */ 2684 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2685 (unsigned long) ( 2686 op == OP_EXEC ? data->gva + 1 : data->gva)); 2687 #endif 2688 2689 /* Fix the violation and resume the op loop. */ 2690 ept_untwiddle(data->gpa, level, orig_pte); 2691 enter_guest(); 2692 skip_exit_vmcall(); 2693 } 2694 2695 static void ept_misconfig_at_level_mkhuge(bool mkhuge, int level, 2696 unsigned long clear, 2697 unsigned long set) 2698 { 2699 /* The op shouldn't matter (read, write, exec), so try them all! */ 2700 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_READ); 2701 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_WRITE); 2702 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_EXEC); 2703 } 2704 2705 static void ept_misconfig_at_level(int level, unsigned long clear, 2706 unsigned long set) 2707 { 2708 ept_misconfig_at_level_mkhuge(false, level, clear, set); 2709 if (ept_huge_pages_supported(level)) 2710 ept_misconfig_at_level_mkhuge(true, level, clear, set); 2711 } 2712 2713 static void ept_misconfig(unsigned long clear, unsigned long set) 2714 { 2715 ept_misconfig_at_level(1, clear, set); 2716 ept_misconfig_at_level(2, clear, set); 2717 ept_misconfig_at_level(3, clear, set); 2718 ept_misconfig_at_level(4, clear, set); 2719 } 2720 2721 static void ept_access_misconfig(unsigned long access) 2722 { 2723 ept_misconfig(EPT_PRESENT, access); 2724 } 2725 2726 static void ept_reserved_bit_at_level_nohuge(int level, int bit) 2727 { 2728 /* Setting the bit causes a misconfig. */ 2729 ept_misconfig_at_level_mkhuge(false, level, 0, 1ul << bit); 2730 2731 /* Making the entry non-present turns reserved bits into ignored. */ 2732 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2733 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2734 } 2735 2736 static void ept_reserved_bit_at_level_huge(int level, int bit) 2737 { 2738 /* Setting the bit causes a misconfig. */ 2739 ept_misconfig_at_level_mkhuge(true, level, 0, 1ul << bit); 2740 2741 /* Making the entry non-present turns reserved bits into ignored. */ 2742 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2743 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2744 } 2745 2746 static void ept_reserved_bit_at_level(int level, int bit) 2747 { 2748 /* Setting the bit causes a misconfig. */ 2749 ept_misconfig_at_level(level, 0, 1ul << bit); 2750 2751 /* Making the entry non-present turns reserved bits into ignored. */ 2752 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2753 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2754 } 2755 2756 static void ept_reserved_bit(int bit) 2757 { 2758 ept_reserved_bit_at_level(1, bit); 2759 ept_reserved_bit_at_level(2, bit); 2760 ept_reserved_bit_at_level(3, bit); 2761 ept_reserved_bit_at_level(4, bit); 2762 } 2763 2764 #define PAGE_2M_ORDER 9 2765 #define PAGE_1G_ORDER 18 2766 2767 static void *get_1g_page(void) 2768 { 2769 static void *alloc; 2770 2771 if (!alloc) 2772 alloc = alloc_pages(PAGE_1G_ORDER); 2773 return alloc; 2774 } 2775 2776 static void ept_access_test_teardown(void *unused) 2777 { 2778 /* Exit the guest cleanly. */ 2779 do_ept_access_op(OP_EXIT); 2780 } 2781 2782 static void ept_access_test_guest(void) 2783 { 2784 struct ept_access_test_data *data = &ept_access_test_data; 2785 int (*code)(void) = (int (*)(void)) &data->gva[1]; 2786 2787 while (true) { 2788 switch (data->op) { 2789 case OP_READ: 2790 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_1); 2791 break; 2792 case OP_WRITE: 2793 *data->gva = MAGIC_VAL_2; 2794 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_2); 2795 *data->gva = MAGIC_VAL_1; 2796 break; 2797 case OP_EXEC: 2798 TEST_ASSERT_EQ(42, code()); 2799 break; 2800 case OP_FLUSH_TLB: 2801 write_cr3(read_cr3()); 2802 break; 2803 case OP_EXIT: 2804 return; 2805 default: 2806 TEST_ASSERT_MSG(false, "Unknown op %d", data->op); 2807 } 2808 vmcall(); 2809 } 2810 } 2811 2812 static void ept_access_test_setup(void) 2813 { 2814 struct ept_access_test_data *data = &ept_access_test_data; 2815 unsigned long npages = 1ul << PAGE_1G_ORDER; 2816 unsigned long size = npages * PAGE_SIZE; 2817 unsigned long *page_table = current_page_table(); 2818 unsigned long pte; 2819 2820 if (setup_ept(false)) 2821 test_skip("EPT not supported"); 2822 2823 /* We use data->gpa = 1 << 39 so that test data has a separate pml4 entry */ 2824 if (cpuid_maxphyaddr() < 40) 2825 test_skip("Test needs MAXPHYADDR >= 40"); 2826 2827 test_set_guest(ept_access_test_guest); 2828 test_add_teardown(ept_access_test_teardown, NULL); 2829 2830 data->hva = get_1g_page(); 2831 TEST_ASSERT(data->hva); 2832 data->hpa = virt_to_phys(data->hva); 2833 2834 data->gpa = 1ul << 39; 2835 data->gva = (void *) ALIGN((unsigned long) alloc_vpages(npages * 2), 2836 size); 2837 TEST_ASSERT(!any_present_pages(page_table, data->gva, size)); 2838 install_pages(page_table, data->gpa, size, data->gva); 2839 2840 /* 2841 * Make sure nothing's mapped here so the tests that screw with the 2842 * pml4 entry don't inadvertently break something. 2843 */ 2844 TEST_ASSERT(get_ept_pte(pml4, data->gpa, 4, &pte) && pte == 0); 2845 TEST_ASSERT(get_ept_pte(pml4, data->gpa + size - 1, 4, &pte) && pte == 0); 2846 install_ept(pml4, data->hpa, data->gpa, EPT_PRESENT); 2847 2848 data->hva[0] = MAGIC_VAL_1; 2849 memcpy(&data->hva[1], &ret42_start, &ret42_end - &ret42_start); 2850 } 2851 2852 static void ept_access_test_not_present(void) 2853 { 2854 ept_access_test_setup(); 2855 /* --- */ 2856 ept_access_violation(0, OP_READ, EPT_VLT_RD); 2857 ept_access_violation(0, OP_WRITE, EPT_VLT_WR); 2858 ept_access_violation(0, OP_EXEC, EPT_VLT_FETCH); 2859 } 2860 2861 static void ept_access_test_read_only(void) 2862 { 2863 ept_access_test_setup(); 2864 2865 /* r-- */ 2866 ept_access_allowed(EPT_RA, OP_READ); 2867 ept_access_violation(EPT_RA, OP_WRITE, EPT_VLT_WR | EPT_VLT_PERM_RD); 2868 ept_access_violation(EPT_RA, OP_EXEC, EPT_VLT_FETCH | EPT_VLT_PERM_RD); 2869 } 2870 2871 static void ept_access_test_write_only(void) 2872 { 2873 ept_access_test_setup(); 2874 /* -w- */ 2875 ept_access_misconfig(EPT_WA); 2876 } 2877 2878 static void ept_access_test_read_write(void) 2879 { 2880 ept_access_test_setup(); 2881 /* rw- */ 2882 ept_access_allowed(EPT_RA | EPT_WA, OP_READ); 2883 ept_access_allowed(EPT_RA | EPT_WA, OP_WRITE); 2884 ept_access_violation(EPT_RA | EPT_WA, OP_EXEC, 2885 EPT_VLT_FETCH | EPT_VLT_PERM_RD | EPT_VLT_PERM_WR); 2886 } 2887 2888 2889 static void ept_access_test_execute_only(void) 2890 { 2891 ept_access_test_setup(); 2892 /* --x */ 2893 if (ept_execute_only_supported()) { 2894 ept_access_violation(EPT_EA, OP_READ, 2895 EPT_VLT_RD | EPT_VLT_PERM_EX); 2896 ept_access_violation(EPT_EA, OP_WRITE, 2897 EPT_VLT_WR | EPT_VLT_PERM_EX); 2898 ept_access_allowed(EPT_EA, OP_EXEC); 2899 } else { 2900 ept_access_misconfig(EPT_EA); 2901 } 2902 } 2903 2904 static void ept_access_test_read_execute(void) 2905 { 2906 ept_access_test_setup(); 2907 /* r-x */ 2908 ept_access_allowed(EPT_RA | EPT_EA, OP_READ); 2909 ept_access_violation(EPT_RA | EPT_EA, OP_WRITE, 2910 EPT_VLT_WR | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX); 2911 ept_access_allowed(EPT_RA | EPT_EA, OP_EXEC); 2912 } 2913 2914 static void ept_access_test_write_execute(void) 2915 { 2916 ept_access_test_setup(); 2917 /* -wx */ 2918 ept_access_misconfig(EPT_WA | EPT_EA); 2919 } 2920 2921 static void ept_access_test_read_write_execute(void) 2922 { 2923 ept_access_test_setup(); 2924 /* rwx */ 2925 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_READ); 2926 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_WRITE); 2927 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_EXEC); 2928 } 2929 2930 static void ept_access_test_reserved_bits(void) 2931 { 2932 int i; 2933 int maxphyaddr; 2934 2935 ept_access_test_setup(); 2936 2937 /* Reserved bits above maxphyaddr. */ 2938 maxphyaddr = cpuid_maxphyaddr(); 2939 for (i = maxphyaddr; i <= 51; i++) { 2940 report_prefix_pushf("reserved_bit=%d", i); 2941 ept_reserved_bit(i); 2942 report_prefix_pop(); 2943 } 2944 2945 /* Level-specific reserved bits. */ 2946 ept_reserved_bit_at_level_nohuge(2, 3); 2947 ept_reserved_bit_at_level_nohuge(2, 4); 2948 ept_reserved_bit_at_level_nohuge(2, 5); 2949 ept_reserved_bit_at_level_nohuge(2, 6); 2950 /* 2M alignment. */ 2951 for (i = 12; i < 20; i++) { 2952 report_prefix_pushf("reserved_bit=%d", i); 2953 ept_reserved_bit_at_level_huge(2, i); 2954 report_prefix_pop(); 2955 } 2956 ept_reserved_bit_at_level_nohuge(3, 3); 2957 ept_reserved_bit_at_level_nohuge(3, 4); 2958 ept_reserved_bit_at_level_nohuge(3, 5); 2959 ept_reserved_bit_at_level_nohuge(3, 6); 2960 /* 1G alignment. */ 2961 for (i = 12; i < 29; i++) { 2962 report_prefix_pushf("reserved_bit=%d", i); 2963 ept_reserved_bit_at_level_huge(3, i); 2964 report_prefix_pop(); 2965 } 2966 ept_reserved_bit_at_level(4, 3); 2967 ept_reserved_bit_at_level(4, 4); 2968 ept_reserved_bit_at_level(4, 5); 2969 ept_reserved_bit_at_level(4, 6); 2970 ept_reserved_bit_at_level(4, 7); 2971 } 2972 2973 static void ept_access_test_ignored_bits(void) 2974 { 2975 ept_access_test_setup(); 2976 /* 2977 * Bits ignored at every level. Bits 8 and 9 (A and D) are ignored as 2978 * far as translation is concerned even if AD bits are enabled in the 2979 * EPTP. Bit 63 is ignored because "EPT-violation #VE" VM-execution 2980 * control is 0. 2981 */ 2982 ept_ignored_bit(8); 2983 ept_ignored_bit(9); 2984 ept_ignored_bit(10); 2985 ept_ignored_bit(11); 2986 ept_ignored_bit(52); 2987 ept_ignored_bit(53); 2988 ept_ignored_bit(54); 2989 ept_ignored_bit(55); 2990 ept_ignored_bit(56); 2991 ept_ignored_bit(57); 2992 ept_ignored_bit(58); 2993 ept_ignored_bit(59); 2994 ept_ignored_bit(60); 2995 ept_ignored_bit(61); 2996 ept_ignored_bit(62); 2997 ept_ignored_bit(63); 2998 } 2999 3000 static void ept_access_test_paddr_not_present_ad_disabled(void) 3001 { 3002 ept_access_test_setup(); 3003 ept_disable_ad_bits(); 3004 3005 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, EPT_VLT_RD); 3006 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, EPT_VLT_RD); 3007 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, EPT_VLT_RD); 3008 } 3009 3010 static void ept_access_test_paddr_not_present_ad_enabled(void) 3011 { 3012 u64 qual = EPT_VLT_RD | EPT_VLT_WR; 3013 3014 ept_access_test_setup(); 3015 ept_enable_ad_bits_or_skip_test(); 3016 3017 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, qual); 3018 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, qual); 3019 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, qual); 3020 } 3021 3022 static void ept_access_test_paddr_read_only_ad_disabled(void) 3023 { 3024 /* 3025 * When EPT AD bits are disabled, all accesses to guest paging 3026 * structures are reported separately as a read and (after 3027 * translation of the GPA to host physical address) a read+write 3028 * if the A/D bits have to be set. 3029 */ 3030 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 3031 3032 ept_access_test_setup(); 3033 ept_disable_ad_bits(); 3034 3035 /* Can't update A bit, so all accesses fail. */ 3036 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 3037 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 3038 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 3039 /* AD bits disabled, so only writes try to update the D bit. */ 3040 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ); 3041 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 3042 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC); 3043 /* Both A and D already set, so read-only is OK. */ 3044 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_READ); 3045 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_WRITE); 3046 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_EXEC); 3047 } 3048 3049 static void ept_access_test_paddr_read_only_ad_enabled(void) 3050 { 3051 /* 3052 * When EPT AD bits are enabled, all accesses to guest paging 3053 * structures are considered writes as far as EPT translation 3054 * is concerned. 3055 */ 3056 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 3057 3058 ept_access_test_setup(); 3059 ept_enable_ad_bits_or_skip_test(); 3060 3061 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 3062 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 3063 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 3064 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ, qual); 3065 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 3066 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC, qual); 3067 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_READ, qual); 3068 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_WRITE, qual); 3069 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_EXEC, qual); 3070 } 3071 3072 static void ept_access_test_paddr_read_write(void) 3073 { 3074 ept_access_test_setup(); 3075 /* Read-write access to paging structure. */ 3076 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_READ); 3077 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_WRITE); 3078 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_EXEC); 3079 } 3080 3081 static void ept_access_test_paddr_read_write_execute(void) 3082 { 3083 ept_access_test_setup(); 3084 /* RWX access to paging structure. */ 3085 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_READ); 3086 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_WRITE); 3087 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_EXEC); 3088 } 3089 3090 static void ept_access_test_paddr_read_execute_ad_disabled(void) 3091 { 3092 /* 3093 * When EPT AD bits are disabled, all accesses to guest paging 3094 * structures are reported separately as a read and (after 3095 * translation of the GPA to host physical address) a read+write 3096 * if the A/D bits have to be set. 3097 */ 3098 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3099 3100 ept_access_test_setup(); 3101 ept_disable_ad_bits(); 3102 3103 /* Can't update A bit, so all accesses fail. */ 3104 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3105 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3106 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3107 /* AD bits disabled, so only writes try to update the D bit. */ 3108 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ); 3109 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3110 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC); 3111 /* Both A and D already set, so read-only is OK. */ 3112 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ); 3113 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE); 3114 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC); 3115 } 3116 3117 static void ept_access_test_paddr_read_execute_ad_enabled(void) 3118 { 3119 /* 3120 * When EPT AD bits are enabled, all accesses to guest paging 3121 * structures are considered writes as far as EPT translation 3122 * is concerned. 3123 */ 3124 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3125 3126 ept_access_test_setup(); 3127 ept_enable_ad_bits_or_skip_test(); 3128 3129 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3130 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3131 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3132 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ, qual); 3133 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3134 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC, qual); 3135 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ, qual); 3136 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE, qual); 3137 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC, qual); 3138 } 3139 3140 static void ept_access_test_paddr_not_present_page_fault(void) 3141 { 3142 ept_access_test_setup(); 3143 /* 3144 * TODO: test no EPT violation as long as guest PF occurs. e.g., GPA is 3145 * page is read-only in EPT but GVA is also mapped read only in PT. 3146 * Thus guest page fault before host takes EPT violation for trying to 3147 * update A bit. 3148 */ 3149 } 3150 3151 static void ept_access_test_force_2m_page(void) 3152 { 3153 ept_access_test_setup(); 3154 3155 TEST_ASSERT_EQ(ept_2m_supported(), true); 3156 ept_allowed_at_level_mkhuge(true, 2, 0, 0, OP_READ); 3157 ept_violation_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_RA, OP_WRITE, 3158 EPT_VLT_WR | EPT_VLT_PERM_RD | 3159 EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 3160 ept_misconfig_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_WA); 3161 } 3162 3163 static bool invvpid_valid(u64 type, u64 vpid, u64 gla) 3164 { 3165 if (!is_invvpid_type_supported(type)) 3166 return false; 3167 3168 if (vpid >> 16) 3169 return false; 3170 3171 if (type != INVVPID_ALL && !vpid) 3172 return false; 3173 3174 if (type == INVVPID_ADDR && !is_canonical(gla)) 3175 return false; 3176 3177 return true; 3178 } 3179 3180 static void try_invvpid(u64 type, u64 vpid, u64 gla) 3181 { 3182 int rc; 3183 bool valid = invvpid_valid(type, vpid, gla); 3184 u64 expected = valid ? VMXERR_UNSUPPORTED_VMCS_COMPONENT 3185 : VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID; 3186 /* 3187 * Set VMX_INST_ERROR to VMXERR_UNVALID_VMCS_COMPONENT, so 3188 * that we can tell if it is updated by INVVPID. 3189 */ 3190 vmcs_read(~0); 3191 rc = __invvpid(type, vpid, gla); 3192 report(!rc == valid, "INVVPID type %ld VPID %lx GLA %lx %s", type, 3193 vpid, gla, 3194 valid ? "passes" : "fails"); 3195 report(vmcs_read(VMX_INST_ERROR) == expected, 3196 "After %s INVVPID, VMX_INST_ERR is %ld (actual %ld)", 3197 rc ? "failed" : "successful", 3198 expected, vmcs_read(VMX_INST_ERROR)); 3199 } 3200 3201 static inline unsigned long get_first_supported_invvpid_type(void) 3202 { 3203 u64 type = ffs(ept_vpid.val >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 3204 3205 __TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 3206 return type; 3207 } 3208 3209 static void ds_invvpid(void *data) 3210 { 3211 asm volatile("invvpid %0, %1" 3212 : 3213 : "m"(*(struct invvpid_operand *)data), 3214 "r"(get_first_supported_invvpid_type())); 3215 } 3216 3217 /* 3218 * The SS override is ignored in 64-bit mode, so we use an addressing 3219 * mode with %rsp as the base register to generate an implicit SS 3220 * reference. 3221 */ 3222 static void ss_invvpid(void *data) 3223 { 3224 asm volatile("sub %%rsp,%0; invvpid (%%rsp,%0,1), %1" 3225 : "+r"(data) 3226 : "r"(get_first_supported_invvpid_type())); 3227 } 3228 3229 static void invvpid_test_gp(void) 3230 { 3231 bool fault; 3232 3233 fault = test_for_exception(GP_VECTOR, &ds_invvpid, 3234 (void *)NONCANONICAL); 3235 report(fault, "INVVPID with non-canonical DS operand raises #GP"); 3236 } 3237 3238 static void invvpid_test_ss(void) 3239 { 3240 bool fault; 3241 3242 fault = test_for_exception(SS_VECTOR, &ss_invvpid, 3243 (void *)NONCANONICAL); 3244 report(fault, "INVVPID with non-canonical SS operand raises #SS"); 3245 } 3246 3247 static void invvpid_test_pf(void) 3248 { 3249 void *vpage = alloc_vpage(); 3250 bool fault; 3251 3252 fault = test_for_exception(PF_VECTOR, &ds_invvpid, vpage); 3253 report(fault, "INVVPID with unmapped operand raises #PF"); 3254 } 3255 3256 static void try_compat_invvpid(void *unused) 3257 { 3258 struct far_pointer32 fp = { 3259 .offset = (uintptr_t)&&invvpid, 3260 .selector = KERNEL_CS32, 3261 }; 3262 uintptr_t rsp; 3263 3264 asm volatile ("mov %%rsp, %0" : "=r"(rsp)); 3265 3266 TEST_ASSERT_MSG(fp.offset == (uintptr_t)&&invvpid, 3267 "Code address too high."); 3268 TEST_ASSERT_MSG(rsp == (u32)rsp, "Stack address too high."); 3269 3270 asm goto ("lcall *%0" : : "m" (fp) : "rax" : invvpid); 3271 return; 3272 invvpid: 3273 asm volatile (".code32;" 3274 "invvpid (%eax), %eax;" 3275 "lret;" 3276 ".code64"); 3277 __builtin_unreachable(); 3278 } 3279 3280 static void invvpid_test_compatibility_mode(void) 3281 { 3282 bool fault; 3283 3284 fault = test_for_exception(UD_VECTOR, &try_compat_invvpid, NULL); 3285 report(fault, "Compatibility mode INVVPID raises #UD"); 3286 } 3287 3288 static void invvpid_test_not_in_vmx_operation(void) 3289 { 3290 bool fault; 3291 3292 TEST_ASSERT(!vmx_off()); 3293 fault = test_for_exception(UD_VECTOR, &ds_invvpid, NULL); 3294 report(fault, "INVVPID outside of VMX operation raises #UD"); 3295 TEST_ASSERT(!vmx_on()); 3296 } 3297 3298 /* 3299 * This does not test real-address mode, virtual-8086 mode, protected mode, 3300 * or CPL > 0. 3301 */ 3302 static void invvpid_test(void) 3303 { 3304 int i; 3305 unsigned types = 0; 3306 unsigned type; 3307 3308 if (!is_vpid_supported()) 3309 test_skip("VPID not supported"); 3310 3311 if (!is_invvpid_supported()) 3312 test_skip("INVVPID not supported.\n"); 3313 3314 if (is_invvpid_type_supported(INVVPID_ADDR)) 3315 types |= 1u << INVVPID_ADDR; 3316 if (is_invvpid_type_supported(INVVPID_CONTEXT_GLOBAL)) 3317 types |= 1u << INVVPID_CONTEXT_GLOBAL; 3318 if (is_invvpid_type_supported(INVVPID_ALL)) 3319 types |= 1u << INVVPID_ALL; 3320 if (is_invvpid_type_supported(INVVPID_CONTEXT_LOCAL)) 3321 types |= 1u << INVVPID_CONTEXT_LOCAL; 3322 3323 if (!types) 3324 test_skip("No INVVPID types supported.\n"); 3325 3326 for (i = -127; i < 128; i++) 3327 try_invvpid(i, 0xffff, 0); 3328 3329 /* 3330 * VPID must not be more than 16 bits. 3331 */ 3332 for (i = 0; i < 64; i++) 3333 for (type = 0; type < 4; type++) 3334 if (types & (1u << type)) 3335 try_invvpid(type, 1ul << i, 0); 3336 3337 /* 3338 * VPID must not be zero, except for "all contexts." 3339 */ 3340 for (type = 0; type < 4; type++) 3341 if (types & (1u << type)) 3342 try_invvpid(type, 0, 0); 3343 3344 /* 3345 * The gla operand is only validated for single-address INVVPID. 3346 */ 3347 if (types & (1u << INVVPID_ADDR)) 3348 try_invvpid(INVVPID_ADDR, 0xffff, NONCANONICAL); 3349 3350 invvpid_test_gp(); 3351 invvpid_test_ss(); 3352 invvpid_test_pf(); 3353 invvpid_test_compatibility_mode(); 3354 invvpid_test_not_in_vmx_operation(); 3355 } 3356 3357 /* 3358 * Test for early VMLAUNCH failure. Returns true if VMLAUNCH makes it 3359 * at least as far as the guest-state checks. Returns false if the 3360 * VMLAUNCH fails early and execution falls through to the next 3361 * instruction. 3362 */ 3363 static bool vmlaunch_succeeds(void) 3364 { 3365 u32 exit_reason; 3366 3367 /* 3368 * Indirectly set VMX_INST_ERR to 12 ("VMREAD/VMWRITE from/to 3369 * unsupported VMCS component"). The caller can then check 3370 * to see if a failed VM-entry sets VMX_INST_ERR as expected. 3371 */ 3372 vmcs_write(~0u, 0); 3373 3374 vmcs_write(HOST_RIP, (uintptr_t)&&success); 3375 __asm__ __volatile__ goto ("vmwrite %%rsp, %0; vmlaunch" 3376 : 3377 : "r" ((u64)HOST_RSP) 3378 : "cc", "memory" 3379 : success); 3380 return false; 3381 success: 3382 exit_reason = vmcs_read(EXI_REASON); 3383 TEST_ASSERT(exit_reason == (VMX_FAIL_STATE | VMX_ENTRY_FAILURE) || 3384 exit_reason == (VMX_FAIL_MSR | VMX_ENTRY_FAILURE)); 3385 return true; 3386 } 3387 3388 /* 3389 * Try to launch the current VMCS. 3390 */ 3391 static void test_vmx_vmlaunch(u32 xerror) 3392 { 3393 bool success = vmlaunch_succeeds(); 3394 u32 vmx_inst_err; 3395 3396 report(success == !xerror, "vmlaunch %s", 3397 !xerror ? "succeeds" : "fails"); 3398 if (!success && xerror) { 3399 vmx_inst_err = vmcs_read(VMX_INST_ERROR); 3400 report(vmx_inst_err == xerror, 3401 "VMX inst error is %d (actual %d)", xerror, 3402 vmx_inst_err); 3403 } 3404 } 3405 3406 /* 3407 * Try to launch the current VMCS, and expect one of two possible 3408 * errors (or success) codes. 3409 */ 3410 static void test_vmx_vmlaunch2(u32 xerror1, u32 xerror2) 3411 { 3412 bool success = vmlaunch_succeeds(); 3413 u32 vmx_inst_err; 3414 3415 if (!xerror1 == !xerror2) 3416 report(success == !xerror1, "vmlaunch %s", 3417 !xerror1 ? "succeeds" : "fails"); 3418 3419 if (!success && (xerror1 || xerror2)) { 3420 vmx_inst_err = vmcs_read(VMX_INST_ERROR); 3421 report(vmx_inst_err == xerror1 || vmx_inst_err == xerror2, 3422 "VMX inst error is %d or %d (actual %d)", xerror1, 3423 xerror2, vmx_inst_err); 3424 } 3425 } 3426 3427 static void test_vmx_invalid_controls(void) 3428 { 3429 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_CONTROL_FIELD); 3430 } 3431 3432 static void test_vmx_valid_controls(void) 3433 { 3434 test_vmx_vmlaunch(0); 3435 } 3436 3437 /* 3438 * Test a particular value of a VM-execution control bit, if the value 3439 * is required or if the value is zero. 3440 */ 3441 static void test_rsvd_ctl_bit_value(const char *name, union vmx_ctrl_msr msr, 3442 enum Encoding encoding, unsigned bit, 3443 unsigned val) 3444 { 3445 u32 mask = 1u << bit; 3446 bool expected; 3447 u32 controls; 3448 3449 if (msr.set & mask) 3450 TEST_ASSERT(msr.clr & mask); 3451 3452 /* 3453 * We can't arbitrarily turn on a control bit, because it may 3454 * introduce dependencies on other VMCS fields. So, we only 3455 * test turning on bits that have a required setting. 3456 */ 3457 if (val && (msr.clr & mask) && !(msr.set & mask)) 3458 return; 3459 3460 report_prefix_pushf("%s %s bit %d", 3461 val ? "Set" : "Clear", name, bit); 3462 3463 controls = vmcs_read(encoding); 3464 if (val) { 3465 vmcs_write(encoding, msr.set | mask); 3466 expected = (msr.clr & mask); 3467 } else { 3468 vmcs_write(encoding, msr.set & ~mask); 3469 expected = !(msr.set & mask); 3470 } 3471 if (expected) 3472 test_vmx_valid_controls(); 3473 else 3474 test_vmx_invalid_controls(); 3475 vmcs_write(encoding, controls); 3476 report_prefix_pop(); 3477 } 3478 3479 /* 3480 * Test reserved values of a VM-execution control bit, based on the 3481 * allowed bit settings from the corresponding VMX capability MSR. 3482 */ 3483 static void test_rsvd_ctl_bit(const char *name, union vmx_ctrl_msr msr, 3484 enum Encoding encoding, unsigned bit) 3485 { 3486 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 0); 3487 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 1); 3488 } 3489 3490 /* 3491 * Reserved bits in the pin-based VM-execution controls must be set 3492 * properly. Software may consult the VMX capability MSRs to determine 3493 * the proper settings. 3494 * [Intel SDM] 3495 */ 3496 static void test_pin_based_ctls(void) 3497 { 3498 unsigned bit; 3499 3500 printf("%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PIN" : 3501 "MSR_IA32_VMX_PINBASED_CTLS", ctrl_pin_rev.val); 3502 for (bit = 0; bit < 32; bit++) 3503 test_rsvd_ctl_bit("pin-based controls", 3504 ctrl_pin_rev, PIN_CONTROLS, bit); 3505 } 3506 3507 /* 3508 * Reserved bits in the primary processor-based VM-execution controls 3509 * must be set properly. Software may consult the VMX capability MSRs 3510 * to determine the proper settings. 3511 * [Intel SDM] 3512 */ 3513 static void test_primary_processor_based_ctls(void) 3514 { 3515 unsigned bit; 3516 3517 printf("\n%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PROC" : 3518 "MSR_IA32_VMX_PROCBASED_CTLS", ctrl_cpu_rev[0].val); 3519 for (bit = 0; bit < 32; bit++) 3520 test_rsvd_ctl_bit("primary processor-based controls", 3521 ctrl_cpu_rev[0], CPU_EXEC_CTRL0, bit); 3522 } 3523 3524 /* 3525 * If the "activate secondary controls" primary processor-based 3526 * VM-execution control is 1, reserved bits in the secondary 3527 * processor-based VM-execution controls must be cleared. Software may 3528 * consult the VMX capability MSRs to determine which bits are 3529 * reserved. 3530 * If the "activate secondary controls" primary processor-based 3531 * VM-execution control is 0 (or if the processor does not support the 3532 * 1-setting of that control), no checks are performed on the 3533 * secondary processor-based VM-execution controls. 3534 * [Intel SDM] 3535 */ 3536 static void test_secondary_processor_based_ctls(void) 3537 { 3538 u32 primary; 3539 u32 secondary; 3540 unsigned bit; 3541 3542 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) 3543 return; 3544 3545 primary = vmcs_read(CPU_EXEC_CTRL0); 3546 secondary = vmcs_read(CPU_EXEC_CTRL1); 3547 3548 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3549 printf("\nMSR_IA32_VMX_PROCBASED_CTLS2: %lx\n", ctrl_cpu_rev[1].val); 3550 for (bit = 0; bit < 32; bit++) 3551 test_rsvd_ctl_bit("secondary processor-based controls", 3552 ctrl_cpu_rev[1], CPU_EXEC_CTRL1, bit); 3553 3554 /* 3555 * When the "activate secondary controls" VM-execution control 3556 * is clear, there are no checks on the secondary controls. 3557 */ 3558 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3559 vmcs_write(CPU_EXEC_CTRL1, ~0); 3560 report(vmlaunch_succeeds(), 3561 "Secondary processor-based controls ignored"); 3562 vmcs_write(CPU_EXEC_CTRL1, secondary); 3563 vmcs_write(CPU_EXEC_CTRL0, primary); 3564 } 3565 3566 static void try_cr3_target_count(unsigned i, unsigned max) 3567 { 3568 report_prefix_pushf("CR3 target count 0x%x", i); 3569 vmcs_write(CR3_TARGET_COUNT, i); 3570 if (i <= max) 3571 test_vmx_valid_controls(); 3572 else 3573 test_vmx_invalid_controls(); 3574 report_prefix_pop(); 3575 } 3576 3577 /* 3578 * The CR3-target count must not be greater than 4. Future processors 3579 * may support a different number of CR3-target values. Software 3580 * should read the VMX capability MSR IA32_VMX_MISC to determine the 3581 * number of values supported. 3582 * [Intel SDM] 3583 */ 3584 static void test_cr3_targets(void) 3585 { 3586 unsigned supported_targets = (rdmsr(MSR_IA32_VMX_MISC) >> 16) & 0x1ff; 3587 u32 cr3_targets = vmcs_read(CR3_TARGET_COUNT); 3588 unsigned i; 3589 3590 printf("\nSupported CR3 targets: %d\n", supported_targets); 3591 TEST_ASSERT(supported_targets <= 256); 3592 3593 try_cr3_target_count(-1u, supported_targets); 3594 try_cr3_target_count(0x80000000, supported_targets); 3595 try_cr3_target_count(0x7fffffff, supported_targets); 3596 for (i = 0; i <= supported_targets + 1; i++) 3597 try_cr3_target_count(i, supported_targets); 3598 vmcs_write(CR3_TARGET_COUNT, cr3_targets); 3599 3600 /* VMWRITE to nonexistent target fields should fail. */ 3601 for (i = supported_targets; i < 256; i++) 3602 TEST_ASSERT(vmcs_write(CR3_TARGET_0 + i*2, 0)); 3603 } 3604 3605 /* 3606 * Test a particular address setting in the VMCS 3607 */ 3608 static void test_vmcs_addr(const char *name, 3609 enum Encoding encoding, 3610 u64 align, 3611 bool ignored, 3612 bool skip_beyond_mapped_ram, 3613 u64 addr) 3614 { 3615 report_prefix_pushf("%s = %lx", name, addr); 3616 vmcs_write(encoding, addr); 3617 if (skip_beyond_mapped_ram && 3618 addr > fwcfg_get_u64(FW_CFG_RAM_SIZE) - align && 3619 addr < (1ul << cpuid_maxphyaddr())) 3620 printf("Skipping physical address beyond mapped RAM\n"); 3621 else if (ignored || (IS_ALIGNED(addr, align) && 3622 addr < (1ul << cpuid_maxphyaddr()))) 3623 test_vmx_valid_controls(); 3624 else 3625 test_vmx_invalid_controls(); 3626 report_prefix_pop(); 3627 } 3628 3629 /* 3630 * Test interesting values for a VMCS address 3631 */ 3632 static void test_vmcs_addr_values(const char *name, 3633 enum Encoding encoding, 3634 u64 align, 3635 bool ignored, 3636 bool skip_beyond_mapped_ram, 3637 u32 bit_start, u32 bit_end) 3638 { 3639 unsigned i; 3640 u64 orig_val = vmcs_read(encoding); 3641 3642 for (i = bit_start; i <= bit_end; i++) 3643 test_vmcs_addr(name, encoding, align, ignored, 3644 skip_beyond_mapped_ram, 1ul << i); 3645 3646 test_vmcs_addr(name, encoding, align, ignored, 3647 skip_beyond_mapped_ram, PAGE_SIZE - 1); 3648 test_vmcs_addr(name, encoding, align, ignored, 3649 skip_beyond_mapped_ram, PAGE_SIZE); 3650 test_vmcs_addr(name, encoding, align, ignored, 3651 skip_beyond_mapped_ram, 3652 (1ul << cpuid_maxphyaddr()) - PAGE_SIZE); 3653 test_vmcs_addr(name, encoding, align, ignored, 3654 skip_beyond_mapped_ram, -1ul); 3655 3656 vmcs_write(encoding, orig_val); 3657 } 3658 3659 /* 3660 * Test a physical address reference in the VMCS, when the corresponding 3661 * feature is enabled and when the corresponding feature is disabled. 3662 */ 3663 static void test_vmcs_addr_reference(u32 control_bit, enum Encoding field, 3664 const char *field_name, 3665 const char *control_name, u64 align, 3666 bool skip_beyond_mapped_ram, 3667 bool control_primary) 3668 { 3669 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 3670 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 3671 u64 page_addr; 3672 3673 if (control_primary) { 3674 if (!(ctrl_cpu_rev[0].clr & control_bit)) 3675 return; 3676 } else { 3677 if (!(ctrl_cpu_rev[1].clr & control_bit)) 3678 return; 3679 } 3680 3681 page_addr = vmcs_read(field); 3682 3683 report_prefix_pushf("%s enabled", control_name); 3684 if (control_primary) { 3685 vmcs_write(CPU_EXEC_CTRL0, primary | control_bit); 3686 } else { 3687 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3688 vmcs_write(CPU_EXEC_CTRL1, secondary | control_bit); 3689 } 3690 3691 test_vmcs_addr_values(field_name, field, align, false, 3692 skip_beyond_mapped_ram, 0, 63); 3693 report_prefix_pop(); 3694 3695 report_prefix_pushf("%s disabled", control_name); 3696 if (control_primary) { 3697 vmcs_write(CPU_EXEC_CTRL0, primary & ~control_bit); 3698 } else { 3699 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3700 vmcs_write(CPU_EXEC_CTRL1, secondary & ~control_bit); 3701 } 3702 3703 test_vmcs_addr_values(field_name, field, align, true, false, 0, 63); 3704 report_prefix_pop(); 3705 3706 vmcs_write(field, page_addr); 3707 vmcs_write(CPU_EXEC_CTRL0, primary); 3708 vmcs_write(CPU_EXEC_CTRL1, secondary); 3709 } 3710 3711 /* 3712 * If the "use I/O bitmaps" VM-execution control is 1, bits 11:0 of 3713 * each I/O-bitmap address must be 0. Neither address should set any 3714 * bits beyond the processor's physical-address width. 3715 * [Intel SDM] 3716 */ 3717 static void test_io_bitmaps(void) 3718 { 3719 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_A, 3720 "I/O bitmap A", "Use I/O bitmaps", 3721 PAGE_SIZE, false, true); 3722 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_B, 3723 "I/O bitmap B", "Use I/O bitmaps", 3724 PAGE_SIZE, false, true); 3725 } 3726 3727 /* 3728 * If the "use MSR bitmaps" VM-execution control is 1, bits 11:0 of 3729 * the MSR-bitmap address must be 0. The address should not set any 3730 * bits beyond the processor's physical-address width. 3731 * [Intel SDM] 3732 */ 3733 static void test_msr_bitmap(void) 3734 { 3735 test_vmcs_addr_reference(CPU_MSR_BITMAP, MSR_BITMAP, 3736 "MSR bitmap", "Use MSR bitmaps", 3737 PAGE_SIZE, false, true); 3738 } 3739 3740 /* 3741 * If the "use TPR shadow" VM-execution control is 1, the virtual-APIC 3742 * address must satisfy the following checks: 3743 * - Bits 11:0 of the address must be 0. 3744 * - The address should not set any bits beyond the processor's 3745 * physical-address width. 3746 * [Intel SDM] 3747 */ 3748 static void test_apic_virt_addr(void) 3749 { 3750 /* 3751 * Ensure the processor will never use the virtual-APIC page, since 3752 * we will point it to invalid RAM. Otherwise KVM is puzzled about 3753 * what we're trying to achieve and fails vmentry. 3754 */ 3755 u32 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 3756 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0 | CPU_CR8_LOAD | CPU_CR8_STORE); 3757 test_vmcs_addr_reference(CPU_TPR_SHADOW, APIC_VIRT_ADDR, 3758 "virtual-APIC address", "Use TPR shadow", 3759 PAGE_SIZE, false, true); 3760 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 3761 } 3762 3763 /* 3764 * If the "virtualize APIC-accesses" VM-execution control is 1, the 3765 * APIC-access address must satisfy the following checks: 3766 * - Bits 11:0 of the address must be 0. 3767 * - The address should not set any bits beyond the processor's 3768 * physical-address width. 3769 * [Intel SDM] 3770 */ 3771 static void test_apic_access_addr(void) 3772 { 3773 void *apic_access_page = alloc_page(); 3774 3775 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_page)); 3776 3777 test_vmcs_addr_reference(CPU_VIRT_APIC_ACCESSES, APIC_ACCS_ADDR, 3778 "APIC-access address", 3779 "virtualize APIC-accesses", PAGE_SIZE, 3780 true, false); 3781 } 3782 3783 static bool set_bit_pattern(u8 mask, u32 *secondary) 3784 { 3785 u8 i; 3786 bool flag = false; 3787 u32 test_bits[3] = { 3788 CPU_VIRT_X2APIC, 3789 CPU_APIC_REG_VIRT, 3790 CPU_VINTD 3791 }; 3792 3793 for (i = 0; i < ARRAY_SIZE(test_bits); i++) { 3794 if ((mask & (1u << i)) && 3795 (ctrl_cpu_rev[1].clr & test_bits[i])) { 3796 *secondary |= test_bits[i]; 3797 flag = true; 3798 } 3799 } 3800 3801 return (flag); 3802 } 3803 3804 /* 3805 * If the "use TPR shadow" VM-execution control is 0, the following 3806 * VM-execution controls must also be 0: 3807 * - virtualize x2APIC mode 3808 * - APIC-register virtualization 3809 * - virtual-interrupt delivery 3810 * [Intel SDM] 3811 * 3812 * 2. If the "virtualize x2APIC mode" VM-execution control is 1, the 3813 * "virtualize APIC accesses" VM-execution control must be 0. 3814 * [Intel SDM] 3815 */ 3816 static void test_apic_virtual_ctls(void) 3817 { 3818 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3819 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3820 u32 primary = saved_primary; 3821 u32 secondary = saved_secondary; 3822 bool is_ctrl_valid = false; 3823 char str[10] = "disabled"; 3824 u8 i = 0, j; 3825 3826 /* 3827 * First test 3828 */ 3829 if (!((ctrl_cpu_rev[0].clr & (CPU_SECONDARY | CPU_TPR_SHADOW)) == 3830 (CPU_SECONDARY | CPU_TPR_SHADOW))) 3831 return; 3832 3833 primary |= CPU_SECONDARY; 3834 primary &= ~CPU_TPR_SHADOW; 3835 vmcs_write(CPU_EXEC_CTRL0, primary); 3836 3837 while (1) { 3838 for (j = 1; j < 8; j++) { 3839 secondary &= ~(CPU_VIRT_X2APIC | CPU_APIC_REG_VIRT | CPU_VINTD); 3840 if (primary & CPU_TPR_SHADOW) { 3841 is_ctrl_valid = true; 3842 } else { 3843 if (! set_bit_pattern(j, &secondary)) 3844 is_ctrl_valid = true; 3845 else 3846 is_ctrl_valid = false; 3847 } 3848 3849 vmcs_write(CPU_EXEC_CTRL1, secondary); 3850 report_prefix_pushf("Use TPR shadow %s, virtualize x2APIC mode %s, APIC-register virtualization %s, virtual-interrupt delivery %s", 3851 str, (secondary & CPU_VIRT_X2APIC) ? "enabled" : "disabled", (secondary & CPU_APIC_REG_VIRT) ? "enabled" : "disabled", (secondary & CPU_VINTD) ? "enabled" : "disabled"); 3852 if (is_ctrl_valid) 3853 test_vmx_valid_controls(); 3854 else 3855 test_vmx_invalid_controls(); 3856 report_prefix_pop(); 3857 } 3858 3859 if (i == 1) 3860 break; 3861 i++; 3862 3863 primary |= CPU_TPR_SHADOW; 3864 vmcs_write(CPU_EXEC_CTRL0, primary); 3865 strcpy(str, "enabled"); 3866 } 3867 3868 /* 3869 * Second test 3870 */ 3871 u32 apic_virt_ctls = (CPU_VIRT_X2APIC | CPU_VIRT_APIC_ACCESSES); 3872 3873 primary = saved_primary; 3874 secondary = saved_secondary; 3875 if (!((ctrl_cpu_rev[1].clr & apic_virt_ctls) == apic_virt_ctls)) 3876 return; 3877 3878 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3879 secondary &= ~CPU_VIRT_APIC_ACCESSES; 3880 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_X2APIC); 3881 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access disabled"); 3882 test_vmx_valid_controls(); 3883 report_prefix_pop(); 3884 3885 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_APIC_ACCESSES); 3886 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access enabled"); 3887 test_vmx_valid_controls(); 3888 report_prefix_pop(); 3889 3890 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_X2APIC); 3891 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access enabled"); 3892 test_vmx_invalid_controls(); 3893 report_prefix_pop(); 3894 3895 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_APIC_ACCESSES); 3896 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access disabled"); 3897 test_vmx_valid_controls(); 3898 report_prefix_pop(); 3899 3900 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3901 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3902 } 3903 3904 /* 3905 * If the "virtual-interrupt delivery" VM-execution control is 1, the 3906 * "external-interrupt exiting" VM-execution control must be 1. 3907 * [Intel SDM] 3908 */ 3909 static void test_virtual_intr_ctls(void) 3910 { 3911 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3912 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3913 u32 saved_pin = vmcs_read(PIN_CONTROLS); 3914 u32 primary = saved_primary; 3915 u32 secondary = saved_secondary; 3916 u32 pin = saved_pin; 3917 3918 if (!((ctrl_cpu_rev[1].clr & CPU_VINTD) && 3919 (ctrl_pin_rev.clr & PIN_EXTINT))) 3920 return; 3921 3922 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 3923 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VINTD); 3924 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 3925 report_prefix_pushf("Virtualize interrupt-delivery disabled; external-interrupt exiting disabled"); 3926 test_vmx_valid_controls(); 3927 report_prefix_pop(); 3928 3929 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VINTD); 3930 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 3931 test_vmx_invalid_controls(); 3932 report_prefix_pop(); 3933 3934 vmcs_write(PIN_CONTROLS, pin | PIN_EXTINT); 3935 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting enabled"); 3936 test_vmx_valid_controls(); 3937 report_prefix_pop(); 3938 3939 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 3940 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 3941 test_vmx_invalid_controls(); 3942 report_prefix_pop(); 3943 3944 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3945 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3946 vmcs_write(PIN_CONTROLS, saved_pin); 3947 } 3948 3949 static void test_pi_desc_addr(u64 addr, bool is_ctrl_valid) 3950 { 3951 vmcs_write(POSTED_INTR_DESC_ADDR, addr); 3952 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-descriptor-address 0x%lx", addr); 3953 if (is_ctrl_valid) 3954 test_vmx_valid_controls(); 3955 else 3956 test_vmx_invalid_controls(); 3957 report_prefix_pop(); 3958 } 3959 3960 /* 3961 * If the "process posted interrupts" VM-execution control is 1, the 3962 * following must be true: 3963 * 3964 * - The "virtual-interrupt delivery" VM-execution control is 1. 3965 * - The "acknowledge interrupt on exit" VM-exit control is 1. 3966 * - The posted-interrupt notification vector has a value in the 3967 * - range 0 - 255 (bits 15:8 are all 0). 3968 * - Bits 5:0 of the posted-interrupt descriptor address are all 0. 3969 * - The posted-interrupt descriptor address does not set any bits 3970 * beyond the processor's physical-address width. 3971 * [Intel SDM] 3972 */ 3973 static void test_posted_intr(void) 3974 { 3975 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3976 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3977 u32 saved_pin = vmcs_read(PIN_CONTROLS); 3978 u32 exit_ctl_saved = vmcs_read(EXI_CONTROLS); 3979 u32 primary = saved_primary; 3980 u32 secondary = saved_secondary; 3981 u32 pin = saved_pin; 3982 u32 exit_ctl = exit_ctl_saved; 3983 u16 vec; 3984 int i; 3985 3986 if (!((ctrl_pin_rev.clr & PIN_POST_INTR) && 3987 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 3988 (ctrl_exit_rev.clr & EXI_INTA))) 3989 return; 3990 3991 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 3992 3993 /* 3994 * Test virtual-interrupt-delivery and acknowledge-interrupt-on-exit 3995 */ 3996 pin |= PIN_POST_INTR; 3997 vmcs_write(PIN_CONTROLS, pin); 3998 secondary &= ~CPU_VINTD; 3999 vmcs_write(CPU_EXEC_CTRL1, secondary); 4000 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled"); 4001 test_vmx_invalid_controls(); 4002 report_prefix_pop(); 4003 4004 secondary |= CPU_VINTD; 4005 vmcs_write(CPU_EXEC_CTRL1, secondary); 4006 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled"); 4007 test_vmx_invalid_controls(); 4008 report_prefix_pop(); 4009 4010 exit_ctl &= ~EXI_INTA; 4011 vmcs_write(EXI_CONTROLS, exit_ctl); 4012 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit disabled"); 4013 test_vmx_invalid_controls(); 4014 report_prefix_pop(); 4015 4016 exit_ctl |= EXI_INTA; 4017 vmcs_write(EXI_CONTROLS, exit_ctl); 4018 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 4019 test_vmx_valid_controls(); 4020 report_prefix_pop(); 4021 4022 secondary &= ~CPU_VINTD; 4023 vmcs_write(CPU_EXEC_CTRL1, secondary); 4024 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled; acknowledge-interrupt-on-exit enabled"); 4025 test_vmx_invalid_controls(); 4026 report_prefix_pop(); 4027 4028 secondary |= CPU_VINTD; 4029 vmcs_write(CPU_EXEC_CTRL1, secondary); 4030 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 4031 test_vmx_valid_controls(); 4032 report_prefix_pop(); 4033 4034 /* 4035 * Test posted-interrupt notification vector 4036 */ 4037 for (i = 0; i < 8; i++) { 4038 vec = (1ul << i); 4039 vmcs_write(PINV, vec); 4040 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 4041 test_vmx_valid_controls(); 4042 report_prefix_pop(); 4043 } 4044 for (i = 8; i < 16; i++) { 4045 vec = (1ul << i); 4046 vmcs_write(PINV, vec); 4047 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 4048 test_vmx_invalid_controls(); 4049 report_prefix_pop(); 4050 } 4051 4052 vec &= ~(0xff << 8); 4053 vmcs_write(PINV, vec); 4054 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 4055 test_vmx_valid_controls(); 4056 report_prefix_pop(); 4057 4058 /* 4059 * Test posted-interrupt descriptor addresss 4060 */ 4061 for (i = 0; i < 6; i++) { 4062 test_pi_desc_addr(1ul << i, false); 4063 } 4064 4065 test_pi_desc_addr(0xf0, false); 4066 test_pi_desc_addr(0xff, false); 4067 test_pi_desc_addr(0x0f, false); 4068 test_pi_desc_addr(0x8000, true); 4069 test_pi_desc_addr(0x00, true); 4070 test_pi_desc_addr(0xc000, true); 4071 4072 test_vmcs_addr_values("process-posted interrupts", 4073 POSTED_INTR_DESC_ADDR, 64, 4074 false, false, 0, 63); 4075 4076 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 4077 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 4078 vmcs_write(PIN_CONTROLS, saved_pin); 4079 } 4080 4081 static void test_apic_ctls(void) 4082 { 4083 test_apic_virt_addr(); 4084 test_apic_access_addr(); 4085 test_apic_virtual_ctls(); 4086 test_virtual_intr_ctls(); 4087 test_posted_intr(); 4088 } 4089 4090 /* 4091 * If the "enable VPID" VM-execution control is 1, the value of the 4092 * of the VPID VM-execution control field must not be 0000H. 4093 * [Intel SDM] 4094 */ 4095 static void test_vpid(void) 4096 { 4097 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 4098 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 4099 u16 vpid = 0x0000; 4100 int i; 4101 4102 if (!is_vpid_supported()) { 4103 printf("Secondary controls and/or VPID not supported\n"); 4104 return; 4105 } 4106 4107 vmcs_write(CPU_EXEC_CTRL0, saved_primary | CPU_SECONDARY); 4108 vmcs_write(CPU_EXEC_CTRL1, saved_secondary & ~CPU_VPID); 4109 vmcs_write(VPID, vpid); 4110 report_prefix_pushf("VPID disabled; VPID value %x", vpid); 4111 test_vmx_valid_controls(); 4112 report_prefix_pop(); 4113 4114 vmcs_write(CPU_EXEC_CTRL1, saved_secondary | CPU_VPID); 4115 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 4116 test_vmx_invalid_controls(); 4117 report_prefix_pop(); 4118 4119 for (i = 0; i < 16; i++) { 4120 vpid = (short)1 << i;; 4121 vmcs_write(VPID, vpid); 4122 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 4123 test_vmx_valid_controls(); 4124 report_prefix_pop(); 4125 } 4126 4127 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 4128 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 4129 } 4130 4131 static void set_vtpr(unsigned vtpr) 4132 { 4133 *(u32 *)phys_to_virt(vmcs_read(APIC_VIRT_ADDR) + APIC_TASKPRI) = vtpr; 4134 } 4135 4136 static void try_tpr_threshold_and_vtpr(unsigned threshold, unsigned vtpr) 4137 { 4138 bool valid = true; 4139 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4140 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4141 4142 if ((primary & CPU_TPR_SHADOW) && 4143 (!(primary & CPU_SECONDARY) || 4144 !(secondary & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 4145 valid = (threshold & 0xf) <= ((vtpr >> 4) & 0xf); 4146 4147 set_vtpr(vtpr); 4148 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0x%x", 4149 threshold, (vtpr >> 4) & 0xf); 4150 if (valid) 4151 test_vmx_valid_controls(); 4152 else 4153 test_vmx_invalid_controls(); 4154 report_prefix_pop(); 4155 } 4156 4157 static void test_invalid_event_injection(void) 4158 { 4159 u32 ent_intr_info_save = vmcs_read(ENT_INTR_INFO); 4160 u32 ent_intr_error_save = vmcs_read(ENT_INTR_ERROR); 4161 u32 ent_inst_len_save = vmcs_read(ENT_INST_LEN); 4162 u32 primary_save = vmcs_read(CPU_EXEC_CTRL0); 4163 u32 secondary_save = vmcs_read(CPU_EXEC_CTRL1); 4164 u64 guest_cr0_save = vmcs_read(GUEST_CR0); 4165 u32 ent_intr_info_base = INTR_INFO_VALID_MASK; 4166 u32 ent_intr_info, ent_intr_err, ent_intr_len; 4167 u32 cnt; 4168 4169 /* Setup */ 4170 report_prefix_push("invalid event injection"); 4171 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4172 vmcs_write(ENT_INST_LEN, 0x00000001); 4173 4174 /* The field's interruption type is not set to a reserved value. */ 4175 ent_intr_info = ent_intr_info_base | INTR_TYPE_RESERVED | DE_VECTOR; 4176 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4177 "RESERVED interruption type invalid [-]", 4178 ent_intr_info); 4179 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4180 test_vmx_invalid_controls(); 4181 report_prefix_pop(); 4182 4183 ent_intr_info = ent_intr_info_base | INTR_TYPE_EXT_INTR | 4184 DE_VECTOR; 4185 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4186 "RESERVED interruption type invalid [+]", 4187 ent_intr_info); 4188 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4189 test_vmx_valid_controls(); 4190 report_prefix_pop(); 4191 4192 /* If the interruption type is other event, the vector is 0. */ 4193 ent_intr_info = ent_intr_info_base | INTR_TYPE_OTHER_EVENT | DB_VECTOR; 4194 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4195 "(OTHER EVENT && vector != 0) invalid [-]", 4196 ent_intr_info); 4197 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4198 test_vmx_invalid_controls(); 4199 report_prefix_pop(); 4200 4201 /* If the interruption type is NMI, the vector is 2 (negative case). */ 4202 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | DE_VECTOR; 4203 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4204 "(NMI && vector != 2) invalid [-]", ent_intr_info); 4205 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4206 test_vmx_invalid_controls(); 4207 report_prefix_pop(); 4208 4209 /* If the interruption type is NMI, the vector is 2 (positive case). */ 4210 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | NMI_VECTOR; 4211 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4212 "(NMI && vector == 2) valid [+]", ent_intr_info); 4213 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4214 test_vmx_valid_controls(); 4215 report_prefix_pop(); 4216 4217 /* 4218 * If the interruption type 4219 * is HW exception, the vector is at most 31. 4220 */ 4221 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 0x20; 4222 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4223 "(HW exception && vector > 31) invalid [-]", 4224 ent_intr_info); 4225 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4226 test_vmx_invalid_controls(); 4227 report_prefix_pop(); 4228 4229 /* 4230 * deliver-error-code is 1 iff either 4231 * (a) the "unrestricted guest" VM-execution control is 0 4232 * (b) CR0.PE is set. 4233 */ 4234 4235 /* Assert that unrestricted guest is disabled or unsupported */ 4236 assert(!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 4237 !(secondary_save & CPU_URG)); 4238 4239 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4240 GP_VECTOR; 4241 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4242 "error code <-> (!URG || prot_mode) [-]", 4243 ent_intr_info); 4244 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4245 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4246 test_vmx_invalid_controls(); 4247 report_prefix_pop(); 4248 4249 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4250 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4251 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4252 "error code <-> (!URG || prot_mode) [+]", 4253 ent_intr_info); 4254 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4255 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4256 test_vmx_valid_controls(); 4257 report_prefix_pop(); 4258 4259 if (enable_unrestricted_guest(false)) 4260 goto skip_unrestricted_guest; 4261 4262 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4263 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4264 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4265 "error code <-> (!URG || prot_mode) [-]", 4266 ent_intr_info); 4267 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4268 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4269 test_vmx_invalid_controls(); 4270 report_prefix_pop(); 4271 4272 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4273 GP_VECTOR; 4274 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4275 "error code <-> (!URG || prot_mode) [-]", 4276 ent_intr_info); 4277 vmcs_write(GUEST_CR0, guest_cr0_save | X86_CR0_PE); 4278 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4279 test_vmx_invalid_controls(); 4280 report_prefix_pop(); 4281 4282 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4283 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4284 4285 skip_unrestricted_guest: 4286 vmcs_write(GUEST_CR0, guest_cr0_save); 4287 4288 /* deliver-error-code is 1 iff the interruption type is HW exception */ 4289 report_prefix_push("error code <-> HW exception"); 4290 for (cnt = 0; cnt < 8; cnt++) { 4291 u32 exception_type_mask = cnt << 8; 4292 u32 deliver_error_code_mask = 4293 exception_type_mask != INTR_TYPE_HARD_EXCEPTION ? 4294 INTR_INFO_DELIVER_CODE_MASK : 0; 4295 4296 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4297 exception_type_mask | GP_VECTOR; 4298 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4299 ent_intr_info); 4300 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4301 test_vmx_invalid_controls(); 4302 report_prefix_pop(); 4303 } 4304 report_prefix_pop(); 4305 4306 /* 4307 * deliver-error-code is 1 iff the the vector 4308 * indicates an exception that would normally deliver an error code 4309 */ 4310 report_prefix_push("error code <-> vector delivers error code"); 4311 for (cnt = 0; cnt < 32; cnt++) { 4312 bool has_error_code = false; 4313 u32 deliver_error_code_mask; 4314 4315 switch (cnt) { 4316 case DF_VECTOR: 4317 case TS_VECTOR: 4318 case NP_VECTOR: 4319 case SS_VECTOR: 4320 case GP_VECTOR: 4321 case PF_VECTOR: 4322 case AC_VECTOR: 4323 has_error_code = true; 4324 case CP_VECTOR: 4325 /* Some CPUs have error code and some do not, skip */ 4326 continue; 4327 } 4328 4329 /* Negative case */ 4330 deliver_error_code_mask = has_error_code ? 4331 0 : 4332 INTR_INFO_DELIVER_CODE_MASK; 4333 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4334 INTR_TYPE_HARD_EXCEPTION | cnt; 4335 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4336 ent_intr_info); 4337 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4338 test_vmx_invalid_controls(); 4339 report_prefix_pop(); 4340 4341 /* Positive case */ 4342 deliver_error_code_mask = has_error_code ? 4343 INTR_INFO_DELIVER_CODE_MASK : 4344 0; 4345 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4346 INTR_TYPE_HARD_EXCEPTION | cnt; 4347 report_prefix_pushf("VM-entry intr info=0x%x [+]", 4348 ent_intr_info); 4349 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4350 test_vmx_valid_controls(); 4351 report_prefix_pop(); 4352 } 4353 report_prefix_pop(); 4354 4355 /* Reserved bits in the field (30:12) are 0. */ 4356 report_prefix_push("reserved bits clear"); 4357 for (cnt = 12; cnt <= 30; cnt++) { 4358 ent_intr_info = ent_intr_info_base | 4359 INTR_INFO_DELIVER_CODE_MASK | 4360 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR | 4361 (1U << cnt); 4362 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4363 ent_intr_info); 4364 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4365 test_vmx_invalid_controls(); 4366 report_prefix_pop(); 4367 } 4368 report_prefix_pop(); 4369 4370 /* 4371 * If deliver-error-code is 1 4372 * bits 31:16 of the VM-entry exception error-code field are 0. 4373 */ 4374 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4375 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4376 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4377 "VM-entry exception error code[31:16] clear", 4378 ent_intr_info); 4379 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4380 for (cnt = 16; cnt <= 31; cnt++) { 4381 ent_intr_err = 1U << cnt; 4382 report_prefix_pushf("VM-entry intr error=0x%x [-]", 4383 ent_intr_err); 4384 vmcs_write(ENT_INTR_ERROR, ent_intr_err); 4385 test_vmx_invalid_controls(); 4386 report_prefix_pop(); 4387 } 4388 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4389 report_prefix_pop(); 4390 4391 /* 4392 * If the interruption type is software interrupt, software exception, 4393 * or privileged software exception, the VM-entry instruction-length 4394 * field is in the range 0 - 15. 4395 */ 4396 4397 for (cnt = 0; cnt < 3; cnt++) { 4398 switch (cnt) { 4399 case 0: 4400 ent_intr_info = ent_intr_info_base | 4401 INTR_TYPE_SOFT_INTR; 4402 break; 4403 case 1: 4404 ent_intr_info = ent_intr_info_base | 4405 INTR_TYPE_SOFT_EXCEPTION; 4406 break; 4407 case 2: 4408 ent_intr_info = ent_intr_info_base | 4409 INTR_TYPE_PRIV_SW_EXCEPTION; 4410 break; 4411 } 4412 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4413 "VM-entry instruction-length check", 4414 ent_intr_info); 4415 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4416 4417 /* Instruction length set to -1 (0xFFFFFFFF) should fail */ 4418 ent_intr_len = -1; 4419 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4420 ent_intr_len); 4421 vmcs_write(ENT_INST_LEN, ent_intr_len); 4422 test_vmx_invalid_controls(); 4423 report_prefix_pop(); 4424 4425 /* Instruction length set to 16 should fail */ 4426 ent_intr_len = 0x00000010; 4427 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4428 ent_intr_len); 4429 vmcs_write(ENT_INST_LEN, 0x00000010); 4430 test_vmx_invalid_controls(); 4431 report_prefix_pop(); 4432 4433 report_prefix_pop(); 4434 } 4435 4436 /* Cleanup */ 4437 vmcs_write(ENT_INTR_INFO, ent_intr_info_save); 4438 vmcs_write(ENT_INTR_ERROR, ent_intr_error_save); 4439 vmcs_write(ENT_INST_LEN, ent_inst_len_save); 4440 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4441 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4442 vmcs_write(GUEST_CR0, guest_cr0_save); 4443 report_prefix_pop(); 4444 } 4445 4446 /* 4447 * Test interesting vTPR values for a given TPR threshold. 4448 */ 4449 static void test_vtpr_values(unsigned threshold) 4450 { 4451 try_tpr_threshold_and_vtpr(threshold, (threshold - 1) << 4); 4452 try_tpr_threshold_and_vtpr(threshold, threshold << 4); 4453 try_tpr_threshold_and_vtpr(threshold, (threshold + 1) << 4); 4454 } 4455 4456 static void try_tpr_threshold(unsigned threshold) 4457 { 4458 bool valid = true; 4459 4460 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4461 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4462 4463 if ((primary & CPU_TPR_SHADOW) && !((primary & CPU_SECONDARY) && 4464 (secondary & CPU_VINTD))) 4465 valid = !(threshold >> 4); 4466 4467 set_vtpr(-1); 4468 vmcs_write(TPR_THRESHOLD, threshold); 4469 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0xf", threshold); 4470 if (valid) 4471 test_vmx_valid_controls(); 4472 else 4473 test_vmx_invalid_controls(); 4474 report_prefix_pop(); 4475 4476 if (valid) 4477 test_vtpr_values(threshold); 4478 } 4479 4480 /* 4481 * Test interesting TPR threshold values. 4482 */ 4483 static void test_tpr_threshold_values(void) 4484 { 4485 unsigned i; 4486 4487 for (i = 0; i < 0x10; i++) 4488 try_tpr_threshold(i); 4489 for (i = 4; i < 32; i++) 4490 try_tpr_threshold(1u << i); 4491 try_tpr_threshold(-1u); 4492 try_tpr_threshold(0x7fffffff); 4493 } 4494 4495 /* 4496 * This test covers the following two VM entry checks: 4497 * 4498 * i) If the "use TPR shadow" VM-execution control is 1 and the 4499 * "virtual-interrupt delivery" VM-execution control is 0, bits 4500 * 31:4 of the TPR threshold VM-execution control field must 4501 be 0. 4502 * [Intel SDM] 4503 * 4504 * ii) If the "use TPR shadow" VM-execution control is 1, the 4505 * "virtual-interrupt delivery" VM-execution control is 0 4506 * and the "virtualize APIC accesses" VM-execution control 4507 * is 0, the value of bits 3:0 of the TPR threshold VM-execution 4508 * control field must not be greater than the value of bits 4509 * 7:4 of VTPR. 4510 * [Intel SDM] 4511 */ 4512 static void test_tpr_threshold(void) 4513 { 4514 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4515 u64 apic_virt_addr = vmcs_read(APIC_VIRT_ADDR); 4516 u64 threshold = vmcs_read(TPR_THRESHOLD); 4517 void *virtual_apic_page; 4518 4519 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) 4520 return; 4521 4522 virtual_apic_page = alloc_page(); 4523 memset(virtual_apic_page, 0xff, PAGE_SIZE); 4524 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 4525 4526 vmcs_write(CPU_EXEC_CTRL0, primary & ~(CPU_TPR_SHADOW | CPU_SECONDARY)); 4527 report_prefix_pushf("Use TPR shadow disabled, secondary controls disabled"); 4528 test_tpr_threshold_values(); 4529 report_prefix_pop(); 4530 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_TPR_SHADOW); 4531 report_prefix_pushf("Use TPR shadow enabled, secondary controls disabled"); 4532 test_tpr_threshold_values(); 4533 report_prefix_pop(); 4534 4535 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4536 (ctrl_cpu_rev[1].clr & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 4537 goto out; 4538 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4539 4540 if (ctrl_cpu_rev[1].clr & CPU_VINTD) { 4541 vmcs_write(CPU_EXEC_CTRL1, CPU_VINTD); 4542 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4543 test_tpr_threshold_values(); 4544 report_prefix_pop(); 4545 4546 vmcs_write(CPU_EXEC_CTRL0, 4547 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4548 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4549 test_tpr_threshold_values(); 4550 report_prefix_pop(); 4551 } 4552 4553 if (ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES) { 4554 vmcs_write(CPU_EXEC_CTRL0, 4555 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4556 vmcs_write(CPU_EXEC_CTRL1, CPU_VIRT_APIC_ACCESSES); 4557 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4558 test_tpr_threshold_values(); 4559 report_prefix_pop(); 4560 4561 vmcs_write(CPU_EXEC_CTRL0, 4562 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4563 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4564 test_tpr_threshold_values(); 4565 report_prefix_pop(); 4566 } 4567 4568 if ((ctrl_cpu_rev[1].clr & 4569 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) == 4570 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) { 4571 vmcs_write(CPU_EXEC_CTRL0, 4572 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4573 vmcs_write(CPU_EXEC_CTRL1, 4574 CPU_VINTD | CPU_VIRT_APIC_ACCESSES); 4575 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4576 test_tpr_threshold_values(); 4577 report_prefix_pop(); 4578 4579 vmcs_write(CPU_EXEC_CTRL0, 4580 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4581 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4582 test_tpr_threshold_values(); 4583 report_prefix_pop(); 4584 } 4585 4586 vmcs_write(CPU_EXEC_CTRL1, secondary); 4587 out: 4588 vmcs_write(TPR_THRESHOLD, threshold); 4589 vmcs_write(APIC_VIRT_ADDR, apic_virt_addr); 4590 vmcs_write(CPU_EXEC_CTRL0, primary); 4591 } 4592 4593 /* 4594 * This test verifies the following two vmentry checks: 4595 * 4596 * If the "NMI exiting" VM-execution control is 0, "Virtual NMIs" 4597 * VM-execution control must be 0. 4598 * [Intel SDM] 4599 * 4600 * If the "virtual NMIs" VM-execution control is 0, the "NMI-window 4601 * exiting" VM-execution control must be 0. 4602 * [Intel SDM] 4603 */ 4604 static void test_nmi_ctrls(void) 4605 { 4606 u32 pin_ctrls, cpu_ctrls0, test_pin_ctrls, test_cpu_ctrls0; 4607 4608 if ((ctrl_pin_rev.clr & (PIN_NMI | PIN_VIRT_NMI)) != 4609 (PIN_NMI | PIN_VIRT_NMI)) { 4610 printf("NMI exiting and Virtual NMIs are not supported !\n"); 4611 return; 4612 } 4613 4614 /* Save the controls so that we can restore them after our tests */ 4615 pin_ctrls = vmcs_read(PIN_CONTROLS); 4616 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 4617 4618 test_pin_ctrls = pin_ctrls & ~(PIN_NMI | PIN_VIRT_NMI); 4619 test_cpu_ctrls0 = cpu_ctrls0 & ~CPU_NMI_WINDOW; 4620 4621 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4622 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs disabled"); 4623 test_vmx_valid_controls(); 4624 report_prefix_pop(); 4625 4626 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_VIRT_NMI); 4627 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs enabled"); 4628 test_vmx_invalid_controls(); 4629 report_prefix_pop(); 4630 4631 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4632 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs enabled"); 4633 test_vmx_valid_controls(); 4634 report_prefix_pop(); 4635 4636 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_NMI); 4637 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs disabled"); 4638 test_vmx_valid_controls(); 4639 report_prefix_pop(); 4640 4641 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 4642 report_info("NMI-window exiting is not supported, skipping..."); 4643 goto done; 4644 } 4645 4646 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4647 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4648 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting enabled"); 4649 test_vmx_invalid_controls(); 4650 report_prefix_pop(); 4651 4652 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4653 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4654 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting disabled"); 4655 test_vmx_valid_controls(); 4656 report_prefix_pop(); 4657 4658 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4659 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4660 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting enabled"); 4661 test_vmx_valid_controls(); 4662 report_prefix_pop(); 4663 4664 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4665 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4666 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting disabled"); 4667 test_vmx_valid_controls(); 4668 report_prefix_pop(); 4669 4670 /* Restore the controls to their original values */ 4671 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 4672 done: 4673 vmcs_write(PIN_CONTROLS, pin_ctrls); 4674 } 4675 4676 static void test_eptp_ad_bit(u64 eptp, bool is_ctrl_valid) 4677 { 4678 vmcs_write(EPTP, eptp); 4679 report_prefix_pushf("Enable-EPT enabled; EPT accessed and dirty flag %s", 4680 (eptp & EPTP_AD_FLAG) ? "1": "0"); 4681 if (is_ctrl_valid) 4682 test_vmx_valid_controls(); 4683 else 4684 test_vmx_invalid_controls(); 4685 report_prefix_pop(); 4686 4687 } 4688 4689 /* 4690 * 1. If the "enable EPT" VM-execution control is 1, the "EPTP VM-execution" 4691 * control field must satisfy the following checks: 4692 * 4693 * - The EPT memory type (bits 2:0) must be a value supported by the 4694 * processor as indicated in the IA32_VMX_EPT_VPID_CAP MSR. 4695 * - Bits 5:3 (1 less than the EPT page-walk length) must indicate a 4696 * supported EPT page-walk length. 4697 * - Bit 6 (enable bit for accessed and dirty flags for EPT) must be 4698 * 0 if bit 21 of the IA32_VMX_EPT_VPID_CAP MSR is read as 0, 4699 * indicating that the processor does not support accessed and dirty 4700 * dirty flags for EPT. 4701 * - Reserved bits 11:7 and 63:N (where N is the processor's 4702 * physical-address width) must all be 0. 4703 * 4704 * 2. If the "unrestricted guest" VM-execution control is 1, the 4705 * "enable EPT" VM-execution control must also be 1. 4706 */ 4707 static void test_ept_eptp(void) 4708 { 4709 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4710 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4711 u64 eptp_saved = vmcs_read(EPTP); 4712 u32 primary = primary_saved; 4713 u32 secondary = secondary_saved; 4714 u64 eptp = eptp_saved; 4715 u32 i, maxphysaddr; 4716 u64 j, resv_bits_mask = 0; 4717 4718 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4719 (ctrl_cpu_rev[1].clr & CPU_EPT))) { 4720 printf("\"CPU secondary\" and/or \"enable EPT\" execution controls are not supported !\n"); 4721 return; 4722 } 4723 4724 /* Support for 4-level EPT is mandatory. */ 4725 report(is_4_level_ept_supported(), "4-level EPT support check"); 4726 4727 primary |= CPU_SECONDARY; 4728 vmcs_write(CPU_EXEC_CTRL0, primary); 4729 secondary |= CPU_EPT; 4730 vmcs_write(CPU_EXEC_CTRL1, secondary); 4731 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4732 (3ul << EPTP_PG_WALK_LEN_SHIFT); 4733 vmcs_write(EPTP, eptp); 4734 4735 for (i = 0; i < 8; i++) { 4736 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | i; 4737 vmcs_write(EPTP, eptp); 4738 report_prefix_pushf("Enable-EPT enabled; EPT memory type %lu", 4739 eptp & EPT_MEM_TYPE_MASK); 4740 if (is_ept_memtype_supported(i)) 4741 test_vmx_valid_controls(); 4742 else 4743 test_vmx_invalid_controls(); 4744 report_prefix_pop(); 4745 } 4746 4747 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | 6ul; 4748 4749 /* 4750 * Page walk length (bits 5:3). Note, the value in VMCS.EPTP "is 1 4751 * less than the EPT page-walk length". 4752 */ 4753 for (i = 0; i < 8; i++) { 4754 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4755 (i << EPTP_PG_WALK_LEN_SHIFT); 4756 4757 vmcs_write(EPTP, eptp); 4758 report_prefix_pushf("Enable-EPT enabled; EPT page walk length %lu", 4759 eptp & EPTP_PG_WALK_LEN_MASK); 4760 if (i == 3 || (i == 4 && is_5_level_ept_supported())) 4761 test_vmx_valid_controls(); 4762 else 4763 test_vmx_invalid_controls(); 4764 report_prefix_pop(); 4765 } 4766 4767 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4768 3ul << EPTP_PG_WALK_LEN_SHIFT; 4769 4770 /* 4771 * Accessed and dirty flag (bit 6) 4772 */ 4773 if (ept_ad_bits_supported()) { 4774 report_info("Processor supports accessed and dirty flag"); 4775 eptp &= ~EPTP_AD_FLAG; 4776 test_eptp_ad_bit(eptp, true); 4777 4778 eptp |= EPTP_AD_FLAG; 4779 test_eptp_ad_bit(eptp, true); 4780 } else { 4781 report_info("Processor does not supports accessed and dirty flag"); 4782 eptp &= ~EPTP_AD_FLAG; 4783 test_eptp_ad_bit(eptp, true); 4784 4785 eptp |= EPTP_AD_FLAG; 4786 test_eptp_ad_bit(eptp, false); 4787 } 4788 4789 /* 4790 * Reserved bits [11:7] and [63:N] 4791 */ 4792 for (i = 0; i < 32; i++) { 4793 eptp = (eptp & 4794 ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)) | 4795 (i << EPTP_RESERV_BITS_SHIFT); 4796 vmcs_write(EPTP, eptp); 4797 report_prefix_pushf("Enable-EPT enabled; reserved bits [11:7] %lu", 4798 (eptp >> EPTP_RESERV_BITS_SHIFT) & 4799 EPTP_RESERV_BITS_MASK); 4800 if (i == 0) 4801 test_vmx_valid_controls(); 4802 else 4803 test_vmx_invalid_controls(); 4804 report_prefix_pop(); 4805 } 4806 4807 eptp = (eptp & ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)); 4808 4809 maxphysaddr = cpuid_maxphyaddr(); 4810 for (i = 0; i < (63 - maxphysaddr + 1); i++) { 4811 resv_bits_mask |= 1ul << i; 4812 } 4813 4814 for (j = maxphysaddr - 1; j <= 63; j++) { 4815 eptp = (eptp & ~(resv_bits_mask << maxphysaddr)) | 4816 (j < maxphysaddr ? 0 : 1ul << j); 4817 vmcs_write(EPTP, eptp); 4818 report_prefix_pushf("Enable-EPT enabled; reserved bits [63:N] %lu", 4819 (eptp >> maxphysaddr) & resv_bits_mask); 4820 if (j < maxphysaddr) 4821 test_vmx_valid_controls(); 4822 else 4823 test_vmx_invalid_controls(); 4824 report_prefix_pop(); 4825 } 4826 4827 secondary &= ~(CPU_EPT | CPU_URG); 4828 vmcs_write(CPU_EXEC_CTRL1, secondary); 4829 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest disabled"); 4830 test_vmx_valid_controls(); 4831 report_prefix_pop(); 4832 4833 if (!(ctrl_cpu_rev[1].clr & CPU_URG)) 4834 goto skip_unrestricted_guest; 4835 4836 secondary |= CPU_URG; 4837 vmcs_write(CPU_EXEC_CTRL1, secondary); 4838 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest enabled"); 4839 test_vmx_invalid_controls(); 4840 report_prefix_pop(); 4841 4842 secondary |= CPU_EPT; 4843 setup_dummy_ept(); 4844 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest enabled"); 4845 test_vmx_valid_controls(); 4846 report_prefix_pop(); 4847 4848 skip_unrestricted_guest: 4849 secondary &= ~CPU_URG; 4850 vmcs_write(CPU_EXEC_CTRL1, secondary); 4851 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest disabled"); 4852 test_vmx_valid_controls(); 4853 report_prefix_pop(); 4854 4855 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4856 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4857 vmcs_write(EPTP, eptp_saved); 4858 } 4859 4860 /* 4861 * If the 'enable PML' VM-execution control is 1, the 'enable EPT' 4862 * VM-execution control must also be 1. In addition, the PML address 4863 * must satisfy the following checks: 4864 * 4865 * * Bits 11:0 of the address must be 0. 4866 * * The address should not set any bits beyond the processor's 4867 * physical-address width. 4868 * 4869 * [Intel SDM] 4870 */ 4871 static void test_pml(void) 4872 { 4873 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4874 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4875 u32 primary = primary_saved; 4876 u32 secondary = secondary_saved; 4877 4878 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4879 (ctrl_cpu_rev[1].clr & CPU_EPT) && (ctrl_cpu_rev[1].clr & CPU_PML))) { 4880 printf("\"Secondary execution\" control or \"enable EPT\" control or \"enable PML\" control is not supported !\n"); 4881 return; 4882 } 4883 4884 primary |= CPU_SECONDARY; 4885 vmcs_write(CPU_EXEC_CTRL0, primary); 4886 secondary &= ~(CPU_PML | CPU_EPT); 4887 vmcs_write(CPU_EXEC_CTRL1, secondary); 4888 report_prefix_pushf("enable-PML disabled, enable-EPT disabled"); 4889 test_vmx_valid_controls(); 4890 report_prefix_pop(); 4891 4892 secondary |= CPU_PML; 4893 vmcs_write(CPU_EXEC_CTRL1, secondary); 4894 report_prefix_pushf("enable-PML enabled, enable-EPT disabled"); 4895 test_vmx_invalid_controls(); 4896 report_prefix_pop(); 4897 4898 secondary |= CPU_EPT; 4899 setup_dummy_ept(); 4900 report_prefix_pushf("enable-PML enabled, enable-EPT enabled"); 4901 test_vmx_valid_controls(); 4902 report_prefix_pop(); 4903 4904 secondary &= ~CPU_PML; 4905 vmcs_write(CPU_EXEC_CTRL1, secondary); 4906 report_prefix_pushf("enable-PML disabled, enable EPT enabled"); 4907 test_vmx_valid_controls(); 4908 report_prefix_pop(); 4909 4910 test_vmcs_addr_reference(CPU_PML, PMLADDR, "PML address", "PML", 4911 PAGE_SIZE, false, false); 4912 4913 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4914 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4915 } 4916 4917 /* 4918 * If the "activate VMX-preemption timer" VM-execution control is 0, the 4919 * the "save VMX-preemption timer value" VM-exit control must also be 0. 4920 * 4921 * [Intel SDM] 4922 */ 4923 static void test_vmx_preemption_timer(void) 4924 { 4925 u32 saved_pin = vmcs_read(PIN_CONTROLS); 4926 u32 saved_exit = vmcs_read(EXI_CONTROLS); 4927 u32 pin = saved_pin; 4928 u32 exit = saved_exit; 4929 4930 if (!((ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) || 4931 (ctrl_pin_rev.clr & PIN_PREEMPT))) { 4932 printf("\"Save-VMX-preemption-timer\" control and/or \"Enable-VMX-preemption-timer\" control is not supported\n"); 4933 return; 4934 } 4935 4936 pin |= PIN_PREEMPT; 4937 vmcs_write(PIN_CONTROLS, pin); 4938 exit &= ~EXI_SAVE_PREEMPT; 4939 vmcs_write(EXI_CONTROLS, exit); 4940 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer disabled"); 4941 test_vmx_valid_controls(); 4942 report_prefix_pop(); 4943 4944 exit |= EXI_SAVE_PREEMPT; 4945 vmcs_write(EXI_CONTROLS, exit); 4946 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer enabled"); 4947 test_vmx_valid_controls(); 4948 report_prefix_pop(); 4949 4950 pin &= ~PIN_PREEMPT; 4951 vmcs_write(PIN_CONTROLS, pin); 4952 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer enabled"); 4953 test_vmx_invalid_controls(); 4954 report_prefix_pop(); 4955 4956 exit &= ~EXI_SAVE_PREEMPT; 4957 vmcs_write(EXI_CONTROLS, exit); 4958 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer disabled"); 4959 test_vmx_valid_controls(); 4960 report_prefix_pop(); 4961 4962 vmcs_write(PIN_CONTROLS, saved_pin); 4963 vmcs_write(EXI_CONTROLS, saved_exit); 4964 } 4965 4966 extern unsigned char test_mtf1; 4967 extern unsigned char test_mtf2; 4968 extern unsigned char test_mtf3; 4969 extern unsigned char test_mtf4; 4970 4971 static void test_mtf_guest(void) 4972 { 4973 asm ("vmcall;\n\t" 4974 "out %al, $0x80;\n\t" 4975 "test_mtf1:\n\t" 4976 "vmcall;\n\t" 4977 "out %al, $0x80;\n\t" 4978 "test_mtf2:\n\t" 4979 /* 4980 * Prepare for the 'MOV CR3' test. Attempt to induce a 4981 * general-protection fault by moving a non-canonical address into 4982 * CR3. The 'MOV CR3' instruction does not take an imm64 operand, 4983 * so we must MOV the desired value into a register first. 4984 * 4985 * MOV RAX is done before the VMCALL such that MTF is only enabled 4986 * for the instruction under test. 4987 */ 4988 "mov $0xaaaaaaaaaaaaaaaa, %rax;\n\t" 4989 "vmcall;\n\t" 4990 "mov %rax, %cr3;\n\t" 4991 "test_mtf3:\n\t" 4992 "vmcall;\n\t" 4993 /* 4994 * ICEBP/INT1 instruction. Though the instruction is now 4995 * documented, don't rely on assemblers enumerating the 4996 * instruction. Resort to hand assembly. 4997 */ 4998 ".byte 0xf1;\n\t" 4999 "vmcall;\n\t" 5000 "test_mtf4:\n\t" 5001 "mov $0, %eax;\n\t"); 5002 } 5003 5004 static void test_mtf_gp_handler(struct ex_regs *regs) 5005 { 5006 regs->rip = (unsigned long) &test_mtf3; 5007 } 5008 5009 static void test_mtf_db_handler(struct ex_regs *regs) 5010 { 5011 } 5012 5013 static void enable_mtf(void) 5014 { 5015 u32 ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 5016 5017 vmcs_write(CPU_EXEC_CTRL0, ctrl0 | CPU_MTF); 5018 } 5019 5020 static void disable_mtf(void) 5021 { 5022 u32 ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 5023 5024 vmcs_write(CPU_EXEC_CTRL0, ctrl0 & ~CPU_MTF); 5025 } 5026 5027 static void enable_tf(void) 5028 { 5029 unsigned long rflags = vmcs_read(GUEST_RFLAGS); 5030 5031 vmcs_write(GUEST_RFLAGS, rflags | X86_EFLAGS_TF); 5032 } 5033 5034 static void disable_tf(void) 5035 { 5036 unsigned long rflags = vmcs_read(GUEST_RFLAGS); 5037 5038 vmcs_write(GUEST_RFLAGS, rflags & ~X86_EFLAGS_TF); 5039 } 5040 5041 static void report_mtf(const char *insn_name, unsigned long exp_rip) 5042 { 5043 unsigned long rip = vmcs_read(GUEST_RIP); 5044 5045 assert_exit_reason(VMX_MTF); 5046 report(rip == exp_rip, "MTF VM-exit after %s. RIP: 0x%lx (expected 0x%lx)", 5047 insn_name, rip, exp_rip); 5048 } 5049 5050 static void vmx_mtf_test(void) 5051 { 5052 unsigned long pending_dbg; 5053 handler old_gp, old_db; 5054 5055 if (!(ctrl_cpu_rev[0].clr & CPU_MTF)) { 5056 printf("CPU does not support the 'monitor trap flag' processor-based VM-execution control.\n"); 5057 return; 5058 } 5059 5060 test_set_guest(test_mtf_guest); 5061 5062 /* Expect an MTF VM-exit after OUT instruction */ 5063 enter_guest(); 5064 skip_exit_vmcall(); 5065 5066 enable_mtf(); 5067 enter_guest(); 5068 report_mtf("OUT", (unsigned long) &test_mtf1); 5069 disable_mtf(); 5070 5071 /* 5072 * Concurrent #DB trap and MTF on instruction boundary. Expect MTF 5073 * VM-exit with populated 'pending debug exceptions' VMCS field. 5074 */ 5075 enter_guest(); 5076 skip_exit_vmcall(); 5077 5078 enable_mtf(); 5079 enable_tf(); 5080 5081 enter_guest(); 5082 report_mtf("OUT", (unsigned long) &test_mtf2); 5083 pending_dbg = vmcs_read(GUEST_PENDING_DEBUG); 5084 report(pending_dbg & DR_STEP, 5085 "'pending debug exceptions' field after MTF VM-exit: 0x%lx (expected 0x%lx)", 5086 pending_dbg, (unsigned long) DR_STEP); 5087 5088 disable_mtf(); 5089 disable_tf(); 5090 vmcs_write(GUEST_PENDING_DEBUG, 0); 5091 5092 /* 5093 * #GP exception takes priority over MTF. Expect MTF VM-exit with RIP 5094 * advanced to first instruction of #GP handler. 5095 */ 5096 enter_guest(); 5097 skip_exit_vmcall(); 5098 5099 old_gp = handle_exception(GP_VECTOR, test_mtf_gp_handler); 5100 5101 enable_mtf(); 5102 enter_guest(); 5103 report_mtf("MOV CR3", (unsigned long) get_idt_addr(&boot_idt[GP_VECTOR])); 5104 disable_mtf(); 5105 5106 /* 5107 * Concurrent MTF and privileged software exception (i.e. ICEBP/INT1). 5108 * MTF should follow the delivery of #DB trap, though the SDM doesn't 5109 * provide clear indication of the relative priority. 5110 */ 5111 enter_guest(); 5112 skip_exit_vmcall(); 5113 5114 handle_exception(GP_VECTOR, old_gp); 5115 old_db = handle_exception(DB_VECTOR, test_mtf_db_handler); 5116 5117 enable_mtf(); 5118 enter_guest(); 5119 report_mtf("INT1", (unsigned long) get_idt_addr(&boot_idt[DB_VECTOR])); 5120 disable_mtf(); 5121 5122 enter_guest(); 5123 skip_exit_vmcall(); 5124 handle_exception(DB_VECTOR, old_db); 5125 vmcs_write(ENT_INTR_INFO, INTR_INFO_VALID_MASK | INTR_TYPE_OTHER_EVENT); 5126 enter_guest(); 5127 report_mtf("injected MTF", (unsigned long) &test_mtf4); 5128 enter_guest(); 5129 } 5130 5131 extern char vmx_mtf_pdpte_guest_begin; 5132 extern char vmx_mtf_pdpte_guest_end; 5133 5134 asm("vmx_mtf_pdpte_guest_begin:\n\t" 5135 "mov %cr0, %rax\n\t" /* save CR0 with PG=1 */ 5136 "vmcall\n\t" /* on return from this CR0.PG=0 */ 5137 "mov %rax, %cr0\n\t" /* restore CR0.PG=1 to enter PAE mode */ 5138 "vmcall\n\t" 5139 "retq\n\t" 5140 "vmx_mtf_pdpte_guest_end:"); 5141 5142 static void vmx_mtf_pdpte_test(void) 5143 { 5144 void *test_mtf_pdpte_guest; 5145 pteval_t *pdpt; 5146 u32 guest_ar_cs; 5147 u64 guest_efer; 5148 pteval_t *pte; 5149 u64 guest_cr0; 5150 u64 guest_cr3; 5151 u64 guest_cr4; 5152 u64 ent_ctls; 5153 int i; 5154 5155 if (setup_ept(false)) 5156 return; 5157 5158 if (!(ctrl_cpu_rev[0].clr & CPU_MTF)) { 5159 printf("CPU does not support 'monitor trap flag.'\n"); 5160 return; 5161 } 5162 5163 if (!(ctrl_cpu_rev[1].clr & CPU_URG)) { 5164 printf("CPU does not support 'unrestricted guest.'\n"); 5165 return; 5166 } 5167 5168 vmcs_write(EXC_BITMAP, ~0); 5169 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | CPU_URG); 5170 5171 /* 5172 * Copy the guest code to an identity-mapped page. 5173 */ 5174 test_mtf_pdpte_guest = alloc_page(); 5175 memcpy(test_mtf_pdpte_guest, &vmx_mtf_pdpte_guest_begin, 5176 &vmx_mtf_pdpte_guest_end - &vmx_mtf_pdpte_guest_begin); 5177 5178 test_set_guest(test_mtf_pdpte_guest); 5179 5180 enter_guest(); 5181 skip_exit_vmcall(); 5182 5183 /* 5184 * Put the guest in non-paged 32-bit protected mode, ready to enter 5185 * PAE mode when CR0.PG is set. CR4.PAE will already have been set 5186 * when the guest started out in long mode. 5187 */ 5188 ent_ctls = vmcs_read(ENT_CONTROLS); 5189 vmcs_write(ENT_CONTROLS, ent_ctls & ~ENT_GUEST_64); 5190 5191 guest_efer = vmcs_read(GUEST_EFER); 5192 vmcs_write(GUEST_EFER, guest_efer & ~(EFER_LMA | EFER_LME)); 5193 5194 /* 5195 * Set CS access rights bits for 32-bit protected mode: 5196 * 3:0 B execute/read/accessed 5197 * 4 1 code or data 5198 * 6:5 0 descriptor privilege level 5199 * 7 1 present 5200 * 11:8 0 reserved 5201 * 12 0 available for use by system software 5202 * 13 0 64 bit mode not active 5203 * 14 1 default operation size 32-bit segment 5204 * 15 1 page granularity: segment limit in 4K units 5205 * 16 0 segment usable 5206 * 31:17 0 reserved 5207 */ 5208 guest_ar_cs = vmcs_read(GUEST_AR_CS); 5209 vmcs_write(GUEST_AR_CS, 0xc09b); 5210 5211 guest_cr0 = vmcs_read(GUEST_CR0); 5212 vmcs_write(GUEST_CR0, guest_cr0 & ~X86_CR0_PG); 5213 5214 guest_cr4 = vmcs_read(GUEST_CR4); 5215 vmcs_write(GUEST_CR4, guest_cr4 & ~X86_CR4_PCIDE); 5216 5217 guest_cr3 = vmcs_read(GUEST_CR3); 5218 5219 /* 5220 * Turn the 4-level page table into a PAE page table by following the 0th 5221 * PML4 entry to a PDPT page, and grab the first four PDPTEs from that 5222 * page. 5223 * 5224 * Why does this work? 5225 * 5226 * PAE uses 32-bit addressing which implies: 5227 * Bits 11:0 page offset 5228 * Bits 20:12 entry into 512-entry page table 5229 * Bits 29:21 entry into a 512-entry directory table 5230 * Bits 31:30 entry into the page directory pointer table. 5231 * Bits 63:32 zero 5232 * 5233 * As only 2 bits are needed to select the PDPTEs for the entire 5234 * 32-bit address space, take the first 4 PDPTEs in the level 3 page 5235 * directory pointer table. It doesn't matter which of these PDPTEs 5236 * are present because they must cover the guest code given that it 5237 * has already run successfully. 5238 * 5239 * Get a pointer to PTE for GVA=0 in the page directory pointer table 5240 */ 5241 pte = get_pte_level( 5242 (pgd_t *)phys_to_virt(guest_cr3 & ~X86_CR3_PCID_MASK), 0, 5243 PDPT_LEVEL); 5244 5245 /* 5246 * Need some memory for the 4-entry PAE page directory pointer 5247 * table. Use the end of the identity-mapped page where the guest code 5248 * is stored. There is definitely space as the guest code is only a 5249 * few bytes. 5250 */ 5251 pdpt = test_mtf_pdpte_guest + PAGE_SIZE - 4 * sizeof(pteval_t); 5252 5253 /* 5254 * Copy the first four PDPTEs into the PAE page table with reserved 5255 * bits cleared. Note that permission bits from the PML4E and PDPTE 5256 * are not propagated. 5257 */ 5258 for (i = 0; i < 4; i++) { 5259 TEST_ASSERT_EQ_MSG(0, (pte[i] & PDPTE64_RSVD_MASK), 5260 "PDPTE has invalid reserved bits"); 5261 TEST_ASSERT_EQ_MSG(0, (pte[i] & PDPTE64_PAGE_SIZE_MASK), 5262 "Cannot use 1GB super pages for PAE"); 5263 pdpt[i] = pte[i] & ~(PAE_PDPTE_RSVD_MASK); 5264 } 5265 vmcs_write(GUEST_CR3, virt_to_phys(pdpt)); 5266 5267 enable_mtf(); 5268 enter_guest(); 5269 assert_exit_reason(VMX_MTF); 5270 disable_mtf(); 5271 5272 /* 5273 * The four PDPTEs should have been loaded into the VMCS when 5274 * the guest set CR0.PG to enter PAE mode. 5275 */ 5276 for (i = 0; i < 4; i++) { 5277 u64 pdpte = vmcs_read(GUEST_PDPTE + 2 * i); 5278 5279 report(pdpte == pdpt[i], "PDPTE%d is 0x%lx (expected 0x%lx)", 5280 i, pdpte, pdpt[i]); 5281 } 5282 5283 /* 5284 * Now, try to enter the guest in PAE mode. If the PDPTEs in the 5285 * vmcs are wrong, this will fail. 5286 */ 5287 enter_guest(); 5288 skip_exit_vmcall(); 5289 5290 /* 5291 * Return guest to 64-bit mode and wrap up. 5292 */ 5293 vmcs_write(ENT_CONTROLS, ent_ctls); 5294 vmcs_write(GUEST_EFER, guest_efer); 5295 vmcs_write(GUEST_AR_CS, guest_ar_cs); 5296 vmcs_write(GUEST_CR0, guest_cr0); 5297 vmcs_write(GUEST_CR4, guest_cr4); 5298 vmcs_write(GUEST_CR3, guest_cr3); 5299 5300 enter_guest(); 5301 } 5302 5303 /* 5304 * Tests for VM-execution control fields 5305 */ 5306 static void test_vm_execution_ctls(void) 5307 { 5308 test_pin_based_ctls(); 5309 test_primary_processor_based_ctls(); 5310 test_secondary_processor_based_ctls(); 5311 test_cr3_targets(); 5312 test_io_bitmaps(); 5313 test_msr_bitmap(); 5314 test_apic_ctls(); 5315 test_tpr_threshold(); 5316 test_nmi_ctrls(); 5317 test_pml(); 5318 test_vpid(); 5319 test_ept_eptp(); 5320 test_vmx_preemption_timer(); 5321 } 5322 5323 /* 5324 * The following checks are performed for the VM-entry MSR-load address if 5325 * the VM-entry MSR-load count field is non-zero: 5326 * 5327 * - The lower 4 bits of the VM-entry MSR-load address must be 0. 5328 * The address should not set any bits beyond the processor's 5329 * physical-address width. 5330 * 5331 * - The address of the last byte in the VM-entry MSR-load area 5332 * should not set any bits beyond the processor's physical-address 5333 * width. The address of this last byte is VM-entry MSR-load address 5334 * + (MSR count * 16) - 1. (The arithmetic used for the computation 5335 * uses more bits than the processor's physical-address width.) 5336 * 5337 * 5338 * [Intel SDM] 5339 */ 5340 static void test_entry_msr_load(void) 5341 { 5342 entry_msr_load = alloc_page(); 5343 u64 tmp; 5344 u32 entry_msr_ld_cnt = 1; 5345 int i; 5346 u32 addr_len = 64; 5347 5348 vmcs_write(ENT_MSR_LD_CNT, entry_msr_ld_cnt); 5349 5350 /* Check first 4 bits of VM-entry MSR-load address */ 5351 for (i = 0; i < 4; i++) { 5352 tmp = (u64)entry_msr_load | 1ull << i; 5353 vmcs_write(ENTER_MSR_LD_ADDR, tmp); 5354 report_prefix_pushf("VM-entry MSR-load addr [4:0] %lx", 5355 tmp & 0xf); 5356 test_vmx_invalid_controls(); 5357 report_prefix_pop(); 5358 } 5359 5360 if (basic.val & (1ul << 48)) 5361 addr_len = 32; 5362 5363 test_vmcs_addr_values("VM-entry-MSR-load address", 5364 ENTER_MSR_LD_ADDR, 16, false, false, 5365 4, addr_len - 1); 5366 5367 /* 5368 * Check last byte of VM-entry MSR-load address 5369 */ 5370 entry_msr_load = (struct vmx_msr_entry *)((u64)entry_msr_load & ~0xf); 5371 5372 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 5373 i < 64; i++) { 5374 tmp = ((u64)entry_msr_load + entry_msr_ld_cnt * 16 - 1) | 5375 1ul << i; 5376 vmcs_write(ENTER_MSR_LD_ADDR, 5377 tmp - (entry_msr_ld_cnt * 16 - 1)); 5378 test_vmx_invalid_controls(); 5379 } 5380 5381 vmcs_write(ENT_MSR_LD_CNT, 2); 5382 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 5383 test_vmx_invalid_controls(); 5384 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 5385 test_vmx_valid_controls(); 5386 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 5387 test_vmx_valid_controls(); 5388 } 5389 5390 static struct vmx_state_area_test_data { 5391 u32 msr; 5392 u64 exp; 5393 bool enabled; 5394 } vmx_state_area_test_data; 5395 5396 static void guest_state_test_main(void) 5397 { 5398 u64 obs; 5399 struct vmx_state_area_test_data *data = &vmx_state_area_test_data; 5400 5401 while (1) { 5402 if (vmx_get_test_stage() == 2) 5403 break; 5404 5405 if (data->enabled) { 5406 obs = rdmsr(data->msr); 5407 report(data->exp == obs, 5408 "Guest state is 0x%lx (expected 0x%lx)", 5409 obs, data->exp); 5410 } 5411 5412 vmcall(); 5413 } 5414 5415 asm volatile("fnop"); 5416 } 5417 5418 static void test_guest_state(const char *test, bool xfail, u64 field, 5419 const char * field_name) 5420 { 5421 struct vmentry_result result; 5422 u8 abort_flags; 5423 5424 abort_flags = ABORT_ON_EARLY_VMENTRY_FAIL; 5425 if (!xfail) 5426 abort_flags = ABORT_ON_INVALID_GUEST_STATE; 5427 5428 __enter_guest(abort_flags, &result); 5429 5430 report(result.exit_reason.failed_vmentry == xfail && 5431 ((xfail && result.exit_reason.basic == VMX_FAIL_STATE) || 5432 (!xfail && result.exit_reason.basic == VMX_VMCALL)) && 5433 (!xfail || vmcs_read(EXI_QUALIFICATION) == ENTRY_FAIL_DEFAULT), 5434 "%s, %s = %lx", test, field_name, field); 5435 5436 if (!result.exit_reason.failed_vmentry) 5437 skip_exit_insn(); 5438 } 5439 5440 /* 5441 * Tests for VM-entry control fields 5442 */ 5443 static void test_vm_entry_ctls(void) 5444 { 5445 test_invalid_event_injection(); 5446 test_entry_msr_load(); 5447 } 5448 5449 /* 5450 * The following checks are performed for the VM-exit MSR-store address if 5451 * the VM-exit MSR-store count field is non-zero: 5452 * 5453 * - The lower 4 bits of the VM-exit MSR-store address must be 0. 5454 * The address should not set any bits beyond the processor's 5455 * physical-address width. 5456 * 5457 * - The address of the last byte in the VM-exit MSR-store area 5458 * should not set any bits beyond the processor's physical-address 5459 * width. The address of this last byte is VM-exit MSR-store address 5460 * + (MSR count * 16) - 1. (The arithmetic used for the computation 5461 * uses more bits than the processor's physical-address width.) 5462 * 5463 * If IA32_VMX_BASIC[48] is read as 1, neither address should set any bits 5464 * in the range 63:32. 5465 * 5466 * [Intel SDM] 5467 */ 5468 static void test_exit_msr_store(void) 5469 { 5470 exit_msr_store = alloc_page(); 5471 u64 tmp; 5472 u32 exit_msr_st_cnt = 1; 5473 int i; 5474 u32 addr_len = 64; 5475 5476 vmcs_write(EXI_MSR_ST_CNT, exit_msr_st_cnt); 5477 5478 /* Check first 4 bits of VM-exit MSR-store address */ 5479 for (i = 0; i < 4; i++) { 5480 tmp = (u64)exit_msr_store | 1ull << i; 5481 vmcs_write(EXIT_MSR_ST_ADDR, tmp); 5482 report_prefix_pushf("VM-exit MSR-store addr [4:0] %lx", 5483 tmp & 0xf); 5484 test_vmx_invalid_controls(); 5485 report_prefix_pop(); 5486 } 5487 5488 if (basic.val & (1ul << 48)) 5489 addr_len = 32; 5490 5491 test_vmcs_addr_values("VM-exit-MSR-store address", 5492 EXIT_MSR_ST_ADDR, 16, false, false, 5493 4, addr_len - 1); 5494 5495 /* 5496 * Check last byte of VM-exit MSR-store address 5497 */ 5498 exit_msr_store = (struct vmx_msr_entry *)((u64)exit_msr_store & ~0xf); 5499 5500 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 5501 i < 64; i++) { 5502 tmp = ((u64)exit_msr_store + exit_msr_st_cnt * 16 - 1) | 5503 1ul << i; 5504 vmcs_write(EXIT_MSR_ST_ADDR, 5505 tmp - (exit_msr_st_cnt * 16 - 1)); 5506 test_vmx_invalid_controls(); 5507 } 5508 5509 vmcs_write(EXI_MSR_ST_CNT, 2); 5510 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 5511 test_vmx_invalid_controls(); 5512 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 5513 test_vmx_valid_controls(); 5514 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 5515 test_vmx_valid_controls(); 5516 } 5517 5518 /* 5519 * Tests for VM-exit controls 5520 */ 5521 static void test_vm_exit_ctls(void) 5522 { 5523 test_exit_msr_store(); 5524 } 5525 5526 /* 5527 * Check that the virtual CPU checks all of the VMX controls as 5528 * documented in the Intel SDM. 5529 */ 5530 static void vmx_controls_test(void) 5531 { 5532 /* 5533 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 5534 * fail due to invalid guest state, should we make it that 5535 * far. 5536 */ 5537 vmcs_write(GUEST_RFLAGS, 0); 5538 5539 test_vm_execution_ctls(); 5540 test_vm_exit_ctls(); 5541 test_vm_entry_ctls(); 5542 } 5543 5544 struct apic_reg_virt_config { 5545 bool apic_register_virtualization; 5546 bool use_tpr_shadow; 5547 bool virtualize_apic_accesses; 5548 bool virtualize_x2apic_mode; 5549 bool activate_secondary_controls; 5550 }; 5551 5552 struct apic_reg_test { 5553 const char *name; 5554 struct apic_reg_virt_config apic_reg_virt_config; 5555 }; 5556 5557 struct apic_reg_virt_expectation { 5558 enum Reason rd_exit_reason; 5559 enum Reason wr_exit_reason; 5560 u32 val; 5561 u32 (*virt_fn)(u32); 5562 5563 /* 5564 * If false, accessing the APIC access address from L2 is treated as a 5565 * normal memory operation, rather than triggering virtualization. 5566 */ 5567 bool virtualize_apic_accesses; 5568 }; 5569 5570 static u32 apic_virt_identity(u32 val) 5571 { 5572 return val; 5573 } 5574 5575 static u32 apic_virt_nibble1(u32 val) 5576 { 5577 return val & 0xf0; 5578 } 5579 5580 static u32 apic_virt_byte3(u32 val) 5581 { 5582 return val & (0xff << 24); 5583 } 5584 5585 static bool apic_reg_virt_exit_expectation( 5586 u32 reg, struct apic_reg_virt_config *config, 5587 struct apic_reg_virt_expectation *expectation) 5588 { 5589 /* Good configs, where some L2 APIC accesses are virtualized. */ 5590 bool virtualize_apic_accesses_only = 5591 config->virtualize_apic_accesses && 5592 !config->use_tpr_shadow && 5593 !config->apic_register_virtualization && 5594 !config->virtualize_x2apic_mode && 5595 config->activate_secondary_controls; 5596 bool virtualize_apic_accesses_and_use_tpr_shadow = 5597 config->virtualize_apic_accesses && 5598 config->use_tpr_shadow && 5599 !config->apic_register_virtualization && 5600 !config->virtualize_x2apic_mode && 5601 config->activate_secondary_controls; 5602 bool apic_register_virtualization = 5603 config->virtualize_apic_accesses && 5604 config->use_tpr_shadow && 5605 config->apic_register_virtualization && 5606 !config->virtualize_x2apic_mode && 5607 config->activate_secondary_controls; 5608 5609 expectation->val = MAGIC_VAL_1; 5610 expectation->virt_fn = apic_virt_identity; 5611 expectation->virtualize_apic_accesses = 5612 config->virtualize_apic_accesses && 5613 config->activate_secondary_controls; 5614 if (virtualize_apic_accesses_only) { 5615 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5616 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5617 } else if (virtualize_apic_accesses_and_use_tpr_shadow) { 5618 switch (reg) { 5619 case APIC_TASKPRI: 5620 expectation->rd_exit_reason = VMX_VMCALL; 5621 expectation->wr_exit_reason = VMX_VMCALL; 5622 expectation->virt_fn = apic_virt_nibble1; 5623 break; 5624 default: 5625 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5626 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5627 } 5628 } else if (apic_register_virtualization) { 5629 expectation->rd_exit_reason = VMX_VMCALL; 5630 5631 switch (reg) { 5632 case APIC_ID: 5633 case APIC_EOI: 5634 case APIC_LDR: 5635 case APIC_DFR: 5636 case APIC_SPIV: 5637 case APIC_ESR: 5638 case APIC_ICR: 5639 case APIC_LVTT: 5640 case APIC_LVTTHMR: 5641 case APIC_LVTPC: 5642 case APIC_LVT0: 5643 case APIC_LVT1: 5644 case APIC_LVTERR: 5645 case APIC_TMICT: 5646 case APIC_TDCR: 5647 expectation->wr_exit_reason = VMX_APIC_WRITE; 5648 break; 5649 case APIC_LVR: 5650 case APIC_ISR ... APIC_ISR + 0x70: 5651 case APIC_TMR ... APIC_TMR + 0x70: 5652 case APIC_IRR ... APIC_IRR + 0x70: 5653 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5654 break; 5655 case APIC_TASKPRI: 5656 expectation->wr_exit_reason = VMX_VMCALL; 5657 expectation->virt_fn = apic_virt_nibble1; 5658 break; 5659 case APIC_ICR2: 5660 expectation->wr_exit_reason = VMX_VMCALL; 5661 expectation->virt_fn = apic_virt_byte3; 5662 break; 5663 default: 5664 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5665 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5666 } 5667 } else if (!expectation->virtualize_apic_accesses) { 5668 /* 5669 * No APIC registers are directly virtualized. This includes 5670 * VTPR, which can be virtualized through MOV to/from CR8 via 5671 * the use TPR shadow control, but not through directly 5672 * accessing VTPR. 5673 */ 5674 expectation->rd_exit_reason = VMX_VMCALL; 5675 expectation->wr_exit_reason = VMX_VMCALL; 5676 } else { 5677 printf("Cannot parse APIC register virtualization config:\n" 5678 "\tvirtualize_apic_accesses: %d\n" 5679 "\tuse_tpr_shadow: %d\n" 5680 "\tapic_register_virtualization: %d\n" 5681 "\tvirtualize_x2apic_mode: %d\n" 5682 "\tactivate_secondary_controls: %d\n", 5683 config->virtualize_apic_accesses, 5684 config->use_tpr_shadow, 5685 config->apic_register_virtualization, 5686 config->virtualize_x2apic_mode, 5687 config->activate_secondary_controls); 5688 5689 return false; 5690 } 5691 5692 return true; 5693 } 5694 5695 struct apic_reg_test apic_reg_tests[] = { 5696 /* Good configs, where some L2 APIC accesses are virtualized. */ 5697 { 5698 .name = "Virtualize APIC accesses", 5699 .apic_reg_virt_config = { 5700 .virtualize_apic_accesses = true, 5701 .use_tpr_shadow = false, 5702 .apic_register_virtualization = false, 5703 .virtualize_x2apic_mode = false, 5704 .activate_secondary_controls = true, 5705 }, 5706 }, 5707 { 5708 .name = "Virtualize APIC accesses + Use TPR shadow", 5709 .apic_reg_virt_config = { 5710 .virtualize_apic_accesses = true, 5711 .use_tpr_shadow = true, 5712 .apic_register_virtualization = false, 5713 .virtualize_x2apic_mode = false, 5714 .activate_secondary_controls = true, 5715 }, 5716 }, 5717 { 5718 .name = "APIC-register virtualization", 5719 .apic_reg_virt_config = { 5720 .virtualize_apic_accesses = true, 5721 .use_tpr_shadow = true, 5722 .apic_register_virtualization = true, 5723 .virtualize_x2apic_mode = false, 5724 .activate_secondary_controls = true, 5725 }, 5726 }, 5727 5728 /* 5729 * Test that the secondary processor-based VM-execution controls are 5730 * correctly ignored when "activate secondary controls" is disabled. 5731 */ 5732 { 5733 .name = "Activate secondary controls off", 5734 .apic_reg_virt_config = { 5735 .virtualize_apic_accesses = true, 5736 .use_tpr_shadow = false, 5737 .apic_register_virtualization = true, 5738 .virtualize_x2apic_mode = true, 5739 .activate_secondary_controls = false, 5740 }, 5741 }, 5742 { 5743 .name = "Activate secondary controls off + Use TPR shadow", 5744 .apic_reg_virt_config = { 5745 .virtualize_apic_accesses = true, 5746 .use_tpr_shadow = true, 5747 .apic_register_virtualization = true, 5748 .virtualize_x2apic_mode = true, 5749 .activate_secondary_controls = false, 5750 }, 5751 }, 5752 5753 /* 5754 * Test that the APIC access address is treated like an arbitrary memory 5755 * address when "virtualize APIC accesses" is disabled. 5756 */ 5757 { 5758 .name = "Virtualize APIC accesses off + Use TPR shadow", 5759 .apic_reg_virt_config = { 5760 .virtualize_apic_accesses = false, 5761 .use_tpr_shadow = true, 5762 .apic_register_virtualization = true, 5763 .virtualize_x2apic_mode = true, 5764 .activate_secondary_controls = true, 5765 }, 5766 }, 5767 5768 /* 5769 * Test that VM entry fails due to invalid controls when 5770 * "APIC-register virtualization" is enabled while "use TPR shadow" is 5771 * disabled. 5772 */ 5773 { 5774 .name = "APIC-register virtualization + Use TPR shadow off", 5775 .apic_reg_virt_config = { 5776 .virtualize_apic_accesses = true, 5777 .use_tpr_shadow = false, 5778 .apic_register_virtualization = true, 5779 .virtualize_x2apic_mode = false, 5780 .activate_secondary_controls = true, 5781 }, 5782 }, 5783 5784 /* 5785 * Test that VM entry fails due to invalid controls when 5786 * "Virtualize x2APIC mode" is enabled while "use TPR shadow" is 5787 * disabled. 5788 */ 5789 { 5790 .name = "Virtualize x2APIC mode + Use TPR shadow off", 5791 .apic_reg_virt_config = { 5792 .virtualize_apic_accesses = false, 5793 .use_tpr_shadow = false, 5794 .apic_register_virtualization = false, 5795 .virtualize_x2apic_mode = true, 5796 .activate_secondary_controls = true, 5797 }, 5798 }, 5799 { 5800 .name = "Virtualize x2APIC mode + Use TPR shadow off v2", 5801 .apic_reg_virt_config = { 5802 .virtualize_apic_accesses = false, 5803 .use_tpr_shadow = false, 5804 .apic_register_virtualization = true, 5805 .virtualize_x2apic_mode = true, 5806 .activate_secondary_controls = true, 5807 }, 5808 }, 5809 5810 /* 5811 * Test that VM entry fails due to invalid controls when 5812 * "virtualize x2APIC mode" is enabled while "virtualize APIC accesses" 5813 * is enabled. 5814 */ 5815 { 5816 .name = "Virtualize x2APIC mode + Virtualize APIC accesses", 5817 .apic_reg_virt_config = { 5818 .virtualize_apic_accesses = true, 5819 .use_tpr_shadow = true, 5820 .apic_register_virtualization = false, 5821 .virtualize_x2apic_mode = true, 5822 .activate_secondary_controls = true, 5823 }, 5824 }, 5825 { 5826 .name = "Virtualize x2APIC mode + Virtualize APIC accesses v2", 5827 .apic_reg_virt_config = { 5828 .virtualize_apic_accesses = true, 5829 .use_tpr_shadow = true, 5830 .apic_register_virtualization = true, 5831 .virtualize_x2apic_mode = true, 5832 .activate_secondary_controls = true, 5833 }, 5834 }, 5835 }; 5836 5837 enum Apic_op { 5838 APIC_OP_XAPIC_RD, 5839 APIC_OP_XAPIC_WR, 5840 TERMINATE, 5841 }; 5842 5843 static u32 vmx_xapic_read(u32 *apic_access_address, u32 reg) 5844 { 5845 return *(volatile u32 *)((uintptr_t)apic_access_address + reg); 5846 } 5847 5848 static void vmx_xapic_write(u32 *apic_access_address, u32 reg, u32 val) 5849 { 5850 *(volatile u32 *)((uintptr_t)apic_access_address + reg) = val; 5851 } 5852 5853 struct apic_reg_virt_guest_args { 5854 enum Apic_op op; 5855 u32 *apic_access_address; 5856 u32 reg; 5857 u32 val; 5858 bool check_rd; 5859 u32 (*virt_fn)(u32); 5860 } apic_reg_virt_guest_args; 5861 5862 static void apic_reg_virt_guest(void) 5863 { 5864 volatile struct apic_reg_virt_guest_args *args = 5865 &apic_reg_virt_guest_args; 5866 5867 for (;;) { 5868 enum Apic_op op = args->op; 5869 u32 *apic_access_address = args->apic_access_address; 5870 u32 reg = args->reg; 5871 u32 val = args->val; 5872 bool check_rd = args->check_rd; 5873 u32 (*virt_fn)(u32) = args->virt_fn; 5874 5875 if (op == TERMINATE) 5876 break; 5877 5878 if (op == APIC_OP_XAPIC_RD) { 5879 u32 ret = vmx_xapic_read(apic_access_address, reg); 5880 5881 if (check_rd) { 5882 u32 want = virt_fn(val); 5883 u32 got = virt_fn(ret); 5884 5885 report(got == want, 5886 "read 0x%x, expected 0x%x.", got, want); 5887 } 5888 } else if (op == APIC_OP_XAPIC_WR) { 5889 vmx_xapic_write(apic_access_address, reg, val); 5890 } 5891 5892 /* 5893 * The L1 should always execute a vmcall after it's done testing 5894 * an individual APIC operation. This helps to validate that the 5895 * L1 and L2 are in sync with each other, as expected. 5896 */ 5897 vmcall(); 5898 } 5899 } 5900 5901 static void test_xapic_rd( 5902 u32 reg, struct apic_reg_virt_expectation *expectation, 5903 u32 *apic_access_address, u32 *virtual_apic_page) 5904 { 5905 u32 val = expectation->val; 5906 u32 exit_reason_want = expectation->rd_exit_reason; 5907 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 5908 5909 report_prefix_pushf("xapic - reading 0x%03x", reg); 5910 5911 /* Configure guest to do an xapic read */ 5912 args->op = APIC_OP_XAPIC_RD; 5913 args->apic_access_address = apic_access_address; 5914 args->reg = reg; 5915 args->val = val; 5916 args->check_rd = exit_reason_want == VMX_VMCALL; 5917 args->virt_fn = expectation->virt_fn; 5918 5919 /* Setup virtual APIC page */ 5920 if (!expectation->virtualize_apic_accesses) { 5921 apic_access_address[apic_reg_index(reg)] = val; 5922 virtual_apic_page[apic_reg_index(reg)] = 0; 5923 } else if (exit_reason_want == VMX_VMCALL) { 5924 apic_access_address[apic_reg_index(reg)] = 0; 5925 virtual_apic_page[apic_reg_index(reg)] = val; 5926 } 5927 5928 /* Enter guest */ 5929 enter_guest(); 5930 5931 /* 5932 * Validate the behavior and 5933 * pass a magic value back to the guest. 5934 */ 5935 if (exit_reason_want == VMX_APIC_ACCESS) { 5936 u32 apic_page_offset = vmcs_read(EXI_QUALIFICATION) & 0xfff; 5937 5938 assert_exit_reason(exit_reason_want); 5939 report(apic_page_offset == reg, 5940 "got APIC access exit @ page offset 0x%03x, want 0x%03x", 5941 apic_page_offset, reg); 5942 skip_exit_insn(); 5943 5944 /* Reenter guest so it can consume/check rcx and exit again. */ 5945 enter_guest(); 5946 } else if (exit_reason_want != VMX_VMCALL) { 5947 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 5948 } 5949 5950 skip_exit_vmcall(); 5951 report_prefix_pop(); 5952 } 5953 5954 static void test_xapic_wr( 5955 u32 reg, struct apic_reg_virt_expectation *expectation, 5956 u32 *apic_access_address, u32 *virtual_apic_page) 5957 { 5958 u32 val = expectation->val; 5959 u32 exit_reason_want = expectation->wr_exit_reason; 5960 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 5961 bool virtualized = 5962 expectation->virtualize_apic_accesses && 5963 (exit_reason_want == VMX_APIC_WRITE || 5964 exit_reason_want == VMX_VMCALL); 5965 bool checked = false; 5966 5967 report_prefix_pushf("xapic - writing 0x%x to 0x%03x", val, reg); 5968 5969 /* Configure guest to do an xapic read */ 5970 args->op = APIC_OP_XAPIC_WR; 5971 args->apic_access_address = apic_access_address; 5972 args->reg = reg; 5973 args->val = val; 5974 5975 /* Setup virtual APIC page */ 5976 if (virtualized || !expectation->virtualize_apic_accesses) { 5977 apic_access_address[apic_reg_index(reg)] = 0; 5978 virtual_apic_page[apic_reg_index(reg)] = 0; 5979 } 5980 5981 /* Enter guest */ 5982 enter_guest(); 5983 5984 /* 5985 * Validate the behavior and 5986 * pass a magic value back to the guest. 5987 */ 5988 if (exit_reason_want == VMX_APIC_ACCESS) { 5989 u32 apic_page_offset = vmcs_read(EXI_QUALIFICATION) & 0xfff; 5990 5991 assert_exit_reason(exit_reason_want); 5992 report(apic_page_offset == reg, 5993 "got APIC access exit @ page offset 0x%03x, want 0x%03x", 5994 apic_page_offset, reg); 5995 skip_exit_insn(); 5996 5997 /* Reenter guest so it can consume/check rcx and exit again. */ 5998 enter_guest(); 5999 } else if (exit_reason_want == VMX_APIC_WRITE) { 6000 assert_exit_reason(exit_reason_want); 6001 report(virtual_apic_page[apic_reg_index(reg)] == val, 6002 "got APIC write exit @ page offset 0x%03x; val is 0x%x, want 0x%x", 6003 apic_reg_index(reg), 6004 virtual_apic_page[apic_reg_index(reg)], val); 6005 checked = true; 6006 6007 /* Reenter guest so it can consume/check rcx and exit again. */ 6008 enter_guest(); 6009 } else if (exit_reason_want != VMX_VMCALL) { 6010 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 6011 } 6012 6013 assert_exit_reason(VMX_VMCALL); 6014 if (virtualized && !checked) { 6015 u32 want = expectation->virt_fn(val); 6016 u32 got = virtual_apic_page[apic_reg_index(reg)]; 6017 got = expectation->virt_fn(got); 6018 6019 report(got == want, "exitless write; val is 0x%x, want 0x%x", 6020 got, want); 6021 } else if (!expectation->virtualize_apic_accesses && !checked) { 6022 u32 got = apic_access_address[apic_reg_index(reg)]; 6023 6024 report(got == val, 6025 "non-virtualized write; val is 0x%x, want 0x%x", got, 6026 val); 6027 } else if (!expectation->virtualize_apic_accesses && checked) { 6028 report_fail("Non-virtualized write was prematurely checked!"); 6029 } 6030 6031 skip_exit_vmcall(); 6032 report_prefix_pop(); 6033 } 6034 6035 enum Config_type { 6036 CONFIG_TYPE_GOOD, 6037 CONFIG_TYPE_UNSUPPORTED, 6038 CONFIG_TYPE_VMENTRY_FAILS_EARLY, 6039 }; 6040 6041 static enum Config_type configure_apic_reg_virt_test( 6042 struct apic_reg_virt_config *apic_reg_virt_config) 6043 { 6044 u32 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6045 u32 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6046 /* Configs where L2 entry fails early, due to invalid controls. */ 6047 bool use_tpr_shadow_incorrectly_off = 6048 !apic_reg_virt_config->use_tpr_shadow && 6049 (apic_reg_virt_config->apic_register_virtualization || 6050 apic_reg_virt_config->virtualize_x2apic_mode) && 6051 apic_reg_virt_config->activate_secondary_controls; 6052 bool virtualize_apic_accesses_incorrectly_on = 6053 apic_reg_virt_config->virtualize_apic_accesses && 6054 apic_reg_virt_config->virtualize_x2apic_mode && 6055 apic_reg_virt_config->activate_secondary_controls; 6056 bool vmentry_fails_early = 6057 use_tpr_shadow_incorrectly_off || 6058 virtualize_apic_accesses_incorrectly_on; 6059 6060 if (apic_reg_virt_config->activate_secondary_controls) { 6061 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 6062 printf("VM-execution control \"activate secondary controls\" NOT supported.\n"); 6063 return CONFIG_TYPE_UNSUPPORTED; 6064 } 6065 cpu_exec_ctrl0 |= CPU_SECONDARY; 6066 } else { 6067 cpu_exec_ctrl0 &= ~CPU_SECONDARY; 6068 } 6069 6070 if (apic_reg_virt_config->virtualize_apic_accesses) { 6071 if (!(ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES)) { 6072 printf("VM-execution control \"virtualize APIC accesses\" NOT supported.\n"); 6073 return CONFIG_TYPE_UNSUPPORTED; 6074 } 6075 cpu_exec_ctrl1 |= CPU_VIRT_APIC_ACCESSES; 6076 } else { 6077 cpu_exec_ctrl1 &= ~CPU_VIRT_APIC_ACCESSES; 6078 } 6079 6080 if (apic_reg_virt_config->use_tpr_shadow) { 6081 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) { 6082 printf("VM-execution control \"use TPR shadow\" NOT supported.\n"); 6083 return CONFIG_TYPE_UNSUPPORTED; 6084 } 6085 cpu_exec_ctrl0 |= CPU_TPR_SHADOW; 6086 } else { 6087 cpu_exec_ctrl0 &= ~CPU_TPR_SHADOW; 6088 } 6089 6090 if (apic_reg_virt_config->apic_register_virtualization) { 6091 if (!(ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT)) { 6092 printf("VM-execution control \"APIC-register virtualization\" NOT supported.\n"); 6093 return CONFIG_TYPE_UNSUPPORTED; 6094 } 6095 cpu_exec_ctrl1 |= CPU_APIC_REG_VIRT; 6096 } else { 6097 cpu_exec_ctrl1 &= ~CPU_APIC_REG_VIRT; 6098 } 6099 6100 if (apic_reg_virt_config->virtualize_x2apic_mode) { 6101 if (!(ctrl_cpu_rev[1].clr & CPU_VIRT_X2APIC)) { 6102 printf("VM-execution control \"virtualize x2APIC mode\" NOT supported.\n"); 6103 return CONFIG_TYPE_UNSUPPORTED; 6104 } 6105 cpu_exec_ctrl1 |= CPU_VIRT_X2APIC; 6106 } else { 6107 cpu_exec_ctrl1 &= ~CPU_VIRT_X2APIC; 6108 } 6109 6110 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6111 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6112 6113 if (vmentry_fails_early) 6114 return CONFIG_TYPE_VMENTRY_FAILS_EARLY; 6115 6116 return CONFIG_TYPE_GOOD; 6117 } 6118 6119 static bool cpu_has_apicv(void) 6120 { 6121 return ((ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT) && 6122 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 6123 (ctrl_pin_rev.clr & PIN_POST_INTR)); 6124 } 6125 6126 /* Validates APIC register access across valid virtualization configurations. */ 6127 static void apic_reg_virt_test(void) 6128 { 6129 u32 *apic_access_address; 6130 u32 *virtual_apic_page; 6131 u64 control; 6132 u64 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6133 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6134 int i; 6135 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 6136 6137 if (!cpu_has_apicv()) { 6138 report_skip(__func__); 6139 return; 6140 } 6141 6142 control = cpu_exec_ctrl1; 6143 control &= ~CPU_VINTD; 6144 vmcs_write(CPU_EXEC_CTRL1, control); 6145 6146 test_set_guest(apic_reg_virt_guest); 6147 6148 /* 6149 * From the SDM: The 1-setting of the "virtualize APIC accesses" 6150 * VM-execution is guaranteed to apply only if translations to the 6151 * APIC-access address use a 4-KByte page. 6152 */ 6153 apic_access_address = alloc_page(); 6154 force_4k_page(apic_access_address); 6155 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_address)); 6156 6157 virtual_apic_page = alloc_page(); 6158 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 6159 6160 for (i = 0; i < ARRAY_SIZE(apic_reg_tests); i++) { 6161 struct apic_reg_test *apic_reg_test = &apic_reg_tests[i]; 6162 struct apic_reg_virt_config *apic_reg_virt_config = 6163 &apic_reg_test->apic_reg_virt_config; 6164 enum Config_type config_type; 6165 u32 reg; 6166 6167 printf("--- %s test ---\n", apic_reg_test->name); 6168 config_type = 6169 configure_apic_reg_virt_test(apic_reg_virt_config); 6170 if (config_type == CONFIG_TYPE_UNSUPPORTED) { 6171 printf("Skip because of missing features.\n"); 6172 continue; 6173 } 6174 6175 if (config_type == CONFIG_TYPE_VMENTRY_FAILS_EARLY) { 6176 enter_guest_with_bad_controls(); 6177 continue; 6178 } 6179 6180 for (reg = 0; reg < PAGE_SIZE / sizeof(u32); reg += 0x10) { 6181 struct apic_reg_virt_expectation expectation = {}; 6182 bool ok; 6183 6184 ok = apic_reg_virt_exit_expectation( 6185 reg, apic_reg_virt_config, &expectation); 6186 if (!ok) { 6187 report_fail("Malformed test."); 6188 break; 6189 } 6190 6191 test_xapic_rd(reg, &expectation, apic_access_address, 6192 virtual_apic_page); 6193 test_xapic_wr(reg, &expectation, apic_access_address, 6194 virtual_apic_page); 6195 } 6196 } 6197 6198 /* Terminate the guest */ 6199 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6200 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6201 args->op = TERMINATE; 6202 enter_guest(); 6203 assert_exit_reason(VMX_VMCALL); 6204 } 6205 6206 struct virt_x2apic_mode_config { 6207 struct apic_reg_virt_config apic_reg_virt_config; 6208 bool virtual_interrupt_delivery; 6209 bool use_msr_bitmaps; 6210 bool disable_x2apic_msr_intercepts; 6211 bool disable_x2apic; 6212 }; 6213 6214 struct virt_x2apic_mode_test_case { 6215 const char *name; 6216 struct virt_x2apic_mode_config virt_x2apic_mode_config; 6217 }; 6218 6219 enum Virt_x2apic_mode_behavior_type { 6220 X2APIC_ACCESS_VIRTUALIZED, 6221 X2APIC_ACCESS_PASSED_THROUGH, 6222 X2APIC_ACCESS_TRIGGERS_GP, 6223 }; 6224 6225 struct virt_x2apic_mode_expectation { 6226 enum Reason rd_exit_reason; 6227 enum Reason wr_exit_reason; 6228 6229 /* 6230 * RDMSR and WRMSR handle 64-bit values. However, except for ICR, all of 6231 * the x2APIC registers are 32 bits. Notice: 6232 * 1. vmx_x2apic_read() clears the upper 32 bits for 32-bit registers. 6233 * 2. vmx_x2apic_write() expects the val arg to be well-formed. 6234 */ 6235 u64 rd_val; 6236 u64 wr_val; 6237 6238 /* 6239 * Compares input to virtualized output; 6240 * 1st arg is pointer to return expected virtualization output. 6241 */ 6242 u64 (*virt_fn)(u64); 6243 6244 enum Virt_x2apic_mode_behavior_type rd_behavior; 6245 enum Virt_x2apic_mode_behavior_type wr_behavior; 6246 bool wr_only; 6247 }; 6248 6249 static u64 virt_x2apic_mode_identity(u64 val) 6250 { 6251 return val; 6252 } 6253 6254 static u64 virt_x2apic_mode_nibble1(u64 val) 6255 { 6256 return val & 0xf0; 6257 } 6258 6259 static void virt_x2apic_mode_rd_expectation( 6260 u32 reg, bool virt_x2apic_mode_on, bool disable_x2apic, 6261 bool apic_register_virtualization, bool virtual_interrupt_delivery, 6262 struct virt_x2apic_mode_expectation *expectation) 6263 { 6264 bool readable = 6265 !x2apic_reg_reserved(reg) && 6266 reg != APIC_EOI; 6267 6268 expectation->rd_exit_reason = VMX_VMCALL; 6269 expectation->virt_fn = virt_x2apic_mode_identity; 6270 if (virt_x2apic_mode_on && apic_register_virtualization) { 6271 expectation->rd_val = MAGIC_VAL_1; 6272 if (reg == APIC_PROCPRI && virtual_interrupt_delivery) 6273 expectation->virt_fn = virt_x2apic_mode_nibble1; 6274 else if (reg == APIC_TASKPRI) 6275 expectation->virt_fn = virt_x2apic_mode_nibble1; 6276 expectation->rd_behavior = X2APIC_ACCESS_VIRTUALIZED; 6277 } else if (virt_x2apic_mode_on && !apic_register_virtualization && 6278 reg == APIC_TASKPRI) { 6279 expectation->rd_val = MAGIC_VAL_1; 6280 expectation->virt_fn = virt_x2apic_mode_nibble1; 6281 expectation->rd_behavior = X2APIC_ACCESS_VIRTUALIZED; 6282 } else if (!disable_x2apic && readable) { 6283 expectation->rd_val = apic_read(reg); 6284 expectation->rd_behavior = X2APIC_ACCESS_PASSED_THROUGH; 6285 } else { 6286 expectation->rd_behavior = X2APIC_ACCESS_TRIGGERS_GP; 6287 } 6288 } 6289 6290 /* 6291 * get_x2apic_wr_val() creates an innocuous write value for an x2APIC register. 6292 * 6293 * For writable registers, get_x2apic_wr_val() deposits the write value into the 6294 * val pointer arg and returns true. For non-writable registers, val is not 6295 * modified and get_x2apic_wr_val() returns false. 6296 */ 6297 static bool get_x2apic_wr_val(u32 reg, u64 *val) 6298 { 6299 switch (reg) { 6300 case APIC_TASKPRI: 6301 /* Bits 31:8 are reserved. */ 6302 *val &= 0xff; 6303 break; 6304 case APIC_EOI: 6305 case APIC_ESR: 6306 case APIC_TMICT: 6307 /* 6308 * EOI, ESR: WRMSR of a non-zero value causes #GP(0). 6309 * TMICT: A write of 0 to the initial-count register effectively 6310 * stops the local APIC timer, in both one-shot and 6311 * periodic mode. 6312 */ 6313 *val = 0; 6314 break; 6315 case APIC_SPIV: 6316 case APIC_LVTT: 6317 case APIC_LVTTHMR: 6318 case APIC_LVTPC: 6319 case APIC_LVT0: 6320 case APIC_LVT1: 6321 case APIC_LVTERR: 6322 case APIC_TDCR: 6323 /* 6324 * To avoid writing a 1 to a reserved bit or causing some other 6325 * unintended side effect, read the current value and use it as 6326 * the write value. 6327 */ 6328 *val = apic_read(reg); 6329 break; 6330 case APIC_CMCI: 6331 if (!apic_lvt_entry_supported(6)) 6332 return false; 6333 *val = apic_read(reg); 6334 break; 6335 case APIC_ICR: 6336 *val = 0x40000 | 0xf1; 6337 break; 6338 case APIC_SELF_IPI: 6339 /* 6340 * With special processing (i.e., virtualize x2APIC mode + 6341 * virtual interrupt delivery), writing zero causes an 6342 * APIC-write VM exit. We plan to add a test for enabling 6343 * "virtual-interrupt delivery" in VMCS12, and that's where we 6344 * will test a self IPI with special processing. 6345 */ 6346 *val = 0x0; 6347 break; 6348 default: 6349 return false; 6350 } 6351 6352 return true; 6353 } 6354 6355 static bool special_processing_applies(u32 reg, u64 *val, 6356 bool virt_int_delivery) 6357 { 6358 bool special_processing = 6359 (reg == APIC_TASKPRI) || 6360 (virt_int_delivery && 6361 (reg == APIC_EOI || reg == APIC_SELF_IPI)); 6362 6363 if (special_processing) { 6364 TEST_ASSERT(get_x2apic_wr_val(reg, val)); 6365 return true; 6366 } 6367 6368 return false; 6369 } 6370 6371 static void virt_x2apic_mode_wr_expectation( 6372 u32 reg, bool virt_x2apic_mode_on, bool disable_x2apic, 6373 bool virt_int_delivery, 6374 struct virt_x2apic_mode_expectation *expectation) 6375 { 6376 expectation->wr_exit_reason = VMX_VMCALL; 6377 expectation->wr_val = MAGIC_VAL_1; 6378 expectation->wr_only = false; 6379 6380 if (virt_x2apic_mode_on && 6381 special_processing_applies(reg, &expectation->wr_val, 6382 virt_int_delivery)) { 6383 expectation->wr_behavior = X2APIC_ACCESS_VIRTUALIZED; 6384 if (reg == APIC_SELF_IPI) 6385 expectation->wr_exit_reason = VMX_APIC_WRITE; 6386 } else if (!disable_x2apic && 6387 get_x2apic_wr_val(reg, &expectation->wr_val)) { 6388 expectation->wr_behavior = X2APIC_ACCESS_PASSED_THROUGH; 6389 if (reg == APIC_EOI || reg == APIC_SELF_IPI) 6390 expectation->wr_only = true; 6391 if (reg == APIC_ICR) 6392 expectation->wr_exit_reason = VMX_EXTINT; 6393 } else { 6394 expectation->wr_behavior = X2APIC_ACCESS_TRIGGERS_GP; 6395 /* 6396 * Writing 1 to a reserved bit triggers a #GP. 6397 * Thus, set the write value to 0, which seems 6398 * the most likely to detect a missed #GP. 6399 */ 6400 expectation->wr_val = 0; 6401 } 6402 } 6403 6404 static void virt_x2apic_mode_exit_expectation( 6405 u32 reg, struct virt_x2apic_mode_config *config, 6406 struct virt_x2apic_mode_expectation *expectation) 6407 { 6408 struct apic_reg_virt_config *base_config = 6409 &config->apic_reg_virt_config; 6410 bool virt_x2apic_mode_on = 6411 base_config->virtualize_x2apic_mode && 6412 config->use_msr_bitmaps && 6413 config->disable_x2apic_msr_intercepts && 6414 base_config->activate_secondary_controls; 6415 6416 virt_x2apic_mode_wr_expectation( 6417 reg, virt_x2apic_mode_on, config->disable_x2apic, 6418 config->virtual_interrupt_delivery, expectation); 6419 virt_x2apic_mode_rd_expectation( 6420 reg, virt_x2apic_mode_on, config->disable_x2apic, 6421 base_config->apic_register_virtualization, 6422 config->virtual_interrupt_delivery, expectation); 6423 } 6424 6425 struct virt_x2apic_mode_test_case virt_x2apic_mode_tests[] = { 6426 /* 6427 * Baseline "virtualize x2APIC mode" configuration: 6428 * - virtualize x2APIC mode 6429 * - virtual-interrupt delivery 6430 * - APIC-register virtualization 6431 * - x2APIC MSR intercepts disabled 6432 * 6433 * Reads come from virtual APIC page, special processing applies to 6434 * VTPR, EOI, and SELF IPI, and all other writes pass through to L1 6435 * APIC. 6436 */ 6437 { 6438 .name = "Baseline", 6439 .virt_x2apic_mode_config = { 6440 .virtual_interrupt_delivery = true, 6441 .use_msr_bitmaps = true, 6442 .disable_x2apic_msr_intercepts = true, 6443 .disable_x2apic = false, 6444 .apic_reg_virt_config = { 6445 .apic_register_virtualization = true, 6446 .use_tpr_shadow = true, 6447 .virtualize_apic_accesses = false, 6448 .virtualize_x2apic_mode = true, 6449 .activate_secondary_controls = true, 6450 }, 6451 }, 6452 }, 6453 { 6454 .name = "Baseline w/ x2apic disabled", 6455 .virt_x2apic_mode_config = { 6456 .virtual_interrupt_delivery = true, 6457 .use_msr_bitmaps = true, 6458 .disable_x2apic_msr_intercepts = true, 6459 .disable_x2apic = true, 6460 .apic_reg_virt_config = { 6461 .apic_register_virtualization = true, 6462 .use_tpr_shadow = true, 6463 .virtualize_apic_accesses = false, 6464 .virtualize_x2apic_mode = true, 6465 .activate_secondary_controls = true, 6466 }, 6467 }, 6468 }, 6469 6470 /* 6471 * Baseline, minus virtual-interrupt delivery. Reads come from virtual 6472 * APIC page, special processing applies to VTPR, and all other writes 6473 * pass through to L1 APIC. 6474 */ 6475 { 6476 .name = "Baseline - virtual interrupt delivery", 6477 .virt_x2apic_mode_config = { 6478 .virtual_interrupt_delivery = false, 6479 .use_msr_bitmaps = true, 6480 .disable_x2apic_msr_intercepts = true, 6481 .disable_x2apic = false, 6482 .apic_reg_virt_config = { 6483 .apic_register_virtualization = true, 6484 .use_tpr_shadow = true, 6485 .virtualize_apic_accesses = false, 6486 .virtualize_x2apic_mode = true, 6487 .activate_secondary_controls = true, 6488 }, 6489 }, 6490 }, 6491 6492 /* 6493 * Baseline, minus APIC-register virtualization. x2APIC reads pass 6494 * through to L1's APIC, unless reading VTPR 6495 */ 6496 { 6497 .name = "Virtualize x2APIC mode, no APIC reg virt", 6498 .virt_x2apic_mode_config = { 6499 .virtual_interrupt_delivery = true, 6500 .use_msr_bitmaps = true, 6501 .disable_x2apic_msr_intercepts = true, 6502 .disable_x2apic = false, 6503 .apic_reg_virt_config = { 6504 .apic_register_virtualization = false, 6505 .use_tpr_shadow = true, 6506 .virtualize_apic_accesses = false, 6507 .virtualize_x2apic_mode = true, 6508 .activate_secondary_controls = true, 6509 }, 6510 }, 6511 }, 6512 { 6513 .name = "Virtualize x2APIC mode, no APIC reg virt, x2APIC off", 6514 .virt_x2apic_mode_config = { 6515 .virtual_interrupt_delivery = true, 6516 .use_msr_bitmaps = true, 6517 .disable_x2apic_msr_intercepts = true, 6518 .disable_x2apic = true, 6519 .apic_reg_virt_config = { 6520 .apic_register_virtualization = false, 6521 .use_tpr_shadow = true, 6522 .virtualize_apic_accesses = false, 6523 .virtualize_x2apic_mode = true, 6524 .activate_secondary_controls = true, 6525 }, 6526 }, 6527 }, 6528 6529 /* 6530 * Enable "virtualize x2APIC mode" and "APIC-register virtualization", 6531 * and disable intercepts for the x2APIC MSRs, but fail to enable 6532 * "activate secondary controls" (i.e. L2 gets access to L1's x2APIC 6533 * MSRs). 6534 */ 6535 { 6536 .name = "Fail to enable activate secondary controls", 6537 .virt_x2apic_mode_config = { 6538 .virtual_interrupt_delivery = true, 6539 .use_msr_bitmaps = true, 6540 .disable_x2apic_msr_intercepts = true, 6541 .disable_x2apic = false, 6542 .apic_reg_virt_config = { 6543 .apic_register_virtualization = true, 6544 .use_tpr_shadow = true, 6545 .virtualize_apic_accesses = false, 6546 .virtualize_x2apic_mode = true, 6547 .activate_secondary_controls = false, 6548 }, 6549 }, 6550 }, 6551 6552 /* 6553 * Enable "APIC-register virtualization" and enable "activate secondary 6554 * controls" and disable intercepts for the x2APIC MSRs, but do not 6555 * enable the "virtualize x2APIC mode" VM-execution control (i.e. L2 6556 * gets access to L1's x2APIC MSRs). 6557 */ 6558 { 6559 .name = "Fail to enable virtualize x2APIC mode", 6560 .virt_x2apic_mode_config = { 6561 .virtual_interrupt_delivery = true, 6562 .use_msr_bitmaps = true, 6563 .disable_x2apic_msr_intercepts = true, 6564 .disable_x2apic = false, 6565 .apic_reg_virt_config = { 6566 .apic_register_virtualization = true, 6567 .use_tpr_shadow = true, 6568 .virtualize_apic_accesses = false, 6569 .virtualize_x2apic_mode = false, 6570 .activate_secondary_controls = true, 6571 }, 6572 }, 6573 }, 6574 6575 /* 6576 * Disable "Virtualize x2APIC mode", disable x2APIC MSR intercepts, and 6577 * enable "APIC-register virtualization" --> L2 gets L1's x2APIC MSRs. 6578 */ 6579 { 6580 .name = "Baseline", 6581 .virt_x2apic_mode_config = { 6582 .virtual_interrupt_delivery = true, 6583 .use_msr_bitmaps = true, 6584 .disable_x2apic_msr_intercepts = true, 6585 .disable_x2apic = false, 6586 .apic_reg_virt_config = { 6587 .apic_register_virtualization = true, 6588 .use_tpr_shadow = true, 6589 .virtualize_apic_accesses = false, 6590 .virtualize_x2apic_mode = false, 6591 .activate_secondary_controls = true, 6592 }, 6593 }, 6594 }, 6595 }; 6596 6597 enum X2apic_op { 6598 X2APIC_OP_RD, 6599 X2APIC_OP_WR, 6600 X2APIC_TERMINATE, 6601 }; 6602 6603 static u64 vmx_x2apic_read(u32 reg) 6604 { 6605 u32 msr_addr = x2apic_msr(reg); 6606 u64 val; 6607 6608 val = rdmsr(msr_addr); 6609 6610 return val; 6611 } 6612 6613 static void vmx_x2apic_write(u32 reg, u64 val) 6614 { 6615 u32 msr_addr = x2apic_msr(reg); 6616 6617 wrmsr(msr_addr, val); 6618 } 6619 6620 struct virt_x2apic_mode_guest_args { 6621 enum X2apic_op op; 6622 u32 reg; 6623 u64 val; 6624 bool should_gp; 6625 u64 (*virt_fn)(u64); 6626 } virt_x2apic_mode_guest_args; 6627 6628 static volatile bool handle_x2apic_gp_ran; 6629 static volatile u32 handle_x2apic_gp_insn_len; 6630 static void handle_x2apic_gp(struct ex_regs *regs) 6631 { 6632 handle_x2apic_gp_ran = true; 6633 regs->rip += handle_x2apic_gp_insn_len; 6634 } 6635 6636 static handler setup_x2apic_gp_handler(void) 6637 { 6638 handler old_handler; 6639 6640 old_handler = handle_exception(GP_VECTOR, handle_x2apic_gp); 6641 /* RDMSR and WRMSR are both 2 bytes, assuming no prefixes. */ 6642 handle_x2apic_gp_insn_len = 2; 6643 6644 return old_handler; 6645 } 6646 6647 static void teardown_x2apic_gp_handler(handler old_handler) 6648 { 6649 handle_exception(GP_VECTOR, old_handler); 6650 6651 /* 6652 * Defensively reset instruction length, so that if the handler is 6653 * incorrectly used, it will loop infinitely, rather than run off into 6654 * la la land. 6655 */ 6656 handle_x2apic_gp_insn_len = 0; 6657 handle_x2apic_gp_ran = false; 6658 } 6659 6660 static void virt_x2apic_mode_guest(void) 6661 { 6662 volatile struct virt_x2apic_mode_guest_args *args = 6663 &virt_x2apic_mode_guest_args; 6664 6665 for (;;) { 6666 enum X2apic_op op = args->op; 6667 u32 reg = args->reg; 6668 u64 val = args->val; 6669 bool should_gp = args->should_gp; 6670 u64 (*virt_fn)(u64) = args->virt_fn; 6671 handler old_handler; 6672 6673 if (op == X2APIC_TERMINATE) 6674 break; 6675 6676 if (should_gp) { 6677 TEST_ASSERT(!handle_x2apic_gp_ran); 6678 old_handler = setup_x2apic_gp_handler(); 6679 } 6680 6681 if (op == X2APIC_OP_RD) { 6682 u64 ret = vmx_x2apic_read(reg); 6683 6684 if (!should_gp) { 6685 u64 want = virt_fn(val); 6686 u64 got = virt_fn(ret); 6687 6688 report(got == want, 6689 "APIC read; got 0x%lx, want 0x%lx.", 6690 got, want); 6691 } 6692 } else if (op == X2APIC_OP_WR) { 6693 vmx_x2apic_write(reg, val); 6694 } 6695 6696 if (should_gp) { 6697 report(handle_x2apic_gp_ran, 6698 "x2APIC op triggered GP."); 6699 teardown_x2apic_gp_handler(old_handler); 6700 } 6701 6702 /* 6703 * The L1 should always execute a vmcall after it's done testing 6704 * an individual APIC operation. This helps to validate that the 6705 * L1 and L2 are in sync with each other, as expected. 6706 */ 6707 vmcall(); 6708 } 6709 } 6710 6711 static void test_x2apic_rd( 6712 u32 reg, struct virt_x2apic_mode_expectation *expectation, 6713 u32 *virtual_apic_page) 6714 { 6715 u64 val = expectation->rd_val; 6716 u32 exit_reason_want = expectation->rd_exit_reason; 6717 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6718 6719 report_prefix_pushf("x2apic - reading 0x%03x", reg); 6720 6721 /* Configure guest to do an x2apic read */ 6722 args->op = X2APIC_OP_RD; 6723 args->reg = reg; 6724 args->val = val; 6725 args->should_gp = expectation->rd_behavior == X2APIC_ACCESS_TRIGGERS_GP; 6726 args->virt_fn = expectation->virt_fn; 6727 6728 /* Setup virtual APIC page */ 6729 if (expectation->rd_behavior == X2APIC_ACCESS_VIRTUALIZED) 6730 virtual_apic_page[apic_reg_index(reg)] = (u32)val; 6731 6732 /* Enter guest */ 6733 enter_guest(); 6734 6735 if (exit_reason_want != VMX_VMCALL) { 6736 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 6737 } 6738 6739 skip_exit_vmcall(); 6740 report_prefix_pop(); 6741 } 6742 6743 static volatile bool handle_x2apic_ipi_ran; 6744 static void handle_x2apic_ipi(isr_regs_t *regs) 6745 { 6746 handle_x2apic_ipi_ran = true; 6747 eoi(); 6748 } 6749 6750 static void test_x2apic_wr( 6751 u32 reg, struct virt_x2apic_mode_expectation *expectation, 6752 u32 *virtual_apic_page) 6753 { 6754 u64 val = expectation->wr_val; 6755 u32 exit_reason_want = expectation->wr_exit_reason; 6756 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6757 int ipi_vector = 0xf1; 6758 u32 restore_val = 0; 6759 6760 report_prefix_pushf("x2apic - writing 0x%lx to 0x%03x", val, reg); 6761 6762 /* Configure guest to do an x2apic read */ 6763 args->op = X2APIC_OP_WR; 6764 args->reg = reg; 6765 args->val = val; 6766 args->should_gp = expectation->wr_behavior == X2APIC_ACCESS_TRIGGERS_GP; 6767 6768 /* Setup virtual APIC page */ 6769 if (expectation->wr_behavior == X2APIC_ACCESS_VIRTUALIZED) 6770 virtual_apic_page[apic_reg_index(reg)] = 0; 6771 if (expectation->wr_behavior == X2APIC_ACCESS_PASSED_THROUGH && !expectation->wr_only) 6772 restore_val = apic_read(reg); 6773 6774 /* Setup IPI handler */ 6775 handle_x2apic_ipi_ran = false; 6776 handle_irq(ipi_vector, handle_x2apic_ipi); 6777 6778 /* Enter guest */ 6779 enter_guest(); 6780 6781 /* 6782 * Validate the behavior and 6783 * pass a magic value back to the guest. 6784 */ 6785 if (exit_reason_want == VMX_EXTINT) { 6786 assert_exit_reason(exit_reason_want); 6787 6788 /* Clear the external interrupt. */ 6789 irq_enable(); 6790 asm volatile ("nop"); 6791 irq_disable(); 6792 report(handle_x2apic_ipi_ran, 6793 "Got pending interrupt after IRQ enabled."); 6794 6795 enter_guest(); 6796 } else if (exit_reason_want == VMX_APIC_WRITE) { 6797 assert_exit_reason(exit_reason_want); 6798 report(virtual_apic_page[apic_reg_index(reg)] == val, 6799 "got APIC write exit @ page offset 0x%03x; val is 0x%x, want 0x%lx", 6800 apic_reg_index(reg), 6801 virtual_apic_page[apic_reg_index(reg)], val); 6802 6803 /* Reenter guest so it can consume/check rcx and exit again. */ 6804 enter_guest(); 6805 } else if (exit_reason_want != VMX_VMCALL) { 6806 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 6807 } 6808 6809 assert_exit_reason(VMX_VMCALL); 6810 if (expectation->wr_behavior == X2APIC_ACCESS_VIRTUALIZED) { 6811 u64 want = val; 6812 u32 got = virtual_apic_page[apic_reg_index(reg)]; 6813 6814 report(got == want, "x2APIC write; got 0x%x, want 0x%lx", got, 6815 want); 6816 } else if (expectation->wr_behavior == X2APIC_ACCESS_PASSED_THROUGH) { 6817 if (!expectation->wr_only) { 6818 u32 got = apic_read(reg); 6819 bool ok; 6820 6821 /* 6822 * When L1's TPR is passed through to L2, the lower 6823 * nibble can be lost. For example, if L2 executes 6824 * WRMSR(0x808, 0x78), then, L1 might read 0x70. 6825 * 6826 * Here's how the lower nibble can get lost: 6827 * 1. L2 executes WRMSR(0x808, 0x78). 6828 * 2. L2 exits to L0 with a WRMSR exit. 6829 * 3. L0 emulates WRMSR, by writing L1's TPR. 6830 * 4. L0 re-enters L2. 6831 * 5. L2 exits to L0 (reason doesn't matter). 6832 * 6. L0 reflects L2's exit to L1. 6833 * 7. Before entering L1, L0 exits to user-space 6834 * (e.g., to satisfy TPR access reporting). 6835 * 8. User-space executes KVM_SET_REGS ioctl, which 6836 * clears the lower nibble of L1's TPR. 6837 */ 6838 if (reg == APIC_TASKPRI) { 6839 got = apic_virt_nibble1(got); 6840 val = apic_virt_nibble1(val); 6841 } 6842 6843 ok = got == val; 6844 report(ok, 6845 "non-virtualized write; val is 0x%x, want 0x%lx", 6846 got, val); 6847 apic_write(reg, restore_val); 6848 } else { 6849 report_pass("non-virtualized and write-only OK"); 6850 } 6851 } 6852 skip_exit_insn(); 6853 6854 report_prefix_pop(); 6855 } 6856 6857 static enum Config_type configure_virt_x2apic_mode_test( 6858 struct virt_x2apic_mode_config *virt_x2apic_mode_config, 6859 u8 *msr_bitmap_page) 6860 { 6861 int msr; 6862 u32 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6863 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6864 6865 /* x2apic-specific VMCS config */ 6866 if (virt_x2apic_mode_config->use_msr_bitmaps) { 6867 /* virt_x2apic_mode_test() checks for MSR bitmaps support */ 6868 cpu_exec_ctrl0 |= CPU_MSR_BITMAP; 6869 } else { 6870 cpu_exec_ctrl0 &= ~CPU_MSR_BITMAP; 6871 } 6872 6873 if (virt_x2apic_mode_config->virtual_interrupt_delivery) { 6874 if (!(ctrl_cpu_rev[1].clr & CPU_VINTD)) { 6875 report_skip("VM-execution control \"virtual-interrupt delivery\" NOT supported.\n"); 6876 return CONFIG_TYPE_UNSUPPORTED; 6877 } 6878 cpu_exec_ctrl1 |= CPU_VINTD; 6879 } else { 6880 cpu_exec_ctrl1 &= ~CPU_VINTD; 6881 } 6882 6883 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6884 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6885 6886 /* x2APIC MSR intercepts are usually off for "Virtualize x2APIC mode" */ 6887 for (msr = 0x800; msr <= 0x8ff; msr++) { 6888 if (virt_x2apic_mode_config->disable_x2apic_msr_intercepts) { 6889 clear_bit(msr, msr_bitmap_page + 0x000); 6890 clear_bit(msr, msr_bitmap_page + 0x800); 6891 } else { 6892 set_bit(msr, msr_bitmap_page + 0x000); 6893 set_bit(msr, msr_bitmap_page + 0x800); 6894 } 6895 } 6896 6897 /* x2APIC mode can impact virtualization */ 6898 reset_apic(); 6899 if (!virt_x2apic_mode_config->disable_x2apic) 6900 enable_x2apic(); 6901 6902 return configure_apic_reg_virt_test( 6903 &virt_x2apic_mode_config->apic_reg_virt_config); 6904 } 6905 6906 static void virt_x2apic_mode_test(void) 6907 { 6908 u32 *virtual_apic_page; 6909 u8 *msr_bitmap_page; 6910 u64 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6911 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6912 int i; 6913 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6914 6915 if (!cpu_has_apicv()) { 6916 report_skip(__func__); 6917 return; 6918 } 6919 6920 /* 6921 * This is to exercise an issue in KVM's logic to merge L0's and L1's 6922 * MSR bitmaps. Previously, an L1 could get at L0's x2APIC MSRs by 6923 * writing the IA32_SPEC_CTRL MSR or the IA32_PRED_CMD MSRs. KVM would 6924 * then proceed to manipulate the MSR bitmaps, as if VMCS12 had the 6925 * "Virtualize x2APIC mod" control set, even when it didn't. 6926 */ 6927 if (has_spec_ctrl()) 6928 wrmsr(MSR_IA32_SPEC_CTRL, 1); 6929 6930 /* 6931 * Check that VMCS12 supports: 6932 * - "Virtual-APIC address", indicated by "use TPR shadow" 6933 * - "MSR-bitmap address", indicated by "use MSR bitmaps" 6934 */ 6935 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) { 6936 report_skip("VM-execution control \"use TPR shadow\" NOT supported.\n"); 6937 return; 6938 } else if (!(ctrl_cpu_rev[0].clr & CPU_MSR_BITMAP)) { 6939 report_skip("VM-execution control \"use MSR bitmaps\" NOT supported.\n"); 6940 return; 6941 } 6942 6943 test_set_guest(virt_x2apic_mode_guest); 6944 6945 virtual_apic_page = alloc_page(); 6946 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 6947 6948 msr_bitmap_page = alloc_page(); 6949 memset(msr_bitmap_page, 0xff, PAGE_SIZE); 6950 vmcs_write(MSR_BITMAP, virt_to_phys(msr_bitmap_page)); 6951 6952 for (i = 0; i < ARRAY_SIZE(virt_x2apic_mode_tests); i++) { 6953 struct virt_x2apic_mode_test_case *virt_x2apic_mode_test_case = 6954 &virt_x2apic_mode_tests[i]; 6955 struct virt_x2apic_mode_config *virt_x2apic_mode_config = 6956 &virt_x2apic_mode_test_case->virt_x2apic_mode_config; 6957 enum Config_type config_type; 6958 u32 reg; 6959 6960 printf("--- %s test ---\n", virt_x2apic_mode_test_case->name); 6961 config_type = 6962 configure_virt_x2apic_mode_test(virt_x2apic_mode_config, 6963 msr_bitmap_page); 6964 if (config_type == CONFIG_TYPE_UNSUPPORTED) { 6965 report_skip("Skip because of missing features.\n"); 6966 continue; 6967 } else if (config_type == CONFIG_TYPE_VMENTRY_FAILS_EARLY) { 6968 enter_guest_with_bad_controls(); 6969 continue; 6970 } 6971 6972 for (reg = 0; reg < PAGE_SIZE / sizeof(u32); reg += 0x10) { 6973 struct virt_x2apic_mode_expectation expectation; 6974 6975 virt_x2apic_mode_exit_expectation( 6976 reg, virt_x2apic_mode_config, &expectation); 6977 6978 test_x2apic_rd(reg, &expectation, virtual_apic_page); 6979 test_x2apic_wr(reg, &expectation, virtual_apic_page); 6980 } 6981 } 6982 6983 6984 /* Terminate the guest */ 6985 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6986 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6987 args->op = X2APIC_TERMINATE; 6988 enter_guest(); 6989 assert_exit_reason(VMX_VMCALL); 6990 } 6991 6992 static void test_ctl_reg(const char *cr_name, u64 cr, u64 fixed0, u64 fixed1) 6993 { 6994 u64 val; 6995 u64 cr_saved = vmcs_read(cr); 6996 int i; 6997 6998 val = fixed0 & fixed1; 6999 if (cr == HOST_CR4) 7000 vmcs_write(cr, val | X86_CR4_PAE); 7001 else 7002 vmcs_write(cr, val); 7003 report_prefix_pushf("%s %lx", cr_name, val); 7004 if (val == fixed0) 7005 test_vmx_vmlaunch(0); 7006 else 7007 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7008 report_prefix_pop(); 7009 7010 for (i = 0; i < 64; i++) { 7011 7012 /* Set a bit when the corresponding bit in fixed1 is 0 */ 7013 if ((fixed1 & (1ull << i)) == 0) { 7014 if (cr == HOST_CR4 && ((1ull << i) & X86_CR4_SMEP || 7015 (1ull << i) & X86_CR4_SMAP)) 7016 continue; 7017 7018 vmcs_write(cr, cr_saved | (1ull << i)); 7019 report_prefix_pushf("%s %llx", cr_name, 7020 cr_saved | (1ull << i)); 7021 test_vmx_vmlaunch( 7022 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7023 report_prefix_pop(); 7024 } 7025 7026 /* Unset a bit when the corresponding bit in fixed0 is 1 */ 7027 if (fixed0 & (1ull << i)) { 7028 vmcs_write(cr, cr_saved & ~(1ull << i)); 7029 report_prefix_pushf("%s %llx", cr_name, 7030 cr_saved & ~(1ull << i)); 7031 test_vmx_vmlaunch( 7032 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7033 report_prefix_pop(); 7034 } 7035 } 7036 7037 vmcs_write(cr, cr_saved); 7038 } 7039 7040 /* 7041 * 1. The CR0 field must not set any bit to a value not supported in VMX 7042 * operation. 7043 * 2. The CR4 field must not set any bit to a value not supported in VMX 7044 * operation. 7045 * 3. On processors that support Intel 64 architecture, the CR3 field must 7046 * be such that bits 63:52 and bits in the range 51:32 beyond the 7047 * processor's physical-address width must be 0. 7048 * 7049 * [Intel SDM] 7050 */ 7051 static void test_host_ctl_regs(void) 7052 { 7053 u64 fixed0, fixed1, cr3, cr3_saved; 7054 int i; 7055 7056 /* Test CR0 */ 7057 fixed0 = rdmsr(MSR_IA32_VMX_CR0_FIXED0); 7058 fixed1 = rdmsr(MSR_IA32_VMX_CR0_FIXED1); 7059 test_ctl_reg("HOST_CR0", HOST_CR0, fixed0, fixed1); 7060 7061 /* Test CR4 */ 7062 fixed0 = rdmsr(MSR_IA32_VMX_CR4_FIXED0); 7063 fixed1 = rdmsr(MSR_IA32_VMX_CR4_FIXED1) & 7064 ~(X86_CR4_SMEP | X86_CR4_SMAP); 7065 test_ctl_reg("HOST_CR4", HOST_CR4, fixed0, fixed1); 7066 7067 /* Test CR3 */ 7068 cr3_saved = vmcs_read(HOST_CR3); 7069 for (i = cpuid_maxphyaddr(); i < 64; i++) { 7070 cr3 = cr3_saved | (1ul << i); 7071 vmcs_write(HOST_CR3, cr3); 7072 report_prefix_pushf("HOST_CR3 %lx", cr3); 7073 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7074 report_prefix_pop(); 7075 } 7076 7077 vmcs_write(HOST_CR3, cr3_saved); 7078 } 7079 7080 static void test_efer_vmlaunch(u32 fld, bool ok) 7081 { 7082 if (fld == HOST_EFER) { 7083 if (ok) 7084 test_vmx_vmlaunch(0); 7085 else 7086 test_vmx_vmlaunch2(VMXERR_ENTRY_INVALID_CONTROL_FIELD, 7087 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7088 } else { 7089 test_guest_state("EFER test", !ok, GUEST_EFER, "GUEST_EFER"); 7090 } 7091 } 7092 7093 static void test_efer_one(u32 fld, const char * fld_name, u64 efer, 7094 u32 ctrl_fld, u64 ctrl, 7095 int i, const char *efer_bit_name) 7096 { 7097 bool ok; 7098 7099 ok = true; 7100 if (ctrl_fld == EXI_CONTROLS && (ctrl & EXI_LOAD_EFER)) { 7101 if (!!(efer & EFER_LMA) != !!(ctrl & EXI_HOST_64)) 7102 ok = false; 7103 if (!!(efer & EFER_LME) != !!(ctrl & EXI_HOST_64)) 7104 ok = false; 7105 } 7106 if (ctrl_fld == ENT_CONTROLS && (ctrl & ENT_LOAD_EFER)) { 7107 /* Check LMA too since CR0.PG is set. */ 7108 if (!!(efer & EFER_LMA) != !!(ctrl & ENT_GUEST_64)) 7109 ok = false; 7110 if (!!(efer & EFER_LME) != !!(ctrl & ENT_GUEST_64)) 7111 ok = false; 7112 } 7113 7114 /* 7115 * Skip the test if it would enter the guest in 32-bit mode. 7116 * Perhaps write the test in assembly and make sure it 7117 * can be run in either mode? 7118 */ 7119 if (fld == GUEST_EFER && ok && !(ctrl & ENT_GUEST_64)) 7120 return; 7121 7122 vmcs_write(ctrl_fld, ctrl); 7123 vmcs_write(fld, efer); 7124 report_prefix_pushf("%s %s bit turned %s, controls %s", 7125 fld_name, efer_bit_name, 7126 (i & 1) ? "on" : "off", 7127 (i & 2) ? "on" : "off"); 7128 7129 test_efer_vmlaunch(fld, ok); 7130 report_prefix_pop(); 7131 } 7132 7133 static void test_efer_bit(u32 fld, const char * fld_name, 7134 u32 ctrl_fld, u64 ctrl_bit, u64 efer_bit, 7135 const char *efer_bit_name) 7136 { 7137 u64 efer_saved = vmcs_read(fld); 7138 u32 ctrl_saved = vmcs_read(ctrl_fld); 7139 int i; 7140 7141 for (i = 0; i < 4; i++) { 7142 u64 efer = efer_saved & ~efer_bit; 7143 u64 ctrl = ctrl_saved & ~ctrl_bit; 7144 7145 if (i & 1) 7146 efer |= efer_bit; 7147 if (i & 2) 7148 ctrl |= ctrl_bit; 7149 7150 test_efer_one(fld, fld_name, efer, ctrl_fld, ctrl, 7151 i, efer_bit_name); 7152 } 7153 7154 vmcs_write(ctrl_fld, ctrl_saved); 7155 vmcs_write(fld, efer_saved); 7156 } 7157 7158 static void test_efer(u32 fld, const char * fld_name, u32 ctrl_fld, 7159 u64 ctrl_bit1, u64 ctrl_bit2) 7160 { 7161 u64 efer_saved = vmcs_read(fld); 7162 u32 ctrl_saved = vmcs_read(ctrl_fld); 7163 u64 efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 7164 u64 i; 7165 u64 efer; 7166 7167 if (cpu_has_efer_nx()) 7168 efer_reserved_bits &= ~EFER_NX; 7169 7170 if (!ctrl_bit1) { 7171 printf("\"Load-IA32-EFER\" exit control not supported\n"); 7172 goto test_entry_exit_mode; 7173 } 7174 7175 report_prefix_pushf("%s %lx", fld_name, efer_saved); 7176 test_efer_vmlaunch(fld, true); 7177 report_prefix_pop(); 7178 7179 /* 7180 * Check reserved bits 7181 */ 7182 vmcs_write(ctrl_fld, ctrl_saved & ~ctrl_bit1); 7183 for (i = 0; i < 64; i++) { 7184 if ((1ull << i) & efer_reserved_bits) { 7185 efer = efer_saved | (1ull << i); 7186 vmcs_write(fld, efer); 7187 report_prefix_pushf("%s %lx", fld_name, efer); 7188 test_efer_vmlaunch(fld, true); 7189 report_prefix_pop(); 7190 } 7191 } 7192 7193 vmcs_write(ctrl_fld, ctrl_saved | ctrl_bit1); 7194 for (i = 0; i < 64; i++) { 7195 if ((1ull << i) & efer_reserved_bits) { 7196 efer = efer_saved | (1ull << i); 7197 vmcs_write(fld, efer); 7198 report_prefix_pushf("%s %lx", fld_name, efer); 7199 test_efer_vmlaunch(fld, false); 7200 report_prefix_pop(); 7201 } 7202 } 7203 7204 vmcs_write(ctrl_fld, ctrl_saved); 7205 vmcs_write(fld, efer_saved); 7206 7207 /* 7208 * Check LMA and LME bits 7209 */ 7210 test_efer_bit(fld, fld_name, 7211 ctrl_fld, ctrl_bit1, 7212 EFER_LMA, 7213 "EFER_LMA"); 7214 test_efer_bit(fld, fld_name, 7215 ctrl_fld, ctrl_bit1, 7216 EFER_LME, 7217 "EFER_LME"); 7218 7219 test_entry_exit_mode: 7220 test_efer_bit(fld, fld_name, 7221 ctrl_fld, ctrl_bit2, 7222 EFER_LMA, 7223 "EFER_LMA"); 7224 test_efer_bit(fld, fld_name, 7225 ctrl_fld, ctrl_bit2, 7226 EFER_LME, 7227 "EFER_LME"); 7228 } 7229 7230 /* 7231 * If the 'load IA32_EFER' VM-exit control is 1, bits reserved in the 7232 * IA32_EFER MSR must be 0 in the field for that register. In addition, 7233 * the values of the LMA and LME bits in the field must each be that of 7234 * the 'host address-space size' VM-exit control. 7235 * 7236 * [Intel SDM] 7237 */ 7238 static void test_host_efer(void) 7239 { 7240 test_efer(HOST_EFER, "HOST_EFER", EXI_CONTROLS, 7241 ctrl_exit_rev.clr & EXI_LOAD_EFER, 7242 EXI_HOST_64); 7243 } 7244 7245 /* 7246 * If the 'load IA32_EFER' VM-enter control is 1, bits reserved in the 7247 * IA32_EFER MSR must be 0 in the field for that register. In addition, 7248 * the values of the LMA and LME bits in the field must each be that of 7249 * the 'IA32e-mode guest' VM-exit control. 7250 */ 7251 static void test_guest_efer(void) 7252 { 7253 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) { 7254 printf("\"Load-IA32-EFER\" entry control not supported\n"); 7255 return; 7256 } 7257 7258 vmcs_write(GUEST_EFER, rdmsr(MSR_EFER)); 7259 test_efer(GUEST_EFER, "GUEST_EFER", ENT_CONTROLS, 7260 ctrl_enter_rev.clr & ENT_LOAD_EFER, 7261 ENT_GUEST_64); 7262 } 7263 7264 /* 7265 * PAT values higher than 8 are uninteresting since they're likely lumped 7266 * in with "8". We only test values above 8 one bit at a time, 7267 * in order to reduce the number of VM-Entries and keep the runtime reasonable. 7268 */ 7269 #define PAT_VAL_LIMIT 8 7270 7271 static void test_pat(u32 field, const char * field_name, u32 ctrl_field, 7272 u64 ctrl_bit) 7273 { 7274 u32 ctrl_saved = vmcs_read(ctrl_field); 7275 u64 pat_saved = vmcs_read(field); 7276 u64 i, val; 7277 u32 j; 7278 int error; 7279 7280 vmcs_clear_bits(ctrl_field, ctrl_bit); 7281 7282 for (i = 0; i < 256; i = (i < PAT_VAL_LIMIT) ? i + 1 : i * 2) { 7283 /* Test PAT0..PAT7 fields */ 7284 for (j = 0; j < (i ? 8 : 1); j++) { 7285 val = i << j * 8; 7286 vmcs_write(field, val); 7287 if (field == HOST_PAT) { 7288 report_prefix_pushf("%s %lx", field_name, val); 7289 test_vmx_vmlaunch(0); 7290 report_prefix_pop(); 7291 7292 } else { // GUEST_PAT 7293 test_guest_state("ENT_LOAD_PAT enabled", false, 7294 val, "GUEST_PAT"); 7295 } 7296 } 7297 } 7298 7299 vmcs_set_bits(ctrl_field, ctrl_bit); 7300 for (i = 0; i < 256; i = (i < PAT_VAL_LIMIT) ? i + 1 : i * 2) { 7301 /* Test PAT0..PAT7 fields */ 7302 for (j = 0; j < (i ? 8 : 1); j++) { 7303 val = i << j * 8; 7304 vmcs_write(field, val); 7305 7306 if (field == HOST_PAT) { 7307 report_prefix_pushf("%s %lx", field_name, val); 7308 if (i == 0x2 || i == 0x3 || i >= 0x8) 7309 error = 7310 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD; 7311 else 7312 error = 0; 7313 7314 test_vmx_vmlaunch(error); 7315 report_prefix_pop(); 7316 7317 } else { // GUEST_PAT 7318 error = (i == 0x2 || i == 0x3 || i >= 0x8); 7319 test_guest_state("ENT_LOAD_PAT enabled", !!error, 7320 val, "GUEST_PAT"); 7321 } 7322 7323 } 7324 } 7325 7326 vmcs_write(ctrl_field, ctrl_saved); 7327 vmcs_write(field, pat_saved); 7328 } 7329 7330 /* 7331 * If the "load IA32_PAT" VM-exit control is 1, the value of the field 7332 * for the IA32_PAT MSR must be one that could be written by WRMSR 7333 * without fault at CPL 0. Specifically, each of the 8 bytes in the 7334 * field must have one of the values 0 (UC), 1 (WC), 4 (WT), 5 (WP), 7335 * 6 (WB), or 7 (UC-). 7336 * 7337 * [Intel SDM] 7338 */ 7339 static void test_load_host_pat(void) 7340 { 7341 /* 7342 * "load IA32_PAT" VM-exit control 7343 */ 7344 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) { 7345 printf("\"Load-IA32-PAT\" exit control not supported\n"); 7346 return; 7347 } 7348 7349 test_pat(HOST_PAT, "HOST_PAT", EXI_CONTROLS, EXI_LOAD_PAT); 7350 } 7351 7352 union cpuidA_eax { 7353 struct { 7354 unsigned int version_id:8; 7355 unsigned int num_counters_gp:8; 7356 unsigned int bit_width:8; 7357 unsigned int mask_length:8; 7358 } split; 7359 unsigned int full; 7360 }; 7361 7362 union cpuidA_edx { 7363 struct { 7364 unsigned int num_counters_fixed:5; 7365 unsigned int bit_width_fixed:8; 7366 unsigned int reserved:9; 7367 } split; 7368 unsigned int full; 7369 }; 7370 7371 static bool valid_pgc(u64 val) 7372 { 7373 struct cpuid id; 7374 union cpuidA_eax eax; 7375 union cpuidA_edx edx; 7376 u64 mask; 7377 7378 id = cpuid(0xA); 7379 eax.full = id.a; 7380 edx.full = id.d; 7381 mask = ~(((1ull << eax.split.num_counters_gp) - 1) | 7382 (((1ull << edx.split.num_counters_fixed) - 1) << 32)); 7383 7384 return !(val & mask); 7385 } 7386 7387 static void test_pgc_vmlaunch(u32 xerror, u32 xreason, bool xfail, bool host) 7388 { 7389 u32 inst_err; 7390 u64 obs; 7391 bool success; 7392 struct vmx_state_area_test_data *data = &vmx_state_area_test_data; 7393 7394 if (host) { 7395 success = vmlaunch_succeeds(); 7396 obs = rdmsr(data->msr); 7397 if (!success) { 7398 inst_err = vmcs_read(VMX_INST_ERROR); 7399 report(xerror == inst_err, "vmlaunch failed, " 7400 "VMX Inst Error is %d (expected %d)", 7401 inst_err, xerror); 7402 } else { 7403 report(!data->enabled || data->exp == obs, 7404 "Host state is 0x%lx (expected 0x%lx)", 7405 obs, data->exp); 7406 report(success != xfail, "vmlaunch succeeded"); 7407 } 7408 } else { 7409 test_guest_state("load GUEST_PERF_GLOBAL_CTRL", xfail, 7410 GUEST_PERF_GLOBAL_CTRL, 7411 "GUEST_PERF_GLOBAL_CTRL"); 7412 } 7413 } 7414 7415 /* 7416 * test_load_perf_global_ctrl is a generic function for testing the 7417 * "load IA32_PERF_GLOBAL_CTRL" VM-{Entry,Exit} controls. This test function 7418 * tests the provided ctrl_val when disabled and enabled. 7419 * 7420 * @nr: VMCS field number corresponding to the host/guest state field 7421 * @name: Name of the above VMCS field for printing in test report 7422 * @ctrl_nr: VMCS field number corresponding to the VM-{Entry,Exit} control 7423 * @ctrl_val: Bit to set on the ctrl_field 7424 */ 7425 static void test_perf_global_ctrl(u32 nr, const char *name, u32 ctrl_nr, 7426 const char *ctrl_name, u64 ctrl_val) 7427 { 7428 u64 ctrl_saved = vmcs_read(ctrl_nr); 7429 u64 pgc_saved = vmcs_read(nr); 7430 u64 i, val; 7431 bool host = nr == HOST_PERF_GLOBAL_CTRL; 7432 struct vmx_state_area_test_data *data = &vmx_state_area_test_data; 7433 7434 data->msr = MSR_CORE_PERF_GLOBAL_CTRL; 7435 msr_bmp_init(); 7436 vmcs_write(ctrl_nr, ctrl_saved & ~ctrl_val); 7437 data->enabled = false; 7438 report_prefix_pushf("\"load IA32_PERF_GLOBAL_CTRL\"=0 on %s", 7439 ctrl_name); 7440 7441 for (i = 0; i < 64; i++) { 7442 val = 1ull << i; 7443 vmcs_write(nr, val); 7444 report_prefix_pushf("%s = 0x%lx", name, val); 7445 test_pgc_vmlaunch(0, VMX_VMCALL, false, host); 7446 report_prefix_pop(); 7447 } 7448 report_prefix_pop(); 7449 7450 vmcs_write(ctrl_nr, ctrl_saved | ctrl_val); 7451 data->enabled = true; 7452 report_prefix_pushf("\"load IA32_PERF_GLOBAL_CTRL\"=1 on %s", 7453 ctrl_name); 7454 for (i = 0; i < 64; i++) { 7455 val = 1ull << i; 7456 data->exp = val; 7457 vmcs_write(nr, val); 7458 report_prefix_pushf("%s = 0x%lx", name, val); 7459 if (valid_pgc(val)) { 7460 test_pgc_vmlaunch(0, VMX_VMCALL, false, host); 7461 } else { 7462 if (host) 7463 test_pgc_vmlaunch( 7464 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, 7465 0, 7466 true, 7467 host); 7468 else 7469 test_pgc_vmlaunch( 7470 0, 7471 VMX_ENTRY_FAILURE | VMX_FAIL_STATE, 7472 true, 7473 host); 7474 } 7475 report_prefix_pop(); 7476 } 7477 7478 data->enabled = false; 7479 report_prefix_pop(); 7480 vmcs_write(ctrl_nr, ctrl_saved); 7481 vmcs_write(nr, pgc_saved); 7482 } 7483 7484 static void test_load_host_perf_global_ctrl(void) 7485 { 7486 if (!(ctrl_exit_rev.clr & EXI_LOAD_PERF)) { 7487 printf("\"load IA32_PERF_GLOBAL_CTRL\" exit control not supported\n"); 7488 return; 7489 } 7490 7491 test_perf_global_ctrl(HOST_PERF_GLOBAL_CTRL, "HOST_PERF_GLOBAL_CTRL", 7492 EXI_CONTROLS, "EXI_CONTROLS", EXI_LOAD_PERF); 7493 } 7494 7495 7496 static void test_load_guest_perf_global_ctrl(void) 7497 { 7498 if (!(ctrl_enter_rev.clr & ENT_LOAD_PERF)) { 7499 printf("\"load IA32_PERF_GLOBAL_CTRL\" entry control not supported\n"); 7500 return; 7501 } 7502 7503 test_perf_global_ctrl(GUEST_PERF_GLOBAL_CTRL, "GUEST_PERF_GLOBAL_CTRL", 7504 ENT_CONTROLS, "ENT_CONTROLS", ENT_LOAD_PERF); 7505 } 7506 7507 7508 /* 7509 * test_vmcs_field - test a value for the given VMCS field 7510 * @field: VMCS field 7511 * @field_name: string name of VMCS field 7512 * @bit_start: starting bit 7513 * @bit_end: ending bit 7514 * @val: value that the bit range must or must not contain 7515 * @valid_val: whether value given in 'val' must be valid or not 7516 * @error: expected VMCS error when vmentry fails for an invalid value 7517 */ 7518 static void test_vmcs_field(u64 field, const char *field_name, u32 bit_start, 7519 u32 bit_end, u64 val, bool valid_val, u32 error) 7520 { 7521 u64 field_saved = vmcs_read(field); 7522 u32 i; 7523 u64 tmp; 7524 u32 bit_on; 7525 u64 mask = ~0ull; 7526 7527 mask = (mask >> bit_end) << bit_end; 7528 mask = mask | ((1 << bit_start) - 1); 7529 tmp = (field_saved & mask) | (val << bit_start); 7530 7531 vmcs_write(field, tmp); 7532 report_prefix_pushf("%s %lx", field_name, tmp); 7533 if (valid_val) 7534 test_vmx_vmlaunch(0); 7535 else 7536 test_vmx_vmlaunch(error); 7537 report_prefix_pop(); 7538 7539 for (i = bit_start; i <= bit_end; i = i + 2) { 7540 bit_on = ((1ull < i) & (val << bit_start)) ? 0 : 1; 7541 if (bit_on) 7542 tmp = field_saved | (1ull << i); 7543 else 7544 tmp = field_saved & ~(1ull << i); 7545 vmcs_write(field, tmp); 7546 report_prefix_pushf("%s %lx", field_name, tmp); 7547 if (valid_val) 7548 test_vmx_vmlaunch(error); 7549 else 7550 test_vmx_vmlaunch(0); 7551 report_prefix_pop(); 7552 } 7553 7554 vmcs_write(field, field_saved); 7555 } 7556 7557 static void test_canonical(u64 field, const char * field_name, bool host) 7558 { 7559 u64 addr_saved = vmcs_read(field); 7560 7561 /* 7562 * Use the existing value if possible. Writing a random canonical 7563 * value is not an option as doing so would corrupt the field being 7564 * tested and likely hose the test. 7565 */ 7566 if (is_canonical(addr_saved)) { 7567 if (host) { 7568 report_prefix_pushf("%s %lx", field_name, addr_saved); 7569 test_vmx_vmlaunch(0); 7570 report_prefix_pop(); 7571 } else { 7572 test_guest_state("Test canonical address", false, 7573 addr_saved, field_name); 7574 } 7575 } 7576 7577 vmcs_write(field, NONCANONICAL); 7578 7579 if (host) { 7580 report_prefix_pushf("%s %llx", field_name, NONCANONICAL); 7581 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7582 report_prefix_pop(); 7583 } else { 7584 test_guest_state("Test non-canonical address", true, 7585 NONCANONICAL, field_name); 7586 } 7587 7588 vmcs_write(field, addr_saved); 7589 } 7590 7591 #define TEST_RPL_TI_FLAGS(reg, name) \ 7592 test_vmcs_field(reg, name, 0, 2, 0x0, true, \ 7593 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7594 7595 #define TEST_CS_TR_FLAGS(reg, name) \ 7596 test_vmcs_field(reg, name, 3, 15, 0x0000, false, \ 7597 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7598 7599 /* 7600 * 1. In the selector field for each of CS, SS, DS, ES, FS, GS and TR, the 7601 * RPL (bits 1:0) and the TI flag (bit 2) must be 0. 7602 * 2. The selector fields for CS and TR cannot be 0000H. 7603 * 3. The selector field for SS cannot be 0000H if the "host address-space 7604 * size" VM-exit control is 0. 7605 * 4. On processors that support Intel 64 architecture, the base-address 7606 * fields for FS, GS and TR must contain canonical addresses. 7607 */ 7608 static void test_host_segment_regs(void) 7609 { 7610 u16 selector_saved; 7611 7612 /* 7613 * Test RPL and TI flags 7614 */ 7615 TEST_RPL_TI_FLAGS(HOST_SEL_CS, "HOST_SEL_CS"); 7616 TEST_RPL_TI_FLAGS(HOST_SEL_SS, "HOST_SEL_SS"); 7617 TEST_RPL_TI_FLAGS(HOST_SEL_DS, "HOST_SEL_DS"); 7618 TEST_RPL_TI_FLAGS(HOST_SEL_ES, "HOST_SEL_ES"); 7619 TEST_RPL_TI_FLAGS(HOST_SEL_FS, "HOST_SEL_FS"); 7620 TEST_RPL_TI_FLAGS(HOST_SEL_GS, "HOST_SEL_GS"); 7621 TEST_RPL_TI_FLAGS(HOST_SEL_TR, "HOST_SEL_TR"); 7622 7623 /* 7624 * Test that CS and TR fields can not be 0x0000 7625 */ 7626 TEST_CS_TR_FLAGS(HOST_SEL_CS, "HOST_SEL_CS"); 7627 TEST_CS_TR_FLAGS(HOST_SEL_TR, "HOST_SEL_TR"); 7628 7629 /* 7630 * SS field can not be 0x0000 if "host address-space size" VM-exit 7631 * control is 0 7632 */ 7633 selector_saved = vmcs_read(HOST_SEL_SS); 7634 vmcs_write(HOST_SEL_SS, 0); 7635 report_prefix_pushf("HOST_SEL_SS 0"); 7636 if (vmcs_read(EXI_CONTROLS) & EXI_HOST_64) { 7637 test_vmx_vmlaunch(0); 7638 } else { 7639 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7640 } 7641 report_prefix_pop(); 7642 7643 vmcs_write(HOST_SEL_SS, selector_saved); 7644 7645 /* 7646 * Base address for FS, GS and TR must be canonical 7647 */ 7648 test_canonical(HOST_BASE_FS, "HOST_BASE_FS", true); 7649 test_canonical(HOST_BASE_GS, "HOST_BASE_GS", true); 7650 test_canonical(HOST_BASE_TR, "HOST_BASE_TR", true); 7651 } 7652 7653 /* 7654 * On processors that support Intel 64 architecture, the base-address 7655 * fields for GDTR and IDTR must contain canonical addresses. 7656 */ 7657 static void test_host_desc_tables(void) 7658 { 7659 test_canonical(HOST_BASE_GDTR, "HOST_BASE_GDTR", true); 7660 test_canonical(HOST_BASE_IDTR, "HOST_BASE_IDTR", true); 7661 } 7662 7663 /* 7664 * If the "host address-space size" VM-exit control is 0, the following must 7665 * hold: 7666 * - The "IA-32e mode guest" VM-entry control is 0. 7667 * - Bit 17 of the CR4 field (corresponding to CR4.PCIDE) is 0. 7668 * - Bits 63:32 in the RIP field are 0. 7669 * 7670 * If the "host address-space size" VM-exit control is 1, the following must 7671 * hold: 7672 * - Bit 5 of the CR4 field (corresponding to CR4.PAE) is 1. 7673 * - The RIP field contains a canonical address. 7674 * 7675 */ 7676 static void test_host_addr_size(void) 7677 { 7678 u64 cr4_saved = vmcs_read(HOST_CR4); 7679 u64 rip_saved = vmcs_read(HOST_RIP); 7680 u64 entry_ctrl_saved = vmcs_read(ENT_CONTROLS); 7681 int i; 7682 u64 tmp; 7683 7684 if (vmcs_read(EXI_CONTROLS) & EXI_HOST_64) { 7685 vmcs_write(ENT_CONTROLS, entry_ctrl_saved | ENT_GUEST_64); 7686 report_prefix_pushf("\"IA-32e mode guest\" enabled"); 7687 test_vmx_vmlaunch(0); 7688 report_prefix_pop(); 7689 7690 vmcs_write(HOST_CR4, cr4_saved | X86_CR4_PCIDE); 7691 report_prefix_pushf("\"CR4.PCIDE\" set"); 7692 test_vmx_vmlaunch(0); 7693 report_prefix_pop(); 7694 7695 for (i = 32; i <= 63; i = i + 4) { 7696 tmp = rip_saved | 1ull << i; 7697 vmcs_write(HOST_RIP, tmp); 7698 report_prefix_pushf("HOST_RIP %lx", tmp); 7699 test_vmx_vmlaunch(0); 7700 report_prefix_pop(); 7701 } 7702 7703 if (cr4_saved & X86_CR4_PAE) { 7704 vmcs_write(HOST_CR4, cr4_saved & ~X86_CR4_PAE); 7705 report_prefix_pushf("\"CR4.PAE\" unset"); 7706 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7707 } else { 7708 report_prefix_pushf("\"CR4.PAE\" set"); 7709 test_vmx_vmlaunch(0); 7710 } 7711 report_prefix_pop(); 7712 7713 vmcs_write(HOST_RIP, NONCANONICAL); 7714 report_prefix_pushf("HOST_RIP %llx", NONCANONICAL); 7715 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7716 report_prefix_pop(); 7717 7718 vmcs_write(ENT_CONTROLS, entry_ctrl_saved | ENT_GUEST_64); 7719 vmcs_write(HOST_RIP, rip_saved); 7720 vmcs_write(HOST_CR4, cr4_saved); 7721 7722 /* Restore host's active RIP and CR4 values. */ 7723 report_prefix_pushf("restore host state"); 7724 test_vmx_vmlaunch(0); 7725 report_prefix_pop(); 7726 } 7727 } 7728 7729 /* 7730 * Check that the virtual CPU checks the VMX Host State Area as 7731 * documented in the Intel SDM. 7732 */ 7733 static void vmx_host_state_area_test(void) 7734 { 7735 /* 7736 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 7737 * fail due to invalid guest state, should we make it that 7738 * far. 7739 */ 7740 vmcs_write(GUEST_RFLAGS, 0); 7741 7742 test_host_ctl_regs(); 7743 7744 test_canonical(HOST_SYSENTER_ESP, "HOST_SYSENTER_ESP", true); 7745 test_canonical(HOST_SYSENTER_EIP, "HOST_SYSENTER_EIP", true); 7746 7747 test_host_efer(); 7748 test_load_host_pat(); 7749 test_host_segment_regs(); 7750 test_host_desc_tables(); 7751 test_host_addr_size(); 7752 test_load_host_perf_global_ctrl(); 7753 } 7754 7755 /* 7756 * If the "load debug controls" VM-entry control is 1, bits 63:32 in 7757 * the DR7 field must be 0. 7758 * 7759 * [Intel SDM] 7760 */ 7761 static void test_guest_dr7(void) 7762 { 7763 u32 ent_saved = vmcs_read(ENT_CONTROLS); 7764 u64 dr7_saved = vmcs_read(GUEST_DR7); 7765 u64 val; 7766 int i; 7767 7768 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS) { 7769 vmcs_clear_bits(ENT_CONTROLS, ENT_LOAD_DBGCTLS); 7770 for (i = 0; i < 64; i++) { 7771 val = 1ull << i; 7772 vmcs_write(GUEST_DR7, val); 7773 test_guest_state("ENT_LOAD_DBGCTLS disabled", false, 7774 val, "GUEST_DR7"); 7775 } 7776 } 7777 if (ctrl_enter_rev.clr & ENT_LOAD_DBGCTLS) { 7778 vmcs_set_bits(ENT_CONTROLS, ENT_LOAD_DBGCTLS); 7779 for (i = 0; i < 64; i++) { 7780 val = 1ull << i; 7781 vmcs_write(GUEST_DR7, val); 7782 test_guest_state("ENT_LOAD_DBGCTLS enabled", i >= 32, 7783 val, "GUEST_DR7"); 7784 } 7785 } 7786 vmcs_write(GUEST_DR7, dr7_saved); 7787 vmcs_write(ENT_CONTROLS, ent_saved); 7788 } 7789 7790 /* 7791 * If the "load IA32_PAT" VM-entry control is 1, the value of the field 7792 * for the IA32_PAT MSR must be one that could be written by WRMSR 7793 * without fault at CPL 0. Specifically, each of the 8 bytes in the 7794 * field must have one of the values 0 (UC), 1 (WC), 4 (WT), 5 (WP), 7795 * 6 (WB), or 7 (UC-). 7796 * 7797 * [Intel SDM] 7798 */ 7799 static void test_load_guest_pat(void) 7800 { 7801 /* 7802 * "load IA32_PAT" VM-entry control 7803 */ 7804 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 7805 printf("\"Load-IA32-PAT\" entry control not supported\n"); 7806 return; 7807 } 7808 7809 test_pat(GUEST_PAT, "GUEST_PAT", ENT_CONTROLS, ENT_LOAD_PAT); 7810 } 7811 7812 #define MSR_IA32_BNDCFGS_RSVD_MASK 0x00000ffc 7813 7814 /* 7815 * If the "load IA32_BNDCFGS" VM-entry control is 1, the following 7816 * checks are performed on the field for the IA32_BNDCFGS MSR: 7817 * 7818 * - Bits reserved in the IA32_BNDCFGS MSR must be 0. 7819 * - The linear address in bits 63:12 must be canonical. 7820 * 7821 * [Intel SDM] 7822 */ 7823 static void test_load_guest_bndcfgs(void) 7824 { 7825 u64 bndcfgs_saved = vmcs_read(GUEST_BNDCFGS); 7826 u64 bndcfgs; 7827 7828 if (!(ctrl_enter_rev.clr & ENT_LOAD_BNDCFGS)) { 7829 printf("\"Load-IA32-BNDCFGS\" entry control not supported\n"); 7830 return; 7831 } 7832 7833 vmcs_clear_bits(ENT_CONTROLS, ENT_LOAD_BNDCFGS); 7834 7835 vmcs_write(GUEST_BNDCFGS, NONCANONICAL); 7836 test_guest_state("ENT_LOAD_BNDCFGS disabled", false, 7837 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7838 bndcfgs = bndcfgs_saved | MSR_IA32_BNDCFGS_RSVD_MASK; 7839 vmcs_write(GUEST_BNDCFGS, bndcfgs); 7840 test_guest_state("ENT_LOAD_BNDCFGS disabled", false, 7841 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7842 7843 vmcs_set_bits(ENT_CONTROLS, ENT_LOAD_BNDCFGS); 7844 7845 vmcs_write(GUEST_BNDCFGS, NONCANONICAL); 7846 test_guest_state("ENT_LOAD_BNDCFGS enabled", true, 7847 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7848 bndcfgs = bndcfgs_saved | MSR_IA32_BNDCFGS_RSVD_MASK; 7849 vmcs_write(GUEST_BNDCFGS, bndcfgs); 7850 test_guest_state("ENT_LOAD_BNDCFGS enabled", true, 7851 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7852 7853 vmcs_write(GUEST_BNDCFGS, bndcfgs_saved); 7854 } 7855 7856 #define GUEST_SEG_UNUSABLE_MASK (1u << 16) 7857 #define GUEST_SEG_SEL_TI_MASK (1u << 2) 7858 7859 7860 #define TEST_SEGMENT_SEL(test, xfail, sel, val) \ 7861 do { \ 7862 vmcs_write(sel, val); \ 7863 test_guest_state(test " segment", xfail, val, xstr(sel)); \ 7864 } while (0) 7865 7866 #define TEST_INVALID_SEG_SEL(sel, val) \ 7867 TEST_SEGMENT_SEL("Invalid: " xstr(val), true, sel, val); 7868 7869 #define TEST_VALID_SEG_SEL(sel, val) \ 7870 TEST_SEGMENT_SEL("Valid: " xstr(val), false, sel, val); 7871 7872 /* 7873 * The following checks are done on the Selector field of the Guest Segment 7874 * Registers: 7875 * - TR. The TI flag (bit 2) must be 0. 7876 * - LDTR. If LDTR is usable, the TI flag (bit 2) must be 0. 7877 * - SS. If the guest will not be virtual-8086 and the "unrestricted 7878 * guest" VM-execution control is 0, the RPL (bits 1:0) must equal 7879 * the RPL of the selector field for CS. 7880 * 7881 * [Intel SDM] 7882 */ 7883 static void test_guest_segment_sel_fields(void) 7884 { 7885 u16 sel_saved; 7886 u32 ar_saved; 7887 u32 cpu_ctrl0_saved; 7888 u32 cpu_ctrl1_saved; 7889 u16 cs_rpl_bits; 7890 7891 /* 7892 * Test for GUEST_SEL_TR 7893 */ 7894 sel_saved = vmcs_read(GUEST_SEL_TR); 7895 TEST_INVALID_SEG_SEL(GUEST_SEL_TR, sel_saved | GUEST_SEG_SEL_TI_MASK); 7896 vmcs_write(GUEST_SEL_TR, sel_saved); 7897 7898 /* 7899 * Test for GUEST_SEL_LDTR 7900 */ 7901 sel_saved = vmcs_read(GUEST_SEL_LDTR); 7902 ar_saved = vmcs_read(GUEST_AR_LDTR); 7903 /* LDTR is set unusable */ 7904 vmcs_write(GUEST_AR_LDTR, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7905 TEST_VALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved | GUEST_SEG_SEL_TI_MASK); 7906 TEST_VALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved & ~GUEST_SEG_SEL_TI_MASK); 7907 /* LDTR is set usable */ 7908 vmcs_write(GUEST_AR_LDTR, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7909 TEST_INVALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved | GUEST_SEG_SEL_TI_MASK); 7910 7911 TEST_VALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved & ~GUEST_SEG_SEL_TI_MASK); 7912 7913 vmcs_write(GUEST_AR_LDTR, ar_saved); 7914 vmcs_write(GUEST_SEL_LDTR, sel_saved); 7915 7916 /* 7917 * Test for GUEST_SEL_SS 7918 */ 7919 cpu_ctrl0_saved = vmcs_read(CPU_EXEC_CTRL0); 7920 cpu_ctrl1_saved = vmcs_read(CPU_EXEC_CTRL1); 7921 ar_saved = vmcs_read(GUEST_AR_SS); 7922 /* Turn off "unrestricted guest" vm-execution control */ 7923 vmcs_write(CPU_EXEC_CTRL1, cpu_ctrl1_saved & ~CPU_URG); 7924 cs_rpl_bits = vmcs_read(GUEST_SEL_CS) & 0x3; 7925 sel_saved = vmcs_read(GUEST_SEL_SS); 7926 TEST_INVALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 7927 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 7928 /* Make SS usable if it's unusable or vice-versa */ 7929 if (ar_saved & GUEST_SEG_UNUSABLE_MASK) 7930 vmcs_write(GUEST_AR_SS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7931 else 7932 vmcs_write(GUEST_AR_SS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7933 TEST_INVALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 7934 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 7935 7936 /* Need a valid EPTP as the passing case fully enters the guest. */ 7937 if (enable_unrestricted_guest(true)) 7938 goto skip_ss_tests; 7939 7940 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 7941 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 7942 7943 /* Make SS usable if it's unusable or vice-versa */ 7944 if (vmcs_read(GUEST_AR_SS) & GUEST_SEG_UNUSABLE_MASK) 7945 vmcs_write(GUEST_AR_SS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7946 else 7947 vmcs_write(GUEST_AR_SS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7948 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 7949 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 7950 skip_ss_tests: 7951 7952 vmcs_write(GUEST_AR_SS, ar_saved); 7953 vmcs_write(GUEST_SEL_SS, sel_saved); 7954 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrl0_saved); 7955 vmcs_write(CPU_EXEC_CTRL1, cpu_ctrl1_saved); 7956 } 7957 7958 #define TEST_SEGMENT_BASE_ADDR_UPPER_BITS(xfail, seg_base) \ 7959 do { \ 7960 addr_saved = vmcs_read(seg_base); \ 7961 for (i = 32; i < 63; i = i + 4) { \ 7962 addr = addr_saved | 1ull << i; \ 7963 vmcs_write(seg_base, addr); \ 7964 test_guest_state("seg.BASE[63:32] != 0, usable = " xstr(xfail), \ 7965 xfail, addr, xstr(seg_base)); \ 7966 } \ 7967 vmcs_write(seg_base, addr_saved); \ 7968 } while (0) 7969 7970 #define TEST_SEGMENT_BASE_ADDR_CANONICAL(xfail, seg_base) \ 7971 do { \ 7972 addr_saved = vmcs_read(seg_base); \ 7973 vmcs_write(seg_base, NONCANONICAL); \ 7974 test_guest_state("seg.BASE non-canonical, usable = " xstr(xfail), \ 7975 xfail, NONCANONICAL, xstr(seg_base)); \ 7976 vmcs_write(seg_base, addr_saved); \ 7977 } while (0) 7978 7979 /* 7980 * The following checks are done on the Base Address field of the Guest 7981 * Segment Registers on processors that support Intel 64 architecture: 7982 * - TR, FS, GS : The address must be canonical. 7983 * - LDTR : If LDTR is usable, the address must be canonical. 7984 * - CS : Bits 63:32 of the address must be zero. 7985 * - SS, DS, ES : If the register is usable, bits 63:32 of the address 7986 * must be zero. 7987 * 7988 * [Intel SDM] 7989 */ 7990 static void test_guest_segment_base_addr_fields(void) 7991 { 7992 u64 addr_saved; 7993 u64 addr; 7994 u32 ar_saved; 7995 int i; 7996 7997 /* 7998 * The address of TR, FS, GS and LDTR must be canonical. 7999 */ 8000 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_TR); 8001 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_FS); 8002 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_GS); 8003 ar_saved = vmcs_read(GUEST_AR_LDTR); 8004 /* Make LDTR unusable */ 8005 vmcs_write(GUEST_AR_LDTR, ar_saved | GUEST_SEG_UNUSABLE_MASK); 8006 TEST_SEGMENT_BASE_ADDR_CANONICAL(false, GUEST_BASE_LDTR); 8007 /* Make LDTR usable */ 8008 vmcs_write(GUEST_AR_LDTR, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 8009 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_LDTR); 8010 8011 vmcs_write(GUEST_AR_LDTR, ar_saved); 8012 8013 /* 8014 * Bits 63:32 in CS, SS, DS and ES base address must be zero 8015 */ 8016 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_CS); 8017 ar_saved = vmcs_read(GUEST_AR_SS); 8018 /* Make SS unusable */ 8019 vmcs_write(GUEST_AR_SS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 8020 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(false, GUEST_BASE_SS); 8021 /* Make SS usable */ 8022 vmcs_write(GUEST_AR_SS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 8023 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_SS); 8024 vmcs_write(GUEST_AR_SS, ar_saved); 8025 8026 ar_saved = vmcs_read(GUEST_AR_DS); 8027 /* Make DS unusable */ 8028 vmcs_write(GUEST_AR_DS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 8029 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(false, GUEST_BASE_DS); 8030 /* Make DS usable */ 8031 vmcs_write(GUEST_AR_DS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 8032 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_DS); 8033 vmcs_write(GUEST_AR_DS, ar_saved); 8034 8035 ar_saved = vmcs_read(GUEST_AR_ES); 8036 /* Make ES unusable */ 8037 vmcs_write(GUEST_AR_ES, ar_saved | GUEST_SEG_UNUSABLE_MASK); 8038 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(false, GUEST_BASE_ES); 8039 /* Make ES usable */ 8040 vmcs_write(GUEST_AR_ES, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 8041 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_ES); 8042 vmcs_write(GUEST_AR_ES, ar_saved); 8043 } 8044 8045 /* 8046 * Check that the virtual CPU checks the VMX Guest State Area as 8047 * documented in the Intel SDM. 8048 */ 8049 static void vmx_guest_state_area_test(void) 8050 { 8051 vmx_set_test_stage(1); 8052 test_set_guest(guest_state_test_main); 8053 8054 /* 8055 * The IA32_SYSENTER_ESP field and the IA32_SYSENTER_EIP field 8056 * must each contain a canonical address. 8057 */ 8058 test_canonical(GUEST_SYSENTER_ESP, "GUEST_SYSENTER_ESP", false); 8059 test_canonical(GUEST_SYSENTER_EIP, "GUEST_SYSENTER_EIP", false); 8060 8061 test_guest_dr7(); 8062 test_load_guest_pat(); 8063 test_guest_efer(); 8064 test_load_guest_perf_global_ctrl(); 8065 test_load_guest_bndcfgs(); 8066 8067 test_guest_segment_sel_fields(); 8068 test_guest_segment_base_addr_fields(); 8069 8070 test_canonical(GUEST_BASE_GDTR, "GUEST_BASE_GDTR", false); 8071 test_canonical(GUEST_BASE_IDTR, "GUEST_BASE_IDTR", false); 8072 8073 u32 guest_desc_limit_saved = vmcs_read(GUEST_LIMIT_GDTR); 8074 int i; 8075 for (i = 16; i <= 31; i++) { 8076 u32 tmp = guest_desc_limit_saved | (1ull << i); 8077 vmcs_write(GUEST_LIMIT_GDTR, tmp); 8078 test_guest_state("GDT.limit > 0xffff", true, tmp, "GUEST_LIMIT_GDTR"); 8079 } 8080 vmcs_write(GUEST_LIMIT_GDTR, guest_desc_limit_saved); 8081 8082 guest_desc_limit_saved = vmcs_read(GUEST_LIMIT_IDTR); 8083 for (i = 16; i <= 31; i++) { 8084 u32 tmp = guest_desc_limit_saved | (1ull << i); 8085 vmcs_write(GUEST_LIMIT_IDTR, tmp); 8086 test_guest_state("IDT.limit > 0xffff", true, tmp, "GUEST_LIMIT_IDTR"); 8087 } 8088 vmcs_write(GUEST_LIMIT_IDTR, guest_desc_limit_saved); 8089 8090 /* 8091 * Let the guest finish execution 8092 */ 8093 vmx_set_test_stage(2); 8094 enter_guest(); 8095 } 8096 8097 extern void unrestricted_guest_main(void); 8098 asm (".code32\n" 8099 "unrestricted_guest_main:\n" 8100 "vmcall\n" 8101 "nop\n" 8102 "mov $1, %edi\n" 8103 "call hypercall\n" 8104 ".code64\n"); 8105 8106 static void setup_unrestricted_guest(void) 8107 { 8108 vmcs_write(GUEST_CR0, vmcs_read(GUEST_CR0) & ~(X86_CR0_PG)); 8109 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) & ~ENT_GUEST_64); 8110 vmcs_write(GUEST_EFER, vmcs_read(GUEST_EFER) & ~EFER_LMA); 8111 vmcs_write(GUEST_RIP, virt_to_phys(unrestricted_guest_main)); 8112 } 8113 8114 static void unsetup_unrestricted_guest(void) 8115 { 8116 vmcs_write(GUEST_CR0, vmcs_read(GUEST_CR0) | X86_CR0_PG); 8117 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) | ENT_GUEST_64); 8118 vmcs_write(GUEST_EFER, vmcs_read(GUEST_EFER) | EFER_LMA); 8119 vmcs_write(GUEST_RIP, (u64) phys_to_virt(vmcs_read(GUEST_RIP))); 8120 vmcs_write(GUEST_RSP, (u64) phys_to_virt(vmcs_read(GUEST_RSP))); 8121 } 8122 8123 /* 8124 * If "unrestricted guest" secondary VM-execution control is set, guests 8125 * can run in unpaged protected mode. 8126 */ 8127 static void vmentry_unrestricted_guest_test(void) 8128 { 8129 if (enable_unrestricted_guest(true)) { 8130 report_skip("Unrestricted guest not supported"); 8131 return; 8132 } 8133 8134 test_set_guest(unrestricted_guest_main); 8135 setup_unrestricted_guest(); 8136 test_guest_state("Unrestricted guest test", false, CPU_URG, "CPU_URG"); 8137 8138 /* 8139 * Let the guest finish execution as a regular guest 8140 */ 8141 unsetup_unrestricted_guest(); 8142 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) & ~CPU_URG); 8143 enter_guest(); 8144 } 8145 8146 static bool valid_vmcs_for_vmentry(void) 8147 { 8148 struct vmcs *current_vmcs = NULL; 8149 8150 if (vmcs_save(¤t_vmcs)) 8151 return false; 8152 8153 return current_vmcs && !current_vmcs->hdr.shadow_vmcs; 8154 } 8155 8156 static void try_vmentry_in_movss_shadow(void) 8157 { 8158 u32 vm_inst_err; 8159 u32 flags; 8160 bool early_failure = false; 8161 u32 expected_flags = X86_EFLAGS_FIXED; 8162 bool valid_vmcs = valid_vmcs_for_vmentry(); 8163 8164 expected_flags |= valid_vmcs ? X86_EFLAGS_ZF : X86_EFLAGS_CF; 8165 8166 /* 8167 * Indirectly set VM_INST_ERR to 12 ("VMREAD/VMWRITE from/to 8168 * unsupported VMCS component"). 8169 */ 8170 vmcs_write(~0u, 0); 8171 8172 __asm__ __volatile__ ("mov %[host_rsp], %%edx;" 8173 "vmwrite %%rsp, %%rdx;" 8174 "mov 0f, %%rax;" 8175 "mov %[host_rip], %%edx;" 8176 "vmwrite %%rax, %%rdx;" 8177 "mov $-1, %%ah;" 8178 "sahf;" 8179 "mov %%ss, %%ax;" 8180 "mov %%ax, %%ss;" 8181 "vmlaunch;" 8182 "mov $1, %[early_failure];" 8183 "0: lahf;" 8184 "movzbl %%ah, %[flags]" 8185 : [early_failure] "+r" (early_failure), 8186 [flags] "=&a" (flags) 8187 : [host_rsp] "i" (HOST_RSP), 8188 [host_rip] "i" (HOST_RIP) 8189 : "rdx", "cc", "memory"); 8190 vm_inst_err = vmcs_read(VMX_INST_ERROR); 8191 8192 report(early_failure, "Early VM-entry failure"); 8193 report(flags == expected_flags, "RFLAGS[8:0] is %x (actual %x)", 8194 expected_flags, flags); 8195 if (valid_vmcs) 8196 report(vm_inst_err == VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, 8197 "VM-instruction error is %d (actual %d)", 8198 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, vm_inst_err); 8199 } 8200 8201 static void vmentry_movss_shadow_test(void) 8202 { 8203 struct vmcs *orig_vmcs; 8204 8205 TEST_ASSERT(!vmcs_save(&orig_vmcs)); 8206 8207 /* 8208 * Set the launched flag on the current VMCS to verify the correct 8209 * error priority, below. 8210 */ 8211 test_set_guest(v2_null_test_guest); 8212 enter_guest(); 8213 8214 /* 8215 * With bit 1 of the guest's RFLAGS clear, VM-entry should 8216 * fail due to invalid guest state (if we make it that far). 8217 */ 8218 vmcs_write(GUEST_RFLAGS, 0); 8219 8220 /* 8221 * "VM entry with events blocked by MOV SS" takes precedence over 8222 * "VMLAUNCH with non-clear VMCS." 8223 */ 8224 report_prefix_push("valid current-VMCS"); 8225 try_vmentry_in_movss_shadow(); 8226 report_prefix_pop(); 8227 8228 /* 8229 * VMfailInvalid takes precedence over "VM entry with events 8230 * blocked by MOV SS." 8231 */ 8232 TEST_ASSERT(!vmcs_clear(orig_vmcs)); 8233 report_prefix_push("no current-VMCS"); 8234 try_vmentry_in_movss_shadow(); 8235 report_prefix_pop(); 8236 8237 TEST_ASSERT(!make_vmcs_current(orig_vmcs)); 8238 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 8239 } 8240 8241 static void vmx_ldtr_test_guest(void) 8242 { 8243 u16 ldtr = sldt(); 8244 8245 report(ldtr == NP_SEL, "Expected %x for L2 LDTR selector (got %x)", 8246 NP_SEL, ldtr); 8247 } 8248 8249 /* 8250 * Ensure that the L1 LDTR is set to 0 on VM-exit. 8251 */ 8252 static void vmx_ldtr_test(void) 8253 { 8254 const u8 ldt_ar = 0x82; /* Present LDT */ 8255 u16 sel = FIRST_SPARE_SEL; 8256 8257 /* Set up a non-zero L1 LDTR prior to VM-entry. */ 8258 set_gdt_entry(sel, 0, 0, ldt_ar, 0); 8259 lldt(sel); 8260 8261 test_set_guest(vmx_ldtr_test_guest); 8262 /* 8263 * Set up a different LDTR for L2. The actual GDT contents are 8264 * irrelevant, since we stuff the hidden descriptor state 8265 * straight into the VMCS rather than reading it from the GDT. 8266 */ 8267 vmcs_write(GUEST_SEL_LDTR, NP_SEL); 8268 vmcs_write(GUEST_AR_LDTR, ldt_ar); 8269 enter_guest(); 8270 8271 /* 8272 * VM-exit should clear LDTR (and make it unusable, but we 8273 * won't verify that here). 8274 */ 8275 sel = sldt(); 8276 report(!sel, "Expected 0 for L1 LDTR selector (got %x)", sel); 8277 } 8278 8279 static void vmx_single_vmcall_guest(void) 8280 { 8281 vmcall(); 8282 } 8283 8284 static void vmx_cr_load_test(void) 8285 { 8286 unsigned long cr3, cr4, orig_cr3, orig_cr4; 8287 u32 ctrls[2] = {0}; 8288 pgd_t *pml5; 8289 8290 orig_cr4 = read_cr4(); 8291 orig_cr3 = read_cr3(); 8292 8293 if (!this_cpu_has(X86_FEATURE_PCID)) { 8294 report_skip("PCID not detected"); 8295 return; 8296 } 8297 if (!this_cpu_has(X86_FEATURE_MCE)) { 8298 report_skip("MCE not detected"); 8299 return; 8300 } 8301 8302 TEST_ASSERT(!(orig_cr3 & X86_CR3_PCID_MASK)); 8303 8304 /* Enable PCID for L1. */ 8305 cr4 = orig_cr4 | X86_CR4_PCIDE; 8306 cr3 = orig_cr3 | 0x1; 8307 TEST_ASSERT(!write_cr4_checking(cr4)); 8308 write_cr3(cr3); 8309 8310 test_set_guest(vmx_single_vmcall_guest); 8311 vmcs_write(HOST_CR4, cr4); 8312 vmcs_write(HOST_CR3, cr3); 8313 enter_guest(); 8314 8315 /* 8316 * No exception is expected. 8317 * 8318 * NB. KVM loads the last guest write to CR4 into CR4 read 8319 * shadow. In order to trigger an exit to KVM, we can toggle a 8320 * bit that is owned by KVM. We use CR4.MCE, which shall 8321 * have no side effect because normally no guest MCE (e.g., as the 8322 * result of bad memory) would happen during this test. 8323 */ 8324 TEST_ASSERT(!write_cr4_checking(cr4 ^ X86_CR4_MCE)); 8325 8326 /* Cleanup L1 state. */ 8327 write_cr3(orig_cr3); 8328 TEST_ASSERT(!write_cr4_checking(orig_cr4)); 8329 8330 if (!this_cpu_has(X86_FEATURE_LA57)) 8331 goto done; 8332 8333 /* 8334 * Allocate a full page for PML5 to guarantee alignment, though only 8335 * the first entry needs to be filled (the test's virtual addresses 8336 * most definitely do not have any of bits 56:48 set). 8337 */ 8338 pml5 = alloc_page(); 8339 *pml5 = orig_cr3 | PT_PRESENT_MASK | PT_WRITABLE_MASK; 8340 8341 /* 8342 * Transition to/from 5-level paging in the host via VM-Exit. CR4.LA57 8343 * can't be toggled while long is active via MOV CR4, but there are no 8344 * such restrictions on VM-Exit. 8345 */ 8346 lol_5level: 8347 vmcs_write(HOST_CR4, orig_cr4 | X86_CR4_LA57); 8348 vmcs_write(HOST_CR3, virt_to_phys(pml5)); 8349 enter_guest(); 8350 8351 /* 8352 * VMREAD with a memory operand to verify KVM detects the LA57 change, 8353 * e.g. uses the correct guest root level in gva_to_gpa(). 8354 */ 8355 TEST_ASSERT(vmcs_readm(HOST_CR3) == virt_to_phys(pml5)); 8356 TEST_ASSERT(vmcs_readm(HOST_CR4) == (orig_cr4 | X86_CR4_LA57)); 8357 8358 vmcs_write(HOST_CR4, orig_cr4); 8359 vmcs_write(HOST_CR3, orig_cr3); 8360 enter_guest(); 8361 8362 TEST_ASSERT(vmcs_readm(HOST_CR3) == orig_cr3); 8363 TEST_ASSERT(vmcs_readm(HOST_CR4) == orig_cr4); 8364 8365 /* 8366 * And now do the same LA57 shenanigans with EPT enabled. KVM uses 8367 * two separate MMUs when L1 uses TDP, whereas the above shadow paging 8368 * version shares an MMU between L1 and L2. 8369 * 8370 * If the saved execution controls are non-zero then the EPT version 8371 * has already run. In that case, restore the old controls. If EPT 8372 * setup fails, e.g. EPT isn't supported, fall through and finish up. 8373 */ 8374 if (ctrls[0]) { 8375 vmcs_write(CPU_EXEC_CTRL0, ctrls[0]); 8376 vmcs_write(CPU_EXEC_CTRL1, ctrls[1]); 8377 } else if (!setup_ept(false)) { 8378 ctrls[0] = vmcs_read(CPU_EXEC_CTRL0); 8379 ctrls[1] = vmcs_read(CPU_EXEC_CTRL1); 8380 goto lol_5level; 8381 } 8382 8383 free_page(pml5); 8384 8385 done: 8386 skip_exit_vmcall(); 8387 enter_guest(); 8388 } 8389 8390 static void vmx_cr4_osxsave_test_guest(void) 8391 { 8392 write_cr4(read_cr4() & ~X86_CR4_OSXSAVE); 8393 } 8394 8395 /* 8396 * Ensure that kvm recalculates the L1 guest's CPUID.01H:ECX.OSXSAVE 8397 * after VM-exit from an L2 guest that sets CR4.OSXSAVE to a different 8398 * value than in L1. 8399 */ 8400 static void vmx_cr4_osxsave_test(void) 8401 { 8402 if (!this_cpu_has(X86_FEATURE_XSAVE)) { 8403 report_skip("XSAVE not detected"); 8404 return; 8405 } 8406 8407 if (!(read_cr4() & X86_CR4_OSXSAVE)) { 8408 unsigned long cr4 = read_cr4() | X86_CR4_OSXSAVE; 8409 8410 write_cr4(cr4); 8411 vmcs_write(GUEST_CR4, cr4); 8412 vmcs_write(HOST_CR4, cr4); 8413 } 8414 8415 TEST_ASSERT(cpuid_osxsave()); 8416 8417 test_set_guest(vmx_cr4_osxsave_test_guest); 8418 enter_guest(); 8419 8420 TEST_ASSERT(cpuid_osxsave()); 8421 } 8422 8423 static void vmx_nm_test_guest(void) 8424 { 8425 write_cr0(read_cr0() | X86_CR0_TS); 8426 asm volatile("fnop"); 8427 } 8428 8429 static void check_nm_exit(const char *test) 8430 { 8431 u32 reason = vmcs_read(EXI_REASON); 8432 u32 intr_info = vmcs_read(EXI_INTR_INFO); 8433 const u32 expected = INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 8434 NM_VECTOR; 8435 8436 report(reason == VMX_EXC_NMI && intr_info == expected, "%s", test); 8437 } 8438 8439 /* 8440 * This test checks that: 8441 * 8442 * (a) If L2 launches with CR0.TS clear, but later sets CR0.TS, then 8443 * a subsequent #NM VM-exit is reflected to L1. 8444 * 8445 * (b) If L2 launches with CR0.TS clear and CR0.EM set, then a 8446 * subsequent #NM VM-exit is reflected to L1. 8447 */ 8448 static void vmx_nm_test(void) 8449 { 8450 unsigned long cr0 = read_cr0(); 8451 8452 test_set_guest(vmx_nm_test_guest); 8453 8454 /* 8455 * L1 wants to intercept #NM exceptions encountered in L2. 8456 */ 8457 vmcs_write(EXC_BITMAP, 1 << NM_VECTOR); 8458 8459 /* 8460 * Launch L2 with CR0.TS clear, but don't claim host ownership of 8461 * any CR0 bits. L2 will set CR0.TS and then try to execute fnop, 8462 * which will raise #NM. L0 should reflect the #NM VM-exit to L1. 8463 */ 8464 vmcs_write(CR0_MASK, 0); 8465 vmcs_write(GUEST_CR0, cr0 & ~X86_CR0_TS); 8466 enter_guest(); 8467 check_nm_exit("fnop with CR0.TS set in L2 triggers #NM VM-exit to L1"); 8468 8469 /* 8470 * Re-enter L2 at the fnop instruction, with CR0.TS clear but 8471 * CR0.EM set. The fnop will still raise #NM, and L0 should 8472 * reflect the #NM VM-exit to L1. 8473 */ 8474 vmcs_write(GUEST_CR0, (cr0 & ~X86_CR0_TS) | X86_CR0_EM); 8475 enter_guest(); 8476 check_nm_exit("fnop with CR0.EM set in L2 triggers #NM VM-exit to L1"); 8477 8478 /* 8479 * Re-enter L2 at the fnop instruction, with both CR0.TS and 8480 * CR0.EM clear. There will be no #NM, and the L2 guest should 8481 * exit normally. 8482 */ 8483 vmcs_write(GUEST_CR0, cr0 & ~(X86_CR0_TS | X86_CR0_EM)); 8484 enter_guest(); 8485 } 8486 8487 bool vmx_pending_event_ipi_fired; 8488 static void vmx_pending_event_ipi_isr(isr_regs_t *regs) 8489 { 8490 vmx_pending_event_ipi_fired = true; 8491 eoi(); 8492 } 8493 8494 bool vmx_pending_event_guest_run; 8495 static void vmx_pending_event_guest(void) 8496 { 8497 vmcall(); 8498 vmx_pending_event_guest_run = true; 8499 } 8500 8501 static void vmx_pending_event_test_core(bool guest_hlt) 8502 { 8503 int ipi_vector = 0xf1; 8504 8505 vmx_pending_event_ipi_fired = false; 8506 handle_irq(ipi_vector, vmx_pending_event_ipi_isr); 8507 8508 vmx_pending_event_guest_run = false; 8509 test_set_guest(vmx_pending_event_guest); 8510 8511 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 8512 8513 enter_guest(); 8514 skip_exit_vmcall(); 8515 8516 if (guest_hlt) 8517 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8518 8519 irq_disable(); 8520 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | 8521 APIC_DM_FIXED | ipi_vector, 8522 0); 8523 8524 enter_guest(); 8525 8526 assert_exit_reason(VMX_EXTINT); 8527 report(!vmx_pending_event_guest_run, 8528 "Guest did not run before host received IPI"); 8529 8530 irq_enable(); 8531 asm volatile ("nop"); 8532 irq_disable(); 8533 report(vmx_pending_event_ipi_fired, 8534 "Got pending interrupt after IRQ enabled"); 8535 8536 if (guest_hlt) 8537 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 8538 8539 enter_guest(); 8540 report(vmx_pending_event_guest_run, 8541 "Guest finished running when no interrupt"); 8542 } 8543 8544 static void vmx_pending_event_test(void) 8545 { 8546 vmx_pending_event_test_core(false); 8547 } 8548 8549 static void vmx_pending_event_hlt_test(void) 8550 { 8551 vmx_pending_event_test_core(true); 8552 } 8553 8554 static int vmx_window_test_db_count; 8555 8556 static void vmx_window_test_db_handler(struct ex_regs *regs) 8557 { 8558 vmx_window_test_db_count++; 8559 } 8560 8561 static void vmx_nmi_window_test_guest(void) 8562 { 8563 handle_exception(DB_VECTOR, vmx_window_test_db_handler); 8564 8565 asm volatile("vmcall\n\t" 8566 "nop\n\t"); 8567 8568 handle_exception(DB_VECTOR, NULL); 8569 } 8570 8571 static void verify_nmi_window_exit(u64 rip) 8572 { 8573 u32 exit_reason = vmcs_read(EXI_REASON); 8574 8575 report(exit_reason == VMX_NMI_WINDOW, 8576 "Exit reason (%d) is 'NMI window'", exit_reason); 8577 report(vmcs_read(GUEST_RIP) == rip, "RIP (%#lx) is %#lx", 8578 vmcs_read(GUEST_RIP), rip); 8579 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 8580 } 8581 8582 static void vmx_nmi_window_test(void) 8583 { 8584 u64 nop_addr; 8585 void *db_fault_addr = get_idt_addr(&boot_idt[DB_VECTOR]); 8586 8587 if (!(ctrl_pin_rev.clr & PIN_VIRT_NMI)) { 8588 report_skip("CPU does not support the \"Virtual NMIs\" VM-execution control."); 8589 return; 8590 } 8591 8592 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 8593 report_skip("CPU does not support the \"NMI-window exiting\" VM-execution control."); 8594 return; 8595 } 8596 8597 vmx_window_test_db_count = 0; 8598 8599 report_prefix_push("NMI-window"); 8600 test_set_guest(vmx_nmi_window_test_guest); 8601 vmcs_set_bits(PIN_CONTROLS, PIN_VIRT_NMI); 8602 enter_guest(); 8603 skip_exit_vmcall(); 8604 nop_addr = vmcs_read(GUEST_RIP); 8605 8606 /* 8607 * Ask for "NMI-window exiting," and expect an immediate VM-exit. 8608 * RIP will not advance. 8609 */ 8610 report_prefix_push("active, no blocking"); 8611 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 8612 enter_guest(); 8613 verify_nmi_window_exit(nop_addr); 8614 report_prefix_pop(); 8615 8616 /* 8617 * Ask for "NMI-window exiting" in a MOV-SS shadow, and expect 8618 * a VM-exit on the next instruction after the nop. (The nop 8619 * is one byte.) 8620 */ 8621 report_prefix_push("active, blocking by MOV-SS"); 8622 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 8623 enter_guest(); 8624 verify_nmi_window_exit(nop_addr + 1); 8625 report_prefix_pop(); 8626 8627 /* 8628 * Ask for "NMI-window exiting" (with event injection), and 8629 * expect a VM-exit after the event is injected. (RIP should 8630 * be at the address specified in the IDT entry for #DB.) 8631 */ 8632 report_prefix_push("active, no blocking, injecting #DB"); 8633 vmcs_write(ENT_INTR_INFO, 8634 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 8635 enter_guest(); 8636 verify_nmi_window_exit((u64)db_fault_addr); 8637 report_prefix_pop(); 8638 8639 /* 8640 * Ask for "NMI-window exiting" with NMI blocking, and expect 8641 * a VM-exit after the next IRET (i.e. after the #DB handler 8642 * returns). So, RIP should be back at one byte past the nop. 8643 */ 8644 report_prefix_push("active, blocking by NMI"); 8645 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_NMI); 8646 enter_guest(); 8647 verify_nmi_window_exit(nop_addr + 1); 8648 report(vmx_window_test_db_count == 1, 8649 "#DB handler executed once (actual %d times)", 8650 vmx_window_test_db_count); 8651 report_prefix_pop(); 8652 8653 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 8654 report_skip("CPU does not support activity state HLT."); 8655 } else { 8656 /* 8657 * Ask for "NMI-window exiting" when entering activity 8658 * state HLT, and expect an immediate VM-exit. RIP is 8659 * still one byte past the nop. 8660 */ 8661 report_prefix_push("halted, no blocking"); 8662 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8663 enter_guest(); 8664 verify_nmi_window_exit(nop_addr + 1); 8665 report_prefix_pop(); 8666 8667 /* 8668 * Ask for "NMI-window exiting" when entering activity 8669 * state HLT (with event injection), and expect a 8670 * VM-exit after the event is injected. (RIP should be 8671 * at the address specified in the IDT entry for #DB.) 8672 */ 8673 report_prefix_push("halted, no blocking, injecting #DB"); 8674 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8675 vmcs_write(ENT_INTR_INFO, 8676 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 8677 DB_VECTOR); 8678 enter_guest(); 8679 verify_nmi_window_exit((u64)db_fault_addr); 8680 report_prefix_pop(); 8681 } 8682 8683 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 8684 enter_guest(); 8685 report_prefix_pop(); 8686 } 8687 8688 static void vmx_intr_window_test_guest(void) 8689 { 8690 handle_exception(DB_VECTOR, vmx_window_test_db_handler); 8691 8692 /* 8693 * The two consecutive STIs are to ensure that only the first 8694 * one has a shadow. Note that NOP and STI are one byte 8695 * instructions. 8696 */ 8697 asm volatile("vmcall\n\t" 8698 "nop\n\t" 8699 "sti\n\t" 8700 "sti\n\t"); 8701 8702 handle_exception(DB_VECTOR, NULL); 8703 } 8704 8705 static void verify_intr_window_exit(u64 rip) 8706 { 8707 u32 exit_reason = vmcs_read(EXI_REASON); 8708 8709 report(exit_reason == VMX_INTR_WINDOW, 8710 "Exit reason (%d) is 'interrupt window'", exit_reason); 8711 report(vmcs_read(GUEST_RIP) == rip, "RIP (%#lx) is %#lx", 8712 vmcs_read(GUEST_RIP), rip); 8713 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 8714 } 8715 8716 static void vmx_intr_window_test(void) 8717 { 8718 u64 vmcall_addr; 8719 u64 nop_addr; 8720 unsigned int orig_db_gate_type; 8721 void *db_fault_addr = get_idt_addr(&boot_idt[DB_VECTOR]); 8722 8723 if (!(ctrl_cpu_rev[0].clr & CPU_INTR_WINDOW)) { 8724 report_skip("CPU does not support the \"interrupt-window exiting\" VM-execution control."); 8725 return; 8726 } 8727 8728 /* 8729 * Change the IDT entry for #DB from interrupt gate to trap gate, 8730 * so that it won't clear RFLAGS.IF. We don't want interrupts to 8731 * be disabled after vectoring a #DB. 8732 */ 8733 orig_db_gate_type = boot_idt[DB_VECTOR].type; 8734 boot_idt[DB_VECTOR].type = 15; 8735 8736 report_prefix_push("interrupt-window"); 8737 test_set_guest(vmx_intr_window_test_guest); 8738 enter_guest(); 8739 assert_exit_reason(VMX_VMCALL); 8740 vmcall_addr = vmcs_read(GUEST_RIP); 8741 8742 /* 8743 * Ask for "interrupt-window exiting" with RFLAGS.IF set and 8744 * no blocking; expect an immediate VM-exit. Note that we have 8745 * not advanced past the vmcall instruction yet, so RIP should 8746 * point to the vmcall instruction. 8747 */ 8748 report_prefix_push("active, no blocking, RFLAGS.IF=1"); 8749 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8750 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_IF); 8751 enter_guest(); 8752 verify_intr_window_exit(vmcall_addr); 8753 report_prefix_pop(); 8754 8755 /* 8756 * Ask for "interrupt-window exiting" (with event injection) 8757 * with RFLAGS.IF set and no blocking; expect a VM-exit after 8758 * the event is injected. That is, RIP should should be at the 8759 * address specified in the IDT entry for #DB. 8760 */ 8761 report_prefix_push("active, no blocking, RFLAGS.IF=1, injecting #DB"); 8762 vmcs_write(ENT_INTR_INFO, 8763 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 8764 vmcall_addr = vmcs_read(GUEST_RIP); 8765 enter_guest(); 8766 verify_intr_window_exit((u64)db_fault_addr); 8767 report_prefix_pop(); 8768 8769 /* 8770 * Let the L2 guest run through the IRET, back to the VMCALL. 8771 * We have to clear the "interrupt-window exiting" 8772 * VM-execution control, or it would just keep causing 8773 * VM-exits. Then, advance past the VMCALL and set the 8774 * "interrupt-window exiting" VM-execution control again. 8775 */ 8776 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8777 enter_guest(); 8778 skip_exit_vmcall(); 8779 nop_addr = vmcs_read(GUEST_RIP); 8780 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8781 8782 /* 8783 * Ask for "interrupt-window exiting" in a MOV-SS shadow with 8784 * RFLAGS.IF set, and expect a VM-exit on the next 8785 * instruction. (NOP is one byte.) 8786 */ 8787 report_prefix_push("active, blocking by MOV-SS, RFLAGS.IF=1"); 8788 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 8789 enter_guest(); 8790 verify_intr_window_exit(nop_addr + 1); 8791 report_prefix_pop(); 8792 8793 /* 8794 * Back up to the NOP and ask for "interrupt-window exiting" 8795 * in an STI shadow with RFLAGS.IF set, and expect a VM-exit 8796 * on the next instruction. (NOP is one byte.) 8797 */ 8798 report_prefix_push("active, blocking by STI, RFLAGS.IF=1"); 8799 vmcs_write(GUEST_RIP, nop_addr); 8800 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_STI); 8801 enter_guest(); 8802 verify_intr_window_exit(nop_addr + 1); 8803 report_prefix_pop(); 8804 8805 /* 8806 * Ask for "interrupt-window exiting" with RFLAGS.IF clear, 8807 * and expect a VM-exit on the instruction following the STI 8808 * shadow. Only the first STI (which is one byte past the NOP) 8809 * should have a shadow. The second STI (which is two bytes 8810 * past the NOP) has no shadow. Therefore, the interrupt 8811 * window opens at three bytes past the NOP. 8812 */ 8813 report_prefix_push("active, RFLAGS.IF = 0"); 8814 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 8815 enter_guest(); 8816 verify_intr_window_exit(nop_addr + 3); 8817 report_prefix_pop(); 8818 8819 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 8820 report_skip("CPU does not support activity state HLT."); 8821 } else { 8822 /* 8823 * Ask for "interrupt-window exiting" when entering 8824 * activity state HLT, and expect an immediate 8825 * VM-exit. RIP is still three bytes past the nop. 8826 */ 8827 report_prefix_push("halted, no blocking"); 8828 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8829 enter_guest(); 8830 verify_intr_window_exit(nop_addr + 3); 8831 report_prefix_pop(); 8832 8833 /* 8834 * Ask for "interrupt-window exiting" when entering 8835 * activity state HLT (with event injection), and 8836 * expect a VM-exit after the event is injected. That 8837 * is, RIP should should be at the address specified 8838 * in the IDT entry for #DB. 8839 */ 8840 report_prefix_push("halted, no blocking, injecting #DB"); 8841 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8842 vmcs_write(ENT_INTR_INFO, 8843 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 8844 DB_VECTOR); 8845 enter_guest(); 8846 verify_intr_window_exit((u64)db_fault_addr); 8847 report_prefix_pop(); 8848 } 8849 8850 boot_idt[DB_VECTOR].type = orig_db_gate_type; 8851 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8852 enter_guest(); 8853 report_prefix_pop(); 8854 } 8855 8856 #define GUEST_TSC_OFFSET (1u << 30) 8857 8858 static u64 guest_tsc; 8859 8860 static void vmx_store_tsc_test_guest(void) 8861 { 8862 guest_tsc = rdtsc(); 8863 } 8864 8865 /* 8866 * This test ensures that when IA32_TSC is in the VM-exit MSR-store 8867 * list, the value saved is not subject to the TSC offset that is 8868 * applied to RDTSC/RDTSCP/RDMSR(IA32_TSC) in guest execution. 8869 */ 8870 static void vmx_store_tsc_test(void) 8871 { 8872 struct vmx_msr_entry msr_entry = { .index = MSR_IA32_TSC }; 8873 u64 low, high; 8874 8875 if (!(ctrl_cpu_rev[0].clr & CPU_USE_TSC_OFFSET)) { 8876 report_skip("'Use TSC offsetting' not supported"); 8877 return; 8878 } 8879 8880 test_set_guest(vmx_store_tsc_test_guest); 8881 8882 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_USE_TSC_OFFSET); 8883 vmcs_write(EXI_MSR_ST_CNT, 1); 8884 vmcs_write(EXIT_MSR_ST_ADDR, virt_to_phys(&msr_entry)); 8885 vmcs_write(TSC_OFFSET, GUEST_TSC_OFFSET); 8886 8887 low = rdtsc(); 8888 enter_guest(); 8889 high = rdtsc(); 8890 8891 report(low + GUEST_TSC_OFFSET <= guest_tsc && 8892 guest_tsc <= high + GUEST_TSC_OFFSET, 8893 "RDTSC value in the guest (%lu) is in range [%lu, %lu]", 8894 guest_tsc, low + GUEST_TSC_OFFSET, high + GUEST_TSC_OFFSET); 8895 report(low <= msr_entry.value && msr_entry.value <= high, 8896 "IA32_TSC value saved in the VM-exit MSR-store list (%lu) is in range [%lu, %lu]", 8897 msr_entry.value, low, high); 8898 } 8899 8900 static void vmx_preemption_timer_zero_test_db_handler(struct ex_regs *regs) 8901 { 8902 } 8903 8904 static void vmx_preemption_timer_zero_test_guest(void) 8905 { 8906 while (vmx_get_test_stage() < 3) 8907 vmcall(); 8908 } 8909 8910 static void vmx_preemption_timer_zero_activate_preemption_timer(void) 8911 { 8912 vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT); 8913 vmcs_write(PREEMPT_TIMER_VALUE, 0); 8914 } 8915 8916 static void vmx_preemption_timer_zero_advance_past_vmcall(void) 8917 { 8918 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 8919 enter_guest(); 8920 skip_exit_vmcall(); 8921 } 8922 8923 static void vmx_preemption_timer_zero_inject_db(bool intercept_db) 8924 { 8925 vmx_preemption_timer_zero_activate_preemption_timer(); 8926 vmcs_write(ENT_INTR_INFO, INTR_INFO_VALID_MASK | 8927 INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 8928 vmcs_write(EXC_BITMAP, intercept_db ? 1 << DB_VECTOR : 0); 8929 enter_guest(); 8930 } 8931 8932 static void vmx_preemption_timer_zero_set_pending_dbg(u32 exception_bitmap) 8933 { 8934 vmx_preemption_timer_zero_activate_preemption_timer(); 8935 vmcs_write(GUEST_PENDING_DEBUG, BIT(12) | DR_TRAP1); 8936 vmcs_write(EXC_BITMAP, exception_bitmap); 8937 enter_guest(); 8938 } 8939 8940 static void vmx_preemption_timer_zero_expect_preempt_at_rip(u64 expected_rip) 8941 { 8942 u32 reason = (u32)vmcs_read(EXI_REASON); 8943 u64 guest_rip = vmcs_read(GUEST_RIP); 8944 8945 report(reason == VMX_PREEMPT && guest_rip == expected_rip, 8946 "Exit reason is 0x%x (expected 0x%x) and guest RIP is %lx (0x%lx expected).", 8947 reason, VMX_PREEMPT, guest_rip, expected_rip); 8948 } 8949 8950 /* 8951 * This test ensures that when the VMX preemption timer is zero at 8952 * VM-entry, a VM-exit occurs after any event injection and after any 8953 * pending debug exceptions are raised, but before execution of any 8954 * guest instructions. 8955 */ 8956 static void vmx_preemption_timer_zero_test(void) 8957 { 8958 u64 db_fault_address = (u64)get_idt_addr(&boot_idt[DB_VECTOR]); 8959 handler old_db; 8960 u32 reason; 8961 8962 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 8963 report_skip("'Activate VMX-preemption timer' not supported"); 8964 return; 8965 } 8966 8967 /* 8968 * Install a custom #DB handler that doesn't abort. 8969 */ 8970 old_db = handle_exception(DB_VECTOR, 8971 vmx_preemption_timer_zero_test_db_handler); 8972 8973 test_set_guest(vmx_preemption_timer_zero_test_guest); 8974 8975 /* 8976 * VMX-preemption timer should fire after event injection. 8977 */ 8978 vmx_set_test_stage(0); 8979 vmx_preemption_timer_zero_inject_db(0); 8980 vmx_preemption_timer_zero_expect_preempt_at_rip(db_fault_address); 8981 vmx_preemption_timer_zero_advance_past_vmcall(); 8982 8983 /* 8984 * VMX-preemption timer should fire after event injection. 8985 * Exception bitmap is irrelevant, since you can't intercept 8986 * an event that you injected. 8987 */ 8988 vmx_set_test_stage(1); 8989 vmx_preemption_timer_zero_inject_db(true); 8990 vmx_preemption_timer_zero_expect_preempt_at_rip(db_fault_address); 8991 vmx_preemption_timer_zero_advance_past_vmcall(); 8992 8993 /* 8994 * VMX-preemption timer should fire after pending debug exceptions 8995 * have delivered a #DB trap. 8996 */ 8997 vmx_set_test_stage(2); 8998 vmx_preemption_timer_zero_set_pending_dbg(0); 8999 vmx_preemption_timer_zero_expect_preempt_at_rip(db_fault_address); 9000 vmx_preemption_timer_zero_advance_past_vmcall(); 9001 9002 /* 9003 * VMX-preemption timer would fire after pending debug exceptions 9004 * have delivered a #DB trap, but in this case, the #DB trap is 9005 * intercepted. 9006 */ 9007 vmx_set_test_stage(3); 9008 vmx_preemption_timer_zero_set_pending_dbg(1 << DB_VECTOR); 9009 reason = (u32)vmcs_read(EXI_REASON); 9010 report(reason == VMX_EXC_NMI, "Exit reason is 0x%x (expected 0x%x)", 9011 reason, VMX_EXC_NMI); 9012 9013 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 9014 enter_guest(); 9015 9016 handle_exception(DB_VECTOR, old_db); 9017 } 9018 9019 static u64 vmx_preemption_timer_tf_test_prev_rip; 9020 9021 static void vmx_preemption_timer_tf_test_db_handler(struct ex_regs *regs) 9022 { 9023 extern char vmx_preemption_timer_tf_test_endloop; 9024 9025 if (vmx_get_test_stage() == 2) { 9026 /* 9027 * Stage 2 means that we're done, one way or another. 9028 * Arrange for the iret to drop us out of the wbinvd 9029 * loop and stop single-stepping. 9030 */ 9031 regs->rip = (u64)&vmx_preemption_timer_tf_test_endloop; 9032 regs->rflags &= ~X86_EFLAGS_TF; 9033 } else if (regs->rip == vmx_preemption_timer_tf_test_prev_rip) { 9034 /* 9035 * The RIP should alternate between the wbinvd and the 9036 * jmp instruction in the code below. If we ever see 9037 * the same instruction twice in a row, that means a 9038 * single-step trap has been dropped. Let the 9039 * hypervisor know about the failure by executing a 9040 * VMCALL. 9041 */ 9042 vmcall(); 9043 } 9044 vmx_preemption_timer_tf_test_prev_rip = regs->rip; 9045 } 9046 9047 static void vmx_preemption_timer_tf_test_guest(void) 9048 { 9049 /* 9050 * The hypervisor doesn't intercept WBINVD, so the loop below 9051 * shouldn't be a problem--it's just two instructions 9052 * executing in VMX non-root mode. However, when the 9053 * hypervisor is running in a virtual environment, the parent 9054 * hypervisor might intercept WBINVD and emulate it. If the 9055 * parent hypervisor is broken, the single-step trap after the 9056 * WBINVD might be lost. 9057 */ 9058 asm volatile("vmcall\n\t" 9059 "0: wbinvd\n\t" 9060 "1: jmp 0b\n\t" 9061 "vmx_preemption_timer_tf_test_endloop:"); 9062 } 9063 9064 /* 9065 * Ensure that the delivery of a "VMX-preemption timer expired" 9066 * VM-exit doesn't disrupt single-stepping in the guest. Note that 9067 * passing this test doesn't ensure correctness, because the test will 9068 * only fail if the VMX-preemtion timer fires at the right time (or 9069 * the wrong time, as it were). 9070 */ 9071 static void vmx_preemption_timer_tf_test(void) 9072 { 9073 handler old_db; 9074 u32 reason; 9075 int i; 9076 9077 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 9078 report_skip("'Activate VMX-preemption timer' not supported"); 9079 return; 9080 } 9081 9082 old_db = handle_exception(DB_VECTOR, 9083 vmx_preemption_timer_tf_test_db_handler); 9084 9085 test_set_guest(vmx_preemption_timer_tf_test_guest); 9086 9087 enter_guest(); 9088 skip_exit_vmcall(); 9089 9090 vmx_set_test_stage(1); 9091 vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT); 9092 vmcs_write(PREEMPT_TIMER_VALUE, 50000); 9093 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_TF); 9094 9095 /* 9096 * The only exit we should see is "VMX-preemption timer 9097 * expired." If we get a VMCALL exit, that means the #DB 9098 * handler has detected a missing single-step trap. It doesn't 9099 * matter where the guest RIP is when the VMX-preemption timer 9100 * expires (whether it's in the WBINVD loop or in the #DB 9101 * handler)--a single-step trap should never be discarded. 9102 */ 9103 for (i = 0; i < 10000; i++) { 9104 enter_guest(); 9105 reason = (u32)vmcs_read(EXI_REASON); 9106 if (reason == VMX_PREEMPT) 9107 continue; 9108 TEST_ASSERT(reason == VMX_VMCALL); 9109 skip_exit_insn(); 9110 break; 9111 } 9112 9113 report(reason == VMX_PREEMPT, "No single-step traps skipped"); 9114 9115 vmx_set_test_stage(2); 9116 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 9117 enter_guest(); 9118 9119 handle_exception(DB_VECTOR, old_db); 9120 } 9121 9122 #define VMX_PREEMPTION_TIMER_EXPIRY_CYCLES 1000000 9123 9124 static u64 vmx_preemption_timer_expiry_start; 9125 static u64 vmx_preemption_timer_expiry_finish; 9126 9127 static void vmx_preemption_timer_expiry_test_guest(void) 9128 { 9129 vmcall(); 9130 vmx_preemption_timer_expiry_start = fenced_rdtsc(); 9131 9132 while (vmx_get_test_stage() == 0) 9133 vmx_preemption_timer_expiry_finish = fenced_rdtsc(); 9134 } 9135 9136 /* 9137 * Test that the VMX-preemption timer is not excessively delayed. 9138 * 9139 * Per the SDM, volume 3, VM-entry starts the VMX-preemption timer 9140 * with the unsigned value in the VMX-preemption timer-value field, 9141 * and the VMX-preemption timer counts down by 1 every time bit X in 9142 * the TSC changes due to a TSC increment (where X is 9143 * IA32_VMX_MISC[4:0]). If the timer counts down to zero in any state 9144 * other than the wait-for-SIPI state, the logical processor 9145 * transitions to the C0 C-state and causes a VM-exit. 9146 * 9147 * The guest code above reads the starting TSC after VM-entry. At this 9148 * point, the VMX-preemption timer has already been activated. Next, 9149 * the guest code reads the current TSC in a loop, storing the value 9150 * read to memory. 9151 * 9152 * If the RDTSC in the loop reads a value past the VMX-preemption 9153 * timer deadline, then the VMX-preemption timer VM-exit must be 9154 * delivered before the next instruction retires. Even if a higher 9155 * priority SMI is delivered first, the VMX-preemption timer VM-exit 9156 * must be delivered before the next instruction retires. Hence, a TSC 9157 * value past the VMX-preemption timer deadline might be read, but it 9158 * cannot be stored. If a TSC value past the deadline *is* stored, 9159 * then the architectural specification has been violated. 9160 */ 9161 static void vmx_preemption_timer_expiry_test(void) 9162 { 9163 u32 preemption_timer_value; 9164 union vmx_misc misc; 9165 u64 tsc_deadline; 9166 u32 reason; 9167 9168 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 9169 report_skip("'Activate VMX-preemption timer' not supported"); 9170 return; 9171 } 9172 9173 test_set_guest(vmx_preemption_timer_expiry_test_guest); 9174 9175 enter_guest(); 9176 skip_exit_vmcall(); 9177 9178 misc.val = rdmsr(MSR_IA32_VMX_MISC); 9179 preemption_timer_value = 9180 VMX_PREEMPTION_TIMER_EXPIRY_CYCLES >> misc.pt_bit; 9181 9182 vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT); 9183 vmcs_write(PREEMPT_TIMER_VALUE, preemption_timer_value); 9184 vmx_set_test_stage(0); 9185 9186 enter_guest(); 9187 reason = (u32)vmcs_read(EXI_REASON); 9188 TEST_ASSERT(reason == VMX_PREEMPT); 9189 9190 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 9191 vmx_set_test_stage(1); 9192 enter_guest(); 9193 9194 tsc_deadline = ((vmx_preemption_timer_expiry_start >> misc.pt_bit) << 9195 misc.pt_bit) + (preemption_timer_value << misc.pt_bit); 9196 9197 report(vmx_preemption_timer_expiry_finish < tsc_deadline, 9198 "Last stored guest TSC (%lu) < TSC deadline (%lu)", 9199 vmx_preemption_timer_expiry_finish, tsc_deadline); 9200 } 9201 9202 static void vmx_db_test_guest(void) 9203 { 9204 /* 9205 * For a hardware generated single-step #DB. 9206 */ 9207 asm volatile("vmcall;" 9208 "nop;" 9209 ".Lpost_nop:"); 9210 /* 9211 * ...in a MOVSS shadow, with pending debug exceptions. 9212 */ 9213 asm volatile("vmcall;" 9214 "nop;" 9215 ".Lpost_movss_nop:"); 9216 /* 9217 * For an L0 synthesized single-step #DB. (L0 intercepts WBINVD and 9218 * emulates it in software.) 9219 */ 9220 asm volatile("vmcall;" 9221 "wbinvd;" 9222 ".Lpost_wbinvd:"); 9223 /* 9224 * ...in a MOVSS shadow, with pending debug exceptions. 9225 */ 9226 asm volatile("vmcall;" 9227 "wbinvd;" 9228 ".Lpost_movss_wbinvd:"); 9229 /* 9230 * For a hardware generated single-step #DB in a transactional region. 9231 */ 9232 asm volatile("vmcall;" 9233 ".Lxbegin: xbegin .Lskip_rtm;" 9234 "xend;" 9235 ".Lskip_rtm:"); 9236 } 9237 9238 /* 9239 * Clear the pending debug exceptions and RFLAGS.TF and re-enter 9240 * L2. No #DB is delivered and L2 continues to the next point of 9241 * interest. 9242 */ 9243 static void dismiss_db(void) 9244 { 9245 vmcs_write(GUEST_PENDING_DEBUG, 0); 9246 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 9247 enter_guest(); 9248 } 9249 9250 /* 9251 * Check a variety of VMCS fields relevant to an intercepted #DB exception. 9252 * Then throw away the #DB exception and resume L2. 9253 */ 9254 static void check_db_exit(bool xfail_qual, bool xfail_dr6, bool xfail_pdbg, 9255 void *expected_rip, u64 expected_exit_qual, 9256 u64 expected_dr6) 9257 { 9258 u32 reason = vmcs_read(EXI_REASON); 9259 u32 intr_info = vmcs_read(EXI_INTR_INFO); 9260 u64 exit_qual = vmcs_read(EXI_QUALIFICATION); 9261 u64 guest_rip = vmcs_read(GUEST_RIP); 9262 u64 guest_pending_dbg = vmcs_read(GUEST_PENDING_DEBUG); 9263 u64 dr6 = read_dr6(); 9264 const u32 expected_intr_info = INTR_INFO_VALID_MASK | 9265 INTR_TYPE_HARD_EXCEPTION | DB_VECTOR; 9266 9267 report(reason == VMX_EXC_NMI && intr_info == expected_intr_info, 9268 "Expected #DB VM-exit"); 9269 report((u64)expected_rip == guest_rip, "Expected RIP %p (actual %lx)", 9270 expected_rip, guest_rip); 9271 report_xfail(xfail_pdbg, 0 == guest_pending_dbg, 9272 "Expected pending debug exceptions 0 (actual %lx)", 9273 guest_pending_dbg); 9274 report_xfail(xfail_qual, expected_exit_qual == exit_qual, 9275 "Expected exit qualification %lx (actual %lx)", 9276 expected_exit_qual, exit_qual); 9277 report_xfail(xfail_dr6, expected_dr6 == dr6, 9278 "Expected DR6 %lx (actual %lx)", expected_dr6, dr6); 9279 dismiss_db(); 9280 } 9281 9282 /* 9283 * Assuming the guest has just exited on a VMCALL instruction, skip 9284 * over the vmcall, and set the guest's RFLAGS.TF in the VMCS. If 9285 * pending debug exceptions are non-zero, set the VMCS up as if the 9286 * previous instruction was a MOVSS that generated the indicated 9287 * pending debug exceptions. Then enter L2. 9288 */ 9289 static void single_step_guest(const char *test_name, u64 starting_dr6, 9290 u64 pending_debug_exceptions) 9291 { 9292 printf("\n%s\n", test_name); 9293 skip_exit_vmcall(); 9294 write_dr6(starting_dr6); 9295 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_TF); 9296 if (pending_debug_exceptions) { 9297 vmcs_write(GUEST_PENDING_DEBUG, pending_debug_exceptions); 9298 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 9299 } 9300 enter_guest(); 9301 } 9302 9303 /* 9304 * When L1 intercepts #DB, verify that a single-step trap clears 9305 * pending debug exceptions, populates the exit qualification field 9306 * properly, and that DR6 is not prematurely clobbered. In a 9307 * (simulated) MOVSS shadow, make sure that the pending debug 9308 * exception bits are properly accumulated into the exit qualification 9309 * field. 9310 */ 9311 static void vmx_db_test(void) 9312 { 9313 /* 9314 * We are going to set a few arbitrary bits in DR6 to verify that 9315 * (a) DR6 is not modified by an intercepted #DB, and 9316 * (b) stale bits in DR6 (DR6.BD, in particular) don't leak into 9317 * the exit qualification field for a subsequent #DB exception. 9318 */ 9319 const u64 starting_dr6 = DR6_RESERVED | BIT(13) | DR_TRAP3 | DR_TRAP1; 9320 extern char post_nop asm(".Lpost_nop"); 9321 extern char post_movss_nop asm(".Lpost_movss_nop"); 9322 extern char post_wbinvd asm(".Lpost_wbinvd"); 9323 extern char post_movss_wbinvd asm(".Lpost_movss_wbinvd"); 9324 extern char xbegin asm(".Lxbegin"); 9325 extern char skip_rtm asm(".Lskip_rtm"); 9326 9327 /* 9328 * L1 wants to intercept #DB exceptions encountered in L2. 9329 */ 9330 vmcs_write(EXC_BITMAP, BIT(DB_VECTOR)); 9331 9332 /* 9333 * Start L2 and run it up to the first point of interest. 9334 */ 9335 test_set_guest(vmx_db_test_guest); 9336 enter_guest(); 9337 9338 /* 9339 * Hardware-delivered #DB trap for single-step sets the 9340 * standard that L0 has to follow for emulated instructions. 9341 */ 9342 single_step_guest("Hardware delivered single-step", starting_dr6, 0); 9343 check_db_exit(false, false, false, &post_nop, DR_STEP, starting_dr6); 9344 9345 /* 9346 * Hardware-delivered #DB trap for single-step in MOVSS shadow 9347 * also sets the standard that L0 has to follow for emulated 9348 * instructions. Here, we establish the VMCS pending debug 9349 * exceptions to indicate that the simulated MOVSS triggered a 9350 * data breakpoint as well as the single-step trap. 9351 */ 9352 single_step_guest("Hardware delivered single-step in MOVSS shadow", 9353 starting_dr6, BIT(12) | DR_STEP | DR_TRAP0 ); 9354 check_db_exit(false, false, false, &post_movss_nop, DR_STEP | DR_TRAP0, 9355 starting_dr6); 9356 9357 /* 9358 * L0 synthesized #DB trap for single-step is buggy, because 9359 * kvm (a) clobbers DR6 too early, and (b) tries its best to 9360 * reconstitute the exit qualification from the prematurely 9361 * modified DR6, but fails miserably. 9362 */ 9363 single_step_guest("Software synthesized single-step", starting_dr6, 0); 9364 check_db_exit(false, false, false, &post_wbinvd, DR_STEP, starting_dr6); 9365 9366 /* 9367 * L0 synthesized #DB trap for single-step in MOVSS shadow is 9368 * even worse, because L0 also leaves the pending debug 9369 * exceptions in the VMCS instead of accumulating them into 9370 * the exit qualification field for the #DB exception. 9371 */ 9372 single_step_guest("Software synthesized single-step in MOVSS shadow", 9373 starting_dr6, BIT(12) | DR_STEP | DR_TRAP0); 9374 check_db_exit(true, false, true, &post_movss_wbinvd, DR_STEP | DR_TRAP0, 9375 starting_dr6); 9376 9377 /* 9378 * Optional RTM test for hardware that supports RTM, to 9379 * demonstrate that the current volume 3 of the SDM 9380 * (325384-067US), table 27-1 is incorrect. Bit 16 of the exit 9381 * qualification for debug exceptions is not reserved. It is 9382 * set to 1 if a debug exception (#DB) or a breakpoint 9383 * exception (#BP) occurs inside an RTM region while advanced 9384 * debugging of RTM transactional regions is enabled. 9385 */ 9386 if (this_cpu_has(X86_FEATURE_RTM)) { 9387 vmcs_write(ENT_CONTROLS, 9388 vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 9389 /* 9390 * Set DR7.RTM[bit 11] and IA32_DEBUGCTL.RTM[bit 15] 9391 * in the guest to enable advanced debugging of RTM 9392 * transactional regions. 9393 */ 9394 vmcs_write(GUEST_DR7, BIT(11)); 9395 vmcs_write(GUEST_DEBUGCTL, BIT(15)); 9396 single_step_guest("Hardware delivered single-step in " 9397 "transactional region", starting_dr6, 0); 9398 check_db_exit(false, false, false, &xbegin, BIT(16), 9399 starting_dr6); 9400 } else { 9401 vmcs_write(GUEST_RIP, (u64)&skip_rtm); 9402 enter_guest(); 9403 } 9404 } 9405 9406 static void enable_vid(void) 9407 { 9408 void *virtual_apic_page; 9409 9410 assert(cpu_has_apicv()); 9411 9412 disable_intercept_for_x2apic_msrs(); 9413 9414 virtual_apic_page = alloc_page(); 9415 vmcs_write(APIC_VIRT_ADDR, (u64)virtual_apic_page); 9416 9417 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 9418 9419 vmcs_write(EOI_EXIT_BITMAP0, 0x0); 9420 vmcs_write(EOI_EXIT_BITMAP1, 0x0); 9421 vmcs_write(EOI_EXIT_BITMAP2, 0x0); 9422 vmcs_write(EOI_EXIT_BITMAP3, 0x0); 9423 9424 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY | CPU_TPR_SHADOW); 9425 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_VINTD | CPU_VIRT_X2APIC); 9426 } 9427 9428 static void trigger_ioapic_scan_thread(void *data) 9429 { 9430 /* Wait until other CPU entered L2 */ 9431 while (vmx_get_test_stage() != 1) 9432 ; 9433 9434 /* Trigger ioapic scan */ 9435 ioapic_set_redir(0xf, 0x79, TRIGGER_LEVEL); 9436 vmx_set_test_stage(2); 9437 } 9438 9439 static void irq_79_handler_guest(isr_regs_t *regs) 9440 { 9441 eoi(); 9442 9443 /* L1 expects vmexit on VMX_VMCALL and not VMX_EOI_INDUCED */ 9444 vmcall(); 9445 } 9446 9447 /* 9448 * Constant for num of busy-loop iterations after which 9449 * a timer interrupt should have happened in host 9450 */ 9451 #define TIMER_INTERRUPT_DELAY 100000000 9452 9453 static void vmx_eoi_bitmap_ioapic_scan_test_guest(void) 9454 { 9455 handle_irq(0x79, irq_79_handler_guest); 9456 irq_enable(); 9457 9458 /* Signal to L1 CPU to trigger ioapic scan */ 9459 vmx_set_test_stage(1); 9460 /* Wait until L1 CPU to trigger ioapic scan */ 9461 while (vmx_get_test_stage() != 2) 9462 ; 9463 9464 /* 9465 * Wait for L0 timer interrupt to be raised while we run in L2 9466 * such that L0 will process the IOAPIC scan request before 9467 * resuming L2 9468 */ 9469 delay(TIMER_INTERRUPT_DELAY); 9470 9471 asm volatile ("int $0x79"); 9472 } 9473 9474 static void vmx_eoi_bitmap_ioapic_scan_test(void) 9475 { 9476 if (!cpu_has_apicv() || (cpu_count() < 2)) { 9477 report_skip(__func__); 9478 return; 9479 } 9480 9481 enable_vid(); 9482 9483 on_cpu_async(1, trigger_ioapic_scan_thread, NULL); 9484 test_set_guest(vmx_eoi_bitmap_ioapic_scan_test_guest); 9485 9486 /* 9487 * Launch L2. 9488 * We expect the exit reason to be VMX_VMCALL (and not EOI INDUCED). 9489 * In case the reason isn't VMX_VMCALL, the asserion inside 9490 * skip_exit_vmcall() will fail. 9491 */ 9492 enter_guest(); 9493 skip_exit_vmcall(); 9494 9495 /* Let L2 finish */ 9496 enter_guest(); 9497 report_pass(__func__); 9498 } 9499 9500 #define HLT_WITH_RVI_VECTOR (0xf1) 9501 9502 bool vmx_hlt_with_rvi_guest_isr_fired; 9503 static void vmx_hlt_with_rvi_guest_isr(isr_regs_t *regs) 9504 { 9505 vmx_hlt_with_rvi_guest_isr_fired = true; 9506 eoi(); 9507 } 9508 9509 static void vmx_hlt_with_rvi_guest(void) 9510 { 9511 handle_irq(HLT_WITH_RVI_VECTOR, vmx_hlt_with_rvi_guest_isr); 9512 9513 irq_enable(); 9514 asm volatile ("nop"); 9515 9516 vmcall(); 9517 } 9518 9519 static void vmx_hlt_with_rvi_test(void) 9520 { 9521 if (!cpu_has_apicv()) { 9522 report_skip(__func__); 9523 return; 9524 } 9525 9526 enable_vid(); 9527 9528 vmx_hlt_with_rvi_guest_isr_fired = false; 9529 test_set_guest(vmx_hlt_with_rvi_guest); 9530 9531 enter_guest(); 9532 skip_exit_vmcall(); 9533 9534 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 9535 vmcs_write(GUEST_INT_STATUS, HLT_WITH_RVI_VECTOR); 9536 enter_guest(); 9537 9538 report(vmx_hlt_with_rvi_guest_isr_fired, "Interrupt raised in guest"); 9539 } 9540 9541 static void set_irq_line_thread(void *data) 9542 { 9543 /* Wait until other CPU entered L2 */ 9544 while (vmx_get_test_stage() != 1) 9545 ; 9546 9547 /* Set irq-line 0xf to raise vector 0x78 for vCPU 0 */ 9548 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 9549 vmx_set_test_stage(2); 9550 } 9551 9552 static bool irq_78_handler_vmcall_before_eoi; 9553 static void irq_78_handler_guest(isr_regs_t *regs) 9554 { 9555 set_irq_line(0xf, 0); 9556 if (irq_78_handler_vmcall_before_eoi) 9557 vmcall(); 9558 eoi(); 9559 vmcall(); 9560 } 9561 9562 static void vmx_apic_passthrough_guest(void) 9563 { 9564 handle_irq(0x78, irq_78_handler_guest); 9565 irq_enable(); 9566 9567 /* If requested, wait for other CPU to trigger ioapic scan */ 9568 if (vmx_get_test_stage() < 1) { 9569 vmx_set_test_stage(1); 9570 while (vmx_get_test_stage() != 2) 9571 ; 9572 } 9573 9574 set_irq_line(0xf, 1); 9575 } 9576 9577 static void vmx_apic_passthrough(bool set_irq_line_from_thread) 9578 { 9579 if (set_irq_line_from_thread && (cpu_count() < 2)) { 9580 report_skip(__func__); 9581 return; 9582 } 9583 9584 /* Test device is required for generating IRQs */ 9585 if (!test_device_enabled()) { 9586 report_skip(__func__); 9587 return; 9588 } 9589 u64 cpu_ctrl_0 = CPU_SECONDARY; 9590 u64 cpu_ctrl_1 = 0; 9591 9592 disable_intercept_for_x2apic_msrs(); 9593 9594 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 9595 9596 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 9597 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 9598 9599 if (set_irq_line_from_thread) { 9600 irq_78_handler_vmcall_before_eoi = false; 9601 on_cpu_async(1, set_irq_line_thread, NULL); 9602 } else { 9603 irq_78_handler_vmcall_before_eoi = true; 9604 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 9605 vmx_set_test_stage(2); 9606 } 9607 test_set_guest(vmx_apic_passthrough_guest); 9608 9609 if (irq_78_handler_vmcall_before_eoi) { 9610 /* Before EOI remote_irr should still be set */ 9611 enter_guest(); 9612 skip_exit_vmcall(); 9613 TEST_ASSERT_EQ_MSG(1, (int)ioapic_read_redir(0xf).remote_irr, 9614 "IOAPIC pass-through: remote_irr=1 before EOI"); 9615 } 9616 9617 /* After EOI remote_irr should be cleared */ 9618 enter_guest(); 9619 skip_exit_vmcall(); 9620 TEST_ASSERT_EQ_MSG(0, (int)ioapic_read_redir(0xf).remote_irr, 9621 "IOAPIC pass-through: remote_irr=0 after EOI"); 9622 9623 /* Let L2 finish */ 9624 enter_guest(); 9625 report_pass(__func__); 9626 } 9627 9628 static void vmx_apic_passthrough_test(void) 9629 { 9630 vmx_apic_passthrough(false); 9631 } 9632 9633 static void vmx_apic_passthrough_thread_test(void) 9634 { 9635 vmx_apic_passthrough(true); 9636 } 9637 9638 static void vmx_apic_passthrough_tpr_threshold_guest(void) 9639 { 9640 cli(); 9641 apic_set_tpr(0); 9642 } 9643 9644 static bool vmx_apic_passthrough_tpr_threshold_ipi_isr_fired; 9645 static void vmx_apic_passthrough_tpr_threshold_ipi_isr(isr_regs_t *regs) 9646 { 9647 vmx_apic_passthrough_tpr_threshold_ipi_isr_fired = true; 9648 eoi(); 9649 } 9650 9651 static void vmx_apic_passthrough_tpr_threshold_test(void) 9652 { 9653 int ipi_vector = 0xe1; 9654 9655 disable_intercept_for_x2apic_msrs(); 9656 vmcs_clear_bits(PIN_CONTROLS, PIN_EXTINT); 9657 9658 /* Raise L0 TPR-threshold by queueing vector in LAPIC IRR */ 9659 cli(); 9660 apic_set_tpr((ipi_vector >> 4) + 1); 9661 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | 9662 APIC_DM_FIXED | ipi_vector, 9663 0); 9664 9665 test_set_guest(vmx_apic_passthrough_tpr_threshold_guest); 9666 enter_guest(); 9667 9668 report(apic_get_tpr() == 0, "TPR was zero by guest"); 9669 9670 /* Clean pending self-IPI */ 9671 vmx_apic_passthrough_tpr_threshold_ipi_isr_fired = false; 9672 handle_irq(ipi_vector, vmx_apic_passthrough_tpr_threshold_ipi_isr); 9673 sti(); 9674 asm volatile ("nop"); 9675 report(vmx_apic_passthrough_tpr_threshold_ipi_isr_fired, "self-IPI fired"); 9676 9677 report_pass(__func__); 9678 } 9679 9680 static u64 init_signal_test_exit_reason; 9681 static bool init_signal_test_thread_continued; 9682 9683 static void init_signal_test_thread(void *data) 9684 { 9685 struct vmcs *test_vmcs = data; 9686 9687 /* Enter VMX operation (i.e. exec VMXON) */ 9688 u64 *ap_vmxon_region = alloc_page(); 9689 enable_vmx(); 9690 init_vmx(ap_vmxon_region); 9691 _vmx_on(ap_vmxon_region); 9692 9693 /* Signal CPU have entered VMX operation */ 9694 vmx_set_test_stage(1); 9695 9696 /* Wait for BSP CPU to send INIT signal */ 9697 while (vmx_get_test_stage() != 2) 9698 ; 9699 9700 /* 9701 * Signal that we continue as usual as INIT signal 9702 * should be blocked while CPU is in VMX operation 9703 */ 9704 vmx_set_test_stage(3); 9705 9706 /* Wait for signal to enter VMX non-root mode */ 9707 while (vmx_get_test_stage() != 4) 9708 ; 9709 9710 /* Enter VMX non-root mode */ 9711 test_set_guest(v2_null_test_guest); 9712 make_vmcs_current(test_vmcs); 9713 enter_guest(); 9714 /* Save exit reason for BSP CPU to compare to expected result */ 9715 init_signal_test_exit_reason = vmcs_read(EXI_REASON); 9716 /* VMCLEAR test-vmcs so it could be loaded by BSP CPU */ 9717 vmcs_clear(test_vmcs); 9718 launched = false; 9719 /* Signal that CPU exited to VMX root mode */ 9720 vmx_set_test_stage(5); 9721 9722 /* Wait for BSP CPU to signal to exit VMX operation */ 9723 while (vmx_get_test_stage() != 6) 9724 ; 9725 9726 /* Exit VMX operation (i.e. exec VMXOFF) */ 9727 vmx_off(); 9728 9729 /* 9730 * Signal to BSP CPU that we continue as usual as INIT signal 9731 * should have been consumed by VMX_INIT exit from guest 9732 */ 9733 vmx_set_test_stage(7); 9734 9735 /* Wait for BSP CPU to signal to enter VMX operation */ 9736 while (vmx_get_test_stage() != 8) 9737 ; 9738 /* Enter VMX operation (i.e. exec VMXON) */ 9739 _vmx_on(ap_vmxon_region); 9740 /* Signal to BSP we are in VMX operation */ 9741 vmx_set_test_stage(9); 9742 9743 /* Wait for BSP CPU to send INIT signal */ 9744 while (vmx_get_test_stage() != 10) 9745 ; 9746 9747 /* Exit VMX operation (i.e. exec VMXOFF) */ 9748 vmx_off(); 9749 9750 /* 9751 * Exiting VMX operation should result in latched 9752 * INIT signal being processed. Therefore, we should 9753 * never reach the below code. Thus, signal to BSP 9754 * CPU if we have reached here so it is able to 9755 * report an issue if it happens. 9756 */ 9757 init_signal_test_thread_continued = true; 9758 } 9759 9760 #define INIT_SIGNAL_TEST_DELAY 100000000ULL 9761 9762 static void vmx_init_signal_test(void) 9763 { 9764 struct vmcs *test_vmcs; 9765 9766 if (cpu_count() < 2) { 9767 report_skip(__func__); 9768 return; 9769 } 9770 9771 /* VMCLEAR test-vmcs so it could be loaded by other CPU */ 9772 vmcs_save(&test_vmcs); 9773 vmcs_clear(test_vmcs); 9774 9775 vmx_set_test_stage(0); 9776 on_cpu_async(1, init_signal_test_thread, test_vmcs); 9777 9778 /* Wait for other CPU to enter VMX operation */ 9779 while (vmx_get_test_stage() != 1) 9780 ; 9781 9782 /* Send INIT signal to other CPU */ 9783 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_INIT | APIC_INT_ASSERT, 9784 id_map[1]); 9785 /* Signal other CPU we have sent INIT signal */ 9786 vmx_set_test_stage(2); 9787 9788 /* 9789 * Wait reasonable amount of time for INIT signal to 9790 * be received on other CPU and verify that other CPU 9791 * have proceed as usual to next test stage as INIT 9792 * signal should be blocked while other CPU in 9793 * VMX operation 9794 */ 9795 delay(INIT_SIGNAL_TEST_DELAY); 9796 report(vmx_get_test_stage() == 3, 9797 "INIT signal blocked when CPU in VMX operation"); 9798 /* No point to continue if we failed at this point */ 9799 if (vmx_get_test_stage() != 3) 9800 return; 9801 9802 /* Signal other CPU to enter VMX non-root mode */ 9803 init_signal_test_exit_reason = -1ull; 9804 vmx_set_test_stage(4); 9805 /* 9806 * Wait reasonable amont of time for other CPU 9807 * to exit to VMX root mode 9808 */ 9809 delay(INIT_SIGNAL_TEST_DELAY); 9810 if (vmx_get_test_stage() != 5) { 9811 report_fail("Pending INIT signal didn't result in VMX exit"); 9812 return; 9813 } 9814 report(init_signal_test_exit_reason == VMX_INIT, 9815 "INIT signal during VMX non-root mode result in exit-reason %s (%lu)", 9816 exit_reason_description(init_signal_test_exit_reason), 9817 init_signal_test_exit_reason); 9818 9819 /* Run guest to completion */ 9820 make_vmcs_current(test_vmcs); 9821 enter_guest(); 9822 9823 /* Signal other CPU to exit VMX operation */ 9824 init_signal_test_thread_continued = false; 9825 vmx_set_test_stage(6); 9826 9827 /* Wait reasonable amount of time for other CPU to exit VMX operation */ 9828 delay(INIT_SIGNAL_TEST_DELAY); 9829 report(vmx_get_test_stage() == 7, 9830 "INIT signal consumed on VMX_INIT exit"); 9831 /* No point to continue if we failed at this point */ 9832 if (vmx_get_test_stage() != 7) 9833 return; 9834 9835 /* Signal other CPU to enter VMX operation */ 9836 vmx_set_test_stage(8); 9837 /* Wait for other CPU to enter VMX operation */ 9838 while (vmx_get_test_stage() != 9) 9839 ; 9840 9841 /* Send INIT signal to other CPU */ 9842 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_INIT | APIC_INT_ASSERT, 9843 id_map[1]); 9844 /* Signal other CPU we have sent INIT signal */ 9845 vmx_set_test_stage(10); 9846 9847 /* 9848 * Wait reasonable amount of time for other CPU 9849 * to exit VMX operation and process INIT signal 9850 */ 9851 delay(INIT_SIGNAL_TEST_DELAY); 9852 report(!init_signal_test_thread_continued, 9853 "INIT signal processed after exit VMX operation"); 9854 9855 /* 9856 * TODO: Send SIPI to other CPU to sipi_entry (See x86/cstart64.S) 9857 * to re-init it to kvm-unit-tests standard environment. 9858 * Somehow (?) verify that SIPI was indeed received. 9859 */ 9860 } 9861 9862 #define SIPI_SIGNAL_TEST_DELAY 100000000ULL 9863 9864 static void vmx_sipi_test_guest(void) 9865 { 9866 if (apic_id() == 0) { 9867 /* wait AP enter guest with activity=WAIT_SIPI */ 9868 while (vmx_get_test_stage() != 1) 9869 ; 9870 delay(SIPI_SIGNAL_TEST_DELAY); 9871 9872 /* First SIPI signal */ 9873 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_STARTUP | APIC_INT_ASSERT, id_map[1]); 9874 report_pass("BSP(L2): Send first SIPI to cpu[%d]", id_map[1]); 9875 9876 /* wait AP enter guest */ 9877 while (vmx_get_test_stage() != 2) 9878 ; 9879 delay(SIPI_SIGNAL_TEST_DELAY); 9880 9881 /* Second SIPI signal should be ignored since AP is not in WAIT_SIPI state */ 9882 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_STARTUP | APIC_INT_ASSERT, id_map[1]); 9883 report_pass("BSP(L2): Send second SIPI to cpu[%d]", id_map[1]); 9884 9885 /* Delay a while to check whether second SIPI would cause VMExit */ 9886 delay(SIPI_SIGNAL_TEST_DELAY); 9887 9888 /* Test is done, notify AP to exit test */ 9889 vmx_set_test_stage(3); 9890 9891 /* wait AP exit non-root mode */ 9892 while (vmx_get_test_stage() != 5) 9893 ; 9894 } else { 9895 /* wait BSP notify test is done */ 9896 while (vmx_get_test_stage() != 3) 9897 ; 9898 9899 /* AP exit guest */ 9900 vmx_set_test_stage(4); 9901 } 9902 } 9903 9904 static void sipi_test_ap_thread(void *data) 9905 { 9906 struct vmcs *ap_vmcs; 9907 u64 *ap_vmxon_region; 9908 void *ap_stack, *ap_syscall_stack; 9909 u64 cpu_ctrl_0 = CPU_SECONDARY; 9910 u64 cpu_ctrl_1 = 0; 9911 9912 /* Enter VMX operation (i.e. exec VMXON) */ 9913 ap_vmxon_region = alloc_page(); 9914 enable_vmx(); 9915 init_vmx(ap_vmxon_region); 9916 _vmx_on(ap_vmxon_region); 9917 init_vmcs(&ap_vmcs); 9918 make_vmcs_current(ap_vmcs); 9919 9920 /* Set stack for AP */ 9921 ap_stack = alloc_page(); 9922 ap_syscall_stack = alloc_page(); 9923 vmcs_write(GUEST_RSP, (u64)(ap_stack + PAGE_SIZE - 1)); 9924 vmcs_write(GUEST_SYSENTER_ESP, (u64)(ap_syscall_stack + PAGE_SIZE - 1)); 9925 9926 /* passthrough lapic to L2 */ 9927 disable_intercept_for_x2apic_msrs(); 9928 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 9929 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 9930 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 9931 9932 /* Set guest activity state to wait-for-SIPI state */ 9933 vmcs_write(GUEST_ACTV_STATE, ACTV_WAIT_SIPI); 9934 9935 vmx_set_test_stage(1); 9936 9937 /* AP enter guest */ 9938 enter_guest(); 9939 9940 if (vmcs_read(EXI_REASON) == VMX_SIPI) { 9941 report_pass("AP: Handle SIPI VMExit"); 9942 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 9943 vmx_set_test_stage(2); 9944 } else { 9945 report_fail("AP: Unexpected VMExit, reason=%ld", vmcs_read(EXI_REASON)); 9946 vmx_off(); 9947 return; 9948 } 9949 9950 /* AP enter guest */ 9951 enter_guest(); 9952 9953 report(vmcs_read(EXI_REASON) != VMX_SIPI, 9954 "AP: should no SIPI VMExit since activity is not in WAIT_SIPI state"); 9955 9956 /* notify BSP that AP is already exit from non-root mode */ 9957 vmx_set_test_stage(5); 9958 9959 /* Leave VMX operation */ 9960 vmx_off(); 9961 } 9962 9963 static void vmx_sipi_signal_test(void) 9964 { 9965 if (!(rdmsr(MSR_IA32_VMX_MISC) & MSR_IA32_VMX_MISC_ACTIVITY_WAIT_SIPI)) { 9966 printf("\tACTIVITY_WAIT_SIPI state is not supported.\n"); 9967 return; 9968 } 9969 9970 if (cpu_count() < 2) { 9971 report_skip(__func__); 9972 return; 9973 } 9974 9975 u64 cpu_ctrl_0 = CPU_SECONDARY; 9976 u64 cpu_ctrl_1 = 0; 9977 9978 /* passthrough lapic to L2 */ 9979 disable_intercept_for_x2apic_msrs(); 9980 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 9981 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 9982 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 9983 9984 test_set_guest(vmx_sipi_test_guest); 9985 9986 /* update CR3 on AP */ 9987 on_cpu(1, update_cr3, (void *)read_cr3()); 9988 9989 /* start AP */ 9990 on_cpu_async(1, sipi_test_ap_thread, NULL); 9991 9992 vmx_set_test_stage(0); 9993 9994 /* BSP enter guest */ 9995 enter_guest(); 9996 } 9997 9998 9999 enum vmcs_access { 10000 ACCESS_VMREAD, 10001 ACCESS_VMWRITE, 10002 ACCESS_NONE, 10003 }; 10004 10005 struct vmcs_shadow_test_common { 10006 enum vmcs_access op; 10007 enum Reason reason; 10008 u64 field; 10009 u64 value; 10010 u64 flags; 10011 u64 time; 10012 } l1_l2_common; 10013 10014 static inline u64 vmread_flags(u64 field, u64 *val) 10015 { 10016 u64 flags; 10017 10018 asm volatile ("vmread %2, %1; pushf; pop %0" 10019 : "=r" (flags), "=rm" (*val) : "r" (field) : "cc"); 10020 return flags & X86_EFLAGS_ALU; 10021 } 10022 10023 static inline u64 vmwrite_flags(u64 field, u64 val) 10024 { 10025 u64 flags; 10026 10027 asm volatile ("vmwrite %1, %2; pushf; pop %0" 10028 : "=r"(flags) : "rm" (val), "r" (field) : "cc"); 10029 return flags & X86_EFLAGS_ALU; 10030 } 10031 10032 static void vmx_vmcs_shadow_test_guest(void) 10033 { 10034 struct vmcs_shadow_test_common *c = &l1_l2_common; 10035 u64 start; 10036 10037 while (c->op != ACCESS_NONE) { 10038 start = rdtsc(); 10039 switch (c->op) { 10040 default: 10041 c->flags = -1ull; 10042 break; 10043 case ACCESS_VMREAD: 10044 c->flags = vmread_flags(c->field, &c->value); 10045 break; 10046 case ACCESS_VMWRITE: 10047 c->flags = vmwrite_flags(c->field, 0); 10048 break; 10049 } 10050 c->time = rdtsc() - start; 10051 vmcall(); 10052 } 10053 } 10054 10055 static u64 vmread_from_shadow(u64 field) 10056 { 10057 struct vmcs *primary; 10058 struct vmcs *shadow; 10059 u64 value; 10060 10061 TEST_ASSERT(!vmcs_save(&primary)); 10062 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 10063 TEST_ASSERT(!make_vmcs_current(shadow)); 10064 value = vmcs_read(field); 10065 TEST_ASSERT(!make_vmcs_current(primary)); 10066 return value; 10067 } 10068 10069 static u64 vmwrite_to_shadow(u64 field, u64 value) 10070 { 10071 struct vmcs *primary; 10072 struct vmcs *shadow; 10073 10074 TEST_ASSERT(!vmcs_save(&primary)); 10075 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 10076 TEST_ASSERT(!make_vmcs_current(shadow)); 10077 vmcs_write(field, value); 10078 value = vmcs_read(field); 10079 TEST_ASSERT(!make_vmcs_current(primary)); 10080 return value; 10081 } 10082 10083 static void vmcs_shadow_test_access(u8 *bitmap[2], enum vmcs_access access) 10084 { 10085 struct vmcs_shadow_test_common *c = &l1_l2_common; 10086 10087 c->op = access; 10088 vmcs_write(VMX_INST_ERROR, 0); 10089 enter_guest(); 10090 c->reason = vmcs_read(EXI_REASON) & 0xffff; 10091 if (c->reason != VMX_VMCALL) { 10092 skip_exit_insn(); 10093 enter_guest(); 10094 } 10095 skip_exit_vmcall(); 10096 } 10097 10098 static void vmcs_shadow_test_field(u8 *bitmap[2], u64 field) 10099 { 10100 struct vmcs_shadow_test_common *c = &l1_l2_common; 10101 struct vmcs *shadow; 10102 u64 value; 10103 uintptr_t flags[2]; 10104 bool good_shadow; 10105 u32 vmx_inst_error; 10106 10107 report_prefix_pushf("field %lx", field); 10108 c->field = field; 10109 10110 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 10111 if (shadow != (struct vmcs *)-1ull) { 10112 flags[ACCESS_VMREAD] = vmread_flags(field, &value); 10113 flags[ACCESS_VMWRITE] = vmwrite_flags(field, value); 10114 good_shadow = !flags[ACCESS_VMREAD] && !flags[ACCESS_VMWRITE]; 10115 } else { 10116 /* 10117 * When VMCS link pointer is -1ull, VMWRITE/VMREAD on 10118 * shadowed-fields should fail with setting RFLAGS.CF. 10119 */ 10120 flags[ACCESS_VMREAD] = X86_EFLAGS_CF; 10121 flags[ACCESS_VMWRITE] = X86_EFLAGS_CF; 10122 good_shadow = false; 10123 } 10124 10125 /* Intercept both VMREAD and VMWRITE. */ 10126 report_prefix_push("no VMREAD/VMWRITE permission"); 10127 /* VMWRITE/VMREAD done on reserved-bit should always intercept */ 10128 if (!(field >> VMCS_FIELD_RESERVED_SHIFT)) { 10129 set_bit(field, bitmap[ACCESS_VMREAD]); 10130 set_bit(field, bitmap[ACCESS_VMWRITE]); 10131 } 10132 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10133 report(c->reason == VMX_VMWRITE, "not shadowed for VMWRITE"); 10134 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10135 report(c->reason == VMX_VMREAD, "not shadowed for VMREAD"); 10136 report_prefix_pop(); 10137 10138 if (field >> VMCS_FIELD_RESERVED_SHIFT) 10139 goto out; 10140 10141 /* Permit shadowed VMREAD. */ 10142 report_prefix_push("VMREAD permission only"); 10143 clear_bit(field, bitmap[ACCESS_VMREAD]); 10144 set_bit(field, bitmap[ACCESS_VMWRITE]); 10145 if (good_shadow) 10146 value = vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 10147 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10148 report(c->reason == VMX_VMWRITE, "not shadowed for VMWRITE"); 10149 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10150 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10151 report(c->reason == VMX_VMCALL, "shadowed for VMREAD (in %ld cycles)", 10152 c->time); 10153 report(c->flags == flags[ACCESS_VMREAD], 10154 "ALU flags after VMREAD (%lx) are as expected (%lx)", 10155 c->flags, flags[ACCESS_VMREAD]); 10156 if (good_shadow) 10157 report(c->value == value, 10158 "value read from shadow (%lx) is as expected (%lx)", 10159 c->value, value); 10160 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 10161 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10162 "VMX_INST_ERROR (%d) is as expected (%d)", 10163 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10164 report_prefix_pop(); 10165 10166 /* Permit shadowed VMWRITE. */ 10167 report_prefix_push("VMWRITE permission only"); 10168 set_bit(field, bitmap[ACCESS_VMREAD]); 10169 clear_bit(field, bitmap[ACCESS_VMWRITE]); 10170 if (good_shadow) 10171 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 10172 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10173 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10174 report(c->reason == VMX_VMCALL, 10175 "shadowed for VMWRITE (in %ld cycles)", 10176 c->time); 10177 report(c->flags == flags[ACCESS_VMREAD], 10178 "ALU flags after VMWRITE (%lx) are as expected (%lx)", 10179 c->flags, flags[ACCESS_VMREAD]); 10180 if (good_shadow) { 10181 value = vmread_from_shadow(field); 10182 report(value == 0, 10183 "shadow VMCS value (%lx) is as expected (%lx)", value, 10184 0ul); 10185 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 10186 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10187 "VMX_INST_ERROR (%d) is as expected (%d)", 10188 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10189 } 10190 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10191 report(c->reason == VMX_VMREAD, "not shadowed for VMREAD"); 10192 report_prefix_pop(); 10193 10194 /* Permit shadowed VMREAD and VMWRITE. */ 10195 report_prefix_push("VMREAD and VMWRITE permission"); 10196 clear_bit(field, bitmap[ACCESS_VMREAD]); 10197 clear_bit(field, bitmap[ACCESS_VMWRITE]); 10198 if (good_shadow) 10199 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 10200 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10201 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10202 report(c->reason == VMX_VMCALL, 10203 "shadowed for VMWRITE (in %ld cycles)", 10204 c->time); 10205 report(c->flags == flags[ACCESS_VMREAD], 10206 "ALU flags after VMWRITE (%lx) are as expected (%lx)", 10207 c->flags, flags[ACCESS_VMREAD]); 10208 if (good_shadow) { 10209 value = vmread_from_shadow(field); 10210 report(value == 0, 10211 "shadow VMCS value (%lx) is as expected (%lx)", value, 10212 0ul); 10213 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 10214 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10215 "VMX_INST_ERROR (%d) is as expected (%d)", 10216 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10217 } 10218 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10219 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10220 report(c->reason == VMX_VMCALL, "shadowed for VMREAD (in %ld cycles)", 10221 c->time); 10222 report(c->flags == flags[ACCESS_VMREAD], 10223 "ALU flags after VMREAD (%lx) are as expected (%lx)", 10224 c->flags, flags[ACCESS_VMREAD]); 10225 if (good_shadow) 10226 report(c->value == 0, 10227 "value read from shadow (%lx) is as expected (%lx)", 10228 c->value, 0ul); 10229 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 10230 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10231 "VMX_INST_ERROR (%d) is as expected (%d)", 10232 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10233 report_prefix_pop(); 10234 10235 out: 10236 report_prefix_pop(); 10237 } 10238 10239 static void vmx_vmcs_shadow_test_body(u8 *bitmap[2]) 10240 { 10241 unsigned base; 10242 unsigned index; 10243 unsigned bit; 10244 unsigned highest_index = rdmsr(MSR_IA32_VMX_VMCS_ENUM); 10245 10246 /* Run test on all possible valid VMCS fields */ 10247 for (base = 0; 10248 base < (1 << VMCS_FIELD_RESERVED_SHIFT); 10249 base += (1 << VMCS_FIELD_TYPE_SHIFT)) 10250 for (index = 0; index <= highest_index; index++) 10251 vmcs_shadow_test_field(bitmap, base + index); 10252 10253 /* 10254 * Run tests on some invalid VMCS fields 10255 * (Have reserved bit set). 10256 */ 10257 for (bit = VMCS_FIELD_RESERVED_SHIFT; bit < VMCS_FIELD_BIT_SIZE; bit++) 10258 vmcs_shadow_test_field(bitmap, (1ull << bit)); 10259 } 10260 10261 static void vmx_vmcs_shadow_test(void) 10262 { 10263 u8 *bitmap[2]; 10264 struct vmcs *shadow; 10265 10266 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 10267 printf("\t'Activate secondary controls' not supported.\n"); 10268 return; 10269 } 10270 10271 if (!(ctrl_cpu_rev[1].clr & CPU_SHADOW_VMCS)) { 10272 printf("\t'VMCS shadowing' not supported.\n"); 10273 return; 10274 } 10275 10276 if (!(rdmsr(MSR_IA32_VMX_MISC) & 10277 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS)) { 10278 printf("\tVMWRITE can't modify VM-exit information fields.\n"); 10279 return; 10280 } 10281 10282 test_set_guest(vmx_vmcs_shadow_test_guest); 10283 10284 bitmap[ACCESS_VMREAD] = alloc_page(); 10285 bitmap[ACCESS_VMWRITE] = alloc_page(); 10286 10287 vmcs_write(VMREAD_BITMAP, virt_to_phys(bitmap[ACCESS_VMREAD])); 10288 vmcs_write(VMWRITE_BITMAP, virt_to_phys(bitmap[ACCESS_VMWRITE])); 10289 10290 shadow = alloc_page(); 10291 shadow->hdr.revision_id = basic.revision; 10292 shadow->hdr.shadow_vmcs = 1; 10293 TEST_ASSERT(!vmcs_clear(shadow)); 10294 10295 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_RDTSC); 10296 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY); 10297 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_SHADOW_VMCS); 10298 10299 vmcs_write(VMCS_LINK_PTR, virt_to_phys(shadow)); 10300 report_prefix_push("valid link pointer"); 10301 vmx_vmcs_shadow_test_body(bitmap); 10302 report_prefix_pop(); 10303 10304 vmcs_write(VMCS_LINK_PTR, -1ull); 10305 report_prefix_push("invalid link pointer"); 10306 vmx_vmcs_shadow_test_body(bitmap); 10307 report_prefix_pop(); 10308 10309 l1_l2_common.op = ACCESS_NONE; 10310 enter_guest(); 10311 } 10312 10313 /* 10314 * This test monitors the difference between a guest RDTSC instruction 10315 * and the IA32_TIME_STAMP_COUNTER MSR value stored in the VMCS12 10316 * VM-exit MSR-store list when taking a VM-exit on the instruction 10317 * following RDTSC. 10318 */ 10319 #define RDTSC_DIFF_ITERS 100000 10320 #define RDTSC_DIFF_FAILS 100 10321 #define HOST_CAPTURED_GUEST_TSC_DIFF_THRESHOLD 750 10322 10323 /* 10324 * Set 'use TSC offsetting' and set the guest offset to the 10325 * inverse of the host's current TSC value, so that the guest starts running 10326 * with an effective TSC value of 0. 10327 */ 10328 static void reset_guest_tsc_to_zero(void) 10329 { 10330 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_USE_TSC_OFFSET); 10331 vmcs_write(TSC_OFFSET, -rdtsc()); 10332 } 10333 10334 static void rdtsc_vmexit_diff_test_guest(void) 10335 { 10336 int i; 10337 10338 for (i = 0; i < RDTSC_DIFF_ITERS; i++) 10339 /* Ensure rdtsc is the last instruction before the vmcall. */ 10340 asm volatile("rdtsc; vmcall" : : : "eax", "edx"); 10341 } 10342 10343 /* 10344 * This function only considers the "use TSC offsetting" VM-execution 10345 * control. It does not handle "use TSC scaling" (because the latter 10346 * isn't available to the host today.) 10347 */ 10348 static unsigned long long host_time_to_guest_time(unsigned long long t) 10349 { 10350 TEST_ASSERT(!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 10351 !(vmcs_read(CPU_EXEC_CTRL1) & CPU_USE_TSC_SCALING)); 10352 10353 if (vmcs_read(CPU_EXEC_CTRL0) & CPU_USE_TSC_OFFSET) 10354 t += vmcs_read(TSC_OFFSET); 10355 10356 return t; 10357 } 10358 10359 static unsigned long long rdtsc_vmexit_diff_test_iteration(void) 10360 { 10361 unsigned long long guest_tsc, host_to_guest_tsc; 10362 10363 enter_guest(); 10364 skip_exit_vmcall(); 10365 guest_tsc = (u32) regs.rax + (regs.rdx << 32); 10366 host_to_guest_tsc = host_time_to_guest_time(exit_msr_store[0].value); 10367 10368 return host_to_guest_tsc - guest_tsc; 10369 } 10370 10371 static void rdtsc_vmexit_diff_test(void) 10372 { 10373 unsigned long long delta; 10374 int fail = 0; 10375 int i; 10376 10377 if (!(ctrl_cpu_rev[0].clr & CPU_USE_TSC_OFFSET)) 10378 test_skip("CPU doesn't support the 'use TSC offsetting' processor-based VM-execution control.\n"); 10379 10380 test_set_guest(rdtsc_vmexit_diff_test_guest); 10381 10382 reset_guest_tsc_to_zero(); 10383 10384 /* 10385 * Set up the VMCS12 VM-exit MSR-store list to store just one 10386 * MSR: IA32_TIME_STAMP_COUNTER. Note that the value stored is 10387 * in the host time domain (i.e., it is not adjusted according 10388 * to the TSC multiplier and TSC offset fields in the VMCS12, 10389 * as a guest RDTSC would be.) 10390 */ 10391 exit_msr_store = alloc_page(); 10392 exit_msr_store[0].index = MSR_IA32_TSC; 10393 vmcs_write(EXI_MSR_ST_CNT, 1); 10394 vmcs_write(EXIT_MSR_ST_ADDR, virt_to_phys(exit_msr_store)); 10395 10396 for (i = 0; i < RDTSC_DIFF_ITERS && fail < RDTSC_DIFF_FAILS; i++) { 10397 delta = rdtsc_vmexit_diff_test_iteration(); 10398 if (delta >= HOST_CAPTURED_GUEST_TSC_DIFF_THRESHOLD) 10399 fail++; 10400 } 10401 10402 enter_guest(); 10403 10404 report(fail < RDTSC_DIFF_FAILS, 10405 "RDTSC to VM-exit delta too high in %d of %d iterations, last = %llu", 10406 fail, i, delta); 10407 } 10408 10409 static int invalid_msr_init(struct vmcs *vmcs) 10410 { 10411 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 10412 printf("\tPreemption timer is not supported\n"); 10413 return VMX_TEST_EXIT; 10414 } 10415 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 10416 preempt_val = 10000000; 10417 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 10418 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 10419 10420 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 10421 printf("\tSave preemption value is not supported\n"); 10422 10423 vmcs_write(ENT_MSR_LD_CNT, 1); 10424 vmcs_write(ENTER_MSR_LD_ADDR, (u64)0x13370000); 10425 10426 return VMX_TEST_START; 10427 } 10428 10429 10430 static void invalid_msr_main(void) 10431 { 10432 report_fail("Invalid MSR load"); 10433 } 10434 10435 static int invalid_msr_exit_handler(union exit_reason exit_reason) 10436 { 10437 report_fail("Invalid MSR load"); 10438 print_vmexit_info(exit_reason); 10439 return VMX_TEST_EXIT; 10440 } 10441 10442 static int invalid_msr_entry_failure(struct vmentry_result *result) 10443 { 10444 report(result->exit_reason.failed_vmentry && 10445 result->exit_reason.basic == VMX_FAIL_MSR, "Invalid MSR load"); 10446 return VMX_TEST_VMEXIT; 10447 } 10448 10449 /* 10450 * The max number of MSRs in an atomic switch MSR list is: 10451 * (111B + 1) * 512 = 4096 10452 * 10453 * Each list entry consumes: 10454 * 4-byte MSR index + 4 bytes reserved + 8-byte data = 16 bytes 10455 * 10456 * Allocate 128 kB to cover max_msr_list_size (i.e., 64 kB) and then some. 10457 */ 10458 static const u32 msr_list_page_order = 5; 10459 10460 static void atomic_switch_msr_limit_test_guest(void) 10461 { 10462 vmcall(); 10463 } 10464 10465 static void populate_msr_list(struct vmx_msr_entry *msr_list, 10466 size_t byte_capacity, int count) 10467 { 10468 int i; 10469 10470 for (i = 0; i < count; i++) { 10471 msr_list[i].index = MSR_IA32_TSC; 10472 msr_list[i].reserved = 0; 10473 msr_list[i].value = 0x1234567890abcdef; 10474 } 10475 10476 memset(msr_list + count, 0xff, 10477 byte_capacity - count * sizeof(*msr_list)); 10478 } 10479 10480 static int max_msr_list_size(void) 10481 { 10482 u32 vmx_misc = rdmsr(MSR_IA32_VMX_MISC); 10483 u32 factor = ((vmx_misc & GENMASK(27, 25)) >> 25) + 1; 10484 10485 return factor * 512; 10486 } 10487 10488 static void atomic_switch_msrs_test(int count) 10489 { 10490 struct vmx_msr_entry *vm_enter_load; 10491 struct vmx_msr_entry *vm_exit_load; 10492 struct vmx_msr_entry *vm_exit_store; 10493 int max_allowed = max_msr_list_size(); 10494 int byte_capacity = 1ul << (msr_list_page_order + PAGE_SHIFT); 10495 /* Exceeding the max MSR list size at exit trigers KVM to abort. */ 10496 int exit_count = count > max_allowed ? max_allowed : count; 10497 int cleanup_count = count > max_allowed ? 2 : 1; 10498 int i; 10499 10500 /* 10501 * Check for the IA32_TSC MSR, 10502 * available with the "TSC flag" and used to populate the MSR lists. 10503 */ 10504 if (!(cpuid(1).d & (1 << 4))) { 10505 report_skip(__func__); 10506 return; 10507 } 10508 10509 /* Set L2 guest. */ 10510 test_set_guest(atomic_switch_msr_limit_test_guest); 10511 10512 /* Setup atomic MSR switch lists. */ 10513 vm_enter_load = alloc_pages(msr_list_page_order); 10514 vm_exit_load = alloc_pages(msr_list_page_order); 10515 vm_exit_store = alloc_pages(msr_list_page_order); 10516 10517 vmcs_write(ENTER_MSR_LD_ADDR, (u64)vm_enter_load); 10518 vmcs_write(EXIT_MSR_LD_ADDR, (u64)vm_exit_load); 10519 vmcs_write(EXIT_MSR_ST_ADDR, (u64)vm_exit_store); 10520 10521 /* 10522 * VM-Enter should succeed up to the max number of MSRs per list, and 10523 * should not consume junk beyond the last entry. 10524 */ 10525 populate_msr_list(vm_enter_load, byte_capacity, count); 10526 populate_msr_list(vm_exit_load, byte_capacity, exit_count); 10527 populate_msr_list(vm_exit_store, byte_capacity, exit_count); 10528 10529 vmcs_write(ENT_MSR_LD_CNT, count); 10530 vmcs_write(EXI_MSR_LD_CNT, exit_count); 10531 vmcs_write(EXI_MSR_ST_CNT, exit_count); 10532 10533 if (count <= max_allowed) { 10534 enter_guest(); 10535 assert_exit_reason(VMX_VMCALL); 10536 skip_exit_vmcall(); 10537 } else { 10538 u32 exit_qual; 10539 10540 test_guest_state("Invalid MSR Load Count", true, count, 10541 "ENT_MSR_LD_CNT"); 10542 10543 exit_qual = vmcs_read(EXI_QUALIFICATION); 10544 report(exit_qual == max_allowed + 1, "exit_qual, %u, is %u.", 10545 exit_qual, max_allowed + 1); 10546 } 10547 10548 /* Cleanup. */ 10549 vmcs_write(ENT_MSR_LD_CNT, 0); 10550 vmcs_write(EXI_MSR_LD_CNT, 0); 10551 vmcs_write(EXI_MSR_ST_CNT, 0); 10552 for (i = 0; i < cleanup_count; i++) { 10553 enter_guest(); 10554 skip_exit_vmcall(); 10555 } 10556 free_pages_by_order(vm_enter_load, msr_list_page_order); 10557 free_pages_by_order(vm_exit_load, msr_list_page_order); 10558 free_pages_by_order(vm_exit_store, msr_list_page_order); 10559 } 10560 10561 static void atomic_switch_max_msrs_test(void) 10562 { 10563 atomic_switch_msrs_test(max_msr_list_size()); 10564 } 10565 10566 static void atomic_switch_overflow_msrs_test(void) 10567 { 10568 if (test_device_enabled()) 10569 atomic_switch_msrs_test(max_msr_list_size() + 1); 10570 else 10571 test_skip("Test is only supported on KVM"); 10572 } 10573 10574 static void vmx_pf_exception_test_guest(void) 10575 { 10576 ac_test_run(PT_LEVEL_PML4); 10577 } 10578 10579 typedef void (*invalidate_tlb_t)(void *data); 10580 10581 static void __vmx_pf_exception_test(invalidate_tlb_t inv_fn, void *data) 10582 { 10583 u64 efer; 10584 struct cpuid cpuid; 10585 10586 test_set_guest(vmx_pf_exception_test_guest); 10587 10588 /* Intercept INVLPG when to perform TLB invalidation from L1 (this). */ 10589 if (inv_fn) 10590 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INVLPG); 10591 else 10592 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INVLPG); 10593 10594 enter_guest(); 10595 10596 while (vmcs_read(EXI_REASON) != VMX_VMCALL) { 10597 switch (vmcs_read(EXI_REASON)) { 10598 case VMX_RDMSR: 10599 assert(regs.rcx == MSR_EFER); 10600 efer = vmcs_read(GUEST_EFER); 10601 regs.rdx = efer >> 32; 10602 regs.rax = efer & 0xffffffff; 10603 break; 10604 case VMX_WRMSR: 10605 assert(regs.rcx == MSR_EFER); 10606 efer = regs.rdx << 32 | (regs.rax & 0xffffffff); 10607 vmcs_write(GUEST_EFER, efer); 10608 break; 10609 case VMX_CPUID: 10610 cpuid = (struct cpuid) {0, 0, 0, 0}; 10611 cpuid = raw_cpuid(regs.rax, regs.rcx); 10612 regs.rax = cpuid.a; 10613 regs.rbx = cpuid.b; 10614 regs.rcx = cpuid.c; 10615 regs.rdx = cpuid.d; 10616 break; 10617 case VMX_INVLPG: 10618 inv_fn(data); 10619 break; 10620 default: 10621 assert_msg(false, 10622 "Unexpected exit to L1, exit_reason: %s (0x%lx)", 10623 exit_reason_description(vmcs_read(EXI_REASON)), 10624 vmcs_read(EXI_REASON)); 10625 } 10626 skip_exit_insn(); 10627 enter_guest(); 10628 } 10629 10630 assert_exit_reason(VMX_VMCALL); 10631 } 10632 10633 static void vmx_pf_exception_test(void) 10634 { 10635 __vmx_pf_exception_test(NULL, NULL); 10636 } 10637 10638 static void invalidate_tlb_no_vpid(void *data) 10639 { 10640 /* If VPID is disabled, the TLB is flushed on VM-Enter and VM-Exit. */ 10641 } 10642 10643 static void vmx_pf_no_vpid_test(void) 10644 { 10645 if (is_vpid_supported()) 10646 vmcs_clear_bits(CPU_EXEC_CTRL1, CPU_VPID); 10647 10648 __vmx_pf_exception_test(invalidate_tlb_no_vpid, NULL); 10649 } 10650 10651 static void invalidate_tlb_invvpid_addr(void *data) 10652 { 10653 invvpid(INVVPID_ALL, *(u16 *)data, vmcs_read(EXI_QUALIFICATION)); 10654 } 10655 10656 static void invalidate_tlb_new_vpid(void *data) 10657 { 10658 u16 *vpid = data; 10659 10660 /* 10661 * Bump VPID to effectively flush L2's TLB from L0's perspective. 10662 * Invalidate all VPIDs when the VPID wraps to zero as hardware/KVM is 10663 * architecturally allowed to keep TLB entries indefinitely. 10664 */ 10665 ++(*vpid); 10666 if (*vpid == 0) { 10667 ++(*vpid); 10668 invvpid(INVVPID_ALL, 0, 0); 10669 } 10670 vmcs_write(VPID, *vpid); 10671 } 10672 10673 static void __vmx_pf_vpid_test(invalidate_tlb_t inv_fn, u16 vpid) 10674 { 10675 if (!is_vpid_supported()) 10676 test_skip("VPID unsupported"); 10677 10678 if (!is_invvpid_supported()) 10679 test_skip("INVVPID unsupported"); 10680 10681 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY); 10682 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_VPID); 10683 vmcs_write(VPID, vpid); 10684 10685 __vmx_pf_exception_test(inv_fn, &vpid); 10686 } 10687 10688 static void vmx_pf_invvpid_test(void) 10689 { 10690 if (!is_invvpid_type_supported(INVVPID_ADDR)) 10691 test_skip("INVVPID ADDR unsupported"); 10692 10693 __vmx_pf_vpid_test(invalidate_tlb_invvpid_addr, 0xaaaa); 10694 } 10695 10696 static void vmx_pf_vpid_test(void) 10697 { 10698 /* Need INVVPID(ALL) to flush VPIDs upon wrap/reuse. */ 10699 if (!is_invvpid_type_supported(INVVPID_ALL)) 10700 test_skip("INVVPID ALL unsupported"); 10701 10702 __vmx_pf_vpid_test(invalidate_tlb_new_vpid, 1); 10703 } 10704 10705 static void vmx_l2_gp_test(void) 10706 { 10707 *(volatile u64 *)NONCANONICAL = 0; 10708 } 10709 10710 static void vmx_l2_ud_test(void) 10711 { 10712 asm volatile ("ud2"); 10713 } 10714 10715 static void vmx_l2_de_test(void) 10716 { 10717 asm volatile ( 10718 "xor %%eax, %%eax\n\t" 10719 "xor %%ebx, %%ebx\n\t" 10720 "xor %%edx, %%edx\n\t" 10721 "idiv %%ebx\n\t" 10722 ::: "eax", "ebx", "edx"); 10723 } 10724 10725 static void vmx_l2_bp_test(void) 10726 { 10727 asm volatile ("int3"); 10728 } 10729 10730 static void vmx_l2_db_test(void) 10731 { 10732 write_rflags(read_rflags() | X86_EFLAGS_TF); 10733 } 10734 10735 static uint64_t usermode_callback(void) 10736 { 10737 /* 10738 * Trigger an #AC by writing 8 bytes to a 4-byte aligned address. 10739 * Disclaimer: It is assumed that the stack pointer is aligned 10740 * on a 16-byte boundary as x86_64 stacks should be. 10741 */ 10742 asm volatile("movq $0, -0x4(%rsp)"); 10743 10744 return 0; 10745 } 10746 10747 static void vmx_l2_ac_test(void) 10748 { 10749 bool hit_ac = false; 10750 10751 write_cr0(read_cr0() | X86_CR0_AM); 10752 write_rflags(read_rflags() | X86_EFLAGS_AC); 10753 10754 run_in_user(usermode_callback, AC_VECTOR, 0, 0, 0, 0, &hit_ac); 10755 report(hit_ac, "Usermode #AC handled in L2"); 10756 vmcall(); 10757 } 10758 10759 struct vmx_exception_test { 10760 u8 vector; 10761 void (*guest_code)(void); 10762 }; 10763 10764 struct vmx_exception_test vmx_exception_tests[] = { 10765 { GP_VECTOR, vmx_l2_gp_test }, 10766 { UD_VECTOR, vmx_l2_ud_test }, 10767 { DE_VECTOR, vmx_l2_de_test }, 10768 { DB_VECTOR, vmx_l2_db_test }, 10769 { BP_VECTOR, vmx_l2_bp_test }, 10770 { AC_VECTOR, vmx_l2_ac_test }, 10771 }; 10772 10773 static u8 vmx_exception_test_vector; 10774 10775 static void vmx_exception_handler(struct ex_regs *regs) 10776 { 10777 report(regs->vector == vmx_exception_test_vector, 10778 "Handling %s in L2's exception handler", 10779 exception_mnemonic(vmx_exception_test_vector)); 10780 vmcall(); 10781 } 10782 10783 static void handle_exception_in_l2(u8 vector) 10784 { 10785 handler old_handler = handle_exception(vector, vmx_exception_handler); 10786 10787 vmx_exception_test_vector = vector; 10788 10789 enter_guest(); 10790 report(vmcs_read(EXI_REASON) == VMX_VMCALL, 10791 "%s handled by L2", exception_mnemonic(vector)); 10792 10793 handle_exception(vector, old_handler); 10794 } 10795 10796 static void handle_exception_in_l1(u32 vector) 10797 { 10798 u32 old_eb = vmcs_read(EXC_BITMAP); 10799 10800 vmcs_write(EXC_BITMAP, old_eb | (1u << vector)); 10801 10802 enter_guest(); 10803 10804 report((vmcs_read(EXI_REASON) == VMX_EXC_NMI) && 10805 ((vmcs_read(EXI_INTR_INFO) & 0xff) == vector), 10806 "%s handled by L1", exception_mnemonic(vector)); 10807 10808 vmcs_write(EXC_BITMAP, old_eb); 10809 } 10810 10811 static void vmx_exception_test(void) 10812 { 10813 struct vmx_exception_test *t; 10814 int i; 10815 10816 for (i = 0; i < ARRAY_SIZE(vmx_exception_tests); i++) { 10817 t = &vmx_exception_tests[i]; 10818 10819 /* 10820 * Override the guest code before each run even though it's the 10821 * same code, the VMCS guest state needs to be reinitialized. 10822 */ 10823 test_override_guest(t->guest_code); 10824 handle_exception_in_l2(t->vector); 10825 10826 test_override_guest(t->guest_code); 10827 handle_exception_in_l1(t->vector); 10828 } 10829 10830 test_set_guest_finished(); 10831 } 10832 10833 #define TEST(name) { #name, .v2 = name } 10834 10835 /* name/init/guest_main/exit_handler/syscall_handler/guest_regs */ 10836 struct vmx_test vmx_tests[] = { 10837 { "null", NULL, basic_guest_main, basic_exit_handler, NULL, {0} }, 10838 { "vmenter", NULL, vmenter_main, vmenter_exit_handler, NULL, {0} }, 10839 { "preemption timer", preemption_timer_init, preemption_timer_main, 10840 preemption_timer_exit_handler, NULL, {0} }, 10841 { "control field PAT", test_ctrl_pat_init, test_ctrl_pat_main, 10842 test_ctrl_pat_exit_handler, NULL, {0} }, 10843 { "control field EFER", test_ctrl_efer_init, test_ctrl_efer_main, 10844 test_ctrl_efer_exit_handler, NULL, {0} }, 10845 { "CR shadowing", NULL, cr_shadowing_main, 10846 cr_shadowing_exit_handler, NULL, {0} }, 10847 { "I/O bitmap", iobmp_init, iobmp_main, iobmp_exit_handler, 10848 NULL, {0} }, 10849 { "instruction intercept", insn_intercept_init, insn_intercept_main, 10850 insn_intercept_exit_handler, NULL, {0} }, 10851 { "EPT A/D disabled", ept_init, ept_main, ept_exit_handler, NULL, {0} }, 10852 { "EPT A/D enabled", eptad_init, eptad_main, eptad_exit_handler, NULL, {0} }, 10853 { "PML", pml_init, pml_main, pml_exit_handler, NULL, {0} }, 10854 { "interrupt", interrupt_init, interrupt_main, 10855 interrupt_exit_handler, NULL, {0} }, 10856 { "nmi_hlt", nmi_hlt_init, nmi_hlt_main, 10857 nmi_hlt_exit_handler, NULL, {0} }, 10858 { "debug controls", dbgctls_init, dbgctls_main, dbgctls_exit_handler, 10859 NULL, {0} }, 10860 { "MSR switch", msr_switch_init, msr_switch_main, 10861 msr_switch_exit_handler, NULL, {0}, msr_switch_entry_failure }, 10862 { "vmmcall", vmmcall_init, vmmcall_main, vmmcall_exit_handler, NULL, {0} }, 10863 { "disable RDTSCP", disable_rdtscp_init, disable_rdtscp_main, 10864 disable_rdtscp_exit_handler, NULL, {0} }, 10865 { "int3", int3_init, int3_guest_main, int3_exit_handler, NULL, {0} }, 10866 { "into", into_init, into_guest_main, into_exit_handler, NULL, {0} }, 10867 { "exit_monitor_from_l2_test", NULL, exit_monitor_from_l2_main, 10868 exit_monitor_from_l2_handler, NULL, {0} }, 10869 { "invalid_msr", invalid_msr_init, invalid_msr_main, 10870 invalid_msr_exit_handler, NULL, {0}, invalid_msr_entry_failure}, 10871 /* Basic V2 tests. */ 10872 TEST(v2_null_test), 10873 TEST(v2_multiple_entries_test), 10874 TEST(fixture_test_case1), 10875 TEST(fixture_test_case2), 10876 /* Opcode tests. */ 10877 TEST(invvpid_test), 10878 /* VM-entry tests */ 10879 TEST(vmx_controls_test), 10880 TEST(vmx_host_state_area_test), 10881 TEST(vmx_guest_state_area_test), 10882 TEST(vmentry_movss_shadow_test), 10883 TEST(vmentry_unrestricted_guest_test), 10884 /* APICv tests */ 10885 TEST(vmx_eoi_bitmap_ioapic_scan_test), 10886 TEST(vmx_hlt_with_rvi_test), 10887 TEST(apic_reg_virt_test), 10888 TEST(virt_x2apic_mode_test), 10889 /* APIC pass-through tests */ 10890 TEST(vmx_apic_passthrough_test), 10891 TEST(vmx_apic_passthrough_thread_test), 10892 TEST(vmx_apic_passthrough_tpr_threshold_test), 10893 TEST(vmx_init_signal_test), 10894 TEST(vmx_sipi_signal_test), 10895 /* VMCS Shadowing tests */ 10896 TEST(vmx_vmcs_shadow_test), 10897 /* Regression tests */ 10898 TEST(vmx_ldtr_test), 10899 TEST(vmx_cr_load_test), 10900 TEST(vmx_cr4_osxsave_test), 10901 TEST(vmx_nm_test), 10902 TEST(vmx_db_test), 10903 TEST(vmx_nmi_window_test), 10904 TEST(vmx_intr_window_test), 10905 TEST(vmx_pending_event_test), 10906 TEST(vmx_pending_event_hlt_test), 10907 TEST(vmx_store_tsc_test), 10908 TEST(vmx_preemption_timer_zero_test), 10909 TEST(vmx_preemption_timer_tf_test), 10910 TEST(vmx_preemption_timer_expiry_test), 10911 /* EPT access tests. */ 10912 TEST(ept_access_test_not_present), 10913 TEST(ept_access_test_read_only), 10914 TEST(ept_access_test_write_only), 10915 TEST(ept_access_test_read_write), 10916 TEST(ept_access_test_execute_only), 10917 TEST(ept_access_test_read_execute), 10918 TEST(ept_access_test_write_execute), 10919 TEST(ept_access_test_read_write_execute), 10920 TEST(ept_access_test_reserved_bits), 10921 TEST(ept_access_test_ignored_bits), 10922 TEST(ept_access_test_paddr_not_present_ad_disabled), 10923 TEST(ept_access_test_paddr_not_present_ad_enabled), 10924 TEST(ept_access_test_paddr_read_only_ad_disabled), 10925 TEST(ept_access_test_paddr_read_only_ad_enabled), 10926 TEST(ept_access_test_paddr_read_write), 10927 TEST(ept_access_test_paddr_read_write_execute), 10928 TEST(ept_access_test_paddr_read_execute_ad_disabled), 10929 TEST(ept_access_test_paddr_read_execute_ad_enabled), 10930 TEST(ept_access_test_paddr_not_present_page_fault), 10931 TEST(ept_access_test_force_2m_page), 10932 /* Atomic MSR switch tests. */ 10933 TEST(atomic_switch_max_msrs_test), 10934 TEST(atomic_switch_overflow_msrs_test), 10935 TEST(rdtsc_vmexit_diff_test), 10936 TEST(vmx_mtf_test), 10937 TEST(vmx_mtf_pdpte_test), 10938 TEST(vmx_pf_exception_test), 10939 TEST(vmx_pf_no_vpid_test), 10940 TEST(vmx_pf_invvpid_test), 10941 TEST(vmx_pf_vpid_test), 10942 TEST(vmx_exception_test), 10943 { NULL, NULL, NULL, NULL, NULL, {0} }, 10944 }; 10945