1 /* 2 * All test cases of nested virtualization should be in this file 3 * 4 * Author : Arthur Chunqi Li <yzt356@gmail.com> 5 */ 6 7 #include <asm/debugreg.h> 8 9 #include "vmx.h" 10 #include "msr.h" 11 #include "processor.h" 12 #include "vm.h" 13 #include "pci.h" 14 #include "fwcfg.h" 15 #include "isr.h" 16 #include "desc.h" 17 #include "apic.h" 18 #include "types.h" 19 #include "vmalloc.h" 20 #include "alloc_page.h" 21 #include "smp.h" 22 #include "delay.h" 23 24 #define NONCANONICAL 0xaaaaaaaaaaaaaaaaull 25 26 #define VPID_CAP_INVVPID_TYPES_SHIFT 40 27 28 u64 ia32_pat; 29 u64 ia32_efer; 30 void *io_bitmap_a, *io_bitmap_b; 31 u16 ioport; 32 33 unsigned long *pml4; 34 u64 eptp; 35 void *data_page1, *data_page2; 36 37 phys_addr_t pci_physaddr; 38 39 void *pml_log; 40 #define PML_INDEX 512 41 42 static inline unsigned ffs(unsigned x) 43 { 44 int pos = -1; 45 46 __asm__ __volatile__("bsf %1, %%eax; cmovnz %%eax, %0" 47 : "+r"(pos) : "rm"(x) : "eax"); 48 return pos + 1; 49 } 50 51 static inline void vmcall(void) 52 { 53 asm volatile("vmcall"); 54 } 55 56 static void basic_guest_main(void) 57 { 58 report("Basic VMX test", 1); 59 } 60 61 static int basic_exit_handler(void) 62 { 63 report("Basic VMX test", 0); 64 print_vmexit_info(); 65 return VMX_TEST_EXIT; 66 } 67 68 static void vmenter_main(void) 69 { 70 u64 rax; 71 u64 rsp, resume_rsp; 72 73 report("test vmlaunch", 1); 74 75 asm volatile( 76 "mov %%rsp, %0\n\t" 77 "mov %3, %%rax\n\t" 78 "vmcall\n\t" 79 "mov %%rax, %1\n\t" 80 "mov %%rsp, %2\n\t" 81 : "=r"(rsp), "=r"(rax), "=r"(resume_rsp) 82 : "g"(0xABCD)); 83 report("test vmresume", (rax == 0xFFFF) && (rsp == resume_rsp)); 84 } 85 86 static int vmenter_exit_handler(void) 87 { 88 u64 guest_rip; 89 ulong reason; 90 91 guest_rip = vmcs_read(GUEST_RIP); 92 reason = vmcs_read(EXI_REASON) & 0xff; 93 switch (reason) { 94 case VMX_VMCALL: 95 if (regs.rax != 0xABCD) { 96 report("test vmresume", 0); 97 return VMX_TEST_VMEXIT; 98 } 99 regs.rax = 0xFFFF; 100 vmcs_write(GUEST_RIP, guest_rip + 3); 101 return VMX_TEST_RESUME; 102 default: 103 report("test vmresume", 0); 104 print_vmexit_info(); 105 } 106 return VMX_TEST_VMEXIT; 107 } 108 109 u32 preempt_scale; 110 volatile unsigned long long tsc_val; 111 volatile u32 preempt_val; 112 u64 saved_rip; 113 114 static int preemption_timer_init(struct vmcs *vmcs) 115 { 116 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 117 printf("\tPreemption timer is not supported\n"); 118 return VMX_TEST_EXIT; 119 } 120 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 121 preempt_val = 10000000; 122 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 123 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 124 125 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 126 printf("\tSave preemption value is not supported\n"); 127 128 return VMX_TEST_START; 129 } 130 131 static void preemption_timer_main(void) 132 { 133 tsc_val = rdtsc(); 134 if (ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) { 135 vmx_set_test_stage(0); 136 vmcall(); 137 if (vmx_get_test_stage() == 1) 138 vmcall(); 139 } 140 vmx_set_test_stage(1); 141 while (vmx_get_test_stage() == 1) { 142 if (((rdtsc() - tsc_val) >> preempt_scale) 143 > 10 * preempt_val) { 144 vmx_set_test_stage(2); 145 vmcall(); 146 } 147 } 148 tsc_val = rdtsc(); 149 asm volatile ("hlt"); 150 vmcall(); 151 vmx_set_test_stage(5); 152 vmcall(); 153 } 154 155 static int preemption_timer_exit_handler(void) 156 { 157 bool guest_halted; 158 u64 guest_rip; 159 ulong reason; 160 u32 insn_len; 161 u32 ctrl_exit; 162 163 guest_rip = vmcs_read(GUEST_RIP); 164 reason = vmcs_read(EXI_REASON) & 0xff; 165 insn_len = vmcs_read(EXI_INST_LEN); 166 switch (reason) { 167 case VMX_PREEMPT: 168 switch (vmx_get_test_stage()) { 169 case 1: 170 case 2: 171 report("busy-wait for preemption timer", 172 ((rdtsc() - tsc_val) >> preempt_scale) >= 173 preempt_val); 174 vmx_set_test_stage(3); 175 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 176 return VMX_TEST_RESUME; 177 case 3: 178 guest_halted = 179 (vmcs_read(GUEST_ACTV_STATE) == ACTV_HLT); 180 report("preemption timer during hlt", 181 ((rdtsc() - tsc_val) >> preempt_scale) >= 182 preempt_val && guest_halted); 183 vmx_set_test_stage(4); 184 vmcs_write(PIN_CONTROLS, 185 vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 186 vmcs_write(EXI_CONTROLS, 187 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_PREEMPT); 188 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 189 return VMX_TEST_RESUME; 190 case 4: 191 report("preemption timer with 0 value", 192 saved_rip == guest_rip); 193 break; 194 default: 195 report("Invalid stage.", false); 196 print_vmexit_info(); 197 break; 198 } 199 break; 200 case VMX_VMCALL: 201 vmcs_write(GUEST_RIP, guest_rip + insn_len); 202 switch (vmx_get_test_stage()) { 203 case 0: 204 report("Keep preemption value", 205 vmcs_read(PREEMPT_TIMER_VALUE) == preempt_val); 206 vmx_set_test_stage(1); 207 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 208 ctrl_exit = (vmcs_read(EXI_CONTROLS) | 209 EXI_SAVE_PREEMPT) & ctrl_exit_rev.clr; 210 vmcs_write(EXI_CONTROLS, ctrl_exit); 211 return VMX_TEST_RESUME; 212 case 1: 213 report("Save preemption value", 214 vmcs_read(PREEMPT_TIMER_VALUE) < preempt_val); 215 return VMX_TEST_RESUME; 216 case 2: 217 report("busy-wait for preemption timer", 0); 218 vmx_set_test_stage(3); 219 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 220 return VMX_TEST_RESUME; 221 case 3: 222 report("preemption timer during hlt", 0); 223 vmx_set_test_stage(4); 224 /* fall through */ 225 case 4: 226 vmcs_write(PIN_CONTROLS, 227 vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 228 vmcs_write(PREEMPT_TIMER_VALUE, 0); 229 saved_rip = guest_rip + insn_len; 230 return VMX_TEST_RESUME; 231 case 5: 232 report("preemption timer with 0 value (vmcall stage 5)", 0); 233 break; 234 default: 235 // Should not reach here 236 report("unexpected stage, %d", false, 237 vmx_get_test_stage()); 238 print_vmexit_info(); 239 return VMX_TEST_VMEXIT; 240 } 241 break; 242 default: 243 report("Unknown exit reason, %ld", false, reason); 244 print_vmexit_info(); 245 } 246 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 247 return VMX_TEST_VMEXIT; 248 } 249 250 static void msr_bmp_init(void) 251 { 252 void *msr_bitmap; 253 u32 ctrl_cpu0; 254 255 msr_bitmap = alloc_page(); 256 memset(msr_bitmap, 0x0, PAGE_SIZE); 257 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 258 ctrl_cpu0 |= CPU_MSR_BITMAP; 259 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 260 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 261 } 262 263 static void *get_msr_bitmap(void) 264 { 265 void *msr_bitmap; 266 267 if (vmcs_read(CPU_EXEC_CTRL0) & CPU_MSR_BITMAP) { 268 msr_bitmap = (void *)vmcs_read(MSR_BITMAP); 269 } else { 270 msr_bitmap = alloc_page(); 271 memset(msr_bitmap, 0xff, PAGE_SIZE); 272 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 273 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_MSR_BITMAP); 274 } 275 276 return msr_bitmap; 277 } 278 279 static void disable_intercept_for_x2apic_msrs(void) 280 { 281 unsigned long *msr_bitmap = (unsigned long *)get_msr_bitmap(); 282 u32 msr; 283 284 for (msr = APIC_BASE_MSR; 285 msr < (APIC_BASE_MSR+0xff); 286 msr += BITS_PER_LONG) { 287 unsigned int word = msr / BITS_PER_LONG; 288 289 msr_bitmap[word] = 0; 290 msr_bitmap[word + (0x800 / sizeof(long))] = 0; 291 } 292 } 293 294 static int test_ctrl_pat_init(struct vmcs *vmcs) 295 { 296 u64 ctrl_ent; 297 u64 ctrl_exi; 298 299 msr_bmp_init(); 300 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT) && 301 !(ctrl_exit_rev.clr & EXI_LOAD_PAT) && 302 !(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 303 printf("\tSave/load PAT is not supported\n"); 304 return 1; 305 } 306 307 ctrl_ent = vmcs_read(ENT_CONTROLS); 308 ctrl_exi = vmcs_read(EXI_CONTROLS); 309 ctrl_ent |= ctrl_enter_rev.clr & ENT_LOAD_PAT; 310 ctrl_exi |= ctrl_exit_rev.clr & (EXI_SAVE_PAT | EXI_LOAD_PAT); 311 vmcs_write(ENT_CONTROLS, ctrl_ent); 312 vmcs_write(EXI_CONTROLS, ctrl_exi); 313 ia32_pat = rdmsr(MSR_IA32_CR_PAT); 314 vmcs_write(GUEST_PAT, 0x0); 315 vmcs_write(HOST_PAT, ia32_pat); 316 return VMX_TEST_START; 317 } 318 319 static void test_ctrl_pat_main(void) 320 { 321 u64 guest_ia32_pat; 322 323 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 324 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) 325 printf("\tENT_LOAD_PAT is not supported.\n"); 326 else { 327 if (guest_ia32_pat != 0) { 328 report("Entry load PAT", 0); 329 return; 330 } 331 } 332 wrmsr(MSR_IA32_CR_PAT, 0x6); 333 vmcall(); 334 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 335 if (ctrl_enter_rev.clr & ENT_LOAD_PAT) 336 report("Entry load PAT", guest_ia32_pat == ia32_pat); 337 } 338 339 static int test_ctrl_pat_exit_handler(void) 340 { 341 u64 guest_rip; 342 ulong reason; 343 u64 guest_pat; 344 345 guest_rip = vmcs_read(GUEST_RIP); 346 reason = vmcs_read(EXI_REASON) & 0xff; 347 switch (reason) { 348 case VMX_VMCALL: 349 guest_pat = vmcs_read(GUEST_PAT); 350 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT)) { 351 printf("\tEXI_SAVE_PAT is not supported\n"); 352 vmcs_write(GUEST_PAT, 0x6); 353 } else { 354 report("Exit save PAT", guest_pat == 0x6); 355 } 356 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) 357 printf("\tEXI_LOAD_PAT is not supported\n"); 358 else 359 report("Exit load PAT", rdmsr(MSR_IA32_CR_PAT) == ia32_pat); 360 vmcs_write(GUEST_PAT, ia32_pat); 361 vmcs_write(GUEST_RIP, guest_rip + 3); 362 return VMX_TEST_RESUME; 363 default: 364 printf("ERROR : Undefined exit reason, reason = %ld.\n", reason); 365 break; 366 } 367 return VMX_TEST_VMEXIT; 368 } 369 370 static int test_ctrl_efer_init(struct vmcs *vmcs) 371 { 372 u64 ctrl_ent; 373 u64 ctrl_exi; 374 375 msr_bmp_init(); 376 ctrl_ent = vmcs_read(ENT_CONTROLS) | ENT_LOAD_EFER; 377 ctrl_exi = vmcs_read(EXI_CONTROLS) | EXI_SAVE_EFER | EXI_LOAD_EFER; 378 vmcs_write(ENT_CONTROLS, ctrl_ent & ctrl_enter_rev.clr); 379 vmcs_write(EXI_CONTROLS, ctrl_exi & ctrl_exit_rev.clr); 380 ia32_efer = rdmsr(MSR_EFER); 381 vmcs_write(GUEST_EFER, ia32_efer ^ EFER_NX); 382 vmcs_write(HOST_EFER, ia32_efer ^ EFER_NX); 383 return VMX_TEST_START; 384 } 385 386 static void test_ctrl_efer_main(void) 387 { 388 u64 guest_ia32_efer; 389 390 guest_ia32_efer = rdmsr(MSR_EFER); 391 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) 392 printf("\tENT_LOAD_EFER is not supported.\n"); 393 else { 394 if (guest_ia32_efer != (ia32_efer ^ EFER_NX)) { 395 report("Entry load EFER", 0); 396 return; 397 } 398 } 399 wrmsr(MSR_EFER, ia32_efer); 400 vmcall(); 401 guest_ia32_efer = rdmsr(MSR_EFER); 402 if (ctrl_enter_rev.clr & ENT_LOAD_EFER) 403 report("Entry load EFER", guest_ia32_efer == ia32_efer); 404 } 405 406 static int test_ctrl_efer_exit_handler(void) 407 { 408 u64 guest_rip; 409 ulong reason; 410 u64 guest_efer; 411 412 guest_rip = vmcs_read(GUEST_RIP); 413 reason = vmcs_read(EXI_REASON) & 0xff; 414 switch (reason) { 415 case VMX_VMCALL: 416 guest_efer = vmcs_read(GUEST_EFER); 417 if (!(ctrl_exit_rev.clr & EXI_SAVE_EFER)) { 418 printf("\tEXI_SAVE_EFER is not supported\n"); 419 vmcs_write(GUEST_EFER, ia32_efer); 420 } else { 421 report("Exit save EFER", guest_efer == ia32_efer); 422 } 423 if (!(ctrl_exit_rev.clr & EXI_LOAD_EFER)) { 424 printf("\tEXI_LOAD_EFER is not supported\n"); 425 wrmsr(MSR_EFER, ia32_efer ^ EFER_NX); 426 } else { 427 report("Exit load EFER", rdmsr(MSR_EFER) == (ia32_efer ^ EFER_NX)); 428 } 429 vmcs_write(GUEST_PAT, ia32_efer); 430 vmcs_write(GUEST_RIP, guest_rip + 3); 431 return VMX_TEST_RESUME; 432 default: 433 printf("ERROR : Undefined exit reason, reason = %ld.\n", reason); 434 break; 435 } 436 return VMX_TEST_VMEXIT; 437 } 438 439 u32 guest_cr0, guest_cr4; 440 441 static void cr_shadowing_main(void) 442 { 443 u32 cr0, cr4, tmp; 444 445 // Test read through 446 vmx_set_test_stage(0); 447 guest_cr0 = read_cr0(); 448 if (vmx_get_test_stage() == 1) 449 report("Read through CR0", 0); 450 else 451 vmcall(); 452 vmx_set_test_stage(1); 453 guest_cr4 = read_cr4(); 454 if (vmx_get_test_stage() == 2) 455 report("Read through CR4", 0); 456 else 457 vmcall(); 458 // Test write through 459 guest_cr0 = guest_cr0 ^ (X86_CR0_TS | X86_CR0_MP); 460 guest_cr4 = guest_cr4 ^ (X86_CR4_TSD | X86_CR4_DE); 461 vmx_set_test_stage(2); 462 write_cr0(guest_cr0); 463 if (vmx_get_test_stage() == 3) 464 report("Write throuth CR0", 0); 465 else 466 vmcall(); 467 vmx_set_test_stage(3); 468 write_cr4(guest_cr4); 469 if (vmx_get_test_stage() == 4) 470 report("Write through CR4", 0); 471 else 472 vmcall(); 473 // Test read shadow 474 vmx_set_test_stage(4); 475 vmcall(); 476 cr0 = read_cr0(); 477 if (vmx_get_test_stage() != 5) 478 report("Read shadowing CR0", cr0 == guest_cr0); 479 vmx_set_test_stage(5); 480 cr4 = read_cr4(); 481 if (vmx_get_test_stage() != 6) 482 report("Read shadowing CR4", cr4 == guest_cr4); 483 // Test write shadow (same value with shadow) 484 vmx_set_test_stage(6); 485 write_cr0(guest_cr0); 486 if (vmx_get_test_stage() == 7) 487 report("Write shadowing CR0 (same value with shadow)", 0); 488 else 489 vmcall(); 490 vmx_set_test_stage(7); 491 write_cr4(guest_cr4); 492 if (vmx_get_test_stage() == 8) 493 report("Write shadowing CR4 (same value with shadow)", 0); 494 else 495 vmcall(); 496 // Test write shadow (different value) 497 vmx_set_test_stage(8); 498 tmp = guest_cr0 ^ X86_CR0_TS; 499 asm volatile("mov %0, %%rsi\n\t" 500 "mov %%rsi, %%cr0\n\t" 501 ::"m"(tmp) 502 :"rsi", "memory", "cc"); 503 report("Write shadowing different X86_CR0_TS", vmx_get_test_stage() == 9); 504 vmx_set_test_stage(9); 505 tmp = guest_cr0 ^ X86_CR0_MP; 506 asm volatile("mov %0, %%rsi\n\t" 507 "mov %%rsi, %%cr0\n\t" 508 ::"m"(tmp) 509 :"rsi", "memory", "cc"); 510 report("Write shadowing different X86_CR0_MP", vmx_get_test_stage() == 10); 511 vmx_set_test_stage(10); 512 tmp = guest_cr4 ^ X86_CR4_TSD; 513 asm volatile("mov %0, %%rsi\n\t" 514 "mov %%rsi, %%cr4\n\t" 515 ::"m"(tmp) 516 :"rsi", "memory", "cc"); 517 report("Write shadowing different X86_CR4_TSD", vmx_get_test_stage() == 11); 518 vmx_set_test_stage(11); 519 tmp = guest_cr4 ^ X86_CR4_DE; 520 asm volatile("mov %0, %%rsi\n\t" 521 "mov %%rsi, %%cr4\n\t" 522 ::"m"(tmp) 523 :"rsi", "memory", "cc"); 524 report("Write shadowing different X86_CR4_DE", vmx_get_test_stage() == 12); 525 } 526 527 static int cr_shadowing_exit_handler(void) 528 { 529 u64 guest_rip; 530 ulong reason; 531 u32 insn_len; 532 u32 exit_qual; 533 534 guest_rip = vmcs_read(GUEST_RIP); 535 reason = vmcs_read(EXI_REASON) & 0xff; 536 insn_len = vmcs_read(EXI_INST_LEN); 537 exit_qual = vmcs_read(EXI_QUALIFICATION); 538 switch (reason) { 539 case VMX_VMCALL: 540 switch (vmx_get_test_stage()) { 541 case 0: 542 report("Read through CR0", guest_cr0 == vmcs_read(GUEST_CR0)); 543 break; 544 case 1: 545 report("Read through CR4", guest_cr4 == vmcs_read(GUEST_CR4)); 546 break; 547 case 2: 548 report("Write through CR0", guest_cr0 == vmcs_read(GUEST_CR0)); 549 break; 550 case 3: 551 report("Write through CR4", guest_cr4 == vmcs_read(GUEST_CR4)); 552 break; 553 case 4: 554 guest_cr0 = vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP); 555 guest_cr4 = vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE); 556 vmcs_write(CR0_MASK, X86_CR0_TS | X86_CR0_MP); 557 vmcs_write(CR0_READ_SHADOW, guest_cr0 & (X86_CR0_TS | X86_CR0_MP)); 558 vmcs_write(CR4_MASK, X86_CR4_TSD | X86_CR4_DE); 559 vmcs_write(CR4_READ_SHADOW, guest_cr4 & (X86_CR4_TSD | X86_CR4_DE)); 560 break; 561 case 6: 562 report("Write shadowing CR0 (same value)", 563 guest_cr0 == (vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP))); 564 break; 565 case 7: 566 report("Write shadowing CR4 (same value)", 567 guest_cr4 == (vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE))); 568 break; 569 default: 570 // Should not reach here 571 report("unexpected stage, %d", false, 572 vmx_get_test_stage()); 573 print_vmexit_info(); 574 return VMX_TEST_VMEXIT; 575 } 576 vmcs_write(GUEST_RIP, guest_rip + insn_len); 577 return VMX_TEST_RESUME; 578 case VMX_CR: 579 switch (vmx_get_test_stage()) { 580 case 4: 581 report("Read shadowing CR0", 0); 582 vmx_inc_test_stage(); 583 break; 584 case 5: 585 report("Read shadowing CR4", 0); 586 vmx_inc_test_stage(); 587 break; 588 case 6: 589 report("Write shadowing CR0 (same value)", 0); 590 vmx_inc_test_stage(); 591 break; 592 case 7: 593 report("Write shadowing CR4 (same value)", 0); 594 vmx_inc_test_stage(); 595 break; 596 case 8: 597 case 9: 598 // 0x600 encodes "mov %esi, %cr0" 599 if (exit_qual == 0x600) 600 vmx_inc_test_stage(); 601 break; 602 case 10: 603 case 11: 604 // 0x604 encodes "mov %esi, %cr4" 605 if (exit_qual == 0x604) 606 vmx_inc_test_stage(); 607 break; 608 default: 609 // Should not reach here 610 report("unexpected stage, %d", false, 611 vmx_get_test_stage()); 612 print_vmexit_info(); 613 return VMX_TEST_VMEXIT; 614 } 615 vmcs_write(GUEST_RIP, guest_rip + insn_len); 616 return VMX_TEST_RESUME; 617 default: 618 report("Unknown exit reason, %ld", false, reason); 619 print_vmexit_info(); 620 } 621 return VMX_TEST_VMEXIT; 622 } 623 624 static int iobmp_init(struct vmcs *vmcs) 625 { 626 u32 ctrl_cpu0; 627 628 io_bitmap_a = alloc_page(); 629 io_bitmap_b = alloc_page(); 630 memset(io_bitmap_a, 0x0, PAGE_SIZE); 631 memset(io_bitmap_b, 0x0, PAGE_SIZE); 632 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 633 ctrl_cpu0 |= CPU_IO_BITMAP; 634 ctrl_cpu0 &= (~CPU_IO); 635 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 636 vmcs_write(IO_BITMAP_A, (u64)io_bitmap_a); 637 vmcs_write(IO_BITMAP_B, (u64)io_bitmap_b); 638 return VMX_TEST_START; 639 } 640 641 static void iobmp_main(void) 642 { 643 // stage 0, test IO pass 644 vmx_set_test_stage(0); 645 inb(0x5000); 646 outb(0x0, 0x5000); 647 report("I/O bitmap - I/O pass", vmx_get_test_stage() == 0); 648 // test IO width, in/out 649 ((u8 *)io_bitmap_a)[0] = 0xFF; 650 vmx_set_test_stage(2); 651 inb(0x0); 652 report("I/O bitmap - trap in", vmx_get_test_stage() == 3); 653 vmx_set_test_stage(3); 654 outw(0x0, 0x0); 655 report("I/O bitmap - trap out", vmx_get_test_stage() == 4); 656 vmx_set_test_stage(4); 657 inl(0x0); 658 report("I/O bitmap - I/O width, long", vmx_get_test_stage() == 5); 659 // test low/high IO port 660 vmx_set_test_stage(5); 661 ((u8 *)io_bitmap_a)[0x5000 / 8] = (1 << (0x5000 % 8)); 662 inb(0x5000); 663 report("I/O bitmap - I/O port, low part", vmx_get_test_stage() == 6); 664 vmx_set_test_stage(6); 665 ((u8 *)io_bitmap_b)[0x1000 / 8] = (1 << (0x1000 % 8)); 666 inb(0x9000); 667 report("I/O bitmap - I/O port, high part", vmx_get_test_stage() == 7); 668 // test partial pass 669 vmx_set_test_stage(7); 670 inl(0x4FFF); 671 report("I/O bitmap - partial pass", vmx_get_test_stage() == 8); 672 // test overrun 673 vmx_set_test_stage(8); 674 memset(io_bitmap_a, 0x0, PAGE_SIZE); 675 memset(io_bitmap_b, 0x0, PAGE_SIZE); 676 inl(0xFFFF); 677 report("I/O bitmap - overrun", vmx_get_test_stage() == 9); 678 vmx_set_test_stage(9); 679 vmcall(); 680 outb(0x0, 0x0); 681 report("I/O bitmap - ignore unconditional exiting", 682 vmx_get_test_stage() == 9); 683 vmx_set_test_stage(10); 684 vmcall(); 685 outb(0x0, 0x0); 686 report("I/O bitmap - unconditional exiting", 687 vmx_get_test_stage() == 11); 688 } 689 690 static int iobmp_exit_handler(void) 691 { 692 u64 guest_rip; 693 ulong reason, exit_qual; 694 u32 insn_len, ctrl_cpu0; 695 696 guest_rip = vmcs_read(GUEST_RIP); 697 reason = vmcs_read(EXI_REASON) & 0xff; 698 exit_qual = vmcs_read(EXI_QUALIFICATION); 699 insn_len = vmcs_read(EXI_INST_LEN); 700 switch (reason) { 701 case VMX_IO: 702 switch (vmx_get_test_stage()) { 703 case 0: 704 case 1: 705 vmx_inc_test_stage(); 706 break; 707 case 2: 708 report("I/O bitmap - I/O width, byte", 709 (exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_BYTE); 710 report("I/O bitmap - I/O direction, in", exit_qual & VMX_IO_IN); 711 vmx_inc_test_stage(); 712 break; 713 case 3: 714 report("I/O bitmap - I/O width, word", 715 (exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_WORD); 716 report("I/O bitmap - I/O direction, out", 717 !(exit_qual & VMX_IO_IN)); 718 vmx_inc_test_stage(); 719 break; 720 case 4: 721 report("I/O bitmap - I/O width, long", 722 (exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_LONG); 723 vmx_inc_test_stage(); 724 break; 725 case 5: 726 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x5000) 727 vmx_inc_test_stage(); 728 break; 729 case 6: 730 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x9000) 731 vmx_inc_test_stage(); 732 break; 733 case 7: 734 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x4FFF) 735 vmx_inc_test_stage(); 736 break; 737 case 8: 738 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0xFFFF) 739 vmx_inc_test_stage(); 740 break; 741 case 9: 742 case 10: 743 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 744 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0 & ~CPU_IO); 745 vmx_inc_test_stage(); 746 break; 747 default: 748 // Should not reach here 749 report("unexpected stage, %d", false, 750 vmx_get_test_stage()); 751 print_vmexit_info(); 752 return VMX_TEST_VMEXIT; 753 } 754 vmcs_write(GUEST_RIP, guest_rip + insn_len); 755 return VMX_TEST_RESUME; 756 case VMX_VMCALL: 757 switch (vmx_get_test_stage()) { 758 case 9: 759 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 760 ctrl_cpu0 |= CPU_IO | CPU_IO_BITMAP; 761 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 762 break; 763 case 10: 764 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 765 ctrl_cpu0 = (ctrl_cpu0 & ~CPU_IO_BITMAP) | CPU_IO; 766 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 767 break; 768 default: 769 // Should not reach here 770 report("unexpected stage, %d", false, 771 vmx_get_test_stage()); 772 print_vmexit_info(); 773 return VMX_TEST_VMEXIT; 774 } 775 vmcs_write(GUEST_RIP, guest_rip + insn_len); 776 return VMX_TEST_RESUME; 777 default: 778 printf("guest_rip = %#lx\n", guest_rip); 779 printf("\tERROR : Undefined exit reason, reason = %ld.\n", reason); 780 break; 781 } 782 return VMX_TEST_VMEXIT; 783 } 784 785 #define INSN_CPU0 0 786 #define INSN_CPU1 1 787 #define INSN_ALWAYS_TRAP 2 788 789 #define FIELD_EXIT_QUAL (1 << 0) 790 #define FIELD_INSN_INFO (1 << 1) 791 792 asm( 793 "insn_hlt: hlt;ret\n\t" 794 "insn_invlpg: invlpg 0x12345678;ret\n\t" 795 "insn_mwait: xor %eax, %eax; xor %ecx, %ecx; mwait;ret\n\t" 796 "insn_rdpmc: xor %ecx, %ecx; rdpmc;ret\n\t" 797 "insn_rdtsc: rdtsc;ret\n\t" 798 "insn_cr3_load: mov cr3,%rax; mov %rax,%cr3;ret\n\t" 799 "insn_cr3_store: mov %cr3,%rax;ret\n\t" 800 #ifdef __x86_64__ 801 "insn_cr8_load: xor %eax, %eax; mov %rax,%cr8;ret\n\t" 802 "insn_cr8_store: mov %cr8,%rax;ret\n\t" 803 #endif 804 "insn_monitor: xor %eax, %eax; xor %ecx, %ecx; xor %edx, %edx; monitor;ret\n\t" 805 "insn_pause: pause;ret\n\t" 806 "insn_wbinvd: wbinvd;ret\n\t" 807 "insn_cpuid: mov $10, %eax; cpuid;ret\n\t" 808 "insn_invd: invd;ret\n\t" 809 "insn_sgdt: sgdt gdt64_desc;ret\n\t" 810 "insn_lgdt: lgdt gdt64_desc;ret\n\t" 811 "insn_sidt: sidt idt_descr;ret\n\t" 812 "insn_lidt: lidt idt_descr;ret\n\t" 813 "insn_sldt: sldt %ax;ret\n\t" 814 "insn_lldt: xor %eax, %eax; lldt %ax;ret\n\t" 815 "insn_str: str %ax;ret\n\t" 816 "insn_rdrand: rdrand %rax;ret\n\t" 817 "insn_rdseed: rdseed %rax;ret\n\t" 818 ); 819 extern void insn_hlt(void); 820 extern void insn_invlpg(void); 821 extern void insn_mwait(void); 822 extern void insn_rdpmc(void); 823 extern void insn_rdtsc(void); 824 extern void insn_cr3_load(void); 825 extern void insn_cr3_store(void); 826 #ifdef __x86_64__ 827 extern void insn_cr8_load(void); 828 extern void insn_cr8_store(void); 829 #endif 830 extern void insn_monitor(void); 831 extern void insn_pause(void); 832 extern void insn_wbinvd(void); 833 extern void insn_sgdt(void); 834 extern void insn_lgdt(void); 835 extern void insn_sidt(void); 836 extern void insn_lidt(void); 837 extern void insn_sldt(void); 838 extern void insn_lldt(void); 839 extern void insn_str(void); 840 extern void insn_cpuid(void); 841 extern void insn_invd(void); 842 extern void insn_rdrand(void); 843 extern void insn_rdseed(void); 844 845 u32 cur_insn; 846 u64 cr3; 847 848 struct insn_table { 849 const char *name; 850 u32 flag; 851 void (*insn_func)(void); 852 u32 type; 853 u32 reason; 854 ulong exit_qual; 855 u32 insn_info; 856 // Use FIELD_EXIT_QUAL and FIELD_INSN_INFO to define 857 // which field need to be tested, reason is always tested 858 u32 test_field; 859 }; 860 861 /* 862 * Add more test cases of instruction intercept here. Elements in this 863 * table is: 864 * name/control flag/insn function/type/exit reason/exit qulification/ 865 * instruction info/field to test 866 * The last field defines which fields (exit_qual and insn_info) need to be 867 * tested in exit handler. If set to 0, only "reason" is checked. 868 */ 869 static struct insn_table insn_table[] = { 870 // Flags for Primary Processor-Based VM-Execution Controls 871 {"HLT", CPU_HLT, insn_hlt, INSN_CPU0, 12, 0, 0, 0}, 872 {"INVLPG", CPU_INVLPG, insn_invlpg, INSN_CPU0, 14, 873 0x12345678, 0, FIELD_EXIT_QUAL}, 874 {"MWAIT", CPU_MWAIT, insn_mwait, INSN_CPU0, 36, 0, 0, 0}, 875 {"RDPMC", CPU_RDPMC, insn_rdpmc, INSN_CPU0, 15, 0, 0, 0}, 876 {"RDTSC", CPU_RDTSC, insn_rdtsc, INSN_CPU0, 16, 0, 0, 0}, 877 {"CR3 load", CPU_CR3_LOAD, insn_cr3_load, INSN_CPU0, 28, 0x3, 0, 878 FIELD_EXIT_QUAL}, 879 {"CR3 store", CPU_CR3_STORE, insn_cr3_store, INSN_CPU0, 28, 0x13, 0, 880 FIELD_EXIT_QUAL}, 881 #ifdef __x86_64__ 882 {"CR8 load", CPU_CR8_LOAD, insn_cr8_load, INSN_CPU0, 28, 0x8, 0, 883 FIELD_EXIT_QUAL}, 884 {"CR8 store", CPU_CR8_STORE, insn_cr8_store, INSN_CPU0, 28, 0x18, 0, 885 FIELD_EXIT_QUAL}, 886 #endif 887 {"MONITOR", CPU_MONITOR, insn_monitor, INSN_CPU0, 39, 0, 0, 0}, 888 {"PAUSE", CPU_PAUSE, insn_pause, INSN_CPU0, 40, 0, 0, 0}, 889 // Flags for Secondary Processor-Based VM-Execution Controls 890 {"WBINVD", CPU_WBINVD, insn_wbinvd, INSN_CPU1, 54, 0, 0, 0}, 891 {"DESC_TABLE (SGDT)", CPU_DESC_TABLE, insn_sgdt, INSN_CPU1, 46, 0, 0, 0}, 892 {"DESC_TABLE (LGDT)", CPU_DESC_TABLE, insn_lgdt, INSN_CPU1, 46, 0, 0, 0}, 893 {"DESC_TABLE (SIDT)", CPU_DESC_TABLE, insn_sidt, INSN_CPU1, 46, 0, 0, 0}, 894 {"DESC_TABLE (LIDT)", CPU_DESC_TABLE, insn_lidt, INSN_CPU1, 46, 0, 0, 0}, 895 {"DESC_TABLE (SLDT)", CPU_DESC_TABLE, insn_sldt, INSN_CPU1, 47, 0, 0, 0}, 896 {"DESC_TABLE (LLDT)", CPU_DESC_TABLE, insn_lldt, INSN_CPU1, 47, 0, 0, 0}, 897 {"DESC_TABLE (STR)", CPU_DESC_TABLE, insn_str, INSN_CPU1, 47, 0, 0, 0}, 898 /* LTR causes a #GP if done with a busy selector, so it is not tested. */ 899 {"RDRAND", CPU_RDRAND, insn_rdrand, INSN_CPU1, VMX_RDRAND, 0, 0, 0}, 900 {"RDSEED", CPU_RDSEED, insn_rdseed, INSN_CPU1, VMX_RDSEED, 0, 0, 0}, 901 // Instructions always trap 902 {"CPUID", 0, insn_cpuid, INSN_ALWAYS_TRAP, 10, 0, 0, 0}, 903 {"INVD", 0, insn_invd, INSN_ALWAYS_TRAP, 13, 0, 0, 0}, 904 // Instructions never trap 905 {NULL}, 906 }; 907 908 static int insn_intercept_init(struct vmcs *vmcs) 909 { 910 u32 ctrl_cpu; 911 912 ctrl_cpu = ctrl_cpu_rev[0].set | CPU_SECONDARY; 913 ctrl_cpu &= ctrl_cpu_rev[0].clr; 914 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu); 915 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu_rev[1].set); 916 cr3 = read_cr3(); 917 return VMX_TEST_START; 918 } 919 920 static void insn_intercept_main(void) 921 { 922 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 923 vmx_set_test_stage(cur_insn * 2); 924 if ((insn_table[cur_insn].type == INSN_CPU0 && 925 !(ctrl_cpu_rev[0].clr & insn_table[cur_insn].flag)) || 926 (insn_table[cur_insn].type == INSN_CPU1 && 927 !(ctrl_cpu_rev[1].clr & insn_table[cur_insn].flag))) { 928 printf("\tCPU_CTRL%d.CPU_%s is not supported.\n", 929 insn_table[cur_insn].type - INSN_CPU0, 930 insn_table[cur_insn].name); 931 continue; 932 } 933 934 if ((insn_table[cur_insn].type == INSN_CPU0 && 935 !(ctrl_cpu_rev[0].set & insn_table[cur_insn].flag)) || 936 (insn_table[cur_insn].type == INSN_CPU1 && 937 !(ctrl_cpu_rev[1].set & insn_table[cur_insn].flag))) { 938 /* skip hlt, it stalls the guest and is tested below */ 939 if (insn_table[cur_insn].insn_func != insn_hlt) 940 insn_table[cur_insn].insn_func(); 941 report("execute %s", vmx_get_test_stage() == cur_insn * 2, 942 insn_table[cur_insn].name); 943 } else if (insn_table[cur_insn].type != INSN_ALWAYS_TRAP) 944 printf("\tCPU_CTRL%d.CPU_%s always traps.\n", 945 insn_table[cur_insn].type - INSN_CPU0, 946 insn_table[cur_insn].name); 947 948 vmcall(); 949 950 insn_table[cur_insn].insn_func(); 951 report("intercept %s", vmx_get_test_stage() == cur_insn * 2 + 1, 952 insn_table[cur_insn].name); 953 954 vmx_set_test_stage(cur_insn * 2 + 1); 955 vmcall(); 956 } 957 } 958 959 static int insn_intercept_exit_handler(void) 960 { 961 u64 guest_rip; 962 u32 reason; 963 ulong exit_qual; 964 u32 insn_len; 965 u32 insn_info; 966 bool pass; 967 968 guest_rip = vmcs_read(GUEST_RIP); 969 reason = vmcs_read(EXI_REASON) & 0xff; 970 exit_qual = vmcs_read(EXI_QUALIFICATION); 971 insn_len = vmcs_read(EXI_INST_LEN); 972 insn_info = vmcs_read(EXI_INST_INFO); 973 974 if (reason == VMX_VMCALL) { 975 u32 val = 0; 976 977 if (insn_table[cur_insn].type == INSN_CPU0) 978 val = vmcs_read(CPU_EXEC_CTRL0); 979 else if (insn_table[cur_insn].type == INSN_CPU1) 980 val = vmcs_read(CPU_EXEC_CTRL1); 981 982 if (vmx_get_test_stage() & 1) 983 val &= ~insn_table[cur_insn].flag; 984 else 985 val |= insn_table[cur_insn].flag; 986 987 if (insn_table[cur_insn].type == INSN_CPU0) 988 vmcs_write(CPU_EXEC_CTRL0, val | ctrl_cpu_rev[0].set); 989 else if (insn_table[cur_insn].type == INSN_CPU1) 990 vmcs_write(CPU_EXEC_CTRL1, val | ctrl_cpu_rev[1].set); 991 } else { 992 pass = (cur_insn * 2 == vmx_get_test_stage()) && 993 insn_table[cur_insn].reason == reason; 994 if (insn_table[cur_insn].test_field & FIELD_EXIT_QUAL && 995 insn_table[cur_insn].exit_qual != exit_qual) 996 pass = false; 997 if (insn_table[cur_insn].test_field & FIELD_INSN_INFO && 998 insn_table[cur_insn].insn_info != insn_info) 999 pass = false; 1000 if (pass) 1001 vmx_inc_test_stage(); 1002 } 1003 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1004 return VMX_TEST_RESUME; 1005 } 1006 1007 1008 /* Enables EPT and sets up the identity map. */ 1009 static int setup_ept(bool enable_ad) 1010 { 1011 unsigned long end_of_memory; 1012 u32 ctrl_cpu[2]; 1013 1014 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1015 !(ctrl_cpu_rev[1].clr & CPU_EPT)) { 1016 printf("\tEPT is not supported"); 1017 return 1; 1018 } 1019 1020 1021 if (!(ept_vpid.val & EPT_CAP_UC) && 1022 !(ept_vpid.val & EPT_CAP_WB)) { 1023 printf("\tEPT paging-structure memory type " 1024 "UC&WB are not supported\n"); 1025 return 1; 1026 } 1027 if (ept_vpid.val & EPT_CAP_UC) 1028 eptp = EPT_MEM_TYPE_UC; 1029 else 1030 eptp = EPT_MEM_TYPE_WB; 1031 if (!(ept_vpid.val & EPT_CAP_PWL4)) { 1032 printf("\tPWL4 is not supported\n"); 1033 return 1; 1034 } 1035 ctrl_cpu[0] = vmcs_read(CPU_EXEC_CTRL0); 1036 ctrl_cpu[1] = vmcs_read(CPU_EXEC_CTRL1); 1037 ctrl_cpu[0] = (ctrl_cpu[0] | CPU_SECONDARY) 1038 & ctrl_cpu_rev[0].clr; 1039 ctrl_cpu[1] = (ctrl_cpu[1] | CPU_EPT) 1040 & ctrl_cpu_rev[1].clr; 1041 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu[0]); 1042 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu[1]); 1043 eptp |= (3 << EPTP_PG_WALK_LEN_SHIFT); 1044 pml4 = alloc_page(); 1045 memset(pml4, 0, PAGE_SIZE); 1046 eptp |= virt_to_phys(pml4); 1047 if (enable_ad) 1048 eptp |= EPTP_AD_FLAG; 1049 vmcs_write(EPTP, eptp); 1050 end_of_memory = fwcfg_get_u64(FW_CFG_RAM_SIZE); 1051 if (end_of_memory < (1ul << 32)) 1052 end_of_memory = (1ul << 32); 1053 /* Cannot use large EPT pages if we need to track EPT 1054 * accessed/dirty bits at 4K granularity. 1055 */ 1056 setup_ept_range(pml4, 0, end_of_memory, 0, 1057 !enable_ad && ept_2m_supported(), 1058 EPT_WA | EPT_RA | EPT_EA); 1059 return 0; 1060 } 1061 1062 static void ept_enable_ad_bits(void) 1063 { 1064 eptp |= EPTP_AD_FLAG; 1065 vmcs_write(EPTP, eptp); 1066 } 1067 1068 static void ept_disable_ad_bits(void) 1069 { 1070 eptp &= ~EPTP_AD_FLAG; 1071 vmcs_write(EPTP, eptp); 1072 } 1073 1074 static void ept_enable_ad_bits_or_skip_test(void) 1075 { 1076 if (!ept_ad_bits_supported()) 1077 test_skip("EPT AD bits not supported."); 1078 ept_enable_ad_bits(); 1079 } 1080 1081 static int apic_version; 1082 1083 static int ept_init_common(bool have_ad) 1084 { 1085 int ret; 1086 struct pci_dev pcidev; 1087 1088 if (setup_ept(have_ad)) 1089 return VMX_TEST_EXIT; 1090 data_page1 = alloc_page(); 1091 data_page2 = alloc_page(); 1092 memset(data_page1, 0x0, PAGE_SIZE); 1093 memset(data_page2, 0x0, PAGE_SIZE); 1094 *((u32 *)data_page1) = MAGIC_VAL_1; 1095 *((u32 *)data_page2) = MAGIC_VAL_2; 1096 install_ept(pml4, (unsigned long)data_page1, (unsigned long)data_page2, 1097 EPT_RA | EPT_WA | EPT_EA); 1098 1099 apic_version = apic_read(APIC_LVR); 1100 1101 ret = pci_find_dev(PCI_VENDOR_ID_REDHAT, PCI_DEVICE_ID_REDHAT_TEST); 1102 if (ret != PCIDEVADDR_INVALID) { 1103 pci_dev_init(&pcidev, ret); 1104 pci_physaddr = pcidev.resource[PCI_TESTDEV_BAR_MEM]; 1105 } 1106 1107 return VMX_TEST_START; 1108 } 1109 1110 static int ept_init(struct vmcs *vmcs) 1111 { 1112 return ept_init_common(false); 1113 } 1114 1115 static void ept_common(void) 1116 { 1117 vmx_set_test_stage(0); 1118 if (*((u32 *)data_page2) != MAGIC_VAL_1 || 1119 *((u32 *)data_page1) != MAGIC_VAL_1) 1120 report("EPT basic framework - read", 0); 1121 else { 1122 *((u32 *)data_page2) = MAGIC_VAL_3; 1123 vmcall(); 1124 if (vmx_get_test_stage() == 1) { 1125 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1126 *((u32 *)data_page2) == MAGIC_VAL_2) 1127 report("EPT basic framework", 1); 1128 else 1129 report("EPT basic framework - remap", 1); 1130 } 1131 } 1132 // Test EPT Misconfigurations 1133 vmx_set_test_stage(1); 1134 vmcall(); 1135 *((u32 *)data_page1) = MAGIC_VAL_1; 1136 if (vmx_get_test_stage() != 2) { 1137 report("EPT misconfigurations", 0); 1138 goto t1; 1139 } 1140 vmx_set_test_stage(2); 1141 vmcall(); 1142 *((u32 *)data_page1) = MAGIC_VAL_1; 1143 report("EPT misconfigurations", vmx_get_test_stage() == 3); 1144 t1: 1145 // Test EPT violation 1146 vmx_set_test_stage(3); 1147 vmcall(); 1148 *((u32 *)data_page1) = MAGIC_VAL_1; 1149 report("EPT violation - page permission", vmx_get_test_stage() == 4); 1150 // Violation caused by EPT paging structure 1151 vmx_set_test_stage(4); 1152 vmcall(); 1153 *((u32 *)data_page1) = MAGIC_VAL_2; 1154 report("EPT violation - paging structure", vmx_get_test_stage() == 5); 1155 1156 // MMIO Read/Write 1157 vmx_set_test_stage(5); 1158 vmcall(); 1159 1160 *(u32 volatile *)pci_physaddr; 1161 report("MMIO EPT violation - read", vmx_get_test_stage() == 6); 1162 1163 *(u32 volatile *)pci_physaddr = MAGIC_VAL_1; 1164 report("MMIO EPT violation - write", vmx_get_test_stage() == 7); 1165 } 1166 1167 static void ept_main(void) 1168 { 1169 ept_common(); 1170 1171 // Test EPT access to L1 MMIO 1172 vmx_set_test_stage(7); 1173 report("EPT - MMIO access", *((u32 *)0xfee00030UL) == apic_version); 1174 1175 // Test invalid operand for INVEPT 1176 vmcall(); 1177 report("EPT - unsupported INVEPT", vmx_get_test_stage() == 8); 1178 } 1179 1180 static bool invept_test(int type, u64 eptp) 1181 { 1182 bool ret, supported; 1183 1184 supported = ept_vpid.val & (EPT_CAP_INVEPT_SINGLE >> INVEPT_SINGLE << type); 1185 ret = invept(type, eptp); 1186 1187 if (ret == !supported) 1188 return false; 1189 1190 if (!supported) 1191 printf("WARNING: unsupported invept passed!\n"); 1192 else 1193 printf("WARNING: invept failed!\n"); 1194 1195 return true; 1196 } 1197 1198 static int pml_exit_handler(void) 1199 { 1200 u16 index, count; 1201 ulong reason = vmcs_read(EXI_REASON) & 0xff; 1202 u64 *pmlbuf = pml_log; 1203 u64 guest_rip = vmcs_read(GUEST_RIP);; 1204 u64 guest_cr3 = vmcs_read(GUEST_CR3); 1205 u32 insn_len = vmcs_read(EXI_INST_LEN); 1206 1207 switch (reason) { 1208 case VMX_VMCALL: 1209 switch (vmx_get_test_stage()) { 1210 case 0: 1211 index = vmcs_read(GUEST_PML_INDEX); 1212 for (count = index + 1; count < PML_INDEX; count++) { 1213 if (pmlbuf[count] == (u64)data_page2) { 1214 vmx_inc_test_stage(); 1215 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1216 break; 1217 } 1218 } 1219 break; 1220 case 1: 1221 index = vmcs_read(GUEST_PML_INDEX); 1222 /* Keep clearing the dirty bit till a overflow */ 1223 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1224 break; 1225 default: 1226 report("unexpected stage, %d.", false, 1227 vmx_get_test_stage()); 1228 print_vmexit_info(); 1229 return VMX_TEST_VMEXIT; 1230 } 1231 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1232 return VMX_TEST_RESUME; 1233 case VMX_PML_FULL: 1234 vmx_inc_test_stage(); 1235 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1236 return VMX_TEST_RESUME; 1237 default: 1238 report("Unknown exit reason, %ld", false, reason); 1239 print_vmexit_info(); 1240 } 1241 return VMX_TEST_VMEXIT; 1242 } 1243 1244 static int ept_exit_handler_common(bool have_ad) 1245 { 1246 u64 guest_rip; 1247 u64 guest_cr3; 1248 ulong reason; 1249 u32 insn_len; 1250 u32 exit_qual; 1251 static unsigned long data_page1_pte, data_page1_pte_pte, memaddr_pte; 1252 1253 guest_rip = vmcs_read(GUEST_RIP); 1254 guest_cr3 = vmcs_read(GUEST_CR3); 1255 reason = vmcs_read(EXI_REASON) & 0xff; 1256 insn_len = vmcs_read(EXI_INST_LEN); 1257 exit_qual = vmcs_read(EXI_QUALIFICATION); 1258 switch (reason) { 1259 case VMX_VMCALL: 1260 switch (vmx_get_test_stage()) { 1261 case 0: 1262 check_ept_ad(pml4, guest_cr3, 1263 (unsigned long)data_page1, 1264 have_ad ? EPT_ACCESS_FLAG : 0, 1265 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1266 check_ept_ad(pml4, guest_cr3, 1267 (unsigned long)data_page2, 1268 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0, 1269 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1270 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1271 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1272 if (have_ad) 1273 ept_sync(INVEPT_SINGLE, eptp);; 1274 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1275 *((u32 *)data_page2) == MAGIC_VAL_2) { 1276 vmx_inc_test_stage(); 1277 install_ept(pml4, (unsigned long)data_page2, 1278 (unsigned long)data_page2, 1279 EPT_RA | EPT_WA | EPT_EA); 1280 } else 1281 report("EPT basic framework - write", 0); 1282 break; 1283 case 1: 1284 install_ept(pml4, (unsigned long)data_page1, 1285 (unsigned long)data_page1, EPT_WA); 1286 ept_sync(INVEPT_SINGLE, eptp); 1287 break; 1288 case 2: 1289 install_ept(pml4, (unsigned long)data_page1, 1290 (unsigned long)data_page1, 1291 EPT_RA | EPT_WA | EPT_EA | 1292 (2 << EPT_MEM_TYPE_SHIFT)); 1293 ept_sync(INVEPT_SINGLE, eptp); 1294 break; 1295 case 3: 1296 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1297 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)data_page1, 1298 1, &data_page1_pte)); 1299 set_ept_pte(pml4, (unsigned long)data_page1, 1300 1, data_page1_pte & ~EPT_PRESENT); 1301 ept_sync(INVEPT_SINGLE, eptp); 1302 break; 1303 case 4: 1304 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)data_page1, 1305 2, &data_page1_pte)); 1306 data_page1_pte &= PAGE_MASK; 1307 TEST_ASSERT(get_ept_pte(pml4, data_page1_pte, 1308 2, &data_page1_pte_pte)); 1309 set_ept_pte(pml4, data_page1_pte, 2, 1310 data_page1_pte_pte & ~EPT_PRESENT); 1311 ept_sync(INVEPT_SINGLE, eptp); 1312 break; 1313 case 5: 1314 install_ept(pml4, (unsigned long)pci_physaddr, 1315 (unsigned long)pci_physaddr, 0); 1316 ept_sync(INVEPT_SINGLE, eptp); 1317 break; 1318 case 7: 1319 if (!invept_test(0, eptp)) 1320 vmx_inc_test_stage(); 1321 break; 1322 // Should not reach here 1323 default: 1324 report("ERROR - unexpected stage, %d.", false, 1325 vmx_get_test_stage()); 1326 print_vmexit_info(); 1327 return VMX_TEST_VMEXIT; 1328 } 1329 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1330 return VMX_TEST_RESUME; 1331 case VMX_EPT_MISCONFIG: 1332 switch (vmx_get_test_stage()) { 1333 case 1: 1334 case 2: 1335 vmx_inc_test_stage(); 1336 install_ept(pml4, (unsigned long)data_page1, 1337 (unsigned long)data_page1, 1338 EPT_RA | EPT_WA | EPT_EA); 1339 ept_sync(INVEPT_SINGLE, eptp); 1340 break; 1341 // Should not reach here 1342 default: 1343 report("ERROR - unexpected stage, %d.", false, 1344 vmx_get_test_stage()); 1345 print_vmexit_info(); 1346 return VMX_TEST_VMEXIT; 1347 } 1348 return VMX_TEST_RESUME; 1349 case VMX_EPT_VIOLATION: 1350 switch(vmx_get_test_stage()) { 1351 case 3: 1352 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1353 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1354 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1355 if (exit_qual == (EPT_VLT_WR | EPT_VLT_LADDR_VLD | 1356 EPT_VLT_PADDR)) 1357 vmx_inc_test_stage(); 1358 set_ept_pte(pml4, (unsigned long)data_page1, 1359 1, data_page1_pte | (EPT_PRESENT)); 1360 ept_sync(INVEPT_SINGLE, eptp); 1361 break; 1362 case 4: 1363 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1364 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1365 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1366 if (exit_qual == (EPT_VLT_RD | 1367 (have_ad ? EPT_VLT_WR : 0) | 1368 EPT_VLT_LADDR_VLD)) 1369 vmx_inc_test_stage(); 1370 set_ept_pte(pml4, data_page1_pte, 2, 1371 data_page1_pte_pte | (EPT_PRESENT)); 1372 ept_sync(INVEPT_SINGLE, eptp); 1373 break; 1374 case 5: 1375 if (exit_qual & EPT_VLT_RD) 1376 vmx_inc_test_stage(); 1377 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1378 1, &memaddr_pte)); 1379 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA); 1380 ept_sync(INVEPT_SINGLE, eptp); 1381 break; 1382 case 6: 1383 if (exit_qual & EPT_VLT_WR) 1384 vmx_inc_test_stage(); 1385 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1386 1, &memaddr_pte)); 1387 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA | EPT_WA); 1388 ept_sync(INVEPT_SINGLE, eptp); 1389 break; 1390 default: 1391 // Should not reach here 1392 report("ERROR : unexpected stage, %d", false, 1393 vmx_get_test_stage()); 1394 print_vmexit_info(); 1395 return VMX_TEST_VMEXIT; 1396 } 1397 return VMX_TEST_RESUME; 1398 default: 1399 report("Unknown exit reason, %ld", false, reason); 1400 print_vmexit_info(); 1401 } 1402 return VMX_TEST_VMEXIT; 1403 } 1404 1405 static int ept_exit_handler(void) 1406 { 1407 return ept_exit_handler_common(false); 1408 } 1409 1410 static int eptad_init(struct vmcs *vmcs) 1411 { 1412 int r = ept_init_common(true); 1413 1414 if (r == VMX_TEST_EXIT) 1415 return r; 1416 1417 if ((rdmsr(MSR_IA32_VMX_EPT_VPID_CAP) & EPT_CAP_AD_FLAG) == 0) { 1418 printf("\tEPT A/D bits are not supported"); 1419 return VMX_TEST_EXIT; 1420 } 1421 1422 return r; 1423 } 1424 1425 static int pml_init(struct vmcs *vmcs) 1426 { 1427 u32 ctrl_cpu; 1428 int r = eptad_init(vmcs); 1429 1430 if (r == VMX_TEST_EXIT) 1431 return r; 1432 1433 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1434 !(ctrl_cpu_rev[1].clr & CPU_PML)) { 1435 printf("\tPML is not supported"); 1436 return VMX_TEST_EXIT; 1437 } 1438 1439 pml_log = alloc_page(); 1440 memset(pml_log, 0x0, PAGE_SIZE); 1441 vmcs_write(PMLADDR, (u64)pml_log); 1442 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1443 1444 ctrl_cpu = vmcs_read(CPU_EXEC_CTRL1) | CPU_PML; 1445 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu); 1446 1447 return VMX_TEST_START; 1448 } 1449 1450 static void pml_main(void) 1451 { 1452 int count = 0; 1453 1454 vmx_set_test_stage(0); 1455 *((u32 *)data_page2) = 0x1; 1456 vmcall(); 1457 report("PML - Dirty GPA Logging", vmx_get_test_stage() == 1); 1458 1459 while (vmx_get_test_stage() == 1) { 1460 vmcall(); 1461 *((u32 *)data_page2) = 0x1; 1462 if (count++ > PML_INDEX) 1463 break; 1464 } 1465 report("PML Full Event", vmx_get_test_stage() == 2); 1466 } 1467 1468 static void eptad_main(void) 1469 { 1470 ept_common(); 1471 } 1472 1473 static int eptad_exit_handler(void) 1474 { 1475 return ept_exit_handler_common(true); 1476 } 1477 1478 static bool invvpid_test(int type, u16 vpid) 1479 { 1480 bool ret, supported; 1481 1482 supported = ept_vpid.val & 1483 (VPID_CAP_INVVPID_ADDR >> INVVPID_ADDR << type); 1484 ret = invvpid(type, vpid, 0); 1485 1486 if (ret == !supported) 1487 return false; 1488 1489 if (!supported) 1490 printf("WARNING: unsupported invvpid passed!\n"); 1491 else 1492 printf("WARNING: invvpid failed!\n"); 1493 1494 return true; 1495 } 1496 1497 static int vpid_init(struct vmcs *vmcs) 1498 { 1499 u32 ctrl_cpu1; 1500 1501 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1502 !(ctrl_cpu_rev[1].clr & CPU_VPID)) { 1503 printf("\tVPID is not supported"); 1504 return VMX_TEST_EXIT; 1505 } 1506 1507 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 1508 ctrl_cpu1 |= CPU_VPID; 1509 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 1510 return VMX_TEST_START; 1511 } 1512 1513 static void vpid_main(void) 1514 { 1515 vmx_set_test_stage(0); 1516 vmcall(); 1517 report("INVVPID SINGLE ADDRESS", vmx_get_test_stage() == 1); 1518 vmx_set_test_stage(2); 1519 vmcall(); 1520 report("INVVPID SINGLE", vmx_get_test_stage() == 3); 1521 vmx_set_test_stage(4); 1522 vmcall(); 1523 report("INVVPID ALL", vmx_get_test_stage() == 5); 1524 } 1525 1526 static int vpid_exit_handler(void) 1527 { 1528 u64 guest_rip; 1529 ulong reason; 1530 u32 insn_len; 1531 1532 guest_rip = vmcs_read(GUEST_RIP); 1533 reason = vmcs_read(EXI_REASON) & 0xff; 1534 insn_len = vmcs_read(EXI_INST_LEN); 1535 1536 switch (reason) { 1537 case VMX_VMCALL: 1538 switch(vmx_get_test_stage()) { 1539 case 0: 1540 if (!invvpid_test(INVVPID_ADDR, 1)) 1541 vmx_inc_test_stage(); 1542 break; 1543 case 2: 1544 if (!invvpid_test(INVVPID_CONTEXT_GLOBAL, 1)) 1545 vmx_inc_test_stage(); 1546 break; 1547 case 4: 1548 if (!invvpid_test(INVVPID_ALL, 1)) 1549 vmx_inc_test_stage(); 1550 break; 1551 default: 1552 report("ERROR: unexpected stage, %d", false, 1553 vmx_get_test_stage()); 1554 print_vmexit_info(); 1555 return VMX_TEST_VMEXIT; 1556 } 1557 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1558 return VMX_TEST_RESUME; 1559 default: 1560 report("Unknown exit reason, %ld", false, reason); 1561 print_vmexit_info(); 1562 } 1563 return VMX_TEST_VMEXIT; 1564 } 1565 1566 #define TIMER_VECTOR 222 1567 1568 static volatile bool timer_fired; 1569 1570 static void timer_isr(isr_regs_t *regs) 1571 { 1572 timer_fired = true; 1573 apic_write(APIC_EOI, 0); 1574 } 1575 1576 static int interrupt_init(struct vmcs *vmcs) 1577 { 1578 msr_bmp_init(); 1579 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1580 handle_irq(TIMER_VECTOR, timer_isr); 1581 return VMX_TEST_START; 1582 } 1583 1584 static void interrupt_main(void) 1585 { 1586 long long start, loops; 1587 1588 vmx_set_test_stage(0); 1589 1590 apic_write(APIC_LVTT, TIMER_VECTOR); 1591 irq_enable(); 1592 1593 apic_write(APIC_TMICT, 1); 1594 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1595 asm volatile ("nop"); 1596 report("direct interrupt while running guest", timer_fired); 1597 1598 apic_write(APIC_TMICT, 0); 1599 irq_disable(); 1600 vmcall(); 1601 timer_fired = false; 1602 apic_write(APIC_TMICT, 1); 1603 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1604 asm volatile ("nop"); 1605 report("intercepted interrupt while running guest", timer_fired); 1606 1607 irq_enable(); 1608 apic_write(APIC_TMICT, 0); 1609 irq_disable(); 1610 vmcall(); 1611 timer_fired = false; 1612 start = rdtsc(); 1613 apic_write(APIC_TMICT, 1000000); 1614 1615 asm volatile ("sti; hlt"); 1616 1617 report("direct interrupt + hlt", 1618 rdtsc() - start > 1000000 && timer_fired); 1619 1620 apic_write(APIC_TMICT, 0); 1621 irq_disable(); 1622 vmcall(); 1623 timer_fired = false; 1624 start = rdtsc(); 1625 apic_write(APIC_TMICT, 1000000); 1626 1627 asm volatile ("sti; hlt"); 1628 1629 report("intercepted interrupt + hlt", 1630 rdtsc() - start > 10000 && timer_fired); 1631 1632 apic_write(APIC_TMICT, 0); 1633 irq_disable(); 1634 vmcall(); 1635 timer_fired = false; 1636 start = rdtsc(); 1637 apic_write(APIC_TMICT, 1000000); 1638 1639 irq_enable(); 1640 asm volatile ("nop"); 1641 vmcall(); 1642 1643 report("direct interrupt + activity state hlt", 1644 rdtsc() - start > 10000 && timer_fired); 1645 1646 apic_write(APIC_TMICT, 0); 1647 irq_disable(); 1648 vmcall(); 1649 timer_fired = false; 1650 start = rdtsc(); 1651 apic_write(APIC_TMICT, 1000000); 1652 1653 irq_enable(); 1654 asm volatile ("nop"); 1655 vmcall(); 1656 1657 report("intercepted interrupt + activity state hlt", 1658 rdtsc() - start > 10000 && timer_fired); 1659 1660 apic_write(APIC_TMICT, 0); 1661 irq_disable(); 1662 vmx_set_test_stage(7); 1663 vmcall(); 1664 timer_fired = false; 1665 apic_write(APIC_TMICT, 1); 1666 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1667 asm volatile ("nop"); 1668 report("running a guest with interrupt acknowledgement set", timer_fired); 1669 1670 apic_write(APIC_TMICT, 0); 1671 irq_enable(); 1672 timer_fired = false; 1673 vmcall(); 1674 report("Inject an event to a halted guest", timer_fired); 1675 } 1676 1677 static int interrupt_exit_handler(void) 1678 { 1679 u64 guest_rip = vmcs_read(GUEST_RIP); 1680 ulong reason = vmcs_read(EXI_REASON) & 0xff; 1681 u32 insn_len = vmcs_read(EXI_INST_LEN); 1682 1683 switch (reason) { 1684 case VMX_VMCALL: 1685 switch (vmx_get_test_stage()) { 1686 case 0: 1687 case 2: 1688 case 5: 1689 vmcs_write(PIN_CONTROLS, 1690 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1691 break; 1692 case 7: 1693 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_INTA); 1694 vmcs_write(PIN_CONTROLS, 1695 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1696 break; 1697 case 1: 1698 case 3: 1699 vmcs_write(PIN_CONTROLS, 1700 vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1701 break; 1702 case 4: 1703 case 6: 1704 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1705 break; 1706 1707 case 8: 1708 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1709 vmcs_write(ENT_INTR_INFO, 1710 TIMER_VECTOR | 1711 (VMX_INTR_TYPE_EXT_INTR << INTR_INFO_INTR_TYPE_SHIFT) | 1712 INTR_INFO_VALID_MASK); 1713 break; 1714 } 1715 vmx_inc_test_stage(); 1716 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1717 return VMX_TEST_RESUME; 1718 case VMX_EXTINT: 1719 if (vmcs_read(EXI_CONTROLS) & EXI_INTA) { 1720 int vector = vmcs_read(EXI_INTR_INFO) & 0xff; 1721 handle_external_interrupt(vector); 1722 } else { 1723 irq_enable(); 1724 asm volatile ("nop"); 1725 irq_disable(); 1726 } 1727 if (vmx_get_test_stage() >= 2) 1728 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 1729 return VMX_TEST_RESUME; 1730 default: 1731 report("Unknown exit reason, %ld", false, reason); 1732 print_vmexit_info(); 1733 } 1734 1735 return VMX_TEST_VMEXIT; 1736 } 1737 1738 static int dbgctls_init(struct vmcs *vmcs) 1739 { 1740 u64 dr7 = 0x402; 1741 u64 zero = 0; 1742 1743 msr_bmp_init(); 1744 asm volatile( 1745 "mov %0,%%dr0\n\t" 1746 "mov %0,%%dr1\n\t" 1747 "mov %0,%%dr2\n\t" 1748 "mov %1,%%dr7\n\t" 1749 : : "r" (zero), "r" (dr7)); 1750 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1751 vmcs_write(GUEST_DR7, 0x404); 1752 vmcs_write(GUEST_DEBUGCTL, 0x2); 1753 1754 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 1755 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_SAVE_DBGCTLS); 1756 1757 return VMX_TEST_START; 1758 } 1759 1760 static void dbgctls_main(void) 1761 { 1762 u64 dr7, debugctl; 1763 1764 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1765 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1766 /* Commented out: KVM does not support DEBUGCTL so far */ 1767 (void)debugctl; 1768 report("Load debug controls", dr7 == 0x404 /* && debugctl == 0x2 */); 1769 1770 dr7 = 0x408; 1771 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1772 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1773 1774 vmx_set_test_stage(0); 1775 vmcall(); 1776 report("Save debug controls", vmx_get_test_stage() == 1); 1777 1778 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS || 1779 ctrl_exit_rev.set & EXI_SAVE_DBGCTLS) { 1780 printf("\tDebug controls are always loaded/saved\n"); 1781 return; 1782 } 1783 vmx_set_test_stage(2); 1784 vmcall(); 1785 1786 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1787 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1788 /* Commented out: KVM does not support DEBUGCTL so far */ 1789 (void)debugctl; 1790 report("Guest=host debug controls", dr7 == 0x402 /* && debugctl == 0x1 */); 1791 1792 dr7 = 0x408; 1793 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1794 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1795 1796 vmx_set_test_stage(3); 1797 vmcall(); 1798 report("Don't save debug controls", vmx_get_test_stage() == 4); 1799 } 1800 1801 static int dbgctls_exit_handler(void) 1802 { 1803 unsigned int reason = vmcs_read(EXI_REASON) & 0xff; 1804 u32 insn_len = vmcs_read(EXI_INST_LEN); 1805 u64 guest_rip = vmcs_read(GUEST_RIP); 1806 u64 dr7, debugctl; 1807 1808 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1809 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1810 1811 switch (reason) { 1812 case VMX_VMCALL: 1813 switch (vmx_get_test_stage()) { 1814 case 0: 1815 if (dr7 == 0x400 && debugctl == 0 && 1816 vmcs_read(GUEST_DR7) == 0x408 /* && 1817 Commented out: KVM does not support DEBUGCTL so far 1818 vmcs_read(GUEST_DEBUGCTL) == 0x3 */) 1819 vmx_inc_test_stage(); 1820 break; 1821 case 2: 1822 dr7 = 0x402; 1823 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1824 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1825 vmcs_write(GUEST_DR7, 0x404); 1826 vmcs_write(GUEST_DEBUGCTL, 0x2); 1827 1828 vmcs_write(ENT_CONTROLS, 1829 vmcs_read(ENT_CONTROLS) & ~ENT_LOAD_DBGCTLS); 1830 vmcs_write(EXI_CONTROLS, 1831 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_DBGCTLS); 1832 break; 1833 case 3: 1834 if (dr7 == 0x400 && debugctl == 0 && 1835 vmcs_read(GUEST_DR7) == 0x404 /* && 1836 Commented out: KVM does not support DEBUGCTL so far 1837 vmcs_read(GUEST_DEBUGCTL) == 0x2 */) 1838 vmx_inc_test_stage(); 1839 break; 1840 } 1841 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1842 return VMX_TEST_RESUME; 1843 default: 1844 report("Unknown exit reason, %d", false, reason); 1845 print_vmexit_info(); 1846 } 1847 return VMX_TEST_VMEXIT; 1848 } 1849 1850 struct vmx_msr_entry { 1851 u32 index; 1852 u32 reserved; 1853 u64 value; 1854 } __attribute__((packed)); 1855 1856 #define MSR_MAGIC 0x31415926 1857 struct vmx_msr_entry *exit_msr_store, *entry_msr_load, *exit_msr_load; 1858 1859 static int msr_switch_init(struct vmcs *vmcs) 1860 { 1861 msr_bmp_init(); 1862 exit_msr_store = alloc_page(); 1863 exit_msr_load = alloc_page(); 1864 entry_msr_load = alloc_page(); 1865 memset(exit_msr_store, 0, PAGE_SIZE); 1866 memset(exit_msr_load, 0, PAGE_SIZE); 1867 memset(entry_msr_load, 0, PAGE_SIZE); 1868 entry_msr_load[0].index = MSR_KERNEL_GS_BASE; 1869 entry_msr_load[0].value = MSR_MAGIC; 1870 1871 vmx_set_test_stage(1); 1872 vmcs_write(ENT_MSR_LD_CNT, 1); 1873 vmcs_write(ENTER_MSR_LD_ADDR, (u64)entry_msr_load); 1874 vmcs_write(EXI_MSR_ST_CNT, 1); 1875 vmcs_write(EXIT_MSR_ST_ADDR, (u64)exit_msr_store); 1876 vmcs_write(EXI_MSR_LD_CNT, 1); 1877 vmcs_write(EXIT_MSR_LD_ADDR, (u64)exit_msr_load); 1878 return VMX_TEST_START; 1879 } 1880 1881 static void msr_switch_main(void) 1882 { 1883 if (vmx_get_test_stage() == 1) { 1884 report("VM entry MSR load", 1885 rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC); 1886 vmx_set_test_stage(2); 1887 wrmsr(MSR_KERNEL_GS_BASE, MSR_MAGIC + 1); 1888 exit_msr_store[0].index = MSR_KERNEL_GS_BASE; 1889 exit_msr_load[0].index = MSR_KERNEL_GS_BASE; 1890 exit_msr_load[0].value = MSR_MAGIC + 2; 1891 } 1892 vmcall(); 1893 } 1894 1895 static int msr_switch_exit_handler(void) 1896 { 1897 ulong reason; 1898 1899 reason = vmcs_read(EXI_REASON); 1900 if (reason == VMX_VMCALL && vmx_get_test_stage() == 2) { 1901 report("VM exit MSR store", 1902 exit_msr_store[0].value == MSR_MAGIC + 1); 1903 report("VM exit MSR load", 1904 rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC + 2); 1905 vmx_set_test_stage(3); 1906 entry_msr_load[0].index = MSR_FS_BASE; 1907 return VMX_TEST_RESUME; 1908 } 1909 printf("ERROR %s: unexpected stage=%u or reason=%lu\n", 1910 __func__, vmx_get_test_stage(), reason); 1911 return VMX_TEST_EXIT; 1912 } 1913 1914 static int msr_switch_entry_failure(struct vmentry_failure *failure) 1915 { 1916 ulong reason; 1917 1918 if (failure->early) { 1919 printf("ERROR %s: early exit\n", __func__); 1920 return VMX_TEST_EXIT; 1921 } 1922 1923 reason = vmcs_read(EXI_REASON); 1924 if (reason == (VMX_ENTRY_FAILURE | VMX_FAIL_MSR) && 1925 vmx_get_test_stage() == 3) { 1926 report("VM entry MSR load: try to load FS_BASE", 1927 vmcs_read(EXI_QUALIFICATION) == 1); 1928 return VMX_TEST_VMEXIT; 1929 } 1930 printf("ERROR %s: unexpected stage=%u or reason=%lu\n", 1931 __func__, vmx_get_test_stage(), reason); 1932 return VMX_TEST_EXIT; 1933 } 1934 1935 static int vmmcall_init(struct vmcs *vmcs) 1936 { 1937 vmcs_write(EXC_BITMAP, 1 << UD_VECTOR); 1938 return VMX_TEST_START; 1939 } 1940 1941 static void vmmcall_main(void) 1942 { 1943 asm volatile( 1944 "mov $0xABCD, %%rax\n\t" 1945 "vmmcall\n\t" 1946 ::: "rax"); 1947 1948 report("VMMCALL", 0); 1949 } 1950 1951 static int vmmcall_exit_handler(void) 1952 { 1953 ulong reason; 1954 1955 reason = vmcs_read(EXI_REASON); 1956 switch (reason) { 1957 case VMX_VMCALL: 1958 printf("here\n"); 1959 report("VMMCALL triggers #UD", 0); 1960 break; 1961 case VMX_EXC_NMI: 1962 report("VMMCALL triggers #UD", 1963 (vmcs_read(EXI_INTR_INFO) & 0xff) == UD_VECTOR); 1964 break; 1965 default: 1966 report("Unknown exit reason, %ld", false, reason); 1967 print_vmexit_info(); 1968 } 1969 1970 return VMX_TEST_VMEXIT; 1971 } 1972 1973 static int disable_rdtscp_init(struct vmcs *vmcs) 1974 { 1975 u32 ctrl_cpu1; 1976 1977 if (ctrl_cpu_rev[0].clr & CPU_SECONDARY) { 1978 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 1979 ctrl_cpu1 &= ~CPU_RDTSCP; 1980 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 1981 } 1982 1983 return VMX_TEST_START; 1984 } 1985 1986 static void disable_rdtscp_ud_handler(struct ex_regs *regs) 1987 { 1988 switch (vmx_get_test_stage()) { 1989 case 0: 1990 report("RDTSCP triggers #UD", true); 1991 vmx_inc_test_stage(); 1992 regs->rip += 3; 1993 break; 1994 case 2: 1995 report("RDPID triggers #UD", true); 1996 vmx_inc_test_stage(); 1997 regs->rip += 4; 1998 break; 1999 } 2000 return; 2001 2002 } 2003 2004 static void disable_rdtscp_main(void) 2005 { 2006 /* Test that #UD is properly injected in L2. */ 2007 handle_exception(UD_VECTOR, disable_rdtscp_ud_handler); 2008 2009 vmx_set_test_stage(0); 2010 asm volatile("rdtscp" : : : "eax", "ecx", "edx"); 2011 vmcall(); 2012 asm volatile(".byte 0xf3, 0x0f, 0xc7, 0xf8" : : : "eax"); 2013 2014 handle_exception(UD_VECTOR, 0); 2015 vmcall(); 2016 } 2017 2018 static int disable_rdtscp_exit_handler(void) 2019 { 2020 unsigned int reason = vmcs_read(EXI_REASON) & 0xff; 2021 2022 switch (reason) { 2023 case VMX_VMCALL: 2024 switch (vmx_get_test_stage()) { 2025 case 0: 2026 report("RDTSCP triggers #UD", false); 2027 vmx_inc_test_stage(); 2028 /* fallthrough */ 2029 case 1: 2030 vmx_inc_test_stage(); 2031 vmcs_write(GUEST_RIP, vmcs_read(GUEST_RIP) + 3); 2032 return VMX_TEST_RESUME; 2033 case 2: 2034 report("RDPID triggers #UD", false); 2035 break; 2036 } 2037 break; 2038 2039 default: 2040 report("Unknown exit reason, %d", false, reason); 2041 print_vmexit_info(); 2042 } 2043 return VMX_TEST_VMEXIT; 2044 } 2045 2046 static int int3_init(struct vmcs *vmcs) 2047 { 2048 vmcs_write(EXC_BITMAP, ~0u); 2049 return VMX_TEST_START; 2050 } 2051 2052 static void int3_guest_main(void) 2053 { 2054 asm volatile ("int3"); 2055 } 2056 2057 static int int3_exit_handler(void) 2058 { 2059 u32 reason = vmcs_read(EXI_REASON); 2060 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2061 2062 report("L1 intercepts #BP", reason == VMX_EXC_NMI && 2063 (intr_info & INTR_INFO_VALID_MASK) && 2064 (intr_info & INTR_INFO_VECTOR_MASK) == BP_VECTOR && 2065 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2066 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION); 2067 2068 return VMX_TEST_VMEXIT; 2069 } 2070 2071 static int into_init(struct vmcs *vmcs) 2072 { 2073 vmcs_write(EXC_BITMAP, ~0u); 2074 return VMX_TEST_START; 2075 } 2076 2077 static void into_guest_main(void) 2078 { 2079 struct far_pointer32 fp = { 2080 .offset = (uintptr_t)&&into, 2081 .selector = KERNEL_CS32, 2082 }; 2083 register uintptr_t rsp asm("rsp"); 2084 2085 if (fp.offset != (uintptr_t)&&into) { 2086 printf("Code address too high.\n"); 2087 return; 2088 } 2089 if ((u32)rsp != rsp) { 2090 printf("Stack address too high.\n"); 2091 return; 2092 } 2093 2094 asm goto ("lcall *%0" : : "m" (fp) : "rax" : into); 2095 return; 2096 into: 2097 asm volatile (".code32;" 2098 "movl $0x7fffffff, %eax;" 2099 "addl %eax, %eax;" 2100 "into;" 2101 "lret;" 2102 ".code64"); 2103 __builtin_unreachable(); 2104 } 2105 2106 static int into_exit_handler(void) 2107 { 2108 u32 reason = vmcs_read(EXI_REASON); 2109 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2110 2111 report("L1 intercepts #OF", reason == VMX_EXC_NMI && 2112 (intr_info & INTR_INFO_VALID_MASK) && 2113 (intr_info & INTR_INFO_VECTOR_MASK) == OF_VECTOR && 2114 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2115 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION); 2116 2117 return VMX_TEST_VMEXIT; 2118 } 2119 2120 static void exit_monitor_from_l2_main(void) 2121 { 2122 printf("Calling exit(0) from l2...\n"); 2123 exit(0); 2124 } 2125 2126 static int exit_monitor_from_l2_handler(void) 2127 { 2128 report("The guest should have killed the VMM", false); 2129 return VMX_TEST_EXIT; 2130 } 2131 2132 static void assert_exit_reason(u64 expected) 2133 { 2134 u64 actual = vmcs_read(EXI_REASON); 2135 2136 TEST_ASSERT_EQ_MSG(expected, actual, "Expected %s, got %s.", 2137 exit_reason_description(expected), 2138 exit_reason_description(actual)); 2139 } 2140 2141 static void skip_exit_insn(void) 2142 { 2143 u64 guest_rip = vmcs_read(GUEST_RIP); 2144 u32 insn_len = vmcs_read(EXI_INST_LEN); 2145 vmcs_write(GUEST_RIP, guest_rip + insn_len); 2146 } 2147 2148 static void skip_exit_vmcall(void) 2149 { 2150 assert_exit_reason(VMX_VMCALL); 2151 skip_exit_insn(); 2152 } 2153 2154 static void v2_null_test_guest(void) 2155 { 2156 } 2157 2158 static void v2_null_test(void) 2159 { 2160 test_set_guest(v2_null_test_guest); 2161 enter_guest(); 2162 report(__func__, 1); 2163 } 2164 2165 static void v2_multiple_entries_test_guest(void) 2166 { 2167 vmx_set_test_stage(1); 2168 vmcall(); 2169 vmx_set_test_stage(2); 2170 } 2171 2172 static void v2_multiple_entries_test(void) 2173 { 2174 test_set_guest(v2_multiple_entries_test_guest); 2175 enter_guest(); 2176 TEST_ASSERT_EQ(vmx_get_test_stage(), 1); 2177 skip_exit_vmcall(); 2178 enter_guest(); 2179 TEST_ASSERT_EQ(vmx_get_test_stage(), 2); 2180 report(__func__, 1); 2181 } 2182 2183 static int fixture_test_data = 1; 2184 2185 static void fixture_test_teardown(void *data) 2186 { 2187 *((int *) data) = 1; 2188 } 2189 2190 static void fixture_test_guest(void) 2191 { 2192 fixture_test_data++; 2193 } 2194 2195 2196 static void fixture_test_setup(void) 2197 { 2198 TEST_ASSERT_EQ_MSG(1, fixture_test_data, 2199 "fixture_test_teardown didn't run?!"); 2200 fixture_test_data = 2; 2201 test_add_teardown(fixture_test_teardown, &fixture_test_data); 2202 test_set_guest(fixture_test_guest); 2203 } 2204 2205 static void fixture_test_case1(void) 2206 { 2207 fixture_test_setup(); 2208 TEST_ASSERT_EQ(2, fixture_test_data); 2209 enter_guest(); 2210 TEST_ASSERT_EQ(3, fixture_test_data); 2211 report(__func__, 1); 2212 } 2213 2214 static void fixture_test_case2(void) 2215 { 2216 fixture_test_setup(); 2217 TEST_ASSERT_EQ(2, fixture_test_data); 2218 enter_guest(); 2219 TEST_ASSERT_EQ(3, fixture_test_data); 2220 report(__func__, 1); 2221 } 2222 2223 enum ept_access_op { 2224 OP_READ, 2225 OP_WRITE, 2226 OP_EXEC, 2227 OP_FLUSH_TLB, 2228 OP_EXIT, 2229 }; 2230 2231 static struct ept_access_test_data { 2232 unsigned long gpa; 2233 unsigned long *gva; 2234 unsigned long hpa; 2235 unsigned long *hva; 2236 enum ept_access_op op; 2237 } ept_access_test_data; 2238 2239 extern unsigned char ret42_start; 2240 extern unsigned char ret42_end; 2241 2242 /* Returns 42. */ 2243 asm( 2244 ".align 64\n" 2245 "ret42_start:\n" 2246 "mov $42, %eax\n" 2247 "ret\n" 2248 "ret42_end:\n" 2249 ); 2250 2251 static void 2252 diagnose_ept_violation_qual(u64 expected, u64 actual) 2253 { 2254 2255 #define DIAGNOSE(flag) \ 2256 do { \ 2257 if ((expected & flag) != (actual & flag)) \ 2258 printf(#flag " %sexpected\n", \ 2259 (expected & flag) ? "" : "un"); \ 2260 } while (0) 2261 2262 DIAGNOSE(EPT_VLT_RD); 2263 DIAGNOSE(EPT_VLT_WR); 2264 DIAGNOSE(EPT_VLT_FETCH); 2265 DIAGNOSE(EPT_VLT_PERM_RD); 2266 DIAGNOSE(EPT_VLT_PERM_WR); 2267 DIAGNOSE(EPT_VLT_PERM_EX); 2268 DIAGNOSE(EPT_VLT_LADDR_VLD); 2269 DIAGNOSE(EPT_VLT_PADDR); 2270 2271 #undef DIAGNOSE 2272 } 2273 2274 static void do_ept_access_op(enum ept_access_op op) 2275 { 2276 ept_access_test_data.op = op; 2277 enter_guest(); 2278 } 2279 2280 /* 2281 * Force the guest to flush its TLB (i.e., flush gva -> gpa mappings). Only 2282 * needed by tests that modify guest PTEs. 2283 */ 2284 static void ept_access_test_guest_flush_tlb(void) 2285 { 2286 do_ept_access_op(OP_FLUSH_TLB); 2287 skip_exit_vmcall(); 2288 } 2289 2290 /* 2291 * Modifies the EPT entry at @level in the mapping of @gpa. First clears the 2292 * bits in @clear then sets the bits in @set. @mkhuge transforms the entry into 2293 * a huge page. 2294 */ 2295 static unsigned long ept_twiddle(unsigned long gpa, bool mkhuge, int level, 2296 unsigned long clear, unsigned long set) 2297 { 2298 struct ept_access_test_data *data = &ept_access_test_data; 2299 unsigned long orig_pte; 2300 unsigned long pte; 2301 2302 /* Screw with the mapping at the requested level. */ 2303 TEST_ASSERT(get_ept_pte(pml4, gpa, level, &orig_pte)); 2304 pte = orig_pte; 2305 if (mkhuge) 2306 pte = (orig_pte & ~EPT_ADDR_MASK) | data->hpa | EPT_LARGE_PAGE; 2307 else 2308 pte = orig_pte; 2309 pte = (pte & ~clear) | set; 2310 set_ept_pte(pml4, gpa, level, pte); 2311 ept_sync(INVEPT_SINGLE, eptp); 2312 2313 return orig_pte; 2314 } 2315 2316 static void ept_untwiddle(unsigned long gpa, int level, unsigned long orig_pte) 2317 { 2318 set_ept_pte(pml4, gpa, level, orig_pte); 2319 } 2320 2321 static void do_ept_violation(bool leaf, enum ept_access_op op, 2322 u64 expected_qual, u64 expected_paddr) 2323 { 2324 u64 qual; 2325 2326 /* Try the access and observe the violation. */ 2327 do_ept_access_op(op); 2328 2329 assert_exit_reason(VMX_EPT_VIOLATION); 2330 2331 qual = vmcs_read(EXI_QUALIFICATION); 2332 2333 diagnose_ept_violation_qual(expected_qual, qual); 2334 TEST_EXPECT_EQ(expected_qual, qual); 2335 2336 #if 0 2337 /* Disable for now otherwise every test will fail */ 2338 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2339 (unsigned long) ( 2340 op == OP_EXEC ? data->gva + 1 : data->gva)); 2341 #endif 2342 /* 2343 * TODO: tests that probe expected_paddr in pages other than the one at 2344 * the beginning of the 1g region. 2345 */ 2346 TEST_EXPECT_EQ(vmcs_read(INFO_PHYS_ADDR), expected_paddr); 2347 } 2348 2349 static void 2350 ept_violation_at_level_mkhuge(bool mkhuge, int level, unsigned long clear, 2351 unsigned long set, enum ept_access_op op, 2352 u64 expected_qual) 2353 { 2354 struct ept_access_test_data *data = &ept_access_test_data; 2355 unsigned long orig_pte; 2356 2357 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2358 2359 do_ept_violation(level == 1 || mkhuge, op, expected_qual, 2360 op == OP_EXEC ? data->gpa + sizeof(unsigned long) : 2361 data->gpa); 2362 2363 /* Fix the violation and resume the op loop. */ 2364 ept_untwiddle(data->gpa, level, orig_pte); 2365 enter_guest(); 2366 skip_exit_vmcall(); 2367 } 2368 2369 static void 2370 ept_violation_at_level(int level, unsigned long clear, unsigned long set, 2371 enum ept_access_op op, u64 expected_qual) 2372 { 2373 ept_violation_at_level_mkhuge(false, level, clear, set, op, 2374 expected_qual); 2375 if (ept_huge_pages_supported(level)) 2376 ept_violation_at_level_mkhuge(true, level, clear, set, op, 2377 expected_qual); 2378 } 2379 2380 static void ept_violation(unsigned long clear, unsigned long set, 2381 enum ept_access_op op, u64 expected_qual) 2382 { 2383 ept_violation_at_level(1, clear, set, op, expected_qual); 2384 ept_violation_at_level(2, clear, set, op, expected_qual); 2385 ept_violation_at_level(3, clear, set, op, expected_qual); 2386 ept_violation_at_level(4, clear, set, op, expected_qual); 2387 } 2388 2389 static void ept_access_violation(unsigned long access, enum ept_access_op op, 2390 u64 expected_qual) 2391 { 2392 ept_violation(EPT_PRESENT, access, op, 2393 expected_qual | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2394 } 2395 2396 /* 2397 * For translations that don't involve a GVA, that is physical address (paddr) 2398 * accesses, EPT violations don't set the flag EPT_VLT_PADDR. For a typical 2399 * guest memory access, the hardware does GVA -> GPA -> HPA. However, certain 2400 * translations don't involve GVAs, such as when the hardware does the guest 2401 * page table walk. For example, in translating GVA_1 -> GPA_1, the guest MMU 2402 * might try to set an A bit on a guest PTE. If the GPA_2 that the PTE resides 2403 * on isn't present in the EPT, then the EPT violation will be for GPA_2 and 2404 * the EPT_VLT_PADDR bit will be clear in the exit qualification. 2405 * 2406 * Note that paddr violations can also be triggered by loading PAE page tables 2407 * with wonky addresses. We don't test that yet. 2408 * 2409 * This function modifies the EPT entry that maps the GPA that the guest page 2410 * table entry mapping ept_access_data.gva resides on. 2411 * 2412 * @ept_access EPT permissions to set. Other permissions are cleared. 2413 * 2414 * @pte_ad Set the A/D bits on the guest PTE accordingly. 2415 * 2416 * @op Guest operation to perform with ept_access_data.gva. 2417 * 2418 * @expect_violation 2419 * Is a violation expected during the paddr access? 2420 * 2421 * @expected_qual Expected qualification for the EPT violation. 2422 * EPT_VLT_PADDR should be clear. 2423 */ 2424 static void ept_access_paddr(unsigned long ept_access, unsigned long pte_ad, 2425 enum ept_access_op op, bool expect_violation, 2426 u64 expected_qual) 2427 { 2428 struct ept_access_test_data *data = &ept_access_test_data; 2429 unsigned long *ptep; 2430 unsigned long gpa; 2431 unsigned long orig_epte; 2432 2433 /* Modify the guest PTE mapping data->gva according to @pte_ad. */ 2434 ptep = get_pte_level(current_page_table(), data->gva, /*level=*/1); 2435 TEST_ASSERT(ptep); 2436 TEST_ASSERT_EQ(*ptep & PT_ADDR_MASK, data->gpa); 2437 *ptep = (*ptep & ~PT_AD_MASK) | pte_ad; 2438 ept_access_test_guest_flush_tlb(); 2439 2440 /* 2441 * Now modify the access bits on the EPT entry for the GPA that the 2442 * guest PTE resides on. Note that by modifying a single EPT entry, 2443 * we're potentially affecting 512 guest PTEs. However, we've carefully 2444 * constructed our test such that those other 511 PTEs aren't used by 2445 * the guest: data->gva is at the beginning of a 1G huge page, thus the 2446 * PTE we're modifying is at the beginning of a 4K page and the 2447 * following 511 entires are also under our control (and not touched by 2448 * the guest). 2449 */ 2450 gpa = virt_to_phys(ptep); 2451 TEST_ASSERT_EQ(gpa & ~PAGE_MASK, 0); 2452 /* 2453 * Make sure the guest page table page is mapped with a 4K EPT entry, 2454 * otherwise our level=1 twiddling below will fail. We use the 2455 * identity map (gpa = gpa) since page tables are shared with the host. 2456 */ 2457 install_ept(pml4, gpa, gpa, EPT_PRESENT); 2458 orig_epte = ept_twiddle(gpa, /*mkhuge=*/0, /*level=*/1, 2459 /*clear=*/EPT_PRESENT, /*set=*/ept_access); 2460 2461 if (expect_violation) { 2462 do_ept_violation(/*leaf=*/true, op, 2463 expected_qual | EPT_VLT_LADDR_VLD, gpa); 2464 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2465 do_ept_access_op(op); 2466 } else { 2467 do_ept_access_op(op); 2468 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2469 } 2470 2471 TEST_ASSERT(*ptep & PT_ACCESSED_MASK); 2472 if ((pte_ad & PT_DIRTY_MASK) || op == OP_WRITE) 2473 TEST_ASSERT(*ptep & PT_DIRTY_MASK); 2474 2475 skip_exit_vmcall(); 2476 } 2477 2478 static void ept_access_allowed_paddr(unsigned long ept_access, 2479 unsigned long pte_ad, 2480 enum ept_access_op op) 2481 { 2482 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/false, 2483 /*expected_qual=*/-1); 2484 } 2485 2486 static void ept_access_violation_paddr(unsigned long ept_access, 2487 unsigned long pte_ad, 2488 enum ept_access_op op, 2489 u64 expected_qual) 2490 { 2491 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/true, 2492 expected_qual); 2493 } 2494 2495 2496 static void ept_allowed_at_level_mkhuge(bool mkhuge, int level, 2497 unsigned long clear, 2498 unsigned long set, 2499 enum ept_access_op op) 2500 { 2501 struct ept_access_test_data *data = &ept_access_test_data; 2502 unsigned long orig_pte; 2503 2504 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2505 2506 /* No violation. Should proceed to vmcall. */ 2507 do_ept_access_op(op); 2508 skip_exit_vmcall(); 2509 2510 ept_untwiddle(data->gpa, level, orig_pte); 2511 } 2512 2513 static void ept_allowed_at_level(int level, unsigned long clear, 2514 unsigned long set, enum ept_access_op op) 2515 { 2516 ept_allowed_at_level_mkhuge(false, level, clear, set, op); 2517 if (ept_huge_pages_supported(level)) 2518 ept_allowed_at_level_mkhuge(true, level, clear, set, op); 2519 } 2520 2521 static void ept_allowed(unsigned long clear, unsigned long set, 2522 enum ept_access_op op) 2523 { 2524 ept_allowed_at_level(1, clear, set, op); 2525 ept_allowed_at_level(2, clear, set, op); 2526 ept_allowed_at_level(3, clear, set, op); 2527 ept_allowed_at_level(4, clear, set, op); 2528 } 2529 2530 static void ept_ignored_bit(int bit) 2531 { 2532 /* Set the bit. */ 2533 ept_allowed(0, 1ul << bit, OP_READ); 2534 ept_allowed(0, 1ul << bit, OP_WRITE); 2535 ept_allowed(0, 1ul << bit, OP_EXEC); 2536 2537 /* Clear the bit. */ 2538 ept_allowed(1ul << bit, 0, OP_READ); 2539 ept_allowed(1ul << bit, 0, OP_WRITE); 2540 ept_allowed(1ul << bit, 0, OP_EXEC); 2541 } 2542 2543 static void ept_access_allowed(unsigned long access, enum ept_access_op op) 2544 { 2545 ept_allowed(EPT_PRESENT, access, op); 2546 } 2547 2548 2549 static void ept_misconfig_at_level_mkhuge_op(bool mkhuge, int level, 2550 unsigned long clear, 2551 unsigned long set, 2552 enum ept_access_op op) 2553 { 2554 struct ept_access_test_data *data = &ept_access_test_data; 2555 unsigned long orig_pte; 2556 2557 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2558 2559 do_ept_access_op(op); 2560 assert_exit_reason(VMX_EPT_MISCONFIG); 2561 2562 /* Intel 27.2.1, "For all other VM exits, this field is cleared." */ 2563 #if 0 2564 /* broken: */ 2565 TEST_EXPECT_EQ_MSG(vmcs_read(EXI_QUALIFICATION), 0); 2566 #endif 2567 #if 0 2568 /* 2569 * broken: 2570 * According to description of exit qual for EPT violation, 2571 * EPT_VLT_LADDR_VLD indicates if GUEST_LINEAR_ADDRESS is valid. 2572 * However, I can't find anything that says GUEST_LINEAR_ADDRESS ought 2573 * to be set for msiconfig. 2574 */ 2575 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2576 (unsigned long) ( 2577 op == OP_EXEC ? data->gva + 1 : data->gva)); 2578 #endif 2579 2580 /* Fix the violation and resume the op loop. */ 2581 ept_untwiddle(data->gpa, level, orig_pte); 2582 enter_guest(); 2583 skip_exit_vmcall(); 2584 } 2585 2586 static void ept_misconfig_at_level_mkhuge(bool mkhuge, int level, 2587 unsigned long clear, 2588 unsigned long set) 2589 { 2590 /* The op shouldn't matter (read, write, exec), so try them all! */ 2591 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_READ); 2592 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_WRITE); 2593 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_EXEC); 2594 } 2595 2596 static void ept_misconfig_at_level(int level, unsigned long clear, 2597 unsigned long set) 2598 { 2599 ept_misconfig_at_level_mkhuge(false, level, clear, set); 2600 if (ept_huge_pages_supported(level)) 2601 ept_misconfig_at_level_mkhuge(true, level, clear, set); 2602 } 2603 2604 static void ept_misconfig(unsigned long clear, unsigned long set) 2605 { 2606 ept_misconfig_at_level(1, clear, set); 2607 ept_misconfig_at_level(2, clear, set); 2608 ept_misconfig_at_level(3, clear, set); 2609 ept_misconfig_at_level(4, clear, set); 2610 } 2611 2612 static void ept_access_misconfig(unsigned long access) 2613 { 2614 ept_misconfig(EPT_PRESENT, access); 2615 } 2616 2617 static void ept_reserved_bit_at_level_nohuge(int level, int bit) 2618 { 2619 /* Setting the bit causes a misconfig. */ 2620 ept_misconfig_at_level_mkhuge(false, level, 0, 1ul << bit); 2621 2622 /* Making the entry non-present turns reserved bits into ignored. */ 2623 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2624 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2625 } 2626 2627 static void ept_reserved_bit_at_level_huge(int level, int bit) 2628 { 2629 /* Setting the bit causes a misconfig. */ 2630 ept_misconfig_at_level_mkhuge(true, level, 0, 1ul << bit); 2631 2632 /* Making the entry non-present turns reserved bits into ignored. */ 2633 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2634 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2635 } 2636 2637 static void ept_reserved_bit_at_level(int level, int bit) 2638 { 2639 /* Setting the bit causes a misconfig. */ 2640 ept_misconfig_at_level(level, 0, 1ul << bit); 2641 2642 /* Making the entry non-present turns reserved bits into ignored. */ 2643 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2644 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2645 } 2646 2647 static void ept_reserved_bit(int bit) 2648 { 2649 ept_reserved_bit_at_level(1, bit); 2650 ept_reserved_bit_at_level(2, bit); 2651 ept_reserved_bit_at_level(3, bit); 2652 ept_reserved_bit_at_level(4, bit); 2653 } 2654 2655 #define PAGE_2M_ORDER 9 2656 #define PAGE_1G_ORDER 18 2657 2658 static void *get_1g_page(void) 2659 { 2660 static void *alloc; 2661 2662 if (!alloc) 2663 alloc = alloc_pages(PAGE_1G_ORDER); 2664 return alloc; 2665 } 2666 2667 static void ept_access_test_teardown(void *unused) 2668 { 2669 /* Exit the guest cleanly. */ 2670 do_ept_access_op(OP_EXIT); 2671 } 2672 2673 static void ept_access_test_guest(void) 2674 { 2675 struct ept_access_test_data *data = &ept_access_test_data; 2676 int (*code)(void) = (int (*)(void)) &data->gva[1]; 2677 2678 while (true) { 2679 switch (data->op) { 2680 case OP_READ: 2681 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_1); 2682 break; 2683 case OP_WRITE: 2684 *data->gva = MAGIC_VAL_2; 2685 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_2); 2686 *data->gva = MAGIC_VAL_1; 2687 break; 2688 case OP_EXEC: 2689 TEST_ASSERT_EQ(42, code()); 2690 break; 2691 case OP_FLUSH_TLB: 2692 write_cr3(read_cr3()); 2693 break; 2694 case OP_EXIT: 2695 return; 2696 default: 2697 TEST_ASSERT_MSG(false, "Unknown op %d", data->op); 2698 } 2699 vmcall(); 2700 } 2701 } 2702 2703 static void ept_access_test_setup(void) 2704 { 2705 struct ept_access_test_data *data = &ept_access_test_data; 2706 unsigned long npages = 1ul << PAGE_1G_ORDER; 2707 unsigned long size = npages * PAGE_SIZE; 2708 unsigned long *page_table = current_page_table(); 2709 unsigned long pte; 2710 2711 if (setup_ept(false)) 2712 test_skip("EPT not supported"); 2713 2714 /* We use data->gpa = 1 << 39 so that test data has a separate pml4 entry */ 2715 if (cpuid_maxphyaddr() < 40) 2716 test_skip("Test needs MAXPHYADDR >= 40"); 2717 2718 test_set_guest(ept_access_test_guest); 2719 test_add_teardown(ept_access_test_teardown, NULL); 2720 2721 data->hva = get_1g_page(); 2722 TEST_ASSERT(data->hva); 2723 data->hpa = virt_to_phys(data->hva); 2724 2725 data->gpa = 1ul << 39; 2726 data->gva = (void *) ALIGN((unsigned long) alloc_vpages(npages * 2), 2727 size); 2728 TEST_ASSERT(!any_present_pages(page_table, data->gva, size)); 2729 install_pages(page_table, data->gpa, size, data->gva); 2730 2731 /* 2732 * Make sure nothing's mapped here so the tests that screw with the 2733 * pml4 entry don't inadvertently break something. 2734 */ 2735 TEST_ASSERT(get_ept_pte(pml4, data->gpa, 4, &pte) && pte == 0); 2736 TEST_ASSERT(get_ept_pte(pml4, data->gpa + size - 1, 4, &pte) && pte == 0); 2737 install_ept(pml4, data->hpa, data->gpa, EPT_PRESENT); 2738 2739 data->hva[0] = MAGIC_VAL_1; 2740 memcpy(&data->hva[1], &ret42_start, &ret42_end - &ret42_start); 2741 } 2742 2743 static void ept_access_test_not_present(void) 2744 { 2745 ept_access_test_setup(); 2746 /* --- */ 2747 ept_access_violation(0, OP_READ, EPT_VLT_RD); 2748 ept_access_violation(0, OP_WRITE, EPT_VLT_WR); 2749 ept_access_violation(0, OP_EXEC, EPT_VLT_FETCH); 2750 } 2751 2752 static void ept_access_test_read_only(void) 2753 { 2754 ept_access_test_setup(); 2755 2756 /* r-- */ 2757 ept_access_allowed(EPT_RA, OP_READ); 2758 ept_access_violation(EPT_RA, OP_WRITE, EPT_VLT_WR | EPT_VLT_PERM_RD); 2759 ept_access_violation(EPT_RA, OP_EXEC, EPT_VLT_FETCH | EPT_VLT_PERM_RD); 2760 } 2761 2762 static void ept_access_test_write_only(void) 2763 { 2764 ept_access_test_setup(); 2765 /* -w- */ 2766 ept_access_misconfig(EPT_WA); 2767 } 2768 2769 static void ept_access_test_read_write(void) 2770 { 2771 ept_access_test_setup(); 2772 /* rw- */ 2773 ept_access_allowed(EPT_RA | EPT_WA, OP_READ); 2774 ept_access_allowed(EPT_RA | EPT_WA, OP_WRITE); 2775 ept_access_violation(EPT_RA | EPT_WA, OP_EXEC, 2776 EPT_VLT_FETCH | EPT_VLT_PERM_RD | EPT_VLT_PERM_WR); 2777 } 2778 2779 2780 static void ept_access_test_execute_only(void) 2781 { 2782 ept_access_test_setup(); 2783 /* --x */ 2784 if (ept_execute_only_supported()) { 2785 ept_access_violation(EPT_EA, OP_READ, 2786 EPT_VLT_RD | EPT_VLT_PERM_EX); 2787 ept_access_violation(EPT_EA, OP_WRITE, 2788 EPT_VLT_WR | EPT_VLT_PERM_EX); 2789 ept_access_allowed(EPT_EA, OP_EXEC); 2790 } else { 2791 ept_access_misconfig(EPT_EA); 2792 } 2793 } 2794 2795 static void ept_access_test_read_execute(void) 2796 { 2797 ept_access_test_setup(); 2798 /* r-x */ 2799 ept_access_allowed(EPT_RA | EPT_EA, OP_READ); 2800 ept_access_violation(EPT_RA | EPT_EA, OP_WRITE, 2801 EPT_VLT_WR | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX); 2802 ept_access_allowed(EPT_RA | EPT_EA, OP_EXEC); 2803 } 2804 2805 static void ept_access_test_write_execute(void) 2806 { 2807 ept_access_test_setup(); 2808 /* -wx */ 2809 ept_access_misconfig(EPT_WA | EPT_EA); 2810 } 2811 2812 static void ept_access_test_read_write_execute(void) 2813 { 2814 ept_access_test_setup(); 2815 /* rwx */ 2816 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_READ); 2817 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_WRITE); 2818 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_EXEC); 2819 } 2820 2821 static void ept_access_test_reserved_bits(void) 2822 { 2823 int i; 2824 int maxphyaddr; 2825 2826 ept_access_test_setup(); 2827 2828 /* Reserved bits above maxphyaddr. */ 2829 maxphyaddr = cpuid_maxphyaddr(); 2830 for (i = maxphyaddr; i <= 51; i++) { 2831 report_prefix_pushf("reserved_bit=%d", i); 2832 ept_reserved_bit(i); 2833 report_prefix_pop(); 2834 } 2835 2836 /* Level-specific reserved bits. */ 2837 ept_reserved_bit_at_level_nohuge(2, 3); 2838 ept_reserved_bit_at_level_nohuge(2, 4); 2839 ept_reserved_bit_at_level_nohuge(2, 5); 2840 ept_reserved_bit_at_level_nohuge(2, 6); 2841 /* 2M alignment. */ 2842 for (i = 12; i < 20; i++) { 2843 report_prefix_pushf("reserved_bit=%d", i); 2844 ept_reserved_bit_at_level_huge(2, i); 2845 report_prefix_pop(); 2846 } 2847 ept_reserved_bit_at_level_nohuge(3, 3); 2848 ept_reserved_bit_at_level_nohuge(3, 4); 2849 ept_reserved_bit_at_level_nohuge(3, 5); 2850 ept_reserved_bit_at_level_nohuge(3, 6); 2851 /* 1G alignment. */ 2852 for (i = 12; i < 29; i++) { 2853 report_prefix_pushf("reserved_bit=%d", i); 2854 ept_reserved_bit_at_level_huge(3, i); 2855 report_prefix_pop(); 2856 } 2857 ept_reserved_bit_at_level(4, 3); 2858 ept_reserved_bit_at_level(4, 4); 2859 ept_reserved_bit_at_level(4, 5); 2860 ept_reserved_bit_at_level(4, 6); 2861 ept_reserved_bit_at_level(4, 7); 2862 } 2863 2864 static void ept_access_test_ignored_bits(void) 2865 { 2866 ept_access_test_setup(); 2867 /* 2868 * Bits ignored at every level. Bits 8 and 9 (A and D) are ignored as 2869 * far as translation is concerned even if AD bits are enabled in the 2870 * EPTP. Bit 63 is ignored because "EPT-violation #VE" VM-execution 2871 * control is 0. 2872 */ 2873 ept_ignored_bit(8); 2874 ept_ignored_bit(9); 2875 ept_ignored_bit(10); 2876 ept_ignored_bit(11); 2877 ept_ignored_bit(52); 2878 ept_ignored_bit(53); 2879 ept_ignored_bit(54); 2880 ept_ignored_bit(55); 2881 ept_ignored_bit(56); 2882 ept_ignored_bit(57); 2883 ept_ignored_bit(58); 2884 ept_ignored_bit(59); 2885 ept_ignored_bit(60); 2886 ept_ignored_bit(61); 2887 ept_ignored_bit(62); 2888 ept_ignored_bit(63); 2889 } 2890 2891 static void ept_access_test_paddr_not_present_ad_disabled(void) 2892 { 2893 ept_access_test_setup(); 2894 ept_disable_ad_bits(); 2895 2896 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, EPT_VLT_RD); 2897 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, EPT_VLT_RD); 2898 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, EPT_VLT_RD); 2899 } 2900 2901 static void ept_access_test_paddr_not_present_ad_enabled(void) 2902 { 2903 u64 qual = EPT_VLT_RD | EPT_VLT_WR; 2904 2905 ept_access_test_setup(); 2906 ept_enable_ad_bits_or_skip_test(); 2907 2908 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, qual); 2909 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, qual); 2910 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, qual); 2911 } 2912 2913 static void ept_access_test_paddr_read_only_ad_disabled(void) 2914 { 2915 /* 2916 * When EPT AD bits are disabled, all accesses to guest paging 2917 * structures are reported separately as a read and (after 2918 * translation of the GPA to host physical address) a read+write 2919 * if the A/D bits have to be set. 2920 */ 2921 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 2922 2923 ept_access_test_setup(); 2924 ept_disable_ad_bits(); 2925 2926 /* Can't update A bit, so all accesses fail. */ 2927 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 2928 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 2929 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 2930 /* AD bits disabled, so only writes try to update the D bit. */ 2931 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ); 2932 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 2933 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC); 2934 /* Both A and D already set, so read-only is OK. */ 2935 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_READ); 2936 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_WRITE); 2937 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_EXEC); 2938 } 2939 2940 static void ept_access_test_paddr_read_only_ad_enabled(void) 2941 { 2942 /* 2943 * When EPT AD bits are enabled, all accesses to guest paging 2944 * structures are considered writes as far as EPT translation 2945 * is concerned. 2946 */ 2947 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 2948 2949 ept_access_test_setup(); 2950 ept_enable_ad_bits_or_skip_test(); 2951 2952 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 2953 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 2954 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 2955 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ, qual); 2956 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 2957 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC, qual); 2958 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_READ, qual); 2959 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_WRITE, qual); 2960 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_EXEC, qual); 2961 } 2962 2963 static void ept_access_test_paddr_read_write(void) 2964 { 2965 ept_access_test_setup(); 2966 /* Read-write access to paging structure. */ 2967 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_READ); 2968 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_WRITE); 2969 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_EXEC); 2970 } 2971 2972 static void ept_access_test_paddr_read_write_execute(void) 2973 { 2974 ept_access_test_setup(); 2975 /* RWX access to paging structure. */ 2976 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_READ); 2977 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_WRITE); 2978 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_EXEC); 2979 } 2980 2981 static void ept_access_test_paddr_read_execute_ad_disabled(void) 2982 { 2983 /* 2984 * When EPT AD bits are disabled, all accesses to guest paging 2985 * structures are reported separately as a read and (after 2986 * translation of the GPA to host physical address) a read+write 2987 * if the A/D bits have to be set. 2988 */ 2989 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 2990 2991 ept_access_test_setup(); 2992 ept_disable_ad_bits(); 2993 2994 /* Can't update A bit, so all accesses fail. */ 2995 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 2996 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 2997 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 2998 /* AD bits disabled, so only writes try to update the D bit. */ 2999 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ); 3000 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3001 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC); 3002 /* Both A and D already set, so read-only is OK. */ 3003 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ); 3004 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE); 3005 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC); 3006 } 3007 3008 static void ept_access_test_paddr_read_execute_ad_enabled(void) 3009 { 3010 /* 3011 * When EPT AD bits are enabled, all accesses to guest paging 3012 * structures are considered writes as far as EPT translation 3013 * is concerned. 3014 */ 3015 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3016 3017 ept_access_test_setup(); 3018 ept_enable_ad_bits_or_skip_test(); 3019 3020 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3021 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3022 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3023 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ, qual); 3024 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3025 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC, qual); 3026 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ, qual); 3027 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE, qual); 3028 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC, qual); 3029 } 3030 3031 static void ept_access_test_paddr_not_present_page_fault(void) 3032 { 3033 ept_access_test_setup(); 3034 /* 3035 * TODO: test no EPT violation as long as guest PF occurs. e.g., GPA is 3036 * page is read-only in EPT but GVA is also mapped read only in PT. 3037 * Thus guest page fault before host takes EPT violation for trying to 3038 * update A bit. 3039 */ 3040 } 3041 3042 static void ept_access_test_force_2m_page(void) 3043 { 3044 ept_access_test_setup(); 3045 3046 TEST_ASSERT_EQ(ept_2m_supported(), true); 3047 ept_allowed_at_level_mkhuge(true, 2, 0, 0, OP_READ); 3048 ept_violation_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_RA, OP_WRITE, 3049 EPT_VLT_WR | EPT_VLT_PERM_RD | 3050 EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 3051 ept_misconfig_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_WA); 3052 } 3053 3054 static bool invvpid_valid(u64 type, u64 vpid, u64 gla) 3055 { 3056 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3057 3058 TEST_ASSERT(msr & VPID_CAP_INVVPID); 3059 3060 if (type < INVVPID_ADDR || type > INVVPID_CONTEXT_LOCAL) 3061 return false; 3062 3063 if (!(msr & (1ull << (type + VPID_CAP_INVVPID_TYPES_SHIFT)))) 3064 return false; 3065 3066 if (vpid >> 16) 3067 return false; 3068 3069 if (type != INVVPID_ALL && !vpid) 3070 return false; 3071 3072 if (type == INVVPID_ADDR && !is_canonical(gla)) 3073 return false; 3074 3075 return true; 3076 } 3077 3078 static void try_invvpid(u64 type, u64 vpid, u64 gla) 3079 { 3080 int rc; 3081 bool valid = invvpid_valid(type, vpid, gla); 3082 u64 expected = valid ? VMXERR_UNSUPPORTED_VMCS_COMPONENT 3083 : VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID; 3084 /* 3085 * Set VMX_INST_ERROR to VMXERR_UNVALID_VMCS_COMPONENT, so 3086 * that we can tell if it is updated by INVVPID. 3087 */ 3088 vmcs_read(~0); 3089 rc = invvpid(type, vpid, gla); 3090 report("INVVPID type %ld VPID %lx GLA %lx %s", 3091 !rc == valid, type, vpid, gla, 3092 valid ? "passes" : "fails"); 3093 report("After %s INVVPID, VMX_INST_ERR is %ld (actual %ld)", 3094 vmcs_read(VMX_INST_ERROR) == expected, 3095 rc ? "failed" : "successful", 3096 expected, vmcs_read(VMX_INST_ERROR)); 3097 } 3098 3099 static void ds_invvpid(void *data) 3100 { 3101 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3102 u64 type = ffs(msr >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 3103 3104 TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 3105 asm volatile("invvpid %0, %1" 3106 : 3107 : "m"(*(struct invvpid_operand *)data), 3108 "r"(type)); 3109 } 3110 3111 /* 3112 * The SS override is ignored in 64-bit mode, so we use an addressing 3113 * mode with %rsp as the base register to generate an implicit SS 3114 * reference. 3115 */ 3116 static void ss_invvpid(void *data) 3117 { 3118 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3119 u64 type = ffs(msr >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 3120 3121 TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 3122 asm volatile("sub %%rsp,%0; invvpid (%%rsp,%0,1), %1" 3123 : "+r"(data) 3124 : "r"(type)); 3125 } 3126 3127 static void invvpid_test_gp(void) 3128 { 3129 bool fault; 3130 3131 fault = test_for_exception(GP_VECTOR, &ds_invvpid, 3132 (void *)NONCANONICAL); 3133 report("INVVPID with non-canonical DS operand raises #GP", fault); 3134 } 3135 3136 static void invvpid_test_ss(void) 3137 { 3138 bool fault; 3139 3140 fault = test_for_exception(SS_VECTOR, &ss_invvpid, 3141 (void *)NONCANONICAL); 3142 report("INVVPID with non-canonical SS operand raises #SS", fault); 3143 } 3144 3145 static void invvpid_test_pf(void) 3146 { 3147 void *vpage = alloc_vpage(); 3148 bool fault; 3149 3150 fault = test_for_exception(PF_VECTOR, &ds_invvpid, vpage); 3151 report("INVVPID with unmapped operand raises #PF", fault); 3152 } 3153 3154 static void try_compat_invvpid(void *unused) 3155 { 3156 struct far_pointer32 fp = { 3157 .offset = (uintptr_t)&&invvpid, 3158 .selector = KERNEL_CS32, 3159 }; 3160 register uintptr_t rsp asm("rsp"); 3161 3162 TEST_ASSERT_MSG(fp.offset == (uintptr_t)&&invvpid, 3163 "Code address too high."); 3164 TEST_ASSERT_MSG(rsp == (u32)rsp, "Stack address too high."); 3165 3166 asm goto ("lcall *%0" : : "m" (fp) : "rax" : invvpid); 3167 return; 3168 invvpid: 3169 asm volatile (".code32;" 3170 "invvpid (%eax), %eax;" 3171 "lret;" 3172 ".code64"); 3173 __builtin_unreachable(); 3174 } 3175 3176 static void invvpid_test_compatibility_mode(void) 3177 { 3178 bool fault; 3179 3180 fault = test_for_exception(UD_VECTOR, &try_compat_invvpid, NULL); 3181 report("Compatibility mode INVVPID raises #UD", fault); 3182 } 3183 3184 static void invvpid_test_not_in_vmx_operation(void) 3185 { 3186 bool fault; 3187 3188 TEST_ASSERT(!vmx_off()); 3189 fault = test_for_exception(UD_VECTOR, &ds_invvpid, NULL); 3190 report("INVVPID outside of VMX operation raises #UD", fault); 3191 TEST_ASSERT(!vmx_on()); 3192 } 3193 3194 /* 3195 * This does not test real-address mode, virtual-8086 mode, protected mode, 3196 * or CPL > 0. 3197 */ 3198 static void invvpid_test_v2(void) 3199 { 3200 u64 msr; 3201 int i; 3202 unsigned types = 0; 3203 unsigned type; 3204 3205 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 3206 !(ctrl_cpu_rev[1].clr & CPU_VPID)) 3207 test_skip("VPID not supported"); 3208 3209 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3210 3211 if (!(msr & VPID_CAP_INVVPID)) 3212 test_skip("INVVPID not supported.\n"); 3213 3214 if (msr & VPID_CAP_INVVPID_ADDR) 3215 types |= 1u << INVVPID_ADDR; 3216 if (msr & VPID_CAP_INVVPID_CXTGLB) 3217 types |= 1u << INVVPID_CONTEXT_GLOBAL; 3218 if (msr & VPID_CAP_INVVPID_ALL) 3219 types |= 1u << INVVPID_ALL; 3220 if (msr & VPID_CAP_INVVPID_CXTLOC) 3221 types |= 1u << INVVPID_CONTEXT_LOCAL; 3222 3223 if (!types) 3224 test_skip("No INVVPID types supported.\n"); 3225 3226 for (i = -127; i < 128; i++) 3227 try_invvpid(i, 0xffff, 0); 3228 3229 /* 3230 * VPID must not be more than 16 bits. 3231 */ 3232 for (i = 0; i < 64; i++) 3233 for (type = 0; type < 4; type++) 3234 if (types & (1u << type)) 3235 try_invvpid(type, 1ul << i, 0); 3236 3237 /* 3238 * VPID must not be zero, except for "all contexts." 3239 */ 3240 for (type = 0; type < 4; type++) 3241 if (types & (1u << type)) 3242 try_invvpid(type, 0, 0); 3243 3244 /* 3245 * The gla operand is only validated for single-address INVVPID. 3246 */ 3247 if (types & (1u << INVVPID_ADDR)) 3248 try_invvpid(INVVPID_ADDR, 0xffff, NONCANONICAL); 3249 3250 invvpid_test_gp(); 3251 invvpid_test_ss(); 3252 invvpid_test_pf(); 3253 invvpid_test_compatibility_mode(); 3254 invvpid_test_not_in_vmx_operation(); 3255 } 3256 3257 /* 3258 * Test for early VMLAUNCH failure. Returns true if VMLAUNCH makes it 3259 * at least as far as the guest-state checks. Returns false if the 3260 * VMLAUNCH fails early and execution falls through to the next 3261 * instruction. 3262 */ 3263 static bool vmlaunch_succeeds(void) 3264 { 3265 u32 exit_reason; 3266 3267 /* 3268 * Indirectly set VMX_INST_ERR to 12 ("VMREAD/VMWRITE from/to 3269 * unsupported VMCS component"). The caller can then check 3270 * to see if a failed VM-entry sets VMX_INST_ERR as expected. 3271 */ 3272 vmcs_write(~0u, 0); 3273 3274 vmcs_write(HOST_RIP, (uintptr_t)&&success); 3275 __asm__ __volatile__ goto ("vmwrite %%rsp, %0; vmlaunch" 3276 : 3277 : "r" ((u64)HOST_RSP) 3278 : "cc", "memory" 3279 : success); 3280 return false; 3281 success: 3282 exit_reason = vmcs_read(EXI_REASON); 3283 TEST_ASSERT(exit_reason == (VMX_FAIL_STATE | VMX_ENTRY_FAILURE) || 3284 exit_reason == (VMX_FAIL_MSR | VMX_ENTRY_FAILURE)); 3285 return true; 3286 } 3287 3288 /* 3289 * Try to launch the current VMCS. 3290 */ 3291 static void test_vmx_controls(bool controls_valid, bool xfail) 3292 { 3293 bool success = vmlaunch_succeeds(); 3294 u32 vmx_inst_err; 3295 3296 report_xfail("vmlaunch %s", xfail, success == controls_valid, 3297 controls_valid ? "succeeds" : "fails"); 3298 if (!success) { 3299 vmx_inst_err = vmcs_read(VMX_INST_ERROR); 3300 report("VMX inst error is %d (actual %d)", 3301 vmx_inst_err == VMXERR_ENTRY_INVALID_CONTROL_FIELD, 3302 VMXERR_ENTRY_INVALID_CONTROL_FIELD, vmx_inst_err); 3303 } 3304 } 3305 3306 /* 3307 * Test a particular value of a VM-execution control bit, if the value 3308 * is required or if the value is zero. 3309 */ 3310 static void test_rsvd_ctl_bit_value(const char *name, union vmx_ctrl_msr msr, 3311 enum Encoding encoding, unsigned bit, 3312 unsigned val) 3313 { 3314 u32 mask = 1u << bit; 3315 bool expected; 3316 u32 controls; 3317 3318 if (msr.set & mask) 3319 TEST_ASSERT(msr.clr & mask); 3320 3321 /* 3322 * We can't arbitrarily turn on a control bit, because it may 3323 * introduce dependencies on other VMCS fields. So, we only 3324 * test turning on bits that have a required setting. 3325 */ 3326 if (val && (msr.clr & mask) && !(msr.set & mask)) 3327 return; 3328 3329 report_prefix_pushf("%s %s bit %d", 3330 val ? "Set" : "Clear", name, bit); 3331 3332 controls = vmcs_read(encoding); 3333 if (val) { 3334 vmcs_write(encoding, msr.set | mask); 3335 expected = (msr.clr & mask); 3336 } else { 3337 vmcs_write(encoding, msr.set & ~mask); 3338 expected = !(msr.set & mask); 3339 } 3340 test_vmx_controls(expected, false); 3341 vmcs_write(encoding, controls); 3342 report_prefix_pop(); 3343 } 3344 3345 /* 3346 * Test reserved values of a VM-execution control bit, based on the 3347 * allowed bit settings from the corresponding VMX capability MSR. 3348 */ 3349 static void test_rsvd_ctl_bit(const char *name, union vmx_ctrl_msr msr, 3350 enum Encoding encoding, unsigned bit) 3351 { 3352 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 0); 3353 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 1); 3354 } 3355 3356 /* 3357 * Reserved bits in the pin-based VM-execution controls must be set 3358 * properly. Software may consult the VMX capability MSRs to determine 3359 * the proper settings. 3360 * [Intel SDM] 3361 */ 3362 static void test_pin_based_ctls(void) 3363 { 3364 unsigned bit; 3365 3366 printf("%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PIN" : 3367 "MSR_IA32_VMX_PINBASED_CTLS", ctrl_pin_rev.val); 3368 for (bit = 0; bit < 32; bit++) 3369 test_rsvd_ctl_bit("pin-based controls", 3370 ctrl_pin_rev, PIN_CONTROLS, bit); 3371 } 3372 3373 /* 3374 * Reserved bits in the primary processor-based VM-execution controls 3375 * must be set properly. Software may consult the VMX capability MSRs 3376 * to determine the proper settings. 3377 * [Intel SDM] 3378 */ 3379 static void test_primary_processor_based_ctls(void) 3380 { 3381 unsigned bit; 3382 3383 printf("\n%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PROC" : 3384 "MSR_IA32_VMX_PROCBASED_CTLS", ctrl_cpu_rev[0].val); 3385 for (bit = 0; bit < 32; bit++) 3386 test_rsvd_ctl_bit("primary processor-based controls", 3387 ctrl_cpu_rev[0], CPU_EXEC_CTRL0, bit); 3388 } 3389 3390 /* 3391 * If the "activate secondary controls" primary processor-based 3392 * VM-execution control is 1, reserved bits in the secondary 3393 * processor-based VM-execution controls must be cleared. Software may 3394 * consult the VMX capability MSRs to determine which bits are 3395 * reserved. 3396 * If the "activate secondary controls" primary processor-based 3397 * VM-execution control is 0 (or if the processor does not support the 3398 * 1-setting of that control), no checks are performed on the 3399 * secondary processor-based VM-execution controls. 3400 * [Intel SDM] 3401 */ 3402 static void test_secondary_processor_based_ctls(void) 3403 { 3404 u32 primary; 3405 u32 secondary; 3406 unsigned bit; 3407 3408 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) 3409 return; 3410 3411 primary = vmcs_read(CPU_EXEC_CTRL0); 3412 secondary = vmcs_read(CPU_EXEC_CTRL1); 3413 3414 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3415 printf("\nMSR_IA32_VMX_PROCBASED_CTLS2: %lx\n", ctrl_cpu_rev[1].val); 3416 for (bit = 0; bit < 32; bit++) 3417 test_rsvd_ctl_bit("secondary processor-based controls", 3418 ctrl_cpu_rev[1], CPU_EXEC_CTRL1, bit); 3419 3420 /* 3421 * When the "activate secondary controls" VM-execution control 3422 * is clear, there are no checks on the secondary controls. 3423 */ 3424 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3425 vmcs_write(CPU_EXEC_CTRL1, ~0); 3426 report("Secondary processor-based controls ignored", 3427 vmlaunch_succeeds()); 3428 vmcs_write(CPU_EXEC_CTRL1, secondary); 3429 vmcs_write(CPU_EXEC_CTRL0, primary); 3430 } 3431 3432 static void try_cr3_target_count(unsigned i, unsigned max) 3433 { 3434 report_prefix_pushf("CR3 target count 0x%x", i); 3435 vmcs_write(CR3_TARGET_COUNT, i); 3436 test_vmx_controls(i <= max, false); 3437 report_prefix_pop(); 3438 } 3439 3440 /* 3441 * The CR3-target count must not be greater than 4. Future processors 3442 * may support a different number of CR3-target values. Software 3443 * should read the VMX capability MSR IA32_VMX_MISC to determine the 3444 * number of values supported. 3445 * [Intel SDM] 3446 */ 3447 static void test_cr3_targets(void) 3448 { 3449 unsigned supported_targets = (rdmsr(MSR_IA32_VMX_MISC) >> 16) & 0x1ff; 3450 u32 cr3_targets = vmcs_read(CR3_TARGET_COUNT); 3451 unsigned i; 3452 3453 printf("\nSupported CR3 targets: %d\n", supported_targets); 3454 TEST_ASSERT(supported_targets <= 256); 3455 3456 try_cr3_target_count(-1u, supported_targets); 3457 try_cr3_target_count(0x80000000, supported_targets); 3458 try_cr3_target_count(0x7fffffff, supported_targets); 3459 for (i = 0; i <= supported_targets + 1; i++) 3460 try_cr3_target_count(i, supported_targets); 3461 vmcs_write(CR3_TARGET_COUNT, cr3_targets); 3462 } 3463 3464 /* 3465 * Test a particular address setting in the VMCS 3466 */ 3467 static void test_vmcs_addr(const char *name, 3468 enum Encoding encoding, 3469 u64 align, 3470 bool ignored, 3471 bool xfail_beyond_mapped_ram, 3472 u64 addr) 3473 { 3474 bool xfail = 3475 (xfail_beyond_mapped_ram && 3476 addr > fwcfg_get_u64(FW_CFG_RAM_SIZE) - align && 3477 addr < (1ul << cpuid_maxphyaddr())); 3478 3479 report_prefix_pushf("%s = %lx", name, addr); 3480 vmcs_write(encoding, addr); 3481 test_vmx_controls(ignored || (IS_ALIGNED(addr, align) && 3482 addr < (1ul << cpuid_maxphyaddr())), 3483 xfail); 3484 report_prefix_pop(); 3485 xfail = false; 3486 } 3487 3488 /* 3489 * Test interesting values for a VMCS address 3490 */ 3491 static void test_vmcs_addr_values(const char *name, 3492 enum Encoding encoding, 3493 u64 align, 3494 bool ignored, 3495 bool xfail_beyond_mapped_ram, 3496 u32 bit_start, u32 bit_end) 3497 { 3498 unsigned i; 3499 u64 orig_val = vmcs_read(encoding); 3500 3501 for (i = bit_start; i <= bit_end; i++) 3502 test_vmcs_addr(name, encoding, align, ignored, 3503 xfail_beyond_mapped_ram, 1ul << i); 3504 3505 test_vmcs_addr(name, encoding, align, ignored, 3506 xfail_beyond_mapped_ram, PAGE_SIZE - 1); 3507 test_vmcs_addr(name, encoding, align, ignored, 3508 xfail_beyond_mapped_ram, PAGE_SIZE); 3509 test_vmcs_addr(name, encoding, align, ignored, 3510 xfail_beyond_mapped_ram, 3511 (1ul << cpuid_maxphyaddr()) - PAGE_SIZE); 3512 test_vmcs_addr(name, encoding, align, ignored, 3513 xfail_beyond_mapped_ram, -1ul); 3514 3515 vmcs_write(encoding, orig_val); 3516 } 3517 3518 /* 3519 * Test a physical address reference in the VMCS, when the corresponding 3520 * feature is enabled and when the corresponding feature is disabled. 3521 */ 3522 static void test_vmcs_addr_reference(u32 control_bit, enum Encoding field, 3523 const char *field_name, 3524 const char *control_name, u64 align, 3525 bool xfail_beyond_mapped_ram, 3526 bool control_primary) 3527 { 3528 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 3529 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 3530 u64 page_addr; 3531 3532 if (control_primary) { 3533 if (!(ctrl_cpu_rev[0].clr & control_bit)) 3534 return; 3535 } else { 3536 if (!(ctrl_cpu_rev[1].clr & control_bit)) 3537 return; 3538 } 3539 3540 page_addr = vmcs_read(field); 3541 3542 report_prefix_pushf("%s enabled", control_name); 3543 if (control_primary) { 3544 vmcs_write(CPU_EXEC_CTRL0, primary | control_bit); 3545 } else { 3546 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3547 vmcs_write(CPU_EXEC_CTRL1, secondary | control_bit); 3548 } 3549 3550 test_vmcs_addr_values(field_name, field, align, false, 3551 xfail_beyond_mapped_ram, 0, 63); 3552 report_prefix_pop(); 3553 3554 report_prefix_pushf("%s disabled", control_name); 3555 if (control_primary) { 3556 vmcs_write(CPU_EXEC_CTRL0, primary & ~control_bit); 3557 } else { 3558 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3559 vmcs_write(CPU_EXEC_CTRL1, secondary & ~control_bit); 3560 } 3561 3562 test_vmcs_addr_values(field_name, field, align, true, false, 0, 63); 3563 report_prefix_pop(); 3564 3565 vmcs_write(field, page_addr); 3566 vmcs_write(CPU_EXEC_CTRL0, primary); 3567 } 3568 3569 /* 3570 * If the "use I/O bitmaps" VM-execution control is 1, bits 11:0 of 3571 * each I/O-bitmap address must be 0. Neither address should set any 3572 * bits beyond the processor's physical-address width. 3573 * [Intel SDM] 3574 */ 3575 static void test_io_bitmaps(void) 3576 { 3577 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_A, 3578 "I/O bitmap A", "Use I/O bitmaps", 3579 PAGE_SIZE, false, true); 3580 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_B, 3581 "I/O bitmap B", "Use I/O bitmaps", 3582 PAGE_SIZE, false, true); 3583 } 3584 3585 /* 3586 * If the "use MSR bitmaps" VM-execution control is 1, bits 11:0 of 3587 * the MSR-bitmap address must be 0. The address should not set any 3588 * bits beyond the processor's physical-address width. 3589 * [Intel SDM] 3590 */ 3591 static void test_msr_bitmap(void) 3592 { 3593 test_vmcs_addr_reference(CPU_MSR_BITMAP, MSR_BITMAP, 3594 "MSR bitmap", "Use MSR bitmaps", 3595 PAGE_SIZE, false, true); 3596 } 3597 3598 /* 3599 * If the "use TPR shadow" VM-execution control is 1, the virtual-APIC 3600 * address must satisfy the following checks: 3601 * - Bits 11:0 of the address must be 0. 3602 * - The address should not set any bits beyond the processor's 3603 * physical-address width. 3604 * [Intel SDM] 3605 */ 3606 static void test_apic_virt_addr(void) 3607 { 3608 test_vmcs_addr_reference(CPU_TPR_SHADOW, APIC_VIRT_ADDR, 3609 "virtual-APIC address", "Use TPR shadow", 3610 PAGE_SIZE, true, true); 3611 } 3612 3613 /* 3614 * If the "virtualize APIC-accesses" VM-execution control is 1, the 3615 * APIC-access address must satisfy the following checks: 3616 * - Bits 11:0 of the address must be 0. 3617 * - The address should not set any bits beyond the processor's 3618 * physical-address width. 3619 * [Intel SDM] 3620 */ 3621 static void test_apic_access_addr(void) 3622 { 3623 void *apic_access_page = alloc_page(); 3624 3625 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_page)); 3626 3627 test_vmcs_addr_reference(CPU_VIRT_APIC_ACCESSES, APIC_ACCS_ADDR, 3628 "APIC-access address", 3629 "virtualize APIC-accesses", PAGE_SIZE, 3630 false, false); 3631 } 3632 3633 static bool set_bit_pattern(u8 mask, u32 *secondary) 3634 { 3635 u8 i; 3636 bool flag = false; 3637 u32 test_bits[3] = { 3638 CPU_VIRT_X2APIC, 3639 CPU_APIC_REG_VIRT, 3640 CPU_VINTD 3641 }; 3642 3643 for (i = 0; i < ARRAY_SIZE(test_bits); i++) { 3644 if ((mask & (1u << i)) && 3645 (ctrl_cpu_rev[1].clr & test_bits[i])) { 3646 *secondary |= test_bits[i]; 3647 flag = true; 3648 } 3649 } 3650 3651 return (flag); 3652 } 3653 3654 /* 3655 * If the "use TPR shadow" VM-execution control is 0, the following 3656 * VM-execution controls must also be 0: 3657 * - virtualize x2APIC mode 3658 * - APIC-register virtualization 3659 * - virtual-interrupt delivery 3660 * [Intel SDM] 3661 * 3662 * 2. If the "virtualize x2APIC mode" VM-execution control is 1, the 3663 * "virtualize APIC accesses" VM-execution control must be 0. 3664 * [Intel SDM] 3665 */ 3666 static void test_apic_virtual_ctls(void) 3667 { 3668 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3669 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3670 u32 primary = saved_primary; 3671 u32 secondary = saved_secondary; 3672 bool ctrl = false; 3673 char str[10] = "disabled"; 3674 u8 i = 0, j; 3675 3676 /* 3677 * First test 3678 */ 3679 if (!((ctrl_cpu_rev[0].clr & (CPU_SECONDARY | CPU_TPR_SHADOW)) == 3680 (CPU_SECONDARY | CPU_TPR_SHADOW))) 3681 return; 3682 3683 primary |= CPU_SECONDARY; 3684 primary &= ~CPU_TPR_SHADOW; 3685 vmcs_write(CPU_EXEC_CTRL0, primary); 3686 3687 while (1) { 3688 for (j = 1; j < 8; j++) { 3689 secondary &= ~(CPU_VIRT_X2APIC | CPU_APIC_REG_VIRT | CPU_VINTD); 3690 if (primary & CPU_TPR_SHADOW) { 3691 ctrl = true; 3692 } else { 3693 if (! set_bit_pattern(j, &secondary)) 3694 ctrl = true; 3695 else 3696 ctrl = false; 3697 } 3698 3699 vmcs_write(CPU_EXEC_CTRL1, secondary); 3700 report_prefix_pushf("Use TPR shadow %s, virtualize x2APIC mode %s, APIC-register virtualization %s, virtual-interrupt delivery %s", 3701 str, (secondary & CPU_VIRT_X2APIC) ? "enabled" : "disabled", (secondary & CPU_APIC_REG_VIRT) ? "enabled" : "disabled", (secondary & CPU_VINTD) ? "enabled" : "disabled"); 3702 test_vmx_controls(ctrl, false); 3703 report_prefix_pop(); 3704 } 3705 3706 if (i == 1) 3707 break; 3708 i++; 3709 3710 primary |= CPU_TPR_SHADOW; 3711 vmcs_write(CPU_EXEC_CTRL0, primary); 3712 strcpy(str, "enabled"); 3713 } 3714 3715 /* 3716 * Second test 3717 */ 3718 u32 apic_virt_ctls = (CPU_VIRT_X2APIC | CPU_VIRT_APIC_ACCESSES); 3719 3720 primary = saved_primary; 3721 secondary = saved_secondary; 3722 if (!((ctrl_cpu_rev[1].clr & apic_virt_ctls) == apic_virt_ctls)) 3723 return; 3724 3725 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3726 secondary &= ~CPU_VIRT_APIC_ACCESSES; 3727 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_X2APIC); 3728 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access disabled"); 3729 test_vmx_controls(true, false); 3730 report_prefix_pop(); 3731 3732 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_APIC_ACCESSES); 3733 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access enabled"); 3734 test_vmx_controls(true, false); 3735 report_prefix_pop(); 3736 3737 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_X2APIC); 3738 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access enabled"); 3739 test_vmx_controls(false, false); 3740 report_prefix_pop(); 3741 3742 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_APIC_ACCESSES); 3743 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access disabled"); 3744 test_vmx_controls(true, false); 3745 report_prefix_pop(); 3746 3747 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3748 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3749 } 3750 3751 /* 3752 * If the "virtual-interrupt delivery" VM-execution control is 1, the 3753 * "external-interrupt exiting" VM-execution control must be 1. 3754 * [Intel SDM] 3755 */ 3756 static void test_virtual_intr_ctls(void) 3757 { 3758 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3759 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3760 u32 saved_pin = vmcs_read(PIN_CONTROLS); 3761 u32 primary = saved_primary; 3762 u32 secondary = saved_secondary; 3763 u32 pin = saved_pin; 3764 3765 if (!((ctrl_cpu_rev[1].clr & CPU_VINTD) && 3766 (ctrl_pin_rev.clr & PIN_EXTINT))) 3767 return; 3768 3769 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 3770 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VINTD); 3771 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 3772 report_prefix_pushf("Virtualize interrupt-delivery disabled; external-interrupt exiting disabled"); 3773 test_vmx_controls(true, false); 3774 report_prefix_pop(); 3775 3776 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VINTD); 3777 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 3778 test_vmx_controls(false, false); 3779 report_prefix_pop(); 3780 3781 vmcs_write(PIN_CONTROLS, pin | PIN_EXTINT); 3782 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting enabled"); 3783 test_vmx_controls(true, false); 3784 report_prefix_pop(); 3785 3786 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 3787 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 3788 test_vmx_controls(false, false); 3789 report_prefix_pop(); 3790 3791 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3792 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3793 vmcs_write(PIN_CONTROLS, saved_pin); 3794 } 3795 3796 static void test_pi_desc_addr(u64 addr, bool ctrl) 3797 { 3798 vmcs_write(POSTED_INTR_DESC_ADDR, addr); 3799 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-descriptor-address 0x%lx", addr); 3800 test_vmx_controls(ctrl, false); 3801 report_prefix_pop(); 3802 } 3803 3804 /* 3805 * If the “process posted interrupts†VM-execution control is 1, the 3806 * following must be true: 3807 * 3808 * - The “virtual-interrupt delivery†VM-execution control is 1. 3809 * - The “acknowledge interrupt on exit†VM-exit control is 1. 3810 * - The posted-interrupt notification vector has a value in the 3811 * - range 0–255 (bits 15:8 are all 0). 3812 * - Bits 5:0 of the posted-interrupt descriptor address are all 0. 3813 * - The posted-interrupt descriptor address does not set any bits 3814 * beyond the processor's physical-address width. 3815 * [Intel SDM] 3816 */ 3817 static void test_posted_intr(void) 3818 { 3819 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3820 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3821 u32 saved_pin = vmcs_read(PIN_CONTROLS); 3822 u32 exit_ctl_saved = vmcs_read(EXI_CONTROLS); 3823 u32 primary = saved_primary; 3824 u32 secondary = saved_secondary; 3825 u32 pin = saved_pin; 3826 u32 exit_ctl = exit_ctl_saved; 3827 u16 vec; 3828 int i; 3829 3830 if (!((ctrl_pin_rev.clr & PIN_POST_INTR) && 3831 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 3832 (ctrl_exit_rev.clr & EXI_INTA))) 3833 return; 3834 3835 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 3836 3837 /* 3838 * Test virtual-interrupt-delivery and acknowledge-interrupt-on-exit 3839 */ 3840 pin |= PIN_POST_INTR; 3841 vmcs_write(PIN_CONTROLS, pin); 3842 secondary &= ~CPU_VINTD; 3843 vmcs_write(CPU_EXEC_CTRL1, secondary); 3844 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled"); 3845 test_vmx_controls(false, false); 3846 report_prefix_pop(); 3847 3848 secondary |= CPU_VINTD; 3849 vmcs_write(CPU_EXEC_CTRL1, secondary); 3850 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled"); 3851 test_vmx_controls(false, false); 3852 report_prefix_pop(); 3853 3854 exit_ctl &= ~EXI_INTA; 3855 vmcs_write(EXI_CONTROLS, exit_ctl); 3856 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit disabled"); 3857 test_vmx_controls(false, false); 3858 report_prefix_pop(); 3859 3860 exit_ctl |= EXI_INTA; 3861 vmcs_write(EXI_CONTROLS, exit_ctl); 3862 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 3863 test_vmx_controls(true, false); 3864 report_prefix_pop(); 3865 3866 secondary &= ~CPU_VINTD; 3867 vmcs_write(CPU_EXEC_CTRL1, secondary); 3868 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled; acknowledge-interrupt-on-exit enabled"); 3869 test_vmx_controls(false, false); 3870 report_prefix_pop(); 3871 3872 secondary |= CPU_VINTD; 3873 vmcs_write(CPU_EXEC_CTRL1, secondary); 3874 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 3875 test_vmx_controls(true, false); 3876 report_prefix_pop(); 3877 3878 /* 3879 * Test posted-interrupt notification vector 3880 */ 3881 for (i = 0; i < 8; i++) { 3882 vec = (1ul << i); 3883 vmcs_write(PINV, vec); 3884 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 3885 test_vmx_controls(true, false); 3886 report_prefix_pop(); 3887 } 3888 for (i = 8; i < 16; i++) { 3889 vec = (1ul << i); 3890 vmcs_write(PINV, vec); 3891 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 3892 test_vmx_controls(false, false); 3893 report_prefix_pop(); 3894 } 3895 3896 vec &= ~(0xff << 8); 3897 vmcs_write(PINV, vec); 3898 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 3899 test_vmx_controls(true, false); 3900 report_prefix_pop(); 3901 3902 /* 3903 * Test posted-interrupt descriptor addresss 3904 */ 3905 for (i = 0; i < 6; i++) { 3906 test_pi_desc_addr(1ul << i, false); 3907 } 3908 3909 test_pi_desc_addr(0xf0, false); 3910 test_pi_desc_addr(0xff, false); 3911 test_pi_desc_addr(0x0f, false); 3912 test_pi_desc_addr(0x8000, true); 3913 test_pi_desc_addr(0x00, true); 3914 test_pi_desc_addr(0xc000, true); 3915 3916 test_vmcs_addr_values("process-posted interrupts", 3917 POSTED_INTR_DESC_ADDR, 64, 3918 false, false, 0, 63); 3919 3920 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3921 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3922 vmcs_write(PIN_CONTROLS, saved_pin); 3923 } 3924 3925 static void test_apic_ctls(void) 3926 { 3927 test_apic_virt_addr(); 3928 test_apic_access_addr(); 3929 test_apic_virtual_ctls(); 3930 test_virtual_intr_ctls(); 3931 test_posted_intr(); 3932 } 3933 3934 /* 3935 * If the “enable VPID†VM-execution control is 1, the value of the 3936 * of the VPID VM-execution control field must not be 0000H. 3937 * [Intel SDM] 3938 */ 3939 static void test_vpid(void) 3940 { 3941 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3942 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3943 u16 vpid = 0x0000; 3944 int i; 3945 3946 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 3947 (ctrl_cpu_rev[1].clr & CPU_VPID))) { 3948 test_skip("Secondary controls and/or VPID not supported"); 3949 return; 3950 } 3951 3952 vmcs_write(CPU_EXEC_CTRL0, saved_primary | CPU_SECONDARY); 3953 vmcs_write(CPU_EXEC_CTRL1, saved_secondary & ~CPU_VPID); 3954 vmcs_write(VPID, vpid); 3955 report_prefix_pushf("VPID disabled; VPID value %x", vpid); 3956 test_vmx_controls(true, false); 3957 report_prefix_pop(); 3958 3959 vmcs_write(CPU_EXEC_CTRL1, saved_secondary | CPU_VPID); 3960 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 3961 test_vmx_controls(false, false); 3962 report_prefix_pop(); 3963 3964 for (i = 0; i < 16; i++) { 3965 vpid = (short)1 << i;; 3966 vmcs_write(VPID, vpid); 3967 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 3968 test_vmx_controls(true, false); 3969 report_prefix_pop(); 3970 } 3971 3972 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3973 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3974 } 3975 3976 static void set_vtpr(unsigned vtpr) 3977 { 3978 *(u32 *)phys_to_virt(vmcs_read(APIC_VIRT_ADDR) + APIC_TASKPRI) = vtpr; 3979 } 3980 3981 static void try_tpr_threshold_and_vtpr(unsigned threshold, unsigned vtpr) 3982 { 3983 bool valid = true; 3984 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 3985 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 3986 3987 if ((primary & CPU_TPR_SHADOW) && 3988 (!(primary & CPU_SECONDARY) || 3989 !(secondary & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 3990 valid = (threshold & 0xf) <= ((vtpr >> 4) & 0xf); 3991 3992 set_vtpr(vtpr); 3993 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0x%x", 3994 threshold, (vtpr >> 4) & 0xf); 3995 test_vmx_controls(valid, false); 3996 report_prefix_pop(); 3997 } 3998 3999 static void test_invalid_event_injection(void) 4000 { 4001 u32 ent_intr_info_save = vmcs_read(ENT_INTR_INFO); 4002 u32 ent_intr_error_save = vmcs_read(ENT_INTR_ERROR); 4003 u32 ent_inst_len_save = vmcs_read(ENT_INST_LEN); 4004 u32 primary_save = vmcs_read(CPU_EXEC_CTRL0); 4005 u32 secondary_save = vmcs_read(CPU_EXEC_CTRL1); 4006 u64 guest_cr0_save = vmcs_read(GUEST_CR0); 4007 u32 ent_intr_info_base = INTR_INFO_VALID_MASK; 4008 u32 ent_intr_info, ent_intr_err, ent_intr_len; 4009 u32 cnt; 4010 4011 /* Setup */ 4012 report_prefix_push("invalid event injection"); 4013 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4014 vmcs_write(ENT_INST_LEN, 0x00000001); 4015 4016 /* The field’s interruption type is not set to a reserved value. */ 4017 ent_intr_info = ent_intr_info_base | INTR_TYPE_RESERVED | DE_VECTOR; 4018 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4019 "RESERVED interruption type invalid [-]", 4020 ent_intr_info); 4021 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4022 test_vmx_controls(false, false); 4023 report_prefix_pop(); 4024 4025 ent_intr_info = ent_intr_info_base | INTR_TYPE_EXT_INTR | 4026 DE_VECTOR; 4027 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4028 "RESERVED interruption type invalid [+]", 4029 ent_intr_info); 4030 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4031 test_vmx_controls(true, false); 4032 report_prefix_pop(); 4033 4034 /* If the interruption type is other event, the vector is 0. */ 4035 ent_intr_info = ent_intr_info_base | INTR_TYPE_OTHER_EVENT | DB_VECTOR; 4036 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4037 "(OTHER EVENT && vector != 0) invalid [-]", 4038 ent_intr_info); 4039 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4040 test_vmx_controls(false, false); 4041 report_prefix_pop(); 4042 4043 /* If the interruption type is NMI, the vector is 2 (negative case). */ 4044 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | DE_VECTOR; 4045 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4046 "(NMI && vector != 2) invalid [-]", ent_intr_info); 4047 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4048 test_vmx_controls(false, false); 4049 report_prefix_pop(); 4050 4051 /* If the interruption type is NMI, the vector is 2 (positive case). */ 4052 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | NMI_VECTOR; 4053 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4054 "(NMI && vector == 2) valid [+]", ent_intr_info); 4055 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4056 test_vmx_controls(true, false); 4057 report_prefix_pop(); 4058 4059 /* 4060 * If the interruption type 4061 * is HW exception, the vector is at most 31. 4062 */ 4063 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 0x20; 4064 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4065 "(HW exception && vector > 31) invalid [-]", 4066 ent_intr_info); 4067 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4068 test_vmx_controls(false, false); 4069 report_prefix_pop(); 4070 4071 /* 4072 * deliver-error-code is 1 iff either 4073 * (a) the "unrestricted guest" VM-execution control is 0 4074 * (b) CR0.PE is set. 4075 */ 4076 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4077 GP_VECTOR; 4078 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4079 "error code <-> (!URG || prot_mode) [-]", 4080 ent_intr_info); 4081 disable_unrestricted_guest(); 4082 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4083 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4084 test_vmx_controls(false, false); 4085 report_prefix_pop(); 4086 4087 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4088 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4089 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4090 "error code <-> (!URG || prot_mode) [+]", 4091 ent_intr_info); 4092 disable_unrestricted_guest(); 4093 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4094 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4095 test_vmx_controls(true, false); 4096 report_prefix_pop(); 4097 4098 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4099 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4100 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4101 "error code <-> (!URG || prot_mode) [-]", 4102 ent_intr_info); 4103 enable_unrestricted_guest(); 4104 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4105 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4106 test_vmx_controls(false, false); 4107 report_prefix_pop(); 4108 4109 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4110 GP_VECTOR; 4111 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4112 "error code <-> (!URG || prot_mode) [-]", 4113 ent_intr_info); 4114 vmcs_write(GUEST_CR0, guest_cr0_save | X86_CR0_PE); 4115 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4116 test_vmx_controls(false, false); 4117 report_prefix_pop(); 4118 4119 /* deliver-error-code is 1 iff the interruption type is HW exception */ 4120 report_prefix_push("error code <-> HW exception"); 4121 for (cnt = 0; cnt < 8; cnt++) { 4122 u32 exception_type_mask = cnt << 8; 4123 u32 deliver_error_code_mask = 4124 exception_type_mask != INTR_TYPE_HARD_EXCEPTION ? 4125 INTR_INFO_DELIVER_CODE_MASK : 0; 4126 4127 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4128 exception_type_mask | GP_VECTOR; 4129 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4130 ent_intr_info); 4131 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4132 test_vmx_controls(false, false); 4133 report_prefix_pop(); 4134 } 4135 report_prefix_pop(); 4136 4137 /* 4138 * deliver-error-code is 1 iff the the vector 4139 * indicates an exception that would normally deliver an error code 4140 */ 4141 report_prefix_push("error code <-> vector delivers error code"); 4142 for (cnt = 0; cnt < 32; cnt++) { 4143 bool has_error_code = false; 4144 u32 deliver_error_code_mask; 4145 4146 switch (cnt) { 4147 case DF_VECTOR: 4148 case TS_VECTOR: 4149 case NP_VECTOR: 4150 case SS_VECTOR: 4151 case GP_VECTOR: 4152 case PF_VECTOR: 4153 case AC_VECTOR: 4154 has_error_code = true; 4155 } 4156 4157 /* Negative case */ 4158 deliver_error_code_mask = has_error_code ? 4159 0 : 4160 INTR_INFO_DELIVER_CODE_MASK; 4161 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4162 INTR_TYPE_HARD_EXCEPTION | cnt; 4163 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4164 ent_intr_info); 4165 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4166 test_vmx_controls(false, false); 4167 report_prefix_pop(); 4168 4169 /* Positive case */ 4170 deliver_error_code_mask = has_error_code ? 4171 INTR_INFO_DELIVER_CODE_MASK : 4172 0; 4173 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4174 INTR_TYPE_HARD_EXCEPTION | cnt; 4175 report_prefix_pushf("VM-entry intr info=0x%x [+]", 4176 ent_intr_info); 4177 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4178 test_vmx_controls(true, false); 4179 report_prefix_pop(); 4180 } 4181 report_prefix_pop(); 4182 4183 /* Reserved bits in the field (30:12) are 0. */ 4184 report_prefix_push("reserved bits clear"); 4185 for (cnt = 12; cnt <= 30; cnt++) { 4186 ent_intr_info = ent_intr_info_base | 4187 INTR_INFO_DELIVER_CODE_MASK | 4188 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR | 4189 (1U << cnt); 4190 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4191 ent_intr_info); 4192 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4193 test_vmx_controls(false, false); 4194 report_prefix_pop(); 4195 } 4196 report_prefix_pop(); 4197 4198 /* 4199 * If deliver-error-code is 1 4200 * bits 31:15 of the VM-entry exception error-code field are 0. 4201 */ 4202 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4203 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4204 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4205 "VM-entry exception error code[31:15] clear", 4206 ent_intr_info); 4207 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4208 for (cnt = 15; cnt <= 31; cnt++) { 4209 ent_intr_err = 1U << cnt; 4210 report_prefix_pushf("VM-entry intr error=0x%x [-]", 4211 ent_intr_err); 4212 vmcs_write(ENT_INTR_ERROR, ent_intr_err); 4213 test_vmx_controls(false, false); 4214 report_prefix_pop(); 4215 } 4216 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4217 report_prefix_pop(); 4218 4219 /* 4220 * If the interruption type is software interrupt, software exception, 4221 * or privileged software exception, the VM-entry instruction-length 4222 * field is in the range 0–15. 4223 */ 4224 4225 for (cnt = 0; cnt < 3; cnt++) { 4226 switch (cnt) { 4227 case 0: 4228 ent_intr_info = ent_intr_info_base | 4229 INTR_TYPE_SOFT_INTR; 4230 break; 4231 case 1: 4232 ent_intr_info = ent_intr_info_base | 4233 INTR_TYPE_SOFT_EXCEPTION; 4234 break; 4235 case 2: 4236 ent_intr_info = ent_intr_info_base | 4237 INTR_TYPE_PRIV_SW_EXCEPTION; 4238 break; 4239 } 4240 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4241 "VM-entry instruction-length check", 4242 ent_intr_info); 4243 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4244 4245 /* Instruction length set to -1 (0xFFFFFFFF) should fail */ 4246 ent_intr_len = -1; 4247 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4248 ent_intr_len); 4249 vmcs_write(ENT_INST_LEN, ent_intr_len); 4250 test_vmx_controls(false, false); 4251 report_prefix_pop(); 4252 4253 /* Instruction length set to 16 should fail */ 4254 ent_intr_len = 0x00000010; 4255 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4256 ent_intr_len); 4257 vmcs_write(ENT_INST_LEN, 0x00000010); 4258 test_vmx_controls(false, false); 4259 report_prefix_pop(); 4260 4261 report_prefix_pop(); 4262 } 4263 4264 /* Cleanup */ 4265 vmcs_write(ENT_INTR_INFO, ent_intr_info_save); 4266 vmcs_write(ENT_INTR_ERROR, ent_intr_error_save); 4267 vmcs_write(ENT_INST_LEN, ent_inst_len_save); 4268 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4269 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4270 vmcs_write(GUEST_CR0, guest_cr0_save); 4271 report_prefix_pop(); 4272 } 4273 4274 /* 4275 * Test interesting vTPR values for a given TPR threshold. 4276 */ 4277 static void test_vtpr_values(unsigned threshold) 4278 { 4279 try_tpr_threshold_and_vtpr(threshold, (threshold - 1) << 4); 4280 try_tpr_threshold_and_vtpr(threshold, threshold << 4); 4281 try_tpr_threshold_and_vtpr(threshold, (threshold + 1) << 4); 4282 } 4283 4284 static void try_tpr_threshold(unsigned threshold) 4285 { 4286 bool valid = true; 4287 4288 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4289 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4290 4291 if ((primary & CPU_TPR_SHADOW) && !((primary & CPU_SECONDARY) && 4292 (secondary & CPU_VINTD))) 4293 valid = !(threshold >> 4); 4294 4295 set_vtpr(-1); 4296 vmcs_write(TPR_THRESHOLD, threshold); 4297 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0xf", threshold); 4298 test_vmx_controls(valid, false); 4299 report_prefix_pop(); 4300 4301 if (valid) 4302 test_vtpr_values(threshold); 4303 } 4304 4305 /* 4306 * Test interesting TPR threshold values. 4307 */ 4308 static void test_tpr_threshold_values(void) 4309 { 4310 unsigned i; 4311 4312 for (i = 0; i < 0x10; i++) 4313 try_tpr_threshold(i); 4314 for (i = 4; i < 32; i++) 4315 try_tpr_threshold(1u << i); 4316 try_tpr_threshold(-1u); 4317 try_tpr_threshold(0x7fffffff); 4318 } 4319 4320 /* 4321 * This test covers the following two VM entry checks: 4322 * 4323 * i) If the "use TPR shadow" VM-execution control is 1 and the 4324 * "virtual-interrupt delivery" VM-execution control is 0, bits 4325 * 31:4 of the TPR threshold VM-execution control field must 4326 be 0. 4327 * [Intel SDM] 4328 * 4329 * ii) If the "use TPR shadow" VM-execution control is 1, the 4330 * "virtual-interrupt delivery" VM-execution control is 0 4331 * and the "virtualize APIC accesses" VM-execution control 4332 * is 0, the value of bits 3:0 of the TPR threshold VM-execution 4333 * control field must not be greater than the value of bits 4334 * 7:4 of VTPR. 4335 * [Intel SDM] 4336 */ 4337 static void test_tpr_threshold(void) 4338 { 4339 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4340 void *virtual_apic_page; 4341 4342 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) 4343 return; 4344 4345 virtual_apic_page = alloc_page(); 4346 memset(virtual_apic_page, 0xff, PAGE_SIZE); 4347 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 4348 4349 vmcs_write(CPU_EXEC_CTRL0, primary & ~(CPU_TPR_SHADOW | CPU_SECONDARY)); 4350 report_prefix_pushf("Use TPR shadow disabled, secondary controls disabled"); 4351 test_tpr_threshold_values(); 4352 report_prefix_pop(); 4353 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_TPR_SHADOW); 4354 report_prefix_pushf("Use TPR shadow enabled, secondary controls disabled"); 4355 test_tpr_threshold_values(); 4356 report_prefix_pop(); 4357 4358 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4359 (ctrl_cpu_rev[1].clr & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) { 4360 vmcs_write(CPU_EXEC_CTRL0, primary); 4361 return; 4362 } 4363 4364 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4365 4366 if (ctrl_cpu_rev[1].clr & CPU_VINTD) { 4367 vmcs_write(CPU_EXEC_CTRL1, CPU_VINTD); 4368 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4369 test_tpr_threshold_values(); 4370 report_prefix_pop(); 4371 4372 vmcs_write(CPU_EXEC_CTRL0, 4373 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4374 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4375 test_tpr_threshold_values(); 4376 report_prefix_pop(); 4377 } 4378 4379 if (ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES) { 4380 vmcs_write(CPU_EXEC_CTRL0, 4381 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4382 vmcs_write(CPU_EXEC_CTRL1, CPU_VIRT_APIC_ACCESSES); 4383 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4384 test_tpr_threshold_values(); 4385 report_prefix_pop(); 4386 4387 vmcs_write(CPU_EXEC_CTRL0, 4388 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4389 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4390 test_tpr_threshold_values(); 4391 report_prefix_pop(); 4392 } 4393 4394 if ((ctrl_cpu_rev[1].clr & 4395 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) == 4396 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) { 4397 vmcs_write(CPU_EXEC_CTRL0, 4398 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4399 vmcs_write(CPU_EXEC_CTRL1, 4400 CPU_VINTD | CPU_VIRT_APIC_ACCESSES); 4401 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4402 test_tpr_threshold_values(); 4403 report_prefix_pop(); 4404 4405 vmcs_write(CPU_EXEC_CTRL0, 4406 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4407 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4408 test_tpr_threshold_values(); 4409 report_prefix_pop(); 4410 } 4411 4412 vmcs_write(CPU_EXEC_CTRL1, secondary); 4413 vmcs_write(CPU_EXEC_CTRL0, primary); 4414 } 4415 4416 /* 4417 * This test verifies the following two vmentry checks: 4418 * 4419 * If the "NMI exiting" VM-execution control is 0, "Virtual NMIs" 4420 * VM-execution control must be 0. 4421 * [Intel SDM] 4422 * 4423 * If the “virtual NMIs” VM-execution control is 0, the “NMI-window 4424 * exiting” VM-execution control must be 0. 4425 * [Intel SDM] 4426 */ 4427 static void test_nmi_ctrls(void) 4428 { 4429 u32 pin_ctrls, cpu_ctrls0, test_pin_ctrls, test_cpu_ctrls0; 4430 4431 if ((ctrl_pin_rev.clr & (PIN_NMI | PIN_VIRT_NMI)) != 4432 (PIN_NMI | PIN_VIRT_NMI)) { 4433 test_skip("NMI exiting and Virtual NMIs are not supported !"); 4434 return; 4435 } 4436 4437 /* Save the controls so that we can restore them after our tests */ 4438 pin_ctrls = vmcs_read(PIN_CONTROLS); 4439 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 4440 4441 test_pin_ctrls = pin_ctrls & ~(PIN_NMI | PIN_VIRT_NMI); 4442 test_cpu_ctrls0 = cpu_ctrls0 & ~CPU_NMI_WINDOW; 4443 4444 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4445 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs disabled"); 4446 test_vmx_controls(true, false); 4447 report_prefix_pop(); 4448 4449 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_VIRT_NMI); 4450 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs enabled"); 4451 test_vmx_controls(false, false); 4452 report_prefix_pop(); 4453 4454 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4455 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs enabled"); 4456 test_vmx_controls(true, false); 4457 report_prefix_pop(); 4458 4459 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_NMI); 4460 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs disabled"); 4461 test_vmx_controls(true, false); 4462 report_prefix_pop(); 4463 4464 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 4465 report_info("NMI-window exiting is not supported, skipping..."); 4466 goto done; 4467 } 4468 4469 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4470 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4471 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting enabled"); 4472 test_vmx_controls(false, false); 4473 report_prefix_pop(); 4474 4475 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4476 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4477 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting disabled"); 4478 test_vmx_controls(true, false); 4479 report_prefix_pop(); 4480 4481 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4482 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4483 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting enabled"); 4484 test_vmx_controls(true, false); 4485 report_prefix_pop(); 4486 4487 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4488 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4489 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting disabled"); 4490 test_vmx_controls(true, false); 4491 report_prefix_pop(); 4492 4493 /* Restore the controls to their original values */ 4494 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 4495 done: 4496 vmcs_write(PIN_CONTROLS, pin_ctrls); 4497 } 4498 4499 static void test_eptp_ad_bit(u64 eptp, bool ctrl) 4500 { 4501 vmcs_write(EPTP, eptp); 4502 report_prefix_pushf("Enable-EPT enabled; EPT accessed and dirty flag %s", 4503 (eptp & EPTP_AD_FLAG) ? "1": "0"); 4504 test_vmx_controls(ctrl, false); 4505 report_prefix_pop(); 4506 4507 } 4508 4509 /* 4510 * 1. If the "enable EPT" VM-execution control is 1, the "EPTP VM-execution" 4511 * control field must satisfy the following checks: 4512 * 4513 * - The EPT memory type (bits 2:0) must be a value supported by the 4514 * processor as indicated in the IA32_VMX_EPT_VPID_CAP MSR. 4515 * - Bits 5:3 (1 less than the EPT page-walk length) must be 3, 4516 * indicating an EPT page-walk length of 4. 4517 * - Bit 6 (enable bit for accessed and dirty flags for EPT) must be 4518 * 0 if bit 21 of the IA32_VMX_EPT_VPID_CAP MSR is read as 0, 4519 * indicating that the processor does not support accessed and dirty 4520 * dirty flags for EPT. 4521 * - Reserved bits 11:7 and 63:N (where N is the processor's 4522 * physical-address width) must all be 0. 4523 * 4524 * 2. If the "unrestricted guest" VM-execution control is 1, the 4525 * "enable EPT" VM-execution control must also be 1. 4526 */ 4527 static void test_ept_eptp(void) 4528 { 4529 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4530 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4531 u64 eptp_saved = vmcs_read(EPTP); 4532 u32 primary = primary_saved; 4533 u32 secondary = secondary_saved; 4534 u64 msr, eptp = eptp_saved; 4535 bool un_cache = false; 4536 bool wr_bk = false; 4537 bool ctrl; 4538 u32 i, maxphysaddr; 4539 u64 j, resv_bits_mask = 0; 4540 4541 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4542 (ctrl_cpu_rev[1].clr & CPU_EPT))) { 4543 test_skip("\"CPU secondary\" and/or \"enable EPT\" execution controls are not supported !"); 4544 return; 4545 } 4546 4547 /* 4548 * Memory type (bits 2:0) 4549 */ 4550 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 4551 if (msr & EPT_CAP_UC) 4552 un_cache = true; 4553 if (msr & EPT_CAP_WB) 4554 wr_bk = true; 4555 4556 primary |= CPU_SECONDARY; 4557 vmcs_write(CPU_EXEC_CTRL0, primary); 4558 secondary |= CPU_EPT; 4559 vmcs_write(CPU_EXEC_CTRL1, secondary); 4560 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4561 (3ul << EPTP_PG_WALK_LEN_SHIFT); 4562 vmcs_write(EPTP, eptp); 4563 4564 for (i = 0; i < 8; i++) { 4565 if (i == 0) { 4566 if (un_cache) { 4567 report_info("EPT paging structure memory-type is Un-cacheable\n"); 4568 ctrl = true; 4569 } else { 4570 ctrl = false; 4571 } 4572 } else if (i == 6) { 4573 if (wr_bk) { 4574 report_info("EPT paging structure memory-type is Write-back\n"); 4575 ctrl = true; 4576 } else { 4577 ctrl = false; 4578 } 4579 } else { 4580 ctrl = false; 4581 } 4582 4583 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | i; 4584 vmcs_write(EPTP, eptp); 4585 report_prefix_pushf("Enable-EPT enabled; EPT memory type %lu", 4586 eptp & EPT_MEM_TYPE_MASK); 4587 test_vmx_controls(ctrl, false); 4588 report_prefix_pop(); 4589 } 4590 4591 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | 6ul; 4592 4593 /* 4594 * Page walk length (bits 5:3) 4595 */ 4596 for (i = 0; i < 8; i++) { 4597 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4598 (i << EPTP_PG_WALK_LEN_SHIFT); 4599 if (i == 3) 4600 ctrl = true; 4601 else 4602 ctrl = false; 4603 4604 vmcs_write(EPTP, eptp); 4605 report_prefix_pushf("Enable-EPT enabled; EPT page walk length %lu", 4606 eptp & EPTP_PG_WALK_LEN_MASK); 4607 test_vmx_controls(ctrl, false); 4608 report_prefix_pop(); 4609 } 4610 4611 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4612 3ul << EPTP_PG_WALK_LEN_SHIFT; 4613 4614 /* 4615 * Accessed and dirty flag (bit 6) 4616 */ 4617 if (msr & EPT_CAP_AD_FLAG) { 4618 report_info("Processor supports accessed and dirty flag"); 4619 eptp &= ~EPTP_AD_FLAG; 4620 test_eptp_ad_bit(eptp, true); 4621 4622 eptp |= EPTP_AD_FLAG; 4623 test_eptp_ad_bit(eptp, true); 4624 } else { 4625 report_info("Processor does not supports accessed and dirty flag"); 4626 eptp &= ~EPTP_AD_FLAG; 4627 test_eptp_ad_bit(eptp, true); 4628 4629 eptp |= EPTP_AD_FLAG; 4630 test_eptp_ad_bit(eptp, false); 4631 } 4632 4633 /* 4634 * Reserved bits [11:7] and [63:N] 4635 */ 4636 for (i = 0; i < 32; i++) { 4637 if (i == 0) 4638 ctrl = true; 4639 else 4640 ctrl = false; 4641 4642 eptp = (eptp & 4643 ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)) | 4644 (i << EPTP_RESERV_BITS_SHIFT); 4645 vmcs_write(EPTP, eptp); 4646 report_prefix_pushf("Enable-EPT enabled; reserved bits [11:7] %lu", 4647 (eptp >> EPTP_RESERV_BITS_SHIFT) & 4648 EPTP_RESERV_BITS_MASK); 4649 test_vmx_controls(ctrl, false); 4650 report_prefix_pop(); 4651 } 4652 4653 eptp = (eptp & ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)); 4654 4655 maxphysaddr = cpuid_maxphyaddr(); 4656 for (i = 0; i < (63 - maxphysaddr + 1); i++) { 4657 resv_bits_mask |= 1ul << i; 4658 } 4659 4660 for (j = 0; j < (63 - maxphysaddr + 1); j++) { 4661 if (j == 0) 4662 ctrl = true; 4663 else 4664 ctrl = false; 4665 4666 eptp = (eptp & ~(resv_bits_mask << maxphysaddr)) | 4667 (j << maxphysaddr); 4668 vmcs_write(EPTP, eptp); 4669 report_prefix_pushf("Enable-EPT enabled; reserved bits [63:N] %lu", 4670 (eptp >> maxphysaddr) & resv_bits_mask); 4671 test_vmx_controls(ctrl, false); 4672 report_prefix_pop(); 4673 } 4674 4675 secondary &= ~(CPU_EPT | CPU_URG); 4676 vmcs_write(CPU_EXEC_CTRL1, secondary); 4677 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest disabled"); 4678 test_vmx_controls(true, false); 4679 report_prefix_pop(); 4680 4681 secondary |= CPU_URG; 4682 vmcs_write(CPU_EXEC_CTRL1, secondary); 4683 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest enabled"); 4684 test_vmx_controls(false, false); 4685 report_prefix_pop(); 4686 4687 secondary |= CPU_EPT; 4688 setup_ept(false); 4689 vmcs_write(CPU_EXEC_CTRL1, secondary); 4690 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest enabled"); 4691 test_vmx_controls(true, false); 4692 report_prefix_pop(); 4693 4694 secondary &= ~CPU_URG; 4695 vmcs_write(CPU_EXEC_CTRL1, secondary); 4696 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest disabled"); 4697 test_vmx_controls(true, false); 4698 report_prefix_pop(); 4699 4700 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4701 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4702 vmcs_write(EPTP, eptp_saved); 4703 } 4704 4705 /* 4706 * If the 'enable PML' VM-execution control is 1, the 'enable EPT' 4707 * VM-execution control must also be 1. In addition, the PML address 4708 * must satisfy the following checks: 4709 * 4710 * * Bits 11:0 of the address must be 0. 4711 * * The address should not set any bits beyond the processor's 4712 * physical-address width. 4713 * 4714 * [Intel SDM] 4715 */ 4716 static void test_pml(void) 4717 { 4718 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4719 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4720 u32 primary = primary_saved; 4721 u32 secondary = secondary_saved; 4722 4723 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4724 (ctrl_cpu_rev[1].clr & CPU_EPT) && (ctrl_cpu_rev[1].clr & CPU_PML))) { 4725 test_skip("\"Secondary execution\" control or \"enable EPT\" control or \"enable PML\" control is not supported !"); 4726 return; 4727 } 4728 4729 primary |= CPU_SECONDARY; 4730 vmcs_write(CPU_EXEC_CTRL0, primary); 4731 secondary &= ~(CPU_PML | CPU_EPT); 4732 vmcs_write(CPU_EXEC_CTRL1, secondary); 4733 report_prefix_pushf("enable-PML disabled, enable-EPT disabled"); 4734 test_vmx_controls(true, false); 4735 report_prefix_pop(); 4736 4737 secondary |= CPU_PML; 4738 vmcs_write(CPU_EXEC_CTRL1, secondary); 4739 report_prefix_pushf("enable-PML enabled, enable-EPT disabled"); 4740 test_vmx_controls(false, false); 4741 report_prefix_pop(); 4742 4743 secondary |= CPU_EPT; 4744 setup_ept(false); 4745 vmcs_write(CPU_EXEC_CTRL1, secondary); 4746 report_prefix_pushf("enable-PML enabled, enable-EPT enabled"); 4747 test_vmx_controls(true, false); 4748 report_prefix_pop(); 4749 4750 secondary &= ~CPU_PML; 4751 vmcs_write(CPU_EXEC_CTRL1, secondary); 4752 report_prefix_pushf("enable-PML disabled, enable EPT enabled"); 4753 test_vmx_controls(true, false); 4754 report_prefix_pop(); 4755 4756 test_vmcs_addr_reference(CPU_PML, PMLADDR, "PML address", "PML", 4757 PAGE_SIZE, false, false); 4758 4759 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4760 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4761 } 4762 4763 /* 4764 * If the "activate VMX-preemption timer" VM-execution control is 0, the 4765 * the "save VMX-preemption timer value" VM-exit control must also be 0. 4766 * 4767 * [Intel SDM] 4768 */ 4769 static void test_vmx_preemption_timer(void) 4770 { 4771 u32 saved_pin = vmcs_read(PIN_CONTROLS); 4772 u32 saved_exit = vmcs_read(EXI_CONTROLS); 4773 u32 pin = saved_pin; 4774 u32 exit = saved_exit; 4775 4776 if (!((ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) || 4777 (ctrl_pin_rev.clr & PIN_PREEMPT))) { 4778 printf("\"Save-VMX-preemption-timer\" control and/or \"Enable-VMX-preemption-timer\" control is not supported\n"); 4779 return; 4780 } 4781 4782 pin |= PIN_PREEMPT; 4783 vmcs_write(PIN_CONTROLS, pin); 4784 exit &= ~EXI_SAVE_PREEMPT; 4785 vmcs_write(EXI_CONTROLS, exit); 4786 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer disabled"); 4787 test_vmx_controls(true, false); 4788 report_prefix_pop(); 4789 4790 exit |= EXI_SAVE_PREEMPT; 4791 vmcs_write(EXI_CONTROLS, exit); 4792 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer enabled"); 4793 test_vmx_controls(true, false); 4794 report_prefix_pop(); 4795 4796 pin &= ~PIN_PREEMPT; 4797 vmcs_write(PIN_CONTROLS, pin); 4798 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer enabled"); 4799 test_vmx_controls(false, false); 4800 report_prefix_pop(); 4801 4802 exit &= ~EXI_SAVE_PREEMPT; 4803 vmcs_write(EXI_CONTROLS, exit); 4804 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer disabled"); 4805 test_vmx_controls(true, false); 4806 report_prefix_pop(); 4807 4808 vmcs_write(PIN_CONTROLS, saved_pin); 4809 vmcs_write(EXI_CONTROLS, saved_exit); 4810 } 4811 4812 /* 4813 * Tests for VM-execution control fields 4814 */ 4815 static void test_vm_execution_ctls(void) 4816 { 4817 test_pin_based_ctls(); 4818 test_primary_processor_based_ctls(); 4819 test_secondary_processor_based_ctls(); 4820 test_cr3_targets(); 4821 test_io_bitmaps(); 4822 test_msr_bitmap(); 4823 test_apic_ctls(); 4824 test_tpr_threshold(); 4825 test_nmi_ctrls(); 4826 test_pml(); 4827 test_vpid(); 4828 test_ept_eptp(); 4829 test_vmx_preemption_timer(); 4830 } 4831 4832 /* 4833 * The following checks are performed for the VM-entry MSR-load address if 4834 * the VM-entry MSR-load count field is non-zero: 4835 * 4836 * - The lower 4 bits of the VM-entry MSR-load address must be 0. 4837 * The address should not set any bits beyond the processor’s 4838 * physical-address width. 4839 * 4840 * - The address of the last byte in the VM-entry MSR-load area 4841 * should not set any bits beyond the processor’s physical-address 4842 * width. The address of this last byte is VM-entry MSR-load address 4843 * + (MSR count * 16) - 1. (The arithmetic used for the computation 4844 * uses more bits than the processor’s physical-address width.) 4845 * 4846 * 4847 * [Intel SDM] 4848 */ 4849 static void test_entry_msr_load(void) 4850 { 4851 entry_msr_load = alloc_page(); 4852 u64 tmp; 4853 u32 entry_msr_ld_cnt = 1; 4854 int i; 4855 u32 addr_len = 64; 4856 4857 vmcs_write(ENT_MSR_LD_CNT, entry_msr_ld_cnt); 4858 4859 /* Check first 4 bits of VM-entry MSR-load address */ 4860 for (i = 0; i < 4; i++) { 4861 tmp = (u64)entry_msr_load | 1ull << i; 4862 vmcs_write(ENTER_MSR_LD_ADDR, tmp); 4863 report_prefix_pushf("VM-entry MSR-load addr [4:0] %lx", 4864 tmp & 0xf); 4865 test_vmx_controls(false, false); 4866 report_prefix_pop(); 4867 } 4868 4869 if (basic.val & (1ul << 48)) 4870 addr_len = 32; 4871 4872 test_vmcs_addr_values("VM-entry-MSR-load address", 4873 ENTER_MSR_LD_ADDR, 16, false, false, 4874 4, addr_len - 1); 4875 4876 /* 4877 * Check last byte of VM-entry MSR-load address 4878 */ 4879 entry_msr_load = (struct vmx_msr_entry *)((u64)entry_msr_load & ~0xf); 4880 4881 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 4882 i < 64; i++) { 4883 tmp = ((u64)entry_msr_load + entry_msr_ld_cnt * 16 - 1) | 4884 1ul << i; 4885 vmcs_write(ENTER_MSR_LD_ADDR, 4886 tmp - (entry_msr_ld_cnt * 16 - 1)); 4887 test_vmx_controls(false, false); 4888 } 4889 4890 vmcs_write(ENT_MSR_LD_CNT, 2); 4891 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 4892 test_vmx_controls(false, false); 4893 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 4894 test_vmx_controls(true, false); 4895 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 4896 test_vmx_controls(true, false); 4897 } 4898 4899 /* 4900 * Tests for VM-entry control fields 4901 */ 4902 static void test_vm_entry_ctls(void) 4903 { 4904 test_invalid_event_injection(); 4905 test_entry_msr_load(); 4906 } 4907 4908 /* 4909 * The following checks are performed for the VM-exit MSR-store address if 4910 * the VM-exit MSR-store count field is non-zero: 4911 * 4912 * - The lower 4 bits of the VM-exit MSR-store address must be 0. 4913 * The address should not set any bits beyond the processor’s 4914 * physical-address width. 4915 * 4916 * - The address of the last byte in the VM-exit MSR-store area 4917 * should not set any bits beyond the processor’s physical-address 4918 * width. The address of this last byte is VM-exit MSR-store address 4919 * + (MSR count * 16) - 1. (The arithmetic used for the computation 4920 * uses more bits than the processor’s physical-address width.) 4921 * 4922 * If IA32_VMX_BASIC[48] is read as 1, neither address should set any bits 4923 * in the range 63:32. 4924 * 4925 * [Intel SDM] 4926 */ 4927 static void test_exit_msr_store(void) 4928 { 4929 exit_msr_store = alloc_page(); 4930 u64 tmp; 4931 u32 exit_msr_st_cnt = 1; 4932 int i; 4933 u32 addr_len = 64; 4934 4935 vmcs_write(EXI_MSR_ST_CNT, exit_msr_st_cnt); 4936 4937 /* Check first 4 bits of VM-exit MSR-store address */ 4938 for (i = 0; i < 4; i++) { 4939 tmp = (u64)exit_msr_store | 1ull << i; 4940 vmcs_write(EXIT_MSR_ST_ADDR, tmp); 4941 report_prefix_pushf("VM-exit MSR-store addr [4:0] %lx", 4942 tmp & 0xf); 4943 test_vmx_controls(false, false); 4944 report_prefix_pop(); 4945 } 4946 4947 if (basic.val & (1ul << 48)) 4948 addr_len = 32; 4949 4950 test_vmcs_addr_values("VM-exit-MSR-store address", 4951 EXIT_MSR_ST_ADDR, 16, false, false, 4952 4, addr_len - 1); 4953 4954 /* 4955 * Check last byte of VM-exit MSR-store address 4956 */ 4957 exit_msr_store = (struct vmx_msr_entry *)((u64)exit_msr_store & ~0xf); 4958 4959 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 4960 i < 64; i++) { 4961 tmp = ((u64)exit_msr_store + exit_msr_st_cnt * 16 - 1) | 4962 1ul << i; 4963 vmcs_write(EXIT_MSR_ST_ADDR, 4964 tmp - (exit_msr_st_cnt * 16 - 1)); 4965 test_vmx_controls(false, false); 4966 } 4967 4968 vmcs_write(EXI_MSR_ST_CNT, 2); 4969 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 4970 test_vmx_controls(false, false); 4971 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 4972 test_vmx_controls(true, false); 4973 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 4974 test_vmx_controls(true, false); 4975 } 4976 4977 /* 4978 * Tests for VM-exit controls 4979 */ 4980 static void test_vm_exit_ctls(void) 4981 { 4982 test_exit_msr_store(); 4983 } 4984 4985 /* 4986 * Check that the virtual CPU checks all of the VMX controls as 4987 * documented in the Intel SDM. 4988 */ 4989 static void vmx_controls_test(void) 4990 { 4991 /* 4992 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 4993 * fail due to invalid guest state, should we make it that 4994 * far. 4995 */ 4996 vmcs_write(GUEST_RFLAGS, 0); 4997 4998 test_vm_execution_ctls(); 4999 test_vm_entry_ctls(); 5000 test_vm_exit_ctls(); 5001 } 5002 5003 static bool valid_vmcs_for_vmentry(void) 5004 { 5005 struct vmcs *current_vmcs = NULL; 5006 5007 if (vmcs_save(¤t_vmcs)) 5008 return false; 5009 5010 return current_vmcs && !current_vmcs->hdr.shadow_vmcs; 5011 } 5012 5013 static void try_vmentry_in_movss_shadow(void) 5014 { 5015 u32 vm_inst_err; 5016 u32 flags; 5017 bool early_failure = false; 5018 u32 expected_flags = X86_EFLAGS_FIXED; 5019 bool valid_vmcs = valid_vmcs_for_vmentry(); 5020 5021 expected_flags |= valid_vmcs ? X86_EFLAGS_ZF : X86_EFLAGS_CF; 5022 5023 /* 5024 * Indirectly set VM_INST_ERR to 12 ("VMREAD/VMWRITE from/to 5025 * unsupported VMCS component"). 5026 */ 5027 vmcs_write(~0u, 0); 5028 5029 __asm__ __volatile__ ("mov %[host_rsp], %%edx;" 5030 "vmwrite %%rsp, %%rdx;" 5031 "mov 0f, %%rax;" 5032 "mov %[host_rip], %%edx;" 5033 "vmwrite %%rax, %%rdx;" 5034 "mov $-1, %%ah;" 5035 "sahf;" 5036 "mov %%ss, %%ax;" 5037 "mov %%ax, %%ss;" 5038 "vmlaunch;" 5039 "mov $1, %[early_failure];" 5040 "0: lahf;" 5041 "movzbl %%ah, %[flags]" 5042 : [early_failure] "+r" (early_failure), 5043 [flags] "=&a" (flags) 5044 : [host_rsp] "i" (HOST_RSP), 5045 [host_rip] "i" (HOST_RIP) 5046 : "rdx", "cc", "memory"); 5047 vm_inst_err = vmcs_read(VMX_INST_ERROR); 5048 5049 report("Early VM-entry failure", early_failure); 5050 report("RFLAGS[8:0] is %x (actual %x)", flags == expected_flags, 5051 expected_flags, flags); 5052 if (valid_vmcs) 5053 report("VM-instruction error is %d (actual %d)", 5054 vm_inst_err == VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, 5055 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, vm_inst_err); 5056 } 5057 5058 static void vmentry_movss_shadow_test(void) 5059 { 5060 struct vmcs *orig_vmcs; 5061 5062 TEST_ASSERT(!vmcs_save(&orig_vmcs)); 5063 5064 /* 5065 * Set the launched flag on the current VMCS to verify the correct 5066 * error priority, below. 5067 */ 5068 test_set_guest(v2_null_test_guest); 5069 enter_guest(); 5070 5071 /* 5072 * With bit 1 of the guest's RFLAGS clear, VM-entry should 5073 * fail due to invalid guest state (if we make it that far). 5074 */ 5075 vmcs_write(GUEST_RFLAGS, 0); 5076 5077 /* 5078 * "VM entry with events blocked by MOV SS" takes precedence over 5079 * "VMLAUNCH with non-clear VMCS." 5080 */ 5081 report_prefix_push("valid current-VMCS"); 5082 try_vmentry_in_movss_shadow(); 5083 report_prefix_pop(); 5084 5085 /* 5086 * VMfailInvalid takes precedence over "VM entry with events 5087 * blocked by MOV SS." 5088 */ 5089 TEST_ASSERT(!vmcs_clear(orig_vmcs)); 5090 report_prefix_push("no current-VMCS"); 5091 try_vmentry_in_movss_shadow(); 5092 report_prefix_pop(); 5093 5094 TEST_ASSERT(!make_vmcs_current(orig_vmcs)); 5095 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 5096 } 5097 5098 #define X86_FEATURE_PCID (1 << 17) 5099 #define X86_FEATURE_MCE (1 << 7) 5100 5101 static int write_cr4_checking(unsigned long val) 5102 { 5103 asm volatile(ASM_TRY("1f") 5104 "mov %0, %%cr4\n\t" 5105 "1:": : "r" (val)); 5106 return exception_vector(); 5107 } 5108 5109 static void vmx_cr_load_test(void) 5110 { 5111 struct cpuid _cpuid = cpuid(1); 5112 unsigned long cr4 = read_cr4(), cr3 = read_cr3(); 5113 5114 if (!(_cpuid.c & X86_FEATURE_PCID)) { 5115 report_skip("PCID not detected"); 5116 return; 5117 } 5118 if (!(_cpuid.d & X86_FEATURE_MCE)) { 5119 report_skip("MCE not detected"); 5120 return; 5121 } 5122 5123 TEST_ASSERT(!(cr4 & (X86_CR4_PCIDE | X86_CR4_MCE))); 5124 TEST_ASSERT(!(cr3 & X86_CR3_PCID_MASK)); 5125 5126 /* Enable PCID for L1. */ 5127 cr4 |= X86_CR4_PCIDE; 5128 cr3 |= 0x1; 5129 TEST_ASSERT(!write_cr4_checking(cr4)); 5130 write_cr3(cr3); 5131 5132 test_set_guest(v2_null_test_guest); 5133 vmcs_write(HOST_CR4, cr4); 5134 vmcs_write(HOST_CR3, cr3); 5135 enter_guest(); 5136 5137 /* 5138 * No exception is expected. 5139 * 5140 * NB. KVM loads the last guest write to CR4 into CR4 read 5141 * shadow. In order to trigger an exit to KVM, we can set a 5142 * bit that was zero in the above CR4 write and is owned by 5143 * KVM. We choose to set CR4.MCE, which shall have no side 5144 * effect because normally no guest MCE (e.g., as the result 5145 * of bad memory) would happen during this test. 5146 */ 5147 TEST_ASSERT(!write_cr4_checking(cr4 | X86_CR4_MCE)); 5148 5149 /* Cleanup L1 state: disable PCID. */ 5150 write_cr3(cr3 & ~X86_CR3_PCID_MASK); 5151 TEST_ASSERT(!write_cr4_checking(cr4 & ~X86_CR4_PCIDE)); 5152 } 5153 5154 static void vmx_nm_test_guest(void) 5155 { 5156 write_cr0(read_cr0() | X86_CR0_TS); 5157 asm volatile("fnop"); 5158 } 5159 5160 static void check_nm_exit(const char *test) 5161 { 5162 u32 reason = vmcs_read(EXI_REASON); 5163 u32 intr_info = vmcs_read(EXI_INTR_INFO); 5164 const u32 expected = INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 5165 NM_VECTOR; 5166 5167 report("%s", reason == VMX_EXC_NMI && intr_info == expected, test); 5168 } 5169 5170 /* 5171 * This test checks that: 5172 * 5173 * (a) If L2 launches with CR0.TS clear, but later sets CR0.TS, then 5174 * a subsequent #NM VM-exit is reflected to L1. 5175 * 5176 * (b) If L2 launches with CR0.TS clear and CR0.EM set, then a 5177 * subsequent #NM VM-exit is reflected to L1. 5178 */ 5179 static void vmx_nm_test(void) 5180 { 5181 unsigned long cr0 = read_cr0(); 5182 5183 test_set_guest(vmx_nm_test_guest); 5184 5185 /* 5186 * L1 wants to intercept #NM exceptions encountered in L2. 5187 */ 5188 vmcs_write(EXC_BITMAP, 1 << NM_VECTOR); 5189 5190 /* 5191 * Launch L2 with CR0.TS clear, but don't claim host ownership of 5192 * any CR0 bits. L2 will set CR0.TS and then try to execute fnop, 5193 * which will raise #NM. L0 should reflect the #NM VM-exit to L1. 5194 */ 5195 vmcs_write(CR0_MASK, 0); 5196 vmcs_write(GUEST_CR0, cr0 & ~X86_CR0_TS); 5197 enter_guest(); 5198 check_nm_exit("fnop with CR0.TS set in L2 triggers #NM VM-exit to L1"); 5199 5200 /* 5201 * Re-enter L2 at the fnop instruction, with CR0.TS clear but 5202 * CR0.EM set. The fnop will still raise #NM, and L0 should 5203 * reflect the #NM VM-exit to L1. 5204 */ 5205 vmcs_write(GUEST_CR0, (cr0 & ~X86_CR0_TS) | X86_CR0_EM); 5206 enter_guest(); 5207 check_nm_exit("fnop with CR0.EM set in L2 triggers #NM VM-exit to L1"); 5208 5209 /* 5210 * Re-enter L2 at the fnop instruction, with both CR0.TS and 5211 * CR0.EM clear. There will be no #NM, and the L2 guest should 5212 * exit normally. 5213 */ 5214 vmcs_write(GUEST_CR0, cr0 & ~(X86_CR0_TS | X86_CR0_EM)); 5215 enter_guest(); 5216 } 5217 5218 bool vmx_pending_event_ipi_fired; 5219 static void vmx_pending_event_ipi_isr(isr_regs_t *regs) 5220 { 5221 vmx_pending_event_ipi_fired = true; 5222 eoi(); 5223 } 5224 5225 bool vmx_pending_event_guest_run; 5226 static void vmx_pending_event_guest(void) 5227 { 5228 vmcall(); 5229 vmx_pending_event_guest_run = true; 5230 } 5231 5232 static void vmx_pending_event_test_core(bool guest_hlt) 5233 { 5234 int ipi_vector = 0xf1; 5235 5236 vmx_pending_event_ipi_fired = false; 5237 handle_irq(ipi_vector, vmx_pending_event_ipi_isr); 5238 5239 vmx_pending_event_guest_run = false; 5240 test_set_guest(vmx_pending_event_guest); 5241 5242 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 5243 5244 enter_guest(); 5245 skip_exit_vmcall(); 5246 5247 if (guest_hlt) 5248 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 5249 5250 irq_disable(); 5251 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | 5252 APIC_DM_FIXED | ipi_vector, 5253 0); 5254 5255 enter_guest(); 5256 5257 assert_exit_reason(VMX_EXTINT); 5258 report("Guest did not run before host received IPI", 5259 !vmx_pending_event_guest_run); 5260 5261 irq_enable(); 5262 asm volatile ("nop"); 5263 irq_disable(); 5264 report("Got pending interrupt after IRQ enabled", 5265 vmx_pending_event_ipi_fired); 5266 5267 if (guest_hlt) 5268 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 5269 5270 enter_guest(); 5271 report("Guest finished running when no interrupt", 5272 vmx_pending_event_guest_run); 5273 } 5274 5275 static void vmx_pending_event_test(void) 5276 { 5277 vmx_pending_event_test_core(false); 5278 } 5279 5280 static void vmx_pending_event_hlt_test(void) 5281 { 5282 vmx_pending_event_test_core(true); 5283 } 5284 5285 static int vmx_window_test_ud_count; 5286 5287 static void vmx_window_test_ud_handler(struct ex_regs *regs) 5288 { 5289 vmx_window_test_ud_count++; 5290 } 5291 5292 static void vmx_nmi_window_test_guest(void) 5293 { 5294 handle_exception(UD_VECTOR, vmx_window_test_ud_handler); 5295 5296 asm volatile("vmcall\n\t" 5297 "nop\n\t"); 5298 5299 handle_exception(UD_VECTOR, NULL); 5300 } 5301 5302 static void verify_nmi_window_exit(u64 rip) 5303 { 5304 u32 exit_reason = vmcs_read(EXI_REASON); 5305 5306 report("Exit reason (%d) is 'NMI window'", 5307 exit_reason == VMX_NMI_WINDOW, exit_reason); 5308 report("RIP (%#lx) is %#lx", vmcs_read(GUEST_RIP) == rip, 5309 vmcs_read(GUEST_RIP), rip); 5310 report("Activity state (%ld) is 'ACTIVE'", 5311 vmcs_read(GUEST_ACTV_STATE) == ACTV_ACTIVE, 5312 vmcs_read(GUEST_ACTV_STATE)); 5313 } 5314 5315 static void vmx_nmi_window_test(void) 5316 { 5317 u64 nop_addr; 5318 void *ud_fault_addr = get_idt_addr(&boot_idt[UD_VECTOR]); 5319 5320 if (!(ctrl_pin_rev.clr & PIN_VIRT_NMI)) { 5321 report_skip("CPU does not support the \"Virtual NMIs\" VM-execution control."); 5322 return; 5323 } 5324 5325 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 5326 report_skip("CPU does not support the \"NMI-window exiting\" VM-execution control."); 5327 return; 5328 } 5329 5330 vmx_window_test_ud_count = 0; 5331 5332 report_prefix_push("NMI-window"); 5333 test_set_guest(vmx_nmi_window_test_guest); 5334 vmcs_set_bits(PIN_CONTROLS, PIN_VIRT_NMI); 5335 enter_guest(); 5336 skip_exit_vmcall(); 5337 nop_addr = vmcs_read(GUEST_RIP); 5338 5339 /* 5340 * Ask for "NMI-window exiting," and expect an immediate VM-exit. 5341 * RIP will not advance. 5342 */ 5343 report_prefix_push("active, no blocking"); 5344 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 5345 enter_guest(); 5346 verify_nmi_window_exit(nop_addr); 5347 report_prefix_pop(); 5348 5349 /* 5350 * Ask for "NMI-window exiting" in a MOV-SS shadow, and expect 5351 * a VM-exit on the next instruction after the nop. (The nop 5352 * is one byte.) 5353 */ 5354 report_prefix_push("active, blocking by MOV-SS"); 5355 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 5356 enter_guest(); 5357 verify_nmi_window_exit(nop_addr + 1); 5358 report_prefix_pop(); 5359 5360 /* 5361 * Ask for "NMI-window exiting" (with event injection), and 5362 * expect a VM-exit after the event is injected. (RIP should 5363 * be at the address specified in the IDT entry for #UD.) 5364 */ 5365 report_prefix_push("active, no blocking, injecting #UD"); 5366 vmcs_write(ENT_INTR_INFO, 5367 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | UD_VECTOR); 5368 enter_guest(); 5369 verify_nmi_window_exit((u64)ud_fault_addr); 5370 report_prefix_pop(); 5371 5372 /* 5373 * Ask for "NMI-window exiting" with NMI blocking, and expect 5374 * a VM-exit after the next IRET (i.e. after the #UD handler 5375 * returns). So, RIP should be back at one byte past the nop. 5376 */ 5377 report_prefix_push("active, blocking by NMI"); 5378 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_NMI); 5379 enter_guest(); 5380 verify_nmi_window_exit(nop_addr + 1); 5381 report("#UD handler executed once (actual %d times)", 5382 vmx_window_test_ud_count == 1, 5383 vmx_window_test_ud_count); 5384 report_prefix_pop(); 5385 5386 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 5387 report_skip("CPU does not support activity state HLT."); 5388 } else { 5389 /* 5390 * Ask for "NMI-window exiting" when entering activity 5391 * state HLT, and expect an immediate VM-exit. RIP is 5392 * still one byte past the nop. 5393 */ 5394 report_prefix_push("halted, no blocking"); 5395 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 5396 enter_guest(); 5397 verify_nmi_window_exit(nop_addr + 1); 5398 report_prefix_pop(); 5399 5400 /* 5401 * Ask for "NMI-window exiting" when entering activity 5402 * state HLT (with event injection), and expect a 5403 * VM-exit after the event is injected. (RIP should be 5404 * at the address specified in the IDT entry for #UD.) 5405 */ 5406 report_prefix_push("halted, no blocking, injecting #UD"); 5407 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 5408 vmcs_write(ENT_INTR_INFO, 5409 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 5410 UD_VECTOR); 5411 enter_guest(); 5412 verify_nmi_window_exit((u64)ud_fault_addr); 5413 report_prefix_pop(); 5414 } 5415 5416 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 5417 enter_guest(); 5418 report_prefix_pop(); 5419 } 5420 5421 static void vmx_intr_window_test_guest(void) 5422 { 5423 handle_exception(UD_VECTOR, vmx_window_test_ud_handler); 5424 5425 /* 5426 * The two consecutive STIs are to ensure that only the first 5427 * one has a shadow. Note that NOP and STI are one byte 5428 * instructions. 5429 */ 5430 asm volatile("vmcall\n\t" 5431 "nop\n\t" 5432 "sti\n\t" 5433 "sti\n\t"); 5434 5435 handle_exception(UD_VECTOR, NULL); 5436 } 5437 5438 static void verify_intr_window_exit(u64 rip) 5439 { 5440 u32 exit_reason = vmcs_read(EXI_REASON); 5441 5442 report("Exit reason (%d) is 'interrupt window'", 5443 exit_reason == VMX_INTR_WINDOW, exit_reason); 5444 report("RIP (%#lx) is %#lx", vmcs_read(GUEST_RIP) == rip, 5445 vmcs_read(GUEST_RIP), rip); 5446 report("Activity state (%ld) is 'ACTIVE'", 5447 vmcs_read(GUEST_ACTV_STATE) == ACTV_ACTIVE, 5448 vmcs_read(GUEST_ACTV_STATE)); 5449 } 5450 5451 static void vmx_intr_window_test(void) 5452 { 5453 u64 vmcall_addr; 5454 u64 nop_addr; 5455 unsigned int orig_ud_gate_type; 5456 void *ud_fault_addr = get_idt_addr(&boot_idt[UD_VECTOR]); 5457 5458 if (!(ctrl_cpu_rev[0].clr & CPU_INTR_WINDOW)) { 5459 report_skip("CPU does not support the \"interrupt-window exiting\" VM-execution control."); 5460 return; 5461 } 5462 5463 /* 5464 * Change the IDT entry for #UD from interrupt gate to trap gate, 5465 * so that it won't clear RFLAGS.IF. We don't want interrupts to 5466 * be disabled after vectoring a #UD. 5467 */ 5468 orig_ud_gate_type = boot_idt[UD_VECTOR].type; 5469 boot_idt[UD_VECTOR].type = 15; 5470 5471 report_prefix_push("interrupt-window"); 5472 test_set_guest(vmx_intr_window_test_guest); 5473 enter_guest(); 5474 assert_exit_reason(VMX_VMCALL); 5475 vmcall_addr = vmcs_read(GUEST_RIP); 5476 5477 /* 5478 * Ask for "interrupt-window exiting" with RFLAGS.IF set and 5479 * no blocking; expect an immediate VM-exit. Note that we have 5480 * not advanced past the vmcall instruction yet, so RIP should 5481 * point to the vmcall instruction. 5482 */ 5483 report_prefix_push("active, no blocking, RFLAGS.IF=1"); 5484 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 5485 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_IF); 5486 enter_guest(); 5487 verify_intr_window_exit(vmcall_addr); 5488 report_prefix_pop(); 5489 5490 /* 5491 * Ask for "interrupt-window exiting" (with event injection) 5492 * with RFLAGS.IF set and no blocking; expect a VM-exit after 5493 * the event is injected. That is, RIP should should be at the 5494 * address specified in the IDT entry for #UD. 5495 */ 5496 report_prefix_push("active, no blocking, RFLAGS.IF=1, injecting #UD"); 5497 vmcs_write(ENT_INTR_INFO, 5498 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | UD_VECTOR); 5499 vmcall_addr = vmcs_read(GUEST_RIP); 5500 enter_guest(); 5501 verify_intr_window_exit((u64)ud_fault_addr); 5502 report_prefix_pop(); 5503 5504 /* 5505 * Let the L2 guest run through the IRET, back to the VMCALL. 5506 * We have to clear the "interrupt-window exiting" 5507 * VM-execution control, or it would just keep causing 5508 * VM-exits. Then, advance past the VMCALL and set the 5509 * "interrupt-window exiting" VM-execution control again. 5510 */ 5511 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 5512 enter_guest(); 5513 skip_exit_vmcall(); 5514 nop_addr = vmcs_read(GUEST_RIP); 5515 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 5516 5517 /* 5518 * Ask for "interrupt-window exiting" in a MOV-SS shadow with 5519 * RFLAGS.IF set, and expect a VM-exit on the next 5520 * instruction. (NOP is one byte.) 5521 */ 5522 report_prefix_push("active, blocking by MOV-SS, RFLAGS.IF=1"); 5523 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 5524 enter_guest(); 5525 verify_intr_window_exit(nop_addr + 1); 5526 report_prefix_pop(); 5527 5528 /* 5529 * Back up to the NOP and ask for "interrupt-window exiting" 5530 * in an STI shadow with RFLAGS.IF set, and expect a VM-exit 5531 * on the next instruction. (NOP is one byte.) 5532 */ 5533 report_prefix_push("active, blocking by STI, RFLAGS.IF=1"); 5534 vmcs_write(GUEST_RIP, nop_addr); 5535 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_STI); 5536 enter_guest(); 5537 verify_intr_window_exit(nop_addr + 1); 5538 report_prefix_pop(); 5539 5540 /* 5541 * Ask for "interrupt-window exiting" with RFLAGS.IF clear, 5542 * and expect a VM-exit on the instruction following the STI 5543 * shadow. Only the first STI (which is one byte past the NOP) 5544 * should have a shadow. The second STI (which is two bytes 5545 * past the NOP) has no shadow. Therefore, the interrupt 5546 * window opens at three bytes past the NOP. 5547 */ 5548 report_prefix_push("active, RFLAGS.IF = 0"); 5549 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 5550 enter_guest(); 5551 verify_intr_window_exit(nop_addr + 3); 5552 report_prefix_pop(); 5553 5554 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 5555 report_skip("CPU does not support activity state HLT."); 5556 } else { 5557 /* 5558 * Ask for "interrupt-window exiting" when entering 5559 * activity state HLT, and expect an immediate 5560 * VM-exit. RIP is still three bytes past the nop. 5561 */ 5562 report_prefix_push("halted, no blocking"); 5563 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 5564 enter_guest(); 5565 verify_intr_window_exit(nop_addr + 3); 5566 report_prefix_pop(); 5567 5568 /* 5569 * Ask for "interrupt-window exiting" when entering 5570 * activity state HLT (with event injection), and 5571 * expect a VM-exit after the event is injected. That 5572 * is, RIP should should be at the address specified 5573 * in the IDT entry for #UD. 5574 */ 5575 report_prefix_push("halted, no blocking, injecting #UD"); 5576 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 5577 vmcs_write(ENT_INTR_INFO, 5578 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 5579 UD_VECTOR); 5580 enter_guest(); 5581 verify_intr_window_exit((u64)ud_fault_addr); 5582 report_prefix_pop(); 5583 } 5584 5585 boot_idt[UD_VECTOR].type = orig_ud_gate_type; 5586 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 5587 enter_guest(); 5588 report_prefix_pop(); 5589 } 5590 5591 #define GUEST_TSC_OFFSET (1u << 30) 5592 5593 static u64 guest_tsc; 5594 5595 static void vmx_store_tsc_test_guest(void) 5596 { 5597 guest_tsc = rdtsc(); 5598 } 5599 5600 /* 5601 * This test ensures that when IA32_TSC is in the VM-exit MSR-store 5602 * list, the value saved is not subject to the TSC offset that is 5603 * applied to RDTSC/RDTSCP/RDMSR(IA32_TSC) in guest execution. 5604 */ 5605 static void vmx_store_tsc_test(void) 5606 { 5607 struct vmx_msr_entry msr_entry = { .index = MSR_IA32_TSC }; 5608 u64 low, high; 5609 5610 if (!(ctrl_cpu_rev[0].clr & CPU_USE_TSC_OFFSET)) { 5611 report_skip("'Use TSC offsetting' not supported"); 5612 return; 5613 } 5614 5615 test_set_guest(vmx_store_tsc_test_guest); 5616 5617 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_USE_TSC_OFFSET); 5618 vmcs_write(EXI_MSR_ST_CNT, 1); 5619 vmcs_write(EXIT_MSR_ST_ADDR, virt_to_phys(&msr_entry)); 5620 vmcs_write(TSC_OFFSET, GUEST_TSC_OFFSET); 5621 5622 low = rdtsc(); 5623 enter_guest(); 5624 high = rdtsc(); 5625 5626 report("RDTSC value in the guest (%lu) is in range [%lu, %lu]", 5627 low + GUEST_TSC_OFFSET <= guest_tsc && 5628 guest_tsc <= high + GUEST_TSC_OFFSET, 5629 guest_tsc, low + GUEST_TSC_OFFSET, high + GUEST_TSC_OFFSET); 5630 report("IA32_TSC value saved in the VM-exit MSR-store list (%lu) is in range [%lu, %lu]", 5631 low <= msr_entry.value && msr_entry.value <= high, 5632 msr_entry.value, low, high); 5633 } 5634 5635 static void vmx_db_test_guest(void) 5636 { 5637 /* 5638 * For a hardware generated single-step #DB. 5639 */ 5640 asm volatile("vmcall;" 5641 "nop;" 5642 ".Lpost_nop:"); 5643 /* 5644 * ...in a MOVSS shadow, with pending debug exceptions. 5645 */ 5646 asm volatile("vmcall;" 5647 "nop;" 5648 ".Lpost_movss_nop:"); 5649 /* 5650 * For an L0 synthesized single-step #DB. (L0 intercepts WBINVD and 5651 * emulates it in software.) 5652 */ 5653 asm volatile("vmcall;" 5654 "wbinvd;" 5655 ".Lpost_wbinvd:"); 5656 /* 5657 * ...in a MOVSS shadow, with pending debug exceptions. 5658 */ 5659 asm volatile("vmcall;" 5660 "wbinvd;" 5661 ".Lpost_movss_wbinvd:"); 5662 /* 5663 * For a hardware generated single-step #DB in a transactional region. 5664 */ 5665 asm volatile("vmcall;" 5666 ".Lxbegin: xbegin .Lskip_rtm;" 5667 "xend;" 5668 ".Lskip_rtm:"); 5669 } 5670 5671 /* 5672 * Clear the pending debug exceptions and RFLAGS.TF and re-enter 5673 * L2. No #DB is delivered and L2 continues to the next point of 5674 * interest. 5675 */ 5676 static void dismiss_db(void) 5677 { 5678 vmcs_write(GUEST_PENDING_DEBUG, 0); 5679 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 5680 enter_guest(); 5681 } 5682 5683 /* 5684 * Check a variety of VMCS fields relevant to an intercepted #DB exception. 5685 * Then throw away the #DB exception and resume L2. 5686 */ 5687 static void check_db_exit(bool xfail_qual, bool xfail_dr6, bool xfail_pdbg, 5688 void *expected_rip, u64 expected_exit_qual, 5689 u64 expected_dr6) 5690 { 5691 u32 reason = vmcs_read(EXI_REASON); 5692 u32 intr_info = vmcs_read(EXI_INTR_INFO); 5693 u64 exit_qual = vmcs_read(EXI_QUALIFICATION); 5694 u64 guest_rip = vmcs_read(GUEST_RIP); 5695 u64 guest_pending_dbg = vmcs_read(GUEST_PENDING_DEBUG); 5696 u64 dr6 = read_dr6(); 5697 const u32 expected_intr_info = INTR_INFO_VALID_MASK | 5698 INTR_TYPE_HARD_EXCEPTION | DB_VECTOR; 5699 5700 report("Expected #DB VM-exit", 5701 reason == VMX_EXC_NMI && intr_info == expected_intr_info); 5702 report("Expected RIP %p (actual %lx)", (u64)expected_rip == guest_rip, 5703 expected_rip, guest_rip); 5704 report_xfail("Expected pending debug exceptions 0 (actual %lx)", 5705 xfail_pdbg, 0 == guest_pending_dbg, guest_pending_dbg); 5706 report_xfail("Expected exit qualification %lx (actual %lx)", xfail_qual, 5707 expected_exit_qual == exit_qual, 5708 expected_exit_qual, exit_qual); 5709 report_xfail("Expected DR6 %lx (actual %lx)", xfail_dr6, 5710 expected_dr6 == dr6, expected_dr6, dr6); 5711 dismiss_db(); 5712 } 5713 5714 /* 5715 * Assuming the guest has just exited on a VMCALL instruction, skip 5716 * over the vmcall, and set the guest's RFLAGS.TF in the VMCS. If 5717 * pending debug exceptions are non-zero, set the VMCS up as if the 5718 * previous instruction was a MOVSS that generated the indicated 5719 * pending debug exceptions. Then enter L2. 5720 */ 5721 static void single_step_guest(const char *test_name, u64 starting_dr6, 5722 u64 pending_debug_exceptions) 5723 { 5724 printf("\n%s\n", test_name); 5725 skip_exit_vmcall(); 5726 write_dr6(starting_dr6); 5727 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_TF); 5728 if (pending_debug_exceptions) { 5729 vmcs_write(GUEST_PENDING_DEBUG, pending_debug_exceptions); 5730 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 5731 } 5732 enter_guest(); 5733 } 5734 5735 /* 5736 * When L1 intercepts #DB, verify that a single-step trap clears 5737 * pending debug exceptions, populates the exit qualification field 5738 * properly, and that DR6 is not prematurely clobbered. In a 5739 * (simulated) MOVSS shadow, make sure that the pending debug 5740 * exception bits are properly accumulated into the exit qualification 5741 * field. 5742 */ 5743 static void vmx_db_test(void) 5744 { 5745 /* 5746 * We are going to set a few arbitrary bits in DR6 to verify that 5747 * (a) DR6 is not modified by an intercepted #DB, and 5748 * (b) stale bits in DR6 (DR6.BD, in particular) don't leak into 5749 * the exit qualification field for a subsequent #DB exception. 5750 */ 5751 const u64 starting_dr6 = DR6_RESERVED | BIT(13) | DR_TRAP3 | DR_TRAP1; 5752 extern char post_nop asm(".Lpost_nop"); 5753 extern char post_movss_nop asm(".Lpost_movss_nop"); 5754 extern char post_wbinvd asm(".Lpost_wbinvd"); 5755 extern char post_movss_wbinvd asm(".Lpost_movss_wbinvd"); 5756 extern char xbegin asm(".Lxbegin"); 5757 extern char skip_rtm asm(".Lskip_rtm"); 5758 5759 /* 5760 * L1 wants to intercept #DB exceptions encountered in L2. 5761 */ 5762 vmcs_write(EXC_BITMAP, BIT(DB_VECTOR)); 5763 5764 /* 5765 * Start L2 and run it up to the first point of interest. 5766 */ 5767 test_set_guest(vmx_db_test_guest); 5768 enter_guest(); 5769 5770 /* 5771 * Hardware-delivered #DB trap for single-step sets the 5772 * standard that L0 has to follow for emulated instructions. 5773 */ 5774 single_step_guest("Hardware delivered single-step", starting_dr6, 0); 5775 check_db_exit(false, false, false, &post_nop, DR_STEP, starting_dr6); 5776 5777 /* 5778 * Hardware-delivered #DB trap for single-step in MOVSS shadow 5779 * also sets the standard that L0 has to follow for emulated 5780 * instructions. Here, we establish the VMCS pending debug 5781 * exceptions to indicate that the simulated MOVSS triggered a 5782 * data breakpoint as well as the single-step trap. 5783 */ 5784 single_step_guest("Hardware delivered single-step in MOVSS shadow", 5785 starting_dr6, BIT(12) | DR_STEP | DR_TRAP0 ); 5786 check_db_exit(false, false, false, &post_movss_nop, DR_STEP | DR_TRAP0, 5787 starting_dr6); 5788 5789 /* 5790 * L0 synthesized #DB trap for single-step is buggy, because 5791 * kvm (a) clobbers DR6 too early, and (b) tries its best to 5792 * reconstitute the exit qualification from the prematurely 5793 * modified DR6, but fails miserably. 5794 */ 5795 single_step_guest("Software synthesized single-step", starting_dr6, 0); 5796 check_db_exit(true, true, false, &post_wbinvd, DR_STEP, starting_dr6); 5797 5798 /* 5799 * L0 synthesized #DB trap for single-step in MOVSS shadow is 5800 * even worse, because L0 also leaves the pending debug 5801 * exceptions in the VMCS instead of accumulating them into 5802 * the exit qualification field for the #DB exception. 5803 */ 5804 single_step_guest("Software synthesized single-step in MOVSS shadow", 5805 starting_dr6, BIT(12) | DR_STEP | DR_TRAP0); 5806 check_db_exit(true, true, true, &post_movss_wbinvd, DR_STEP | DR_TRAP0, 5807 starting_dr6); 5808 5809 /* 5810 * Optional RTM test for hardware that supports RTM, to 5811 * demonstrate that the current volume 3 of the SDM 5812 * (325384-067US), table 27-1 is incorrect. Bit 16 of the exit 5813 * qualification for debug exceptions is not reserved. It is 5814 * set to 1 if a debug exception (#DB) or a breakpoint 5815 * exception (#BP) occurs inside an RTM region while advanced 5816 * debugging of RTM transactional regions is enabled. 5817 */ 5818 if (cpuid(7).b & BIT(11)) { 5819 vmcs_write(ENT_CONTROLS, 5820 vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 5821 /* 5822 * Set DR7.RTM[bit 11] and IA32_DEBUGCTL.RTM[bit 15] 5823 * in the guest to enable advanced debugging of RTM 5824 * transactional regions. 5825 */ 5826 vmcs_write(GUEST_DR7, BIT(11)); 5827 vmcs_write(GUEST_DEBUGCTL, BIT(15)); 5828 single_step_guest("Hardware delivered single-step in " 5829 "transactional region", starting_dr6, 0); 5830 check_db_exit(false, false, false, &xbegin, BIT(16), 5831 starting_dr6); 5832 } else { 5833 vmcs_write(GUEST_RIP, (u64)&skip_rtm); 5834 enter_guest(); 5835 } 5836 } 5837 5838 static bool cpu_has_apicv(void) 5839 { 5840 return ((ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT) && 5841 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 5842 (ctrl_pin_rev.clr & PIN_POST_INTR)); 5843 } 5844 5845 static void enable_vid(void) 5846 { 5847 void *virtual_apic_page; 5848 5849 assert(cpu_has_apicv()); 5850 5851 disable_intercept_for_x2apic_msrs(); 5852 5853 virtual_apic_page = alloc_page(); 5854 vmcs_write(APIC_VIRT_ADDR, (u64)virtual_apic_page); 5855 5856 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 5857 5858 vmcs_write(EOI_EXIT_BITMAP0, 0x0); 5859 vmcs_write(EOI_EXIT_BITMAP1, 0x0); 5860 vmcs_write(EOI_EXIT_BITMAP2, 0x0); 5861 vmcs_write(EOI_EXIT_BITMAP3, 0x0); 5862 5863 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY | CPU_TPR_SHADOW); 5864 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_VINTD | CPU_VIRT_X2APIC); 5865 } 5866 5867 static void trigger_ioapic_scan_thread(void *data) 5868 { 5869 /* Wait until other CPU entered L2 */ 5870 while (vmx_get_test_stage() != 1) 5871 ; 5872 5873 /* Trigger ioapic scan */ 5874 ioapic_set_redir(0xf, 0x79, TRIGGER_LEVEL); 5875 vmx_set_test_stage(2); 5876 } 5877 5878 static void irq_79_handler_guest(isr_regs_t *regs) 5879 { 5880 eoi(); 5881 5882 /* L1 expects vmexit on VMX_VMCALL and not VMX_EOI_INDUCED */ 5883 vmcall(); 5884 } 5885 5886 /* 5887 * Constant for num of busy-loop iterations after which 5888 * a timer interrupt should have happened in host 5889 */ 5890 #define TIMER_INTERRUPT_DELAY 100000000 5891 5892 static void vmx_eoi_bitmap_ioapic_scan_test_guest(void) 5893 { 5894 handle_irq(0x79, irq_79_handler_guest); 5895 irq_enable(); 5896 5897 /* Signal to L1 CPU to trigger ioapic scan */ 5898 vmx_set_test_stage(1); 5899 /* Wait until L1 CPU to trigger ioapic scan */ 5900 while (vmx_get_test_stage() != 2) 5901 ; 5902 5903 /* 5904 * Wait for L0 timer interrupt to be raised while we run in L2 5905 * such that L0 will process the IOAPIC scan request before 5906 * resuming L2 5907 */ 5908 delay(TIMER_INTERRUPT_DELAY); 5909 5910 asm volatile ("int $0x79"); 5911 } 5912 5913 static void vmx_eoi_bitmap_ioapic_scan_test(void) 5914 { 5915 if (!cpu_has_apicv() || (cpu_count() < 2)) { 5916 report_skip(__func__); 5917 return; 5918 } 5919 5920 enable_vid(); 5921 5922 on_cpu_async(1, trigger_ioapic_scan_thread, NULL); 5923 test_set_guest(vmx_eoi_bitmap_ioapic_scan_test_guest); 5924 5925 /* 5926 * Launch L2. 5927 * We expect the exit reason to be VMX_VMCALL (and not EOI INDUCED). 5928 * In case the reason isn't VMX_VMCALL, the asserion inside 5929 * skip_exit_vmcall() will fail. 5930 */ 5931 enter_guest(); 5932 skip_exit_vmcall(); 5933 5934 /* Let L2 finish */ 5935 enter_guest(); 5936 report(__func__, 1); 5937 } 5938 5939 #define HLT_WITH_RVI_VECTOR (0xf1) 5940 5941 bool vmx_hlt_with_rvi_guest_isr_fired; 5942 static void vmx_hlt_with_rvi_guest_isr(isr_regs_t *regs) 5943 { 5944 vmx_hlt_with_rvi_guest_isr_fired = true; 5945 eoi(); 5946 } 5947 5948 static void vmx_hlt_with_rvi_guest(void) 5949 { 5950 handle_irq(HLT_WITH_RVI_VECTOR, vmx_hlt_with_rvi_guest_isr); 5951 5952 irq_enable(); 5953 asm volatile ("nop"); 5954 5955 vmcall(); 5956 } 5957 5958 static void vmx_hlt_with_rvi_test(void) 5959 { 5960 if (!cpu_has_apicv()) { 5961 report_skip(__func__); 5962 return; 5963 } 5964 5965 enable_vid(); 5966 5967 vmx_hlt_with_rvi_guest_isr_fired = false; 5968 test_set_guest(vmx_hlt_with_rvi_guest); 5969 5970 enter_guest(); 5971 skip_exit_vmcall(); 5972 5973 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 5974 vmcs_write(GUEST_INT_STATUS, HLT_WITH_RVI_VECTOR); 5975 enter_guest(); 5976 5977 report("Interrupt raised in guest", vmx_hlt_with_rvi_guest_isr_fired); 5978 } 5979 5980 static void set_irq_line_thread(void *data) 5981 { 5982 /* Wait until other CPU entered L2 */ 5983 while (vmx_get_test_stage() != 1) 5984 ; 5985 5986 /* Set irq-line 0xf to raise vector 0x78 for vCPU 0 */ 5987 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 5988 vmx_set_test_stage(2); 5989 } 5990 5991 static bool irq_78_handler_vmcall_before_eoi; 5992 static void irq_78_handler_guest(isr_regs_t *regs) 5993 { 5994 set_irq_line(0xf, 0); 5995 if (irq_78_handler_vmcall_before_eoi) 5996 vmcall(); 5997 eoi(); 5998 vmcall(); 5999 } 6000 6001 static void vmx_apic_passthrough_guest(void) 6002 { 6003 handle_irq(0x78, irq_78_handler_guest); 6004 irq_enable(); 6005 6006 /* If requested, wait for other CPU to trigger ioapic scan */ 6007 if (vmx_get_test_stage() < 1) { 6008 vmx_set_test_stage(1); 6009 while (vmx_get_test_stage() != 2) 6010 ; 6011 } 6012 6013 set_irq_line(0xf, 1); 6014 } 6015 6016 static void vmx_apic_passthrough(bool set_irq_line_from_thread) 6017 { 6018 if (set_irq_line_from_thread && (cpu_count() < 2)) { 6019 report_skip(__func__); 6020 return; 6021 } 6022 6023 u64 cpu_ctrl_0 = CPU_SECONDARY; 6024 u64 cpu_ctrl_1 = 0; 6025 6026 disable_intercept_for_x2apic_msrs(); 6027 6028 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 6029 6030 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 6031 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 6032 6033 if (set_irq_line_from_thread) { 6034 irq_78_handler_vmcall_before_eoi = false; 6035 on_cpu_async(1, set_irq_line_thread, NULL); 6036 } else { 6037 irq_78_handler_vmcall_before_eoi = true; 6038 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 6039 vmx_set_test_stage(2); 6040 } 6041 test_set_guest(vmx_apic_passthrough_guest); 6042 6043 if (irq_78_handler_vmcall_before_eoi) { 6044 /* Before EOI remote_irr should still be set */ 6045 enter_guest(); 6046 skip_exit_vmcall(); 6047 TEST_ASSERT_EQ_MSG(1, (int)ioapic_read_redir(0xf).remote_irr, 6048 "IOAPIC pass-through: remote_irr=1 before EOI"); 6049 } 6050 6051 /* After EOI remote_irr should be cleared */ 6052 enter_guest(); 6053 skip_exit_vmcall(); 6054 TEST_ASSERT_EQ_MSG(0, (int)ioapic_read_redir(0xf).remote_irr, 6055 "IOAPIC pass-through: remote_irr=0 after EOI"); 6056 6057 /* Let L2 finish */ 6058 enter_guest(); 6059 report(__func__, 1); 6060 } 6061 6062 static void vmx_apic_passthrough_test(void) 6063 { 6064 vmx_apic_passthrough(false); 6065 } 6066 6067 static void vmx_apic_passthrough_thread_test(void) 6068 { 6069 vmx_apic_passthrough(true); 6070 } 6071 6072 enum vmcs_access { 6073 ACCESS_VMREAD, 6074 ACCESS_VMWRITE, 6075 ACCESS_NONE, 6076 }; 6077 6078 struct vmcs_shadow_test_common { 6079 enum vmcs_access op; 6080 enum Reason reason; 6081 u64 field; 6082 u64 value; 6083 u64 flags; 6084 u64 time; 6085 } l1_l2_common; 6086 6087 static inline u64 vmread_flags(u64 field, u64 *val) 6088 { 6089 u64 flags; 6090 6091 asm volatile ("vmread %2, %1; pushf; pop %0" 6092 : "=r" (flags), "=rm" (*val) : "r" (field) : "cc"); 6093 return flags & X86_EFLAGS_ALU; 6094 } 6095 6096 static inline u64 vmwrite_flags(u64 field, u64 val) 6097 { 6098 u64 flags; 6099 6100 asm volatile ("vmwrite %1, %2; pushf; pop %0" 6101 : "=r"(flags) : "rm" (val), "r" (field) : "cc"); 6102 return flags & X86_EFLAGS_ALU; 6103 } 6104 6105 static void vmx_vmcs_shadow_test_guest(void) 6106 { 6107 struct vmcs_shadow_test_common *c = &l1_l2_common; 6108 u64 start; 6109 6110 while (c->op != ACCESS_NONE) { 6111 start = rdtsc(); 6112 switch (c->op) { 6113 default: 6114 c->flags = -1ull; 6115 break; 6116 case ACCESS_VMREAD: 6117 c->flags = vmread_flags(c->field, &c->value); 6118 break; 6119 case ACCESS_VMWRITE: 6120 c->flags = vmwrite_flags(c->field, 0); 6121 break; 6122 } 6123 c->time = rdtsc() - start; 6124 vmcall(); 6125 } 6126 } 6127 6128 static u64 vmread_from_shadow(u64 field) 6129 { 6130 struct vmcs *primary; 6131 struct vmcs *shadow; 6132 u64 value; 6133 6134 TEST_ASSERT(!vmcs_save(&primary)); 6135 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 6136 TEST_ASSERT(!make_vmcs_current(shadow)); 6137 value = vmcs_read(field); 6138 TEST_ASSERT(!make_vmcs_current(primary)); 6139 return value; 6140 } 6141 6142 static u64 vmwrite_to_shadow(u64 field, u64 value) 6143 { 6144 struct vmcs *primary; 6145 struct vmcs *shadow; 6146 6147 TEST_ASSERT(!vmcs_save(&primary)); 6148 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 6149 TEST_ASSERT(!make_vmcs_current(shadow)); 6150 vmcs_write(field, value); 6151 value = vmcs_read(field); 6152 TEST_ASSERT(!make_vmcs_current(primary)); 6153 return value; 6154 } 6155 6156 static void vmcs_shadow_test_access(u8 *bitmap[2], enum vmcs_access access) 6157 { 6158 struct vmcs_shadow_test_common *c = &l1_l2_common; 6159 6160 c->op = access; 6161 vmcs_write(VMX_INST_ERROR, 0); 6162 enter_guest(); 6163 c->reason = vmcs_read(EXI_REASON) & 0xffff; 6164 if (c->reason != VMX_VMCALL) { 6165 skip_exit_insn(); 6166 enter_guest(); 6167 } 6168 skip_exit_vmcall(); 6169 } 6170 6171 static void vmcs_shadow_test_field(u8 *bitmap[2], u64 field) 6172 { 6173 struct vmcs_shadow_test_common *c = &l1_l2_common; 6174 struct vmcs *shadow; 6175 u64 value; 6176 uintptr_t flags[2]; 6177 bool good_shadow; 6178 u32 vmx_inst_error; 6179 6180 report_prefix_pushf("field %lx", field); 6181 c->field = field; 6182 6183 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 6184 if (shadow != (struct vmcs *)-1ull) { 6185 flags[ACCESS_VMREAD] = vmread_flags(field, &value); 6186 flags[ACCESS_VMWRITE] = vmwrite_flags(field, value); 6187 good_shadow = !flags[ACCESS_VMREAD] && !flags[ACCESS_VMWRITE]; 6188 } else { 6189 /* 6190 * When VMCS link pointer is -1ull, VMWRITE/VMREAD on 6191 * shadowed-fields should fail with setting RFLAGS.CF. 6192 */ 6193 flags[ACCESS_VMREAD] = X86_EFLAGS_CF; 6194 flags[ACCESS_VMWRITE] = X86_EFLAGS_CF; 6195 good_shadow = false; 6196 } 6197 6198 /* Intercept both VMREAD and VMWRITE. */ 6199 report_prefix_push("no VMREAD/VMWRITE permission"); 6200 /* VMWRITE/VMREAD done on reserved-bit should always intercept */ 6201 if (!(field >> VMCS_FIELD_RESERVED_SHIFT)) { 6202 set_bit(field, bitmap[ACCESS_VMREAD]); 6203 set_bit(field, bitmap[ACCESS_VMWRITE]); 6204 } 6205 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 6206 report("not shadowed for VMWRITE", c->reason == VMX_VMWRITE); 6207 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 6208 report("not shadowed for VMREAD", c->reason == VMX_VMREAD); 6209 report_prefix_pop(); 6210 6211 if (field >> VMCS_FIELD_RESERVED_SHIFT) 6212 goto out; 6213 6214 /* Permit shadowed VMREAD. */ 6215 report_prefix_push("VMREAD permission only"); 6216 clear_bit(field, bitmap[ACCESS_VMREAD]); 6217 set_bit(field, bitmap[ACCESS_VMWRITE]); 6218 if (good_shadow) 6219 value = vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 6220 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 6221 report("not shadowed for VMWRITE", c->reason == VMX_VMWRITE); 6222 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 6223 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 6224 report("shadowed for VMREAD (in %ld cycles)", c->reason == VMX_VMCALL, 6225 c->time); 6226 report("ALU flags after VMREAD (%lx) are as expected (%lx)", 6227 c->flags == flags[ACCESS_VMREAD], 6228 c->flags, flags[ACCESS_VMREAD]); 6229 if (good_shadow) 6230 report("value read from shadow (%lx) is as expected (%lx)", 6231 c->value == value, c->value, value); 6232 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 6233 report("VMX_INST_ERROR (%d) is as expected (%d)", 6234 vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 6235 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 6236 report_prefix_pop(); 6237 6238 /* Permit shadowed VMWRITE. */ 6239 report_prefix_push("VMWRITE permission only"); 6240 set_bit(field, bitmap[ACCESS_VMREAD]); 6241 clear_bit(field, bitmap[ACCESS_VMWRITE]); 6242 if (good_shadow) 6243 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 6244 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 6245 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 6246 report("shadowed for VMWRITE (in %ld cycles)", c->reason == VMX_VMCALL, 6247 c->time); 6248 report("ALU flags after VMWRITE (%lx) are as expected (%lx)", 6249 c->flags == flags[ACCESS_VMREAD], 6250 c->flags, flags[ACCESS_VMREAD]); 6251 if (good_shadow) { 6252 value = vmread_from_shadow(field); 6253 report("shadow VMCS value (%lx) is as expected (%lx)", 6254 value == 0, value, 0ul); 6255 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 6256 report("VMX_INST_ERROR (%d) is as expected (%d)", 6257 vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 6258 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 6259 } 6260 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 6261 report("not shadowed for VMREAD", c->reason == VMX_VMREAD); 6262 report_prefix_pop(); 6263 6264 /* Permit shadowed VMREAD and VMWRITE. */ 6265 report_prefix_push("VMREAD and VMWRITE permission"); 6266 clear_bit(field, bitmap[ACCESS_VMREAD]); 6267 clear_bit(field, bitmap[ACCESS_VMWRITE]); 6268 if (good_shadow) 6269 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 6270 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 6271 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 6272 report("shadowed for VMWRITE (in %ld cycles)", c->reason == VMX_VMCALL, 6273 c->time); 6274 report("ALU flags after VMWRITE (%lx) are as expected (%lx)", 6275 c->flags == flags[ACCESS_VMREAD], 6276 c->flags, flags[ACCESS_VMREAD]); 6277 if (good_shadow) { 6278 value = vmread_from_shadow(field); 6279 report("shadow VMCS value (%lx) is as expected (%lx)", 6280 value == 0, value, 0ul); 6281 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 6282 report("VMX_INST_ERROR (%d) is as expected (%d)", 6283 vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 6284 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 6285 } 6286 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 6287 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 6288 report("shadowed for VMREAD (in %ld cycles)", c->reason == VMX_VMCALL, 6289 c->time); 6290 report("ALU flags after VMREAD (%lx) are as expected (%lx)", 6291 c->flags == flags[ACCESS_VMREAD], 6292 c->flags, flags[ACCESS_VMREAD]); 6293 if (good_shadow) 6294 report("value read from shadow (%lx) is as expected (%lx)", 6295 c->value == 0, c->value, 0ul); 6296 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 6297 report("VMX_INST_ERROR (%d) is as expected (%d)", 6298 vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 6299 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 6300 report_prefix_pop(); 6301 6302 out: 6303 report_prefix_pop(); 6304 } 6305 6306 static void vmx_vmcs_shadow_test_body(u8 *bitmap[2]) 6307 { 6308 unsigned base; 6309 unsigned index; 6310 unsigned bit; 6311 unsigned highest_index = rdmsr(MSR_IA32_VMX_VMCS_ENUM); 6312 6313 /* Run test on all possible valid VMCS fields */ 6314 for (base = 0; 6315 base < (1 << VMCS_FIELD_RESERVED_SHIFT); 6316 base += (1 << VMCS_FIELD_TYPE_SHIFT)) 6317 for (index = 0; index <= highest_index; index++) 6318 vmcs_shadow_test_field(bitmap, base + index); 6319 6320 /* 6321 * Run tests on some invalid VMCS fields 6322 * (Have reserved bit set). 6323 */ 6324 for (bit = VMCS_FIELD_RESERVED_SHIFT; bit < VMCS_FIELD_BIT_SIZE; bit++) 6325 vmcs_shadow_test_field(bitmap, (1ull << bit)); 6326 } 6327 6328 static void vmx_vmcs_shadow_test(void) 6329 { 6330 u8 *bitmap[2]; 6331 struct vmcs *shadow; 6332 6333 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 6334 printf("\t'Activate secondary controls' not supported.\n"); 6335 return; 6336 } 6337 6338 if (!(ctrl_cpu_rev[1].clr & CPU_SHADOW_VMCS)) { 6339 printf("\t'VMCS shadowing' not supported.\n"); 6340 return; 6341 } 6342 6343 if (!(rdmsr(MSR_IA32_VMX_MISC) & 6344 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS)) { 6345 printf("\tVMWRITE can't modify VM-exit information fields.\n"); 6346 return; 6347 } 6348 6349 test_set_guest(vmx_vmcs_shadow_test_guest); 6350 6351 bitmap[ACCESS_VMREAD] = alloc_page(); 6352 bitmap[ACCESS_VMWRITE] = alloc_page(); 6353 6354 vmcs_write(VMREAD_BITMAP, virt_to_phys(bitmap[ACCESS_VMREAD])); 6355 vmcs_write(VMWRITE_BITMAP, virt_to_phys(bitmap[ACCESS_VMWRITE])); 6356 6357 shadow = alloc_page(); 6358 shadow->hdr.revision_id = basic.revision; 6359 shadow->hdr.shadow_vmcs = 1; 6360 TEST_ASSERT(!vmcs_clear(shadow)); 6361 6362 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_RDTSC); 6363 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY); 6364 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_SHADOW_VMCS); 6365 6366 vmcs_write(VMCS_LINK_PTR, virt_to_phys(shadow)); 6367 report_prefix_push("valid link pointer"); 6368 vmx_vmcs_shadow_test_body(bitmap); 6369 report_prefix_pop(); 6370 6371 vmcs_write(VMCS_LINK_PTR, -1ull); 6372 report_prefix_push("invalid link pointer"); 6373 vmx_vmcs_shadow_test_body(bitmap); 6374 report_prefix_pop(); 6375 6376 l1_l2_common.op = ACCESS_NONE; 6377 enter_guest(); 6378 } 6379 6380 6381 6382 static int invalid_msr_init(struct vmcs *vmcs) 6383 { 6384 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 6385 printf("\tPreemption timer is not supported\n"); 6386 return VMX_TEST_EXIT; 6387 } 6388 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 6389 preempt_val = 10000000; 6390 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 6391 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 6392 6393 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 6394 printf("\tSave preemption value is not supported\n"); 6395 6396 vmcs_write(ENT_MSR_LD_CNT, 1); 6397 vmcs_write(ENTER_MSR_LD_ADDR, (u64)0x13370000); 6398 6399 return VMX_TEST_START; 6400 } 6401 6402 6403 static void invalid_msr_main(void) 6404 { 6405 report("Invalid MSR load", 0); 6406 } 6407 6408 static int invalid_msr_exit_handler(void) 6409 { 6410 report("Invalid MSR load", 0); 6411 print_vmexit_info(); 6412 return VMX_TEST_EXIT; 6413 } 6414 6415 static int invalid_msr_entry_failure(struct vmentry_failure *failure) 6416 { 6417 ulong reason; 6418 6419 reason = vmcs_read(EXI_REASON); 6420 report("Invalid MSR load", reason == (0x80000000u | VMX_FAIL_MSR)); 6421 return VMX_TEST_VMEXIT; 6422 } 6423 6424 6425 #define TEST(name) { #name, .v2 = name } 6426 6427 /* name/init/guest_main/exit_handler/syscall_handler/guest_regs */ 6428 struct vmx_test vmx_tests[] = { 6429 { "null", NULL, basic_guest_main, basic_exit_handler, NULL, {0} }, 6430 { "vmenter", NULL, vmenter_main, vmenter_exit_handler, NULL, {0} }, 6431 { "preemption timer", preemption_timer_init, preemption_timer_main, 6432 preemption_timer_exit_handler, NULL, {0} }, 6433 { "control field PAT", test_ctrl_pat_init, test_ctrl_pat_main, 6434 test_ctrl_pat_exit_handler, NULL, {0} }, 6435 { "control field EFER", test_ctrl_efer_init, test_ctrl_efer_main, 6436 test_ctrl_efer_exit_handler, NULL, {0} }, 6437 { "CR shadowing", NULL, cr_shadowing_main, 6438 cr_shadowing_exit_handler, NULL, {0} }, 6439 { "I/O bitmap", iobmp_init, iobmp_main, iobmp_exit_handler, 6440 NULL, {0} }, 6441 { "instruction intercept", insn_intercept_init, insn_intercept_main, 6442 insn_intercept_exit_handler, NULL, {0} }, 6443 { "EPT A/D disabled", ept_init, ept_main, ept_exit_handler, NULL, {0} }, 6444 { "EPT A/D enabled", eptad_init, eptad_main, eptad_exit_handler, NULL, {0} }, 6445 { "PML", pml_init, pml_main, pml_exit_handler, NULL, {0} }, 6446 { "VPID", vpid_init, vpid_main, vpid_exit_handler, NULL, {0} }, 6447 { "interrupt", interrupt_init, interrupt_main, 6448 interrupt_exit_handler, NULL, {0} }, 6449 { "debug controls", dbgctls_init, dbgctls_main, dbgctls_exit_handler, 6450 NULL, {0} }, 6451 { "MSR switch", msr_switch_init, msr_switch_main, 6452 msr_switch_exit_handler, NULL, {0}, msr_switch_entry_failure }, 6453 { "vmmcall", vmmcall_init, vmmcall_main, vmmcall_exit_handler, NULL, {0} }, 6454 { "disable RDTSCP", disable_rdtscp_init, disable_rdtscp_main, 6455 disable_rdtscp_exit_handler, NULL, {0} }, 6456 { "int3", int3_init, int3_guest_main, int3_exit_handler, NULL, {0} }, 6457 { "into", into_init, into_guest_main, into_exit_handler, NULL, {0} }, 6458 { "exit_monitor_from_l2_test", NULL, exit_monitor_from_l2_main, 6459 exit_monitor_from_l2_handler, NULL, {0} }, 6460 { "invalid_msr", invalid_msr_init, invalid_msr_main, 6461 invalid_msr_exit_handler, NULL, {0}, invalid_msr_entry_failure}, 6462 /* Basic V2 tests. */ 6463 TEST(v2_null_test), 6464 TEST(v2_multiple_entries_test), 6465 TEST(fixture_test_case1), 6466 TEST(fixture_test_case2), 6467 /* Opcode tests. */ 6468 TEST(invvpid_test_v2), 6469 /* VM-entry tests */ 6470 TEST(vmx_controls_test), 6471 TEST(vmentry_movss_shadow_test), 6472 /* APICv tests */ 6473 TEST(vmx_eoi_bitmap_ioapic_scan_test), 6474 TEST(vmx_hlt_with_rvi_test), 6475 /* APIC pass-through tests */ 6476 TEST(vmx_apic_passthrough_test), 6477 TEST(vmx_apic_passthrough_thread_test), 6478 /* VMCS Shadowing tests */ 6479 TEST(vmx_vmcs_shadow_test), 6480 /* Regression tests */ 6481 TEST(vmx_cr_load_test), 6482 TEST(vmx_nm_test), 6483 TEST(vmx_db_test), 6484 TEST(vmx_nmi_window_test), 6485 TEST(vmx_intr_window_test), 6486 TEST(vmx_pending_event_test), 6487 TEST(vmx_pending_event_hlt_test), 6488 TEST(vmx_store_tsc_test), 6489 /* EPT access tests. */ 6490 TEST(ept_access_test_not_present), 6491 TEST(ept_access_test_read_only), 6492 TEST(ept_access_test_write_only), 6493 TEST(ept_access_test_read_write), 6494 TEST(ept_access_test_execute_only), 6495 TEST(ept_access_test_read_execute), 6496 TEST(ept_access_test_write_execute), 6497 TEST(ept_access_test_read_write_execute), 6498 TEST(ept_access_test_reserved_bits), 6499 TEST(ept_access_test_ignored_bits), 6500 TEST(ept_access_test_paddr_not_present_ad_disabled), 6501 TEST(ept_access_test_paddr_not_present_ad_enabled), 6502 TEST(ept_access_test_paddr_read_only_ad_disabled), 6503 TEST(ept_access_test_paddr_read_only_ad_enabled), 6504 TEST(ept_access_test_paddr_read_write), 6505 TEST(ept_access_test_paddr_read_write_execute), 6506 TEST(ept_access_test_paddr_read_execute_ad_disabled), 6507 TEST(ept_access_test_paddr_read_execute_ad_enabled), 6508 TEST(ept_access_test_paddr_not_present_page_fault), 6509 TEST(ept_access_test_force_2m_page), 6510 { NULL, NULL, NULL, NULL, NULL, {0} }, 6511 }; 6512