1 /* 2 * All test cases of nested virtualization should be in this file 3 * 4 * Author : Arthur Chunqi Li <yzt356@gmail.com> 5 */ 6 7 #include <asm/debugreg.h> 8 9 #include "vmx.h" 10 #include "msr.h" 11 #include "processor.h" 12 #include "vm.h" 13 #include "pci.h" 14 #include "fwcfg.h" 15 #include "isr.h" 16 #include "desc.h" 17 #include "apic.h" 18 #include "types.h" 19 #include "vmalloc.h" 20 #include "alloc_page.h" 21 #include "smp.h" 22 #include "delay.h" 23 24 #define NONCANONICAL 0xaaaaaaaaaaaaaaaaull 25 26 #define VPID_CAP_INVVPID_TYPES_SHIFT 40 27 28 u64 ia32_pat; 29 u64 ia32_efer; 30 void *io_bitmap_a, *io_bitmap_b; 31 u16 ioport; 32 33 unsigned long *pml4; 34 u64 eptp; 35 void *data_page1, *data_page2; 36 37 phys_addr_t pci_physaddr; 38 39 void *pml_log; 40 #define PML_INDEX 512 41 42 static inline unsigned ffs(unsigned x) 43 { 44 int pos = -1; 45 46 __asm__ __volatile__("bsf %1, %%eax; cmovnz %%eax, %0" 47 : "+r"(pos) : "rm"(x) : "eax"); 48 return pos + 1; 49 } 50 51 static inline void vmcall(void) 52 { 53 asm volatile("vmcall"); 54 } 55 56 static void basic_guest_main(void) 57 { 58 report("Basic VMX test", 1); 59 } 60 61 static int basic_exit_handler(void) 62 { 63 report("Basic VMX test", 0); 64 print_vmexit_info(); 65 return VMX_TEST_EXIT; 66 } 67 68 static void vmenter_main(void) 69 { 70 u64 rax; 71 u64 rsp, resume_rsp; 72 73 report("test vmlaunch", 1); 74 75 asm volatile( 76 "mov %%rsp, %0\n\t" 77 "mov %3, %%rax\n\t" 78 "vmcall\n\t" 79 "mov %%rax, %1\n\t" 80 "mov %%rsp, %2\n\t" 81 : "=r"(rsp), "=r"(rax), "=r"(resume_rsp) 82 : "g"(0xABCD)); 83 report("test vmresume", (rax == 0xFFFF) && (rsp == resume_rsp)); 84 } 85 86 static int vmenter_exit_handler(void) 87 { 88 u64 guest_rip; 89 ulong reason; 90 91 guest_rip = vmcs_read(GUEST_RIP); 92 reason = vmcs_read(EXI_REASON) & 0xff; 93 switch (reason) { 94 case VMX_VMCALL: 95 if (regs.rax != 0xABCD) { 96 report("test vmresume", 0); 97 return VMX_TEST_VMEXIT; 98 } 99 regs.rax = 0xFFFF; 100 vmcs_write(GUEST_RIP, guest_rip + 3); 101 return VMX_TEST_RESUME; 102 default: 103 report("test vmresume", 0); 104 print_vmexit_info(); 105 } 106 return VMX_TEST_VMEXIT; 107 } 108 109 u32 preempt_scale; 110 volatile unsigned long long tsc_val; 111 volatile u32 preempt_val; 112 u64 saved_rip; 113 114 static int preemption_timer_init(struct vmcs *vmcs) 115 { 116 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 117 printf("\tPreemption timer is not supported\n"); 118 return VMX_TEST_EXIT; 119 } 120 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 121 preempt_val = 10000000; 122 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 123 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 124 125 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 126 printf("\tSave preemption value is not supported\n"); 127 128 return VMX_TEST_START; 129 } 130 131 static void preemption_timer_main(void) 132 { 133 tsc_val = rdtsc(); 134 if (ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) { 135 vmx_set_test_stage(0); 136 vmcall(); 137 if (vmx_get_test_stage() == 1) 138 vmcall(); 139 } 140 vmx_set_test_stage(1); 141 while (vmx_get_test_stage() == 1) { 142 if (((rdtsc() - tsc_val) >> preempt_scale) 143 > 10 * preempt_val) { 144 vmx_set_test_stage(2); 145 vmcall(); 146 } 147 } 148 tsc_val = rdtsc(); 149 asm volatile ("hlt"); 150 vmcall(); 151 vmx_set_test_stage(5); 152 vmcall(); 153 } 154 155 static int preemption_timer_exit_handler(void) 156 { 157 bool guest_halted; 158 u64 guest_rip; 159 ulong reason; 160 u32 insn_len; 161 u32 ctrl_exit; 162 163 guest_rip = vmcs_read(GUEST_RIP); 164 reason = vmcs_read(EXI_REASON) & 0xff; 165 insn_len = vmcs_read(EXI_INST_LEN); 166 switch (reason) { 167 case VMX_PREEMPT: 168 switch (vmx_get_test_stage()) { 169 case 1: 170 case 2: 171 report("busy-wait for preemption timer", 172 ((rdtsc() - tsc_val) >> preempt_scale) >= 173 preempt_val); 174 vmx_set_test_stage(3); 175 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 176 return VMX_TEST_RESUME; 177 case 3: 178 guest_halted = 179 (vmcs_read(GUEST_ACTV_STATE) == ACTV_HLT); 180 report("preemption timer during hlt", 181 ((rdtsc() - tsc_val) >> preempt_scale) >= 182 preempt_val && guest_halted); 183 vmx_set_test_stage(4); 184 vmcs_write(PIN_CONTROLS, 185 vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 186 vmcs_write(EXI_CONTROLS, 187 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_PREEMPT); 188 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 189 return VMX_TEST_RESUME; 190 case 4: 191 report("preemption timer with 0 value", 192 saved_rip == guest_rip); 193 break; 194 default: 195 report("Invalid stage.", false); 196 print_vmexit_info(); 197 break; 198 } 199 break; 200 case VMX_VMCALL: 201 vmcs_write(GUEST_RIP, guest_rip + insn_len); 202 switch (vmx_get_test_stage()) { 203 case 0: 204 report("Keep preemption value", 205 vmcs_read(PREEMPT_TIMER_VALUE) == preempt_val); 206 vmx_set_test_stage(1); 207 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 208 ctrl_exit = (vmcs_read(EXI_CONTROLS) | 209 EXI_SAVE_PREEMPT) & ctrl_exit_rev.clr; 210 vmcs_write(EXI_CONTROLS, ctrl_exit); 211 return VMX_TEST_RESUME; 212 case 1: 213 report("Save preemption value", 214 vmcs_read(PREEMPT_TIMER_VALUE) < preempt_val); 215 return VMX_TEST_RESUME; 216 case 2: 217 report("busy-wait for preemption timer", 0); 218 vmx_set_test_stage(3); 219 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 220 return VMX_TEST_RESUME; 221 case 3: 222 report("preemption timer during hlt", 0); 223 vmx_set_test_stage(4); 224 /* fall through */ 225 case 4: 226 vmcs_write(PIN_CONTROLS, 227 vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 228 vmcs_write(PREEMPT_TIMER_VALUE, 0); 229 saved_rip = guest_rip + insn_len; 230 return VMX_TEST_RESUME; 231 case 5: 232 report("preemption timer with 0 value (vmcall stage 5)", 0); 233 break; 234 default: 235 // Should not reach here 236 report("unexpected stage, %d", false, 237 vmx_get_test_stage()); 238 print_vmexit_info(); 239 return VMX_TEST_VMEXIT; 240 } 241 break; 242 default: 243 report("Unknown exit reason, %ld", false, reason); 244 print_vmexit_info(); 245 } 246 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 247 return VMX_TEST_VMEXIT; 248 } 249 250 static void msr_bmp_init(void) 251 { 252 void *msr_bitmap; 253 u32 ctrl_cpu0; 254 255 msr_bitmap = alloc_page(); 256 memset(msr_bitmap, 0x0, PAGE_SIZE); 257 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 258 ctrl_cpu0 |= CPU_MSR_BITMAP; 259 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 260 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 261 } 262 263 static void *get_msr_bitmap(void) 264 { 265 void *msr_bitmap; 266 267 if (vmcs_read(CPU_EXEC_CTRL0) & CPU_MSR_BITMAP) { 268 msr_bitmap = (void *)vmcs_read(MSR_BITMAP); 269 } else { 270 msr_bitmap = alloc_page(); 271 memset(msr_bitmap, 0xff, PAGE_SIZE); 272 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 273 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_MSR_BITMAP); 274 } 275 276 return msr_bitmap; 277 } 278 279 static void disable_intercept_for_x2apic_msrs(void) 280 { 281 unsigned long *msr_bitmap = (unsigned long *)get_msr_bitmap(); 282 u32 msr; 283 284 for (msr = APIC_BASE_MSR; 285 msr < (APIC_BASE_MSR+0xff); 286 msr += BITS_PER_LONG) { 287 unsigned int word = msr / BITS_PER_LONG; 288 289 msr_bitmap[word] = 0; 290 msr_bitmap[word + (0x800 / sizeof(long))] = 0; 291 } 292 } 293 294 static int test_ctrl_pat_init(struct vmcs *vmcs) 295 { 296 u64 ctrl_ent; 297 u64 ctrl_exi; 298 299 msr_bmp_init(); 300 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT) && 301 !(ctrl_exit_rev.clr & EXI_LOAD_PAT) && 302 !(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 303 printf("\tSave/load PAT is not supported\n"); 304 return 1; 305 } 306 307 ctrl_ent = vmcs_read(ENT_CONTROLS); 308 ctrl_exi = vmcs_read(EXI_CONTROLS); 309 ctrl_ent |= ctrl_enter_rev.clr & ENT_LOAD_PAT; 310 ctrl_exi |= ctrl_exit_rev.clr & (EXI_SAVE_PAT | EXI_LOAD_PAT); 311 vmcs_write(ENT_CONTROLS, ctrl_ent); 312 vmcs_write(EXI_CONTROLS, ctrl_exi); 313 ia32_pat = rdmsr(MSR_IA32_CR_PAT); 314 vmcs_write(GUEST_PAT, 0x0); 315 vmcs_write(HOST_PAT, ia32_pat); 316 return VMX_TEST_START; 317 } 318 319 static void test_ctrl_pat_main(void) 320 { 321 u64 guest_ia32_pat; 322 323 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 324 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) 325 printf("\tENT_LOAD_PAT is not supported.\n"); 326 else { 327 if (guest_ia32_pat != 0) { 328 report("Entry load PAT", 0); 329 return; 330 } 331 } 332 wrmsr(MSR_IA32_CR_PAT, 0x6); 333 vmcall(); 334 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 335 if (ctrl_enter_rev.clr & ENT_LOAD_PAT) 336 report("Entry load PAT", guest_ia32_pat == ia32_pat); 337 } 338 339 static int test_ctrl_pat_exit_handler(void) 340 { 341 u64 guest_rip; 342 ulong reason; 343 u64 guest_pat; 344 345 guest_rip = vmcs_read(GUEST_RIP); 346 reason = vmcs_read(EXI_REASON) & 0xff; 347 switch (reason) { 348 case VMX_VMCALL: 349 guest_pat = vmcs_read(GUEST_PAT); 350 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT)) { 351 printf("\tEXI_SAVE_PAT is not supported\n"); 352 vmcs_write(GUEST_PAT, 0x6); 353 } else { 354 report("Exit save PAT", guest_pat == 0x6); 355 } 356 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) 357 printf("\tEXI_LOAD_PAT is not supported\n"); 358 else 359 report("Exit load PAT", rdmsr(MSR_IA32_CR_PAT) == ia32_pat); 360 vmcs_write(GUEST_PAT, ia32_pat); 361 vmcs_write(GUEST_RIP, guest_rip + 3); 362 return VMX_TEST_RESUME; 363 default: 364 printf("ERROR : Undefined exit reason, reason = %ld.\n", reason); 365 break; 366 } 367 return VMX_TEST_VMEXIT; 368 } 369 370 static int test_ctrl_efer_init(struct vmcs *vmcs) 371 { 372 u64 ctrl_ent; 373 u64 ctrl_exi; 374 375 msr_bmp_init(); 376 ctrl_ent = vmcs_read(ENT_CONTROLS) | ENT_LOAD_EFER; 377 ctrl_exi = vmcs_read(EXI_CONTROLS) | EXI_SAVE_EFER | EXI_LOAD_EFER; 378 vmcs_write(ENT_CONTROLS, ctrl_ent & ctrl_enter_rev.clr); 379 vmcs_write(EXI_CONTROLS, ctrl_exi & ctrl_exit_rev.clr); 380 ia32_efer = rdmsr(MSR_EFER); 381 vmcs_write(GUEST_EFER, ia32_efer ^ EFER_NX); 382 vmcs_write(HOST_EFER, ia32_efer ^ EFER_NX); 383 return VMX_TEST_START; 384 } 385 386 static void test_ctrl_efer_main(void) 387 { 388 u64 guest_ia32_efer; 389 390 guest_ia32_efer = rdmsr(MSR_EFER); 391 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) 392 printf("\tENT_LOAD_EFER is not supported.\n"); 393 else { 394 if (guest_ia32_efer != (ia32_efer ^ EFER_NX)) { 395 report("Entry load EFER", 0); 396 return; 397 } 398 } 399 wrmsr(MSR_EFER, ia32_efer); 400 vmcall(); 401 guest_ia32_efer = rdmsr(MSR_EFER); 402 if (ctrl_enter_rev.clr & ENT_LOAD_EFER) 403 report("Entry load EFER", guest_ia32_efer == ia32_efer); 404 } 405 406 static int test_ctrl_efer_exit_handler(void) 407 { 408 u64 guest_rip; 409 ulong reason; 410 u64 guest_efer; 411 412 guest_rip = vmcs_read(GUEST_RIP); 413 reason = vmcs_read(EXI_REASON) & 0xff; 414 switch (reason) { 415 case VMX_VMCALL: 416 guest_efer = vmcs_read(GUEST_EFER); 417 if (!(ctrl_exit_rev.clr & EXI_SAVE_EFER)) { 418 printf("\tEXI_SAVE_EFER is not supported\n"); 419 vmcs_write(GUEST_EFER, ia32_efer); 420 } else { 421 report("Exit save EFER", guest_efer == ia32_efer); 422 } 423 if (!(ctrl_exit_rev.clr & EXI_LOAD_EFER)) { 424 printf("\tEXI_LOAD_EFER is not supported\n"); 425 wrmsr(MSR_EFER, ia32_efer ^ EFER_NX); 426 } else { 427 report("Exit load EFER", rdmsr(MSR_EFER) == (ia32_efer ^ EFER_NX)); 428 } 429 vmcs_write(GUEST_PAT, ia32_efer); 430 vmcs_write(GUEST_RIP, guest_rip + 3); 431 return VMX_TEST_RESUME; 432 default: 433 printf("ERROR : Undefined exit reason, reason = %ld.\n", reason); 434 break; 435 } 436 return VMX_TEST_VMEXIT; 437 } 438 439 u32 guest_cr0, guest_cr4; 440 441 static void cr_shadowing_main(void) 442 { 443 u32 cr0, cr4, tmp; 444 445 // Test read through 446 vmx_set_test_stage(0); 447 guest_cr0 = read_cr0(); 448 if (vmx_get_test_stage() == 1) 449 report("Read through CR0", 0); 450 else 451 vmcall(); 452 vmx_set_test_stage(1); 453 guest_cr4 = read_cr4(); 454 if (vmx_get_test_stage() == 2) 455 report("Read through CR4", 0); 456 else 457 vmcall(); 458 // Test write through 459 guest_cr0 = guest_cr0 ^ (X86_CR0_TS | X86_CR0_MP); 460 guest_cr4 = guest_cr4 ^ (X86_CR4_TSD | X86_CR4_DE); 461 vmx_set_test_stage(2); 462 write_cr0(guest_cr0); 463 if (vmx_get_test_stage() == 3) 464 report("Write throuth CR0", 0); 465 else 466 vmcall(); 467 vmx_set_test_stage(3); 468 write_cr4(guest_cr4); 469 if (vmx_get_test_stage() == 4) 470 report("Write through CR4", 0); 471 else 472 vmcall(); 473 // Test read shadow 474 vmx_set_test_stage(4); 475 vmcall(); 476 cr0 = read_cr0(); 477 if (vmx_get_test_stage() != 5) 478 report("Read shadowing CR0", cr0 == guest_cr0); 479 vmx_set_test_stage(5); 480 cr4 = read_cr4(); 481 if (vmx_get_test_stage() != 6) 482 report("Read shadowing CR4", cr4 == guest_cr4); 483 // Test write shadow (same value with shadow) 484 vmx_set_test_stage(6); 485 write_cr0(guest_cr0); 486 if (vmx_get_test_stage() == 7) 487 report("Write shadowing CR0 (same value with shadow)", 0); 488 else 489 vmcall(); 490 vmx_set_test_stage(7); 491 write_cr4(guest_cr4); 492 if (vmx_get_test_stage() == 8) 493 report("Write shadowing CR4 (same value with shadow)", 0); 494 else 495 vmcall(); 496 // Test write shadow (different value) 497 vmx_set_test_stage(8); 498 tmp = guest_cr0 ^ X86_CR0_TS; 499 asm volatile("mov %0, %%rsi\n\t" 500 "mov %%rsi, %%cr0\n\t" 501 ::"m"(tmp) 502 :"rsi", "memory", "cc"); 503 report("Write shadowing different X86_CR0_TS", vmx_get_test_stage() == 9); 504 vmx_set_test_stage(9); 505 tmp = guest_cr0 ^ X86_CR0_MP; 506 asm volatile("mov %0, %%rsi\n\t" 507 "mov %%rsi, %%cr0\n\t" 508 ::"m"(tmp) 509 :"rsi", "memory", "cc"); 510 report("Write shadowing different X86_CR0_MP", vmx_get_test_stage() == 10); 511 vmx_set_test_stage(10); 512 tmp = guest_cr4 ^ X86_CR4_TSD; 513 asm volatile("mov %0, %%rsi\n\t" 514 "mov %%rsi, %%cr4\n\t" 515 ::"m"(tmp) 516 :"rsi", "memory", "cc"); 517 report("Write shadowing different X86_CR4_TSD", vmx_get_test_stage() == 11); 518 vmx_set_test_stage(11); 519 tmp = guest_cr4 ^ X86_CR4_DE; 520 asm volatile("mov %0, %%rsi\n\t" 521 "mov %%rsi, %%cr4\n\t" 522 ::"m"(tmp) 523 :"rsi", "memory", "cc"); 524 report("Write shadowing different X86_CR4_DE", vmx_get_test_stage() == 12); 525 } 526 527 static int cr_shadowing_exit_handler(void) 528 { 529 u64 guest_rip; 530 ulong reason; 531 u32 insn_len; 532 u32 exit_qual; 533 534 guest_rip = vmcs_read(GUEST_RIP); 535 reason = vmcs_read(EXI_REASON) & 0xff; 536 insn_len = vmcs_read(EXI_INST_LEN); 537 exit_qual = vmcs_read(EXI_QUALIFICATION); 538 switch (reason) { 539 case VMX_VMCALL: 540 switch (vmx_get_test_stage()) { 541 case 0: 542 report("Read through CR0", guest_cr0 == vmcs_read(GUEST_CR0)); 543 break; 544 case 1: 545 report("Read through CR4", guest_cr4 == vmcs_read(GUEST_CR4)); 546 break; 547 case 2: 548 report("Write through CR0", guest_cr0 == vmcs_read(GUEST_CR0)); 549 break; 550 case 3: 551 report("Write through CR4", guest_cr4 == vmcs_read(GUEST_CR4)); 552 break; 553 case 4: 554 guest_cr0 = vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP); 555 guest_cr4 = vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE); 556 vmcs_write(CR0_MASK, X86_CR0_TS | X86_CR0_MP); 557 vmcs_write(CR0_READ_SHADOW, guest_cr0 & (X86_CR0_TS | X86_CR0_MP)); 558 vmcs_write(CR4_MASK, X86_CR4_TSD | X86_CR4_DE); 559 vmcs_write(CR4_READ_SHADOW, guest_cr4 & (X86_CR4_TSD | X86_CR4_DE)); 560 break; 561 case 6: 562 report("Write shadowing CR0 (same value)", 563 guest_cr0 == (vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP))); 564 break; 565 case 7: 566 report("Write shadowing CR4 (same value)", 567 guest_cr4 == (vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE))); 568 break; 569 default: 570 // Should not reach here 571 report("unexpected stage, %d", false, 572 vmx_get_test_stage()); 573 print_vmexit_info(); 574 return VMX_TEST_VMEXIT; 575 } 576 vmcs_write(GUEST_RIP, guest_rip + insn_len); 577 return VMX_TEST_RESUME; 578 case VMX_CR: 579 switch (vmx_get_test_stage()) { 580 case 4: 581 report("Read shadowing CR0", 0); 582 vmx_inc_test_stage(); 583 break; 584 case 5: 585 report("Read shadowing CR4", 0); 586 vmx_inc_test_stage(); 587 break; 588 case 6: 589 report("Write shadowing CR0 (same value)", 0); 590 vmx_inc_test_stage(); 591 break; 592 case 7: 593 report("Write shadowing CR4 (same value)", 0); 594 vmx_inc_test_stage(); 595 break; 596 case 8: 597 case 9: 598 // 0x600 encodes "mov %esi, %cr0" 599 if (exit_qual == 0x600) 600 vmx_inc_test_stage(); 601 break; 602 case 10: 603 case 11: 604 // 0x604 encodes "mov %esi, %cr4" 605 if (exit_qual == 0x604) 606 vmx_inc_test_stage(); 607 break; 608 default: 609 // Should not reach here 610 report("unexpected stage, %d", false, 611 vmx_get_test_stage()); 612 print_vmexit_info(); 613 return VMX_TEST_VMEXIT; 614 } 615 vmcs_write(GUEST_RIP, guest_rip + insn_len); 616 return VMX_TEST_RESUME; 617 default: 618 report("Unknown exit reason, %ld", false, reason); 619 print_vmexit_info(); 620 } 621 return VMX_TEST_VMEXIT; 622 } 623 624 static int iobmp_init(struct vmcs *vmcs) 625 { 626 u32 ctrl_cpu0; 627 628 io_bitmap_a = alloc_page(); 629 io_bitmap_b = alloc_page(); 630 memset(io_bitmap_a, 0x0, PAGE_SIZE); 631 memset(io_bitmap_b, 0x0, PAGE_SIZE); 632 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 633 ctrl_cpu0 |= CPU_IO_BITMAP; 634 ctrl_cpu0 &= (~CPU_IO); 635 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 636 vmcs_write(IO_BITMAP_A, (u64)io_bitmap_a); 637 vmcs_write(IO_BITMAP_B, (u64)io_bitmap_b); 638 return VMX_TEST_START; 639 } 640 641 static void iobmp_main(void) 642 { 643 // stage 0, test IO pass 644 vmx_set_test_stage(0); 645 inb(0x5000); 646 outb(0x0, 0x5000); 647 report("I/O bitmap - I/O pass", vmx_get_test_stage() == 0); 648 // test IO width, in/out 649 ((u8 *)io_bitmap_a)[0] = 0xFF; 650 vmx_set_test_stage(2); 651 inb(0x0); 652 report("I/O bitmap - trap in", vmx_get_test_stage() == 3); 653 vmx_set_test_stage(3); 654 outw(0x0, 0x0); 655 report("I/O bitmap - trap out", vmx_get_test_stage() == 4); 656 vmx_set_test_stage(4); 657 inl(0x0); 658 report("I/O bitmap - I/O width, long", vmx_get_test_stage() == 5); 659 // test low/high IO port 660 vmx_set_test_stage(5); 661 ((u8 *)io_bitmap_a)[0x5000 / 8] = (1 << (0x5000 % 8)); 662 inb(0x5000); 663 report("I/O bitmap - I/O port, low part", vmx_get_test_stage() == 6); 664 vmx_set_test_stage(6); 665 ((u8 *)io_bitmap_b)[0x1000 / 8] = (1 << (0x1000 % 8)); 666 inb(0x9000); 667 report("I/O bitmap - I/O port, high part", vmx_get_test_stage() == 7); 668 // test partial pass 669 vmx_set_test_stage(7); 670 inl(0x4FFF); 671 report("I/O bitmap - partial pass", vmx_get_test_stage() == 8); 672 // test overrun 673 vmx_set_test_stage(8); 674 memset(io_bitmap_a, 0x0, PAGE_SIZE); 675 memset(io_bitmap_b, 0x0, PAGE_SIZE); 676 inl(0xFFFF); 677 report("I/O bitmap - overrun", vmx_get_test_stage() == 9); 678 vmx_set_test_stage(9); 679 vmcall(); 680 outb(0x0, 0x0); 681 report("I/O bitmap - ignore unconditional exiting", 682 vmx_get_test_stage() == 9); 683 vmx_set_test_stage(10); 684 vmcall(); 685 outb(0x0, 0x0); 686 report("I/O bitmap - unconditional exiting", 687 vmx_get_test_stage() == 11); 688 } 689 690 static int iobmp_exit_handler(void) 691 { 692 u64 guest_rip; 693 ulong reason, exit_qual; 694 u32 insn_len, ctrl_cpu0; 695 696 guest_rip = vmcs_read(GUEST_RIP); 697 reason = vmcs_read(EXI_REASON) & 0xff; 698 exit_qual = vmcs_read(EXI_QUALIFICATION); 699 insn_len = vmcs_read(EXI_INST_LEN); 700 switch (reason) { 701 case VMX_IO: 702 switch (vmx_get_test_stage()) { 703 case 0: 704 case 1: 705 vmx_inc_test_stage(); 706 break; 707 case 2: 708 report("I/O bitmap - I/O width, byte", 709 (exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_BYTE); 710 report("I/O bitmap - I/O direction, in", exit_qual & VMX_IO_IN); 711 vmx_inc_test_stage(); 712 break; 713 case 3: 714 report("I/O bitmap - I/O width, word", 715 (exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_WORD); 716 report("I/O bitmap - I/O direction, out", 717 !(exit_qual & VMX_IO_IN)); 718 vmx_inc_test_stage(); 719 break; 720 case 4: 721 report("I/O bitmap - I/O width, long", 722 (exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_LONG); 723 vmx_inc_test_stage(); 724 break; 725 case 5: 726 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x5000) 727 vmx_inc_test_stage(); 728 break; 729 case 6: 730 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x9000) 731 vmx_inc_test_stage(); 732 break; 733 case 7: 734 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x4FFF) 735 vmx_inc_test_stage(); 736 break; 737 case 8: 738 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0xFFFF) 739 vmx_inc_test_stage(); 740 break; 741 case 9: 742 case 10: 743 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 744 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0 & ~CPU_IO); 745 vmx_inc_test_stage(); 746 break; 747 default: 748 // Should not reach here 749 report("unexpected stage, %d", false, 750 vmx_get_test_stage()); 751 print_vmexit_info(); 752 return VMX_TEST_VMEXIT; 753 } 754 vmcs_write(GUEST_RIP, guest_rip + insn_len); 755 return VMX_TEST_RESUME; 756 case VMX_VMCALL: 757 switch (vmx_get_test_stage()) { 758 case 9: 759 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 760 ctrl_cpu0 |= CPU_IO | CPU_IO_BITMAP; 761 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 762 break; 763 case 10: 764 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 765 ctrl_cpu0 = (ctrl_cpu0 & ~CPU_IO_BITMAP) | CPU_IO; 766 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 767 break; 768 default: 769 // Should not reach here 770 report("unexpected stage, %d", false, 771 vmx_get_test_stage()); 772 print_vmexit_info(); 773 return VMX_TEST_VMEXIT; 774 } 775 vmcs_write(GUEST_RIP, guest_rip + insn_len); 776 return VMX_TEST_RESUME; 777 default: 778 printf("guest_rip = %#lx\n", guest_rip); 779 printf("\tERROR : Undefined exit reason, reason = %ld.\n", reason); 780 break; 781 } 782 return VMX_TEST_VMEXIT; 783 } 784 785 #define INSN_CPU0 0 786 #define INSN_CPU1 1 787 #define INSN_ALWAYS_TRAP 2 788 789 #define FIELD_EXIT_QUAL (1 << 0) 790 #define FIELD_INSN_INFO (1 << 1) 791 792 asm( 793 "insn_hlt: hlt;ret\n\t" 794 "insn_invlpg: invlpg 0x12345678;ret\n\t" 795 "insn_mwait: xor %eax, %eax; xor %ecx, %ecx; mwait;ret\n\t" 796 "insn_rdpmc: xor %ecx, %ecx; rdpmc;ret\n\t" 797 "insn_rdtsc: rdtsc;ret\n\t" 798 "insn_cr3_load: mov cr3,%rax; mov %rax,%cr3;ret\n\t" 799 "insn_cr3_store: mov %cr3,%rax;ret\n\t" 800 #ifdef __x86_64__ 801 "insn_cr8_load: xor %eax, %eax; mov %rax,%cr8;ret\n\t" 802 "insn_cr8_store: mov %cr8,%rax;ret\n\t" 803 #endif 804 "insn_monitor: xor %eax, %eax; xor %ecx, %ecx; xor %edx, %edx; monitor;ret\n\t" 805 "insn_pause: pause;ret\n\t" 806 "insn_wbinvd: wbinvd;ret\n\t" 807 "insn_cpuid: mov $10, %eax; cpuid;ret\n\t" 808 "insn_invd: invd;ret\n\t" 809 "insn_sgdt: sgdt gdt64_desc;ret\n\t" 810 "insn_lgdt: lgdt gdt64_desc;ret\n\t" 811 "insn_sidt: sidt idt_descr;ret\n\t" 812 "insn_lidt: lidt idt_descr;ret\n\t" 813 "insn_sldt: sldt %ax;ret\n\t" 814 "insn_lldt: xor %eax, %eax; lldt %ax;ret\n\t" 815 "insn_str: str %ax;ret\n\t" 816 "insn_rdrand: rdrand %rax;ret\n\t" 817 "insn_rdseed: rdseed %rax;ret\n\t" 818 ); 819 extern void insn_hlt(void); 820 extern void insn_invlpg(void); 821 extern void insn_mwait(void); 822 extern void insn_rdpmc(void); 823 extern void insn_rdtsc(void); 824 extern void insn_cr3_load(void); 825 extern void insn_cr3_store(void); 826 #ifdef __x86_64__ 827 extern void insn_cr8_load(void); 828 extern void insn_cr8_store(void); 829 #endif 830 extern void insn_monitor(void); 831 extern void insn_pause(void); 832 extern void insn_wbinvd(void); 833 extern void insn_sgdt(void); 834 extern void insn_lgdt(void); 835 extern void insn_sidt(void); 836 extern void insn_lidt(void); 837 extern void insn_sldt(void); 838 extern void insn_lldt(void); 839 extern void insn_str(void); 840 extern void insn_cpuid(void); 841 extern void insn_invd(void); 842 extern void insn_rdrand(void); 843 extern void insn_rdseed(void); 844 845 u32 cur_insn; 846 u64 cr3; 847 848 struct insn_table { 849 const char *name; 850 u32 flag; 851 void (*insn_func)(void); 852 u32 type; 853 u32 reason; 854 ulong exit_qual; 855 u32 insn_info; 856 // Use FIELD_EXIT_QUAL and FIELD_INSN_INFO to define 857 // which field need to be tested, reason is always tested 858 u32 test_field; 859 }; 860 861 /* 862 * Add more test cases of instruction intercept here. Elements in this 863 * table is: 864 * name/control flag/insn function/type/exit reason/exit qulification/ 865 * instruction info/field to test 866 * The last field defines which fields (exit_qual and insn_info) need to be 867 * tested in exit handler. If set to 0, only "reason" is checked. 868 */ 869 static struct insn_table insn_table[] = { 870 // Flags for Primary Processor-Based VM-Execution Controls 871 {"HLT", CPU_HLT, insn_hlt, INSN_CPU0, 12, 0, 0, 0}, 872 {"INVLPG", CPU_INVLPG, insn_invlpg, INSN_CPU0, 14, 873 0x12345678, 0, FIELD_EXIT_QUAL}, 874 {"MWAIT", CPU_MWAIT, insn_mwait, INSN_CPU0, 36, 0, 0, 0}, 875 {"RDPMC", CPU_RDPMC, insn_rdpmc, INSN_CPU0, 15, 0, 0, 0}, 876 {"RDTSC", CPU_RDTSC, insn_rdtsc, INSN_CPU0, 16, 0, 0, 0}, 877 {"CR3 load", CPU_CR3_LOAD, insn_cr3_load, INSN_CPU0, 28, 0x3, 0, 878 FIELD_EXIT_QUAL}, 879 {"CR3 store", CPU_CR3_STORE, insn_cr3_store, INSN_CPU0, 28, 0x13, 0, 880 FIELD_EXIT_QUAL}, 881 #ifdef __x86_64__ 882 {"CR8 load", CPU_CR8_LOAD, insn_cr8_load, INSN_CPU0, 28, 0x8, 0, 883 FIELD_EXIT_QUAL}, 884 {"CR8 store", CPU_CR8_STORE, insn_cr8_store, INSN_CPU0, 28, 0x18, 0, 885 FIELD_EXIT_QUAL}, 886 #endif 887 {"MONITOR", CPU_MONITOR, insn_monitor, INSN_CPU0, 39, 0, 0, 0}, 888 {"PAUSE", CPU_PAUSE, insn_pause, INSN_CPU0, 40, 0, 0, 0}, 889 // Flags for Secondary Processor-Based VM-Execution Controls 890 {"WBINVD", CPU_WBINVD, insn_wbinvd, INSN_CPU1, 54, 0, 0, 0}, 891 {"DESC_TABLE (SGDT)", CPU_DESC_TABLE, insn_sgdt, INSN_CPU1, 46, 0, 0, 0}, 892 {"DESC_TABLE (LGDT)", CPU_DESC_TABLE, insn_lgdt, INSN_CPU1, 46, 0, 0, 0}, 893 {"DESC_TABLE (SIDT)", CPU_DESC_TABLE, insn_sidt, INSN_CPU1, 46, 0, 0, 0}, 894 {"DESC_TABLE (LIDT)", CPU_DESC_TABLE, insn_lidt, INSN_CPU1, 46, 0, 0, 0}, 895 {"DESC_TABLE (SLDT)", CPU_DESC_TABLE, insn_sldt, INSN_CPU1, 47, 0, 0, 0}, 896 {"DESC_TABLE (LLDT)", CPU_DESC_TABLE, insn_lldt, INSN_CPU1, 47, 0, 0, 0}, 897 {"DESC_TABLE (STR)", CPU_DESC_TABLE, insn_str, INSN_CPU1, 47, 0, 0, 0}, 898 /* LTR causes a #GP if done with a busy selector, so it is not tested. */ 899 {"RDRAND", CPU_RDRAND, insn_rdrand, INSN_CPU1, VMX_RDRAND, 0, 0, 0}, 900 {"RDSEED", CPU_RDSEED, insn_rdseed, INSN_CPU1, VMX_RDSEED, 0, 0, 0}, 901 // Instructions always trap 902 {"CPUID", 0, insn_cpuid, INSN_ALWAYS_TRAP, 10, 0, 0, 0}, 903 {"INVD", 0, insn_invd, INSN_ALWAYS_TRAP, 13, 0, 0, 0}, 904 // Instructions never trap 905 {NULL}, 906 }; 907 908 static int insn_intercept_init(struct vmcs *vmcs) 909 { 910 u32 ctrl_cpu; 911 912 ctrl_cpu = ctrl_cpu_rev[0].set | CPU_SECONDARY; 913 ctrl_cpu &= ctrl_cpu_rev[0].clr; 914 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu); 915 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu_rev[1].set); 916 cr3 = read_cr3(); 917 return VMX_TEST_START; 918 } 919 920 static void insn_intercept_main(void) 921 { 922 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 923 vmx_set_test_stage(cur_insn * 2); 924 if ((insn_table[cur_insn].type == INSN_CPU0 && 925 !(ctrl_cpu_rev[0].clr & insn_table[cur_insn].flag)) || 926 (insn_table[cur_insn].type == INSN_CPU1 && 927 !(ctrl_cpu_rev[1].clr & insn_table[cur_insn].flag))) { 928 printf("\tCPU_CTRL%d.CPU_%s is not supported.\n", 929 insn_table[cur_insn].type - INSN_CPU0, 930 insn_table[cur_insn].name); 931 continue; 932 } 933 934 if ((insn_table[cur_insn].type == INSN_CPU0 && 935 !(ctrl_cpu_rev[0].set & insn_table[cur_insn].flag)) || 936 (insn_table[cur_insn].type == INSN_CPU1 && 937 !(ctrl_cpu_rev[1].set & insn_table[cur_insn].flag))) { 938 /* skip hlt, it stalls the guest and is tested below */ 939 if (insn_table[cur_insn].insn_func != insn_hlt) 940 insn_table[cur_insn].insn_func(); 941 report("execute %s", vmx_get_test_stage() == cur_insn * 2, 942 insn_table[cur_insn].name); 943 } else if (insn_table[cur_insn].type != INSN_ALWAYS_TRAP) 944 printf("\tCPU_CTRL%d.CPU_%s always traps.\n", 945 insn_table[cur_insn].type - INSN_CPU0, 946 insn_table[cur_insn].name); 947 948 vmcall(); 949 950 insn_table[cur_insn].insn_func(); 951 report("intercept %s", vmx_get_test_stage() == cur_insn * 2 + 1, 952 insn_table[cur_insn].name); 953 954 vmx_set_test_stage(cur_insn * 2 + 1); 955 vmcall(); 956 } 957 } 958 959 static int insn_intercept_exit_handler(void) 960 { 961 u64 guest_rip; 962 u32 reason; 963 ulong exit_qual; 964 u32 insn_len; 965 u32 insn_info; 966 bool pass; 967 968 guest_rip = vmcs_read(GUEST_RIP); 969 reason = vmcs_read(EXI_REASON) & 0xff; 970 exit_qual = vmcs_read(EXI_QUALIFICATION); 971 insn_len = vmcs_read(EXI_INST_LEN); 972 insn_info = vmcs_read(EXI_INST_INFO); 973 974 if (reason == VMX_VMCALL) { 975 u32 val = 0; 976 977 if (insn_table[cur_insn].type == INSN_CPU0) 978 val = vmcs_read(CPU_EXEC_CTRL0); 979 else if (insn_table[cur_insn].type == INSN_CPU1) 980 val = vmcs_read(CPU_EXEC_CTRL1); 981 982 if (vmx_get_test_stage() & 1) 983 val &= ~insn_table[cur_insn].flag; 984 else 985 val |= insn_table[cur_insn].flag; 986 987 if (insn_table[cur_insn].type == INSN_CPU0) 988 vmcs_write(CPU_EXEC_CTRL0, val | ctrl_cpu_rev[0].set); 989 else if (insn_table[cur_insn].type == INSN_CPU1) 990 vmcs_write(CPU_EXEC_CTRL1, val | ctrl_cpu_rev[1].set); 991 } else { 992 pass = (cur_insn * 2 == vmx_get_test_stage()) && 993 insn_table[cur_insn].reason == reason; 994 if (insn_table[cur_insn].test_field & FIELD_EXIT_QUAL && 995 insn_table[cur_insn].exit_qual != exit_qual) 996 pass = false; 997 if (insn_table[cur_insn].test_field & FIELD_INSN_INFO && 998 insn_table[cur_insn].insn_info != insn_info) 999 pass = false; 1000 if (pass) 1001 vmx_inc_test_stage(); 1002 } 1003 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1004 return VMX_TEST_RESUME; 1005 } 1006 1007 static int setup_eptp(u64 hpa, bool enable_ad) 1008 { 1009 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1010 !(ctrl_cpu_rev[1].clr & CPU_EPT)) { 1011 printf("\tEPT is not supported"); 1012 return 1; 1013 } 1014 1015 if (!(ept_vpid.val & EPT_CAP_UC) && 1016 !(ept_vpid.val & EPT_CAP_WB)) { 1017 printf("\tEPT paging-structure memory type " 1018 "UC&WB are not supported\n"); 1019 return 1; 1020 } 1021 if (!(ept_vpid.val & EPT_CAP_PWL4)) { 1022 printf("\tPWL4 is not supported\n"); 1023 return 1; 1024 } 1025 1026 if (ept_vpid.val & EPT_CAP_UC) 1027 eptp = EPT_MEM_TYPE_UC; 1028 else 1029 eptp = EPT_MEM_TYPE_WB; 1030 eptp |= (3 << EPTP_PG_WALK_LEN_SHIFT); 1031 eptp |= hpa; 1032 if (enable_ad) 1033 eptp |= EPTP_AD_FLAG; 1034 1035 vmcs_write(EPTP, eptp); 1036 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0)| CPU_SECONDARY); 1037 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1)| CPU_EPT); 1038 1039 return 0; 1040 } 1041 1042 /* Enables EPT and sets up the identity map. */ 1043 static int setup_ept(bool enable_ad) 1044 { 1045 unsigned long end_of_memory; 1046 1047 pml4 = alloc_page(); 1048 1049 if (setup_eptp(virt_to_phys(pml4), enable_ad)) 1050 return 1; 1051 1052 memset(pml4, 0, PAGE_SIZE); 1053 1054 end_of_memory = fwcfg_get_u64(FW_CFG_RAM_SIZE); 1055 if (end_of_memory < (1ul << 32)) 1056 end_of_memory = (1ul << 32); 1057 /* Cannot use large EPT pages if we need to track EPT 1058 * accessed/dirty bits at 4K granularity. 1059 */ 1060 setup_ept_range(pml4, 0, end_of_memory, 0, 1061 !enable_ad && ept_2m_supported(), 1062 EPT_WA | EPT_RA | EPT_EA); 1063 return 0; 1064 } 1065 1066 static void enable_ept(void) 1067 { 1068 if (setup_eptp(0, false)) 1069 report_abort("EPT setup unexpectedly failed"); 1070 } 1071 1072 static int enable_unrestricted_guest(void) 1073 { 1074 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1075 !(ctrl_cpu_rev[1].clr & CPU_URG) || 1076 !(ctrl_cpu_rev[1].clr & CPU_EPT)) 1077 return 1; 1078 1079 enable_ept(); 1080 1081 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 1082 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | CPU_URG); 1083 1084 return 0; 1085 } 1086 1087 static void ept_enable_ad_bits(void) 1088 { 1089 eptp |= EPTP_AD_FLAG; 1090 vmcs_write(EPTP, eptp); 1091 } 1092 1093 static void ept_disable_ad_bits(void) 1094 { 1095 eptp &= ~EPTP_AD_FLAG; 1096 vmcs_write(EPTP, eptp); 1097 } 1098 1099 static void ept_enable_ad_bits_or_skip_test(void) 1100 { 1101 if (!ept_ad_bits_supported()) 1102 test_skip("EPT AD bits not supported."); 1103 ept_enable_ad_bits(); 1104 } 1105 1106 static int apic_version; 1107 1108 static int ept_init_common(bool have_ad) 1109 { 1110 int ret; 1111 struct pci_dev pcidev; 1112 1113 if (setup_ept(have_ad)) 1114 return VMX_TEST_EXIT; 1115 data_page1 = alloc_page(); 1116 data_page2 = alloc_page(); 1117 memset(data_page1, 0x0, PAGE_SIZE); 1118 memset(data_page2, 0x0, PAGE_SIZE); 1119 *((u32 *)data_page1) = MAGIC_VAL_1; 1120 *((u32 *)data_page2) = MAGIC_VAL_2; 1121 install_ept(pml4, (unsigned long)data_page1, (unsigned long)data_page2, 1122 EPT_RA | EPT_WA | EPT_EA); 1123 1124 apic_version = apic_read(APIC_LVR); 1125 1126 ret = pci_find_dev(PCI_VENDOR_ID_REDHAT, PCI_DEVICE_ID_REDHAT_TEST); 1127 if (ret != PCIDEVADDR_INVALID) { 1128 pci_dev_init(&pcidev, ret); 1129 pci_physaddr = pcidev.resource[PCI_TESTDEV_BAR_MEM]; 1130 } 1131 1132 return VMX_TEST_START; 1133 } 1134 1135 static int ept_init(struct vmcs *vmcs) 1136 { 1137 return ept_init_common(false); 1138 } 1139 1140 static void ept_common(void) 1141 { 1142 vmx_set_test_stage(0); 1143 if (*((u32 *)data_page2) != MAGIC_VAL_1 || 1144 *((u32 *)data_page1) != MAGIC_VAL_1) 1145 report("EPT basic framework - read", 0); 1146 else { 1147 *((u32 *)data_page2) = MAGIC_VAL_3; 1148 vmcall(); 1149 if (vmx_get_test_stage() == 1) { 1150 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1151 *((u32 *)data_page2) == MAGIC_VAL_2) 1152 report("EPT basic framework", 1); 1153 else 1154 report("EPT basic framework - remap", 1); 1155 } 1156 } 1157 // Test EPT Misconfigurations 1158 vmx_set_test_stage(1); 1159 vmcall(); 1160 *((u32 *)data_page1) = MAGIC_VAL_1; 1161 if (vmx_get_test_stage() != 2) { 1162 report("EPT misconfigurations", 0); 1163 goto t1; 1164 } 1165 vmx_set_test_stage(2); 1166 vmcall(); 1167 *((u32 *)data_page1) = MAGIC_VAL_1; 1168 report("EPT misconfigurations", vmx_get_test_stage() == 3); 1169 t1: 1170 // Test EPT violation 1171 vmx_set_test_stage(3); 1172 vmcall(); 1173 *((u32 *)data_page1) = MAGIC_VAL_1; 1174 report("EPT violation - page permission", vmx_get_test_stage() == 4); 1175 // Violation caused by EPT paging structure 1176 vmx_set_test_stage(4); 1177 vmcall(); 1178 *((u32 *)data_page1) = MAGIC_VAL_2; 1179 report("EPT violation - paging structure", vmx_get_test_stage() == 5); 1180 1181 // MMIO Read/Write 1182 vmx_set_test_stage(5); 1183 vmcall(); 1184 1185 *(u32 volatile *)pci_physaddr; 1186 report("MMIO EPT violation - read", vmx_get_test_stage() == 6); 1187 1188 *(u32 volatile *)pci_physaddr = MAGIC_VAL_1; 1189 report("MMIO EPT violation - write", vmx_get_test_stage() == 7); 1190 } 1191 1192 static void ept_main(void) 1193 { 1194 ept_common(); 1195 1196 // Test EPT access to L1 MMIO 1197 vmx_set_test_stage(7); 1198 report("EPT - MMIO access", *((u32 *)0xfee00030UL) == apic_version); 1199 1200 // Test invalid operand for INVEPT 1201 vmcall(); 1202 report("EPT - unsupported INVEPT", vmx_get_test_stage() == 8); 1203 } 1204 1205 static bool invept_test(int type, u64 eptp) 1206 { 1207 bool ret, supported; 1208 1209 supported = ept_vpid.val & (EPT_CAP_INVEPT_SINGLE >> INVEPT_SINGLE << type); 1210 ret = invept(type, eptp); 1211 1212 if (ret == !supported) 1213 return false; 1214 1215 if (!supported) 1216 printf("WARNING: unsupported invept passed!\n"); 1217 else 1218 printf("WARNING: invept failed!\n"); 1219 1220 return true; 1221 } 1222 1223 static int pml_exit_handler(void) 1224 { 1225 u16 index, count; 1226 ulong reason = vmcs_read(EXI_REASON) & 0xff; 1227 u64 *pmlbuf = pml_log; 1228 u64 guest_rip = vmcs_read(GUEST_RIP);; 1229 u64 guest_cr3 = vmcs_read(GUEST_CR3); 1230 u32 insn_len = vmcs_read(EXI_INST_LEN); 1231 1232 switch (reason) { 1233 case VMX_VMCALL: 1234 switch (vmx_get_test_stage()) { 1235 case 0: 1236 index = vmcs_read(GUEST_PML_INDEX); 1237 for (count = index + 1; count < PML_INDEX; count++) { 1238 if (pmlbuf[count] == (u64)data_page2) { 1239 vmx_inc_test_stage(); 1240 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1241 break; 1242 } 1243 } 1244 break; 1245 case 1: 1246 index = vmcs_read(GUEST_PML_INDEX); 1247 /* Keep clearing the dirty bit till a overflow */ 1248 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1249 break; 1250 default: 1251 report("unexpected stage, %d.", false, 1252 vmx_get_test_stage()); 1253 print_vmexit_info(); 1254 return VMX_TEST_VMEXIT; 1255 } 1256 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1257 return VMX_TEST_RESUME; 1258 case VMX_PML_FULL: 1259 vmx_inc_test_stage(); 1260 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1261 return VMX_TEST_RESUME; 1262 default: 1263 report("Unknown exit reason, %ld", false, reason); 1264 print_vmexit_info(); 1265 } 1266 return VMX_TEST_VMEXIT; 1267 } 1268 1269 static int ept_exit_handler_common(bool have_ad) 1270 { 1271 u64 guest_rip; 1272 u64 guest_cr3; 1273 ulong reason; 1274 u32 insn_len; 1275 u32 exit_qual; 1276 static unsigned long data_page1_pte, data_page1_pte_pte, memaddr_pte; 1277 1278 guest_rip = vmcs_read(GUEST_RIP); 1279 guest_cr3 = vmcs_read(GUEST_CR3); 1280 reason = vmcs_read(EXI_REASON) & 0xff; 1281 insn_len = vmcs_read(EXI_INST_LEN); 1282 exit_qual = vmcs_read(EXI_QUALIFICATION); 1283 switch (reason) { 1284 case VMX_VMCALL: 1285 switch (vmx_get_test_stage()) { 1286 case 0: 1287 check_ept_ad(pml4, guest_cr3, 1288 (unsigned long)data_page1, 1289 have_ad ? EPT_ACCESS_FLAG : 0, 1290 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1291 check_ept_ad(pml4, guest_cr3, 1292 (unsigned long)data_page2, 1293 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0, 1294 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1295 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1296 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1297 if (have_ad) 1298 ept_sync(INVEPT_SINGLE, eptp);; 1299 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1300 *((u32 *)data_page2) == MAGIC_VAL_2) { 1301 vmx_inc_test_stage(); 1302 install_ept(pml4, (unsigned long)data_page2, 1303 (unsigned long)data_page2, 1304 EPT_RA | EPT_WA | EPT_EA); 1305 } else 1306 report("EPT basic framework - write", 0); 1307 break; 1308 case 1: 1309 install_ept(pml4, (unsigned long)data_page1, 1310 (unsigned long)data_page1, EPT_WA); 1311 ept_sync(INVEPT_SINGLE, eptp); 1312 break; 1313 case 2: 1314 install_ept(pml4, (unsigned long)data_page1, 1315 (unsigned long)data_page1, 1316 EPT_RA | EPT_WA | EPT_EA | 1317 (2 << EPT_MEM_TYPE_SHIFT)); 1318 ept_sync(INVEPT_SINGLE, eptp); 1319 break; 1320 case 3: 1321 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1322 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)data_page1, 1323 1, &data_page1_pte)); 1324 set_ept_pte(pml4, (unsigned long)data_page1, 1325 1, data_page1_pte & ~EPT_PRESENT); 1326 ept_sync(INVEPT_SINGLE, eptp); 1327 break; 1328 case 4: 1329 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)data_page1, 1330 2, &data_page1_pte)); 1331 data_page1_pte &= PAGE_MASK; 1332 TEST_ASSERT(get_ept_pte(pml4, data_page1_pte, 1333 2, &data_page1_pte_pte)); 1334 set_ept_pte(pml4, data_page1_pte, 2, 1335 data_page1_pte_pte & ~EPT_PRESENT); 1336 ept_sync(INVEPT_SINGLE, eptp); 1337 break; 1338 case 5: 1339 install_ept(pml4, (unsigned long)pci_physaddr, 1340 (unsigned long)pci_physaddr, 0); 1341 ept_sync(INVEPT_SINGLE, eptp); 1342 break; 1343 case 7: 1344 if (!invept_test(0, eptp)) 1345 vmx_inc_test_stage(); 1346 break; 1347 // Should not reach here 1348 default: 1349 report("ERROR - unexpected stage, %d.", false, 1350 vmx_get_test_stage()); 1351 print_vmexit_info(); 1352 return VMX_TEST_VMEXIT; 1353 } 1354 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1355 return VMX_TEST_RESUME; 1356 case VMX_EPT_MISCONFIG: 1357 switch (vmx_get_test_stage()) { 1358 case 1: 1359 case 2: 1360 vmx_inc_test_stage(); 1361 install_ept(pml4, (unsigned long)data_page1, 1362 (unsigned long)data_page1, 1363 EPT_RA | EPT_WA | EPT_EA); 1364 ept_sync(INVEPT_SINGLE, eptp); 1365 break; 1366 // Should not reach here 1367 default: 1368 report("ERROR - unexpected stage, %d.", false, 1369 vmx_get_test_stage()); 1370 print_vmexit_info(); 1371 return VMX_TEST_VMEXIT; 1372 } 1373 return VMX_TEST_RESUME; 1374 case VMX_EPT_VIOLATION: 1375 switch(vmx_get_test_stage()) { 1376 case 3: 1377 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1378 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1379 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1380 if (exit_qual == (EPT_VLT_WR | EPT_VLT_LADDR_VLD | 1381 EPT_VLT_PADDR)) 1382 vmx_inc_test_stage(); 1383 set_ept_pte(pml4, (unsigned long)data_page1, 1384 1, data_page1_pte | (EPT_PRESENT)); 1385 ept_sync(INVEPT_SINGLE, eptp); 1386 break; 1387 case 4: 1388 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1389 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1390 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1391 if (exit_qual == (EPT_VLT_RD | 1392 (have_ad ? EPT_VLT_WR : 0) | 1393 EPT_VLT_LADDR_VLD)) 1394 vmx_inc_test_stage(); 1395 set_ept_pte(pml4, data_page1_pte, 2, 1396 data_page1_pte_pte | (EPT_PRESENT)); 1397 ept_sync(INVEPT_SINGLE, eptp); 1398 break; 1399 case 5: 1400 if (exit_qual & EPT_VLT_RD) 1401 vmx_inc_test_stage(); 1402 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1403 1, &memaddr_pte)); 1404 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA); 1405 ept_sync(INVEPT_SINGLE, eptp); 1406 break; 1407 case 6: 1408 if (exit_qual & EPT_VLT_WR) 1409 vmx_inc_test_stage(); 1410 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1411 1, &memaddr_pte)); 1412 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA | EPT_WA); 1413 ept_sync(INVEPT_SINGLE, eptp); 1414 break; 1415 default: 1416 // Should not reach here 1417 report("ERROR : unexpected stage, %d", false, 1418 vmx_get_test_stage()); 1419 print_vmexit_info(); 1420 return VMX_TEST_VMEXIT; 1421 } 1422 return VMX_TEST_RESUME; 1423 default: 1424 report("Unknown exit reason, %ld", false, reason); 1425 print_vmexit_info(); 1426 } 1427 return VMX_TEST_VMEXIT; 1428 } 1429 1430 static int ept_exit_handler(void) 1431 { 1432 return ept_exit_handler_common(false); 1433 } 1434 1435 static int eptad_init(struct vmcs *vmcs) 1436 { 1437 int r = ept_init_common(true); 1438 1439 if (r == VMX_TEST_EXIT) 1440 return r; 1441 1442 if ((rdmsr(MSR_IA32_VMX_EPT_VPID_CAP) & EPT_CAP_AD_FLAG) == 0) { 1443 printf("\tEPT A/D bits are not supported"); 1444 return VMX_TEST_EXIT; 1445 } 1446 1447 return r; 1448 } 1449 1450 static int pml_init(struct vmcs *vmcs) 1451 { 1452 u32 ctrl_cpu; 1453 int r = eptad_init(vmcs); 1454 1455 if (r == VMX_TEST_EXIT) 1456 return r; 1457 1458 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1459 !(ctrl_cpu_rev[1].clr & CPU_PML)) { 1460 printf("\tPML is not supported"); 1461 return VMX_TEST_EXIT; 1462 } 1463 1464 pml_log = alloc_page(); 1465 memset(pml_log, 0x0, PAGE_SIZE); 1466 vmcs_write(PMLADDR, (u64)pml_log); 1467 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1468 1469 ctrl_cpu = vmcs_read(CPU_EXEC_CTRL1) | CPU_PML; 1470 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu); 1471 1472 return VMX_TEST_START; 1473 } 1474 1475 static void pml_main(void) 1476 { 1477 int count = 0; 1478 1479 vmx_set_test_stage(0); 1480 *((u32 *)data_page2) = 0x1; 1481 vmcall(); 1482 report("PML - Dirty GPA Logging", vmx_get_test_stage() == 1); 1483 1484 while (vmx_get_test_stage() == 1) { 1485 vmcall(); 1486 *((u32 *)data_page2) = 0x1; 1487 if (count++ > PML_INDEX) 1488 break; 1489 } 1490 report("PML Full Event", vmx_get_test_stage() == 2); 1491 } 1492 1493 static void eptad_main(void) 1494 { 1495 ept_common(); 1496 } 1497 1498 static int eptad_exit_handler(void) 1499 { 1500 return ept_exit_handler_common(true); 1501 } 1502 1503 static bool invvpid_test(int type, u16 vpid) 1504 { 1505 bool ret, supported; 1506 1507 supported = ept_vpid.val & 1508 (VPID_CAP_INVVPID_ADDR >> INVVPID_ADDR << type); 1509 ret = invvpid(type, vpid, 0); 1510 1511 if (ret == !supported) 1512 return false; 1513 1514 if (!supported) 1515 printf("WARNING: unsupported invvpid passed!\n"); 1516 else 1517 printf("WARNING: invvpid failed!\n"); 1518 1519 return true; 1520 } 1521 1522 static int vpid_init(struct vmcs *vmcs) 1523 { 1524 u32 ctrl_cpu1; 1525 1526 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1527 !(ctrl_cpu_rev[1].clr & CPU_VPID)) { 1528 printf("\tVPID is not supported"); 1529 return VMX_TEST_EXIT; 1530 } 1531 1532 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 1533 ctrl_cpu1 |= CPU_VPID; 1534 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 1535 return VMX_TEST_START; 1536 } 1537 1538 static void vpid_main(void) 1539 { 1540 vmx_set_test_stage(0); 1541 vmcall(); 1542 report("INVVPID SINGLE ADDRESS", vmx_get_test_stage() == 1); 1543 vmx_set_test_stage(2); 1544 vmcall(); 1545 report("INVVPID SINGLE", vmx_get_test_stage() == 3); 1546 vmx_set_test_stage(4); 1547 vmcall(); 1548 report("INVVPID ALL", vmx_get_test_stage() == 5); 1549 } 1550 1551 static int vpid_exit_handler(void) 1552 { 1553 u64 guest_rip; 1554 ulong reason; 1555 u32 insn_len; 1556 1557 guest_rip = vmcs_read(GUEST_RIP); 1558 reason = vmcs_read(EXI_REASON) & 0xff; 1559 insn_len = vmcs_read(EXI_INST_LEN); 1560 1561 switch (reason) { 1562 case VMX_VMCALL: 1563 switch(vmx_get_test_stage()) { 1564 case 0: 1565 if (!invvpid_test(INVVPID_ADDR, 1)) 1566 vmx_inc_test_stage(); 1567 break; 1568 case 2: 1569 if (!invvpid_test(INVVPID_CONTEXT_GLOBAL, 1)) 1570 vmx_inc_test_stage(); 1571 break; 1572 case 4: 1573 if (!invvpid_test(INVVPID_ALL, 1)) 1574 vmx_inc_test_stage(); 1575 break; 1576 default: 1577 report("ERROR: unexpected stage, %d", false, 1578 vmx_get_test_stage()); 1579 print_vmexit_info(); 1580 return VMX_TEST_VMEXIT; 1581 } 1582 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1583 return VMX_TEST_RESUME; 1584 default: 1585 report("Unknown exit reason, %ld", false, reason); 1586 print_vmexit_info(); 1587 } 1588 return VMX_TEST_VMEXIT; 1589 } 1590 1591 #define TIMER_VECTOR 222 1592 1593 static volatile bool timer_fired; 1594 1595 static void timer_isr(isr_regs_t *regs) 1596 { 1597 timer_fired = true; 1598 apic_write(APIC_EOI, 0); 1599 } 1600 1601 static int interrupt_init(struct vmcs *vmcs) 1602 { 1603 msr_bmp_init(); 1604 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1605 handle_irq(TIMER_VECTOR, timer_isr); 1606 return VMX_TEST_START; 1607 } 1608 1609 static void interrupt_main(void) 1610 { 1611 long long start, loops; 1612 1613 vmx_set_test_stage(0); 1614 1615 apic_write(APIC_LVTT, TIMER_VECTOR); 1616 irq_enable(); 1617 1618 apic_write(APIC_TMICT, 1); 1619 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1620 asm volatile ("nop"); 1621 report("direct interrupt while running guest", timer_fired); 1622 1623 apic_write(APIC_TMICT, 0); 1624 irq_disable(); 1625 vmcall(); 1626 timer_fired = false; 1627 apic_write(APIC_TMICT, 1); 1628 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1629 asm volatile ("nop"); 1630 report("intercepted interrupt while running guest", timer_fired); 1631 1632 irq_enable(); 1633 apic_write(APIC_TMICT, 0); 1634 irq_disable(); 1635 vmcall(); 1636 timer_fired = false; 1637 start = rdtsc(); 1638 apic_write(APIC_TMICT, 1000000); 1639 1640 asm volatile ("sti; hlt"); 1641 1642 report("direct interrupt + hlt", 1643 rdtsc() - start > 1000000 && timer_fired); 1644 1645 apic_write(APIC_TMICT, 0); 1646 irq_disable(); 1647 vmcall(); 1648 timer_fired = false; 1649 start = rdtsc(); 1650 apic_write(APIC_TMICT, 1000000); 1651 1652 asm volatile ("sti; hlt"); 1653 1654 report("intercepted interrupt + hlt", 1655 rdtsc() - start > 10000 && timer_fired); 1656 1657 apic_write(APIC_TMICT, 0); 1658 irq_disable(); 1659 vmcall(); 1660 timer_fired = false; 1661 start = rdtsc(); 1662 apic_write(APIC_TMICT, 1000000); 1663 1664 irq_enable(); 1665 asm volatile ("nop"); 1666 vmcall(); 1667 1668 report("direct interrupt + activity state hlt", 1669 rdtsc() - start > 10000 && timer_fired); 1670 1671 apic_write(APIC_TMICT, 0); 1672 irq_disable(); 1673 vmcall(); 1674 timer_fired = false; 1675 start = rdtsc(); 1676 apic_write(APIC_TMICT, 1000000); 1677 1678 irq_enable(); 1679 asm volatile ("nop"); 1680 vmcall(); 1681 1682 report("intercepted interrupt + activity state hlt", 1683 rdtsc() - start > 10000 && timer_fired); 1684 1685 apic_write(APIC_TMICT, 0); 1686 irq_disable(); 1687 vmx_set_test_stage(7); 1688 vmcall(); 1689 timer_fired = false; 1690 apic_write(APIC_TMICT, 1); 1691 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1692 asm volatile ("nop"); 1693 report("running a guest with interrupt acknowledgement set", timer_fired); 1694 1695 apic_write(APIC_TMICT, 0); 1696 irq_enable(); 1697 timer_fired = false; 1698 vmcall(); 1699 report("Inject an event to a halted guest", timer_fired); 1700 } 1701 1702 static int interrupt_exit_handler(void) 1703 { 1704 u64 guest_rip = vmcs_read(GUEST_RIP); 1705 ulong reason = vmcs_read(EXI_REASON) & 0xff; 1706 u32 insn_len = vmcs_read(EXI_INST_LEN); 1707 1708 switch (reason) { 1709 case VMX_VMCALL: 1710 switch (vmx_get_test_stage()) { 1711 case 0: 1712 case 2: 1713 case 5: 1714 vmcs_write(PIN_CONTROLS, 1715 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1716 break; 1717 case 7: 1718 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_INTA); 1719 vmcs_write(PIN_CONTROLS, 1720 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1721 break; 1722 case 1: 1723 case 3: 1724 vmcs_write(PIN_CONTROLS, 1725 vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1726 break; 1727 case 4: 1728 case 6: 1729 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1730 break; 1731 1732 case 8: 1733 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1734 vmcs_write(ENT_INTR_INFO, 1735 TIMER_VECTOR | 1736 (VMX_INTR_TYPE_EXT_INTR << INTR_INFO_INTR_TYPE_SHIFT) | 1737 INTR_INFO_VALID_MASK); 1738 break; 1739 } 1740 vmx_inc_test_stage(); 1741 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1742 return VMX_TEST_RESUME; 1743 case VMX_EXTINT: 1744 if (vmcs_read(EXI_CONTROLS) & EXI_INTA) { 1745 int vector = vmcs_read(EXI_INTR_INFO) & 0xff; 1746 handle_external_interrupt(vector); 1747 } else { 1748 irq_enable(); 1749 asm volatile ("nop"); 1750 irq_disable(); 1751 } 1752 if (vmx_get_test_stage() >= 2) 1753 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 1754 return VMX_TEST_RESUME; 1755 default: 1756 report("Unknown exit reason, %ld", false, reason); 1757 print_vmexit_info(); 1758 } 1759 1760 return VMX_TEST_VMEXIT; 1761 } 1762 1763 static int dbgctls_init(struct vmcs *vmcs) 1764 { 1765 u64 dr7 = 0x402; 1766 u64 zero = 0; 1767 1768 msr_bmp_init(); 1769 asm volatile( 1770 "mov %0,%%dr0\n\t" 1771 "mov %0,%%dr1\n\t" 1772 "mov %0,%%dr2\n\t" 1773 "mov %1,%%dr7\n\t" 1774 : : "r" (zero), "r" (dr7)); 1775 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1776 vmcs_write(GUEST_DR7, 0x404); 1777 vmcs_write(GUEST_DEBUGCTL, 0x2); 1778 1779 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 1780 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_SAVE_DBGCTLS); 1781 1782 return VMX_TEST_START; 1783 } 1784 1785 static void dbgctls_main(void) 1786 { 1787 u64 dr7, debugctl; 1788 1789 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1790 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1791 /* Commented out: KVM does not support DEBUGCTL so far */ 1792 (void)debugctl; 1793 report("Load debug controls", dr7 == 0x404 /* && debugctl == 0x2 */); 1794 1795 dr7 = 0x408; 1796 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1797 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1798 1799 vmx_set_test_stage(0); 1800 vmcall(); 1801 report("Save debug controls", vmx_get_test_stage() == 1); 1802 1803 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS || 1804 ctrl_exit_rev.set & EXI_SAVE_DBGCTLS) { 1805 printf("\tDebug controls are always loaded/saved\n"); 1806 return; 1807 } 1808 vmx_set_test_stage(2); 1809 vmcall(); 1810 1811 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1812 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1813 /* Commented out: KVM does not support DEBUGCTL so far */ 1814 (void)debugctl; 1815 report("Guest=host debug controls", dr7 == 0x402 /* && debugctl == 0x1 */); 1816 1817 dr7 = 0x408; 1818 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1819 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1820 1821 vmx_set_test_stage(3); 1822 vmcall(); 1823 report("Don't save debug controls", vmx_get_test_stage() == 4); 1824 } 1825 1826 static int dbgctls_exit_handler(void) 1827 { 1828 unsigned int reason = vmcs_read(EXI_REASON) & 0xff; 1829 u32 insn_len = vmcs_read(EXI_INST_LEN); 1830 u64 guest_rip = vmcs_read(GUEST_RIP); 1831 u64 dr7, debugctl; 1832 1833 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1834 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1835 1836 switch (reason) { 1837 case VMX_VMCALL: 1838 switch (vmx_get_test_stage()) { 1839 case 0: 1840 if (dr7 == 0x400 && debugctl == 0 && 1841 vmcs_read(GUEST_DR7) == 0x408 /* && 1842 Commented out: KVM does not support DEBUGCTL so far 1843 vmcs_read(GUEST_DEBUGCTL) == 0x3 */) 1844 vmx_inc_test_stage(); 1845 break; 1846 case 2: 1847 dr7 = 0x402; 1848 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1849 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1850 vmcs_write(GUEST_DR7, 0x404); 1851 vmcs_write(GUEST_DEBUGCTL, 0x2); 1852 1853 vmcs_write(ENT_CONTROLS, 1854 vmcs_read(ENT_CONTROLS) & ~ENT_LOAD_DBGCTLS); 1855 vmcs_write(EXI_CONTROLS, 1856 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_DBGCTLS); 1857 break; 1858 case 3: 1859 if (dr7 == 0x400 && debugctl == 0 && 1860 vmcs_read(GUEST_DR7) == 0x404 /* && 1861 Commented out: KVM does not support DEBUGCTL so far 1862 vmcs_read(GUEST_DEBUGCTL) == 0x2 */) 1863 vmx_inc_test_stage(); 1864 break; 1865 } 1866 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1867 return VMX_TEST_RESUME; 1868 default: 1869 report("Unknown exit reason, %d", false, reason); 1870 print_vmexit_info(); 1871 } 1872 return VMX_TEST_VMEXIT; 1873 } 1874 1875 struct vmx_msr_entry { 1876 u32 index; 1877 u32 reserved; 1878 u64 value; 1879 } __attribute__((packed)); 1880 1881 #define MSR_MAGIC 0x31415926 1882 struct vmx_msr_entry *exit_msr_store, *entry_msr_load, *exit_msr_load; 1883 1884 static int msr_switch_init(struct vmcs *vmcs) 1885 { 1886 msr_bmp_init(); 1887 exit_msr_store = alloc_page(); 1888 exit_msr_load = alloc_page(); 1889 entry_msr_load = alloc_page(); 1890 memset(exit_msr_store, 0, PAGE_SIZE); 1891 memset(exit_msr_load, 0, PAGE_SIZE); 1892 memset(entry_msr_load, 0, PAGE_SIZE); 1893 entry_msr_load[0].index = MSR_KERNEL_GS_BASE; 1894 entry_msr_load[0].value = MSR_MAGIC; 1895 1896 vmx_set_test_stage(1); 1897 vmcs_write(ENT_MSR_LD_CNT, 1); 1898 vmcs_write(ENTER_MSR_LD_ADDR, (u64)entry_msr_load); 1899 vmcs_write(EXI_MSR_ST_CNT, 1); 1900 vmcs_write(EXIT_MSR_ST_ADDR, (u64)exit_msr_store); 1901 vmcs_write(EXI_MSR_LD_CNT, 1); 1902 vmcs_write(EXIT_MSR_LD_ADDR, (u64)exit_msr_load); 1903 return VMX_TEST_START; 1904 } 1905 1906 static void msr_switch_main(void) 1907 { 1908 if (vmx_get_test_stage() == 1) { 1909 report("VM entry MSR load", 1910 rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC); 1911 vmx_set_test_stage(2); 1912 wrmsr(MSR_KERNEL_GS_BASE, MSR_MAGIC + 1); 1913 exit_msr_store[0].index = MSR_KERNEL_GS_BASE; 1914 exit_msr_load[0].index = MSR_KERNEL_GS_BASE; 1915 exit_msr_load[0].value = MSR_MAGIC + 2; 1916 } 1917 vmcall(); 1918 } 1919 1920 static int msr_switch_exit_handler(void) 1921 { 1922 ulong reason; 1923 1924 reason = vmcs_read(EXI_REASON); 1925 if (reason == VMX_VMCALL && vmx_get_test_stage() == 2) { 1926 report("VM exit MSR store", 1927 exit_msr_store[0].value == MSR_MAGIC + 1); 1928 report("VM exit MSR load", 1929 rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC + 2); 1930 vmx_set_test_stage(3); 1931 entry_msr_load[0].index = MSR_FS_BASE; 1932 return VMX_TEST_RESUME; 1933 } 1934 printf("ERROR %s: unexpected stage=%u or reason=%lu\n", 1935 __func__, vmx_get_test_stage(), reason); 1936 return VMX_TEST_EXIT; 1937 } 1938 1939 static int msr_switch_entry_failure(struct vmentry_failure *failure) 1940 { 1941 ulong reason; 1942 1943 if (failure->early) { 1944 printf("ERROR %s: early exit\n", __func__); 1945 return VMX_TEST_EXIT; 1946 } 1947 1948 reason = vmcs_read(EXI_REASON); 1949 if (reason == (VMX_ENTRY_FAILURE | VMX_FAIL_MSR) && 1950 vmx_get_test_stage() == 3) { 1951 report("VM entry MSR load: try to load FS_BASE", 1952 vmcs_read(EXI_QUALIFICATION) == 1); 1953 return VMX_TEST_VMEXIT; 1954 } 1955 printf("ERROR %s: unexpected stage=%u or reason=%lu\n", 1956 __func__, vmx_get_test_stage(), reason); 1957 return VMX_TEST_EXIT; 1958 } 1959 1960 static int vmmcall_init(struct vmcs *vmcs) 1961 { 1962 vmcs_write(EXC_BITMAP, 1 << UD_VECTOR); 1963 return VMX_TEST_START; 1964 } 1965 1966 static void vmmcall_main(void) 1967 { 1968 asm volatile( 1969 "mov $0xABCD, %%rax\n\t" 1970 "vmmcall\n\t" 1971 ::: "rax"); 1972 1973 report("VMMCALL", 0); 1974 } 1975 1976 static int vmmcall_exit_handler(void) 1977 { 1978 ulong reason; 1979 1980 reason = vmcs_read(EXI_REASON); 1981 switch (reason) { 1982 case VMX_VMCALL: 1983 printf("here\n"); 1984 report("VMMCALL triggers #UD", 0); 1985 break; 1986 case VMX_EXC_NMI: 1987 report("VMMCALL triggers #UD", 1988 (vmcs_read(EXI_INTR_INFO) & 0xff) == UD_VECTOR); 1989 break; 1990 default: 1991 report("Unknown exit reason, %ld", false, reason); 1992 print_vmexit_info(); 1993 } 1994 1995 return VMX_TEST_VMEXIT; 1996 } 1997 1998 static int disable_rdtscp_init(struct vmcs *vmcs) 1999 { 2000 u32 ctrl_cpu1; 2001 2002 if (ctrl_cpu_rev[0].clr & CPU_SECONDARY) { 2003 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 2004 ctrl_cpu1 &= ~CPU_RDTSCP; 2005 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 2006 } 2007 2008 return VMX_TEST_START; 2009 } 2010 2011 static void disable_rdtscp_ud_handler(struct ex_regs *regs) 2012 { 2013 switch (vmx_get_test_stage()) { 2014 case 0: 2015 report("RDTSCP triggers #UD", true); 2016 vmx_inc_test_stage(); 2017 regs->rip += 3; 2018 break; 2019 case 2: 2020 report("RDPID triggers #UD", true); 2021 vmx_inc_test_stage(); 2022 regs->rip += 4; 2023 break; 2024 } 2025 return; 2026 2027 } 2028 2029 static void disable_rdtscp_main(void) 2030 { 2031 /* Test that #UD is properly injected in L2. */ 2032 handle_exception(UD_VECTOR, disable_rdtscp_ud_handler); 2033 2034 vmx_set_test_stage(0); 2035 asm volatile("rdtscp" : : : "eax", "ecx", "edx"); 2036 vmcall(); 2037 asm volatile(".byte 0xf3, 0x0f, 0xc7, 0xf8" : : : "eax"); 2038 2039 handle_exception(UD_VECTOR, 0); 2040 vmcall(); 2041 } 2042 2043 static int disable_rdtscp_exit_handler(void) 2044 { 2045 unsigned int reason = vmcs_read(EXI_REASON) & 0xff; 2046 2047 switch (reason) { 2048 case VMX_VMCALL: 2049 switch (vmx_get_test_stage()) { 2050 case 0: 2051 report("RDTSCP triggers #UD", false); 2052 vmx_inc_test_stage(); 2053 /* fallthrough */ 2054 case 1: 2055 vmx_inc_test_stage(); 2056 vmcs_write(GUEST_RIP, vmcs_read(GUEST_RIP) + 3); 2057 return VMX_TEST_RESUME; 2058 case 2: 2059 report("RDPID triggers #UD", false); 2060 break; 2061 } 2062 break; 2063 2064 default: 2065 report("Unknown exit reason, %d", false, reason); 2066 print_vmexit_info(); 2067 } 2068 return VMX_TEST_VMEXIT; 2069 } 2070 2071 static int int3_init(struct vmcs *vmcs) 2072 { 2073 vmcs_write(EXC_BITMAP, ~0u); 2074 return VMX_TEST_START; 2075 } 2076 2077 static void int3_guest_main(void) 2078 { 2079 asm volatile ("int3"); 2080 } 2081 2082 static int int3_exit_handler(void) 2083 { 2084 u32 reason = vmcs_read(EXI_REASON); 2085 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2086 2087 report("L1 intercepts #BP", reason == VMX_EXC_NMI && 2088 (intr_info & INTR_INFO_VALID_MASK) && 2089 (intr_info & INTR_INFO_VECTOR_MASK) == BP_VECTOR && 2090 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2091 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION); 2092 2093 return VMX_TEST_VMEXIT; 2094 } 2095 2096 static int into_init(struct vmcs *vmcs) 2097 { 2098 vmcs_write(EXC_BITMAP, ~0u); 2099 return VMX_TEST_START; 2100 } 2101 2102 static void into_guest_main(void) 2103 { 2104 struct far_pointer32 fp = { 2105 .offset = (uintptr_t)&&into, 2106 .selector = KERNEL_CS32, 2107 }; 2108 register uintptr_t rsp asm("rsp"); 2109 2110 if (fp.offset != (uintptr_t)&&into) { 2111 printf("Code address too high.\n"); 2112 return; 2113 } 2114 if ((u32)rsp != rsp) { 2115 printf("Stack address too high.\n"); 2116 return; 2117 } 2118 2119 asm goto ("lcall *%0" : : "m" (fp) : "rax" : into); 2120 return; 2121 into: 2122 asm volatile (".code32;" 2123 "movl $0x7fffffff, %eax;" 2124 "addl %eax, %eax;" 2125 "into;" 2126 "lret;" 2127 ".code64"); 2128 __builtin_unreachable(); 2129 } 2130 2131 static int into_exit_handler(void) 2132 { 2133 u32 reason = vmcs_read(EXI_REASON); 2134 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2135 2136 report("L1 intercepts #OF", reason == VMX_EXC_NMI && 2137 (intr_info & INTR_INFO_VALID_MASK) && 2138 (intr_info & INTR_INFO_VECTOR_MASK) == OF_VECTOR && 2139 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2140 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION); 2141 2142 return VMX_TEST_VMEXIT; 2143 } 2144 2145 static void exit_monitor_from_l2_main(void) 2146 { 2147 printf("Calling exit(0) from l2...\n"); 2148 exit(0); 2149 } 2150 2151 static int exit_monitor_from_l2_handler(void) 2152 { 2153 report("The guest should have killed the VMM", false); 2154 return VMX_TEST_EXIT; 2155 } 2156 2157 static void assert_exit_reason(u64 expected) 2158 { 2159 u64 actual = vmcs_read(EXI_REASON); 2160 2161 TEST_ASSERT_EQ_MSG(expected, actual, "Expected %s, got %s.", 2162 exit_reason_description(expected), 2163 exit_reason_description(actual)); 2164 } 2165 2166 static void skip_exit_insn(void) 2167 { 2168 u64 guest_rip = vmcs_read(GUEST_RIP); 2169 u32 insn_len = vmcs_read(EXI_INST_LEN); 2170 vmcs_write(GUEST_RIP, guest_rip + insn_len); 2171 } 2172 2173 static void skip_exit_vmcall(void) 2174 { 2175 assert_exit_reason(VMX_VMCALL); 2176 skip_exit_insn(); 2177 } 2178 2179 static void v2_null_test_guest(void) 2180 { 2181 } 2182 2183 static void v2_null_test(void) 2184 { 2185 test_set_guest(v2_null_test_guest); 2186 enter_guest(); 2187 report(__func__, 1); 2188 } 2189 2190 static void v2_multiple_entries_test_guest(void) 2191 { 2192 vmx_set_test_stage(1); 2193 vmcall(); 2194 vmx_set_test_stage(2); 2195 } 2196 2197 static void v2_multiple_entries_test(void) 2198 { 2199 test_set_guest(v2_multiple_entries_test_guest); 2200 enter_guest(); 2201 TEST_ASSERT_EQ(vmx_get_test_stage(), 1); 2202 skip_exit_vmcall(); 2203 enter_guest(); 2204 TEST_ASSERT_EQ(vmx_get_test_stage(), 2); 2205 report(__func__, 1); 2206 } 2207 2208 static int fixture_test_data = 1; 2209 2210 static void fixture_test_teardown(void *data) 2211 { 2212 *((int *) data) = 1; 2213 } 2214 2215 static void fixture_test_guest(void) 2216 { 2217 fixture_test_data++; 2218 } 2219 2220 2221 static void fixture_test_setup(void) 2222 { 2223 TEST_ASSERT_EQ_MSG(1, fixture_test_data, 2224 "fixture_test_teardown didn't run?!"); 2225 fixture_test_data = 2; 2226 test_add_teardown(fixture_test_teardown, &fixture_test_data); 2227 test_set_guest(fixture_test_guest); 2228 } 2229 2230 static void fixture_test_case1(void) 2231 { 2232 fixture_test_setup(); 2233 TEST_ASSERT_EQ(2, fixture_test_data); 2234 enter_guest(); 2235 TEST_ASSERT_EQ(3, fixture_test_data); 2236 report(__func__, 1); 2237 } 2238 2239 static void fixture_test_case2(void) 2240 { 2241 fixture_test_setup(); 2242 TEST_ASSERT_EQ(2, fixture_test_data); 2243 enter_guest(); 2244 TEST_ASSERT_EQ(3, fixture_test_data); 2245 report(__func__, 1); 2246 } 2247 2248 enum ept_access_op { 2249 OP_READ, 2250 OP_WRITE, 2251 OP_EXEC, 2252 OP_FLUSH_TLB, 2253 OP_EXIT, 2254 }; 2255 2256 static struct ept_access_test_data { 2257 unsigned long gpa; 2258 unsigned long *gva; 2259 unsigned long hpa; 2260 unsigned long *hva; 2261 enum ept_access_op op; 2262 } ept_access_test_data; 2263 2264 extern unsigned char ret42_start; 2265 extern unsigned char ret42_end; 2266 2267 /* Returns 42. */ 2268 asm( 2269 ".align 64\n" 2270 "ret42_start:\n" 2271 "mov $42, %eax\n" 2272 "ret\n" 2273 "ret42_end:\n" 2274 ); 2275 2276 static void 2277 diagnose_ept_violation_qual(u64 expected, u64 actual) 2278 { 2279 2280 #define DIAGNOSE(flag) \ 2281 do { \ 2282 if ((expected & flag) != (actual & flag)) \ 2283 printf(#flag " %sexpected\n", \ 2284 (expected & flag) ? "" : "un"); \ 2285 } while (0) 2286 2287 DIAGNOSE(EPT_VLT_RD); 2288 DIAGNOSE(EPT_VLT_WR); 2289 DIAGNOSE(EPT_VLT_FETCH); 2290 DIAGNOSE(EPT_VLT_PERM_RD); 2291 DIAGNOSE(EPT_VLT_PERM_WR); 2292 DIAGNOSE(EPT_VLT_PERM_EX); 2293 DIAGNOSE(EPT_VLT_LADDR_VLD); 2294 DIAGNOSE(EPT_VLT_PADDR); 2295 2296 #undef DIAGNOSE 2297 } 2298 2299 static void do_ept_access_op(enum ept_access_op op) 2300 { 2301 ept_access_test_data.op = op; 2302 enter_guest(); 2303 } 2304 2305 /* 2306 * Force the guest to flush its TLB (i.e., flush gva -> gpa mappings). Only 2307 * needed by tests that modify guest PTEs. 2308 */ 2309 static void ept_access_test_guest_flush_tlb(void) 2310 { 2311 do_ept_access_op(OP_FLUSH_TLB); 2312 skip_exit_vmcall(); 2313 } 2314 2315 /* 2316 * Modifies the EPT entry at @level in the mapping of @gpa. First clears the 2317 * bits in @clear then sets the bits in @set. @mkhuge transforms the entry into 2318 * a huge page. 2319 */ 2320 static unsigned long ept_twiddle(unsigned long gpa, bool mkhuge, int level, 2321 unsigned long clear, unsigned long set) 2322 { 2323 struct ept_access_test_data *data = &ept_access_test_data; 2324 unsigned long orig_pte; 2325 unsigned long pte; 2326 2327 /* Screw with the mapping at the requested level. */ 2328 TEST_ASSERT(get_ept_pte(pml4, gpa, level, &orig_pte)); 2329 pte = orig_pte; 2330 if (mkhuge) 2331 pte = (orig_pte & ~EPT_ADDR_MASK) | data->hpa | EPT_LARGE_PAGE; 2332 else 2333 pte = orig_pte; 2334 pte = (pte & ~clear) | set; 2335 set_ept_pte(pml4, gpa, level, pte); 2336 ept_sync(INVEPT_SINGLE, eptp); 2337 2338 return orig_pte; 2339 } 2340 2341 static void ept_untwiddle(unsigned long gpa, int level, unsigned long orig_pte) 2342 { 2343 set_ept_pte(pml4, gpa, level, orig_pte); 2344 } 2345 2346 static void do_ept_violation(bool leaf, enum ept_access_op op, 2347 u64 expected_qual, u64 expected_paddr) 2348 { 2349 u64 qual; 2350 2351 /* Try the access and observe the violation. */ 2352 do_ept_access_op(op); 2353 2354 assert_exit_reason(VMX_EPT_VIOLATION); 2355 2356 qual = vmcs_read(EXI_QUALIFICATION); 2357 2358 diagnose_ept_violation_qual(expected_qual, qual); 2359 TEST_EXPECT_EQ(expected_qual, qual); 2360 2361 #if 0 2362 /* Disable for now otherwise every test will fail */ 2363 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2364 (unsigned long) ( 2365 op == OP_EXEC ? data->gva + 1 : data->gva)); 2366 #endif 2367 /* 2368 * TODO: tests that probe expected_paddr in pages other than the one at 2369 * the beginning of the 1g region. 2370 */ 2371 TEST_EXPECT_EQ(vmcs_read(INFO_PHYS_ADDR), expected_paddr); 2372 } 2373 2374 static void 2375 ept_violation_at_level_mkhuge(bool mkhuge, int level, unsigned long clear, 2376 unsigned long set, enum ept_access_op op, 2377 u64 expected_qual) 2378 { 2379 struct ept_access_test_data *data = &ept_access_test_data; 2380 unsigned long orig_pte; 2381 2382 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2383 2384 do_ept_violation(level == 1 || mkhuge, op, expected_qual, 2385 op == OP_EXEC ? data->gpa + sizeof(unsigned long) : 2386 data->gpa); 2387 2388 /* Fix the violation and resume the op loop. */ 2389 ept_untwiddle(data->gpa, level, orig_pte); 2390 enter_guest(); 2391 skip_exit_vmcall(); 2392 } 2393 2394 static void 2395 ept_violation_at_level(int level, unsigned long clear, unsigned long set, 2396 enum ept_access_op op, u64 expected_qual) 2397 { 2398 ept_violation_at_level_mkhuge(false, level, clear, set, op, 2399 expected_qual); 2400 if (ept_huge_pages_supported(level)) 2401 ept_violation_at_level_mkhuge(true, level, clear, set, op, 2402 expected_qual); 2403 } 2404 2405 static void ept_violation(unsigned long clear, unsigned long set, 2406 enum ept_access_op op, u64 expected_qual) 2407 { 2408 ept_violation_at_level(1, clear, set, op, expected_qual); 2409 ept_violation_at_level(2, clear, set, op, expected_qual); 2410 ept_violation_at_level(3, clear, set, op, expected_qual); 2411 ept_violation_at_level(4, clear, set, op, expected_qual); 2412 } 2413 2414 static void ept_access_violation(unsigned long access, enum ept_access_op op, 2415 u64 expected_qual) 2416 { 2417 ept_violation(EPT_PRESENT, access, op, 2418 expected_qual | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2419 } 2420 2421 /* 2422 * For translations that don't involve a GVA, that is physical address (paddr) 2423 * accesses, EPT violations don't set the flag EPT_VLT_PADDR. For a typical 2424 * guest memory access, the hardware does GVA -> GPA -> HPA. However, certain 2425 * translations don't involve GVAs, such as when the hardware does the guest 2426 * page table walk. For example, in translating GVA_1 -> GPA_1, the guest MMU 2427 * might try to set an A bit on a guest PTE. If the GPA_2 that the PTE resides 2428 * on isn't present in the EPT, then the EPT violation will be for GPA_2 and 2429 * the EPT_VLT_PADDR bit will be clear in the exit qualification. 2430 * 2431 * Note that paddr violations can also be triggered by loading PAE page tables 2432 * with wonky addresses. We don't test that yet. 2433 * 2434 * This function modifies the EPT entry that maps the GPA that the guest page 2435 * table entry mapping ept_access_data.gva resides on. 2436 * 2437 * @ept_access EPT permissions to set. Other permissions are cleared. 2438 * 2439 * @pte_ad Set the A/D bits on the guest PTE accordingly. 2440 * 2441 * @op Guest operation to perform with ept_access_data.gva. 2442 * 2443 * @expect_violation 2444 * Is a violation expected during the paddr access? 2445 * 2446 * @expected_qual Expected qualification for the EPT violation. 2447 * EPT_VLT_PADDR should be clear. 2448 */ 2449 static void ept_access_paddr(unsigned long ept_access, unsigned long pte_ad, 2450 enum ept_access_op op, bool expect_violation, 2451 u64 expected_qual) 2452 { 2453 struct ept_access_test_data *data = &ept_access_test_data; 2454 unsigned long *ptep; 2455 unsigned long gpa; 2456 unsigned long orig_epte; 2457 2458 /* Modify the guest PTE mapping data->gva according to @pte_ad. */ 2459 ptep = get_pte_level(current_page_table(), data->gva, /*level=*/1); 2460 TEST_ASSERT(ptep); 2461 TEST_ASSERT_EQ(*ptep & PT_ADDR_MASK, data->gpa); 2462 *ptep = (*ptep & ~PT_AD_MASK) | pte_ad; 2463 ept_access_test_guest_flush_tlb(); 2464 2465 /* 2466 * Now modify the access bits on the EPT entry for the GPA that the 2467 * guest PTE resides on. Note that by modifying a single EPT entry, 2468 * we're potentially affecting 512 guest PTEs. However, we've carefully 2469 * constructed our test such that those other 511 PTEs aren't used by 2470 * the guest: data->gva is at the beginning of a 1G huge page, thus the 2471 * PTE we're modifying is at the beginning of a 4K page and the 2472 * following 511 entires are also under our control (and not touched by 2473 * the guest). 2474 */ 2475 gpa = virt_to_phys(ptep); 2476 TEST_ASSERT_EQ(gpa & ~PAGE_MASK, 0); 2477 /* 2478 * Make sure the guest page table page is mapped with a 4K EPT entry, 2479 * otherwise our level=1 twiddling below will fail. We use the 2480 * identity map (gpa = gpa) since page tables are shared with the host. 2481 */ 2482 install_ept(pml4, gpa, gpa, EPT_PRESENT); 2483 orig_epte = ept_twiddle(gpa, /*mkhuge=*/0, /*level=*/1, 2484 /*clear=*/EPT_PRESENT, /*set=*/ept_access); 2485 2486 if (expect_violation) { 2487 do_ept_violation(/*leaf=*/true, op, 2488 expected_qual | EPT_VLT_LADDR_VLD, gpa); 2489 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2490 do_ept_access_op(op); 2491 } else { 2492 do_ept_access_op(op); 2493 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2494 } 2495 2496 TEST_ASSERT(*ptep & PT_ACCESSED_MASK); 2497 if ((pte_ad & PT_DIRTY_MASK) || op == OP_WRITE) 2498 TEST_ASSERT(*ptep & PT_DIRTY_MASK); 2499 2500 skip_exit_vmcall(); 2501 } 2502 2503 static void ept_access_allowed_paddr(unsigned long ept_access, 2504 unsigned long pte_ad, 2505 enum ept_access_op op) 2506 { 2507 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/false, 2508 /*expected_qual=*/-1); 2509 } 2510 2511 static void ept_access_violation_paddr(unsigned long ept_access, 2512 unsigned long pte_ad, 2513 enum ept_access_op op, 2514 u64 expected_qual) 2515 { 2516 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/true, 2517 expected_qual); 2518 } 2519 2520 2521 static void ept_allowed_at_level_mkhuge(bool mkhuge, int level, 2522 unsigned long clear, 2523 unsigned long set, 2524 enum ept_access_op op) 2525 { 2526 struct ept_access_test_data *data = &ept_access_test_data; 2527 unsigned long orig_pte; 2528 2529 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2530 2531 /* No violation. Should proceed to vmcall. */ 2532 do_ept_access_op(op); 2533 skip_exit_vmcall(); 2534 2535 ept_untwiddle(data->gpa, level, orig_pte); 2536 } 2537 2538 static void ept_allowed_at_level(int level, unsigned long clear, 2539 unsigned long set, enum ept_access_op op) 2540 { 2541 ept_allowed_at_level_mkhuge(false, level, clear, set, op); 2542 if (ept_huge_pages_supported(level)) 2543 ept_allowed_at_level_mkhuge(true, level, clear, set, op); 2544 } 2545 2546 static void ept_allowed(unsigned long clear, unsigned long set, 2547 enum ept_access_op op) 2548 { 2549 ept_allowed_at_level(1, clear, set, op); 2550 ept_allowed_at_level(2, clear, set, op); 2551 ept_allowed_at_level(3, clear, set, op); 2552 ept_allowed_at_level(4, clear, set, op); 2553 } 2554 2555 static void ept_ignored_bit(int bit) 2556 { 2557 /* Set the bit. */ 2558 ept_allowed(0, 1ul << bit, OP_READ); 2559 ept_allowed(0, 1ul << bit, OP_WRITE); 2560 ept_allowed(0, 1ul << bit, OP_EXEC); 2561 2562 /* Clear the bit. */ 2563 ept_allowed(1ul << bit, 0, OP_READ); 2564 ept_allowed(1ul << bit, 0, OP_WRITE); 2565 ept_allowed(1ul << bit, 0, OP_EXEC); 2566 } 2567 2568 static void ept_access_allowed(unsigned long access, enum ept_access_op op) 2569 { 2570 ept_allowed(EPT_PRESENT, access, op); 2571 } 2572 2573 2574 static void ept_misconfig_at_level_mkhuge_op(bool mkhuge, int level, 2575 unsigned long clear, 2576 unsigned long set, 2577 enum ept_access_op op) 2578 { 2579 struct ept_access_test_data *data = &ept_access_test_data; 2580 unsigned long orig_pte; 2581 2582 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2583 2584 do_ept_access_op(op); 2585 assert_exit_reason(VMX_EPT_MISCONFIG); 2586 2587 /* Intel 27.2.1, "For all other VM exits, this field is cleared." */ 2588 #if 0 2589 /* broken: */ 2590 TEST_EXPECT_EQ_MSG(vmcs_read(EXI_QUALIFICATION), 0); 2591 #endif 2592 #if 0 2593 /* 2594 * broken: 2595 * According to description of exit qual for EPT violation, 2596 * EPT_VLT_LADDR_VLD indicates if GUEST_LINEAR_ADDRESS is valid. 2597 * However, I can't find anything that says GUEST_LINEAR_ADDRESS ought 2598 * to be set for msiconfig. 2599 */ 2600 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2601 (unsigned long) ( 2602 op == OP_EXEC ? data->gva + 1 : data->gva)); 2603 #endif 2604 2605 /* Fix the violation and resume the op loop. */ 2606 ept_untwiddle(data->gpa, level, orig_pte); 2607 enter_guest(); 2608 skip_exit_vmcall(); 2609 } 2610 2611 static void ept_misconfig_at_level_mkhuge(bool mkhuge, int level, 2612 unsigned long clear, 2613 unsigned long set) 2614 { 2615 /* The op shouldn't matter (read, write, exec), so try them all! */ 2616 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_READ); 2617 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_WRITE); 2618 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_EXEC); 2619 } 2620 2621 static void ept_misconfig_at_level(int level, unsigned long clear, 2622 unsigned long set) 2623 { 2624 ept_misconfig_at_level_mkhuge(false, level, clear, set); 2625 if (ept_huge_pages_supported(level)) 2626 ept_misconfig_at_level_mkhuge(true, level, clear, set); 2627 } 2628 2629 static void ept_misconfig(unsigned long clear, unsigned long set) 2630 { 2631 ept_misconfig_at_level(1, clear, set); 2632 ept_misconfig_at_level(2, clear, set); 2633 ept_misconfig_at_level(3, clear, set); 2634 ept_misconfig_at_level(4, clear, set); 2635 } 2636 2637 static void ept_access_misconfig(unsigned long access) 2638 { 2639 ept_misconfig(EPT_PRESENT, access); 2640 } 2641 2642 static void ept_reserved_bit_at_level_nohuge(int level, int bit) 2643 { 2644 /* Setting the bit causes a misconfig. */ 2645 ept_misconfig_at_level_mkhuge(false, level, 0, 1ul << bit); 2646 2647 /* Making the entry non-present turns reserved bits into ignored. */ 2648 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2649 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2650 } 2651 2652 static void ept_reserved_bit_at_level_huge(int level, int bit) 2653 { 2654 /* Setting the bit causes a misconfig. */ 2655 ept_misconfig_at_level_mkhuge(true, level, 0, 1ul << bit); 2656 2657 /* Making the entry non-present turns reserved bits into ignored. */ 2658 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2659 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2660 } 2661 2662 static void ept_reserved_bit_at_level(int level, int bit) 2663 { 2664 /* Setting the bit causes a misconfig. */ 2665 ept_misconfig_at_level(level, 0, 1ul << bit); 2666 2667 /* Making the entry non-present turns reserved bits into ignored. */ 2668 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2669 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2670 } 2671 2672 static void ept_reserved_bit(int bit) 2673 { 2674 ept_reserved_bit_at_level(1, bit); 2675 ept_reserved_bit_at_level(2, bit); 2676 ept_reserved_bit_at_level(3, bit); 2677 ept_reserved_bit_at_level(4, bit); 2678 } 2679 2680 #define PAGE_2M_ORDER 9 2681 #define PAGE_1G_ORDER 18 2682 2683 static void *get_1g_page(void) 2684 { 2685 static void *alloc; 2686 2687 if (!alloc) 2688 alloc = alloc_pages(PAGE_1G_ORDER); 2689 return alloc; 2690 } 2691 2692 static void ept_access_test_teardown(void *unused) 2693 { 2694 /* Exit the guest cleanly. */ 2695 do_ept_access_op(OP_EXIT); 2696 } 2697 2698 static void ept_access_test_guest(void) 2699 { 2700 struct ept_access_test_data *data = &ept_access_test_data; 2701 int (*code)(void) = (int (*)(void)) &data->gva[1]; 2702 2703 while (true) { 2704 switch (data->op) { 2705 case OP_READ: 2706 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_1); 2707 break; 2708 case OP_WRITE: 2709 *data->gva = MAGIC_VAL_2; 2710 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_2); 2711 *data->gva = MAGIC_VAL_1; 2712 break; 2713 case OP_EXEC: 2714 TEST_ASSERT_EQ(42, code()); 2715 break; 2716 case OP_FLUSH_TLB: 2717 write_cr3(read_cr3()); 2718 break; 2719 case OP_EXIT: 2720 return; 2721 default: 2722 TEST_ASSERT_MSG(false, "Unknown op %d", data->op); 2723 } 2724 vmcall(); 2725 } 2726 } 2727 2728 static void ept_access_test_setup(void) 2729 { 2730 struct ept_access_test_data *data = &ept_access_test_data; 2731 unsigned long npages = 1ul << PAGE_1G_ORDER; 2732 unsigned long size = npages * PAGE_SIZE; 2733 unsigned long *page_table = current_page_table(); 2734 unsigned long pte; 2735 2736 if (setup_ept(false)) 2737 test_skip("EPT not supported"); 2738 2739 /* We use data->gpa = 1 << 39 so that test data has a separate pml4 entry */ 2740 if (cpuid_maxphyaddr() < 40) 2741 test_skip("Test needs MAXPHYADDR >= 40"); 2742 2743 test_set_guest(ept_access_test_guest); 2744 test_add_teardown(ept_access_test_teardown, NULL); 2745 2746 data->hva = get_1g_page(); 2747 TEST_ASSERT(data->hva); 2748 data->hpa = virt_to_phys(data->hva); 2749 2750 data->gpa = 1ul << 39; 2751 data->gva = (void *) ALIGN((unsigned long) alloc_vpages(npages * 2), 2752 size); 2753 TEST_ASSERT(!any_present_pages(page_table, data->gva, size)); 2754 install_pages(page_table, data->gpa, size, data->gva); 2755 2756 /* 2757 * Make sure nothing's mapped here so the tests that screw with the 2758 * pml4 entry don't inadvertently break something. 2759 */ 2760 TEST_ASSERT(get_ept_pte(pml4, data->gpa, 4, &pte) && pte == 0); 2761 TEST_ASSERT(get_ept_pte(pml4, data->gpa + size - 1, 4, &pte) && pte == 0); 2762 install_ept(pml4, data->hpa, data->gpa, EPT_PRESENT); 2763 2764 data->hva[0] = MAGIC_VAL_1; 2765 memcpy(&data->hva[1], &ret42_start, &ret42_end - &ret42_start); 2766 } 2767 2768 static void ept_access_test_not_present(void) 2769 { 2770 ept_access_test_setup(); 2771 /* --- */ 2772 ept_access_violation(0, OP_READ, EPT_VLT_RD); 2773 ept_access_violation(0, OP_WRITE, EPT_VLT_WR); 2774 ept_access_violation(0, OP_EXEC, EPT_VLT_FETCH); 2775 } 2776 2777 static void ept_access_test_read_only(void) 2778 { 2779 ept_access_test_setup(); 2780 2781 /* r-- */ 2782 ept_access_allowed(EPT_RA, OP_READ); 2783 ept_access_violation(EPT_RA, OP_WRITE, EPT_VLT_WR | EPT_VLT_PERM_RD); 2784 ept_access_violation(EPT_RA, OP_EXEC, EPT_VLT_FETCH | EPT_VLT_PERM_RD); 2785 } 2786 2787 static void ept_access_test_write_only(void) 2788 { 2789 ept_access_test_setup(); 2790 /* -w- */ 2791 ept_access_misconfig(EPT_WA); 2792 } 2793 2794 static void ept_access_test_read_write(void) 2795 { 2796 ept_access_test_setup(); 2797 /* rw- */ 2798 ept_access_allowed(EPT_RA | EPT_WA, OP_READ); 2799 ept_access_allowed(EPT_RA | EPT_WA, OP_WRITE); 2800 ept_access_violation(EPT_RA | EPT_WA, OP_EXEC, 2801 EPT_VLT_FETCH | EPT_VLT_PERM_RD | EPT_VLT_PERM_WR); 2802 } 2803 2804 2805 static void ept_access_test_execute_only(void) 2806 { 2807 ept_access_test_setup(); 2808 /* --x */ 2809 if (ept_execute_only_supported()) { 2810 ept_access_violation(EPT_EA, OP_READ, 2811 EPT_VLT_RD | EPT_VLT_PERM_EX); 2812 ept_access_violation(EPT_EA, OP_WRITE, 2813 EPT_VLT_WR | EPT_VLT_PERM_EX); 2814 ept_access_allowed(EPT_EA, OP_EXEC); 2815 } else { 2816 ept_access_misconfig(EPT_EA); 2817 } 2818 } 2819 2820 static void ept_access_test_read_execute(void) 2821 { 2822 ept_access_test_setup(); 2823 /* r-x */ 2824 ept_access_allowed(EPT_RA | EPT_EA, OP_READ); 2825 ept_access_violation(EPT_RA | EPT_EA, OP_WRITE, 2826 EPT_VLT_WR | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX); 2827 ept_access_allowed(EPT_RA | EPT_EA, OP_EXEC); 2828 } 2829 2830 static void ept_access_test_write_execute(void) 2831 { 2832 ept_access_test_setup(); 2833 /* -wx */ 2834 ept_access_misconfig(EPT_WA | EPT_EA); 2835 } 2836 2837 static void ept_access_test_read_write_execute(void) 2838 { 2839 ept_access_test_setup(); 2840 /* rwx */ 2841 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_READ); 2842 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_WRITE); 2843 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_EXEC); 2844 } 2845 2846 static void ept_access_test_reserved_bits(void) 2847 { 2848 int i; 2849 int maxphyaddr; 2850 2851 ept_access_test_setup(); 2852 2853 /* Reserved bits above maxphyaddr. */ 2854 maxphyaddr = cpuid_maxphyaddr(); 2855 for (i = maxphyaddr; i <= 51; i++) { 2856 report_prefix_pushf("reserved_bit=%d", i); 2857 ept_reserved_bit(i); 2858 report_prefix_pop(); 2859 } 2860 2861 /* Level-specific reserved bits. */ 2862 ept_reserved_bit_at_level_nohuge(2, 3); 2863 ept_reserved_bit_at_level_nohuge(2, 4); 2864 ept_reserved_bit_at_level_nohuge(2, 5); 2865 ept_reserved_bit_at_level_nohuge(2, 6); 2866 /* 2M alignment. */ 2867 for (i = 12; i < 20; i++) { 2868 report_prefix_pushf("reserved_bit=%d", i); 2869 ept_reserved_bit_at_level_huge(2, i); 2870 report_prefix_pop(); 2871 } 2872 ept_reserved_bit_at_level_nohuge(3, 3); 2873 ept_reserved_bit_at_level_nohuge(3, 4); 2874 ept_reserved_bit_at_level_nohuge(3, 5); 2875 ept_reserved_bit_at_level_nohuge(3, 6); 2876 /* 1G alignment. */ 2877 for (i = 12; i < 29; i++) { 2878 report_prefix_pushf("reserved_bit=%d", i); 2879 ept_reserved_bit_at_level_huge(3, i); 2880 report_prefix_pop(); 2881 } 2882 ept_reserved_bit_at_level(4, 3); 2883 ept_reserved_bit_at_level(4, 4); 2884 ept_reserved_bit_at_level(4, 5); 2885 ept_reserved_bit_at_level(4, 6); 2886 ept_reserved_bit_at_level(4, 7); 2887 } 2888 2889 static void ept_access_test_ignored_bits(void) 2890 { 2891 ept_access_test_setup(); 2892 /* 2893 * Bits ignored at every level. Bits 8 and 9 (A and D) are ignored as 2894 * far as translation is concerned even if AD bits are enabled in the 2895 * EPTP. Bit 63 is ignored because "EPT-violation #VE" VM-execution 2896 * control is 0. 2897 */ 2898 ept_ignored_bit(8); 2899 ept_ignored_bit(9); 2900 ept_ignored_bit(10); 2901 ept_ignored_bit(11); 2902 ept_ignored_bit(52); 2903 ept_ignored_bit(53); 2904 ept_ignored_bit(54); 2905 ept_ignored_bit(55); 2906 ept_ignored_bit(56); 2907 ept_ignored_bit(57); 2908 ept_ignored_bit(58); 2909 ept_ignored_bit(59); 2910 ept_ignored_bit(60); 2911 ept_ignored_bit(61); 2912 ept_ignored_bit(62); 2913 ept_ignored_bit(63); 2914 } 2915 2916 static void ept_access_test_paddr_not_present_ad_disabled(void) 2917 { 2918 ept_access_test_setup(); 2919 ept_disable_ad_bits(); 2920 2921 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, EPT_VLT_RD); 2922 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, EPT_VLT_RD); 2923 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, EPT_VLT_RD); 2924 } 2925 2926 static void ept_access_test_paddr_not_present_ad_enabled(void) 2927 { 2928 u64 qual = EPT_VLT_RD | EPT_VLT_WR; 2929 2930 ept_access_test_setup(); 2931 ept_enable_ad_bits_or_skip_test(); 2932 2933 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, qual); 2934 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, qual); 2935 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, qual); 2936 } 2937 2938 static void ept_access_test_paddr_read_only_ad_disabled(void) 2939 { 2940 /* 2941 * When EPT AD bits are disabled, all accesses to guest paging 2942 * structures are reported separately as a read and (after 2943 * translation of the GPA to host physical address) a read+write 2944 * if the A/D bits have to be set. 2945 */ 2946 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 2947 2948 ept_access_test_setup(); 2949 ept_disable_ad_bits(); 2950 2951 /* Can't update A bit, so all accesses fail. */ 2952 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 2953 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 2954 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 2955 /* AD bits disabled, so only writes try to update the D bit. */ 2956 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ); 2957 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 2958 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC); 2959 /* Both A and D already set, so read-only is OK. */ 2960 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_READ); 2961 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_WRITE); 2962 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_EXEC); 2963 } 2964 2965 static void ept_access_test_paddr_read_only_ad_enabled(void) 2966 { 2967 /* 2968 * When EPT AD bits are enabled, all accesses to guest paging 2969 * structures are considered writes as far as EPT translation 2970 * is concerned. 2971 */ 2972 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 2973 2974 ept_access_test_setup(); 2975 ept_enable_ad_bits_or_skip_test(); 2976 2977 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 2978 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 2979 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 2980 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ, qual); 2981 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 2982 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC, qual); 2983 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_READ, qual); 2984 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_WRITE, qual); 2985 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_EXEC, qual); 2986 } 2987 2988 static void ept_access_test_paddr_read_write(void) 2989 { 2990 ept_access_test_setup(); 2991 /* Read-write access to paging structure. */ 2992 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_READ); 2993 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_WRITE); 2994 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_EXEC); 2995 } 2996 2997 static void ept_access_test_paddr_read_write_execute(void) 2998 { 2999 ept_access_test_setup(); 3000 /* RWX access to paging structure. */ 3001 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_READ); 3002 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_WRITE); 3003 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_EXEC); 3004 } 3005 3006 static void ept_access_test_paddr_read_execute_ad_disabled(void) 3007 { 3008 /* 3009 * When EPT AD bits are disabled, all accesses to guest paging 3010 * structures are reported separately as a read and (after 3011 * translation of the GPA to host physical address) a read+write 3012 * if the A/D bits have to be set. 3013 */ 3014 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3015 3016 ept_access_test_setup(); 3017 ept_disable_ad_bits(); 3018 3019 /* Can't update A bit, so all accesses fail. */ 3020 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3021 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3022 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3023 /* AD bits disabled, so only writes try to update the D bit. */ 3024 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ); 3025 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3026 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC); 3027 /* Both A and D already set, so read-only is OK. */ 3028 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ); 3029 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE); 3030 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC); 3031 } 3032 3033 static void ept_access_test_paddr_read_execute_ad_enabled(void) 3034 { 3035 /* 3036 * When EPT AD bits are enabled, all accesses to guest paging 3037 * structures are considered writes as far as EPT translation 3038 * is concerned. 3039 */ 3040 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3041 3042 ept_access_test_setup(); 3043 ept_enable_ad_bits_or_skip_test(); 3044 3045 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3046 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3047 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3048 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ, qual); 3049 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3050 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC, qual); 3051 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ, qual); 3052 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE, qual); 3053 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC, qual); 3054 } 3055 3056 static void ept_access_test_paddr_not_present_page_fault(void) 3057 { 3058 ept_access_test_setup(); 3059 /* 3060 * TODO: test no EPT violation as long as guest PF occurs. e.g., GPA is 3061 * page is read-only in EPT but GVA is also mapped read only in PT. 3062 * Thus guest page fault before host takes EPT violation for trying to 3063 * update A bit. 3064 */ 3065 } 3066 3067 static void ept_access_test_force_2m_page(void) 3068 { 3069 ept_access_test_setup(); 3070 3071 TEST_ASSERT_EQ(ept_2m_supported(), true); 3072 ept_allowed_at_level_mkhuge(true, 2, 0, 0, OP_READ); 3073 ept_violation_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_RA, OP_WRITE, 3074 EPT_VLT_WR | EPT_VLT_PERM_RD | 3075 EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 3076 ept_misconfig_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_WA); 3077 } 3078 3079 static bool invvpid_valid(u64 type, u64 vpid, u64 gla) 3080 { 3081 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3082 3083 TEST_ASSERT(msr & VPID_CAP_INVVPID); 3084 3085 if (type < INVVPID_ADDR || type > INVVPID_CONTEXT_LOCAL) 3086 return false; 3087 3088 if (!(msr & (1ull << (type + VPID_CAP_INVVPID_TYPES_SHIFT)))) 3089 return false; 3090 3091 if (vpid >> 16) 3092 return false; 3093 3094 if (type != INVVPID_ALL && !vpid) 3095 return false; 3096 3097 if (type == INVVPID_ADDR && !is_canonical(gla)) 3098 return false; 3099 3100 return true; 3101 } 3102 3103 static void try_invvpid(u64 type, u64 vpid, u64 gla) 3104 { 3105 int rc; 3106 bool valid = invvpid_valid(type, vpid, gla); 3107 u64 expected = valid ? VMXERR_UNSUPPORTED_VMCS_COMPONENT 3108 : VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID; 3109 /* 3110 * Set VMX_INST_ERROR to VMXERR_UNVALID_VMCS_COMPONENT, so 3111 * that we can tell if it is updated by INVVPID. 3112 */ 3113 vmcs_read(~0); 3114 rc = invvpid(type, vpid, gla); 3115 report("INVVPID type %ld VPID %lx GLA %lx %s", 3116 !rc == valid, type, vpid, gla, 3117 valid ? "passes" : "fails"); 3118 report("After %s INVVPID, VMX_INST_ERR is %ld (actual %ld)", 3119 vmcs_read(VMX_INST_ERROR) == expected, 3120 rc ? "failed" : "successful", 3121 expected, vmcs_read(VMX_INST_ERROR)); 3122 } 3123 3124 static void ds_invvpid(void *data) 3125 { 3126 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3127 u64 type = ffs(msr >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 3128 3129 TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 3130 asm volatile("invvpid %0, %1" 3131 : 3132 : "m"(*(struct invvpid_operand *)data), 3133 "r"(type)); 3134 } 3135 3136 /* 3137 * The SS override is ignored in 64-bit mode, so we use an addressing 3138 * mode with %rsp as the base register to generate an implicit SS 3139 * reference. 3140 */ 3141 static void ss_invvpid(void *data) 3142 { 3143 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3144 u64 type = ffs(msr >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 3145 3146 TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 3147 asm volatile("sub %%rsp,%0; invvpid (%%rsp,%0,1), %1" 3148 : "+r"(data) 3149 : "r"(type)); 3150 } 3151 3152 static void invvpid_test_gp(void) 3153 { 3154 bool fault; 3155 3156 fault = test_for_exception(GP_VECTOR, &ds_invvpid, 3157 (void *)NONCANONICAL); 3158 report("INVVPID with non-canonical DS operand raises #GP", fault); 3159 } 3160 3161 static void invvpid_test_ss(void) 3162 { 3163 bool fault; 3164 3165 fault = test_for_exception(SS_VECTOR, &ss_invvpid, 3166 (void *)NONCANONICAL); 3167 report("INVVPID with non-canonical SS operand raises #SS", fault); 3168 } 3169 3170 static void invvpid_test_pf(void) 3171 { 3172 void *vpage = alloc_vpage(); 3173 bool fault; 3174 3175 fault = test_for_exception(PF_VECTOR, &ds_invvpid, vpage); 3176 report("INVVPID with unmapped operand raises #PF", fault); 3177 } 3178 3179 static void try_compat_invvpid(void *unused) 3180 { 3181 struct far_pointer32 fp = { 3182 .offset = (uintptr_t)&&invvpid, 3183 .selector = KERNEL_CS32, 3184 }; 3185 register uintptr_t rsp asm("rsp"); 3186 3187 TEST_ASSERT_MSG(fp.offset == (uintptr_t)&&invvpid, 3188 "Code address too high."); 3189 TEST_ASSERT_MSG(rsp == (u32)rsp, "Stack address too high."); 3190 3191 asm goto ("lcall *%0" : : "m" (fp) : "rax" : invvpid); 3192 return; 3193 invvpid: 3194 asm volatile (".code32;" 3195 "invvpid (%eax), %eax;" 3196 "lret;" 3197 ".code64"); 3198 __builtin_unreachable(); 3199 } 3200 3201 static void invvpid_test_compatibility_mode(void) 3202 { 3203 bool fault; 3204 3205 fault = test_for_exception(UD_VECTOR, &try_compat_invvpid, NULL); 3206 report("Compatibility mode INVVPID raises #UD", fault); 3207 } 3208 3209 static void invvpid_test_not_in_vmx_operation(void) 3210 { 3211 bool fault; 3212 3213 TEST_ASSERT(!vmx_off()); 3214 fault = test_for_exception(UD_VECTOR, &ds_invvpid, NULL); 3215 report("INVVPID outside of VMX operation raises #UD", fault); 3216 TEST_ASSERT(!vmx_on()); 3217 } 3218 3219 /* 3220 * This does not test real-address mode, virtual-8086 mode, protected mode, 3221 * or CPL > 0. 3222 */ 3223 static void invvpid_test_v2(void) 3224 { 3225 u64 msr; 3226 int i; 3227 unsigned types = 0; 3228 unsigned type; 3229 3230 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 3231 !(ctrl_cpu_rev[1].clr & CPU_VPID)) 3232 test_skip("VPID not supported"); 3233 3234 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3235 3236 if (!(msr & VPID_CAP_INVVPID)) 3237 test_skip("INVVPID not supported.\n"); 3238 3239 if (msr & VPID_CAP_INVVPID_ADDR) 3240 types |= 1u << INVVPID_ADDR; 3241 if (msr & VPID_CAP_INVVPID_CXTGLB) 3242 types |= 1u << INVVPID_CONTEXT_GLOBAL; 3243 if (msr & VPID_CAP_INVVPID_ALL) 3244 types |= 1u << INVVPID_ALL; 3245 if (msr & VPID_CAP_INVVPID_CXTLOC) 3246 types |= 1u << INVVPID_CONTEXT_LOCAL; 3247 3248 if (!types) 3249 test_skip("No INVVPID types supported.\n"); 3250 3251 for (i = -127; i < 128; i++) 3252 try_invvpid(i, 0xffff, 0); 3253 3254 /* 3255 * VPID must not be more than 16 bits. 3256 */ 3257 for (i = 0; i < 64; i++) 3258 for (type = 0; type < 4; type++) 3259 if (types & (1u << type)) 3260 try_invvpid(type, 1ul << i, 0); 3261 3262 /* 3263 * VPID must not be zero, except for "all contexts." 3264 */ 3265 for (type = 0; type < 4; type++) 3266 if (types & (1u << type)) 3267 try_invvpid(type, 0, 0); 3268 3269 /* 3270 * The gla operand is only validated for single-address INVVPID. 3271 */ 3272 if (types & (1u << INVVPID_ADDR)) 3273 try_invvpid(INVVPID_ADDR, 0xffff, NONCANONICAL); 3274 3275 invvpid_test_gp(); 3276 invvpid_test_ss(); 3277 invvpid_test_pf(); 3278 invvpid_test_compatibility_mode(); 3279 invvpid_test_not_in_vmx_operation(); 3280 } 3281 3282 /* 3283 * Test for early VMLAUNCH failure. Returns true if VMLAUNCH makes it 3284 * at least as far as the guest-state checks. Returns false if the 3285 * VMLAUNCH fails early and execution falls through to the next 3286 * instruction. 3287 */ 3288 static bool vmlaunch_succeeds(void) 3289 { 3290 u32 exit_reason; 3291 3292 /* 3293 * Indirectly set VMX_INST_ERR to 12 ("VMREAD/VMWRITE from/to 3294 * unsupported VMCS component"). The caller can then check 3295 * to see if a failed VM-entry sets VMX_INST_ERR as expected. 3296 */ 3297 vmcs_write(~0u, 0); 3298 3299 vmcs_write(HOST_RIP, (uintptr_t)&&success); 3300 __asm__ __volatile__ goto ("vmwrite %%rsp, %0; vmlaunch" 3301 : 3302 : "r" ((u64)HOST_RSP) 3303 : "cc", "memory" 3304 : success); 3305 return false; 3306 success: 3307 exit_reason = vmcs_read(EXI_REASON); 3308 TEST_ASSERT(exit_reason == (VMX_FAIL_STATE | VMX_ENTRY_FAILURE) || 3309 exit_reason == (VMX_FAIL_MSR | VMX_ENTRY_FAILURE)); 3310 return true; 3311 } 3312 3313 /* 3314 * Try to launch the current VMCS. 3315 */ 3316 static void test_vmx_controls(bool controls_valid, bool xfail) 3317 { 3318 bool success = vmlaunch_succeeds(); 3319 u32 vmx_inst_err; 3320 3321 report_xfail("vmlaunch %s", xfail, success == controls_valid, 3322 controls_valid ? "succeeds" : "fails"); 3323 if (!success) { 3324 vmx_inst_err = vmcs_read(VMX_INST_ERROR); 3325 report("VMX inst error is %d (actual %d)", 3326 vmx_inst_err == VMXERR_ENTRY_INVALID_CONTROL_FIELD, 3327 VMXERR_ENTRY_INVALID_CONTROL_FIELD, vmx_inst_err); 3328 } 3329 } 3330 3331 /* 3332 * Test a particular value of a VM-execution control bit, if the value 3333 * is required or if the value is zero. 3334 */ 3335 static void test_rsvd_ctl_bit_value(const char *name, union vmx_ctrl_msr msr, 3336 enum Encoding encoding, unsigned bit, 3337 unsigned val) 3338 { 3339 u32 mask = 1u << bit; 3340 bool expected; 3341 u32 controls; 3342 3343 if (msr.set & mask) 3344 TEST_ASSERT(msr.clr & mask); 3345 3346 /* 3347 * We can't arbitrarily turn on a control bit, because it may 3348 * introduce dependencies on other VMCS fields. So, we only 3349 * test turning on bits that have a required setting. 3350 */ 3351 if (val && (msr.clr & mask) && !(msr.set & mask)) 3352 return; 3353 3354 report_prefix_pushf("%s %s bit %d", 3355 val ? "Set" : "Clear", name, bit); 3356 3357 controls = vmcs_read(encoding); 3358 if (val) { 3359 vmcs_write(encoding, msr.set | mask); 3360 expected = (msr.clr & mask); 3361 } else { 3362 vmcs_write(encoding, msr.set & ~mask); 3363 expected = !(msr.set & mask); 3364 } 3365 test_vmx_controls(expected, false); 3366 vmcs_write(encoding, controls); 3367 report_prefix_pop(); 3368 } 3369 3370 /* 3371 * Test reserved values of a VM-execution control bit, based on the 3372 * allowed bit settings from the corresponding VMX capability MSR. 3373 */ 3374 static void test_rsvd_ctl_bit(const char *name, union vmx_ctrl_msr msr, 3375 enum Encoding encoding, unsigned bit) 3376 { 3377 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 0); 3378 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 1); 3379 } 3380 3381 /* 3382 * Reserved bits in the pin-based VM-execution controls must be set 3383 * properly. Software may consult the VMX capability MSRs to determine 3384 * the proper settings. 3385 * [Intel SDM] 3386 */ 3387 static void test_pin_based_ctls(void) 3388 { 3389 unsigned bit; 3390 3391 printf("%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PIN" : 3392 "MSR_IA32_VMX_PINBASED_CTLS", ctrl_pin_rev.val); 3393 for (bit = 0; bit < 32; bit++) 3394 test_rsvd_ctl_bit("pin-based controls", 3395 ctrl_pin_rev, PIN_CONTROLS, bit); 3396 } 3397 3398 /* 3399 * Reserved bits in the primary processor-based VM-execution controls 3400 * must be set properly. Software may consult the VMX capability MSRs 3401 * to determine the proper settings. 3402 * [Intel SDM] 3403 */ 3404 static void test_primary_processor_based_ctls(void) 3405 { 3406 unsigned bit; 3407 3408 printf("\n%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PROC" : 3409 "MSR_IA32_VMX_PROCBASED_CTLS", ctrl_cpu_rev[0].val); 3410 for (bit = 0; bit < 32; bit++) 3411 test_rsvd_ctl_bit("primary processor-based controls", 3412 ctrl_cpu_rev[0], CPU_EXEC_CTRL0, bit); 3413 } 3414 3415 /* 3416 * If the "activate secondary controls" primary processor-based 3417 * VM-execution control is 1, reserved bits in the secondary 3418 * processor-based VM-execution controls must be cleared. Software may 3419 * consult the VMX capability MSRs to determine which bits are 3420 * reserved. 3421 * If the "activate secondary controls" primary processor-based 3422 * VM-execution control is 0 (or if the processor does not support the 3423 * 1-setting of that control), no checks are performed on the 3424 * secondary processor-based VM-execution controls. 3425 * [Intel SDM] 3426 */ 3427 static void test_secondary_processor_based_ctls(void) 3428 { 3429 u32 primary; 3430 u32 secondary; 3431 unsigned bit; 3432 3433 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) 3434 return; 3435 3436 primary = vmcs_read(CPU_EXEC_CTRL0); 3437 secondary = vmcs_read(CPU_EXEC_CTRL1); 3438 3439 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3440 printf("\nMSR_IA32_VMX_PROCBASED_CTLS2: %lx\n", ctrl_cpu_rev[1].val); 3441 for (bit = 0; bit < 32; bit++) 3442 test_rsvd_ctl_bit("secondary processor-based controls", 3443 ctrl_cpu_rev[1], CPU_EXEC_CTRL1, bit); 3444 3445 /* 3446 * When the "activate secondary controls" VM-execution control 3447 * is clear, there are no checks on the secondary controls. 3448 */ 3449 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3450 vmcs_write(CPU_EXEC_CTRL1, ~0); 3451 report("Secondary processor-based controls ignored", 3452 vmlaunch_succeeds()); 3453 vmcs_write(CPU_EXEC_CTRL1, secondary); 3454 vmcs_write(CPU_EXEC_CTRL0, primary); 3455 } 3456 3457 static void try_cr3_target_count(unsigned i, unsigned max) 3458 { 3459 report_prefix_pushf("CR3 target count 0x%x", i); 3460 vmcs_write(CR3_TARGET_COUNT, i); 3461 test_vmx_controls(i <= max, false); 3462 report_prefix_pop(); 3463 } 3464 3465 /* 3466 * The CR3-target count must not be greater than 4. Future processors 3467 * may support a different number of CR3-target values. Software 3468 * should read the VMX capability MSR IA32_VMX_MISC to determine the 3469 * number of values supported. 3470 * [Intel SDM] 3471 */ 3472 static void test_cr3_targets(void) 3473 { 3474 unsigned supported_targets = (rdmsr(MSR_IA32_VMX_MISC) >> 16) & 0x1ff; 3475 u32 cr3_targets = vmcs_read(CR3_TARGET_COUNT); 3476 unsigned i; 3477 3478 printf("\nSupported CR3 targets: %d\n", supported_targets); 3479 TEST_ASSERT(supported_targets <= 256); 3480 3481 try_cr3_target_count(-1u, supported_targets); 3482 try_cr3_target_count(0x80000000, supported_targets); 3483 try_cr3_target_count(0x7fffffff, supported_targets); 3484 for (i = 0; i <= supported_targets + 1; i++) 3485 try_cr3_target_count(i, supported_targets); 3486 vmcs_write(CR3_TARGET_COUNT, cr3_targets); 3487 } 3488 3489 /* 3490 * Test a particular address setting in the VMCS 3491 */ 3492 static void test_vmcs_addr(const char *name, 3493 enum Encoding encoding, 3494 u64 align, 3495 bool ignored, 3496 bool xfail_beyond_mapped_ram, 3497 u64 addr) 3498 { 3499 bool xfail = 3500 (xfail_beyond_mapped_ram && 3501 addr > fwcfg_get_u64(FW_CFG_RAM_SIZE) - align && 3502 addr < (1ul << cpuid_maxphyaddr())); 3503 3504 report_prefix_pushf("%s = %lx", name, addr); 3505 vmcs_write(encoding, addr); 3506 test_vmx_controls(ignored || (IS_ALIGNED(addr, align) && 3507 addr < (1ul << cpuid_maxphyaddr())), 3508 xfail); 3509 report_prefix_pop(); 3510 xfail = false; 3511 } 3512 3513 /* 3514 * Test interesting values for a VMCS address 3515 */ 3516 static void test_vmcs_addr_values(const char *name, 3517 enum Encoding encoding, 3518 u64 align, 3519 bool ignored, 3520 bool xfail_beyond_mapped_ram, 3521 u32 bit_start, u32 bit_end) 3522 { 3523 unsigned i; 3524 u64 orig_val = vmcs_read(encoding); 3525 3526 for (i = bit_start; i <= bit_end; i++) 3527 test_vmcs_addr(name, encoding, align, ignored, 3528 xfail_beyond_mapped_ram, 1ul << i); 3529 3530 test_vmcs_addr(name, encoding, align, ignored, 3531 xfail_beyond_mapped_ram, PAGE_SIZE - 1); 3532 test_vmcs_addr(name, encoding, align, ignored, 3533 xfail_beyond_mapped_ram, PAGE_SIZE); 3534 test_vmcs_addr(name, encoding, align, ignored, 3535 xfail_beyond_mapped_ram, 3536 (1ul << cpuid_maxphyaddr()) - PAGE_SIZE); 3537 test_vmcs_addr(name, encoding, align, ignored, 3538 xfail_beyond_mapped_ram, -1ul); 3539 3540 vmcs_write(encoding, orig_val); 3541 } 3542 3543 /* 3544 * Test a physical address reference in the VMCS, when the corresponding 3545 * feature is enabled and when the corresponding feature is disabled. 3546 */ 3547 static void test_vmcs_addr_reference(u32 control_bit, enum Encoding field, 3548 const char *field_name, 3549 const char *control_name, u64 align, 3550 bool xfail_beyond_mapped_ram, 3551 bool control_primary) 3552 { 3553 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 3554 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 3555 u64 page_addr; 3556 3557 if (control_primary) { 3558 if (!(ctrl_cpu_rev[0].clr & control_bit)) 3559 return; 3560 } else { 3561 if (!(ctrl_cpu_rev[1].clr & control_bit)) 3562 return; 3563 } 3564 3565 page_addr = vmcs_read(field); 3566 3567 report_prefix_pushf("%s enabled", control_name); 3568 if (control_primary) { 3569 vmcs_write(CPU_EXEC_CTRL0, primary | control_bit); 3570 } else { 3571 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3572 vmcs_write(CPU_EXEC_CTRL1, secondary | control_bit); 3573 } 3574 3575 test_vmcs_addr_values(field_name, field, align, false, 3576 xfail_beyond_mapped_ram, 0, 63); 3577 report_prefix_pop(); 3578 3579 report_prefix_pushf("%s disabled", control_name); 3580 if (control_primary) { 3581 vmcs_write(CPU_EXEC_CTRL0, primary & ~control_bit); 3582 } else { 3583 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3584 vmcs_write(CPU_EXEC_CTRL1, secondary & ~control_bit); 3585 } 3586 3587 test_vmcs_addr_values(field_name, field, align, true, false, 0, 63); 3588 report_prefix_pop(); 3589 3590 vmcs_write(field, page_addr); 3591 vmcs_write(CPU_EXEC_CTRL0, primary); 3592 } 3593 3594 /* 3595 * If the "use I/O bitmaps" VM-execution control is 1, bits 11:0 of 3596 * each I/O-bitmap address must be 0. Neither address should set any 3597 * bits beyond the processor's physical-address width. 3598 * [Intel SDM] 3599 */ 3600 static void test_io_bitmaps(void) 3601 { 3602 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_A, 3603 "I/O bitmap A", "Use I/O bitmaps", 3604 PAGE_SIZE, false, true); 3605 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_B, 3606 "I/O bitmap B", "Use I/O bitmaps", 3607 PAGE_SIZE, false, true); 3608 } 3609 3610 /* 3611 * If the "use MSR bitmaps" VM-execution control is 1, bits 11:0 of 3612 * the MSR-bitmap address must be 0. The address should not set any 3613 * bits beyond the processor's physical-address width. 3614 * [Intel SDM] 3615 */ 3616 static void test_msr_bitmap(void) 3617 { 3618 test_vmcs_addr_reference(CPU_MSR_BITMAP, MSR_BITMAP, 3619 "MSR bitmap", "Use MSR bitmaps", 3620 PAGE_SIZE, false, true); 3621 } 3622 3623 /* 3624 * If the "use TPR shadow" VM-execution control is 1, the virtual-APIC 3625 * address must satisfy the following checks: 3626 * - Bits 11:0 of the address must be 0. 3627 * - The address should not set any bits beyond the processor's 3628 * physical-address width. 3629 * [Intel SDM] 3630 */ 3631 static void test_apic_virt_addr(void) 3632 { 3633 test_vmcs_addr_reference(CPU_TPR_SHADOW, APIC_VIRT_ADDR, 3634 "virtual-APIC address", "Use TPR shadow", 3635 PAGE_SIZE, true, true); 3636 } 3637 3638 /* 3639 * If the "virtualize APIC-accesses" VM-execution control is 1, the 3640 * APIC-access address must satisfy the following checks: 3641 * - Bits 11:0 of the address must be 0. 3642 * - The address should not set any bits beyond the processor's 3643 * physical-address width. 3644 * [Intel SDM] 3645 */ 3646 static void test_apic_access_addr(void) 3647 { 3648 void *apic_access_page = alloc_page(); 3649 3650 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_page)); 3651 3652 test_vmcs_addr_reference(CPU_VIRT_APIC_ACCESSES, APIC_ACCS_ADDR, 3653 "APIC-access address", 3654 "virtualize APIC-accesses", PAGE_SIZE, 3655 false, false); 3656 } 3657 3658 static bool set_bit_pattern(u8 mask, u32 *secondary) 3659 { 3660 u8 i; 3661 bool flag = false; 3662 u32 test_bits[3] = { 3663 CPU_VIRT_X2APIC, 3664 CPU_APIC_REG_VIRT, 3665 CPU_VINTD 3666 }; 3667 3668 for (i = 0; i < ARRAY_SIZE(test_bits); i++) { 3669 if ((mask & (1u << i)) && 3670 (ctrl_cpu_rev[1].clr & test_bits[i])) { 3671 *secondary |= test_bits[i]; 3672 flag = true; 3673 } 3674 } 3675 3676 return (flag); 3677 } 3678 3679 /* 3680 * If the "use TPR shadow" VM-execution control is 0, the following 3681 * VM-execution controls must also be 0: 3682 * - virtualize x2APIC mode 3683 * - APIC-register virtualization 3684 * - virtual-interrupt delivery 3685 * [Intel SDM] 3686 * 3687 * 2. If the "virtualize x2APIC mode" VM-execution control is 1, the 3688 * "virtualize APIC accesses" VM-execution control must be 0. 3689 * [Intel SDM] 3690 */ 3691 static void test_apic_virtual_ctls(void) 3692 { 3693 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3694 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3695 u32 primary = saved_primary; 3696 u32 secondary = saved_secondary; 3697 bool ctrl = false; 3698 char str[10] = "disabled"; 3699 u8 i = 0, j; 3700 3701 /* 3702 * First test 3703 */ 3704 if (!((ctrl_cpu_rev[0].clr & (CPU_SECONDARY | CPU_TPR_SHADOW)) == 3705 (CPU_SECONDARY | CPU_TPR_SHADOW))) 3706 return; 3707 3708 primary |= CPU_SECONDARY; 3709 primary &= ~CPU_TPR_SHADOW; 3710 vmcs_write(CPU_EXEC_CTRL0, primary); 3711 3712 while (1) { 3713 for (j = 1; j < 8; j++) { 3714 secondary &= ~(CPU_VIRT_X2APIC | CPU_APIC_REG_VIRT | CPU_VINTD); 3715 if (primary & CPU_TPR_SHADOW) { 3716 ctrl = true; 3717 } else { 3718 if (! set_bit_pattern(j, &secondary)) 3719 ctrl = true; 3720 else 3721 ctrl = false; 3722 } 3723 3724 vmcs_write(CPU_EXEC_CTRL1, secondary); 3725 report_prefix_pushf("Use TPR shadow %s, virtualize x2APIC mode %s, APIC-register virtualization %s, virtual-interrupt delivery %s", 3726 str, (secondary & CPU_VIRT_X2APIC) ? "enabled" : "disabled", (secondary & CPU_APIC_REG_VIRT) ? "enabled" : "disabled", (secondary & CPU_VINTD) ? "enabled" : "disabled"); 3727 test_vmx_controls(ctrl, false); 3728 report_prefix_pop(); 3729 } 3730 3731 if (i == 1) 3732 break; 3733 i++; 3734 3735 primary |= CPU_TPR_SHADOW; 3736 vmcs_write(CPU_EXEC_CTRL0, primary); 3737 strcpy(str, "enabled"); 3738 } 3739 3740 /* 3741 * Second test 3742 */ 3743 u32 apic_virt_ctls = (CPU_VIRT_X2APIC | CPU_VIRT_APIC_ACCESSES); 3744 3745 primary = saved_primary; 3746 secondary = saved_secondary; 3747 if (!((ctrl_cpu_rev[1].clr & apic_virt_ctls) == apic_virt_ctls)) 3748 return; 3749 3750 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3751 secondary &= ~CPU_VIRT_APIC_ACCESSES; 3752 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_X2APIC); 3753 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access disabled"); 3754 test_vmx_controls(true, false); 3755 report_prefix_pop(); 3756 3757 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_APIC_ACCESSES); 3758 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access enabled"); 3759 test_vmx_controls(true, false); 3760 report_prefix_pop(); 3761 3762 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_X2APIC); 3763 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access enabled"); 3764 test_vmx_controls(false, false); 3765 report_prefix_pop(); 3766 3767 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_APIC_ACCESSES); 3768 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access disabled"); 3769 test_vmx_controls(true, false); 3770 report_prefix_pop(); 3771 3772 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3773 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3774 } 3775 3776 /* 3777 * If the "virtual-interrupt delivery" VM-execution control is 1, the 3778 * "external-interrupt exiting" VM-execution control must be 1. 3779 * [Intel SDM] 3780 */ 3781 static void test_virtual_intr_ctls(void) 3782 { 3783 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3784 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3785 u32 saved_pin = vmcs_read(PIN_CONTROLS); 3786 u32 primary = saved_primary; 3787 u32 secondary = saved_secondary; 3788 u32 pin = saved_pin; 3789 3790 if (!((ctrl_cpu_rev[1].clr & CPU_VINTD) && 3791 (ctrl_pin_rev.clr & PIN_EXTINT))) 3792 return; 3793 3794 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 3795 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VINTD); 3796 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 3797 report_prefix_pushf("Virtualize interrupt-delivery disabled; external-interrupt exiting disabled"); 3798 test_vmx_controls(true, false); 3799 report_prefix_pop(); 3800 3801 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VINTD); 3802 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 3803 test_vmx_controls(false, false); 3804 report_prefix_pop(); 3805 3806 vmcs_write(PIN_CONTROLS, pin | PIN_EXTINT); 3807 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting enabled"); 3808 test_vmx_controls(true, false); 3809 report_prefix_pop(); 3810 3811 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 3812 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 3813 test_vmx_controls(false, false); 3814 report_prefix_pop(); 3815 3816 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3817 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3818 vmcs_write(PIN_CONTROLS, saved_pin); 3819 } 3820 3821 static void test_pi_desc_addr(u64 addr, bool ctrl) 3822 { 3823 vmcs_write(POSTED_INTR_DESC_ADDR, addr); 3824 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-descriptor-address 0x%lx", addr); 3825 test_vmx_controls(ctrl, false); 3826 report_prefix_pop(); 3827 } 3828 3829 /* 3830 * If the “process posted interrupts†VM-execution control is 1, the 3831 * following must be true: 3832 * 3833 * - The “virtual-interrupt delivery†VM-execution control is 1. 3834 * - The “acknowledge interrupt on exit†VM-exit control is 1. 3835 * - The posted-interrupt notification vector has a value in the 3836 * - range 0–255 (bits 15:8 are all 0). 3837 * - Bits 5:0 of the posted-interrupt descriptor address are all 0. 3838 * - The posted-interrupt descriptor address does not set any bits 3839 * beyond the processor's physical-address width. 3840 * [Intel SDM] 3841 */ 3842 static void test_posted_intr(void) 3843 { 3844 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3845 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3846 u32 saved_pin = vmcs_read(PIN_CONTROLS); 3847 u32 exit_ctl_saved = vmcs_read(EXI_CONTROLS); 3848 u32 primary = saved_primary; 3849 u32 secondary = saved_secondary; 3850 u32 pin = saved_pin; 3851 u32 exit_ctl = exit_ctl_saved; 3852 u16 vec; 3853 int i; 3854 3855 if (!((ctrl_pin_rev.clr & PIN_POST_INTR) && 3856 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 3857 (ctrl_exit_rev.clr & EXI_INTA))) 3858 return; 3859 3860 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 3861 3862 /* 3863 * Test virtual-interrupt-delivery and acknowledge-interrupt-on-exit 3864 */ 3865 pin |= PIN_POST_INTR; 3866 vmcs_write(PIN_CONTROLS, pin); 3867 secondary &= ~CPU_VINTD; 3868 vmcs_write(CPU_EXEC_CTRL1, secondary); 3869 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled"); 3870 test_vmx_controls(false, false); 3871 report_prefix_pop(); 3872 3873 secondary |= CPU_VINTD; 3874 vmcs_write(CPU_EXEC_CTRL1, secondary); 3875 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled"); 3876 test_vmx_controls(false, false); 3877 report_prefix_pop(); 3878 3879 exit_ctl &= ~EXI_INTA; 3880 vmcs_write(EXI_CONTROLS, exit_ctl); 3881 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit disabled"); 3882 test_vmx_controls(false, false); 3883 report_prefix_pop(); 3884 3885 exit_ctl |= EXI_INTA; 3886 vmcs_write(EXI_CONTROLS, exit_ctl); 3887 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 3888 test_vmx_controls(true, false); 3889 report_prefix_pop(); 3890 3891 secondary &= ~CPU_VINTD; 3892 vmcs_write(CPU_EXEC_CTRL1, secondary); 3893 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled; acknowledge-interrupt-on-exit enabled"); 3894 test_vmx_controls(false, false); 3895 report_prefix_pop(); 3896 3897 secondary |= CPU_VINTD; 3898 vmcs_write(CPU_EXEC_CTRL1, secondary); 3899 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 3900 test_vmx_controls(true, false); 3901 report_prefix_pop(); 3902 3903 /* 3904 * Test posted-interrupt notification vector 3905 */ 3906 for (i = 0; i < 8; i++) { 3907 vec = (1ul << i); 3908 vmcs_write(PINV, vec); 3909 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 3910 test_vmx_controls(true, false); 3911 report_prefix_pop(); 3912 } 3913 for (i = 8; i < 16; i++) { 3914 vec = (1ul << i); 3915 vmcs_write(PINV, vec); 3916 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 3917 test_vmx_controls(false, false); 3918 report_prefix_pop(); 3919 } 3920 3921 vec &= ~(0xff << 8); 3922 vmcs_write(PINV, vec); 3923 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 3924 test_vmx_controls(true, false); 3925 report_prefix_pop(); 3926 3927 /* 3928 * Test posted-interrupt descriptor addresss 3929 */ 3930 for (i = 0; i < 6; i++) { 3931 test_pi_desc_addr(1ul << i, false); 3932 } 3933 3934 test_pi_desc_addr(0xf0, false); 3935 test_pi_desc_addr(0xff, false); 3936 test_pi_desc_addr(0x0f, false); 3937 test_pi_desc_addr(0x8000, true); 3938 test_pi_desc_addr(0x00, true); 3939 test_pi_desc_addr(0xc000, true); 3940 3941 test_vmcs_addr_values("process-posted interrupts", 3942 POSTED_INTR_DESC_ADDR, 64, 3943 false, false, 0, 63); 3944 3945 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3946 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3947 vmcs_write(PIN_CONTROLS, saved_pin); 3948 } 3949 3950 static void test_apic_ctls(void) 3951 { 3952 test_apic_virt_addr(); 3953 test_apic_access_addr(); 3954 test_apic_virtual_ctls(); 3955 test_virtual_intr_ctls(); 3956 test_posted_intr(); 3957 } 3958 3959 /* 3960 * If the “enable VPID†VM-execution control is 1, the value of the 3961 * of the VPID VM-execution control field must not be 0000H. 3962 * [Intel SDM] 3963 */ 3964 static void test_vpid(void) 3965 { 3966 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3967 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3968 u16 vpid = 0x0000; 3969 int i; 3970 3971 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 3972 (ctrl_cpu_rev[1].clr & CPU_VPID))) { 3973 test_skip("Secondary controls and/or VPID not supported"); 3974 return; 3975 } 3976 3977 vmcs_write(CPU_EXEC_CTRL0, saved_primary | CPU_SECONDARY); 3978 vmcs_write(CPU_EXEC_CTRL1, saved_secondary & ~CPU_VPID); 3979 vmcs_write(VPID, vpid); 3980 report_prefix_pushf("VPID disabled; VPID value %x", vpid); 3981 test_vmx_controls(true, false); 3982 report_prefix_pop(); 3983 3984 vmcs_write(CPU_EXEC_CTRL1, saved_secondary | CPU_VPID); 3985 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 3986 test_vmx_controls(false, false); 3987 report_prefix_pop(); 3988 3989 for (i = 0; i < 16; i++) { 3990 vpid = (short)1 << i;; 3991 vmcs_write(VPID, vpid); 3992 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 3993 test_vmx_controls(true, false); 3994 report_prefix_pop(); 3995 } 3996 3997 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3998 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3999 } 4000 4001 static void set_vtpr(unsigned vtpr) 4002 { 4003 *(u32 *)phys_to_virt(vmcs_read(APIC_VIRT_ADDR) + APIC_TASKPRI) = vtpr; 4004 } 4005 4006 static void try_tpr_threshold_and_vtpr(unsigned threshold, unsigned vtpr) 4007 { 4008 bool valid = true; 4009 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4010 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4011 4012 if ((primary & CPU_TPR_SHADOW) && 4013 (!(primary & CPU_SECONDARY) || 4014 !(secondary & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 4015 valid = (threshold & 0xf) <= ((vtpr >> 4) & 0xf); 4016 4017 set_vtpr(vtpr); 4018 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0x%x", 4019 threshold, (vtpr >> 4) & 0xf); 4020 test_vmx_controls(valid, false); 4021 report_prefix_pop(); 4022 } 4023 4024 static void test_invalid_event_injection(void) 4025 { 4026 u32 ent_intr_info_save = vmcs_read(ENT_INTR_INFO); 4027 u32 ent_intr_error_save = vmcs_read(ENT_INTR_ERROR); 4028 u32 ent_inst_len_save = vmcs_read(ENT_INST_LEN); 4029 u32 primary_save = vmcs_read(CPU_EXEC_CTRL0); 4030 u32 secondary_save = vmcs_read(CPU_EXEC_CTRL1); 4031 u64 guest_cr0_save = vmcs_read(GUEST_CR0); 4032 u32 ent_intr_info_base = INTR_INFO_VALID_MASK; 4033 u32 ent_intr_info, ent_intr_err, ent_intr_len; 4034 u32 cnt; 4035 4036 /* Setup */ 4037 report_prefix_push("invalid event injection"); 4038 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4039 vmcs_write(ENT_INST_LEN, 0x00000001); 4040 4041 /* The field’s interruption type is not set to a reserved value. */ 4042 ent_intr_info = ent_intr_info_base | INTR_TYPE_RESERVED | DE_VECTOR; 4043 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4044 "RESERVED interruption type invalid [-]", 4045 ent_intr_info); 4046 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4047 test_vmx_controls(false, false); 4048 report_prefix_pop(); 4049 4050 ent_intr_info = ent_intr_info_base | INTR_TYPE_EXT_INTR | 4051 DE_VECTOR; 4052 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4053 "RESERVED interruption type invalid [+]", 4054 ent_intr_info); 4055 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4056 test_vmx_controls(true, false); 4057 report_prefix_pop(); 4058 4059 /* If the interruption type is other event, the vector is 0. */ 4060 ent_intr_info = ent_intr_info_base | INTR_TYPE_OTHER_EVENT | DB_VECTOR; 4061 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4062 "(OTHER EVENT && vector != 0) invalid [-]", 4063 ent_intr_info); 4064 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4065 test_vmx_controls(false, false); 4066 report_prefix_pop(); 4067 4068 /* If the interruption type is NMI, the vector is 2 (negative case). */ 4069 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | DE_VECTOR; 4070 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4071 "(NMI && vector != 2) invalid [-]", ent_intr_info); 4072 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4073 test_vmx_controls(false, false); 4074 report_prefix_pop(); 4075 4076 /* If the interruption type is NMI, the vector is 2 (positive case). */ 4077 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | NMI_VECTOR; 4078 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4079 "(NMI && vector == 2) valid [+]", ent_intr_info); 4080 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4081 test_vmx_controls(true, false); 4082 report_prefix_pop(); 4083 4084 /* 4085 * If the interruption type 4086 * is HW exception, the vector is at most 31. 4087 */ 4088 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 0x20; 4089 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4090 "(HW exception && vector > 31) invalid [-]", 4091 ent_intr_info); 4092 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4093 test_vmx_controls(false, false); 4094 report_prefix_pop(); 4095 4096 /* 4097 * deliver-error-code is 1 iff either 4098 * (a) the "unrestricted guest" VM-execution control is 0 4099 * (b) CR0.PE is set. 4100 */ 4101 4102 /* Assert that unrestricted guest is disabled or unsupported */ 4103 assert(!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 4104 !(secondary_save & CPU_URG)); 4105 4106 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4107 GP_VECTOR; 4108 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4109 "error code <-> (!URG || prot_mode) [-]", 4110 ent_intr_info); 4111 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4112 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4113 test_vmx_controls(false, false); 4114 report_prefix_pop(); 4115 4116 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4117 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4118 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4119 "error code <-> (!URG || prot_mode) [+]", 4120 ent_intr_info); 4121 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4122 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4123 test_vmx_controls(true, false); 4124 report_prefix_pop(); 4125 4126 if (enable_unrestricted_guest()) 4127 goto skip_unrestricted_guest; 4128 4129 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4130 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4131 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4132 "error code <-> (!URG || prot_mode) [-]", 4133 ent_intr_info); 4134 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4135 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4136 test_vmx_controls(false, false); 4137 report_prefix_pop(); 4138 4139 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4140 GP_VECTOR; 4141 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4142 "error code <-> (!URG || prot_mode) [-]", 4143 ent_intr_info); 4144 vmcs_write(GUEST_CR0, guest_cr0_save | X86_CR0_PE); 4145 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4146 test_vmx_controls(false, false); 4147 report_prefix_pop(); 4148 4149 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4150 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4151 4152 skip_unrestricted_guest: 4153 vmcs_write(GUEST_CR0, guest_cr0_save); 4154 4155 /* deliver-error-code is 1 iff the interruption type is HW exception */ 4156 report_prefix_push("error code <-> HW exception"); 4157 for (cnt = 0; cnt < 8; cnt++) { 4158 u32 exception_type_mask = cnt << 8; 4159 u32 deliver_error_code_mask = 4160 exception_type_mask != INTR_TYPE_HARD_EXCEPTION ? 4161 INTR_INFO_DELIVER_CODE_MASK : 0; 4162 4163 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4164 exception_type_mask | GP_VECTOR; 4165 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4166 ent_intr_info); 4167 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4168 test_vmx_controls(false, false); 4169 report_prefix_pop(); 4170 } 4171 report_prefix_pop(); 4172 4173 /* 4174 * deliver-error-code is 1 iff the the vector 4175 * indicates an exception that would normally deliver an error code 4176 */ 4177 report_prefix_push("error code <-> vector delivers error code"); 4178 for (cnt = 0; cnt < 32; cnt++) { 4179 bool has_error_code = false; 4180 u32 deliver_error_code_mask; 4181 4182 switch (cnt) { 4183 case DF_VECTOR: 4184 case TS_VECTOR: 4185 case NP_VECTOR: 4186 case SS_VECTOR: 4187 case GP_VECTOR: 4188 case PF_VECTOR: 4189 case AC_VECTOR: 4190 has_error_code = true; 4191 } 4192 4193 /* Negative case */ 4194 deliver_error_code_mask = has_error_code ? 4195 0 : 4196 INTR_INFO_DELIVER_CODE_MASK; 4197 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4198 INTR_TYPE_HARD_EXCEPTION | cnt; 4199 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4200 ent_intr_info); 4201 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4202 test_vmx_controls(false, false); 4203 report_prefix_pop(); 4204 4205 /* Positive case */ 4206 deliver_error_code_mask = has_error_code ? 4207 INTR_INFO_DELIVER_CODE_MASK : 4208 0; 4209 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4210 INTR_TYPE_HARD_EXCEPTION | cnt; 4211 report_prefix_pushf("VM-entry intr info=0x%x [+]", 4212 ent_intr_info); 4213 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4214 test_vmx_controls(true, false); 4215 report_prefix_pop(); 4216 } 4217 report_prefix_pop(); 4218 4219 /* Reserved bits in the field (30:12) are 0. */ 4220 report_prefix_push("reserved bits clear"); 4221 for (cnt = 12; cnt <= 30; cnt++) { 4222 ent_intr_info = ent_intr_info_base | 4223 INTR_INFO_DELIVER_CODE_MASK | 4224 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR | 4225 (1U << cnt); 4226 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4227 ent_intr_info); 4228 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4229 test_vmx_controls(false, false); 4230 report_prefix_pop(); 4231 } 4232 report_prefix_pop(); 4233 4234 /* 4235 * If deliver-error-code is 1 4236 * bits 31:15 of the VM-entry exception error-code field are 0. 4237 */ 4238 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4239 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4240 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4241 "VM-entry exception error code[31:15] clear", 4242 ent_intr_info); 4243 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4244 for (cnt = 15; cnt <= 31; cnt++) { 4245 ent_intr_err = 1U << cnt; 4246 report_prefix_pushf("VM-entry intr error=0x%x [-]", 4247 ent_intr_err); 4248 vmcs_write(ENT_INTR_ERROR, ent_intr_err); 4249 test_vmx_controls(false, false); 4250 report_prefix_pop(); 4251 } 4252 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4253 report_prefix_pop(); 4254 4255 /* 4256 * If the interruption type is software interrupt, software exception, 4257 * or privileged software exception, the VM-entry instruction-length 4258 * field is in the range 0–15. 4259 */ 4260 4261 for (cnt = 0; cnt < 3; cnt++) { 4262 switch (cnt) { 4263 case 0: 4264 ent_intr_info = ent_intr_info_base | 4265 INTR_TYPE_SOFT_INTR; 4266 break; 4267 case 1: 4268 ent_intr_info = ent_intr_info_base | 4269 INTR_TYPE_SOFT_EXCEPTION; 4270 break; 4271 case 2: 4272 ent_intr_info = ent_intr_info_base | 4273 INTR_TYPE_PRIV_SW_EXCEPTION; 4274 break; 4275 } 4276 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4277 "VM-entry instruction-length check", 4278 ent_intr_info); 4279 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4280 4281 /* Instruction length set to -1 (0xFFFFFFFF) should fail */ 4282 ent_intr_len = -1; 4283 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4284 ent_intr_len); 4285 vmcs_write(ENT_INST_LEN, ent_intr_len); 4286 test_vmx_controls(false, false); 4287 report_prefix_pop(); 4288 4289 /* Instruction length set to 16 should fail */ 4290 ent_intr_len = 0x00000010; 4291 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4292 ent_intr_len); 4293 vmcs_write(ENT_INST_LEN, 0x00000010); 4294 test_vmx_controls(false, false); 4295 report_prefix_pop(); 4296 4297 report_prefix_pop(); 4298 } 4299 4300 /* Cleanup */ 4301 vmcs_write(ENT_INTR_INFO, ent_intr_info_save); 4302 vmcs_write(ENT_INTR_ERROR, ent_intr_error_save); 4303 vmcs_write(ENT_INST_LEN, ent_inst_len_save); 4304 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4305 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4306 vmcs_write(GUEST_CR0, guest_cr0_save); 4307 report_prefix_pop(); 4308 } 4309 4310 /* 4311 * Test interesting vTPR values for a given TPR threshold. 4312 */ 4313 static void test_vtpr_values(unsigned threshold) 4314 { 4315 try_tpr_threshold_and_vtpr(threshold, (threshold - 1) << 4); 4316 try_tpr_threshold_and_vtpr(threshold, threshold << 4); 4317 try_tpr_threshold_and_vtpr(threshold, (threshold + 1) << 4); 4318 } 4319 4320 static void try_tpr_threshold(unsigned threshold) 4321 { 4322 bool valid = true; 4323 4324 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4325 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4326 4327 if ((primary & CPU_TPR_SHADOW) && !((primary & CPU_SECONDARY) && 4328 (secondary & CPU_VINTD))) 4329 valid = !(threshold >> 4); 4330 4331 set_vtpr(-1); 4332 vmcs_write(TPR_THRESHOLD, threshold); 4333 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0xf", threshold); 4334 test_vmx_controls(valid, false); 4335 report_prefix_pop(); 4336 4337 if (valid) 4338 test_vtpr_values(threshold); 4339 } 4340 4341 /* 4342 * Test interesting TPR threshold values. 4343 */ 4344 static void test_tpr_threshold_values(void) 4345 { 4346 unsigned i; 4347 4348 for (i = 0; i < 0x10; i++) 4349 try_tpr_threshold(i); 4350 for (i = 4; i < 32; i++) 4351 try_tpr_threshold(1u << i); 4352 try_tpr_threshold(-1u); 4353 try_tpr_threshold(0x7fffffff); 4354 } 4355 4356 /* 4357 * This test covers the following two VM entry checks: 4358 * 4359 * i) If the "use TPR shadow" VM-execution control is 1 and the 4360 * "virtual-interrupt delivery" VM-execution control is 0, bits 4361 * 31:4 of the TPR threshold VM-execution control field must 4362 be 0. 4363 * [Intel SDM] 4364 * 4365 * ii) If the "use TPR shadow" VM-execution control is 1, the 4366 * "virtual-interrupt delivery" VM-execution control is 0 4367 * and the "virtualize APIC accesses" VM-execution control 4368 * is 0, the value of bits 3:0 of the TPR threshold VM-execution 4369 * control field must not be greater than the value of bits 4370 * 7:4 of VTPR. 4371 * [Intel SDM] 4372 */ 4373 static void test_tpr_threshold(void) 4374 { 4375 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4376 void *virtual_apic_page; 4377 4378 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) 4379 return; 4380 4381 virtual_apic_page = alloc_page(); 4382 memset(virtual_apic_page, 0xff, PAGE_SIZE); 4383 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 4384 4385 vmcs_write(CPU_EXEC_CTRL0, primary & ~(CPU_TPR_SHADOW | CPU_SECONDARY)); 4386 report_prefix_pushf("Use TPR shadow disabled, secondary controls disabled"); 4387 test_tpr_threshold_values(); 4388 report_prefix_pop(); 4389 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_TPR_SHADOW); 4390 report_prefix_pushf("Use TPR shadow enabled, secondary controls disabled"); 4391 test_tpr_threshold_values(); 4392 report_prefix_pop(); 4393 4394 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4395 (ctrl_cpu_rev[1].clr & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) { 4396 vmcs_write(CPU_EXEC_CTRL0, primary); 4397 return; 4398 } 4399 4400 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4401 4402 if (ctrl_cpu_rev[1].clr & CPU_VINTD) { 4403 vmcs_write(CPU_EXEC_CTRL1, CPU_VINTD); 4404 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4405 test_tpr_threshold_values(); 4406 report_prefix_pop(); 4407 4408 vmcs_write(CPU_EXEC_CTRL0, 4409 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4410 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4411 test_tpr_threshold_values(); 4412 report_prefix_pop(); 4413 } 4414 4415 if (ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES) { 4416 vmcs_write(CPU_EXEC_CTRL0, 4417 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4418 vmcs_write(CPU_EXEC_CTRL1, CPU_VIRT_APIC_ACCESSES); 4419 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4420 test_tpr_threshold_values(); 4421 report_prefix_pop(); 4422 4423 vmcs_write(CPU_EXEC_CTRL0, 4424 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4425 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4426 test_tpr_threshold_values(); 4427 report_prefix_pop(); 4428 } 4429 4430 if ((ctrl_cpu_rev[1].clr & 4431 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) == 4432 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) { 4433 vmcs_write(CPU_EXEC_CTRL0, 4434 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4435 vmcs_write(CPU_EXEC_CTRL1, 4436 CPU_VINTD | CPU_VIRT_APIC_ACCESSES); 4437 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4438 test_tpr_threshold_values(); 4439 report_prefix_pop(); 4440 4441 vmcs_write(CPU_EXEC_CTRL0, 4442 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4443 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4444 test_tpr_threshold_values(); 4445 report_prefix_pop(); 4446 } 4447 4448 vmcs_write(CPU_EXEC_CTRL1, secondary); 4449 vmcs_write(CPU_EXEC_CTRL0, primary); 4450 } 4451 4452 /* 4453 * This test verifies the following two vmentry checks: 4454 * 4455 * If the "NMI exiting" VM-execution control is 0, "Virtual NMIs" 4456 * VM-execution control must be 0. 4457 * [Intel SDM] 4458 * 4459 * If the “virtual NMIs” VM-execution control is 0, the “NMI-window 4460 * exiting” VM-execution control must be 0. 4461 * [Intel SDM] 4462 */ 4463 static void test_nmi_ctrls(void) 4464 { 4465 u32 pin_ctrls, cpu_ctrls0, test_pin_ctrls, test_cpu_ctrls0; 4466 4467 if ((ctrl_pin_rev.clr & (PIN_NMI | PIN_VIRT_NMI)) != 4468 (PIN_NMI | PIN_VIRT_NMI)) { 4469 test_skip("NMI exiting and Virtual NMIs are not supported !"); 4470 return; 4471 } 4472 4473 /* Save the controls so that we can restore them after our tests */ 4474 pin_ctrls = vmcs_read(PIN_CONTROLS); 4475 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 4476 4477 test_pin_ctrls = pin_ctrls & ~(PIN_NMI | PIN_VIRT_NMI); 4478 test_cpu_ctrls0 = cpu_ctrls0 & ~CPU_NMI_WINDOW; 4479 4480 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4481 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs disabled"); 4482 test_vmx_controls(true, false); 4483 report_prefix_pop(); 4484 4485 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_VIRT_NMI); 4486 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs enabled"); 4487 test_vmx_controls(false, false); 4488 report_prefix_pop(); 4489 4490 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4491 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs enabled"); 4492 test_vmx_controls(true, false); 4493 report_prefix_pop(); 4494 4495 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_NMI); 4496 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs disabled"); 4497 test_vmx_controls(true, false); 4498 report_prefix_pop(); 4499 4500 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 4501 report_info("NMI-window exiting is not supported, skipping..."); 4502 goto done; 4503 } 4504 4505 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4506 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4507 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting enabled"); 4508 test_vmx_controls(false, false); 4509 report_prefix_pop(); 4510 4511 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4512 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4513 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting disabled"); 4514 test_vmx_controls(true, false); 4515 report_prefix_pop(); 4516 4517 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4518 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4519 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting enabled"); 4520 test_vmx_controls(true, false); 4521 report_prefix_pop(); 4522 4523 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4524 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4525 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting disabled"); 4526 test_vmx_controls(true, false); 4527 report_prefix_pop(); 4528 4529 /* Restore the controls to their original values */ 4530 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 4531 done: 4532 vmcs_write(PIN_CONTROLS, pin_ctrls); 4533 } 4534 4535 static void test_eptp_ad_bit(u64 eptp, bool ctrl) 4536 { 4537 vmcs_write(EPTP, eptp); 4538 report_prefix_pushf("Enable-EPT enabled; EPT accessed and dirty flag %s", 4539 (eptp & EPTP_AD_FLAG) ? "1": "0"); 4540 test_vmx_controls(ctrl, false); 4541 report_prefix_pop(); 4542 4543 } 4544 4545 /* 4546 * 1. If the "enable EPT" VM-execution control is 1, the "EPTP VM-execution" 4547 * control field must satisfy the following checks: 4548 * 4549 * - The EPT memory type (bits 2:0) must be a value supported by the 4550 * processor as indicated in the IA32_VMX_EPT_VPID_CAP MSR. 4551 * - Bits 5:3 (1 less than the EPT page-walk length) must be 3, 4552 * indicating an EPT page-walk length of 4. 4553 * - Bit 6 (enable bit for accessed and dirty flags for EPT) must be 4554 * 0 if bit 21 of the IA32_VMX_EPT_VPID_CAP MSR is read as 0, 4555 * indicating that the processor does not support accessed and dirty 4556 * dirty flags for EPT. 4557 * - Reserved bits 11:7 and 63:N (where N is the processor's 4558 * physical-address width) must all be 0. 4559 * 4560 * 2. If the "unrestricted guest" VM-execution control is 1, the 4561 * "enable EPT" VM-execution control must also be 1. 4562 */ 4563 static void test_ept_eptp(void) 4564 { 4565 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4566 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4567 u64 eptp_saved = vmcs_read(EPTP); 4568 u32 primary = primary_saved; 4569 u32 secondary = secondary_saved; 4570 u64 msr, eptp = eptp_saved; 4571 bool un_cache = false; 4572 bool wr_bk = false; 4573 bool ctrl; 4574 u32 i, maxphysaddr; 4575 u64 j, resv_bits_mask = 0; 4576 4577 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4578 (ctrl_cpu_rev[1].clr & CPU_EPT))) { 4579 test_skip("\"CPU secondary\" and/or \"enable EPT\" execution controls are not supported !"); 4580 return; 4581 } 4582 4583 /* 4584 * Memory type (bits 2:0) 4585 */ 4586 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 4587 if (msr & EPT_CAP_UC) 4588 un_cache = true; 4589 if (msr & EPT_CAP_WB) 4590 wr_bk = true; 4591 4592 primary |= CPU_SECONDARY; 4593 vmcs_write(CPU_EXEC_CTRL0, primary); 4594 secondary |= CPU_EPT; 4595 vmcs_write(CPU_EXEC_CTRL1, secondary); 4596 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4597 (3ul << EPTP_PG_WALK_LEN_SHIFT); 4598 vmcs_write(EPTP, eptp); 4599 4600 for (i = 0; i < 8; i++) { 4601 if (i == 0) { 4602 if (un_cache) { 4603 report_info("EPT paging structure memory-type is Un-cacheable\n"); 4604 ctrl = true; 4605 } else { 4606 ctrl = false; 4607 } 4608 } else if (i == 6) { 4609 if (wr_bk) { 4610 report_info("EPT paging structure memory-type is Write-back\n"); 4611 ctrl = true; 4612 } else { 4613 ctrl = false; 4614 } 4615 } else { 4616 ctrl = false; 4617 } 4618 4619 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | i; 4620 vmcs_write(EPTP, eptp); 4621 report_prefix_pushf("Enable-EPT enabled; EPT memory type %lu", 4622 eptp & EPT_MEM_TYPE_MASK); 4623 test_vmx_controls(ctrl, false); 4624 report_prefix_pop(); 4625 } 4626 4627 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | 6ul; 4628 4629 /* 4630 * Page walk length (bits 5:3) 4631 */ 4632 for (i = 0; i < 8; i++) { 4633 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4634 (i << EPTP_PG_WALK_LEN_SHIFT); 4635 if (i == 3) 4636 ctrl = true; 4637 else 4638 ctrl = false; 4639 4640 vmcs_write(EPTP, eptp); 4641 report_prefix_pushf("Enable-EPT enabled; EPT page walk length %lu", 4642 eptp & EPTP_PG_WALK_LEN_MASK); 4643 test_vmx_controls(ctrl, false); 4644 report_prefix_pop(); 4645 } 4646 4647 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4648 3ul << EPTP_PG_WALK_LEN_SHIFT; 4649 4650 /* 4651 * Accessed and dirty flag (bit 6) 4652 */ 4653 if (msr & EPT_CAP_AD_FLAG) { 4654 report_info("Processor supports accessed and dirty flag"); 4655 eptp &= ~EPTP_AD_FLAG; 4656 test_eptp_ad_bit(eptp, true); 4657 4658 eptp |= EPTP_AD_FLAG; 4659 test_eptp_ad_bit(eptp, true); 4660 } else { 4661 report_info("Processor does not supports accessed and dirty flag"); 4662 eptp &= ~EPTP_AD_FLAG; 4663 test_eptp_ad_bit(eptp, true); 4664 4665 eptp |= EPTP_AD_FLAG; 4666 test_eptp_ad_bit(eptp, false); 4667 } 4668 4669 /* 4670 * Reserved bits [11:7] and [63:N] 4671 */ 4672 for (i = 0; i < 32; i++) { 4673 if (i == 0) 4674 ctrl = true; 4675 else 4676 ctrl = false; 4677 4678 eptp = (eptp & 4679 ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)) | 4680 (i << EPTP_RESERV_BITS_SHIFT); 4681 vmcs_write(EPTP, eptp); 4682 report_prefix_pushf("Enable-EPT enabled; reserved bits [11:7] %lu", 4683 (eptp >> EPTP_RESERV_BITS_SHIFT) & 4684 EPTP_RESERV_BITS_MASK); 4685 test_vmx_controls(ctrl, false); 4686 report_prefix_pop(); 4687 } 4688 4689 eptp = (eptp & ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)); 4690 4691 maxphysaddr = cpuid_maxphyaddr(); 4692 for (i = 0; i < (63 - maxphysaddr + 1); i++) { 4693 resv_bits_mask |= 1ul << i; 4694 } 4695 4696 for (j = 0; j < (63 - maxphysaddr + 1); j++) { 4697 if (j == 0) 4698 ctrl = true; 4699 else 4700 ctrl = false; 4701 4702 eptp = (eptp & ~(resv_bits_mask << maxphysaddr)) | 4703 (j << maxphysaddr); 4704 vmcs_write(EPTP, eptp); 4705 report_prefix_pushf("Enable-EPT enabled; reserved bits [63:N] %lu", 4706 (eptp >> maxphysaddr) & resv_bits_mask); 4707 test_vmx_controls(ctrl, false); 4708 report_prefix_pop(); 4709 } 4710 4711 secondary &= ~(CPU_EPT | CPU_URG); 4712 vmcs_write(CPU_EXEC_CTRL1, secondary); 4713 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest disabled"); 4714 test_vmx_controls(true, false); 4715 report_prefix_pop(); 4716 4717 secondary |= CPU_URG; 4718 vmcs_write(CPU_EXEC_CTRL1, secondary); 4719 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest enabled"); 4720 test_vmx_controls(false, false); 4721 report_prefix_pop(); 4722 4723 secondary |= CPU_EPT; 4724 enable_ept(); 4725 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest enabled"); 4726 test_vmx_controls(true, false); 4727 report_prefix_pop(); 4728 4729 secondary &= ~CPU_URG; 4730 vmcs_write(CPU_EXEC_CTRL1, secondary); 4731 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest disabled"); 4732 test_vmx_controls(true, false); 4733 report_prefix_pop(); 4734 4735 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4736 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4737 vmcs_write(EPTP, eptp_saved); 4738 } 4739 4740 /* 4741 * If the 'enable PML' VM-execution control is 1, the 'enable EPT' 4742 * VM-execution control must also be 1. In addition, the PML address 4743 * must satisfy the following checks: 4744 * 4745 * * Bits 11:0 of the address must be 0. 4746 * * The address should not set any bits beyond the processor's 4747 * physical-address width. 4748 * 4749 * [Intel SDM] 4750 */ 4751 static void test_pml(void) 4752 { 4753 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4754 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4755 u32 primary = primary_saved; 4756 u32 secondary = secondary_saved; 4757 4758 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4759 (ctrl_cpu_rev[1].clr & CPU_EPT) && (ctrl_cpu_rev[1].clr & CPU_PML))) { 4760 test_skip("\"Secondary execution\" control or \"enable EPT\" control or \"enable PML\" control is not supported !"); 4761 return; 4762 } 4763 4764 primary |= CPU_SECONDARY; 4765 vmcs_write(CPU_EXEC_CTRL0, primary); 4766 secondary &= ~(CPU_PML | CPU_EPT); 4767 vmcs_write(CPU_EXEC_CTRL1, secondary); 4768 report_prefix_pushf("enable-PML disabled, enable-EPT disabled"); 4769 test_vmx_controls(true, false); 4770 report_prefix_pop(); 4771 4772 secondary |= CPU_PML; 4773 vmcs_write(CPU_EXEC_CTRL1, secondary); 4774 report_prefix_pushf("enable-PML enabled, enable-EPT disabled"); 4775 test_vmx_controls(false, false); 4776 report_prefix_pop(); 4777 4778 secondary |= CPU_EPT; 4779 enable_ept(); 4780 report_prefix_pushf("enable-PML enabled, enable-EPT enabled"); 4781 test_vmx_controls(true, false); 4782 report_prefix_pop(); 4783 4784 secondary &= ~CPU_PML; 4785 vmcs_write(CPU_EXEC_CTRL1, secondary); 4786 report_prefix_pushf("enable-PML disabled, enable EPT enabled"); 4787 test_vmx_controls(true, false); 4788 report_prefix_pop(); 4789 4790 test_vmcs_addr_reference(CPU_PML, PMLADDR, "PML address", "PML", 4791 PAGE_SIZE, false, false); 4792 4793 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4794 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4795 } 4796 4797 /* 4798 * If the "activate VMX-preemption timer" VM-execution control is 0, the 4799 * the "save VMX-preemption timer value" VM-exit control must also be 0. 4800 * 4801 * [Intel SDM] 4802 */ 4803 static void test_vmx_preemption_timer(void) 4804 { 4805 u32 saved_pin = vmcs_read(PIN_CONTROLS); 4806 u32 saved_exit = vmcs_read(EXI_CONTROLS); 4807 u32 pin = saved_pin; 4808 u32 exit = saved_exit; 4809 4810 if (!((ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) || 4811 (ctrl_pin_rev.clr & PIN_PREEMPT))) { 4812 printf("\"Save-VMX-preemption-timer\" control and/or \"Enable-VMX-preemption-timer\" control is not supported\n"); 4813 return; 4814 } 4815 4816 pin |= PIN_PREEMPT; 4817 vmcs_write(PIN_CONTROLS, pin); 4818 exit &= ~EXI_SAVE_PREEMPT; 4819 vmcs_write(EXI_CONTROLS, exit); 4820 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer disabled"); 4821 test_vmx_controls(true, false); 4822 report_prefix_pop(); 4823 4824 exit |= EXI_SAVE_PREEMPT; 4825 vmcs_write(EXI_CONTROLS, exit); 4826 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer enabled"); 4827 test_vmx_controls(true, false); 4828 report_prefix_pop(); 4829 4830 pin &= ~PIN_PREEMPT; 4831 vmcs_write(PIN_CONTROLS, pin); 4832 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer enabled"); 4833 test_vmx_controls(false, false); 4834 report_prefix_pop(); 4835 4836 exit &= ~EXI_SAVE_PREEMPT; 4837 vmcs_write(EXI_CONTROLS, exit); 4838 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer disabled"); 4839 test_vmx_controls(true, false); 4840 report_prefix_pop(); 4841 4842 vmcs_write(PIN_CONTROLS, saved_pin); 4843 vmcs_write(EXI_CONTROLS, saved_exit); 4844 } 4845 4846 /* 4847 * Tests for VM-execution control fields 4848 */ 4849 static void test_vm_execution_ctls(void) 4850 { 4851 test_pin_based_ctls(); 4852 test_primary_processor_based_ctls(); 4853 test_secondary_processor_based_ctls(); 4854 test_cr3_targets(); 4855 test_io_bitmaps(); 4856 test_msr_bitmap(); 4857 test_apic_ctls(); 4858 test_tpr_threshold(); 4859 test_nmi_ctrls(); 4860 test_pml(); 4861 test_vpid(); 4862 test_ept_eptp(); 4863 test_vmx_preemption_timer(); 4864 } 4865 4866 /* 4867 * The following checks are performed for the VM-entry MSR-load address if 4868 * the VM-entry MSR-load count field is non-zero: 4869 * 4870 * - The lower 4 bits of the VM-entry MSR-load address must be 0. 4871 * The address should not set any bits beyond the processor’s 4872 * physical-address width. 4873 * 4874 * - The address of the last byte in the VM-entry MSR-load area 4875 * should not set any bits beyond the processor’s physical-address 4876 * width. The address of this last byte is VM-entry MSR-load address 4877 * + (MSR count * 16) - 1. (The arithmetic used for the computation 4878 * uses more bits than the processor’s physical-address width.) 4879 * 4880 * 4881 * [Intel SDM] 4882 */ 4883 static void test_entry_msr_load(void) 4884 { 4885 entry_msr_load = alloc_page(); 4886 u64 tmp; 4887 u32 entry_msr_ld_cnt = 1; 4888 int i; 4889 u32 addr_len = 64; 4890 4891 vmcs_write(ENT_MSR_LD_CNT, entry_msr_ld_cnt); 4892 4893 /* Check first 4 bits of VM-entry MSR-load address */ 4894 for (i = 0; i < 4; i++) { 4895 tmp = (u64)entry_msr_load | 1ull << i; 4896 vmcs_write(ENTER_MSR_LD_ADDR, tmp); 4897 report_prefix_pushf("VM-entry MSR-load addr [4:0] %lx", 4898 tmp & 0xf); 4899 test_vmx_controls(false, false); 4900 report_prefix_pop(); 4901 } 4902 4903 if (basic.val & (1ul << 48)) 4904 addr_len = 32; 4905 4906 test_vmcs_addr_values("VM-entry-MSR-load address", 4907 ENTER_MSR_LD_ADDR, 16, false, false, 4908 4, addr_len - 1); 4909 4910 /* 4911 * Check last byte of VM-entry MSR-load address 4912 */ 4913 entry_msr_load = (struct vmx_msr_entry *)((u64)entry_msr_load & ~0xf); 4914 4915 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 4916 i < 64; i++) { 4917 tmp = ((u64)entry_msr_load + entry_msr_ld_cnt * 16 - 1) | 4918 1ul << i; 4919 vmcs_write(ENTER_MSR_LD_ADDR, 4920 tmp - (entry_msr_ld_cnt * 16 - 1)); 4921 test_vmx_controls(false, false); 4922 } 4923 4924 vmcs_write(ENT_MSR_LD_CNT, 2); 4925 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 4926 test_vmx_controls(false, false); 4927 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 4928 test_vmx_controls(true, false); 4929 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 4930 test_vmx_controls(true, false); 4931 } 4932 4933 /* 4934 * Tests for VM-entry control fields 4935 */ 4936 static void test_vm_entry_ctls(void) 4937 { 4938 test_invalid_event_injection(); 4939 test_entry_msr_load(); 4940 } 4941 4942 /* 4943 * The following checks are performed for the VM-exit MSR-store address if 4944 * the VM-exit MSR-store count field is non-zero: 4945 * 4946 * - The lower 4 bits of the VM-exit MSR-store address must be 0. 4947 * The address should not set any bits beyond the processor’s 4948 * physical-address width. 4949 * 4950 * - The address of the last byte in the VM-exit MSR-store area 4951 * should not set any bits beyond the processor’s physical-address 4952 * width. The address of this last byte is VM-exit MSR-store address 4953 * + (MSR count * 16) - 1. (The arithmetic used for the computation 4954 * uses more bits than the processor’s physical-address width.) 4955 * 4956 * If IA32_VMX_BASIC[48] is read as 1, neither address should set any bits 4957 * in the range 63:32. 4958 * 4959 * [Intel SDM] 4960 */ 4961 static void test_exit_msr_store(void) 4962 { 4963 exit_msr_store = alloc_page(); 4964 u64 tmp; 4965 u32 exit_msr_st_cnt = 1; 4966 int i; 4967 u32 addr_len = 64; 4968 4969 vmcs_write(EXI_MSR_ST_CNT, exit_msr_st_cnt); 4970 4971 /* Check first 4 bits of VM-exit MSR-store address */ 4972 for (i = 0; i < 4; i++) { 4973 tmp = (u64)exit_msr_store | 1ull << i; 4974 vmcs_write(EXIT_MSR_ST_ADDR, tmp); 4975 report_prefix_pushf("VM-exit MSR-store addr [4:0] %lx", 4976 tmp & 0xf); 4977 test_vmx_controls(false, false); 4978 report_prefix_pop(); 4979 } 4980 4981 if (basic.val & (1ul << 48)) 4982 addr_len = 32; 4983 4984 test_vmcs_addr_values("VM-exit-MSR-store address", 4985 EXIT_MSR_ST_ADDR, 16, false, false, 4986 4, addr_len - 1); 4987 4988 /* 4989 * Check last byte of VM-exit MSR-store address 4990 */ 4991 exit_msr_store = (struct vmx_msr_entry *)((u64)exit_msr_store & ~0xf); 4992 4993 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 4994 i < 64; i++) { 4995 tmp = ((u64)exit_msr_store + exit_msr_st_cnt * 16 - 1) | 4996 1ul << i; 4997 vmcs_write(EXIT_MSR_ST_ADDR, 4998 tmp - (exit_msr_st_cnt * 16 - 1)); 4999 test_vmx_controls(false, false); 5000 } 5001 5002 vmcs_write(EXI_MSR_ST_CNT, 2); 5003 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 5004 test_vmx_controls(false, false); 5005 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 5006 test_vmx_controls(true, false); 5007 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 5008 test_vmx_controls(true, false); 5009 } 5010 5011 /* 5012 * Tests for VM-exit controls 5013 */ 5014 static void test_vm_exit_ctls(void) 5015 { 5016 test_exit_msr_store(); 5017 } 5018 5019 /* 5020 * Check that the virtual CPU checks all of the VMX controls as 5021 * documented in the Intel SDM. 5022 */ 5023 static void vmx_controls_test(void) 5024 { 5025 /* 5026 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 5027 * fail due to invalid guest state, should we make it that 5028 * far. 5029 */ 5030 vmcs_write(GUEST_RFLAGS, 0); 5031 5032 test_vm_execution_ctls(); 5033 test_vm_entry_ctls(); 5034 test_vm_exit_ctls(); 5035 } 5036 5037 static bool valid_vmcs_for_vmentry(void) 5038 { 5039 struct vmcs *current_vmcs = NULL; 5040 5041 if (vmcs_save(¤t_vmcs)) 5042 return false; 5043 5044 return current_vmcs && !current_vmcs->hdr.shadow_vmcs; 5045 } 5046 5047 static void try_vmentry_in_movss_shadow(void) 5048 { 5049 u32 vm_inst_err; 5050 u32 flags; 5051 bool early_failure = false; 5052 u32 expected_flags = X86_EFLAGS_FIXED; 5053 bool valid_vmcs = valid_vmcs_for_vmentry(); 5054 5055 expected_flags |= valid_vmcs ? X86_EFLAGS_ZF : X86_EFLAGS_CF; 5056 5057 /* 5058 * Indirectly set VM_INST_ERR to 12 ("VMREAD/VMWRITE from/to 5059 * unsupported VMCS component"). 5060 */ 5061 vmcs_write(~0u, 0); 5062 5063 __asm__ __volatile__ ("mov %[host_rsp], %%edx;" 5064 "vmwrite %%rsp, %%rdx;" 5065 "mov 0f, %%rax;" 5066 "mov %[host_rip], %%edx;" 5067 "vmwrite %%rax, %%rdx;" 5068 "mov $-1, %%ah;" 5069 "sahf;" 5070 "mov %%ss, %%ax;" 5071 "mov %%ax, %%ss;" 5072 "vmlaunch;" 5073 "mov $1, %[early_failure];" 5074 "0: lahf;" 5075 "movzbl %%ah, %[flags]" 5076 : [early_failure] "+r" (early_failure), 5077 [flags] "=&a" (flags) 5078 : [host_rsp] "i" (HOST_RSP), 5079 [host_rip] "i" (HOST_RIP) 5080 : "rdx", "cc", "memory"); 5081 vm_inst_err = vmcs_read(VMX_INST_ERROR); 5082 5083 report("Early VM-entry failure", early_failure); 5084 report("RFLAGS[8:0] is %x (actual %x)", flags == expected_flags, 5085 expected_flags, flags); 5086 if (valid_vmcs) 5087 report("VM-instruction error is %d (actual %d)", 5088 vm_inst_err == VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, 5089 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, vm_inst_err); 5090 } 5091 5092 static void vmentry_movss_shadow_test(void) 5093 { 5094 struct vmcs *orig_vmcs; 5095 5096 TEST_ASSERT(!vmcs_save(&orig_vmcs)); 5097 5098 /* 5099 * Set the launched flag on the current VMCS to verify the correct 5100 * error priority, below. 5101 */ 5102 test_set_guest(v2_null_test_guest); 5103 enter_guest(); 5104 5105 /* 5106 * With bit 1 of the guest's RFLAGS clear, VM-entry should 5107 * fail due to invalid guest state (if we make it that far). 5108 */ 5109 vmcs_write(GUEST_RFLAGS, 0); 5110 5111 /* 5112 * "VM entry with events blocked by MOV SS" takes precedence over 5113 * "VMLAUNCH with non-clear VMCS." 5114 */ 5115 report_prefix_push("valid current-VMCS"); 5116 try_vmentry_in_movss_shadow(); 5117 report_prefix_pop(); 5118 5119 /* 5120 * VMfailInvalid takes precedence over "VM entry with events 5121 * blocked by MOV SS." 5122 */ 5123 TEST_ASSERT(!vmcs_clear(orig_vmcs)); 5124 report_prefix_push("no current-VMCS"); 5125 try_vmentry_in_movss_shadow(); 5126 report_prefix_pop(); 5127 5128 TEST_ASSERT(!make_vmcs_current(orig_vmcs)); 5129 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 5130 } 5131 5132 #define X86_FEATURE_PCID (1 << 17) 5133 #define X86_FEATURE_MCE (1 << 7) 5134 5135 static int write_cr4_checking(unsigned long val) 5136 { 5137 asm volatile(ASM_TRY("1f") 5138 "mov %0, %%cr4\n\t" 5139 "1:": : "r" (val)); 5140 return exception_vector(); 5141 } 5142 5143 static void vmx_cr_load_test(void) 5144 { 5145 struct cpuid _cpuid = cpuid(1); 5146 unsigned long cr4 = read_cr4(), cr3 = read_cr3(); 5147 5148 if (!(_cpuid.c & X86_FEATURE_PCID)) { 5149 report_skip("PCID not detected"); 5150 return; 5151 } 5152 if (!(_cpuid.d & X86_FEATURE_MCE)) { 5153 report_skip("MCE not detected"); 5154 return; 5155 } 5156 5157 TEST_ASSERT(!(cr4 & (X86_CR4_PCIDE | X86_CR4_MCE))); 5158 TEST_ASSERT(!(cr3 & X86_CR3_PCID_MASK)); 5159 5160 /* Enable PCID for L1. */ 5161 cr4 |= X86_CR4_PCIDE; 5162 cr3 |= 0x1; 5163 TEST_ASSERT(!write_cr4_checking(cr4)); 5164 write_cr3(cr3); 5165 5166 test_set_guest(v2_null_test_guest); 5167 vmcs_write(HOST_CR4, cr4); 5168 vmcs_write(HOST_CR3, cr3); 5169 enter_guest(); 5170 5171 /* 5172 * No exception is expected. 5173 * 5174 * NB. KVM loads the last guest write to CR4 into CR4 read 5175 * shadow. In order to trigger an exit to KVM, we can set a 5176 * bit that was zero in the above CR4 write and is owned by 5177 * KVM. We choose to set CR4.MCE, which shall have no side 5178 * effect because normally no guest MCE (e.g., as the result 5179 * of bad memory) would happen during this test. 5180 */ 5181 TEST_ASSERT(!write_cr4_checking(cr4 | X86_CR4_MCE)); 5182 5183 /* Cleanup L1 state: disable PCID. */ 5184 write_cr3(cr3 & ~X86_CR3_PCID_MASK); 5185 TEST_ASSERT(!write_cr4_checking(cr4 & ~X86_CR4_PCIDE)); 5186 } 5187 5188 static void vmx_nm_test_guest(void) 5189 { 5190 write_cr0(read_cr0() | X86_CR0_TS); 5191 asm volatile("fnop"); 5192 } 5193 5194 static void check_nm_exit(const char *test) 5195 { 5196 u32 reason = vmcs_read(EXI_REASON); 5197 u32 intr_info = vmcs_read(EXI_INTR_INFO); 5198 const u32 expected = INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 5199 NM_VECTOR; 5200 5201 report("%s", reason == VMX_EXC_NMI && intr_info == expected, test); 5202 } 5203 5204 /* 5205 * This test checks that: 5206 * 5207 * (a) If L2 launches with CR0.TS clear, but later sets CR0.TS, then 5208 * a subsequent #NM VM-exit is reflected to L1. 5209 * 5210 * (b) If L2 launches with CR0.TS clear and CR0.EM set, then a 5211 * subsequent #NM VM-exit is reflected to L1. 5212 */ 5213 static void vmx_nm_test(void) 5214 { 5215 unsigned long cr0 = read_cr0(); 5216 5217 test_set_guest(vmx_nm_test_guest); 5218 5219 /* 5220 * L1 wants to intercept #NM exceptions encountered in L2. 5221 */ 5222 vmcs_write(EXC_BITMAP, 1 << NM_VECTOR); 5223 5224 /* 5225 * Launch L2 with CR0.TS clear, but don't claim host ownership of 5226 * any CR0 bits. L2 will set CR0.TS and then try to execute fnop, 5227 * which will raise #NM. L0 should reflect the #NM VM-exit to L1. 5228 */ 5229 vmcs_write(CR0_MASK, 0); 5230 vmcs_write(GUEST_CR0, cr0 & ~X86_CR0_TS); 5231 enter_guest(); 5232 check_nm_exit("fnop with CR0.TS set in L2 triggers #NM VM-exit to L1"); 5233 5234 /* 5235 * Re-enter L2 at the fnop instruction, with CR0.TS clear but 5236 * CR0.EM set. The fnop will still raise #NM, and L0 should 5237 * reflect the #NM VM-exit to L1. 5238 */ 5239 vmcs_write(GUEST_CR0, (cr0 & ~X86_CR0_TS) | X86_CR0_EM); 5240 enter_guest(); 5241 check_nm_exit("fnop with CR0.EM set in L2 triggers #NM VM-exit to L1"); 5242 5243 /* 5244 * Re-enter L2 at the fnop instruction, with both CR0.TS and 5245 * CR0.EM clear. There will be no #NM, and the L2 guest should 5246 * exit normally. 5247 */ 5248 vmcs_write(GUEST_CR0, cr0 & ~(X86_CR0_TS | X86_CR0_EM)); 5249 enter_guest(); 5250 } 5251 5252 bool vmx_pending_event_ipi_fired; 5253 static void vmx_pending_event_ipi_isr(isr_regs_t *regs) 5254 { 5255 vmx_pending_event_ipi_fired = true; 5256 eoi(); 5257 } 5258 5259 bool vmx_pending_event_guest_run; 5260 static void vmx_pending_event_guest(void) 5261 { 5262 vmcall(); 5263 vmx_pending_event_guest_run = true; 5264 } 5265 5266 static void vmx_pending_event_test_core(bool guest_hlt) 5267 { 5268 int ipi_vector = 0xf1; 5269 5270 vmx_pending_event_ipi_fired = false; 5271 handle_irq(ipi_vector, vmx_pending_event_ipi_isr); 5272 5273 vmx_pending_event_guest_run = false; 5274 test_set_guest(vmx_pending_event_guest); 5275 5276 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 5277 5278 enter_guest(); 5279 skip_exit_vmcall(); 5280 5281 if (guest_hlt) 5282 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 5283 5284 irq_disable(); 5285 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | 5286 APIC_DM_FIXED | ipi_vector, 5287 0); 5288 5289 enter_guest(); 5290 5291 assert_exit_reason(VMX_EXTINT); 5292 report("Guest did not run before host received IPI", 5293 !vmx_pending_event_guest_run); 5294 5295 irq_enable(); 5296 asm volatile ("nop"); 5297 irq_disable(); 5298 report("Got pending interrupt after IRQ enabled", 5299 vmx_pending_event_ipi_fired); 5300 5301 if (guest_hlt) 5302 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 5303 5304 enter_guest(); 5305 report("Guest finished running when no interrupt", 5306 vmx_pending_event_guest_run); 5307 } 5308 5309 static void vmx_pending_event_test(void) 5310 { 5311 vmx_pending_event_test_core(false); 5312 } 5313 5314 static void vmx_pending_event_hlt_test(void) 5315 { 5316 vmx_pending_event_test_core(true); 5317 } 5318 5319 static int vmx_window_test_ud_count; 5320 5321 static void vmx_window_test_ud_handler(struct ex_regs *regs) 5322 { 5323 vmx_window_test_ud_count++; 5324 } 5325 5326 static void vmx_nmi_window_test_guest(void) 5327 { 5328 handle_exception(UD_VECTOR, vmx_window_test_ud_handler); 5329 5330 asm volatile("vmcall\n\t" 5331 "nop\n\t"); 5332 5333 handle_exception(UD_VECTOR, NULL); 5334 } 5335 5336 static void verify_nmi_window_exit(u64 rip) 5337 { 5338 u32 exit_reason = vmcs_read(EXI_REASON); 5339 5340 report("Exit reason (%d) is 'NMI window'", 5341 exit_reason == VMX_NMI_WINDOW, exit_reason); 5342 report("RIP (%#lx) is %#lx", vmcs_read(GUEST_RIP) == rip, 5343 vmcs_read(GUEST_RIP), rip); 5344 report("Activity state (%ld) is 'ACTIVE'", 5345 vmcs_read(GUEST_ACTV_STATE) == ACTV_ACTIVE, 5346 vmcs_read(GUEST_ACTV_STATE)); 5347 } 5348 5349 static void vmx_nmi_window_test(void) 5350 { 5351 u64 nop_addr; 5352 void *ud_fault_addr = get_idt_addr(&boot_idt[UD_VECTOR]); 5353 5354 if (!(ctrl_pin_rev.clr & PIN_VIRT_NMI)) { 5355 report_skip("CPU does not support the \"Virtual NMIs\" VM-execution control."); 5356 return; 5357 } 5358 5359 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 5360 report_skip("CPU does not support the \"NMI-window exiting\" VM-execution control."); 5361 return; 5362 } 5363 5364 vmx_window_test_ud_count = 0; 5365 5366 report_prefix_push("NMI-window"); 5367 test_set_guest(vmx_nmi_window_test_guest); 5368 vmcs_set_bits(PIN_CONTROLS, PIN_VIRT_NMI); 5369 enter_guest(); 5370 skip_exit_vmcall(); 5371 nop_addr = vmcs_read(GUEST_RIP); 5372 5373 /* 5374 * Ask for "NMI-window exiting," and expect an immediate VM-exit. 5375 * RIP will not advance. 5376 */ 5377 report_prefix_push("active, no blocking"); 5378 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 5379 enter_guest(); 5380 verify_nmi_window_exit(nop_addr); 5381 report_prefix_pop(); 5382 5383 /* 5384 * Ask for "NMI-window exiting" in a MOV-SS shadow, and expect 5385 * a VM-exit on the next instruction after the nop. (The nop 5386 * is one byte.) 5387 */ 5388 report_prefix_push("active, blocking by MOV-SS"); 5389 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 5390 enter_guest(); 5391 verify_nmi_window_exit(nop_addr + 1); 5392 report_prefix_pop(); 5393 5394 /* 5395 * Ask for "NMI-window exiting" (with event injection), and 5396 * expect a VM-exit after the event is injected. (RIP should 5397 * be at the address specified in the IDT entry for #UD.) 5398 */ 5399 report_prefix_push("active, no blocking, injecting #UD"); 5400 vmcs_write(ENT_INTR_INFO, 5401 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | UD_VECTOR); 5402 enter_guest(); 5403 verify_nmi_window_exit((u64)ud_fault_addr); 5404 report_prefix_pop(); 5405 5406 /* 5407 * Ask for "NMI-window exiting" with NMI blocking, and expect 5408 * a VM-exit after the next IRET (i.e. after the #UD handler 5409 * returns). So, RIP should be back at one byte past the nop. 5410 */ 5411 report_prefix_push("active, blocking by NMI"); 5412 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_NMI); 5413 enter_guest(); 5414 verify_nmi_window_exit(nop_addr + 1); 5415 report("#UD handler executed once (actual %d times)", 5416 vmx_window_test_ud_count == 1, 5417 vmx_window_test_ud_count); 5418 report_prefix_pop(); 5419 5420 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 5421 report_skip("CPU does not support activity state HLT."); 5422 } else { 5423 /* 5424 * Ask for "NMI-window exiting" when entering activity 5425 * state HLT, and expect an immediate VM-exit. RIP is 5426 * still one byte past the nop. 5427 */ 5428 report_prefix_push("halted, no blocking"); 5429 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 5430 enter_guest(); 5431 verify_nmi_window_exit(nop_addr + 1); 5432 report_prefix_pop(); 5433 5434 /* 5435 * Ask for "NMI-window exiting" when entering activity 5436 * state HLT (with event injection), and expect a 5437 * VM-exit after the event is injected. (RIP should be 5438 * at the address specified in the IDT entry for #UD.) 5439 */ 5440 report_prefix_push("halted, no blocking, injecting #UD"); 5441 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 5442 vmcs_write(ENT_INTR_INFO, 5443 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 5444 UD_VECTOR); 5445 enter_guest(); 5446 verify_nmi_window_exit((u64)ud_fault_addr); 5447 report_prefix_pop(); 5448 } 5449 5450 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 5451 enter_guest(); 5452 report_prefix_pop(); 5453 } 5454 5455 static void vmx_intr_window_test_guest(void) 5456 { 5457 handle_exception(UD_VECTOR, vmx_window_test_ud_handler); 5458 5459 /* 5460 * The two consecutive STIs are to ensure that only the first 5461 * one has a shadow. Note that NOP and STI are one byte 5462 * instructions. 5463 */ 5464 asm volatile("vmcall\n\t" 5465 "nop\n\t" 5466 "sti\n\t" 5467 "sti\n\t"); 5468 5469 handle_exception(UD_VECTOR, NULL); 5470 } 5471 5472 static void verify_intr_window_exit(u64 rip) 5473 { 5474 u32 exit_reason = vmcs_read(EXI_REASON); 5475 5476 report("Exit reason (%d) is 'interrupt window'", 5477 exit_reason == VMX_INTR_WINDOW, exit_reason); 5478 report("RIP (%#lx) is %#lx", vmcs_read(GUEST_RIP) == rip, 5479 vmcs_read(GUEST_RIP), rip); 5480 report("Activity state (%ld) is 'ACTIVE'", 5481 vmcs_read(GUEST_ACTV_STATE) == ACTV_ACTIVE, 5482 vmcs_read(GUEST_ACTV_STATE)); 5483 } 5484 5485 static void vmx_intr_window_test(void) 5486 { 5487 u64 vmcall_addr; 5488 u64 nop_addr; 5489 unsigned int orig_ud_gate_type; 5490 void *ud_fault_addr = get_idt_addr(&boot_idt[UD_VECTOR]); 5491 5492 if (!(ctrl_cpu_rev[0].clr & CPU_INTR_WINDOW)) { 5493 report_skip("CPU does not support the \"interrupt-window exiting\" VM-execution control."); 5494 return; 5495 } 5496 5497 /* 5498 * Change the IDT entry for #UD from interrupt gate to trap gate, 5499 * so that it won't clear RFLAGS.IF. We don't want interrupts to 5500 * be disabled after vectoring a #UD. 5501 */ 5502 orig_ud_gate_type = boot_idt[UD_VECTOR].type; 5503 boot_idt[UD_VECTOR].type = 15; 5504 5505 report_prefix_push("interrupt-window"); 5506 test_set_guest(vmx_intr_window_test_guest); 5507 enter_guest(); 5508 assert_exit_reason(VMX_VMCALL); 5509 vmcall_addr = vmcs_read(GUEST_RIP); 5510 5511 /* 5512 * Ask for "interrupt-window exiting" with RFLAGS.IF set and 5513 * no blocking; expect an immediate VM-exit. Note that we have 5514 * not advanced past the vmcall instruction yet, so RIP should 5515 * point to the vmcall instruction. 5516 */ 5517 report_prefix_push("active, no blocking, RFLAGS.IF=1"); 5518 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 5519 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_IF); 5520 enter_guest(); 5521 verify_intr_window_exit(vmcall_addr); 5522 report_prefix_pop(); 5523 5524 /* 5525 * Ask for "interrupt-window exiting" (with event injection) 5526 * with RFLAGS.IF set and no blocking; expect a VM-exit after 5527 * the event is injected. That is, RIP should should be at the 5528 * address specified in the IDT entry for #UD. 5529 */ 5530 report_prefix_push("active, no blocking, RFLAGS.IF=1, injecting #UD"); 5531 vmcs_write(ENT_INTR_INFO, 5532 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | UD_VECTOR); 5533 vmcall_addr = vmcs_read(GUEST_RIP); 5534 enter_guest(); 5535 verify_intr_window_exit((u64)ud_fault_addr); 5536 report_prefix_pop(); 5537 5538 /* 5539 * Let the L2 guest run through the IRET, back to the VMCALL. 5540 * We have to clear the "interrupt-window exiting" 5541 * VM-execution control, or it would just keep causing 5542 * VM-exits. Then, advance past the VMCALL and set the 5543 * "interrupt-window exiting" VM-execution control again. 5544 */ 5545 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 5546 enter_guest(); 5547 skip_exit_vmcall(); 5548 nop_addr = vmcs_read(GUEST_RIP); 5549 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 5550 5551 /* 5552 * Ask for "interrupt-window exiting" in a MOV-SS shadow with 5553 * RFLAGS.IF set, and expect a VM-exit on the next 5554 * instruction. (NOP is one byte.) 5555 */ 5556 report_prefix_push("active, blocking by MOV-SS, RFLAGS.IF=1"); 5557 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 5558 enter_guest(); 5559 verify_intr_window_exit(nop_addr + 1); 5560 report_prefix_pop(); 5561 5562 /* 5563 * Back up to the NOP and ask for "interrupt-window exiting" 5564 * in an STI shadow with RFLAGS.IF set, and expect a VM-exit 5565 * on the next instruction. (NOP is one byte.) 5566 */ 5567 report_prefix_push("active, blocking by STI, RFLAGS.IF=1"); 5568 vmcs_write(GUEST_RIP, nop_addr); 5569 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_STI); 5570 enter_guest(); 5571 verify_intr_window_exit(nop_addr + 1); 5572 report_prefix_pop(); 5573 5574 /* 5575 * Ask for "interrupt-window exiting" with RFLAGS.IF clear, 5576 * and expect a VM-exit on the instruction following the STI 5577 * shadow. Only the first STI (which is one byte past the NOP) 5578 * should have a shadow. The second STI (which is two bytes 5579 * past the NOP) has no shadow. Therefore, the interrupt 5580 * window opens at three bytes past the NOP. 5581 */ 5582 report_prefix_push("active, RFLAGS.IF = 0"); 5583 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 5584 enter_guest(); 5585 verify_intr_window_exit(nop_addr + 3); 5586 report_prefix_pop(); 5587 5588 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 5589 report_skip("CPU does not support activity state HLT."); 5590 } else { 5591 /* 5592 * Ask for "interrupt-window exiting" when entering 5593 * activity state HLT, and expect an immediate 5594 * VM-exit. RIP is still three bytes past the nop. 5595 */ 5596 report_prefix_push("halted, no blocking"); 5597 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 5598 enter_guest(); 5599 verify_intr_window_exit(nop_addr + 3); 5600 report_prefix_pop(); 5601 5602 /* 5603 * Ask for "interrupt-window exiting" when entering 5604 * activity state HLT (with event injection), and 5605 * expect a VM-exit after the event is injected. That 5606 * is, RIP should should be at the address specified 5607 * in the IDT entry for #UD. 5608 */ 5609 report_prefix_push("halted, no blocking, injecting #UD"); 5610 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 5611 vmcs_write(ENT_INTR_INFO, 5612 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 5613 UD_VECTOR); 5614 enter_guest(); 5615 verify_intr_window_exit((u64)ud_fault_addr); 5616 report_prefix_pop(); 5617 } 5618 5619 boot_idt[UD_VECTOR].type = orig_ud_gate_type; 5620 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 5621 enter_guest(); 5622 report_prefix_pop(); 5623 } 5624 5625 #define GUEST_TSC_OFFSET (1u << 30) 5626 5627 static u64 guest_tsc; 5628 5629 static void vmx_store_tsc_test_guest(void) 5630 { 5631 guest_tsc = rdtsc(); 5632 } 5633 5634 /* 5635 * This test ensures that when IA32_TSC is in the VM-exit MSR-store 5636 * list, the value saved is not subject to the TSC offset that is 5637 * applied to RDTSC/RDTSCP/RDMSR(IA32_TSC) in guest execution. 5638 */ 5639 static void vmx_store_tsc_test(void) 5640 { 5641 struct vmx_msr_entry msr_entry = { .index = MSR_IA32_TSC }; 5642 u64 low, high; 5643 5644 if (!(ctrl_cpu_rev[0].clr & CPU_USE_TSC_OFFSET)) { 5645 report_skip("'Use TSC offsetting' not supported"); 5646 return; 5647 } 5648 5649 test_set_guest(vmx_store_tsc_test_guest); 5650 5651 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_USE_TSC_OFFSET); 5652 vmcs_write(EXI_MSR_ST_CNT, 1); 5653 vmcs_write(EXIT_MSR_ST_ADDR, virt_to_phys(&msr_entry)); 5654 vmcs_write(TSC_OFFSET, GUEST_TSC_OFFSET); 5655 5656 low = rdtsc(); 5657 enter_guest(); 5658 high = rdtsc(); 5659 5660 report("RDTSC value in the guest (%lu) is in range [%lu, %lu]", 5661 low + GUEST_TSC_OFFSET <= guest_tsc && 5662 guest_tsc <= high + GUEST_TSC_OFFSET, 5663 guest_tsc, low + GUEST_TSC_OFFSET, high + GUEST_TSC_OFFSET); 5664 report("IA32_TSC value saved in the VM-exit MSR-store list (%lu) is in range [%lu, %lu]", 5665 low <= msr_entry.value && msr_entry.value <= high, 5666 msr_entry.value, low, high); 5667 } 5668 5669 static void vmx_db_test_guest(void) 5670 { 5671 /* 5672 * For a hardware generated single-step #DB. 5673 */ 5674 asm volatile("vmcall;" 5675 "nop;" 5676 ".Lpost_nop:"); 5677 /* 5678 * ...in a MOVSS shadow, with pending debug exceptions. 5679 */ 5680 asm volatile("vmcall;" 5681 "nop;" 5682 ".Lpost_movss_nop:"); 5683 /* 5684 * For an L0 synthesized single-step #DB. (L0 intercepts WBINVD and 5685 * emulates it in software.) 5686 */ 5687 asm volatile("vmcall;" 5688 "wbinvd;" 5689 ".Lpost_wbinvd:"); 5690 /* 5691 * ...in a MOVSS shadow, with pending debug exceptions. 5692 */ 5693 asm volatile("vmcall;" 5694 "wbinvd;" 5695 ".Lpost_movss_wbinvd:"); 5696 /* 5697 * For a hardware generated single-step #DB in a transactional region. 5698 */ 5699 asm volatile("vmcall;" 5700 ".Lxbegin: xbegin .Lskip_rtm;" 5701 "xend;" 5702 ".Lskip_rtm:"); 5703 } 5704 5705 /* 5706 * Clear the pending debug exceptions and RFLAGS.TF and re-enter 5707 * L2. No #DB is delivered and L2 continues to the next point of 5708 * interest. 5709 */ 5710 static void dismiss_db(void) 5711 { 5712 vmcs_write(GUEST_PENDING_DEBUG, 0); 5713 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 5714 enter_guest(); 5715 } 5716 5717 /* 5718 * Check a variety of VMCS fields relevant to an intercepted #DB exception. 5719 * Then throw away the #DB exception and resume L2. 5720 */ 5721 static void check_db_exit(bool xfail_qual, bool xfail_dr6, bool xfail_pdbg, 5722 void *expected_rip, u64 expected_exit_qual, 5723 u64 expected_dr6) 5724 { 5725 u32 reason = vmcs_read(EXI_REASON); 5726 u32 intr_info = vmcs_read(EXI_INTR_INFO); 5727 u64 exit_qual = vmcs_read(EXI_QUALIFICATION); 5728 u64 guest_rip = vmcs_read(GUEST_RIP); 5729 u64 guest_pending_dbg = vmcs_read(GUEST_PENDING_DEBUG); 5730 u64 dr6 = read_dr6(); 5731 const u32 expected_intr_info = INTR_INFO_VALID_MASK | 5732 INTR_TYPE_HARD_EXCEPTION | DB_VECTOR; 5733 5734 report("Expected #DB VM-exit", 5735 reason == VMX_EXC_NMI && intr_info == expected_intr_info); 5736 report("Expected RIP %p (actual %lx)", (u64)expected_rip == guest_rip, 5737 expected_rip, guest_rip); 5738 report_xfail("Expected pending debug exceptions 0 (actual %lx)", 5739 xfail_pdbg, 0 == guest_pending_dbg, guest_pending_dbg); 5740 report_xfail("Expected exit qualification %lx (actual %lx)", xfail_qual, 5741 expected_exit_qual == exit_qual, 5742 expected_exit_qual, exit_qual); 5743 report_xfail("Expected DR6 %lx (actual %lx)", xfail_dr6, 5744 expected_dr6 == dr6, expected_dr6, dr6); 5745 dismiss_db(); 5746 } 5747 5748 /* 5749 * Assuming the guest has just exited on a VMCALL instruction, skip 5750 * over the vmcall, and set the guest's RFLAGS.TF in the VMCS. If 5751 * pending debug exceptions are non-zero, set the VMCS up as if the 5752 * previous instruction was a MOVSS that generated the indicated 5753 * pending debug exceptions. Then enter L2. 5754 */ 5755 static void single_step_guest(const char *test_name, u64 starting_dr6, 5756 u64 pending_debug_exceptions) 5757 { 5758 printf("\n%s\n", test_name); 5759 skip_exit_vmcall(); 5760 write_dr6(starting_dr6); 5761 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_TF); 5762 if (pending_debug_exceptions) { 5763 vmcs_write(GUEST_PENDING_DEBUG, pending_debug_exceptions); 5764 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 5765 } 5766 enter_guest(); 5767 } 5768 5769 /* 5770 * When L1 intercepts #DB, verify that a single-step trap clears 5771 * pending debug exceptions, populates the exit qualification field 5772 * properly, and that DR6 is not prematurely clobbered. In a 5773 * (simulated) MOVSS shadow, make sure that the pending debug 5774 * exception bits are properly accumulated into the exit qualification 5775 * field. 5776 */ 5777 static void vmx_db_test(void) 5778 { 5779 /* 5780 * We are going to set a few arbitrary bits in DR6 to verify that 5781 * (a) DR6 is not modified by an intercepted #DB, and 5782 * (b) stale bits in DR6 (DR6.BD, in particular) don't leak into 5783 * the exit qualification field for a subsequent #DB exception. 5784 */ 5785 const u64 starting_dr6 = DR6_RESERVED | BIT(13) | DR_TRAP3 | DR_TRAP1; 5786 extern char post_nop asm(".Lpost_nop"); 5787 extern char post_movss_nop asm(".Lpost_movss_nop"); 5788 extern char post_wbinvd asm(".Lpost_wbinvd"); 5789 extern char post_movss_wbinvd asm(".Lpost_movss_wbinvd"); 5790 extern char xbegin asm(".Lxbegin"); 5791 extern char skip_rtm asm(".Lskip_rtm"); 5792 5793 /* 5794 * L1 wants to intercept #DB exceptions encountered in L2. 5795 */ 5796 vmcs_write(EXC_BITMAP, BIT(DB_VECTOR)); 5797 5798 /* 5799 * Start L2 and run it up to the first point of interest. 5800 */ 5801 test_set_guest(vmx_db_test_guest); 5802 enter_guest(); 5803 5804 /* 5805 * Hardware-delivered #DB trap for single-step sets the 5806 * standard that L0 has to follow for emulated instructions. 5807 */ 5808 single_step_guest("Hardware delivered single-step", starting_dr6, 0); 5809 check_db_exit(false, false, false, &post_nop, DR_STEP, starting_dr6); 5810 5811 /* 5812 * Hardware-delivered #DB trap for single-step in MOVSS shadow 5813 * also sets the standard that L0 has to follow for emulated 5814 * instructions. Here, we establish the VMCS pending debug 5815 * exceptions to indicate that the simulated MOVSS triggered a 5816 * data breakpoint as well as the single-step trap. 5817 */ 5818 single_step_guest("Hardware delivered single-step in MOVSS shadow", 5819 starting_dr6, BIT(12) | DR_STEP | DR_TRAP0 ); 5820 check_db_exit(false, false, false, &post_movss_nop, DR_STEP | DR_TRAP0, 5821 starting_dr6); 5822 5823 /* 5824 * L0 synthesized #DB trap for single-step is buggy, because 5825 * kvm (a) clobbers DR6 too early, and (b) tries its best to 5826 * reconstitute the exit qualification from the prematurely 5827 * modified DR6, but fails miserably. 5828 */ 5829 single_step_guest("Software synthesized single-step", starting_dr6, 0); 5830 check_db_exit(true, true, false, &post_wbinvd, DR_STEP, starting_dr6); 5831 5832 /* 5833 * L0 synthesized #DB trap for single-step in MOVSS shadow is 5834 * even worse, because L0 also leaves the pending debug 5835 * exceptions in the VMCS instead of accumulating them into 5836 * the exit qualification field for the #DB exception. 5837 */ 5838 single_step_guest("Software synthesized single-step in MOVSS shadow", 5839 starting_dr6, BIT(12) | DR_STEP | DR_TRAP0); 5840 check_db_exit(true, true, true, &post_movss_wbinvd, DR_STEP | DR_TRAP0, 5841 starting_dr6); 5842 5843 /* 5844 * Optional RTM test for hardware that supports RTM, to 5845 * demonstrate that the current volume 3 of the SDM 5846 * (325384-067US), table 27-1 is incorrect. Bit 16 of the exit 5847 * qualification for debug exceptions is not reserved. It is 5848 * set to 1 if a debug exception (#DB) or a breakpoint 5849 * exception (#BP) occurs inside an RTM region while advanced 5850 * debugging of RTM transactional regions is enabled. 5851 */ 5852 if (cpuid(7).b & BIT(11)) { 5853 vmcs_write(ENT_CONTROLS, 5854 vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 5855 /* 5856 * Set DR7.RTM[bit 11] and IA32_DEBUGCTL.RTM[bit 15] 5857 * in the guest to enable advanced debugging of RTM 5858 * transactional regions. 5859 */ 5860 vmcs_write(GUEST_DR7, BIT(11)); 5861 vmcs_write(GUEST_DEBUGCTL, BIT(15)); 5862 single_step_guest("Hardware delivered single-step in " 5863 "transactional region", starting_dr6, 0); 5864 check_db_exit(false, false, false, &xbegin, BIT(16), 5865 starting_dr6); 5866 } else { 5867 vmcs_write(GUEST_RIP, (u64)&skip_rtm); 5868 enter_guest(); 5869 } 5870 } 5871 5872 static bool cpu_has_apicv(void) 5873 { 5874 return ((ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT) && 5875 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 5876 (ctrl_pin_rev.clr & PIN_POST_INTR)); 5877 } 5878 5879 static void enable_vid(void) 5880 { 5881 void *virtual_apic_page; 5882 5883 assert(cpu_has_apicv()); 5884 5885 disable_intercept_for_x2apic_msrs(); 5886 5887 virtual_apic_page = alloc_page(); 5888 vmcs_write(APIC_VIRT_ADDR, (u64)virtual_apic_page); 5889 5890 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 5891 5892 vmcs_write(EOI_EXIT_BITMAP0, 0x0); 5893 vmcs_write(EOI_EXIT_BITMAP1, 0x0); 5894 vmcs_write(EOI_EXIT_BITMAP2, 0x0); 5895 vmcs_write(EOI_EXIT_BITMAP3, 0x0); 5896 5897 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY | CPU_TPR_SHADOW); 5898 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_VINTD | CPU_VIRT_X2APIC); 5899 } 5900 5901 static void trigger_ioapic_scan_thread(void *data) 5902 { 5903 /* Wait until other CPU entered L2 */ 5904 while (vmx_get_test_stage() != 1) 5905 ; 5906 5907 /* Trigger ioapic scan */ 5908 ioapic_set_redir(0xf, 0x79, TRIGGER_LEVEL); 5909 vmx_set_test_stage(2); 5910 } 5911 5912 static void irq_79_handler_guest(isr_regs_t *regs) 5913 { 5914 eoi(); 5915 5916 /* L1 expects vmexit on VMX_VMCALL and not VMX_EOI_INDUCED */ 5917 vmcall(); 5918 } 5919 5920 /* 5921 * Constant for num of busy-loop iterations after which 5922 * a timer interrupt should have happened in host 5923 */ 5924 #define TIMER_INTERRUPT_DELAY 100000000 5925 5926 static void vmx_eoi_bitmap_ioapic_scan_test_guest(void) 5927 { 5928 handle_irq(0x79, irq_79_handler_guest); 5929 irq_enable(); 5930 5931 /* Signal to L1 CPU to trigger ioapic scan */ 5932 vmx_set_test_stage(1); 5933 /* Wait until L1 CPU to trigger ioapic scan */ 5934 while (vmx_get_test_stage() != 2) 5935 ; 5936 5937 /* 5938 * Wait for L0 timer interrupt to be raised while we run in L2 5939 * such that L0 will process the IOAPIC scan request before 5940 * resuming L2 5941 */ 5942 delay(TIMER_INTERRUPT_DELAY); 5943 5944 asm volatile ("int $0x79"); 5945 } 5946 5947 static void vmx_eoi_bitmap_ioapic_scan_test(void) 5948 { 5949 if (!cpu_has_apicv() || (cpu_count() < 2)) { 5950 report_skip(__func__); 5951 return; 5952 } 5953 5954 enable_vid(); 5955 5956 on_cpu_async(1, trigger_ioapic_scan_thread, NULL); 5957 test_set_guest(vmx_eoi_bitmap_ioapic_scan_test_guest); 5958 5959 /* 5960 * Launch L2. 5961 * We expect the exit reason to be VMX_VMCALL (and not EOI INDUCED). 5962 * In case the reason isn't VMX_VMCALL, the asserion inside 5963 * skip_exit_vmcall() will fail. 5964 */ 5965 enter_guest(); 5966 skip_exit_vmcall(); 5967 5968 /* Let L2 finish */ 5969 enter_guest(); 5970 report(__func__, 1); 5971 } 5972 5973 #define HLT_WITH_RVI_VECTOR (0xf1) 5974 5975 bool vmx_hlt_with_rvi_guest_isr_fired; 5976 static void vmx_hlt_with_rvi_guest_isr(isr_regs_t *regs) 5977 { 5978 vmx_hlt_with_rvi_guest_isr_fired = true; 5979 eoi(); 5980 } 5981 5982 static void vmx_hlt_with_rvi_guest(void) 5983 { 5984 handle_irq(HLT_WITH_RVI_VECTOR, vmx_hlt_with_rvi_guest_isr); 5985 5986 irq_enable(); 5987 asm volatile ("nop"); 5988 5989 vmcall(); 5990 } 5991 5992 static void vmx_hlt_with_rvi_test(void) 5993 { 5994 if (!cpu_has_apicv()) { 5995 report_skip(__func__); 5996 return; 5997 } 5998 5999 enable_vid(); 6000 6001 vmx_hlt_with_rvi_guest_isr_fired = false; 6002 test_set_guest(vmx_hlt_with_rvi_guest); 6003 6004 enter_guest(); 6005 skip_exit_vmcall(); 6006 6007 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 6008 vmcs_write(GUEST_INT_STATUS, HLT_WITH_RVI_VECTOR); 6009 enter_guest(); 6010 6011 report("Interrupt raised in guest", vmx_hlt_with_rvi_guest_isr_fired); 6012 } 6013 6014 static void set_irq_line_thread(void *data) 6015 { 6016 /* Wait until other CPU entered L2 */ 6017 while (vmx_get_test_stage() != 1) 6018 ; 6019 6020 /* Set irq-line 0xf to raise vector 0x78 for vCPU 0 */ 6021 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 6022 vmx_set_test_stage(2); 6023 } 6024 6025 static bool irq_78_handler_vmcall_before_eoi; 6026 static void irq_78_handler_guest(isr_regs_t *regs) 6027 { 6028 set_irq_line(0xf, 0); 6029 if (irq_78_handler_vmcall_before_eoi) 6030 vmcall(); 6031 eoi(); 6032 vmcall(); 6033 } 6034 6035 static void vmx_apic_passthrough_guest(void) 6036 { 6037 handle_irq(0x78, irq_78_handler_guest); 6038 irq_enable(); 6039 6040 /* If requested, wait for other CPU to trigger ioapic scan */ 6041 if (vmx_get_test_stage() < 1) { 6042 vmx_set_test_stage(1); 6043 while (vmx_get_test_stage() != 2) 6044 ; 6045 } 6046 6047 set_irq_line(0xf, 1); 6048 } 6049 6050 static void vmx_apic_passthrough(bool set_irq_line_from_thread) 6051 { 6052 if (set_irq_line_from_thread && (cpu_count() < 2)) { 6053 report_skip(__func__); 6054 return; 6055 } 6056 6057 u64 cpu_ctrl_0 = CPU_SECONDARY; 6058 u64 cpu_ctrl_1 = 0; 6059 6060 disable_intercept_for_x2apic_msrs(); 6061 6062 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 6063 6064 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 6065 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 6066 6067 if (set_irq_line_from_thread) { 6068 irq_78_handler_vmcall_before_eoi = false; 6069 on_cpu_async(1, set_irq_line_thread, NULL); 6070 } else { 6071 irq_78_handler_vmcall_before_eoi = true; 6072 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 6073 vmx_set_test_stage(2); 6074 } 6075 test_set_guest(vmx_apic_passthrough_guest); 6076 6077 if (irq_78_handler_vmcall_before_eoi) { 6078 /* Before EOI remote_irr should still be set */ 6079 enter_guest(); 6080 skip_exit_vmcall(); 6081 TEST_ASSERT_EQ_MSG(1, (int)ioapic_read_redir(0xf).remote_irr, 6082 "IOAPIC pass-through: remote_irr=1 before EOI"); 6083 } 6084 6085 /* After EOI remote_irr should be cleared */ 6086 enter_guest(); 6087 skip_exit_vmcall(); 6088 TEST_ASSERT_EQ_MSG(0, (int)ioapic_read_redir(0xf).remote_irr, 6089 "IOAPIC pass-through: remote_irr=0 after EOI"); 6090 6091 /* Let L2 finish */ 6092 enter_guest(); 6093 report(__func__, 1); 6094 } 6095 6096 static void vmx_apic_passthrough_test(void) 6097 { 6098 vmx_apic_passthrough(false); 6099 } 6100 6101 static void vmx_apic_passthrough_thread_test(void) 6102 { 6103 vmx_apic_passthrough(true); 6104 } 6105 6106 enum vmcs_access { 6107 ACCESS_VMREAD, 6108 ACCESS_VMWRITE, 6109 ACCESS_NONE, 6110 }; 6111 6112 struct vmcs_shadow_test_common { 6113 enum vmcs_access op; 6114 enum Reason reason; 6115 u64 field; 6116 u64 value; 6117 u64 flags; 6118 u64 time; 6119 } l1_l2_common; 6120 6121 static inline u64 vmread_flags(u64 field, u64 *val) 6122 { 6123 u64 flags; 6124 6125 asm volatile ("vmread %2, %1; pushf; pop %0" 6126 : "=r" (flags), "=rm" (*val) : "r" (field) : "cc"); 6127 return flags & X86_EFLAGS_ALU; 6128 } 6129 6130 static inline u64 vmwrite_flags(u64 field, u64 val) 6131 { 6132 u64 flags; 6133 6134 asm volatile ("vmwrite %1, %2; pushf; pop %0" 6135 : "=r"(flags) : "rm" (val), "r" (field) : "cc"); 6136 return flags & X86_EFLAGS_ALU; 6137 } 6138 6139 static void vmx_vmcs_shadow_test_guest(void) 6140 { 6141 struct vmcs_shadow_test_common *c = &l1_l2_common; 6142 u64 start; 6143 6144 while (c->op != ACCESS_NONE) { 6145 start = rdtsc(); 6146 switch (c->op) { 6147 default: 6148 c->flags = -1ull; 6149 break; 6150 case ACCESS_VMREAD: 6151 c->flags = vmread_flags(c->field, &c->value); 6152 break; 6153 case ACCESS_VMWRITE: 6154 c->flags = vmwrite_flags(c->field, 0); 6155 break; 6156 } 6157 c->time = rdtsc() - start; 6158 vmcall(); 6159 } 6160 } 6161 6162 static u64 vmread_from_shadow(u64 field) 6163 { 6164 struct vmcs *primary; 6165 struct vmcs *shadow; 6166 u64 value; 6167 6168 TEST_ASSERT(!vmcs_save(&primary)); 6169 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 6170 TEST_ASSERT(!make_vmcs_current(shadow)); 6171 value = vmcs_read(field); 6172 TEST_ASSERT(!make_vmcs_current(primary)); 6173 return value; 6174 } 6175 6176 static u64 vmwrite_to_shadow(u64 field, u64 value) 6177 { 6178 struct vmcs *primary; 6179 struct vmcs *shadow; 6180 6181 TEST_ASSERT(!vmcs_save(&primary)); 6182 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 6183 TEST_ASSERT(!make_vmcs_current(shadow)); 6184 vmcs_write(field, value); 6185 value = vmcs_read(field); 6186 TEST_ASSERT(!make_vmcs_current(primary)); 6187 return value; 6188 } 6189 6190 static void vmcs_shadow_test_access(u8 *bitmap[2], enum vmcs_access access) 6191 { 6192 struct vmcs_shadow_test_common *c = &l1_l2_common; 6193 6194 c->op = access; 6195 vmcs_write(VMX_INST_ERROR, 0); 6196 enter_guest(); 6197 c->reason = vmcs_read(EXI_REASON) & 0xffff; 6198 if (c->reason != VMX_VMCALL) { 6199 skip_exit_insn(); 6200 enter_guest(); 6201 } 6202 skip_exit_vmcall(); 6203 } 6204 6205 static void vmcs_shadow_test_field(u8 *bitmap[2], u64 field) 6206 { 6207 struct vmcs_shadow_test_common *c = &l1_l2_common; 6208 struct vmcs *shadow; 6209 u64 value; 6210 uintptr_t flags[2]; 6211 bool good_shadow; 6212 u32 vmx_inst_error; 6213 6214 report_prefix_pushf("field %lx", field); 6215 c->field = field; 6216 6217 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 6218 if (shadow != (struct vmcs *)-1ull) { 6219 flags[ACCESS_VMREAD] = vmread_flags(field, &value); 6220 flags[ACCESS_VMWRITE] = vmwrite_flags(field, value); 6221 good_shadow = !flags[ACCESS_VMREAD] && !flags[ACCESS_VMWRITE]; 6222 } else { 6223 /* 6224 * When VMCS link pointer is -1ull, VMWRITE/VMREAD on 6225 * shadowed-fields should fail with setting RFLAGS.CF. 6226 */ 6227 flags[ACCESS_VMREAD] = X86_EFLAGS_CF; 6228 flags[ACCESS_VMWRITE] = X86_EFLAGS_CF; 6229 good_shadow = false; 6230 } 6231 6232 /* Intercept both VMREAD and VMWRITE. */ 6233 report_prefix_push("no VMREAD/VMWRITE permission"); 6234 /* VMWRITE/VMREAD done on reserved-bit should always intercept */ 6235 if (!(field >> VMCS_FIELD_RESERVED_SHIFT)) { 6236 set_bit(field, bitmap[ACCESS_VMREAD]); 6237 set_bit(field, bitmap[ACCESS_VMWRITE]); 6238 } 6239 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 6240 report("not shadowed for VMWRITE", c->reason == VMX_VMWRITE); 6241 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 6242 report("not shadowed for VMREAD", c->reason == VMX_VMREAD); 6243 report_prefix_pop(); 6244 6245 if (field >> VMCS_FIELD_RESERVED_SHIFT) 6246 goto out; 6247 6248 /* Permit shadowed VMREAD. */ 6249 report_prefix_push("VMREAD permission only"); 6250 clear_bit(field, bitmap[ACCESS_VMREAD]); 6251 set_bit(field, bitmap[ACCESS_VMWRITE]); 6252 if (good_shadow) 6253 value = vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 6254 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 6255 report("not shadowed for VMWRITE", c->reason == VMX_VMWRITE); 6256 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 6257 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 6258 report("shadowed for VMREAD (in %ld cycles)", c->reason == VMX_VMCALL, 6259 c->time); 6260 report("ALU flags after VMREAD (%lx) are as expected (%lx)", 6261 c->flags == flags[ACCESS_VMREAD], 6262 c->flags, flags[ACCESS_VMREAD]); 6263 if (good_shadow) 6264 report("value read from shadow (%lx) is as expected (%lx)", 6265 c->value == value, c->value, value); 6266 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 6267 report("VMX_INST_ERROR (%d) is as expected (%d)", 6268 vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 6269 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 6270 report_prefix_pop(); 6271 6272 /* Permit shadowed VMWRITE. */ 6273 report_prefix_push("VMWRITE permission only"); 6274 set_bit(field, bitmap[ACCESS_VMREAD]); 6275 clear_bit(field, bitmap[ACCESS_VMWRITE]); 6276 if (good_shadow) 6277 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 6278 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 6279 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 6280 report("shadowed for VMWRITE (in %ld cycles)", c->reason == VMX_VMCALL, 6281 c->time); 6282 report("ALU flags after VMWRITE (%lx) are as expected (%lx)", 6283 c->flags == flags[ACCESS_VMREAD], 6284 c->flags, flags[ACCESS_VMREAD]); 6285 if (good_shadow) { 6286 value = vmread_from_shadow(field); 6287 report("shadow VMCS value (%lx) is as expected (%lx)", 6288 value == 0, value, 0ul); 6289 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 6290 report("VMX_INST_ERROR (%d) is as expected (%d)", 6291 vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 6292 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 6293 } 6294 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 6295 report("not shadowed for VMREAD", c->reason == VMX_VMREAD); 6296 report_prefix_pop(); 6297 6298 /* Permit shadowed VMREAD and VMWRITE. */ 6299 report_prefix_push("VMREAD and VMWRITE permission"); 6300 clear_bit(field, bitmap[ACCESS_VMREAD]); 6301 clear_bit(field, bitmap[ACCESS_VMWRITE]); 6302 if (good_shadow) 6303 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 6304 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 6305 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 6306 report("shadowed for VMWRITE (in %ld cycles)", c->reason == VMX_VMCALL, 6307 c->time); 6308 report("ALU flags after VMWRITE (%lx) are as expected (%lx)", 6309 c->flags == flags[ACCESS_VMREAD], 6310 c->flags, flags[ACCESS_VMREAD]); 6311 if (good_shadow) { 6312 value = vmread_from_shadow(field); 6313 report("shadow VMCS value (%lx) is as expected (%lx)", 6314 value == 0, value, 0ul); 6315 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 6316 report("VMX_INST_ERROR (%d) is as expected (%d)", 6317 vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 6318 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 6319 } 6320 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 6321 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 6322 report("shadowed for VMREAD (in %ld cycles)", c->reason == VMX_VMCALL, 6323 c->time); 6324 report("ALU flags after VMREAD (%lx) are as expected (%lx)", 6325 c->flags == flags[ACCESS_VMREAD], 6326 c->flags, flags[ACCESS_VMREAD]); 6327 if (good_shadow) 6328 report("value read from shadow (%lx) is as expected (%lx)", 6329 c->value == 0, c->value, 0ul); 6330 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 6331 report("VMX_INST_ERROR (%d) is as expected (%d)", 6332 vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 6333 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 6334 report_prefix_pop(); 6335 6336 out: 6337 report_prefix_pop(); 6338 } 6339 6340 static void vmx_vmcs_shadow_test_body(u8 *bitmap[2]) 6341 { 6342 unsigned base; 6343 unsigned index; 6344 unsigned bit; 6345 unsigned highest_index = rdmsr(MSR_IA32_VMX_VMCS_ENUM); 6346 6347 /* Run test on all possible valid VMCS fields */ 6348 for (base = 0; 6349 base < (1 << VMCS_FIELD_RESERVED_SHIFT); 6350 base += (1 << VMCS_FIELD_TYPE_SHIFT)) 6351 for (index = 0; index <= highest_index; index++) 6352 vmcs_shadow_test_field(bitmap, base + index); 6353 6354 /* 6355 * Run tests on some invalid VMCS fields 6356 * (Have reserved bit set). 6357 */ 6358 for (bit = VMCS_FIELD_RESERVED_SHIFT; bit < VMCS_FIELD_BIT_SIZE; bit++) 6359 vmcs_shadow_test_field(bitmap, (1ull << bit)); 6360 } 6361 6362 static void vmx_vmcs_shadow_test(void) 6363 { 6364 u8 *bitmap[2]; 6365 struct vmcs *shadow; 6366 6367 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 6368 printf("\t'Activate secondary controls' not supported.\n"); 6369 return; 6370 } 6371 6372 if (!(ctrl_cpu_rev[1].clr & CPU_SHADOW_VMCS)) { 6373 printf("\t'VMCS shadowing' not supported.\n"); 6374 return; 6375 } 6376 6377 if (!(rdmsr(MSR_IA32_VMX_MISC) & 6378 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS)) { 6379 printf("\tVMWRITE can't modify VM-exit information fields.\n"); 6380 return; 6381 } 6382 6383 test_set_guest(vmx_vmcs_shadow_test_guest); 6384 6385 bitmap[ACCESS_VMREAD] = alloc_page(); 6386 bitmap[ACCESS_VMWRITE] = alloc_page(); 6387 6388 vmcs_write(VMREAD_BITMAP, virt_to_phys(bitmap[ACCESS_VMREAD])); 6389 vmcs_write(VMWRITE_BITMAP, virt_to_phys(bitmap[ACCESS_VMWRITE])); 6390 6391 shadow = alloc_page(); 6392 shadow->hdr.revision_id = basic.revision; 6393 shadow->hdr.shadow_vmcs = 1; 6394 TEST_ASSERT(!vmcs_clear(shadow)); 6395 6396 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_RDTSC); 6397 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY); 6398 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_SHADOW_VMCS); 6399 6400 vmcs_write(VMCS_LINK_PTR, virt_to_phys(shadow)); 6401 report_prefix_push("valid link pointer"); 6402 vmx_vmcs_shadow_test_body(bitmap); 6403 report_prefix_pop(); 6404 6405 vmcs_write(VMCS_LINK_PTR, -1ull); 6406 report_prefix_push("invalid link pointer"); 6407 vmx_vmcs_shadow_test_body(bitmap); 6408 report_prefix_pop(); 6409 6410 l1_l2_common.op = ACCESS_NONE; 6411 enter_guest(); 6412 } 6413 6414 6415 6416 static int invalid_msr_init(struct vmcs *vmcs) 6417 { 6418 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 6419 printf("\tPreemption timer is not supported\n"); 6420 return VMX_TEST_EXIT; 6421 } 6422 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 6423 preempt_val = 10000000; 6424 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 6425 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 6426 6427 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 6428 printf("\tSave preemption value is not supported\n"); 6429 6430 vmcs_write(ENT_MSR_LD_CNT, 1); 6431 vmcs_write(ENTER_MSR_LD_ADDR, (u64)0x13370000); 6432 6433 return VMX_TEST_START; 6434 } 6435 6436 6437 static void invalid_msr_main(void) 6438 { 6439 report("Invalid MSR load", 0); 6440 } 6441 6442 static int invalid_msr_exit_handler(void) 6443 { 6444 report("Invalid MSR load", 0); 6445 print_vmexit_info(); 6446 return VMX_TEST_EXIT; 6447 } 6448 6449 static int invalid_msr_entry_failure(struct vmentry_failure *failure) 6450 { 6451 ulong reason; 6452 6453 reason = vmcs_read(EXI_REASON); 6454 report("Invalid MSR load", reason == (0x80000000u | VMX_FAIL_MSR)); 6455 return VMX_TEST_VMEXIT; 6456 } 6457 6458 6459 #define TEST(name) { #name, .v2 = name } 6460 6461 /* name/init/guest_main/exit_handler/syscall_handler/guest_regs */ 6462 struct vmx_test vmx_tests[] = { 6463 { "null", NULL, basic_guest_main, basic_exit_handler, NULL, {0} }, 6464 { "vmenter", NULL, vmenter_main, vmenter_exit_handler, NULL, {0} }, 6465 { "preemption timer", preemption_timer_init, preemption_timer_main, 6466 preemption_timer_exit_handler, NULL, {0} }, 6467 { "control field PAT", test_ctrl_pat_init, test_ctrl_pat_main, 6468 test_ctrl_pat_exit_handler, NULL, {0} }, 6469 { "control field EFER", test_ctrl_efer_init, test_ctrl_efer_main, 6470 test_ctrl_efer_exit_handler, NULL, {0} }, 6471 { "CR shadowing", NULL, cr_shadowing_main, 6472 cr_shadowing_exit_handler, NULL, {0} }, 6473 { "I/O bitmap", iobmp_init, iobmp_main, iobmp_exit_handler, 6474 NULL, {0} }, 6475 { "instruction intercept", insn_intercept_init, insn_intercept_main, 6476 insn_intercept_exit_handler, NULL, {0} }, 6477 { "EPT A/D disabled", ept_init, ept_main, ept_exit_handler, NULL, {0} }, 6478 { "EPT A/D enabled", eptad_init, eptad_main, eptad_exit_handler, NULL, {0} }, 6479 { "PML", pml_init, pml_main, pml_exit_handler, NULL, {0} }, 6480 { "VPID", vpid_init, vpid_main, vpid_exit_handler, NULL, {0} }, 6481 { "interrupt", interrupt_init, interrupt_main, 6482 interrupt_exit_handler, NULL, {0} }, 6483 { "debug controls", dbgctls_init, dbgctls_main, dbgctls_exit_handler, 6484 NULL, {0} }, 6485 { "MSR switch", msr_switch_init, msr_switch_main, 6486 msr_switch_exit_handler, NULL, {0}, msr_switch_entry_failure }, 6487 { "vmmcall", vmmcall_init, vmmcall_main, vmmcall_exit_handler, NULL, {0} }, 6488 { "disable RDTSCP", disable_rdtscp_init, disable_rdtscp_main, 6489 disable_rdtscp_exit_handler, NULL, {0} }, 6490 { "int3", int3_init, int3_guest_main, int3_exit_handler, NULL, {0} }, 6491 { "into", into_init, into_guest_main, into_exit_handler, NULL, {0} }, 6492 { "exit_monitor_from_l2_test", NULL, exit_monitor_from_l2_main, 6493 exit_monitor_from_l2_handler, NULL, {0} }, 6494 { "invalid_msr", invalid_msr_init, invalid_msr_main, 6495 invalid_msr_exit_handler, NULL, {0}, invalid_msr_entry_failure}, 6496 /* Basic V2 tests. */ 6497 TEST(v2_null_test), 6498 TEST(v2_multiple_entries_test), 6499 TEST(fixture_test_case1), 6500 TEST(fixture_test_case2), 6501 /* Opcode tests. */ 6502 TEST(invvpid_test_v2), 6503 /* VM-entry tests */ 6504 TEST(vmx_controls_test), 6505 TEST(vmentry_movss_shadow_test), 6506 /* APICv tests */ 6507 TEST(vmx_eoi_bitmap_ioapic_scan_test), 6508 TEST(vmx_hlt_with_rvi_test), 6509 /* APIC pass-through tests */ 6510 TEST(vmx_apic_passthrough_test), 6511 TEST(vmx_apic_passthrough_thread_test), 6512 /* VMCS Shadowing tests */ 6513 TEST(vmx_vmcs_shadow_test), 6514 /* Regression tests */ 6515 TEST(vmx_cr_load_test), 6516 TEST(vmx_nm_test), 6517 TEST(vmx_db_test), 6518 TEST(vmx_nmi_window_test), 6519 TEST(vmx_intr_window_test), 6520 TEST(vmx_pending_event_test), 6521 TEST(vmx_pending_event_hlt_test), 6522 TEST(vmx_store_tsc_test), 6523 /* EPT access tests. */ 6524 TEST(ept_access_test_not_present), 6525 TEST(ept_access_test_read_only), 6526 TEST(ept_access_test_write_only), 6527 TEST(ept_access_test_read_write), 6528 TEST(ept_access_test_execute_only), 6529 TEST(ept_access_test_read_execute), 6530 TEST(ept_access_test_write_execute), 6531 TEST(ept_access_test_read_write_execute), 6532 TEST(ept_access_test_reserved_bits), 6533 TEST(ept_access_test_ignored_bits), 6534 TEST(ept_access_test_paddr_not_present_ad_disabled), 6535 TEST(ept_access_test_paddr_not_present_ad_enabled), 6536 TEST(ept_access_test_paddr_read_only_ad_disabled), 6537 TEST(ept_access_test_paddr_read_only_ad_enabled), 6538 TEST(ept_access_test_paddr_read_write), 6539 TEST(ept_access_test_paddr_read_write_execute), 6540 TEST(ept_access_test_paddr_read_execute_ad_disabled), 6541 TEST(ept_access_test_paddr_read_execute_ad_enabled), 6542 TEST(ept_access_test_paddr_not_present_page_fault), 6543 TEST(ept_access_test_force_2m_page), 6544 { NULL, NULL, NULL, NULL, NULL, {0} }, 6545 }; 6546