1 /* 2 * All test cases of nested virtualization should be in this file 3 * 4 * Author : Arthur Chunqi Li <yzt356@gmail.com> 5 */ 6 #include "vmx.h" 7 #include "msr.h" 8 #include "processor.h" 9 #include "vm.h" 10 #include "fwcfg.h" 11 #include "isr.h" 12 #include "desc.h" 13 #include "apic.h" 14 #include "types.h" 15 16 #define NONCANONICAL 0xaaaaaaaaaaaaaaaaull 17 18 #define VPID_CAP_INVVPID_TYPES_SHIFT 40 19 20 u64 ia32_pat; 21 u64 ia32_efer; 22 void *io_bitmap_a, *io_bitmap_b; 23 u16 ioport; 24 25 unsigned long *pml4; 26 u64 eptp; 27 void *data_page1, *data_page2; 28 29 void *pml_log; 30 #define PML_INDEX 512 31 32 static inline unsigned ffs(unsigned x) 33 { 34 int pos = -1; 35 36 __asm__ __volatile__("bsf %1, %%eax; cmovnz %%eax, %0" 37 : "+r"(pos) : "rm"(x) : "eax"); 38 return pos + 1; 39 } 40 41 static inline void vmcall() 42 { 43 asm volatile("vmcall"); 44 } 45 46 void basic_guest_main() 47 { 48 report("Basic VMX test", 1); 49 } 50 51 int basic_exit_handler() 52 { 53 report("Basic VMX test", 0); 54 print_vmexit_info(); 55 return VMX_TEST_EXIT; 56 } 57 58 void vmenter_main() 59 { 60 u64 rax; 61 u64 rsp, resume_rsp; 62 63 report("test vmlaunch", 1); 64 65 asm volatile( 66 "mov %%rsp, %0\n\t" 67 "mov %3, %%rax\n\t" 68 "vmcall\n\t" 69 "mov %%rax, %1\n\t" 70 "mov %%rsp, %2\n\t" 71 : "=r"(rsp), "=r"(rax), "=r"(resume_rsp) 72 : "g"(0xABCD)); 73 report("test vmresume", (rax == 0xFFFF) && (rsp == resume_rsp)); 74 } 75 76 int vmenter_exit_handler() 77 { 78 u64 guest_rip; 79 ulong reason; 80 81 guest_rip = vmcs_read(GUEST_RIP); 82 reason = vmcs_read(EXI_REASON) & 0xff; 83 switch (reason) { 84 case VMX_VMCALL: 85 if (regs.rax != 0xABCD) { 86 report("test vmresume", 0); 87 return VMX_TEST_VMEXIT; 88 } 89 regs.rax = 0xFFFF; 90 vmcs_write(GUEST_RIP, guest_rip + 3); 91 return VMX_TEST_RESUME; 92 default: 93 report("test vmresume", 0); 94 print_vmexit_info(); 95 } 96 return VMX_TEST_VMEXIT; 97 } 98 99 u32 preempt_scale; 100 volatile unsigned long long tsc_val; 101 volatile u32 preempt_val; 102 u64 saved_rip; 103 104 int preemption_timer_init() 105 { 106 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 107 printf("\tPreemption timer is not supported\n"); 108 return VMX_TEST_EXIT; 109 } 110 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 111 preempt_val = 10000000; 112 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 113 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 114 115 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 116 printf("\tSave preemption value is not supported\n"); 117 118 return VMX_TEST_START; 119 } 120 121 void preemption_timer_main() 122 { 123 tsc_val = rdtsc(); 124 if (ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) { 125 vmx_set_test_stage(0); 126 vmcall(); 127 if (vmx_get_test_stage() == 1) 128 vmcall(); 129 } 130 vmx_set_test_stage(1); 131 while (vmx_get_test_stage() == 1) { 132 if (((rdtsc() - tsc_val) >> preempt_scale) 133 > 10 * preempt_val) { 134 vmx_set_test_stage(2); 135 vmcall(); 136 } 137 } 138 tsc_val = rdtsc(); 139 asm volatile ("hlt"); 140 vmcall(); 141 vmx_set_test_stage(5); 142 vmcall(); 143 } 144 145 int preemption_timer_exit_handler() 146 { 147 bool guest_halted; 148 u64 guest_rip; 149 ulong reason; 150 u32 insn_len; 151 u32 ctrl_exit; 152 153 guest_rip = vmcs_read(GUEST_RIP); 154 reason = vmcs_read(EXI_REASON) & 0xff; 155 insn_len = vmcs_read(EXI_INST_LEN); 156 switch (reason) { 157 case VMX_PREEMPT: 158 switch (vmx_get_test_stage()) { 159 case 1: 160 case 2: 161 report("busy-wait for preemption timer", 162 ((rdtsc() - tsc_val) >> preempt_scale) >= 163 preempt_val); 164 vmx_set_test_stage(3); 165 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 166 return VMX_TEST_RESUME; 167 case 3: 168 guest_halted = 169 (vmcs_read(GUEST_ACTV_STATE) == ACTV_HLT); 170 report("preemption timer during hlt", 171 ((rdtsc() - tsc_val) >> preempt_scale) >= 172 preempt_val && guest_halted); 173 vmx_set_test_stage(4); 174 vmcs_write(PIN_CONTROLS, 175 vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 176 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 177 return VMX_TEST_RESUME; 178 case 4: 179 report("preemption timer with 0 value", 180 saved_rip == guest_rip); 181 break; 182 default: 183 printf("Invalid stage.\n"); 184 print_vmexit_info(); 185 break; 186 } 187 break; 188 case VMX_VMCALL: 189 vmcs_write(GUEST_RIP, guest_rip + insn_len); 190 switch (vmx_get_test_stage()) { 191 case 0: 192 report("Keep preemption value", 193 vmcs_read(PREEMPT_TIMER_VALUE) == preempt_val); 194 vmx_set_test_stage(1); 195 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 196 ctrl_exit = (vmcs_read(EXI_CONTROLS) | 197 EXI_SAVE_PREEMPT) & ctrl_exit_rev.clr; 198 vmcs_write(EXI_CONTROLS, ctrl_exit); 199 return VMX_TEST_RESUME; 200 case 1: 201 report("Save preemption value", 202 vmcs_read(PREEMPT_TIMER_VALUE) < preempt_val); 203 return VMX_TEST_RESUME; 204 case 2: 205 report("busy-wait for preemption timer", 0); 206 vmx_set_test_stage(3); 207 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 208 return VMX_TEST_RESUME; 209 case 3: 210 report("preemption timer during hlt", 0); 211 vmx_set_test_stage(4); 212 /* fall through */ 213 case 4: 214 vmcs_write(PIN_CONTROLS, 215 vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 216 vmcs_write(PREEMPT_TIMER_VALUE, 0); 217 saved_rip = guest_rip + insn_len; 218 return VMX_TEST_RESUME; 219 case 5: 220 report("preemption timer with 0 value (vmcall stage 5)", 0); 221 break; 222 default: 223 // Should not reach here 224 printf("ERROR : unexpected stage, %d\n", 225 vmx_get_test_stage()); 226 print_vmexit_info(); 227 return VMX_TEST_VMEXIT; 228 } 229 break; 230 default: 231 printf("Unknown exit reason, %ld\n", reason); 232 print_vmexit_info(); 233 } 234 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 235 return VMX_TEST_VMEXIT; 236 } 237 238 void msr_bmp_init() 239 { 240 void *msr_bitmap; 241 u32 ctrl_cpu0; 242 243 msr_bitmap = alloc_page(); 244 memset(msr_bitmap, 0x0, PAGE_SIZE); 245 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 246 ctrl_cpu0 |= CPU_MSR_BITMAP; 247 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 248 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 249 } 250 251 static int test_ctrl_pat_init() 252 { 253 u64 ctrl_ent; 254 u64 ctrl_exi; 255 256 msr_bmp_init(); 257 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT) && 258 !(ctrl_exit_rev.clr & EXI_LOAD_PAT) && 259 !(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 260 printf("\tSave/load PAT is not supported\n"); 261 return 1; 262 } 263 264 ctrl_ent = vmcs_read(ENT_CONTROLS); 265 ctrl_exi = vmcs_read(EXI_CONTROLS); 266 ctrl_ent |= ctrl_enter_rev.clr & ENT_LOAD_PAT; 267 ctrl_exi |= ctrl_exit_rev.clr & (EXI_SAVE_PAT | EXI_LOAD_PAT); 268 vmcs_write(ENT_CONTROLS, ctrl_ent); 269 vmcs_write(EXI_CONTROLS, ctrl_exi); 270 ia32_pat = rdmsr(MSR_IA32_CR_PAT); 271 vmcs_write(GUEST_PAT, 0x0); 272 vmcs_write(HOST_PAT, ia32_pat); 273 return VMX_TEST_START; 274 } 275 276 static void test_ctrl_pat_main() 277 { 278 u64 guest_ia32_pat; 279 280 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 281 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) 282 printf("\tENT_LOAD_PAT is not supported.\n"); 283 else { 284 if (guest_ia32_pat != 0) { 285 report("Entry load PAT", 0); 286 return; 287 } 288 } 289 wrmsr(MSR_IA32_CR_PAT, 0x6); 290 vmcall(); 291 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 292 if (ctrl_enter_rev.clr & ENT_LOAD_PAT) 293 report("Entry load PAT", guest_ia32_pat == ia32_pat); 294 } 295 296 static int test_ctrl_pat_exit_handler() 297 { 298 u64 guest_rip; 299 ulong reason; 300 u64 guest_pat; 301 302 guest_rip = vmcs_read(GUEST_RIP); 303 reason = vmcs_read(EXI_REASON) & 0xff; 304 switch (reason) { 305 case VMX_VMCALL: 306 guest_pat = vmcs_read(GUEST_PAT); 307 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT)) { 308 printf("\tEXI_SAVE_PAT is not supported\n"); 309 vmcs_write(GUEST_PAT, 0x6); 310 } else { 311 report("Exit save PAT", guest_pat == 0x6); 312 } 313 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) 314 printf("\tEXI_LOAD_PAT is not supported\n"); 315 else 316 report("Exit load PAT", rdmsr(MSR_IA32_CR_PAT) == ia32_pat); 317 vmcs_write(GUEST_PAT, ia32_pat); 318 vmcs_write(GUEST_RIP, guest_rip + 3); 319 return VMX_TEST_RESUME; 320 default: 321 printf("ERROR : Undefined exit reason, reason = %ld.\n", reason); 322 break; 323 } 324 return VMX_TEST_VMEXIT; 325 } 326 327 static int test_ctrl_efer_init() 328 { 329 u64 ctrl_ent; 330 u64 ctrl_exi; 331 332 msr_bmp_init(); 333 ctrl_ent = vmcs_read(ENT_CONTROLS) | ENT_LOAD_EFER; 334 ctrl_exi = vmcs_read(EXI_CONTROLS) | EXI_SAVE_EFER | EXI_LOAD_EFER; 335 vmcs_write(ENT_CONTROLS, ctrl_ent & ctrl_enter_rev.clr); 336 vmcs_write(EXI_CONTROLS, ctrl_exi & ctrl_exit_rev.clr); 337 ia32_efer = rdmsr(MSR_EFER); 338 vmcs_write(GUEST_EFER, ia32_efer ^ EFER_NX); 339 vmcs_write(HOST_EFER, ia32_efer ^ EFER_NX); 340 return VMX_TEST_START; 341 } 342 343 static void test_ctrl_efer_main() 344 { 345 u64 guest_ia32_efer; 346 347 guest_ia32_efer = rdmsr(MSR_EFER); 348 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) 349 printf("\tENT_LOAD_EFER is not supported.\n"); 350 else { 351 if (guest_ia32_efer != (ia32_efer ^ EFER_NX)) { 352 report("Entry load EFER", 0); 353 return; 354 } 355 } 356 wrmsr(MSR_EFER, ia32_efer); 357 vmcall(); 358 guest_ia32_efer = rdmsr(MSR_EFER); 359 if (ctrl_enter_rev.clr & ENT_LOAD_EFER) 360 report("Entry load EFER", guest_ia32_efer == ia32_efer); 361 } 362 363 static int test_ctrl_efer_exit_handler() 364 { 365 u64 guest_rip; 366 ulong reason; 367 u64 guest_efer; 368 369 guest_rip = vmcs_read(GUEST_RIP); 370 reason = vmcs_read(EXI_REASON) & 0xff; 371 switch (reason) { 372 case VMX_VMCALL: 373 guest_efer = vmcs_read(GUEST_EFER); 374 if (!(ctrl_exit_rev.clr & EXI_SAVE_EFER)) { 375 printf("\tEXI_SAVE_EFER is not supported\n"); 376 vmcs_write(GUEST_EFER, ia32_efer); 377 } else { 378 report("Exit save EFER", guest_efer == ia32_efer); 379 } 380 if (!(ctrl_exit_rev.clr & EXI_LOAD_EFER)) { 381 printf("\tEXI_LOAD_EFER is not supported\n"); 382 wrmsr(MSR_EFER, ia32_efer ^ EFER_NX); 383 } else { 384 report("Exit load EFER", rdmsr(MSR_EFER) == (ia32_efer ^ EFER_NX)); 385 } 386 vmcs_write(GUEST_PAT, ia32_efer); 387 vmcs_write(GUEST_RIP, guest_rip + 3); 388 return VMX_TEST_RESUME; 389 default: 390 printf("ERROR : Undefined exit reason, reason = %ld.\n", reason); 391 break; 392 } 393 return VMX_TEST_VMEXIT; 394 } 395 396 u32 guest_cr0, guest_cr4; 397 398 static void cr_shadowing_main() 399 { 400 u32 cr0, cr4, tmp; 401 402 // Test read through 403 vmx_set_test_stage(0); 404 guest_cr0 = read_cr0(); 405 if (vmx_get_test_stage() == 1) 406 report("Read through CR0", 0); 407 else 408 vmcall(); 409 vmx_set_test_stage(1); 410 guest_cr4 = read_cr4(); 411 if (vmx_get_test_stage() == 2) 412 report("Read through CR4", 0); 413 else 414 vmcall(); 415 // Test write through 416 guest_cr0 = guest_cr0 ^ (X86_CR0_TS | X86_CR0_MP); 417 guest_cr4 = guest_cr4 ^ (X86_CR4_TSD | X86_CR4_DE); 418 vmx_set_test_stage(2); 419 write_cr0(guest_cr0); 420 if (vmx_get_test_stage() == 3) 421 report("Write throuth CR0", 0); 422 else 423 vmcall(); 424 vmx_set_test_stage(3); 425 write_cr4(guest_cr4); 426 if (vmx_get_test_stage() == 4) 427 report("Write through CR4", 0); 428 else 429 vmcall(); 430 // Test read shadow 431 vmx_set_test_stage(4); 432 vmcall(); 433 cr0 = read_cr0(); 434 if (vmx_get_test_stage() != 5) 435 report("Read shadowing CR0", cr0 == guest_cr0); 436 vmx_set_test_stage(5); 437 cr4 = read_cr4(); 438 if (vmx_get_test_stage() != 6) 439 report("Read shadowing CR4", cr4 == guest_cr4); 440 // Test write shadow (same value with shadow) 441 vmx_set_test_stage(6); 442 write_cr0(guest_cr0); 443 if (vmx_get_test_stage() == 7) 444 report("Write shadowing CR0 (same value with shadow)", 0); 445 else 446 vmcall(); 447 vmx_set_test_stage(7); 448 write_cr4(guest_cr4); 449 if (vmx_get_test_stage() == 8) 450 report("Write shadowing CR4 (same value with shadow)", 0); 451 else 452 vmcall(); 453 // Test write shadow (different value) 454 vmx_set_test_stage(8); 455 tmp = guest_cr0 ^ X86_CR0_TS; 456 asm volatile("mov %0, %%rsi\n\t" 457 "mov %%rsi, %%cr0\n\t" 458 ::"m"(tmp) 459 :"rsi", "memory", "cc"); 460 report("Write shadowing different X86_CR0_TS", vmx_get_test_stage() == 9); 461 vmx_set_test_stage(9); 462 tmp = guest_cr0 ^ X86_CR0_MP; 463 asm volatile("mov %0, %%rsi\n\t" 464 "mov %%rsi, %%cr0\n\t" 465 ::"m"(tmp) 466 :"rsi", "memory", "cc"); 467 report("Write shadowing different X86_CR0_MP", vmx_get_test_stage() == 10); 468 vmx_set_test_stage(10); 469 tmp = guest_cr4 ^ X86_CR4_TSD; 470 asm volatile("mov %0, %%rsi\n\t" 471 "mov %%rsi, %%cr4\n\t" 472 ::"m"(tmp) 473 :"rsi", "memory", "cc"); 474 report("Write shadowing different X86_CR4_TSD", vmx_get_test_stage() == 11); 475 vmx_set_test_stage(11); 476 tmp = guest_cr4 ^ X86_CR4_DE; 477 asm volatile("mov %0, %%rsi\n\t" 478 "mov %%rsi, %%cr4\n\t" 479 ::"m"(tmp) 480 :"rsi", "memory", "cc"); 481 report("Write shadowing different X86_CR4_DE", vmx_get_test_stage() == 12); 482 } 483 484 static int cr_shadowing_exit_handler() 485 { 486 u64 guest_rip; 487 ulong reason; 488 u32 insn_len; 489 u32 exit_qual; 490 491 guest_rip = vmcs_read(GUEST_RIP); 492 reason = vmcs_read(EXI_REASON) & 0xff; 493 insn_len = vmcs_read(EXI_INST_LEN); 494 exit_qual = vmcs_read(EXI_QUALIFICATION); 495 switch (reason) { 496 case VMX_VMCALL: 497 switch (vmx_get_test_stage()) { 498 case 0: 499 report("Read through CR0", guest_cr0 == vmcs_read(GUEST_CR0)); 500 break; 501 case 1: 502 report("Read through CR4", guest_cr4 == vmcs_read(GUEST_CR4)); 503 break; 504 case 2: 505 report("Write through CR0", guest_cr0 == vmcs_read(GUEST_CR0)); 506 break; 507 case 3: 508 report("Write through CR4", guest_cr4 == vmcs_read(GUEST_CR4)); 509 break; 510 case 4: 511 guest_cr0 = vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP); 512 guest_cr4 = vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE); 513 vmcs_write(CR0_MASK, X86_CR0_TS | X86_CR0_MP); 514 vmcs_write(CR0_READ_SHADOW, guest_cr0 & (X86_CR0_TS | X86_CR0_MP)); 515 vmcs_write(CR4_MASK, X86_CR4_TSD | X86_CR4_DE); 516 vmcs_write(CR4_READ_SHADOW, guest_cr4 & (X86_CR4_TSD | X86_CR4_DE)); 517 break; 518 case 6: 519 report("Write shadowing CR0 (same value)", 520 guest_cr0 == (vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP))); 521 break; 522 case 7: 523 report("Write shadowing CR4 (same value)", 524 guest_cr4 == (vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE))); 525 break; 526 default: 527 // Should not reach here 528 printf("ERROR : unexpected stage, %d\n", 529 vmx_get_test_stage()); 530 print_vmexit_info(); 531 return VMX_TEST_VMEXIT; 532 } 533 vmcs_write(GUEST_RIP, guest_rip + insn_len); 534 return VMX_TEST_RESUME; 535 case VMX_CR: 536 switch (vmx_get_test_stage()) { 537 case 4: 538 report("Read shadowing CR0", 0); 539 vmx_inc_test_stage(); 540 break; 541 case 5: 542 report("Read shadowing CR4", 0); 543 vmx_inc_test_stage(); 544 break; 545 case 6: 546 report("Write shadowing CR0 (same value)", 0); 547 vmx_inc_test_stage(); 548 break; 549 case 7: 550 report("Write shadowing CR4 (same value)", 0); 551 vmx_inc_test_stage(); 552 break; 553 case 8: 554 case 9: 555 // 0x600 encodes "mov %esi, %cr0" 556 if (exit_qual == 0x600) 557 vmx_inc_test_stage(); 558 break; 559 case 10: 560 case 11: 561 // 0x604 encodes "mov %esi, %cr4" 562 if (exit_qual == 0x604) 563 vmx_inc_test_stage(); 564 break; 565 default: 566 // Should not reach here 567 printf("ERROR : unexpected stage, %d\n", 568 vmx_get_test_stage()); 569 print_vmexit_info(); 570 return VMX_TEST_VMEXIT; 571 } 572 vmcs_write(GUEST_RIP, guest_rip + insn_len); 573 return VMX_TEST_RESUME; 574 default: 575 printf("Unknown exit reason, %ld\n", reason); 576 print_vmexit_info(); 577 } 578 return VMX_TEST_VMEXIT; 579 } 580 581 static int iobmp_init() 582 { 583 u32 ctrl_cpu0; 584 585 io_bitmap_a = alloc_page(); 586 io_bitmap_b = alloc_page(); 587 memset(io_bitmap_a, 0x0, PAGE_SIZE); 588 memset(io_bitmap_b, 0x0, PAGE_SIZE); 589 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 590 ctrl_cpu0 |= CPU_IO_BITMAP; 591 ctrl_cpu0 &= (~CPU_IO); 592 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 593 vmcs_write(IO_BITMAP_A, (u64)io_bitmap_a); 594 vmcs_write(IO_BITMAP_B, (u64)io_bitmap_b); 595 return VMX_TEST_START; 596 } 597 598 static void iobmp_main() 599 { 600 // stage 0, test IO pass 601 vmx_set_test_stage(0); 602 inb(0x5000); 603 outb(0x0, 0x5000); 604 report("I/O bitmap - I/O pass", vmx_get_test_stage() == 0); 605 // test IO width, in/out 606 ((u8 *)io_bitmap_a)[0] = 0xFF; 607 vmx_set_test_stage(2); 608 inb(0x0); 609 report("I/O bitmap - trap in", vmx_get_test_stage() == 3); 610 vmx_set_test_stage(3); 611 outw(0x0, 0x0); 612 report("I/O bitmap - trap out", vmx_get_test_stage() == 4); 613 vmx_set_test_stage(4); 614 inl(0x0); 615 report("I/O bitmap - I/O width, long", vmx_get_test_stage() == 5); 616 // test low/high IO port 617 vmx_set_test_stage(5); 618 ((u8 *)io_bitmap_a)[0x5000 / 8] = (1 << (0x5000 % 8)); 619 inb(0x5000); 620 report("I/O bitmap - I/O port, low part", vmx_get_test_stage() == 6); 621 vmx_set_test_stage(6); 622 ((u8 *)io_bitmap_b)[0x1000 / 8] = (1 << (0x1000 % 8)); 623 inb(0x9000); 624 report("I/O bitmap - I/O port, high part", vmx_get_test_stage() == 7); 625 // test partial pass 626 vmx_set_test_stage(7); 627 inl(0x4FFF); 628 report("I/O bitmap - partial pass", vmx_get_test_stage() == 8); 629 // test overrun 630 vmx_set_test_stage(8); 631 memset(io_bitmap_a, 0x0, PAGE_SIZE); 632 memset(io_bitmap_b, 0x0, PAGE_SIZE); 633 inl(0xFFFF); 634 report("I/O bitmap - overrun", vmx_get_test_stage() == 9); 635 vmx_set_test_stage(9); 636 vmcall(); 637 outb(0x0, 0x0); 638 report("I/O bitmap - ignore unconditional exiting", 639 vmx_get_test_stage() == 9); 640 vmx_set_test_stage(10); 641 vmcall(); 642 outb(0x0, 0x0); 643 report("I/O bitmap - unconditional exiting", 644 vmx_get_test_stage() == 11); 645 } 646 647 static int iobmp_exit_handler() 648 { 649 u64 guest_rip; 650 ulong reason, exit_qual; 651 u32 insn_len, ctrl_cpu0; 652 653 guest_rip = vmcs_read(GUEST_RIP); 654 reason = vmcs_read(EXI_REASON) & 0xff; 655 exit_qual = vmcs_read(EXI_QUALIFICATION); 656 insn_len = vmcs_read(EXI_INST_LEN); 657 switch (reason) { 658 case VMX_IO: 659 switch (vmx_get_test_stage()) { 660 case 0: 661 case 1: 662 vmx_inc_test_stage(); 663 break; 664 case 2: 665 report("I/O bitmap - I/O width, byte", 666 (exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_BYTE); 667 report("I/O bitmap - I/O direction, in", exit_qual & VMX_IO_IN); 668 vmx_inc_test_stage(); 669 break; 670 case 3: 671 report("I/O bitmap - I/O width, word", 672 (exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_WORD); 673 report("I/O bitmap - I/O direction, out", 674 !(exit_qual & VMX_IO_IN)); 675 vmx_inc_test_stage(); 676 break; 677 case 4: 678 report("I/O bitmap - I/O width, long", 679 (exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_LONG); 680 vmx_inc_test_stage(); 681 break; 682 case 5: 683 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x5000) 684 vmx_inc_test_stage(); 685 break; 686 case 6: 687 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x9000) 688 vmx_inc_test_stage(); 689 break; 690 case 7: 691 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x4FFF) 692 vmx_inc_test_stage(); 693 break; 694 case 8: 695 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0xFFFF) 696 vmx_inc_test_stage(); 697 break; 698 case 9: 699 case 10: 700 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 701 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0 & ~CPU_IO); 702 vmx_inc_test_stage(); 703 break; 704 default: 705 // Should not reach here 706 printf("ERROR : unexpected stage, %d\n", 707 vmx_get_test_stage()); 708 print_vmexit_info(); 709 return VMX_TEST_VMEXIT; 710 } 711 vmcs_write(GUEST_RIP, guest_rip + insn_len); 712 return VMX_TEST_RESUME; 713 case VMX_VMCALL: 714 switch (vmx_get_test_stage()) { 715 case 9: 716 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 717 ctrl_cpu0 |= CPU_IO | CPU_IO_BITMAP; 718 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 719 break; 720 case 10: 721 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 722 ctrl_cpu0 = (ctrl_cpu0 & ~CPU_IO_BITMAP) | CPU_IO; 723 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 724 break; 725 default: 726 // Should not reach here 727 printf("ERROR : unexpected stage, %d\n", 728 vmx_get_test_stage()); 729 print_vmexit_info(); 730 return VMX_TEST_VMEXIT; 731 } 732 vmcs_write(GUEST_RIP, guest_rip + insn_len); 733 return VMX_TEST_RESUME; 734 default: 735 printf("guest_rip = %#lx\n", guest_rip); 736 printf("\tERROR : Undefined exit reason, reason = %ld.\n", reason); 737 break; 738 } 739 return VMX_TEST_VMEXIT; 740 } 741 742 #define INSN_CPU0 0 743 #define INSN_CPU1 1 744 #define INSN_ALWAYS_TRAP 2 745 746 #define FIELD_EXIT_QUAL (1 << 0) 747 #define FIELD_INSN_INFO (1 << 1) 748 749 asm( 750 "insn_hlt: hlt;ret\n\t" 751 "insn_invlpg: invlpg 0x12345678;ret\n\t" 752 "insn_mwait: xor %eax, %eax; xor %ecx, %ecx; mwait;ret\n\t" 753 "insn_rdpmc: xor %ecx, %ecx; rdpmc;ret\n\t" 754 "insn_rdtsc: rdtsc;ret\n\t" 755 "insn_cr3_load: mov cr3,%rax; mov %rax,%cr3;ret\n\t" 756 "insn_cr3_store: mov %cr3,%rax;ret\n\t" 757 #ifdef __x86_64__ 758 "insn_cr8_load: mov %rax,%cr8;ret\n\t" 759 "insn_cr8_store: mov %cr8,%rax;ret\n\t" 760 #endif 761 "insn_monitor: xor %eax, %eax; xor %ecx, %ecx; xor %edx, %edx; monitor;ret\n\t" 762 "insn_pause: pause;ret\n\t" 763 "insn_wbinvd: wbinvd;ret\n\t" 764 "insn_cpuid: mov $10, %eax; cpuid;ret\n\t" 765 "insn_invd: invd;ret\n\t" 766 "insn_sgdt: sgdt gdt64_desc;ret\n\t" 767 "insn_lgdt: lgdt gdt64_desc;ret\n\t" 768 "insn_sidt: sidt idt_descr;ret\n\t" 769 "insn_lidt: lidt idt_descr;ret\n\t" 770 "insn_sldt: sldt %ax;ret\n\t" 771 "insn_lldt: xor %eax, %eax; lldt %ax;ret\n\t" 772 "insn_str: str %ax;ret\n\t" 773 ); 774 extern void insn_hlt(); 775 extern void insn_invlpg(); 776 extern void insn_mwait(); 777 extern void insn_rdpmc(); 778 extern void insn_rdtsc(); 779 extern void insn_cr3_load(); 780 extern void insn_cr3_store(); 781 #ifdef __x86_64__ 782 extern void insn_cr8_load(); 783 extern void insn_cr8_store(); 784 #endif 785 extern void insn_monitor(); 786 extern void insn_pause(); 787 extern void insn_wbinvd(); 788 extern void insn_sgdt(); 789 extern void insn_lgdt(); 790 extern void insn_sidt(); 791 extern void insn_lidt(); 792 extern void insn_sldt(); 793 extern void insn_lldt(); 794 extern void insn_str(); 795 extern void insn_cpuid(); 796 extern void insn_invd(); 797 798 u32 cur_insn; 799 u64 cr3; 800 801 struct insn_table { 802 const char *name; 803 u32 flag; 804 void (*insn_func)(); 805 u32 type; 806 u32 reason; 807 ulong exit_qual; 808 u32 insn_info; 809 // Use FIELD_EXIT_QUAL and FIELD_INSN_INFO to define 810 // which field need to be tested, reason is always tested 811 u32 test_field; 812 }; 813 814 /* 815 * Add more test cases of instruction intercept here. Elements in this 816 * table is: 817 * name/control flag/insn function/type/exit reason/exit qulification/ 818 * instruction info/field to test 819 * The last field defines which fields (exit_qual and insn_info) need to be 820 * tested in exit handler. If set to 0, only "reason" is checked. 821 */ 822 static struct insn_table insn_table[] = { 823 // Flags for Primary Processor-Based VM-Execution Controls 824 {"HLT", CPU_HLT, insn_hlt, INSN_CPU0, 12, 0, 0, 0}, 825 {"INVLPG", CPU_INVLPG, insn_invlpg, INSN_CPU0, 14, 826 0x12345678, 0, FIELD_EXIT_QUAL}, 827 {"MWAIT", CPU_MWAIT, insn_mwait, INSN_CPU0, 36, 0, 0, 0}, 828 {"RDPMC", CPU_RDPMC, insn_rdpmc, INSN_CPU0, 15, 0, 0, 0}, 829 {"RDTSC", CPU_RDTSC, insn_rdtsc, INSN_CPU0, 16, 0, 0, 0}, 830 {"CR3 load", CPU_CR3_LOAD, insn_cr3_load, INSN_CPU0, 28, 0x3, 0, 831 FIELD_EXIT_QUAL}, 832 {"CR3 store", CPU_CR3_STORE, insn_cr3_store, INSN_CPU0, 28, 0x13, 0, 833 FIELD_EXIT_QUAL}, 834 #ifdef __x86_64__ 835 {"CR8 load", CPU_CR8_LOAD, insn_cr8_load, INSN_CPU0, 28, 0x8, 0, 836 FIELD_EXIT_QUAL}, 837 {"CR8 store", CPU_CR8_STORE, insn_cr8_store, INSN_CPU0, 28, 0x18, 0, 838 FIELD_EXIT_QUAL}, 839 #endif 840 {"MONITOR", CPU_MONITOR, insn_monitor, INSN_CPU0, 39, 0, 0, 0}, 841 {"PAUSE", CPU_PAUSE, insn_pause, INSN_CPU0, 40, 0, 0, 0}, 842 // Flags for Secondary Processor-Based VM-Execution Controls 843 {"WBINVD", CPU_WBINVD, insn_wbinvd, INSN_CPU1, 54, 0, 0, 0}, 844 {"DESC_TABLE (SGDT)", CPU_DESC_TABLE, insn_sgdt, INSN_CPU1, 46, 0, 0, 0}, 845 {"DESC_TABLE (LGDT)", CPU_DESC_TABLE, insn_lgdt, INSN_CPU1, 46, 0, 0, 0}, 846 {"DESC_TABLE (SIDT)", CPU_DESC_TABLE, insn_sidt, INSN_CPU1, 46, 0, 0, 0}, 847 {"DESC_TABLE (LIDT)", CPU_DESC_TABLE, insn_lidt, INSN_CPU1, 46, 0, 0, 0}, 848 {"DESC_TABLE (SLDT)", CPU_DESC_TABLE, insn_sldt, INSN_CPU1, 47, 0, 0, 0}, 849 {"DESC_TABLE (LLDT)", CPU_DESC_TABLE, insn_lldt, INSN_CPU1, 47, 0, 0, 0}, 850 {"DESC_TABLE (STR)", CPU_DESC_TABLE, insn_str, INSN_CPU1, 47, 0, 0, 0}, 851 /* LTR causes a #GP if done with a busy selector, so it is not tested. */ 852 // Instructions always trap 853 {"CPUID", 0, insn_cpuid, INSN_ALWAYS_TRAP, 10, 0, 0, 0}, 854 {"INVD", 0, insn_invd, INSN_ALWAYS_TRAP, 13, 0, 0, 0}, 855 // Instructions never trap 856 {NULL}, 857 }; 858 859 static int insn_intercept_init() 860 { 861 u32 ctrl_cpu; 862 863 ctrl_cpu = ctrl_cpu_rev[0].set | CPU_SECONDARY; 864 ctrl_cpu &= ctrl_cpu_rev[0].clr; 865 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu); 866 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu_rev[1].set); 867 cr3 = read_cr3(); 868 return VMX_TEST_START; 869 } 870 871 static void insn_intercept_main() 872 { 873 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 874 vmx_set_test_stage(cur_insn * 2); 875 if ((insn_table[cur_insn].type == INSN_CPU0 && 876 !(ctrl_cpu_rev[0].clr & insn_table[cur_insn].flag)) || 877 (insn_table[cur_insn].type == INSN_CPU1 && 878 !(ctrl_cpu_rev[1].clr & insn_table[cur_insn].flag))) { 879 printf("\tCPU_CTRL%d.CPU_%s is not supported.\n", 880 insn_table[cur_insn].type - INSN_CPU0, 881 insn_table[cur_insn].name); 882 continue; 883 } 884 885 if ((insn_table[cur_insn].type == INSN_CPU0 && 886 !(ctrl_cpu_rev[0].set & insn_table[cur_insn].flag)) || 887 (insn_table[cur_insn].type == INSN_CPU1 && 888 !(ctrl_cpu_rev[1].set & insn_table[cur_insn].flag))) { 889 /* skip hlt, it stalls the guest and is tested below */ 890 if (insn_table[cur_insn].insn_func != insn_hlt) 891 insn_table[cur_insn].insn_func(); 892 report("execute %s", vmx_get_test_stage() == cur_insn * 2, 893 insn_table[cur_insn].name); 894 } else if (insn_table[cur_insn].type != INSN_ALWAYS_TRAP) 895 printf("\tCPU_CTRL%d.CPU_%s always traps.\n", 896 insn_table[cur_insn].type - INSN_CPU0, 897 insn_table[cur_insn].name); 898 899 vmcall(); 900 901 insn_table[cur_insn].insn_func(); 902 report("intercept %s", vmx_get_test_stage() == cur_insn * 2 + 1, 903 insn_table[cur_insn].name); 904 905 vmx_set_test_stage(cur_insn * 2 + 1); 906 vmcall(); 907 } 908 } 909 910 static int insn_intercept_exit_handler() 911 { 912 u64 guest_rip; 913 u32 reason; 914 ulong exit_qual; 915 u32 insn_len; 916 u32 insn_info; 917 bool pass; 918 919 guest_rip = vmcs_read(GUEST_RIP); 920 reason = vmcs_read(EXI_REASON) & 0xff; 921 exit_qual = vmcs_read(EXI_QUALIFICATION); 922 insn_len = vmcs_read(EXI_INST_LEN); 923 insn_info = vmcs_read(EXI_INST_INFO); 924 925 if (reason == VMX_VMCALL) { 926 u32 val = 0; 927 928 if (insn_table[cur_insn].type == INSN_CPU0) 929 val = vmcs_read(CPU_EXEC_CTRL0); 930 else if (insn_table[cur_insn].type == INSN_CPU1) 931 val = vmcs_read(CPU_EXEC_CTRL1); 932 933 if (vmx_get_test_stage() & 1) 934 val &= ~insn_table[cur_insn].flag; 935 else 936 val |= insn_table[cur_insn].flag; 937 938 if (insn_table[cur_insn].type == INSN_CPU0) 939 vmcs_write(CPU_EXEC_CTRL0, val | ctrl_cpu_rev[0].set); 940 else if (insn_table[cur_insn].type == INSN_CPU1) 941 vmcs_write(CPU_EXEC_CTRL1, val | ctrl_cpu_rev[1].set); 942 } else { 943 pass = (cur_insn * 2 == vmx_get_test_stage()) && 944 insn_table[cur_insn].reason == reason; 945 if (insn_table[cur_insn].test_field & FIELD_EXIT_QUAL && 946 insn_table[cur_insn].exit_qual != exit_qual) 947 pass = false; 948 if (insn_table[cur_insn].test_field & FIELD_INSN_INFO && 949 insn_table[cur_insn].insn_info != insn_info) 950 pass = false; 951 if (pass) 952 vmx_inc_test_stage(); 953 } 954 vmcs_write(GUEST_RIP, guest_rip + insn_len); 955 return VMX_TEST_RESUME; 956 } 957 958 959 /* Enables EPT and sets up the identity map. */ 960 static int setup_ept(bool enable_ad) 961 { 962 unsigned long end_of_memory; 963 u32 ctrl_cpu[2]; 964 965 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 966 !(ctrl_cpu_rev[1].clr & CPU_EPT)) { 967 printf("\tEPT is not supported"); 968 return 1; 969 } 970 971 972 if (!(ept_vpid.val & EPT_CAP_UC) && 973 !(ept_vpid.val & EPT_CAP_WB)) { 974 printf("\tEPT paging-structure memory type " 975 "UC&WB are not supported\n"); 976 return 1; 977 } 978 if (ept_vpid.val & EPT_CAP_UC) 979 eptp = EPT_MEM_TYPE_UC; 980 else 981 eptp = EPT_MEM_TYPE_WB; 982 if (!(ept_vpid.val & EPT_CAP_PWL4)) { 983 printf("\tPWL4 is not supported\n"); 984 return 1; 985 } 986 ctrl_cpu[0] = vmcs_read(CPU_EXEC_CTRL0); 987 ctrl_cpu[1] = vmcs_read(CPU_EXEC_CTRL1); 988 ctrl_cpu[0] = (ctrl_cpu[0] | CPU_SECONDARY) 989 & ctrl_cpu_rev[0].clr; 990 ctrl_cpu[1] = (ctrl_cpu[1] | CPU_EPT) 991 & ctrl_cpu_rev[1].clr; 992 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu[0]); 993 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu[1]); 994 eptp |= (3 << EPTP_PG_WALK_LEN_SHIFT); 995 pml4 = alloc_page(); 996 memset(pml4, 0, PAGE_SIZE); 997 eptp |= virt_to_phys(pml4); 998 if (enable_ad) 999 eptp |= EPTP_AD_FLAG; 1000 vmcs_write(EPTP, eptp); 1001 end_of_memory = fwcfg_get_u64(FW_CFG_RAM_SIZE); 1002 if (end_of_memory < (1ul << 32)) 1003 end_of_memory = (1ul << 32); 1004 /* Cannot use large EPT pages if we need to track EPT 1005 * accessed/dirty bits at 4K granularity. 1006 */ 1007 setup_ept_range(pml4, 0, end_of_memory, 0, 1008 !enable_ad && ept_2m_supported(), 1009 EPT_WA | EPT_RA | EPT_EA); 1010 return 0; 1011 } 1012 1013 static void ept_enable_ad_bits(void) 1014 { 1015 eptp |= EPTP_AD_FLAG; 1016 vmcs_write(EPTP, eptp); 1017 } 1018 1019 static void ept_disable_ad_bits(void) 1020 { 1021 eptp &= ~EPTP_AD_FLAG; 1022 vmcs_write(EPTP, eptp); 1023 } 1024 1025 static void ept_enable_ad_bits_or_skip_test(void) 1026 { 1027 if (!ept_ad_bits_supported()) 1028 test_skip("EPT AD bits not supported."); 1029 ept_enable_ad_bits(); 1030 } 1031 1032 static int apic_version; 1033 1034 static int ept_init_common(bool have_ad) 1035 { 1036 if (setup_ept(have_ad)) 1037 return VMX_TEST_EXIT; 1038 data_page1 = alloc_page(); 1039 data_page2 = alloc_page(); 1040 memset(data_page1, 0x0, PAGE_SIZE); 1041 memset(data_page2, 0x0, PAGE_SIZE); 1042 *((u32 *)data_page1) = MAGIC_VAL_1; 1043 *((u32 *)data_page2) = MAGIC_VAL_2; 1044 install_ept(pml4, (unsigned long)data_page1, (unsigned long)data_page2, 1045 EPT_RA | EPT_WA | EPT_EA); 1046 1047 apic_version = *((u32 *)0xfee00030UL); 1048 return VMX_TEST_START; 1049 } 1050 1051 static int ept_init() 1052 { 1053 return ept_init_common(false); 1054 } 1055 1056 static void ept_common() 1057 { 1058 vmx_set_test_stage(0); 1059 if (*((u32 *)data_page2) != MAGIC_VAL_1 || 1060 *((u32 *)data_page1) != MAGIC_VAL_1) 1061 report("EPT basic framework - read", 0); 1062 else { 1063 *((u32 *)data_page2) = MAGIC_VAL_3; 1064 vmcall(); 1065 if (vmx_get_test_stage() == 1) { 1066 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1067 *((u32 *)data_page2) == MAGIC_VAL_2) 1068 report("EPT basic framework", 1); 1069 else 1070 report("EPT basic framework - remap", 1); 1071 } 1072 } 1073 // Test EPT Misconfigurations 1074 vmx_set_test_stage(1); 1075 vmcall(); 1076 *((u32 *)data_page1) = MAGIC_VAL_1; 1077 if (vmx_get_test_stage() != 2) { 1078 report("EPT misconfigurations", 0); 1079 goto t1; 1080 } 1081 vmx_set_test_stage(2); 1082 vmcall(); 1083 *((u32 *)data_page1) = MAGIC_VAL_1; 1084 report("EPT misconfigurations", vmx_get_test_stage() == 3); 1085 t1: 1086 // Test EPT violation 1087 vmx_set_test_stage(3); 1088 vmcall(); 1089 *((u32 *)data_page1) = MAGIC_VAL_1; 1090 report("EPT violation - page permission", vmx_get_test_stage() == 4); 1091 // Violation caused by EPT paging structure 1092 vmx_set_test_stage(4); 1093 vmcall(); 1094 *((u32 *)data_page1) = MAGIC_VAL_2; 1095 report("EPT violation - paging structure", vmx_get_test_stage() == 5); 1096 } 1097 1098 static void ept_main() 1099 { 1100 ept_common(); 1101 1102 // Test EPT access to L1 MMIO 1103 vmx_set_test_stage(6); 1104 report("EPT - MMIO access", *((u32 *)0xfee00030UL) == apic_version); 1105 1106 // Test invalid operand for INVEPT 1107 vmcall(); 1108 report("EPT - unsupported INVEPT", vmx_get_test_stage() == 7); 1109 } 1110 1111 bool invept_test(int type, u64 eptp) 1112 { 1113 bool ret, supported; 1114 1115 supported = ept_vpid.val & (EPT_CAP_INVEPT_SINGLE >> INVEPT_SINGLE << type); 1116 ret = invept(type, eptp); 1117 1118 if (ret == !supported) 1119 return false; 1120 1121 if (!supported) 1122 printf("WARNING: unsupported invept passed!\n"); 1123 else 1124 printf("WARNING: invept failed!\n"); 1125 1126 return true; 1127 } 1128 1129 static int pml_exit_handler(void) 1130 { 1131 u16 index, count; 1132 ulong reason = vmcs_read(EXI_REASON) & 0xff; 1133 u64 *pmlbuf = pml_log; 1134 u64 guest_rip = vmcs_read(GUEST_RIP);; 1135 u64 guest_cr3 = vmcs_read(GUEST_CR3); 1136 u32 insn_len = vmcs_read(EXI_INST_LEN); 1137 1138 switch (reason) { 1139 case VMX_VMCALL: 1140 switch (vmx_get_test_stage()) { 1141 case 0: 1142 index = vmcs_read(GUEST_PML_INDEX); 1143 for (count = index + 1; count < PML_INDEX; count++) { 1144 if (pmlbuf[count] == (u64)data_page2) { 1145 vmx_inc_test_stage(); 1146 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1147 break; 1148 } 1149 } 1150 break; 1151 case 1: 1152 index = vmcs_read(GUEST_PML_INDEX); 1153 /* Keep clearing the dirty bit till a overflow */ 1154 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1155 break; 1156 default: 1157 printf("ERROR - unexpected stage, %d.\n", 1158 vmx_get_test_stage()); 1159 print_vmexit_info(); 1160 return VMX_TEST_VMEXIT; 1161 } 1162 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1163 return VMX_TEST_RESUME; 1164 case VMX_PML_FULL: 1165 vmx_inc_test_stage(); 1166 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1167 return VMX_TEST_RESUME; 1168 default: 1169 printf("Unknown exit reason, %ld\n", reason); 1170 print_vmexit_info(); 1171 } 1172 return VMX_TEST_VMEXIT; 1173 } 1174 1175 static int ept_exit_handler_common(bool have_ad) 1176 { 1177 u64 guest_rip; 1178 u64 guest_cr3; 1179 ulong reason; 1180 u32 insn_len; 1181 u32 exit_qual; 1182 static unsigned long data_page1_pte, data_page1_pte_pte; 1183 1184 guest_rip = vmcs_read(GUEST_RIP); 1185 guest_cr3 = vmcs_read(GUEST_CR3); 1186 reason = vmcs_read(EXI_REASON) & 0xff; 1187 insn_len = vmcs_read(EXI_INST_LEN); 1188 exit_qual = vmcs_read(EXI_QUALIFICATION); 1189 switch (reason) { 1190 case VMX_VMCALL: 1191 switch (vmx_get_test_stage()) { 1192 case 0: 1193 check_ept_ad(pml4, guest_cr3, 1194 (unsigned long)data_page1, 1195 have_ad ? EPT_ACCESS_FLAG : 0, 1196 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1197 check_ept_ad(pml4, guest_cr3, 1198 (unsigned long)data_page2, 1199 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0, 1200 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1201 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1202 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1203 if (have_ad) 1204 ept_sync(INVEPT_SINGLE, eptp);; 1205 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1206 *((u32 *)data_page2) == MAGIC_VAL_2) { 1207 vmx_inc_test_stage(); 1208 install_ept(pml4, (unsigned long)data_page2, 1209 (unsigned long)data_page2, 1210 EPT_RA | EPT_WA | EPT_EA); 1211 } else 1212 report("EPT basic framework - write", 0); 1213 break; 1214 case 1: 1215 install_ept(pml4, (unsigned long)data_page1, 1216 (unsigned long)data_page1, EPT_WA); 1217 ept_sync(INVEPT_SINGLE, eptp); 1218 break; 1219 case 2: 1220 install_ept(pml4, (unsigned long)data_page1, 1221 (unsigned long)data_page1, 1222 EPT_RA | EPT_WA | EPT_EA | 1223 (2 << EPT_MEM_TYPE_SHIFT)); 1224 ept_sync(INVEPT_SINGLE, eptp); 1225 break; 1226 case 3: 1227 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1228 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)data_page1, 1229 1, &data_page1_pte)); 1230 set_ept_pte(pml4, (unsigned long)data_page1, 1231 1, data_page1_pte & ~EPT_PRESENT); 1232 ept_sync(INVEPT_SINGLE, eptp); 1233 break; 1234 case 4: 1235 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)data_page1, 1236 2, &data_page1_pte)); 1237 data_page1_pte &= PAGE_MASK; 1238 TEST_ASSERT(get_ept_pte(pml4, data_page1_pte, 1239 2, &data_page1_pte_pte)); 1240 set_ept_pte(pml4, data_page1_pte, 2, 1241 data_page1_pte_pte & ~EPT_PRESENT); 1242 ept_sync(INVEPT_SINGLE, eptp); 1243 break; 1244 case 6: 1245 if (!invept_test(0, eptp)) 1246 vmx_inc_test_stage(); 1247 break; 1248 // Should not reach here 1249 default: 1250 printf("ERROR - unexpected stage, %d.\n", 1251 vmx_get_test_stage()); 1252 print_vmexit_info(); 1253 return VMX_TEST_VMEXIT; 1254 } 1255 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1256 return VMX_TEST_RESUME; 1257 case VMX_EPT_MISCONFIG: 1258 switch (vmx_get_test_stage()) { 1259 case 1: 1260 case 2: 1261 vmx_inc_test_stage(); 1262 install_ept(pml4, (unsigned long)data_page1, 1263 (unsigned long)data_page1, 1264 EPT_RA | EPT_WA | EPT_EA); 1265 ept_sync(INVEPT_SINGLE, eptp); 1266 break; 1267 // Should not reach here 1268 default: 1269 printf("ERROR - unexpected stage, %d.\n", 1270 vmx_get_test_stage()); 1271 print_vmexit_info(); 1272 return VMX_TEST_VMEXIT; 1273 } 1274 return VMX_TEST_RESUME; 1275 case VMX_EPT_VIOLATION: 1276 switch(vmx_get_test_stage()) { 1277 case 3: 1278 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1279 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1280 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1281 if (exit_qual == (EPT_VLT_WR | EPT_VLT_LADDR_VLD | 1282 EPT_VLT_PADDR)) 1283 vmx_inc_test_stage(); 1284 set_ept_pte(pml4, (unsigned long)data_page1, 1285 1, data_page1_pte | (EPT_PRESENT)); 1286 ept_sync(INVEPT_SINGLE, eptp); 1287 break; 1288 case 4: 1289 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1290 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1291 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1292 if (exit_qual == (EPT_VLT_RD | 1293 (have_ad ? EPT_VLT_WR : 0) | 1294 EPT_VLT_LADDR_VLD)) 1295 vmx_inc_test_stage(); 1296 set_ept_pte(pml4, data_page1_pte, 2, 1297 data_page1_pte_pte | (EPT_PRESENT)); 1298 ept_sync(INVEPT_SINGLE, eptp); 1299 break; 1300 default: 1301 // Should not reach here 1302 printf("ERROR : unexpected stage, %d\n", 1303 vmx_get_test_stage()); 1304 print_vmexit_info(); 1305 return VMX_TEST_VMEXIT; 1306 } 1307 return VMX_TEST_RESUME; 1308 default: 1309 printf("Unknown exit reason, %ld\n", reason); 1310 print_vmexit_info(); 1311 } 1312 return VMX_TEST_VMEXIT; 1313 } 1314 1315 static int ept_exit_handler() 1316 { 1317 return ept_exit_handler_common(false); 1318 } 1319 1320 static int eptad_init() 1321 { 1322 int r = ept_init_common(true); 1323 1324 if (r == VMX_TEST_EXIT) 1325 return r; 1326 1327 if ((rdmsr(MSR_IA32_VMX_EPT_VPID_CAP) & EPT_CAP_AD_FLAG) == 0) { 1328 printf("\tEPT A/D bits are not supported"); 1329 return VMX_TEST_EXIT; 1330 } 1331 1332 return r; 1333 } 1334 1335 static int pml_init() 1336 { 1337 u32 ctrl_cpu; 1338 int r = eptad_init(); 1339 1340 if (r == VMX_TEST_EXIT) 1341 return r; 1342 1343 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1344 !(ctrl_cpu_rev[1].clr & CPU_PML)) { 1345 printf("\tPML is not supported"); 1346 return VMX_TEST_EXIT; 1347 } 1348 1349 pml_log = alloc_page(); 1350 memset(pml_log, 0x0, PAGE_SIZE); 1351 vmcs_write(PMLADDR, (u64)pml_log); 1352 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1353 1354 ctrl_cpu = vmcs_read(CPU_EXEC_CTRL1) | CPU_PML; 1355 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu); 1356 1357 return VMX_TEST_START; 1358 } 1359 1360 static void pml_main() 1361 { 1362 int count = 0; 1363 1364 vmx_set_test_stage(0); 1365 *((u32 *)data_page2) = 0x1; 1366 vmcall(); 1367 report("PML - Dirty GPA Logging", vmx_get_test_stage() == 1); 1368 1369 while (vmx_get_test_stage() == 1) { 1370 *((u32 *)data_page2) = 0x1; 1371 if (count++ > PML_INDEX) 1372 break; 1373 vmcall(); 1374 } 1375 report("PML Full Event", vmx_get_test_stage() == 2); 1376 } 1377 1378 static void eptad_main() 1379 { 1380 ept_common(); 1381 } 1382 1383 static int eptad_exit_handler() 1384 { 1385 return ept_exit_handler_common(true); 1386 } 1387 1388 bool invvpid_test(int type, u16 vpid) 1389 { 1390 bool ret, supported; 1391 1392 supported = ept_vpid.val & 1393 (VPID_CAP_INVVPID_ADDR >> INVVPID_ADDR << type); 1394 ret = invvpid(type, vpid, 0); 1395 1396 if (ret == !supported) 1397 return false; 1398 1399 if (!supported) 1400 printf("WARNING: unsupported invvpid passed!\n"); 1401 else 1402 printf("WARNING: invvpid failed!\n"); 1403 1404 return true; 1405 } 1406 1407 static int vpid_init() 1408 { 1409 u32 ctrl_cpu1; 1410 1411 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1412 !(ctrl_cpu_rev[1].clr & CPU_VPID)) { 1413 printf("\tVPID is not supported"); 1414 return VMX_TEST_EXIT; 1415 } 1416 1417 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 1418 ctrl_cpu1 |= CPU_VPID; 1419 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 1420 return VMX_TEST_START; 1421 } 1422 1423 static void vpid_main() 1424 { 1425 vmx_set_test_stage(0); 1426 vmcall(); 1427 report("INVVPID SINGLE ADDRESS", vmx_get_test_stage() == 1); 1428 vmx_set_test_stage(2); 1429 vmcall(); 1430 report("INVVPID SINGLE", vmx_get_test_stage() == 3); 1431 vmx_set_test_stage(4); 1432 vmcall(); 1433 report("INVVPID ALL", vmx_get_test_stage() == 5); 1434 } 1435 1436 static int vpid_exit_handler() 1437 { 1438 u64 guest_rip; 1439 ulong reason; 1440 u32 insn_len; 1441 1442 guest_rip = vmcs_read(GUEST_RIP); 1443 reason = vmcs_read(EXI_REASON) & 0xff; 1444 insn_len = vmcs_read(EXI_INST_LEN); 1445 1446 switch (reason) { 1447 case VMX_VMCALL: 1448 switch(vmx_get_test_stage()) { 1449 case 0: 1450 if (!invvpid_test(INVVPID_ADDR, 1)) 1451 vmx_inc_test_stage(); 1452 break; 1453 case 2: 1454 if (!invvpid_test(INVVPID_CONTEXT_GLOBAL, 1)) 1455 vmx_inc_test_stage(); 1456 break; 1457 case 4: 1458 if (!invvpid_test(INVVPID_ALL, 1)) 1459 vmx_inc_test_stage(); 1460 break; 1461 default: 1462 printf("ERROR: unexpected stage, %d\n", 1463 vmx_get_test_stage()); 1464 print_vmexit_info(); 1465 return VMX_TEST_VMEXIT; 1466 } 1467 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1468 return VMX_TEST_RESUME; 1469 default: 1470 printf("Unknown exit reason, %ld\n", reason); 1471 print_vmexit_info(); 1472 } 1473 return VMX_TEST_VMEXIT; 1474 } 1475 1476 #define TIMER_VECTOR 222 1477 1478 static volatile bool timer_fired; 1479 1480 static void timer_isr(isr_regs_t *regs) 1481 { 1482 timer_fired = true; 1483 apic_write(APIC_EOI, 0); 1484 } 1485 1486 static int interrupt_init(struct vmcs *vmcs) 1487 { 1488 msr_bmp_init(); 1489 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1490 handle_irq(TIMER_VECTOR, timer_isr); 1491 return VMX_TEST_START; 1492 } 1493 1494 static void interrupt_main(void) 1495 { 1496 long long start, loops; 1497 1498 vmx_set_test_stage(0); 1499 1500 apic_write(APIC_LVTT, TIMER_VECTOR); 1501 irq_enable(); 1502 1503 apic_write(APIC_TMICT, 1); 1504 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1505 asm volatile ("nop"); 1506 report("direct interrupt while running guest", timer_fired); 1507 1508 apic_write(APIC_TMICT, 0); 1509 irq_disable(); 1510 vmcall(); 1511 timer_fired = false; 1512 apic_write(APIC_TMICT, 1); 1513 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1514 asm volatile ("nop"); 1515 report("intercepted interrupt while running guest", timer_fired); 1516 1517 irq_enable(); 1518 apic_write(APIC_TMICT, 0); 1519 irq_disable(); 1520 vmcall(); 1521 timer_fired = false; 1522 start = rdtsc(); 1523 apic_write(APIC_TMICT, 1000000); 1524 1525 asm volatile ("sti; hlt"); 1526 1527 report("direct interrupt + hlt", 1528 rdtsc() - start > 1000000 && timer_fired); 1529 1530 apic_write(APIC_TMICT, 0); 1531 irq_disable(); 1532 vmcall(); 1533 timer_fired = false; 1534 start = rdtsc(); 1535 apic_write(APIC_TMICT, 1000000); 1536 1537 asm volatile ("sti; hlt"); 1538 1539 report("intercepted interrupt + hlt", 1540 rdtsc() - start > 10000 && timer_fired); 1541 1542 apic_write(APIC_TMICT, 0); 1543 irq_disable(); 1544 vmcall(); 1545 timer_fired = false; 1546 start = rdtsc(); 1547 apic_write(APIC_TMICT, 1000000); 1548 1549 irq_enable(); 1550 asm volatile ("nop"); 1551 vmcall(); 1552 1553 report("direct interrupt + activity state hlt", 1554 rdtsc() - start > 10000 && timer_fired); 1555 1556 apic_write(APIC_TMICT, 0); 1557 irq_disable(); 1558 vmcall(); 1559 timer_fired = false; 1560 start = rdtsc(); 1561 apic_write(APIC_TMICT, 1000000); 1562 1563 irq_enable(); 1564 asm volatile ("nop"); 1565 vmcall(); 1566 1567 report("intercepted interrupt + activity state hlt", 1568 rdtsc() - start > 10000 && timer_fired); 1569 1570 apic_write(APIC_TMICT, 0); 1571 irq_disable(); 1572 vmx_set_test_stage(7); 1573 vmcall(); 1574 timer_fired = false; 1575 apic_write(APIC_TMICT, 1); 1576 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1577 asm volatile ("nop"); 1578 report("running a guest with interrupt acknowledgement set", timer_fired); 1579 } 1580 1581 static int interrupt_exit_handler(void) 1582 { 1583 u64 guest_rip = vmcs_read(GUEST_RIP); 1584 ulong reason = vmcs_read(EXI_REASON) & 0xff; 1585 u32 insn_len = vmcs_read(EXI_INST_LEN); 1586 1587 switch (reason) { 1588 case VMX_VMCALL: 1589 switch (vmx_get_test_stage()) { 1590 case 0: 1591 case 2: 1592 case 5: 1593 vmcs_write(PIN_CONTROLS, 1594 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1595 break; 1596 case 7: 1597 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_INTA); 1598 vmcs_write(PIN_CONTROLS, 1599 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1600 break; 1601 case 1: 1602 case 3: 1603 vmcs_write(PIN_CONTROLS, 1604 vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1605 break; 1606 case 4: 1607 case 6: 1608 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1609 break; 1610 } 1611 vmx_inc_test_stage(); 1612 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1613 return VMX_TEST_RESUME; 1614 case VMX_EXTINT: 1615 if (vmcs_read(EXI_CONTROLS) & EXI_INTA) { 1616 int vector = vmcs_read(EXI_INTR_INFO) & 0xff; 1617 handle_external_interrupt(vector); 1618 } else { 1619 irq_enable(); 1620 asm volatile ("nop"); 1621 irq_disable(); 1622 } 1623 if (vmx_get_test_stage() >= 2) 1624 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 1625 return VMX_TEST_RESUME; 1626 default: 1627 printf("Unknown exit reason, %ld\n", reason); 1628 print_vmexit_info(); 1629 } 1630 1631 return VMX_TEST_VMEXIT; 1632 } 1633 1634 static int dbgctls_init(struct vmcs *vmcs) 1635 { 1636 u64 dr7 = 0x402; 1637 u64 zero = 0; 1638 1639 msr_bmp_init(); 1640 asm volatile( 1641 "mov %0,%%dr0\n\t" 1642 "mov %0,%%dr1\n\t" 1643 "mov %0,%%dr2\n\t" 1644 "mov %1,%%dr7\n\t" 1645 : : "r" (zero), "r" (dr7)); 1646 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1647 vmcs_write(GUEST_DR7, 0x404); 1648 vmcs_write(GUEST_DEBUGCTL, 0x2); 1649 1650 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 1651 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_SAVE_DBGCTLS); 1652 1653 return VMX_TEST_START; 1654 } 1655 1656 static void dbgctls_main(void) 1657 { 1658 u64 dr7, debugctl; 1659 1660 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1661 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1662 /* Commented out: KVM does not support DEBUGCTL so far */ 1663 (void)debugctl; 1664 report("Load debug controls", dr7 == 0x404 /* && debugctl == 0x2 */); 1665 1666 dr7 = 0x408; 1667 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1668 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1669 1670 vmx_set_test_stage(0); 1671 vmcall(); 1672 report("Save debug controls", vmx_get_test_stage() == 1); 1673 1674 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS || 1675 ctrl_exit_rev.set & EXI_SAVE_DBGCTLS) { 1676 printf("\tDebug controls are always loaded/saved\n"); 1677 return; 1678 } 1679 vmx_set_test_stage(2); 1680 vmcall(); 1681 1682 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1683 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1684 /* Commented out: KVM does not support DEBUGCTL so far */ 1685 (void)debugctl; 1686 report("Guest=host debug controls", dr7 == 0x402 /* && debugctl == 0x1 */); 1687 1688 dr7 = 0x408; 1689 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1690 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1691 1692 vmx_set_test_stage(3); 1693 vmcall(); 1694 report("Don't save debug controls", vmx_get_test_stage() == 4); 1695 } 1696 1697 static int dbgctls_exit_handler(void) 1698 { 1699 unsigned int reason = vmcs_read(EXI_REASON) & 0xff; 1700 u32 insn_len = vmcs_read(EXI_INST_LEN); 1701 u64 guest_rip = vmcs_read(GUEST_RIP); 1702 u64 dr7, debugctl; 1703 1704 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1705 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1706 1707 switch (reason) { 1708 case VMX_VMCALL: 1709 switch (vmx_get_test_stage()) { 1710 case 0: 1711 if (dr7 == 0x400 && debugctl == 0 && 1712 vmcs_read(GUEST_DR7) == 0x408 /* && 1713 Commented out: KVM does not support DEBUGCTL so far 1714 vmcs_read(GUEST_DEBUGCTL) == 0x3 */) 1715 vmx_inc_test_stage(); 1716 break; 1717 case 2: 1718 dr7 = 0x402; 1719 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1720 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1721 vmcs_write(GUEST_DR7, 0x404); 1722 vmcs_write(GUEST_DEBUGCTL, 0x2); 1723 1724 vmcs_write(ENT_CONTROLS, 1725 vmcs_read(ENT_CONTROLS) & ~ENT_LOAD_DBGCTLS); 1726 vmcs_write(EXI_CONTROLS, 1727 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_DBGCTLS); 1728 break; 1729 case 3: 1730 if (dr7 == 0x400 && debugctl == 0 && 1731 vmcs_read(GUEST_DR7) == 0x404 /* && 1732 Commented out: KVM does not support DEBUGCTL so far 1733 vmcs_read(GUEST_DEBUGCTL) == 0x2 */) 1734 vmx_inc_test_stage(); 1735 break; 1736 } 1737 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1738 return VMX_TEST_RESUME; 1739 default: 1740 printf("Unknown exit reason, %d\n", reason); 1741 print_vmexit_info(); 1742 } 1743 return VMX_TEST_VMEXIT; 1744 } 1745 1746 struct vmx_msr_entry { 1747 u32 index; 1748 u32 reserved; 1749 u64 value; 1750 } __attribute__((packed)); 1751 1752 #define MSR_MAGIC 0x31415926 1753 struct vmx_msr_entry *exit_msr_store, *entry_msr_load, *exit_msr_load; 1754 1755 static int msr_switch_init(struct vmcs *vmcs) 1756 { 1757 msr_bmp_init(); 1758 exit_msr_store = alloc_page(); 1759 exit_msr_load = alloc_page(); 1760 entry_msr_load = alloc_page(); 1761 memset(exit_msr_store, 0, PAGE_SIZE); 1762 memset(exit_msr_load, 0, PAGE_SIZE); 1763 memset(entry_msr_load, 0, PAGE_SIZE); 1764 entry_msr_load[0].index = MSR_KERNEL_GS_BASE; 1765 entry_msr_load[0].value = MSR_MAGIC; 1766 1767 vmx_set_test_stage(1); 1768 vmcs_write(ENT_MSR_LD_CNT, 1); 1769 vmcs_write(ENTER_MSR_LD_ADDR, (u64)entry_msr_load); 1770 vmcs_write(EXI_MSR_ST_CNT, 1); 1771 vmcs_write(EXIT_MSR_ST_ADDR, (u64)exit_msr_store); 1772 vmcs_write(EXI_MSR_LD_CNT, 1); 1773 vmcs_write(EXIT_MSR_LD_ADDR, (u64)exit_msr_load); 1774 return VMX_TEST_START; 1775 } 1776 1777 static void msr_switch_main() 1778 { 1779 if (vmx_get_test_stage() == 1) { 1780 report("VM entry MSR load", 1781 rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC); 1782 vmx_set_test_stage(2); 1783 wrmsr(MSR_KERNEL_GS_BASE, MSR_MAGIC + 1); 1784 exit_msr_store[0].index = MSR_KERNEL_GS_BASE; 1785 exit_msr_load[0].index = MSR_KERNEL_GS_BASE; 1786 exit_msr_load[0].value = MSR_MAGIC + 2; 1787 } 1788 vmcall(); 1789 } 1790 1791 static int msr_switch_exit_handler() 1792 { 1793 ulong reason; 1794 1795 reason = vmcs_read(EXI_REASON); 1796 if (reason == VMX_VMCALL && vmx_get_test_stage() == 2) { 1797 report("VM exit MSR store", 1798 exit_msr_store[0].value == MSR_MAGIC + 1); 1799 report("VM exit MSR load", 1800 rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC + 2); 1801 vmx_set_test_stage(3); 1802 entry_msr_load[0].index = MSR_FS_BASE; 1803 return VMX_TEST_RESUME; 1804 } 1805 printf("ERROR %s: unexpected stage=%u or reason=%lu\n", 1806 __func__, vmx_get_test_stage(), reason); 1807 return VMX_TEST_EXIT; 1808 } 1809 1810 static int msr_switch_entry_failure(struct vmentry_failure *failure) 1811 { 1812 ulong reason; 1813 1814 if (failure->early) { 1815 printf("ERROR %s: early exit\n", __func__); 1816 return VMX_TEST_EXIT; 1817 } 1818 1819 reason = vmcs_read(EXI_REASON); 1820 if (reason == (VMX_ENTRY_FAILURE | VMX_FAIL_MSR) && 1821 vmx_get_test_stage() == 3) { 1822 report("VM entry MSR load: try to load FS_BASE", 1823 vmcs_read(EXI_QUALIFICATION) == 1); 1824 return VMX_TEST_VMEXIT; 1825 } 1826 printf("ERROR %s: unexpected stage=%u or reason=%lu\n", 1827 __func__, vmx_get_test_stage(), reason); 1828 return VMX_TEST_EXIT; 1829 } 1830 1831 static int vmmcall_init(struct vmcs *vmcs ) 1832 { 1833 vmcs_write(EXC_BITMAP, 1 << UD_VECTOR); 1834 return VMX_TEST_START; 1835 } 1836 1837 static void vmmcall_main(void) 1838 { 1839 asm volatile( 1840 "mov $0xABCD, %%rax\n\t" 1841 "vmmcall\n\t" 1842 ::: "rax"); 1843 1844 report("VMMCALL", 0); 1845 } 1846 1847 static int vmmcall_exit_handler() 1848 { 1849 ulong reason; 1850 1851 reason = vmcs_read(EXI_REASON); 1852 switch (reason) { 1853 case VMX_VMCALL: 1854 printf("here\n"); 1855 report("VMMCALL triggers #UD", 0); 1856 break; 1857 case VMX_EXC_NMI: 1858 report("VMMCALL triggers #UD", 1859 (vmcs_read(EXI_INTR_INFO) & 0xff) == UD_VECTOR); 1860 break; 1861 default: 1862 printf("Unknown exit reason, %ld\n", reason); 1863 print_vmexit_info(); 1864 } 1865 1866 return VMX_TEST_VMEXIT; 1867 } 1868 1869 static int disable_rdtscp_init(struct vmcs *vmcs) 1870 { 1871 u32 ctrl_cpu1; 1872 1873 if (ctrl_cpu_rev[0].clr & CPU_SECONDARY) { 1874 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 1875 ctrl_cpu1 &= ~CPU_RDTSCP; 1876 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 1877 } 1878 1879 return VMX_TEST_START; 1880 } 1881 1882 static void disable_rdtscp_ud_handler(struct ex_regs *regs) 1883 { 1884 switch (vmx_get_test_stage()) { 1885 case 0: 1886 report("RDTSCP triggers #UD", true); 1887 vmx_inc_test_stage(); 1888 regs->rip += 3; 1889 break; 1890 case 2: 1891 report("RDPID triggers #UD", true); 1892 vmx_inc_test_stage(); 1893 regs->rip += 4; 1894 break; 1895 } 1896 return; 1897 1898 } 1899 1900 static void disable_rdtscp_main(void) 1901 { 1902 /* Test that #UD is properly injected in L2. */ 1903 handle_exception(UD_VECTOR, disable_rdtscp_ud_handler); 1904 1905 vmx_set_test_stage(0); 1906 asm volatile("rdtscp" : : : "eax", "ecx", "edx"); 1907 vmcall(); 1908 asm volatile(".byte 0xf3, 0x0f, 0xc7, 0xf8" : : : "eax"); 1909 vmcall(); 1910 } 1911 1912 static int disable_rdtscp_exit_handler(void) 1913 { 1914 unsigned int reason = vmcs_read(EXI_REASON) & 0xff; 1915 1916 switch (reason) { 1917 case VMX_VMCALL: 1918 switch (vmx_get_test_stage()) { 1919 case 0: 1920 report("RDTSCP triggers #UD", false); 1921 vmx_inc_test_stage(); 1922 /* fallthrough */ 1923 case 1: 1924 vmx_inc_test_stage(); 1925 vmcs_write(GUEST_RIP, vmcs_read(GUEST_RIP) + 3); 1926 return VMX_TEST_RESUME; 1927 case 2: 1928 report("RDPID triggers #UD", false); 1929 break; 1930 } 1931 break; 1932 1933 default: 1934 printf("Unknown exit reason, %d\n", reason); 1935 print_vmexit_info(); 1936 } 1937 return VMX_TEST_VMEXIT; 1938 } 1939 1940 int int3_init() 1941 { 1942 vmcs_write(EXC_BITMAP, ~0u); 1943 return VMX_TEST_START; 1944 } 1945 1946 void int3_guest_main() 1947 { 1948 asm volatile ("int3"); 1949 } 1950 1951 int int3_exit_handler() 1952 { 1953 u32 reason = vmcs_read(EXI_REASON); 1954 u32 intr_info = vmcs_read(EXI_INTR_INFO); 1955 1956 report("L1 intercepts #BP", reason == VMX_EXC_NMI && 1957 (intr_info & INTR_INFO_VALID_MASK) && 1958 (intr_info & INTR_INFO_VECTOR_MASK) == BP_VECTOR && 1959 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 1960 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION); 1961 1962 return VMX_TEST_VMEXIT; 1963 } 1964 1965 int into_init() 1966 { 1967 vmcs_write(EXC_BITMAP, ~0u); 1968 return VMX_TEST_START; 1969 } 1970 1971 void into_guest_main() 1972 { 1973 struct far_pointer32 fp = { 1974 .offset = (uintptr_t)&&into, 1975 .selector = KERNEL_CS32, 1976 }; 1977 register uintptr_t rsp asm("rsp"); 1978 1979 if (fp.offset != (uintptr_t)&&into) { 1980 printf("Code address too high.\n"); 1981 return; 1982 } 1983 if ((u32)rsp != rsp) { 1984 printf("Stack address too high.\n"); 1985 return; 1986 } 1987 1988 asm goto ("lcall *%0" : : "m" (fp) : "rax" : into); 1989 return; 1990 into: 1991 asm volatile (".code32;" 1992 "movl $0x7fffffff, %eax;" 1993 "addl %eax, %eax;" 1994 "into;" 1995 "lret;" 1996 ".code64"); 1997 __builtin_unreachable(); 1998 } 1999 2000 int into_exit_handler() 2001 { 2002 u32 reason = vmcs_read(EXI_REASON); 2003 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2004 2005 report("L1 intercepts #OF", reason == VMX_EXC_NMI && 2006 (intr_info & INTR_INFO_VALID_MASK) && 2007 (intr_info & INTR_INFO_VECTOR_MASK) == OF_VECTOR && 2008 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2009 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION); 2010 2011 return VMX_TEST_VMEXIT; 2012 } 2013 2014 static void exit_monitor_from_l2_main(void) 2015 { 2016 printf("Calling exit(0) from l2...\n"); 2017 exit(0); 2018 } 2019 2020 static int exit_monitor_from_l2_handler(void) 2021 { 2022 report("The guest should have killed the VMM", false); 2023 return VMX_TEST_EXIT; 2024 } 2025 2026 static void assert_exit_reason(u64 expected) 2027 { 2028 u64 actual = vmcs_read(EXI_REASON); 2029 2030 TEST_ASSERT_EQ_MSG(expected, actual, "Expected %s, got %s.", 2031 exit_reason_description(expected), 2032 exit_reason_description(actual)); 2033 } 2034 2035 static void skip_exit_vmcall() 2036 { 2037 u64 guest_rip = vmcs_read(GUEST_RIP); 2038 u32 insn_len = vmcs_read(EXI_INST_LEN); 2039 2040 assert_exit_reason(VMX_VMCALL); 2041 vmcs_write(GUEST_RIP, guest_rip + insn_len); 2042 } 2043 2044 static void v2_null_test_guest(void) 2045 { 2046 } 2047 2048 static void v2_null_test(void) 2049 { 2050 test_set_guest(v2_null_test_guest); 2051 enter_guest(); 2052 report(__func__, 1); 2053 } 2054 2055 static void v2_multiple_entries_test_guest(void) 2056 { 2057 vmx_set_test_stage(1); 2058 vmcall(); 2059 vmx_set_test_stage(2); 2060 } 2061 2062 static void v2_multiple_entries_test(void) 2063 { 2064 test_set_guest(v2_multiple_entries_test_guest); 2065 enter_guest(); 2066 TEST_ASSERT_EQ(vmx_get_test_stage(), 1); 2067 skip_exit_vmcall(); 2068 enter_guest(); 2069 TEST_ASSERT_EQ(vmx_get_test_stage(), 2); 2070 report(__func__, 1); 2071 } 2072 2073 static int fixture_test_data = 1; 2074 2075 static void fixture_test_teardown(void *data) 2076 { 2077 *((int *) data) = 1; 2078 } 2079 2080 static void fixture_test_guest(void) 2081 { 2082 fixture_test_data++; 2083 } 2084 2085 2086 static void fixture_test_setup(void) 2087 { 2088 TEST_ASSERT_EQ_MSG(1, fixture_test_data, 2089 "fixture_test_teardown didn't run?!"); 2090 fixture_test_data = 2; 2091 test_add_teardown(fixture_test_teardown, &fixture_test_data); 2092 test_set_guest(fixture_test_guest); 2093 } 2094 2095 static void fixture_test_case1(void) 2096 { 2097 fixture_test_setup(); 2098 TEST_ASSERT_EQ(2, fixture_test_data); 2099 enter_guest(); 2100 TEST_ASSERT_EQ(3, fixture_test_data); 2101 report(__func__, 1); 2102 } 2103 2104 static void fixture_test_case2(void) 2105 { 2106 fixture_test_setup(); 2107 TEST_ASSERT_EQ(2, fixture_test_data); 2108 enter_guest(); 2109 TEST_ASSERT_EQ(3, fixture_test_data); 2110 report(__func__, 1); 2111 } 2112 2113 enum ept_access_op { 2114 OP_READ, 2115 OP_WRITE, 2116 OP_EXEC, 2117 OP_FLUSH_TLB, 2118 OP_EXIT, 2119 }; 2120 2121 static struct ept_access_test_data { 2122 unsigned long gpa; 2123 unsigned long *gva; 2124 unsigned long hpa; 2125 unsigned long *hva; 2126 enum ept_access_op op; 2127 } ept_access_test_data; 2128 2129 extern unsigned char ret42_start; 2130 extern unsigned char ret42_end; 2131 2132 /* Returns 42. */ 2133 asm( 2134 ".align 64\n" 2135 "ret42_start:\n" 2136 "mov $42, %eax\n" 2137 "ret\n" 2138 "ret42_end:\n" 2139 ); 2140 2141 static void 2142 diagnose_ept_violation_qual(u64 expected, u64 actual) 2143 { 2144 2145 #define DIAGNOSE(flag) \ 2146 do { \ 2147 if ((expected & flag) != (actual & flag)) \ 2148 printf(#flag " %sexpected\n", \ 2149 (expected & flag) ? "" : "un"); \ 2150 } while (0) 2151 2152 DIAGNOSE(EPT_VLT_RD); 2153 DIAGNOSE(EPT_VLT_WR); 2154 DIAGNOSE(EPT_VLT_FETCH); 2155 DIAGNOSE(EPT_VLT_PERM_RD); 2156 DIAGNOSE(EPT_VLT_PERM_WR); 2157 DIAGNOSE(EPT_VLT_PERM_EX); 2158 DIAGNOSE(EPT_VLT_LADDR_VLD); 2159 DIAGNOSE(EPT_VLT_PADDR); 2160 2161 #undef DIAGNOSE 2162 } 2163 2164 static void do_ept_access_op(enum ept_access_op op) 2165 { 2166 ept_access_test_data.op = op; 2167 enter_guest(); 2168 } 2169 2170 /* 2171 * Force the guest to flush its TLB (i.e., flush gva -> gpa mappings). Only 2172 * needed by tests that modify guest PTEs. 2173 */ 2174 static void ept_access_test_guest_flush_tlb(void) 2175 { 2176 do_ept_access_op(OP_FLUSH_TLB); 2177 skip_exit_vmcall(); 2178 } 2179 2180 /* 2181 * Modifies the EPT entry at @level in the mapping of @gpa. First clears the 2182 * bits in @clear then sets the bits in @set. @mkhuge transforms the entry into 2183 * a huge page. 2184 */ 2185 static unsigned long ept_twiddle(unsigned long gpa, bool mkhuge, int level, 2186 unsigned long clear, unsigned long set) 2187 { 2188 struct ept_access_test_data *data = &ept_access_test_data; 2189 unsigned long orig_pte; 2190 unsigned long pte; 2191 2192 /* Screw with the mapping at the requested level. */ 2193 TEST_ASSERT(get_ept_pte(pml4, gpa, level, &orig_pte)); 2194 pte = orig_pte; 2195 if (mkhuge) 2196 pte = (orig_pte & ~EPT_ADDR_MASK) | data->hpa | EPT_LARGE_PAGE; 2197 else 2198 pte = orig_pte; 2199 pte = (pte & ~clear) | set; 2200 set_ept_pte(pml4, gpa, level, pte); 2201 ept_sync(INVEPT_SINGLE, eptp); 2202 2203 return orig_pte; 2204 } 2205 2206 static void ept_untwiddle(unsigned long gpa, int level, unsigned long orig_pte) 2207 { 2208 set_ept_pte(pml4, gpa, level, orig_pte); 2209 } 2210 2211 static void do_ept_violation(bool leaf, enum ept_access_op op, 2212 u64 expected_qual, u64 expected_paddr) 2213 { 2214 u64 qual; 2215 2216 /* Try the access and observe the violation. */ 2217 do_ept_access_op(op); 2218 2219 assert_exit_reason(VMX_EPT_VIOLATION); 2220 2221 qual = vmcs_read(EXI_QUALIFICATION); 2222 2223 diagnose_ept_violation_qual(expected_qual, qual); 2224 TEST_EXPECT_EQ(expected_qual, qual); 2225 2226 #if 0 2227 /* Disable for now otherwise every test will fail */ 2228 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2229 (unsigned long) ( 2230 op == OP_EXEC ? data->gva + 1 : data->gva)); 2231 #endif 2232 /* 2233 * TODO: tests that probe expected_paddr in pages other than the one at 2234 * the beginning of the 1g region. 2235 */ 2236 TEST_EXPECT_EQ(vmcs_read(INFO_PHYS_ADDR), expected_paddr); 2237 } 2238 2239 static void 2240 ept_violation_at_level_mkhuge(bool mkhuge, int level, unsigned long clear, 2241 unsigned long set, enum ept_access_op op, 2242 u64 expected_qual) 2243 { 2244 struct ept_access_test_data *data = &ept_access_test_data; 2245 unsigned long orig_pte; 2246 2247 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2248 2249 do_ept_violation(level == 1 || mkhuge, op, expected_qual, 2250 op == OP_EXEC ? data->gpa + sizeof(unsigned long) : 2251 data->gpa); 2252 2253 /* Fix the violation and resume the op loop. */ 2254 ept_untwiddle(data->gpa, level, orig_pte); 2255 enter_guest(); 2256 skip_exit_vmcall(); 2257 } 2258 2259 static void 2260 ept_violation_at_level(int level, unsigned long clear, unsigned long set, 2261 enum ept_access_op op, u64 expected_qual) 2262 { 2263 ept_violation_at_level_mkhuge(false, level, clear, set, op, 2264 expected_qual); 2265 if (ept_huge_pages_supported(level)) 2266 ept_violation_at_level_mkhuge(true, level, clear, set, op, 2267 expected_qual); 2268 } 2269 2270 static void ept_violation(unsigned long clear, unsigned long set, 2271 enum ept_access_op op, u64 expected_qual) 2272 { 2273 ept_violation_at_level(1, clear, set, op, expected_qual); 2274 ept_violation_at_level(2, clear, set, op, expected_qual); 2275 ept_violation_at_level(3, clear, set, op, expected_qual); 2276 ept_violation_at_level(4, clear, set, op, expected_qual); 2277 } 2278 2279 static void ept_access_violation(unsigned long access, enum ept_access_op op, 2280 u64 expected_qual) 2281 { 2282 ept_violation(EPT_PRESENT, access, op, 2283 expected_qual | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2284 } 2285 2286 /* 2287 * For translations that don't involve a GVA, that is physical address (paddr) 2288 * accesses, EPT violations don't set the flag EPT_VLT_PADDR. For a typical 2289 * guest memory access, the hardware does GVA -> GPA -> HPA. However, certain 2290 * translations don't involve GVAs, such as when the hardware does the guest 2291 * page table walk. For example, in translating GVA_1 -> GPA_1, the guest MMU 2292 * might try to set an A bit on a guest PTE. If the GPA_2 that the PTE resides 2293 * on isn't present in the EPT, then the EPT violation will be for GPA_2 and 2294 * the EPT_VLT_PADDR bit will be clear in the exit qualification. 2295 * 2296 * Note that paddr violations can also be triggered by loading PAE page tables 2297 * with wonky addresses. We don't test that yet. 2298 * 2299 * This function modifies the EPT entry that maps the GPA that the guest page 2300 * table entry mapping ept_access_data.gva resides on. 2301 * 2302 * @ept_access EPT permissions to set. Other permissions are cleared. 2303 * 2304 * @pte_ad Set the A/D bits on the guest PTE accordingly. 2305 * 2306 * @op Guest operation to perform with ept_access_data.gva. 2307 * 2308 * @expect_violation 2309 * Is a violation expected during the paddr access? 2310 * 2311 * @expected_qual Expected qualification for the EPT violation. 2312 * EPT_VLT_PADDR should be clear. 2313 */ 2314 static void ept_access_paddr(unsigned long ept_access, unsigned long pte_ad, 2315 enum ept_access_op op, bool expect_violation, 2316 u64 expected_qual) 2317 { 2318 struct ept_access_test_data *data = &ept_access_test_data; 2319 unsigned long *ptep; 2320 unsigned long gpa; 2321 unsigned long orig_epte; 2322 2323 /* Modify the guest PTE mapping data->gva according to @pte_ad. */ 2324 ptep = get_pte_level(current_page_table(), data->gva, /*level=*/1); 2325 TEST_ASSERT(ptep); 2326 TEST_ASSERT_EQ(*ptep & PT_ADDR_MASK, data->gpa); 2327 *ptep = (*ptep & ~PT_AD_MASK) | pte_ad; 2328 ept_access_test_guest_flush_tlb(); 2329 2330 /* 2331 * Now modify the access bits on the EPT entry for the GPA that the 2332 * guest PTE resides on. Note that by modifying a single EPT entry, 2333 * we're potentially affecting 512 guest PTEs. However, we've carefully 2334 * constructed our test such that those other 511 PTEs aren't used by 2335 * the guest: data->gva is at the beginning of a 1G huge page, thus the 2336 * PTE we're modifying is at the beginning of a 4K page and the 2337 * following 511 entires are also under our control (and not touched by 2338 * the guest). 2339 */ 2340 gpa = virt_to_phys(ptep); 2341 TEST_ASSERT_EQ(gpa & ~PAGE_MASK, 0); 2342 /* 2343 * Make sure the guest page table page is mapped with a 4K EPT entry, 2344 * otherwise our level=1 twiddling below will fail. We use the 2345 * identity map (gpa = gpa) since page tables are shared with the host. 2346 */ 2347 install_ept(pml4, gpa, gpa, EPT_PRESENT); 2348 orig_epte = ept_twiddle(gpa, /*mkhuge=*/0, /*level=*/1, 2349 /*clear=*/EPT_PRESENT, /*set=*/ept_access); 2350 2351 if (expect_violation) { 2352 do_ept_violation(/*leaf=*/true, op, 2353 expected_qual | EPT_VLT_LADDR_VLD, gpa); 2354 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2355 do_ept_access_op(op); 2356 } else { 2357 do_ept_access_op(op); 2358 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2359 } 2360 2361 TEST_ASSERT(*ptep & PT_ACCESSED_MASK); 2362 if ((pte_ad & PT_DIRTY_MASK) || op == OP_WRITE) 2363 TEST_ASSERT(*ptep & PT_DIRTY_MASK); 2364 2365 skip_exit_vmcall(); 2366 } 2367 2368 static void ept_access_allowed_paddr(unsigned long ept_access, 2369 unsigned long pte_ad, 2370 enum ept_access_op op) 2371 { 2372 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/false, 2373 /*expected_qual=*/-1); 2374 } 2375 2376 static void ept_access_violation_paddr(unsigned long ept_access, 2377 unsigned long pte_ad, 2378 enum ept_access_op op, 2379 u64 expected_qual) 2380 { 2381 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/true, 2382 expected_qual); 2383 } 2384 2385 2386 static void ept_allowed_at_level_mkhuge(bool mkhuge, int level, 2387 unsigned long clear, 2388 unsigned long set, 2389 enum ept_access_op op) 2390 { 2391 struct ept_access_test_data *data = &ept_access_test_data; 2392 unsigned long orig_pte; 2393 2394 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2395 2396 /* No violation. Should proceed to vmcall. */ 2397 do_ept_access_op(op); 2398 skip_exit_vmcall(); 2399 2400 ept_untwiddle(data->gpa, level, orig_pte); 2401 } 2402 2403 static void ept_allowed_at_level(int level, unsigned long clear, 2404 unsigned long set, enum ept_access_op op) 2405 { 2406 ept_allowed_at_level_mkhuge(false, level, clear, set, op); 2407 if (ept_huge_pages_supported(level)) 2408 ept_allowed_at_level_mkhuge(true, level, clear, set, op); 2409 } 2410 2411 static void ept_allowed(unsigned long clear, unsigned long set, 2412 enum ept_access_op op) 2413 { 2414 ept_allowed_at_level(1, clear, set, op); 2415 ept_allowed_at_level(2, clear, set, op); 2416 ept_allowed_at_level(3, clear, set, op); 2417 ept_allowed_at_level(4, clear, set, op); 2418 } 2419 2420 static void ept_ignored_bit(int bit) 2421 { 2422 /* Set the bit. */ 2423 ept_allowed(0, 1ul << bit, OP_READ); 2424 ept_allowed(0, 1ul << bit, OP_WRITE); 2425 ept_allowed(0, 1ul << bit, OP_EXEC); 2426 2427 /* Clear the bit. */ 2428 ept_allowed(1ul << bit, 0, OP_READ); 2429 ept_allowed(1ul << bit, 0, OP_WRITE); 2430 ept_allowed(1ul << bit, 0, OP_EXEC); 2431 } 2432 2433 static void ept_access_allowed(unsigned long access, enum ept_access_op op) 2434 { 2435 ept_allowed(EPT_PRESENT, access, op); 2436 } 2437 2438 2439 static void ept_misconfig_at_level_mkhuge_op(bool mkhuge, int level, 2440 unsigned long clear, 2441 unsigned long set, 2442 enum ept_access_op op) 2443 { 2444 struct ept_access_test_data *data = &ept_access_test_data; 2445 unsigned long orig_pte; 2446 2447 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2448 2449 do_ept_access_op(op); 2450 assert_exit_reason(VMX_EPT_MISCONFIG); 2451 2452 /* Intel 27.2.1, "For all other VM exits, this field is cleared." */ 2453 #if 0 2454 /* broken: */ 2455 TEST_EXPECT_EQ_MSG(vmcs_read(EXI_QUALIFICATION), 0); 2456 #endif 2457 #if 0 2458 /* 2459 * broken: 2460 * According to description of exit qual for EPT violation, 2461 * EPT_VLT_LADDR_VLD indicates if GUEST_LINEAR_ADDRESS is valid. 2462 * However, I can't find anything that says GUEST_LINEAR_ADDRESS ought 2463 * to be set for msiconfig. 2464 */ 2465 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2466 (unsigned long) ( 2467 op == OP_EXEC ? data->gva + 1 : data->gva)); 2468 #endif 2469 2470 /* Fix the violation and resume the op loop. */ 2471 ept_untwiddle(data->gpa, level, orig_pte); 2472 enter_guest(); 2473 skip_exit_vmcall(); 2474 } 2475 2476 static void ept_misconfig_at_level_mkhuge(bool mkhuge, int level, 2477 unsigned long clear, 2478 unsigned long set) 2479 { 2480 /* The op shouldn't matter (read, write, exec), so try them all! */ 2481 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_READ); 2482 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_WRITE); 2483 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_EXEC); 2484 } 2485 2486 static void ept_misconfig_at_level(int level, unsigned long clear, 2487 unsigned long set) 2488 { 2489 ept_misconfig_at_level_mkhuge(false, level, clear, set); 2490 if (ept_huge_pages_supported(level)) 2491 ept_misconfig_at_level_mkhuge(true, level, clear, set); 2492 } 2493 2494 static void ept_misconfig(unsigned long clear, unsigned long set) 2495 { 2496 ept_misconfig_at_level(1, clear, set); 2497 ept_misconfig_at_level(2, clear, set); 2498 ept_misconfig_at_level(3, clear, set); 2499 ept_misconfig_at_level(4, clear, set); 2500 } 2501 2502 static void ept_access_misconfig(unsigned long access) 2503 { 2504 ept_misconfig(EPT_PRESENT, access); 2505 } 2506 2507 static void ept_reserved_bit_at_level_nohuge(int level, int bit) 2508 { 2509 /* Setting the bit causes a misconfig. */ 2510 ept_misconfig_at_level_mkhuge(false, level, 0, 1ul << bit); 2511 2512 /* Making the entry non-present turns reserved bits into ignored. */ 2513 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2514 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2515 } 2516 2517 static void ept_reserved_bit_at_level_huge(int level, int bit) 2518 { 2519 /* Setting the bit causes a misconfig. */ 2520 ept_misconfig_at_level_mkhuge(true, level, 0, 1ul << bit); 2521 2522 /* Making the entry non-present turns reserved bits into ignored. */ 2523 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2524 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2525 } 2526 2527 static void ept_reserved_bit_at_level(int level, int bit) 2528 { 2529 /* Setting the bit causes a misconfig. */ 2530 ept_misconfig_at_level(level, 0, 1ul << bit); 2531 2532 /* Making the entry non-present turns reserved bits into ignored. */ 2533 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2534 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2535 } 2536 2537 static void ept_reserved_bit(int bit) 2538 { 2539 ept_reserved_bit_at_level(1, bit); 2540 ept_reserved_bit_at_level(2, bit); 2541 ept_reserved_bit_at_level(3, bit); 2542 ept_reserved_bit_at_level(4, bit); 2543 } 2544 2545 #define PAGE_2M_ORDER 9 2546 #define PAGE_1G_ORDER 18 2547 2548 static void *get_1g_page(void) 2549 { 2550 static void *alloc; 2551 2552 if (!alloc) 2553 alloc = alloc_pages(PAGE_1G_ORDER); 2554 return alloc; 2555 } 2556 2557 static void ept_access_test_teardown(void *unused) 2558 { 2559 /* Exit the guest cleanly. */ 2560 do_ept_access_op(OP_EXIT); 2561 } 2562 2563 static void ept_access_test_guest(void) 2564 { 2565 struct ept_access_test_data *data = &ept_access_test_data; 2566 int (*code)(void) = (int (*)(void)) &data->gva[1]; 2567 2568 while (true) { 2569 switch (data->op) { 2570 case OP_READ: 2571 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_1); 2572 break; 2573 case OP_WRITE: 2574 *data->gva = MAGIC_VAL_2; 2575 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_2); 2576 *data->gva = MAGIC_VAL_1; 2577 break; 2578 case OP_EXEC: 2579 TEST_ASSERT_EQ(42, code()); 2580 break; 2581 case OP_FLUSH_TLB: 2582 write_cr3(read_cr3()); 2583 break; 2584 case OP_EXIT: 2585 return; 2586 default: 2587 TEST_ASSERT_MSG(false, "Unknown op %d", data->op); 2588 } 2589 vmcall(); 2590 } 2591 } 2592 2593 static void ept_access_test_setup(void) 2594 { 2595 struct ept_access_test_data *data = &ept_access_test_data; 2596 unsigned long npages = 1ul << PAGE_1G_ORDER; 2597 unsigned long size = npages * PAGE_SIZE; 2598 unsigned long *page_table = current_page_table(); 2599 unsigned long pte; 2600 2601 if (setup_ept(false)) 2602 test_skip("EPT not supported"); 2603 2604 test_set_guest(ept_access_test_guest); 2605 test_add_teardown(ept_access_test_teardown, NULL); 2606 2607 data->hva = get_1g_page(); 2608 TEST_ASSERT(data->hva); 2609 data->hpa = virt_to_phys(data->hva); 2610 2611 data->gpa = 1ul << 40; 2612 data->gva = (void *) ALIGN((unsigned long) alloc_vpages(npages * 2), 2613 size); 2614 TEST_ASSERT(!any_present_pages(page_table, data->gva, size)); 2615 install_pages(page_table, data->gpa, size, data->gva); 2616 2617 /* 2618 * Make sure nothing's mapped here so the tests that screw with the 2619 * pml4 entry don't inadvertently break something. 2620 */ 2621 TEST_ASSERT(get_ept_pte(pml4, data->gpa, 4, &pte) && pte == 0); 2622 TEST_ASSERT(get_ept_pte(pml4, data->gpa + size - 1, 4, &pte) && pte == 0); 2623 install_ept(pml4, data->hpa, data->gpa, EPT_PRESENT); 2624 2625 data->hva[0] = MAGIC_VAL_1; 2626 memcpy(&data->hva[1], &ret42_start, &ret42_end - &ret42_start); 2627 } 2628 2629 static void ept_access_test_not_present(void) 2630 { 2631 ept_access_test_setup(); 2632 /* --- */ 2633 ept_access_violation(0, OP_READ, EPT_VLT_RD); 2634 ept_access_violation(0, OP_WRITE, EPT_VLT_WR); 2635 ept_access_violation(0, OP_EXEC, EPT_VLT_FETCH); 2636 } 2637 2638 static void ept_access_test_read_only(void) 2639 { 2640 ept_access_test_setup(); 2641 2642 /* r-- */ 2643 ept_access_allowed(EPT_RA, OP_READ); 2644 ept_access_violation(EPT_RA, OP_WRITE, EPT_VLT_WR | EPT_VLT_PERM_RD); 2645 ept_access_violation(EPT_RA, OP_EXEC, EPT_VLT_FETCH | EPT_VLT_PERM_RD); 2646 } 2647 2648 static void ept_access_test_write_only(void) 2649 { 2650 ept_access_test_setup(); 2651 /* -w- */ 2652 ept_access_misconfig(EPT_WA); 2653 } 2654 2655 static void ept_access_test_read_write(void) 2656 { 2657 ept_access_test_setup(); 2658 /* rw- */ 2659 ept_access_allowed(EPT_RA | EPT_WA, OP_READ); 2660 ept_access_allowed(EPT_RA | EPT_WA, OP_WRITE); 2661 ept_access_violation(EPT_RA | EPT_WA, OP_EXEC, 2662 EPT_VLT_FETCH | EPT_VLT_PERM_RD | EPT_VLT_PERM_WR); 2663 } 2664 2665 2666 static void ept_access_test_execute_only(void) 2667 { 2668 ept_access_test_setup(); 2669 /* --x */ 2670 if (ept_execute_only_supported()) { 2671 ept_access_violation(EPT_EA, OP_READ, 2672 EPT_VLT_RD | EPT_VLT_PERM_EX); 2673 ept_access_violation(EPT_EA, OP_WRITE, 2674 EPT_VLT_WR | EPT_VLT_PERM_EX); 2675 ept_access_allowed(EPT_EA, OP_EXEC); 2676 } else { 2677 ept_access_misconfig(EPT_EA); 2678 } 2679 } 2680 2681 static void ept_access_test_read_execute(void) 2682 { 2683 ept_access_test_setup(); 2684 /* r-x */ 2685 ept_access_allowed(EPT_RA | EPT_EA, OP_READ); 2686 ept_access_violation(EPT_RA | EPT_EA, OP_WRITE, 2687 EPT_VLT_WR | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX); 2688 ept_access_allowed(EPT_RA | EPT_EA, OP_EXEC); 2689 } 2690 2691 static void ept_access_test_write_execute(void) 2692 { 2693 ept_access_test_setup(); 2694 /* -wx */ 2695 ept_access_misconfig(EPT_WA | EPT_EA); 2696 } 2697 2698 static void ept_access_test_read_write_execute(void) 2699 { 2700 ept_access_test_setup(); 2701 /* rwx */ 2702 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_READ); 2703 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_WRITE); 2704 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_EXEC); 2705 } 2706 2707 static void ept_access_test_reserved_bits(void) 2708 { 2709 int i; 2710 int maxphyaddr; 2711 2712 ept_access_test_setup(); 2713 2714 /* Reserved bits above maxphyaddr. */ 2715 maxphyaddr = cpuid_maxphyaddr(); 2716 for (i = maxphyaddr; i <= 51; i++) { 2717 report_prefix_pushf("reserved_bit=%d", i); 2718 ept_reserved_bit(i); 2719 report_prefix_pop(); 2720 } 2721 2722 /* Level-specific reserved bits. */ 2723 ept_reserved_bit_at_level_nohuge(2, 3); 2724 ept_reserved_bit_at_level_nohuge(2, 4); 2725 ept_reserved_bit_at_level_nohuge(2, 5); 2726 ept_reserved_bit_at_level_nohuge(2, 6); 2727 /* 2M alignment. */ 2728 for (i = 12; i < 20; i++) { 2729 report_prefix_pushf("reserved_bit=%d", i); 2730 ept_reserved_bit_at_level_huge(2, i); 2731 report_prefix_pop(); 2732 } 2733 ept_reserved_bit_at_level_nohuge(3, 3); 2734 ept_reserved_bit_at_level_nohuge(3, 4); 2735 ept_reserved_bit_at_level_nohuge(3, 5); 2736 ept_reserved_bit_at_level_nohuge(3, 6); 2737 /* 1G alignment. */ 2738 for (i = 12; i < 29; i++) { 2739 report_prefix_pushf("reserved_bit=%d", i); 2740 ept_reserved_bit_at_level_huge(3, i); 2741 report_prefix_pop(); 2742 } 2743 ept_reserved_bit_at_level(4, 3); 2744 ept_reserved_bit_at_level(4, 4); 2745 ept_reserved_bit_at_level(4, 5); 2746 ept_reserved_bit_at_level(4, 6); 2747 ept_reserved_bit_at_level(4, 7); 2748 } 2749 2750 static void ept_access_test_ignored_bits(void) 2751 { 2752 ept_access_test_setup(); 2753 /* 2754 * Bits ignored at every level. Bits 8 and 9 (A and D) are ignored as 2755 * far as translation is concerned even if AD bits are enabled in the 2756 * EPTP. Bit 63 is ignored because "EPT-violation #VE" VM-execution 2757 * control is 0. 2758 */ 2759 ept_ignored_bit(8); 2760 ept_ignored_bit(9); 2761 ept_ignored_bit(10); 2762 ept_ignored_bit(11); 2763 ept_ignored_bit(52); 2764 ept_ignored_bit(53); 2765 ept_ignored_bit(54); 2766 ept_ignored_bit(55); 2767 ept_ignored_bit(56); 2768 ept_ignored_bit(57); 2769 ept_ignored_bit(58); 2770 ept_ignored_bit(59); 2771 ept_ignored_bit(60); 2772 ept_ignored_bit(61); 2773 ept_ignored_bit(62); 2774 ept_ignored_bit(63); 2775 } 2776 2777 static void ept_access_test_paddr_not_present_ad_disabled(void) 2778 { 2779 ept_access_test_setup(); 2780 ept_disable_ad_bits(); 2781 2782 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, EPT_VLT_RD); 2783 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, EPT_VLT_RD); 2784 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, EPT_VLT_RD); 2785 } 2786 2787 static void ept_access_test_paddr_not_present_ad_enabled(void) 2788 { 2789 u64 qual = EPT_VLT_RD | EPT_VLT_WR; 2790 2791 ept_access_test_setup(); 2792 ept_enable_ad_bits_or_skip_test(); 2793 2794 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, qual); 2795 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, qual); 2796 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, qual); 2797 } 2798 2799 static void ept_access_test_paddr_read_only_ad_disabled(void) 2800 { 2801 /* 2802 * When EPT AD bits are disabled, all accesses to guest paging 2803 * structures are reported separately as a read and (after 2804 * translation of the GPA to host physical address) a read+write 2805 * if the A/D bits have to be set. 2806 */ 2807 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 2808 2809 ept_access_test_setup(); 2810 ept_disable_ad_bits(); 2811 2812 /* Can't update A bit, so all accesses fail. */ 2813 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 2814 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 2815 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 2816 /* AD bits disabled, so only writes try to update the D bit. */ 2817 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ); 2818 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 2819 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC); 2820 /* Both A and D already set, so read-only is OK. */ 2821 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_READ); 2822 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_WRITE); 2823 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_EXEC); 2824 } 2825 2826 static void ept_access_test_paddr_read_only_ad_enabled(void) 2827 { 2828 /* 2829 * When EPT AD bits are enabled, all accesses to guest paging 2830 * structures are considered writes as far as EPT translation 2831 * is concerned. 2832 */ 2833 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 2834 2835 ept_access_test_setup(); 2836 ept_enable_ad_bits_or_skip_test(); 2837 2838 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 2839 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 2840 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 2841 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ, qual); 2842 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 2843 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC, qual); 2844 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_READ, qual); 2845 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_WRITE, qual); 2846 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_EXEC, qual); 2847 } 2848 2849 static void ept_access_test_paddr_read_write(void) 2850 { 2851 ept_access_test_setup(); 2852 /* Read-write access to paging structure. */ 2853 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_READ); 2854 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_WRITE); 2855 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_EXEC); 2856 } 2857 2858 static void ept_access_test_paddr_read_write_execute(void) 2859 { 2860 ept_access_test_setup(); 2861 /* RWX access to paging structure. */ 2862 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_READ); 2863 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_WRITE); 2864 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_EXEC); 2865 } 2866 2867 static void ept_access_test_paddr_read_execute_ad_disabled(void) 2868 { 2869 /* 2870 * When EPT AD bits are disabled, all accesses to guest paging 2871 * structures are reported separately as a read and (after 2872 * translation of the GPA to host physical address) a read+write 2873 * if the A/D bits have to be set. 2874 */ 2875 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 2876 2877 ept_access_test_setup(); 2878 ept_disable_ad_bits(); 2879 2880 /* Can't update A bit, so all accesses fail. */ 2881 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 2882 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 2883 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 2884 /* AD bits disabled, so only writes try to update the D bit. */ 2885 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ); 2886 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 2887 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC); 2888 /* Both A and D already set, so read-only is OK. */ 2889 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ); 2890 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE); 2891 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC); 2892 } 2893 2894 static void ept_access_test_paddr_read_execute_ad_enabled(void) 2895 { 2896 /* 2897 * When EPT AD bits are enabled, all accesses to guest paging 2898 * structures are considered writes as far as EPT translation 2899 * is concerned. 2900 */ 2901 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 2902 2903 ept_access_test_setup(); 2904 ept_enable_ad_bits_or_skip_test(); 2905 2906 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 2907 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 2908 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 2909 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ, qual); 2910 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 2911 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC, qual); 2912 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ, qual); 2913 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE, qual); 2914 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC, qual); 2915 } 2916 2917 static void ept_access_test_paddr_not_present_page_fault(void) 2918 { 2919 ept_access_test_setup(); 2920 /* 2921 * TODO: test no EPT violation as long as guest PF occurs. e.g., GPA is 2922 * page is read-only in EPT but GVA is also mapped read only in PT. 2923 * Thus guest page fault before host takes EPT violation for trying to 2924 * update A bit. 2925 */ 2926 } 2927 2928 static void ept_access_test_force_2m_page(void) 2929 { 2930 ept_access_test_setup(); 2931 2932 TEST_ASSERT_EQ(ept_2m_supported(), true); 2933 ept_allowed_at_level_mkhuge(true, 2, 0, 0, OP_READ); 2934 ept_violation_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_RA, OP_WRITE, 2935 EPT_VLT_WR | EPT_VLT_PERM_RD | 2936 EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2937 ept_misconfig_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_WA); 2938 } 2939 2940 static bool invvpid_valid(u64 type, u64 vpid, u64 gla) 2941 { 2942 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 2943 2944 TEST_ASSERT(msr & VPID_CAP_INVVPID); 2945 2946 if (type < INVVPID_ADDR || type > INVVPID_CONTEXT_LOCAL) 2947 return false; 2948 2949 if (!(msr & (1ull << (type + VPID_CAP_INVVPID_TYPES_SHIFT)))) 2950 return false; 2951 2952 if (vpid >> 16) 2953 return false; 2954 2955 if (type != INVVPID_ALL && !vpid) 2956 return false; 2957 2958 if (type == INVVPID_ADDR && !is_canonical(gla)) 2959 return false; 2960 2961 return true; 2962 } 2963 2964 static void try_invvpid(u64 type, u64 vpid, u64 gla) 2965 { 2966 int rc; 2967 bool valid = invvpid_valid(type, vpid, gla); 2968 u64 expected = valid ? VMXERR_UNSUPPORTED_VMCS_COMPONENT 2969 : VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID; 2970 /* 2971 * Set VMX_INST_ERROR to VMXERR_UNVALID_VMCS_COMPONENT, so 2972 * that we can tell if it is updated by INVVPID. 2973 */ 2974 vmcs_read(~0); 2975 rc = invvpid(type, vpid, gla); 2976 report("INVVPID type %ld VPID %lx GLA %lx %s", 2977 !rc == valid, type, vpid, gla, 2978 valid ? "passes" : "fails"); 2979 report("After %s INVVPID, VMX_INST_ERR is %ld (actual %ld)", 2980 vmcs_read(VMX_INST_ERROR) == expected, 2981 rc ? "failed" : "successful", 2982 expected, vmcs_read(VMX_INST_ERROR)); 2983 } 2984 2985 static void ds_invvpid(void *data) 2986 { 2987 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 2988 u64 type = ffs(msr >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 2989 2990 TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 2991 asm volatile("invvpid %0, %1" 2992 : 2993 : "m"(*(struct invvpid_operand *)data), 2994 "r"(type)); 2995 } 2996 2997 /* 2998 * The SS override is ignored in 64-bit mode, so we use an addressing 2999 * mode with %rsp as the base register to generate an implicit SS 3000 * reference. 3001 */ 3002 static void ss_invvpid(void *data) 3003 { 3004 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3005 u64 type = ffs(msr >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 3006 3007 TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 3008 asm volatile("sub %%rsp,%0; invvpid (%%rsp,%0,1), %1" 3009 : "+r"(data) 3010 : "r"(type)); 3011 } 3012 3013 static void invvpid_test_gp(void) 3014 { 3015 bool fault; 3016 3017 fault = test_for_exception(GP_VECTOR, &ds_invvpid, 3018 (void *)NONCANONICAL); 3019 report("INVVPID with non-canonical DS operand raises #GP", fault); 3020 } 3021 3022 static void invvpid_test_ss(void) 3023 { 3024 bool fault; 3025 3026 fault = test_for_exception(SS_VECTOR, &ss_invvpid, 3027 (void *)NONCANONICAL); 3028 report("INVVPID with non-canonical SS operand raises #SS", fault); 3029 } 3030 3031 static void invvpid_test_pf(void) 3032 { 3033 void *vpage = alloc_vpage(); 3034 bool fault; 3035 3036 fault = test_for_exception(PF_VECTOR, &ds_invvpid, vpage); 3037 report("INVVPID with unmapped operand raises #PF", fault); 3038 } 3039 3040 static void try_compat_invvpid(void *unused) 3041 { 3042 struct far_pointer32 fp = { 3043 .offset = (uintptr_t)&&invvpid, 3044 .selector = KERNEL_CS32, 3045 }; 3046 register uintptr_t rsp asm("rsp"); 3047 3048 TEST_ASSERT_MSG(fp.offset == (uintptr_t)&&invvpid, 3049 "Code address too high."); 3050 TEST_ASSERT_MSG(rsp == (u32)rsp, "Stack address too high."); 3051 3052 asm goto ("lcall *%0" : : "m" (fp) : "rax" : invvpid); 3053 return; 3054 invvpid: 3055 asm volatile (".code32;" 3056 "invvpid (%eax), %eax;" 3057 "lret;" 3058 ".code64"); 3059 __builtin_unreachable(); 3060 } 3061 3062 static void invvpid_test_compatibility_mode(void) 3063 { 3064 bool fault; 3065 3066 fault = test_for_exception(UD_VECTOR, &try_compat_invvpid, NULL); 3067 report("Compatibility mode INVVPID raises #UD", fault); 3068 } 3069 3070 static void invvpid_test_not_in_vmx_operation(void) 3071 { 3072 bool fault; 3073 3074 TEST_ASSERT(!vmx_off()); 3075 fault = test_for_exception(UD_VECTOR, &ds_invvpid, NULL); 3076 report("INVVPID outside of VMX operation raises #UD", fault); 3077 TEST_ASSERT(!vmx_on()); 3078 } 3079 3080 /* 3081 * This does not test real-address mode, virtual-8086 mode, protected mode, 3082 * or CPL > 0. 3083 */ 3084 static void invvpid_test_v2(void) 3085 { 3086 u64 msr; 3087 int i; 3088 unsigned types = 0; 3089 unsigned type; 3090 3091 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 3092 !(ctrl_cpu_rev[1].clr & CPU_VPID)) 3093 test_skip("VPID not supported"); 3094 3095 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3096 3097 if (!(msr & VPID_CAP_INVVPID)) 3098 test_skip("INVVPID not supported.\n"); 3099 3100 if (msr & VPID_CAP_INVVPID_ADDR) 3101 types |= 1u << INVVPID_ADDR; 3102 if (msr & VPID_CAP_INVVPID_CXTGLB) 3103 types |= 1u << INVVPID_CONTEXT_GLOBAL; 3104 if (msr & VPID_CAP_INVVPID_ALL) 3105 types |= 1u << INVVPID_ALL; 3106 if (msr & VPID_CAP_INVVPID_CXTLOC) 3107 types |= 1u << INVVPID_CONTEXT_LOCAL; 3108 3109 if (!types) 3110 test_skip("No INVVPID types supported.\n"); 3111 3112 for (i = -127; i < 128; i++) 3113 try_invvpid(i, 0xffff, 0); 3114 3115 /* 3116 * VPID must not be more than 16 bits. 3117 */ 3118 for (i = 0; i < 64; i++) 3119 for (type = 0; type < 4; type++) 3120 if (types & (1u << type)) 3121 try_invvpid(type, 1ul << i, 0); 3122 3123 /* 3124 * VPID must not be zero, except for "all contexts." 3125 */ 3126 for (type = 0; type < 4; type++) 3127 if (types & (1u << type)) 3128 try_invvpid(type, 0, 0); 3129 3130 /* 3131 * The gla operand is only validated for single-address INVVPID. 3132 */ 3133 if (types & (1u << INVVPID_ADDR)) 3134 try_invvpid(INVVPID_ADDR, 0xffff, NONCANONICAL); 3135 3136 invvpid_test_gp(); 3137 invvpid_test_ss(); 3138 invvpid_test_pf(); 3139 invvpid_test_compatibility_mode(); 3140 invvpid_test_not_in_vmx_operation(); 3141 } 3142 3143 #define TEST(name) { #name, .v2 = name } 3144 3145 /* name/init/guest_main/exit_handler/syscall_handler/guest_regs */ 3146 struct vmx_test vmx_tests[] = { 3147 { "null", NULL, basic_guest_main, basic_exit_handler, NULL, {0} }, 3148 { "vmenter", NULL, vmenter_main, vmenter_exit_handler, NULL, {0} }, 3149 { "preemption timer", preemption_timer_init, preemption_timer_main, 3150 preemption_timer_exit_handler, NULL, {0} }, 3151 { "control field PAT", test_ctrl_pat_init, test_ctrl_pat_main, 3152 test_ctrl_pat_exit_handler, NULL, {0} }, 3153 { "control field EFER", test_ctrl_efer_init, test_ctrl_efer_main, 3154 test_ctrl_efer_exit_handler, NULL, {0} }, 3155 { "CR shadowing", NULL, cr_shadowing_main, 3156 cr_shadowing_exit_handler, NULL, {0} }, 3157 { "I/O bitmap", iobmp_init, iobmp_main, iobmp_exit_handler, 3158 NULL, {0} }, 3159 { "instruction intercept", insn_intercept_init, insn_intercept_main, 3160 insn_intercept_exit_handler, NULL, {0} }, 3161 { "EPT A/D disabled", ept_init, ept_main, ept_exit_handler, NULL, {0} }, 3162 { "EPT A/D enabled", eptad_init, eptad_main, eptad_exit_handler, NULL, {0} }, 3163 { "PML", pml_init, pml_main, pml_exit_handler, NULL, {0} }, 3164 { "VPID", vpid_init, vpid_main, vpid_exit_handler, NULL, {0} }, 3165 { "interrupt", interrupt_init, interrupt_main, 3166 interrupt_exit_handler, NULL, {0} }, 3167 { "debug controls", dbgctls_init, dbgctls_main, dbgctls_exit_handler, 3168 NULL, {0} }, 3169 { "MSR switch", msr_switch_init, msr_switch_main, 3170 msr_switch_exit_handler, NULL, {0}, msr_switch_entry_failure }, 3171 { "vmmcall", vmmcall_init, vmmcall_main, vmmcall_exit_handler, NULL, {0} }, 3172 { "disable RDTSCP", disable_rdtscp_init, disable_rdtscp_main, 3173 disable_rdtscp_exit_handler, NULL, {0} }, 3174 { "int3", int3_init, int3_guest_main, int3_exit_handler, NULL, {0} }, 3175 { "into", into_init, into_guest_main, into_exit_handler, NULL, {0} }, 3176 { "exit_monitor_from_l2_test", NULL, exit_monitor_from_l2_main, 3177 exit_monitor_from_l2_handler, NULL, {0} }, 3178 /* Basic V2 tests. */ 3179 TEST(v2_null_test), 3180 TEST(v2_multiple_entries_test), 3181 TEST(fixture_test_case1), 3182 TEST(fixture_test_case2), 3183 /* EPT access tests. */ 3184 TEST(ept_access_test_not_present), 3185 TEST(ept_access_test_read_only), 3186 TEST(ept_access_test_write_only), 3187 TEST(ept_access_test_read_write), 3188 TEST(ept_access_test_execute_only), 3189 TEST(ept_access_test_read_execute), 3190 TEST(ept_access_test_write_execute), 3191 TEST(ept_access_test_read_write_execute), 3192 TEST(ept_access_test_reserved_bits), 3193 TEST(ept_access_test_ignored_bits), 3194 TEST(ept_access_test_paddr_not_present_ad_disabled), 3195 TEST(ept_access_test_paddr_not_present_ad_enabled), 3196 TEST(ept_access_test_paddr_read_only_ad_disabled), 3197 TEST(ept_access_test_paddr_read_only_ad_enabled), 3198 TEST(ept_access_test_paddr_read_write), 3199 TEST(ept_access_test_paddr_read_write_execute), 3200 TEST(ept_access_test_paddr_read_execute_ad_disabled), 3201 TEST(ept_access_test_paddr_read_execute_ad_enabled), 3202 TEST(ept_access_test_paddr_not_present_page_fault), 3203 TEST(ept_access_test_force_2m_page), 3204 /* Opcode tests. */ 3205 TEST(invvpid_test_v2), 3206 { NULL, NULL, NULL, NULL, NULL, {0} }, 3207 }; 3208