1 /* 2 * All test cases of nested virtualization should be in this file 3 * 4 * Author : Arthur Chunqi Li <yzt356@gmail.com> 5 */ 6 7 #include <asm/debugreg.h> 8 9 #include "vmx.h" 10 #include "msr.h" 11 #include "processor.h" 12 #include "vm.h" 13 #include "pci.h" 14 #include "fwcfg.h" 15 #include "isr.h" 16 #include "desc.h" 17 #include "apic.h" 18 #include "types.h" 19 #include "vmalloc.h" 20 #include "alloc_page.h" 21 #include "smp.h" 22 #include "delay.h" 23 24 #define NONCANONICAL 0xaaaaaaaaaaaaaaaaull 25 26 #define VPID_CAP_INVVPID_TYPES_SHIFT 40 27 28 u64 ia32_pat; 29 u64 ia32_efer; 30 void *io_bitmap_a, *io_bitmap_b; 31 u16 ioport; 32 33 unsigned long *pml4; 34 u64 eptp; 35 void *data_page1, *data_page2; 36 37 phys_addr_t pci_physaddr; 38 39 void *pml_log; 40 #define PML_INDEX 512 41 42 static inline unsigned ffs(unsigned x) 43 { 44 int pos = -1; 45 46 __asm__ __volatile__("bsf %1, %%eax; cmovnz %%eax, %0" 47 : "+r"(pos) : "rm"(x) : "eax"); 48 return pos + 1; 49 } 50 51 static inline void vmcall(void) 52 { 53 asm volatile("vmcall"); 54 } 55 56 static void basic_guest_main(void) 57 { 58 report(1, "Basic VMX test"); 59 } 60 61 static int basic_exit_handler(union exit_reason exit_reason) 62 { 63 report(0, "Basic VMX test"); 64 print_vmexit_info(exit_reason); 65 return VMX_TEST_EXIT; 66 } 67 68 static void vmenter_main(void) 69 { 70 u64 rax; 71 u64 rsp, resume_rsp; 72 73 report(1, "test vmlaunch"); 74 75 asm volatile( 76 "mov %%rsp, %0\n\t" 77 "mov %3, %%rax\n\t" 78 "vmcall\n\t" 79 "mov %%rax, %1\n\t" 80 "mov %%rsp, %2\n\t" 81 : "=r"(rsp), "=r"(rax), "=r"(resume_rsp) 82 : "g"(0xABCD)); 83 report((rax == 0xFFFF) && (rsp == resume_rsp), "test vmresume"); 84 } 85 86 static int vmenter_exit_handler(union exit_reason exit_reason) 87 { 88 u64 guest_rip = vmcs_read(GUEST_RIP); 89 90 switch (exit_reason.basic) { 91 case VMX_VMCALL: 92 if (regs.rax != 0xABCD) { 93 report(0, "test vmresume"); 94 return VMX_TEST_VMEXIT; 95 } 96 regs.rax = 0xFFFF; 97 vmcs_write(GUEST_RIP, guest_rip + 3); 98 return VMX_TEST_RESUME; 99 default: 100 report(0, "test vmresume"); 101 print_vmexit_info(exit_reason); 102 } 103 return VMX_TEST_VMEXIT; 104 } 105 106 u32 preempt_scale; 107 volatile unsigned long long tsc_val; 108 volatile u32 preempt_val; 109 u64 saved_rip; 110 111 static int preemption_timer_init(struct vmcs *vmcs) 112 { 113 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 114 printf("\tPreemption timer is not supported\n"); 115 return VMX_TEST_EXIT; 116 } 117 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 118 preempt_val = 10000000; 119 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 120 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 121 122 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 123 printf("\tSave preemption value is not supported\n"); 124 125 return VMX_TEST_START; 126 } 127 128 static void preemption_timer_main(void) 129 { 130 tsc_val = rdtsc(); 131 if (ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) { 132 vmx_set_test_stage(0); 133 vmcall(); 134 if (vmx_get_test_stage() == 1) 135 vmcall(); 136 } 137 vmx_set_test_stage(1); 138 while (vmx_get_test_stage() == 1) { 139 if (((rdtsc() - tsc_val) >> preempt_scale) 140 > 10 * preempt_val) { 141 vmx_set_test_stage(2); 142 vmcall(); 143 } 144 } 145 tsc_val = rdtsc(); 146 asm volatile ("hlt"); 147 vmcall(); 148 vmx_set_test_stage(5); 149 vmcall(); 150 } 151 152 static int preemption_timer_exit_handler(union exit_reason exit_reason) 153 { 154 bool guest_halted; 155 u64 guest_rip; 156 u32 insn_len; 157 u32 ctrl_exit; 158 159 guest_rip = vmcs_read(GUEST_RIP); 160 insn_len = vmcs_read(EXI_INST_LEN); 161 switch (exit_reason.basic) { 162 case VMX_PREEMPT: 163 switch (vmx_get_test_stage()) { 164 case 1: 165 case 2: 166 report(((rdtsc() - tsc_val) >> preempt_scale) >= preempt_val, 167 "busy-wait for preemption timer"); 168 vmx_set_test_stage(3); 169 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 170 return VMX_TEST_RESUME; 171 case 3: 172 guest_halted = 173 (vmcs_read(GUEST_ACTV_STATE) == ACTV_HLT); 174 report(((rdtsc() - tsc_val) >> preempt_scale) >= preempt_val 175 && guest_halted, 176 "preemption timer during hlt"); 177 vmx_set_test_stage(4); 178 vmcs_write(PIN_CONTROLS, 179 vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 180 vmcs_write(EXI_CONTROLS, 181 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_PREEMPT); 182 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 183 return VMX_TEST_RESUME; 184 case 4: 185 report(saved_rip == guest_rip, 186 "preemption timer with 0 value"); 187 break; 188 default: 189 report(false, "Invalid stage."); 190 print_vmexit_info(exit_reason); 191 break; 192 } 193 break; 194 case VMX_VMCALL: 195 vmcs_write(GUEST_RIP, guest_rip + insn_len); 196 switch (vmx_get_test_stage()) { 197 case 0: 198 report(vmcs_read(PREEMPT_TIMER_VALUE) == preempt_val, 199 "Keep preemption value"); 200 vmx_set_test_stage(1); 201 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 202 ctrl_exit = (vmcs_read(EXI_CONTROLS) | 203 EXI_SAVE_PREEMPT) & ctrl_exit_rev.clr; 204 vmcs_write(EXI_CONTROLS, ctrl_exit); 205 return VMX_TEST_RESUME; 206 case 1: 207 report(vmcs_read(PREEMPT_TIMER_VALUE) < preempt_val, 208 "Save preemption value"); 209 return VMX_TEST_RESUME; 210 case 2: 211 report(0, "busy-wait for preemption timer"); 212 vmx_set_test_stage(3); 213 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 214 return VMX_TEST_RESUME; 215 case 3: 216 report(0, "preemption timer during hlt"); 217 vmx_set_test_stage(4); 218 /* fall through */ 219 case 4: 220 vmcs_write(PIN_CONTROLS, 221 vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 222 vmcs_write(PREEMPT_TIMER_VALUE, 0); 223 saved_rip = guest_rip + insn_len; 224 return VMX_TEST_RESUME; 225 case 5: 226 report(0, 227 "preemption timer with 0 value (vmcall stage 5)"); 228 break; 229 default: 230 // Should not reach here 231 report(false, "unexpected stage, %d", 232 vmx_get_test_stage()); 233 print_vmexit_info(exit_reason); 234 return VMX_TEST_VMEXIT; 235 } 236 break; 237 default: 238 report(false, "Unknown exit reason, 0x%x", exit_reason.full); 239 print_vmexit_info(exit_reason); 240 } 241 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 242 return VMX_TEST_VMEXIT; 243 } 244 245 static void msr_bmp_init(void) 246 { 247 void *msr_bitmap; 248 u32 ctrl_cpu0; 249 250 msr_bitmap = alloc_page(); 251 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 252 ctrl_cpu0 |= CPU_MSR_BITMAP; 253 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 254 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 255 } 256 257 static void *get_msr_bitmap(void) 258 { 259 void *msr_bitmap; 260 261 if (vmcs_read(CPU_EXEC_CTRL0) & CPU_MSR_BITMAP) { 262 msr_bitmap = (void *)vmcs_read(MSR_BITMAP); 263 } else { 264 msr_bitmap = alloc_page(); 265 memset(msr_bitmap, 0xff, PAGE_SIZE); 266 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 267 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_MSR_BITMAP); 268 } 269 270 return msr_bitmap; 271 } 272 273 static void disable_intercept_for_x2apic_msrs(void) 274 { 275 unsigned long *msr_bitmap = (unsigned long *)get_msr_bitmap(); 276 u32 msr; 277 278 for (msr = APIC_BASE_MSR; 279 msr < (APIC_BASE_MSR+0xff); 280 msr += BITS_PER_LONG) { 281 unsigned int word = msr / BITS_PER_LONG; 282 283 msr_bitmap[word] = 0; 284 msr_bitmap[word + (0x800 / sizeof(long))] = 0; 285 } 286 } 287 288 static int test_ctrl_pat_init(struct vmcs *vmcs) 289 { 290 u64 ctrl_ent; 291 u64 ctrl_exi; 292 293 msr_bmp_init(); 294 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT) && 295 !(ctrl_exit_rev.clr & EXI_LOAD_PAT) && 296 !(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 297 printf("\tSave/load PAT is not supported\n"); 298 return 1; 299 } 300 301 ctrl_ent = vmcs_read(ENT_CONTROLS); 302 ctrl_exi = vmcs_read(EXI_CONTROLS); 303 ctrl_ent |= ctrl_enter_rev.clr & ENT_LOAD_PAT; 304 ctrl_exi |= ctrl_exit_rev.clr & (EXI_SAVE_PAT | EXI_LOAD_PAT); 305 vmcs_write(ENT_CONTROLS, ctrl_ent); 306 vmcs_write(EXI_CONTROLS, ctrl_exi); 307 ia32_pat = rdmsr(MSR_IA32_CR_PAT); 308 vmcs_write(GUEST_PAT, 0x0); 309 vmcs_write(HOST_PAT, ia32_pat); 310 return VMX_TEST_START; 311 } 312 313 static void test_ctrl_pat_main(void) 314 { 315 u64 guest_ia32_pat; 316 317 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 318 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) 319 printf("\tENT_LOAD_PAT is not supported.\n"); 320 else { 321 if (guest_ia32_pat != 0) { 322 report(0, "Entry load PAT"); 323 return; 324 } 325 } 326 wrmsr(MSR_IA32_CR_PAT, 0x6); 327 vmcall(); 328 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 329 if (ctrl_enter_rev.clr & ENT_LOAD_PAT) 330 report(guest_ia32_pat == ia32_pat, "Entry load PAT"); 331 } 332 333 static int test_ctrl_pat_exit_handler(union exit_reason exit_reason) 334 { 335 u64 guest_rip; 336 u64 guest_pat; 337 338 guest_rip = vmcs_read(GUEST_RIP); 339 switch (exit_reason.basic) { 340 case VMX_VMCALL: 341 guest_pat = vmcs_read(GUEST_PAT); 342 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT)) { 343 printf("\tEXI_SAVE_PAT is not supported\n"); 344 vmcs_write(GUEST_PAT, 0x6); 345 } else { 346 report(guest_pat == 0x6, "Exit save PAT"); 347 } 348 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) 349 printf("\tEXI_LOAD_PAT is not supported\n"); 350 else 351 report(rdmsr(MSR_IA32_CR_PAT) == ia32_pat, 352 "Exit load PAT"); 353 vmcs_write(GUEST_PAT, ia32_pat); 354 vmcs_write(GUEST_RIP, guest_rip + 3); 355 return VMX_TEST_RESUME; 356 default: 357 printf("ERROR : Unknown exit reason, 0x%x.\n", exit_reason.full); 358 break; 359 } 360 return VMX_TEST_VMEXIT; 361 } 362 363 static int test_ctrl_efer_init(struct vmcs *vmcs) 364 { 365 u64 ctrl_ent; 366 u64 ctrl_exi; 367 368 msr_bmp_init(); 369 ctrl_ent = vmcs_read(ENT_CONTROLS) | ENT_LOAD_EFER; 370 ctrl_exi = vmcs_read(EXI_CONTROLS) | EXI_SAVE_EFER | EXI_LOAD_EFER; 371 vmcs_write(ENT_CONTROLS, ctrl_ent & ctrl_enter_rev.clr); 372 vmcs_write(EXI_CONTROLS, ctrl_exi & ctrl_exit_rev.clr); 373 ia32_efer = rdmsr(MSR_EFER); 374 vmcs_write(GUEST_EFER, ia32_efer ^ EFER_NX); 375 vmcs_write(HOST_EFER, ia32_efer ^ EFER_NX); 376 return VMX_TEST_START; 377 } 378 379 static void test_ctrl_efer_main(void) 380 { 381 u64 guest_ia32_efer; 382 383 guest_ia32_efer = rdmsr(MSR_EFER); 384 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) 385 printf("\tENT_LOAD_EFER is not supported.\n"); 386 else { 387 if (guest_ia32_efer != (ia32_efer ^ EFER_NX)) { 388 report(0, "Entry load EFER"); 389 return; 390 } 391 } 392 wrmsr(MSR_EFER, ia32_efer); 393 vmcall(); 394 guest_ia32_efer = rdmsr(MSR_EFER); 395 if (ctrl_enter_rev.clr & ENT_LOAD_EFER) 396 report(guest_ia32_efer == ia32_efer, "Entry load EFER"); 397 } 398 399 static int test_ctrl_efer_exit_handler(union exit_reason exit_reason) 400 { 401 u64 guest_rip; 402 u64 guest_efer; 403 404 guest_rip = vmcs_read(GUEST_RIP); 405 switch (exit_reason.basic) { 406 case VMX_VMCALL: 407 guest_efer = vmcs_read(GUEST_EFER); 408 if (!(ctrl_exit_rev.clr & EXI_SAVE_EFER)) { 409 printf("\tEXI_SAVE_EFER is not supported\n"); 410 vmcs_write(GUEST_EFER, ia32_efer); 411 } else { 412 report(guest_efer == ia32_efer, "Exit save EFER"); 413 } 414 if (!(ctrl_exit_rev.clr & EXI_LOAD_EFER)) { 415 printf("\tEXI_LOAD_EFER is not supported\n"); 416 wrmsr(MSR_EFER, ia32_efer ^ EFER_NX); 417 } else { 418 report(rdmsr(MSR_EFER) == (ia32_efer ^ EFER_NX), 419 "Exit load EFER"); 420 } 421 vmcs_write(GUEST_PAT, ia32_efer); 422 vmcs_write(GUEST_RIP, guest_rip + 3); 423 return VMX_TEST_RESUME; 424 default: 425 printf("ERROR : Unknown exit reason, 0x%x.\n", exit_reason.full); 426 break; 427 } 428 return VMX_TEST_VMEXIT; 429 } 430 431 u32 guest_cr0, guest_cr4; 432 433 static void cr_shadowing_main(void) 434 { 435 u32 cr0, cr4, tmp; 436 437 // Test read through 438 vmx_set_test_stage(0); 439 guest_cr0 = read_cr0(); 440 if (vmx_get_test_stage() == 1) 441 report(0, "Read through CR0"); 442 else 443 vmcall(); 444 vmx_set_test_stage(1); 445 guest_cr4 = read_cr4(); 446 if (vmx_get_test_stage() == 2) 447 report(0, "Read through CR4"); 448 else 449 vmcall(); 450 // Test write through 451 guest_cr0 = guest_cr0 ^ (X86_CR0_TS | X86_CR0_MP); 452 guest_cr4 = guest_cr4 ^ (X86_CR4_TSD | X86_CR4_DE); 453 vmx_set_test_stage(2); 454 write_cr0(guest_cr0); 455 if (vmx_get_test_stage() == 3) 456 report(0, "Write throuth CR0"); 457 else 458 vmcall(); 459 vmx_set_test_stage(3); 460 write_cr4(guest_cr4); 461 if (vmx_get_test_stage() == 4) 462 report(0, "Write through CR4"); 463 else 464 vmcall(); 465 // Test read shadow 466 vmx_set_test_stage(4); 467 vmcall(); 468 cr0 = read_cr0(); 469 if (vmx_get_test_stage() != 5) 470 report(cr0 == guest_cr0, "Read shadowing CR0"); 471 vmx_set_test_stage(5); 472 cr4 = read_cr4(); 473 if (vmx_get_test_stage() != 6) 474 report(cr4 == guest_cr4, "Read shadowing CR4"); 475 // Test write shadow (same value with shadow) 476 vmx_set_test_stage(6); 477 write_cr0(guest_cr0); 478 if (vmx_get_test_stage() == 7) 479 report(0, "Write shadowing CR0 (same value with shadow)"); 480 else 481 vmcall(); 482 vmx_set_test_stage(7); 483 write_cr4(guest_cr4); 484 if (vmx_get_test_stage() == 8) 485 report(0, "Write shadowing CR4 (same value with shadow)"); 486 else 487 vmcall(); 488 // Test write shadow (different value) 489 vmx_set_test_stage(8); 490 tmp = guest_cr0 ^ X86_CR0_TS; 491 asm volatile("mov %0, %%rsi\n\t" 492 "mov %%rsi, %%cr0\n\t" 493 ::"m"(tmp) 494 :"rsi", "memory", "cc"); 495 report(vmx_get_test_stage() == 9, 496 "Write shadowing different X86_CR0_TS"); 497 vmx_set_test_stage(9); 498 tmp = guest_cr0 ^ X86_CR0_MP; 499 asm volatile("mov %0, %%rsi\n\t" 500 "mov %%rsi, %%cr0\n\t" 501 ::"m"(tmp) 502 :"rsi", "memory", "cc"); 503 report(vmx_get_test_stage() == 10, 504 "Write shadowing different X86_CR0_MP"); 505 vmx_set_test_stage(10); 506 tmp = guest_cr4 ^ X86_CR4_TSD; 507 asm volatile("mov %0, %%rsi\n\t" 508 "mov %%rsi, %%cr4\n\t" 509 ::"m"(tmp) 510 :"rsi", "memory", "cc"); 511 report(vmx_get_test_stage() == 11, 512 "Write shadowing different X86_CR4_TSD"); 513 vmx_set_test_stage(11); 514 tmp = guest_cr4 ^ X86_CR4_DE; 515 asm volatile("mov %0, %%rsi\n\t" 516 "mov %%rsi, %%cr4\n\t" 517 ::"m"(tmp) 518 :"rsi", "memory", "cc"); 519 report(vmx_get_test_stage() == 12, 520 "Write shadowing different X86_CR4_DE"); 521 } 522 523 static int cr_shadowing_exit_handler(union exit_reason exit_reason) 524 { 525 u64 guest_rip; 526 u32 insn_len; 527 u32 exit_qual; 528 529 guest_rip = vmcs_read(GUEST_RIP); 530 insn_len = vmcs_read(EXI_INST_LEN); 531 exit_qual = vmcs_read(EXI_QUALIFICATION); 532 switch (exit_reason.basic) { 533 case VMX_VMCALL: 534 switch (vmx_get_test_stage()) { 535 case 0: 536 report(guest_cr0 == vmcs_read(GUEST_CR0), 537 "Read through CR0"); 538 break; 539 case 1: 540 report(guest_cr4 == vmcs_read(GUEST_CR4), 541 "Read through CR4"); 542 break; 543 case 2: 544 report(guest_cr0 == vmcs_read(GUEST_CR0), 545 "Write through CR0"); 546 break; 547 case 3: 548 report(guest_cr4 == vmcs_read(GUEST_CR4), 549 "Write through CR4"); 550 break; 551 case 4: 552 guest_cr0 = vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP); 553 guest_cr4 = vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE); 554 vmcs_write(CR0_MASK, X86_CR0_TS | X86_CR0_MP); 555 vmcs_write(CR0_READ_SHADOW, guest_cr0 & (X86_CR0_TS | X86_CR0_MP)); 556 vmcs_write(CR4_MASK, X86_CR4_TSD | X86_CR4_DE); 557 vmcs_write(CR4_READ_SHADOW, guest_cr4 & (X86_CR4_TSD | X86_CR4_DE)); 558 break; 559 case 6: 560 report(guest_cr0 == (vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP)), 561 "Write shadowing CR0 (same value)"); 562 break; 563 case 7: 564 report(guest_cr4 == (vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE)), 565 "Write shadowing CR4 (same value)"); 566 break; 567 default: 568 // Should not reach here 569 report(false, "unexpected stage, %d", 570 vmx_get_test_stage()); 571 print_vmexit_info(exit_reason); 572 return VMX_TEST_VMEXIT; 573 } 574 vmcs_write(GUEST_RIP, guest_rip + insn_len); 575 return VMX_TEST_RESUME; 576 case VMX_CR: 577 switch (vmx_get_test_stage()) { 578 case 4: 579 report(0, "Read shadowing CR0"); 580 vmx_inc_test_stage(); 581 break; 582 case 5: 583 report(0, "Read shadowing CR4"); 584 vmx_inc_test_stage(); 585 break; 586 case 6: 587 report(0, "Write shadowing CR0 (same value)"); 588 vmx_inc_test_stage(); 589 break; 590 case 7: 591 report(0, "Write shadowing CR4 (same value)"); 592 vmx_inc_test_stage(); 593 break; 594 case 8: 595 case 9: 596 // 0x600 encodes "mov %esi, %cr0" 597 if (exit_qual == 0x600) 598 vmx_inc_test_stage(); 599 break; 600 case 10: 601 case 11: 602 // 0x604 encodes "mov %esi, %cr4" 603 if (exit_qual == 0x604) 604 vmx_inc_test_stage(); 605 break; 606 default: 607 // Should not reach here 608 report(false, "unexpected stage, %d", 609 vmx_get_test_stage()); 610 print_vmexit_info(exit_reason); 611 return VMX_TEST_VMEXIT; 612 } 613 vmcs_write(GUEST_RIP, guest_rip + insn_len); 614 return VMX_TEST_RESUME; 615 default: 616 report(false, "Unknown exit reason, 0x%x", exit_reason.full); 617 print_vmexit_info(exit_reason); 618 } 619 return VMX_TEST_VMEXIT; 620 } 621 622 static int iobmp_init(struct vmcs *vmcs) 623 { 624 u32 ctrl_cpu0; 625 626 io_bitmap_a = alloc_page(); 627 io_bitmap_b = alloc_page(); 628 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 629 ctrl_cpu0 |= CPU_IO_BITMAP; 630 ctrl_cpu0 &= (~CPU_IO); 631 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 632 vmcs_write(IO_BITMAP_A, (u64)io_bitmap_a); 633 vmcs_write(IO_BITMAP_B, (u64)io_bitmap_b); 634 return VMX_TEST_START; 635 } 636 637 static void iobmp_main(void) 638 { 639 // stage 0, test IO pass 640 vmx_set_test_stage(0); 641 inb(0x5000); 642 outb(0x0, 0x5000); 643 report(vmx_get_test_stage() == 0, "I/O bitmap - I/O pass"); 644 // test IO width, in/out 645 ((u8 *)io_bitmap_a)[0] = 0xFF; 646 vmx_set_test_stage(2); 647 inb(0x0); 648 report(vmx_get_test_stage() == 3, "I/O bitmap - trap in"); 649 vmx_set_test_stage(3); 650 outw(0x0, 0x0); 651 report(vmx_get_test_stage() == 4, "I/O bitmap - trap out"); 652 vmx_set_test_stage(4); 653 inl(0x0); 654 report(vmx_get_test_stage() == 5, "I/O bitmap - I/O width, long"); 655 // test low/high IO port 656 vmx_set_test_stage(5); 657 ((u8 *)io_bitmap_a)[0x5000 / 8] = (1 << (0x5000 % 8)); 658 inb(0x5000); 659 report(vmx_get_test_stage() == 6, "I/O bitmap - I/O port, low part"); 660 vmx_set_test_stage(6); 661 ((u8 *)io_bitmap_b)[0x1000 / 8] = (1 << (0x1000 % 8)); 662 inb(0x9000); 663 report(vmx_get_test_stage() == 7, "I/O bitmap - I/O port, high part"); 664 // test partial pass 665 vmx_set_test_stage(7); 666 inl(0x4FFF); 667 report(vmx_get_test_stage() == 8, "I/O bitmap - partial pass"); 668 // test overrun 669 vmx_set_test_stage(8); 670 memset(io_bitmap_a, 0x0, PAGE_SIZE); 671 memset(io_bitmap_b, 0x0, PAGE_SIZE); 672 inl(0xFFFF); 673 report(vmx_get_test_stage() == 9, "I/O bitmap - overrun"); 674 vmx_set_test_stage(9); 675 vmcall(); 676 outb(0x0, 0x0); 677 report(vmx_get_test_stage() == 9, 678 "I/O bitmap - ignore unconditional exiting"); 679 vmx_set_test_stage(10); 680 vmcall(); 681 outb(0x0, 0x0); 682 report(vmx_get_test_stage() == 11, 683 "I/O bitmap - unconditional exiting"); 684 } 685 686 static int iobmp_exit_handler(union exit_reason exit_reason) 687 { 688 u64 guest_rip; 689 ulong exit_qual; 690 u32 insn_len, ctrl_cpu0; 691 692 guest_rip = vmcs_read(GUEST_RIP); 693 exit_qual = vmcs_read(EXI_QUALIFICATION); 694 insn_len = vmcs_read(EXI_INST_LEN); 695 switch (exit_reason.basic) { 696 case VMX_IO: 697 switch (vmx_get_test_stage()) { 698 case 0: 699 case 1: 700 vmx_inc_test_stage(); 701 break; 702 case 2: 703 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_BYTE, 704 "I/O bitmap - I/O width, byte"); 705 report(exit_qual & VMX_IO_IN, 706 "I/O bitmap - I/O direction, in"); 707 vmx_inc_test_stage(); 708 break; 709 case 3: 710 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_WORD, 711 "I/O bitmap - I/O width, word"); 712 report(!(exit_qual & VMX_IO_IN), 713 "I/O bitmap - I/O direction, out"); 714 vmx_inc_test_stage(); 715 break; 716 case 4: 717 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_LONG, 718 "I/O bitmap - I/O width, long"); 719 vmx_inc_test_stage(); 720 break; 721 case 5: 722 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x5000) 723 vmx_inc_test_stage(); 724 break; 725 case 6: 726 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x9000) 727 vmx_inc_test_stage(); 728 break; 729 case 7: 730 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x4FFF) 731 vmx_inc_test_stage(); 732 break; 733 case 8: 734 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0xFFFF) 735 vmx_inc_test_stage(); 736 break; 737 case 9: 738 case 10: 739 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 740 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0 & ~CPU_IO); 741 vmx_inc_test_stage(); 742 break; 743 default: 744 // Should not reach here 745 report(false, "unexpected stage, %d", 746 vmx_get_test_stage()); 747 print_vmexit_info(exit_reason); 748 return VMX_TEST_VMEXIT; 749 } 750 vmcs_write(GUEST_RIP, guest_rip + insn_len); 751 return VMX_TEST_RESUME; 752 case VMX_VMCALL: 753 switch (vmx_get_test_stage()) { 754 case 9: 755 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 756 ctrl_cpu0 |= CPU_IO | CPU_IO_BITMAP; 757 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 758 break; 759 case 10: 760 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 761 ctrl_cpu0 = (ctrl_cpu0 & ~CPU_IO_BITMAP) | CPU_IO; 762 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 763 break; 764 default: 765 // Should not reach here 766 report(false, "unexpected stage, %d", 767 vmx_get_test_stage()); 768 print_vmexit_info(exit_reason); 769 return VMX_TEST_VMEXIT; 770 } 771 vmcs_write(GUEST_RIP, guest_rip + insn_len); 772 return VMX_TEST_RESUME; 773 default: 774 printf("guest_rip = %#lx\n", guest_rip); 775 printf("\tERROR : Unknown exit reason, 0x%x\n", exit_reason.full); 776 break; 777 } 778 return VMX_TEST_VMEXIT; 779 } 780 781 #define INSN_CPU0 0 782 #define INSN_CPU1 1 783 #define INSN_ALWAYS_TRAP 2 784 785 #define FIELD_EXIT_QUAL (1 << 0) 786 #define FIELD_INSN_INFO (1 << 1) 787 788 asm( 789 "insn_hlt: hlt;ret\n\t" 790 "insn_invlpg: invlpg 0x12345678;ret\n\t" 791 "insn_mwait: xor %eax, %eax; xor %ecx, %ecx; mwait;ret\n\t" 792 "insn_rdpmc: xor %ecx, %ecx; rdpmc;ret\n\t" 793 "insn_rdtsc: rdtsc;ret\n\t" 794 "insn_cr3_load: mov cr3,%rax; mov %rax,%cr3;ret\n\t" 795 "insn_cr3_store: mov %cr3,%rax;ret\n\t" 796 #ifdef __x86_64__ 797 "insn_cr8_load: xor %eax, %eax; mov %rax,%cr8;ret\n\t" 798 "insn_cr8_store: mov %cr8,%rax;ret\n\t" 799 #endif 800 "insn_monitor: xor %eax, %eax; xor %ecx, %ecx; xor %edx, %edx; monitor;ret\n\t" 801 "insn_pause: pause;ret\n\t" 802 "insn_wbinvd: wbinvd;ret\n\t" 803 "insn_cpuid: mov $10, %eax; cpuid;ret\n\t" 804 "insn_invd: invd;ret\n\t" 805 "insn_sgdt: sgdt gdt64_desc;ret\n\t" 806 "insn_lgdt: lgdt gdt64_desc;ret\n\t" 807 "insn_sidt: sidt idt_descr;ret\n\t" 808 "insn_lidt: lidt idt_descr;ret\n\t" 809 "insn_sldt: sldt %ax;ret\n\t" 810 "insn_lldt: xor %eax, %eax; lldt %ax;ret\n\t" 811 "insn_str: str %ax;ret\n\t" 812 "insn_rdrand: rdrand %rax;ret\n\t" 813 "insn_rdseed: rdseed %rax;ret\n\t" 814 ); 815 extern void insn_hlt(void); 816 extern void insn_invlpg(void); 817 extern void insn_mwait(void); 818 extern void insn_rdpmc(void); 819 extern void insn_rdtsc(void); 820 extern void insn_cr3_load(void); 821 extern void insn_cr3_store(void); 822 #ifdef __x86_64__ 823 extern void insn_cr8_load(void); 824 extern void insn_cr8_store(void); 825 #endif 826 extern void insn_monitor(void); 827 extern void insn_pause(void); 828 extern void insn_wbinvd(void); 829 extern void insn_sgdt(void); 830 extern void insn_lgdt(void); 831 extern void insn_sidt(void); 832 extern void insn_lidt(void); 833 extern void insn_sldt(void); 834 extern void insn_lldt(void); 835 extern void insn_str(void); 836 extern void insn_cpuid(void); 837 extern void insn_invd(void); 838 extern void insn_rdrand(void); 839 extern void insn_rdseed(void); 840 841 u32 cur_insn; 842 u64 cr3; 843 844 #define X86_FEATURE_MONITOR (1 << 3) 845 846 typedef bool (*supported_fn)(void); 847 848 static bool monitor_supported(void) 849 { 850 return this_cpu_has(X86_FEATURE_MWAIT); 851 } 852 853 struct insn_table { 854 const char *name; 855 u32 flag; 856 void (*insn_func)(void); 857 u32 type; 858 u32 reason; 859 ulong exit_qual; 860 u32 insn_info; 861 // Use FIELD_EXIT_QUAL and FIELD_INSN_INFO to define 862 // which field need to be tested, reason is always tested 863 u32 test_field; 864 const supported_fn supported_fn; 865 u8 disabled; 866 }; 867 868 /* 869 * Add more test cases of instruction intercept here. Elements in this 870 * table is: 871 * name/control flag/insn function/type/exit reason/exit qulification/ 872 * instruction info/field to test 873 * The last field defines which fields (exit_qual and insn_info) need to be 874 * tested in exit handler. If set to 0, only "reason" is checked. 875 */ 876 static struct insn_table insn_table[] = { 877 // Flags for Primary Processor-Based VM-Execution Controls 878 {"HLT", CPU_HLT, insn_hlt, INSN_CPU0, 12, 0, 0, 0}, 879 {"INVLPG", CPU_INVLPG, insn_invlpg, INSN_CPU0, 14, 880 0x12345678, 0, FIELD_EXIT_QUAL}, 881 {"MWAIT", CPU_MWAIT, insn_mwait, INSN_CPU0, 36, 0, 0, 0, &monitor_supported}, 882 {"RDPMC", CPU_RDPMC, insn_rdpmc, INSN_CPU0, 15, 0, 0, 0}, 883 {"RDTSC", CPU_RDTSC, insn_rdtsc, INSN_CPU0, 16, 0, 0, 0}, 884 {"CR3 load", CPU_CR3_LOAD, insn_cr3_load, INSN_CPU0, 28, 0x3, 0, 885 FIELD_EXIT_QUAL}, 886 {"CR3 store", CPU_CR3_STORE, insn_cr3_store, INSN_CPU0, 28, 0x13, 0, 887 FIELD_EXIT_QUAL}, 888 #ifdef __x86_64__ 889 {"CR8 load", CPU_CR8_LOAD, insn_cr8_load, INSN_CPU0, 28, 0x8, 0, 890 FIELD_EXIT_QUAL}, 891 {"CR8 store", CPU_CR8_STORE, insn_cr8_store, INSN_CPU0, 28, 0x18, 0, 892 FIELD_EXIT_QUAL}, 893 #endif 894 {"MONITOR", CPU_MONITOR, insn_monitor, INSN_CPU0, 39, 0, 0, 0, &monitor_supported}, 895 {"PAUSE", CPU_PAUSE, insn_pause, INSN_CPU0, 40, 0, 0, 0}, 896 // Flags for Secondary Processor-Based VM-Execution Controls 897 {"WBINVD", CPU_WBINVD, insn_wbinvd, INSN_CPU1, 54, 0, 0, 0}, 898 {"DESC_TABLE (SGDT)", CPU_DESC_TABLE, insn_sgdt, INSN_CPU1, 46, 0, 0, 0}, 899 {"DESC_TABLE (LGDT)", CPU_DESC_TABLE, insn_lgdt, INSN_CPU1, 46, 0, 0, 0}, 900 {"DESC_TABLE (SIDT)", CPU_DESC_TABLE, insn_sidt, INSN_CPU1, 46, 0, 0, 0}, 901 {"DESC_TABLE (LIDT)", CPU_DESC_TABLE, insn_lidt, INSN_CPU1, 46, 0, 0, 0}, 902 {"DESC_TABLE (SLDT)", CPU_DESC_TABLE, insn_sldt, INSN_CPU1, 47, 0, 0, 0}, 903 {"DESC_TABLE (LLDT)", CPU_DESC_TABLE, insn_lldt, INSN_CPU1, 47, 0, 0, 0}, 904 {"DESC_TABLE (STR)", CPU_DESC_TABLE, insn_str, INSN_CPU1, 47, 0, 0, 0}, 905 /* LTR causes a #GP if done with a busy selector, so it is not tested. */ 906 {"RDRAND", CPU_RDRAND, insn_rdrand, INSN_CPU1, VMX_RDRAND, 0, 0, 0}, 907 {"RDSEED", CPU_RDSEED, insn_rdseed, INSN_CPU1, VMX_RDSEED, 0, 0, 0}, 908 // Instructions always trap 909 {"CPUID", 0, insn_cpuid, INSN_ALWAYS_TRAP, 10, 0, 0, 0}, 910 {"INVD", 0, insn_invd, INSN_ALWAYS_TRAP, 13, 0, 0, 0}, 911 // Instructions never trap 912 {NULL}, 913 }; 914 915 static int insn_intercept_init(struct vmcs *vmcs) 916 { 917 u32 ctrl_cpu, cur_insn; 918 919 ctrl_cpu = ctrl_cpu_rev[0].set | CPU_SECONDARY; 920 ctrl_cpu &= ctrl_cpu_rev[0].clr; 921 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu); 922 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu_rev[1].set); 923 cr3 = read_cr3(); 924 925 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 926 if (insn_table[cur_insn].supported_fn == NULL) 927 continue; 928 insn_table[cur_insn].disabled = !insn_table[cur_insn].supported_fn(); 929 } 930 return VMX_TEST_START; 931 } 932 933 static void insn_intercept_main(void) 934 { 935 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 936 vmx_set_test_stage(cur_insn * 2); 937 if ((insn_table[cur_insn].type == INSN_CPU0 && 938 !(ctrl_cpu_rev[0].clr & insn_table[cur_insn].flag)) || 939 (insn_table[cur_insn].type == INSN_CPU1 && 940 !(ctrl_cpu_rev[1].clr & insn_table[cur_insn].flag))) { 941 printf("\tCPU_CTRL%d.CPU_%s is not supported.\n", 942 insn_table[cur_insn].type - INSN_CPU0, 943 insn_table[cur_insn].name); 944 continue; 945 } 946 947 if (insn_table[cur_insn].disabled) { 948 printf("\tFeature required for %s is not supported.\n", 949 insn_table[cur_insn].name); 950 continue; 951 } 952 953 if ((insn_table[cur_insn].type == INSN_CPU0 && 954 !(ctrl_cpu_rev[0].set & insn_table[cur_insn].flag)) || 955 (insn_table[cur_insn].type == INSN_CPU1 && 956 !(ctrl_cpu_rev[1].set & insn_table[cur_insn].flag))) { 957 /* skip hlt, it stalls the guest and is tested below */ 958 if (insn_table[cur_insn].insn_func != insn_hlt) 959 insn_table[cur_insn].insn_func(); 960 report(vmx_get_test_stage() == cur_insn * 2, 961 "execute %s", 962 insn_table[cur_insn].name); 963 } else if (insn_table[cur_insn].type != INSN_ALWAYS_TRAP) 964 printf("\tCPU_CTRL%d.CPU_%s always traps.\n", 965 insn_table[cur_insn].type - INSN_CPU0, 966 insn_table[cur_insn].name); 967 968 vmcall(); 969 970 insn_table[cur_insn].insn_func(); 971 report(vmx_get_test_stage() == cur_insn * 2 + 1, 972 "intercept %s", 973 insn_table[cur_insn].name); 974 975 vmx_set_test_stage(cur_insn * 2 + 1); 976 vmcall(); 977 } 978 } 979 980 static int insn_intercept_exit_handler(union exit_reason exit_reason) 981 { 982 u64 guest_rip; 983 ulong exit_qual; 984 u32 insn_len; 985 u32 insn_info; 986 bool pass; 987 988 guest_rip = vmcs_read(GUEST_RIP); 989 exit_qual = vmcs_read(EXI_QUALIFICATION); 990 insn_len = vmcs_read(EXI_INST_LEN); 991 insn_info = vmcs_read(EXI_INST_INFO); 992 993 if (exit_reason.basic == VMX_VMCALL) { 994 u32 val = 0; 995 996 if (insn_table[cur_insn].type == INSN_CPU0) 997 val = vmcs_read(CPU_EXEC_CTRL0); 998 else if (insn_table[cur_insn].type == INSN_CPU1) 999 val = vmcs_read(CPU_EXEC_CTRL1); 1000 1001 if (vmx_get_test_stage() & 1) 1002 val &= ~insn_table[cur_insn].flag; 1003 else 1004 val |= insn_table[cur_insn].flag; 1005 1006 if (insn_table[cur_insn].type == INSN_CPU0) 1007 vmcs_write(CPU_EXEC_CTRL0, val | ctrl_cpu_rev[0].set); 1008 else if (insn_table[cur_insn].type == INSN_CPU1) 1009 vmcs_write(CPU_EXEC_CTRL1, val | ctrl_cpu_rev[1].set); 1010 } else { 1011 pass = (cur_insn * 2 == vmx_get_test_stage()) && 1012 insn_table[cur_insn].reason == exit_reason.full; 1013 if (insn_table[cur_insn].test_field & FIELD_EXIT_QUAL && 1014 insn_table[cur_insn].exit_qual != exit_qual) 1015 pass = false; 1016 if (insn_table[cur_insn].test_field & FIELD_INSN_INFO && 1017 insn_table[cur_insn].insn_info != insn_info) 1018 pass = false; 1019 if (pass) 1020 vmx_inc_test_stage(); 1021 } 1022 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1023 return VMX_TEST_RESUME; 1024 } 1025 1026 /** 1027 * __setup_ept - Setup the VMCS fields to enable Extended Page Tables (EPT) 1028 * @hpa: Host physical address of the top-level, a.k.a. root, EPT table 1029 * @enable_ad: Whether or not to enable Access/Dirty bits for EPT entries 1030 * 1031 * Returns 0 on success, 1 on failure. 1032 * 1033 * Note that @hpa doesn't need to point at actual memory if VM-Launch is 1034 * expected to fail, e.g. setup_dummy_ept() arbitrarily passes '0' to satisfy 1035 * the various EPTP consistency checks, but doesn't ensure backing for HPA '0'. 1036 */ 1037 static int __setup_ept(u64 hpa, bool enable_ad) 1038 { 1039 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1040 !(ctrl_cpu_rev[1].clr & CPU_EPT)) { 1041 printf("\tEPT is not supported"); 1042 return 1; 1043 } 1044 if (!(ept_vpid.val & EPT_CAP_WB)) { 1045 printf("WB memtype for EPT walks not supported\n"); 1046 return 1; 1047 } 1048 if (!(ept_vpid.val & EPT_CAP_PWL4)) { 1049 printf("\tPWL4 is not supported\n"); 1050 return 1; 1051 } 1052 1053 eptp = EPT_MEM_TYPE_WB; 1054 eptp |= (3 << EPTP_PG_WALK_LEN_SHIFT); 1055 eptp |= hpa; 1056 if (enable_ad) 1057 eptp |= EPTP_AD_FLAG; 1058 1059 vmcs_write(EPTP, eptp); 1060 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0)| CPU_SECONDARY); 1061 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1)| CPU_EPT); 1062 1063 return 0; 1064 } 1065 1066 /** 1067 * setup_ept - Enable Extended Page Tables (EPT) and setup an identity map 1068 * @enable_ad: Whether or not to enable Access/Dirty bits for EPT entries 1069 * 1070 * Returns 0 on success, 1 on failure. 1071 * 1072 * This is the "real" function for setting up EPT tables, i.e. use this for 1073 * tests that need to run code in the guest with EPT enabled. 1074 */ 1075 static int setup_ept(bool enable_ad) 1076 { 1077 unsigned long end_of_memory; 1078 1079 pml4 = alloc_page(); 1080 1081 if (__setup_ept(virt_to_phys(pml4), enable_ad)) 1082 return 1; 1083 1084 end_of_memory = fwcfg_get_u64(FW_CFG_RAM_SIZE); 1085 if (end_of_memory < (1ul << 32)) 1086 end_of_memory = (1ul << 32); 1087 /* Cannot use large EPT pages if we need to track EPT 1088 * accessed/dirty bits at 4K granularity. 1089 */ 1090 setup_ept_range(pml4, 0, end_of_memory, 0, 1091 !enable_ad && ept_2m_supported(), 1092 EPT_WA | EPT_RA | EPT_EA); 1093 return 0; 1094 } 1095 1096 /** 1097 * setup_dummy_ept - Enable Extended Page Tables (EPT) with a dummy root HPA 1098 * 1099 * Setup EPT using a semi-arbitrary dummy root HPA. This function is intended 1100 * for use by tests that need EPT enabled to verify dependent VMCS controls 1101 * but never expect to fully enter the guest, i.e. don't need setup the actual 1102 * EPT tables. 1103 */ 1104 static void setup_dummy_ept(void) 1105 { 1106 if (__setup_ept(0, false)) 1107 report_abort("EPT setup unexpectedly failed"); 1108 } 1109 1110 static int enable_unrestricted_guest(void) 1111 { 1112 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1113 !(ctrl_cpu_rev[1].clr & CPU_URG) || 1114 !(ctrl_cpu_rev[1].clr & CPU_EPT)) 1115 return 1; 1116 1117 setup_dummy_ept(); 1118 1119 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 1120 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | CPU_URG); 1121 1122 return 0; 1123 } 1124 1125 static void ept_enable_ad_bits(void) 1126 { 1127 eptp |= EPTP_AD_FLAG; 1128 vmcs_write(EPTP, eptp); 1129 } 1130 1131 static void ept_disable_ad_bits(void) 1132 { 1133 eptp &= ~EPTP_AD_FLAG; 1134 vmcs_write(EPTP, eptp); 1135 } 1136 1137 static int ept_ad_enabled(void) 1138 { 1139 return eptp & EPTP_AD_FLAG; 1140 } 1141 1142 static void ept_enable_ad_bits_or_skip_test(void) 1143 { 1144 if (!ept_ad_bits_supported()) 1145 test_skip("EPT AD bits not supported."); 1146 ept_enable_ad_bits(); 1147 } 1148 1149 static int apic_version; 1150 1151 static int ept_init_common(bool have_ad) 1152 { 1153 int ret; 1154 struct pci_dev pcidev; 1155 1156 if (setup_ept(have_ad)) 1157 return VMX_TEST_EXIT; 1158 data_page1 = alloc_page(); 1159 data_page2 = alloc_page(); 1160 *((u32 *)data_page1) = MAGIC_VAL_1; 1161 *((u32 *)data_page2) = MAGIC_VAL_2; 1162 install_ept(pml4, (unsigned long)data_page1, (unsigned long)data_page2, 1163 EPT_RA | EPT_WA | EPT_EA); 1164 1165 apic_version = apic_read(APIC_LVR); 1166 1167 ret = pci_find_dev(PCI_VENDOR_ID_REDHAT, PCI_DEVICE_ID_REDHAT_TEST); 1168 if (ret != PCIDEVADDR_INVALID) { 1169 pci_dev_init(&pcidev, ret); 1170 pci_physaddr = pcidev.resource[PCI_TESTDEV_BAR_MEM]; 1171 } 1172 1173 return VMX_TEST_START; 1174 } 1175 1176 static int ept_init(struct vmcs *vmcs) 1177 { 1178 return ept_init_common(false); 1179 } 1180 1181 static void ept_common(void) 1182 { 1183 vmx_set_test_stage(0); 1184 if (*((u32 *)data_page2) != MAGIC_VAL_1 || 1185 *((u32 *)data_page1) != MAGIC_VAL_1) 1186 report(0, "EPT basic framework - read"); 1187 else { 1188 *((u32 *)data_page2) = MAGIC_VAL_3; 1189 vmcall(); 1190 if (vmx_get_test_stage() == 1) { 1191 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1192 *((u32 *)data_page2) == MAGIC_VAL_2) 1193 report(1, "EPT basic framework"); 1194 else 1195 report(1, "EPT basic framework - remap"); 1196 } 1197 } 1198 // Test EPT Misconfigurations 1199 vmx_set_test_stage(1); 1200 vmcall(); 1201 *((u32 *)data_page1) = MAGIC_VAL_1; 1202 if (vmx_get_test_stage() != 2) { 1203 report(0, "EPT misconfigurations"); 1204 goto t1; 1205 } 1206 vmx_set_test_stage(2); 1207 vmcall(); 1208 *((u32 *)data_page1) = MAGIC_VAL_1; 1209 report(vmx_get_test_stage() == 3, "EPT misconfigurations"); 1210 t1: 1211 // Test EPT violation 1212 vmx_set_test_stage(3); 1213 vmcall(); 1214 *((u32 *)data_page1) = MAGIC_VAL_1; 1215 report(vmx_get_test_stage() == 4, "EPT violation - page permission"); 1216 // Violation caused by EPT paging structure 1217 vmx_set_test_stage(4); 1218 vmcall(); 1219 *((u32 *)data_page1) = MAGIC_VAL_2; 1220 report(vmx_get_test_stage() == 5, "EPT violation - paging structure"); 1221 1222 // MMIO Read/Write 1223 vmx_set_test_stage(5); 1224 vmcall(); 1225 1226 *(u32 volatile *)pci_physaddr; 1227 report(vmx_get_test_stage() == 6, "MMIO EPT violation - read"); 1228 1229 *(u32 volatile *)pci_physaddr = MAGIC_VAL_1; 1230 report(vmx_get_test_stage() == 7, "MMIO EPT violation - write"); 1231 } 1232 1233 static void ept_main(void) 1234 { 1235 ept_common(); 1236 1237 // Test EPT access to L1 MMIO 1238 vmx_set_test_stage(7); 1239 report(*((u32 *)0xfee00030UL) == apic_version, "EPT - MMIO access"); 1240 1241 // Test invalid operand for INVEPT 1242 vmcall(); 1243 report(vmx_get_test_stage() == 8, "EPT - unsupported INVEPT"); 1244 } 1245 1246 static bool invept_test(int type, u64 eptp) 1247 { 1248 bool ret, supported; 1249 1250 supported = ept_vpid.val & (EPT_CAP_INVEPT_SINGLE >> INVEPT_SINGLE << type); 1251 ret = invept(type, eptp); 1252 1253 if (ret == !supported) 1254 return false; 1255 1256 if (!supported) 1257 printf("WARNING: unsupported invept passed!\n"); 1258 else 1259 printf("WARNING: invept failed!\n"); 1260 1261 return true; 1262 } 1263 1264 static int pml_exit_handler(union exit_reason exit_reason) 1265 { 1266 u16 index, count; 1267 u64 *pmlbuf = pml_log; 1268 u64 guest_rip = vmcs_read(GUEST_RIP);; 1269 u64 guest_cr3 = vmcs_read(GUEST_CR3); 1270 u32 insn_len = vmcs_read(EXI_INST_LEN); 1271 1272 switch (exit_reason.basic) { 1273 case VMX_VMCALL: 1274 switch (vmx_get_test_stage()) { 1275 case 0: 1276 index = vmcs_read(GUEST_PML_INDEX); 1277 for (count = index + 1; count < PML_INDEX; count++) { 1278 if (pmlbuf[count] == (u64)data_page2) { 1279 vmx_inc_test_stage(); 1280 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1281 break; 1282 } 1283 } 1284 break; 1285 case 1: 1286 index = vmcs_read(GUEST_PML_INDEX); 1287 /* Keep clearing the dirty bit till a overflow */ 1288 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1289 break; 1290 default: 1291 report(false, "unexpected stage, %d.", 1292 vmx_get_test_stage()); 1293 print_vmexit_info(exit_reason); 1294 return VMX_TEST_VMEXIT; 1295 } 1296 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1297 return VMX_TEST_RESUME; 1298 case VMX_PML_FULL: 1299 vmx_inc_test_stage(); 1300 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1301 return VMX_TEST_RESUME; 1302 default: 1303 report(false, "Unknown exit reason, 0x%x", exit_reason.full); 1304 print_vmexit_info(exit_reason); 1305 } 1306 return VMX_TEST_VMEXIT; 1307 } 1308 1309 static int ept_exit_handler_common(union exit_reason exit_reason, bool have_ad) 1310 { 1311 u64 guest_rip; 1312 u64 guest_cr3; 1313 u32 insn_len; 1314 u32 exit_qual; 1315 static unsigned long data_page1_pte, data_page1_pte_pte, memaddr_pte, 1316 guest_pte_addr; 1317 1318 guest_rip = vmcs_read(GUEST_RIP); 1319 guest_cr3 = vmcs_read(GUEST_CR3); 1320 insn_len = vmcs_read(EXI_INST_LEN); 1321 exit_qual = vmcs_read(EXI_QUALIFICATION); 1322 pteval_t *ptep; 1323 switch (exit_reason.basic) { 1324 case VMX_VMCALL: 1325 switch (vmx_get_test_stage()) { 1326 case 0: 1327 check_ept_ad(pml4, guest_cr3, 1328 (unsigned long)data_page1, 1329 have_ad ? EPT_ACCESS_FLAG : 0, 1330 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1331 check_ept_ad(pml4, guest_cr3, 1332 (unsigned long)data_page2, 1333 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0, 1334 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1335 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1336 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1337 if (have_ad) 1338 ept_sync(INVEPT_SINGLE, eptp);; 1339 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1340 *((u32 *)data_page2) == MAGIC_VAL_2) { 1341 vmx_inc_test_stage(); 1342 install_ept(pml4, (unsigned long)data_page2, 1343 (unsigned long)data_page2, 1344 EPT_RA | EPT_WA | EPT_EA); 1345 } else 1346 report(0, "EPT basic framework - write"); 1347 break; 1348 case 1: 1349 install_ept(pml4, (unsigned long)data_page1, 1350 (unsigned long)data_page1, EPT_WA); 1351 ept_sync(INVEPT_SINGLE, eptp); 1352 break; 1353 case 2: 1354 install_ept(pml4, (unsigned long)data_page1, 1355 (unsigned long)data_page1, 1356 EPT_RA | EPT_WA | EPT_EA | 1357 (2 << EPT_MEM_TYPE_SHIFT)); 1358 ept_sync(INVEPT_SINGLE, eptp); 1359 break; 1360 case 3: 1361 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1362 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)data_page1, 1363 1, &data_page1_pte)); 1364 set_ept_pte(pml4, (unsigned long)data_page1, 1365 1, data_page1_pte & ~EPT_PRESENT); 1366 ept_sync(INVEPT_SINGLE, eptp); 1367 break; 1368 case 4: 1369 ptep = get_pte_level((pgd_t *)guest_cr3, data_page1, /*level=*/2); 1370 guest_pte_addr = virt_to_phys(ptep) & PAGE_MASK; 1371 1372 TEST_ASSERT(get_ept_pte(pml4, guest_pte_addr, 2, &data_page1_pte_pte)); 1373 set_ept_pte(pml4, guest_pte_addr, 2, 1374 data_page1_pte_pte & ~EPT_PRESENT); 1375 ept_sync(INVEPT_SINGLE, eptp); 1376 break; 1377 case 5: 1378 install_ept(pml4, (unsigned long)pci_physaddr, 1379 (unsigned long)pci_physaddr, 0); 1380 ept_sync(INVEPT_SINGLE, eptp); 1381 break; 1382 case 7: 1383 if (!invept_test(0, eptp)) 1384 vmx_inc_test_stage(); 1385 break; 1386 // Should not reach here 1387 default: 1388 report(false, "ERROR - unexpected stage, %d.", 1389 vmx_get_test_stage()); 1390 print_vmexit_info(exit_reason); 1391 return VMX_TEST_VMEXIT; 1392 } 1393 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1394 return VMX_TEST_RESUME; 1395 case VMX_EPT_MISCONFIG: 1396 switch (vmx_get_test_stage()) { 1397 case 1: 1398 case 2: 1399 vmx_inc_test_stage(); 1400 install_ept(pml4, (unsigned long)data_page1, 1401 (unsigned long)data_page1, 1402 EPT_RA | EPT_WA | EPT_EA); 1403 ept_sync(INVEPT_SINGLE, eptp); 1404 break; 1405 // Should not reach here 1406 default: 1407 report(false, "ERROR - unexpected stage, %d.", 1408 vmx_get_test_stage()); 1409 print_vmexit_info(exit_reason); 1410 return VMX_TEST_VMEXIT; 1411 } 1412 return VMX_TEST_RESUME; 1413 case VMX_EPT_VIOLATION: 1414 /* 1415 * Exit-qualifications are masked not to account for advanced 1416 * VM-exit information. Once KVM supports this feature, this 1417 * masking should be removed. 1418 */ 1419 exit_qual &= ~EPT_VLT_GUEST_MASK; 1420 1421 switch(vmx_get_test_stage()) { 1422 case 3: 1423 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1424 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1425 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1426 if (exit_qual == (EPT_VLT_WR | EPT_VLT_LADDR_VLD | 1427 EPT_VLT_PADDR)) 1428 vmx_inc_test_stage(); 1429 set_ept_pte(pml4, (unsigned long)data_page1, 1430 1, data_page1_pte | (EPT_PRESENT)); 1431 ept_sync(INVEPT_SINGLE, eptp); 1432 break; 1433 case 4: 1434 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1435 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1436 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1437 if (exit_qual == (EPT_VLT_RD | 1438 (have_ad ? EPT_VLT_WR : 0) | 1439 EPT_VLT_LADDR_VLD)) 1440 vmx_inc_test_stage(); 1441 set_ept_pte(pml4, guest_pte_addr, 2, 1442 data_page1_pte_pte | (EPT_PRESENT)); 1443 ept_sync(INVEPT_SINGLE, eptp); 1444 break; 1445 case 5: 1446 if (exit_qual & EPT_VLT_RD) 1447 vmx_inc_test_stage(); 1448 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1449 1, &memaddr_pte)); 1450 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA); 1451 ept_sync(INVEPT_SINGLE, eptp); 1452 break; 1453 case 6: 1454 if (exit_qual & EPT_VLT_WR) 1455 vmx_inc_test_stage(); 1456 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1457 1, &memaddr_pte)); 1458 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA | EPT_WA); 1459 ept_sync(INVEPT_SINGLE, eptp); 1460 break; 1461 default: 1462 // Should not reach here 1463 report(false, "ERROR : unexpected stage, %d", 1464 vmx_get_test_stage()); 1465 print_vmexit_info(exit_reason); 1466 return VMX_TEST_VMEXIT; 1467 } 1468 return VMX_TEST_RESUME; 1469 default: 1470 report(false, "Unknown exit reason, 0x%x", exit_reason.full); 1471 print_vmexit_info(exit_reason); 1472 } 1473 return VMX_TEST_VMEXIT; 1474 } 1475 1476 static int ept_exit_handler(union exit_reason exit_reason) 1477 { 1478 return ept_exit_handler_common(exit_reason, false); 1479 } 1480 1481 static int eptad_init(struct vmcs *vmcs) 1482 { 1483 int r = ept_init_common(true); 1484 1485 if (r == VMX_TEST_EXIT) 1486 return r; 1487 1488 if ((rdmsr(MSR_IA32_VMX_EPT_VPID_CAP) & EPT_CAP_AD_FLAG) == 0) { 1489 printf("\tEPT A/D bits are not supported"); 1490 return VMX_TEST_EXIT; 1491 } 1492 1493 return r; 1494 } 1495 1496 static int pml_init(struct vmcs *vmcs) 1497 { 1498 u32 ctrl_cpu; 1499 int r = eptad_init(vmcs); 1500 1501 if (r == VMX_TEST_EXIT) 1502 return r; 1503 1504 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1505 !(ctrl_cpu_rev[1].clr & CPU_PML)) { 1506 printf("\tPML is not supported"); 1507 return VMX_TEST_EXIT; 1508 } 1509 1510 pml_log = alloc_page(); 1511 vmcs_write(PMLADDR, (u64)pml_log); 1512 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1513 1514 ctrl_cpu = vmcs_read(CPU_EXEC_CTRL1) | CPU_PML; 1515 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu); 1516 1517 return VMX_TEST_START; 1518 } 1519 1520 static void pml_main(void) 1521 { 1522 int count = 0; 1523 1524 vmx_set_test_stage(0); 1525 *((u32 *)data_page2) = 0x1; 1526 vmcall(); 1527 report(vmx_get_test_stage() == 1, "PML - Dirty GPA Logging"); 1528 1529 while (vmx_get_test_stage() == 1) { 1530 vmcall(); 1531 *((u32 *)data_page2) = 0x1; 1532 if (count++ > PML_INDEX) 1533 break; 1534 } 1535 report(vmx_get_test_stage() == 2, "PML Full Event"); 1536 } 1537 1538 static void eptad_main(void) 1539 { 1540 ept_common(); 1541 } 1542 1543 static int eptad_exit_handler(union exit_reason exit_reason) 1544 { 1545 return ept_exit_handler_common(exit_reason, true); 1546 } 1547 1548 static bool invvpid_test(int type, u16 vpid) 1549 { 1550 bool ret, supported; 1551 1552 supported = ept_vpid.val & 1553 (VPID_CAP_INVVPID_ADDR >> INVVPID_ADDR << type); 1554 ret = invvpid(type, vpid, 0); 1555 1556 if (ret == !supported) 1557 return false; 1558 1559 if (!supported) 1560 printf("WARNING: unsupported invvpid passed!\n"); 1561 else 1562 printf("WARNING: invvpid failed!\n"); 1563 1564 return true; 1565 } 1566 1567 static int vpid_init(struct vmcs *vmcs) 1568 { 1569 u32 ctrl_cpu1; 1570 1571 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1572 !(ctrl_cpu_rev[1].clr & CPU_VPID)) { 1573 printf("\tVPID is not supported"); 1574 return VMX_TEST_EXIT; 1575 } 1576 1577 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 1578 ctrl_cpu1 |= CPU_VPID; 1579 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 1580 return VMX_TEST_START; 1581 } 1582 1583 static void vpid_main(void) 1584 { 1585 vmx_set_test_stage(0); 1586 vmcall(); 1587 report(vmx_get_test_stage() == 1, "INVVPID SINGLE ADDRESS"); 1588 vmx_set_test_stage(2); 1589 vmcall(); 1590 report(vmx_get_test_stage() == 3, "INVVPID SINGLE"); 1591 vmx_set_test_stage(4); 1592 vmcall(); 1593 report(vmx_get_test_stage() == 5, "INVVPID ALL"); 1594 } 1595 1596 static int vpid_exit_handler(union exit_reason exit_reason) 1597 { 1598 u64 guest_rip; 1599 u32 insn_len; 1600 1601 guest_rip = vmcs_read(GUEST_RIP); 1602 insn_len = vmcs_read(EXI_INST_LEN); 1603 1604 switch (exit_reason.basic) { 1605 case VMX_VMCALL: 1606 switch(vmx_get_test_stage()) { 1607 case 0: 1608 if (!invvpid_test(INVVPID_ADDR, 1)) 1609 vmx_inc_test_stage(); 1610 break; 1611 case 2: 1612 if (!invvpid_test(INVVPID_CONTEXT_GLOBAL, 1)) 1613 vmx_inc_test_stage(); 1614 break; 1615 case 4: 1616 if (!invvpid_test(INVVPID_ALL, 1)) 1617 vmx_inc_test_stage(); 1618 break; 1619 default: 1620 report(false, "ERROR: unexpected stage, %d", 1621 vmx_get_test_stage()); 1622 print_vmexit_info(exit_reason); 1623 return VMX_TEST_VMEXIT; 1624 } 1625 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1626 return VMX_TEST_RESUME; 1627 default: 1628 report(false, "Unknown exit reason, 0x%x", exit_reason.full); 1629 print_vmexit_info(exit_reason); 1630 } 1631 return VMX_TEST_VMEXIT; 1632 } 1633 1634 #define TIMER_VECTOR 222 1635 1636 static volatile bool timer_fired; 1637 1638 static void timer_isr(isr_regs_t *regs) 1639 { 1640 timer_fired = true; 1641 apic_write(APIC_EOI, 0); 1642 } 1643 1644 static int interrupt_init(struct vmcs *vmcs) 1645 { 1646 msr_bmp_init(); 1647 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1648 handle_irq(TIMER_VECTOR, timer_isr); 1649 return VMX_TEST_START; 1650 } 1651 1652 static void interrupt_main(void) 1653 { 1654 long long start, loops; 1655 1656 vmx_set_test_stage(0); 1657 1658 apic_write(APIC_LVTT, TIMER_VECTOR); 1659 irq_enable(); 1660 1661 apic_write(APIC_TMICT, 1); 1662 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1663 asm volatile ("nop"); 1664 report(timer_fired, "direct interrupt while running guest"); 1665 1666 apic_write(APIC_TMICT, 0); 1667 irq_disable(); 1668 vmcall(); 1669 timer_fired = false; 1670 apic_write(APIC_TMICT, 1); 1671 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1672 asm volatile ("nop"); 1673 report(timer_fired, "intercepted interrupt while running guest"); 1674 1675 irq_enable(); 1676 apic_write(APIC_TMICT, 0); 1677 irq_disable(); 1678 vmcall(); 1679 timer_fired = false; 1680 start = rdtsc(); 1681 apic_write(APIC_TMICT, 1000000); 1682 1683 asm volatile ("sti; hlt"); 1684 1685 report(rdtsc() - start > 1000000 && timer_fired, 1686 "direct interrupt + hlt"); 1687 1688 apic_write(APIC_TMICT, 0); 1689 irq_disable(); 1690 vmcall(); 1691 timer_fired = false; 1692 start = rdtsc(); 1693 apic_write(APIC_TMICT, 1000000); 1694 1695 asm volatile ("sti; hlt"); 1696 1697 report(rdtsc() - start > 10000 && timer_fired, 1698 "intercepted interrupt + hlt"); 1699 1700 apic_write(APIC_TMICT, 0); 1701 irq_disable(); 1702 vmcall(); 1703 timer_fired = false; 1704 start = rdtsc(); 1705 apic_write(APIC_TMICT, 1000000); 1706 1707 irq_enable(); 1708 asm volatile ("nop"); 1709 vmcall(); 1710 1711 report(rdtsc() - start > 10000 && timer_fired, 1712 "direct interrupt + activity state hlt"); 1713 1714 apic_write(APIC_TMICT, 0); 1715 irq_disable(); 1716 vmcall(); 1717 timer_fired = false; 1718 start = rdtsc(); 1719 apic_write(APIC_TMICT, 1000000); 1720 1721 irq_enable(); 1722 asm volatile ("nop"); 1723 vmcall(); 1724 1725 report(rdtsc() - start > 10000 && timer_fired, 1726 "intercepted interrupt + activity state hlt"); 1727 1728 apic_write(APIC_TMICT, 0); 1729 irq_disable(); 1730 vmx_set_test_stage(7); 1731 vmcall(); 1732 timer_fired = false; 1733 apic_write(APIC_TMICT, 1); 1734 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1735 asm volatile ("nop"); 1736 report(timer_fired, 1737 "running a guest with interrupt acknowledgement set"); 1738 1739 apic_write(APIC_TMICT, 0); 1740 irq_enable(); 1741 timer_fired = false; 1742 vmcall(); 1743 report(timer_fired, "Inject an event to a halted guest"); 1744 } 1745 1746 static int interrupt_exit_handler(union exit_reason exit_reason) 1747 { 1748 u64 guest_rip = vmcs_read(GUEST_RIP); 1749 u32 insn_len = vmcs_read(EXI_INST_LEN); 1750 1751 switch (exit_reason.basic) { 1752 case VMX_VMCALL: 1753 switch (vmx_get_test_stage()) { 1754 case 0: 1755 case 2: 1756 case 5: 1757 vmcs_write(PIN_CONTROLS, 1758 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1759 break; 1760 case 7: 1761 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_INTA); 1762 vmcs_write(PIN_CONTROLS, 1763 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1764 break; 1765 case 1: 1766 case 3: 1767 vmcs_write(PIN_CONTROLS, 1768 vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1769 break; 1770 case 4: 1771 case 6: 1772 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1773 break; 1774 1775 case 8: 1776 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1777 vmcs_write(ENT_INTR_INFO, 1778 TIMER_VECTOR | 1779 (VMX_INTR_TYPE_EXT_INTR << INTR_INFO_INTR_TYPE_SHIFT) | 1780 INTR_INFO_VALID_MASK); 1781 break; 1782 } 1783 vmx_inc_test_stage(); 1784 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1785 return VMX_TEST_RESUME; 1786 case VMX_EXTINT: 1787 if (vmcs_read(EXI_CONTROLS) & EXI_INTA) { 1788 int vector = vmcs_read(EXI_INTR_INFO) & 0xff; 1789 handle_external_interrupt(vector); 1790 } else { 1791 irq_enable(); 1792 asm volatile ("nop"); 1793 irq_disable(); 1794 } 1795 if (vmx_get_test_stage() >= 2) 1796 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 1797 return VMX_TEST_RESUME; 1798 default: 1799 report(false, "Unknown exit reason, 0x%x", exit_reason.full); 1800 print_vmexit_info(exit_reason); 1801 } 1802 1803 return VMX_TEST_VMEXIT; 1804 } 1805 1806 1807 static volatile int nmi_fired; 1808 1809 #define NMI_DELAY 100000000ULL 1810 1811 static void nmi_isr(isr_regs_t *regs) 1812 { 1813 nmi_fired = true; 1814 } 1815 1816 static int nmi_hlt_init(struct vmcs *vmcs) 1817 { 1818 msr_bmp_init(); 1819 handle_irq(NMI_VECTOR, nmi_isr); 1820 vmcs_write(PIN_CONTROLS, 1821 vmcs_read(PIN_CONTROLS) & ~PIN_NMI); 1822 vmcs_write(PIN_CONTROLS, 1823 vmcs_read(PIN_CONTROLS) & ~PIN_VIRT_NMI); 1824 return VMX_TEST_START; 1825 } 1826 1827 static void nmi_message_thread(void *data) 1828 { 1829 while (vmx_get_test_stage() != 1) 1830 pause(); 1831 1832 delay(NMI_DELAY); 1833 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_NMI | APIC_INT_ASSERT, id_map[0]); 1834 1835 while (vmx_get_test_stage() != 2) 1836 pause(); 1837 1838 delay(NMI_DELAY); 1839 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_NMI | APIC_INT_ASSERT, id_map[0]); 1840 } 1841 1842 static void nmi_hlt_main(void) 1843 { 1844 long long start; 1845 1846 if (cpu_count() < 2) { 1847 report_skip(__func__); 1848 vmx_set_test_stage(-1); 1849 return; 1850 } 1851 1852 vmx_set_test_stage(0); 1853 on_cpu_async(1, nmi_message_thread, NULL); 1854 start = rdtsc(); 1855 vmx_set_test_stage(1); 1856 asm volatile ("hlt"); 1857 report((rdtsc() - start > NMI_DELAY) && nmi_fired, 1858 "direct NMI + hlt"); 1859 if (!nmi_fired) 1860 vmx_set_test_stage(-1); 1861 nmi_fired = false; 1862 1863 vmcall(); 1864 1865 start = rdtsc(); 1866 vmx_set_test_stage(2); 1867 asm volatile ("hlt"); 1868 report((rdtsc() - start > NMI_DELAY) && !nmi_fired, 1869 "intercepted NMI + hlt"); 1870 if (nmi_fired) { 1871 report(!nmi_fired, "intercepted NMI was dispatched"); 1872 vmx_set_test_stage(-1); 1873 return; 1874 } 1875 vmx_set_test_stage(3); 1876 } 1877 1878 static int nmi_hlt_exit_handler(union exit_reason exit_reason) 1879 { 1880 u64 guest_rip = vmcs_read(GUEST_RIP); 1881 u32 insn_len = vmcs_read(EXI_INST_LEN); 1882 1883 switch (vmx_get_test_stage()) { 1884 case 1: 1885 if (exit_reason.basic != VMX_VMCALL) { 1886 report(false, "VMEXIT not due to vmcall. Exit reason 0x%x", 1887 exit_reason.full); 1888 print_vmexit_info(exit_reason); 1889 return VMX_TEST_VMEXIT; 1890 } 1891 1892 vmcs_write(PIN_CONTROLS, 1893 vmcs_read(PIN_CONTROLS) | PIN_NMI); 1894 vmcs_write(PIN_CONTROLS, 1895 vmcs_read(PIN_CONTROLS) | PIN_VIRT_NMI); 1896 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1897 break; 1898 1899 case 2: 1900 if (exit_reason.basic != VMX_EXC_NMI) { 1901 report(false, "VMEXIT not due to NMI intercept. Exit reason 0x%x", 1902 exit_reason.full); 1903 print_vmexit_info(exit_reason); 1904 return VMX_TEST_VMEXIT; 1905 } 1906 report(true, "NMI intercept while running guest"); 1907 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 1908 break; 1909 1910 case 3: 1911 break; 1912 1913 default: 1914 return VMX_TEST_VMEXIT; 1915 } 1916 1917 if (vmx_get_test_stage() == 3) 1918 return VMX_TEST_VMEXIT; 1919 1920 return VMX_TEST_RESUME; 1921 } 1922 1923 1924 static int dbgctls_init(struct vmcs *vmcs) 1925 { 1926 u64 dr7 = 0x402; 1927 u64 zero = 0; 1928 1929 msr_bmp_init(); 1930 asm volatile( 1931 "mov %0,%%dr0\n\t" 1932 "mov %0,%%dr1\n\t" 1933 "mov %0,%%dr2\n\t" 1934 "mov %1,%%dr7\n\t" 1935 : : "r" (zero), "r" (dr7)); 1936 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1937 vmcs_write(GUEST_DR7, 0x404); 1938 vmcs_write(GUEST_DEBUGCTL, 0x2); 1939 1940 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 1941 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_SAVE_DBGCTLS); 1942 1943 return VMX_TEST_START; 1944 } 1945 1946 static void dbgctls_main(void) 1947 { 1948 u64 dr7, debugctl; 1949 1950 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1951 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1952 /* Commented out: KVM does not support DEBUGCTL so far */ 1953 (void)debugctl; 1954 report(dr7 == 0x404, "Load debug controls" /* && debugctl == 0x2 */); 1955 1956 dr7 = 0x408; 1957 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1958 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1959 1960 vmx_set_test_stage(0); 1961 vmcall(); 1962 report(vmx_get_test_stage() == 1, "Save debug controls"); 1963 1964 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS || 1965 ctrl_exit_rev.set & EXI_SAVE_DBGCTLS) { 1966 printf("\tDebug controls are always loaded/saved\n"); 1967 return; 1968 } 1969 vmx_set_test_stage(2); 1970 vmcall(); 1971 1972 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1973 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1974 /* Commented out: KVM does not support DEBUGCTL so far */ 1975 (void)debugctl; 1976 report(dr7 == 0x402, 1977 "Guest=host debug controls" /* && debugctl == 0x1 */); 1978 1979 dr7 = 0x408; 1980 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1981 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1982 1983 vmx_set_test_stage(3); 1984 vmcall(); 1985 report(vmx_get_test_stage() == 4, "Don't save debug controls"); 1986 } 1987 1988 static int dbgctls_exit_handler(union exit_reason exit_reason) 1989 { 1990 u32 insn_len = vmcs_read(EXI_INST_LEN); 1991 u64 guest_rip = vmcs_read(GUEST_RIP); 1992 u64 dr7, debugctl; 1993 1994 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1995 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1996 1997 switch (exit_reason.basic) { 1998 case VMX_VMCALL: 1999 switch (vmx_get_test_stage()) { 2000 case 0: 2001 if (dr7 == 0x400 && debugctl == 0 && 2002 vmcs_read(GUEST_DR7) == 0x408 /* && 2003 Commented out: KVM does not support DEBUGCTL so far 2004 vmcs_read(GUEST_DEBUGCTL) == 0x3 */) 2005 vmx_inc_test_stage(); 2006 break; 2007 case 2: 2008 dr7 = 0x402; 2009 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 2010 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 2011 vmcs_write(GUEST_DR7, 0x404); 2012 vmcs_write(GUEST_DEBUGCTL, 0x2); 2013 2014 vmcs_write(ENT_CONTROLS, 2015 vmcs_read(ENT_CONTROLS) & ~ENT_LOAD_DBGCTLS); 2016 vmcs_write(EXI_CONTROLS, 2017 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_DBGCTLS); 2018 break; 2019 case 3: 2020 if (dr7 == 0x400 && debugctl == 0 && 2021 vmcs_read(GUEST_DR7) == 0x404 /* && 2022 Commented out: KVM does not support DEBUGCTL so far 2023 vmcs_read(GUEST_DEBUGCTL) == 0x2 */) 2024 vmx_inc_test_stage(); 2025 break; 2026 } 2027 vmcs_write(GUEST_RIP, guest_rip + insn_len); 2028 return VMX_TEST_RESUME; 2029 default: 2030 report(false, "Unknown exit reason, %d", exit_reason.full); 2031 print_vmexit_info(exit_reason); 2032 } 2033 return VMX_TEST_VMEXIT; 2034 } 2035 2036 struct vmx_msr_entry { 2037 u32 index; 2038 u32 reserved; 2039 u64 value; 2040 } __attribute__((packed)); 2041 2042 #define MSR_MAGIC 0x31415926 2043 struct vmx_msr_entry *exit_msr_store, *entry_msr_load, *exit_msr_load; 2044 2045 static int msr_switch_init(struct vmcs *vmcs) 2046 { 2047 msr_bmp_init(); 2048 exit_msr_store = alloc_page(); 2049 exit_msr_load = alloc_page(); 2050 entry_msr_load = alloc_page(); 2051 entry_msr_load[0].index = MSR_KERNEL_GS_BASE; 2052 entry_msr_load[0].value = MSR_MAGIC; 2053 2054 vmx_set_test_stage(1); 2055 vmcs_write(ENT_MSR_LD_CNT, 1); 2056 vmcs_write(ENTER_MSR_LD_ADDR, (u64)entry_msr_load); 2057 vmcs_write(EXI_MSR_ST_CNT, 1); 2058 vmcs_write(EXIT_MSR_ST_ADDR, (u64)exit_msr_store); 2059 vmcs_write(EXI_MSR_LD_CNT, 1); 2060 vmcs_write(EXIT_MSR_LD_ADDR, (u64)exit_msr_load); 2061 return VMX_TEST_START; 2062 } 2063 2064 static void msr_switch_main(void) 2065 { 2066 if (vmx_get_test_stage() == 1) { 2067 report(rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC, 2068 "VM entry MSR load"); 2069 vmx_set_test_stage(2); 2070 wrmsr(MSR_KERNEL_GS_BASE, MSR_MAGIC + 1); 2071 exit_msr_store[0].index = MSR_KERNEL_GS_BASE; 2072 exit_msr_load[0].index = MSR_KERNEL_GS_BASE; 2073 exit_msr_load[0].value = MSR_MAGIC + 2; 2074 } 2075 vmcall(); 2076 } 2077 2078 static int msr_switch_exit_handler(union exit_reason exit_reason) 2079 { 2080 if (exit_reason.basic == VMX_VMCALL && vmx_get_test_stage() == 2) { 2081 report(exit_msr_store[0].value == MSR_MAGIC + 1, 2082 "VM exit MSR store"); 2083 report(rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC + 2, 2084 "VM exit MSR load"); 2085 vmx_set_test_stage(3); 2086 entry_msr_load[0].index = MSR_FS_BASE; 2087 return VMX_TEST_RESUME; 2088 } 2089 printf("ERROR %s: unexpected stage=%u or reason=0x%x\n", 2090 __func__, vmx_get_test_stage(), exit_reason.full); 2091 return VMX_TEST_EXIT; 2092 } 2093 2094 static int msr_switch_entry_failure(struct vmentry_result *result) 2095 { 2096 if (result->vm_fail) { 2097 printf("ERROR %s: VM-Fail on %s\n", __func__, result->instr); 2098 return VMX_TEST_EXIT; 2099 } 2100 2101 if (result->exit_reason.failed_vmentry && 2102 result->exit_reason.basic == VMX_FAIL_MSR && 2103 vmx_get_test_stage() == 3) { 2104 report(vmcs_read(EXI_QUALIFICATION) == 1, 2105 "VM entry MSR load: try to load FS_BASE"); 2106 return VMX_TEST_VMEXIT; 2107 } 2108 printf("ERROR %s: unexpected stage=%u or reason=%x\n", 2109 __func__, vmx_get_test_stage(), result->exit_reason.full); 2110 return VMX_TEST_EXIT; 2111 } 2112 2113 static int vmmcall_init(struct vmcs *vmcs) 2114 { 2115 vmcs_write(EXC_BITMAP, 1 << UD_VECTOR); 2116 return VMX_TEST_START; 2117 } 2118 2119 static void vmmcall_main(void) 2120 { 2121 asm volatile( 2122 "mov $0xABCD, %%rax\n\t" 2123 "vmmcall\n\t" 2124 ::: "rax"); 2125 2126 report(0, "VMMCALL"); 2127 } 2128 2129 static int vmmcall_exit_handler(union exit_reason exit_reason) 2130 { 2131 switch (exit_reason.basic) { 2132 case VMX_VMCALL: 2133 printf("here\n"); 2134 report(0, "VMMCALL triggers #UD"); 2135 break; 2136 case VMX_EXC_NMI: 2137 report((vmcs_read(EXI_INTR_INFO) & 0xff) == UD_VECTOR, 2138 "VMMCALL triggers #UD"); 2139 break; 2140 default: 2141 report(false, "Unknown exit reason, 0x%x", exit_reason.full); 2142 print_vmexit_info(exit_reason); 2143 } 2144 2145 return VMX_TEST_VMEXIT; 2146 } 2147 2148 static int disable_rdtscp_init(struct vmcs *vmcs) 2149 { 2150 u32 ctrl_cpu1; 2151 2152 if (ctrl_cpu_rev[0].clr & CPU_SECONDARY) { 2153 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 2154 ctrl_cpu1 &= ~CPU_RDTSCP; 2155 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 2156 } 2157 2158 return VMX_TEST_START; 2159 } 2160 2161 static void disable_rdtscp_ud_handler(struct ex_regs *regs) 2162 { 2163 switch (vmx_get_test_stage()) { 2164 case 0: 2165 report(true, "RDTSCP triggers #UD"); 2166 vmx_inc_test_stage(); 2167 regs->rip += 3; 2168 break; 2169 case 2: 2170 report(true, "RDPID triggers #UD"); 2171 vmx_inc_test_stage(); 2172 regs->rip += 4; 2173 break; 2174 } 2175 return; 2176 2177 } 2178 2179 static void disable_rdtscp_main(void) 2180 { 2181 /* Test that #UD is properly injected in L2. */ 2182 handle_exception(UD_VECTOR, disable_rdtscp_ud_handler); 2183 2184 vmx_set_test_stage(0); 2185 asm volatile("rdtscp" : : : "eax", "ecx", "edx"); 2186 vmcall(); 2187 asm volatile(".byte 0xf3, 0x0f, 0xc7, 0xf8" : : : "eax"); 2188 2189 handle_exception(UD_VECTOR, 0); 2190 vmcall(); 2191 } 2192 2193 static int disable_rdtscp_exit_handler(union exit_reason exit_reason) 2194 { 2195 switch (exit_reason.basic) { 2196 case VMX_VMCALL: 2197 switch (vmx_get_test_stage()) { 2198 case 0: 2199 report(false, "RDTSCP triggers #UD"); 2200 vmx_inc_test_stage(); 2201 /* fallthrough */ 2202 case 1: 2203 vmx_inc_test_stage(); 2204 vmcs_write(GUEST_RIP, vmcs_read(GUEST_RIP) + 3); 2205 return VMX_TEST_RESUME; 2206 case 2: 2207 report(false, "RDPID triggers #UD"); 2208 break; 2209 } 2210 break; 2211 2212 default: 2213 report(false, "Unknown exit reason, 0x%x", exit_reason.full); 2214 print_vmexit_info(exit_reason); 2215 } 2216 return VMX_TEST_VMEXIT; 2217 } 2218 2219 static int int3_init(struct vmcs *vmcs) 2220 { 2221 vmcs_write(EXC_BITMAP, ~0u); 2222 return VMX_TEST_START; 2223 } 2224 2225 static void int3_guest_main(void) 2226 { 2227 asm volatile ("int3"); 2228 } 2229 2230 static int int3_exit_handler(union exit_reason exit_reason) 2231 { 2232 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2233 2234 report(exit_reason.basic == VMX_EXC_NMI && 2235 (intr_info & INTR_INFO_VALID_MASK) && 2236 (intr_info & INTR_INFO_VECTOR_MASK) == BP_VECTOR && 2237 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2238 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION, 2239 "L1 intercepts #BP"); 2240 2241 return VMX_TEST_VMEXIT; 2242 } 2243 2244 static int into_init(struct vmcs *vmcs) 2245 { 2246 vmcs_write(EXC_BITMAP, ~0u); 2247 return VMX_TEST_START; 2248 } 2249 2250 static void into_guest_main(void) 2251 { 2252 struct far_pointer32 fp = { 2253 .offset = (uintptr_t)&&into, 2254 .selector = KERNEL_CS32, 2255 }; 2256 uintptr_t rsp; 2257 2258 asm volatile ("mov %%rsp, %0" : "=r"(rsp)); 2259 2260 if (fp.offset != (uintptr_t)&&into) { 2261 printf("Code address too high.\n"); 2262 return; 2263 } 2264 if ((u32)rsp != rsp) { 2265 printf("Stack address too high.\n"); 2266 return; 2267 } 2268 2269 asm goto ("lcall *%0" : : "m" (fp) : "rax" : into); 2270 return; 2271 into: 2272 asm volatile (".code32;" 2273 "movl $0x7fffffff, %eax;" 2274 "addl %eax, %eax;" 2275 "into;" 2276 "lret;" 2277 ".code64"); 2278 __builtin_unreachable(); 2279 } 2280 2281 static int into_exit_handler(union exit_reason exit_reason) 2282 { 2283 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2284 2285 report(exit_reason.basic == VMX_EXC_NMI && 2286 (intr_info & INTR_INFO_VALID_MASK) && 2287 (intr_info & INTR_INFO_VECTOR_MASK) == OF_VECTOR && 2288 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2289 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION, 2290 "L1 intercepts #OF"); 2291 2292 return VMX_TEST_VMEXIT; 2293 } 2294 2295 static void exit_monitor_from_l2_main(void) 2296 { 2297 printf("Calling exit(0) from l2...\n"); 2298 exit(0); 2299 } 2300 2301 static int exit_monitor_from_l2_handler(union exit_reason exit_reason) 2302 { 2303 report(false, "The guest should have killed the VMM"); 2304 return VMX_TEST_EXIT; 2305 } 2306 2307 static void assert_exit_reason(u64 expected) 2308 { 2309 u64 actual = vmcs_read(EXI_REASON); 2310 2311 TEST_ASSERT_EQ_MSG(expected, actual, "Expected %s, got %s.", 2312 exit_reason_description(expected), 2313 exit_reason_description(actual)); 2314 } 2315 2316 static void skip_exit_insn(void) 2317 { 2318 u64 guest_rip = vmcs_read(GUEST_RIP); 2319 u32 insn_len = vmcs_read(EXI_INST_LEN); 2320 vmcs_write(GUEST_RIP, guest_rip + insn_len); 2321 } 2322 2323 static void skip_exit_vmcall(void) 2324 { 2325 assert_exit_reason(VMX_VMCALL); 2326 skip_exit_insn(); 2327 } 2328 2329 static void v2_null_test_guest(void) 2330 { 2331 } 2332 2333 static void v2_null_test(void) 2334 { 2335 test_set_guest(v2_null_test_guest); 2336 enter_guest(); 2337 report(1, __func__); 2338 } 2339 2340 static void v2_multiple_entries_test_guest(void) 2341 { 2342 vmx_set_test_stage(1); 2343 vmcall(); 2344 vmx_set_test_stage(2); 2345 } 2346 2347 static void v2_multiple_entries_test(void) 2348 { 2349 test_set_guest(v2_multiple_entries_test_guest); 2350 enter_guest(); 2351 TEST_ASSERT_EQ(vmx_get_test_stage(), 1); 2352 skip_exit_vmcall(); 2353 enter_guest(); 2354 TEST_ASSERT_EQ(vmx_get_test_stage(), 2); 2355 report(1, __func__); 2356 } 2357 2358 static int fixture_test_data = 1; 2359 2360 static void fixture_test_teardown(void *data) 2361 { 2362 *((int *) data) = 1; 2363 } 2364 2365 static void fixture_test_guest(void) 2366 { 2367 fixture_test_data++; 2368 } 2369 2370 2371 static void fixture_test_setup(void) 2372 { 2373 TEST_ASSERT_EQ_MSG(1, fixture_test_data, 2374 "fixture_test_teardown didn't run?!"); 2375 fixture_test_data = 2; 2376 test_add_teardown(fixture_test_teardown, &fixture_test_data); 2377 test_set_guest(fixture_test_guest); 2378 } 2379 2380 static void fixture_test_case1(void) 2381 { 2382 fixture_test_setup(); 2383 TEST_ASSERT_EQ(2, fixture_test_data); 2384 enter_guest(); 2385 TEST_ASSERT_EQ(3, fixture_test_data); 2386 report(1, __func__); 2387 } 2388 2389 static void fixture_test_case2(void) 2390 { 2391 fixture_test_setup(); 2392 TEST_ASSERT_EQ(2, fixture_test_data); 2393 enter_guest(); 2394 TEST_ASSERT_EQ(3, fixture_test_data); 2395 report(1, __func__); 2396 } 2397 2398 enum ept_access_op { 2399 OP_READ, 2400 OP_WRITE, 2401 OP_EXEC, 2402 OP_FLUSH_TLB, 2403 OP_EXIT, 2404 }; 2405 2406 static struct ept_access_test_data { 2407 unsigned long gpa; 2408 unsigned long *gva; 2409 unsigned long hpa; 2410 unsigned long *hva; 2411 enum ept_access_op op; 2412 } ept_access_test_data; 2413 2414 extern unsigned char ret42_start; 2415 extern unsigned char ret42_end; 2416 2417 /* Returns 42. */ 2418 asm( 2419 ".align 64\n" 2420 "ret42_start:\n" 2421 "mov $42, %eax\n" 2422 "ret\n" 2423 "ret42_end:\n" 2424 ); 2425 2426 static void 2427 diagnose_ept_violation_qual(u64 expected, u64 actual) 2428 { 2429 2430 #define DIAGNOSE(flag) \ 2431 do { \ 2432 if ((expected & flag) != (actual & flag)) \ 2433 printf(#flag " %sexpected\n", \ 2434 (expected & flag) ? "" : "un"); \ 2435 } while (0) 2436 2437 DIAGNOSE(EPT_VLT_RD); 2438 DIAGNOSE(EPT_VLT_WR); 2439 DIAGNOSE(EPT_VLT_FETCH); 2440 DIAGNOSE(EPT_VLT_PERM_RD); 2441 DIAGNOSE(EPT_VLT_PERM_WR); 2442 DIAGNOSE(EPT_VLT_PERM_EX); 2443 DIAGNOSE(EPT_VLT_LADDR_VLD); 2444 DIAGNOSE(EPT_VLT_PADDR); 2445 2446 #undef DIAGNOSE 2447 } 2448 2449 static void do_ept_access_op(enum ept_access_op op) 2450 { 2451 ept_access_test_data.op = op; 2452 enter_guest(); 2453 } 2454 2455 /* 2456 * Force the guest to flush its TLB (i.e., flush gva -> gpa mappings). Only 2457 * needed by tests that modify guest PTEs. 2458 */ 2459 static void ept_access_test_guest_flush_tlb(void) 2460 { 2461 do_ept_access_op(OP_FLUSH_TLB); 2462 skip_exit_vmcall(); 2463 } 2464 2465 /* 2466 * Modifies the EPT entry at @level in the mapping of @gpa. First clears the 2467 * bits in @clear then sets the bits in @set. @mkhuge transforms the entry into 2468 * a huge page. 2469 */ 2470 static unsigned long ept_twiddle(unsigned long gpa, bool mkhuge, int level, 2471 unsigned long clear, unsigned long set) 2472 { 2473 struct ept_access_test_data *data = &ept_access_test_data; 2474 unsigned long orig_pte; 2475 unsigned long pte; 2476 2477 /* Screw with the mapping at the requested level. */ 2478 TEST_ASSERT(get_ept_pte(pml4, gpa, level, &orig_pte)); 2479 pte = orig_pte; 2480 if (mkhuge) 2481 pte = (orig_pte & ~EPT_ADDR_MASK) | data->hpa | EPT_LARGE_PAGE; 2482 else 2483 pte = orig_pte; 2484 pte = (pte & ~clear) | set; 2485 set_ept_pte(pml4, gpa, level, pte); 2486 ept_sync(INVEPT_SINGLE, eptp); 2487 2488 return orig_pte; 2489 } 2490 2491 static void ept_untwiddle(unsigned long gpa, int level, unsigned long orig_pte) 2492 { 2493 set_ept_pte(pml4, gpa, level, orig_pte); 2494 ept_sync(INVEPT_SINGLE, eptp); 2495 } 2496 2497 static void do_ept_violation(bool leaf, enum ept_access_op op, 2498 u64 expected_qual, u64 expected_paddr) 2499 { 2500 u64 qual; 2501 2502 /* Try the access and observe the violation. */ 2503 do_ept_access_op(op); 2504 2505 assert_exit_reason(VMX_EPT_VIOLATION); 2506 2507 qual = vmcs_read(EXI_QUALIFICATION); 2508 2509 /* Mask undefined bits (which may later be defined in certain cases). */ 2510 qual &= ~(EPT_VLT_GUEST_USER | EPT_VLT_GUEST_RW | EPT_VLT_GUEST_EX | 2511 EPT_VLT_PERM_USER_EX); 2512 2513 diagnose_ept_violation_qual(expected_qual, qual); 2514 TEST_EXPECT_EQ(expected_qual, qual); 2515 2516 #if 0 2517 /* Disable for now otherwise every test will fail */ 2518 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2519 (unsigned long) ( 2520 op == OP_EXEC ? data->gva + 1 : data->gva)); 2521 #endif 2522 /* 2523 * TODO: tests that probe expected_paddr in pages other than the one at 2524 * the beginning of the 1g region. 2525 */ 2526 TEST_EXPECT_EQ(vmcs_read(INFO_PHYS_ADDR), expected_paddr); 2527 } 2528 2529 static void 2530 ept_violation_at_level_mkhuge(bool mkhuge, int level, unsigned long clear, 2531 unsigned long set, enum ept_access_op op, 2532 u64 expected_qual) 2533 { 2534 struct ept_access_test_data *data = &ept_access_test_data; 2535 unsigned long orig_pte; 2536 2537 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2538 2539 do_ept_violation(level == 1 || mkhuge, op, expected_qual, 2540 op == OP_EXEC ? data->gpa + sizeof(unsigned long) : 2541 data->gpa); 2542 2543 /* Fix the violation and resume the op loop. */ 2544 ept_untwiddle(data->gpa, level, orig_pte); 2545 enter_guest(); 2546 skip_exit_vmcall(); 2547 } 2548 2549 static void 2550 ept_violation_at_level(int level, unsigned long clear, unsigned long set, 2551 enum ept_access_op op, u64 expected_qual) 2552 { 2553 ept_violation_at_level_mkhuge(false, level, clear, set, op, 2554 expected_qual); 2555 if (ept_huge_pages_supported(level)) 2556 ept_violation_at_level_mkhuge(true, level, clear, set, op, 2557 expected_qual); 2558 } 2559 2560 static void ept_violation(unsigned long clear, unsigned long set, 2561 enum ept_access_op op, u64 expected_qual) 2562 { 2563 ept_violation_at_level(1, clear, set, op, expected_qual); 2564 ept_violation_at_level(2, clear, set, op, expected_qual); 2565 ept_violation_at_level(3, clear, set, op, expected_qual); 2566 ept_violation_at_level(4, clear, set, op, expected_qual); 2567 } 2568 2569 static void ept_access_violation(unsigned long access, enum ept_access_op op, 2570 u64 expected_qual) 2571 { 2572 ept_violation(EPT_PRESENT, access, op, 2573 expected_qual | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2574 } 2575 2576 /* 2577 * For translations that don't involve a GVA, that is physical address (paddr) 2578 * accesses, EPT violations don't set the flag EPT_VLT_PADDR. For a typical 2579 * guest memory access, the hardware does GVA -> GPA -> HPA. However, certain 2580 * translations don't involve GVAs, such as when the hardware does the guest 2581 * page table walk. For example, in translating GVA_1 -> GPA_1, the guest MMU 2582 * might try to set an A bit on a guest PTE. If the GPA_2 that the PTE resides 2583 * on isn't present in the EPT, then the EPT violation will be for GPA_2 and 2584 * the EPT_VLT_PADDR bit will be clear in the exit qualification. 2585 * 2586 * Note that paddr violations can also be triggered by loading PAE page tables 2587 * with wonky addresses. We don't test that yet. 2588 * 2589 * This function modifies the EPT entry that maps the GPA that the guest page 2590 * table entry mapping ept_access_test_data.gva resides on. 2591 * 2592 * @ept_access EPT permissions to set. Other permissions are cleared. 2593 * 2594 * @pte_ad Set the A/D bits on the guest PTE accordingly. 2595 * 2596 * @op Guest operation to perform with 2597 * ept_access_test_data.gva. 2598 * 2599 * @expect_violation 2600 * Is a violation expected during the paddr access? 2601 * 2602 * @expected_qual Expected qualification for the EPT violation. 2603 * EPT_VLT_PADDR should be clear. 2604 */ 2605 static void ept_access_paddr(unsigned long ept_access, unsigned long pte_ad, 2606 enum ept_access_op op, bool expect_violation, 2607 u64 expected_qual) 2608 { 2609 struct ept_access_test_data *data = &ept_access_test_data; 2610 unsigned long *ptep; 2611 unsigned long gpa; 2612 unsigned long orig_epte; 2613 unsigned long epte; 2614 int i; 2615 2616 /* Modify the guest PTE mapping data->gva according to @pte_ad. */ 2617 ptep = get_pte_level(current_page_table(), data->gva, /*level=*/1); 2618 TEST_ASSERT(ptep); 2619 TEST_ASSERT_EQ(*ptep & PT_ADDR_MASK, data->gpa); 2620 *ptep = (*ptep & ~PT_AD_MASK) | pte_ad; 2621 ept_access_test_guest_flush_tlb(); 2622 2623 /* 2624 * Now modify the access bits on the EPT entry for the GPA that the 2625 * guest PTE resides on. Note that by modifying a single EPT entry, 2626 * we're potentially affecting 512 guest PTEs. However, we've carefully 2627 * constructed our test such that those other 511 PTEs aren't used by 2628 * the guest: data->gva is at the beginning of a 1G huge page, thus the 2629 * PTE we're modifying is at the beginning of a 4K page and the 2630 * following 511 entires are also under our control (and not touched by 2631 * the guest). 2632 */ 2633 gpa = virt_to_phys(ptep); 2634 TEST_ASSERT_EQ(gpa & ~PAGE_MASK, 0); 2635 /* 2636 * Make sure the guest page table page is mapped with a 4K EPT entry, 2637 * otherwise our level=1 twiddling below will fail. We use the 2638 * identity map (gpa = gpa) since page tables are shared with the host. 2639 */ 2640 install_ept(pml4, gpa, gpa, EPT_PRESENT); 2641 orig_epte = ept_twiddle(gpa, /*mkhuge=*/0, /*level=*/1, 2642 /*clear=*/EPT_PRESENT, /*set=*/ept_access); 2643 2644 if (expect_violation) { 2645 do_ept_violation(/*leaf=*/true, op, 2646 expected_qual | EPT_VLT_LADDR_VLD, gpa); 2647 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2648 do_ept_access_op(op); 2649 } else { 2650 do_ept_access_op(op); 2651 if (ept_ad_enabled()) { 2652 for (i = EPT_PAGE_LEVEL; i > 0; i--) { 2653 TEST_ASSERT(get_ept_pte(pml4, gpa, i, &epte)); 2654 TEST_ASSERT(epte & EPT_ACCESS_FLAG); 2655 if (i == 1) 2656 TEST_ASSERT(epte & EPT_DIRTY_FLAG); 2657 else 2658 TEST_ASSERT_EQ(epte & EPT_DIRTY_FLAG, 0); 2659 } 2660 } 2661 2662 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2663 } 2664 2665 TEST_ASSERT(*ptep & PT_ACCESSED_MASK); 2666 if ((pte_ad & PT_DIRTY_MASK) || op == OP_WRITE) 2667 TEST_ASSERT(*ptep & PT_DIRTY_MASK); 2668 2669 skip_exit_vmcall(); 2670 } 2671 2672 static void ept_access_allowed_paddr(unsigned long ept_access, 2673 unsigned long pte_ad, 2674 enum ept_access_op op) 2675 { 2676 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/false, 2677 /*expected_qual=*/-1); 2678 } 2679 2680 static void ept_access_violation_paddr(unsigned long ept_access, 2681 unsigned long pte_ad, 2682 enum ept_access_op op, 2683 u64 expected_qual) 2684 { 2685 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/true, 2686 expected_qual); 2687 } 2688 2689 2690 static void ept_allowed_at_level_mkhuge(bool mkhuge, int level, 2691 unsigned long clear, 2692 unsigned long set, 2693 enum ept_access_op op) 2694 { 2695 struct ept_access_test_data *data = &ept_access_test_data; 2696 unsigned long orig_pte; 2697 2698 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2699 2700 /* No violation. Should proceed to vmcall. */ 2701 do_ept_access_op(op); 2702 skip_exit_vmcall(); 2703 2704 ept_untwiddle(data->gpa, level, orig_pte); 2705 } 2706 2707 static void ept_allowed_at_level(int level, unsigned long clear, 2708 unsigned long set, enum ept_access_op op) 2709 { 2710 ept_allowed_at_level_mkhuge(false, level, clear, set, op); 2711 if (ept_huge_pages_supported(level)) 2712 ept_allowed_at_level_mkhuge(true, level, clear, set, op); 2713 } 2714 2715 static void ept_allowed(unsigned long clear, unsigned long set, 2716 enum ept_access_op op) 2717 { 2718 ept_allowed_at_level(1, clear, set, op); 2719 ept_allowed_at_level(2, clear, set, op); 2720 ept_allowed_at_level(3, clear, set, op); 2721 ept_allowed_at_level(4, clear, set, op); 2722 } 2723 2724 static void ept_ignored_bit(int bit) 2725 { 2726 /* Set the bit. */ 2727 ept_allowed(0, 1ul << bit, OP_READ); 2728 ept_allowed(0, 1ul << bit, OP_WRITE); 2729 ept_allowed(0, 1ul << bit, OP_EXEC); 2730 2731 /* Clear the bit. */ 2732 ept_allowed(1ul << bit, 0, OP_READ); 2733 ept_allowed(1ul << bit, 0, OP_WRITE); 2734 ept_allowed(1ul << bit, 0, OP_EXEC); 2735 } 2736 2737 static void ept_access_allowed(unsigned long access, enum ept_access_op op) 2738 { 2739 ept_allowed(EPT_PRESENT, access, op); 2740 } 2741 2742 2743 static void ept_misconfig_at_level_mkhuge_op(bool mkhuge, int level, 2744 unsigned long clear, 2745 unsigned long set, 2746 enum ept_access_op op) 2747 { 2748 struct ept_access_test_data *data = &ept_access_test_data; 2749 unsigned long orig_pte; 2750 2751 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2752 2753 do_ept_access_op(op); 2754 assert_exit_reason(VMX_EPT_MISCONFIG); 2755 2756 /* Intel 27.2.1, "For all other VM exits, this field is cleared." */ 2757 #if 0 2758 /* broken: */ 2759 TEST_EXPECT_EQ_MSG(vmcs_read(EXI_QUALIFICATION), 0); 2760 #endif 2761 #if 0 2762 /* 2763 * broken: 2764 * According to description of exit qual for EPT violation, 2765 * EPT_VLT_LADDR_VLD indicates if GUEST_LINEAR_ADDRESS is valid. 2766 * However, I can't find anything that says GUEST_LINEAR_ADDRESS ought 2767 * to be set for msiconfig. 2768 */ 2769 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2770 (unsigned long) ( 2771 op == OP_EXEC ? data->gva + 1 : data->gva)); 2772 #endif 2773 2774 /* Fix the violation and resume the op loop. */ 2775 ept_untwiddle(data->gpa, level, orig_pte); 2776 enter_guest(); 2777 skip_exit_vmcall(); 2778 } 2779 2780 static void ept_misconfig_at_level_mkhuge(bool mkhuge, int level, 2781 unsigned long clear, 2782 unsigned long set) 2783 { 2784 /* The op shouldn't matter (read, write, exec), so try them all! */ 2785 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_READ); 2786 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_WRITE); 2787 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_EXEC); 2788 } 2789 2790 static void ept_misconfig_at_level(int level, unsigned long clear, 2791 unsigned long set) 2792 { 2793 ept_misconfig_at_level_mkhuge(false, level, clear, set); 2794 if (ept_huge_pages_supported(level)) 2795 ept_misconfig_at_level_mkhuge(true, level, clear, set); 2796 } 2797 2798 static void ept_misconfig(unsigned long clear, unsigned long set) 2799 { 2800 ept_misconfig_at_level(1, clear, set); 2801 ept_misconfig_at_level(2, clear, set); 2802 ept_misconfig_at_level(3, clear, set); 2803 ept_misconfig_at_level(4, clear, set); 2804 } 2805 2806 static void ept_access_misconfig(unsigned long access) 2807 { 2808 ept_misconfig(EPT_PRESENT, access); 2809 } 2810 2811 static void ept_reserved_bit_at_level_nohuge(int level, int bit) 2812 { 2813 /* Setting the bit causes a misconfig. */ 2814 ept_misconfig_at_level_mkhuge(false, level, 0, 1ul << bit); 2815 2816 /* Making the entry non-present turns reserved bits into ignored. */ 2817 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2818 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2819 } 2820 2821 static void ept_reserved_bit_at_level_huge(int level, int bit) 2822 { 2823 /* Setting the bit causes a misconfig. */ 2824 ept_misconfig_at_level_mkhuge(true, level, 0, 1ul << bit); 2825 2826 /* Making the entry non-present turns reserved bits into ignored. */ 2827 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2828 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2829 } 2830 2831 static void ept_reserved_bit_at_level(int level, int bit) 2832 { 2833 /* Setting the bit causes a misconfig. */ 2834 ept_misconfig_at_level(level, 0, 1ul << bit); 2835 2836 /* Making the entry non-present turns reserved bits into ignored. */ 2837 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2838 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2839 } 2840 2841 static void ept_reserved_bit(int bit) 2842 { 2843 ept_reserved_bit_at_level(1, bit); 2844 ept_reserved_bit_at_level(2, bit); 2845 ept_reserved_bit_at_level(3, bit); 2846 ept_reserved_bit_at_level(4, bit); 2847 } 2848 2849 #define PAGE_2M_ORDER 9 2850 #define PAGE_1G_ORDER 18 2851 2852 static void *get_1g_page(void) 2853 { 2854 static void *alloc; 2855 2856 if (!alloc) 2857 alloc = alloc_pages(PAGE_1G_ORDER); 2858 return alloc; 2859 } 2860 2861 static void ept_access_test_teardown(void *unused) 2862 { 2863 /* Exit the guest cleanly. */ 2864 do_ept_access_op(OP_EXIT); 2865 } 2866 2867 static void ept_access_test_guest(void) 2868 { 2869 struct ept_access_test_data *data = &ept_access_test_data; 2870 int (*code)(void) = (int (*)(void)) &data->gva[1]; 2871 2872 while (true) { 2873 switch (data->op) { 2874 case OP_READ: 2875 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_1); 2876 break; 2877 case OP_WRITE: 2878 *data->gva = MAGIC_VAL_2; 2879 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_2); 2880 *data->gva = MAGIC_VAL_1; 2881 break; 2882 case OP_EXEC: 2883 TEST_ASSERT_EQ(42, code()); 2884 break; 2885 case OP_FLUSH_TLB: 2886 write_cr3(read_cr3()); 2887 break; 2888 case OP_EXIT: 2889 return; 2890 default: 2891 TEST_ASSERT_MSG(false, "Unknown op %d", data->op); 2892 } 2893 vmcall(); 2894 } 2895 } 2896 2897 static void ept_access_test_setup(void) 2898 { 2899 struct ept_access_test_data *data = &ept_access_test_data; 2900 unsigned long npages = 1ul << PAGE_1G_ORDER; 2901 unsigned long size = npages * PAGE_SIZE; 2902 unsigned long *page_table = current_page_table(); 2903 unsigned long pte; 2904 2905 if (setup_ept(false)) 2906 test_skip("EPT not supported"); 2907 2908 /* We use data->gpa = 1 << 39 so that test data has a separate pml4 entry */ 2909 if (cpuid_maxphyaddr() < 40) 2910 test_skip("Test needs MAXPHYADDR >= 40"); 2911 2912 test_set_guest(ept_access_test_guest); 2913 test_add_teardown(ept_access_test_teardown, NULL); 2914 2915 data->hva = get_1g_page(); 2916 TEST_ASSERT(data->hva); 2917 data->hpa = virt_to_phys(data->hva); 2918 2919 data->gpa = 1ul << 39; 2920 data->gva = (void *) ALIGN((unsigned long) alloc_vpages(npages * 2), 2921 size); 2922 TEST_ASSERT(!any_present_pages(page_table, data->gva, size)); 2923 install_pages(page_table, data->gpa, size, data->gva); 2924 2925 /* 2926 * Make sure nothing's mapped here so the tests that screw with the 2927 * pml4 entry don't inadvertently break something. 2928 */ 2929 TEST_ASSERT(get_ept_pte(pml4, data->gpa, 4, &pte) && pte == 0); 2930 TEST_ASSERT(get_ept_pte(pml4, data->gpa + size - 1, 4, &pte) && pte == 0); 2931 install_ept(pml4, data->hpa, data->gpa, EPT_PRESENT); 2932 2933 data->hva[0] = MAGIC_VAL_1; 2934 memcpy(&data->hva[1], &ret42_start, &ret42_end - &ret42_start); 2935 } 2936 2937 static void ept_access_test_not_present(void) 2938 { 2939 ept_access_test_setup(); 2940 /* --- */ 2941 ept_access_violation(0, OP_READ, EPT_VLT_RD); 2942 ept_access_violation(0, OP_WRITE, EPT_VLT_WR); 2943 ept_access_violation(0, OP_EXEC, EPT_VLT_FETCH); 2944 } 2945 2946 static void ept_access_test_read_only(void) 2947 { 2948 ept_access_test_setup(); 2949 2950 /* r-- */ 2951 ept_access_allowed(EPT_RA, OP_READ); 2952 ept_access_violation(EPT_RA, OP_WRITE, EPT_VLT_WR | EPT_VLT_PERM_RD); 2953 ept_access_violation(EPT_RA, OP_EXEC, EPT_VLT_FETCH | EPT_VLT_PERM_RD); 2954 } 2955 2956 static void ept_access_test_write_only(void) 2957 { 2958 ept_access_test_setup(); 2959 /* -w- */ 2960 ept_access_misconfig(EPT_WA); 2961 } 2962 2963 static void ept_access_test_read_write(void) 2964 { 2965 ept_access_test_setup(); 2966 /* rw- */ 2967 ept_access_allowed(EPT_RA | EPT_WA, OP_READ); 2968 ept_access_allowed(EPT_RA | EPT_WA, OP_WRITE); 2969 ept_access_violation(EPT_RA | EPT_WA, OP_EXEC, 2970 EPT_VLT_FETCH | EPT_VLT_PERM_RD | EPT_VLT_PERM_WR); 2971 } 2972 2973 2974 static void ept_access_test_execute_only(void) 2975 { 2976 ept_access_test_setup(); 2977 /* --x */ 2978 if (ept_execute_only_supported()) { 2979 ept_access_violation(EPT_EA, OP_READ, 2980 EPT_VLT_RD | EPT_VLT_PERM_EX); 2981 ept_access_violation(EPT_EA, OP_WRITE, 2982 EPT_VLT_WR | EPT_VLT_PERM_EX); 2983 ept_access_allowed(EPT_EA, OP_EXEC); 2984 } else { 2985 ept_access_misconfig(EPT_EA); 2986 } 2987 } 2988 2989 static void ept_access_test_read_execute(void) 2990 { 2991 ept_access_test_setup(); 2992 /* r-x */ 2993 ept_access_allowed(EPT_RA | EPT_EA, OP_READ); 2994 ept_access_violation(EPT_RA | EPT_EA, OP_WRITE, 2995 EPT_VLT_WR | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX); 2996 ept_access_allowed(EPT_RA | EPT_EA, OP_EXEC); 2997 } 2998 2999 static void ept_access_test_write_execute(void) 3000 { 3001 ept_access_test_setup(); 3002 /* -wx */ 3003 ept_access_misconfig(EPT_WA | EPT_EA); 3004 } 3005 3006 static void ept_access_test_read_write_execute(void) 3007 { 3008 ept_access_test_setup(); 3009 /* rwx */ 3010 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_READ); 3011 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_WRITE); 3012 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_EXEC); 3013 } 3014 3015 static void ept_access_test_reserved_bits(void) 3016 { 3017 int i; 3018 int maxphyaddr; 3019 3020 ept_access_test_setup(); 3021 3022 /* Reserved bits above maxphyaddr. */ 3023 maxphyaddr = cpuid_maxphyaddr(); 3024 for (i = maxphyaddr; i <= 51; i++) { 3025 report_prefix_pushf("reserved_bit=%d", i); 3026 ept_reserved_bit(i); 3027 report_prefix_pop(); 3028 } 3029 3030 /* Level-specific reserved bits. */ 3031 ept_reserved_bit_at_level_nohuge(2, 3); 3032 ept_reserved_bit_at_level_nohuge(2, 4); 3033 ept_reserved_bit_at_level_nohuge(2, 5); 3034 ept_reserved_bit_at_level_nohuge(2, 6); 3035 /* 2M alignment. */ 3036 for (i = 12; i < 20; i++) { 3037 report_prefix_pushf("reserved_bit=%d", i); 3038 ept_reserved_bit_at_level_huge(2, i); 3039 report_prefix_pop(); 3040 } 3041 ept_reserved_bit_at_level_nohuge(3, 3); 3042 ept_reserved_bit_at_level_nohuge(3, 4); 3043 ept_reserved_bit_at_level_nohuge(3, 5); 3044 ept_reserved_bit_at_level_nohuge(3, 6); 3045 /* 1G alignment. */ 3046 for (i = 12; i < 29; i++) { 3047 report_prefix_pushf("reserved_bit=%d", i); 3048 ept_reserved_bit_at_level_huge(3, i); 3049 report_prefix_pop(); 3050 } 3051 ept_reserved_bit_at_level(4, 3); 3052 ept_reserved_bit_at_level(4, 4); 3053 ept_reserved_bit_at_level(4, 5); 3054 ept_reserved_bit_at_level(4, 6); 3055 ept_reserved_bit_at_level(4, 7); 3056 } 3057 3058 static void ept_access_test_ignored_bits(void) 3059 { 3060 ept_access_test_setup(); 3061 /* 3062 * Bits ignored at every level. Bits 8 and 9 (A and D) are ignored as 3063 * far as translation is concerned even if AD bits are enabled in the 3064 * EPTP. Bit 63 is ignored because "EPT-violation #VE" VM-execution 3065 * control is 0. 3066 */ 3067 ept_ignored_bit(8); 3068 ept_ignored_bit(9); 3069 ept_ignored_bit(10); 3070 ept_ignored_bit(11); 3071 ept_ignored_bit(52); 3072 ept_ignored_bit(53); 3073 ept_ignored_bit(54); 3074 ept_ignored_bit(55); 3075 ept_ignored_bit(56); 3076 ept_ignored_bit(57); 3077 ept_ignored_bit(58); 3078 ept_ignored_bit(59); 3079 ept_ignored_bit(60); 3080 ept_ignored_bit(61); 3081 ept_ignored_bit(62); 3082 ept_ignored_bit(63); 3083 } 3084 3085 static void ept_access_test_paddr_not_present_ad_disabled(void) 3086 { 3087 ept_access_test_setup(); 3088 ept_disable_ad_bits(); 3089 3090 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, EPT_VLT_RD); 3091 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, EPT_VLT_RD); 3092 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, EPT_VLT_RD); 3093 } 3094 3095 static void ept_access_test_paddr_not_present_ad_enabled(void) 3096 { 3097 u64 qual = EPT_VLT_RD | EPT_VLT_WR; 3098 3099 ept_access_test_setup(); 3100 ept_enable_ad_bits_or_skip_test(); 3101 3102 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, qual); 3103 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, qual); 3104 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, qual); 3105 } 3106 3107 static void ept_access_test_paddr_read_only_ad_disabled(void) 3108 { 3109 /* 3110 * When EPT AD bits are disabled, all accesses to guest paging 3111 * structures are reported separately as a read and (after 3112 * translation of the GPA to host physical address) a read+write 3113 * if the A/D bits have to be set. 3114 */ 3115 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 3116 3117 ept_access_test_setup(); 3118 ept_disable_ad_bits(); 3119 3120 /* Can't update A bit, so all accesses fail. */ 3121 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 3122 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 3123 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 3124 /* AD bits disabled, so only writes try to update the D bit. */ 3125 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ); 3126 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 3127 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC); 3128 /* Both A and D already set, so read-only is OK. */ 3129 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_READ); 3130 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_WRITE); 3131 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_EXEC); 3132 } 3133 3134 static void ept_access_test_paddr_read_only_ad_enabled(void) 3135 { 3136 /* 3137 * When EPT AD bits are enabled, all accesses to guest paging 3138 * structures are considered writes as far as EPT translation 3139 * is concerned. 3140 */ 3141 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 3142 3143 ept_access_test_setup(); 3144 ept_enable_ad_bits_or_skip_test(); 3145 3146 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 3147 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 3148 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 3149 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ, qual); 3150 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 3151 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC, qual); 3152 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_READ, qual); 3153 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_WRITE, qual); 3154 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_EXEC, qual); 3155 } 3156 3157 static void ept_access_test_paddr_read_write(void) 3158 { 3159 ept_access_test_setup(); 3160 /* Read-write access to paging structure. */ 3161 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_READ); 3162 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_WRITE); 3163 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_EXEC); 3164 } 3165 3166 static void ept_access_test_paddr_read_write_execute(void) 3167 { 3168 ept_access_test_setup(); 3169 /* RWX access to paging structure. */ 3170 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_READ); 3171 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_WRITE); 3172 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_EXEC); 3173 } 3174 3175 static void ept_access_test_paddr_read_execute_ad_disabled(void) 3176 { 3177 /* 3178 * When EPT AD bits are disabled, all accesses to guest paging 3179 * structures are reported separately as a read and (after 3180 * translation of the GPA to host physical address) a read+write 3181 * if the A/D bits have to be set. 3182 */ 3183 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3184 3185 ept_access_test_setup(); 3186 ept_disable_ad_bits(); 3187 3188 /* Can't update A bit, so all accesses fail. */ 3189 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3190 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3191 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3192 /* AD bits disabled, so only writes try to update the D bit. */ 3193 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ); 3194 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3195 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC); 3196 /* Both A and D already set, so read-only is OK. */ 3197 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ); 3198 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE); 3199 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC); 3200 } 3201 3202 static void ept_access_test_paddr_read_execute_ad_enabled(void) 3203 { 3204 /* 3205 * When EPT AD bits are enabled, all accesses to guest paging 3206 * structures are considered writes as far as EPT translation 3207 * is concerned. 3208 */ 3209 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3210 3211 ept_access_test_setup(); 3212 ept_enable_ad_bits_or_skip_test(); 3213 3214 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3215 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3216 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3217 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ, qual); 3218 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3219 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC, qual); 3220 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ, qual); 3221 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE, qual); 3222 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC, qual); 3223 } 3224 3225 static void ept_access_test_paddr_not_present_page_fault(void) 3226 { 3227 ept_access_test_setup(); 3228 /* 3229 * TODO: test no EPT violation as long as guest PF occurs. e.g., GPA is 3230 * page is read-only in EPT but GVA is also mapped read only in PT. 3231 * Thus guest page fault before host takes EPT violation for trying to 3232 * update A bit. 3233 */ 3234 } 3235 3236 static void ept_access_test_force_2m_page(void) 3237 { 3238 ept_access_test_setup(); 3239 3240 TEST_ASSERT_EQ(ept_2m_supported(), true); 3241 ept_allowed_at_level_mkhuge(true, 2, 0, 0, OP_READ); 3242 ept_violation_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_RA, OP_WRITE, 3243 EPT_VLT_WR | EPT_VLT_PERM_RD | 3244 EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 3245 ept_misconfig_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_WA); 3246 } 3247 3248 static bool invvpid_valid(u64 type, u64 vpid, u64 gla) 3249 { 3250 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3251 3252 TEST_ASSERT(msr & VPID_CAP_INVVPID); 3253 3254 if (type < INVVPID_ADDR || type > INVVPID_CONTEXT_LOCAL) 3255 return false; 3256 3257 if (!(msr & (1ull << (type + VPID_CAP_INVVPID_TYPES_SHIFT)))) 3258 return false; 3259 3260 if (vpid >> 16) 3261 return false; 3262 3263 if (type != INVVPID_ALL && !vpid) 3264 return false; 3265 3266 if (type == INVVPID_ADDR && !is_canonical(gla)) 3267 return false; 3268 3269 return true; 3270 } 3271 3272 static void try_invvpid(u64 type, u64 vpid, u64 gla) 3273 { 3274 int rc; 3275 bool valid = invvpid_valid(type, vpid, gla); 3276 u64 expected = valid ? VMXERR_UNSUPPORTED_VMCS_COMPONENT 3277 : VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID; 3278 /* 3279 * Set VMX_INST_ERROR to VMXERR_UNVALID_VMCS_COMPONENT, so 3280 * that we can tell if it is updated by INVVPID. 3281 */ 3282 vmcs_read(~0); 3283 rc = invvpid(type, vpid, gla); 3284 report(!rc == valid, "INVVPID type %ld VPID %lx GLA %lx %s", type, 3285 vpid, gla, 3286 valid ? "passes" : "fails"); 3287 report(vmcs_read(VMX_INST_ERROR) == expected, 3288 "After %s INVVPID, VMX_INST_ERR is %ld (actual %ld)", 3289 rc ? "failed" : "successful", 3290 expected, vmcs_read(VMX_INST_ERROR)); 3291 } 3292 3293 static void ds_invvpid(void *data) 3294 { 3295 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3296 u64 type = ffs(msr >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 3297 3298 TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 3299 asm volatile("invvpid %0, %1" 3300 : 3301 : "m"(*(struct invvpid_operand *)data), 3302 "r"(type)); 3303 } 3304 3305 /* 3306 * The SS override is ignored in 64-bit mode, so we use an addressing 3307 * mode with %rsp as the base register to generate an implicit SS 3308 * reference. 3309 */ 3310 static void ss_invvpid(void *data) 3311 { 3312 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3313 u64 type = ffs(msr >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 3314 3315 TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 3316 asm volatile("sub %%rsp,%0; invvpid (%%rsp,%0,1), %1" 3317 : "+r"(data) 3318 : "r"(type)); 3319 } 3320 3321 static void invvpid_test_gp(void) 3322 { 3323 bool fault; 3324 3325 fault = test_for_exception(GP_VECTOR, &ds_invvpid, 3326 (void *)NONCANONICAL); 3327 report(fault, "INVVPID with non-canonical DS operand raises #GP"); 3328 } 3329 3330 static void invvpid_test_ss(void) 3331 { 3332 bool fault; 3333 3334 fault = test_for_exception(SS_VECTOR, &ss_invvpid, 3335 (void *)NONCANONICAL); 3336 report(fault, "INVVPID with non-canonical SS operand raises #SS"); 3337 } 3338 3339 static void invvpid_test_pf(void) 3340 { 3341 void *vpage = alloc_vpage(); 3342 bool fault; 3343 3344 fault = test_for_exception(PF_VECTOR, &ds_invvpid, vpage); 3345 report(fault, "INVVPID with unmapped operand raises #PF"); 3346 } 3347 3348 static void try_compat_invvpid(void *unused) 3349 { 3350 struct far_pointer32 fp = { 3351 .offset = (uintptr_t)&&invvpid, 3352 .selector = KERNEL_CS32, 3353 }; 3354 uintptr_t rsp; 3355 3356 asm volatile ("mov %%rsp, %0" : "=r"(rsp)); 3357 3358 TEST_ASSERT_MSG(fp.offset == (uintptr_t)&&invvpid, 3359 "Code address too high."); 3360 TEST_ASSERT_MSG(rsp == (u32)rsp, "Stack address too high."); 3361 3362 asm goto ("lcall *%0" : : "m" (fp) : "rax" : invvpid); 3363 return; 3364 invvpid: 3365 asm volatile (".code32;" 3366 "invvpid (%eax), %eax;" 3367 "lret;" 3368 ".code64"); 3369 __builtin_unreachable(); 3370 } 3371 3372 static void invvpid_test_compatibility_mode(void) 3373 { 3374 bool fault; 3375 3376 fault = test_for_exception(UD_VECTOR, &try_compat_invvpid, NULL); 3377 report(fault, "Compatibility mode INVVPID raises #UD"); 3378 } 3379 3380 static void invvpid_test_not_in_vmx_operation(void) 3381 { 3382 bool fault; 3383 3384 TEST_ASSERT(!vmx_off()); 3385 fault = test_for_exception(UD_VECTOR, &ds_invvpid, NULL); 3386 report(fault, "INVVPID outside of VMX operation raises #UD"); 3387 TEST_ASSERT(!vmx_on()); 3388 } 3389 3390 /* 3391 * This does not test real-address mode, virtual-8086 mode, protected mode, 3392 * or CPL > 0. 3393 */ 3394 static void invvpid_test_v2(void) 3395 { 3396 u64 msr; 3397 int i; 3398 unsigned types = 0; 3399 unsigned type; 3400 3401 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 3402 !(ctrl_cpu_rev[1].clr & CPU_VPID)) 3403 test_skip("VPID not supported"); 3404 3405 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3406 3407 if (!(msr & VPID_CAP_INVVPID)) 3408 test_skip("INVVPID not supported.\n"); 3409 3410 if (msr & VPID_CAP_INVVPID_ADDR) 3411 types |= 1u << INVVPID_ADDR; 3412 if (msr & VPID_CAP_INVVPID_CXTGLB) 3413 types |= 1u << INVVPID_CONTEXT_GLOBAL; 3414 if (msr & VPID_CAP_INVVPID_ALL) 3415 types |= 1u << INVVPID_ALL; 3416 if (msr & VPID_CAP_INVVPID_CXTLOC) 3417 types |= 1u << INVVPID_CONTEXT_LOCAL; 3418 3419 if (!types) 3420 test_skip("No INVVPID types supported.\n"); 3421 3422 for (i = -127; i < 128; i++) 3423 try_invvpid(i, 0xffff, 0); 3424 3425 /* 3426 * VPID must not be more than 16 bits. 3427 */ 3428 for (i = 0; i < 64; i++) 3429 for (type = 0; type < 4; type++) 3430 if (types & (1u << type)) 3431 try_invvpid(type, 1ul << i, 0); 3432 3433 /* 3434 * VPID must not be zero, except for "all contexts." 3435 */ 3436 for (type = 0; type < 4; type++) 3437 if (types & (1u << type)) 3438 try_invvpid(type, 0, 0); 3439 3440 /* 3441 * The gla operand is only validated for single-address INVVPID. 3442 */ 3443 if (types & (1u << INVVPID_ADDR)) 3444 try_invvpid(INVVPID_ADDR, 0xffff, NONCANONICAL); 3445 3446 invvpid_test_gp(); 3447 invvpid_test_ss(); 3448 invvpid_test_pf(); 3449 invvpid_test_compatibility_mode(); 3450 invvpid_test_not_in_vmx_operation(); 3451 } 3452 3453 /* 3454 * Test for early VMLAUNCH failure. Returns true if VMLAUNCH makes it 3455 * at least as far as the guest-state checks. Returns false if the 3456 * VMLAUNCH fails early and execution falls through to the next 3457 * instruction. 3458 */ 3459 static bool vmlaunch_succeeds(void) 3460 { 3461 u32 exit_reason; 3462 3463 /* 3464 * Indirectly set VMX_INST_ERR to 12 ("VMREAD/VMWRITE from/to 3465 * unsupported VMCS component"). The caller can then check 3466 * to see if a failed VM-entry sets VMX_INST_ERR as expected. 3467 */ 3468 vmcs_write(~0u, 0); 3469 3470 vmcs_write(HOST_RIP, (uintptr_t)&&success); 3471 __asm__ __volatile__ goto ("vmwrite %%rsp, %0; vmlaunch" 3472 : 3473 : "r" ((u64)HOST_RSP) 3474 : "cc", "memory" 3475 : success); 3476 return false; 3477 success: 3478 exit_reason = vmcs_read(EXI_REASON); 3479 TEST_ASSERT(exit_reason == (VMX_FAIL_STATE | VMX_ENTRY_FAILURE) || 3480 exit_reason == (VMX_FAIL_MSR | VMX_ENTRY_FAILURE)); 3481 return true; 3482 } 3483 3484 /* 3485 * Try to launch the current VMCS. 3486 */ 3487 static void test_vmx_vmlaunch(u32 xerror) 3488 { 3489 bool success = vmlaunch_succeeds(); 3490 u32 vmx_inst_err; 3491 3492 report(success == !xerror, "vmlaunch %s", 3493 !xerror ? "succeeds" : "fails"); 3494 if (!success && xerror) { 3495 vmx_inst_err = vmcs_read(VMX_INST_ERROR); 3496 report(vmx_inst_err == xerror, 3497 "VMX inst error is %d (actual %d)", xerror, 3498 vmx_inst_err); 3499 } 3500 } 3501 3502 /* 3503 * Try to launch the current VMCS, and expect one of two possible 3504 * errors (or success) codes. 3505 */ 3506 static void test_vmx_vmlaunch2(u32 xerror1, u32 xerror2) 3507 { 3508 bool success = vmlaunch_succeeds(); 3509 u32 vmx_inst_err; 3510 3511 if (!xerror1 == !xerror2) 3512 report(success == !xerror1, "vmlaunch %s", 3513 !xerror1 ? "succeeds" : "fails"); 3514 3515 if (!success && (xerror1 || xerror2)) { 3516 vmx_inst_err = vmcs_read(VMX_INST_ERROR); 3517 report(vmx_inst_err == xerror1 || vmx_inst_err == xerror2, 3518 "VMX inst error is %d or %d (actual %d)", xerror1, 3519 xerror2, vmx_inst_err); 3520 } 3521 } 3522 3523 static void test_vmx_invalid_controls(void) 3524 { 3525 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_CONTROL_FIELD); 3526 } 3527 3528 static void test_vmx_valid_controls(void) 3529 { 3530 test_vmx_vmlaunch(0); 3531 } 3532 3533 /* 3534 * Test a particular value of a VM-execution control bit, if the value 3535 * is required or if the value is zero. 3536 */ 3537 static void test_rsvd_ctl_bit_value(const char *name, union vmx_ctrl_msr msr, 3538 enum Encoding encoding, unsigned bit, 3539 unsigned val) 3540 { 3541 u32 mask = 1u << bit; 3542 bool expected; 3543 u32 controls; 3544 3545 if (msr.set & mask) 3546 TEST_ASSERT(msr.clr & mask); 3547 3548 /* 3549 * We can't arbitrarily turn on a control bit, because it may 3550 * introduce dependencies on other VMCS fields. So, we only 3551 * test turning on bits that have a required setting. 3552 */ 3553 if (val && (msr.clr & mask) && !(msr.set & mask)) 3554 return; 3555 3556 report_prefix_pushf("%s %s bit %d", 3557 val ? "Set" : "Clear", name, bit); 3558 3559 controls = vmcs_read(encoding); 3560 if (val) { 3561 vmcs_write(encoding, msr.set | mask); 3562 expected = (msr.clr & mask); 3563 } else { 3564 vmcs_write(encoding, msr.set & ~mask); 3565 expected = !(msr.set & mask); 3566 } 3567 if (expected) 3568 test_vmx_valid_controls(); 3569 else 3570 test_vmx_invalid_controls(); 3571 vmcs_write(encoding, controls); 3572 report_prefix_pop(); 3573 } 3574 3575 /* 3576 * Test reserved values of a VM-execution control bit, based on the 3577 * allowed bit settings from the corresponding VMX capability MSR. 3578 */ 3579 static void test_rsvd_ctl_bit(const char *name, union vmx_ctrl_msr msr, 3580 enum Encoding encoding, unsigned bit) 3581 { 3582 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 0); 3583 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 1); 3584 } 3585 3586 /* 3587 * Reserved bits in the pin-based VM-execution controls must be set 3588 * properly. Software may consult the VMX capability MSRs to determine 3589 * the proper settings. 3590 * [Intel SDM] 3591 */ 3592 static void test_pin_based_ctls(void) 3593 { 3594 unsigned bit; 3595 3596 printf("%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PIN" : 3597 "MSR_IA32_VMX_PINBASED_CTLS", ctrl_pin_rev.val); 3598 for (bit = 0; bit < 32; bit++) 3599 test_rsvd_ctl_bit("pin-based controls", 3600 ctrl_pin_rev, PIN_CONTROLS, bit); 3601 } 3602 3603 /* 3604 * Reserved bits in the primary processor-based VM-execution controls 3605 * must be set properly. Software may consult the VMX capability MSRs 3606 * to determine the proper settings. 3607 * [Intel SDM] 3608 */ 3609 static void test_primary_processor_based_ctls(void) 3610 { 3611 unsigned bit; 3612 3613 printf("\n%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PROC" : 3614 "MSR_IA32_VMX_PROCBASED_CTLS", ctrl_cpu_rev[0].val); 3615 for (bit = 0; bit < 32; bit++) 3616 test_rsvd_ctl_bit("primary processor-based controls", 3617 ctrl_cpu_rev[0], CPU_EXEC_CTRL0, bit); 3618 } 3619 3620 /* 3621 * If the "activate secondary controls" primary processor-based 3622 * VM-execution control is 1, reserved bits in the secondary 3623 * processor-based VM-execution controls must be cleared. Software may 3624 * consult the VMX capability MSRs to determine which bits are 3625 * reserved. 3626 * If the "activate secondary controls" primary processor-based 3627 * VM-execution control is 0 (or if the processor does not support the 3628 * 1-setting of that control), no checks are performed on the 3629 * secondary processor-based VM-execution controls. 3630 * [Intel SDM] 3631 */ 3632 static void test_secondary_processor_based_ctls(void) 3633 { 3634 u32 primary; 3635 u32 secondary; 3636 unsigned bit; 3637 3638 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) 3639 return; 3640 3641 primary = vmcs_read(CPU_EXEC_CTRL0); 3642 secondary = vmcs_read(CPU_EXEC_CTRL1); 3643 3644 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3645 printf("\nMSR_IA32_VMX_PROCBASED_CTLS2: %lx\n", ctrl_cpu_rev[1].val); 3646 for (bit = 0; bit < 32; bit++) 3647 test_rsvd_ctl_bit("secondary processor-based controls", 3648 ctrl_cpu_rev[1], CPU_EXEC_CTRL1, bit); 3649 3650 /* 3651 * When the "activate secondary controls" VM-execution control 3652 * is clear, there are no checks on the secondary controls. 3653 */ 3654 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3655 vmcs_write(CPU_EXEC_CTRL1, ~0); 3656 report(vmlaunch_succeeds(), 3657 "Secondary processor-based controls ignored"); 3658 vmcs_write(CPU_EXEC_CTRL1, secondary); 3659 vmcs_write(CPU_EXEC_CTRL0, primary); 3660 } 3661 3662 static void try_cr3_target_count(unsigned i, unsigned max) 3663 { 3664 report_prefix_pushf("CR3 target count 0x%x", i); 3665 vmcs_write(CR3_TARGET_COUNT, i); 3666 if (i <= max) 3667 test_vmx_valid_controls(); 3668 else 3669 test_vmx_invalid_controls(); 3670 report_prefix_pop(); 3671 } 3672 3673 /* 3674 * The CR3-target count must not be greater than 4. Future processors 3675 * may support a different number of CR3-target values. Software 3676 * should read the VMX capability MSR IA32_VMX_MISC to determine the 3677 * number of values supported. 3678 * [Intel SDM] 3679 */ 3680 static void test_cr3_targets(void) 3681 { 3682 unsigned supported_targets = (rdmsr(MSR_IA32_VMX_MISC) >> 16) & 0x1ff; 3683 u32 cr3_targets = vmcs_read(CR3_TARGET_COUNT); 3684 unsigned i; 3685 3686 printf("\nSupported CR3 targets: %d\n", supported_targets); 3687 TEST_ASSERT(supported_targets <= 256); 3688 3689 try_cr3_target_count(-1u, supported_targets); 3690 try_cr3_target_count(0x80000000, supported_targets); 3691 try_cr3_target_count(0x7fffffff, supported_targets); 3692 for (i = 0; i <= supported_targets + 1; i++) 3693 try_cr3_target_count(i, supported_targets); 3694 vmcs_write(CR3_TARGET_COUNT, cr3_targets); 3695 3696 /* VMWRITE to nonexistent target fields should fail. */ 3697 for (i = supported_targets; i < 256; i++) 3698 TEST_ASSERT(vmcs_write(CR3_TARGET_0 + i*2, 0)); 3699 } 3700 3701 /* 3702 * Test a particular address setting in the VMCS 3703 */ 3704 static void test_vmcs_addr(const char *name, 3705 enum Encoding encoding, 3706 u64 align, 3707 bool ignored, 3708 bool skip_beyond_mapped_ram, 3709 u64 addr) 3710 { 3711 report_prefix_pushf("%s = %lx", name, addr); 3712 vmcs_write(encoding, addr); 3713 if (skip_beyond_mapped_ram && 3714 addr > fwcfg_get_u64(FW_CFG_RAM_SIZE) - align && 3715 addr < (1ul << cpuid_maxphyaddr())) 3716 printf("Skipping physical address beyond mapped RAM\n"); 3717 else if (ignored || (IS_ALIGNED(addr, align) && 3718 addr < (1ul << cpuid_maxphyaddr()))) 3719 test_vmx_valid_controls(); 3720 else 3721 test_vmx_invalid_controls(); 3722 report_prefix_pop(); 3723 } 3724 3725 /* 3726 * Test interesting values for a VMCS address 3727 */ 3728 static void test_vmcs_addr_values(const char *name, 3729 enum Encoding encoding, 3730 u64 align, 3731 bool ignored, 3732 bool skip_beyond_mapped_ram, 3733 u32 bit_start, u32 bit_end) 3734 { 3735 unsigned i; 3736 u64 orig_val = vmcs_read(encoding); 3737 3738 for (i = bit_start; i <= bit_end; i++) 3739 test_vmcs_addr(name, encoding, align, ignored, 3740 skip_beyond_mapped_ram, 1ul << i); 3741 3742 test_vmcs_addr(name, encoding, align, ignored, 3743 skip_beyond_mapped_ram, PAGE_SIZE - 1); 3744 test_vmcs_addr(name, encoding, align, ignored, 3745 skip_beyond_mapped_ram, PAGE_SIZE); 3746 test_vmcs_addr(name, encoding, align, ignored, 3747 skip_beyond_mapped_ram, 3748 (1ul << cpuid_maxphyaddr()) - PAGE_SIZE); 3749 test_vmcs_addr(name, encoding, align, ignored, 3750 skip_beyond_mapped_ram, -1ul); 3751 3752 vmcs_write(encoding, orig_val); 3753 } 3754 3755 /* 3756 * Test a physical address reference in the VMCS, when the corresponding 3757 * feature is enabled and when the corresponding feature is disabled. 3758 */ 3759 static void test_vmcs_addr_reference(u32 control_bit, enum Encoding field, 3760 const char *field_name, 3761 const char *control_name, u64 align, 3762 bool skip_beyond_mapped_ram, 3763 bool control_primary) 3764 { 3765 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 3766 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 3767 u64 page_addr; 3768 3769 if (control_primary) { 3770 if (!(ctrl_cpu_rev[0].clr & control_bit)) 3771 return; 3772 } else { 3773 if (!(ctrl_cpu_rev[1].clr & control_bit)) 3774 return; 3775 } 3776 3777 page_addr = vmcs_read(field); 3778 3779 report_prefix_pushf("%s enabled", control_name); 3780 if (control_primary) { 3781 vmcs_write(CPU_EXEC_CTRL0, primary | control_bit); 3782 } else { 3783 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3784 vmcs_write(CPU_EXEC_CTRL1, secondary | control_bit); 3785 } 3786 3787 test_vmcs_addr_values(field_name, field, align, false, 3788 skip_beyond_mapped_ram, 0, 63); 3789 report_prefix_pop(); 3790 3791 report_prefix_pushf("%s disabled", control_name); 3792 if (control_primary) { 3793 vmcs_write(CPU_EXEC_CTRL0, primary & ~control_bit); 3794 } else { 3795 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3796 vmcs_write(CPU_EXEC_CTRL1, secondary & ~control_bit); 3797 } 3798 3799 test_vmcs_addr_values(field_name, field, align, true, false, 0, 63); 3800 report_prefix_pop(); 3801 3802 vmcs_write(field, page_addr); 3803 vmcs_write(CPU_EXEC_CTRL0, primary); 3804 vmcs_write(CPU_EXEC_CTRL1, secondary); 3805 } 3806 3807 /* 3808 * If the "use I/O bitmaps" VM-execution control is 1, bits 11:0 of 3809 * each I/O-bitmap address must be 0. Neither address should set any 3810 * bits beyond the processor's physical-address width. 3811 * [Intel SDM] 3812 */ 3813 static void test_io_bitmaps(void) 3814 { 3815 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_A, 3816 "I/O bitmap A", "Use I/O bitmaps", 3817 PAGE_SIZE, false, true); 3818 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_B, 3819 "I/O bitmap B", "Use I/O bitmaps", 3820 PAGE_SIZE, false, true); 3821 } 3822 3823 /* 3824 * If the "use MSR bitmaps" VM-execution control is 1, bits 11:0 of 3825 * the MSR-bitmap address must be 0. The address should not set any 3826 * bits beyond the processor's physical-address width. 3827 * [Intel SDM] 3828 */ 3829 static void test_msr_bitmap(void) 3830 { 3831 test_vmcs_addr_reference(CPU_MSR_BITMAP, MSR_BITMAP, 3832 "MSR bitmap", "Use MSR bitmaps", 3833 PAGE_SIZE, false, true); 3834 } 3835 3836 /* 3837 * If the "use TPR shadow" VM-execution control is 1, the virtual-APIC 3838 * address must satisfy the following checks: 3839 * - Bits 11:0 of the address must be 0. 3840 * - The address should not set any bits beyond the processor's 3841 * physical-address width. 3842 * [Intel SDM] 3843 */ 3844 static void test_apic_virt_addr(void) 3845 { 3846 /* 3847 * Ensure the processor will never use the virtual-APIC page, since 3848 * we will point it to invalid RAM. Otherwise KVM is puzzled about 3849 * what we're trying to achieve and fails vmentry. 3850 */ 3851 u32 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 3852 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0 | CPU_CR8_LOAD | CPU_CR8_STORE); 3853 test_vmcs_addr_reference(CPU_TPR_SHADOW, APIC_VIRT_ADDR, 3854 "virtual-APIC address", "Use TPR shadow", 3855 PAGE_SIZE, false, true); 3856 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 3857 } 3858 3859 /* 3860 * If the "virtualize APIC-accesses" VM-execution control is 1, the 3861 * APIC-access address must satisfy the following checks: 3862 * - Bits 11:0 of the address must be 0. 3863 * - The address should not set any bits beyond the processor's 3864 * physical-address width. 3865 * [Intel SDM] 3866 */ 3867 static void test_apic_access_addr(void) 3868 { 3869 void *apic_access_page = alloc_page(); 3870 3871 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_page)); 3872 3873 test_vmcs_addr_reference(CPU_VIRT_APIC_ACCESSES, APIC_ACCS_ADDR, 3874 "APIC-access address", 3875 "virtualize APIC-accesses", PAGE_SIZE, 3876 true, false); 3877 } 3878 3879 static bool set_bit_pattern(u8 mask, u32 *secondary) 3880 { 3881 u8 i; 3882 bool flag = false; 3883 u32 test_bits[3] = { 3884 CPU_VIRT_X2APIC, 3885 CPU_APIC_REG_VIRT, 3886 CPU_VINTD 3887 }; 3888 3889 for (i = 0; i < ARRAY_SIZE(test_bits); i++) { 3890 if ((mask & (1u << i)) && 3891 (ctrl_cpu_rev[1].clr & test_bits[i])) { 3892 *secondary |= test_bits[i]; 3893 flag = true; 3894 } 3895 } 3896 3897 return (flag); 3898 } 3899 3900 /* 3901 * If the "use TPR shadow" VM-execution control is 0, the following 3902 * VM-execution controls must also be 0: 3903 * - virtualize x2APIC mode 3904 * - APIC-register virtualization 3905 * - virtual-interrupt delivery 3906 * [Intel SDM] 3907 * 3908 * 2. If the "virtualize x2APIC mode" VM-execution control is 1, the 3909 * "virtualize APIC accesses" VM-execution control must be 0. 3910 * [Intel SDM] 3911 */ 3912 static void test_apic_virtual_ctls(void) 3913 { 3914 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3915 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3916 u32 primary = saved_primary; 3917 u32 secondary = saved_secondary; 3918 bool ctrl = false; 3919 char str[10] = "disabled"; 3920 u8 i = 0, j; 3921 3922 /* 3923 * First test 3924 */ 3925 if (!((ctrl_cpu_rev[0].clr & (CPU_SECONDARY | CPU_TPR_SHADOW)) == 3926 (CPU_SECONDARY | CPU_TPR_SHADOW))) 3927 return; 3928 3929 primary |= CPU_SECONDARY; 3930 primary &= ~CPU_TPR_SHADOW; 3931 vmcs_write(CPU_EXEC_CTRL0, primary); 3932 3933 while (1) { 3934 for (j = 1; j < 8; j++) { 3935 secondary &= ~(CPU_VIRT_X2APIC | CPU_APIC_REG_VIRT | CPU_VINTD); 3936 if (primary & CPU_TPR_SHADOW) { 3937 ctrl = true; 3938 } else { 3939 if (! set_bit_pattern(j, &secondary)) 3940 ctrl = true; 3941 else 3942 ctrl = false; 3943 } 3944 3945 vmcs_write(CPU_EXEC_CTRL1, secondary); 3946 report_prefix_pushf("Use TPR shadow %s, virtualize x2APIC mode %s, APIC-register virtualization %s, virtual-interrupt delivery %s", 3947 str, (secondary & CPU_VIRT_X2APIC) ? "enabled" : "disabled", (secondary & CPU_APIC_REG_VIRT) ? "enabled" : "disabled", (secondary & CPU_VINTD) ? "enabled" : "disabled"); 3948 if (ctrl) 3949 test_vmx_valid_controls(); 3950 else 3951 test_vmx_invalid_controls(); 3952 report_prefix_pop(); 3953 } 3954 3955 if (i == 1) 3956 break; 3957 i++; 3958 3959 primary |= CPU_TPR_SHADOW; 3960 vmcs_write(CPU_EXEC_CTRL0, primary); 3961 strcpy(str, "enabled"); 3962 } 3963 3964 /* 3965 * Second test 3966 */ 3967 u32 apic_virt_ctls = (CPU_VIRT_X2APIC | CPU_VIRT_APIC_ACCESSES); 3968 3969 primary = saved_primary; 3970 secondary = saved_secondary; 3971 if (!((ctrl_cpu_rev[1].clr & apic_virt_ctls) == apic_virt_ctls)) 3972 return; 3973 3974 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3975 secondary &= ~CPU_VIRT_APIC_ACCESSES; 3976 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_X2APIC); 3977 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access disabled"); 3978 test_vmx_valid_controls(); 3979 report_prefix_pop(); 3980 3981 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_APIC_ACCESSES); 3982 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access enabled"); 3983 test_vmx_valid_controls(); 3984 report_prefix_pop(); 3985 3986 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_X2APIC); 3987 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access enabled"); 3988 test_vmx_invalid_controls(); 3989 report_prefix_pop(); 3990 3991 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_APIC_ACCESSES); 3992 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access disabled"); 3993 test_vmx_valid_controls(); 3994 report_prefix_pop(); 3995 3996 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3997 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3998 } 3999 4000 /* 4001 * If the "virtual-interrupt delivery" VM-execution control is 1, the 4002 * "external-interrupt exiting" VM-execution control must be 1. 4003 * [Intel SDM] 4004 */ 4005 static void test_virtual_intr_ctls(void) 4006 { 4007 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 4008 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 4009 u32 saved_pin = vmcs_read(PIN_CONTROLS); 4010 u32 primary = saved_primary; 4011 u32 secondary = saved_secondary; 4012 u32 pin = saved_pin; 4013 4014 if (!((ctrl_cpu_rev[1].clr & CPU_VINTD) && 4015 (ctrl_pin_rev.clr & PIN_EXTINT))) 4016 return; 4017 4018 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 4019 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VINTD); 4020 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 4021 report_prefix_pushf("Virtualize interrupt-delivery disabled; external-interrupt exiting disabled"); 4022 test_vmx_valid_controls(); 4023 report_prefix_pop(); 4024 4025 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VINTD); 4026 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 4027 test_vmx_invalid_controls(); 4028 report_prefix_pop(); 4029 4030 vmcs_write(PIN_CONTROLS, pin | PIN_EXTINT); 4031 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting enabled"); 4032 test_vmx_valid_controls(); 4033 report_prefix_pop(); 4034 4035 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 4036 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 4037 test_vmx_invalid_controls(); 4038 report_prefix_pop(); 4039 4040 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 4041 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 4042 vmcs_write(PIN_CONTROLS, saved_pin); 4043 } 4044 4045 static void test_pi_desc_addr(u64 addr, bool ctrl) 4046 { 4047 vmcs_write(POSTED_INTR_DESC_ADDR, addr); 4048 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-descriptor-address 0x%lx", addr); 4049 if (ctrl) 4050 test_vmx_valid_controls(); 4051 else 4052 test_vmx_invalid_controls(); 4053 report_prefix_pop(); 4054 } 4055 4056 /* 4057 * If the “process posted interrupts†VM-execution control is 1, the 4058 * following must be true: 4059 * 4060 * - The “virtual-interrupt delivery†VM-execution control is 1. 4061 * - The “acknowledge interrupt on exit†VM-exit control is 1. 4062 * - The posted-interrupt notification vector has a value in the 4063 * - range 0–255 (bits 15:8 are all 0). 4064 * - Bits 5:0 of the posted-interrupt descriptor address are all 0. 4065 * - The posted-interrupt descriptor address does not set any bits 4066 * beyond the processor's physical-address width. 4067 * [Intel SDM] 4068 */ 4069 static void test_posted_intr(void) 4070 { 4071 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 4072 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 4073 u32 saved_pin = vmcs_read(PIN_CONTROLS); 4074 u32 exit_ctl_saved = vmcs_read(EXI_CONTROLS); 4075 u32 primary = saved_primary; 4076 u32 secondary = saved_secondary; 4077 u32 pin = saved_pin; 4078 u32 exit_ctl = exit_ctl_saved; 4079 u16 vec; 4080 int i; 4081 4082 if (!((ctrl_pin_rev.clr & PIN_POST_INTR) && 4083 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 4084 (ctrl_exit_rev.clr & EXI_INTA))) 4085 return; 4086 4087 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 4088 4089 /* 4090 * Test virtual-interrupt-delivery and acknowledge-interrupt-on-exit 4091 */ 4092 pin |= PIN_POST_INTR; 4093 vmcs_write(PIN_CONTROLS, pin); 4094 secondary &= ~CPU_VINTD; 4095 vmcs_write(CPU_EXEC_CTRL1, secondary); 4096 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled"); 4097 test_vmx_invalid_controls(); 4098 report_prefix_pop(); 4099 4100 secondary |= CPU_VINTD; 4101 vmcs_write(CPU_EXEC_CTRL1, secondary); 4102 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled"); 4103 test_vmx_invalid_controls(); 4104 report_prefix_pop(); 4105 4106 exit_ctl &= ~EXI_INTA; 4107 vmcs_write(EXI_CONTROLS, exit_ctl); 4108 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit disabled"); 4109 test_vmx_invalid_controls(); 4110 report_prefix_pop(); 4111 4112 exit_ctl |= EXI_INTA; 4113 vmcs_write(EXI_CONTROLS, exit_ctl); 4114 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 4115 test_vmx_valid_controls(); 4116 report_prefix_pop(); 4117 4118 secondary &= ~CPU_VINTD; 4119 vmcs_write(CPU_EXEC_CTRL1, secondary); 4120 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled; acknowledge-interrupt-on-exit enabled"); 4121 test_vmx_invalid_controls(); 4122 report_prefix_pop(); 4123 4124 secondary |= CPU_VINTD; 4125 vmcs_write(CPU_EXEC_CTRL1, secondary); 4126 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 4127 test_vmx_valid_controls(); 4128 report_prefix_pop(); 4129 4130 /* 4131 * Test posted-interrupt notification vector 4132 */ 4133 for (i = 0; i < 8; i++) { 4134 vec = (1ul << i); 4135 vmcs_write(PINV, vec); 4136 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 4137 test_vmx_valid_controls(); 4138 report_prefix_pop(); 4139 } 4140 for (i = 8; i < 16; i++) { 4141 vec = (1ul << i); 4142 vmcs_write(PINV, vec); 4143 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 4144 test_vmx_invalid_controls(); 4145 report_prefix_pop(); 4146 } 4147 4148 vec &= ~(0xff << 8); 4149 vmcs_write(PINV, vec); 4150 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 4151 test_vmx_valid_controls(); 4152 report_prefix_pop(); 4153 4154 /* 4155 * Test posted-interrupt descriptor addresss 4156 */ 4157 for (i = 0; i < 6; i++) { 4158 test_pi_desc_addr(1ul << i, false); 4159 } 4160 4161 test_pi_desc_addr(0xf0, false); 4162 test_pi_desc_addr(0xff, false); 4163 test_pi_desc_addr(0x0f, false); 4164 test_pi_desc_addr(0x8000, true); 4165 test_pi_desc_addr(0x00, true); 4166 test_pi_desc_addr(0xc000, true); 4167 4168 test_vmcs_addr_values("process-posted interrupts", 4169 POSTED_INTR_DESC_ADDR, 64, 4170 false, false, 0, 63); 4171 4172 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 4173 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 4174 vmcs_write(PIN_CONTROLS, saved_pin); 4175 } 4176 4177 static void test_apic_ctls(void) 4178 { 4179 test_apic_virt_addr(); 4180 test_apic_access_addr(); 4181 test_apic_virtual_ctls(); 4182 test_virtual_intr_ctls(); 4183 test_posted_intr(); 4184 } 4185 4186 /* 4187 * If the “enable VPID†VM-execution control is 1, the value of the 4188 * of the VPID VM-execution control field must not be 0000H. 4189 * [Intel SDM] 4190 */ 4191 static void test_vpid(void) 4192 { 4193 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 4194 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 4195 u16 vpid = 0x0000; 4196 int i; 4197 4198 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4199 (ctrl_cpu_rev[1].clr & CPU_VPID))) { 4200 printf("Secondary controls and/or VPID not supported\n"); 4201 return; 4202 } 4203 4204 vmcs_write(CPU_EXEC_CTRL0, saved_primary | CPU_SECONDARY); 4205 vmcs_write(CPU_EXEC_CTRL1, saved_secondary & ~CPU_VPID); 4206 vmcs_write(VPID, vpid); 4207 report_prefix_pushf("VPID disabled; VPID value %x", vpid); 4208 test_vmx_valid_controls(); 4209 report_prefix_pop(); 4210 4211 vmcs_write(CPU_EXEC_CTRL1, saved_secondary | CPU_VPID); 4212 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 4213 test_vmx_invalid_controls(); 4214 report_prefix_pop(); 4215 4216 for (i = 0; i < 16; i++) { 4217 vpid = (short)1 << i;; 4218 vmcs_write(VPID, vpid); 4219 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 4220 test_vmx_valid_controls(); 4221 report_prefix_pop(); 4222 } 4223 4224 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 4225 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 4226 } 4227 4228 static void set_vtpr(unsigned vtpr) 4229 { 4230 *(u32 *)phys_to_virt(vmcs_read(APIC_VIRT_ADDR) + APIC_TASKPRI) = vtpr; 4231 } 4232 4233 static void try_tpr_threshold_and_vtpr(unsigned threshold, unsigned vtpr) 4234 { 4235 bool valid = true; 4236 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4237 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4238 4239 if ((primary & CPU_TPR_SHADOW) && 4240 (!(primary & CPU_SECONDARY) || 4241 !(secondary & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 4242 valid = (threshold & 0xf) <= ((vtpr >> 4) & 0xf); 4243 4244 set_vtpr(vtpr); 4245 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0x%x", 4246 threshold, (vtpr >> 4) & 0xf); 4247 if (valid) 4248 test_vmx_valid_controls(); 4249 else 4250 test_vmx_invalid_controls(); 4251 report_prefix_pop(); 4252 } 4253 4254 static void test_invalid_event_injection(void) 4255 { 4256 u32 ent_intr_info_save = vmcs_read(ENT_INTR_INFO); 4257 u32 ent_intr_error_save = vmcs_read(ENT_INTR_ERROR); 4258 u32 ent_inst_len_save = vmcs_read(ENT_INST_LEN); 4259 u32 primary_save = vmcs_read(CPU_EXEC_CTRL0); 4260 u32 secondary_save = vmcs_read(CPU_EXEC_CTRL1); 4261 u64 guest_cr0_save = vmcs_read(GUEST_CR0); 4262 u32 ent_intr_info_base = INTR_INFO_VALID_MASK; 4263 u32 ent_intr_info, ent_intr_err, ent_intr_len; 4264 u32 cnt; 4265 4266 /* Setup */ 4267 report_prefix_push("invalid event injection"); 4268 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4269 vmcs_write(ENT_INST_LEN, 0x00000001); 4270 4271 /* The field’s interruption type is not set to a reserved value. */ 4272 ent_intr_info = ent_intr_info_base | INTR_TYPE_RESERVED | DE_VECTOR; 4273 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4274 "RESERVED interruption type invalid [-]", 4275 ent_intr_info); 4276 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4277 test_vmx_invalid_controls(); 4278 report_prefix_pop(); 4279 4280 ent_intr_info = ent_intr_info_base | INTR_TYPE_EXT_INTR | 4281 DE_VECTOR; 4282 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4283 "RESERVED interruption type invalid [+]", 4284 ent_intr_info); 4285 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4286 test_vmx_valid_controls(); 4287 report_prefix_pop(); 4288 4289 /* If the interruption type is other event, the vector is 0. */ 4290 ent_intr_info = ent_intr_info_base | INTR_TYPE_OTHER_EVENT | DB_VECTOR; 4291 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4292 "(OTHER EVENT && vector != 0) invalid [-]", 4293 ent_intr_info); 4294 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4295 test_vmx_invalid_controls(); 4296 report_prefix_pop(); 4297 4298 /* If the interruption type is NMI, the vector is 2 (negative case). */ 4299 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | DE_VECTOR; 4300 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4301 "(NMI && vector != 2) invalid [-]", ent_intr_info); 4302 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4303 test_vmx_invalid_controls(); 4304 report_prefix_pop(); 4305 4306 /* If the interruption type is NMI, the vector is 2 (positive case). */ 4307 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | NMI_VECTOR; 4308 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4309 "(NMI && vector == 2) valid [+]", ent_intr_info); 4310 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4311 test_vmx_valid_controls(); 4312 report_prefix_pop(); 4313 4314 /* 4315 * If the interruption type 4316 * is HW exception, the vector is at most 31. 4317 */ 4318 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 0x20; 4319 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4320 "(HW exception && vector > 31) invalid [-]", 4321 ent_intr_info); 4322 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4323 test_vmx_invalid_controls(); 4324 report_prefix_pop(); 4325 4326 /* 4327 * deliver-error-code is 1 iff either 4328 * (a) the "unrestricted guest" VM-execution control is 0 4329 * (b) CR0.PE is set. 4330 */ 4331 4332 /* Assert that unrestricted guest is disabled or unsupported */ 4333 assert(!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 4334 !(secondary_save & CPU_URG)); 4335 4336 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4337 GP_VECTOR; 4338 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4339 "error code <-> (!URG || prot_mode) [-]", 4340 ent_intr_info); 4341 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4342 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4343 test_vmx_invalid_controls(); 4344 report_prefix_pop(); 4345 4346 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4347 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4348 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4349 "error code <-> (!URG || prot_mode) [+]", 4350 ent_intr_info); 4351 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4352 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4353 test_vmx_valid_controls(); 4354 report_prefix_pop(); 4355 4356 if (enable_unrestricted_guest()) 4357 goto skip_unrestricted_guest; 4358 4359 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4360 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4361 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4362 "error code <-> (!URG || prot_mode) [-]", 4363 ent_intr_info); 4364 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4365 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4366 test_vmx_invalid_controls(); 4367 report_prefix_pop(); 4368 4369 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4370 GP_VECTOR; 4371 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4372 "error code <-> (!URG || prot_mode) [-]", 4373 ent_intr_info); 4374 vmcs_write(GUEST_CR0, guest_cr0_save | X86_CR0_PE); 4375 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4376 test_vmx_invalid_controls(); 4377 report_prefix_pop(); 4378 4379 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4380 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4381 4382 skip_unrestricted_guest: 4383 vmcs_write(GUEST_CR0, guest_cr0_save); 4384 4385 /* deliver-error-code is 1 iff the interruption type is HW exception */ 4386 report_prefix_push("error code <-> HW exception"); 4387 for (cnt = 0; cnt < 8; cnt++) { 4388 u32 exception_type_mask = cnt << 8; 4389 u32 deliver_error_code_mask = 4390 exception_type_mask != INTR_TYPE_HARD_EXCEPTION ? 4391 INTR_INFO_DELIVER_CODE_MASK : 0; 4392 4393 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4394 exception_type_mask | GP_VECTOR; 4395 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4396 ent_intr_info); 4397 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4398 test_vmx_invalid_controls(); 4399 report_prefix_pop(); 4400 } 4401 report_prefix_pop(); 4402 4403 /* 4404 * deliver-error-code is 1 iff the the vector 4405 * indicates an exception that would normally deliver an error code 4406 */ 4407 report_prefix_push("error code <-> vector delivers error code"); 4408 for (cnt = 0; cnt < 32; cnt++) { 4409 bool has_error_code = false; 4410 u32 deliver_error_code_mask; 4411 4412 switch (cnt) { 4413 case DF_VECTOR: 4414 case TS_VECTOR: 4415 case NP_VECTOR: 4416 case SS_VECTOR: 4417 case GP_VECTOR: 4418 case PF_VECTOR: 4419 case AC_VECTOR: 4420 has_error_code = true; 4421 } 4422 4423 /* Negative case */ 4424 deliver_error_code_mask = has_error_code ? 4425 0 : 4426 INTR_INFO_DELIVER_CODE_MASK; 4427 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4428 INTR_TYPE_HARD_EXCEPTION | cnt; 4429 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4430 ent_intr_info); 4431 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4432 test_vmx_invalid_controls(); 4433 report_prefix_pop(); 4434 4435 /* Positive case */ 4436 deliver_error_code_mask = has_error_code ? 4437 INTR_INFO_DELIVER_CODE_MASK : 4438 0; 4439 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4440 INTR_TYPE_HARD_EXCEPTION | cnt; 4441 report_prefix_pushf("VM-entry intr info=0x%x [+]", 4442 ent_intr_info); 4443 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4444 test_vmx_valid_controls(); 4445 report_prefix_pop(); 4446 } 4447 report_prefix_pop(); 4448 4449 /* Reserved bits in the field (30:12) are 0. */ 4450 report_prefix_push("reserved bits clear"); 4451 for (cnt = 12; cnt <= 30; cnt++) { 4452 ent_intr_info = ent_intr_info_base | 4453 INTR_INFO_DELIVER_CODE_MASK | 4454 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR | 4455 (1U << cnt); 4456 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4457 ent_intr_info); 4458 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4459 test_vmx_invalid_controls(); 4460 report_prefix_pop(); 4461 } 4462 report_prefix_pop(); 4463 4464 /* 4465 * If deliver-error-code is 1 4466 * bits 31:16 of the VM-entry exception error-code field are 0. 4467 */ 4468 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4469 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4470 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4471 "VM-entry exception error code[31:16] clear", 4472 ent_intr_info); 4473 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4474 for (cnt = 16; cnt <= 31; cnt++) { 4475 ent_intr_err = 1U << cnt; 4476 report_prefix_pushf("VM-entry intr error=0x%x [-]", 4477 ent_intr_err); 4478 vmcs_write(ENT_INTR_ERROR, ent_intr_err); 4479 test_vmx_invalid_controls(); 4480 report_prefix_pop(); 4481 } 4482 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4483 report_prefix_pop(); 4484 4485 /* 4486 * If the interruption type is software interrupt, software exception, 4487 * or privileged software exception, the VM-entry instruction-length 4488 * field is in the range 0–15. 4489 */ 4490 4491 for (cnt = 0; cnt < 3; cnt++) { 4492 switch (cnt) { 4493 case 0: 4494 ent_intr_info = ent_intr_info_base | 4495 INTR_TYPE_SOFT_INTR; 4496 break; 4497 case 1: 4498 ent_intr_info = ent_intr_info_base | 4499 INTR_TYPE_SOFT_EXCEPTION; 4500 break; 4501 case 2: 4502 ent_intr_info = ent_intr_info_base | 4503 INTR_TYPE_PRIV_SW_EXCEPTION; 4504 break; 4505 } 4506 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4507 "VM-entry instruction-length check", 4508 ent_intr_info); 4509 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4510 4511 /* Instruction length set to -1 (0xFFFFFFFF) should fail */ 4512 ent_intr_len = -1; 4513 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4514 ent_intr_len); 4515 vmcs_write(ENT_INST_LEN, ent_intr_len); 4516 test_vmx_invalid_controls(); 4517 report_prefix_pop(); 4518 4519 /* Instruction length set to 16 should fail */ 4520 ent_intr_len = 0x00000010; 4521 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4522 ent_intr_len); 4523 vmcs_write(ENT_INST_LEN, 0x00000010); 4524 test_vmx_invalid_controls(); 4525 report_prefix_pop(); 4526 4527 report_prefix_pop(); 4528 } 4529 4530 /* Cleanup */ 4531 vmcs_write(ENT_INTR_INFO, ent_intr_info_save); 4532 vmcs_write(ENT_INTR_ERROR, ent_intr_error_save); 4533 vmcs_write(ENT_INST_LEN, ent_inst_len_save); 4534 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4535 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4536 vmcs_write(GUEST_CR0, guest_cr0_save); 4537 report_prefix_pop(); 4538 } 4539 4540 /* 4541 * Test interesting vTPR values for a given TPR threshold. 4542 */ 4543 static void test_vtpr_values(unsigned threshold) 4544 { 4545 try_tpr_threshold_and_vtpr(threshold, (threshold - 1) << 4); 4546 try_tpr_threshold_and_vtpr(threshold, threshold << 4); 4547 try_tpr_threshold_and_vtpr(threshold, (threshold + 1) << 4); 4548 } 4549 4550 static void try_tpr_threshold(unsigned threshold) 4551 { 4552 bool valid = true; 4553 4554 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4555 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4556 4557 if ((primary & CPU_TPR_SHADOW) && !((primary & CPU_SECONDARY) && 4558 (secondary & CPU_VINTD))) 4559 valid = !(threshold >> 4); 4560 4561 set_vtpr(-1); 4562 vmcs_write(TPR_THRESHOLD, threshold); 4563 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0xf", threshold); 4564 if (valid) 4565 test_vmx_valid_controls(); 4566 else 4567 test_vmx_invalid_controls(); 4568 report_prefix_pop(); 4569 4570 if (valid) 4571 test_vtpr_values(threshold); 4572 } 4573 4574 /* 4575 * Test interesting TPR threshold values. 4576 */ 4577 static void test_tpr_threshold_values(void) 4578 { 4579 unsigned i; 4580 4581 for (i = 0; i < 0x10; i++) 4582 try_tpr_threshold(i); 4583 for (i = 4; i < 32; i++) 4584 try_tpr_threshold(1u << i); 4585 try_tpr_threshold(-1u); 4586 try_tpr_threshold(0x7fffffff); 4587 } 4588 4589 /* 4590 * This test covers the following two VM entry checks: 4591 * 4592 * i) If the "use TPR shadow" VM-execution control is 1 and the 4593 * "virtual-interrupt delivery" VM-execution control is 0, bits 4594 * 31:4 of the TPR threshold VM-execution control field must 4595 be 0. 4596 * [Intel SDM] 4597 * 4598 * ii) If the "use TPR shadow" VM-execution control is 1, the 4599 * "virtual-interrupt delivery" VM-execution control is 0 4600 * and the "virtualize APIC accesses" VM-execution control 4601 * is 0, the value of bits 3:0 of the TPR threshold VM-execution 4602 * control field must not be greater than the value of bits 4603 * 7:4 of VTPR. 4604 * [Intel SDM] 4605 */ 4606 static void test_tpr_threshold(void) 4607 { 4608 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4609 u64 apic_virt_addr = vmcs_read(APIC_VIRT_ADDR); 4610 u64 threshold = vmcs_read(TPR_THRESHOLD); 4611 void *virtual_apic_page; 4612 4613 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) 4614 return; 4615 4616 virtual_apic_page = alloc_page(); 4617 memset(virtual_apic_page, 0xff, PAGE_SIZE); 4618 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 4619 4620 vmcs_write(CPU_EXEC_CTRL0, primary & ~(CPU_TPR_SHADOW | CPU_SECONDARY)); 4621 report_prefix_pushf("Use TPR shadow disabled, secondary controls disabled"); 4622 test_tpr_threshold_values(); 4623 report_prefix_pop(); 4624 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_TPR_SHADOW); 4625 report_prefix_pushf("Use TPR shadow enabled, secondary controls disabled"); 4626 test_tpr_threshold_values(); 4627 report_prefix_pop(); 4628 4629 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4630 (ctrl_cpu_rev[1].clr & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 4631 goto out; 4632 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4633 4634 if (ctrl_cpu_rev[1].clr & CPU_VINTD) { 4635 vmcs_write(CPU_EXEC_CTRL1, CPU_VINTD); 4636 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4637 test_tpr_threshold_values(); 4638 report_prefix_pop(); 4639 4640 vmcs_write(CPU_EXEC_CTRL0, 4641 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4642 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4643 test_tpr_threshold_values(); 4644 report_prefix_pop(); 4645 } 4646 4647 if (ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES) { 4648 vmcs_write(CPU_EXEC_CTRL0, 4649 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4650 vmcs_write(CPU_EXEC_CTRL1, CPU_VIRT_APIC_ACCESSES); 4651 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4652 test_tpr_threshold_values(); 4653 report_prefix_pop(); 4654 4655 vmcs_write(CPU_EXEC_CTRL0, 4656 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4657 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4658 test_tpr_threshold_values(); 4659 report_prefix_pop(); 4660 } 4661 4662 if ((ctrl_cpu_rev[1].clr & 4663 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) == 4664 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) { 4665 vmcs_write(CPU_EXEC_CTRL0, 4666 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4667 vmcs_write(CPU_EXEC_CTRL1, 4668 CPU_VINTD | CPU_VIRT_APIC_ACCESSES); 4669 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4670 test_tpr_threshold_values(); 4671 report_prefix_pop(); 4672 4673 vmcs_write(CPU_EXEC_CTRL0, 4674 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4675 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4676 test_tpr_threshold_values(); 4677 report_prefix_pop(); 4678 } 4679 4680 vmcs_write(CPU_EXEC_CTRL1, secondary); 4681 out: 4682 vmcs_write(TPR_THRESHOLD, threshold); 4683 vmcs_write(APIC_VIRT_ADDR, apic_virt_addr); 4684 vmcs_write(CPU_EXEC_CTRL0, primary); 4685 } 4686 4687 /* 4688 * This test verifies the following two vmentry checks: 4689 * 4690 * If the "NMI exiting" VM-execution control is 0, "Virtual NMIs" 4691 * VM-execution control must be 0. 4692 * [Intel SDM] 4693 * 4694 * If the “virtual NMIs” VM-execution control is 0, the “NMI-window 4695 * exiting” VM-execution control must be 0. 4696 * [Intel SDM] 4697 */ 4698 static void test_nmi_ctrls(void) 4699 { 4700 u32 pin_ctrls, cpu_ctrls0, test_pin_ctrls, test_cpu_ctrls0; 4701 4702 if ((ctrl_pin_rev.clr & (PIN_NMI | PIN_VIRT_NMI)) != 4703 (PIN_NMI | PIN_VIRT_NMI)) { 4704 printf("NMI exiting and Virtual NMIs are not supported !\n"); 4705 return; 4706 } 4707 4708 /* Save the controls so that we can restore them after our tests */ 4709 pin_ctrls = vmcs_read(PIN_CONTROLS); 4710 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 4711 4712 test_pin_ctrls = pin_ctrls & ~(PIN_NMI | PIN_VIRT_NMI); 4713 test_cpu_ctrls0 = cpu_ctrls0 & ~CPU_NMI_WINDOW; 4714 4715 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4716 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs disabled"); 4717 test_vmx_valid_controls(); 4718 report_prefix_pop(); 4719 4720 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_VIRT_NMI); 4721 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs enabled"); 4722 test_vmx_invalid_controls(); 4723 report_prefix_pop(); 4724 4725 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4726 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs enabled"); 4727 test_vmx_valid_controls(); 4728 report_prefix_pop(); 4729 4730 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_NMI); 4731 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs disabled"); 4732 test_vmx_valid_controls(); 4733 report_prefix_pop(); 4734 4735 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 4736 report_info("NMI-window exiting is not supported, skipping..."); 4737 goto done; 4738 } 4739 4740 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4741 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4742 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting enabled"); 4743 test_vmx_invalid_controls(); 4744 report_prefix_pop(); 4745 4746 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4747 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4748 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting disabled"); 4749 test_vmx_valid_controls(); 4750 report_prefix_pop(); 4751 4752 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4753 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4754 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting enabled"); 4755 test_vmx_valid_controls(); 4756 report_prefix_pop(); 4757 4758 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4759 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4760 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting disabled"); 4761 test_vmx_valid_controls(); 4762 report_prefix_pop(); 4763 4764 /* Restore the controls to their original values */ 4765 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 4766 done: 4767 vmcs_write(PIN_CONTROLS, pin_ctrls); 4768 } 4769 4770 static void test_eptp_ad_bit(u64 eptp, bool ctrl) 4771 { 4772 vmcs_write(EPTP, eptp); 4773 report_prefix_pushf("Enable-EPT enabled; EPT accessed and dirty flag %s", 4774 (eptp & EPTP_AD_FLAG) ? "1": "0"); 4775 if (ctrl) 4776 test_vmx_valid_controls(); 4777 else 4778 test_vmx_invalid_controls(); 4779 report_prefix_pop(); 4780 4781 } 4782 4783 /* 4784 * 1. If the "enable EPT" VM-execution control is 1, the "EPTP VM-execution" 4785 * control field must satisfy the following checks: 4786 * 4787 * - The EPT memory type (bits 2:0) must be a value supported by the 4788 * processor as indicated in the IA32_VMX_EPT_VPID_CAP MSR. 4789 * - Bits 5:3 (1 less than the EPT page-walk length) must indicate a 4790 * supported EPT page-walk length. 4791 * - Bit 6 (enable bit for accessed and dirty flags for EPT) must be 4792 * 0 if bit 21 of the IA32_VMX_EPT_VPID_CAP MSR is read as 0, 4793 * indicating that the processor does not support accessed and dirty 4794 * dirty flags for EPT. 4795 * - Reserved bits 11:7 and 63:N (where N is the processor's 4796 * physical-address width) must all be 0. 4797 * 4798 * 2. If the "unrestricted guest" VM-execution control is 1, the 4799 * "enable EPT" VM-execution control must also be 1. 4800 */ 4801 static void test_ept_eptp(void) 4802 { 4803 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4804 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4805 u64 eptp_saved = vmcs_read(EPTP); 4806 u32 primary = primary_saved; 4807 u32 secondary = secondary_saved; 4808 u64 msr, eptp = eptp_saved; 4809 bool un_cache = false; 4810 bool wr_bk = false; 4811 bool ctrl; 4812 u32 i, maxphysaddr; 4813 u64 j, resv_bits_mask = 0; 4814 4815 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4816 (ctrl_cpu_rev[1].clr & CPU_EPT))) { 4817 printf("\"CPU secondary\" and/or \"enable EPT\" execution controls are not supported !\n"); 4818 return; 4819 } 4820 4821 /* 4822 * Memory type (bits 2:0) 4823 */ 4824 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 4825 if (msr & EPT_CAP_UC) 4826 un_cache = true; 4827 if (msr & EPT_CAP_WB) 4828 wr_bk = true; 4829 4830 /* Support for 4-level EPT is mandatory. */ 4831 report(msr & EPT_CAP_PWL4, "4-level EPT support check"); 4832 4833 primary |= CPU_SECONDARY; 4834 vmcs_write(CPU_EXEC_CTRL0, primary); 4835 secondary |= CPU_EPT; 4836 vmcs_write(CPU_EXEC_CTRL1, secondary); 4837 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4838 (3ul << EPTP_PG_WALK_LEN_SHIFT); 4839 vmcs_write(EPTP, eptp); 4840 4841 for (i = 0; i < 8; i++) { 4842 if (i == 0) { 4843 if (un_cache) { 4844 report_info("EPT paging structure memory-type is Un-cacheable\n"); 4845 ctrl = true; 4846 } else { 4847 ctrl = false; 4848 } 4849 } else if (i == 6) { 4850 if (wr_bk) { 4851 report_info("EPT paging structure memory-type is Write-back\n"); 4852 ctrl = true; 4853 } else { 4854 ctrl = false; 4855 } 4856 } else { 4857 ctrl = false; 4858 } 4859 4860 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | i; 4861 vmcs_write(EPTP, eptp); 4862 report_prefix_pushf("Enable-EPT enabled; EPT memory type %lu", 4863 eptp & EPT_MEM_TYPE_MASK); 4864 if (ctrl) 4865 test_vmx_valid_controls(); 4866 else 4867 test_vmx_invalid_controls(); 4868 report_prefix_pop(); 4869 } 4870 4871 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | 6ul; 4872 4873 /* 4874 * Page walk length (bits 5:3). Note, the value in VMCS.EPTP "is 1 4875 * less than the EPT page-walk length". 4876 */ 4877 for (i = 0; i < 8; i++) { 4878 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4879 (i << EPTP_PG_WALK_LEN_SHIFT); 4880 if (i == 3 || (i == 4 && (msr & EPT_CAP_PWL5))) 4881 ctrl = true; 4882 else 4883 ctrl = false; 4884 4885 vmcs_write(EPTP, eptp); 4886 report_prefix_pushf("Enable-EPT enabled; EPT page walk length %lu", 4887 eptp & EPTP_PG_WALK_LEN_MASK); 4888 if (ctrl) 4889 test_vmx_valid_controls(); 4890 else 4891 test_vmx_invalid_controls(); 4892 report_prefix_pop(); 4893 } 4894 4895 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4896 3ul << EPTP_PG_WALK_LEN_SHIFT; 4897 4898 /* 4899 * Accessed and dirty flag (bit 6) 4900 */ 4901 if (msr & EPT_CAP_AD_FLAG) { 4902 report_info("Processor supports accessed and dirty flag"); 4903 eptp &= ~EPTP_AD_FLAG; 4904 test_eptp_ad_bit(eptp, true); 4905 4906 eptp |= EPTP_AD_FLAG; 4907 test_eptp_ad_bit(eptp, true); 4908 } else { 4909 report_info("Processor does not supports accessed and dirty flag"); 4910 eptp &= ~EPTP_AD_FLAG; 4911 test_eptp_ad_bit(eptp, true); 4912 4913 eptp |= EPTP_AD_FLAG; 4914 test_eptp_ad_bit(eptp, false); 4915 } 4916 4917 /* 4918 * Reserved bits [11:7] and [63:N] 4919 */ 4920 for (i = 0; i < 32; i++) { 4921 eptp = (eptp & 4922 ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)) | 4923 (i << EPTP_RESERV_BITS_SHIFT); 4924 vmcs_write(EPTP, eptp); 4925 report_prefix_pushf("Enable-EPT enabled; reserved bits [11:7] %lu", 4926 (eptp >> EPTP_RESERV_BITS_SHIFT) & 4927 EPTP_RESERV_BITS_MASK); 4928 if (i == 0) 4929 test_vmx_valid_controls(); 4930 else 4931 test_vmx_invalid_controls(); 4932 report_prefix_pop(); 4933 } 4934 4935 eptp = (eptp & ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)); 4936 4937 maxphysaddr = cpuid_maxphyaddr(); 4938 for (i = 0; i < (63 - maxphysaddr + 1); i++) { 4939 resv_bits_mask |= 1ul << i; 4940 } 4941 4942 for (j = maxphysaddr - 1; j <= 63; j++) { 4943 eptp = (eptp & ~(resv_bits_mask << maxphysaddr)) | 4944 (j < maxphysaddr ? 0 : 1ul << j); 4945 vmcs_write(EPTP, eptp); 4946 report_prefix_pushf("Enable-EPT enabled; reserved bits [63:N] %lu", 4947 (eptp >> maxphysaddr) & resv_bits_mask); 4948 if (j < maxphysaddr) 4949 test_vmx_valid_controls(); 4950 else 4951 test_vmx_invalid_controls(); 4952 report_prefix_pop(); 4953 } 4954 4955 secondary &= ~(CPU_EPT | CPU_URG); 4956 vmcs_write(CPU_EXEC_CTRL1, secondary); 4957 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest disabled"); 4958 test_vmx_valid_controls(); 4959 report_prefix_pop(); 4960 4961 if (!(ctrl_cpu_rev[1].clr & CPU_URG)) 4962 goto skip_unrestricted_guest; 4963 4964 secondary |= CPU_URG; 4965 vmcs_write(CPU_EXEC_CTRL1, secondary); 4966 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest enabled"); 4967 test_vmx_invalid_controls(); 4968 report_prefix_pop(); 4969 4970 secondary |= CPU_EPT; 4971 setup_dummy_ept(); 4972 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest enabled"); 4973 test_vmx_valid_controls(); 4974 report_prefix_pop(); 4975 4976 skip_unrestricted_guest: 4977 secondary &= ~CPU_URG; 4978 vmcs_write(CPU_EXEC_CTRL1, secondary); 4979 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest disabled"); 4980 test_vmx_valid_controls(); 4981 report_prefix_pop(); 4982 4983 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4984 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4985 vmcs_write(EPTP, eptp_saved); 4986 } 4987 4988 /* 4989 * If the 'enable PML' VM-execution control is 1, the 'enable EPT' 4990 * VM-execution control must also be 1. In addition, the PML address 4991 * must satisfy the following checks: 4992 * 4993 * * Bits 11:0 of the address must be 0. 4994 * * The address should not set any bits beyond the processor's 4995 * physical-address width. 4996 * 4997 * [Intel SDM] 4998 */ 4999 static void test_pml(void) 5000 { 5001 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 5002 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 5003 u32 primary = primary_saved; 5004 u32 secondary = secondary_saved; 5005 5006 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 5007 (ctrl_cpu_rev[1].clr & CPU_EPT) && (ctrl_cpu_rev[1].clr & CPU_PML))) { 5008 printf("\"Secondary execution\" control or \"enable EPT\" control or \"enable PML\" control is not supported !\n"); 5009 return; 5010 } 5011 5012 primary |= CPU_SECONDARY; 5013 vmcs_write(CPU_EXEC_CTRL0, primary); 5014 secondary &= ~(CPU_PML | CPU_EPT); 5015 vmcs_write(CPU_EXEC_CTRL1, secondary); 5016 report_prefix_pushf("enable-PML disabled, enable-EPT disabled"); 5017 test_vmx_valid_controls(); 5018 report_prefix_pop(); 5019 5020 secondary |= CPU_PML; 5021 vmcs_write(CPU_EXEC_CTRL1, secondary); 5022 report_prefix_pushf("enable-PML enabled, enable-EPT disabled"); 5023 test_vmx_invalid_controls(); 5024 report_prefix_pop(); 5025 5026 secondary |= CPU_EPT; 5027 setup_dummy_ept(); 5028 report_prefix_pushf("enable-PML enabled, enable-EPT enabled"); 5029 test_vmx_valid_controls(); 5030 report_prefix_pop(); 5031 5032 secondary &= ~CPU_PML; 5033 vmcs_write(CPU_EXEC_CTRL1, secondary); 5034 report_prefix_pushf("enable-PML disabled, enable EPT enabled"); 5035 test_vmx_valid_controls(); 5036 report_prefix_pop(); 5037 5038 test_vmcs_addr_reference(CPU_PML, PMLADDR, "PML address", "PML", 5039 PAGE_SIZE, false, false); 5040 5041 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 5042 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 5043 } 5044 5045 /* 5046 * If the "activate VMX-preemption timer" VM-execution control is 0, the 5047 * the "save VMX-preemption timer value" VM-exit control must also be 0. 5048 * 5049 * [Intel SDM] 5050 */ 5051 static void test_vmx_preemption_timer(void) 5052 { 5053 u32 saved_pin = vmcs_read(PIN_CONTROLS); 5054 u32 saved_exit = vmcs_read(EXI_CONTROLS); 5055 u32 pin = saved_pin; 5056 u32 exit = saved_exit; 5057 5058 if (!((ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) || 5059 (ctrl_pin_rev.clr & PIN_PREEMPT))) { 5060 printf("\"Save-VMX-preemption-timer\" control and/or \"Enable-VMX-preemption-timer\" control is not supported\n"); 5061 return; 5062 } 5063 5064 pin |= PIN_PREEMPT; 5065 vmcs_write(PIN_CONTROLS, pin); 5066 exit &= ~EXI_SAVE_PREEMPT; 5067 vmcs_write(EXI_CONTROLS, exit); 5068 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer disabled"); 5069 test_vmx_valid_controls(); 5070 report_prefix_pop(); 5071 5072 exit |= EXI_SAVE_PREEMPT; 5073 vmcs_write(EXI_CONTROLS, exit); 5074 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer enabled"); 5075 test_vmx_valid_controls(); 5076 report_prefix_pop(); 5077 5078 pin &= ~PIN_PREEMPT; 5079 vmcs_write(PIN_CONTROLS, pin); 5080 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer enabled"); 5081 test_vmx_invalid_controls(); 5082 report_prefix_pop(); 5083 5084 exit &= ~EXI_SAVE_PREEMPT; 5085 vmcs_write(EXI_CONTROLS, exit); 5086 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer disabled"); 5087 test_vmx_valid_controls(); 5088 report_prefix_pop(); 5089 5090 vmcs_write(PIN_CONTROLS, saved_pin); 5091 vmcs_write(EXI_CONTROLS, saved_exit); 5092 } 5093 5094 extern unsigned char test_mtf1; 5095 extern unsigned char test_mtf2; 5096 extern unsigned char test_mtf3; 5097 extern unsigned char test_mtf4; 5098 5099 static void test_mtf_guest(void) 5100 { 5101 asm ("vmcall;\n\t" 5102 "out %al, $0x80;\n\t" 5103 "test_mtf1:\n\t" 5104 "vmcall;\n\t" 5105 "out %al, $0x80;\n\t" 5106 "test_mtf2:\n\t" 5107 /* 5108 * Prepare for the 'MOV CR3' test. Attempt to induce a 5109 * general-protection fault by moving a non-canonical address into 5110 * CR3. The 'MOV CR3' instruction does not take an imm64 operand, 5111 * so we must MOV the desired value into a register first. 5112 * 5113 * MOV RAX is done before the VMCALL such that MTF is only enabled 5114 * for the instruction under test. 5115 */ 5116 "mov $0x8000000000000000, %rax;\n\t" 5117 "vmcall;\n\t" 5118 "mov %rax, %cr3;\n\t" 5119 "test_mtf3:\n\t" 5120 "vmcall;\n\t" 5121 /* 5122 * ICEBP/INT1 instruction. Though the instruction is now 5123 * documented, don't rely on assemblers enumerating the 5124 * instruction. Resort to hand assembly. 5125 */ 5126 ".byte 0xf1;\n\t" 5127 "vmcall;\n\t" 5128 "test_mtf4:\n\t" 5129 "mov $0, %eax;\n\t"); 5130 } 5131 5132 static void test_mtf_gp_handler(struct ex_regs *regs) 5133 { 5134 regs->rip = (unsigned long) &test_mtf3; 5135 } 5136 5137 static void test_mtf_db_handler(struct ex_regs *regs) 5138 { 5139 } 5140 5141 static void enable_mtf(void) 5142 { 5143 u32 ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 5144 5145 vmcs_write(CPU_EXEC_CTRL0, ctrl0 | CPU_MTF); 5146 } 5147 5148 static void disable_mtf(void) 5149 { 5150 u32 ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 5151 5152 vmcs_write(CPU_EXEC_CTRL0, ctrl0 & ~CPU_MTF); 5153 } 5154 5155 static void enable_tf(void) 5156 { 5157 unsigned long rflags = vmcs_read(GUEST_RFLAGS); 5158 5159 vmcs_write(GUEST_RFLAGS, rflags | X86_EFLAGS_TF); 5160 } 5161 5162 static void disable_tf(void) 5163 { 5164 unsigned long rflags = vmcs_read(GUEST_RFLAGS); 5165 5166 vmcs_write(GUEST_RFLAGS, rflags & ~X86_EFLAGS_TF); 5167 } 5168 5169 static void report_mtf(const char *insn_name, unsigned long exp_rip) 5170 { 5171 unsigned long rip = vmcs_read(GUEST_RIP); 5172 5173 assert_exit_reason(VMX_MTF); 5174 report(rip == exp_rip, "MTF VM-exit after %s. RIP: 0x%lx (expected 0x%lx)", 5175 insn_name, rip, exp_rip); 5176 } 5177 5178 static void vmx_mtf_test(void) 5179 { 5180 unsigned long pending_dbg; 5181 handler old_gp, old_db; 5182 5183 if (!(ctrl_cpu_rev[0].clr & CPU_MTF)) { 5184 printf("CPU does not support the 'monitor trap flag' processor-based VM-execution control.\n"); 5185 return; 5186 } 5187 5188 test_set_guest(test_mtf_guest); 5189 5190 /* Expect an MTF VM-exit after OUT instruction */ 5191 enter_guest(); 5192 skip_exit_vmcall(); 5193 5194 enable_mtf(); 5195 enter_guest(); 5196 report_mtf("OUT", (unsigned long) &test_mtf1); 5197 disable_mtf(); 5198 5199 /* 5200 * Concurrent #DB trap and MTF on instruction boundary. Expect MTF 5201 * VM-exit with populated 'pending debug exceptions' VMCS field. 5202 */ 5203 enter_guest(); 5204 skip_exit_vmcall(); 5205 5206 enable_mtf(); 5207 enable_tf(); 5208 5209 enter_guest(); 5210 report_mtf("OUT", (unsigned long) &test_mtf2); 5211 pending_dbg = vmcs_read(GUEST_PENDING_DEBUG); 5212 report(pending_dbg & DR_STEP, 5213 "'pending debug exceptions' field after MTF VM-exit: 0x%lx (expected 0x%lx)", 5214 pending_dbg, (unsigned long) DR_STEP); 5215 5216 disable_mtf(); 5217 disable_tf(); 5218 vmcs_write(GUEST_PENDING_DEBUG, 0); 5219 5220 /* 5221 * #GP exception takes priority over MTF. Expect MTF VM-exit with RIP 5222 * advanced to first instruction of #GP handler. 5223 */ 5224 enter_guest(); 5225 skip_exit_vmcall(); 5226 5227 old_gp = handle_exception(GP_VECTOR, test_mtf_gp_handler); 5228 5229 enable_mtf(); 5230 enter_guest(); 5231 report_mtf("MOV CR3", (unsigned long) get_idt_addr(&boot_idt[GP_VECTOR])); 5232 disable_mtf(); 5233 5234 /* 5235 * Concurrent MTF and privileged software exception (i.e. ICEBP/INT1). 5236 * MTF should follow the delivery of #DB trap, though the SDM doesn't 5237 * provide clear indication of the relative priority. 5238 */ 5239 enter_guest(); 5240 skip_exit_vmcall(); 5241 5242 handle_exception(GP_VECTOR, old_gp); 5243 old_db = handle_exception(DB_VECTOR, test_mtf_db_handler); 5244 5245 enable_mtf(); 5246 enter_guest(); 5247 report_mtf("INT1", (unsigned long) get_idt_addr(&boot_idt[DB_VECTOR])); 5248 disable_mtf(); 5249 5250 enter_guest(); 5251 skip_exit_vmcall(); 5252 handle_exception(DB_VECTOR, old_db); 5253 vmcs_write(ENT_INTR_INFO, INTR_INFO_VALID_MASK | INTR_TYPE_OTHER_EVENT); 5254 enter_guest(); 5255 report_mtf("injected MTF", (unsigned long) &test_mtf4); 5256 enter_guest(); 5257 } 5258 5259 /* 5260 * Tests for VM-execution control fields 5261 */ 5262 static void test_vm_execution_ctls(void) 5263 { 5264 test_pin_based_ctls(); 5265 test_primary_processor_based_ctls(); 5266 test_secondary_processor_based_ctls(); 5267 test_cr3_targets(); 5268 test_io_bitmaps(); 5269 test_msr_bitmap(); 5270 test_apic_ctls(); 5271 test_tpr_threshold(); 5272 test_nmi_ctrls(); 5273 test_pml(); 5274 test_vpid(); 5275 test_ept_eptp(); 5276 test_vmx_preemption_timer(); 5277 } 5278 5279 /* 5280 * The following checks are performed for the VM-entry MSR-load address if 5281 * the VM-entry MSR-load count field is non-zero: 5282 * 5283 * - The lower 4 bits of the VM-entry MSR-load address must be 0. 5284 * The address should not set any bits beyond the processor’s 5285 * physical-address width. 5286 * 5287 * - The address of the last byte in the VM-entry MSR-load area 5288 * should not set any bits beyond the processor’s physical-address 5289 * width. The address of this last byte is VM-entry MSR-load address 5290 * + (MSR count * 16) - 1. (The arithmetic used for the computation 5291 * uses more bits than the processor’s physical-address width.) 5292 * 5293 * 5294 * [Intel SDM] 5295 */ 5296 static void test_entry_msr_load(void) 5297 { 5298 entry_msr_load = alloc_page(); 5299 u64 tmp; 5300 u32 entry_msr_ld_cnt = 1; 5301 int i; 5302 u32 addr_len = 64; 5303 5304 vmcs_write(ENT_MSR_LD_CNT, entry_msr_ld_cnt); 5305 5306 /* Check first 4 bits of VM-entry MSR-load address */ 5307 for (i = 0; i < 4; i++) { 5308 tmp = (u64)entry_msr_load | 1ull << i; 5309 vmcs_write(ENTER_MSR_LD_ADDR, tmp); 5310 report_prefix_pushf("VM-entry MSR-load addr [4:0] %lx", 5311 tmp & 0xf); 5312 test_vmx_invalid_controls(); 5313 report_prefix_pop(); 5314 } 5315 5316 if (basic.val & (1ul << 48)) 5317 addr_len = 32; 5318 5319 test_vmcs_addr_values("VM-entry-MSR-load address", 5320 ENTER_MSR_LD_ADDR, 16, false, false, 5321 4, addr_len - 1); 5322 5323 /* 5324 * Check last byte of VM-entry MSR-load address 5325 */ 5326 entry_msr_load = (struct vmx_msr_entry *)((u64)entry_msr_load & ~0xf); 5327 5328 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 5329 i < 64; i++) { 5330 tmp = ((u64)entry_msr_load + entry_msr_ld_cnt * 16 - 1) | 5331 1ul << i; 5332 vmcs_write(ENTER_MSR_LD_ADDR, 5333 tmp - (entry_msr_ld_cnt * 16 - 1)); 5334 test_vmx_invalid_controls(); 5335 } 5336 5337 vmcs_write(ENT_MSR_LD_CNT, 2); 5338 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 5339 test_vmx_invalid_controls(); 5340 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 5341 test_vmx_valid_controls(); 5342 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 5343 test_vmx_valid_controls(); 5344 } 5345 5346 static struct vmx_state_area_test_data { 5347 u32 msr; 5348 u64 exp; 5349 bool enabled; 5350 } vmx_state_area_test_data; 5351 5352 static void guest_state_test_main(void) 5353 { 5354 u64 obs; 5355 struct vmx_state_area_test_data *data = &vmx_state_area_test_data; 5356 5357 while (1) { 5358 if (vmx_get_test_stage() == 2) 5359 break; 5360 5361 if (data->enabled) { 5362 obs = rdmsr(data->msr); 5363 report(data->exp == obs, 5364 "Guest state is 0x%lx (expected 0x%lx)", 5365 obs, data->exp); 5366 } 5367 5368 vmcall(); 5369 } 5370 5371 asm volatile("fnop"); 5372 } 5373 5374 static void test_guest_state(const char *test, bool xfail, u64 field, 5375 const char * field_name) 5376 { 5377 struct vmentry_result result; 5378 u8 abort_flags; 5379 5380 abort_flags = ABORT_ON_EARLY_VMENTRY_FAIL; 5381 if (!xfail) 5382 abort_flags = ABORT_ON_INVALID_GUEST_STATE; 5383 5384 __enter_guest(abort_flags, &result); 5385 5386 report(result.exit_reason.failed_vmentry == xfail && 5387 ((xfail && result.exit_reason.basic == VMX_FAIL_STATE) || 5388 (!xfail && result.exit_reason.basic == VMX_VMCALL)) && 5389 (!xfail || vmcs_read(EXI_QUALIFICATION) == ENTRY_FAIL_DEFAULT), 5390 "%s, %s %lx", test, field_name, field); 5391 5392 if (!result.exit_reason.failed_vmentry) 5393 skip_exit_insn(); 5394 } 5395 5396 /* 5397 * Tests for VM-entry control fields 5398 */ 5399 static void test_vm_entry_ctls(void) 5400 { 5401 test_invalid_event_injection(); 5402 test_entry_msr_load(); 5403 } 5404 5405 /* 5406 * The following checks are performed for the VM-exit MSR-store address if 5407 * the VM-exit MSR-store count field is non-zero: 5408 * 5409 * - The lower 4 bits of the VM-exit MSR-store address must be 0. 5410 * The address should not set any bits beyond the processor’s 5411 * physical-address width. 5412 * 5413 * - The address of the last byte in the VM-exit MSR-store area 5414 * should not set any bits beyond the processor’s physical-address 5415 * width. The address of this last byte is VM-exit MSR-store address 5416 * + (MSR count * 16) - 1. (The arithmetic used for the computation 5417 * uses more bits than the processor’s physical-address width.) 5418 * 5419 * If IA32_VMX_BASIC[48] is read as 1, neither address should set any bits 5420 * in the range 63:32. 5421 * 5422 * [Intel SDM] 5423 */ 5424 static void test_exit_msr_store(void) 5425 { 5426 exit_msr_store = alloc_page(); 5427 u64 tmp; 5428 u32 exit_msr_st_cnt = 1; 5429 int i; 5430 u32 addr_len = 64; 5431 5432 vmcs_write(EXI_MSR_ST_CNT, exit_msr_st_cnt); 5433 5434 /* Check first 4 bits of VM-exit MSR-store address */ 5435 for (i = 0; i < 4; i++) { 5436 tmp = (u64)exit_msr_store | 1ull << i; 5437 vmcs_write(EXIT_MSR_ST_ADDR, tmp); 5438 report_prefix_pushf("VM-exit MSR-store addr [4:0] %lx", 5439 tmp & 0xf); 5440 test_vmx_invalid_controls(); 5441 report_prefix_pop(); 5442 } 5443 5444 if (basic.val & (1ul << 48)) 5445 addr_len = 32; 5446 5447 test_vmcs_addr_values("VM-exit-MSR-store address", 5448 EXIT_MSR_ST_ADDR, 16, false, false, 5449 4, addr_len - 1); 5450 5451 /* 5452 * Check last byte of VM-exit MSR-store address 5453 */ 5454 exit_msr_store = (struct vmx_msr_entry *)((u64)exit_msr_store & ~0xf); 5455 5456 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 5457 i < 64; i++) { 5458 tmp = ((u64)exit_msr_store + exit_msr_st_cnt * 16 - 1) | 5459 1ul << i; 5460 vmcs_write(EXIT_MSR_ST_ADDR, 5461 tmp - (exit_msr_st_cnt * 16 - 1)); 5462 test_vmx_invalid_controls(); 5463 } 5464 5465 vmcs_write(EXI_MSR_ST_CNT, 2); 5466 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 5467 test_vmx_invalid_controls(); 5468 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 5469 test_vmx_valid_controls(); 5470 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 5471 test_vmx_valid_controls(); 5472 } 5473 5474 /* 5475 * Tests for VM-exit controls 5476 */ 5477 static void test_vm_exit_ctls(void) 5478 { 5479 test_exit_msr_store(); 5480 } 5481 5482 /* 5483 * Check that the virtual CPU checks all of the VMX controls as 5484 * documented in the Intel SDM. 5485 */ 5486 static void vmx_controls_test(void) 5487 { 5488 /* 5489 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 5490 * fail due to invalid guest state, should we make it that 5491 * far. 5492 */ 5493 vmcs_write(GUEST_RFLAGS, 0); 5494 5495 test_vm_execution_ctls(); 5496 test_vm_exit_ctls(); 5497 test_vm_entry_ctls(); 5498 } 5499 5500 struct apic_reg_virt_config { 5501 bool apic_register_virtualization; 5502 bool use_tpr_shadow; 5503 bool virtualize_apic_accesses; 5504 bool virtualize_x2apic_mode; 5505 bool activate_secondary_controls; 5506 }; 5507 5508 struct apic_reg_test { 5509 const char *name; 5510 struct apic_reg_virt_config apic_reg_virt_config; 5511 }; 5512 5513 struct apic_reg_virt_expectation { 5514 enum Reason rd_exit_reason; 5515 enum Reason wr_exit_reason; 5516 u32 val; 5517 u32 (*virt_fn)(u32); 5518 5519 /* 5520 * If false, accessing the APIC access address from L2 is treated as a 5521 * normal memory operation, rather than triggering virtualization. 5522 */ 5523 bool virtualize_apic_accesses; 5524 }; 5525 5526 static u32 apic_virt_identity(u32 val) 5527 { 5528 return val; 5529 } 5530 5531 static u32 apic_virt_nibble1(u32 val) 5532 { 5533 return val & 0xf0; 5534 } 5535 5536 static u32 apic_virt_byte3(u32 val) 5537 { 5538 return val & (0xff << 24); 5539 } 5540 5541 static bool apic_reg_virt_exit_expectation( 5542 u32 reg, struct apic_reg_virt_config *config, 5543 struct apic_reg_virt_expectation *expectation) 5544 { 5545 /* Good configs, where some L2 APIC accesses are virtualized. */ 5546 bool virtualize_apic_accesses_only = 5547 config->virtualize_apic_accesses && 5548 !config->use_tpr_shadow && 5549 !config->apic_register_virtualization && 5550 !config->virtualize_x2apic_mode && 5551 config->activate_secondary_controls; 5552 bool virtualize_apic_accesses_and_use_tpr_shadow = 5553 config->virtualize_apic_accesses && 5554 config->use_tpr_shadow && 5555 !config->apic_register_virtualization && 5556 !config->virtualize_x2apic_mode && 5557 config->activate_secondary_controls; 5558 bool apic_register_virtualization = 5559 config->virtualize_apic_accesses && 5560 config->use_tpr_shadow && 5561 config->apic_register_virtualization && 5562 !config->virtualize_x2apic_mode && 5563 config->activate_secondary_controls; 5564 5565 expectation->val = MAGIC_VAL_1; 5566 expectation->virt_fn = apic_virt_identity; 5567 expectation->virtualize_apic_accesses = 5568 config->virtualize_apic_accesses && 5569 config->activate_secondary_controls; 5570 if (virtualize_apic_accesses_only) { 5571 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5572 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5573 } else if (virtualize_apic_accesses_and_use_tpr_shadow) { 5574 switch (reg) { 5575 case APIC_TASKPRI: 5576 expectation->rd_exit_reason = VMX_VMCALL; 5577 expectation->wr_exit_reason = VMX_VMCALL; 5578 expectation->virt_fn = apic_virt_nibble1; 5579 break; 5580 default: 5581 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5582 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5583 } 5584 } else if (apic_register_virtualization) { 5585 expectation->rd_exit_reason = VMX_VMCALL; 5586 5587 switch (reg) { 5588 case APIC_ID: 5589 case APIC_EOI: 5590 case APIC_LDR: 5591 case APIC_DFR: 5592 case APIC_SPIV: 5593 case APIC_ESR: 5594 case APIC_ICR: 5595 case APIC_LVTT: 5596 case APIC_LVTTHMR: 5597 case APIC_LVTPC: 5598 case APIC_LVT0: 5599 case APIC_LVT1: 5600 case APIC_LVTERR: 5601 case APIC_TMICT: 5602 case APIC_TDCR: 5603 expectation->wr_exit_reason = VMX_APIC_WRITE; 5604 break; 5605 case APIC_LVR: 5606 case APIC_ISR ... APIC_ISR + 0x70: 5607 case APIC_TMR ... APIC_TMR + 0x70: 5608 case APIC_IRR ... APIC_IRR + 0x70: 5609 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5610 break; 5611 case APIC_TASKPRI: 5612 expectation->wr_exit_reason = VMX_VMCALL; 5613 expectation->virt_fn = apic_virt_nibble1; 5614 break; 5615 case APIC_ICR2: 5616 expectation->wr_exit_reason = VMX_VMCALL; 5617 expectation->virt_fn = apic_virt_byte3; 5618 break; 5619 default: 5620 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5621 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5622 } 5623 } else if (!expectation->virtualize_apic_accesses) { 5624 /* 5625 * No APIC registers are directly virtualized. This includes 5626 * VTPR, which can be virtualized through MOV to/from CR8 via 5627 * the use TPR shadow control, but not through directly 5628 * accessing VTPR. 5629 */ 5630 expectation->rd_exit_reason = VMX_VMCALL; 5631 expectation->wr_exit_reason = VMX_VMCALL; 5632 } else { 5633 printf("Cannot parse APIC register virtualization config:\n" 5634 "\tvirtualize_apic_accesses: %d\n" 5635 "\tuse_tpr_shadow: %d\n" 5636 "\tapic_register_virtualization: %d\n" 5637 "\tvirtualize_x2apic_mode: %d\n" 5638 "\tactivate_secondary_controls: %d\n", 5639 config->virtualize_apic_accesses, 5640 config->use_tpr_shadow, 5641 config->apic_register_virtualization, 5642 config->virtualize_x2apic_mode, 5643 config->activate_secondary_controls); 5644 5645 return false; 5646 } 5647 5648 return true; 5649 } 5650 5651 struct apic_reg_test apic_reg_tests[] = { 5652 /* Good configs, where some L2 APIC accesses are virtualized. */ 5653 { 5654 .name = "Virtualize APIC accesses", 5655 .apic_reg_virt_config = { 5656 .virtualize_apic_accesses = true, 5657 .use_tpr_shadow = false, 5658 .apic_register_virtualization = false, 5659 .virtualize_x2apic_mode = false, 5660 .activate_secondary_controls = true, 5661 }, 5662 }, 5663 { 5664 .name = "Virtualize APIC accesses + Use TPR shadow", 5665 .apic_reg_virt_config = { 5666 .virtualize_apic_accesses = true, 5667 .use_tpr_shadow = true, 5668 .apic_register_virtualization = false, 5669 .virtualize_x2apic_mode = false, 5670 .activate_secondary_controls = true, 5671 }, 5672 }, 5673 { 5674 .name = "APIC-register virtualization", 5675 .apic_reg_virt_config = { 5676 .virtualize_apic_accesses = true, 5677 .use_tpr_shadow = true, 5678 .apic_register_virtualization = true, 5679 .virtualize_x2apic_mode = false, 5680 .activate_secondary_controls = true, 5681 }, 5682 }, 5683 5684 /* 5685 * Test that the secondary processor-based VM-execution controls are 5686 * correctly ignored when "activate secondary controls" is disabled. 5687 */ 5688 { 5689 .name = "Activate secondary controls off", 5690 .apic_reg_virt_config = { 5691 .virtualize_apic_accesses = true, 5692 .use_tpr_shadow = false, 5693 .apic_register_virtualization = true, 5694 .virtualize_x2apic_mode = true, 5695 .activate_secondary_controls = false, 5696 }, 5697 }, 5698 { 5699 .name = "Activate secondary controls off + Use TPR shadow", 5700 .apic_reg_virt_config = { 5701 .virtualize_apic_accesses = true, 5702 .use_tpr_shadow = true, 5703 .apic_register_virtualization = true, 5704 .virtualize_x2apic_mode = true, 5705 .activate_secondary_controls = false, 5706 }, 5707 }, 5708 5709 /* 5710 * Test that the APIC access address is treated like an arbitrary memory 5711 * address when "virtualize APIC accesses" is disabled. 5712 */ 5713 { 5714 .name = "Virtualize APIC accesses off + Use TPR shadow", 5715 .apic_reg_virt_config = { 5716 .virtualize_apic_accesses = false, 5717 .use_tpr_shadow = true, 5718 .apic_register_virtualization = true, 5719 .virtualize_x2apic_mode = true, 5720 .activate_secondary_controls = true, 5721 }, 5722 }, 5723 5724 /* 5725 * Test that VM entry fails due to invalid controls when 5726 * "APIC-register virtualization" is enabled while "use TPR shadow" is 5727 * disabled. 5728 */ 5729 { 5730 .name = "APIC-register virtualization + Use TPR shadow off", 5731 .apic_reg_virt_config = { 5732 .virtualize_apic_accesses = true, 5733 .use_tpr_shadow = false, 5734 .apic_register_virtualization = true, 5735 .virtualize_x2apic_mode = false, 5736 .activate_secondary_controls = true, 5737 }, 5738 }, 5739 5740 /* 5741 * Test that VM entry fails due to invalid controls when 5742 * "Virtualize x2APIC mode" is enabled while "use TPR shadow" is 5743 * disabled. 5744 */ 5745 { 5746 .name = "Virtualize x2APIC mode + Use TPR shadow off", 5747 .apic_reg_virt_config = { 5748 .virtualize_apic_accesses = false, 5749 .use_tpr_shadow = false, 5750 .apic_register_virtualization = false, 5751 .virtualize_x2apic_mode = true, 5752 .activate_secondary_controls = true, 5753 }, 5754 }, 5755 { 5756 .name = "Virtualize x2APIC mode + Use TPR shadow off v2", 5757 .apic_reg_virt_config = { 5758 .virtualize_apic_accesses = false, 5759 .use_tpr_shadow = false, 5760 .apic_register_virtualization = true, 5761 .virtualize_x2apic_mode = true, 5762 .activate_secondary_controls = true, 5763 }, 5764 }, 5765 5766 /* 5767 * Test that VM entry fails due to invalid controls when 5768 * "virtualize x2APIC mode" is enabled while "virtualize APIC accesses" 5769 * is enabled. 5770 */ 5771 { 5772 .name = "Virtualize x2APIC mode + Virtualize APIC accesses", 5773 .apic_reg_virt_config = { 5774 .virtualize_apic_accesses = true, 5775 .use_tpr_shadow = true, 5776 .apic_register_virtualization = false, 5777 .virtualize_x2apic_mode = true, 5778 .activate_secondary_controls = true, 5779 }, 5780 }, 5781 { 5782 .name = "Virtualize x2APIC mode + Virtualize APIC accesses v2", 5783 .apic_reg_virt_config = { 5784 .virtualize_apic_accesses = true, 5785 .use_tpr_shadow = true, 5786 .apic_register_virtualization = true, 5787 .virtualize_x2apic_mode = true, 5788 .activate_secondary_controls = true, 5789 }, 5790 }, 5791 }; 5792 5793 enum Apic_op { 5794 APIC_OP_XAPIC_RD, 5795 APIC_OP_XAPIC_WR, 5796 TERMINATE, 5797 }; 5798 5799 static u32 vmx_xapic_read(u32 *apic_access_address, u32 reg) 5800 { 5801 return *(volatile u32 *)((uintptr_t)apic_access_address + reg); 5802 } 5803 5804 static void vmx_xapic_write(u32 *apic_access_address, u32 reg, u32 val) 5805 { 5806 *(volatile u32 *)((uintptr_t)apic_access_address + reg) = val; 5807 } 5808 5809 struct apic_reg_virt_guest_args { 5810 enum Apic_op op; 5811 u32 *apic_access_address; 5812 u32 reg; 5813 u32 val; 5814 bool check_rd; 5815 u32 (*virt_fn)(u32); 5816 } apic_reg_virt_guest_args; 5817 5818 static void apic_reg_virt_guest(void) 5819 { 5820 volatile struct apic_reg_virt_guest_args *args = 5821 &apic_reg_virt_guest_args; 5822 5823 for (;;) { 5824 enum Apic_op op = args->op; 5825 u32 *apic_access_address = args->apic_access_address; 5826 u32 reg = args->reg; 5827 u32 val = args->val; 5828 bool check_rd = args->check_rd; 5829 u32 (*virt_fn)(u32) = args->virt_fn; 5830 5831 if (op == TERMINATE) 5832 break; 5833 5834 if (op == APIC_OP_XAPIC_RD) { 5835 u32 ret = vmx_xapic_read(apic_access_address, reg); 5836 5837 if (check_rd) { 5838 u32 want = virt_fn(val); 5839 u32 got = virt_fn(ret); 5840 5841 report(got == want, 5842 "read 0x%x, expected 0x%x.", got, want); 5843 } 5844 } else if (op == APIC_OP_XAPIC_WR) { 5845 vmx_xapic_write(apic_access_address, reg, val); 5846 } 5847 5848 /* 5849 * The L1 should always execute a vmcall after it's done testing 5850 * an individual APIC operation. This helps to validate that the 5851 * L1 and L2 are in sync with each other, as expected. 5852 */ 5853 vmcall(); 5854 } 5855 } 5856 5857 static void test_xapic_rd( 5858 u32 reg, struct apic_reg_virt_expectation *expectation, 5859 u32 *apic_access_address, u32 *virtual_apic_page) 5860 { 5861 u32 val = expectation->val; 5862 u32 exit_reason_want = expectation->rd_exit_reason; 5863 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 5864 5865 report_prefix_pushf("xapic - reading 0x%03x", reg); 5866 5867 /* Configure guest to do an xapic read */ 5868 args->op = APIC_OP_XAPIC_RD; 5869 args->apic_access_address = apic_access_address; 5870 args->reg = reg; 5871 args->val = val; 5872 args->check_rd = exit_reason_want == VMX_VMCALL; 5873 args->virt_fn = expectation->virt_fn; 5874 5875 /* Setup virtual APIC page */ 5876 if (!expectation->virtualize_apic_accesses) { 5877 apic_access_address[apic_reg_index(reg)] = val; 5878 virtual_apic_page[apic_reg_index(reg)] = 0; 5879 } else if (exit_reason_want == VMX_VMCALL) { 5880 apic_access_address[apic_reg_index(reg)] = 0; 5881 virtual_apic_page[apic_reg_index(reg)] = val; 5882 } 5883 5884 /* Enter guest */ 5885 enter_guest(); 5886 5887 /* 5888 * Validate the behavior and 5889 * pass a magic value back to the guest. 5890 */ 5891 if (exit_reason_want == VMX_APIC_ACCESS) { 5892 u32 apic_page_offset = vmcs_read(EXI_QUALIFICATION) & 0xfff; 5893 5894 assert_exit_reason(exit_reason_want); 5895 report(apic_page_offset == reg, 5896 "got APIC access exit @ page offset 0x%03x, want 0x%03x", 5897 apic_page_offset, reg); 5898 skip_exit_insn(); 5899 5900 /* Reenter guest so it can consume/check rcx and exit again. */ 5901 enter_guest(); 5902 } else if (exit_reason_want != VMX_VMCALL) { 5903 report(false, "Oops, bad exit expectation: %u.", 5904 exit_reason_want); 5905 } 5906 5907 skip_exit_vmcall(); 5908 report_prefix_pop(); 5909 } 5910 5911 static void test_xapic_wr( 5912 u32 reg, struct apic_reg_virt_expectation *expectation, 5913 u32 *apic_access_address, u32 *virtual_apic_page) 5914 { 5915 u32 val = expectation->val; 5916 u32 exit_reason_want = expectation->wr_exit_reason; 5917 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 5918 bool virtualized = 5919 expectation->virtualize_apic_accesses && 5920 (exit_reason_want == VMX_APIC_WRITE || 5921 exit_reason_want == VMX_VMCALL); 5922 bool checked = false; 5923 5924 report_prefix_pushf("xapic - writing 0x%x to 0x%03x", val, reg); 5925 5926 /* Configure guest to do an xapic read */ 5927 args->op = APIC_OP_XAPIC_WR; 5928 args->apic_access_address = apic_access_address; 5929 args->reg = reg; 5930 args->val = val; 5931 5932 /* Setup virtual APIC page */ 5933 if (virtualized || !expectation->virtualize_apic_accesses) { 5934 apic_access_address[apic_reg_index(reg)] = 0; 5935 virtual_apic_page[apic_reg_index(reg)] = 0; 5936 } 5937 5938 /* Enter guest */ 5939 enter_guest(); 5940 5941 /* 5942 * Validate the behavior and 5943 * pass a magic value back to the guest. 5944 */ 5945 if (exit_reason_want == VMX_APIC_ACCESS) { 5946 u32 apic_page_offset = vmcs_read(EXI_QUALIFICATION) & 0xfff; 5947 5948 assert_exit_reason(exit_reason_want); 5949 report(apic_page_offset == reg, 5950 "got APIC access exit @ page offset 0x%03x, want 0x%03x", 5951 apic_page_offset, reg); 5952 skip_exit_insn(); 5953 5954 /* Reenter guest so it can consume/check rcx and exit again. */ 5955 enter_guest(); 5956 } else if (exit_reason_want == VMX_APIC_WRITE) { 5957 assert_exit_reason(exit_reason_want); 5958 report(virtual_apic_page[apic_reg_index(reg)] == val, 5959 "got APIC write exit @ page offset 0x%03x; val is 0x%x, want 0x%x", 5960 apic_reg_index(reg), 5961 virtual_apic_page[apic_reg_index(reg)], val); 5962 checked = true; 5963 5964 /* Reenter guest so it can consume/check rcx and exit again. */ 5965 enter_guest(); 5966 } else if (exit_reason_want != VMX_VMCALL) { 5967 report(false, "Oops, bad exit expectation: %u.", 5968 exit_reason_want); 5969 } 5970 5971 assert_exit_reason(VMX_VMCALL); 5972 if (virtualized && !checked) { 5973 u32 want = expectation->virt_fn(val); 5974 u32 got = virtual_apic_page[apic_reg_index(reg)]; 5975 got = expectation->virt_fn(got); 5976 5977 report(got == want, "exitless write; val is 0x%x, want 0x%x", 5978 got, want); 5979 } else if (!expectation->virtualize_apic_accesses && !checked) { 5980 u32 got = apic_access_address[apic_reg_index(reg)]; 5981 5982 report(got == val, 5983 "non-virtualized write; val is 0x%x, want 0x%x", got, 5984 val); 5985 } else if (!expectation->virtualize_apic_accesses && checked) { 5986 report(false, 5987 "Non-virtualized write was prematurely checked!"); 5988 } 5989 5990 skip_exit_vmcall(); 5991 report_prefix_pop(); 5992 } 5993 5994 enum Config_type { 5995 CONFIG_TYPE_GOOD, 5996 CONFIG_TYPE_UNSUPPORTED, 5997 CONFIG_TYPE_VMENTRY_FAILS_EARLY, 5998 }; 5999 6000 static enum Config_type configure_apic_reg_virt_test( 6001 struct apic_reg_virt_config *apic_reg_virt_config) 6002 { 6003 u32 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6004 u32 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6005 /* Configs where L2 entry fails early, due to invalid controls. */ 6006 bool use_tpr_shadow_incorrectly_off = 6007 !apic_reg_virt_config->use_tpr_shadow && 6008 (apic_reg_virt_config->apic_register_virtualization || 6009 apic_reg_virt_config->virtualize_x2apic_mode) && 6010 apic_reg_virt_config->activate_secondary_controls; 6011 bool virtualize_apic_accesses_incorrectly_on = 6012 apic_reg_virt_config->virtualize_apic_accesses && 6013 apic_reg_virt_config->virtualize_x2apic_mode && 6014 apic_reg_virt_config->activate_secondary_controls; 6015 bool vmentry_fails_early = 6016 use_tpr_shadow_incorrectly_off || 6017 virtualize_apic_accesses_incorrectly_on; 6018 6019 if (apic_reg_virt_config->activate_secondary_controls) { 6020 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 6021 printf("VM-execution control \"activate secondary controls\" NOT supported.\n"); 6022 return CONFIG_TYPE_UNSUPPORTED; 6023 } 6024 cpu_exec_ctrl0 |= CPU_SECONDARY; 6025 } else { 6026 cpu_exec_ctrl0 &= ~CPU_SECONDARY; 6027 } 6028 6029 if (apic_reg_virt_config->virtualize_apic_accesses) { 6030 if (!(ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES)) { 6031 printf("VM-execution control \"virtualize APIC accesses\" NOT supported.\n"); 6032 return CONFIG_TYPE_UNSUPPORTED; 6033 } 6034 cpu_exec_ctrl1 |= CPU_VIRT_APIC_ACCESSES; 6035 } else { 6036 cpu_exec_ctrl1 &= ~CPU_VIRT_APIC_ACCESSES; 6037 } 6038 6039 if (apic_reg_virt_config->use_tpr_shadow) { 6040 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) { 6041 printf("VM-execution control \"use TPR shadow\" NOT supported.\n"); 6042 return CONFIG_TYPE_UNSUPPORTED; 6043 } 6044 cpu_exec_ctrl0 |= CPU_TPR_SHADOW; 6045 } else { 6046 cpu_exec_ctrl0 &= ~CPU_TPR_SHADOW; 6047 } 6048 6049 if (apic_reg_virt_config->apic_register_virtualization) { 6050 if (!(ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT)) { 6051 printf("VM-execution control \"APIC-register virtualization\" NOT supported.\n"); 6052 return CONFIG_TYPE_UNSUPPORTED; 6053 } 6054 cpu_exec_ctrl1 |= CPU_APIC_REG_VIRT; 6055 } else { 6056 cpu_exec_ctrl1 &= ~CPU_APIC_REG_VIRT; 6057 } 6058 6059 if (apic_reg_virt_config->virtualize_x2apic_mode) { 6060 if (!(ctrl_cpu_rev[1].clr & CPU_VIRT_X2APIC)) { 6061 printf("VM-execution control \"virtualize x2APIC mode\" NOT supported.\n"); 6062 return CONFIG_TYPE_UNSUPPORTED; 6063 } 6064 cpu_exec_ctrl1 |= CPU_VIRT_X2APIC; 6065 } else { 6066 cpu_exec_ctrl1 &= ~CPU_VIRT_X2APIC; 6067 } 6068 6069 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6070 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6071 6072 if (vmentry_fails_early) 6073 return CONFIG_TYPE_VMENTRY_FAILS_EARLY; 6074 6075 return CONFIG_TYPE_GOOD; 6076 } 6077 6078 static bool cpu_has_apicv(void) 6079 { 6080 return ((ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT) && 6081 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 6082 (ctrl_pin_rev.clr & PIN_POST_INTR)); 6083 } 6084 6085 /* Validates APIC register access across valid virtualization configurations. */ 6086 static void apic_reg_virt_test(void) 6087 { 6088 u32 *apic_access_address; 6089 u32 *virtual_apic_page; 6090 u64 control; 6091 u64 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6092 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6093 int i; 6094 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 6095 6096 if (!cpu_has_apicv()) { 6097 report_skip(__func__); 6098 return; 6099 } 6100 6101 control = cpu_exec_ctrl1; 6102 control &= ~CPU_VINTD; 6103 vmcs_write(CPU_EXEC_CTRL1, control); 6104 6105 test_set_guest(apic_reg_virt_guest); 6106 6107 /* 6108 * From the SDM: The 1-setting of the "virtualize APIC accesses" 6109 * VM-execution is guaranteed to apply only if translations to the 6110 * APIC-access address use a 4-KByte page. 6111 */ 6112 apic_access_address = alloc_page(); 6113 force_4k_page(apic_access_address); 6114 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_address)); 6115 6116 virtual_apic_page = alloc_page(); 6117 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 6118 6119 for (i = 0; i < ARRAY_SIZE(apic_reg_tests); i++) { 6120 struct apic_reg_test *apic_reg_test = &apic_reg_tests[i]; 6121 struct apic_reg_virt_config *apic_reg_virt_config = 6122 &apic_reg_test->apic_reg_virt_config; 6123 enum Config_type config_type; 6124 u32 reg; 6125 6126 printf("--- %s test ---\n", apic_reg_test->name); 6127 config_type = 6128 configure_apic_reg_virt_test(apic_reg_virt_config); 6129 if (config_type == CONFIG_TYPE_UNSUPPORTED) { 6130 printf("Skip because of missing features.\n"); 6131 continue; 6132 } 6133 6134 if (config_type == CONFIG_TYPE_VMENTRY_FAILS_EARLY) { 6135 enter_guest_with_bad_controls(); 6136 continue; 6137 } 6138 6139 for (reg = 0; reg < PAGE_SIZE / sizeof(u32); reg += 0x10) { 6140 struct apic_reg_virt_expectation expectation = {}; 6141 bool ok; 6142 6143 ok = apic_reg_virt_exit_expectation( 6144 reg, apic_reg_virt_config, &expectation); 6145 if (!ok) { 6146 report(false, "Malformed test."); 6147 break; 6148 } 6149 6150 test_xapic_rd(reg, &expectation, apic_access_address, 6151 virtual_apic_page); 6152 test_xapic_wr(reg, &expectation, apic_access_address, 6153 virtual_apic_page); 6154 } 6155 } 6156 6157 /* Terminate the guest */ 6158 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6159 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6160 args->op = TERMINATE; 6161 enter_guest(); 6162 assert_exit_reason(VMX_VMCALL); 6163 } 6164 6165 struct virt_x2apic_mode_config { 6166 struct apic_reg_virt_config apic_reg_virt_config; 6167 bool virtual_interrupt_delivery; 6168 bool use_msr_bitmaps; 6169 bool disable_x2apic_msr_intercepts; 6170 bool disable_x2apic; 6171 }; 6172 6173 struct virt_x2apic_mode_test_case { 6174 const char *name; 6175 struct virt_x2apic_mode_config virt_x2apic_mode_config; 6176 }; 6177 6178 enum Virt_x2apic_mode_behavior_type { 6179 X2APIC_ACCESS_VIRTUALIZED, 6180 X2APIC_ACCESS_PASSED_THROUGH, 6181 X2APIC_ACCESS_TRIGGERS_GP, 6182 }; 6183 6184 struct virt_x2apic_mode_expectation { 6185 enum Reason rd_exit_reason; 6186 enum Reason wr_exit_reason; 6187 6188 /* 6189 * RDMSR and WRMSR handle 64-bit values. However, except for ICR, all of 6190 * the x2APIC registers are 32 bits. Notice: 6191 * 1. vmx_x2apic_read() clears the upper 32 bits for 32-bit registers. 6192 * 2. vmx_x2apic_write() expects the val arg to be well-formed. 6193 */ 6194 u64 rd_val; 6195 u64 wr_val; 6196 6197 /* 6198 * Compares input to virtualized output; 6199 * 1st arg is pointer to return expected virtualization output. 6200 */ 6201 u64 (*virt_fn)(u64); 6202 6203 enum Virt_x2apic_mode_behavior_type rd_behavior; 6204 enum Virt_x2apic_mode_behavior_type wr_behavior; 6205 bool wr_only; 6206 }; 6207 6208 static u64 virt_x2apic_mode_identity(u64 val) 6209 { 6210 return val; 6211 } 6212 6213 static u64 virt_x2apic_mode_nibble1(u64 val) 6214 { 6215 return val & 0xf0; 6216 } 6217 6218 static void virt_x2apic_mode_rd_expectation( 6219 u32 reg, bool virt_x2apic_mode_on, bool disable_x2apic, 6220 bool apic_register_virtualization, bool virtual_interrupt_delivery, 6221 struct virt_x2apic_mode_expectation *expectation) 6222 { 6223 bool readable = 6224 !x2apic_reg_reserved(reg) && 6225 reg != APIC_EOI; 6226 6227 expectation->rd_exit_reason = VMX_VMCALL; 6228 expectation->virt_fn = virt_x2apic_mode_identity; 6229 if (virt_x2apic_mode_on && apic_register_virtualization) { 6230 expectation->rd_val = MAGIC_VAL_1; 6231 if (reg == APIC_PROCPRI && virtual_interrupt_delivery) 6232 expectation->virt_fn = virt_x2apic_mode_nibble1; 6233 else if (reg == APIC_TASKPRI) 6234 expectation->virt_fn = virt_x2apic_mode_nibble1; 6235 expectation->rd_behavior = X2APIC_ACCESS_VIRTUALIZED; 6236 } else if (virt_x2apic_mode_on && !apic_register_virtualization && 6237 reg == APIC_TASKPRI) { 6238 expectation->rd_val = MAGIC_VAL_1; 6239 expectation->virt_fn = virt_x2apic_mode_nibble1; 6240 expectation->rd_behavior = X2APIC_ACCESS_VIRTUALIZED; 6241 } else if (!disable_x2apic && readable) { 6242 expectation->rd_val = apic_read(reg); 6243 expectation->rd_behavior = X2APIC_ACCESS_PASSED_THROUGH; 6244 } else { 6245 expectation->rd_behavior = X2APIC_ACCESS_TRIGGERS_GP; 6246 } 6247 } 6248 6249 /* 6250 * get_x2apic_wr_val() creates an innocuous write value for an x2APIC register. 6251 * 6252 * For writable registers, get_x2apic_wr_val() deposits the write value into the 6253 * val pointer arg and returns true. For non-writable registers, val is not 6254 * modified and get_x2apic_wr_val() returns false. 6255 */ 6256 static bool get_x2apic_wr_val(u32 reg, u64 *val) 6257 { 6258 switch (reg) { 6259 case APIC_TASKPRI: 6260 /* Bits 31:8 are reserved. */ 6261 *val &= 0xff; 6262 break; 6263 case APIC_EOI: 6264 case APIC_ESR: 6265 case APIC_TMICT: 6266 /* 6267 * EOI, ESR: WRMSR of a non-zero value causes #GP(0). 6268 * TMICT: A write of 0 to the initial-count register effectively 6269 * stops the local APIC timer, in both one-shot and 6270 * periodic mode. 6271 */ 6272 *val = 0; 6273 break; 6274 case APIC_SPIV: 6275 case APIC_LVTT: 6276 case APIC_LVTTHMR: 6277 case APIC_LVTPC: 6278 case APIC_LVT0: 6279 case APIC_LVT1: 6280 case APIC_LVTERR: 6281 case APIC_TDCR: 6282 /* 6283 * To avoid writing a 1 to a reserved bit or causing some other 6284 * unintended side effect, read the current value and use it as 6285 * the write value. 6286 */ 6287 *val = apic_read(reg); 6288 break; 6289 case APIC_CMCI: 6290 if (!apic_lvt_entry_supported(6)) 6291 return false; 6292 *val = apic_read(reg); 6293 break; 6294 case APIC_ICR: 6295 *val = 0x40000 | 0xf1; 6296 break; 6297 case APIC_SELF_IPI: 6298 /* 6299 * With special processing (i.e., virtualize x2APIC mode + 6300 * virtual interrupt delivery), writing zero causes an 6301 * APIC-write VM exit. We plan to add a test for enabling 6302 * "virtual-interrupt delivery" in VMCS12, and that's where we 6303 * will test a self IPI with special processing. 6304 */ 6305 *val = 0x0; 6306 break; 6307 default: 6308 return false; 6309 } 6310 6311 return true; 6312 } 6313 6314 static bool special_processing_applies(u32 reg, u64 *val, 6315 bool virt_int_delivery) 6316 { 6317 bool special_processing = 6318 (reg == APIC_TASKPRI) || 6319 (virt_int_delivery && 6320 (reg == APIC_EOI || reg == APIC_SELF_IPI)); 6321 6322 if (special_processing) { 6323 TEST_ASSERT(get_x2apic_wr_val(reg, val)); 6324 return true; 6325 } 6326 6327 return false; 6328 } 6329 6330 static void virt_x2apic_mode_wr_expectation( 6331 u32 reg, bool virt_x2apic_mode_on, bool disable_x2apic, 6332 bool virt_int_delivery, 6333 struct virt_x2apic_mode_expectation *expectation) 6334 { 6335 expectation->wr_exit_reason = VMX_VMCALL; 6336 expectation->wr_val = MAGIC_VAL_1; 6337 expectation->wr_only = false; 6338 6339 if (virt_x2apic_mode_on && 6340 special_processing_applies(reg, &expectation->wr_val, 6341 virt_int_delivery)) { 6342 expectation->wr_behavior = X2APIC_ACCESS_VIRTUALIZED; 6343 if (reg == APIC_SELF_IPI) 6344 expectation->wr_exit_reason = VMX_APIC_WRITE; 6345 } else if (!disable_x2apic && 6346 get_x2apic_wr_val(reg, &expectation->wr_val)) { 6347 expectation->wr_behavior = X2APIC_ACCESS_PASSED_THROUGH; 6348 if (reg == APIC_EOI || reg == APIC_SELF_IPI) 6349 expectation->wr_only = true; 6350 if (reg == APIC_ICR) 6351 expectation->wr_exit_reason = VMX_EXTINT; 6352 } else { 6353 expectation->wr_behavior = X2APIC_ACCESS_TRIGGERS_GP; 6354 /* 6355 * Writing 1 to a reserved bit triggers a #GP. 6356 * Thus, set the write value to 0, which seems 6357 * the most likely to detect a missed #GP. 6358 */ 6359 expectation->wr_val = 0; 6360 } 6361 } 6362 6363 static void virt_x2apic_mode_exit_expectation( 6364 u32 reg, struct virt_x2apic_mode_config *config, 6365 struct virt_x2apic_mode_expectation *expectation) 6366 { 6367 struct apic_reg_virt_config *base_config = 6368 &config->apic_reg_virt_config; 6369 bool virt_x2apic_mode_on = 6370 base_config->virtualize_x2apic_mode && 6371 config->use_msr_bitmaps && 6372 config->disable_x2apic_msr_intercepts && 6373 base_config->activate_secondary_controls; 6374 6375 virt_x2apic_mode_wr_expectation( 6376 reg, virt_x2apic_mode_on, config->disable_x2apic, 6377 config->virtual_interrupt_delivery, expectation); 6378 virt_x2apic_mode_rd_expectation( 6379 reg, virt_x2apic_mode_on, config->disable_x2apic, 6380 base_config->apic_register_virtualization, 6381 config->virtual_interrupt_delivery, expectation); 6382 } 6383 6384 struct virt_x2apic_mode_test_case virt_x2apic_mode_tests[] = { 6385 /* 6386 * Baseline "virtualize x2APIC mode" configuration: 6387 * - virtualize x2APIC mode 6388 * - virtual-interrupt delivery 6389 * - APIC-register virtualization 6390 * - x2APIC MSR intercepts disabled 6391 * 6392 * Reads come from virtual APIC page, special processing applies to 6393 * VTPR, EOI, and SELF IPI, and all other writes pass through to L1 6394 * APIC. 6395 */ 6396 { 6397 .name = "Baseline", 6398 .virt_x2apic_mode_config = { 6399 .virtual_interrupt_delivery = true, 6400 .use_msr_bitmaps = true, 6401 .disable_x2apic_msr_intercepts = true, 6402 .disable_x2apic = false, 6403 .apic_reg_virt_config = { 6404 .apic_register_virtualization = true, 6405 .use_tpr_shadow = true, 6406 .virtualize_apic_accesses = false, 6407 .virtualize_x2apic_mode = true, 6408 .activate_secondary_controls = true, 6409 }, 6410 }, 6411 }, 6412 { 6413 .name = "Baseline w/ x2apic disabled", 6414 .virt_x2apic_mode_config = { 6415 .virtual_interrupt_delivery = true, 6416 .use_msr_bitmaps = true, 6417 .disable_x2apic_msr_intercepts = true, 6418 .disable_x2apic = true, 6419 .apic_reg_virt_config = { 6420 .apic_register_virtualization = true, 6421 .use_tpr_shadow = true, 6422 .virtualize_apic_accesses = false, 6423 .virtualize_x2apic_mode = true, 6424 .activate_secondary_controls = true, 6425 }, 6426 }, 6427 }, 6428 6429 /* 6430 * Baseline, minus virtual-interrupt delivery. Reads come from virtual 6431 * APIC page, special processing applies to VTPR, and all other writes 6432 * pass through to L1 APIC. 6433 */ 6434 { 6435 .name = "Baseline - virtual interrupt delivery", 6436 .virt_x2apic_mode_config = { 6437 .virtual_interrupt_delivery = false, 6438 .use_msr_bitmaps = true, 6439 .disable_x2apic_msr_intercepts = true, 6440 .disable_x2apic = false, 6441 .apic_reg_virt_config = { 6442 .apic_register_virtualization = true, 6443 .use_tpr_shadow = true, 6444 .virtualize_apic_accesses = false, 6445 .virtualize_x2apic_mode = true, 6446 .activate_secondary_controls = true, 6447 }, 6448 }, 6449 }, 6450 6451 /* 6452 * Baseline, minus APIC-register virtualization. x2APIC reads pass 6453 * through to L1's APIC, unless reading VTPR 6454 */ 6455 { 6456 .name = "Virtualize x2APIC mode, no APIC reg virt", 6457 .virt_x2apic_mode_config = { 6458 .virtual_interrupt_delivery = true, 6459 .use_msr_bitmaps = true, 6460 .disable_x2apic_msr_intercepts = true, 6461 .disable_x2apic = false, 6462 .apic_reg_virt_config = { 6463 .apic_register_virtualization = false, 6464 .use_tpr_shadow = true, 6465 .virtualize_apic_accesses = false, 6466 .virtualize_x2apic_mode = true, 6467 .activate_secondary_controls = true, 6468 }, 6469 }, 6470 }, 6471 { 6472 .name = "Virtualize x2APIC mode, no APIC reg virt, x2APIC off", 6473 .virt_x2apic_mode_config = { 6474 .virtual_interrupt_delivery = true, 6475 .use_msr_bitmaps = true, 6476 .disable_x2apic_msr_intercepts = true, 6477 .disable_x2apic = true, 6478 .apic_reg_virt_config = { 6479 .apic_register_virtualization = false, 6480 .use_tpr_shadow = true, 6481 .virtualize_apic_accesses = false, 6482 .virtualize_x2apic_mode = true, 6483 .activate_secondary_controls = true, 6484 }, 6485 }, 6486 }, 6487 6488 /* 6489 * Enable "virtualize x2APIC mode" and "APIC-register virtualization", 6490 * and disable intercepts for the x2APIC MSRs, but fail to enable 6491 * "activate secondary controls" (i.e. L2 gets access to L1's x2APIC 6492 * MSRs). 6493 */ 6494 { 6495 .name = "Fail to enable activate secondary controls", 6496 .virt_x2apic_mode_config = { 6497 .virtual_interrupt_delivery = true, 6498 .use_msr_bitmaps = true, 6499 .disable_x2apic_msr_intercepts = true, 6500 .disable_x2apic = false, 6501 .apic_reg_virt_config = { 6502 .apic_register_virtualization = true, 6503 .use_tpr_shadow = true, 6504 .virtualize_apic_accesses = false, 6505 .virtualize_x2apic_mode = true, 6506 .activate_secondary_controls = false, 6507 }, 6508 }, 6509 }, 6510 6511 /* 6512 * Enable "APIC-register virtualization" and enable "activate secondary 6513 * controls" and disable intercepts for the x2APIC MSRs, but do not 6514 * enable the "virtualize x2APIC mode" VM-execution control (i.e. L2 6515 * gets access to L1's x2APIC MSRs). 6516 */ 6517 { 6518 .name = "Fail to enable virtualize x2APIC mode", 6519 .virt_x2apic_mode_config = { 6520 .virtual_interrupt_delivery = true, 6521 .use_msr_bitmaps = true, 6522 .disable_x2apic_msr_intercepts = true, 6523 .disable_x2apic = false, 6524 .apic_reg_virt_config = { 6525 .apic_register_virtualization = true, 6526 .use_tpr_shadow = true, 6527 .virtualize_apic_accesses = false, 6528 .virtualize_x2apic_mode = false, 6529 .activate_secondary_controls = true, 6530 }, 6531 }, 6532 }, 6533 6534 /* 6535 * Disable "Virtualize x2APIC mode", disable x2APIC MSR intercepts, and 6536 * enable "APIC-register virtualization" --> L2 gets L1's x2APIC MSRs. 6537 */ 6538 { 6539 .name = "Baseline", 6540 .virt_x2apic_mode_config = { 6541 .virtual_interrupt_delivery = true, 6542 .use_msr_bitmaps = true, 6543 .disable_x2apic_msr_intercepts = true, 6544 .disable_x2apic = false, 6545 .apic_reg_virt_config = { 6546 .apic_register_virtualization = true, 6547 .use_tpr_shadow = true, 6548 .virtualize_apic_accesses = false, 6549 .virtualize_x2apic_mode = false, 6550 .activate_secondary_controls = true, 6551 }, 6552 }, 6553 }, 6554 }; 6555 6556 enum X2apic_op { 6557 X2APIC_OP_RD, 6558 X2APIC_OP_WR, 6559 X2APIC_TERMINATE, 6560 }; 6561 6562 static u64 vmx_x2apic_read(u32 reg) 6563 { 6564 u32 msr_addr = x2apic_msr(reg); 6565 u64 val; 6566 6567 val = rdmsr(msr_addr); 6568 6569 return val; 6570 } 6571 6572 static void vmx_x2apic_write(u32 reg, u64 val) 6573 { 6574 u32 msr_addr = x2apic_msr(reg); 6575 6576 wrmsr(msr_addr, val); 6577 } 6578 6579 struct virt_x2apic_mode_guest_args { 6580 enum X2apic_op op; 6581 u32 reg; 6582 u64 val; 6583 bool should_gp; 6584 u64 (*virt_fn)(u64); 6585 } virt_x2apic_mode_guest_args; 6586 6587 static volatile bool handle_x2apic_gp_ran; 6588 static volatile u32 handle_x2apic_gp_insn_len; 6589 static void handle_x2apic_gp(struct ex_regs *regs) 6590 { 6591 handle_x2apic_gp_ran = true; 6592 regs->rip += handle_x2apic_gp_insn_len; 6593 } 6594 6595 static handler setup_x2apic_gp_handler(void) 6596 { 6597 handler old_handler; 6598 6599 old_handler = handle_exception(GP_VECTOR, handle_x2apic_gp); 6600 /* RDMSR and WRMSR are both 2 bytes, assuming no prefixes. */ 6601 handle_x2apic_gp_insn_len = 2; 6602 6603 return old_handler; 6604 } 6605 6606 static void teardown_x2apic_gp_handler(handler old_handler) 6607 { 6608 handle_exception(GP_VECTOR, old_handler); 6609 6610 /* 6611 * Defensively reset instruction length, so that if the handler is 6612 * incorrectly used, it will loop infinitely, rather than run off into 6613 * la la land. 6614 */ 6615 handle_x2apic_gp_insn_len = 0; 6616 handle_x2apic_gp_ran = false; 6617 } 6618 6619 static void virt_x2apic_mode_guest(void) 6620 { 6621 volatile struct virt_x2apic_mode_guest_args *args = 6622 &virt_x2apic_mode_guest_args; 6623 6624 for (;;) { 6625 enum X2apic_op op = args->op; 6626 u32 reg = args->reg; 6627 u64 val = args->val; 6628 bool should_gp = args->should_gp; 6629 u64 (*virt_fn)(u64) = args->virt_fn; 6630 handler old_handler; 6631 6632 if (op == X2APIC_TERMINATE) 6633 break; 6634 6635 if (should_gp) { 6636 TEST_ASSERT(!handle_x2apic_gp_ran); 6637 old_handler = setup_x2apic_gp_handler(); 6638 } 6639 6640 if (op == X2APIC_OP_RD) { 6641 u64 ret = vmx_x2apic_read(reg); 6642 6643 if (!should_gp) { 6644 u64 want = virt_fn(val); 6645 u64 got = virt_fn(ret); 6646 6647 report(got == want, 6648 "APIC read; got 0x%lx, want 0x%lx.", 6649 got, want); 6650 } 6651 } else if (op == X2APIC_OP_WR) { 6652 vmx_x2apic_write(reg, val); 6653 } 6654 6655 if (should_gp) { 6656 report(handle_x2apic_gp_ran, 6657 "x2APIC op triggered GP."); 6658 teardown_x2apic_gp_handler(old_handler); 6659 } 6660 6661 /* 6662 * The L1 should always execute a vmcall after it's done testing 6663 * an individual APIC operation. This helps to validate that the 6664 * L1 and L2 are in sync with each other, as expected. 6665 */ 6666 vmcall(); 6667 } 6668 } 6669 6670 static void test_x2apic_rd( 6671 u32 reg, struct virt_x2apic_mode_expectation *expectation, 6672 u32 *virtual_apic_page) 6673 { 6674 u64 val = expectation->rd_val; 6675 u32 exit_reason_want = expectation->rd_exit_reason; 6676 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6677 6678 report_prefix_pushf("x2apic - reading 0x%03x", reg); 6679 6680 /* Configure guest to do an x2apic read */ 6681 args->op = X2APIC_OP_RD; 6682 args->reg = reg; 6683 args->val = val; 6684 args->should_gp = expectation->rd_behavior == X2APIC_ACCESS_TRIGGERS_GP; 6685 args->virt_fn = expectation->virt_fn; 6686 6687 /* Setup virtual APIC page */ 6688 if (expectation->rd_behavior == X2APIC_ACCESS_VIRTUALIZED) 6689 virtual_apic_page[apic_reg_index(reg)] = (u32)val; 6690 6691 /* Enter guest */ 6692 enter_guest(); 6693 6694 if (exit_reason_want != VMX_VMCALL) { 6695 report(false, "Oops, bad exit expectation: %u.", 6696 exit_reason_want); 6697 } 6698 6699 skip_exit_vmcall(); 6700 report_prefix_pop(); 6701 } 6702 6703 static volatile bool handle_x2apic_ipi_ran; 6704 static void handle_x2apic_ipi(isr_regs_t *regs) 6705 { 6706 handle_x2apic_ipi_ran = true; 6707 eoi(); 6708 } 6709 6710 static void test_x2apic_wr( 6711 u32 reg, struct virt_x2apic_mode_expectation *expectation, 6712 u32 *virtual_apic_page) 6713 { 6714 u64 val = expectation->wr_val; 6715 u32 exit_reason_want = expectation->wr_exit_reason; 6716 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6717 int ipi_vector = 0xf1; 6718 u32 restore_val = 0; 6719 6720 report_prefix_pushf("x2apic - writing 0x%lx to 0x%03x", val, reg); 6721 6722 /* Configure guest to do an x2apic read */ 6723 args->op = X2APIC_OP_WR; 6724 args->reg = reg; 6725 args->val = val; 6726 args->should_gp = expectation->wr_behavior == X2APIC_ACCESS_TRIGGERS_GP; 6727 6728 /* Setup virtual APIC page */ 6729 if (expectation->wr_behavior == X2APIC_ACCESS_VIRTUALIZED) 6730 virtual_apic_page[apic_reg_index(reg)] = 0; 6731 if (expectation->wr_behavior == X2APIC_ACCESS_PASSED_THROUGH && !expectation->wr_only) 6732 restore_val = apic_read(reg); 6733 6734 /* Setup IPI handler */ 6735 handle_x2apic_ipi_ran = false; 6736 handle_irq(ipi_vector, handle_x2apic_ipi); 6737 6738 /* Enter guest */ 6739 enter_guest(); 6740 6741 /* 6742 * Validate the behavior and 6743 * pass a magic value back to the guest. 6744 */ 6745 if (exit_reason_want == VMX_EXTINT) { 6746 assert_exit_reason(exit_reason_want); 6747 6748 /* Clear the external interrupt. */ 6749 irq_enable(); 6750 asm volatile ("nop"); 6751 irq_disable(); 6752 report(handle_x2apic_ipi_ran, 6753 "Got pending interrupt after IRQ enabled."); 6754 6755 enter_guest(); 6756 } else if (exit_reason_want == VMX_APIC_WRITE) { 6757 assert_exit_reason(exit_reason_want); 6758 report(virtual_apic_page[apic_reg_index(reg)] == val, 6759 "got APIC write exit @ page offset 0x%03x; val is 0x%x, want 0x%lx", 6760 apic_reg_index(reg), 6761 virtual_apic_page[apic_reg_index(reg)], val); 6762 6763 /* Reenter guest so it can consume/check rcx and exit again. */ 6764 enter_guest(); 6765 } else if (exit_reason_want != VMX_VMCALL) { 6766 report(false, "Oops, bad exit expectation: %u.", 6767 exit_reason_want); 6768 } 6769 6770 assert_exit_reason(VMX_VMCALL); 6771 if (expectation->wr_behavior == X2APIC_ACCESS_VIRTUALIZED) { 6772 u64 want = val; 6773 u32 got = virtual_apic_page[apic_reg_index(reg)]; 6774 6775 report(got == want, "x2APIC write; got 0x%x, want 0x%lx", got, 6776 want); 6777 } else if (expectation->wr_behavior == X2APIC_ACCESS_PASSED_THROUGH) { 6778 if (!expectation->wr_only) { 6779 u32 got = apic_read(reg); 6780 bool ok; 6781 6782 /* 6783 * When L1's TPR is passed through to L2, the lower 6784 * nibble can be lost. For example, if L2 executes 6785 * WRMSR(0x808, 0x78), then, L1 might read 0x70. 6786 * 6787 * Here's how the lower nibble can get lost: 6788 * 1. L2 executes WRMSR(0x808, 0x78). 6789 * 2. L2 exits to L0 with a WRMSR exit. 6790 * 3. L0 emulates WRMSR, by writing L1's TPR. 6791 * 4. L0 re-enters L2. 6792 * 5. L2 exits to L0 (reason doesn't matter). 6793 * 6. L0 reflects L2's exit to L1. 6794 * 7. Before entering L1, L0 exits to user-space 6795 * (e.g., to satisfy TPR access reporting). 6796 * 8. User-space executes KVM_SET_REGS ioctl, which 6797 * clears the lower nibble of L1's TPR. 6798 */ 6799 if (reg == APIC_TASKPRI) { 6800 got = apic_virt_nibble1(got); 6801 val = apic_virt_nibble1(val); 6802 } 6803 6804 ok = got == val; 6805 report(ok, 6806 "non-virtualized write; val is 0x%x, want 0x%lx", 6807 got, val); 6808 apic_write(reg, restore_val); 6809 } else { 6810 report(true, "non-virtualized and write-only OK"); 6811 } 6812 } 6813 skip_exit_insn(); 6814 6815 report_prefix_pop(); 6816 } 6817 6818 static enum Config_type configure_virt_x2apic_mode_test( 6819 struct virt_x2apic_mode_config *virt_x2apic_mode_config, 6820 u8 *msr_bitmap_page) 6821 { 6822 int msr; 6823 u32 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6824 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6825 6826 /* x2apic-specific VMCS config */ 6827 if (virt_x2apic_mode_config->use_msr_bitmaps) { 6828 /* virt_x2apic_mode_test() checks for MSR bitmaps support */ 6829 cpu_exec_ctrl0 |= CPU_MSR_BITMAP; 6830 } else { 6831 cpu_exec_ctrl0 &= ~CPU_MSR_BITMAP; 6832 } 6833 6834 if (virt_x2apic_mode_config->virtual_interrupt_delivery) { 6835 if (!(ctrl_cpu_rev[1].clr & CPU_VINTD)) { 6836 report_skip("VM-execution control \"virtual-interrupt delivery\" NOT supported.\n"); 6837 return CONFIG_TYPE_UNSUPPORTED; 6838 } 6839 cpu_exec_ctrl1 |= CPU_VINTD; 6840 } else { 6841 cpu_exec_ctrl1 &= ~CPU_VINTD; 6842 } 6843 6844 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6845 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6846 6847 /* x2APIC MSR intercepts are usually off for "Virtualize x2APIC mode" */ 6848 for (msr = 0x800; msr <= 0x8ff; msr++) { 6849 if (virt_x2apic_mode_config->disable_x2apic_msr_intercepts) { 6850 clear_bit(msr, msr_bitmap_page + 0x000); 6851 clear_bit(msr, msr_bitmap_page + 0x800); 6852 } else { 6853 set_bit(msr, msr_bitmap_page + 0x000); 6854 set_bit(msr, msr_bitmap_page + 0x800); 6855 } 6856 } 6857 6858 /* x2APIC mode can impact virtualization */ 6859 reset_apic(); 6860 if (!virt_x2apic_mode_config->disable_x2apic) 6861 enable_x2apic(); 6862 6863 return configure_apic_reg_virt_test( 6864 &virt_x2apic_mode_config->apic_reg_virt_config); 6865 } 6866 6867 static void virt_x2apic_mode_test(void) 6868 { 6869 u32 *virtual_apic_page; 6870 u8 *msr_bitmap_page; 6871 u64 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6872 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6873 int i; 6874 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6875 6876 if (!cpu_has_apicv()) { 6877 report_skip(__func__); 6878 return; 6879 } 6880 6881 /* 6882 * This is to exercise an issue in KVM's logic to merge L0's and L1's 6883 * MSR bitmaps. Previously, an L1 could get at L0's x2APIC MSRs by 6884 * writing the IA32_SPEC_CTRL MSR or the IA32_PRED_CMD MSRs. KVM would 6885 * then proceed to manipulate the MSR bitmaps, as if VMCS12 had the 6886 * "Virtualize x2APIC mod" control set, even when it didn't. 6887 */ 6888 if (has_spec_ctrl()) 6889 wrmsr(MSR_IA32_SPEC_CTRL, 1); 6890 6891 /* 6892 * Check that VMCS12 supports: 6893 * - "Virtual-APIC address", indicated by "use TPR shadow" 6894 * - "MSR-bitmap address", indicated by "use MSR bitmaps" 6895 */ 6896 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) { 6897 report_skip("VM-execution control \"use TPR shadow\" NOT supported.\n"); 6898 return; 6899 } else if (!(ctrl_cpu_rev[0].clr & CPU_MSR_BITMAP)) { 6900 report_skip("VM-execution control \"use MSR bitmaps\" NOT supported.\n"); 6901 return; 6902 } 6903 6904 test_set_guest(virt_x2apic_mode_guest); 6905 6906 virtual_apic_page = alloc_page(); 6907 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 6908 6909 msr_bitmap_page = alloc_page(); 6910 memset(msr_bitmap_page, 0xff, PAGE_SIZE); 6911 vmcs_write(MSR_BITMAP, virt_to_phys(msr_bitmap_page)); 6912 6913 for (i = 0; i < ARRAY_SIZE(virt_x2apic_mode_tests); i++) { 6914 struct virt_x2apic_mode_test_case *virt_x2apic_mode_test_case = 6915 &virt_x2apic_mode_tests[i]; 6916 struct virt_x2apic_mode_config *virt_x2apic_mode_config = 6917 &virt_x2apic_mode_test_case->virt_x2apic_mode_config; 6918 enum Config_type config_type; 6919 u32 reg; 6920 6921 printf("--- %s test ---\n", virt_x2apic_mode_test_case->name); 6922 config_type = 6923 configure_virt_x2apic_mode_test(virt_x2apic_mode_config, 6924 msr_bitmap_page); 6925 if (config_type == CONFIG_TYPE_UNSUPPORTED) { 6926 report_skip("Skip because of missing features.\n"); 6927 continue; 6928 } else if (config_type == CONFIG_TYPE_VMENTRY_FAILS_EARLY) { 6929 enter_guest_with_bad_controls(); 6930 continue; 6931 } 6932 6933 for (reg = 0; reg < PAGE_SIZE / sizeof(u32); reg += 0x10) { 6934 struct virt_x2apic_mode_expectation expectation; 6935 6936 virt_x2apic_mode_exit_expectation( 6937 reg, virt_x2apic_mode_config, &expectation); 6938 6939 test_x2apic_rd(reg, &expectation, virtual_apic_page); 6940 test_x2apic_wr(reg, &expectation, virtual_apic_page); 6941 } 6942 } 6943 6944 6945 /* Terminate the guest */ 6946 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6947 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6948 args->op = X2APIC_TERMINATE; 6949 enter_guest(); 6950 assert_exit_reason(VMX_VMCALL); 6951 } 6952 6953 static void test_ctl_reg(const char *cr_name, u64 cr, u64 fixed0, u64 fixed1) 6954 { 6955 u64 val; 6956 u64 cr_saved = vmcs_read(cr); 6957 int i; 6958 6959 val = fixed0 & fixed1; 6960 if (cr == HOST_CR4) 6961 vmcs_write(cr, val | X86_CR4_PAE); 6962 else 6963 vmcs_write(cr, val); 6964 report_prefix_pushf("%s %lx", cr_name, val); 6965 if (val == fixed0) 6966 test_vmx_vmlaunch(0); 6967 else 6968 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 6969 report_prefix_pop(); 6970 6971 for (i = 0; i < 64; i++) { 6972 6973 /* Set a bit when the corresponding bit in fixed1 is 0 */ 6974 if ((fixed1 & (1ull << i)) == 0) { 6975 if (cr == HOST_CR4 && ((1ull << i) & X86_CR4_SMEP || 6976 (1ull << i) & X86_CR4_SMAP)) 6977 continue; 6978 6979 vmcs_write(cr, cr_saved | (1ull << i)); 6980 report_prefix_pushf("%s %llx", cr_name, 6981 cr_saved | (1ull << i)); 6982 test_vmx_vmlaunch( 6983 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 6984 report_prefix_pop(); 6985 } 6986 6987 /* Unset a bit when the corresponding bit in fixed0 is 1 */ 6988 if (fixed0 & (1ull << i)) { 6989 vmcs_write(cr, cr_saved & ~(1ull << i)); 6990 report_prefix_pushf("%s %llx", cr_name, 6991 cr_saved & ~(1ull << i)); 6992 test_vmx_vmlaunch( 6993 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 6994 report_prefix_pop(); 6995 } 6996 } 6997 6998 vmcs_write(cr, cr_saved); 6999 } 7000 7001 /* 7002 * 1. The CR0 field must not set any bit to a value not supported in VMX 7003 * operation. 7004 * 2. The CR4 field must not set any bit to a value not supported in VMX 7005 * operation. 7006 * 3. On processors that support Intel 64 architecture, the CR3 field must 7007 * be such that bits 63:52 and bits in the range 51:32 beyond the 7008 * processor’s physical-address width must be 0. 7009 * 7010 * [Intel SDM] 7011 */ 7012 static void test_host_ctl_regs(void) 7013 { 7014 u64 fixed0, fixed1, cr3, cr3_saved; 7015 int i; 7016 7017 /* Test CR0 */ 7018 fixed0 = rdmsr(MSR_IA32_VMX_CR0_FIXED0); 7019 fixed1 = rdmsr(MSR_IA32_VMX_CR0_FIXED1); 7020 test_ctl_reg("HOST_CR0", HOST_CR0, fixed0, fixed1); 7021 7022 /* Test CR4 */ 7023 fixed0 = rdmsr(MSR_IA32_VMX_CR4_FIXED0); 7024 fixed1 = rdmsr(MSR_IA32_VMX_CR4_FIXED1) & 7025 ~(X86_CR4_SMEP | X86_CR4_SMAP); 7026 test_ctl_reg("HOST_CR4", HOST_CR4, fixed0, fixed1); 7027 7028 /* Test CR3 */ 7029 cr3_saved = vmcs_read(HOST_CR3); 7030 for (i = cpuid_maxphyaddr(); i < 64; i++) { 7031 cr3 = cr3_saved | (1ul << i); 7032 vmcs_write(HOST_CR3, cr3); 7033 report_prefix_pushf("HOST_CR3 %lx", cr3); 7034 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7035 report_prefix_pop(); 7036 } 7037 7038 vmcs_write(HOST_CR3, cr3_saved); 7039 } 7040 7041 static void test_efer_vmlaunch(u32 fld, bool ok) 7042 { 7043 if (fld == HOST_EFER) { 7044 if (ok) 7045 test_vmx_vmlaunch(0); 7046 else 7047 test_vmx_vmlaunch2(VMXERR_ENTRY_INVALID_CONTROL_FIELD, 7048 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7049 } else { 7050 test_guest_state("EFER test", !ok, GUEST_EFER, "GUEST_EFER"); 7051 } 7052 } 7053 7054 static void test_efer_one(u32 fld, const char * fld_name, u64 efer, 7055 u32 ctrl_fld, u64 ctrl, 7056 int i, const char *efer_bit_name) 7057 { 7058 bool ok; 7059 7060 ok = true; 7061 if (ctrl_fld == EXI_CONTROLS && (ctrl & EXI_LOAD_EFER)) { 7062 if (!!(efer & EFER_LMA) != !!(ctrl & EXI_HOST_64)) 7063 ok = false; 7064 if (!!(efer & EFER_LME) != !!(ctrl & EXI_HOST_64)) 7065 ok = false; 7066 } 7067 if (ctrl_fld == ENT_CONTROLS && (ctrl & ENT_LOAD_EFER)) { 7068 /* Check LMA too since CR0.PG is set. */ 7069 if (!!(efer & EFER_LMA) != !!(ctrl & ENT_GUEST_64)) 7070 ok = false; 7071 if (!!(efer & EFER_LME) != !!(ctrl & ENT_GUEST_64)) 7072 ok = false; 7073 } 7074 7075 /* 7076 * Skip the test if it would enter the guest in 32-bit mode. 7077 * Perhaps write the test in assembly and make sure it 7078 * can be run in either mode? 7079 */ 7080 if (fld == GUEST_EFER && ok && !(ctrl & ENT_GUEST_64)) 7081 return; 7082 7083 vmcs_write(ctrl_fld, ctrl); 7084 vmcs_write(fld, efer); 7085 report_prefix_pushf("%s %s bit turned %s, controls %s", 7086 fld_name, efer_bit_name, 7087 (i & 1) ? "on" : "off", 7088 (i & 2) ? "on" : "off"); 7089 7090 test_efer_vmlaunch(fld, ok); 7091 report_prefix_pop(); 7092 } 7093 7094 static void test_efer_bit(u32 fld, const char * fld_name, 7095 u32 ctrl_fld, u64 ctrl_bit, u64 efer_bit, 7096 const char *efer_bit_name) 7097 { 7098 u64 efer_saved = vmcs_read(fld); 7099 u32 ctrl_saved = vmcs_read(ctrl_fld); 7100 int i; 7101 7102 for (i = 0; i < 4; i++) { 7103 u64 efer = efer_saved & ~efer_bit; 7104 u64 ctrl = ctrl_saved & ~ctrl_bit; 7105 7106 if (i & 1) 7107 efer |= efer_bit; 7108 if (i & 2) 7109 ctrl |= ctrl_bit; 7110 7111 test_efer_one(fld, fld_name, efer, ctrl_fld, ctrl, 7112 i, efer_bit_name); 7113 } 7114 7115 vmcs_write(ctrl_fld, ctrl_saved); 7116 vmcs_write(fld, efer_saved); 7117 } 7118 7119 static void test_efer(u32 fld, const char * fld_name, u32 ctrl_fld, 7120 u64 ctrl_bit1, u64 ctrl_bit2) 7121 { 7122 u64 efer_saved = vmcs_read(fld); 7123 u32 ctrl_saved = vmcs_read(ctrl_fld); 7124 u64 efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 7125 u64 i; 7126 u64 efer; 7127 7128 if (cpu_has_efer_nx()) 7129 efer_reserved_bits &= ~EFER_NX; 7130 7131 if (!ctrl_bit1) { 7132 printf("\"Load-IA32-EFER\" exit control not supported\n"); 7133 goto test_entry_exit_mode; 7134 } 7135 7136 report_prefix_pushf("%s %lx", fld_name, efer_saved); 7137 test_efer_vmlaunch(fld, true); 7138 report_prefix_pop(); 7139 7140 /* 7141 * Check reserved bits 7142 */ 7143 vmcs_write(ctrl_fld, ctrl_saved & ~ctrl_bit1); 7144 for (i = 0; i < 64; i++) { 7145 if ((1ull << i) & efer_reserved_bits) { 7146 efer = efer_saved | (1ull << i); 7147 vmcs_write(fld, efer); 7148 report_prefix_pushf("%s %lx", fld_name, efer); 7149 test_efer_vmlaunch(fld, true); 7150 report_prefix_pop(); 7151 } 7152 } 7153 7154 vmcs_write(ctrl_fld, ctrl_saved | ctrl_bit1); 7155 for (i = 0; i < 64; i++) { 7156 if ((1ull << i) & efer_reserved_bits) { 7157 efer = efer_saved | (1ull << i); 7158 vmcs_write(fld, efer); 7159 report_prefix_pushf("%s %lx", fld_name, efer); 7160 test_efer_vmlaunch(fld, false); 7161 report_prefix_pop(); 7162 } 7163 } 7164 7165 vmcs_write(ctrl_fld, ctrl_saved); 7166 vmcs_write(fld, efer_saved); 7167 7168 /* 7169 * Check LMA and LME bits 7170 */ 7171 test_efer_bit(fld, fld_name, 7172 ctrl_fld, ctrl_bit1, 7173 EFER_LMA, 7174 "EFER_LMA"); 7175 test_efer_bit(fld, fld_name, 7176 ctrl_fld, ctrl_bit1, 7177 EFER_LME, 7178 "EFER_LME"); 7179 7180 test_entry_exit_mode: 7181 test_efer_bit(fld, fld_name, 7182 ctrl_fld, ctrl_bit2, 7183 EFER_LMA, 7184 "EFER_LMA"); 7185 test_efer_bit(fld, fld_name, 7186 ctrl_fld, ctrl_bit2, 7187 EFER_LME, 7188 "EFER_LME"); 7189 } 7190 7191 /* 7192 * If the 'load IA32_EFER' VM-exit control is 1, bits reserved in the 7193 * IA32_EFER MSR must be 0 in the field for that register. In addition, 7194 * the values of the LMA and LME bits in the field must each be that of 7195 * the 'host address-space size' VM-exit control. 7196 * 7197 * [Intel SDM] 7198 */ 7199 static void test_host_efer(void) 7200 { 7201 test_efer(HOST_EFER, "HOST_EFER", EXI_CONTROLS, 7202 ctrl_exit_rev.clr & EXI_LOAD_EFER, 7203 EXI_HOST_64); 7204 } 7205 7206 /* 7207 * If the 'load IA32_EFER' VM-enter control is 1, bits reserved in the 7208 * IA32_EFER MSR must be 0 in the field for that register. In addition, 7209 * the values of the LMA and LME bits in the field must each be that of 7210 * the 'IA32e-mode guest' VM-exit control. 7211 */ 7212 static void test_guest_efer(void) 7213 { 7214 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) { 7215 printf("\"Load-IA32-EFER\" entry control not supported\n"); 7216 return; 7217 } 7218 7219 vmcs_write(GUEST_EFER, rdmsr(MSR_EFER)); 7220 test_efer(GUEST_EFER, "GUEST_EFER", ENT_CONTROLS, 7221 ctrl_enter_rev.clr & ENT_LOAD_EFER, 7222 ENT_GUEST_64); 7223 } 7224 7225 /* 7226 * PAT values higher than 8 are uninteresting since they're likely lumped 7227 * in with "8". We only test values above 8 one bit at a time, 7228 * in order to reduce the number of VM-Entries and keep the runtime reasonable. 7229 */ 7230 #define PAT_VAL_LIMIT 8 7231 7232 static void test_pat(u32 field, const char * field_name, u32 ctrl_field, 7233 u64 ctrl_bit) 7234 { 7235 u32 ctrl_saved = vmcs_read(ctrl_field); 7236 u64 pat_saved = vmcs_read(field); 7237 u64 i, val; 7238 u32 j; 7239 int error; 7240 7241 vmcs_clear_bits(ctrl_field, ctrl_bit); 7242 7243 for (i = 0; i < 256; i = (i < PAT_VAL_LIMIT) ? i + 1 : i * 2) { 7244 /* Test PAT0..PAT7 fields */ 7245 for (j = 0; j < (i ? 8 : 1); j++) { 7246 val = i << j * 8; 7247 vmcs_write(field, val); 7248 if (field == HOST_PAT) { 7249 report_prefix_pushf("%s %lx", field_name, val); 7250 test_vmx_vmlaunch(0); 7251 report_prefix_pop(); 7252 7253 } else { // GUEST_PAT 7254 test_guest_state("ENT_LOAD_PAT enabled", false, 7255 val, "GUEST_PAT"); 7256 } 7257 } 7258 } 7259 7260 vmcs_set_bits(ctrl_field, ctrl_bit); 7261 for (i = 0; i < 256; i = (i < PAT_VAL_LIMIT) ? i + 1 : i * 2) { 7262 /* Test PAT0..PAT7 fields */ 7263 for (j = 0; j < (i ? 8 : 1); j++) { 7264 val = i << j * 8; 7265 vmcs_write(field, val); 7266 7267 if (field == HOST_PAT) { 7268 report_prefix_pushf("%s %lx", field_name, val); 7269 if (i == 0x2 || i == 0x3 || i >= 0x8) 7270 error = 7271 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD; 7272 else 7273 error = 0; 7274 7275 test_vmx_vmlaunch(error); 7276 report_prefix_pop(); 7277 7278 } else { // GUEST_PAT 7279 error = (i == 0x2 || i == 0x3 || i >= 0x8); 7280 test_guest_state("ENT_LOAD_PAT enabled", !!error, 7281 val, "GUEST_PAT"); 7282 } 7283 7284 } 7285 } 7286 7287 vmcs_write(ctrl_field, ctrl_saved); 7288 vmcs_write(field, pat_saved); 7289 } 7290 7291 /* 7292 * If the "load IA32_PAT" VM-exit control is 1, the value of the field 7293 * for the IA32_PAT MSR must be one that could be written by WRMSR 7294 * without fault at CPL 0. Specifically, each of the 8 bytes in the 7295 * field must have one of the values 0 (UC), 1 (WC), 4 (WT), 5 (WP), 7296 * 6 (WB), or 7 (UC-). 7297 * 7298 * [Intel SDM] 7299 */ 7300 static void test_load_host_pat(void) 7301 { 7302 /* 7303 * "load IA32_PAT" VM-exit control 7304 */ 7305 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) { 7306 printf("\"Load-IA32-PAT\" exit control not supported\n"); 7307 return; 7308 } 7309 7310 test_pat(HOST_PAT, "HOST_PAT", EXI_CONTROLS, EXI_LOAD_PAT); 7311 } 7312 7313 union cpuidA_eax { 7314 struct { 7315 unsigned int version_id:8; 7316 unsigned int num_counters_gp:8; 7317 unsigned int bit_width:8; 7318 unsigned int mask_length:8; 7319 } split; 7320 unsigned int full; 7321 }; 7322 7323 union cpuidA_edx { 7324 struct { 7325 unsigned int num_counters_fixed:5; 7326 unsigned int bit_width_fixed:8; 7327 unsigned int reserved:9; 7328 } split; 7329 unsigned int full; 7330 }; 7331 7332 static bool valid_pgc(u64 val) 7333 { 7334 struct cpuid id; 7335 union cpuidA_eax eax; 7336 union cpuidA_edx edx; 7337 u64 mask; 7338 7339 id = cpuid(0xA); 7340 eax.full = id.a; 7341 edx.full = id.d; 7342 mask = ~(((1ull << eax.split.num_counters_gp) - 1) | 7343 (((1ull << edx.split.num_counters_fixed) - 1) << 32)); 7344 7345 return !(val & mask); 7346 } 7347 7348 static void test_pgc_vmlaunch(u32 xerror, u32 xreason, bool xfail, bool host) 7349 { 7350 u32 inst_err; 7351 u64 obs; 7352 bool success; 7353 struct vmx_state_area_test_data *data = &vmx_state_area_test_data; 7354 7355 if (host) { 7356 success = vmlaunch_succeeds(); 7357 obs = rdmsr(data->msr); 7358 if (!success) { 7359 inst_err = vmcs_read(VMX_INST_ERROR); 7360 report(xerror == inst_err, "vmlaunch failed, " 7361 "VMX Inst Error is %d (expected %d)", 7362 inst_err, xerror); 7363 } else { 7364 report(!data->enabled || data->exp == obs, 7365 "Host state is 0x%lx (expected 0x%lx)", 7366 obs, data->exp); 7367 report(success != xfail, "vmlaunch succeeded"); 7368 } 7369 } else { 7370 test_guest_state("load GUEST_PERF_GLOBAL_CTRL", xfail, 7371 GUEST_PERF_GLOBAL_CTRL, 7372 "GUEST_PERF_GLOBAL_CTRL"); 7373 } 7374 } 7375 7376 /* 7377 * test_load_perf_global_ctrl is a generic function for testing the 7378 * "load IA32_PERF_GLOBAL_CTRL" VM-{Entry,Exit} controls. This test function 7379 * tests the provided ctrl_val when disabled and enabled. 7380 * 7381 * @nr: VMCS field number corresponding to the host/guest state field 7382 * @name: Name of the above VMCS field for printing in test report 7383 * @ctrl_nr: VMCS field number corresponding to the VM-{Entry,Exit} control 7384 * @ctrl_val: Bit to set on the ctrl_field 7385 */ 7386 static void test_perf_global_ctrl(u32 nr, const char *name, u32 ctrl_nr, 7387 const char *ctrl_name, u64 ctrl_val) 7388 { 7389 u64 ctrl_saved = vmcs_read(ctrl_nr); 7390 u64 pgc_saved = vmcs_read(nr); 7391 u64 i, val; 7392 bool host = nr == HOST_PERF_GLOBAL_CTRL; 7393 struct vmx_state_area_test_data *data = &vmx_state_area_test_data; 7394 7395 data->msr = MSR_CORE_PERF_GLOBAL_CTRL; 7396 msr_bmp_init(); 7397 vmcs_write(ctrl_nr, ctrl_saved & ~ctrl_val); 7398 data->enabled = false; 7399 report_prefix_pushf("\"load IA32_PERF_GLOBAL_CTRL\"=0 on %s", 7400 ctrl_name); 7401 7402 for (i = 0; i < 64; i++) { 7403 val = 1ull << i; 7404 vmcs_write(nr, val); 7405 report_prefix_pushf("%s = 0x%lx", name, val); 7406 test_pgc_vmlaunch(0, VMX_VMCALL, false, host); 7407 report_prefix_pop(); 7408 } 7409 report_prefix_pop(); 7410 7411 vmcs_write(ctrl_nr, ctrl_saved | ctrl_val); 7412 data->enabled = true; 7413 report_prefix_pushf("\"load IA32_PERF_GLOBAL_CTRL\"=1 on %s", 7414 ctrl_name); 7415 for (i = 0; i < 64; i++) { 7416 val = 1ull << i; 7417 data->exp = val; 7418 vmcs_write(nr, val); 7419 report_prefix_pushf("%s = 0x%lx", name, val); 7420 if (valid_pgc(val)) { 7421 test_pgc_vmlaunch(0, VMX_VMCALL, false, host); 7422 } else { 7423 if (host) 7424 test_pgc_vmlaunch( 7425 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, 7426 0, 7427 true, 7428 host); 7429 else 7430 test_pgc_vmlaunch( 7431 0, 7432 VMX_ENTRY_FAILURE | VMX_FAIL_STATE, 7433 true, 7434 host); 7435 } 7436 report_prefix_pop(); 7437 } 7438 7439 data->enabled = false; 7440 report_prefix_pop(); 7441 vmcs_write(ctrl_nr, ctrl_saved); 7442 vmcs_write(nr, pgc_saved); 7443 } 7444 7445 static void test_load_host_perf_global_ctrl(void) 7446 { 7447 if (!(ctrl_exit_rev.clr & EXI_LOAD_PERF)) { 7448 printf("\"load IA32_PERF_GLOBAL_CTRL\" exit control not supported\n"); 7449 return; 7450 } 7451 7452 test_perf_global_ctrl(HOST_PERF_GLOBAL_CTRL, "HOST_PERF_GLOBAL_CTRL", 7453 EXI_CONTROLS, "EXI_CONTROLS", EXI_LOAD_PERF); 7454 } 7455 7456 7457 static void test_load_guest_perf_global_ctrl(void) 7458 { 7459 if (!(ctrl_enter_rev.clr & ENT_LOAD_PERF)) { 7460 printf("\"load IA32_PERF_GLOBAL_CTRL\" entry control not supported\n"); 7461 return; 7462 } 7463 7464 test_perf_global_ctrl(GUEST_PERF_GLOBAL_CTRL, "GUEST_PERF_GLOBAL_CTRL", 7465 ENT_CONTROLS, "ENT_CONTROLS", ENT_LOAD_PERF); 7466 } 7467 7468 7469 /* 7470 * test_vmcs_field - test a value for the given VMCS field 7471 * @field: VMCS field 7472 * @field_name: string name of VMCS field 7473 * @bit_start: starting bit 7474 * @bit_end: ending bit 7475 * @val: value that the bit range must or must not contain 7476 * @valid_val: whether value given in 'val' must be valid or not 7477 * @error: expected VMCS error when vmentry fails for an invalid value 7478 */ 7479 static void test_vmcs_field(u64 field, const char *field_name, u32 bit_start, 7480 u32 bit_end, u64 val, bool valid_val, u32 error) 7481 { 7482 u64 field_saved = vmcs_read(field); 7483 u32 i; 7484 u64 tmp; 7485 u32 bit_on; 7486 u64 mask = ~0ull; 7487 7488 mask = (mask >> bit_end) << bit_end; 7489 mask = mask | ((1 << bit_start) - 1); 7490 tmp = (field_saved & mask) | (val << bit_start); 7491 7492 vmcs_write(field, tmp); 7493 report_prefix_pushf("%s %lx", field_name, tmp); 7494 if (valid_val) 7495 test_vmx_vmlaunch(0); 7496 else 7497 test_vmx_vmlaunch(error); 7498 report_prefix_pop(); 7499 7500 for (i = bit_start; i <= bit_end; i = i + 2) { 7501 bit_on = ((1ull < i) & (val << bit_start)) ? 0 : 1; 7502 if (bit_on) 7503 tmp = field_saved | (1ull << i); 7504 else 7505 tmp = field_saved & ~(1ull << i); 7506 vmcs_write(field, tmp); 7507 report_prefix_pushf("%s %lx", field_name, tmp); 7508 if (valid_val) 7509 test_vmx_vmlaunch(error); 7510 else 7511 test_vmx_vmlaunch(0); 7512 report_prefix_pop(); 7513 } 7514 7515 vmcs_write(field, field_saved); 7516 } 7517 7518 static void test_canonical(u64 field, const char * field_name, bool host) 7519 { 7520 u64 addr_saved = vmcs_read(field); 7521 7522 /* 7523 * Use the existing value if possible. Writing a random canonical 7524 * value is not an option as doing so would corrupt the field being 7525 * tested and likely hose the test. 7526 */ 7527 if (is_canonical(addr_saved)) { 7528 if (host) { 7529 report_prefix_pushf("%s %lx", field_name, addr_saved); 7530 test_vmx_vmlaunch(0); 7531 report_prefix_pop(); 7532 } else { 7533 test_guest_state("Test canonical address", false, 7534 addr_saved, field_name); 7535 } 7536 } 7537 7538 vmcs_write(field, NONCANONICAL); 7539 7540 if (host) { 7541 report_prefix_pushf("%s %llx", field_name, NONCANONICAL); 7542 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7543 report_prefix_pop(); 7544 } else { 7545 test_guest_state("Test non-canonical address", true, 7546 NONCANONICAL, field_name); 7547 } 7548 7549 vmcs_write(field, addr_saved); 7550 } 7551 7552 #define TEST_RPL_TI_FLAGS(reg, name) \ 7553 test_vmcs_field(reg, name, 0, 2, 0x0, true, \ 7554 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7555 7556 #define TEST_CS_TR_FLAGS(reg, name) \ 7557 test_vmcs_field(reg, name, 3, 15, 0x0000, false, \ 7558 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7559 7560 /* 7561 * 1. In the selector field for each of CS, SS, DS, ES, FS, GS and TR, the 7562 * RPL (bits 1:0) and the TI flag (bit 2) must be 0. 7563 * 2. The selector fields for CS and TR cannot be 0000H. 7564 * 3. The selector field for SS cannot be 0000H if the "host address-space 7565 * size" VM-exit control is 0. 7566 * 4. On processors that support Intel 64 architecture, the base-address 7567 * fields for FS, GS and TR must contain canonical addresses. 7568 */ 7569 static void test_host_segment_regs(void) 7570 { 7571 u16 selector_saved; 7572 7573 /* 7574 * Test RPL and TI flags 7575 */ 7576 TEST_RPL_TI_FLAGS(HOST_SEL_CS, "HOST_SEL_CS"); 7577 TEST_RPL_TI_FLAGS(HOST_SEL_SS, "HOST_SEL_SS"); 7578 TEST_RPL_TI_FLAGS(HOST_SEL_DS, "HOST_SEL_DS"); 7579 TEST_RPL_TI_FLAGS(HOST_SEL_ES, "HOST_SEL_ES"); 7580 TEST_RPL_TI_FLAGS(HOST_SEL_FS, "HOST_SEL_FS"); 7581 TEST_RPL_TI_FLAGS(HOST_SEL_GS, "HOST_SEL_GS"); 7582 TEST_RPL_TI_FLAGS(HOST_SEL_TR, "HOST_SEL_TR"); 7583 7584 /* 7585 * Test that CS and TR fields can not be 0x0000 7586 */ 7587 TEST_CS_TR_FLAGS(HOST_SEL_CS, "HOST_SEL_CS"); 7588 TEST_CS_TR_FLAGS(HOST_SEL_TR, "HOST_SEL_TR"); 7589 7590 /* 7591 * SS field can not be 0x0000 if "host address-space size" VM-exit 7592 * control is 0 7593 */ 7594 selector_saved = vmcs_read(HOST_SEL_SS); 7595 vmcs_write(HOST_SEL_SS, 0); 7596 report_prefix_pushf("HOST_SEL_SS 0"); 7597 if (vmcs_read(EXI_CONTROLS) & EXI_HOST_64) { 7598 test_vmx_vmlaunch(0); 7599 } else { 7600 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7601 } 7602 report_prefix_pop(); 7603 7604 vmcs_write(HOST_SEL_SS, selector_saved); 7605 7606 #ifdef __x86_64__ 7607 /* 7608 * Base address for FS, GS and TR must be canonical 7609 */ 7610 test_canonical(HOST_BASE_FS, "HOST_BASE_FS", true); 7611 test_canonical(HOST_BASE_GS, "HOST_BASE_GS", true); 7612 test_canonical(HOST_BASE_TR, "HOST_BASE_TR", true); 7613 #endif 7614 } 7615 7616 /* 7617 * On processors that support Intel 64 architecture, the base-address 7618 * fields for GDTR and IDTR must contain canonical addresses. 7619 */ 7620 static void test_host_desc_tables(void) 7621 { 7622 #ifdef __x86_64__ 7623 test_canonical(HOST_BASE_GDTR, "HOST_BASE_GDTR", true); 7624 test_canonical(HOST_BASE_IDTR, "HOST_BASE_IDTR", true); 7625 #endif 7626 } 7627 7628 /* 7629 * If the "host address-space size" VM-exit control is 0, the following must 7630 * hold: 7631 * - The "IA-32e mode guest" VM-entry control is 0. 7632 * - Bit 17 of the CR4 field (corresponding to CR4.PCIDE) is 0. 7633 * - Bits 63:32 in the RIP field are 0. 7634 * 7635 * If the "host address-space size" VM-exit control is 1, the following must 7636 * hold: 7637 * - Bit 5 of the CR4 field (corresponding to CR4.PAE) is 1. 7638 * - The RIP field contains a canonical address. 7639 * 7640 */ 7641 static void test_host_addr_size(void) 7642 { 7643 u64 cr4_saved = vmcs_read(HOST_CR4); 7644 u64 rip_saved = vmcs_read(HOST_RIP); 7645 u64 entry_ctrl_saved = vmcs_read(ENT_CONTROLS); 7646 int i; 7647 u64 tmp; 7648 7649 if (vmcs_read(EXI_CONTROLS) & EXI_HOST_64) { 7650 vmcs_write(ENT_CONTROLS, entry_ctrl_saved | ENT_GUEST_64); 7651 report_prefix_pushf("\"IA-32e mode guest\" enabled"); 7652 test_vmx_vmlaunch(0); 7653 report_prefix_pop(); 7654 7655 vmcs_write(HOST_CR4, cr4_saved | X86_CR4_PCIDE); 7656 report_prefix_pushf("\"CR4.PCIDE\" set"); 7657 test_vmx_vmlaunch(0); 7658 report_prefix_pop(); 7659 7660 for (i = 32; i <= 63; i = i + 4) { 7661 tmp = rip_saved | 1ull << i; 7662 vmcs_write(HOST_RIP, tmp); 7663 report_prefix_pushf("HOST_RIP %lx", tmp); 7664 test_vmx_vmlaunch(0); 7665 report_prefix_pop(); 7666 } 7667 7668 if (cr4_saved & X86_CR4_PAE) { 7669 vmcs_write(HOST_CR4, cr4_saved & ~X86_CR4_PAE); 7670 report_prefix_pushf("\"CR4.PAE\" unset"); 7671 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7672 } else { 7673 report_prefix_pushf("\"CR4.PAE\" set"); 7674 test_vmx_vmlaunch(0); 7675 } 7676 report_prefix_pop(); 7677 7678 vmcs_write(HOST_RIP, NONCANONICAL); 7679 report_prefix_pushf("HOST_RIP %llx", NONCANONICAL); 7680 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7681 report_prefix_pop(); 7682 7683 vmcs_write(ENT_CONTROLS, entry_ctrl_saved | ENT_GUEST_64); 7684 vmcs_write(HOST_RIP, rip_saved); 7685 vmcs_write(HOST_CR4, cr4_saved); 7686 } 7687 } 7688 7689 /* 7690 * Check that the virtual CPU checks the VMX Host State Area as 7691 * documented in the Intel SDM. 7692 */ 7693 static void vmx_host_state_area_test(void) 7694 { 7695 /* 7696 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 7697 * fail due to invalid guest state, should we make it that 7698 * far. 7699 */ 7700 vmcs_write(GUEST_RFLAGS, 0); 7701 7702 test_host_ctl_regs(); 7703 7704 test_canonical(HOST_SYSENTER_ESP, "HOST_SYSENTER_ESP", true); 7705 test_canonical(HOST_SYSENTER_EIP, "HOST_SYSENTER_EIP", true); 7706 7707 test_host_efer(); 7708 test_load_host_pat(); 7709 test_host_segment_regs(); 7710 test_host_desc_tables(); 7711 test_host_addr_size(); 7712 test_load_host_perf_global_ctrl(); 7713 } 7714 7715 /* 7716 * If the "load debug controls" VM-entry control is 1, bits 63:32 in 7717 * the DR7 field must be 0. 7718 * 7719 * [Intel SDM] 7720 */ 7721 static void test_guest_dr7(void) 7722 { 7723 u32 ent_saved = vmcs_read(ENT_CONTROLS); 7724 u64 dr7_saved = vmcs_read(GUEST_DR7); 7725 u64 val; 7726 int i; 7727 7728 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS) { 7729 vmcs_clear_bits(ENT_CONTROLS, ENT_LOAD_DBGCTLS); 7730 for (i = 0; i < 64; i++) { 7731 val = 1ull << i; 7732 vmcs_write(GUEST_DR7, val); 7733 test_guest_state("ENT_LOAD_DBGCTLS disabled", false, 7734 val, "GUEST_DR7"); 7735 } 7736 } 7737 if (ctrl_enter_rev.clr & ENT_LOAD_DBGCTLS) { 7738 vmcs_set_bits(ENT_CONTROLS, ENT_LOAD_DBGCTLS); 7739 for (i = 0; i < 64; i++) { 7740 val = 1ull << i; 7741 vmcs_write(GUEST_DR7, val); 7742 test_guest_state("ENT_LOAD_DBGCTLS enabled", i >= 32, 7743 val, "GUEST_DR7"); 7744 } 7745 } 7746 vmcs_write(GUEST_DR7, dr7_saved); 7747 vmcs_write(ENT_CONTROLS, ent_saved); 7748 } 7749 7750 /* 7751 * If the "load IA32_PAT" VM-entry control is 1, the value of the field 7752 * for the IA32_PAT MSR must be one that could be written by WRMSR 7753 * without fault at CPL 0. Specifically, each of the 8 bytes in the 7754 * field must have one of the values 0 (UC), 1 (WC), 4 (WT), 5 (WP), 7755 * 6 (WB), or 7 (UC-). 7756 * 7757 * [Intel SDM] 7758 */ 7759 static void test_load_guest_pat(void) 7760 { 7761 /* 7762 * "load IA32_PAT" VM-entry control 7763 */ 7764 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 7765 printf("\"Load-IA32-PAT\" entry control not supported\n"); 7766 return; 7767 } 7768 7769 test_pat(GUEST_PAT, "GUEST_PAT", ENT_CONTROLS, ENT_LOAD_PAT); 7770 } 7771 7772 #define MSR_IA32_BNDCFGS_RSVD_MASK 0x00000ffc 7773 7774 /* 7775 * If the “load IA32_BNDCFGS†VM-entry control is 1, the following 7776 * checks are performed on the field for the IA32_BNDCFGS MSR: 7777 * 7778 * — Bits reserved in the IA32_BNDCFGS MSR must be 0. 7779 * — The linear address in bits 63:12 must be canonical. 7780 * 7781 * [Intel SDM] 7782 */ 7783 static void test_load_guest_bndcfgs(void) 7784 { 7785 u64 bndcfgs_saved = vmcs_read(GUEST_BNDCFGS); 7786 u64 bndcfgs; 7787 7788 if (!(ctrl_enter_rev.clr & ENT_LOAD_BNDCFGS)) { 7789 printf("\"Load-IA32-BNDCFGS\" entry control not supported\n"); 7790 return; 7791 } 7792 7793 vmcs_clear_bits(ENT_CONTROLS, ENT_LOAD_BNDCFGS); 7794 7795 vmcs_write(GUEST_BNDCFGS, NONCANONICAL); 7796 test_guest_state("ENT_LOAD_BNDCFGS disabled", false, 7797 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7798 bndcfgs = bndcfgs_saved | MSR_IA32_BNDCFGS_RSVD_MASK; 7799 vmcs_write(GUEST_BNDCFGS, bndcfgs); 7800 test_guest_state("ENT_LOAD_BNDCFGS disabled", false, 7801 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7802 7803 vmcs_set_bits(ENT_CONTROLS, ENT_LOAD_BNDCFGS); 7804 7805 vmcs_write(GUEST_BNDCFGS, NONCANONICAL); 7806 test_guest_state("ENT_LOAD_BNDCFGS enabled", true, 7807 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7808 bndcfgs = bndcfgs_saved | MSR_IA32_BNDCFGS_RSVD_MASK; 7809 vmcs_write(GUEST_BNDCFGS, bndcfgs); 7810 test_guest_state("ENT_LOAD_BNDCFGS enabled", true, 7811 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7812 7813 vmcs_write(GUEST_BNDCFGS, bndcfgs_saved); 7814 } 7815 7816 /* 7817 * Check that the virtual CPU checks the VMX Guest State Area as 7818 * documented in the Intel SDM. 7819 */ 7820 static void vmx_guest_state_area_test(void) 7821 { 7822 vmx_set_test_stage(1); 7823 test_set_guest(guest_state_test_main); 7824 7825 /* 7826 * The IA32_SYSENTER_ESP field and the IA32_SYSENTER_EIP field 7827 * must each contain a canonical address. 7828 */ 7829 test_canonical(GUEST_SYSENTER_ESP, "GUEST_SYSENTER_ESP", false); 7830 test_canonical(GUEST_SYSENTER_EIP, "GUEST_SYSENTER_EIP", false); 7831 7832 test_guest_dr7(); 7833 test_load_guest_pat(); 7834 test_guest_efer(); 7835 test_load_guest_perf_global_ctrl(); 7836 test_load_guest_bndcfgs(); 7837 7838 /* 7839 * Let the guest finish execution 7840 */ 7841 vmx_set_test_stage(2); 7842 enter_guest(); 7843 } 7844 7845 static bool valid_vmcs_for_vmentry(void) 7846 { 7847 struct vmcs *current_vmcs = NULL; 7848 7849 if (vmcs_save(¤t_vmcs)) 7850 return false; 7851 7852 return current_vmcs && !current_vmcs->hdr.shadow_vmcs; 7853 } 7854 7855 static void try_vmentry_in_movss_shadow(void) 7856 { 7857 u32 vm_inst_err; 7858 u32 flags; 7859 bool early_failure = false; 7860 u32 expected_flags = X86_EFLAGS_FIXED; 7861 bool valid_vmcs = valid_vmcs_for_vmentry(); 7862 7863 expected_flags |= valid_vmcs ? X86_EFLAGS_ZF : X86_EFLAGS_CF; 7864 7865 /* 7866 * Indirectly set VM_INST_ERR to 12 ("VMREAD/VMWRITE from/to 7867 * unsupported VMCS component"). 7868 */ 7869 vmcs_write(~0u, 0); 7870 7871 __asm__ __volatile__ ("mov %[host_rsp], %%edx;" 7872 "vmwrite %%rsp, %%rdx;" 7873 "mov 0f, %%rax;" 7874 "mov %[host_rip], %%edx;" 7875 "vmwrite %%rax, %%rdx;" 7876 "mov $-1, %%ah;" 7877 "sahf;" 7878 "mov %%ss, %%ax;" 7879 "mov %%ax, %%ss;" 7880 "vmlaunch;" 7881 "mov $1, %[early_failure];" 7882 "0: lahf;" 7883 "movzbl %%ah, %[flags]" 7884 : [early_failure] "+r" (early_failure), 7885 [flags] "=&a" (flags) 7886 : [host_rsp] "i" (HOST_RSP), 7887 [host_rip] "i" (HOST_RIP) 7888 : "rdx", "cc", "memory"); 7889 vm_inst_err = vmcs_read(VMX_INST_ERROR); 7890 7891 report(early_failure, "Early VM-entry failure"); 7892 report(flags == expected_flags, "RFLAGS[8:0] is %x (actual %x)", 7893 expected_flags, flags); 7894 if (valid_vmcs) 7895 report(vm_inst_err == VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, 7896 "VM-instruction error is %d (actual %d)", 7897 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, vm_inst_err); 7898 } 7899 7900 static void vmentry_movss_shadow_test(void) 7901 { 7902 struct vmcs *orig_vmcs; 7903 7904 TEST_ASSERT(!vmcs_save(&orig_vmcs)); 7905 7906 /* 7907 * Set the launched flag on the current VMCS to verify the correct 7908 * error priority, below. 7909 */ 7910 test_set_guest(v2_null_test_guest); 7911 enter_guest(); 7912 7913 /* 7914 * With bit 1 of the guest's RFLAGS clear, VM-entry should 7915 * fail due to invalid guest state (if we make it that far). 7916 */ 7917 vmcs_write(GUEST_RFLAGS, 0); 7918 7919 /* 7920 * "VM entry with events blocked by MOV SS" takes precedence over 7921 * "VMLAUNCH with non-clear VMCS." 7922 */ 7923 report_prefix_push("valid current-VMCS"); 7924 try_vmentry_in_movss_shadow(); 7925 report_prefix_pop(); 7926 7927 /* 7928 * VMfailInvalid takes precedence over "VM entry with events 7929 * blocked by MOV SS." 7930 */ 7931 TEST_ASSERT(!vmcs_clear(orig_vmcs)); 7932 report_prefix_push("no current-VMCS"); 7933 try_vmentry_in_movss_shadow(); 7934 report_prefix_pop(); 7935 7936 TEST_ASSERT(!make_vmcs_current(orig_vmcs)); 7937 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 7938 } 7939 7940 static void vmx_cr_load_test(void) 7941 { 7942 unsigned long cr3, cr4, orig_cr3, orig_cr4; 7943 7944 orig_cr4 = read_cr4(); 7945 orig_cr3 = read_cr3(); 7946 7947 if (!this_cpu_has(X86_FEATURE_PCID)) { 7948 report_skip("PCID not detected"); 7949 return; 7950 } 7951 if (!this_cpu_has(X86_FEATURE_MCE)) { 7952 report_skip("MCE not detected"); 7953 return; 7954 } 7955 7956 TEST_ASSERT(!(orig_cr3 & X86_CR3_PCID_MASK)); 7957 7958 /* Enable PCID for L1. */ 7959 cr4 = orig_cr4 | X86_CR4_PCIDE; 7960 cr3 = orig_cr3 | 0x1; 7961 TEST_ASSERT(!write_cr4_checking(cr4)); 7962 write_cr3(cr3); 7963 7964 test_set_guest(v2_null_test_guest); 7965 vmcs_write(HOST_CR4, cr4); 7966 vmcs_write(HOST_CR3, cr3); 7967 enter_guest(); 7968 7969 /* 7970 * No exception is expected. 7971 * 7972 * NB. KVM loads the last guest write to CR4 into CR4 read 7973 * shadow. In order to trigger an exit to KVM, we can toggle a 7974 * bit that is owned by KVM. We use CR4.MCE, which shall 7975 * have no side effect because normally no guest MCE (e.g., as the 7976 * result of bad memory) would happen during this test. 7977 */ 7978 TEST_ASSERT(!write_cr4_checking(cr4 ^ X86_CR4_MCE)); 7979 7980 /* Cleanup L1 state. */ 7981 write_cr3(orig_cr3); 7982 TEST_ASSERT(!write_cr4_checking(orig_cr4)); 7983 } 7984 7985 static void vmx_nm_test_guest(void) 7986 { 7987 write_cr0(read_cr0() | X86_CR0_TS); 7988 asm volatile("fnop"); 7989 } 7990 7991 static void check_nm_exit(const char *test) 7992 { 7993 u32 reason = vmcs_read(EXI_REASON); 7994 u32 intr_info = vmcs_read(EXI_INTR_INFO); 7995 const u32 expected = INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 7996 NM_VECTOR; 7997 7998 report(reason == VMX_EXC_NMI && intr_info == expected, "%s", test); 7999 } 8000 8001 /* 8002 * This test checks that: 8003 * 8004 * (a) If L2 launches with CR0.TS clear, but later sets CR0.TS, then 8005 * a subsequent #NM VM-exit is reflected to L1. 8006 * 8007 * (b) If L2 launches with CR0.TS clear and CR0.EM set, then a 8008 * subsequent #NM VM-exit is reflected to L1. 8009 */ 8010 static void vmx_nm_test(void) 8011 { 8012 unsigned long cr0 = read_cr0(); 8013 8014 test_set_guest(vmx_nm_test_guest); 8015 8016 /* 8017 * L1 wants to intercept #NM exceptions encountered in L2. 8018 */ 8019 vmcs_write(EXC_BITMAP, 1 << NM_VECTOR); 8020 8021 /* 8022 * Launch L2 with CR0.TS clear, but don't claim host ownership of 8023 * any CR0 bits. L2 will set CR0.TS and then try to execute fnop, 8024 * which will raise #NM. L0 should reflect the #NM VM-exit to L1. 8025 */ 8026 vmcs_write(CR0_MASK, 0); 8027 vmcs_write(GUEST_CR0, cr0 & ~X86_CR0_TS); 8028 enter_guest(); 8029 check_nm_exit("fnop with CR0.TS set in L2 triggers #NM VM-exit to L1"); 8030 8031 /* 8032 * Re-enter L2 at the fnop instruction, with CR0.TS clear but 8033 * CR0.EM set. The fnop will still raise #NM, and L0 should 8034 * reflect the #NM VM-exit to L1. 8035 */ 8036 vmcs_write(GUEST_CR0, (cr0 & ~X86_CR0_TS) | X86_CR0_EM); 8037 enter_guest(); 8038 check_nm_exit("fnop with CR0.EM set in L2 triggers #NM VM-exit to L1"); 8039 8040 /* 8041 * Re-enter L2 at the fnop instruction, with both CR0.TS and 8042 * CR0.EM clear. There will be no #NM, and the L2 guest should 8043 * exit normally. 8044 */ 8045 vmcs_write(GUEST_CR0, cr0 & ~(X86_CR0_TS | X86_CR0_EM)); 8046 enter_guest(); 8047 } 8048 8049 bool vmx_pending_event_ipi_fired; 8050 static void vmx_pending_event_ipi_isr(isr_regs_t *regs) 8051 { 8052 vmx_pending_event_ipi_fired = true; 8053 eoi(); 8054 } 8055 8056 bool vmx_pending_event_guest_run; 8057 static void vmx_pending_event_guest(void) 8058 { 8059 vmcall(); 8060 vmx_pending_event_guest_run = true; 8061 } 8062 8063 static void vmx_pending_event_test_core(bool guest_hlt) 8064 { 8065 int ipi_vector = 0xf1; 8066 8067 vmx_pending_event_ipi_fired = false; 8068 handle_irq(ipi_vector, vmx_pending_event_ipi_isr); 8069 8070 vmx_pending_event_guest_run = false; 8071 test_set_guest(vmx_pending_event_guest); 8072 8073 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 8074 8075 enter_guest(); 8076 skip_exit_vmcall(); 8077 8078 if (guest_hlt) 8079 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8080 8081 irq_disable(); 8082 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | 8083 APIC_DM_FIXED | ipi_vector, 8084 0); 8085 8086 enter_guest(); 8087 8088 assert_exit_reason(VMX_EXTINT); 8089 report(!vmx_pending_event_guest_run, 8090 "Guest did not run before host received IPI"); 8091 8092 irq_enable(); 8093 asm volatile ("nop"); 8094 irq_disable(); 8095 report(vmx_pending_event_ipi_fired, 8096 "Got pending interrupt after IRQ enabled"); 8097 8098 if (guest_hlt) 8099 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 8100 8101 enter_guest(); 8102 report(vmx_pending_event_guest_run, 8103 "Guest finished running when no interrupt"); 8104 } 8105 8106 static void vmx_pending_event_test(void) 8107 { 8108 vmx_pending_event_test_core(false); 8109 } 8110 8111 static void vmx_pending_event_hlt_test(void) 8112 { 8113 vmx_pending_event_test_core(true); 8114 } 8115 8116 static int vmx_window_test_db_count; 8117 8118 static void vmx_window_test_db_handler(struct ex_regs *regs) 8119 { 8120 vmx_window_test_db_count++; 8121 } 8122 8123 static void vmx_nmi_window_test_guest(void) 8124 { 8125 handle_exception(DB_VECTOR, vmx_window_test_db_handler); 8126 8127 asm volatile("vmcall\n\t" 8128 "nop\n\t"); 8129 8130 handle_exception(DB_VECTOR, NULL); 8131 } 8132 8133 static void verify_nmi_window_exit(u64 rip) 8134 { 8135 u32 exit_reason = vmcs_read(EXI_REASON); 8136 8137 report(exit_reason == VMX_NMI_WINDOW, 8138 "Exit reason (%d) is 'NMI window'", exit_reason); 8139 report(vmcs_read(GUEST_RIP) == rip, "RIP (%#lx) is %#lx", 8140 vmcs_read(GUEST_RIP), rip); 8141 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 8142 } 8143 8144 static void vmx_nmi_window_test(void) 8145 { 8146 u64 nop_addr; 8147 void *db_fault_addr = get_idt_addr(&boot_idt[DB_VECTOR]); 8148 8149 if (!(ctrl_pin_rev.clr & PIN_VIRT_NMI)) { 8150 report_skip("CPU does not support the \"Virtual NMIs\" VM-execution control."); 8151 return; 8152 } 8153 8154 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 8155 report_skip("CPU does not support the \"NMI-window exiting\" VM-execution control."); 8156 return; 8157 } 8158 8159 vmx_window_test_db_count = 0; 8160 8161 report_prefix_push("NMI-window"); 8162 test_set_guest(vmx_nmi_window_test_guest); 8163 vmcs_set_bits(PIN_CONTROLS, PIN_VIRT_NMI); 8164 enter_guest(); 8165 skip_exit_vmcall(); 8166 nop_addr = vmcs_read(GUEST_RIP); 8167 8168 /* 8169 * Ask for "NMI-window exiting," and expect an immediate VM-exit. 8170 * RIP will not advance. 8171 */ 8172 report_prefix_push("active, no blocking"); 8173 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 8174 enter_guest(); 8175 verify_nmi_window_exit(nop_addr); 8176 report_prefix_pop(); 8177 8178 /* 8179 * Ask for "NMI-window exiting" in a MOV-SS shadow, and expect 8180 * a VM-exit on the next instruction after the nop. (The nop 8181 * is one byte.) 8182 */ 8183 report_prefix_push("active, blocking by MOV-SS"); 8184 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 8185 enter_guest(); 8186 verify_nmi_window_exit(nop_addr + 1); 8187 report_prefix_pop(); 8188 8189 /* 8190 * Ask for "NMI-window exiting" (with event injection), and 8191 * expect a VM-exit after the event is injected. (RIP should 8192 * be at the address specified in the IDT entry for #DB.) 8193 */ 8194 report_prefix_push("active, no blocking, injecting #DB"); 8195 vmcs_write(ENT_INTR_INFO, 8196 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 8197 enter_guest(); 8198 verify_nmi_window_exit((u64)db_fault_addr); 8199 report_prefix_pop(); 8200 8201 /* 8202 * Ask for "NMI-window exiting" with NMI blocking, and expect 8203 * a VM-exit after the next IRET (i.e. after the #DB handler 8204 * returns). So, RIP should be back at one byte past the nop. 8205 */ 8206 report_prefix_push("active, blocking by NMI"); 8207 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_NMI); 8208 enter_guest(); 8209 verify_nmi_window_exit(nop_addr + 1); 8210 report(vmx_window_test_db_count == 1, 8211 "#DB handler executed once (actual %d times)", 8212 vmx_window_test_db_count); 8213 report_prefix_pop(); 8214 8215 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 8216 report_skip("CPU does not support activity state HLT."); 8217 } else { 8218 /* 8219 * Ask for "NMI-window exiting" when entering activity 8220 * state HLT, and expect an immediate VM-exit. RIP is 8221 * still one byte past the nop. 8222 */ 8223 report_prefix_push("halted, no blocking"); 8224 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8225 enter_guest(); 8226 verify_nmi_window_exit(nop_addr + 1); 8227 report_prefix_pop(); 8228 8229 /* 8230 * Ask for "NMI-window exiting" when entering activity 8231 * state HLT (with event injection), and expect a 8232 * VM-exit after the event is injected. (RIP should be 8233 * at the address specified in the IDT entry for #DB.) 8234 */ 8235 report_prefix_push("halted, no blocking, injecting #DB"); 8236 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8237 vmcs_write(ENT_INTR_INFO, 8238 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 8239 DB_VECTOR); 8240 enter_guest(); 8241 verify_nmi_window_exit((u64)db_fault_addr); 8242 report_prefix_pop(); 8243 } 8244 8245 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 8246 enter_guest(); 8247 report_prefix_pop(); 8248 } 8249 8250 static void vmx_intr_window_test_guest(void) 8251 { 8252 handle_exception(DB_VECTOR, vmx_window_test_db_handler); 8253 8254 /* 8255 * The two consecutive STIs are to ensure that only the first 8256 * one has a shadow. Note that NOP and STI are one byte 8257 * instructions. 8258 */ 8259 asm volatile("vmcall\n\t" 8260 "nop\n\t" 8261 "sti\n\t" 8262 "sti\n\t"); 8263 8264 handle_exception(DB_VECTOR, NULL); 8265 } 8266 8267 static void verify_intr_window_exit(u64 rip) 8268 { 8269 u32 exit_reason = vmcs_read(EXI_REASON); 8270 8271 report(exit_reason == VMX_INTR_WINDOW, 8272 "Exit reason (%d) is 'interrupt window'", exit_reason); 8273 report(vmcs_read(GUEST_RIP) == rip, "RIP (%#lx) is %#lx", 8274 vmcs_read(GUEST_RIP), rip); 8275 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 8276 } 8277 8278 static void vmx_intr_window_test(void) 8279 { 8280 u64 vmcall_addr; 8281 u64 nop_addr; 8282 unsigned int orig_db_gate_type; 8283 void *db_fault_addr = get_idt_addr(&boot_idt[DB_VECTOR]); 8284 8285 if (!(ctrl_cpu_rev[0].clr & CPU_INTR_WINDOW)) { 8286 report_skip("CPU does not support the \"interrupt-window exiting\" VM-execution control."); 8287 return; 8288 } 8289 8290 /* 8291 * Change the IDT entry for #DB from interrupt gate to trap gate, 8292 * so that it won't clear RFLAGS.IF. We don't want interrupts to 8293 * be disabled after vectoring a #DB. 8294 */ 8295 orig_db_gate_type = boot_idt[DB_VECTOR].type; 8296 boot_idt[DB_VECTOR].type = 15; 8297 8298 report_prefix_push("interrupt-window"); 8299 test_set_guest(vmx_intr_window_test_guest); 8300 enter_guest(); 8301 assert_exit_reason(VMX_VMCALL); 8302 vmcall_addr = vmcs_read(GUEST_RIP); 8303 8304 /* 8305 * Ask for "interrupt-window exiting" with RFLAGS.IF set and 8306 * no blocking; expect an immediate VM-exit. Note that we have 8307 * not advanced past the vmcall instruction yet, so RIP should 8308 * point to the vmcall instruction. 8309 */ 8310 report_prefix_push("active, no blocking, RFLAGS.IF=1"); 8311 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8312 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_IF); 8313 enter_guest(); 8314 verify_intr_window_exit(vmcall_addr); 8315 report_prefix_pop(); 8316 8317 /* 8318 * Ask for "interrupt-window exiting" (with event injection) 8319 * with RFLAGS.IF set and no blocking; expect a VM-exit after 8320 * the event is injected. That is, RIP should should be at the 8321 * address specified in the IDT entry for #DB. 8322 */ 8323 report_prefix_push("active, no blocking, RFLAGS.IF=1, injecting #DB"); 8324 vmcs_write(ENT_INTR_INFO, 8325 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 8326 vmcall_addr = vmcs_read(GUEST_RIP); 8327 enter_guest(); 8328 verify_intr_window_exit((u64)db_fault_addr); 8329 report_prefix_pop(); 8330 8331 /* 8332 * Let the L2 guest run through the IRET, back to the VMCALL. 8333 * We have to clear the "interrupt-window exiting" 8334 * VM-execution control, or it would just keep causing 8335 * VM-exits. Then, advance past the VMCALL and set the 8336 * "interrupt-window exiting" VM-execution control again. 8337 */ 8338 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8339 enter_guest(); 8340 skip_exit_vmcall(); 8341 nop_addr = vmcs_read(GUEST_RIP); 8342 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8343 8344 /* 8345 * Ask for "interrupt-window exiting" in a MOV-SS shadow with 8346 * RFLAGS.IF set, and expect a VM-exit on the next 8347 * instruction. (NOP is one byte.) 8348 */ 8349 report_prefix_push("active, blocking by MOV-SS, RFLAGS.IF=1"); 8350 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 8351 enter_guest(); 8352 verify_intr_window_exit(nop_addr + 1); 8353 report_prefix_pop(); 8354 8355 /* 8356 * Back up to the NOP and ask for "interrupt-window exiting" 8357 * in an STI shadow with RFLAGS.IF set, and expect a VM-exit 8358 * on the next instruction. (NOP is one byte.) 8359 */ 8360 report_prefix_push("active, blocking by STI, RFLAGS.IF=1"); 8361 vmcs_write(GUEST_RIP, nop_addr); 8362 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_STI); 8363 enter_guest(); 8364 verify_intr_window_exit(nop_addr + 1); 8365 report_prefix_pop(); 8366 8367 /* 8368 * Ask for "interrupt-window exiting" with RFLAGS.IF clear, 8369 * and expect a VM-exit on the instruction following the STI 8370 * shadow. Only the first STI (which is one byte past the NOP) 8371 * should have a shadow. The second STI (which is two bytes 8372 * past the NOP) has no shadow. Therefore, the interrupt 8373 * window opens at three bytes past the NOP. 8374 */ 8375 report_prefix_push("active, RFLAGS.IF = 0"); 8376 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 8377 enter_guest(); 8378 verify_intr_window_exit(nop_addr + 3); 8379 report_prefix_pop(); 8380 8381 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 8382 report_skip("CPU does not support activity state HLT."); 8383 } else { 8384 /* 8385 * Ask for "interrupt-window exiting" when entering 8386 * activity state HLT, and expect an immediate 8387 * VM-exit. RIP is still three bytes past the nop. 8388 */ 8389 report_prefix_push("halted, no blocking"); 8390 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8391 enter_guest(); 8392 verify_intr_window_exit(nop_addr + 3); 8393 report_prefix_pop(); 8394 8395 /* 8396 * Ask for "interrupt-window exiting" when entering 8397 * activity state HLT (with event injection), and 8398 * expect a VM-exit after the event is injected. That 8399 * is, RIP should should be at the address specified 8400 * in the IDT entry for #DB. 8401 */ 8402 report_prefix_push("halted, no blocking, injecting #DB"); 8403 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8404 vmcs_write(ENT_INTR_INFO, 8405 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 8406 DB_VECTOR); 8407 enter_guest(); 8408 verify_intr_window_exit((u64)db_fault_addr); 8409 report_prefix_pop(); 8410 } 8411 8412 boot_idt[DB_VECTOR].type = orig_db_gate_type; 8413 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8414 enter_guest(); 8415 report_prefix_pop(); 8416 } 8417 8418 #define GUEST_TSC_OFFSET (1u << 30) 8419 8420 static u64 guest_tsc; 8421 8422 static void vmx_store_tsc_test_guest(void) 8423 { 8424 guest_tsc = rdtsc(); 8425 } 8426 8427 /* 8428 * This test ensures that when IA32_TSC is in the VM-exit MSR-store 8429 * list, the value saved is not subject to the TSC offset that is 8430 * applied to RDTSC/RDTSCP/RDMSR(IA32_TSC) in guest execution. 8431 */ 8432 static void vmx_store_tsc_test(void) 8433 { 8434 struct vmx_msr_entry msr_entry = { .index = MSR_IA32_TSC }; 8435 u64 low, high; 8436 8437 if (!(ctrl_cpu_rev[0].clr & CPU_USE_TSC_OFFSET)) { 8438 report_skip("'Use TSC offsetting' not supported"); 8439 return; 8440 } 8441 8442 test_set_guest(vmx_store_tsc_test_guest); 8443 8444 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_USE_TSC_OFFSET); 8445 vmcs_write(EXI_MSR_ST_CNT, 1); 8446 vmcs_write(EXIT_MSR_ST_ADDR, virt_to_phys(&msr_entry)); 8447 vmcs_write(TSC_OFFSET, GUEST_TSC_OFFSET); 8448 8449 low = rdtsc(); 8450 enter_guest(); 8451 high = rdtsc(); 8452 8453 report(low + GUEST_TSC_OFFSET <= guest_tsc && 8454 guest_tsc <= high + GUEST_TSC_OFFSET, 8455 "RDTSC value in the guest (%lu) is in range [%lu, %lu]", 8456 guest_tsc, low + GUEST_TSC_OFFSET, high + GUEST_TSC_OFFSET); 8457 report(low <= msr_entry.value && msr_entry.value <= high, 8458 "IA32_TSC value saved in the VM-exit MSR-store list (%lu) is in range [%lu, %lu]", 8459 msr_entry.value, low, high); 8460 } 8461 8462 static void vmx_preemption_timer_zero_test_db_handler(struct ex_regs *regs) 8463 { 8464 } 8465 8466 static void vmx_preemption_timer_zero_test_guest(void) 8467 { 8468 while (vmx_get_test_stage() < 3) 8469 vmcall(); 8470 } 8471 8472 static void vmx_preemption_timer_zero_activate_preemption_timer(void) 8473 { 8474 vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT); 8475 vmcs_write(PREEMPT_TIMER_VALUE, 0); 8476 } 8477 8478 static void vmx_preemption_timer_zero_advance_past_vmcall(void) 8479 { 8480 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 8481 enter_guest(); 8482 skip_exit_vmcall(); 8483 } 8484 8485 static void vmx_preemption_timer_zero_inject_db(bool intercept_db) 8486 { 8487 vmx_preemption_timer_zero_activate_preemption_timer(); 8488 vmcs_write(ENT_INTR_INFO, INTR_INFO_VALID_MASK | 8489 INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 8490 vmcs_write(EXC_BITMAP, intercept_db ? 1 << DB_VECTOR : 0); 8491 enter_guest(); 8492 } 8493 8494 static void vmx_preemption_timer_zero_set_pending_dbg(u32 exception_bitmap) 8495 { 8496 vmx_preemption_timer_zero_activate_preemption_timer(); 8497 vmcs_write(GUEST_PENDING_DEBUG, BIT(12) | DR_TRAP1); 8498 vmcs_write(EXC_BITMAP, exception_bitmap); 8499 enter_guest(); 8500 } 8501 8502 static void vmx_preemption_timer_zero_expect_preempt_at_rip(u64 expected_rip) 8503 { 8504 u32 reason = (u32)vmcs_read(EXI_REASON); 8505 u64 guest_rip = vmcs_read(GUEST_RIP); 8506 8507 report(reason == VMX_PREEMPT && guest_rip == expected_rip, 8508 "Exit reason is 0x%x (expected 0x%x) and guest RIP is %lx (0x%lx expected).", 8509 reason, VMX_PREEMPT, guest_rip, expected_rip); 8510 } 8511 8512 /* 8513 * This test ensures that when the VMX preemption timer is zero at 8514 * VM-entry, a VM-exit occurs after any event injection and after any 8515 * pending debug exceptions are raised, but before execution of any 8516 * guest instructions. 8517 */ 8518 static void vmx_preemption_timer_zero_test(void) 8519 { 8520 u64 db_fault_address = (u64)get_idt_addr(&boot_idt[DB_VECTOR]); 8521 handler old_db; 8522 u32 reason; 8523 8524 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 8525 report_skip("'Activate VMX-preemption timer' not supported"); 8526 return; 8527 } 8528 8529 /* 8530 * Install a custom #DB handler that doesn't abort. 8531 */ 8532 old_db = handle_exception(DB_VECTOR, 8533 vmx_preemption_timer_zero_test_db_handler); 8534 8535 test_set_guest(vmx_preemption_timer_zero_test_guest); 8536 8537 /* 8538 * VMX-preemption timer should fire after event injection. 8539 */ 8540 vmx_set_test_stage(0); 8541 vmx_preemption_timer_zero_inject_db(0); 8542 vmx_preemption_timer_zero_expect_preempt_at_rip(db_fault_address); 8543 vmx_preemption_timer_zero_advance_past_vmcall(); 8544 8545 /* 8546 * VMX-preemption timer should fire after event injection. 8547 * Exception bitmap is irrelevant, since you can't intercept 8548 * an event that you injected. 8549 */ 8550 vmx_set_test_stage(1); 8551 vmx_preemption_timer_zero_inject_db(true); 8552 vmx_preemption_timer_zero_expect_preempt_at_rip(db_fault_address); 8553 vmx_preemption_timer_zero_advance_past_vmcall(); 8554 8555 /* 8556 * VMX-preemption timer should fire after pending debug exceptions 8557 * have delivered a #DB trap. 8558 */ 8559 vmx_set_test_stage(2); 8560 vmx_preemption_timer_zero_set_pending_dbg(0); 8561 vmx_preemption_timer_zero_expect_preempt_at_rip(db_fault_address); 8562 vmx_preemption_timer_zero_advance_past_vmcall(); 8563 8564 /* 8565 * VMX-preemption timer would fire after pending debug exceptions 8566 * have delivered a #DB trap, but in this case, the #DB trap is 8567 * intercepted. 8568 */ 8569 vmx_set_test_stage(3); 8570 vmx_preemption_timer_zero_set_pending_dbg(1 << DB_VECTOR); 8571 reason = (u32)vmcs_read(EXI_REASON); 8572 report(reason == VMX_EXC_NMI, "Exit reason is 0x%x (expected 0x%x)", 8573 reason, VMX_EXC_NMI); 8574 8575 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 8576 enter_guest(); 8577 8578 handle_exception(DB_VECTOR, old_db); 8579 } 8580 8581 static u64 vmx_preemption_timer_tf_test_prev_rip; 8582 8583 static void vmx_preemption_timer_tf_test_db_handler(struct ex_regs *regs) 8584 { 8585 extern char vmx_preemption_timer_tf_test_endloop; 8586 8587 if (vmx_get_test_stage() == 2) { 8588 /* 8589 * Stage 2 means that we're done, one way or another. 8590 * Arrange for the iret to drop us out of the wbinvd 8591 * loop and stop single-stepping. 8592 */ 8593 regs->rip = (u64)&vmx_preemption_timer_tf_test_endloop; 8594 regs->rflags &= ~X86_EFLAGS_TF; 8595 } else if (regs->rip == vmx_preemption_timer_tf_test_prev_rip) { 8596 /* 8597 * The RIP should alternate between the wbinvd and the 8598 * jmp instruction in the code below. If we ever see 8599 * the same instruction twice in a row, that means a 8600 * single-step trap has been dropped. Let the 8601 * hypervisor know about the failure by executing a 8602 * VMCALL. 8603 */ 8604 vmcall(); 8605 } 8606 vmx_preemption_timer_tf_test_prev_rip = regs->rip; 8607 } 8608 8609 static void vmx_preemption_timer_tf_test_guest(void) 8610 { 8611 /* 8612 * The hypervisor doesn't intercept WBINVD, so the loop below 8613 * shouldn't be a problem--it's just two instructions 8614 * executing in VMX non-root mode. However, when the 8615 * hypervisor is running in a virtual environment, the parent 8616 * hypervisor might intercept WBINVD and emulate it. If the 8617 * parent hypervisor is broken, the single-step trap after the 8618 * WBINVD might be lost. 8619 */ 8620 asm volatile("vmcall\n\t" 8621 "0: wbinvd\n\t" 8622 "1: jmp 0b\n\t" 8623 "vmx_preemption_timer_tf_test_endloop:"); 8624 } 8625 8626 /* 8627 * Ensure that the delivery of a "VMX-preemption timer expired" 8628 * VM-exit doesn't disrupt single-stepping in the guest. Note that 8629 * passing this test doesn't ensure correctness, because the test will 8630 * only fail if the VMX-preemtion timer fires at the right time (or 8631 * the wrong time, as it were). 8632 */ 8633 static void vmx_preemption_timer_tf_test(void) 8634 { 8635 handler old_db; 8636 u32 reason; 8637 int i; 8638 8639 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 8640 report_skip("'Activate VMX-preemption timer' not supported"); 8641 return; 8642 } 8643 8644 old_db = handle_exception(DB_VECTOR, 8645 vmx_preemption_timer_tf_test_db_handler); 8646 8647 test_set_guest(vmx_preemption_timer_tf_test_guest); 8648 8649 enter_guest(); 8650 skip_exit_vmcall(); 8651 8652 vmx_set_test_stage(1); 8653 vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT); 8654 vmcs_write(PREEMPT_TIMER_VALUE, 50000); 8655 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_TF); 8656 8657 /* 8658 * The only exit we should see is "VMX-preemption timer 8659 * expired." If we get a VMCALL exit, that means the #DB 8660 * handler has detected a missing single-step trap. It doesn't 8661 * matter where the guest RIP is when the VMX-preemption timer 8662 * expires (whether it's in the WBINVD loop or in the #DB 8663 * handler)--a single-step trap should never be discarded. 8664 */ 8665 for (i = 0; i < 10000; i++) { 8666 enter_guest(); 8667 reason = (u32)vmcs_read(EXI_REASON); 8668 if (reason == VMX_PREEMPT) 8669 continue; 8670 TEST_ASSERT(reason == VMX_VMCALL); 8671 skip_exit_insn(); 8672 break; 8673 } 8674 8675 report(reason == VMX_PREEMPT, "No single-step traps skipped"); 8676 8677 vmx_set_test_stage(2); 8678 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 8679 enter_guest(); 8680 8681 handle_exception(DB_VECTOR, old_db); 8682 } 8683 8684 #define VMX_PREEMPTION_TIMER_EXPIRY_CYCLES 1000000 8685 8686 static u64 vmx_preemption_timer_expiry_start; 8687 static u64 vmx_preemption_timer_expiry_finish; 8688 8689 static void vmx_preemption_timer_expiry_test_guest(void) 8690 { 8691 vmcall(); 8692 vmx_preemption_timer_expiry_start = fenced_rdtsc(); 8693 8694 while (vmx_get_test_stage() == 0) 8695 vmx_preemption_timer_expiry_finish = fenced_rdtsc(); 8696 } 8697 8698 /* 8699 * Test that the VMX-preemption timer is not excessively delayed. 8700 * 8701 * Per the SDM, volume 3, VM-entry starts the VMX-preemption timer 8702 * with the unsigned value in the VMX-preemption timer-value field, 8703 * and the VMX-preemption timer counts down by 1 every time bit X in 8704 * the TSC changes due to a TSC increment (where X is 8705 * IA32_VMX_MISC[4:0]). If the timer counts down to zero in any state 8706 * other than the wait-for-SIPI state, the logical processor 8707 * transitions to the C0 C-state and causes a VM-exit. 8708 * 8709 * The guest code above reads the starting TSC after VM-entry. At this 8710 * point, the VMX-preemption timer has already been activated. Next, 8711 * the guest code reads the current TSC in a loop, storing the value 8712 * read to memory. 8713 * 8714 * If the RDTSC in the loop reads a value past the VMX-preemption 8715 * timer deadline, then the VMX-preemption timer VM-exit must be 8716 * delivered before the next instruction retires. Even if a higher 8717 * priority SMI is delivered first, the VMX-preemption timer VM-exit 8718 * must be delivered before the next instruction retires. Hence, a TSC 8719 * value past the VMX-preemption timer deadline might be read, but it 8720 * cannot be stored. If a TSC value past the deadline *is* stored, 8721 * then the architectural specification has been violated. 8722 */ 8723 static void vmx_preemption_timer_expiry_test(void) 8724 { 8725 u32 preemption_timer_value; 8726 union vmx_misc misc; 8727 u64 tsc_deadline; 8728 u32 reason; 8729 8730 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 8731 report_skip("'Activate VMX-preemption timer' not supported"); 8732 return; 8733 } 8734 8735 test_set_guest(vmx_preemption_timer_expiry_test_guest); 8736 8737 enter_guest(); 8738 skip_exit_vmcall(); 8739 8740 misc.val = rdmsr(MSR_IA32_VMX_MISC); 8741 preemption_timer_value = 8742 VMX_PREEMPTION_TIMER_EXPIRY_CYCLES >> misc.pt_bit; 8743 8744 vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT); 8745 vmcs_write(PREEMPT_TIMER_VALUE, preemption_timer_value); 8746 vmx_set_test_stage(0); 8747 8748 enter_guest(); 8749 reason = (u32)vmcs_read(EXI_REASON); 8750 TEST_ASSERT(reason == VMX_PREEMPT); 8751 8752 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 8753 vmx_set_test_stage(1); 8754 enter_guest(); 8755 8756 tsc_deadline = ((vmx_preemption_timer_expiry_start >> misc.pt_bit) << 8757 misc.pt_bit) + (preemption_timer_value << misc.pt_bit); 8758 8759 report(vmx_preemption_timer_expiry_finish < tsc_deadline, 8760 "Last stored guest TSC (%lu) < TSC deadline (%lu)", 8761 vmx_preemption_timer_expiry_finish, tsc_deadline); 8762 } 8763 8764 static void vmx_db_test_guest(void) 8765 { 8766 /* 8767 * For a hardware generated single-step #DB. 8768 */ 8769 asm volatile("vmcall;" 8770 "nop;" 8771 ".Lpost_nop:"); 8772 /* 8773 * ...in a MOVSS shadow, with pending debug exceptions. 8774 */ 8775 asm volatile("vmcall;" 8776 "nop;" 8777 ".Lpost_movss_nop:"); 8778 /* 8779 * For an L0 synthesized single-step #DB. (L0 intercepts WBINVD and 8780 * emulates it in software.) 8781 */ 8782 asm volatile("vmcall;" 8783 "wbinvd;" 8784 ".Lpost_wbinvd:"); 8785 /* 8786 * ...in a MOVSS shadow, with pending debug exceptions. 8787 */ 8788 asm volatile("vmcall;" 8789 "wbinvd;" 8790 ".Lpost_movss_wbinvd:"); 8791 /* 8792 * For a hardware generated single-step #DB in a transactional region. 8793 */ 8794 asm volatile("vmcall;" 8795 ".Lxbegin: xbegin .Lskip_rtm;" 8796 "xend;" 8797 ".Lskip_rtm:"); 8798 } 8799 8800 /* 8801 * Clear the pending debug exceptions and RFLAGS.TF and re-enter 8802 * L2. No #DB is delivered and L2 continues to the next point of 8803 * interest. 8804 */ 8805 static void dismiss_db(void) 8806 { 8807 vmcs_write(GUEST_PENDING_DEBUG, 0); 8808 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 8809 enter_guest(); 8810 } 8811 8812 /* 8813 * Check a variety of VMCS fields relevant to an intercepted #DB exception. 8814 * Then throw away the #DB exception and resume L2. 8815 */ 8816 static void check_db_exit(bool xfail_qual, bool xfail_dr6, bool xfail_pdbg, 8817 void *expected_rip, u64 expected_exit_qual, 8818 u64 expected_dr6) 8819 { 8820 u32 reason = vmcs_read(EXI_REASON); 8821 u32 intr_info = vmcs_read(EXI_INTR_INFO); 8822 u64 exit_qual = vmcs_read(EXI_QUALIFICATION); 8823 u64 guest_rip = vmcs_read(GUEST_RIP); 8824 u64 guest_pending_dbg = vmcs_read(GUEST_PENDING_DEBUG); 8825 u64 dr6 = read_dr6(); 8826 const u32 expected_intr_info = INTR_INFO_VALID_MASK | 8827 INTR_TYPE_HARD_EXCEPTION | DB_VECTOR; 8828 8829 report(reason == VMX_EXC_NMI && intr_info == expected_intr_info, 8830 "Expected #DB VM-exit"); 8831 report((u64)expected_rip == guest_rip, "Expected RIP %p (actual %lx)", 8832 expected_rip, guest_rip); 8833 report_xfail(xfail_pdbg, 0 == guest_pending_dbg, 8834 "Expected pending debug exceptions 0 (actual %lx)", 8835 guest_pending_dbg); 8836 report_xfail(xfail_qual, expected_exit_qual == exit_qual, 8837 "Expected exit qualification %lx (actual %lx)", 8838 expected_exit_qual, exit_qual); 8839 report_xfail(xfail_dr6, expected_dr6 == dr6, 8840 "Expected DR6 %lx (actual %lx)", expected_dr6, dr6); 8841 dismiss_db(); 8842 } 8843 8844 /* 8845 * Assuming the guest has just exited on a VMCALL instruction, skip 8846 * over the vmcall, and set the guest's RFLAGS.TF in the VMCS. If 8847 * pending debug exceptions are non-zero, set the VMCS up as if the 8848 * previous instruction was a MOVSS that generated the indicated 8849 * pending debug exceptions. Then enter L2. 8850 */ 8851 static void single_step_guest(const char *test_name, u64 starting_dr6, 8852 u64 pending_debug_exceptions) 8853 { 8854 printf("\n%s\n", test_name); 8855 skip_exit_vmcall(); 8856 write_dr6(starting_dr6); 8857 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_TF); 8858 if (pending_debug_exceptions) { 8859 vmcs_write(GUEST_PENDING_DEBUG, pending_debug_exceptions); 8860 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 8861 } 8862 enter_guest(); 8863 } 8864 8865 /* 8866 * When L1 intercepts #DB, verify that a single-step trap clears 8867 * pending debug exceptions, populates the exit qualification field 8868 * properly, and that DR6 is not prematurely clobbered. In a 8869 * (simulated) MOVSS shadow, make sure that the pending debug 8870 * exception bits are properly accumulated into the exit qualification 8871 * field. 8872 */ 8873 static void vmx_db_test(void) 8874 { 8875 /* 8876 * We are going to set a few arbitrary bits in DR6 to verify that 8877 * (a) DR6 is not modified by an intercepted #DB, and 8878 * (b) stale bits in DR6 (DR6.BD, in particular) don't leak into 8879 * the exit qualification field for a subsequent #DB exception. 8880 */ 8881 const u64 starting_dr6 = DR6_RESERVED | BIT(13) | DR_TRAP3 | DR_TRAP1; 8882 extern char post_nop asm(".Lpost_nop"); 8883 extern char post_movss_nop asm(".Lpost_movss_nop"); 8884 extern char post_wbinvd asm(".Lpost_wbinvd"); 8885 extern char post_movss_wbinvd asm(".Lpost_movss_wbinvd"); 8886 extern char xbegin asm(".Lxbegin"); 8887 extern char skip_rtm asm(".Lskip_rtm"); 8888 8889 /* 8890 * L1 wants to intercept #DB exceptions encountered in L2. 8891 */ 8892 vmcs_write(EXC_BITMAP, BIT(DB_VECTOR)); 8893 8894 /* 8895 * Start L2 and run it up to the first point of interest. 8896 */ 8897 test_set_guest(vmx_db_test_guest); 8898 enter_guest(); 8899 8900 /* 8901 * Hardware-delivered #DB trap for single-step sets the 8902 * standard that L0 has to follow for emulated instructions. 8903 */ 8904 single_step_guest("Hardware delivered single-step", starting_dr6, 0); 8905 check_db_exit(false, false, false, &post_nop, DR_STEP, starting_dr6); 8906 8907 /* 8908 * Hardware-delivered #DB trap for single-step in MOVSS shadow 8909 * also sets the standard that L0 has to follow for emulated 8910 * instructions. Here, we establish the VMCS pending debug 8911 * exceptions to indicate that the simulated MOVSS triggered a 8912 * data breakpoint as well as the single-step trap. 8913 */ 8914 single_step_guest("Hardware delivered single-step in MOVSS shadow", 8915 starting_dr6, BIT(12) | DR_STEP | DR_TRAP0 ); 8916 check_db_exit(false, false, false, &post_movss_nop, DR_STEP | DR_TRAP0, 8917 starting_dr6); 8918 8919 /* 8920 * L0 synthesized #DB trap for single-step is buggy, because 8921 * kvm (a) clobbers DR6 too early, and (b) tries its best to 8922 * reconstitute the exit qualification from the prematurely 8923 * modified DR6, but fails miserably. 8924 */ 8925 single_step_guest("Software synthesized single-step", starting_dr6, 0); 8926 check_db_exit(false, false, false, &post_wbinvd, DR_STEP, starting_dr6); 8927 8928 /* 8929 * L0 synthesized #DB trap for single-step in MOVSS shadow is 8930 * even worse, because L0 also leaves the pending debug 8931 * exceptions in the VMCS instead of accumulating them into 8932 * the exit qualification field for the #DB exception. 8933 */ 8934 single_step_guest("Software synthesized single-step in MOVSS shadow", 8935 starting_dr6, BIT(12) | DR_STEP | DR_TRAP0); 8936 check_db_exit(true, false, true, &post_movss_wbinvd, DR_STEP | DR_TRAP0, 8937 starting_dr6); 8938 8939 /* 8940 * Optional RTM test for hardware that supports RTM, to 8941 * demonstrate that the current volume 3 of the SDM 8942 * (325384-067US), table 27-1 is incorrect. Bit 16 of the exit 8943 * qualification for debug exceptions is not reserved. It is 8944 * set to 1 if a debug exception (#DB) or a breakpoint 8945 * exception (#BP) occurs inside an RTM region while advanced 8946 * debugging of RTM transactional regions is enabled. 8947 */ 8948 if (this_cpu_has(X86_FEATURE_RTM)) { 8949 vmcs_write(ENT_CONTROLS, 8950 vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 8951 /* 8952 * Set DR7.RTM[bit 11] and IA32_DEBUGCTL.RTM[bit 15] 8953 * in the guest to enable advanced debugging of RTM 8954 * transactional regions. 8955 */ 8956 vmcs_write(GUEST_DR7, BIT(11)); 8957 vmcs_write(GUEST_DEBUGCTL, BIT(15)); 8958 single_step_guest("Hardware delivered single-step in " 8959 "transactional region", starting_dr6, 0); 8960 check_db_exit(false, false, false, &xbegin, BIT(16), 8961 starting_dr6); 8962 } else { 8963 vmcs_write(GUEST_RIP, (u64)&skip_rtm); 8964 enter_guest(); 8965 } 8966 } 8967 8968 static void enable_vid(void) 8969 { 8970 void *virtual_apic_page; 8971 8972 assert(cpu_has_apicv()); 8973 8974 disable_intercept_for_x2apic_msrs(); 8975 8976 virtual_apic_page = alloc_page(); 8977 vmcs_write(APIC_VIRT_ADDR, (u64)virtual_apic_page); 8978 8979 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 8980 8981 vmcs_write(EOI_EXIT_BITMAP0, 0x0); 8982 vmcs_write(EOI_EXIT_BITMAP1, 0x0); 8983 vmcs_write(EOI_EXIT_BITMAP2, 0x0); 8984 vmcs_write(EOI_EXIT_BITMAP3, 0x0); 8985 8986 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY | CPU_TPR_SHADOW); 8987 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_VINTD | CPU_VIRT_X2APIC); 8988 } 8989 8990 static void trigger_ioapic_scan_thread(void *data) 8991 { 8992 /* Wait until other CPU entered L2 */ 8993 while (vmx_get_test_stage() != 1) 8994 ; 8995 8996 /* Trigger ioapic scan */ 8997 ioapic_set_redir(0xf, 0x79, TRIGGER_LEVEL); 8998 vmx_set_test_stage(2); 8999 } 9000 9001 static void irq_79_handler_guest(isr_regs_t *regs) 9002 { 9003 eoi(); 9004 9005 /* L1 expects vmexit on VMX_VMCALL and not VMX_EOI_INDUCED */ 9006 vmcall(); 9007 } 9008 9009 /* 9010 * Constant for num of busy-loop iterations after which 9011 * a timer interrupt should have happened in host 9012 */ 9013 #define TIMER_INTERRUPT_DELAY 100000000 9014 9015 static void vmx_eoi_bitmap_ioapic_scan_test_guest(void) 9016 { 9017 handle_irq(0x79, irq_79_handler_guest); 9018 irq_enable(); 9019 9020 /* Signal to L1 CPU to trigger ioapic scan */ 9021 vmx_set_test_stage(1); 9022 /* Wait until L1 CPU to trigger ioapic scan */ 9023 while (vmx_get_test_stage() != 2) 9024 ; 9025 9026 /* 9027 * Wait for L0 timer interrupt to be raised while we run in L2 9028 * such that L0 will process the IOAPIC scan request before 9029 * resuming L2 9030 */ 9031 delay(TIMER_INTERRUPT_DELAY); 9032 9033 asm volatile ("int $0x79"); 9034 } 9035 9036 static void vmx_eoi_bitmap_ioapic_scan_test(void) 9037 { 9038 if (!cpu_has_apicv() || (cpu_count() < 2)) { 9039 report_skip(__func__); 9040 return; 9041 } 9042 9043 enable_vid(); 9044 9045 on_cpu_async(1, trigger_ioapic_scan_thread, NULL); 9046 test_set_guest(vmx_eoi_bitmap_ioapic_scan_test_guest); 9047 9048 /* 9049 * Launch L2. 9050 * We expect the exit reason to be VMX_VMCALL (and not EOI INDUCED). 9051 * In case the reason isn't VMX_VMCALL, the asserion inside 9052 * skip_exit_vmcall() will fail. 9053 */ 9054 enter_guest(); 9055 skip_exit_vmcall(); 9056 9057 /* Let L2 finish */ 9058 enter_guest(); 9059 report(1, __func__); 9060 } 9061 9062 #define HLT_WITH_RVI_VECTOR (0xf1) 9063 9064 bool vmx_hlt_with_rvi_guest_isr_fired; 9065 static void vmx_hlt_with_rvi_guest_isr(isr_regs_t *regs) 9066 { 9067 vmx_hlt_with_rvi_guest_isr_fired = true; 9068 eoi(); 9069 } 9070 9071 static void vmx_hlt_with_rvi_guest(void) 9072 { 9073 handle_irq(HLT_WITH_RVI_VECTOR, vmx_hlt_with_rvi_guest_isr); 9074 9075 irq_enable(); 9076 asm volatile ("nop"); 9077 9078 vmcall(); 9079 } 9080 9081 static void vmx_hlt_with_rvi_test(void) 9082 { 9083 if (!cpu_has_apicv()) { 9084 report_skip(__func__); 9085 return; 9086 } 9087 9088 enable_vid(); 9089 9090 vmx_hlt_with_rvi_guest_isr_fired = false; 9091 test_set_guest(vmx_hlt_with_rvi_guest); 9092 9093 enter_guest(); 9094 skip_exit_vmcall(); 9095 9096 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 9097 vmcs_write(GUEST_INT_STATUS, HLT_WITH_RVI_VECTOR); 9098 enter_guest(); 9099 9100 report(vmx_hlt_with_rvi_guest_isr_fired, "Interrupt raised in guest"); 9101 } 9102 9103 static void set_irq_line_thread(void *data) 9104 { 9105 /* Wait until other CPU entered L2 */ 9106 while (vmx_get_test_stage() != 1) 9107 ; 9108 9109 /* Set irq-line 0xf to raise vector 0x78 for vCPU 0 */ 9110 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 9111 vmx_set_test_stage(2); 9112 } 9113 9114 static bool irq_78_handler_vmcall_before_eoi; 9115 static void irq_78_handler_guest(isr_regs_t *regs) 9116 { 9117 set_irq_line(0xf, 0); 9118 if (irq_78_handler_vmcall_before_eoi) 9119 vmcall(); 9120 eoi(); 9121 vmcall(); 9122 } 9123 9124 static void vmx_apic_passthrough_guest(void) 9125 { 9126 handle_irq(0x78, irq_78_handler_guest); 9127 irq_enable(); 9128 9129 /* If requested, wait for other CPU to trigger ioapic scan */ 9130 if (vmx_get_test_stage() < 1) { 9131 vmx_set_test_stage(1); 9132 while (vmx_get_test_stage() != 2) 9133 ; 9134 } 9135 9136 set_irq_line(0xf, 1); 9137 } 9138 9139 static void vmx_apic_passthrough(bool set_irq_line_from_thread) 9140 { 9141 if (set_irq_line_from_thread && (cpu_count() < 2)) { 9142 report_skip(__func__); 9143 return; 9144 } 9145 9146 /* Test device is required for generating IRQs */ 9147 if (!test_device_enabled()) { 9148 report_skip(__func__); 9149 return; 9150 } 9151 u64 cpu_ctrl_0 = CPU_SECONDARY; 9152 u64 cpu_ctrl_1 = 0; 9153 9154 disable_intercept_for_x2apic_msrs(); 9155 9156 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 9157 9158 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 9159 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 9160 9161 if (set_irq_line_from_thread) { 9162 irq_78_handler_vmcall_before_eoi = false; 9163 on_cpu_async(1, set_irq_line_thread, NULL); 9164 } else { 9165 irq_78_handler_vmcall_before_eoi = true; 9166 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 9167 vmx_set_test_stage(2); 9168 } 9169 test_set_guest(vmx_apic_passthrough_guest); 9170 9171 if (irq_78_handler_vmcall_before_eoi) { 9172 /* Before EOI remote_irr should still be set */ 9173 enter_guest(); 9174 skip_exit_vmcall(); 9175 TEST_ASSERT_EQ_MSG(1, (int)ioapic_read_redir(0xf).remote_irr, 9176 "IOAPIC pass-through: remote_irr=1 before EOI"); 9177 } 9178 9179 /* After EOI remote_irr should be cleared */ 9180 enter_guest(); 9181 skip_exit_vmcall(); 9182 TEST_ASSERT_EQ_MSG(0, (int)ioapic_read_redir(0xf).remote_irr, 9183 "IOAPIC pass-through: remote_irr=0 after EOI"); 9184 9185 /* Let L2 finish */ 9186 enter_guest(); 9187 report(1, __func__); 9188 } 9189 9190 static void vmx_apic_passthrough_test(void) 9191 { 9192 vmx_apic_passthrough(false); 9193 } 9194 9195 static void vmx_apic_passthrough_thread_test(void) 9196 { 9197 vmx_apic_passthrough(true); 9198 } 9199 9200 static void vmx_apic_passthrough_tpr_threshold_guest(void) 9201 { 9202 cli(); 9203 apic_set_tpr(0); 9204 } 9205 9206 static bool vmx_apic_passthrough_tpr_threshold_ipi_isr_fired; 9207 static void vmx_apic_passthrough_tpr_threshold_ipi_isr(isr_regs_t *regs) 9208 { 9209 vmx_apic_passthrough_tpr_threshold_ipi_isr_fired = true; 9210 eoi(); 9211 } 9212 9213 static void vmx_apic_passthrough_tpr_threshold_test(void) 9214 { 9215 int ipi_vector = 0xe1; 9216 9217 disable_intercept_for_x2apic_msrs(); 9218 vmcs_clear_bits(PIN_CONTROLS, PIN_EXTINT); 9219 9220 /* Raise L0 TPR-threshold by queueing vector in LAPIC IRR */ 9221 cli(); 9222 apic_set_tpr((ipi_vector >> 4) + 1); 9223 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | 9224 APIC_DM_FIXED | ipi_vector, 9225 0); 9226 9227 test_set_guest(vmx_apic_passthrough_tpr_threshold_guest); 9228 enter_guest(); 9229 9230 report(apic_get_tpr() == 0, "TPR was zero by guest"); 9231 9232 /* Clean pending self-IPI */ 9233 vmx_apic_passthrough_tpr_threshold_ipi_isr_fired = false; 9234 handle_irq(ipi_vector, vmx_apic_passthrough_tpr_threshold_ipi_isr); 9235 sti(); 9236 asm volatile ("nop"); 9237 report(vmx_apic_passthrough_tpr_threshold_ipi_isr_fired, "self-IPI fired"); 9238 9239 report(1, __func__); 9240 } 9241 9242 static u64 init_signal_test_exit_reason; 9243 static bool init_signal_test_thread_continued; 9244 9245 static void init_signal_test_thread(void *data) 9246 { 9247 struct vmcs *test_vmcs = data; 9248 9249 /* Enter VMX operation (i.e. exec VMXON) */ 9250 u64 *ap_vmxon_region = alloc_page(); 9251 enable_vmx(); 9252 init_vmx(ap_vmxon_region); 9253 _vmx_on(ap_vmxon_region); 9254 9255 /* Signal CPU have entered VMX operation */ 9256 vmx_set_test_stage(1); 9257 9258 /* Wait for BSP CPU to send INIT signal */ 9259 while (vmx_get_test_stage() != 2) 9260 ; 9261 9262 /* 9263 * Signal that we continue as usual as INIT signal 9264 * should be blocked while CPU is in VMX operation 9265 */ 9266 vmx_set_test_stage(3); 9267 9268 /* Wait for signal to enter VMX non-root mode */ 9269 while (vmx_get_test_stage() != 4) 9270 ; 9271 9272 /* Enter VMX non-root mode */ 9273 test_set_guest(v2_null_test_guest); 9274 make_vmcs_current(test_vmcs); 9275 enter_guest(); 9276 /* Save exit reason for BSP CPU to compare to expected result */ 9277 init_signal_test_exit_reason = vmcs_read(EXI_REASON); 9278 /* VMCLEAR test-vmcs so it could be loaded by BSP CPU */ 9279 vmcs_clear(test_vmcs); 9280 launched = false; 9281 /* Signal that CPU exited to VMX root mode */ 9282 vmx_set_test_stage(5); 9283 9284 /* Wait for BSP CPU to signal to exit VMX operation */ 9285 while (vmx_get_test_stage() != 6) 9286 ; 9287 9288 /* Exit VMX operation (i.e. exec VMXOFF) */ 9289 vmx_off(); 9290 9291 /* 9292 * Signal to BSP CPU that we continue as usual as INIT signal 9293 * should have been consumed by VMX_INIT exit from guest 9294 */ 9295 vmx_set_test_stage(7); 9296 9297 /* Wait for BSP CPU to signal to enter VMX operation */ 9298 while (vmx_get_test_stage() != 8) 9299 ; 9300 /* Enter VMX operation (i.e. exec VMXON) */ 9301 _vmx_on(ap_vmxon_region); 9302 /* Signal to BSP we are in VMX operation */ 9303 vmx_set_test_stage(9); 9304 9305 /* Wait for BSP CPU to send INIT signal */ 9306 while (vmx_get_test_stage() != 10) 9307 ; 9308 9309 /* Exit VMX operation (i.e. exec VMXOFF) */ 9310 vmx_off(); 9311 9312 /* 9313 * Exiting VMX operation should result in latched 9314 * INIT signal being processed. Therefore, we should 9315 * never reach the below code. Thus, signal to BSP 9316 * CPU if we have reached here so it is able to 9317 * report an issue if it happens. 9318 */ 9319 init_signal_test_thread_continued = true; 9320 } 9321 9322 #define INIT_SIGNAL_TEST_DELAY 100000000ULL 9323 9324 static void vmx_init_signal_test(void) 9325 { 9326 struct vmcs *test_vmcs; 9327 9328 if (cpu_count() < 2) { 9329 report_skip(__func__); 9330 return; 9331 } 9332 9333 /* VMCLEAR test-vmcs so it could be loaded by other CPU */ 9334 vmcs_save(&test_vmcs); 9335 vmcs_clear(test_vmcs); 9336 9337 vmx_set_test_stage(0); 9338 on_cpu_async(1, init_signal_test_thread, test_vmcs); 9339 9340 /* Wait for other CPU to enter VMX operation */ 9341 while (vmx_get_test_stage() != 1) 9342 ; 9343 9344 /* Send INIT signal to other CPU */ 9345 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_INIT | APIC_INT_ASSERT, 9346 id_map[1]); 9347 /* Signal other CPU we have sent INIT signal */ 9348 vmx_set_test_stage(2); 9349 9350 /* 9351 * Wait reasonable amount of time for INIT signal to 9352 * be received on other CPU and verify that other CPU 9353 * have proceed as usual to next test stage as INIT 9354 * signal should be blocked while other CPU in 9355 * VMX operation 9356 */ 9357 delay(INIT_SIGNAL_TEST_DELAY); 9358 report(vmx_get_test_stage() == 3, 9359 "INIT signal blocked when CPU in VMX operation"); 9360 /* No point to continue if we failed at this point */ 9361 if (vmx_get_test_stage() != 3) 9362 return; 9363 9364 /* Signal other CPU to enter VMX non-root mode */ 9365 init_signal_test_exit_reason = -1ull; 9366 vmx_set_test_stage(4); 9367 /* 9368 * Wait reasonable amont of time for other CPU 9369 * to exit to VMX root mode 9370 */ 9371 delay(INIT_SIGNAL_TEST_DELAY); 9372 if (vmx_get_test_stage() != 5) { 9373 report(false, "Pending INIT signal didn't result in VMX exit"); 9374 return; 9375 } 9376 report(init_signal_test_exit_reason == VMX_INIT, 9377 "INIT signal during VMX non-root mode result in exit-reason %s (%lu)", 9378 exit_reason_description(init_signal_test_exit_reason), 9379 init_signal_test_exit_reason); 9380 9381 /* Run guest to completion */ 9382 make_vmcs_current(test_vmcs); 9383 enter_guest(); 9384 9385 /* Signal other CPU to exit VMX operation */ 9386 init_signal_test_thread_continued = false; 9387 vmx_set_test_stage(6); 9388 9389 /* Wait reasonable amount of time for other CPU to exit VMX operation */ 9390 delay(INIT_SIGNAL_TEST_DELAY); 9391 report(vmx_get_test_stage() == 7, 9392 "INIT signal consumed on VMX_INIT exit"); 9393 /* No point to continue if we failed at this point */ 9394 if (vmx_get_test_stage() != 7) 9395 return; 9396 9397 /* Signal other CPU to enter VMX operation */ 9398 vmx_set_test_stage(8); 9399 /* Wait for other CPU to enter VMX operation */ 9400 while (vmx_get_test_stage() != 9) 9401 ; 9402 9403 /* Send INIT signal to other CPU */ 9404 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_INIT | APIC_INT_ASSERT, 9405 id_map[1]); 9406 /* Signal other CPU we have sent INIT signal */ 9407 vmx_set_test_stage(10); 9408 9409 /* 9410 * Wait reasonable amount of time for other CPU 9411 * to exit VMX operation and process INIT signal 9412 */ 9413 delay(INIT_SIGNAL_TEST_DELAY); 9414 report(!init_signal_test_thread_continued, 9415 "INIT signal processed after exit VMX operation"); 9416 9417 /* 9418 * TODO: Send SIPI to other CPU to sipi_entry (See x86/cstart64.S) 9419 * to re-init it to kvm-unit-tests standard environment. 9420 * Somehow (?) verify that SIPI was indeed received. 9421 */ 9422 } 9423 9424 enum vmcs_access { 9425 ACCESS_VMREAD, 9426 ACCESS_VMWRITE, 9427 ACCESS_NONE, 9428 }; 9429 9430 struct vmcs_shadow_test_common { 9431 enum vmcs_access op; 9432 enum Reason reason; 9433 u64 field; 9434 u64 value; 9435 u64 flags; 9436 u64 time; 9437 } l1_l2_common; 9438 9439 static inline u64 vmread_flags(u64 field, u64 *val) 9440 { 9441 u64 flags; 9442 9443 asm volatile ("vmread %2, %1; pushf; pop %0" 9444 : "=r" (flags), "=rm" (*val) : "r" (field) : "cc"); 9445 return flags & X86_EFLAGS_ALU; 9446 } 9447 9448 static inline u64 vmwrite_flags(u64 field, u64 val) 9449 { 9450 u64 flags; 9451 9452 asm volatile ("vmwrite %1, %2; pushf; pop %0" 9453 : "=r"(flags) : "rm" (val), "r" (field) : "cc"); 9454 return flags & X86_EFLAGS_ALU; 9455 } 9456 9457 static void vmx_vmcs_shadow_test_guest(void) 9458 { 9459 struct vmcs_shadow_test_common *c = &l1_l2_common; 9460 u64 start; 9461 9462 while (c->op != ACCESS_NONE) { 9463 start = rdtsc(); 9464 switch (c->op) { 9465 default: 9466 c->flags = -1ull; 9467 break; 9468 case ACCESS_VMREAD: 9469 c->flags = vmread_flags(c->field, &c->value); 9470 break; 9471 case ACCESS_VMWRITE: 9472 c->flags = vmwrite_flags(c->field, 0); 9473 break; 9474 } 9475 c->time = rdtsc() - start; 9476 vmcall(); 9477 } 9478 } 9479 9480 static u64 vmread_from_shadow(u64 field) 9481 { 9482 struct vmcs *primary; 9483 struct vmcs *shadow; 9484 u64 value; 9485 9486 TEST_ASSERT(!vmcs_save(&primary)); 9487 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 9488 TEST_ASSERT(!make_vmcs_current(shadow)); 9489 value = vmcs_read(field); 9490 TEST_ASSERT(!make_vmcs_current(primary)); 9491 return value; 9492 } 9493 9494 static u64 vmwrite_to_shadow(u64 field, u64 value) 9495 { 9496 struct vmcs *primary; 9497 struct vmcs *shadow; 9498 9499 TEST_ASSERT(!vmcs_save(&primary)); 9500 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 9501 TEST_ASSERT(!make_vmcs_current(shadow)); 9502 vmcs_write(field, value); 9503 value = vmcs_read(field); 9504 TEST_ASSERT(!make_vmcs_current(primary)); 9505 return value; 9506 } 9507 9508 static void vmcs_shadow_test_access(u8 *bitmap[2], enum vmcs_access access) 9509 { 9510 struct vmcs_shadow_test_common *c = &l1_l2_common; 9511 9512 c->op = access; 9513 vmcs_write(VMX_INST_ERROR, 0); 9514 enter_guest(); 9515 c->reason = vmcs_read(EXI_REASON) & 0xffff; 9516 if (c->reason != VMX_VMCALL) { 9517 skip_exit_insn(); 9518 enter_guest(); 9519 } 9520 skip_exit_vmcall(); 9521 } 9522 9523 static void vmcs_shadow_test_field(u8 *bitmap[2], u64 field) 9524 { 9525 struct vmcs_shadow_test_common *c = &l1_l2_common; 9526 struct vmcs *shadow; 9527 u64 value; 9528 uintptr_t flags[2]; 9529 bool good_shadow; 9530 u32 vmx_inst_error; 9531 9532 report_prefix_pushf("field %lx", field); 9533 c->field = field; 9534 9535 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 9536 if (shadow != (struct vmcs *)-1ull) { 9537 flags[ACCESS_VMREAD] = vmread_flags(field, &value); 9538 flags[ACCESS_VMWRITE] = vmwrite_flags(field, value); 9539 good_shadow = !flags[ACCESS_VMREAD] && !flags[ACCESS_VMWRITE]; 9540 } else { 9541 /* 9542 * When VMCS link pointer is -1ull, VMWRITE/VMREAD on 9543 * shadowed-fields should fail with setting RFLAGS.CF. 9544 */ 9545 flags[ACCESS_VMREAD] = X86_EFLAGS_CF; 9546 flags[ACCESS_VMWRITE] = X86_EFLAGS_CF; 9547 good_shadow = false; 9548 } 9549 9550 /* Intercept both VMREAD and VMWRITE. */ 9551 report_prefix_push("no VMREAD/VMWRITE permission"); 9552 /* VMWRITE/VMREAD done on reserved-bit should always intercept */ 9553 if (!(field >> VMCS_FIELD_RESERVED_SHIFT)) { 9554 set_bit(field, bitmap[ACCESS_VMREAD]); 9555 set_bit(field, bitmap[ACCESS_VMWRITE]); 9556 } 9557 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 9558 report(c->reason == VMX_VMWRITE, "not shadowed for VMWRITE"); 9559 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 9560 report(c->reason == VMX_VMREAD, "not shadowed for VMREAD"); 9561 report_prefix_pop(); 9562 9563 if (field >> VMCS_FIELD_RESERVED_SHIFT) 9564 goto out; 9565 9566 /* Permit shadowed VMREAD. */ 9567 report_prefix_push("VMREAD permission only"); 9568 clear_bit(field, bitmap[ACCESS_VMREAD]); 9569 set_bit(field, bitmap[ACCESS_VMWRITE]); 9570 if (good_shadow) 9571 value = vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 9572 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 9573 report(c->reason == VMX_VMWRITE, "not shadowed for VMWRITE"); 9574 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 9575 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 9576 report(c->reason == VMX_VMCALL, "shadowed for VMREAD (in %ld cycles)", 9577 c->time); 9578 report(c->flags == flags[ACCESS_VMREAD], 9579 "ALU flags after VMREAD (%lx) are as expected (%lx)", 9580 c->flags, flags[ACCESS_VMREAD]); 9581 if (good_shadow) 9582 report(c->value == value, 9583 "value read from shadow (%lx) is as expected (%lx)", 9584 c->value, value); 9585 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 9586 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 9587 "VMX_INST_ERROR (%d) is as expected (%d)", 9588 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 9589 report_prefix_pop(); 9590 9591 /* Permit shadowed VMWRITE. */ 9592 report_prefix_push("VMWRITE permission only"); 9593 set_bit(field, bitmap[ACCESS_VMREAD]); 9594 clear_bit(field, bitmap[ACCESS_VMWRITE]); 9595 if (good_shadow) 9596 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 9597 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 9598 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 9599 report(c->reason == VMX_VMCALL, 9600 "shadowed for VMWRITE (in %ld cycles)", 9601 c->time); 9602 report(c->flags == flags[ACCESS_VMREAD], 9603 "ALU flags after VMWRITE (%lx) are as expected (%lx)", 9604 c->flags, flags[ACCESS_VMREAD]); 9605 if (good_shadow) { 9606 value = vmread_from_shadow(field); 9607 report(value == 0, 9608 "shadow VMCS value (%lx) is as expected (%lx)", value, 9609 0ul); 9610 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 9611 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 9612 "VMX_INST_ERROR (%d) is as expected (%d)", 9613 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 9614 } 9615 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 9616 report(c->reason == VMX_VMREAD, "not shadowed for VMREAD"); 9617 report_prefix_pop(); 9618 9619 /* Permit shadowed VMREAD and VMWRITE. */ 9620 report_prefix_push("VMREAD and VMWRITE permission"); 9621 clear_bit(field, bitmap[ACCESS_VMREAD]); 9622 clear_bit(field, bitmap[ACCESS_VMWRITE]); 9623 if (good_shadow) 9624 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 9625 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 9626 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 9627 report(c->reason == VMX_VMCALL, 9628 "shadowed for VMWRITE (in %ld cycles)", 9629 c->time); 9630 report(c->flags == flags[ACCESS_VMREAD], 9631 "ALU flags after VMWRITE (%lx) are as expected (%lx)", 9632 c->flags, flags[ACCESS_VMREAD]); 9633 if (good_shadow) { 9634 value = vmread_from_shadow(field); 9635 report(value == 0, 9636 "shadow VMCS value (%lx) is as expected (%lx)", value, 9637 0ul); 9638 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 9639 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 9640 "VMX_INST_ERROR (%d) is as expected (%d)", 9641 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 9642 } 9643 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 9644 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 9645 report(c->reason == VMX_VMCALL, "shadowed for VMREAD (in %ld cycles)", 9646 c->time); 9647 report(c->flags == flags[ACCESS_VMREAD], 9648 "ALU flags after VMREAD (%lx) are as expected (%lx)", 9649 c->flags, flags[ACCESS_VMREAD]); 9650 if (good_shadow) 9651 report(c->value == 0, 9652 "value read from shadow (%lx) is as expected (%lx)", 9653 c->value, 0ul); 9654 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 9655 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 9656 "VMX_INST_ERROR (%d) is as expected (%d)", 9657 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 9658 report_prefix_pop(); 9659 9660 out: 9661 report_prefix_pop(); 9662 } 9663 9664 static void vmx_vmcs_shadow_test_body(u8 *bitmap[2]) 9665 { 9666 unsigned base; 9667 unsigned index; 9668 unsigned bit; 9669 unsigned highest_index = rdmsr(MSR_IA32_VMX_VMCS_ENUM); 9670 9671 /* Run test on all possible valid VMCS fields */ 9672 for (base = 0; 9673 base < (1 << VMCS_FIELD_RESERVED_SHIFT); 9674 base += (1 << VMCS_FIELD_TYPE_SHIFT)) 9675 for (index = 0; index <= highest_index; index++) 9676 vmcs_shadow_test_field(bitmap, base + index); 9677 9678 /* 9679 * Run tests on some invalid VMCS fields 9680 * (Have reserved bit set). 9681 */ 9682 for (bit = VMCS_FIELD_RESERVED_SHIFT; bit < VMCS_FIELD_BIT_SIZE; bit++) 9683 vmcs_shadow_test_field(bitmap, (1ull << bit)); 9684 } 9685 9686 static void vmx_vmcs_shadow_test(void) 9687 { 9688 u8 *bitmap[2]; 9689 struct vmcs *shadow; 9690 9691 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 9692 printf("\t'Activate secondary controls' not supported.\n"); 9693 return; 9694 } 9695 9696 if (!(ctrl_cpu_rev[1].clr & CPU_SHADOW_VMCS)) { 9697 printf("\t'VMCS shadowing' not supported.\n"); 9698 return; 9699 } 9700 9701 if (!(rdmsr(MSR_IA32_VMX_MISC) & 9702 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS)) { 9703 printf("\tVMWRITE can't modify VM-exit information fields.\n"); 9704 return; 9705 } 9706 9707 test_set_guest(vmx_vmcs_shadow_test_guest); 9708 9709 bitmap[ACCESS_VMREAD] = alloc_page(); 9710 bitmap[ACCESS_VMWRITE] = alloc_page(); 9711 9712 vmcs_write(VMREAD_BITMAP, virt_to_phys(bitmap[ACCESS_VMREAD])); 9713 vmcs_write(VMWRITE_BITMAP, virt_to_phys(bitmap[ACCESS_VMWRITE])); 9714 9715 shadow = alloc_page(); 9716 shadow->hdr.revision_id = basic.revision; 9717 shadow->hdr.shadow_vmcs = 1; 9718 TEST_ASSERT(!vmcs_clear(shadow)); 9719 9720 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_RDTSC); 9721 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY); 9722 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_SHADOW_VMCS); 9723 9724 vmcs_write(VMCS_LINK_PTR, virt_to_phys(shadow)); 9725 report_prefix_push("valid link pointer"); 9726 vmx_vmcs_shadow_test_body(bitmap); 9727 report_prefix_pop(); 9728 9729 vmcs_write(VMCS_LINK_PTR, -1ull); 9730 report_prefix_push("invalid link pointer"); 9731 vmx_vmcs_shadow_test_body(bitmap); 9732 report_prefix_pop(); 9733 9734 l1_l2_common.op = ACCESS_NONE; 9735 enter_guest(); 9736 } 9737 9738 /* 9739 * This test monitors the difference between a guest RDTSC instruction 9740 * and the IA32_TIME_STAMP_COUNTER MSR value stored in the VMCS12 9741 * VM-exit MSR-store list when taking a VM-exit on the instruction 9742 * following RDTSC. 9743 */ 9744 #define RDTSC_DIFF_ITERS 100000 9745 #define RDTSC_DIFF_FAILS 100 9746 #define HOST_CAPTURED_GUEST_TSC_DIFF_THRESHOLD 750 9747 9748 /* 9749 * Set 'use TSC offsetting' and set the guest offset to the 9750 * inverse of the host's current TSC value, so that the guest starts running 9751 * with an effective TSC value of 0. 9752 */ 9753 static void reset_guest_tsc_to_zero(void) 9754 { 9755 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_USE_TSC_OFFSET); 9756 vmcs_write(TSC_OFFSET, -rdtsc()); 9757 } 9758 9759 static void rdtsc_vmexit_diff_test_guest(void) 9760 { 9761 int i; 9762 9763 for (i = 0; i < RDTSC_DIFF_ITERS; i++) 9764 /* Ensure rdtsc is the last instruction before the vmcall. */ 9765 asm volatile("rdtsc; vmcall" : : : "eax", "edx"); 9766 } 9767 9768 /* 9769 * This function only considers the "use TSC offsetting" VM-execution 9770 * control. It does not handle "use TSC scaling" (because the latter 9771 * isn't available to the host today.) 9772 */ 9773 static unsigned long long host_time_to_guest_time(unsigned long long t) 9774 { 9775 TEST_ASSERT(!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 9776 !(vmcs_read(CPU_EXEC_CTRL1) & CPU_USE_TSC_SCALING)); 9777 9778 if (vmcs_read(CPU_EXEC_CTRL0) & CPU_USE_TSC_OFFSET) 9779 t += vmcs_read(TSC_OFFSET); 9780 9781 return t; 9782 } 9783 9784 static unsigned long long rdtsc_vmexit_diff_test_iteration(void) 9785 { 9786 unsigned long long guest_tsc, host_to_guest_tsc; 9787 9788 enter_guest(); 9789 skip_exit_vmcall(); 9790 guest_tsc = (u32) regs.rax + (regs.rdx << 32); 9791 host_to_guest_tsc = host_time_to_guest_time(exit_msr_store[0].value); 9792 9793 return host_to_guest_tsc - guest_tsc; 9794 } 9795 9796 static void rdtsc_vmexit_diff_test(void) 9797 { 9798 unsigned long long delta; 9799 int fail = 0; 9800 int i; 9801 9802 if (!(ctrl_cpu_rev[0].clr & CPU_USE_TSC_OFFSET)) 9803 test_skip("CPU doesn't support the 'use TSC offsetting' processor-based VM-execution control.\n"); 9804 9805 test_set_guest(rdtsc_vmexit_diff_test_guest); 9806 9807 reset_guest_tsc_to_zero(); 9808 9809 /* 9810 * Set up the VMCS12 VM-exit MSR-store list to store just one 9811 * MSR: IA32_TIME_STAMP_COUNTER. Note that the value stored is 9812 * in the host time domain (i.e., it is not adjusted according 9813 * to the TSC multiplier and TSC offset fields in the VMCS12, 9814 * as a guest RDTSC would be.) 9815 */ 9816 exit_msr_store = alloc_page(); 9817 exit_msr_store[0].index = MSR_IA32_TSC; 9818 vmcs_write(EXI_MSR_ST_CNT, 1); 9819 vmcs_write(EXIT_MSR_ST_ADDR, virt_to_phys(exit_msr_store)); 9820 9821 for (i = 0; i < RDTSC_DIFF_ITERS && fail < RDTSC_DIFF_FAILS; i++) { 9822 delta = rdtsc_vmexit_diff_test_iteration(); 9823 if (delta >= HOST_CAPTURED_GUEST_TSC_DIFF_THRESHOLD) 9824 fail++; 9825 } 9826 9827 enter_guest(); 9828 9829 report(fail < RDTSC_DIFF_FAILS, 9830 "RDTSC to VM-exit delta too high in %d of %d iterations, last = %llu", 9831 fail, i, delta); 9832 } 9833 9834 static int invalid_msr_init(struct vmcs *vmcs) 9835 { 9836 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 9837 printf("\tPreemption timer is not supported\n"); 9838 return VMX_TEST_EXIT; 9839 } 9840 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 9841 preempt_val = 10000000; 9842 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 9843 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 9844 9845 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 9846 printf("\tSave preemption value is not supported\n"); 9847 9848 vmcs_write(ENT_MSR_LD_CNT, 1); 9849 vmcs_write(ENTER_MSR_LD_ADDR, (u64)0x13370000); 9850 9851 return VMX_TEST_START; 9852 } 9853 9854 9855 static void invalid_msr_main(void) 9856 { 9857 report(0, "Invalid MSR load"); 9858 } 9859 9860 static int invalid_msr_exit_handler(union exit_reason exit_reason) 9861 { 9862 report(0, "Invalid MSR load"); 9863 print_vmexit_info(exit_reason); 9864 return VMX_TEST_EXIT; 9865 } 9866 9867 static int invalid_msr_entry_failure(struct vmentry_result *result) 9868 { 9869 report(result->exit_reason.failed_vmentry && 9870 result->exit_reason.basic == VMX_FAIL_MSR, "Invalid MSR load"); 9871 return VMX_TEST_VMEXIT; 9872 } 9873 9874 /* 9875 * The max number of MSRs in an atomic switch MSR list is: 9876 * (111B + 1) * 512 = 4096 9877 * 9878 * Each list entry consumes: 9879 * 4-byte MSR index + 4 bytes reserved + 8-byte data = 16 bytes 9880 * 9881 * Allocate 128 kB to cover max_msr_list_size (i.e., 64 kB) and then some. 9882 */ 9883 static const u32 msr_list_page_order = 5; 9884 9885 static void atomic_switch_msr_limit_test_guest(void) 9886 { 9887 vmcall(); 9888 } 9889 9890 static void populate_msr_list(struct vmx_msr_entry *msr_list, 9891 size_t byte_capacity, int count) 9892 { 9893 int i; 9894 9895 for (i = 0; i < count; i++) { 9896 msr_list[i].index = MSR_IA32_TSC; 9897 msr_list[i].reserved = 0; 9898 msr_list[i].value = 0x1234567890abcdef; 9899 } 9900 9901 memset(msr_list + count, 0xff, 9902 byte_capacity - count * sizeof(*msr_list)); 9903 } 9904 9905 static int max_msr_list_size(void) 9906 { 9907 u32 vmx_misc = rdmsr(MSR_IA32_VMX_MISC); 9908 u32 factor = ((vmx_misc & GENMASK(27, 25)) >> 25) + 1; 9909 9910 return factor * 512; 9911 } 9912 9913 static void atomic_switch_msrs_test(int count) 9914 { 9915 struct vmx_msr_entry *vm_enter_load; 9916 struct vmx_msr_entry *vm_exit_load; 9917 struct vmx_msr_entry *vm_exit_store; 9918 int max_allowed = max_msr_list_size(); 9919 int byte_capacity = 1ul << (msr_list_page_order + PAGE_SHIFT); 9920 /* Exceeding the max MSR list size at exit trigers KVM to abort. */ 9921 int exit_count = count > max_allowed ? max_allowed : count; 9922 int cleanup_count = count > max_allowed ? 2 : 1; 9923 int i; 9924 9925 /* 9926 * Check for the IA32_TSC MSR, 9927 * available with the "TSC flag" and used to populate the MSR lists. 9928 */ 9929 if (!(cpuid(1).d & (1 << 4))) { 9930 report_skip(__func__); 9931 return; 9932 } 9933 9934 /* Set L2 guest. */ 9935 test_set_guest(atomic_switch_msr_limit_test_guest); 9936 9937 /* Setup atomic MSR switch lists. */ 9938 vm_enter_load = alloc_pages(msr_list_page_order); 9939 vm_exit_load = alloc_pages(msr_list_page_order); 9940 vm_exit_store = alloc_pages(msr_list_page_order); 9941 9942 vmcs_write(ENTER_MSR_LD_ADDR, (u64)vm_enter_load); 9943 vmcs_write(EXIT_MSR_LD_ADDR, (u64)vm_exit_load); 9944 vmcs_write(EXIT_MSR_ST_ADDR, (u64)vm_exit_store); 9945 9946 /* 9947 * VM-Enter should succeed up to the max number of MSRs per list, and 9948 * should not consume junk beyond the last entry. 9949 */ 9950 populate_msr_list(vm_enter_load, byte_capacity, count); 9951 populate_msr_list(vm_exit_load, byte_capacity, exit_count); 9952 populate_msr_list(vm_exit_store, byte_capacity, exit_count); 9953 9954 vmcs_write(ENT_MSR_LD_CNT, count); 9955 vmcs_write(EXI_MSR_LD_CNT, exit_count); 9956 vmcs_write(EXI_MSR_ST_CNT, exit_count); 9957 9958 if (count <= max_allowed) { 9959 enter_guest(); 9960 assert_exit_reason(VMX_VMCALL); 9961 skip_exit_vmcall(); 9962 } else { 9963 u32 exit_qual; 9964 9965 test_guest_state("Invalid MSR Load Count", true, count, 9966 "ENT_MSR_LD_CNT"); 9967 9968 exit_qual = vmcs_read(EXI_QUALIFICATION); 9969 report(exit_qual == max_allowed + 1, "exit_qual, %u, is %u.", 9970 exit_qual, max_allowed + 1); 9971 } 9972 9973 /* Cleanup. */ 9974 vmcs_write(ENT_MSR_LD_CNT, 0); 9975 vmcs_write(EXI_MSR_LD_CNT, 0); 9976 vmcs_write(EXI_MSR_ST_CNT, 0); 9977 for (i = 0; i < cleanup_count; i++) { 9978 enter_guest(); 9979 skip_exit_vmcall(); 9980 } 9981 free_pages_by_order(vm_enter_load, msr_list_page_order); 9982 free_pages_by_order(vm_exit_load, msr_list_page_order); 9983 free_pages_by_order(vm_exit_store, msr_list_page_order); 9984 } 9985 9986 static void atomic_switch_max_msrs_test(void) 9987 { 9988 atomic_switch_msrs_test(max_msr_list_size()); 9989 } 9990 9991 static void atomic_switch_overflow_msrs_test(void) 9992 { 9993 if (test_device_enabled()) 9994 atomic_switch_msrs_test(max_msr_list_size() + 1); 9995 else 9996 test_skip("Test is only supported on KVM"); 9997 } 9998 9999 #define TEST(name) { #name, .v2 = name } 10000 10001 /* name/init/guest_main/exit_handler/syscall_handler/guest_regs */ 10002 struct vmx_test vmx_tests[] = { 10003 { "null", NULL, basic_guest_main, basic_exit_handler, NULL, {0} }, 10004 { "vmenter", NULL, vmenter_main, vmenter_exit_handler, NULL, {0} }, 10005 { "preemption timer", preemption_timer_init, preemption_timer_main, 10006 preemption_timer_exit_handler, NULL, {0} }, 10007 { "control field PAT", test_ctrl_pat_init, test_ctrl_pat_main, 10008 test_ctrl_pat_exit_handler, NULL, {0} }, 10009 { "control field EFER", test_ctrl_efer_init, test_ctrl_efer_main, 10010 test_ctrl_efer_exit_handler, NULL, {0} }, 10011 { "CR shadowing", NULL, cr_shadowing_main, 10012 cr_shadowing_exit_handler, NULL, {0} }, 10013 { "I/O bitmap", iobmp_init, iobmp_main, iobmp_exit_handler, 10014 NULL, {0} }, 10015 { "instruction intercept", insn_intercept_init, insn_intercept_main, 10016 insn_intercept_exit_handler, NULL, {0} }, 10017 { "EPT A/D disabled", ept_init, ept_main, ept_exit_handler, NULL, {0} }, 10018 { "EPT A/D enabled", eptad_init, eptad_main, eptad_exit_handler, NULL, {0} }, 10019 { "PML", pml_init, pml_main, pml_exit_handler, NULL, {0} }, 10020 { "VPID", vpid_init, vpid_main, vpid_exit_handler, NULL, {0} }, 10021 { "interrupt", interrupt_init, interrupt_main, 10022 interrupt_exit_handler, NULL, {0} }, 10023 { "nmi_hlt", nmi_hlt_init, nmi_hlt_main, 10024 nmi_hlt_exit_handler, NULL, {0} }, 10025 { "debug controls", dbgctls_init, dbgctls_main, dbgctls_exit_handler, 10026 NULL, {0} }, 10027 { "MSR switch", msr_switch_init, msr_switch_main, 10028 msr_switch_exit_handler, NULL, {0}, msr_switch_entry_failure }, 10029 { "vmmcall", vmmcall_init, vmmcall_main, vmmcall_exit_handler, NULL, {0} }, 10030 { "disable RDTSCP", disable_rdtscp_init, disable_rdtscp_main, 10031 disable_rdtscp_exit_handler, NULL, {0} }, 10032 { "int3", int3_init, int3_guest_main, int3_exit_handler, NULL, {0} }, 10033 { "into", into_init, into_guest_main, into_exit_handler, NULL, {0} }, 10034 { "exit_monitor_from_l2_test", NULL, exit_monitor_from_l2_main, 10035 exit_monitor_from_l2_handler, NULL, {0} }, 10036 { "invalid_msr", invalid_msr_init, invalid_msr_main, 10037 invalid_msr_exit_handler, NULL, {0}, invalid_msr_entry_failure}, 10038 /* Basic V2 tests. */ 10039 TEST(v2_null_test), 10040 TEST(v2_multiple_entries_test), 10041 TEST(fixture_test_case1), 10042 TEST(fixture_test_case2), 10043 /* Opcode tests. */ 10044 TEST(invvpid_test_v2), 10045 /* VM-entry tests */ 10046 TEST(vmx_controls_test), 10047 TEST(vmx_host_state_area_test), 10048 TEST(vmx_guest_state_area_test), 10049 TEST(vmentry_movss_shadow_test), 10050 /* APICv tests */ 10051 TEST(vmx_eoi_bitmap_ioapic_scan_test), 10052 TEST(vmx_hlt_with_rvi_test), 10053 TEST(apic_reg_virt_test), 10054 TEST(virt_x2apic_mode_test), 10055 /* APIC pass-through tests */ 10056 TEST(vmx_apic_passthrough_test), 10057 TEST(vmx_apic_passthrough_thread_test), 10058 TEST(vmx_apic_passthrough_tpr_threshold_test), 10059 TEST(vmx_init_signal_test), 10060 /* VMCS Shadowing tests */ 10061 TEST(vmx_vmcs_shadow_test), 10062 /* Regression tests */ 10063 TEST(vmx_cr_load_test), 10064 TEST(vmx_nm_test), 10065 TEST(vmx_db_test), 10066 TEST(vmx_nmi_window_test), 10067 TEST(vmx_intr_window_test), 10068 TEST(vmx_pending_event_test), 10069 TEST(vmx_pending_event_hlt_test), 10070 TEST(vmx_store_tsc_test), 10071 TEST(vmx_preemption_timer_zero_test), 10072 TEST(vmx_preemption_timer_tf_test), 10073 TEST(vmx_preemption_timer_expiry_test), 10074 /* EPT access tests. */ 10075 TEST(ept_access_test_not_present), 10076 TEST(ept_access_test_read_only), 10077 TEST(ept_access_test_write_only), 10078 TEST(ept_access_test_read_write), 10079 TEST(ept_access_test_execute_only), 10080 TEST(ept_access_test_read_execute), 10081 TEST(ept_access_test_write_execute), 10082 TEST(ept_access_test_read_write_execute), 10083 TEST(ept_access_test_reserved_bits), 10084 TEST(ept_access_test_ignored_bits), 10085 TEST(ept_access_test_paddr_not_present_ad_disabled), 10086 TEST(ept_access_test_paddr_not_present_ad_enabled), 10087 TEST(ept_access_test_paddr_read_only_ad_disabled), 10088 TEST(ept_access_test_paddr_read_only_ad_enabled), 10089 TEST(ept_access_test_paddr_read_write), 10090 TEST(ept_access_test_paddr_read_write_execute), 10091 TEST(ept_access_test_paddr_read_execute_ad_disabled), 10092 TEST(ept_access_test_paddr_read_execute_ad_enabled), 10093 TEST(ept_access_test_paddr_not_present_page_fault), 10094 TEST(ept_access_test_force_2m_page), 10095 /* Atomic MSR switch tests. */ 10096 TEST(atomic_switch_max_msrs_test), 10097 TEST(atomic_switch_overflow_msrs_test), 10098 TEST(rdtsc_vmexit_diff_test), 10099 TEST(vmx_mtf_test), 10100 { NULL, NULL, NULL, NULL, NULL, {0} }, 10101 }; 10102