1 /* 2 * All test cases of nested virtualization should be in this file 3 * 4 * Author : Arthur Chunqi Li <yzt356@gmail.com> 5 */ 6 #include "vmx.h" 7 #include "msr.h" 8 #include "processor.h" 9 #include "vm.h" 10 #include "pci.h" 11 #include "fwcfg.h" 12 #include "isr.h" 13 #include "desc.h" 14 #include "apic.h" 15 #include "types.h" 16 #include "vmalloc.h" 17 #include "alloc_page.h" 18 #include "smp.h" 19 #include "delay.h" 20 21 #define NONCANONICAL 0xaaaaaaaaaaaaaaaaull 22 23 #define VPID_CAP_INVVPID_TYPES_SHIFT 40 24 25 u64 ia32_pat; 26 u64 ia32_efer; 27 void *io_bitmap_a, *io_bitmap_b; 28 u16 ioport; 29 30 unsigned long *pml4; 31 u64 eptp; 32 void *data_page1, *data_page2; 33 34 phys_addr_t pci_physaddr; 35 36 void *pml_log; 37 #define PML_INDEX 512 38 39 static inline unsigned ffs(unsigned x) 40 { 41 int pos = -1; 42 43 __asm__ __volatile__("bsf %1, %%eax; cmovnz %%eax, %0" 44 : "+r"(pos) : "rm"(x) : "eax"); 45 return pos + 1; 46 } 47 48 static inline void vmcall(void) 49 { 50 asm volatile("vmcall"); 51 } 52 53 static void basic_guest_main(void) 54 { 55 report("Basic VMX test", 1); 56 } 57 58 static int basic_exit_handler(void) 59 { 60 report("Basic VMX test", 0); 61 print_vmexit_info(); 62 return VMX_TEST_EXIT; 63 } 64 65 static void vmenter_main(void) 66 { 67 u64 rax; 68 u64 rsp, resume_rsp; 69 70 report("test vmlaunch", 1); 71 72 asm volatile( 73 "mov %%rsp, %0\n\t" 74 "mov %3, %%rax\n\t" 75 "vmcall\n\t" 76 "mov %%rax, %1\n\t" 77 "mov %%rsp, %2\n\t" 78 : "=r"(rsp), "=r"(rax), "=r"(resume_rsp) 79 : "g"(0xABCD)); 80 report("test vmresume", (rax == 0xFFFF) && (rsp == resume_rsp)); 81 } 82 83 static int vmenter_exit_handler(void) 84 { 85 u64 guest_rip; 86 ulong reason; 87 88 guest_rip = vmcs_read(GUEST_RIP); 89 reason = vmcs_read(EXI_REASON) & 0xff; 90 switch (reason) { 91 case VMX_VMCALL: 92 if (regs.rax != 0xABCD) { 93 report("test vmresume", 0); 94 return VMX_TEST_VMEXIT; 95 } 96 regs.rax = 0xFFFF; 97 vmcs_write(GUEST_RIP, guest_rip + 3); 98 return VMX_TEST_RESUME; 99 default: 100 report("test vmresume", 0); 101 print_vmexit_info(); 102 } 103 return VMX_TEST_VMEXIT; 104 } 105 106 u32 preempt_scale; 107 volatile unsigned long long tsc_val; 108 volatile u32 preempt_val; 109 u64 saved_rip; 110 111 static int preemption_timer_init(struct vmcs *vmcs) 112 { 113 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 114 printf("\tPreemption timer is not supported\n"); 115 return VMX_TEST_EXIT; 116 } 117 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 118 preempt_val = 10000000; 119 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 120 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 121 122 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 123 printf("\tSave preemption value is not supported\n"); 124 125 return VMX_TEST_START; 126 } 127 128 static void preemption_timer_main(void) 129 { 130 tsc_val = rdtsc(); 131 if (ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) { 132 vmx_set_test_stage(0); 133 vmcall(); 134 if (vmx_get_test_stage() == 1) 135 vmcall(); 136 } 137 vmx_set_test_stage(1); 138 while (vmx_get_test_stage() == 1) { 139 if (((rdtsc() - tsc_val) >> preempt_scale) 140 > 10 * preempt_val) { 141 vmx_set_test_stage(2); 142 vmcall(); 143 } 144 } 145 tsc_val = rdtsc(); 146 asm volatile ("hlt"); 147 vmcall(); 148 vmx_set_test_stage(5); 149 vmcall(); 150 } 151 152 static int preemption_timer_exit_handler(void) 153 { 154 bool guest_halted; 155 u64 guest_rip; 156 ulong reason; 157 u32 insn_len; 158 u32 ctrl_exit; 159 160 guest_rip = vmcs_read(GUEST_RIP); 161 reason = vmcs_read(EXI_REASON) & 0xff; 162 insn_len = vmcs_read(EXI_INST_LEN); 163 switch (reason) { 164 case VMX_PREEMPT: 165 switch (vmx_get_test_stage()) { 166 case 1: 167 case 2: 168 report("busy-wait for preemption timer", 169 ((rdtsc() - tsc_val) >> preempt_scale) >= 170 preempt_val); 171 vmx_set_test_stage(3); 172 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 173 return VMX_TEST_RESUME; 174 case 3: 175 guest_halted = 176 (vmcs_read(GUEST_ACTV_STATE) == ACTV_HLT); 177 report("preemption timer during hlt", 178 ((rdtsc() - tsc_val) >> preempt_scale) >= 179 preempt_val && guest_halted); 180 vmx_set_test_stage(4); 181 vmcs_write(PIN_CONTROLS, 182 vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 183 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 184 return VMX_TEST_RESUME; 185 case 4: 186 report("preemption timer with 0 value", 187 saved_rip == guest_rip); 188 break; 189 default: 190 report("Invalid stage.", false); 191 print_vmexit_info(); 192 break; 193 } 194 break; 195 case VMX_VMCALL: 196 vmcs_write(GUEST_RIP, guest_rip + insn_len); 197 switch (vmx_get_test_stage()) { 198 case 0: 199 report("Keep preemption value", 200 vmcs_read(PREEMPT_TIMER_VALUE) == preempt_val); 201 vmx_set_test_stage(1); 202 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 203 ctrl_exit = (vmcs_read(EXI_CONTROLS) | 204 EXI_SAVE_PREEMPT) & ctrl_exit_rev.clr; 205 vmcs_write(EXI_CONTROLS, ctrl_exit); 206 return VMX_TEST_RESUME; 207 case 1: 208 report("Save preemption value", 209 vmcs_read(PREEMPT_TIMER_VALUE) < preempt_val); 210 return VMX_TEST_RESUME; 211 case 2: 212 report("busy-wait for preemption timer", 0); 213 vmx_set_test_stage(3); 214 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 215 return VMX_TEST_RESUME; 216 case 3: 217 report("preemption timer during hlt", 0); 218 vmx_set_test_stage(4); 219 /* fall through */ 220 case 4: 221 vmcs_write(PIN_CONTROLS, 222 vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 223 vmcs_write(PREEMPT_TIMER_VALUE, 0); 224 saved_rip = guest_rip + insn_len; 225 return VMX_TEST_RESUME; 226 case 5: 227 report("preemption timer with 0 value (vmcall stage 5)", 0); 228 break; 229 default: 230 // Should not reach here 231 report("unexpected stage, %d", false, 232 vmx_get_test_stage()); 233 print_vmexit_info(); 234 return VMX_TEST_VMEXIT; 235 } 236 break; 237 default: 238 report("Unknown exit reason, %ld", false, reason); 239 print_vmexit_info(); 240 } 241 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 242 return VMX_TEST_VMEXIT; 243 } 244 245 static void msr_bmp_init(void) 246 { 247 void *msr_bitmap; 248 u32 ctrl_cpu0; 249 250 msr_bitmap = alloc_page(); 251 memset(msr_bitmap, 0x0, PAGE_SIZE); 252 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 253 ctrl_cpu0 |= CPU_MSR_BITMAP; 254 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 255 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 256 } 257 258 static int test_ctrl_pat_init(struct vmcs *vmcs) 259 { 260 u64 ctrl_ent; 261 u64 ctrl_exi; 262 263 msr_bmp_init(); 264 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT) && 265 !(ctrl_exit_rev.clr & EXI_LOAD_PAT) && 266 !(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 267 printf("\tSave/load PAT is not supported\n"); 268 return 1; 269 } 270 271 ctrl_ent = vmcs_read(ENT_CONTROLS); 272 ctrl_exi = vmcs_read(EXI_CONTROLS); 273 ctrl_ent |= ctrl_enter_rev.clr & ENT_LOAD_PAT; 274 ctrl_exi |= ctrl_exit_rev.clr & (EXI_SAVE_PAT | EXI_LOAD_PAT); 275 vmcs_write(ENT_CONTROLS, ctrl_ent); 276 vmcs_write(EXI_CONTROLS, ctrl_exi); 277 ia32_pat = rdmsr(MSR_IA32_CR_PAT); 278 vmcs_write(GUEST_PAT, 0x0); 279 vmcs_write(HOST_PAT, ia32_pat); 280 return VMX_TEST_START; 281 } 282 283 static void test_ctrl_pat_main(void) 284 { 285 u64 guest_ia32_pat; 286 287 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 288 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) 289 printf("\tENT_LOAD_PAT is not supported.\n"); 290 else { 291 if (guest_ia32_pat != 0) { 292 report("Entry load PAT", 0); 293 return; 294 } 295 } 296 wrmsr(MSR_IA32_CR_PAT, 0x6); 297 vmcall(); 298 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 299 if (ctrl_enter_rev.clr & ENT_LOAD_PAT) 300 report("Entry load PAT", guest_ia32_pat == ia32_pat); 301 } 302 303 static int test_ctrl_pat_exit_handler(void) 304 { 305 u64 guest_rip; 306 ulong reason; 307 u64 guest_pat; 308 309 guest_rip = vmcs_read(GUEST_RIP); 310 reason = vmcs_read(EXI_REASON) & 0xff; 311 switch (reason) { 312 case VMX_VMCALL: 313 guest_pat = vmcs_read(GUEST_PAT); 314 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT)) { 315 printf("\tEXI_SAVE_PAT is not supported\n"); 316 vmcs_write(GUEST_PAT, 0x6); 317 } else { 318 report("Exit save PAT", guest_pat == 0x6); 319 } 320 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) 321 printf("\tEXI_LOAD_PAT is not supported\n"); 322 else 323 report("Exit load PAT", rdmsr(MSR_IA32_CR_PAT) == ia32_pat); 324 vmcs_write(GUEST_PAT, ia32_pat); 325 vmcs_write(GUEST_RIP, guest_rip + 3); 326 return VMX_TEST_RESUME; 327 default: 328 printf("ERROR : Undefined exit reason, reason = %ld.\n", reason); 329 break; 330 } 331 return VMX_TEST_VMEXIT; 332 } 333 334 static int test_ctrl_efer_init(struct vmcs *vmcs) 335 { 336 u64 ctrl_ent; 337 u64 ctrl_exi; 338 339 msr_bmp_init(); 340 ctrl_ent = vmcs_read(ENT_CONTROLS) | ENT_LOAD_EFER; 341 ctrl_exi = vmcs_read(EXI_CONTROLS) | EXI_SAVE_EFER | EXI_LOAD_EFER; 342 vmcs_write(ENT_CONTROLS, ctrl_ent & ctrl_enter_rev.clr); 343 vmcs_write(EXI_CONTROLS, ctrl_exi & ctrl_exit_rev.clr); 344 ia32_efer = rdmsr(MSR_EFER); 345 vmcs_write(GUEST_EFER, ia32_efer ^ EFER_NX); 346 vmcs_write(HOST_EFER, ia32_efer ^ EFER_NX); 347 return VMX_TEST_START; 348 } 349 350 static void test_ctrl_efer_main(void) 351 { 352 u64 guest_ia32_efer; 353 354 guest_ia32_efer = rdmsr(MSR_EFER); 355 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) 356 printf("\tENT_LOAD_EFER is not supported.\n"); 357 else { 358 if (guest_ia32_efer != (ia32_efer ^ EFER_NX)) { 359 report("Entry load EFER", 0); 360 return; 361 } 362 } 363 wrmsr(MSR_EFER, ia32_efer); 364 vmcall(); 365 guest_ia32_efer = rdmsr(MSR_EFER); 366 if (ctrl_enter_rev.clr & ENT_LOAD_EFER) 367 report("Entry load EFER", guest_ia32_efer == ia32_efer); 368 } 369 370 static int test_ctrl_efer_exit_handler(void) 371 { 372 u64 guest_rip; 373 ulong reason; 374 u64 guest_efer; 375 376 guest_rip = vmcs_read(GUEST_RIP); 377 reason = vmcs_read(EXI_REASON) & 0xff; 378 switch (reason) { 379 case VMX_VMCALL: 380 guest_efer = vmcs_read(GUEST_EFER); 381 if (!(ctrl_exit_rev.clr & EXI_SAVE_EFER)) { 382 printf("\tEXI_SAVE_EFER is not supported\n"); 383 vmcs_write(GUEST_EFER, ia32_efer); 384 } else { 385 report("Exit save EFER", guest_efer == ia32_efer); 386 } 387 if (!(ctrl_exit_rev.clr & EXI_LOAD_EFER)) { 388 printf("\tEXI_LOAD_EFER is not supported\n"); 389 wrmsr(MSR_EFER, ia32_efer ^ EFER_NX); 390 } else { 391 report("Exit load EFER", rdmsr(MSR_EFER) == (ia32_efer ^ EFER_NX)); 392 } 393 vmcs_write(GUEST_PAT, ia32_efer); 394 vmcs_write(GUEST_RIP, guest_rip + 3); 395 return VMX_TEST_RESUME; 396 default: 397 printf("ERROR : Undefined exit reason, reason = %ld.\n", reason); 398 break; 399 } 400 return VMX_TEST_VMEXIT; 401 } 402 403 u32 guest_cr0, guest_cr4; 404 405 static void cr_shadowing_main(void) 406 { 407 u32 cr0, cr4, tmp; 408 409 // Test read through 410 vmx_set_test_stage(0); 411 guest_cr0 = read_cr0(); 412 if (vmx_get_test_stage() == 1) 413 report("Read through CR0", 0); 414 else 415 vmcall(); 416 vmx_set_test_stage(1); 417 guest_cr4 = read_cr4(); 418 if (vmx_get_test_stage() == 2) 419 report("Read through CR4", 0); 420 else 421 vmcall(); 422 // Test write through 423 guest_cr0 = guest_cr0 ^ (X86_CR0_TS | X86_CR0_MP); 424 guest_cr4 = guest_cr4 ^ (X86_CR4_TSD | X86_CR4_DE); 425 vmx_set_test_stage(2); 426 write_cr0(guest_cr0); 427 if (vmx_get_test_stage() == 3) 428 report("Write throuth CR0", 0); 429 else 430 vmcall(); 431 vmx_set_test_stage(3); 432 write_cr4(guest_cr4); 433 if (vmx_get_test_stage() == 4) 434 report("Write through CR4", 0); 435 else 436 vmcall(); 437 // Test read shadow 438 vmx_set_test_stage(4); 439 vmcall(); 440 cr0 = read_cr0(); 441 if (vmx_get_test_stage() != 5) 442 report("Read shadowing CR0", cr0 == guest_cr0); 443 vmx_set_test_stage(5); 444 cr4 = read_cr4(); 445 if (vmx_get_test_stage() != 6) 446 report("Read shadowing CR4", cr4 == guest_cr4); 447 // Test write shadow (same value with shadow) 448 vmx_set_test_stage(6); 449 write_cr0(guest_cr0); 450 if (vmx_get_test_stage() == 7) 451 report("Write shadowing CR0 (same value with shadow)", 0); 452 else 453 vmcall(); 454 vmx_set_test_stage(7); 455 write_cr4(guest_cr4); 456 if (vmx_get_test_stage() == 8) 457 report("Write shadowing CR4 (same value with shadow)", 0); 458 else 459 vmcall(); 460 // Test write shadow (different value) 461 vmx_set_test_stage(8); 462 tmp = guest_cr0 ^ X86_CR0_TS; 463 asm volatile("mov %0, %%rsi\n\t" 464 "mov %%rsi, %%cr0\n\t" 465 ::"m"(tmp) 466 :"rsi", "memory", "cc"); 467 report("Write shadowing different X86_CR0_TS", vmx_get_test_stage() == 9); 468 vmx_set_test_stage(9); 469 tmp = guest_cr0 ^ X86_CR0_MP; 470 asm volatile("mov %0, %%rsi\n\t" 471 "mov %%rsi, %%cr0\n\t" 472 ::"m"(tmp) 473 :"rsi", "memory", "cc"); 474 report("Write shadowing different X86_CR0_MP", vmx_get_test_stage() == 10); 475 vmx_set_test_stage(10); 476 tmp = guest_cr4 ^ X86_CR4_TSD; 477 asm volatile("mov %0, %%rsi\n\t" 478 "mov %%rsi, %%cr4\n\t" 479 ::"m"(tmp) 480 :"rsi", "memory", "cc"); 481 report("Write shadowing different X86_CR4_TSD", vmx_get_test_stage() == 11); 482 vmx_set_test_stage(11); 483 tmp = guest_cr4 ^ X86_CR4_DE; 484 asm volatile("mov %0, %%rsi\n\t" 485 "mov %%rsi, %%cr4\n\t" 486 ::"m"(tmp) 487 :"rsi", "memory", "cc"); 488 report("Write shadowing different X86_CR4_DE", vmx_get_test_stage() == 12); 489 } 490 491 static int cr_shadowing_exit_handler(void) 492 { 493 u64 guest_rip; 494 ulong reason; 495 u32 insn_len; 496 u32 exit_qual; 497 498 guest_rip = vmcs_read(GUEST_RIP); 499 reason = vmcs_read(EXI_REASON) & 0xff; 500 insn_len = vmcs_read(EXI_INST_LEN); 501 exit_qual = vmcs_read(EXI_QUALIFICATION); 502 switch (reason) { 503 case VMX_VMCALL: 504 switch (vmx_get_test_stage()) { 505 case 0: 506 report("Read through CR0", guest_cr0 == vmcs_read(GUEST_CR0)); 507 break; 508 case 1: 509 report("Read through CR4", guest_cr4 == vmcs_read(GUEST_CR4)); 510 break; 511 case 2: 512 report("Write through CR0", guest_cr0 == vmcs_read(GUEST_CR0)); 513 break; 514 case 3: 515 report("Write through CR4", guest_cr4 == vmcs_read(GUEST_CR4)); 516 break; 517 case 4: 518 guest_cr0 = vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP); 519 guest_cr4 = vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE); 520 vmcs_write(CR0_MASK, X86_CR0_TS | X86_CR0_MP); 521 vmcs_write(CR0_READ_SHADOW, guest_cr0 & (X86_CR0_TS | X86_CR0_MP)); 522 vmcs_write(CR4_MASK, X86_CR4_TSD | X86_CR4_DE); 523 vmcs_write(CR4_READ_SHADOW, guest_cr4 & (X86_CR4_TSD | X86_CR4_DE)); 524 break; 525 case 6: 526 report("Write shadowing CR0 (same value)", 527 guest_cr0 == (vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP))); 528 break; 529 case 7: 530 report("Write shadowing CR4 (same value)", 531 guest_cr4 == (vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE))); 532 break; 533 default: 534 // Should not reach here 535 report("unexpected stage, %d", false, 536 vmx_get_test_stage()); 537 print_vmexit_info(); 538 return VMX_TEST_VMEXIT; 539 } 540 vmcs_write(GUEST_RIP, guest_rip + insn_len); 541 return VMX_TEST_RESUME; 542 case VMX_CR: 543 switch (vmx_get_test_stage()) { 544 case 4: 545 report("Read shadowing CR0", 0); 546 vmx_inc_test_stage(); 547 break; 548 case 5: 549 report("Read shadowing CR4", 0); 550 vmx_inc_test_stage(); 551 break; 552 case 6: 553 report("Write shadowing CR0 (same value)", 0); 554 vmx_inc_test_stage(); 555 break; 556 case 7: 557 report("Write shadowing CR4 (same value)", 0); 558 vmx_inc_test_stage(); 559 break; 560 case 8: 561 case 9: 562 // 0x600 encodes "mov %esi, %cr0" 563 if (exit_qual == 0x600) 564 vmx_inc_test_stage(); 565 break; 566 case 10: 567 case 11: 568 // 0x604 encodes "mov %esi, %cr4" 569 if (exit_qual == 0x604) 570 vmx_inc_test_stage(); 571 break; 572 default: 573 // Should not reach here 574 report("unexpected stage, %d", false, 575 vmx_get_test_stage()); 576 print_vmexit_info(); 577 return VMX_TEST_VMEXIT; 578 } 579 vmcs_write(GUEST_RIP, guest_rip + insn_len); 580 return VMX_TEST_RESUME; 581 default: 582 report("Unknown exit reason, %ld", false, reason); 583 print_vmexit_info(); 584 } 585 return VMX_TEST_VMEXIT; 586 } 587 588 static int iobmp_init(struct vmcs *vmcs) 589 { 590 u32 ctrl_cpu0; 591 592 io_bitmap_a = alloc_page(); 593 io_bitmap_b = alloc_page(); 594 memset(io_bitmap_a, 0x0, PAGE_SIZE); 595 memset(io_bitmap_b, 0x0, PAGE_SIZE); 596 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 597 ctrl_cpu0 |= CPU_IO_BITMAP; 598 ctrl_cpu0 &= (~CPU_IO); 599 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 600 vmcs_write(IO_BITMAP_A, (u64)io_bitmap_a); 601 vmcs_write(IO_BITMAP_B, (u64)io_bitmap_b); 602 return VMX_TEST_START; 603 } 604 605 static void iobmp_main(void) 606 { 607 // stage 0, test IO pass 608 vmx_set_test_stage(0); 609 inb(0x5000); 610 outb(0x0, 0x5000); 611 report("I/O bitmap - I/O pass", vmx_get_test_stage() == 0); 612 // test IO width, in/out 613 ((u8 *)io_bitmap_a)[0] = 0xFF; 614 vmx_set_test_stage(2); 615 inb(0x0); 616 report("I/O bitmap - trap in", vmx_get_test_stage() == 3); 617 vmx_set_test_stage(3); 618 outw(0x0, 0x0); 619 report("I/O bitmap - trap out", vmx_get_test_stage() == 4); 620 vmx_set_test_stage(4); 621 inl(0x0); 622 report("I/O bitmap - I/O width, long", vmx_get_test_stage() == 5); 623 // test low/high IO port 624 vmx_set_test_stage(5); 625 ((u8 *)io_bitmap_a)[0x5000 / 8] = (1 << (0x5000 % 8)); 626 inb(0x5000); 627 report("I/O bitmap - I/O port, low part", vmx_get_test_stage() == 6); 628 vmx_set_test_stage(6); 629 ((u8 *)io_bitmap_b)[0x1000 / 8] = (1 << (0x1000 % 8)); 630 inb(0x9000); 631 report("I/O bitmap - I/O port, high part", vmx_get_test_stage() == 7); 632 // test partial pass 633 vmx_set_test_stage(7); 634 inl(0x4FFF); 635 report("I/O bitmap - partial pass", vmx_get_test_stage() == 8); 636 // test overrun 637 vmx_set_test_stage(8); 638 memset(io_bitmap_a, 0x0, PAGE_SIZE); 639 memset(io_bitmap_b, 0x0, PAGE_SIZE); 640 inl(0xFFFF); 641 report("I/O bitmap - overrun", vmx_get_test_stage() == 9); 642 vmx_set_test_stage(9); 643 vmcall(); 644 outb(0x0, 0x0); 645 report("I/O bitmap - ignore unconditional exiting", 646 vmx_get_test_stage() == 9); 647 vmx_set_test_stage(10); 648 vmcall(); 649 outb(0x0, 0x0); 650 report("I/O bitmap - unconditional exiting", 651 vmx_get_test_stage() == 11); 652 } 653 654 static int iobmp_exit_handler(void) 655 { 656 u64 guest_rip; 657 ulong reason, exit_qual; 658 u32 insn_len, ctrl_cpu0; 659 660 guest_rip = vmcs_read(GUEST_RIP); 661 reason = vmcs_read(EXI_REASON) & 0xff; 662 exit_qual = vmcs_read(EXI_QUALIFICATION); 663 insn_len = vmcs_read(EXI_INST_LEN); 664 switch (reason) { 665 case VMX_IO: 666 switch (vmx_get_test_stage()) { 667 case 0: 668 case 1: 669 vmx_inc_test_stage(); 670 break; 671 case 2: 672 report("I/O bitmap - I/O width, byte", 673 (exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_BYTE); 674 report("I/O bitmap - I/O direction, in", exit_qual & VMX_IO_IN); 675 vmx_inc_test_stage(); 676 break; 677 case 3: 678 report("I/O bitmap - I/O width, word", 679 (exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_WORD); 680 report("I/O bitmap - I/O direction, out", 681 !(exit_qual & VMX_IO_IN)); 682 vmx_inc_test_stage(); 683 break; 684 case 4: 685 report("I/O bitmap - I/O width, long", 686 (exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_LONG); 687 vmx_inc_test_stage(); 688 break; 689 case 5: 690 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x5000) 691 vmx_inc_test_stage(); 692 break; 693 case 6: 694 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x9000) 695 vmx_inc_test_stage(); 696 break; 697 case 7: 698 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x4FFF) 699 vmx_inc_test_stage(); 700 break; 701 case 8: 702 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0xFFFF) 703 vmx_inc_test_stage(); 704 break; 705 case 9: 706 case 10: 707 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 708 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0 & ~CPU_IO); 709 vmx_inc_test_stage(); 710 break; 711 default: 712 // Should not reach here 713 report("unexpected stage, %d", false, 714 vmx_get_test_stage()); 715 print_vmexit_info(); 716 return VMX_TEST_VMEXIT; 717 } 718 vmcs_write(GUEST_RIP, guest_rip + insn_len); 719 return VMX_TEST_RESUME; 720 case VMX_VMCALL: 721 switch (vmx_get_test_stage()) { 722 case 9: 723 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 724 ctrl_cpu0 |= CPU_IO | CPU_IO_BITMAP; 725 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 726 break; 727 case 10: 728 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 729 ctrl_cpu0 = (ctrl_cpu0 & ~CPU_IO_BITMAP) | CPU_IO; 730 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 731 break; 732 default: 733 // Should not reach here 734 report("unexpected stage, %d", false, 735 vmx_get_test_stage()); 736 print_vmexit_info(); 737 return VMX_TEST_VMEXIT; 738 } 739 vmcs_write(GUEST_RIP, guest_rip + insn_len); 740 return VMX_TEST_RESUME; 741 default: 742 printf("guest_rip = %#lx\n", guest_rip); 743 printf("\tERROR : Undefined exit reason, reason = %ld.\n", reason); 744 break; 745 } 746 return VMX_TEST_VMEXIT; 747 } 748 749 #define INSN_CPU0 0 750 #define INSN_CPU1 1 751 #define INSN_ALWAYS_TRAP 2 752 753 #define FIELD_EXIT_QUAL (1 << 0) 754 #define FIELD_INSN_INFO (1 << 1) 755 756 asm( 757 "insn_hlt: hlt;ret\n\t" 758 "insn_invlpg: invlpg 0x12345678;ret\n\t" 759 "insn_mwait: xor %eax, %eax; xor %ecx, %ecx; mwait;ret\n\t" 760 "insn_rdpmc: xor %ecx, %ecx; rdpmc;ret\n\t" 761 "insn_rdtsc: rdtsc;ret\n\t" 762 "insn_cr3_load: mov cr3,%rax; mov %rax,%cr3;ret\n\t" 763 "insn_cr3_store: mov %cr3,%rax;ret\n\t" 764 #ifdef __x86_64__ 765 "insn_cr8_load: xor %eax, %eax; mov %rax,%cr8;ret\n\t" 766 "insn_cr8_store: mov %cr8,%rax;ret\n\t" 767 #endif 768 "insn_monitor: xor %eax, %eax; xor %ecx, %ecx; xor %edx, %edx; monitor;ret\n\t" 769 "insn_pause: pause;ret\n\t" 770 "insn_wbinvd: wbinvd;ret\n\t" 771 "insn_cpuid: mov $10, %eax; cpuid;ret\n\t" 772 "insn_invd: invd;ret\n\t" 773 "insn_sgdt: sgdt gdt64_desc;ret\n\t" 774 "insn_lgdt: lgdt gdt64_desc;ret\n\t" 775 "insn_sidt: sidt idt_descr;ret\n\t" 776 "insn_lidt: lidt idt_descr;ret\n\t" 777 "insn_sldt: sldt %ax;ret\n\t" 778 "insn_lldt: xor %eax, %eax; lldt %ax;ret\n\t" 779 "insn_str: str %ax;ret\n\t" 780 "insn_rdrand: rdrand %rax;ret\n\t" 781 "insn_rdseed: rdseed %rax;ret\n\t" 782 ); 783 extern void insn_hlt(void); 784 extern void insn_invlpg(void); 785 extern void insn_mwait(void); 786 extern void insn_rdpmc(void); 787 extern void insn_rdtsc(void); 788 extern void insn_cr3_load(void); 789 extern void insn_cr3_store(void); 790 #ifdef __x86_64__ 791 extern void insn_cr8_load(void); 792 extern void insn_cr8_store(void); 793 #endif 794 extern void insn_monitor(void); 795 extern void insn_pause(void); 796 extern void insn_wbinvd(void); 797 extern void insn_sgdt(void); 798 extern void insn_lgdt(void); 799 extern void insn_sidt(void); 800 extern void insn_lidt(void); 801 extern void insn_sldt(void); 802 extern void insn_lldt(void); 803 extern void insn_str(void); 804 extern void insn_cpuid(void); 805 extern void insn_invd(void); 806 extern void insn_rdrand(void); 807 extern void insn_rdseed(void); 808 809 u32 cur_insn; 810 u64 cr3; 811 812 struct insn_table { 813 const char *name; 814 u32 flag; 815 void (*insn_func)(void); 816 u32 type; 817 u32 reason; 818 ulong exit_qual; 819 u32 insn_info; 820 // Use FIELD_EXIT_QUAL and FIELD_INSN_INFO to define 821 // which field need to be tested, reason is always tested 822 u32 test_field; 823 }; 824 825 /* 826 * Add more test cases of instruction intercept here. Elements in this 827 * table is: 828 * name/control flag/insn function/type/exit reason/exit qulification/ 829 * instruction info/field to test 830 * The last field defines which fields (exit_qual and insn_info) need to be 831 * tested in exit handler. If set to 0, only "reason" is checked. 832 */ 833 static struct insn_table insn_table[] = { 834 // Flags for Primary Processor-Based VM-Execution Controls 835 {"HLT", CPU_HLT, insn_hlt, INSN_CPU0, 12, 0, 0, 0}, 836 {"INVLPG", CPU_INVLPG, insn_invlpg, INSN_CPU0, 14, 837 0x12345678, 0, FIELD_EXIT_QUAL}, 838 {"MWAIT", CPU_MWAIT, insn_mwait, INSN_CPU0, 36, 0, 0, 0}, 839 {"RDPMC", CPU_RDPMC, insn_rdpmc, INSN_CPU0, 15, 0, 0, 0}, 840 {"RDTSC", CPU_RDTSC, insn_rdtsc, INSN_CPU0, 16, 0, 0, 0}, 841 {"CR3 load", CPU_CR3_LOAD, insn_cr3_load, INSN_CPU0, 28, 0x3, 0, 842 FIELD_EXIT_QUAL}, 843 {"CR3 store", CPU_CR3_STORE, insn_cr3_store, INSN_CPU0, 28, 0x13, 0, 844 FIELD_EXIT_QUAL}, 845 #ifdef __x86_64__ 846 {"CR8 load", CPU_CR8_LOAD, insn_cr8_load, INSN_CPU0, 28, 0x8, 0, 847 FIELD_EXIT_QUAL}, 848 {"CR8 store", CPU_CR8_STORE, insn_cr8_store, INSN_CPU0, 28, 0x18, 0, 849 FIELD_EXIT_QUAL}, 850 #endif 851 {"MONITOR", CPU_MONITOR, insn_monitor, INSN_CPU0, 39, 0, 0, 0}, 852 {"PAUSE", CPU_PAUSE, insn_pause, INSN_CPU0, 40, 0, 0, 0}, 853 // Flags for Secondary Processor-Based VM-Execution Controls 854 {"WBINVD", CPU_WBINVD, insn_wbinvd, INSN_CPU1, 54, 0, 0, 0}, 855 {"DESC_TABLE (SGDT)", CPU_DESC_TABLE, insn_sgdt, INSN_CPU1, 46, 0, 0, 0}, 856 {"DESC_TABLE (LGDT)", CPU_DESC_TABLE, insn_lgdt, INSN_CPU1, 46, 0, 0, 0}, 857 {"DESC_TABLE (SIDT)", CPU_DESC_TABLE, insn_sidt, INSN_CPU1, 46, 0, 0, 0}, 858 {"DESC_TABLE (LIDT)", CPU_DESC_TABLE, insn_lidt, INSN_CPU1, 46, 0, 0, 0}, 859 {"DESC_TABLE (SLDT)", CPU_DESC_TABLE, insn_sldt, INSN_CPU1, 47, 0, 0, 0}, 860 {"DESC_TABLE (LLDT)", CPU_DESC_TABLE, insn_lldt, INSN_CPU1, 47, 0, 0, 0}, 861 {"DESC_TABLE (STR)", CPU_DESC_TABLE, insn_str, INSN_CPU1, 47, 0, 0, 0}, 862 /* LTR causes a #GP if done with a busy selector, so it is not tested. */ 863 {"RDRAND", CPU_RDRAND, insn_rdrand, INSN_CPU1, VMX_RDRAND, 0, 0, 0}, 864 {"RDSEED", CPU_RDSEED, insn_rdseed, INSN_CPU1, VMX_RDSEED, 0, 0, 0}, 865 // Instructions always trap 866 {"CPUID", 0, insn_cpuid, INSN_ALWAYS_TRAP, 10, 0, 0, 0}, 867 {"INVD", 0, insn_invd, INSN_ALWAYS_TRAP, 13, 0, 0, 0}, 868 // Instructions never trap 869 {NULL}, 870 }; 871 872 static int insn_intercept_init(struct vmcs *vmcs) 873 { 874 u32 ctrl_cpu; 875 876 ctrl_cpu = ctrl_cpu_rev[0].set | CPU_SECONDARY; 877 ctrl_cpu &= ctrl_cpu_rev[0].clr; 878 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu); 879 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu_rev[1].set); 880 cr3 = read_cr3(); 881 return VMX_TEST_START; 882 } 883 884 static void insn_intercept_main(void) 885 { 886 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 887 vmx_set_test_stage(cur_insn * 2); 888 if ((insn_table[cur_insn].type == INSN_CPU0 && 889 !(ctrl_cpu_rev[0].clr & insn_table[cur_insn].flag)) || 890 (insn_table[cur_insn].type == INSN_CPU1 && 891 !(ctrl_cpu_rev[1].clr & insn_table[cur_insn].flag))) { 892 printf("\tCPU_CTRL%d.CPU_%s is not supported.\n", 893 insn_table[cur_insn].type - INSN_CPU0, 894 insn_table[cur_insn].name); 895 continue; 896 } 897 898 if ((insn_table[cur_insn].type == INSN_CPU0 && 899 !(ctrl_cpu_rev[0].set & insn_table[cur_insn].flag)) || 900 (insn_table[cur_insn].type == INSN_CPU1 && 901 !(ctrl_cpu_rev[1].set & insn_table[cur_insn].flag))) { 902 /* skip hlt, it stalls the guest and is tested below */ 903 if (insn_table[cur_insn].insn_func != insn_hlt) 904 insn_table[cur_insn].insn_func(); 905 report("execute %s", vmx_get_test_stage() == cur_insn * 2, 906 insn_table[cur_insn].name); 907 } else if (insn_table[cur_insn].type != INSN_ALWAYS_TRAP) 908 printf("\tCPU_CTRL%d.CPU_%s always traps.\n", 909 insn_table[cur_insn].type - INSN_CPU0, 910 insn_table[cur_insn].name); 911 912 vmcall(); 913 914 insn_table[cur_insn].insn_func(); 915 report("intercept %s", vmx_get_test_stage() == cur_insn * 2 + 1, 916 insn_table[cur_insn].name); 917 918 vmx_set_test_stage(cur_insn * 2 + 1); 919 vmcall(); 920 } 921 } 922 923 static int insn_intercept_exit_handler(void) 924 { 925 u64 guest_rip; 926 u32 reason; 927 ulong exit_qual; 928 u32 insn_len; 929 u32 insn_info; 930 bool pass; 931 932 guest_rip = vmcs_read(GUEST_RIP); 933 reason = vmcs_read(EXI_REASON) & 0xff; 934 exit_qual = vmcs_read(EXI_QUALIFICATION); 935 insn_len = vmcs_read(EXI_INST_LEN); 936 insn_info = vmcs_read(EXI_INST_INFO); 937 938 if (reason == VMX_VMCALL) { 939 u32 val = 0; 940 941 if (insn_table[cur_insn].type == INSN_CPU0) 942 val = vmcs_read(CPU_EXEC_CTRL0); 943 else if (insn_table[cur_insn].type == INSN_CPU1) 944 val = vmcs_read(CPU_EXEC_CTRL1); 945 946 if (vmx_get_test_stage() & 1) 947 val &= ~insn_table[cur_insn].flag; 948 else 949 val |= insn_table[cur_insn].flag; 950 951 if (insn_table[cur_insn].type == INSN_CPU0) 952 vmcs_write(CPU_EXEC_CTRL0, val | ctrl_cpu_rev[0].set); 953 else if (insn_table[cur_insn].type == INSN_CPU1) 954 vmcs_write(CPU_EXEC_CTRL1, val | ctrl_cpu_rev[1].set); 955 } else { 956 pass = (cur_insn * 2 == vmx_get_test_stage()) && 957 insn_table[cur_insn].reason == reason; 958 if (insn_table[cur_insn].test_field & FIELD_EXIT_QUAL && 959 insn_table[cur_insn].exit_qual != exit_qual) 960 pass = false; 961 if (insn_table[cur_insn].test_field & FIELD_INSN_INFO && 962 insn_table[cur_insn].insn_info != insn_info) 963 pass = false; 964 if (pass) 965 vmx_inc_test_stage(); 966 } 967 vmcs_write(GUEST_RIP, guest_rip + insn_len); 968 return VMX_TEST_RESUME; 969 } 970 971 972 /* Enables EPT and sets up the identity map. */ 973 static int setup_ept(bool enable_ad) 974 { 975 unsigned long end_of_memory; 976 u32 ctrl_cpu[2]; 977 978 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 979 !(ctrl_cpu_rev[1].clr & CPU_EPT)) { 980 printf("\tEPT is not supported"); 981 return 1; 982 } 983 984 985 if (!(ept_vpid.val & EPT_CAP_UC) && 986 !(ept_vpid.val & EPT_CAP_WB)) { 987 printf("\tEPT paging-structure memory type " 988 "UC&WB are not supported\n"); 989 return 1; 990 } 991 if (ept_vpid.val & EPT_CAP_UC) 992 eptp = EPT_MEM_TYPE_UC; 993 else 994 eptp = EPT_MEM_TYPE_WB; 995 if (!(ept_vpid.val & EPT_CAP_PWL4)) { 996 printf("\tPWL4 is not supported\n"); 997 return 1; 998 } 999 ctrl_cpu[0] = vmcs_read(CPU_EXEC_CTRL0); 1000 ctrl_cpu[1] = vmcs_read(CPU_EXEC_CTRL1); 1001 ctrl_cpu[0] = (ctrl_cpu[0] | CPU_SECONDARY) 1002 & ctrl_cpu_rev[0].clr; 1003 ctrl_cpu[1] = (ctrl_cpu[1] | CPU_EPT) 1004 & ctrl_cpu_rev[1].clr; 1005 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu[0]); 1006 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu[1]); 1007 eptp |= (3 << EPTP_PG_WALK_LEN_SHIFT); 1008 pml4 = alloc_page(); 1009 memset(pml4, 0, PAGE_SIZE); 1010 eptp |= virt_to_phys(pml4); 1011 if (enable_ad) 1012 eptp |= EPTP_AD_FLAG; 1013 vmcs_write(EPTP, eptp); 1014 end_of_memory = fwcfg_get_u64(FW_CFG_RAM_SIZE); 1015 if (end_of_memory < (1ul << 32)) 1016 end_of_memory = (1ul << 32); 1017 /* Cannot use large EPT pages if we need to track EPT 1018 * accessed/dirty bits at 4K granularity. 1019 */ 1020 setup_ept_range(pml4, 0, end_of_memory, 0, 1021 !enable_ad && ept_2m_supported(), 1022 EPT_WA | EPT_RA | EPT_EA); 1023 return 0; 1024 } 1025 1026 static void ept_enable_ad_bits(void) 1027 { 1028 eptp |= EPTP_AD_FLAG; 1029 vmcs_write(EPTP, eptp); 1030 } 1031 1032 static void ept_disable_ad_bits(void) 1033 { 1034 eptp &= ~EPTP_AD_FLAG; 1035 vmcs_write(EPTP, eptp); 1036 } 1037 1038 static void ept_enable_ad_bits_or_skip_test(void) 1039 { 1040 if (!ept_ad_bits_supported()) 1041 test_skip("EPT AD bits not supported."); 1042 ept_enable_ad_bits(); 1043 } 1044 1045 static int apic_version; 1046 1047 static int ept_init_common(bool have_ad) 1048 { 1049 int ret; 1050 struct pci_dev pcidev; 1051 1052 if (setup_ept(have_ad)) 1053 return VMX_TEST_EXIT; 1054 data_page1 = alloc_page(); 1055 data_page2 = alloc_page(); 1056 memset(data_page1, 0x0, PAGE_SIZE); 1057 memset(data_page2, 0x0, PAGE_SIZE); 1058 *((u32 *)data_page1) = MAGIC_VAL_1; 1059 *((u32 *)data_page2) = MAGIC_VAL_2; 1060 install_ept(pml4, (unsigned long)data_page1, (unsigned long)data_page2, 1061 EPT_RA | EPT_WA | EPT_EA); 1062 1063 apic_version = apic_read(APIC_LVR); 1064 1065 ret = pci_find_dev(PCI_VENDOR_ID_REDHAT, PCI_DEVICE_ID_REDHAT_TEST); 1066 if (ret != PCIDEVADDR_INVALID) { 1067 pci_dev_init(&pcidev, ret); 1068 pci_physaddr = pcidev.resource[PCI_TESTDEV_BAR_MEM]; 1069 } 1070 1071 return VMX_TEST_START; 1072 } 1073 1074 static int ept_init(struct vmcs *vmcs) 1075 { 1076 return ept_init_common(false); 1077 } 1078 1079 static void ept_common(void) 1080 { 1081 vmx_set_test_stage(0); 1082 if (*((u32 *)data_page2) != MAGIC_VAL_1 || 1083 *((u32 *)data_page1) != MAGIC_VAL_1) 1084 report("EPT basic framework - read", 0); 1085 else { 1086 *((u32 *)data_page2) = MAGIC_VAL_3; 1087 vmcall(); 1088 if (vmx_get_test_stage() == 1) { 1089 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1090 *((u32 *)data_page2) == MAGIC_VAL_2) 1091 report("EPT basic framework", 1); 1092 else 1093 report("EPT basic framework - remap", 1); 1094 } 1095 } 1096 // Test EPT Misconfigurations 1097 vmx_set_test_stage(1); 1098 vmcall(); 1099 *((u32 *)data_page1) = MAGIC_VAL_1; 1100 if (vmx_get_test_stage() != 2) { 1101 report("EPT misconfigurations", 0); 1102 goto t1; 1103 } 1104 vmx_set_test_stage(2); 1105 vmcall(); 1106 *((u32 *)data_page1) = MAGIC_VAL_1; 1107 report("EPT misconfigurations", vmx_get_test_stage() == 3); 1108 t1: 1109 // Test EPT violation 1110 vmx_set_test_stage(3); 1111 vmcall(); 1112 *((u32 *)data_page1) = MAGIC_VAL_1; 1113 report("EPT violation - page permission", vmx_get_test_stage() == 4); 1114 // Violation caused by EPT paging structure 1115 vmx_set_test_stage(4); 1116 vmcall(); 1117 *((u32 *)data_page1) = MAGIC_VAL_2; 1118 report("EPT violation - paging structure", vmx_get_test_stage() == 5); 1119 1120 // MMIO Read/Write 1121 vmx_set_test_stage(5); 1122 vmcall(); 1123 1124 *(u32 volatile *)pci_physaddr; 1125 report("MMIO EPT violation - read", vmx_get_test_stage() == 6); 1126 1127 *(u32 volatile *)pci_physaddr = MAGIC_VAL_1; 1128 report("MMIO EPT violation - write", vmx_get_test_stage() == 7); 1129 } 1130 1131 static void ept_main(void) 1132 { 1133 ept_common(); 1134 1135 // Test EPT access to L1 MMIO 1136 vmx_set_test_stage(7); 1137 report("EPT - MMIO access", *((u32 *)0xfee00030UL) == apic_version); 1138 1139 // Test invalid operand for INVEPT 1140 vmcall(); 1141 report("EPT - unsupported INVEPT", vmx_get_test_stage() == 8); 1142 } 1143 1144 static bool invept_test(int type, u64 eptp) 1145 { 1146 bool ret, supported; 1147 1148 supported = ept_vpid.val & (EPT_CAP_INVEPT_SINGLE >> INVEPT_SINGLE << type); 1149 ret = invept(type, eptp); 1150 1151 if (ret == !supported) 1152 return false; 1153 1154 if (!supported) 1155 printf("WARNING: unsupported invept passed!\n"); 1156 else 1157 printf("WARNING: invept failed!\n"); 1158 1159 return true; 1160 } 1161 1162 static int pml_exit_handler(void) 1163 { 1164 u16 index, count; 1165 ulong reason = vmcs_read(EXI_REASON) & 0xff; 1166 u64 *pmlbuf = pml_log; 1167 u64 guest_rip = vmcs_read(GUEST_RIP);; 1168 u64 guest_cr3 = vmcs_read(GUEST_CR3); 1169 u32 insn_len = vmcs_read(EXI_INST_LEN); 1170 1171 switch (reason) { 1172 case VMX_VMCALL: 1173 switch (vmx_get_test_stage()) { 1174 case 0: 1175 index = vmcs_read(GUEST_PML_INDEX); 1176 for (count = index + 1; count < PML_INDEX; count++) { 1177 if (pmlbuf[count] == (u64)data_page2) { 1178 vmx_inc_test_stage(); 1179 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1180 break; 1181 } 1182 } 1183 break; 1184 case 1: 1185 index = vmcs_read(GUEST_PML_INDEX); 1186 /* Keep clearing the dirty bit till a overflow */ 1187 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1188 break; 1189 default: 1190 report("unexpected stage, %d.", false, 1191 vmx_get_test_stage()); 1192 print_vmexit_info(); 1193 return VMX_TEST_VMEXIT; 1194 } 1195 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1196 return VMX_TEST_RESUME; 1197 case VMX_PML_FULL: 1198 vmx_inc_test_stage(); 1199 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1200 return VMX_TEST_RESUME; 1201 default: 1202 report("Unknown exit reason, %ld", false, reason); 1203 print_vmexit_info(); 1204 } 1205 return VMX_TEST_VMEXIT; 1206 } 1207 1208 static int ept_exit_handler_common(bool have_ad) 1209 { 1210 u64 guest_rip; 1211 u64 guest_cr3; 1212 ulong reason; 1213 u32 insn_len; 1214 u32 exit_qual; 1215 static unsigned long data_page1_pte, data_page1_pte_pte, memaddr_pte; 1216 1217 guest_rip = vmcs_read(GUEST_RIP); 1218 guest_cr3 = vmcs_read(GUEST_CR3); 1219 reason = vmcs_read(EXI_REASON) & 0xff; 1220 insn_len = vmcs_read(EXI_INST_LEN); 1221 exit_qual = vmcs_read(EXI_QUALIFICATION); 1222 switch (reason) { 1223 case VMX_VMCALL: 1224 switch (vmx_get_test_stage()) { 1225 case 0: 1226 check_ept_ad(pml4, guest_cr3, 1227 (unsigned long)data_page1, 1228 have_ad ? EPT_ACCESS_FLAG : 0, 1229 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1230 check_ept_ad(pml4, guest_cr3, 1231 (unsigned long)data_page2, 1232 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0, 1233 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1234 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1235 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1236 if (have_ad) 1237 ept_sync(INVEPT_SINGLE, eptp);; 1238 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1239 *((u32 *)data_page2) == MAGIC_VAL_2) { 1240 vmx_inc_test_stage(); 1241 install_ept(pml4, (unsigned long)data_page2, 1242 (unsigned long)data_page2, 1243 EPT_RA | EPT_WA | EPT_EA); 1244 } else 1245 report("EPT basic framework - write", 0); 1246 break; 1247 case 1: 1248 install_ept(pml4, (unsigned long)data_page1, 1249 (unsigned long)data_page1, EPT_WA); 1250 ept_sync(INVEPT_SINGLE, eptp); 1251 break; 1252 case 2: 1253 install_ept(pml4, (unsigned long)data_page1, 1254 (unsigned long)data_page1, 1255 EPT_RA | EPT_WA | EPT_EA | 1256 (2 << EPT_MEM_TYPE_SHIFT)); 1257 ept_sync(INVEPT_SINGLE, eptp); 1258 break; 1259 case 3: 1260 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1261 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)data_page1, 1262 1, &data_page1_pte)); 1263 set_ept_pte(pml4, (unsigned long)data_page1, 1264 1, data_page1_pte & ~EPT_PRESENT); 1265 ept_sync(INVEPT_SINGLE, eptp); 1266 break; 1267 case 4: 1268 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)data_page1, 1269 2, &data_page1_pte)); 1270 data_page1_pte &= PAGE_MASK; 1271 TEST_ASSERT(get_ept_pte(pml4, data_page1_pte, 1272 2, &data_page1_pte_pte)); 1273 set_ept_pte(pml4, data_page1_pte, 2, 1274 data_page1_pte_pte & ~EPT_PRESENT); 1275 ept_sync(INVEPT_SINGLE, eptp); 1276 break; 1277 case 5: 1278 install_ept(pml4, (unsigned long)pci_physaddr, 1279 (unsigned long)pci_physaddr, 0); 1280 ept_sync(INVEPT_SINGLE, eptp); 1281 break; 1282 case 7: 1283 if (!invept_test(0, eptp)) 1284 vmx_inc_test_stage(); 1285 break; 1286 // Should not reach here 1287 default: 1288 report("ERROR - unexpected stage, %d.", false, 1289 vmx_get_test_stage()); 1290 print_vmexit_info(); 1291 return VMX_TEST_VMEXIT; 1292 } 1293 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1294 return VMX_TEST_RESUME; 1295 case VMX_EPT_MISCONFIG: 1296 switch (vmx_get_test_stage()) { 1297 case 1: 1298 case 2: 1299 vmx_inc_test_stage(); 1300 install_ept(pml4, (unsigned long)data_page1, 1301 (unsigned long)data_page1, 1302 EPT_RA | EPT_WA | EPT_EA); 1303 ept_sync(INVEPT_SINGLE, eptp); 1304 break; 1305 // Should not reach here 1306 default: 1307 report("ERROR - unexpected stage, %d.", false, 1308 vmx_get_test_stage()); 1309 print_vmexit_info(); 1310 return VMX_TEST_VMEXIT; 1311 } 1312 return VMX_TEST_RESUME; 1313 case VMX_EPT_VIOLATION: 1314 switch(vmx_get_test_stage()) { 1315 case 3: 1316 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1317 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1318 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1319 if (exit_qual == (EPT_VLT_WR | EPT_VLT_LADDR_VLD | 1320 EPT_VLT_PADDR)) 1321 vmx_inc_test_stage(); 1322 set_ept_pte(pml4, (unsigned long)data_page1, 1323 1, data_page1_pte | (EPT_PRESENT)); 1324 ept_sync(INVEPT_SINGLE, eptp); 1325 break; 1326 case 4: 1327 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1328 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1329 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1330 if (exit_qual == (EPT_VLT_RD | 1331 (have_ad ? EPT_VLT_WR : 0) | 1332 EPT_VLT_LADDR_VLD)) 1333 vmx_inc_test_stage(); 1334 set_ept_pte(pml4, data_page1_pte, 2, 1335 data_page1_pte_pte | (EPT_PRESENT)); 1336 ept_sync(INVEPT_SINGLE, eptp); 1337 break; 1338 case 5: 1339 if (exit_qual & EPT_VLT_RD) 1340 vmx_inc_test_stage(); 1341 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1342 1, &memaddr_pte)); 1343 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA); 1344 ept_sync(INVEPT_SINGLE, eptp); 1345 break; 1346 case 6: 1347 if (exit_qual & EPT_VLT_WR) 1348 vmx_inc_test_stage(); 1349 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1350 1, &memaddr_pte)); 1351 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA | EPT_WA); 1352 ept_sync(INVEPT_SINGLE, eptp); 1353 break; 1354 default: 1355 // Should not reach here 1356 report("ERROR : unexpected stage, %d", false, 1357 vmx_get_test_stage()); 1358 print_vmexit_info(); 1359 return VMX_TEST_VMEXIT; 1360 } 1361 return VMX_TEST_RESUME; 1362 default: 1363 report("Unknown exit reason, %ld", false, reason); 1364 print_vmexit_info(); 1365 } 1366 return VMX_TEST_VMEXIT; 1367 } 1368 1369 static int ept_exit_handler(void) 1370 { 1371 return ept_exit_handler_common(false); 1372 } 1373 1374 static int eptad_init(struct vmcs *vmcs) 1375 { 1376 int r = ept_init_common(true); 1377 1378 if (r == VMX_TEST_EXIT) 1379 return r; 1380 1381 if ((rdmsr(MSR_IA32_VMX_EPT_VPID_CAP) & EPT_CAP_AD_FLAG) == 0) { 1382 printf("\tEPT A/D bits are not supported"); 1383 return VMX_TEST_EXIT; 1384 } 1385 1386 return r; 1387 } 1388 1389 static int pml_init(struct vmcs *vmcs) 1390 { 1391 u32 ctrl_cpu; 1392 int r = eptad_init(vmcs); 1393 1394 if (r == VMX_TEST_EXIT) 1395 return r; 1396 1397 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1398 !(ctrl_cpu_rev[1].clr & CPU_PML)) { 1399 printf("\tPML is not supported"); 1400 return VMX_TEST_EXIT; 1401 } 1402 1403 pml_log = alloc_page(); 1404 memset(pml_log, 0x0, PAGE_SIZE); 1405 vmcs_write(PMLADDR, (u64)pml_log); 1406 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1407 1408 ctrl_cpu = vmcs_read(CPU_EXEC_CTRL1) | CPU_PML; 1409 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu); 1410 1411 return VMX_TEST_START; 1412 } 1413 1414 static void pml_main(void) 1415 { 1416 int count = 0; 1417 1418 vmx_set_test_stage(0); 1419 *((u32 *)data_page2) = 0x1; 1420 vmcall(); 1421 report("PML - Dirty GPA Logging", vmx_get_test_stage() == 1); 1422 1423 while (vmx_get_test_stage() == 1) { 1424 vmcall(); 1425 *((u32 *)data_page2) = 0x1; 1426 if (count++ > PML_INDEX) 1427 break; 1428 } 1429 report("PML Full Event", vmx_get_test_stage() == 2); 1430 } 1431 1432 static void eptad_main(void) 1433 { 1434 ept_common(); 1435 } 1436 1437 static int eptad_exit_handler(void) 1438 { 1439 return ept_exit_handler_common(true); 1440 } 1441 1442 static bool invvpid_test(int type, u16 vpid) 1443 { 1444 bool ret, supported; 1445 1446 supported = ept_vpid.val & 1447 (VPID_CAP_INVVPID_ADDR >> INVVPID_ADDR << type); 1448 ret = invvpid(type, vpid, 0); 1449 1450 if (ret == !supported) 1451 return false; 1452 1453 if (!supported) 1454 printf("WARNING: unsupported invvpid passed!\n"); 1455 else 1456 printf("WARNING: invvpid failed!\n"); 1457 1458 return true; 1459 } 1460 1461 static int vpid_init(struct vmcs *vmcs) 1462 { 1463 u32 ctrl_cpu1; 1464 1465 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1466 !(ctrl_cpu_rev[1].clr & CPU_VPID)) { 1467 printf("\tVPID is not supported"); 1468 return VMX_TEST_EXIT; 1469 } 1470 1471 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 1472 ctrl_cpu1 |= CPU_VPID; 1473 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 1474 return VMX_TEST_START; 1475 } 1476 1477 static void vpid_main(void) 1478 { 1479 vmx_set_test_stage(0); 1480 vmcall(); 1481 report("INVVPID SINGLE ADDRESS", vmx_get_test_stage() == 1); 1482 vmx_set_test_stage(2); 1483 vmcall(); 1484 report("INVVPID SINGLE", vmx_get_test_stage() == 3); 1485 vmx_set_test_stage(4); 1486 vmcall(); 1487 report("INVVPID ALL", vmx_get_test_stage() == 5); 1488 } 1489 1490 static int vpid_exit_handler(void) 1491 { 1492 u64 guest_rip; 1493 ulong reason; 1494 u32 insn_len; 1495 1496 guest_rip = vmcs_read(GUEST_RIP); 1497 reason = vmcs_read(EXI_REASON) & 0xff; 1498 insn_len = vmcs_read(EXI_INST_LEN); 1499 1500 switch (reason) { 1501 case VMX_VMCALL: 1502 switch(vmx_get_test_stage()) { 1503 case 0: 1504 if (!invvpid_test(INVVPID_ADDR, 1)) 1505 vmx_inc_test_stage(); 1506 break; 1507 case 2: 1508 if (!invvpid_test(INVVPID_CONTEXT_GLOBAL, 1)) 1509 vmx_inc_test_stage(); 1510 break; 1511 case 4: 1512 if (!invvpid_test(INVVPID_ALL, 1)) 1513 vmx_inc_test_stage(); 1514 break; 1515 default: 1516 report("ERROR: unexpected stage, %d", false, 1517 vmx_get_test_stage()); 1518 print_vmexit_info(); 1519 return VMX_TEST_VMEXIT; 1520 } 1521 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1522 return VMX_TEST_RESUME; 1523 default: 1524 report("Unknown exit reason, %ld", false, reason); 1525 print_vmexit_info(); 1526 } 1527 return VMX_TEST_VMEXIT; 1528 } 1529 1530 #define TIMER_VECTOR 222 1531 1532 static volatile bool timer_fired; 1533 1534 static void timer_isr(isr_regs_t *regs) 1535 { 1536 timer_fired = true; 1537 apic_write(APIC_EOI, 0); 1538 } 1539 1540 static int interrupt_init(struct vmcs *vmcs) 1541 { 1542 msr_bmp_init(); 1543 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1544 handle_irq(TIMER_VECTOR, timer_isr); 1545 return VMX_TEST_START; 1546 } 1547 1548 static void interrupt_main(void) 1549 { 1550 long long start, loops; 1551 1552 vmx_set_test_stage(0); 1553 1554 apic_write(APIC_LVTT, TIMER_VECTOR); 1555 irq_enable(); 1556 1557 apic_write(APIC_TMICT, 1); 1558 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1559 asm volatile ("nop"); 1560 report("direct interrupt while running guest", timer_fired); 1561 1562 apic_write(APIC_TMICT, 0); 1563 irq_disable(); 1564 vmcall(); 1565 timer_fired = false; 1566 apic_write(APIC_TMICT, 1); 1567 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1568 asm volatile ("nop"); 1569 report("intercepted interrupt while running guest", timer_fired); 1570 1571 irq_enable(); 1572 apic_write(APIC_TMICT, 0); 1573 irq_disable(); 1574 vmcall(); 1575 timer_fired = false; 1576 start = rdtsc(); 1577 apic_write(APIC_TMICT, 1000000); 1578 1579 asm volatile ("sti; hlt"); 1580 1581 report("direct interrupt + hlt", 1582 rdtsc() - start > 1000000 && timer_fired); 1583 1584 apic_write(APIC_TMICT, 0); 1585 irq_disable(); 1586 vmcall(); 1587 timer_fired = false; 1588 start = rdtsc(); 1589 apic_write(APIC_TMICT, 1000000); 1590 1591 asm volatile ("sti; hlt"); 1592 1593 report("intercepted interrupt + hlt", 1594 rdtsc() - start > 10000 && timer_fired); 1595 1596 apic_write(APIC_TMICT, 0); 1597 irq_disable(); 1598 vmcall(); 1599 timer_fired = false; 1600 start = rdtsc(); 1601 apic_write(APIC_TMICT, 1000000); 1602 1603 irq_enable(); 1604 asm volatile ("nop"); 1605 vmcall(); 1606 1607 report("direct interrupt + activity state hlt", 1608 rdtsc() - start > 10000 && timer_fired); 1609 1610 apic_write(APIC_TMICT, 0); 1611 irq_disable(); 1612 vmcall(); 1613 timer_fired = false; 1614 start = rdtsc(); 1615 apic_write(APIC_TMICT, 1000000); 1616 1617 irq_enable(); 1618 asm volatile ("nop"); 1619 vmcall(); 1620 1621 report("intercepted interrupt + activity state hlt", 1622 rdtsc() - start > 10000 && timer_fired); 1623 1624 apic_write(APIC_TMICT, 0); 1625 irq_disable(); 1626 vmx_set_test_stage(7); 1627 vmcall(); 1628 timer_fired = false; 1629 apic_write(APIC_TMICT, 1); 1630 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1631 asm volatile ("nop"); 1632 report("running a guest with interrupt acknowledgement set", timer_fired); 1633 1634 apic_write(APIC_TMICT, 0); 1635 irq_enable(); 1636 timer_fired = false; 1637 vmcall(); 1638 report("Inject an event to a halted guest", timer_fired); 1639 } 1640 1641 static int interrupt_exit_handler(void) 1642 { 1643 u64 guest_rip = vmcs_read(GUEST_RIP); 1644 ulong reason = vmcs_read(EXI_REASON) & 0xff; 1645 u32 insn_len = vmcs_read(EXI_INST_LEN); 1646 1647 switch (reason) { 1648 case VMX_VMCALL: 1649 switch (vmx_get_test_stage()) { 1650 case 0: 1651 case 2: 1652 case 5: 1653 vmcs_write(PIN_CONTROLS, 1654 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1655 break; 1656 case 7: 1657 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_INTA); 1658 vmcs_write(PIN_CONTROLS, 1659 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1660 break; 1661 case 1: 1662 case 3: 1663 vmcs_write(PIN_CONTROLS, 1664 vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1665 break; 1666 case 4: 1667 case 6: 1668 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1669 break; 1670 1671 case 8: 1672 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1673 vmcs_write(ENT_INTR_INFO, 1674 TIMER_VECTOR | 1675 (VMX_INTR_TYPE_EXT_INTR << INTR_INFO_INTR_TYPE_SHIFT) | 1676 INTR_INFO_VALID_MASK); 1677 break; 1678 } 1679 vmx_inc_test_stage(); 1680 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1681 return VMX_TEST_RESUME; 1682 case VMX_EXTINT: 1683 if (vmcs_read(EXI_CONTROLS) & EXI_INTA) { 1684 int vector = vmcs_read(EXI_INTR_INFO) & 0xff; 1685 handle_external_interrupt(vector); 1686 } else { 1687 irq_enable(); 1688 asm volatile ("nop"); 1689 irq_disable(); 1690 } 1691 if (vmx_get_test_stage() >= 2) 1692 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 1693 return VMX_TEST_RESUME; 1694 default: 1695 report("Unknown exit reason, %ld", false, reason); 1696 print_vmexit_info(); 1697 } 1698 1699 return VMX_TEST_VMEXIT; 1700 } 1701 1702 static int dbgctls_init(struct vmcs *vmcs) 1703 { 1704 u64 dr7 = 0x402; 1705 u64 zero = 0; 1706 1707 msr_bmp_init(); 1708 asm volatile( 1709 "mov %0,%%dr0\n\t" 1710 "mov %0,%%dr1\n\t" 1711 "mov %0,%%dr2\n\t" 1712 "mov %1,%%dr7\n\t" 1713 : : "r" (zero), "r" (dr7)); 1714 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1715 vmcs_write(GUEST_DR7, 0x404); 1716 vmcs_write(GUEST_DEBUGCTL, 0x2); 1717 1718 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 1719 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_SAVE_DBGCTLS); 1720 1721 return VMX_TEST_START; 1722 } 1723 1724 static void dbgctls_main(void) 1725 { 1726 u64 dr7, debugctl; 1727 1728 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1729 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1730 /* Commented out: KVM does not support DEBUGCTL so far */ 1731 (void)debugctl; 1732 report("Load debug controls", dr7 == 0x404 /* && debugctl == 0x2 */); 1733 1734 dr7 = 0x408; 1735 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1736 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1737 1738 vmx_set_test_stage(0); 1739 vmcall(); 1740 report("Save debug controls", vmx_get_test_stage() == 1); 1741 1742 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS || 1743 ctrl_exit_rev.set & EXI_SAVE_DBGCTLS) { 1744 printf("\tDebug controls are always loaded/saved\n"); 1745 return; 1746 } 1747 vmx_set_test_stage(2); 1748 vmcall(); 1749 1750 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1751 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1752 /* Commented out: KVM does not support DEBUGCTL so far */ 1753 (void)debugctl; 1754 report("Guest=host debug controls", dr7 == 0x402 /* && debugctl == 0x1 */); 1755 1756 dr7 = 0x408; 1757 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1758 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1759 1760 vmx_set_test_stage(3); 1761 vmcall(); 1762 report("Don't save debug controls", vmx_get_test_stage() == 4); 1763 } 1764 1765 static int dbgctls_exit_handler(void) 1766 { 1767 unsigned int reason = vmcs_read(EXI_REASON) & 0xff; 1768 u32 insn_len = vmcs_read(EXI_INST_LEN); 1769 u64 guest_rip = vmcs_read(GUEST_RIP); 1770 u64 dr7, debugctl; 1771 1772 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1773 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1774 1775 switch (reason) { 1776 case VMX_VMCALL: 1777 switch (vmx_get_test_stage()) { 1778 case 0: 1779 if (dr7 == 0x400 && debugctl == 0 && 1780 vmcs_read(GUEST_DR7) == 0x408 /* && 1781 Commented out: KVM does not support DEBUGCTL so far 1782 vmcs_read(GUEST_DEBUGCTL) == 0x3 */) 1783 vmx_inc_test_stage(); 1784 break; 1785 case 2: 1786 dr7 = 0x402; 1787 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1788 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1789 vmcs_write(GUEST_DR7, 0x404); 1790 vmcs_write(GUEST_DEBUGCTL, 0x2); 1791 1792 vmcs_write(ENT_CONTROLS, 1793 vmcs_read(ENT_CONTROLS) & ~ENT_LOAD_DBGCTLS); 1794 vmcs_write(EXI_CONTROLS, 1795 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_DBGCTLS); 1796 break; 1797 case 3: 1798 if (dr7 == 0x400 && debugctl == 0 && 1799 vmcs_read(GUEST_DR7) == 0x404 /* && 1800 Commented out: KVM does not support DEBUGCTL so far 1801 vmcs_read(GUEST_DEBUGCTL) == 0x2 */) 1802 vmx_inc_test_stage(); 1803 break; 1804 } 1805 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1806 return VMX_TEST_RESUME; 1807 default: 1808 report("Unknown exit reason, %d", false, reason); 1809 print_vmexit_info(); 1810 } 1811 return VMX_TEST_VMEXIT; 1812 } 1813 1814 struct vmx_msr_entry { 1815 u32 index; 1816 u32 reserved; 1817 u64 value; 1818 } __attribute__((packed)); 1819 1820 #define MSR_MAGIC 0x31415926 1821 struct vmx_msr_entry *exit_msr_store, *entry_msr_load, *exit_msr_load; 1822 1823 static int msr_switch_init(struct vmcs *vmcs) 1824 { 1825 msr_bmp_init(); 1826 exit_msr_store = alloc_page(); 1827 exit_msr_load = alloc_page(); 1828 entry_msr_load = alloc_page(); 1829 memset(exit_msr_store, 0, PAGE_SIZE); 1830 memset(exit_msr_load, 0, PAGE_SIZE); 1831 memset(entry_msr_load, 0, PAGE_SIZE); 1832 entry_msr_load[0].index = MSR_KERNEL_GS_BASE; 1833 entry_msr_load[0].value = MSR_MAGIC; 1834 1835 vmx_set_test_stage(1); 1836 vmcs_write(ENT_MSR_LD_CNT, 1); 1837 vmcs_write(ENTER_MSR_LD_ADDR, (u64)entry_msr_load); 1838 vmcs_write(EXI_MSR_ST_CNT, 1); 1839 vmcs_write(EXIT_MSR_ST_ADDR, (u64)exit_msr_store); 1840 vmcs_write(EXI_MSR_LD_CNT, 1); 1841 vmcs_write(EXIT_MSR_LD_ADDR, (u64)exit_msr_load); 1842 return VMX_TEST_START; 1843 } 1844 1845 static void msr_switch_main(void) 1846 { 1847 if (vmx_get_test_stage() == 1) { 1848 report("VM entry MSR load", 1849 rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC); 1850 vmx_set_test_stage(2); 1851 wrmsr(MSR_KERNEL_GS_BASE, MSR_MAGIC + 1); 1852 exit_msr_store[0].index = MSR_KERNEL_GS_BASE; 1853 exit_msr_load[0].index = MSR_KERNEL_GS_BASE; 1854 exit_msr_load[0].value = MSR_MAGIC + 2; 1855 } 1856 vmcall(); 1857 } 1858 1859 static int msr_switch_exit_handler(void) 1860 { 1861 ulong reason; 1862 1863 reason = vmcs_read(EXI_REASON); 1864 if (reason == VMX_VMCALL && vmx_get_test_stage() == 2) { 1865 report("VM exit MSR store", 1866 exit_msr_store[0].value == MSR_MAGIC + 1); 1867 report("VM exit MSR load", 1868 rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC + 2); 1869 vmx_set_test_stage(3); 1870 entry_msr_load[0].index = MSR_FS_BASE; 1871 return VMX_TEST_RESUME; 1872 } 1873 printf("ERROR %s: unexpected stage=%u or reason=%lu\n", 1874 __func__, vmx_get_test_stage(), reason); 1875 return VMX_TEST_EXIT; 1876 } 1877 1878 static int msr_switch_entry_failure(struct vmentry_failure *failure) 1879 { 1880 ulong reason; 1881 1882 if (failure->early) { 1883 printf("ERROR %s: early exit\n", __func__); 1884 return VMX_TEST_EXIT; 1885 } 1886 1887 reason = vmcs_read(EXI_REASON); 1888 if (reason == (VMX_ENTRY_FAILURE | VMX_FAIL_MSR) && 1889 vmx_get_test_stage() == 3) { 1890 report("VM entry MSR load: try to load FS_BASE", 1891 vmcs_read(EXI_QUALIFICATION) == 1); 1892 return VMX_TEST_VMEXIT; 1893 } 1894 printf("ERROR %s: unexpected stage=%u or reason=%lu\n", 1895 __func__, vmx_get_test_stage(), reason); 1896 return VMX_TEST_EXIT; 1897 } 1898 1899 static int vmmcall_init(struct vmcs *vmcs) 1900 { 1901 vmcs_write(EXC_BITMAP, 1 << UD_VECTOR); 1902 return VMX_TEST_START; 1903 } 1904 1905 static void vmmcall_main(void) 1906 { 1907 asm volatile( 1908 "mov $0xABCD, %%rax\n\t" 1909 "vmmcall\n\t" 1910 ::: "rax"); 1911 1912 report("VMMCALL", 0); 1913 } 1914 1915 static int vmmcall_exit_handler(void) 1916 { 1917 ulong reason; 1918 1919 reason = vmcs_read(EXI_REASON); 1920 switch (reason) { 1921 case VMX_VMCALL: 1922 printf("here\n"); 1923 report("VMMCALL triggers #UD", 0); 1924 break; 1925 case VMX_EXC_NMI: 1926 report("VMMCALL triggers #UD", 1927 (vmcs_read(EXI_INTR_INFO) & 0xff) == UD_VECTOR); 1928 break; 1929 default: 1930 report("Unknown exit reason, %ld", false, reason); 1931 print_vmexit_info(); 1932 } 1933 1934 return VMX_TEST_VMEXIT; 1935 } 1936 1937 static int disable_rdtscp_init(struct vmcs *vmcs) 1938 { 1939 u32 ctrl_cpu1; 1940 1941 if (ctrl_cpu_rev[0].clr & CPU_SECONDARY) { 1942 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 1943 ctrl_cpu1 &= ~CPU_RDTSCP; 1944 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 1945 } 1946 1947 return VMX_TEST_START; 1948 } 1949 1950 static void disable_rdtscp_ud_handler(struct ex_regs *regs) 1951 { 1952 switch (vmx_get_test_stage()) { 1953 case 0: 1954 report("RDTSCP triggers #UD", true); 1955 vmx_inc_test_stage(); 1956 regs->rip += 3; 1957 break; 1958 case 2: 1959 report("RDPID triggers #UD", true); 1960 vmx_inc_test_stage(); 1961 regs->rip += 4; 1962 break; 1963 } 1964 return; 1965 1966 } 1967 1968 static void disable_rdtscp_main(void) 1969 { 1970 /* Test that #UD is properly injected in L2. */ 1971 handle_exception(UD_VECTOR, disable_rdtscp_ud_handler); 1972 1973 vmx_set_test_stage(0); 1974 asm volatile("rdtscp" : : : "eax", "ecx", "edx"); 1975 vmcall(); 1976 asm volatile(".byte 0xf3, 0x0f, 0xc7, 0xf8" : : : "eax"); 1977 1978 handle_exception(UD_VECTOR, 0); 1979 vmcall(); 1980 } 1981 1982 static int disable_rdtscp_exit_handler(void) 1983 { 1984 unsigned int reason = vmcs_read(EXI_REASON) & 0xff; 1985 1986 switch (reason) { 1987 case VMX_VMCALL: 1988 switch (vmx_get_test_stage()) { 1989 case 0: 1990 report("RDTSCP triggers #UD", false); 1991 vmx_inc_test_stage(); 1992 /* fallthrough */ 1993 case 1: 1994 vmx_inc_test_stage(); 1995 vmcs_write(GUEST_RIP, vmcs_read(GUEST_RIP) + 3); 1996 return VMX_TEST_RESUME; 1997 case 2: 1998 report("RDPID triggers #UD", false); 1999 break; 2000 } 2001 break; 2002 2003 default: 2004 report("Unknown exit reason, %d", false, reason); 2005 print_vmexit_info(); 2006 } 2007 return VMX_TEST_VMEXIT; 2008 } 2009 2010 static int int3_init(struct vmcs *vmcs) 2011 { 2012 vmcs_write(EXC_BITMAP, ~0u); 2013 return VMX_TEST_START; 2014 } 2015 2016 static void int3_guest_main(void) 2017 { 2018 asm volatile ("int3"); 2019 } 2020 2021 static int int3_exit_handler(void) 2022 { 2023 u32 reason = vmcs_read(EXI_REASON); 2024 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2025 2026 report("L1 intercepts #BP", reason == VMX_EXC_NMI && 2027 (intr_info & INTR_INFO_VALID_MASK) && 2028 (intr_info & INTR_INFO_VECTOR_MASK) == BP_VECTOR && 2029 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2030 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION); 2031 2032 return VMX_TEST_VMEXIT; 2033 } 2034 2035 static int into_init(struct vmcs *vmcs) 2036 { 2037 vmcs_write(EXC_BITMAP, ~0u); 2038 return VMX_TEST_START; 2039 } 2040 2041 static void into_guest_main(void) 2042 { 2043 struct far_pointer32 fp = { 2044 .offset = (uintptr_t)&&into, 2045 .selector = KERNEL_CS32, 2046 }; 2047 register uintptr_t rsp asm("rsp"); 2048 2049 if (fp.offset != (uintptr_t)&&into) { 2050 printf("Code address too high.\n"); 2051 return; 2052 } 2053 if ((u32)rsp != rsp) { 2054 printf("Stack address too high.\n"); 2055 return; 2056 } 2057 2058 asm goto ("lcall *%0" : : "m" (fp) : "rax" : into); 2059 return; 2060 into: 2061 asm volatile (".code32;" 2062 "movl $0x7fffffff, %eax;" 2063 "addl %eax, %eax;" 2064 "into;" 2065 "lret;" 2066 ".code64"); 2067 __builtin_unreachable(); 2068 } 2069 2070 static int into_exit_handler(void) 2071 { 2072 u32 reason = vmcs_read(EXI_REASON); 2073 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2074 2075 report("L1 intercepts #OF", reason == VMX_EXC_NMI && 2076 (intr_info & INTR_INFO_VALID_MASK) && 2077 (intr_info & INTR_INFO_VECTOR_MASK) == OF_VECTOR && 2078 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2079 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION); 2080 2081 return VMX_TEST_VMEXIT; 2082 } 2083 2084 static void exit_monitor_from_l2_main(void) 2085 { 2086 printf("Calling exit(0) from l2...\n"); 2087 exit(0); 2088 } 2089 2090 static int exit_monitor_from_l2_handler(void) 2091 { 2092 report("The guest should have killed the VMM", false); 2093 return VMX_TEST_EXIT; 2094 } 2095 2096 static void assert_exit_reason(u64 expected) 2097 { 2098 u64 actual = vmcs_read(EXI_REASON); 2099 2100 TEST_ASSERT_EQ_MSG(expected, actual, "Expected %s, got %s.", 2101 exit_reason_description(expected), 2102 exit_reason_description(actual)); 2103 } 2104 2105 static void skip_exit_insn(void) 2106 { 2107 u64 guest_rip = vmcs_read(GUEST_RIP); 2108 u32 insn_len = vmcs_read(EXI_INST_LEN); 2109 vmcs_write(GUEST_RIP, guest_rip + insn_len); 2110 } 2111 2112 static void skip_exit_vmcall(void) 2113 { 2114 assert_exit_reason(VMX_VMCALL); 2115 skip_exit_insn(); 2116 } 2117 2118 static void v2_null_test_guest(void) 2119 { 2120 } 2121 2122 static void v2_null_test(void) 2123 { 2124 test_set_guest(v2_null_test_guest); 2125 enter_guest(); 2126 report(__func__, 1); 2127 } 2128 2129 static void v2_multiple_entries_test_guest(void) 2130 { 2131 vmx_set_test_stage(1); 2132 vmcall(); 2133 vmx_set_test_stage(2); 2134 } 2135 2136 static void v2_multiple_entries_test(void) 2137 { 2138 test_set_guest(v2_multiple_entries_test_guest); 2139 enter_guest(); 2140 TEST_ASSERT_EQ(vmx_get_test_stage(), 1); 2141 skip_exit_vmcall(); 2142 enter_guest(); 2143 TEST_ASSERT_EQ(vmx_get_test_stage(), 2); 2144 report(__func__, 1); 2145 } 2146 2147 static int fixture_test_data = 1; 2148 2149 static void fixture_test_teardown(void *data) 2150 { 2151 *((int *) data) = 1; 2152 } 2153 2154 static void fixture_test_guest(void) 2155 { 2156 fixture_test_data++; 2157 } 2158 2159 2160 static void fixture_test_setup(void) 2161 { 2162 TEST_ASSERT_EQ_MSG(1, fixture_test_data, 2163 "fixture_test_teardown didn't run?!"); 2164 fixture_test_data = 2; 2165 test_add_teardown(fixture_test_teardown, &fixture_test_data); 2166 test_set_guest(fixture_test_guest); 2167 } 2168 2169 static void fixture_test_case1(void) 2170 { 2171 fixture_test_setup(); 2172 TEST_ASSERT_EQ(2, fixture_test_data); 2173 enter_guest(); 2174 TEST_ASSERT_EQ(3, fixture_test_data); 2175 report(__func__, 1); 2176 } 2177 2178 static void fixture_test_case2(void) 2179 { 2180 fixture_test_setup(); 2181 TEST_ASSERT_EQ(2, fixture_test_data); 2182 enter_guest(); 2183 TEST_ASSERT_EQ(3, fixture_test_data); 2184 report(__func__, 1); 2185 } 2186 2187 enum ept_access_op { 2188 OP_READ, 2189 OP_WRITE, 2190 OP_EXEC, 2191 OP_FLUSH_TLB, 2192 OP_EXIT, 2193 }; 2194 2195 static struct ept_access_test_data { 2196 unsigned long gpa; 2197 unsigned long *gva; 2198 unsigned long hpa; 2199 unsigned long *hva; 2200 enum ept_access_op op; 2201 } ept_access_test_data; 2202 2203 extern unsigned char ret42_start; 2204 extern unsigned char ret42_end; 2205 2206 /* Returns 42. */ 2207 asm( 2208 ".align 64\n" 2209 "ret42_start:\n" 2210 "mov $42, %eax\n" 2211 "ret\n" 2212 "ret42_end:\n" 2213 ); 2214 2215 static void 2216 diagnose_ept_violation_qual(u64 expected, u64 actual) 2217 { 2218 2219 #define DIAGNOSE(flag) \ 2220 do { \ 2221 if ((expected & flag) != (actual & flag)) \ 2222 printf(#flag " %sexpected\n", \ 2223 (expected & flag) ? "" : "un"); \ 2224 } while (0) 2225 2226 DIAGNOSE(EPT_VLT_RD); 2227 DIAGNOSE(EPT_VLT_WR); 2228 DIAGNOSE(EPT_VLT_FETCH); 2229 DIAGNOSE(EPT_VLT_PERM_RD); 2230 DIAGNOSE(EPT_VLT_PERM_WR); 2231 DIAGNOSE(EPT_VLT_PERM_EX); 2232 DIAGNOSE(EPT_VLT_LADDR_VLD); 2233 DIAGNOSE(EPT_VLT_PADDR); 2234 2235 #undef DIAGNOSE 2236 } 2237 2238 static void do_ept_access_op(enum ept_access_op op) 2239 { 2240 ept_access_test_data.op = op; 2241 enter_guest(); 2242 } 2243 2244 /* 2245 * Force the guest to flush its TLB (i.e., flush gva -> gpa mappings). Only 2246 * needed by tests that modify guest PTEs. 2247 */ 2248 static void ept_access_test_guest_flush_tlb(void) 2249 { 2250 do_ept_access_op(OP_FLUSH_TLB); 2251 skip_exit_vmcall(); 2252 } 2253 2254 /* 2255 * Modifies the EPT entry at @level in the mapping of @gpa. First clears the 2256 * bits in @clear then sets the bits in @set. @mkhuge transforms the entry into 2257 * a huge page. 2258 */ 2259 static unsigned long ept_twiddle(unsigned long gpa, bool mkhuge, int level, 2260 unsigned long clear, unsigned long set) 2261 { 2262 struct ept_access_test_data *data = &ept_access_test_data; 2263 unsigned long orig_pte; 2264 unsigned long pte; 2265 2266 /* Screw with the mapping at the requested level. */ 2267 TEST_ASSERT(get_ept_pte(pml4, gpa, level, &orig_pte)); 2268 pte = orig_pte; 2269 if (mkhuge) 2270 pte = (orig_pte & ~EPT_ADDR_MASK) | data->hpa | EPT_LARGE_PAGE; 2271 else 2272 pte = orig_pte; 2273 pte = (pte & ~clear) | set; 2274 set_ept_pte(pml4, gpa, level, pte); 2275 ept_sync(INVEPT_SINGLE, eptp); 2276 2277 return orig_pte; 2278 } 2279 2280 static void ept_untwiddle(unsigned long gpa, int level, unsigned long orig_pte) 2281 { 2282 set_ept_pte(pml4, gpa, level, orig_pte); 2283 } 2284 2285 static void do_ept_violation(bool leaf, enum ept_access_op op, 2286 u64 expected_qual, u64 expected_paddr) 2287 { 2288 u64 qual; 2289 2290 /* Try the access and observe the violation. */ 2291 do_ept_access_op(op); 2292 2293 assert_exit_reason(VMX_EPT_VIOLATION); 2294 2295 qual = vmcs_read(EXI_QUALIFICATION); 2296 2297 diagnose_ept_violation_qual(expected_qual, qual); 2298 TEST_EXPECT_EQ(expected_qual, qual); 2299 2300 #if 0 2301 /* Disable for now otherwise every test will fail */ 2302 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2303 (unsigned long) ( 2304 op == OP_EXEC ? data->gva + 1 : data->gva)); 2305 #endif 2306 /* 2307 * TODO: tests that probe expected_paddr in pages other than the one at 2308 * the beginning of the 1g region. 2309 */ 2310 TEST_EXPECT_EQ(vmcs_read(INFO_PHYS_ADDR), expected_paddr); 2311 } 2312 2313 static void 2314 ept_violation_at_level_mkhuge(bool mkhuge, int level, unsigned long clear, 2315 unsigned long set, enum ept_access_op op, 2316 u64 expected_qual) 2317 { 2318 struct ept_access_test_data *data = &ept_access_test_data; 2319 unsigned long orig_pte; 2320 2321 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2322 2323 do_ept_violation(level == 1 || mkhuge, op, expected_qual, 2324 op == OP_EXEC ? data->gpa + sizeof(unsigned long) : 2325 data->gpa); 2326 2327 /* Fix the violation and resume the op loop. */ 2328 ept_untwiddle(data->gpa, level, orig_pte); 2329 enter_guest(); 2330 skip_exit_vmcall(); 2331 } 2332 2333 static void 2334 ept_violation_at_level(int level, unsigned long clear, unsigned long set, 2335 enum ept_access_op op, u64 expected_qual) 2336 { 2337 ept_violation_at_level_mkhuge(false, level, clear, set, op, 2338 expected_qual); 2339 if (ept_huge_pages_supported(level)) 2340 ept_violation_at_level_mkhuge(true, level, clear, set, op, 2341 expected_qual); 2342 } 2343 2344 static void ept_violation(unsigned long clear, unsigned long set, 2345 enum ept_access_op op, u64 expected_qual) 2346 { 2347 ept_violation_at_level(1, clear, set, op, expected_qual); 2348 ept_violation_at_level(2, clear, set, op, expected_qual); 2349 ept_violation_at_level(3, clear, set, op, expected_qual); 2350 ept_violation_at_level(4, clear, set, op, expected_qual); 2351 } 2352 2353 static void ept_access_violation(unsigned long access, enum ept_access_op op, 2354 u64 expected_qual) 2355 { 2356 ept_violation(EPT_PRESENT, access, op, 2357 expected_qual | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2358 } 2359 2360 /* 2361 * For translations that don't involve a GVA, that is physical address (paddr) 2362 * accesses, EPT violations don't set the flag EPT_VLT_PADDR. For a typical 2363 * guest memory access, the hardware does GVA -> GPA -> HPA. However, certain 2364 * translations don't involve GVAs, such as when the hardware does the guest 2365 * page table walk. For example, in translating GVA_1 -> GPA_1, the guest MMU 2366 * might try to set an A bit on a guest PTE. If the GPA_2 that the PTE resides 2367 * on isn't present in the EPT, then the EPT violation will be for GPA_2 and 2368 * the EPT_VLT_PADDR bit will be clear in the exit qualification. 2369 * 2370 * Note that paddr violations can also be triggered by loading PAE page tables 2371 * with wonky addresses. We don't test that yet. 2372 * 2373 * This function modifies the EPT entry that maps the GPA that the guest page 2374 * table entry mapping ept_access_data.gva resides on. 2375 * 2376 * @ept_access EPT permissions to set. Other permissions are cleared. 2377 * 2378 * @pte_ad Set the A/D bits on the guest PTE accordingly. 2379 * 2380 * @op Guest operation to perform with ept_access_data.gva. 2381 * 2382 * @expect_violation 2383 * Is a violation expected during the paddr access? 2384 * 2385 * @expected_qual Expected qualification for the EPT violation. 2386 * EPT_VLT_PADDR should be clear. 2387 */ 2388 static void ept_access_paddr(unsigned long ept_access, unsigned long pte_ad, 2389 enum ept_access_op op, bool expect_violation, 2390 u64 expected_qual) 2391 { 2392 struct ept_access_test_data *data = &ept_access_test_data; 2393 unsigned long *ptep; 2394 unsigned long gpa; 2395 unsigned long orig_epte; 2396 2397 /* Modify the guest PTE mapping data->gva according to @pte_ad. */ 2398 ptep = get_pte_level(current_page_table(), data->gva, /*level=*/1); 2399 TEST_ASSERT(ptep); 2400 TEST_ASSERT_EQ(*ptep & PT_ADDR_MASK, data->gpa); 2401 *ptep = (*ptep & ~PT_AD_MASK) | pte_ad; 2402 ept_access_test_guest_flush_tlb(); 2403 2404 /* 2405 * Now modify the access bits on the EPT entry for the GPA that the 2406 * guest PTE resides on. Note that by modifying a single EPT entry, 2407 * we're potentially affecting 512 guest PTEs. However, we've carefully 2408 * constructed our test such that those other 511 PTEs aren't used by 2409 * the guest: data->gva is at the beginning of a 1G huge page, thus the 2410 * PTE we're modifying is at the beginning of a 4K page and the 2411 * following 511 entires are also under our control (and not touched by 2412 * the guest). 2413 */ 2414 gpa = virt_to_phys(ptep); 2415 TEST_ASSERT_EQ(gpa & ~PAGE_MASK, 0); 2416 /* 2417 * Make sure the guest page table page is mapped with a 4K EPT entry, 2418 * otherwise our level=1 twiddling below will fail. We use the 2419 * identity map (gpa = gpa) since page tables are shared with the host. 2420 */ 2421 install_ept(pml4, gpa, gpa, EPT_PRESENT); 2422 orig_epte = ept_twiddle(gpa, /*mkhuge=*/0, /*level=*/1, 2423 /*clear=*/EPT_PRESENT, /*set=*/ept_access); 2424 2425 if (expect_violation) { 2426 do_ept_violation(/*leaf=*/true, op, 2427 expected_qual | EPT_VLT_LADDR_VLD, gpa); 2428 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2429 do_ept_access_op(op); 2430 } else { 2431 do_ept_access_op(op); 2432 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2433 } 2434 2435 TEST_ASSERT(*ptep & PT_ACCESSED_MASK); 2436 if ((pte_ad & PT_DIRTY_MASK) || op == OP_WRITE) 2437 TEST_ASSERT(*ptep & PT_DIRTY_MASK); 2438 2439 skip_exit_vmcall(); 2440 } 2441 2442 static void ept_access_allowed_paddr(unsigned long ept_access, 2443 unsigned long pte_ad, 2444 enum ept_access_op op) 2445 { 2446 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/false, 2447 /*expected_qual=*/-1); 2448 } 2449 2450 static void ept_access_violation_paddr(unsigned long ept_access, 2451 unsigned long pte_ad, 2452 enum ept_access_op op, 2453 u64 expected_qual) 2454 { 2455 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/true, 2456 expected_qual); 2457 } 2458 2459 2460 static void ept_allowed_at_level_mkhuge(bool mkhuge, int level, 2461 unsigned long clear, 2462 unsigned long set, 2463 enum ept_access_op op) 2464 { 2465 struct ept_access_test_data *data = &ept_access_test_data; 2466 unsigned long orig_pte; 2467 2468 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2469 2470 /* No violation. Should proceed to vmcall. */ 2471 do_ept_access_op(op); 2472 skip_exit_vmcall(); 2473 2474 ept_untwiddle(data->gpa, level, orig_pte); 2475 } 2476 2477 static void ept_allowed_at_level(int level, unsigned long clear, 2478 unsigned long set, enum ept_access_op op) 2479 { 2480 ept_allowed_at_level_mkhuge(false, level, clear, set, op); 2481 if (ept_huge_pages_supported(level)) 2482 ept_allowed_at_level_mkhuge(true, level, clear, set, op); 2483 } 2484 2485 static void ept_allowed(unsigned long clear, unsigned long set, 2486 enum ept_access_op op) 2487 { 2488 ept_allowed_at_level(1, clear, set, op); 2489 ept_allowed_at_level(2, clear, set, op); 2490 ept_allowed_at_level(3, clear, set, op); 2491 ept_allowed_at_level(4, clear, set, op); 2492 } 2493 2494 static void ept_ignored_bit(int bit) 2495 { 2496 /* Set the bit. */ 2497 ept_allowed(0, 1ul << bit, OP_READ); 2498 ept_allowed(0, 1ul << bit, OP_WRITE); 2499 ept_allowed(0, 1ul << bit, OP_EXEC); 2500 2501 /* Clear the bit. */ 2502 ept_allowed(1ul << bit, 0, OP_READ); 2503 ept_allowed(1ul << bit, 0, OP_WRITE); 2504 ept_allowed(1ul << bit, 0, OP_EXEC); 2505 } 2506 2507 static void ept_access_allowed(unsigned long access, enum ept_access_op op) 2508 { 2509 ept_allowed(EPT_PRESENT, access, op); 2510 } 2511 2512 2513 static void ept_misconfig_at_level_mkhuge_op(bool mkhuge, int level, 2514 unsigned long clear, 2515 unsigned long set, 2516 enum ept_access_op op) 2517 { 2518 struct ept_access_test_data *data = &ept_access_test_data; 2519 unsigned long orig_pte; 2520 2521 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2522 2523 do_ept_access_op(op); 2524 assert_exit_reason(VMX_EPT_MISCONFIG); 2525 2526 /* Intel 27.2.1, "For all other VM exits, this field is cleared." */ 2527 #if 0 2528 /* broken: */ 2529 TEST_EXPECT_EQ_MSG(vmcs_read(EXI_QUALIFICATION), 0); 2530 #endif 2531 #if 0 2532 /* 2533 * broken: 2534 * According to description of exit qual for EPT violation, 2535 * EPT_VLT_LADDR_VLD indicates if GUEST_LINEAR_ADDRESS is valid. 2536 * However, I can't find anything that says GUEST_LINEAR_ADDRESS ought 2537 * to be set for msiconfig. 2538 */ 2539 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2540 (unsigned long) ( 2541 op == OP_EXEC ? data->gva + 1 : data->gva)); 2542 #endif 2543 2544 /* Fix the violation and resume the op loop. */ 2545 ept_untwiddle(data->gpa, level, orig_pte); 2546 enter_guest(); 2547 skip_exit_vmcall(); 2548 } 2549 2550 static void ept_misconfig_at_level_mkhuge(bool mkhuge, int level, 2551 unsigned long clear, 2552 unsigned long set) 2553 { 2554 /* The op shouldn't matter (read, write, exec), so try them all! */ 2555 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_READ); 2556 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_WRITE); 2557 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_EXEC); 2558 } 2559 2560 static void ept_misconfig_at_level(int level, unsigned long clear, 2561 unsigned long set) 2562 { 2563 ept_misconfig_at_level_mkhuge(false, level, clear, set); 2564 if (ept_huge_pages_supported(level)) 2565 ept_misconfig_at_level_mkhuge(true, level, clear, set); 2566 } 2567 2568 static void ept_misconfig(unsigned long clear, unsigned long set) 2569 { 2570 ept_misconfig_at_level(1, clear, set); 2571 ept_misconfig_at_level(2, clear, set); 2572 ept_misconfig_at_level(3, clear, set); 2573 ept_misconfig_at_level(4, clear, set); 2574 } 2575 2576 static void ept_access_misconfig(unsigned long access) 2577 { 2578 ept_misconfig(EPT_PRESENT, access); 2579 } 2580 2581 static void ept_reserved_bit_at_level_nohuge(int level, int bit) 2582 { 2583 /* Setting the bit causes a misconfig. */ 2584 ept_misconfig_at_level_mkhuge(false, level, 0, 1ul << bit); 2585 2586 /* Making the entry non-present turns reserved bits into ignored. */ 2587 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2588 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2589 } 2590 2591 static void ept_reserved_bit_at_level_huge(int level, int bit) 2592 { 2593 /* Setting the bit causes a misconfig. */ 2594 ept_misconfig_at_level_mkhuge(true, level, 0, 1ul << bit); 2595 2596 /* Making the entry non-present turns reserved bits into ignored. */ 2597 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2598 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2599 } 2600 2601 static void ept_reserved_bit_at_level(int level, int bit) 2602 { 2603 /* Setting the bit causes a misconfig. */ 2604 ept_misconfig_at_level(level, 0, 1ul << bit); 2605 2606 /* Making the entry non-present turns reserved bits into ignored. */ 2607 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2608 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2609 } 2610 2611 static void ept_reserved_bit(int bit) 2612 { 2613 ept_reserved_bit_at_level(1, bit); 2614 ept_reserved_bit_at_level(2, bit); 2615 ept_reserved_bit_at_level(3, bit); 2616 ept_reserved_bit_at_level(4, bit); 2617 } 2618 2619 #define PAGE_2M_ORDER 9 2620 #define PAGE_1G_ORDER 18 2621 2622 static void *get_1g_page(void) 2623 { 2624 static void *alloc; 2625 2626 if (!alloc) 2627 alloc = alloc_pages(PAGE_1G_ORDER); 2628 return alloc; 2629 } 2630 2631 static void ept_access_test_teardown(void *unused) 2632 { 2633 /* Exit the guest cleanly. */ 2634 do_ept_access_op(OP_EXIT); 2635 } 2636 2637 static void ept_access_test_guest(void) 2638 { 2639 struct ept_access_test_data *data = &ept_access_test_data; 2640 int (*code)(void) = (int (*)(void)) &data->gva[1]; 2641 2642 while (true) { 2643 switch (data->op) { 2644 case OP_READ: 2645 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_1); 2646 break; 2647 case OP_WRITE: 2648 *data->gva = MAGIC_VAL_2; 2649 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_2); 2650 *data->gva = MAGIC_VAL_1; 2651 break; 2652 case OP_EXEC: 2653 TEST_ASSERT_EQ(42, code()); 2654 break; 2655 case OP_FLUSH_TLB: 2656 write_cr3(read_cr3()); 2657 break; 2658 case OP_EXIT: 2659 return; 2660 default: 2661 TEST_ASSERT_MSG(false, "Unknown op %d", data->op); 2662 } 2663 vmcall(); 2664 } 2665 } 2666 2667 static void ept_access_test_setup(void) 2668 { 2669 struct ept_access_test_data *data = &ept_access_test_data; 2670 unsigned long npages = 1ul << PAGE_1G_ORDER; 2671 unsigned long size = npages * PAGE_SIZE; 2672 unsigned long *page_table = current_page_table(); 2673 unsigned long pte; 2674 2675 if (setup_ept(false)) 2676 test_skip("EPT not supported"); 2677 2678 /* We use data->gpa = 1 << 39 so that test data has a separate pml4 entry */ 2679 if (cpuid_maxphyaddr() < 40) 2680 test_skip("Test needs MAXPHYADDR >= 40"); 2681 2682 test_set_guest(ept_access_test_guest); 2683 test_add_teardown(ept_access_test_teardown, NULL); 2684 2685 data->hva = get_1g_page(); 2686 TEST_ASSERT(data->hva); 2687 data->hpa = virt_to_phys(data->hva); 2688 2689 data->gpa = 1ul << 39; 2690 data->gva = (void *) ALIGN((unsigned long) alloc_vpages(npages * 2), 2691 size); 2692 TEST_ASSERT(!any_present_pages(page_table, data->gva, size)); 2693 install_pages(page_table, data->gpa, size, data->gva); 2694 2695 /* 2696 * Make sure nothing's mapped here so the tests that screw with the 2697 * pml4 entry don't inadvertently break something. 2698 */ 2699 TEST_ASSERT(get_ept_pte(pml4, data->gpa, 4, &pte) && pte == 0); 2700 TEST_ASSERT(get_ept_pte(pml4, data->gpa + size - 1, 4, &pte) && pte == 0); 2701 install_ept(pml4, data->hpa, data->gpa, EPT_PRESENT); 2702 2703 data->hva[0] = MAGIC_VAL_1; 2704 memcpy(&data->hva[1], &ret42_start, &ret42_end - &ret42_start); 2705 } 2706 2707 static void ept_access_test_not_present(void) 2708 { 2709 ept_access_test_setup(); 2710 /* --- */ 2711 ept_access_violation(0, OP_READ, EPT_VLT_RD); 2712 ept_access_violation(0, OP_WRITE, EPT_VLT_WR); 2713 ept_access_violation(0, OP_EXEC, EPT_VLT_FETCH); 2714 } 2715 2716 static void ept_access_test_read_only(void) 2717 { 2718 ept_access_test_setup(); 2719 2720 /* r-- */ 2721 ept_access_allowed(EPT_RA, OP_READ); 2722 ept_access_violation(EPT_RA, OP_WRITE, EPT_VLT_WR | EPT_VLT_PERM_RD); 2723 ept_access_violation(EPT_RA, OP_EXEC, EPT_VLT_FETCH | EPT_VLT_PERM_RD); 2724 } 2725 2726 static void ept_access_test_write_only(void) 2727 { 2728 ept_access_test_setup(); 2729 /* -w- */ 2730 ept_access_misconfig(EPT_WA); 2731 } 2732 2733 static void ept_access_test_read_write(void) 2734 { 2735 ept_access_test_setup(); 2736 /* rw- */ 2737 ept_access_allowed(EPT_RA | EPT_WA, OP_READ); 2738 ept_access_allowed(EPT_RA | EPT_WA, OP_WRITE); 2739 ept_access_violation(EPT_RA | EPT_WA, OP_EXEC, 2740 EPT_VLT_FETCH | EPT_VLT_PERM_RD | EPT_VLT_PERM_WR); 2741 } 2742 2743 2744 static void ept_access_test_execute_only(void) 2745 { 2746 ept_access_test_setup(); 2747 /* --x */ 2748 if (ept_execute_only_supported()) { 2749 ept_access_violation(EPT_EA, OP_READ, 2750 EPT_VLT_RD | EPT_VLT_PERM_EX); 2751 ept_access_violation(EPT_EA, OP_WRITE, 2752 EPT_VLT_WR | EPT_VLT_PERM_EX); 2753 ept_access_allowed(EPT_EA, OP_EXEC); 2754 } else { 2755 ept_access_misconfig(EPT_EA); 2756 } 2757 } 2758 2759 static void ept_access_test_read_execute(void) 2760 { 2761 ept_access_test_setup(); 2762 /* r-x */ 2763 ept_access_allowed(EPT_RA | EPT_EA, OP_READ); 2764 ept_access_violation(EPT_RA | EPT_EA, OP_WRITE, 2765 EPT_VLT_WR | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX); 2766 ept_access_allowed(EPT_RA | EPT_EA, OP_EXEC); 2767 } 2768 2769 static void ept_access_test_write_execute(void) 2770 { 2771 ept_access_test_setup(); 2772 /* -wx */ 2773 ept_access_misconfig(EPT_WA | EPT_EA); 2774 } 2775 2776 static void ept_access_test_read_write_execute(void) 2777 { 2778 ept_access_test_setup(); 2779 /* rwx */ 2780 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_READ); 2781 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_WRITE); 2782 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_EXEC); 2783 } 2784 2785 static void ept_access_test_reserved_bits(void) 2786 { 2787 int i; 2788 int maxphyaddr; 2789 2790 ept_access_test_setup(); 2791 2792 /* Reserved bits above maxphyaddr. */ 2793 maxphyaddr = cpuid_maxphyaddr(); 2794 for (i = maxphyaddr; i <= 51; i++) { 2795 report_prefix_pushf("reserved_bit=%d", i); 2796 ept_reserved_bit(i); 2797 report_prefix_pop(); 2798 } 2799 2800 /* Level-specific reserved bits. */ 2801 ept_reserved_bit_at_level_nohuge(2, 3); 2802 ept_reserved_bit_at_level_nohuge(2, 4); 2803 ept_reserved_bit_at_level_nohuge(2, 5); 2804 ept_reserved_bit_at_level_nohuge(2, 6); 2805 /* 2M alignment. */ 2806 for (i = 12; i < 20; i++) { 2807 report_prefix_pushf("reserved_bit=%d", i); 2808 ept_reserved_bit_at_level_huge(2, i); 2809 report_prefix_pop(); 2810 } 2811 ept_reserved_bit_at_level_nohuge(3, 3); 2812 ept_reserved_bit_at_level_nohuge(3, 4); 2813 ept_reserved_bit_at_level_nohuge(3, 5); 2814 ept_reserved_bit_at_level_nohuge(3, 6); 2815 /* 1G alignment. */ 2816 for (i = 12; i < 29; i++) { 2817 report_prefix_pushf("reserved_bit=%d", i); 2818 ept_reserved_bit_at_level_huge(3, i); 2819 report_prefix_pop(); 2820 } 2821 ept_reserved_bit_at_level(4, 3); 2822 ept_reserved_bit_at_level(4, 4); 2823 ept_reserved_bit_at_level(4, 5); 2824 ept_reserved_bit_at_level(4, 6); 2825 ept_reserved_bit_at_level(4, 7); 2826 } 2827 2828 static void ept_access_test_ignored_bits(void) 2829 { 2830 ept_access_test_setup(); 2831 /* 2832 * Bits ignored at every level. Bits 8 and 9 (A and D) are ignored as 2833 * far as translation is concerned even if AD bits are enabled in the 2834 * EPTP. Bit 63 is ignored because "EPT-violation #VE" VM-execution 2835 * control is 0. 2836 */ 2837 ept_ignored_bit(8); 2838 ept_ignored_bit(9); 2839 ept_ignored_bit(10); 2840 ept_ignored_bit(11); 2841 ept_ignored_bit(52); 2842 ept_ignored_bit(53); 2843 ept_ignored_bit(54); 2844 ept_ignored_bit(55); 2845 ept_ignored_bit(56); 2846 ept_ignored_bit(57); 2847 ept_ignored_bit(58); 2848 ept_ignored_bit(59); 2849 ept_ignored_bit(60); 2850 ept_ignored_bit(61); 2851 ept_ignored_bit(62); 2852 ept_ignored_bit(63); 2853 } 2854 2855 static void ept_access_test_paddr_not_present_ad_disabled(void) 2856 { 2857 ept_access_test_setup(); 2858 ept_disable_ad_bits(); 2859 2860 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, EPT_VLT_RD); 2861 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, EPT_VLT_RD); 2862 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, EPT_VLT_RD); 2863 } 2864 2865 static void ept_access_test_paddr_not_present_ad_enabled(void) 2866 { 2867 u64 qual = EPT_VLT_RD | EPT_VLT_WR; 2868 2869 ept_access_test_setup(); 2870 ept_enable_ad_bits_or_skip_test(); 2871 2872 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, qual); 2873 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, qual); 2874 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, qual); 2875 } 2876 2877 static void ept_access_test_paddr_read_only_ad_disabled(void) 2878 { 2879 /* 2880 * When EPT AD bits are disabled, all accesses to guest paging 2881 * structures are reported separately as a read and (after 2882 * translation of the GPA to host physical address) a read+write 2883 * if the A/D bits have to be set. 2884 */ 2885 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 2886 2887 ept_access_test_setup(); 2888 ept_disable_ad_bits(); 2889 2890 /* Can't update A bit, so all accesses fail. */ 2891 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 2892 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 2893 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 2894 /* AD bits disabled, so only writes try to update the D bit. */ 2895 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ); 2896 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 2897 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC); 2898 /* Both A and D already set, so read-only is OK. */ 2899 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_READ); 2900 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_WRITE); 2901 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_EXEC); 2902 } 2903 2904 static void ept_access_test_paddr_read_only_ad_enabled(void) 2905 { 2906 /* 2907 * When EPT AD bits are enabled, all accesses to guest paging 2908 * structures are considered writes as far as EPT translation 2909 * is concerned. 2910 */ 2911 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 2912 2913 ept_access_test_setup(); 2914 ept_enable_ad_bits_or_skip_test(); 2915 2916 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 2917 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 2918 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 2919 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ, qual); 2920 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 2921 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC, qual); 2922 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_READ, qual); 2923 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_WRITE, qual); 2924 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_EXEC, qual); 2925 } 2926 2927 static void ept_access_test_paddr_read_write(void) 2928 { 2929 ept_access_test_setup(); 2930 /* Read-write access to paging structure. */ 2931 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_READ); 2932 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_WRITE); 2933 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_EXEC); 2934 } 2935 2936 static void ept_access_test_paddr_read_write_execute(void) 2937 { 2938 ept_access_test_setup(); 2939 /* RWX access to paging structure. */ 2940 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_READ); 2941 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_WRITE); 2942 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_EXEC); 2943 } 2944 2945 static void ept_access_test_paddr_read_execute_ad_disabled(void) 2946 { 2947 /* 2948 * When EPT AD bits are disabled, all accesses to guest paging 2949 * structures are reported separately as a read and (after 2950 * translation of the GPA to host physical address) a read+write 2951 * if the A/D bits have to be set. 2952 */ 2953 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 2954 2955 ept_access_test_setup(); 2956 ept_disable_ad_bits(); 2957 2958 /* Can't update A bit, so all accesses fail. */ 2959 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 2960 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 2961 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 2962 /* AD bits disabled, so only writes try to update the D bit. */ 2963 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ); 2964 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 2965 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC); 2966 /* Both A and D already set, so read-only is OK. */ 2967 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ); 2968 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE); 2969 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC); 2970 } 2971 2972 static void ept_access_test_paddr_read_execute_ad_enabled(void) 2973 { 2974 /* 2975 * When EPT AD bits are enabled, all accesses to guest paging 2976 * structures are considered writes as far as EPT translation 2977 * is concerned. 2978 */ 2979 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 2980 2981 ept_access_test_setup(); 2982 ept_enable_ad_bits_or_skip_test(); 2983 2984 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 2985 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 2986 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 2987 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ, qual); 2988 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 2989 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC, qual); 2990 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ, qual); 2991 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE, qual); 2992 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC, qual); 2993 } 2994 2995 static void ept_access_test_paddr_not_present_page_fault(void) 2996 { 2997 ept_access_test_setup(); 2998 /* 2999 * TODO: test no EPT violation as long as guest PF occurs. e.g., GPA is 3000 * page is read-only in EPT but GVA is also mapped read only in PT. 3001 * Thus guest page fault before host takes EPT violation for trying to 3002 * update A bit. 3003 */ 3004 } 3005 3006 static void ept_access_test_force_2m_page(void) 3007 { 3008 ept_access_test_setup(); 3009 3010 TEST_ASSERT_EQ(ept_2m_supported(), true); 3011 ept_allowed_at_level_mkhuge(true, 2, 0, 0, OP_READ); 3012 ept_violation_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_RA, OP_WRITE, 3013 EPT_VLT_WR | EPT_VLT_PERM_RD | 3014 EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 3015 ept_misconfig_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_WA); 3016 } 3017 3018 static bool invvpid_valid(u64 type, u64 vpid, u64 gla) 3019 { 3020 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3021 3022 TEST_ASSERT(msr & VPID_CAP_INVVPID); 3023 3024 if (type < INVVPID_ADDR || type > INVVPID_CONTEXT_LOCAL) 3025 return false; 3026 3027 if (!(msr & (1ull << (type + VPID_CAP_INVVPID_TYPES_SHIFT)))) 3028 return false; 3029 3030 if (vpid >> 16) 3031 return false; 3032 3033 if (type != INVVPID_ALL && !vpid) 3034 return false; 3035 3036 if (type == INVVPID_ADDR && !is_canonical(gla)) 3037 return false; 3038 3039 return true; 3040 } 3041 3042 static void try_invvpid(u64 type, u64 vpid, u64 gla) 3043 { 3044 int rc; 3045 bool valid = invvpid_valid(type, vpid, gla); 3046 u64 expected = valid ? VMXERR_UNSUPPORTED_VMCS_COMPONENT 3047 : VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID; 3048 /* 3049 * Set VMX_INST_ERROR to VMXERR_UNVALID_VMCS_COMPONENT, so 3050 * that we can tell if it is updated by INVVPID. 3051 */ 3052 vmcs_read(~0); 3053 rc = invvpid(type, vpid, gla); 3054 report("INVVPID type %ld VPID %lx GLA %lx %s", 3055 !rc == valid, type, vpid, gla, 3056 valid ? "passes" : "fails"); 3057 report("After %s INVVPID, VMX_INST_ERR is %ld (actual %ld)", 3058 vmcs_read(VMX_INST_ERROR) == expected, 3059 rc ? "failed" : "successful", 3060 expected, vmcs_read(VMX_INST_ERROR)); 3061 } 3062 3063 static void ds_invvpid(void *data) 3064 { 3065 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3066 u64 type = ffs(msr >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 3067 3068 TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 3069 asm volatile("invvpid %0, %1" 3070 : 3071 : "m"(*(struct invvpid_operand *)data), 3072 "r"(type)); 3073 } 3074 3075 /* 3076 * The SS override is ignored in 64-bit mode, so we use an addressing 3077 * mode with %rsp as the base register to generate an implicit SS 3078 * reference. 3079 */ 3080 static void ss_invvpid(void *data) 3081 { 3082 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3083 u64 type = ffs(msr >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 3084 3085 TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 3086 asm volatile("sub %%rsp,%0; invvpid (%%rsp,%0,1), %1" 3087 : "+r"(data) 3088 : "r"(type)); 3089 } 3090 3091 static void invvpid_test_gp(void) 3092 { 3093 bool fault; 3094 3095 fault = test_for_exception(GP_VECTOR, &ds_invvpid, 3096 (void *)NONCANONICAL); 3097 report("INVVPID with non-canonical DS operand raises #GP", fault); 3098 } 3099 3100 static void invvpid_test_ss(void) 3101 { 3102 bool fault; 3103 3104 fault = test_for_exception(SS_VECTOR, &ss_invvpid, 3105 (void *)NONCANONICAL); 3106 report("INVVPID with non-canonical SS operand raises #SS", fault); 3107 } 3108 3109 static void invvpid_test_pf(void) 3110 { 3111 void *vpage = alloc_vpage(); 3112 bool fault; 3113 3114 fault = test_for_exception(PF_VECTOR, &ds_invvpid, vpage); 3115 report("INVVPID with unmapped operand raises #PF", fault); 3116 } 3117 3118 static void try_compat_invvpid(void *unused) 3119 { 3120 struct far_pointer32 fp = { 3121 .offset = (uintptr_t)&&invvpid, 3122 .selector = KERNEL_CS32, 3123 }; 3124 register uintptr_t rsp asm("rsp"); 3125 3126 TEST_ASSERT_MSG(fp.offset == (uintptr_t)&&invvpid, 3127 "Code address too high."); 3128 TEST_ASSERT_MSG(rsp == (u32)rsp, "Stack address too high."); 3129 3130 asm goto ("lcall *%0" : : "m" (fp) : "rax" : invvpid); 3131 return; 3132 invvpid: 3133 asm volatile (".code32;" 3134 "invvpid (%eax), %eax;" 3135 "lret;" 3136 ".code64"); 3137 __builtin_unreachable(); 3138 } 3139 3140 static void invvpid_test_compatibility_mode(void) 3141 { 3142 bool fault; 3143 3144 fault = test_for_exception(UD_VECTOR, &try_compat_invvpid, NULL); 3145 report("Compatibility mode INVVPID raises #UD", fault); 3146 } 3147 3148 static void invvpid_test_not_in_vmx_operation(void) 3149 { 3150 bool fault; 3151 3152 TEST_ASSERT(!vmx_off()); 3153 fault = test_for_exception(UD_VECTOR, &ds_invvpid, NULL); 3154 report("INVVPID outside of VMX operation raises #UD", fault); 3155 TEST_ASSERT(!vmx_on()); 3156 } 3157 3158 /* 3159 * This does not test real-address mode, virtual-8086 mode, protected mode, 3160 * or CPL > 0. 3161 */ 3162 static void invvpid_test_v2(void) 3163 { 3164 u64 msr; 3165 int i; 3166 unsigned types = 0; 3167 unsigned type; 3168 3169 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 3170 !(ctrl_cpu_rev[1].clr & CPU_VPID)) 3171 test_skip("VPID not supported"); 3172 3173 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3174 3175 if (!(msr & VPID_CAP_INVVPID)) 3176 test_skip("INVVPID not supported.\n"); 3177 3178 if (msr & VPID_CAP_INVVPID_ADDR) 3179 types |= 1u << INVVPID_ADDR; 3180 if (msr & VPID_CAP_INVVPID_CXTGLB) 3181 types |= 1u << INVVPID_CONTEXT_GLOBAL; 3182 if (msr & VPID_CAP_INVVPID_ALL) 3183 types |= 1u << INVVPID_ALL; 3184 if (msr & VPID_CAP_INVVPID_CXTLOC) 3185 types |= 1u << INVVPID_CONTEXT_LOCAL; 3186 3187 if (!types) 3188 test_skip("No INVVPID types supported.\n"); 3189 3190 for (i = -127; i < 128; i++) 3191 try_invvpid(i, 0xffff, 0); 3192 3193 /* 3194 * VPID must not be more than 16 bits. 3195 */ 3196 for (i = 0; i < 64; i++) 3197 for (type = 0; type < 4; type++) 3198 if (types & (1u << type)) 3199 try_invvpid(type, 1ul << i, 0); 3200 3201 /* 3202 * VPID must not be zero, except for "all contexts." 3203 */ 3204 for (type = 0; type < 4; type++) 3205 if (types & (1u << type)) 3206 try_invvpid(type, 0, 0); 3207 3208 /* 3209 * The gla operand is only validated for single-address INVVPID. 3210 */ 3211 if (types & (1u << INVVPID_ADDR)) 3212 try_invvpid(INVVPID_ADDR, 0xffff, NONCANONICAL); 3213 3214 invvpid_test_gp(); 3215 invvpid_test_ss(); 3216 invvpid_test_pf(); 3217 invvpid_test_compatibility_mode(); 3218 invvpid_test_not_in_vmx_operation(); 3219 } 3220 3221 /* 3222 * Test for early VMLAUNCH failure. Returns true if VMLAUNCH makes it 3223 * at least as far as the guest-state checks. Returns false if the 3224 * VMLAUNCH fails early and execution falls through to the next 3225 * instruction. 3226 */ 3227 static bool vmlaunch_succeeds(void) 3228 { 3229 /* 3230 * Indirectly set VMX_INST_ERR to 12 ("VMREAD/VMWRITE from/to 3231 * unsupported VMCS component"). The caller can then check 3232 * to see if a failed VM-entry sets VMX_INST_ERR as expected. 3233 */ 3234 vmcs_write(~0u, 0); 3235 3236 vmcs_write(HOST_RIP, (uintptr_t)&&success); 3237 __asm__ __volatile__ goto ("vmwrite %%rsp, %0; vmlaunch" 3238 : 3239 : "r" ((u64)HOST_RSP) 3240 : "cc", "memory" 3241 : success); 3242 return false; 3243 success: 3244 TEST_ASSERT(vmcs_read(EXI_REASON) == 3245 (VMX_FAIL_STATE | VMX_ENTRY_FAILURE)); 3246 return true; 3247 } 3248 3249 /* 3250 * Try to launch the current VMCS. 3251 */ 3252 static void test_vmx_controls(bool controls_valid, bool xfail) 3253 { 3254 bool success = vmlaunch_succeeds(); 3255 u32 vmx_inst_err; 3256 3257 report_xfail("vmlaunch %s", xfail, success == controls_valid, 3258 controls_valid ? "succeeds" : "fails"); 3259 if (!success) { 3260 vmx_inst_err = vmcs_read(VMX_INST_ERROR); 3261 report("VMX inst error is %d (actual %d)", 3262 vmx_inst_err == VMXERR_ENTRY_INVALID_CONTROL_FIELD, 3263 VMXERR_ENTRY_INVALID_CONTROL_FIELD, vmx_inst_err); 3264 } 3265 } 3266 3267 /* 3268 * Test a particular value of a VM-execution control bit, if the value 3269 * is required or if the value is zero. 3270 */ 3271 static void test_rsvd_ctl_bit_value(const char *name, union vmx_ctrl_msr msr, 3272 enum Encoding encoding, unsigned bit, 3273 unsigned val) 3274 { 3275 u32 mask = 1u << bit; 3276 bool expected; 3277 u32 controls; 3278 3279 if (msr.set & mask) 3280 TEST_ASSERT(msr.clr & mask); 3281 3282 /* 3283 * We can't arbitrarily turn on a control bit, because it may 3284 * introduce dependencies on other VMCS fields. So, we only 3285 * test turning on bits that have a required setting. 3286 */ 3287 if (val && (msr.clr & mask) && !(msr.set & mask)) 3288 return; 3289 3290 report_prefix_pushf("%s %s bit %d", 3291 val ? "Set" : "Clear", name, bit); 3292 3293 controls = vmcs_read(encoding); 3294 if (val) { 3295 vmcs_write(encoding, msr.set | mask); 3296 expected = (msr.clr & mask); 3297 } else { 3298 vmcs_write(encoding, msr.set & ~mask); 3299 expected = !(msr.set & mask); 3300 } 3301 test_vmx_controls(expected, false); 3302 vmcs_write(encoding, controls); 3303 report_prefix_pop(); 3304 } 3305 3306 /* 3307 * Test reserved values of a VM-execution control bit, based on the 3308 * allowed bit settings from the corresponding VMX capability MSR. 3309 */ 3310 static void test_rsvd_ctl_bit(const char *name, union vmx_ctrl_msr msr, 3311 enum Encoding encoding, unsigned bit) 3312 { 3313 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 0); 3314 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 1); 3315 } 3316 3317 /* 3318 * Reserved bits in the pin-based VM-execution controls must be set 3319 * properly. Software may consult the VMX capability MSRs to determine 3320 * the proper settings. 3321 * [Intel SDM] 3322 */ 3323 static void test_pin_based_ctls(void) 3324 { 3325 unsigned bit; 3326 3327 printf("%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PIN" : 3328 "MSR_IA32_VMX_PINBASED_CTLS", ctrl_pin_rev.val); 3329 for (bit = 0; bit < 32; bit++) 3330 test_rsvd_ctl_bit("pin-based controls", 3331 ctrl_pin_rev, PIN_CONTROLS, bit); 3332 } 3333 3334 /* 3335 * Reserved bits in the primary processor-based VM-execution controls 3336 * must be set properly. Software may consult the VMX capability MSRs 3337 * to determine the proper settings. 3338 * [Intel SDM] 3339 */ 3340 static void test_primary_processor_based_ctls(void) 3341 { 3342 unsigned bit; 3343 3344 printf("\n%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PROC" : 3345 "MSR_IA32_VMX_PROCBASED_CTLS", ctrl_cpu_rev[0].val); 3346 for (bit = 0; bit < 32; bit++) 3347 test_rsvd_ctl_bit("primary processor-based controls", 3348 ctrl_cpu_rev[0], CPU_EXEC_CTRL0, bit); 3349 } 3350 3351 /* 3352 * If the "activate secondary controls" primary processor-based 3353 * VM-execution control is 1, reserved bits in the secondary 3354 * processor-based VM-execution controls must be cleared. Software may 3355 * consult the VMX capability MSRs to determine which bits are 3356 * reserved. 3357 * If the "activate secondary controls" primary processor-based 3358 * VM-execution control is 0 (or if the processor does not support the 3359 * 1-setting of that control), no checks are performed on the 3360 * secondary processor-based VM-execution controls. 3361 * [Intel SDM] 3362 */ 3363 static void test_secondary_processor_based_ctls(void) 3364 { 3365 u32 primary; 3366 u32 secondary; 3367 unsigned bit; 3368 3369 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) 3370 return; 3371 3372 primary = vmcs_read(CPU_EXEC_CTRL0); 3373 secondary = vmcs_read(CPU_EXEC_CTRL1); 3374 3375 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3376 printf("\nMSR_IA32_VMX_PROCBASED_CTLS2: %lx\n", ctrl_cpu_rev[1].val); 3377 for (bit = 0; bit < 32; bit++) 3378 test_rsvd_ctl_bit("secondary processor-based controls", 3379 ctrl_cpu_rev[1], CPU_EXEC_CTRL1, bit); 3380 3381 /* 3382 * When the "activate secondary controls" VM-execution control 3383 * is clear, there are no checks on the secondary controls. 3384 */ 3385 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3386 vmcs_write(CPU_EXEC_CTRL1, ~0); 3387 report("Secondary processor-based controls ignored", 3388 vmlaunch_succeeds()); 3389 vmcs_write(CPU_EXEC_CTRL1, secondary); 3390 vmcs_write(CPU_EXEC_CTRL0, primary); 3391 } 3392 3393 static void try_cr3_target_count(unsigned i, unsigned max) 3394 { 3395 report_prefix_pushf("CR3 target count 0x%x", i); 3396 vmcs_write(CR3_TARGET_COUNT, i); 3397 test_vmx_controls(i <= max, false); 3398 report_prefix_pop(); 3399 } 3400 3401 /* 3402 * The CR3-target count must not be greater than 4. Future processors 3403 * may support a different number of CR3-target values. Software 3404 * should read the VMX capability MSR IA32_VMX_MISC to determine the 3405 * number of values supported. 3406 * [Intel SDM] 3407 */ 3408 static void test_cr3_targets(void) 3409 { 3410 unsigned supported_targets = (rdmsr(MSR_IA32_VMX_MISC) >> 16) & 0x1ff; 3411 u32 cr3_targets = vmcs_read(CR3_TARGET_COUNT); 3412 unsigned i; 3413 3414 printf("\nSupported CR3 targets: %d\n", supported_targets); 3415 TEST_ASSERT(supported_targets <= 256); 3416 3417 try_cr3_target_count(-1u, supported_targets); 3418 try_cr3_target_count(0x80000000, supported_targets); 3419 try_cr3_target_count(0x7fffffff, supported_targets); 3420 for (i = 0; i <= supported_targets + 1; i++) 3421 try_cr3_target_count(i, supported_targets); 3422 vmcs_write(CR3_TARGET_COUNT, cr3_targets); 3423 } 3424 3425 /* 3426 * Test a particular address setting for a physical page reference in 3427 * the VMCS. 3428 */ 3429 static void test_vmcs_page_addr(const char *name, 3430 enum Encoding encoding, 3431 bool ignored, 3432 bool xfail_beyond_mapped_ram, 3433 u64 addr) 3434 { 3435 bool xfail = 3436 (xfail_beyond_mapped_ram && 3437 addr > fwcfg_get_u64(FW_CFG_RAM_SIZE) - PAGE_SIZE && 3438 addr < (1ul << cpuid_maxphyaddr())); 3439 3440 report_prefix_pushf("%s = %lx", name, addr); 3441 vmcs_write(encoding, addr); 3442 test_vmx_controls(ignored || (IS_ALIGNED(addr, PAGE_SIZE) && 3443 addr < (1ul << cpuid_maxphyaddr())), 3444 xfail); 3445 report_prefix_pop(); 3446 xfail = false; 3447 } 3448 3449 /* 3450 * Test interesting values for a physical page reference in the VMCS. 3451 */ 3452 static void test_vmcs_page_values(const char *name, 3453 enum Encoding encoding, 3454 bool ignored, 3455 bool xfail_beyond_mapped_ram) 3456 { 3457 unsigned i; 3458 u64 orig_val = vmcs_read(encoding); 3459 3460 for (i = 0; i < 64; i++) 3461 test_vmcs_page_addr(name, encoding, ignored, 3462 xfail_beyond_mapped_ram, 1ul << i); 3463 3464 test_vmcs_page_addr(name, encoding, ignored, 3465 xfail_beyond_mapped_ram, PAGE_SIZE - 1); 3466 test_vmcs_page_addr(name, encoding, ignored, 3467 xfail_beyond_mapped_ram, PAGE_SIZE); 3468 test_vmcs_page_addr(name, encoding, ignored, 3469 xfail_beyond_mapped_ram, 3470 (1ul << cpuid_maxphyaddr()) - PAGE_SIZE); 3471 test_vmcs_page_addr(name, encoding, ignored, 3472 xfail_beyond_mapped_ram, 3473 -1ul); 3474 3475 vmcs_write(encoding, orig_val); 3476 } 3477 3478 /* 3479 * Test a physical page reference in the VMCS, when the corresponding 3480 * feature is enabled and when the corresponding feature is disabled. 3481 */ 3482 static void test_vmcs_page_reference(u32 control_bit, enum Encoding field, 3483 const char *field_name, 3484 const char *control_name, 3485 bool xfail_beyond_mapped_ram, 3486 bool control_primary) 3487 { 3488 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 3489 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 3490 u64 page_addr; 3491 3492 if (control_primary) { 3493 if (!(ctrl_cpu_rev[0].clr & control_bit)) 3494 return; 3495 } else { 3496 if (!(ctrl_cpu_rev[1].clr & control_bit)) 3497 return; 3498 } 3499 3500 page_addr = vmcs_read(field); 3501 3502 report_prefix_pushf("%s enabled", control_name); 3503 if (control_primary) { 3504 vmcs_write(CPU_EXEC_CTRL0, primary | control_bit); 3505 } else { 3506 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3507 vmcs_write(CPU_EXEC_CTRL1, secondary | control_bit); 3508 } 3509 test_vmcs_page_values(field_name, field, false, xfail_beyond_mapped_ram); 3510 report_prefix_pop(); 3511 3512 report_prefix_pushf("%s disabled", control_name); 3513 if (control_primary) { 3514 vmcs_write(CPU_EXEC_CTRL0, primary & ~control_bit); 3515 } else { 3516 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3517 vmcs_write(CPU_EXEC_CTRL1, secondary & ~control_bit); 3518 } 3519 test_vmcs_page_values(field_name, field, true, false); 3520 report_prefix_pop(); 3521 3522 vmcs_write(field, page_addr); 3523 vmcs_write(CPU_EXEC_CTRL0, primary); 3524 } 3525 3526 /* 3527 * If the "use I/O bitmaps" VM-execution control is 1, bits 11:0 of 3528 * each I/O-bitmap address must be 0. Neither address should set any 3529 * bits beyond the processor's physical-address width. 3530 * [Intel SDM] 3531 */ 3532 static void test_io_bitmaps(void) 3533 { 3534 test_vmcs_page_reference(CPU_IO_BITMAP, IO_BITMAP_A, 3535 "I/O bitmap A", "Use I/O bitmaps", false, 3536 true); 3537 test_vmcs_page_reference(CPU_IO_BITMAP, IO_BITMAP_B, 3538 "I/O bitmap B", "Use I/O bitmaps", false, 3539 true); 3540 } 3541 3542 /* 3543 * If the "use MSR bitmaps" VM-execution control is 1, bits 11:0 of 3544 * the MSR-bitmap address must be 0. The address should not set any 3545 * bits beyond the processor's physical-address width. 3546 * [Intel SDM] 3547 */ 3548 static void test_msr_bitmap(void) 3549 { 3550 test_vmcs_page_reference(CPU_MSR_BITMAP, MSR_BITMAP, 3551 "MSR bitmap", "Use MSR bitmaps", false, 3552 true); 3553 } 3554 3555 /* 3556 * If the "use TPR shadow" VM-execution control is 1, the virtual-APIC 3557 * address must satisfy the following checks: 3558 * - Bits 11:0 of the address must be 0. 3559 * - The address should not set any bits beyond the processor's 3560 * physical-address width. 3561 * [Intel SDM] 3562 */ 3563 static void test_apic_virt_addr(void) 3564 { 3565 test_vmcs_page_reference(CPU_TPR_SHADOW, APIC_VIRT_ADDR, 3566 "virtual-APIC address", "Use TPR shadow", 3567 true, true); 3568 } 3569 3570 /* 3571 * If the "virtualize APIC-accesses" VM-execution control is 1, the 3572 * APIC-access address must satisfy the following checks: 3573 * - Bits 11:0 of the address must be 0. 3574 * - The address should not set any bits beyond the processor's 3575 * physical-address width. 3576 * [Intel SDM] 3577 */ 3578 static void test_apic_access_addr(void) 3579 { 3580 void *apic_access_page = alloc_page(); 3581 3582 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_page)); 3583 3584 test_vmcs_page_reference(CPU_VIRT_APIC_ACCESSES, APIC_ACCS_ADDR, 3585 "APIC-access address", 3586 "virtualize APIC-accesses", false, false); 3587 } 3588 3589 static bool set_bit_pattern(u8 mask, u32 *secondary) 3590 { 3591 u8 i; 3592 bool flag = false; 3593 u32 test_bits[3] = { 3594 CPU_VIRT_X2APIC, 3595 CPU_APIC_REG_VIRT, 3596 CPU_VINTD 3597 }; 3598 3599 for (i = 0; i < ARRAY_SIZE(test_bits); i++) { 3600 if ((mask & (1u << i)) && 3601 (ctrl_cpu_rev[1].clr & test_bits[i])) { 3602 *secondary |= test_bits[i]; 3603 flag = true; 3604 } 3605 } 3606 3607 return (flag); 3608 } 3609 3610 /* 3611 * If the "use TPR shadow" VM-execution control is 0, the following 3612 * VM-execution controls must also be 0: 3613 * - virtualize x2APIC mode 3614 * - APIC-register virtualization 3615 * - virtual-interrupt delivery 3616 * [Intel SDM] 3617 * 3618 * 2. If the "virtualize x2APIC mode" VM-execution control is 1, the 3619 * "virtualize APIC accesses" VM-execution control must be 0. 3620 * [Intel SDM] 3621 */ 3622 static void test_apic_virtual_ctls(void) 3623 { 3624 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3625 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3626 u32 primary = saved_primary; 3627 u32 secondary = saved_secondary; 3628 bool ctrl = false; 3629 char str[10] = "disabled"; 3630 u8 i = 0, j; 3631 3632 /* 3633 * First test 3634 */ 3635 if (!((ctrl_cpu_rev[0].clr & (CPU_SECONDARY | CPU_TPR_SHADOW)) == 3636 (CPU_SECONDARY | CPU_TPR_SHADOW))) 3637 return; 3638 3639 primary |= CPU_SECONDARY; 3640 primary &= ~CPU_TPR_SHADOW; 3641 vmcs_write(CPU_EXEC_CTRL0, primary); 3642 3643 while (1) { 3644 for (j = 1; j < 8; j++) { 3645 secondary &= ~(CPU_VIRT_X2APIC | CPU_APIC_REG_VIRT | CPU_VINTD); 3646 if (primary & CPU_TPR_SHADOW) { 3647 ctrl = true; 3648 } else { 3649 if (! set_bit_pattern(j, &secondary)) 3650 ctrl = true; 3651 else 3652 ctrl = false; 3653 } 3654 3655 vmcs_write(CPU_EXEC_CTRL1, secondary); 3656 report_prefix_pushf("Use TPR shadow %s, virtualize x2APIC mode %s, APIC-register virtualization %s, virtual-interrupt delivery %s", 3657 str, (secondary & CPU_VIRT_X2APIC) ? "enabled" : "disabled", (secondary & CPU_APIC_REG_VIRT) ? "enabled" : "disabled", (secondary & CPU_VINTD) ? "enabled" : "disabled"); 3658 test_vmx_controls(ctrl, false); 3659 report_prefix_pop(); 3660 } 3661 3662 if (i == 1) 3663 break; 3664 i++; 3665 3666 primary |= CPU_TPR_SHADOW; 3667 vmcs_write(CPU_EXEC_CTRL0, primary); 3668 strcpy(str, "enabled"); 3669 } 3670 3671 /* 3672 * Second test 3673 */ 3674 u32 apic_virt_ctls = (CPU_VIRT_X2APIC | CPU_VIRT_APIC_ACCESSES); 3675 3676 primary = saved_primary; 3677 secondary = saved_secondary; 3678 if (!((ctrl_cpu_rev[1].clr & apic_virt_ctls) == apic_virt_ctls)) 3679 return; 3680 3681 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3682 secondary &= ~CPU_VIRT_APIC_ACCESSES; 3683 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_X2APIC); 3684 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access disabled"); 3685 test_vmx_controls(true, false); 3686 report_prefix_pop(); 3687 3688 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_APIC_ACCESSES); 3689 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access enabled"); 3690 test_vmx_controls(true, false); 3691 report_prefix_pop(); 3692 3693 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_X2APIC); 3694 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access enabled"); 3695 test_vmx_controls(false, false); 3696 report_prefix_pop(); 3697 3698 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_APIC_ACCESSES); 3699 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access disabled"); 3700 test_vmx_controls(true, false); 3701 report_prefix_pop(); 3702 3703 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3704 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3705 } 3706 3707 static void test_apic_ctls(void) 3708 { 3709 test_apic_virt_addr(); 3710 test_apic_access_addr(); 3711 test_apic_virtual_ctls(); 3712 } 3713 3714 static void set_vtpr(unsigned vtpr) 3715 { 3716 *(u32 *)phys_to_virt(vmcs_read(APIC_VIRT_ADDR) + APIC_TASKPRI) = vtpr; 3717 } 3718 3719 static void try_tpr_threshold_and_vtpr(unsigned threshold, unsigned vtpr) 3720 { 3721 bool valid = true; 3722 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 3723 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 3724 3725 if ((primary & CPU_TPR_SHADOW) && 3726 (!(primary & CPU_SECONDARY) || 3727 !(secondary & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 3728 valid = (threshold & 0xf) <= ((vtpr >> 4) & 0xf); 3729 3730 set_vtpr(vtpr); 3731 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0x%x", 3732 threshold, (vtpr >> 4) & 0xf); 3733 test_vmx_controls(valid, false); 3734 report_prefix_pop(); 3735 } 3736 3737 static void test_invalid_event_injection(void) 3738 { 3739 u32 ent_intr_info_save = vmcs_read(ENT_INTR_INFO); 3740 u32 ent_intr_error_save = vmcs_read(ENT_INTR_ERROR); 3741 u32 ent_inst_len_save = vmcs_read(ENT_INST_LEN); 3742 u32 primary_save = vmcs_read(CPU_EXEC_CTRL0); 3743 u32 secondary_save = vmcs_read(CPU_EXEC_CTRL1); 3744 u64 guest_cr0_save = vmcs_read(GUEST_CR0); 3745 u32 ent_intr_info_base = INTR_INFO_VALID_MASK; 3746 u32 ent_intr_info, ent_intr_err, ent_intr_len; 3747 u32 cnt; 3748 3749 /* Setup */ 3750 report_prefix_push("invalid event injection"); 3751 vmcs_write(ENT_INTR_ERROR, 0x00000000); 3752 vmcs_write(ENT_INST_LEN, 0x00000001); 3753 3754 /* The field’s interruption type is not set to a reserved value. */ 3755 ent_intr_info = ent_intr_info_base | INTR_TYPE_RESERVED | DE_VECTOR; 3756 report_prefix_pushf("%s, VM-entry intr info=0x%x", 3757 "RESERVED interruption type invalid [-]", 3758 ent_intr_info); 3759 vmcs_write(ENT_INTR_INFO, ent_intr_info); 3760 test_vmx_controls(false, false); 3761 report_prefix_pop(); 3762 3763 ent_intr_info = ent_intr_info_base | INTR_TYPE_EXT_INTR | 3764 DE_VECTOR; 3765 report_prefix_pushf("%s, VM-entry intr info=0x%x", 3766 "RESERVED interruption type invalid [+]", 3767 ent_intr_info); 3768 vmcs_write(ENT_INTR_INFO, ent_intr_info); 3769 test_vmx_controls(true, false); 3770 report_prefix_pop(); 3771 3772 /* If the interruption type is other event, the vector is 0. */ 3773 ent_intr_info = ent_intr_info_base | INTR_TYPE_OTHER_EVENT | DB_VECTOR; 3774 report_prefix_pushf("%s, VM-entry intr info=0x%x", 3775 "(OTHER EVENT && vector != 0) invalid [-]", 3776 ent_intr_info); 3777 vmcs_write(ENT_INTR_INFO, ent_intr_info); 3778 test_vmx_controls(false, false); 3779 report_prefix_pop(); 3780 3781 /* If the interruption type is NMI, the vector is 2 (negative case). */ 3782 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | DE_VECTOR; 3783 report_prefix_pushf("%s, VM-entry intr info=0x%x", 3784 "(NMI && vector != 2) invalid [-]", ent_intr_info); 3785 vmcs_write(ENT_INTR_INFO, ent_intr_info); 3786 test_vmx_controls(false, false); 3787 report_prefix_pop(); 3788 3789 /* If the interruption type is NMI, the vector is 2 (positive case). */ 3790 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | NMI_VECTOR; 3791 report_prefix_pushf("%s, VM-entry intr info=0x%x", 3792 "(NMI && vector == 2) valid [+]", ent_intr_info); 3793 vmcs_write(ENT_INTR_INFO, ent_intr_info); 3794 test_vmx_controls(true, false); 3795 report_prefix_pop(); 3796 3797 /* 3798 * If the interruption type 3799 * is HW exception, the vector is at most 31. 3800 */ 3801 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 0x20; 3802 report_prefix_pushf("%s, VM-entry intr info=0x%x", 3803 "(HW exception && vector > 31) invalid [-]", 3804 ent_intr_info); 3805 vmcs_write(ENT_INTR_INFO, ent_intr_info); 3806 test_vmx_controls(false, false); 3807 report_prefix_pop(); 3808 3809 /* 3810 * deliver-error-code is 1 iff either 3811 * (a) the "unrestricted guest" VM-execution control is 0 3812 * (b) CR0.PE is set. 3813 */ 3814 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 3815 GP_VECTOR; 3816 report_prefix_pushf("%s, VM-entry intr info=0x%x", 3817 "error code <-> (!URG || prot_mode) [-]", 3818 ent_intr_info); 3819 disable_unrestricted_guest(); 3820 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 3821 vmcs_write(ENT_INTR_INFO, ent_intr_info); 3822 test_vmx_controls(false, false); 3823 report_prefix_pop(); 3824 3825 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 3826 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 3827 report_prefix_pushf("%s, VM-entry intr info=0x%x", 3828 "error code <-> (!URG || prot_mode) [+]", 3829 ent_intr_info); 3830 disable_unrestricted_guest(); 3831 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 3832 vmcs_write(ENT_INTR_INFO, ent_intr_info); 3833 test_vmx_controls(true, false); 3834 report_prefix_pop(); 3835 3836 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 3837 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 3838 report_prefix_pushf("%s, VM-entry intr info=0x%x", 3839 "error code <-> (!URG || prot_mode) [-]", 3840 ent_intr_info); 3841 enable_unrestricted_guest(); 3842 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 3843 vmcs_write(ENT_INTR_INFO, ent_intr_info); 3844 test_vmx_controls(false, false); 3845 report_prefix_pop(); 3846 3847 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 3848 GP_VECTOR; 3849 report_prefix_pushf("%s, VM-entry intr info=0x%x", 3850 "error code <-> (!URG || prot_mode) [-]", 3851 ent_intr_info); 3852 vmcs_write(GUEST_CR0, guest_cr0_save | X86_CR0_PE); 3853 vmcs_write(ENT_INTR_INFO, ent_intr_info); 3854 test_vmx_controls(false, false); 3855 report_prefix_pop(); 3856 3857 /* deliver-error-code is 1 iff the interruption type is HW exception */ 3858 report_prefix_push("error code <-> HW exception"); 3859 for (cnt = 0; cnt < 8; cnt++) { 3860 u32 exception_type_mask = cnt << 8; 3861 u32 deliver_error_code_mask = 3862 exception_type_mask != INTR_TYPE_HARD_EXCEPTION ? 3863 INTR_INFO_DELIVER_CODE_MASK : 0; 3864 3865 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 3866 exception_type_mask | GP_VECTOR; 3867 report_prefix_pushf("VM-entry intr info=0x%x [-]", 3868 ent_intr_info); 3869 vmcs_write(ENT_INTR_INFO, ent_intr_info); 3870 test_vmx_controls(false, false); 3871 report_prefix_pop(); 3872 } 3873 report_prefix_pop(); 3874 3875 /* 3876 * deliver-error-code is 1 iff the the vector 3877 * indicates an exception that would normally deliver an error code 3878 */ 3879 report_prefix_push("error code <-> vector delivers error code"); 3880 for (cnt = 0; cnt < 32; cnt++) { 3881 bool has_error_code = false; 3882 u32 deliver_error_code_mask; 3883 3884 switch (cnt) { 3885 case DF_VECTOR: 3886 case TS_VECTOR: 3887 case NP_VECTOR: 3888 case SS_VECTOR: 3889 case GP_VECTOR: 3890 case PF_VECTOR: 3891 case AC_VECTOR: 3892 has_error_code = true; 3893 } 3894 3895 /* Negative case */ 3896 deliver_error_code_mask = has_error_code ? 3897 0 : 3898 INTR_INFO_DELIVER_CODE_MASK; 3899 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 3900 INTR_TYPE_HARD_EXCEPTION | cnt; 3901 report_prefix_pushf("VM-entry intr info=0x%x [-]", 3902 ent_intr_info); 3903 vmcs_write(ENT_INTR_INFO, ent_intr_info); 3904 test_vmx_controls(false, false); 3905 report_prefix_pop(); 3906 3907 /* Positive case */ 3908 deliver_error_code_mask = has_error_code ? 3909 INTR_INFO_DELIVER_CODE_MASK : 3910 0; 3911 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 3912 INTR_TYPE_HARD_EXCEPTION | cnt; 3913 report_prefix_pushf("VM-entry intr info=0x%x [+]", 3914 ent_intr_info); 3915 vmcs_write(ENT_INTR_INFO, ent_intr_info); 3916 test_vmx_controls(true, false); 3917 report_prefix_pop(); 3918 } 3919 report_prefix_pop(); 3920 3921 /* Reserved bits in the field (30:12) are 0. */ 3922 report_prefix_push("reserved bits clear"); 3923 for (cnt = 12; cnt <= 30; cnt++) { 3924 ent_intr_info = ent_intr_info_base | 3925 INTR_INFO_DELIVER_CODE_MASK | 3926 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR | 3927 (1U << cnt); 3928 report_prefix_pushf("VM-entry intr info=0x%x [-]", 3929 ent_intr_info); 3930 vmcs_write(ENT_INTR_INFO, ent_intr_info); 3931 test_vmx_controls(false, false); 3932 report_prefix_pop(); 3933 } 3934 report_prefix_pop(); 3935 3936 /* 3937 * If deliver-error-code is 1 3938 * bits 31:15 of the VM-entry exception error-code field are 0. 3939 */ 3940 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 3941 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 3942 report_prefix_pushf("%s, VM-entry intr info=0x%x", 3943 "VM-entry exception error code[31:15] clear", 3944 ent_intr_info); 3945 vmcs_write(ENT_INTR_INFO, ent_intr_info); 3946 for (cnt = 15; cnt <= 31; cnt++) { 3947 ent_intr_err = 1U << cnt; 3948 report_prefix_pushf("VM-entry intr error=0x%x [-]", 3949 ent_intr_err); 3950 vmcs_write(ENT_INTR_ERROR, ent_intr_err); 3951 test_vmx_controls(false, false); 3952 report_prefix_pop(); 3953 } 3954 vmcs_write(ENT_INTR_ERROR, 0x00000000); 3955 report_prefix_pop(); 3956 3957 /* 3958 * If the interruption type is software interrupt, software exception, 3959 * or privileged software exception, the VM-entry instruction-length 3960 * field is in the range 0–15. 3961 */ 3962 3963 for (cnt = 0; cnt < 3; cnt++) { 3964 switch (cnt) { 3965 case 0: 3966 ent_intr_info = ent_intr_info_base | 3967 INTR_TYPE_SOFT_INTR; 3968 break; 3969 case 1: 3970 ent_intr_info = ent_intr_info_base | 3971 INTR_TYPE_SOFT_EXCEPTION; 3972 break; 3973 case 2: 3974 ent_intr_info = ent_intr_info_base | 3975 INTR_TYPE_PRIV_SW_EXCEPTION; 3976 break; 3977 } 3978 report_prefix_pushf("%s, VM-entry intr info=0x%x", 3979 "VM-entry instruction-length check", 3980 ent_intr_info); 3981 vmcs_write(ENT_INTR_INFO, ent_intr_info); 3982 3983 /* Instruction length set to -1 (0xFFFFFFFF) should fail */ 3984 ent_intr_len = -1; 3985 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 3986 ent_intr_len); 3987 vmcs_write(ENT_INST_LEN, ent_intr_len); 3988 test_vmx_controls(false, false); 3989 report_prefix_pop(); 3990 3991 /* Instruction length set to 16 should fail */ 3992 ent_intr_len = 0x00000010; 3993 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 3994 ent_intr_len); 3995 vmcs_write(ENT_INST_LEN, 0x00000010); 3996 test_vmx_controls(false, false); 3997 report_prefix_pop(); 3998 3999 report_prefix_pop(); 4000 } 4001 4002 /* Cleanup */ 4003 vmcs_write(ENT_INTR_INFO, ent_intr_info_save); 4004 vmcs_write(ENT_INTR_ERROR, ent_intr_error_save); 4005 vmcs_write(ENT_INST_LEN, ent_inst_len_save); 4006 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4007 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4008 vmcs_write(GUEST_CR0, guest_cr0_save); 4009 report_prefix_pop(); 4010 } 4011 4012 /* 4013 * Test interesting vTPR values for a given TPR threshold. 4014 */ 4015 static void test_vtpr_values(unsigned threshold) 4016 { 4017 try_tpr_threshold_and_vtpr(threshold, (threshold - 1) << 4); 4018 try_tpr_threshold_and_vtpr(threshold, threshold << 4); 4019 try_tpr_threshold_and_vtpr(threshold, (threshold + 1) << 4); 4020 } 4021 4022 static void try_tpr_threshold(unsigned threshold) 4023 { 4024 bool valid = true; 4025 4026 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4027 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4028 4029 if ((primary & CPU_TPR_SHADOW) && !((primary & CPU_SECONDARY) && 4030 (secondary & CPU_VINTD))) 4031 valid = !(threshold >> 4); 4032 4033 set_vtpr(-1); 4034 vmcs_write(TPR_THRESHOLD, threshold); 4035 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0xf", threshold); 4036 test_vmx_controls(valid, false); 4037 report_prefix_pop(); 4038 4039 if (valid) 4040 test_vtpr_values(threshold); 4041 } 4042 4043 /* 4044 * Test interesting TPR threshold values. 4045 */ 4046 static void test_tpr_threshold_values(void) 4047 { 4048 unsigned i; 4049 4050 for (i = 0; i < 0x10; i++) 4051 try_tpr_threshold(i); 4052 for (i = 4; i < 32; i++) 4053 try_tpr_threshold(1u << i); 4054 try_tpr_threshold(-1u); 4055 try_tpr_threshold(0x7fffffff); 4056 } 4057 4058 /* 4059 * This test covers the following two VM entry checks: 4060 * 4061 * i) If the "use TPR shadow" VM-execution control is 1 and the 4062 * "virtual-interrupt delivery" VM-execution control is 0, bits 4063 * 31:4 of the TPR threshold VM-execution control field must 4064 be 0. 4065 * [Intel SDM] 4066 * 4067 * ii) If the "use TPR shadow" VM-execution control is 1, the 4068 * "virtual-interrupt delivery" VM-execution control is 0 4069 * and the "virtualize APIC accesses" VM-execution control 4070 * is 0, the value of bits 3:0 of the TPR threshold VM-execution 4071 * control field must not be greater than the value of bits 4072 * 7:4 of VTPR. 4073 * [Intel SDM] 4074 */ 4075 static void test_tpr_threshold(void) 4076 { 4077 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4078 void *virtual_apic_page; 4079 4080 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) 4081 return; 4082 4083 virtual_apic_page = alloc_page(); 4084 memset(virtual_apic_page, 0xff, PAGE_SIZE); 4085 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 4086 4087 vmcs_write(CPU_EXEC_CTRL0, primary & ~(CPU_TPR_SHADOW | CPU_SECONDARY)); 4088 report_prefix_pushf("Use TPR shadow disabled, secondary controls disabled"); 4089 test_tpr_threshold_values(); 4090 report_prefix_pop(); 4091 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_TPR_SHADOW); 4092 report_prefix_pushf("Use TPR shadow enabled, secondary controls disabled"); 4093 test_tpr_threshold_values(); 4094 report_prefix_pop(); 4095 4096 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4097 (ctrl_cpu_rev[1].clr & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) { 4098 vmcs_write(CPU_EXEC_CTRL0, primary); 4099 return; 4100 } 4101 4102 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4103 4104 if (ctrl_cpu_rev[1].clr & CPU_VINTD) { 4105 vmcs_write(CPU_EXEC_CTRL1, CPU_VINTD); 4106 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4107 test_tpr_threshold_values(); 4108 report_prefix_pop(); 4109 4110 vmcs_write(CPU_EXEC_CTRL0, 4111 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4112 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4113 test_tpr_threshold_values(); 4114 report_prefix_pop(); 4115 } 4116 4117 if (ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES) { 4118 vmcs_write(CPU_EXEC_CTRL0, 4119 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4120 vmcs_write(CPU_EXEC_CTRL1, CPU_VIRT_APIC_ACCESSES); 4121 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4122 test_tpr_threshold_values(); 4123 report_prefix_pop(); 4124 4125 vmcs_write(CPU_EXEC_CTRL0, 4126 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4127 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4128 test_tpr_threshold_values(); 4129 report_prefix_pop(); 4130 } 4131 4132 if ((ctrl_cpu_rev[1].clr & 4133 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) == 4134 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) { 4135 vmcs_write(CPU_EXEC_CTRL0, 4136 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4137 vmcs_write(CPU_EXEC_CTRL1, 4138 CPU_VINTD | CPU_VIRT_APIC_ACCESSES); 4139 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4140 test_tpr_threshold_values(); 4141 report_prefix_pop(); 4142 4143 vmcs_write(CPU_EXEC_CTRL0, 4144 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4145 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4146 test_tpr_threshold_values(); 4147 report_prefix_pop(); 4148 } 4149 4150 vmcs_write(CPU_EXEC_CTRL1, secondary); 4151 vmcs_write(CPU_EXEC_CTRL0, primary); 4152 } 4153 4154 /* 4155 * This test verifies the following two vmentry checks: 4156 * 4157 * If the "NMI exiting" VM-execution control is 0, "Virtual NMIs" 4158 * VM-execution control must be 0. 4159 * [Intel SDM] 4160 * 4161 * If the “virtual NMIs” VM-execution control is 0, the “NMI-window 4162 * exiting” VM-execution control must be 0. 4163 * [Intel SDM] 4164 */ 4165 static void test_nmi_ctrls(void) 4166 { 4167 u32 pin_ctrls, cpu_ctrls0, test_pin_ctrls, test_cpu_ctrls0; 4168 4169 if ((ctrl_pin_rev.clr & (PIN_NMI | PIN_VIRT_NMI)) != 4170 (PIN_NMI | PIN_VIRT_NMI)) { 4171 test_skip("NMI exiting and Virtual NMIs are not supported !"); 4172 return; 4173 } 4174 4175 /* Save the controls so that we can restore them after our tests */ 4176 pin_ctrls = vmcs_read(PIN_CONTROLS); 4177 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 4178 4179 test_pin_ctrls = pin_ctrls & ~(PIN_NMI | PIN_VIRT_NMI); 4180 test_cpu_ctrls0 = cpu_ctrls0 & ~CPU_NMI_WINDOW; 4181 4182 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4183 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs disabled"); 4184 test_vmx_controls(true, false); 4185 report_prefix_pop(); 4186 4187 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_VIRT_NMI); 4188 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs enabled"); 4189 test_vmx_controls(false, false); 4190 report_prefix_pop(); 4191 4192 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4193 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs enabled"); 4194 test_vmx_controls(true, false); 4195 report_prefix_pop(); 4196 4197 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_NMI); 4198 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs disabled"); 4199 test_vmx_controls(true, false); 4200 report_prefix_pop(); 4201 4202 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 4203 report_info("NMI-window exiting is not supported, skipping..."); 4204 goto done; 4205 } 4206 4207 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4208 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4209 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting enabled"); 4210 test_vmx_controls(false, false); 4211 report_prefix_pop(); 4212 4213 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4214 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4215 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting disabled"); 4216 test_vmx_controls(true, false); 4217 report_prefix_pop(); 4218 4219 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4220 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4221 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting enabled"); 4222 test_vmx_controls(true, false); 4223 report_prefix_pop(); 4224 4225 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4226 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4227 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting disabled"); 4228 test_vmx_controls(true, false); 4229 report_prefix_pop(); 4230 4231 /* Restore the controls to their original values */ 4232 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 4233 done: 4234 vmcs_write(PIN_CONTROLS, pin_ctrls); 4235 } 4236 4237 4238 /* 4239 * Check that the virtual CPU checks all of the VMX controls as 4240 * documented in the Intel SDM. 4241 */ 4242 static void vmx_controls_test(void) 4243 { 4244 /* 4245 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 4246 * fail due to invalid guest state, should we make it that 4247 * far. 4248 */ 4249 vmcs_write(GUEST_RFLAGS, 0); 4250 4251 test_pin_based_ctls(); 4252 test_primary_processor_based_ctls(); 4253 test_secondary_processor_based_ctls(); 4254 test_cr3_targets(); 4255 test_io_bitmaps(); 4256 test_msr_bitmap(); 4257 test_apic_ctls(); 4258 test_tpr_threshold(); 4259 test_nmi_ctrls(); 4260 test_invalid_event_injection(); 4261 } 4262 4263 static bool valid_vmcs_for_vmentry(void) 4264 { 4265 struct vmcs *current_vmcs = NULL; 4266 4267 if (vmcs_save(¤t_vmcs)) 4268 return false; 4269 4270 return current_vmcs && !current_vmcs->hdr.shadow_vmcs; 4271 } 4272 4273 static void try_vmentry_in_movss_shadow(void) 4274 { 4275 u32 vm_inst_err; 4276 u32 flags; 4277 bool early_failure = false; 4278 u32 expected_flags = X86_EFLAGS_FIXED; 4279 bool valid_vmcs = valid_vmcs_for_vmentry(); 4280 4281 expected_flags |= valid_vmcs ? X86_EFLAGS_ZF : X86_EFLAGS_CF; 4282 4283 /* 4284 * Indirectly set VM_INST_ERR to 12 ("VMREAD/VMWRITE from/to 4285 * unsupported VMCS component"). 4286 */ 4287 vmcs_write(~0u, 0); 4288 4289 __asm__ __volatile__ ("mov %[host_rsp], %%edx;" 4290 "vmwrite %%rsp, %%rdx;" 4291 "mov 0f, %%rax;" 4292 "mov %[host_rip], %%edx;" 4293 "vmwrite %%rax, %%rdx;" 4294 "mov $-1, %%ah;" 4295 "sahf;" 4296 "mov %%ss, %%ax;" 4297 "mov %%ax, %%ss;" 4298 "vmlaunch;" 4299 "mov $1, %[early_failure];" 4300 "0: lahf;" 4301 "movzbl %%ah, %[flags]" 4302 : [early_failure] "+r" (early_failure), 4303 [flags] "=&a" (flags) 4304 : [host_rsp] "i" (HOST_RSP), 4305 [host_rip] "i" (HOST_RIP) 4306 : "rdx", "cc", "memory"); 4307 vm_inst_err = vmcs_read(VMX_INST_ERROR); 4308 4309 report("Early VM-entry failure", early_failure); 4310 report("RFLAGS[8:0] is %x (actual %x)", flags == expected_flags, 4311 expected_flags, flags); 4312 if (valid_vmcs) 4313 report("VM-instruction error is %d (actual %d)", 4314 vm_inst_err == VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, 4315 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, vm_inst_err); 4316 } 4317 4318 static void vmentry_movss_shadow_test(void) 4319 { 4320 struct vmcs *orig_vmcs; 4321 4322 TEST_ASSERT(!vmcs_save(&orig_vmcs)); 4323 4324 /* 4325 * Set the launched flag on the current VMCS to verify the correct 4326 * error priority, below. 4327 */ 4328 test_set_guest(v2_null_test_guest); 4329 enter_guest(); 4330 4331 /* 4332 * With bit 1 of the guest's RFLAGS clear, VM-entry should 4333 * fail due to invalid guest state (if we make it that far). 4334 */ 4335 vmcs_write(GUEST_RFLAGS, 0); 4336 4337 /* 4338 * "VM entry with events blocked by MOV SS" takes precedence over 4339 * "VMLAUNCH with non-clear VMCS." 4340 */ 4341 report_prefix_push("valid current-VMCS"); 4342 try_vmentry_in_movss_shadow(); 4343 report_prefix_pop(); 4344 4345 /* 4346 * VMfailInvalid takes precedence over "VM entry with events 4347 * blocked by MOV SS." 4348 */ 4349 TEST_ASSERT(!vmcs_clear(orig_vmcs)); 4350 report_prefix_push("no current-VMCS"); 4351 try_vmentry_in_movss_shadow(); 4352 report_prefix_pop(); 4353 4354 TEST_ASSERT(!make_vmcs_current(orig_vmcs)); 4355 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 4356 } 4357 4358 #define X86_FEATURE_PCID (1 << 17) 4359 #define X86_FEATURE_MCE (1 << 7) 4360 4361 static int write_cr4_checking(unsigned long val) 4362 { 4363 asm volatile(ASM_TRY("1f") 4364 "mov %0, %%cr4\n\t" 4365 "1:": : "r" (val)); 4366 return exception_vector(); 4367 } 4368 4369 static void vmx_cr_load_test(void) 4370 { 4371 struct cpuid _cpuid = cpuid(1); 4372 unsigned long cr4 = read_cr4(), cr3 = read_cr3(); 4373 4374 if (!(_cpuid.c & X86_FEATURE_PCID)) { 4375 report_skip("PCID not detected"); 4376 return; 4377 } 4378 if (!(_cpuid.d & X86_FEATURE_MCE)) { 4379 report_skip("MCE not detected"); 4380 return; 4381 } 4382 4383 TEST_ASSERT(!(cr4 & (X86_CR4_PCIDE | X86_CR4_MCE))); 4384 TEST_ASSERT(!(cr3 & X86_CR3_PCID_MASK)); 4385 4386 /* Enable PCID for L1. */ 4387 cr4 |= X86_CR4_PCIDE; 4388 cr3 |= 0x1; 4389 TEST_ASSERT(!write_cr4_checking(cr4)); 4390 write_cr3(cr3); 4391 4392 test_set_guest(v2_null_test_guest); 4393 vmcs_write(HOST_CR4, cr4); 4394 vmcs_write(HOST_CR3, cr3); 4395 enter_guest(); 4396 4397 /* 4398 * No exception is expected. 4399 * 4400 * NB. KVM loads the last guest write to CR4 into CR4 read 4401 * shadow. In order to trigger an exit to KVM, we can set a 4402 * bit that was zero in the above CR4 write and is owned by 4403 * KVM. We choose to set CR4.MCE, which shall have no side 4404 * effect because normally no guest MCE (e.g., as the result 4405 * of bad memory) would happen during this test. 4406 */ 4407 TEST_ASSERT(!write_cr4_checking(cr4 | X86_CR4_MCE)); 4408 4409 /* Cleanup L1 state: disable PCID. */ 4410 write_cr3(cr3 & ~X86_CR3_PCID_MASK); 4411 TEST_ASSERT(!write_cr4_checking(cr4 & ~X86_CR4_PCIDE)); 4412 } 4413 4414 static bool cpu_has_apicv(void) 4415 { 4416 return ((ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT) && 4417 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 4418 (ctrl_pin_rev.clr & PIN_POST_INTR)); 4419 } 4420 4421 static void trigger_ioapic_scan_thread(void *data) 4422 { 4423 /* Wait until other CPU entered L2 */ 4424 while (vmx_get_test_stage() != 1) 4425 ; 4426 4427 /* Trigger ioapic scan */ 4428 ioapic_set_redir(0xf, 0x79, TRIGGER_LEVEL); 4429 vmx_set_test_stage(2); 4430 } 4431 4432 static void irq_79_handler_guest(isr_regs_t *regs) 4433 { 4434 eoi(); 4435 4436 /* L1 expects vmexit on VMX_VMCALL and not VMX_EOI_INDUCED */ 4437 vmcall(); 4438 } 4439 4440 /* 4441 * Constant for num of busy-loop iterations after which 4442 * a timer interrupt should have happened in host 4443 */ 4444 #define TIMER_INTERRUPT_DELAY 100000000 4445 4446 static void vmx_eoi_bitmap_ioapic_scan_test_guest(void) 4447 { 4448 handle_irq(0x79, irq_79_handler_guest); 4449 irq_enable(); 4450 4451 /* Signal to L1 CPU to trigger ioapic scan */ 4452 vmx_set_test_stage(1); 4453 /* Wait until L1 CPU to trigger ioapic scan */ 4454 while (vmx_get_test_stage() != 2) 4455 ; 4456 4457 /* 4458 * Wait for L0 timer interrupt to be raised while we run in L2 4459 * such that L0 will process the IOAPIC scan request before 4460 * resuming L2 4461 */ 4462 delay(TIMER_INTERRUPT_DELAY); 4463 4464 asm volatile ("int $0x79"); 4465 } 4466 4467 static void vmx_eoi_bitmap_ioapic_scan_test(void) 4468 { 4469 void *msr_bitmap; 4470 void *virtual_apic_page; 4471 4472 if (!cpu_has_apicv() || (cpu_count() < 2)) { 4473 report_skip(__func__); 4474 return; 4475 } 4476 4477 msr_bitmap = alloc_page(); 4478 virtual_apic_page = alloc_page(); 4479 4480 u64 cpu_ctrl_0 = CPU_SECONDARY | CPU_TPR_SHADOW | CPU_MSR_BITMAP; 4481 u64 cpu_ctrl_1 = CPU_VINTD | CPU_VIRT_X2APIC; 4482 4483 memset(msr_bitmap, 0x0, PAGE_SIZE); 4484 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 4485 4486 vmcs_write(APIC_VIRT_ADDR, (u64)virtual_apic_page); 4487 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 4488 4489 vmcs_write(EOI_EXIT_BITMAP0, 0x0); 4490 vmcs_write(EOI_EXIT_BITMAP1, 0x0); 4491 vmcs_write(EOI_EXIT_BITMAP2, 0x0); 4492 vmcs_write(EOI_EXIT_BITMAP3, 0x0); 4493 4494 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 4495 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 4496 4497 on_cpu_async(1, trigger_ioapic_scan_thread, NULL); 4498 test_set_guest(vmx_eoi_bitmap_ioapic_scan_test_guest); 4499 4500 /* 4501 * Launch L2. 4502 * We expect the exit reason to be VMX_VMCALL (and not EOI INDUCED). 4503 * In case the reason isn't VMX_VMCALL, the asserion inside 4504 * skip_exit_vmcall() will fail. 4505 */ 4506 enter_guest(); 4507 skip_exit_vmcall(); 4508 4509 /* Let L2 finish */ 4510 enter_guest(); 4511 report(__func__, 1); 4512 } 4513 4514 static void set_irq_line_thread(void *data) 4515 { 4516 /* Wait until other CPU entered L2 */ 4517 while (vmx_get_test_stage() != 1) 4518 ; 4519 4520 /* Set irq-line 0xf to raise vector 0x78 for vCPU 0 */ 4521 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 4522 vmx_set_test_stage(2); 4523 } 4524 4525 static bool irq_78_handler_vmcall_before_eoi; 4526 static void irq_78_handler_guest(isr_regs_t *regs) 4527 { 4528 set_irq_line(0xf, 0); 4529 if (irq_78_handler_vmcall_before_eoi) 4530 vmcall(); 4531 eoi(); 4532 vmcall(); 4533 } 4534 4535 static void vmx_apic_passthrough_guest(void) 4536 { 4537 handle_irq(0x78, irq_78_handler_guest); 4538 irq_enable(); 4539 4540 /* If requested, wait for other CPU to trigger ioapic scan */ 4541 if (vmx_get_test_stage() < 1) { 4542 vmx_set_test_stage(1); 4543 while (vmx_get_test_stage() != 2) 4544 ; 4545 } 4546 4547 set_irq_line(0xf, 1); 4548 } 4549 4550 static void vmx_apic_passthrough(bool set_irq_line_from_thread) 4551 { 4552 void *msr_bitmap; 4553 4554 if (set_irq_line_from_thread && (cpu_count() < 2)) { 4555 report_skip(__func__); 4556 return; 4557 } 4558 4559 msr_bitmap = alloc_page(); 4560 4561 u64 cpu_ctrl_0 = CPU_SECONDARY | CPU_MSR_BITMAP; 4562 u64 cpu_ctrl_1 = 0; 4563 4564 memset(msr_bitmap, 0x0, PAGE_SIZE); 4565 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 4566 4567 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 4568 4569 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 4570 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 4571 4572 if (set_irq_line_from_thread) { 4573 irq_78_handler_vmcall_before_eoi = false; 4574 on_cpu_async(1, set_irq_line_thread, NULL); 4575 } else { 4576 irq_78_handler_vmcall_before_eoi = true; 4577 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 4578 vmx_set_test_stage(2); 4579 } 4580 test_set_guest(vmx_apic_passthrough_guest); 4581 4582 if (irq_78_handler_vmcall_before_eoi) { 4583 /* Before EOI remote_irr should still be set */ 4584 enter_guest(); 4585 skip_exit_vmcall(); 4586 TEST_ASSERT_EQ_MSG(1, (int)ioapic_read_redir(0xf).remote_irr, 4587 "IOAPIC pass-through: remote_irr=1 before EOI"); 4588 } 4589 4590 /* After EOI remote_irr should be cleared */ 4591 enter_guest(); 4592 skip_exit_vmcall(); 4593 TEST_ASSERT_EQ_MSG(0, (int)ioapic_read_redir(0xf).remote_irr, 4594 "IOAPIC pass-through: remote_irr=0 after EOI"); 4595 4596 /* Let L2 finish */ 4597 enter_guest(); 4598 report(__func__, 1); 4599 } 4600 4601 static void vmx_apic_passthrough_test(void) 4602 { 4603 vmx_apic_passthrough(false); 4604 } 4605 4606 static void vmx_apic_passthrough_thread_test(void) 4607 { 4608 vmx_apic_passthrough(true); 4609 } 4610 4611 enum vmcs_access { 4612 ACCESS_VMREAD, 4613 ACCESS_VMWRITE, 4614 ACCESS_NONE, 4615 }; 4616 4617 struct vmcs_shadow_test_common { 4618 enum vmcs_access op; 4619 enum Reason reason; 4620 u64 field; 4621 u64 value; 4622 u64 flags; 4623 u64 time; 4624 } l1_l2_common; 4625 4626 static inline u64 vmread_flags(u64 field, u64 *val) 4627 { 4628 u64 flags; 4629 4630 asm volatile ("vmread %2, %1; pushf; pop %0" 4631 : "=r" (flags), "=rm" (*val) : "r" (field) : "cc"); 4632 return flags & X86_EFLAGS_ALU; 4633 } 4634 4635 static inline u64 vmwrite_flags(u64 field, u64 val) 4636 { 4637 u64 flags; 4638 4639 asm volatile ("vmwrite %1, %2; pushf; pop %0" 4640 : "=r"(flags) : "rm" (val), "r" (field) : "cc"); 4641 return flags & X86_EFLAGS_ALU; 4642 } 4643 4644 static void vmx_vmcs_shadow_test_guest(void) 4645 { 4646 struct vmcs_shadow_test_common *c = &l1_l2_common; 4647 u64 start; 4648 4649 while (c->op != ACCESS_NONE) { 4650 start = rdtsc(); 4651 switch (c->op) { 4652 default: 4653 c->flags = -1ull; 4654 break; 4655 case ACCESS_VMREAD: 4656 c->flags = vmread_flags(c->field, &c->value); 4657 break; 4658 case ACCESS_VMWRITE: 4659 c->flags = vmwrite_flags(c->field, 0); 4660 break; 4661 } 4662 c->time = rdtsc() - start; 4663 vmcall(); 4664 } 4665 } 4666 4667 static u64 vmread_from_shadow(u64 field) 4668 { 4669 struct vmcs *primary; 4670 struct vmcs *shadow; 4671 u64 value; 4672 4673 TEST_ASSERT(!vmcs_save(&primary)); 4674 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 4675 TEST_ASSERT(!make_vmcs_current(shadow)); 4676 value = vmcs_read(field); 4677 TEST_ASSERT(!make_vmcs_current(primary)); 4678 return value; 4679 } 4680 4681 static u64 vmwrite_to_shadow(u64 field, u64 value) 4682 { 4683 struct vmcs *primary; 4684 struct vmcs *shadow; 4685 4686 TEST_ASSERT(!vmcs_save(&primary)); 4687 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 4688 TEST_ASSERT(!make_vmcs_current(shadow)); 4689 vmcs_write(field, value); 4690 value = vmcs_read(field); 4691 TEST_ASSERT(!make_vmcs_current(primary)); 4692 return value; 4693 } 4694 4695 static void vmcs_shadow_test_access(u8 *bitmap[2], enum vmcs_access access) 4696 { 4697 struct vmcs_shadow_test_common *c = &l1_l2_common; 4698 4699 c->op = access; 4700 vmcs_write(VMX_INST_ERROR, 0); 4701 enter_guest(); 4702 c->reason = vmcs_read(EXI_REASON) & 0xffff; 4703 if (c->reason != VMX_VMCALL) { 4704 skip_exit_insn(); 4705 enter_guest(); 4706 } 4707 skip_exit_vmcall(); 4708 } 4709 4710 static void vmcs_shadow_test_field(u8 *bitmap[2], u64 field) 4711 { 4712 struct vmcs_shadow_test_common *c = &l1_l2_common; 4713 struct vmcs *shadow; 4714 u64 value; 4715 uintptr_t flags[2]; 4716 bool good_shadow; 4717 u32 vmx_inst_error; 4718 4719 report_prefix_pushf("field %lx", field); 4720 c->field = field; 4721 4722 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 4723 if (shadow != (struct vmcs *)-1ull) { 4724 flags[ACCESS_VMREAD] = vmread_flags(field, &value); 4725 flags[ACCESS_VMWRITE] = vmwrite_flags(field, value); 4726 good_shadow = !flags[ACCESS_VMREAD] && !flags[ACCESS_VMWRITE]; 4727 } else { 4728 /* 4729 * When VMCS link pointer is -1ull, VMWRITE/VMREAD on 4730 * shadowed-fields should fail with setting RFLAGS.CF. 4731 */ 4732 flags[ACCESS_VMREAD] = X86_EFLAGS_CF; 4733 flags[ACCESS_VMWRITE] = X86_EFLAGS_CF; 4734 good_shadow = false; 4735 } 4736 4737 /* Intercept both VMREAD and VMWRITE. */ 4738 report_prefix_push("no VMREAD/VMWRITE permission"); 4739 /* VMWRITE/VMREAD done on reserved-bit should always intercept */ 4740 if (!(field >> VMCS_FIELD_RESERVED_SHIFT)) { 4741 set_bit(field, bitmap[ACCESS_VMREAD]); 4742 set_bit(field, bitmap[ACCESS_VMWRITE]); 4743 } 4744 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 4745 report("not shadowed for VMWRITE", c->reason == VMX_VMWRITE); 4746 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 4747 report("not shadowed for VMREAD", c->reason == VMX_VMREAD); 4748 report_prefix_pop(); 4749 4750 if (field >> VMCS_FIELD_RESERVED_SHIFT) 4751 goto out; 4752 4753 /* Permit shadowed VMREAD. */ 4754 report_prefix_push("VMREAD permission only"); 4755 clear_bit(field, bitmap[ACCESS_VMREAD]); 4756 set_bit(field, bitmap[ACCESS_VMWRITE]); 4757 if (good_shadow) 4758 value = vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 4759 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 4760 report("not shadowed for VMWRITE", c->reason == VMX_VMWRITE); 4761 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 4762 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 4763 report("shadowed for VMREAD (in %ld cycles)", c->reason == VMX_VMCALL, 4764 c->time); 4765 report("ALU flags after VMREAD (%lx) are as expected (%lx)", 4766 c->flags == flags[ACCESS_VMREAD], 4767 c->flags, flags[ACCESS_VMREAD]); 4768 if (good_shadow) 4769 report("value read from shadow (%lx) is as expected (%lx)", 4770 c->value == value, c->value, value); 4771 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 4772 report("VMX_INST_ERROR (%d) is as expected (%d)", 4773 vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 4774 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 4775 report_prefix_pop(); 4776 4777 /* Permit shadowed VMWRITE. */ 4778 report_prefix_push("VMWRITE permission only"); 4779 set_bit(field, bitmap[ACCESS_VMREAD]); 4780 clear_bit(field, bitmap[ACCESS_VMWRITE]); 4781 if (good_shadow) 4782 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 4783 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 4784 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 4785 report("shadowed for VMWRITE (in %ld cycles)", c->reason == VMX_VMCALL, 4786 c->time); 4787 report("ALU flags after VMWRITE (%lx) are as expected (%lx)", 4788 c->flags == flags[ACCESS_VMREAD], 4789 c->flags, flags[ACCESS_VMREAD]); 4790 if (good_shadow) { 4791 value = vmread_from_shadow(field); 4792 report("shadow VMCS value (%lx) is as expected (%lx)", 4793 value == 0, value, 0ul); 4794 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 4795 report("VMX_INST_ERROR (%d) is as expected (%d)", 4796 vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 4797 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 4798 } 4799 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 4800 report("not shadowed for VMREAD", c->reason == VMX_VMREAD); 4801 report_prefix_pop(); 4802 4803 /* Permit shadowed VMREAD and VMWRITE. */ 4804 report_prefix_push("VMREAD and VMWRITE permission"); 4805 clear_bit(field, bitmap[ACCESS_VMREAD]); 4806 clear_bit(field, bitmap[ACCESS_VMWRITE]); 4807 if (good_shadow) 4808 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 4809 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 4810 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 4811 report("shadowed for VMWRITE (in %ld cycles)", c->reason == VMX_VMCALL, 4812 c->time); 4813 report("ALU flags after VMWRITE (%lx) are as expected (%lx)", 4814 c->flags == flags[ACCESS_VMREAD], 4815 c->flags, flags[ACCESS_VMREAD]); 4816 if (good_shadow) { 4817 value = vmread_from_shadow(field); 4818 report("shadow VMCS value (%lx) is as expected (%lx)", 4819 value == 0, value, 0ul); 4820 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 4821 report("VMX_INST_ERROR (%d) is as expected (%d)", 4822 vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 4823 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 4824 } 4825 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 4826 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 4827 report("shadowed for VMREAD (in %ld cycles)", c->reason == VMX_VMCALL, 4828 c->time); 4829 report("ALU flags after VMREAD (%lx) are as expected (%lx)", 4830 c->flags == flags[ACCESS_VMREAD], 4831 c->flags, flags[ACCESS_VMREAD]); 4832 if (good_shadow) 4833 report("value read from shadow (%lx) is as expected (%lx)", 4834 c->value == 0, c->value, 0ul); 4835 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 4836 report("VMX_INST_ERROR (%d) is as expected (%d)", 4837 vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 4838 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 4839 report_prefix_pop(); 4840 4841 out: 4842 report_prefix_pop(); 4843 } 4844 4845 static void vmx_vmcs_shadow_test_body(u8 *bitmap[2]) 4846 { 4847 unsigned base; 4848 unsigned index; 4849 unsigned bit; 4850 unsigned highest_index = rdmsr(MSR_IA32_VMX_VMCS_ENUM); 4851 4852 /* Run test on all possible valid VMCS fields */ 4853 for (base = 0; 4854 base < (1 << VMCS_FIELD_RESERVED_SHIFT); 4855 base += (1 << VMCS_FIELD_TYPE_SHIFT)) 4856 for (index = 0; index <= highest_index; index++) 4857 vmcs_shadow_test_field(bitmap, base + index); 4858 4859 /* 4860 * Run tests on some invalid VMCS fields 4861 * (Have reserved bit set). 4862 */ 4863 for (bit = VMCS_FIELD_RESERVED_SHIFT; bit < VMCS_FIELD_BIT_SIZE; bit++) 4864 vmcs_shadow_test_field(bitmap, (1ull << bit)); 4865 } 4866 4867 static void vmx_vmcs_shadow_test(void) 4868 { 4869 u8 *bitmap[2]; 4870 struct vmcs *shadow; 4871 4872 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 4873 printf("\t'Activate secondary controls' not supported.\n"); 4874 return; 4875 } 4876 4877 if (!(ctrl_cpu_rev[1].clr & CPU_SHADOW_VMCS)) { 4878 printf("\t'VMCS shadowing' not supported.\n"); 4879 return; 4880 } 4881 4882 if (!(rdmsr(MSR_IA32_VMX_MISC) & 4883 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS)) { 4884 printf("\tVMWRITE can't modify VM-exit information fields.\n"); 4885 return; 4886 } 4887 4888 test_set_guest(vmx_vmcs_shadow_test_guest); 4889 4890 bitmap[ACCESS_VMREAD] = alloc_page(); 4891 bitmap[ACCESS_VMWRITE] = alloc_page(); 4892 4893 vmcs_write(VMREAD_BITMAP, virt_to_phys(bitmap[ACCESS_VMREAD])); 4894 vmcs_write(VMWRITE_BITMAP, virt_to_phys(bitmap[ACCESS_VMWRITE])); 4895 4896 shadow = alloc_page(); 4897 shadow->hdr.revision_id = basic.revision; 4898 shadow->hdr.shadow_vmcs = 1; 4899 TEST_ASSERT(!vmcs_clear(shadow)); 4900 4901 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_RDTSC); 4902 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY); 4903 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_SHADOW_VMCS); 4904 4905 vmcs_write(VMCS_LINK_PTR, virt_to_phys(shadow)); 4906 report_prefix_push("valid link pointer"); 4907 vmx_vmcs_shadow_test_body(bitmap); 4908 report_prefix_pop(); 4909 4910 vmcs_write(VMCS_LINK_PTR, -1ull); 4911 report_prefix_push("invalid link pointer"); 4912 vmx_vmcs_shadow_test_body(bitmap); 4913 report_prefix_pop(); 4914 4915 l1_l2_common.op = ACCESS_NONE; 4916 enter_guest(); 4917 } 4918 4919 #define TEST(name) { #name, .v2 = name } 4920 4921 /* name/init/guest_main/exit_handler/syscall_handler/guest_regs */ 4922 struct vmx_test vmx_tests[] = { 4923 { "null", NULL, basic_guest_main, basic_exit_handler, NULL, {0} }, 4924 { "vmenter", NULL, vmenter_main, vmenter_exit_handler, NULL, {0} }, 4925 { "preemption timer", preemption_timer_init, preemption_timer_main, 4926 preemption_timer_exit_handler, NULL, {0} }, 4927 { "control field PAT", test_ctrl_pat_init, test_ctrl_pat_main, 4928 test_ctrl_pat_exit_handler, NULL, {0} }, 4929 { "control field EFER", test_ctrl_efer_init, test_ctrl_efer_main, 4930 test_ctrl_efer_exit_handler, NULL, {0} }, 4931 { "CR shadowing", NULL, cr_shadowing_main, 4932 cr_shadowing_exit_handler, NULL, {0} }, 4933 { "I/O bitmap", iobmp_init, iobmp_main, iobmp_exit_handler, 4934 NULL, {0} }, 4935 { "instruction intercept", insn_intercept_init, insn_intercept_main, 4936 insn_intercept_exit_handler, NULL, {0} }, 4937 { "EPT A/D disabled", ept_init, ept_main, ept_exit_handler, NULL, {0} }, 4938 { "EPT A/D enabled", eptad_init, eptad_main, eptad_exit_handler, NULL, {0} }, 4939 { "PML", pml_init, pml_main, pml_exit_handler, NULL, {0} }, 4940 { "VPID", vpid_init, vpid_main, vpid_exit_handler, NULL, {0} }, 4941 { "interrupt", interrupt_init, interrupt_main, 4942 interrupt_exit_handler, NULL, {0} }, 4943 { "debug controls", dbgctls_init, dbgctls_main, dbgctls_exit_handler, 4944 NULL, {0} }, 4945 { "MSR switch", msr_switch_init, msr_switch_main, 4946 msr_switch_exit_handler, NULL, {0}, msr_switch_entry_failure }, 4947 { "vmmcall", vmmcall_init, vmmcall_main, vmmcall_exit_handler, NULL, {0} }, 4948 { "disable RDTSCP", disable_rdtscp_init, disable_rdtscp_main, 4949 disable_rdtscp_exit_handler, NULL, {0} }, 4950 { "int3", int3_init, int3_guest_main, int3_exit_handler, NULL, {0} }, 4951 { "into", into_init, into_guest_main, into_exit_handler, NULL, {0} }, 4952 { "exit_monitor_from_l2_test", NULL, exit_monitor_from_l2_main, 4953 exit_monitor_from_l2_handler, NULL, {0} }, 4954 /* Basic V2 tests. */ 4955 TEST(v2_null_test), 4956 TEST(v2_multiple_entries_test), 4957 TEST(fixture_test_case1), 4958 TEST(fixture_test_case2), 4959 /* Opcode tests. */ 4960 TEST(invvpid_test_v2), 4961 /* VM-entry tests */ 4962 TEST(vmx_controls_test), 4963 TEST(vmentry_movss_shadow_test), 4964 /* APICv tests */ 4965 TEST(vmx_eoi_bitmap_ioapic_scan_test), 4966 /* APIC pass-through tests */ 4967 TEST(vmx_apic_passthrough_test), 4968 TEST(vmx_apic_passthrough_thread_test), 4969 /* VMCS Shadowing tests */ 4970 TEST(vmx_vmcs_shadow_test), 4971 /* Regression tests */ 4972 TEST(vmx_cr_load_test), 4973 /* EPT access tests. */ 4974 TEST(ept_access_test_not_present), 4975 TEST(ept_access_test_read_only), 4976 TEST(ept_access_test_write_only), 4977 TEST(ept_access_test_read_write), 4978 TEST(ept_access_test_execute_only), 4979 TEST(ept_access_test_read_execute), 4980 TEST(ept_access_test_write_execute), 4981 TEST(ept_access_test_read_write_execute), 4982 TEST(ept_access_test_reserved_bits), 4983 TEST(ept_access_test_ignored_bits), 4984 TEST(ept_access_test_paddr_not_present_ad_disabled), 4985 TEST(ept_access_test_paddr_not_present_ad_enabled), 4986 TEST(ept_access_test_paddr_read_only_ad_disabled), 4987 TEST(ept_access_test_paddr_read_only_ad_enabled), 4988 TEST(ept_access_test_paddr_read_write), 4989 TEST(ept_access_test_paddr_read_write_execute), 4990 TEST(ept_access_test_paddr_read_execute_ad_disabled), 4991 TEST(ept_access_test_paddr_read_execute_ad_enabled), 4992 TEST(ept_access_test_paddr_not_present_page_fault), 4993 TEST(ept_access_test_force_2m_page), 4994 { NULL, NULL, NULL, NULL, NULL, {0} }, 4995 }; 4996