1 /* 2 * All test cases of nested virtualization should be in this file 3 * 4 * Author : Arthur Chunqi Li <yzt356@gmail.com> 5 */ 6 7 #include <asm/debugreg.h> 8 9 #include "vmx.h" 10 #include "msr.h" 11 #include "processor.h" 12 #include "vm.h" 13 #include "pci.h" 14 #include "fwcfg.h" 15 #include "isr.h" 16 #include "desc.h" 17 #include "apic.h" 18 #include "types.h" 19 #include "vmalloc.h" 20 #include "alloc_page.h" 21 #include "smp.h" 22 #include "delay.h" 23 #include "access.h" 24 25 #define VPID_CAP_INVVPID_TYPES_SHIFT 40 26 27 u64 ia32_pat; 28 u64 ia32_efer; 29 void *io_bitmap_a, *io_bitmap_b; 30 u16 ioport; 31 32 unsigned long *pml4; 33 u64 eptp; 34 void *data_page1, *data_page2; 35 36 phys_addr_t pci_physaddr; 37 38 void *pml_log; 39 #define PML_INDEX 512 40 41 static inline unsigned ffs(unsigned x) 42 { 43 int pos = -1; 44 45 __asm__ __volatile__("bsf %1, %%eax; cmovnz %%eax, %0" 46 : "+r"(pos) : "rm"(x) : "eax"); 47 return pos + 1; 48 } 49 50 static inline void vmcall(void) 51 { 52 asm volatile("vmcall"); 53 } 54 55 static void basic_guest_main(void) 56 { 57 report_pass("Basic VMX test"); 58 } 59 60 static int basic_exit_handler(union exit_reason exit_reason) 61 { 62 report_fail("Basic VMX test"); 63 print_vmexit_info(exit_reason); 64 return VMX_TEST_EXIT; 65 } 66 67 static void vmenter_main(void) 68 { 69 u64 rax; 70 u64 rsp, resume_rsp; 71 72 report_pass("test vmlaunch"); 73 74 asm volatile( 75 "mov %%rsp, %0\n\t" 76 "mov %3, %%rax\n\t" 77 "vmcall\n\t" 78 "mov %%rax, %1\n\t" 79 "mov %%rsp, %2\n\t" 80 : "=r"(rsp), "=r"(rax), "=r"(resume_rsp) 81 : "g"(0xABCD)); 82 report((rax == 0xFFFF) && (rsp == resume_rsp), "test vmresume"); 83 } 84 85 static int vmenter_exit_handler(union exit_reason exit_reason) 86 { 87 u64 guest_rip = vmcs_read(GUEST_RIP); 88 89 switch (exit_reason.basic) { 90 case VMX_VMCALL: 91 if (regs.rax != 0xABCD) { 92 report_fail("test vmresume"); 93 return VMX_TEST_VMEXIT; 94 } 95 regs.rax = 0xFFFF; 96 vmcs_write(GUEST_RIP, guest_rip + 3); 97 return VMX_TEST_RESUME; 98 default: 99 report_fail("test vmresume"); 100 print_vmexit_info(exit_reason); 101 } 102 return VMX_TEST_VMEXIT; 103 } 104 105 u32 preempt_scale; 106 volatile unsigned long long tsc_val; 107 volatile u32 preempt_val; 108 u64 saved_rip; 109 110 static int preemption_timer_init(struct vmcs *vmcs) 111 { 112 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 113 printf("\tPreemption timer is not supported\n"); 114 return VMX_TEST_EXIT; 115 } 116 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 117 preempt_val = 10000000; 118 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 119 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 120 121 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 122 printf("\tSave preemption value is not supported\n"); 123 124 return VMX_TEST_START; 125 } 126 127 static void preemption_timer_main(void) 128 { 129 tsc_val = rdtsc(); 130 if (ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) { 131 vmx_set_test_stage(0); 132 vmcall(); 133 if (vmx_get_test_stage() == 1) 134 vmcall(); 135 } 136 vmx_set_test_stage(1); 137 while (vmx_get_test_stage() == 1) { 138 if (((rdtsc() - tsc_val) >> preempt_scale) 139 > 10 * preempt_val) { 140 vmx_set_test_stage(2); 141 vmcall(); 142 } 143 } 144 tsc_val = rdtsc(); 145 asm volatile ("hlt"); 146 vmcall(); 147 vmx_set_test_stage(5); 148 vmcall(); 149 } 150 151 static int preemption_timer_exit_handler(union exit_reason exit_reason) 152 { 153 bool guest_halted; 154 u64 guest_rip; 155 u32 insn_len; 156 u32 ctrl_exit; 157 158 guest_rip = vmcs_read(GUEST_RIP); 159 insn_len = vmcs_read(EXI_INST_LEN); 160 switch (exit_reason.basic) { 161 case VMX_PREEMPT: 162 switch (vmx_get_test_stage()) { 163 case 1: 164 case 2: 165 report(((rdtsc() - tsc_val) >> preempt_scale) >= preempt_val, 166 "busy-wait for preemption timer"); 167 vmx_set_test_stage(3); 168 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 169 return VMX_TEST_RESUME; 170 case 3: 171 guest_halted = 172 (vmcs_read(GUEST_ACTV_STATE) == ACTV_HLT); 173 report(((rdtsc() - tsc_val) >> preempt_scale) >= preempt_val 174 && guest_halted, 175 "preemption timer during hlt"); 176 vmx_set_test_stage(4); 177 vmcs_write(PIN_CONTROLS, 178 vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 179 vmcs_write(EXI_CONTROLS, 180 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_PREEMPT); 181 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 182 return VMX_TEST_RESUME; 183 case 4: 184 report(saved_rip == guest_rip, 185 "preemption timer with 0 value"); 186 break; 187 default: 188 report_fail("Invalid stage."); 189 print_vmexit_info(exit_reason); 190 break; 191 } 192 break; 193 case VMX_VMCALL: 194 vmcs_write(GUEST_RIP, guest_rip + insn_len); 195 switch (vmx_get_test_stage()) { 196 case 0: 197 report(vmcs_read(PREEMPT_TIMER_VALUE) == preempt_val, 198 "Keep preemption value"); 199 vmx_set_test_stage(1); 200 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 201 ctrl_exit = (vmcs_read(EXI_CONTROLS) | 202 EXI_SAVE_PREEMPT) & ctrl_exit_rev.clr; 203 vmcs_write(EXI_CONTROLS, ctrl_exit); 204 return VMX_TEST_RESUME; 205 case 1: 206 report(vmcs_read(PREEMPT_TIMER_VALUE) < preempt_val, 207 "Save preemption value"); 208 return VMX_TEST_RESUME; 209 case 2: 210 report_fail("busy-wait for preemption timer"); 211 vmx_set_test_stage(3); 212 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 213 return VMX_TEST_RESUME; 214 case 3: 215 report_fail("preemption timer during hlt"); 216 vmx_set_test_stage(4); 217 /* fall through */ 218 case 4: 219 vmcs_write(PIN_CONTROLS, 220 vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 221 vmcs_write(PREEMPT_TIMER_VALUE, 0); 222 saved_rip = guest_rip + insn_len; 223 return VMX_TEST_RESUME; 224 case 5: 225 report_fail("preemption timer with 0 value (vmcall stage 5)"); 226 break; 227 default: 228 // Should not reach here 229 report_fail("unexpected stage, %d", 230 vmx_get_test_stage()); 231 print_vmexit_info(exit_reason); 232 return VMX_TEST_VMEXIT; 233 } 234 break; 235 default: 236 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 237 print_vmexit_info(exit_reason); 238 } 239 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 240 return VMX_TEST_VMEXIT; 241 } 242 243 static void msr_bmp_init(void) 244 { 245 void *msr_bitmap; 246 u32 ctrl_cpu0; 247 248 msr_bitmap = alloc_page(); 249 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 250 ctrl_cpu0 |= CPU_MSR_BITMAP; 251 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 252 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 253 } 254 255 static void *get_msr_bitmap(void) 256 { 257 void *msr_bitmap; 258 259 if (vmcs_read(CPU_EXEC_CTRL0) & CPU_MSR_BITMAP) { 260 msr_bitmap = (void *)vmcs_read(MSR_BITMAP); 261 } else { 262 msr_bitmap = alloc_page(); 263 memset(msr_bitmap, 0xff, PAGE_SIZE); 264 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 265 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_MSR_BITMAP); 266 } 267 268 return msr_bitmap; 269 } 270 271 static void disable_intercept_for_x2apic_msrs(void) 272 { 273 unsigned long *msr_bitmap = (unsigned long *)get_msr_bitmap(); 274 u32 msr; 275 276 for (msr = APIC_BASE_MSR; 277 msr < (APIC_BASE_MSR+0xff); 278 msr += BITS_PER_LONG) { 279 unsigned int word = msr / BITS_PER_LONG; 280 281 msr_bitmap[word] = 0; 282 msr_bitmap[word + (0x800 / sizeof(long))] = 0; 283 } 284 } 285 286 static int test_ctrl_pat_init(struct vmcs *vmcs) 287 { 288 u64 ctrl_ent; 289 u64 ctrl_exi; 290 291 msr_bmp_init(); 292 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT) && 293 !(ctrl_exit_rev.clr & EXI_LOAD_PAT) && 294 !(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 295 printf("\tSave/load PAT is not supported\n"); 296 return 1; 297 } 298 299 ctrl_ent = vmcs_read(ENT_CONTROLS); 300 ctrl_exi = vmcs_read(EXI_CONTROLS); 301 ctrl_ent |= ctrl_enter_rev.clr & ENT_LOAD_PAT; 302 ctrl_exi |= ctrl_exit_rev.clr & (EXI_SAVE_PAT | EXI_LOAD_PAT); 303 vmcs_write(ENT_CONTROLS, ctrl_ent); 304 vmcs_write(EXI_CONTROLS, ctrl_exi); 305 ia32_pat = rdmsr(MSR_IA32_CR_PAT); 306 vmcs_write(GUEST_PAT, 0x0); 307 vmcs_write(HOST_PAT, ia32_pat); 308 return VMX_TEST_START; 309 } 310 311 static void test_ctrl_pat_main(void) 312 { 313 u64 guest_ia32_pat; 314 315 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 316 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) 317 printf("\tENT_LOAD_PAT is not supported.\n"); 318 else { 319 if (guest_ia32_pat != 0) { 320 report_fail("Entry load PAT"); 321 return; 322 } 323 } 324 wrmsr(MSR_IA32_CR_PAT, 0x6); 325 vmcall(); 326 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 327 if (ctrl_enter_rev.clr & ENT_LOAD_PAT) 328 report(guest_ia32_pat == ia32_pat, "Entry load PAT"); 329 } 330 331 static int test_ctrl_pat_exit_handler(union exit_reason exit_reason) 332 { 333 u64 guest_rip; 334 u64 guest_pat; 335 336 guest_rip = vmcs_read(GUEST_RIP); 337 switch (exit_reason.basic) { 338 case VMX_VMCALL: 339 guest_pat = vmcs_read(GUEST_PAT); 340 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT)) { 341 printf("\tEXI_SAVE_PAT is not supported\n"); 342 vmcs_write(GUEST_PAT, 0x6); 343 } else { 344 report(guest_pat == 0x6, "Exit save PAT"); 345 } 346 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) 347 printf("\tEXI_LOAD_PAT is not supported\n"); 348 else 349 report(rdmsr(MSR_IA32_CR_PAT) == ia32_pat, 350 "Exit load PAT"); 351 vmcs_write(GUEST_PAT, ia32_pat); 352 vmcs_write(GUEST_RIP, guest_rip + 3); 353 return VMX_TEST_RESUME; 354 default: 355 printf("ERROR : Unknown exit reason, 0x%x.\n", exit_reason.full); 356 break; 357 } 358 return VMX_TEST_VMEXIT; 359 } 360 361 static int test_ctrl_efer_init(struct vmcs *vmcs) 362 { 363 u64 ctrl_ent; 364 u64 ctrl_exi; 365 366 msr_bmp_init(); 367 ctrl_ent = vmcs_read(ENT_CONTROLS) | ENT_LOAD_EFER; 368 ctrl_exi = vmcs_read(EXI_CONTROLS) | EXI_SAVE_EFER | EXI_LOAD_EFER; 369 vmcs_write(ENT_CONTROLS, ctrl_ent & ctrl_enter_rev.clr); 370 vmcs_write(EXI_CONTROLS, ctrl_exi & ctrl_exit_rev.clr); 371 ia32_efer = rdmsr(MSR_EFER); 372 vmcs_write(GUEST_EFER, ia32_efer ^ EFER_NX); 373 vmcs_write(HOST_EFER, ia32_efer ^ EFER_NX); 374 return VMX_TEST_START; 375 } 376 377 static void test_ctrl_efer_main(void) 378 { 379 u64 guest_ia32_efer; 380 381 guest_ia32_efer = rdmsr(MSR_EFER); 382 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) 383 printf("\tENT_LOAD_EFER is not supported.\n"); 384 else { 385 if (guest_ia32_efer != (ia32_efer ^ EFER_NX)) { 386 report_fail("Entry load EFER"); 387 return; 388 } 389 } 390 wrmsr(MSR_EFER, ia32_efer); 391 vmcall(); 392 guest_ia32_efer = rdmsr(MSR_EFER); 393 if (ctrl_enter_rev.clr & ENT_LOAD_EFER) 394 report(guest_ia32_efer == ia32_efer, "Entry load EFER"); 395 } 396 397 static int test_ctrl_efer_exit_handler(union exit_reason exit_reason) 398 { 399 u64 guest_rip; 400 u64 guest_efer; 401 402 guest_rip = vmcs_read(GUEST_RIP); 403 switch (exit_reason.basic) { 404 case VMX_VMCALL: 405 guest_efer = vmcs_read(GUEST_EFER); 406 if (!(ctrl_exit_rev.clr & EXI_SAVE_EFER)) { 407 printf("\tEXI_SAVE_EFER is not supported\n"); 408 vmcs_write(GUEST_EFER, ia32_efer); 409 } else { 410 report(guest_efer == ia32_efer, "Exit save EFER"); 411 } 412 if (!(ctrl_exit_rev.clr & EXI_LOAD_EFER)) { 413 printf("\tEXI_LOAD_EFER is not supported\n"); 414 wrmsr(MSR_EFER, ia32_efer ^ EFER_NX); 415 } else { 416 report(rdmsr(MSR_EFER) == (ia32_efer ^ EFER_NX), 417 "Exit load EFER"); 418 } 419 vmcs_write(GUEST_PAT, ia32_efer); 420 vmcs_write(GUEST_RIP, guest_rip + 3); 421 return VMX_TEST_RESUME; 422 default: 423 printf("ERROR : Unknown exit reason, 0x%x.\n", exit_reason.full); 424 break; 425 } 426 return VMX_TEST_VMEXIT; 427 } 428 429 u32 guest_cr0, guest_cr4; 430 431 static void cr_shadowing_main(void) 432 { 433 u32 cr0, cr4, tmp; 434 435 // Test read through 436 vmx_set_test_stage(0); 437 guest_cr0 = read_cr0(); 438 if (vmx_get_test_stage() == 1) 439 report_fail("Read through CR0"); 440 else 441 vmcall(); 442 vmx_set_test_stage(1); 443 guest_cr4 = read_cr4(); 444 if (vmx_get_test_stage() == 2) 445 report_fail("Read through CR4"); 446 else 447 vmcall(); 448 // Test write through 449 guest_cr0 = guest_cr0 ^ (X86_CR0_TS | X86_CR0_MP); 450 guest_cr4 = guest_cr4 ^ (X86_CR4_TSD | X86_CR4_DE); 451 vmx_set_test_stage(2); 452 write_cr0(guest_cr0); 453 if (vmx_get_test_stage() == 3) 454 report_fail("Write throuth CR0"); 455 else 456 vmcall(); 457 vmx_set_test_stage(3); 458 write_cr4(guest_cr4); 459 if (vmx_get_test_stage() == 4) 460 report_fail("Write through CR4"); 461 else 462 vmcall(); 463 // Test read shadow 464 vmx_set_test_stage(4); 465 vmcall(); 466 cr0 = read_cr0(); 467 if (vmx_get_test_stage() != 5) 468 report(cr0 == guest_cr0, "Read shadowing CR0"); 469 vmx_set_test_stage(5); 470 cr4 = read_cr4(); 471 if (vmx_get_test_stage() != 6) 472 report(cr4 == guest_cr4, "Read shadowing CR4"); 473 // Test write shadow (same value with shadow) 474 vmx_set_test_stage(6); 475 write_cr0(guest_cr0); 476 if (vmx_get_test_stage() == 7) 477 report_fail("Write shadowing CR0 (same value with shadow)"); 478 else 479 vmcall(); 480 vmx_set_test_stage(7); 481 write_cr4(guest_cr4); 482 if (vmx_get_test_stage() == 8) 483 report_fail("Write shadowing CR4 (same value with shadow)"); 484 else 485 vmcall(); 486 // Test write shadow (different value) 487 vmx_set_test_stage(8); 488 tmp = guest_cr0 ^ X86_CR0_TS; 489 asm volatile("mov %0, %%rsi\n\t" 490 "mov %%rsi, %%cr0\n\t" 491 ::"m"(tmp) 492 :"rsi", "memory", "cc"); 493 report(vmx_get_test_stage() == 9, 494 "Write shadowing different X86_CR0_TS"); 495 vmx_set_test_stage(9); 496 tmp = guest_cr0 ^ X86_CR0_MP; 497 asm volatile("mov %0, %%rsi\n\t" 498 "mov %%rsi, %%cr0\n\t" 499 ::"m"(tmp) 500 :"rsi", "memory", "cc"); 501 report(vmx_get_test_stage() == 10, 502 "Write shadowing different X86_CR0_MP"); 503 vmx_set_test_stage(10); 504 tmp = guest_cr4 ^ X86_CR4_TSD; 505 asm volatile("mov %0, %%rsi\n\t" 506 "mov %%rsi, %%cr4\n\t" 507 ::"m"(tmp) 508 :"rsi", "memory", "cc"); 509 report(vmx_get_test_stage() == 11, 510 "Write shadowing different X86_CR4_TSD"); 511 vmx_set_test_stage(11); 512 tmp = guest_cr4 ^ X86_CR4_DE; 513 asm volatile("mov %0, %%rsi\n\t" 514 "mov %%rsi, %%cr4\n\t" 515 ::"m"(tmp) 516 :"rsi", "memory", "cc"); 517 report(vmx_get_test_stage() == 12, 518 "Write shadowing different X86_CR4_DE"); 519 } 520 521 static int cr_shadowing_exit_handler(union exit_reason exit_reason) 522 { 523 u64 guest_rip; 524 u32 insn_len; 525 u32 exit_qual; 526 527 guest_rip = vmcs_read(GUEST_RIP); 528 insn_len = vmcs_read(EXI_INST_LEN); 529 exit_qual = vmcs_read(EXI_QUALIFICATION); 530 switch (exit_reason.basic) { 531 case VMX_VMCALL: 532 switch (vmx_get_test_stage()) { 533 case 0: 534 report(guest_cr0 == vmcs_read(GUEST_CR0), 535 "Read through CR0"); 536 break; 537 case 1: 538 report(guest_cr4 == vmcs_read(GUEST_CR4), 539 "Read through CR4"); 540 break; 541 case 2: 542 report(guest_cr0 == vmcs_read(GUEST_CR0), 543 "Write through CR0"); 544 break; 545 case 3: 546 report(guest_cr4 == vmcs_read(GUEST_CR4), 547 "Write through CR4"); 548 break; 549 case 4: 550 guest_cr0 = vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP); 551 guest_cr4 = vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE); 552 vmcs_write(CR0_MASK, X86_CR0_TS | X86_CR0_MP); 553 vmcs_write(CR0_READ_SHADOW, guest_cr0 & (X86_CR0_TS | X86_CR0_MP)); 554 vmcs_write(CR4_MASK, X86_CR4_TSD | X86_CR4_DE); 555 vmcs_write(CR4_READ_SHADOW, guest_cr4 & (X86_CR4_TSD | X86_CR4_DE)); 556 break; 557 case 6: 558 report(guest_cr0 == (vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP)), 559 "Write shadowing CR0 (same value)"); 560 break; 561 case 7: 562 report(guest_cr4 == (vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE)), 563 "Write shadowing CR4 (same value)"); 564 break; 565 default: 566 // Should not reach here 567 report_fail("unexpected stage, %d", 568 vmx_get_test_stage()); 569 print_vmexit_info(exit_reason); 570 return VMX_TEST_VMEXIT; 571 } 572 vmcs_write(GUEST_RIP, guest_rip + insn_len); 573 return VMX_TEST_RESUME; 574 case VMX_CR: 575 switch (vmx_get_test_stage()) { 576 case 4: 577 report_fail("Read shadowing CR0"); 578 vmx_inc_test_stage(); 579 break; 580 case 5: 581 report_fail("Read shadowing CR4"); 582 vmx_inc_test_stage(); 583 break; 584 case 6: 585 report_fail("Write shadowing CR0 (same value)"); 586 vmx_inc_test_stage(); 587 break; 588 case 7: 589 report_fail("Write shadowing CR4 (same value)"); 590 vmx_inc_test_stage(); 591 break; 592 case 8: 593 case 9: 594 // 0x600 encodes "mov %esi, %cr0" 595 if (exit_qual == 0x600) 596 vmx_inc_test_stage(); 597 break; 598 case 10: 599 case 11: 600 // 0x604 encodes "mov %esi, %cr4" 601 if (exit_qual == 0x604) 602 vmx_inc_test_stage(); 603 break; 604 default: 605 // Should not reach here 606 report_fail("unexpected stage, %d", 607 vmx_get_test_stage()); 608 print_vmexit_info(exit_reason); 609 return VMX_TEST_VMEXIT; 610 } 611 vmcs_write(GUEST_RIP, guest_rip + insn_len); 612 return VMX_TEST_RESUME; 613 default: 614 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 615 print_vmexit_info(exit_reason); 616 } 617 return VMX_TEST_VMEXIT; 618 } 619 620 static int iobmp_init(struct vmcs *vmcs) 621 { 622 u32 ctrl_cpu0; 623 624 io_bitmap_a = alloc_page(); 625 io_bitmap_b = alloc_page(); 626 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 627 ctrl_cpu0 |= CPU_IO_BITMAP; 628 ctrl_cpu0 &= (~CPU_IO); 629 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 630 vmcs_write(IO_BITMAP_A, (u64)io_bitmap_a); 631 vmcs_write(IO_BITMAP_B, (u64)io_bitmap_b); 632 return VMX_TEST_START; 633 } 634 635 static void iobmp_main(void) 636 { 637 // stage 0, test IO pass 638 vmx_set_test_stage(0); 639 inb(0x5000); 640 outb(0x0, 0x5000); 641 report(vmx_get_test_stage() == 0, "I/O bitmap - I/O pass"); 642 // test IO width, in/out 643 ((u8 *)io_bitmap_a)[0] = 0xFF; 644 vmx_set_test_stage(2); 645 inb(0x0); 646 report(vmx_get_test_stage() == 3, "I/O bitmap - trap in"); 647 vmx_set_test_stage(3); 648 outw(0x0, 0x0); 649 report(vmx_get_test_stage() == 4, "I/O bitmap - trap out"); 650 vmx_set_test_stage(4); 651 inl(0x0); 652 report(vmx_get_test_stage() == 5, "I/O bitmap - I/O width, long"); 653 // test low/high IO port 654 vmx_set_test_stage(5); 655 ((u8 *)io_bitmap_a)[0x5000 / 8] = (1 << (0x5000 % 8)); 656 inb(0x5000); 657 report(vmx_get_test_stage() == 6, "I/O bitmap - I/O port, low part"); 658 vmx_set_test_stage(6); 659 ((u8 *)io_bitmap_b)[0x1000 / 8] = (1 << (0x1000 % 8)); 660 inb(0x9000); 661 report(vmx_get_test_stage() == 7, "I/O bitmap - I/O port, high part"); 662 // test partial pass 663 vmx_set_test_stage(7); 664 inl(0x4FFF); 665 report(vmx_get_test_stage() == 8, "I/O bitmap - partial pass"); 666 // test overrun 667 vmx_set_test_stage(8); 668 memset(io_bitmap_a, 0x0, PAGE_SIZE); 669 memset(io_bitmap_b, 0x0, PAGE_SIZE); 670 inl(0xFFFF); 671 report(vmx_get_test_stage() == 9, "I/O bitmap - overrun"); 672 vmx_set_test_stage(9); 673 vmcall(); 674 outb(0x0, 0x0); 675 report(vmx_get_test_stage() == 9, 676 "I/O bitmap - ignore unconditional exiting"); 677 vmx_set_test_stage(10); 678 vmcall(); 679 outb(0x0, 0x0); 680 report(vmx_get_test_stage() == 11, 681 "I/O bitmap - unconditional exiting"); 682 } 683 684 static int iobmp_exit_handler(union exit_reason exit_reason) 685 { 686 u64 guest_rip; 687 ulong exit_qual; 688 u32 insn_len, ctrl_cpu0; 689 690 guest_rip = vmcs_read(GUEST_RIP); 691 exit_qual = vmcs_read(EXI_QUALIFICATION); 692 insn_len = vmcs_read(EXI_INST_LEN); 693 switch (exit_reason.basic) { 694 case VMX_IO: 695 switch (vmx_get_test_stage()) { 696 case 0: 697 case 1: 698 vmx_inc_test_stage(); 699 break; 700 case 2: 701 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_BYTE, 702 "I/O bitmap - I/O width, byte"); 703 report(exit_qual & VMX_IO_IN, 704 "I/O bitmap - I/O direction, in"); 705 vmx_inc_test_stage(); 706 break; 707 case 3: 708 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_WORD, 709 "I/O bitmap - I/O width, word"); 710 report(!(exit_qual & VMX_IO_IN), 711 "I/O bitmap - I/O direction, out"); 712 vmx_inc_test_stage(); 713 break; 714 case 4: 715 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_LONG, 716 "I/O bitmap - I/O width, long"); 717 vmx_inc_test_stage(); 718 break; 719 case 5: 720 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x5000) 721 vmx_inc_test_stage(); 722 break; 723 case 6: 724 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x9000) 725 vmx_inc_test_stage(); 726 break; 727 case 7: 728 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x4FFF) 729 vmx_inc_test_stage(); 730 break; 731 case 8: 732 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0xFFFF) 733 vmx_inc_test_stage(); 734 break; 735 case 9: 736 case 10: 737 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 738 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0 & ~CPU_IO); 739 vmx_inc_test_stage(); 740 break; 741 default: 742 // Should not reach here 743 report_fail("unexpected stage, %d", 744 vmx_get_test_stage()); 745 print_vmexit_info(exit_reason); 746 return VMX_TEST_VMEXIT; 747 } 748 vmcs_write(GUEST_RIP, guest_rip + insn_len); 749 return VMX_TEST_RESUME; 750 case VMX_VMCALL: 751 switch (vmx_get_test_stage()) { 752 case 9: 753 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 754 ctrl_cpu0 |= CPU_IO | CPU_IO_BITMAP; 755 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 756 break; 757 case 10: 758 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 759 ctrl_cpu0 = (ctrl_cpu0 & ~CPU_IO_BITMAP) | CPU_IO; 760 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 761 break; 762 default: 763 // Should not reach here 764 report_fail("unexpected stage, %d", 765 vmx_get_test_stage()); 766 print_vmexit_info(exit_reason); 767 return VMX_TEST_VMEXIT; 768 } 769 vmcs_write(GUEST_RIP, guest_rip + insn_len); 770 return VMX_TEST_RESUME; 771 default: 772 printf("guest_rip = %#lx\n", guest_rip); 773 printf("\tERROR : Unknown exit reason, 0x%x\n", exit_reason.full); 774 break; 775 } 776 return VMX_TEST_VMEXIT; 777 } 778 779 #define INSN_CPU0 0 780 #define INSN_CPU1 1 781 #define INSN_ALWAYS_TRAP 2 782 783 #define FIELD_EXIT_QUAL (1 << 0) 784 #define FIELD_INSN_INFO (1 << 1) 785 786 asm( 787 "insn_hlt: hlt;ret\n\t" 788 "insn_invlpg: invlpg 0x12345678;ret\n\t" 789 "insn_mwait: xor %eax, %eax; xor %ecx, %ecx; mwait;ret\n\t" 790 "insn_rdpmc: xor %ecx, %ecx; rdpmc;ret\n\t" 791 "insn_rdtsc: rdtsc;ret\n\t" 792 "insn_cr3_load: mov cr3,%rax; mov %rax,%cr3;ret\n\t" 793 "insn_cr3_store: mov %cr3,%rax;ret\n\t" 794 "insn_cr8_load: xor %eax, %eax; mov %rax,%cr8;ret\n\t" 795 "insn_cr8_store: mov %cr8,%rax;ret\n\t" 796 "insn_monitor: xor %eax, %eax; xor %ecx, %ecx; xor %edx, %edx; monitor;ret\n\t" 797 "insn_pause: pause;ret\n\t" 798 "insn_wbinvd: wbinvd;ret\n\t" 799 "insn_cpuid: mov $10, %eax; cpuid;ret\n\t" 800 "insn_invd: invd;ret\n\t" 801 "insn_sgdt: sgdt gdt_descr;ret\n\t" 802 "insn_lgdt: lgdt gdt_descr;ret\n\t" 803 "insn_sidt: sidt idt_descr;ret\n\t" 804 "insn_lidt: lidt idt_descr;ret\n\t" 805 "insn_sldt: sldt %ax;ret\n\t" 806 "insn_lldt: xor %eax, %eax; lldt %ax;ret\n\t" 807 "insn_str: str %ax;ret\n\t" 808 "insn_rdrand: rdrand %rax;ret\n\t" 809 "insn_rdseed: rdseed %rax;ret\n\t" 810 ); 811 extern void insn_hlt(void); 812 extern void insn_invlpg(void); 813 extern void insn_mwait(void); 814 extern void insn_rdpmc(void); 815 extern void insn_rdtsc(void); 816 extern void insn_cr3_load(void); 817 extern void insn_cr3_store(void); 818 extern void insn_cr8_load(void); 819 extern void insn_cr8_store(void); 820 extern void insn_monitor(void); 821 extern void insn_pause(void); 822 extern void insn_wbinvd(void); 823 extern void insn_sgdt(void); 824 extern void insn_lgdt(void); 825 extern void insn_sidt(void); 826 extern void insn_lidt(void); 827 extern void insn_sldt(void); 828 extern void insn_lldt(void); 829 extern void insn_str(void); 830 extern void insn_cpuid(void); 831 extern void insn_invd(void); 832 extern void insn_rdrand(void); 833 extern void insn_rdseed(void); 834 835 u32 cur_insn; 836 u64 cr3; 837 838 #define X86_FEATURE_MONITOR (1 << 3) 839 840 typedef bool (*supported_fn)(void); 841 842 static bool monitor_supported(void) 843 { 844 return this_cpu_has(X86_FEATURE_MWAIT); 845 } 846 847 struct insn_table { 848 const char *name; 849 u32 flag; 850 void (*insn_func)(void); 851 u32 type; 852 u32 reason; 853 ulong exit_qual; 854 u32 insn_info; 855 // Use FIELD_EXIT_QUAL and FIELD_INSN_INFO to define 856 // which field need to be tested, reason is always tested 857 u32 test_field; 858 const supported_fn supported_fn; 859 u8 disabled; 860 }; 861 862 /* 863 * Add more test cases of instruction intercept here. Elements in this 864 * table is: 865 * name/control flag/insn function/type/exit reason/exit qulification/ 866 * instruction info/field to test 867 * The last field defines which fields (exit_qual and insn_info) need to be 868 * tested in exit handler. If set to 0, only "reason" is checked. 869 */ 870 static struct insn_table insn_table[] = { 871 // Flags for Primary Processor-Based VM-Execution Controls 872 {"HLT", CPU_HLT, insn_hlt, INSN_CPU0, 12, 0, 0, 0}, 873 {"INVLPG", CPU_INVLPG, insn_invlpg, INSN_CPU0, 14, 874 0x12345678, 0, FIELD_EXIT_QUAL}, 875 {"MWAIT", CPU_MWAIT, insn_mwait, INSN_CPU0, 36, 0, 0, 0, &monitor_supported}, 876 {"RDPMC", CPU_RDPMC, insn_rdpmc, INSN_CPU0, 15, 0, 0, 0}, 877 {"RDTSC", CPU_RDTSC, insn_rdtsc, INSN_CPU0, 16, 0, 0, 0}, 878 {"CR3 load", CPU_CR3_LOAD, insn_cr3_load, INSN_CPU0, 28, 0x3, 0, 879 FIELD_EXIT_QUAL}, 880 {"CR3 store", CPU_CR3_STORE, insn_cr3_store, INSN_CPU0, 28, 0x13, 0, 881 FIELD_EXIT_QUAL}, 882 {"CR8 load", CPU_CR8_LOAD, insn_cr8_load, INSN_CPU0, 28, 0x8, 0, 883 FIELD_EXIT_QUAL}, 884 {"CR8 store", CPU_CR8_STORE, insn_cr8_store, INSN_CPU0, 28, 0x18, 0, 885 FIELD_EXIT_QUAL}, 886 {"MONITOR", CPU_MONITOR, insn_monitor, INSN_CPU0, 39, 0, 0, 0, &monitor_supported}, 887 {"PAUSE", CPU_PAUSE, insn_pause, INSN_CPU0, 40, 0, 0, 0}, 888 // Flags for Secondary Processor-Based VM-Execution Controls 889 {"WBINVD", CPU_WBINVD, insn_wbinvd, INSN_CPU1, 54, 0, 0, 0}, 890 {"DESC_TABLE (SGDT)", CPU_DESC_TABLE, insn_sgdt, INSN_CPU1, 46, 0, 0, 0}, 891 {"DESC_TABLE (LGDT)", CPU_DESC_TABLE, insn_lgdt, INSN_CPU1, 46, 0, 0, 0}, 892 {"DESC_TABLE (SIDT)", CPU_DESC_TABLE, insn_sidt, INSN_CPU1, 46, 0, 0, 0}, 893 {"DESC_TABLE (LIDT)", CPU_DESC_TABLE, insn_lidt, INSN_CPU1, 46, 0, 0, 0}, 894 {"DESC_TABLE (SLDT)", CPU_DESC_TABLE, insn_sldt, INSN_CPU1, 47, 0, 0, 0}, 895 {"DESC_TABLE (LLDT)", CPU_DESC_TABLE, insn_lldt, INSN_CPU1, 47, 0, 0, 0}, 896 {"DESC_TABLE (STR)", CPU_DESC_TABLE, insn_str, INSN_CPU1, 47, 0, 0, 0}, 897 /* LTR causes a #GP if done with a busy selector, so it is not tested. */ 898 {"RDRAND", CPU_RDRAND, insn_rdrand, INSN_CPU1, VMX_RDRAND, 0, 0, 0}, 899 {"RDSEED", CPU_RDSEED, insn_rdseed, INSN_CPU1, VMX_RDSEED, 0, 0, 0}, 900 // Instructions always trap 901 {"CPUID", 0, insn_cpuid, INSN_ALWAYS_TRAP, 10, 0, 0, 0}, 902 {"INVD", 0, insn_invd, INSN_ALWAYS_TRAP, 13, 0, 0, 0}, 903 // Instructions never trap 904 {NULL}, 905 }; 906 907 static int insn_intercept_init(struct vmcs *vmcs) 908 { 909 u32 ctrl_cpu, cur_insn; 910 911 ctrl_cpu = ctrl_cpu_rev[0].set | CPU_SECONDARY; 912 ctrl_cpu &= ctrl_cpu_rev[0].clr; 913 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu); 914 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu_rev[1].set); 915 cr3 = read_cr3(); 916 917 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 918 if (insn_table[cur_insn].supported_fn == NULL) 919 continue; 920 insn_table[cur_insn].disabled = !insn_table[cur_insn].supported_fn(); 921 } 922 return VMX_TEST_START; 923 } 924 925 static void insn_intercept_main(void) 926 { 927 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 928 vmx_set_test_stage(cur_insn * 2); 929 if ((insn_table[cur_insn].type == INSN_CPU0 && 930 !(ctrl_cpu_rev[0].clr & insn_table[cur_insn].flag)) || 931 (insn_table[cur_insn].type == INSN_CPU1 && 932 !(ctrl_cpu_rev[1].clr & insn_table[cur_insn].flag))) { 933 printf("\tCPU_CTRL%d.CPU_%s is not supported.\n", 934 insn_table[cur_insn].type - INSN_CPU0, 935 insn_table[cur_insn].name); 936 continue; 937 } 938 939 if (insn_table[cur_insn].disabled) { 940 printf("\tFeature required for %s is not supported.\n", 941 insn_table[cur_insn].name); 942 continue; 943 } 944 945 if ((insn_table[cur_insn].type == INSN_CPU0 && 946 !(ctrl_cpu_rev[0].set & insn_table[cur_insn].flag)) || 947 (insn_table[cur_insn].type == INSN_CPU1 && 948 !(ctrl_cpu_rev[1].set & insn_table[cur_insn].flag))) { 949 /* skip hlt, it stalls the guest and is tested below */ 950 if (insn_table[cur_insn].insn_func != insn_hlt) 951 insn_table[cur_insn].insn_func(); 952 report(vmx_get_test_stage() == cur_insn * 2, 953 "execute %s", 954 insn_table[cur_insn].name); 955 } else if (insn_table[cur_insn].type != INSN_ALWAYS_TRAP) 956 printf("\tCPU_CTRL%d.CPU_%s always traps.\n", 957 insn_table[cur_insn].type - INSN_CPU0, 958 insn_table[cur_insn].name); 959 960 vmcall(); 961 962 insn_table[cur_insn].insn_func(); 963 report(vmx_get_test_stage() == cur_insn * 2 + 1, 964 "intercept %s", 965 insn_table[cur_insn].name); 966 967 vmx_set_test_stage(cur_insn * 2 + 1); 968 vmcall(); 969 } 970 } 971 972 static int insn_intercept_exit_handler(union exit_reason exit_reason) 973 { 974 u64 guest_rip; 975 ulong exit_qual; 976 u32 insn_len; 977 u32 insn_info; 978 bool pass; 979 980 guest_rip = vmcs_read(GUEST_RIP); 981 exit_qual = vmcs_read(EXI_QUALIFICATION); 982 insn_len = vmcs_read(EXI_INST_LEN); 983 insn_info = vmcs_read(EXI_INST_INFO); 984 985 if (exit_reason.basic == VMX_VMCALL) { 986 u32 val = 0; 987 988 if (insn_table[cur_insn].type == INSN_CPU0) 989 val = vmcs_read(CPU_EXEC_CTRL0); 990 else if (insn_table[cur_insn].type == INSN_CPU1) 991 val = vmcs_read(CPU_EXEC_CTRL1); 992 993 if (vmx_get_test_stage() & 1) 994 val &= ~insn_table[cur_insn].flag; 995 else 996 val |= insn_table[cur_insn].flag; 997 998 if (insn_table[cur_insn].type == INSN_CPU0) 999 vmcs_write(CPU_EXEC_CTRL0, val | ctrl_cpu_rev[0].set); 1000 else if (insn_table[cur_insn].type == INSN_CPU1) 1001 vmcs_write(CPU_EXEC_CTRL1, val | ctrl_cpu_rev[1].set); 1002 } else { 1003 pass = (cur_insn * 2 == vmx_get_test_stage()) && 1004 insn_table[cur_insn].reason == exit_reason.full; 1005 if (insn_table[cur_insn].test_field & FIELD_EXIT_QUAL && 1006 insn_table[cur_insn].exit_qual != exit_qual) 1007 pass = false; 1008 if (insn_table[cur_insn].test_field & FIELD_INSN_INFO && 1009 insn_table[cur_insn].insn_info != insn_info) 1010 pass = false; 1011 if (pass) 1012 vmx_inc_test_stage(); 1013 } 1014 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1015 return VMX_TEST_RESUME; 1016 } 1017 1018 /** 1019 * __setup_ept - Setup the VMCS fields to enable Extended Page Tables (EPT) 1020 * @hpa: Host physical address of the top-level, a.k.a. root, EPT table 1021 * @enable_ad: Whether or not to enable Access/Dirty bits for EPT entries 1022 * 1023 * Returns 0 on success, 1 on failure. 1024 * 1025 * Note that @hpa doesn't need to point at actual memory if VM-Launch is 1026 * expected to fail, e.g. setup_dummy_ept() arbitrarily passes '0' to satisfy 1027 * the various EPTP consistency checks, but doesn't ensure backing for HPA '0'. 1028 */ 1029 static int __setup_ept(u64 hpa, bool enable_ad) 1030 { 1031 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1032 !(ctrl_cpu_rev[1].clr & CPU_EPT)) { 1033 printf("\tEPT is not supported\n"); 1034 return 1; 1035 } 1036 if (!(ept_vpid.val & EPT_CAP_WB)) { 1037 printf("\tWB memtype for EPT walks not supported\n"); 1038 return 1; 1039 } 1040 if (!(ept_vpid.val & EPT_CAP_PWL4)) { 1041 printf("\tPWL4 is not supported\n"); 1042 return 1; 1043 } 1044 1045 eptp = EPT_MEM_TYPE_WB; 1046 eptp |= (3 << EPTP_PG_WALK_LEN_SHIFT); 1047 eptp |= hpa; 1048 if (enable_ad) 1049 eptp |= EPTP_AD_FLAG; 1050 1051 vmcs_write(EPTP, eptp); 1052 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0)| CPU_SECONDARY); 1053 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1)| CPU_EPT); 1054 1055 return 0; 1056 } 1057 1058 /** 1059 * setup_ept - Enable Extended Page Tables (EPT) and setup an identity map 1060 * @enable_ad: Whether or not to enable Access/Dirty bits for EPT entries 1061 * 1062 * Returns 0 on success, 1 on failure. 1063 * 1064 * This is the "real" function for setting up EPT tables, i.e. use this for 1065 * tests that need to run code in the guest with EPT enabled. 1066 */ 1067 static int setup_ept(bool enable_ad) 1068 { 1069 unsigned long end_of_memory; 1070 1071 pml4 = alloc_page(); 1072 1073 if (__setup_ept(virt_to_phys(pml4), enable_ad)) 1074 return 1; 1075 1076 end_of_memory = fwcfg_get_u64(FW_CFG_RAM_SIZE); 1077 if (end_of_memory < (1ul << 32)) 1078 end_of_memory = (1ul << 32); 1079 /* Cannot use large EPT pages if we need to track EPT 1080 * accessed/dirty bits at 4K granularity. 1081 */ 1082 setup_ept_range(pml4, 0, end_of_memory, 0, 1083 !enable_ad && ept_2m_supported(), 1084 EPT_WA | EPT_RA | EPT_EA); 1085 return 0; 1086 } 1087 1088 /** 1089 * setup_dummy_ept - Enable Extended Page Tables (EPT) with a dummy root HPA 1090 * 1091 * Setup EPT using a semi-arbitrary dummy root HPA. This function is intended 1092 * for use by tests that need EPT enabled to verify dependent VMCS controls 1093 * but never expect to fully enter the guest, i.e. don't need setup the actual 1094 * EPT tables. 1095 */ 1096 static void setup_dummy_ept(void) 1097 { 1098 if (__setup_ept(0, false)) 1099 report_abort("EPT setup unexpectedly failed"); 1100 } 1101 1102 static int enable_unrestricted_guest(bool need_valid_ept) 1103 { 1104 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1105 !(ctrl_cpu_rev[1].clr & CPU_URG) || 1106 !(ctrl_cpu_rev[1].clr & CPU_EPT)) 1107 return 1; 1108 1109 if (need_valid_ept) 1110 setup_ept(false); 1111 else 1112 setup_dummy_ept(); 1113 1114 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 1115 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | CPU_URG); 1116 1117 return 0; 1118 } 1119 1120 static void ept_enable_ad_bits(void) 1121 { 1122 eptp |= EPTP_AD_FLAG; 1123 vmcs_write(EPTP, eptp); 1124 } 1125 1126 static void ept_disable_ad_bits(void) 1127 { 1128 eptp &= ~EPTP_AD_FLAG; 1129 vmcs_write(EPTP, eptp); 1130 } 1131 1132 static int ept_ad_enabled(void) 1133 { 1134 return eptp & EPTP_AD_FLAG; 1135 } 1136 1137 static void ept_enable_ad_bits_or_skip_test(void) 1138 { 1139 if (!ept_ad_bits_supported()) 1140 test_skip("EPT AD bits not supported."); 1141 ept_enable_ad_bits(); 1142 } 1143 1144 static int apic_version; 1145 1146 static int ept_init_common(bool have_ad) 1147 { 1148 int ret; 1149 struct pci_dev pcidev; 1150 1151 /* INVEPT is required by the EPT violation handler. */ 1152 if (!is_invept_type_supported(INVEPT_SINGLE)) 1153 return VMX_TEST_EXIT; 1154 1155 if (setup_ept(have_ad)) 1156 return VMX_TEST_EXIT; 1157 1158 data_page1 = alloc_page(); 1159 data_page2 = alloc_page(); 1160 *((u32 *)data_page1) = MAGIC_VAL_1; 1161 *((u32 *)data_page2) = MAGIC_VAL_2; 1162 install_ept(pml4, (unsigned long)data_page1, (unsigned long)data_page2, 1163 EPT_RA | EPT_WA | EPT_EA); 1164 1165 apic_version = apic_read(APIC_LVR); 1166 1167 ret = pci_find_dev(PCI_VENDOR_ID_REDHAT, PCI_DEVICE_ID_REDHAT_TEST); 1168 if (ret != PCIDEVADDR_INVALID) { 1169 pci_dev_init(&pcidev, ret); 1170 pci_physaddr = pcidev.resource[PCI_TESTDEV_BAR_MEM]; 1171 } 1172 1173 return VMX_TEST_START; 1174 } 1175 1176 static int ept_init(struct vmcs *vmcs) 1177 { 1178 return ept_init_common(false); 1179 } 1180 1181 static void ept_common(void) 1182 { 1183 vmx_set_test_stage(0); 1184 if (*((u32 *)data_page2) != MAGIC_VAL_1 || 1185 *((u32 *)data_page1) != MAGIC_VAL_1) 1186 report_fail("EPT basic framework - read"); 1187 else { 1188 *((u32 *)data_page2) = MAGIC_VAL_3; 1189 vmcall(); 1190 if (vmx_get_test_stage() == 1) { 1191 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1192 *((u32 *)data_page2) == MAGIC_VAL_2) 1193 report_pass("EPT basic framework"); 1194 else 1195 report_pass("EPT basic framework - remap"); 1196 } 1197 } 1198 // Test EPT Misconfigurations 1199 vmx_set_test_stage(1); 1200 vmcall(); 1201 *((u32 *)data_page1) = MAGIC_VAL_1; 1202 if (vmx_get_test_stage() != 2) { 1203 report_fail("EPT misconfigurations"); 1204 goto t1; 1205 } 1206 vmx_set_test_stage(2); 1207 vmcall(); 1208 *((u32 *)data_page1) = MAGIC_VAL_1; 1209 report(vmx_get_test_stage() == 3, "EPT misconfigurations"); 1210 t1: 1211 // Test EPT violation 1212 vmx_set_test_stage(3); 1213 vmcall(); 1214 *((u32 *)data_page1) = MAGIC_VAL_1; 1215 report(vmx_get_test_stage() == 4, "EPT violation - page permission"); 1216 // Violation caused by EPT paging structure 1217 vmx_set_test_stage(4); 1218 vmcall(); 1219 *((u32 *)data_page1) = MAGIC_VAL_2; 1220 report(vmx_get_test_stage() == 5, "EPT violation - paging structure"); 1221 1222 // MMIO Read/Write 1223 vmx_set_test_stage(5); 1224 vmcall(); 1225 1226 *(u32 volatile *)pci_physaddr; 1227 report(vmx_get_test_stage() == 6, "MMIO EPT violation - read"); 1228 1229 *(u32 volatile *)pci_physaddr = MAGIC_VAL_1; 1230 report(vmx_get_test_stage() == 7, "MMIO EPT violation - write"); 1231 } 1232 1233 static void ept_main(void) 1234 { 1235 ept_common(); 1236 1237 // Test EPT access to L1 MMIO 1238 vmx_set_test_stage(7); 1239 report(*((u32 *)0xfee00030UL) == apic_version, "EPT - MMIO access"); 1240 1241 // Test invalid operand for INVEPT 1242 vmcall(); 1243 report(vmx_get_test_stage() == 8, "EPT - unsupported INVEPT"); 1244 } 1245 1246 static bool invept_test(int type, u64 eptp) 1247 { 1248 bool ret, supported; 1249 1250 supported = ept_vpid.val & (EPT_CAP_INVEPT_SINGLE >> INVEPT_SINGLE << type); 1251 ret = __invept(type, eptp); 1252 1253 if (ret == !supported) 1254 return false; 1255 1256 if (!supported) 1257 printf("WARNING: unsupported invept passed!\n"); 1258 else 1259 printf("WARNING: invept failed!\n"); 1260 1261 return true; 1262 } 1263 1264 static int pml_exit_handler(union exit_reason exit_reason) 1265 { 1266 u16 index, count; 1267 u64 *pmlbuf = pml_log; 1268 u64 guest_rip = vmcs_read(GUEST_RIP);; 1269 u64 guest_cr3 = vmcs_read(GUEST_CR3); 1270 u32 insn_len = vmcs_read(EXI_INST_LEN); 1271 1272 switch (exit_reason.basic) { 1273 case VMX_VMCALL: 1274 switch (vmx_get_test_stage()) { 1275 case 0: 1276 index = vmcs_read(GUEST_PML_INDEX); 1277 for (count = index + 1; count < PML_INDEX; count++) { 1278 if (pmlbuf[count] == (u64)data_page2) { 1279 vmx_inc_test_stage(); 1280 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1281 break; 1282 } 1283 } 1284 break; 1285 case 1: 1286 index = vmcs_read(GUEST_PML_INDEX); 1287 /* Keep clearing the dirty bit till a overflow */ 1288 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1289 break; 1290 default: 1291 report_fail("unexpected stage, %d.", 1292 vmx_get_test_stage()); 1293 print_vmexit_info(exit_reason); 1294 return VMX_TEST_VMEXIT; 1295 } 1296 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1297 return VMX_TEST_RESUME; 1298 case VMX_PML_FULL: 1299 vmx_inc_test_stage(); 1300 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1301 return VMX_TEST_RESUME; 1302 default: 1303 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 1304 print_vmexit_info(exit_reason); 1305 } 1306 return VMX_TEST_VMEXIT; 1307 } 1308 1309 static int ept_exit_handler_common(union exit_reason exit_reason, bool have_ad) 1310 { 1311 u64 guest_rip; 1312 u64 guest_cr3; 1313 u32 insn_len; 1314 u32 exit_qual; 1315 static unsigned long data_page1_pte, data_page1_pte_pte, memaddr_pte, 1316 guest_pte_addr; 1317 1318 guest_rip = vmcs_read(GUEST_RIP); 1319 guest_cr3 = vmcs_read(GUEST_CR3); 1320 insn_len = vmcs_read(EXI_INST_LEN); 1321 exit_qual = vmcs_read(EXI_QUALIFICATION); 1322 pteval_t *ptep; 1323 switch (exit_reason.basic) { 1324 case VMX_VMCALL: 1325 switch (vmx_get_test_stage()) { 1326 case 0: 1327 check_ept_ad(pml4, guest_cr3, 1328 (unsigned long)data_page1, 1329 have_ad ? EPT_ACCESS_FLAG : 0, 1330 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1331 check_ept_ad(pml4, guest_cr3, 1332 (unsigned long)data_page2, 1333 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0, 1334 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1335 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1336 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1337 if (have_ad) 1338 invept(INVEPT_SINGLE, eptp); 1339 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1340 *((u32 *)data_page2) == MAGIC_VAL_2) { 1341 vmx_inc_test_stage(); 1342 install_ept(pml4, (unsigned long)data_page2, 1343 (unsigned long)data_page2, 1344 EPT_RA | EPT_WA | EPT_EA); 1345 } else 1346 report_fail("EPT basic framework - write"); 1347 break; 1348 case 1: 1349 install_ept(pml4, (unsigned long)data_page1, 1350 (unsigned long)data_page1, EPT_WA); 1351 invept(INVEPT_SINGLE, eptp); 1352 break; 1353 case 2: 1354 install_ept(pml4, (unsigned long)data_page1, 1355 (unsigned long)data_page1, 1356 EPT_RA | EPT_WA | EPT_EA | 1357 (2 << EPT_MEM_TYPE_SHIFT)); 1358 invept(INVEPT_SINGLE, eptp); 1359 break; 1360 case 3: 1361 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1362 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)data_page1, 1363 1, &data_page1_pte)); 1364 set_ept_pte(pml4, (unsigned long)data_page1, 1365 1, data_page1_pte & ~EPT_PRESENT); 1366 invept(INVEPT_SINGLE, eptp); 1367 break; 1368 case 4: 1369 ptep = get_pte_level((pgd_t *)guest_cr3, data_page1, /*level=*/2); 1370 guest_pte_addr = virt_to_phys(ptep) & PAGE_MASK; 1371 1372 TEST_ASSERT(get_ept_pte(pml4, guest_pte_addr, 2, &data_page1_pte_pte)); 1373 set_ept_pte(pml4, guest_pte_addr, 2, 1374 data_page1_pte_pte & ~EPT_PRESENT); 1375 invept(INVEPT_SINGLE, eptp); 1376 break; 1377 case 5: 1378 install_ept(pml4, (unsigned long)pci_physaddr, 1379 (unsigned long)pci_physaddr, 0); 1380 invept(INVEPT_SINGLE, eptp); 1381 break; 1382 case 7: 1383 if (!invept_test(0, eptp)) 1384 vmx_inc_test_stage(); 1385 break; 1386 // Should not reach here 1387 default: 1388 report_fail("ERROR - unexpected stage, %d.", 1389 vmx_get_test_stage()); 1390 print_vmexit_info(exit_reason); 1391 return VMX_TEST_VMEXIT; 1392 } 1393 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1394 return VMX_TEST_RESUME; 1395 case VMX_EPT_MISCONFIG: 1396 switch (vmx_get_test_stage()) { 1397 case 1: 1398 case 2: 1399 vmx_inc_test_stage(); 1400 install_ept(pml4, (unsigned long)data_page1, 1401 (unsigned long)data_page1, 1402 EPT_RA | EPT_WA | EPT_EA); 1403 invept(INVEPT_SINGLE, eptp); 1404 break; 1405 // Should not reach here 1406 default: 1407 report_fail("ERROR - unexpected stage, %d.", 1408 vmx_get_test_stage()); 1409 print_vmexit_info(exit_reason); 1410 return VMX_TEST_VMEXIT; 1411 } 1412 return VMX_TEST_RESUME; 1413 case VMX_EPT_VIOLATION: 1414 /* 1415 * Exit-qualifications are masked not to account for advanced 1416 * VM-exit information. Once KVM supports this feature, this 1417 * masking should be removed. 1418 */ 1419 exit_qual &= ~EPT_VLT_GUEST_MASK; 1420 1421 switch(vmx_get_test_stage()) { 1422 case 3: 1423 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1424 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1425 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1426 if (exit_qual == (EPT_VLT_WR | EPT_VLT_LADDR_VLD | 1427 EPT_VLT_PADDR)) 1428 vmx_inc_test_stage(); 1429 set_ept_pte(pml4, (unsigned long)data_page1, 1430 1, data_page1_pte | (EPT_PRESENT)); 1431 invept(INVEPT_SINGLE, eptp); 1432 break; 1433 case 4: 1434 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1435 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1436 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1437 if (exit_qual == (EPT_VLT_RD | 1438 (have_ad ? EPT_VLT_WR : 0) | 1439 EPT_VLT_LADDR_VLD)) 1440 vmx_inc_test_stage(); 1441 set_ept_pte(pml4, guest_pte_addr, 2, 1442 data_page1_pte_pte | (EPT_PRESENT)); 1443 invept(INVEPT_SINGLE, eptp); 1444 break; 1445 case 5: 1446 if (exit_qual & EPT_VLT_RD) 1447 vmx_inc_test_stage(); 1448 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1449 1, &memaddr_pte)); 1450 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA); 1451 invept(INVEPT_SINGLE, eptp); 1452 break; 1453 case 6: 1454 if (exit_qual & EPT_VLT_WR) 1455 vmx_inc_test_stage(); 1456 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1457 1, &memaddr_pte)); 1458 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA | EPT_WA); 1459 invept(INVEPT_SINGLE, eptp); 1460 break; 1461 default: 1462 // Should not reach here 1463 report_fail("ERROR : unexpected stage, %d", 1464 vmx_get_test_stage()); 1465 print_vmexit_info(exit_reason); 1466 return VMX_TEST_VMEXIT; 1467 } 1468 return VMX_TEST_RESUME; 1469 default: 1470 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 1471 print_vmexit_info(exit_reason); 1472 } 1473 return VMX_TEST_VMEXIT; 1474 } 1475 1476 static int ept_exit_handler(union exit_reason exit_reason) 1477 { 1478 return ept_exit_handler_common(exit_reason, false); 1479 } 1480 1481 static int eptad_init(struct vmcs *vmcs) 1482 { 1483 int r = ept_init_common(true); 1484 1485 if (r == VMX_TEST_EXIT) 1486 return r; 1487 1488 if (!ept_ad_bits_supported()) { 1489 printf("\tEPT A/D bits are not supported"); 1490 return VMX_TEST_EXIT; 1491 } 1492 1493 return r; 1494 } 1495 1496 static int pml_init(struct vmcs *vmcs) 1497 { 1498 u32 ctrl_cpu; 1499 int r = eptad_init(vmcs); 1500 1501 if (r == VMX_TEST_EXIT) 1502 return r; 1503 1504 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1505 !(ctrl_cpu_rev[1].clr & CPU_PML)) { 1506 printf("\tPML is not supported"); 1507 return VMX_TEST_EXIT; 1508 } 1509 1510 pml_log = alloc_page(); 1511 vmcs_write(PMLADDR, (u64)pml_log); 1512 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1513 1514 ctrl_cpu = vmcs_read(CPU_EXEC_CTRL1) | CPU_PML; 1515 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu); 1516 1517 return VMX_TEST_START; 1518 } 1519 1520 static void pml_main(void) 1521 { 1522 int count = 0; 1523 1524 vmx_set_test_stage(0); 1525 *((u32 *)data_page2) = 0x1; 1526 vmcall(); 1527 report(vmx_get_test_stage() == 1, "PML - Dirty GPA Logging"); 1528 1529 while (vmx_get_test_stage() == 1) { 1530 vmcall(); 1531 *((u32 *)data_page2) = 0x1; 1532 if (count++ > PML_INDEX) 1533 break; 1534 } 1535 report(vmx_get_test_stage() == 2, "PML Full Event"); 1536 } 1537 1538 static void eptad_main(void) 1539 { 1540 ept_common(); 1541 } 1542 1543 static int eptad_exit_handler(union exit_reason exit_reason) 1544 { 1545 return ept_exit_handler_common(exit_reason, true); 1546 } 1547 1548 #define TIMER_VECTOR 222 1549 1550 static volatile bool timer_fired; 1551 1552 static void timer_isr(isr_regs_t *regs) 1553 { 1554 timer_fired = true; 1555 apic_write(APIC_EOI, 0); 1556 } 1557 1558 static int interrupt_init(struct vmcs *vmcs) 1559 { 1560 msr_bmp_init(); 1561 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1562 handle_irq(TIMER_VECTOR, timer_isr); 1563 return VMX_TEST_START; 1564 } 1565 1566 static void interrupt_main(void) 1567 { 1568 long long start, loops; 1569 1570 vmx_set_test_stage(0); 1571 1572 apic_write(APIC_LVTT, TIMER_VECTOR); 1573 irq_enable(); 1574 1575 apic_write(APIC_TMICT, 1); 1576 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1577 asm volatile ("nop"); 1578 report(timer_fired, "direct interrupt while running guest"); 1579 1580 apic_write(APIC_TMICT, 0); 1581 irq_disable(); 1582 vmcall(); 1583 timer_fired = false; 1584 apic_write(APIC_TMICT, 1); 1585 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1586 asm volatile ("nop"); 1587 report(timer_fired, "intercepted interrupt while running guest"); 1588 1589 irq_enable(); 1590 apic_write(APIC_TMICT, 0); 1591 irq_disable(); 1592 vmcall(); 1593 timer_fired = false; 1594 start = rdtsc(); 1595 apic_write(APIC_TMICT, 1000000); 1596 1597 safe_halt(); 1598 1599 report(rdtsc() - start > 1000000 && timer_fired, 1600 "direct interrupt + hlt"); 1601 1602 apic_write(APIC_TMICT, 0); 1603 irq_disable(); 1604 vmcall(); 1605 timer_fired = false; 1606 start = rdtsc(); 1607 apic_write(APIC_TMICT, 1000000); 1608 1609 safe_halt(); 1610 1611 report(rdtsc() - start > 10000 && timer_fired, 1612 "intercepted interrupt + hlt"); 1613 1614 apic_write(APIC_TMICT, 0); 1615 irq_disable(); 1616 vmcall(); 1617 timer_fired = false; 1618 start = rdtsc(); 1619 apic_write(APIC_TMICT, 1000000); 1620 1621 irq_enable(); 1622 asm volatile ("nop"); 1623 vmcall(); 1624 1625 report(rdtsc() - start > 10000 && timer_fired, 1626 "direct interrupt + activity state hlt"); 1627 1628 apic_write(APIC_TMICT, 0); 1629 irq_disable(); 1630 vmcall(); 1631 timer_fired = false; 1632 start = rdtsc(); 1633 apic_write(APIC_TMICT, 1000000); 1634 1635 irq_enable(); 1636 asm volatile ("nop"); 1637 vmcall(); 1638 1639 report(rdtsc() - start > 10000 && timer_fired, 1640 "intercepted interrupt + activity state hlt"); 1641 1642 apic_write(APIC_TMICT, 0); 1643 irq_disable(); 1644 vmx_set_test_stage(7); 1645 vmcall(); 1646 timer_fired = false; 1647 apic_write(APIC_TMICT, 1); 1648 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1649 asm volatile ("nop"); 1650 report(timer_fired, 1651 "running a guest with interrupt acknowledgement set"); 1652 1653 apic_write(APIC_TMICT, 0); 1654 irq_enable(); 1655 timer_fired = false; 1656 vmcall(); 1657 report(timer_fired, "Inject an event to a halted guest"); 1658 } 1659 1660 static int interrupt_exit_handler(union exit_reason exit_reason) 1661 { 1662 u64 guest_rip = vmcs_read(GUEST_RIP); 1663 u32 insn_len = vmcs_read(EXI_INST_LEN); 1664 1665 switch (exit_reason.basic) { 1666 case VMX_VMCALL: 1667 switch (vmx_get_test_stage()) { 1668 case 0: 1669 case 2: 1670 case 5: 1671 vmcs_write(PIN_CONTROLS, 1672 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1673 break; 1674 case 7: 1675 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_INTA); 1676 vmcs_write(PIN_CONTROLS, 1677 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1678 break; 1679 case 1: 1680 case 3: 1681 vmcs_write(PIN_CONTROLS, 1682 vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1683 break; 1684 case 4: 1685 case 6: 1686 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1687 break; 1688 1689 case 8: 1690 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1691 vmcs_write(ENT_INTR_INFO, 1692 TIMER_VECTOR | 1693 (VMX_INTR_TYPE_EXT_INTR << INTR_INFO_INTR_TYPE_SHIFT) | 1694 INTR_INFO_VALID_MASK); 1695 break; 1696 } 1697 vmx_inc_test_stage(); 1698 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1699 return VMX_TEST_RESUME; 1700 case VMX_EXTINT: 1701 if (vmcs_read(EXI_CONTROLS) & EXI_INTA) { 1702 int vector = vmcs_read(EXI_INTR_INFO) & 0xff; 1703 handle_external_interrupt(vector); 1704 } else { 1705 irq_enable(); 1706 asm volatile ("nop"); 1707 irq_disable(); 1708 } 1709 if (vmx_get_test_stage() >= 2) 1710 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 1711 return VMX_TEST_RESUME; 1712 default: 1713 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 1714 print_vmexit_info(exit_reason); 1715 } 1716 1717 return VMX_TEST_VMEXIT; 1718 } 1719 1720 1721 static volatile int nmi_fired; 1722 1723 #define NMI_DELAY 100000000ULL 1724 1725 static void nmi_isr(isr_regs_t *regs) 1726 { 1727 nmi_fired = true; 1728 } 1729 1730 static int nmi_hlt_init(struct vmcs *vmcs) 1731 { 1732 msr_bmp_init(); 1733 handle_irq(NMI_VECTOR, nmi_isr); 1734 vmcs_write(PIN_CONTROLS, 1735 vmcs_read(PIN_CONTROLS) & ~PIN_NMI); 1736 vmcs_write(PIN_CONTROLS, 1737 vmcs_read(PIN_CONTROLS) & ~PIN_VIRT_NMI); 1738 return VMX_TEST_START; 1739 } 1740 1741 static void nmi_message_thread(void *data) 1742 { 1743 while (vmx_get_test_stage() != 1) 1744 pause(); 1745 1746 delay(NMI_DELAY); 1747 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_NMI | APIC_INT_ASSERT, id_map[0]); 1748 1749 while (vmx_get_test_stage() != 2) 1750 pause(); 1751 1752 delay(NMI_DELAY); 1753 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_NMI | APIC_INT_ASSERT, id_map[0]); 1754 } 1755 1756 static void nmi_hlt_main(void) 1757 { 1758 long long start; 1759 1760 if (cpu_count() < 2) { 1761 report_skip(__func__); 1762 vmx_set_test_stage(-1); 1763 return; 1764 } 1765 1766 vmx_set_test_stage(0); 1767 on_cpu_async(1, nmi_message_thread, NULL); 1768 start = rdtsc(); 1769 vmx_set_test_stage(1); 1770 asm volatile ("hlt"); 1771 report((rdtsc() - start > NMI_DELAY) && nmi_fired, 1772 "direct NMI + hlt"); 1773 if (!nmi_fired) 1774 vmx_set_test_stage(-1); 1775 nmi_fired = false; 1776 1777 vmcall(); 1778 1779 start = rdtsc(); 1780 vmx_set_test_stage(2); 1781 asm volatile ("hlt"); 1782 report((rdtsc() - start > NMI_DELAY) && !nmi_fired, 1783 "intercepted NMI + hlt"); 1784 if (nmi_fired) { 1785 report(!nmi_fired, "intercepted NMI was dispatched"); 1786 vmx_set_test_stage(-1); 1787 return; 1788 } 1789 vmx_set_test_stage(3); 1790 } 1791 1792 static int nmi_hlt_exit_handler(union exit_reason exit_reason) 1793 { 1794 u64 guest_rip = vmcs_read(GUEST_RIP); 1795 u32 insn_len = vmcs_read(EXI_INST_LEN); 1796 1797 switch (vmx_get_test_stage()) { 1798 case 1: 1799 if (exit_reason.basic != VMX_VMCALL) { 1800 report_fail("VMEXIT not due to vmcall. Exit reason 0x%x", 1801 exit_reason.full); 1802 print_vmexit_info(exit_reason); 1803 return VMX_TEST_VMEXIT; 1804 } 1805 1806 vmcs_write(PIN_CONTROLS, 1807 vmcs_read(PIN_CONTROLS) | PIN_NMI); 1808 vmcs_write(PIN_CONTROLS, 1809 vmcs_read(PIN_CONTROLS) | PIN_VIRT_NMI); 1810 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1811 break; 1812 1813 case 2: 1814 if (exit_reason.basic != VMX_EXC_NMI) { 1815 report_fail("VMEXIT not due to NMI intercept. Exit reason 0x%x", 1816 exit_reason.full); 1817 print_vmexit_info(exit_reason); 1818 return VMX_TEST_VMEXIT; 1819 } 1820 report_pass("NMI intercept while running guest"); 1821 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 1822 break; 1823 1824 case 3: 1825 break; 1826 1827 default: 1828 return VMX_TEST_VMEXIT; 1829 } 1830 1831 if (vmx_get_test_stage() == 3) 1832 return VMX_TEST_VMEXIT; 1833 1834 return VMX_TEST_RESUME; 1835 } 1836 1837 1838 static int dbgctls_init(struct vmcs *vmcs) 1839 { 1840 u64 dr7 = 0x402; 1841 u64 zero = 0; 1842 1843 msr_bmp_init(); 1844 asm volatile( 1845 "mov %0,%%dr0\n\t" 1846 "mov %0,%%dr1\n\t" 1847 "mov %0,%%dr2\n\t" 1848 "mov %1,%%dr7\n\t" 1849 : : "r" (zero), "r" (dr7)); 1850 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1851 vmcs_write(GUEST_DR7, 0x404); 1852 vmcs_write(GUEST_DEBUGCTL, 0x2); 1853 1854 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 1855 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_SAVE_DBGCTLS); 1856 1857 return VMX_TEST_START; 1858 } 1859 1860 static void dbgctls_main(void) 1861 { 1862 u64 dr7, debugctl; 1863 1864 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1865 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1866 /* Commented out: KVM does not support DEBUGCTL so far */ 1867 (void)debugctl; 1868 report(dr7 == 0x404, "Load debug controls" /* && debugctl == 0x2 */); 1869 1870 dr7 = 0x408; 1871 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1872 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1873 1874 vmx_set_test_stage(0); 1875 vmcall(); 1876 report(vmx_get_test_stage() == 1, "Save debug controls"); 1877 1878 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS || 1879 ctrl_exit_rev.set & EXI_SAVE_DBGCTLS) { 1880 printf("\tDebug controls are always loaded/saved\n"); 1881 return; 1882 } 1883 vmx_set_test_stage(2); 1884 vmcall(); 1885 1886 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1887 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1888 /* Commented out: KVM does not support DEBUGCTL so far */ 1889 (void)debugctl; 1890 report(dr7 == 0x402, 1891 "Guest=host debug controls" /* && debugctl == 0x1 */); 1892 1893 dr7 = 0x408; 1894 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1895 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1896 1897 vmx_set_test_stage(3); 1898 vmcall(); 1899 report(vmx_get_test_stage() == 4, "Don't save debug controls"); 1900 } 1901 1902 static int dbgctls_exit_handler(union exit_reason exit_reason) 1903 { 1904 u32 insn_len = vmcs_read(EXI_INST_LEN); 1905 u64 guest_rip = vmcs_read(GUEST_RIP); 1906 u64 dr7, debugctl; 1907 1908 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1909 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1910 1911 switch (exit_reason.basic) { 1912 case VMX_VMCALL: 1913 switch (vmx_get_test_stage()) { 1914 case 0: 1915 if (dr7 == 0x400 && debugctl == 0 && 1916 vmcs_read(GUEST_DR7) == 0x408 /* && 1917 Commented out: KVM does not support DEBUGCTL so far 1918 vmcs_read(GUEST_DEBUGCTL) == 0x3 */) 1919 vmx_inc_test_stage(); 1920 break; 1921 case 2: 1922 dr7 = 0x402; 1923 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1924 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1925 vmcs_write(GUEST_DR7, 0x404); 1926 vmcs_write(GUEST_DEBUGCTL, 0x2); 1927 1928 vmcs_write(ENT_CONTROLS, 1929 vmcs_read(ENT_CONTROLS) & ~ENT_LOAD_DBGCTLS); 1930 vmcs_write(EXI_CONTROLS, 1931 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_DBGCTLS); 1932 break; 1933 case 3: 1934 if (dr7 == 0x400 && debugctl == 0 && 1935 vmcs_read(GUEST_DR7) == 0x404 /* && 1936 Commented out: KVM does not support DEBUGCTL so far 1937 vmcs_read(GUEST_DEBUGCTL) == 0x2 */) 1938 vmx_inc_test_stage(); 1939 break; 1940 } 1941 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1942 return VMX_TEST_RESUME; 1943 default: 1944 report_fail("Unknown exit reason, %d", exit_reason.full); 1945 print_vmexit_info(exit_reason); 1946 } 1947 return VMX_TEST_VMEXIT; 1948 } 1949 1950 struct vmx_msr_entry { 1951 u32 index; 1952 u32 reserved; 1953 u64 value; 1954 } __attribute__((packed)); 1955 1956 #define MSR_MAGIC 0x31415926 1957 struct vmx_msr_entry *exit_msr_store, *entry_msr_load, *exit_msr_load; 1958 1959 static int msr_switch_init(struct vmcs *vmcs) 1960 { 1961 msr_bmp_init(); 1962 exit_msr_store = alloc_page(); 1963 exit_msr_load = alloc_page(); 1964 entry_msr_load = alloc_page(); 1965 entry_msr_load[0].index = MSR_KERNEL_GS_BASE; 1966 entry_msr_load[0].value = MSR_MAGIC; 1967 1968 vmx_set_test_stage(1); 1969 vmcs_write(ENT_MSR_LD_CNT, 1); 1970 vmcs_write(ENTER_MSR_LD_ADDR, (u64)entry_msr_load); 1971 vmcs_write(EXI_MSR_ST_CNT, 1); 1972 vmcs_write(EXIT_MSR_ST_ADDR, (u64)exit_msr_store); 1973 vmcs_write(EXI_MSR_LD_CNT, 1); 1974 vmcs_write(EXIT_MSR_LD_ADDR, (u64)exit_msr_load); 1975 return VMX_TEST_START; 1976 } 1977 1978 static void msr_switch_main(void) 1979 { 1980 if (vmx_get_test_stage() == 1) { 1981 report(rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC, 1982 "VM entry MSR load"); 1983 vmx_set_test_stage(2); 1984 wrmsr(MSR_KERNEL_GS_BASE, MSR_MAGIC + 1); 1985 exit_msr_store[0].index = MSR_KERNEL_GS_BASE; 1986 exit_msr_load[0].index = MSR_KERNEL_GS_BASE; 1987 exit_msr_load[0].value = MSR_MAGIC + 2; 1988 } 1989 vmcall(); 1990 } 1991 1992 static int msr_switch_exit_handler(union exit_reason exit_reason) 1993 { 1994 if (exit_reason.basic == VMX_VMCALL && vmx_get_test_stage() == 2) { 1995 report(exit_msr_store[0].value == MSR_MAGIC + 1, 1996 "VM exit MSR store"); 1997 report(rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC + 2, 1998 "VM exit MSR load"); 1999 vmx_set_test_stage(3); 2000 entry_msr_load[0].index = MSR_FS_BASE; 2001 return VMX_TEST_RESUME; 2002 } 2003 printf("ERROR %s: unexpected stage=%u or reason=0x%x\n", 2004 __func__, vmx_get_test_stage(), exit_reason.full); 2005 return VMX_TEST_EXIT; 2006 } 2007 2008 static int msr_switch_entry_failure(struct vmentry_result *result) 2009 { 2010 if (result->vm_fail) { 2011 printf("ERROR %s: VM-Fail on %s\n", __func__, result->instr); 2012 return VMX_TEST_EXIT; 2013 } 2014 2015 if (result->exit_reason.failed_vmentry && 2016 result->exit_reason.basic == VMX_FAIL_MSR && 2017 vmx_get_test_stage() == 3) { 2018 report(vmcs_read(EXI_QUALIFICATION) == 1, 2019 "VM entry MSR load: try to load FS_BASE"); 2020 return VMX_TEST_VMEXIT; 2021 } 2022 printf("ERROR %s: unexpected stage=%u or reason=%x\n", 2023 __func__, vmx_get_test_stage(), result->exit_reason.full); 2024 return VMX_TEST_EXIT; 2025 } 2026 2027 static int vmmcall_init(struct vmcs *vmcs) 2028 { 2029 vmcs_write(EXC_BITMAP, 1 << UD_VECTOR); 2030 return VMX_TEST_START; 2031 } 2032 2033 static void vmmcall_main(void) 2034 { 2035 asm volatile( 2036 "mov $0xABCD, %%rax\n\t" 2037 "vmmcall\n\t" 2038 ::: "rax"); 2039 2040 report_fail("VMMCALL"); 2041 } 2042 2043 static int vmmcall_exit_handler(union exit_reason exit_reason) 2044 { 2045 switch (exit_reason.basic) { 2046 case VMX_VMCALL: 2047 printf("here\n"); 2048 report_fail("VMMCALL triggers #UD"); 2049 break; 2050 case VMX_EXC_NMI: 2051 report((vmcs_read(EXI_INTR_INFO) & 0xff) == UD_VECTOR, 2052 "VMMCALL triggers #UD"); 2053 break; 2054 default: 2055 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 2056 print_vmexit_info(exit_reason); 2057 } 2058 2059 return VMX_TEST_VMEXIT; 2060 } 2061 2062 static int disable_rdtscp_init(struct vmcs *vmcs) 2063 { 2064 u32 ctrl_cpu1; 2065 2066 if (ctrl_cpu_rev[0].clr & CPU_SECONDARY) { 2067 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 2068 ctrl_cpu1 &= ~CPU_RDTSCP; 2069 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 2070 } 2071 2072 return VMX_TEST_START; 2073 } 2074 2075 static void disable_rdtscp_ud_handler(struct ex_regs *regs) 2076 { 2077 switch (vmx_get_test_stage()) { 2078 case 0: 2079 report_pass("RDTSCP triggers #UD"); 2080 vmx_inc_test_stage(); 2081 regs->rip += 3; 2082 break; 2083 case 2: 2084 report_pass("RDPID triggers #UD"); 2085 vmx_inc_test_stage(); 2086 regs->rip += 4; 2087 break; 2088 } 2089 return; 2090 2091 } 2092 2093 static void disable_rdtscp_main(void) 2094 { 2095 /* Test that #UD is properly injected in L2. */ 2096 handle_exception(UD_VECTOR, disable_rdtscp_ud_handler); 2097 2098 vmx_set_test_stage(0); 2099 asm volatile("rdtscp" : : : "eax", "ecx", "edx"); 2100 vmcall(); 2101 asm volatile(".byte 0xf3, 0x0f, 0xc7, 0xf8" : : : "eax"); 2102 2103 handle_exception(UD_VECTOR, 0); 2104 vmcall(); 2105 } 2106 2107 static int disable_rdtscp_exit_handler(union exit_reason exit_reason) 2108 { 2109 switch (exit_reason.basic) { 2110 case VMX_VMCALL: 2111 switch (vmx_get_test_stage()) { 2112 case 0: 2113 report_fail("RDTSCP triggers #UD"); 2114 vmx_inc_test_stage(); 2115 /* fallthrough */ 2116 case 1: 2117 vmx_inc_test_stage(); 2118 vmcs_write(GUEST_RIP, vmcs_read(GUEST_RIP) + 3); 2119 return VMX_TEST_RESUME; 2120 case 2: 2121 report_fail("RDPID triggers #UD"); 2122 break; 2123 } 2124 break; 2125 2126 default: 2127 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 2128 print_vmexit_info(exit_reason); 2129 } 2130 return VMX_TEST_VMEXIT; 2131 } 2132 2133 static int int3_init(struct vmcs *vmcs) 2134 { 2135 vmcs_write(EXC_BITMAP, ~0u); 2136 return VMX_TEST_START; 2137 } 2138 2139 static void int3_guest_main(void) 2140 { 2141 asm volatile ("int3"); 2142 } 2143 2144 static int int3_exit_handler(union exit_reason exit_reason) 2145 { 2146 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2147 2148 report(exit_reason.basic == VMX_EXC_NMI && 2149 (intr_info & INTR_INFO_VALID_MASK) && 2150 (intr_info & INTR_INFO_VECTOR_MASK) == BP_VECTOR && 2151 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2152 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION, 2153 "L1 intercepts #BP"); 2154 2155 return VMX_TEST_VMEXIT; 2156 } 2157 2158 static int into_init(struct vmcs *vmcs) 2159 { 2160 vmcs_write(EXC_BITMAP, ~0u); 2161 return VMX_TEST_START; 2162 } 2163 2164 static void into_guest_main(void) 2165 { 2166 struct far_pointer32 fp = { 2167 .offset = (uintptr_t)&&into, 2168 .selector = KERNEL_CS32, 2169 }; 2170 uintptr_t rsp; 2171 2172 asm volatile ("mov %%rsp, %0" : "=r"(rsp)); 2173 2174 if (fp.offset != (uintptr_t)&&into) { 2175 printf("Code address too high.\n"); 2176 return; 2177 } 2178 if ((u32)rsp != rsp) { 2179 printf("Stack address too high.\n"); 2180 return; 2181 } 2182 2183 asm goto ("lcall *%0" : : "m" (fp) : "rax" : into); 2184 return; 2185 into: 2186 asm volatile (".code32;" 2187 "movl $0x7fffffff, %eax;" 2188 "addl %eax, %eax;" 2189 "into;" 2190 "lret;" 2191 ".code64"); 2192 __builtin_unreachable(); 2193 } 2194 2195 static int into_exit_handler(union exit_reason exit_reason) 2196 { 2197 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2198 2199 report(exit_reason.basic == VMX_EXC_NMI && 2200 (intr_info & INTR_INFO_VALID_MASK) && 2201 (intr_info & INTR_INFO_VECTOR_MASK) == OF_VECTOR && 2202 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2203 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION, 2204 "L1 intercepts #OF"); 2205 2206 return VMX_TEST_VMEXIT; 2207 } 2208 2209 static void exit_monitor_from_l2_main(void) 2210 { 2211 printf("Calling exit(0) from l2...\n"); 2212 exit(0); 2213 } 2214 2215 static int exit_monitor_from_l2_handler(union exit_reason exit_reason) 2216 { 2217 report_fail("The guest should have killed the VMM"); 2218 return VMX_TEST_EXIT; 2219 } 2220 2221 static void assert_exit_reason(u64 expected) 2222 { 2223 u64 actual = vmcs_read(EXI_REASON); 2224 2225 TEST_ASSERT_EQ_MSG(expected, actual, "Expected %s, got %s.", 2226 exit_reason_description(expected), 2227 exit_reason_description(actual)); 2228 } 2229 2230 static void skip_exit_insn(void) 2231 { 2232 u64 guest_rip = vmcs_read(GUEST_RIP); 2233 u32 insn_len = vmcs_read(EXI_INST_LEN); 2234 vmcs_write(GUEST_RIP, guest_rip + insn_len); 2235 } 2236 2237 static void skip_exit_vmcall(void) 2238 { 2239 assert_exit_reason(VMX_VMCALL); 2240 skip_exit_insn(); 2241 } 2242 2243 static void v2_null_test_guest(void) 2244 { 2245 } 2246 2247 static void v2_null_test(void) 2248 { 2249 test_set_guest(v2_null_test_guest); 2250 enter_guest(); 2251 report_pass(__func__); 2252 } 2253 2254 static void v2_multiple_entries_test_guest(void) 2255 { 2256 vmx_set_test_stage(1); 2257 vmcall(); 2258 vmx_set_test_stage(2); 2259 } 2260 2261 static void v2_multiple_entries_test(void) 2262 { 2263 test_set_guest(v2_multiple_entries_test_guest); 2264 enter_guest(); 2265 TEST_ASSERT_EQ(vmx_get_test_stage(), 1); 2266 skip_exit_vmcall(); 2267 enter_guest(); 2268 TEST_ASSERT_EQ(vmx_get_test_stage(), 2); 2269 report_pass(__func__); 2270 } 2271 2272 static int fixture_test_data = 1; 2273 2274 static void fixture_test_teardown(void *data) 2275 { 2276 *((int *) data) = 1; 2277 } 2278 2279 static void fixture_test_guest(void) 2280 { 2281 fixture_test_data++; 2282 } 2283 2284 2285 static void fixture_test_setup(void) 2286 { 2287 TEST_ASSERT_EQ_MSG(1, fixture_test_data, 2288 "fixture_test_teardown didn't run?!"); 2289 fixture_test_data = 2; 2290 test_add_teardown(fixture_test_teardown, &fixture_test_data); 2291 test_set_guest(fixture_test_guest); 2292 } 2293 2294 static void fixture_test_case1(void) 2295 { 2296 fixture_test_setup(); 2297 TEST_ASSERT_EQ(2, fixture_test_data); 2298 enter_guest(); 2299 TEST_ASSERT_EQ(3, fixture_test_data); 2300 report_pass(__func__); 2301 } 2302 2303 static void fixture_test_case2(void) 2304 { 2305 fixture_test_setup(); 2306 TEST_ASSERT_EQ(2, fixture_test_data); 2307 enter_guest(); 2308 TEST_ASSERT_EQ(3, fixture_test_data); 2309 report_pass(__func__); 2310 } 2311 2312 enum ept_access_op { 2313 OP_READ, 2314 OP_WRITE, 2315 OP_EXEC, 2316 OP_FLUSH_TLB, 2317 OP_EXIT, 2318 }; 2319 2320 static struct ept_access_test_data { 2321 unsigned long gpa; 2322 unsigned long *gva; 2323 unsigned long hpa; 2324 unsigned long *hva; 2325 enum ept_access_op op; 2326 } ept_access_test_data; 2327 2328 extern unsigned char ret42_start; 2329 extern unsigned char ret42_end; 2330 2331 /* Returns 42. */ 2332 asm( 2333 ".align 64\n" 2334 "ret42_start:\n" 2335 "mov $42, %eax\n" 2336 "ret\n" 2337 "ret42_end:\n" 2338 ); 2339 2340 static void 2341 diagnose_ept_violation_qual(u64 expected, u64 actual) 2342 { 2343 2344 #define DIAGNOSE(flag) \ 2345 do { \ 2346 if ((expected & flag) != (actual & flag)) \ 2347 printf(#flag " %sexpected\n", \ 2348 (expected & flag) ? "" : "un"); \ 2349 } while (0) 2350 2351 DIAGNOSE(EPT_VLT_RD); 2352 DIAGNOSE(EPT_VLT_WR); 2353 DIAGNOSE(EPT_VLT_FETCH); 2354 DIAGNOSE(EPT_VLT_PERM_RD); 2355 DIAGNOSE(EPT_VLT_PERM_WR); 2356 DIAGNOSE(EPT_VLT_PERM_EX); 2357 DIAGNOSE(EPT_VLT_LADDR_VLD); 2358 DIAGNOSE(EPT_VLT_PADDR); 2359 2360 #undef DIAGNOSE 2361 } 2362 2363 static void do_ept_access_op(enum ept_access_op op) 2364 { 2365 ept_access_test_data.op = op; 2366 enter_guest(); 2367 } 2368 2369 /* 2370 * Force the guest to flush its TLB (i.e., flush gva -> gpa mappings). Only 2371 * needed by tests that modify guest PTEs. 2372 */ 2373 static void ept_access_test_guest_flush_tlb(void) 2374 { 2375 do_ept_access_op(OP_FLUSH_TLB); 2376 skip_exit_vmcall(); 2377 } 2378 2379 /* 2380 * Modifies the EPT entry at @level in the mapping of @gpa. First clears the 2381 * bits in @clear then sets the bits in @set. @mkhuge transforms the entry into 2382 * a huge page. 2383 */ 2384 static unsigned long ept_twiddle(unsigned long gpa, bool mkhuge, int level, 2385 unsigned long clear, unsigned long set) 2386 { 2387 struct ept_access_test_data *data = &ept_access_test_data; 2388 unsigned long orig_pte; 2389 unsigned long pte; 2390 2391 /* Screw with the mapping at the requested level. */ 2392 TEST_ASSERT(get_ept_pte(pml4, gpa, level, &orig_pte)); 2393 pte = orig_pte; 2394 if (mkhuge) 2395 pte = (orig_pte & ~EPT_ADDR_MASK) | data->hpa | EPT_LARGE_PAGE; 2396 else 2397 pte = orig_pte; 2398 pte = (pte & ~clear) | set; 2399 set_ept_pte(pml4, gpa, level, pte); 2400 invept(INVEPT_SINGLE, eptp); 2401 2402 return orig_pte; 2403 } 2404 2405 static void ept_untwiddle(unsigned long gpa, int level, unsigned long orig_pte) 2406 { 2407 set_ept_pte(pml4, gpa, level, orig_pte); 2408 invept(INVEPT_SINGLE, eptp); 2409 } 2410 2411 static void do_ept_violation(bool leaf, enum ept_access_op op, 2412 u64 expected_qual, u64 expected_paddr) 2413 { 2414 u64 qual; 2415 2416 /* Try the access and observe the violation. */ 2417 do_ept_access_op(op); 2418 2419 assert_exit_reason(VMX_EPT_VIOLATION); 2420 2421 qual = vmcs_read(EXI_QUALIFICATION); 2422 2423 /* Mask undefined bits (which may later be defined in certain cases). */ 2424 qual &= ~(EPT_VLT_GUEST_USER | EPT_VLT_GUEST_RW | EPT_VLT_GUEST_EX | 2425 EPT_VLT_PERM_USER_EX); 2426 2427 diagnose_ept_violation_qual(expected_qual, qual); 2428 TEST_EXPECT_EQ(expected_qual, qual); 2429 2430 #if 0 2431 /* Disable for now otherwise every test will fail */ 2432 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2433 (unsigned long) ( 2434 op == OP_EXEC ? data->gva + 1 : data->gva)); 2435 #endif 2436 /* 2437 * TODO: tests that probe expected_paddr in pages other than the one at 2438 * the beginning of the 1g region. 2439 */ 2440 TEST_EXPECT_EQ(vmcs_read(INFO_PHYS_ADDR), expected_paddr); 2441 } 2442 2443 static void 2444 ept_violation_at_level_mkhuge(bool mkhuge, int level, unsigned long clear, 2445 unsigned long set, enum ept_access_op op, 2446 u64 expected_qual) 2447 { 2448 struct ept_access_test_data *data = &ept_access_test_data; 2449 unsigned long orig_pte; 2450 2451 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2452 2453 do_ept_violation(level == 1 || mkhuge, op, expected_qual, 2454 op == OP_EXEC ? data->gpa + sizeof(unsigned long) : 2455 data->gpa); 2456 2457 /* Fix the violation and resume the op loop. */ 2458 ept_untwiddle(data->gpa, level, orig_pte); 2459 enter_guest(); 2460 skip_exit_vmcall(); 2461 } 2462 2463 static void 2464 ept_violation_at_level(int level, unsigned long clear, unsigned long set, 2465 enum ept_access_op op, u64 expected_qual) 2466 { 2467 ept_violation_at_level_mkhuge(false, level, clear, set, op, 2468 expected_qual); 2469 if (ept_huge_pages_supported(level)) 2470 ept_violation_at_level_mkhuge(true, level, clear, set, op, 2471 expected_qual); 2472 } 2473 2474 static void ept_violation(unsigned long clear, unsigned long set, 2475 enum ept_access_op op, u64 expected_qual) 2476 { 2477 ept_violation_at_level(1, clear, set, op, expected_qual); 2478 ept_violation_at_level(2, clear, set, op, expected_qual); 2479 ept_violation_at_level(3, clear, set, op, expected_qual); 2480 ept_violation_at_level(4, clear, set, op, expected_qual); 2481 } 2482 2483 static void ept_access_violation(unsigned long access, enum ept_access_op op, 2484 u64 expected_qual) 2485 { 2486 ept_violation(EPT_PRESENT, access, op, 2487 expected_qual | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2488 } 2489 2490 /* 2491 * For translations that don't involve a GVA, that is physical address (paddr) 2492 * accesses, EPT violations don't set the flag EPT_VLT_PADDR. For a typical 2493 * guest memory access, the hardware does GVA -> GPA -> HPA. However, certain 2494 * translations don't involve GVAs, such as when the hardware does the guest 2495 * page table walk. For example, in translating GVA_1 -> GPA_1, the guest MMU 2496 * might try to set an A bit on a guest PTE. If the GPA_2 that the PTE resides 2497 * on isn't present in the EPT, then the EPT violation will be for GPA_2 and 2498 * the EPT_VLT_PADDR bit will be clear in the exit qualification. 2499 * 2500 * Note that paddr violations can also be triggered by loading PAE page tables 2501 * with wonky addresses. We don't test that yet. 2502 * 2503 * This function modifies the EPT entry that maps the GPA that the guest page 2504 * table entry mapping ept_access_test_data.gva resides on. 2505 * 2506 * @ept_access EPT permissions to set. Other permissions are cleared. 2507 * 2508 * @pte_ad Set the A/D bits on the guest PTE accordingly. 2509 * 2510 * @op Guest operation to perform with 2511 * ept_access_test_data.gva. 2512 * 2513 * @expect_violation 2514 * Is a violation expected during the paddr access? 2515 * 2516 * @expected_qual Expected qualification for the EPT violation. 2517 * EPT_VLT_PADDR should be clear. 2518 */ 2519 static void ept_access_paddr(unsigned long ept_access, unsigned long pte_ad, 2520 enum ept_access_op op, bool expect_violation, 2521 u64 expected_qual) 2522 { 2523 struct ept_access_test_data *data = &ept_access_test_data; 2524 unsigned long *ptep; 2525 unsigned long gpa; 2526 unsigned long orig_epte; 2527 unsigned long epte; 2528 int i; 2529 2530 /* Modify the guest PTE mapping data->gva according to @pte_ad. */ 2531 ptep = get_pte_level(current_page_table(), data->gva, /*level=*/1); 2532 TEST_ASSERT(ptep); 2533 TEST_ASSERT_EQ(*ptep & PT_ADDR_MASK, data->gpa); 2534 *ptep = (*ptep & ~PT_AD_MASK) | pte_ad; 2535 ept_access_test_guest_flush_tlb(); 2536 2537 /* 2538 * Now modify the access bits on the EPT entry for the GPA that the 2539 * guest PTE resides on. Note that by modifying a single EPT entry, 2540 * we're potentially affecting 512 guest PTEs. However, we've carefully 2541 * constructed our test such that those other 511 PTEs aren't used by 2542 * the guest: data->gva is at the beginning of a 1G huge page, thus the 2543 * PTE we're modifying is at the beginning of a 4K page and the 2544 * following 511 entires are also under our control (and not touched by 2545 * the guest). 2546 */ 2547 gpa = virt_to_phys(ptep); 2548 TEST_ASSERT_EQ(gpa & ~PAGE_MASK, 0); 2549 /* 2550 * Make sure the guest page table page is mapped with a 4K EPT entry, 2551 * otherwise our level=1 twiddling below will fail. We use the 2552 * identity map (gpa = gpa) since page tables are shared with the host. 2553 */ 2554 install_ept(pml4, gpa, gpa, EPT_PRESENT); 2555 orig_epte = ept_twiddle(gpa, /*mkhuge=*/0, /*level=*/1, 2556 /*clear=*/EPT_PRESENT, /*set=*/ept_access); 2557 2558 if (expect_violation) { 2559 do_ept_violation(/*leaf=*/true, op, 2560 expected_qual | EPT_VLT_LADDR_VLD, gpa); 2561 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2562 do_ept_access_op(op); 2563 } else { 2564 do_ept_access_op(op); 2565 if (ept_ad_enabled()) { 2566 for (i = EPT_PAGE_LEVEL; i > 0; i--) { 2567 TEST_ASSERT(get_ept_pte(pml4, gpa, i, &epte)); 2568 TEST_ASSERT(epte & EPT_ACCESS_FLAG); 2569 if (i == 1) 2570 TEST_ASSERT(epte & EPT_DIRTY_FLAG); 2571 else 2572 TEST_ASSERT_EQ(epte & EPT_DIRTY_FLAG, 0); 2573 } 2574 } 2575 2576 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2577 } 2578 2579 TEST_ASSERT(*ptep & PT_ACCESSED_MASK); 2580 if ((pte_ad & PT_DIRTY_MASK) || op == OP_WRITE) 2581 TEST_ASSERT(*ptep & PT_DIRTY_MASK); 2582 2583 skip_exit_vmcall(); 2584 } 2585 2586 static void ept_access_allowed_paddr(unsigned long ept_access, 2587 unsigned long pte_ad, 2588 enum ept_access_op op) 2589 { 2590 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/false, 2591 /*expected_qual=*/-1); 2592 } 2593 2594 static void ept_access_violation_paddr(unsigned long ept_access, 2595 unsigned long pte_ad, 2596 enum ept_access_op op, 2597 u64 expected_qual) 2598 { 2599 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/true, 2600 expected_qual); 2601 } 2602 2603 2604 static void ept_allowed_at_level_mkhuge(bool mkhuge, int level, 2605 unsigned long clear, 2606 unsigned long set, 2607 enum ept_access_op op) 2608 { 2609 struct ept_access_test_data *data = &ept_access_test_data; 2610 unsigned long orig_pte; 2611 2612 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2613 2614 /* No violation. Should proceed to vmcall. */ 2615 do_ept_access_op(op); 2616 skip_exit_vmcall(); 2617 2618 ept_untwiddle(data->gpa, level, orig_pte); 2619 } 2620 2621 static void ept_allowed_at_level(int level, unsigned long clear, 2622 unsigned long set, enum ept_access_op op) 2623 { 2624 ept_allowed_at_level_mkhuge(false, level, clear, set, op); 2625 if (ept_huge_pages_supported(level)) 2626 ept_allowed_at_level_mkhuge(true, level, clear, set, op); 2627 } 2628 2629 static void ept_allowed(unsigned long clear, unsigned long set, 2630 enum ept_access_op op) 2631 { 2632 ept_allowed_at_level(1, clear, set, op); 2633 ept_allowed_at_level(2, clear, set, op); 2634 ept_allowed_at_level(3, clear, set, op); 2635 ept_allowed_at_level(4, clear, set, op); 2636 } 2637 2638 static void ept_ignored_bit(int bit) 2639 { 2640 /* Set the bit. */ 2641 ept_allowed(0, 1ul << bit, OP_READ); 2642 ept_allowed(0, 1ul << bit, OP_WRITE); 2643 ept_allowed(0, 1ul << bit, OP_EXEC); 2644 2645 /* Clear the bit. */ 2646 ept_allowed(1ul << bit, 0, OP_READ); 2647 ept_allowed(1ul << bit, 0, OP_WRITE); 2648 ept_allowed(1ul << bit, 0, OP_EXEC); 2649 } 2650 2651 static void ept_access_allowed(unsigned long access, enum ept_access_op op) 2652 { 2653 ept_allowed(EPT_PRESENT, access, op); 2654 } 2655 2656 2657 static void ept_misconfig_at_level_mkhuge_op(bool mkhuge, int level, 2658 unsigned long clear, 2659 unsigned long set, 2660 enum ept_access_op op) 2661 { 2662 struct ept_access_test_data *data = &ept_access_test_data; 2663 unsigned long orig_pte; 2664 2665 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2666 2667 do_ept_access_op(op); 2668 assert_exit_reason(VMX_EPT_MISCONFIG); 2669 2670 /* Intel 27.2.1, "For all other VM exits, this field is cleared." */ 2671 #if 0 2672 /* broken: */ 2673 TEST_EXPECT_EQ_MSG(vmcs_read(EXI_QUALIFICATION), 0); 2674 #endif 2675 #if 0 2676 /* 2677 * broken: 2678 * According to description of exit qual for EPT violation, 2679 * EPT_VLT_LADDR_VLD indicates if GUEST_LINEAR_ADDRESS is valid. 2680 * However, I can't find anything that says GUEST_LINEAR_ADDRESS ought 2681 * to be set for msiconfig. 2682 */ 2683 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2684 (unsigned long) ( 2685 op == OP_EXEC ? data->gva + 1 : data->gva)); 2686 #endif 2687 2688 /* Fix the violation and resume the op loop. */ 2689 ept_untwiddle(data->gpa, level, orig_pte); 2690 enter_guest(); 2691 skip_exit_vmcall(); 2692 } 2693 2694 static void ept_misconfig_at_level_mkhuge(bool mkhuge, int level, 2695 unsigned long clear, 2696 unsigned long set) 2697 { 2698 /* The op shouldn't matter (read, write, exec), so try them all! */ 2699 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_READ); 2700 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_WRITE); 2701 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_EXEC); 2702 } 2703 2704 static void ept_misconfig_at_level(int level, unsigned long clear, 2705 unsigned long set) 2706 { 2707 ept_misconfig_at_level_mkhuge(false, level, clear, set); 2708 if (ept_huge_pages_supported(level)) 2709 ept_misconfig_at_level_mkhuge(true, level, clear, set); 2710 } 2711 2712 static void ept_misconfig(unsigned long clear, unsigned long set) 2713 { 2714 ept_misconfig_at_level(1, clear, set); 2715 ept_misconfig_at_level(2, clear, set); 2716 ept_misconfig_at_level(3, clear, set); 2717 ept_misconfig_at_level(4, clear, set); 2718 } 2719 2720 static void ept_access_misconfig(unsigned long access) 2721 { 2722 ept_misconfig(EPT_PRESENT, access); 2723 } 2724 2725 static void ept_reserved_bit_at_level_nohuge(int level, int bit) 2726 { 2727 /* Setting the bit causes a misconfig. */ 2728 ept_misconfig_at_level_mkhuge(false, level, 0, 1ul << bit); 2729 2730 /* Making the entry non-present turns reserved bits into ignored. */ 2731 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2732 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2733 } 2734 2735 static void ept_reserved_bit_at_level_huge(int level, int bit) 2736 { 2737 /* Setting the bit causes a misconfig. */ 2738 ept_misconfig_at_level_mkhuge(true, level, 0, 1ul << bit); 2739 2740 /* Making the entry non-present turns reserved bits into ignored. */ 2741 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2742 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2743 } 2744 2745 static void ept_reserved_bit_at_level(int level, int bit) 2746 { 2747 /* Setting the bit causes a misconfig. */ 2748 ept_misconfig_at_level(level, 0, 1ul << bit); 2749 2750 /* Making the entry non-present turns reserved bits into ignored. */ 2751 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2752 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2753 } 2754 2755 static void ept_reserved_bit(int bit) 2756 { 2757 ept_reserved_bit_at_level(1, bit); 2758 ept_reserved_bit_at_level(2, bit); 2759 ept_reserved_bit_at_level(3, bit); 2760 ept_reserved_bit_at_level(4, bit); 2761 } 2762 2763 #define PAGE_2M_ORDER 9 2764 #define PAGE_1G_ORDER 18 2765 2766 static void *get_1g_page(void) 2767 { 2768 static void *alloc; 2769 2770 if (!alloc) 2771 alloc = alloc_pages(PAGE_1G_ORDER); 2772 return alloc; 2773 } 2774 2775 static void ept_access_test_teardown(void *unused) 2776 { 2777 /* Exit the guest cleanly. */ 2778 do_ept_access_op(OP_EXIT); 2779 } 2780 2781 static void ept_access_test_guest(void) 2782 { 2783 struct ept_access_test_data *data = &ept_access_test_data; 2784 int (*code)(void) = (int (*)(void)) &data->gva[1]; 2785 2786 while (true) { 2787 switch (data->op) { 2788 case OP_READ: 2789 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_1); 2790 break; 2791 case OP_WRITE: 2792 *data->gva = MAGIC_VAL_2; 2793 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_2); 2794 *data->gva = MAGIC_VAL_1; 2795 break; 2796 case OP_EXEC: 2797 TEST_ASSERT_EQ(42, code()); 2798 break; 2799 case OP_FLUSH_TLB: 2800 write_cr3(read_cr3()); 2801 break; 2802 case OP_EXIT: 2803 return; 2804 default: 2805 TEST_ASSERT_MSG(false, "Unknown op %d", data->op); 2806 } 2807 vmcall(); 2808 } 2809 } 2810 2811 static void ept_access_test_setup(void) 2812 { 2813 struct ept_access_test_data *data = &ept_access_test_data; 2814 unsigned long npages = 1ul << PAGE_1G_ORDER; 2815 unsigned long size = npages * PAGE_SIZE; 2816 unsigned long *page_table = current_page_table(); 2817 unsigned long pte; 2818 2819 if (setup_ept(false)) 2820 test_skip("EPT not supported"); 2821 2822 /* We use data->gpa = 1 << 39 so that test data has a separate pml4 entry */ 2823 if (cpuid_maxphyaddr() < 40) 2824 test_skip("Test needs MAXPHYADDR >= 40"); 2825 2826 test_set_guest(ept_access_test_guest); 2827 test_add_teardown(ept_access_test_teardown, NULL); 2828 2829 data->hva = get_1g_page(); 2830 TEST_ASSERT(data->hva); 2831 data->hpa = virt_to_phys(data->hva); 2832 2833 data->gpa = 1ul << 39; 2834 data->gva = (void *) ALIGN((unsigned long) alloc_vpages(npages * 2), 2835 size); 2836 TEST_ASSERT(!any_present_pages(page_table, data->gva, size)); 2837 install_pages(page_table, data->gpa, size, data->gva); 2838 2839 /* 2840 * Make sure nothing's mapped here so the tests that screw with the 2841 * pml4 entry don't inadvertently break something. 2842 */ 2843 TEST_ASSERT(get_ept_pte(pml4, data->gpa, 4, &pte) && pte == 0); 2844 TEST_ASSERT(get_ept_pte(pml4, data->gpa + size - 1, 4, &pte) && pte == 0); 2845 install_ept(pml4, data->hpa, data->gpa, EPT_PRESENT); 2846 2847 data->hva[0] = MAGIC_VAL_1; 2848 memcpy(&data->hva[1], &ret42_start, &ret42_end - &ret42_start); 2849 } 2850 2851 static void ept_access_test_not_present(void) 2852 { 2853 ept_access_test_setup(); 2854 /* --- */ 2855 ept_access_violation(0, OP_READ, EPT_VLT_RD); 2856 ept_access_violation(0, OP_WRITE, EPT_VLT_WR); 2857 ept_access_violation(0, OP_EXEC, EPT_VLT_FETCH); 2858 } 2859 2860 static void ept_access_test_read_only(void) 2861 { 2862 ept_access_test_setup(); 2863 2864 /* r-- */ 2865 ept_access_allowed(EPT_RA, OP_READ); 2866 ept_access_violation(EPT_RA, OP_WRITE, EPT_VLT_WR | EPT_VLT_PERM_RD); 2867 ept_access_violation(EPT_RA, OP_EXEC, EPT_VLT_FETCH | EPT_VLT_PERM_RD); 2868 } 2869 2870 static void ept_access_test_write_only(void) 2871 { 2872 ept_access_test_setup(); 2873 /* -w- */ 2874 ept_access_misconfig(EPT_WA); 2875 } 2876 2877 static void ept_access_test_read_write(void) 2878 { 2879 ept_access_test_setup(); 2880 /* rw- */ 2881 ept_access_allowed(EPT_RA | EPT_WA, OP_READ); 2882 ept_access_allowed(EPT_RA | EPT_WA, OP_WRITE); 2883 ept_access_violation(EPT_RA | EPT_WA, OP_EXEC, 2884 EPT_VLT_FETCH | EPT_VLT_PERM_RD | EPT_VLT_PERM_WR); 2885 } 2886 2887 2888 static void ept_access_test_execute_only(void) 2889 { 2890 ept_access_test_setup(); 2891 /* --x */ 2892 if (ept_execute_only_supported()) { 2893 ept_access_violation(EPT_EA, OP_READ, 2894 EPT_VLT_RD | EPT_VLT_PERM_EX); 2895 ept_access_violation(EPT_EA, OP_WRITE, 2896 EPT_VLT_WR | EPT_VLT_PERM_EX); 2897 ept_access_allowed(EPT_EA, OP_EXEC); 2898 } else { 2899 ept_access_misconfig(EPT_EA); 2900 } 2901 } 2902 2903 static void ept_access_test_read_execute(void) 2904 { 2905 ept_access_test_setup(); 2906 /* r-x */ 2907 ept_access_allowed(EPT_RA | EPT_EA, OP_READ); 2908 ept_access_violation(EPT_RA | EPT_EA, OP_WRITE, 2909 EPT_VLT_WR | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX); 2910 ept_access_allowed(EPT_RA | EPT_EA, OP_EXEC); 2911 } 2912 2913 static void ept_access_test_write_execute(void) 2914 { 2915 ept_access_test_setup(); 2916 /* -wx */ 2917 ept_access_misconfig(EPT_WA | EPT_EA); 2918 } 2919 2920 static void ept_access_test_read_write_execute(void) 2921 { 2922 ept_access_test_setup(); 2923 /* rwx */ 2924 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_READ); 2925 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_WRITE); 2926 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_EXEC); 2927 } 2928 2929 static void ept_access_test_reserved_bits(void) 2930 { 2931 int i; 2932 int maxphyaddr; 2933 2934 ept_access_test_setup(); 2935 2936 /* Reserved bits above maxphyaddr. */ 2937 maxphyaddr = cpuid_maxphyaddr(); 2938 for (i = maxphyaddr; i <= 51; i++) { 2939 report_prefix_pushf("reserved_bit=%d", i); 2940 ept_reserved_bit(i); 2941 report_prefix_pop(); 2942 } 2943 2944 /* Level-specific reserved bits. */ 2945 ept_reserved_bit_at_level_nohuge(2, 3); 2946 ept_reserved_bit_at_level_nohuge(2, 4); 2947 ept_reserved_bit_at_level_nohuge(2, 5); 2948 ept_reserved_bit_at_level_nohuge(2, 6); 2949 /* 2M alignment. */ 2950 for (i = 12; i < 20; i++) { 2951 report_prefix_pushf("reserved_bit=%d", i); 2952 ept_reserved_bit_at_level_huge(2, i); 2953 report_prefix_pop(); 2954 } 2955 ept_reserved_bit_at_level_nohuge(3, 3); 2956 ept_reserved_bit_at_level_nohuge(3, 4); 2957 ept_reserved_bit_at_level_nohuge(3, 5); 2958 ept_reserved_bit_at_level_nohuge(3, 6); 2959 /* 1G alignment. */ 2960 for (i = 12; i < 29; i++) { 2961 report_prefix_pushf("reserved_bit=%d", i); 2962 ept_reserved_bit_at_level_huge(3, i); 2963 report_prefix_pop(); 2964 } 2965 ept_reserved_bit_at_level(4, 3); 2966 ept_reserved_bit_at_level(4, 4); 2967 ept_reserved_bit_at_level(4, 5); 2968 ept_reserved_bit_at_level(4, 6); 2969 ept_reserved_bit_at_level(4, 7); 2970 } 2971 2972 static void ept_access_test_ignored_bits(void) 2973 { 2974 ept_access_test_setup(); 2975 /* 2976 * Bits ignored at every level. Bits 8 and 9 (A and D) are ignored as 2977 * far as translation is concerned even if AD bits are enabled in the 2978 * EPTP. Bit 63 is ignored because "EPT-violation #VE" VM-execution 2979 * control is 0. 2980 */ 2981 ept_ignored_bit(8); 2982 ept_ignored_bit(9); 2983 ept_ignored_bit(10); 2984 ept_ignored_bit(11); 2985 ept_ignored_bit(52); 2986 ept_ignored_bit(53); 2987 ept_ignored_bit(54); 2988 ept_ignored_bit(55); 2989 ept_ignored_bit(56); 2990 ept_ignored_bit(57); 2991 ept_ignored_bit(58); 2992 ept_ignored_bit(59); 2993 ept_ignored_bit(60); 2994 ept_ignored_bit(61); 2995 ept_ignored_bit(62); 2996 ept_ignored_bit(63); 2997 } 2998 2999 static void ept_access_test_paddr_not_present_ad_disabled(void) 3000 { 3001 ept_access_test_setup(); 3002 ept_disable_ad_bits(); 3003 3004 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, EPT_VLT_RD); 3005 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, EPT_VLT_RD); 3006 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, EPT_VLT_RD); 3007 } 3008 3009 static void ept_access_test_paddr_not_present_ad_enabled(void) 3010 { 3011 u64 qual = EPT_VLT_RD | EPT_VLT_WR; 3012 3013 ept_access_test_setup(); 3014 ept_enable_ad_bits_or_skip_test(); 3015 3016 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, qual); 3017 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, qual); 3018 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, qual); 3019 } 3020 3021 static void ept_access_test_paddr_read_only_ad_disabled(void) 3022 { 3023 /* 3024 * When EPT AD bits are disabled, all accesses to guest paging 3025 * structures are reported separately as a read and (after 3026 * translation of the GPA to host physical address) a read+write 3027 * if the A/D bits have to be set. 3028 */ 3029 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 3030 3031 ept_access_test_setup(); 3032 ept_disable_ad_bits(); 3033 3034 /* Can't update A bit, so all accesses fail. */ 3035 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 3036 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 3037 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 3038 /* AD bits disabled, so only writes try to update the D bit. */ 3039 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ); 3040 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 3041 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC); 3042 /* Both A and D already set, so read-only is OK. */ 3043 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_READ); 3044 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_WRITE); 3045 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_EXEC); 3046 } 3047 3048 static void ept_access_test_paddr_read_only_ad_enabled(void) 3049 { 3050 /* 3051 * When EPT AD bits are enabled, all accesses to guest paging 3052 * structures are considered writes as far as EPT translation 3053 * is concerned. 3054 */ 3055 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 3056 3057 ept_access_test_setup(); 3058 ept_enable_ad_bits_or_skip_test(); 3059 3060 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 3061 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 3062 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 3063 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ, qual); 3064 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 3065 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC, qual); 3066 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_READ, qual); 3067 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_WRITE, qual); 3068 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_EXEC, qual); 3069 } 3070 3071 static void ept_access_test_paddr_read_write(void) 3072 { 3073 ept_access_test_setup(); 3074 /* Read-write access to paging structure. */ 3075 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_READ); 3076 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_WRITE); 3077 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_EXEC); 3078 } 3079 3080 static void ept_access_test_paddr_read_write_execute(void) 3081 { 3082 ept_access_test_setup(); 3083 /* RWX access to paging structure. */ 3084 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_READ); 3085 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_WRITE); 3086 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_EXEC); 3087 } 3088 3089 static void ept_access_test_paddr_read_execute_ad_disabled(void) 3090 { 3091 /* 3092 * When EPT AD bits are disabled, all accesses to guest paging 3093 * structures are reported separately as a read and (after 3094 * translation of the GPA to host physical address) a read+write 3095 * if the A/D bits have to be set. 3096 */ 3097 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3098 3099 ept_access_test_setup(); 3100 ept_disable_ad_bits(); 3101 3102 /* Can't update A bit, so all accesses fail. */ 3103 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3104 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3105 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3106 /* AD bits disabled, so only writes try to update the D bit. */ 3107 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ); 3108 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3109 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC); 3110 /* Both A and D already set, so read-only is OK. */ 3111 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ); 3112 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE); 3113 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC); 3114 } 3115 3116 static void ept_access_test_paddr_read_execute_ad_enabled(void) 3117 { 3118 /* 3119 * When EPT AD bits are enabled, all accesses to guest paging 3120 * structures are considered writes as far as EPT translation 3121 * is concerned. 3122 */ 3123 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3124 3125 ept_access_test_setup(); 3126 ept_enable_ad_bits_or_skip_test(); 3127 3128 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3129 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3130 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3131 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ, qual); 3132 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3133 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC, qual); 3134 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ, qual); 3135 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE, qual); 3136 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC, qual); 3137 } 3138 3139 static void ept_access_test_paddr_not_present_page_fault(void) 3140 { 3141 ept_access_test_setup(); 3142 /* 3143 * TODO: test no EPT violation as long as guest PF occurs. e.g., GPA is 3144 * page is read-only in EPT but GVA is also mapped read only in PT. 3145 * Thus guest page fault before host takes EPT violation for trying to 3146 * update A bit. 3147 */ 3148 } 3149 3150 static void ept_access_test_force_2m_page(void) 3151 { 3152 ept_access_test_setup(); 3153 3154 TEST_ASSERT_EQ(ept_2m_supported(), true); 3155 ept_allowed_at_level_mkhuge(true, 2, 0, 0, OP_READ); 3156 ept_violation_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_RA, OP_WRITE, 3157 EPT_VLT_WR | EPT_VLT_PERM_RD | 3158 EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 3159 ept_misconfig_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_WA); 3160 } 3161 3162 static bool invvpid_valid(u64 type, u64 vpid, u64 gla) 3163 { 3164 if (!is_invvpid_type_supported(type)) 3165 return false; 3166 3167 if (vpid >> 16) 3168 return false; 3169 3170 if (type != INVVPID_ALL && !vpid) 3171 return false; 3172 3173 if (type == INVVPID_ADDR && !is_canonical(gla)) 3174 return false; 3175 3176 return true; 3177 } 3178 3179 static void try_invvpid(u64 type, u64 vpid, u64 gla) 3180 { 3181 int rc; 3182 bool valid = invvpid_valid(type, vpid, gla); 3183 u64 expected = valid ? VMXERR_UNSUPPORTED_VMCS_COMPONENT 3184 : VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID; 3185 /* 3186 * Set VMX_INST_ERROR to VMXERR_UNVALID_VMCS_COMPONENT, so 3187 * that we can tell if it is updated by INVVPID. 3188 */ 3189 vmcs_read(~0); 3190 rc = __invvpid(type, vpid, gla); 3191 report(!rc == valid, "INVVPID type %ld VPID %lx GLA %lx %s", type, 3192 vpid, gla, 3193 valid ? "passes" : "fails"); 3194 report(vmcs_read(VMX_INST_ERROR) == expected, 3195 "After %s INVVPID, VMX_INST_ERR is %ld (actual %ld)", 3196 rc ? "failed" : "successful", 3197 expected, vmcs_read(VMX_INST_ERROR)); 3198 } 3199 3200 static inline unsigned long get_first_supported_invvpid_type(void) 3201 { 3202 u64 type = ffs(ept_vpid.val >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 3203 3204 __TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 3205 return type; 3206 } 3207 3208 static void ds_invvpid(void *data) 3209 { 3210 asm volatile("invvpid %0, %1" 3211 : 3212 : "m"(*(struct invvpid_operand *)data), 3213 "r"(get_first_supported_invvpid_type())); 3214 } 3215 3216 /* 3217 * The SS override is ignored in 64-bit mode, so we use an addressing 3218 * mode with %rsp as the base register to generate an implicit SS 3219 * reference. 3220 */ 3221 static void ss_invvpid(void *data) 3222 { 3223 asm volatile("sub %%rsp,%0; invvpid (%%rsp,%0,1), %1" 3224 : "+r"(data) 3225 : "r"(get_first_supported_invvpid_type())); 3226 } 3227 3228 static void invvpid_test_gp(void) 3229 { 3230 bool fault; 3231 3232 fault = test_for_exception(GP_VECTOR, &ds_invvpid, 3233 (void *)NONCANONICAL); 3234 report(fault, "INVVPID with non-canonical DS operand raises #GP"); 3235 } 3236 3237 static void invvpid_test_ss(void) 3238 { 3239 bool fault; 3240 3241 fault = test_for_exception(SS_VECTOR, &ss_invvpid, 3242 (void *)NONCANONICAL); 3243 report(fault, "INVVPID with non-canonical SS operand raises #SS"); 3244 } 3245 3246 static void invvpid_test_pf(void) 3247 { 3248 void *vpage = alloc_vpage(); 3249 bool fault; 3250 3251 fault = test_for_exception(PF_VECTOR, &ds_invvpid, vpage); 3252 report(fault, "INVVPID with unmapped operand raises #PF"); 3253 } 3254 3255 static void try_compat_invvpid(void *unused) 3256 { 3257 struct far_pointer32 fp = { 3258 .offset = (uintptr_t)&&invvpid, 3259 .selector = KERNEL_CS32, 3260 }; 3261 uintptr_t rsp; 3262 3263 asm volatile ("mov %%rsp, %0" : "=r"(rsp)); 3264 3265 TEST_ASSERT_MSG(fp.offset == (uintptr_t)&&invvpid, 3266 "Code address too high."); 3267 TEST_ASSERT_MSG(rsp == (u32)rsp, "Stack address too high."); 3268 3269 asm goto ("lcall *%0" : : "m" (fp) : "rax" : invvpid); 3270 return; 3271 invvpid: 3272 asm volatile (".code32;" 3273 "invvpid (%eax), %eax;" 3274 "lret;" 3275 ".code64"); 3276 __builtin_unreachable(); 3277 } 3278 3279 static void invvpid_test_compatibility_mode(void) 3280 { 3281 bool fault; 3282 3283 fault = test_for_exception(UD_VECTOR, &try_compat_invvpid, NULL); 3284 report(fault, "Compatibility mode INVVPID raises #UD"); 3285 } 3286 3287 static void invvpid_test_not_in_vmx_operation(void) 3288 { 3289 bool fault; 3290 3291 TEST_ASSERT(!vmx_off()); 3292 fault = test_for_exception(UD_VECTOR, &ds_invvpid, NULL); 3293 report(fault, "INVVPID outside of VMX operation raises #UD"); 3294 TEST_ASSERT(!vmx_on()); 3295 } 3296 3297 /* 3298 * This does not test real-address mode, virtual-8086 mode, protected mode, 3299 * or CPL > 0. 3300 */ 3301 static void invvpid_test(void) 3302 { 3303 int i; 3304 unsigned types = 0; 3305 unsigned type; 3306 3307 if (!is_vpid_supported()) 3308 test_skip("VPID not supported"); 3309 3310 if (!is_invvpid_supported()) 3311 test_skip("INVVPID not supported.\n"); 3312 3313 if (is_invvpid_type_supported(INVVPID_ADDR)) 3314 types |= 1u << INVVPID_ADDR; 3315 if (is_invvpid_type_supported(INVVPID_CONTEXT_GLOBAL)) 3316 types |= 1u << INVVPID_CONTEXT_GLOBAL; 3317 if (is_invvpid_type_supported(INVVPID_ALL)) 3318 types |= 1u << INVVPID_ALL; 3319 if (is_invvpid_type_supported(INVVPID_CONTEXT_LOCAL)) 3320 types |= 1u << INVVPID_CONTEXT_LOCAL; 3321 3322 if (!types) 3323 test_skip("No INVVPID types supported.\n"); 3324 3325 for (i = -127; i < 128; i++) 3326 try_invvpid(i, 0xffff, 0); 3327 3328 /* 3329 * VPID must not be more than 16 bits. 3330 */ 3331 for (i = 0; i < 64; i++) 3332 for (type = 0; type < 4; type++) 3333 if (types & (1u << type)) 3334 try_invvpid(type, 1ul << i, 0); 3335 3336 /* 3337 * VPID must not be zero, except for "all contexts." 3338 */ 3339 for (type = 0; type < 4; type++) 3340 if (types & (1u << type)) 3341 try_invvpid(type, 0, 0); 3342 3343 /* 3344 * The gla operand is only validated for single-address INVVPID. 3345 */ 3346 if (types & (1u << INVVPID_ADDR)) 3347 try_invvpid(INVVPID_ADDR, 0xffff, NONCANONICAL); 3348 3349 invvpid_test_gp(); 3350 invvpid_test_ss(); 3351 invvpid_test_pf(); 3352 invvpid_test_compatibility_mode(); 3353 invvpid_test_not_in_vmx_operation(); 3354 } 3355 3356 /* 3357 * Test for early VMLAUNCH failure. Returns true if VMLAUNCH makes it 3358 * at least as far as the guest-state checks. Returns false if the 3359 * VMLAUNCH fails early and execution falls through to the next 3360 * instruction. 3361 */ 3362 static bool vmlaunch_succeeds(void) 3363 { 3364 u32 exit_reason; 3365 3366 /* 3367 * Indirectly set VMX_INST_ERR to 12 ("VMREAD/VMWRITE from/to 3368 * unsupported VMCS component"). The caller can then check 3369 * to see if a failed VM-entry sets VMX_INST_ERR as expected. 3370 */ 3371 vmcs_write(~0u, 0); 3372 3373 vmcs_write(HOST_RIP, (uintptr_t)&&success); 3374 __asm__ __volatile__ goto ("vmwrite %%rsp, %0; vmlaunch" 3375 : 3376 : "r" ((u64)HOST_RSP) 3377 : "cc", "memory" 3378 : success); 3379 return false; 3380 success: 3381 exit_reason = vmcs_read(EXI_REASON); 3382 TEST_ASSERT(exit_reason == (VMX_FAIL_STATE | VMX_ENTRY_FAILURE) || 3383 exit_reason == (VMX_FAIL_MSR | VMX_ENTRY_FAILURE)); 3384 return true; 3385 } 3386 3387 /* 3388 * Try to launch the current VMCS. 3389 */ 3390 static void test_vmx_vmlaunch(u32 xerror) 3391 { 3392 bool success = vmlaunch_succeeds(); 3393 u32 vmx_inst_err; 3394 3395 report(success == !xerror, "vmlaunch %s", 3396 !xerror ? "succeeds" : "fails"); 3397 if (!success && xerror) { 3398 vmx_inst_err = vmcs_read(VMX_INST_ERROR); 3399 report(vmx_inst_err == xerror, 3400 "VMX inst error is %d (actual %d)", xerror, 3401 vmx_inst_err); 3402 } 3403 } 3404 3405 /* 3406 * Try to launch the current VMCS, and expect one of two possible 3407 * errors (or success) codes. 3408 */ 3409 static void test_vmx_vmlaunch2(u32 xerror1, u32 xerror2) 3410 { 3411 bool success = vmlaunch_succeeds(); 3412 u32 vmx_inst_err; 3413 3414 if (!xerror1 == !xerror2) 3415 report(success == !xerror1, "vmlaunch %s", 3416 !xerror1 ? "succeeds" : "fails"); 3417 3418 if (!success && (xerror1 || xerror2)) { 3419 vmx_inst_err = vmcs_read(VMX_INST_ERROR); 3420 report(vmx_inst_err == xerror1 || vmx_inst_err == xerror2, 3421 "VMX inst error is %d or %d (actual %d)", xerror1, 3422 xerror2, vmx_inst_err); 3423 } 3424 } 3425 3426 static void test_vmx_invalid_controls(void) 3427 { 3428 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_CONTROL_FIELD); 3429 } 3430 3431 static void test_vmx_valid_controls(void) 3432 { 3433 test_vmx_vmlaunch(0); 3434 } 3435 3436 /* 3437 * Test a particular value of a VM-execution control bit, if the value 3438 * is required or if the value is zero. 3439 */ 3440 static void test_rsvd_ctl_bit_value(const char *name, union vmx_ctrl_msr msr, 3441 enum Encoding encoding, unsigned bit, 3442 unsigned val) 3443 { 3444 u32 mask = 1u << bit; 3445 bool expected; 3446 u32 controls; 3447 3448 if (msr.set & mask) 3449 TEST_ASSERT(msr.clr & mask); 3450 3451 /* 3452 * We can't arbitrarily turn on a control bit, because it may 3453 * introduce dependencies on other VMCS fields. So, we only 3454 * test turning on bits that have a required setting. 3455 */ 3456 if (val && (msr.clr & mask) && !(msr.set & mask)) 3457 return; 3458 3459 report_prefix_pushf("%s %s bit %d", 3460 val ? "Set" : "Clear", name, bit); 3461 3462 controls = vmcs_read(encoding); 3463 if (val) { 3464 vmcs_write(encoding, msr.set | mask); 3465 expected = (msr.clr & mask); 3466 } else { 3467 vmcs_write(encoding, msr.set & ~mask); 3468 expected = !(msr.set & mask); 3469 } 3470 if (expected) 3471 test_vmx_valid_controls(); 3472 else 3473 test_vmx_invalid_controls(); 3474 vmcs_write(encoding, controls); 3475 report_prefix_pop(); 3476 } 3477 3478 /* 3479 * Test reserved values of a VM-execution control bit, based on the 3480 * allowed bit settings from the corresponding VMX capability MSR. 3481 */ 3482 static void test_rsvd_ctl_bit(const char *name, union vmx_ctrl_msr msr, 3483 enum Encoding encoding, unsigned bit) 3484 { 3485 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 0); 3486 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 1); 3487 } 3488 3489 /* 3490 * Reserved bits in the pin-based VM-execution controls must be set 3491 * properly. Software may consult the VMX capability MSRs to determine 3492 * the proper settings. 3493 * [Intel SDM] 3494 */ 3495 static void test_pin_based_ctls(void) 3496 { 3497 unsigned bit; 3498 3499 printf("%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PIN" : 3500 "MSR_IA32_VMX_PINBASED_CTLS", ctrl_pin_rev.val); 3501 for (bit = 0; bit < 32; bit++) 3502 test_rsvd_ctl_bit("pin-based controls", 3503 ctrl_pin_rev, PIN_CONTROLS, bit); 3504 } 3505 3506 /* 3507 * Reserved bits in the primary processor-based VM-execution controls 3508 * must be set properly. Software may consult the VMX capability MSRs 3509 * to determine the proper settings. 3510 * [Intel SDM] 3511 */ 3512 static void test_primary_processor_based_ctls(void) 3513 { 3514 unsigned bit; 3515 3516 printf("\n%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PROC" : 3517 "MSR_IA32_VMX_PROCBASED_CTLS", ctrl_cpu_rev[0].val); 3518 for (bit = 0; bit < 32; bit++) 3519 test_rsvd_ctl_bit("primary processor-based controls", 3520 ctrl_cpu_rev[0], CPU_EXEC_CTRL0, bit); 3521 } 3522 3523 /* 3524 * If the "activate secondary controls" primary processor-based 3525 * VM-execution control is 1, reserved bits in the secondary 3526 * processor-based VM-execution controls must be cleared. Software may 3527 * consult the VMX capability MSRs to determine which bits are 3528 * reserved. 3529 * If the "activate secondary controls" primary processor-based 3530 * VM-execution control is 0 (or if the processor does not support the 3531 * 1-setting of that control), no checks are performed on the 3532 * secondary processor-based VM-execution controls. 3533 * [Intel SDM] 3534 */ 3535 static void test_secondary_processor_based_ctls(void) 3536 { 3537 u32 primary; 3538 u32 secondary; 3539 unsigned bit; 3540 3541 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) 3542 return; 3543 3544 primary = vmcs_read(CPU_EXEC_CTRL0); 3545 secondary = vmcs_read(CPU_EXEC_CTRL1); 3546 3547 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3548 printf("\nMSR_IA32_VMX_PROCBASED_CTLS2: %lx\n", ctrl_cpu_rev[1].val); 3549 for (bit = 0; bit < 32; bit++) 3550 test_rsvd_ctl_bit("secondary processor-based controls", 3551 ctrl_cpu_rev[1], CPU_EXEC_CTRL1, bit); 3552 3553 /* 3554 * When the "activate secondary controls" VM-execution control 3555 * is clear, there are no checks on the secondary controls. 3556 */ 3557 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3558 vmcs_write(CPU_EXEC_CTRL1, ~0); 3559 report(vmlaunch_succeeds(), 3560 "Secondary processor-based controls ignored"); 3561 vmcs_write(CPU_EXEC_CTRL1, secondary); 3562 vmcs_write(CPU_EXEC_CTRL0, primary); 3563 } 3564 3565 static void try_cr3_target_count(unsigned i, unsigned max) 3566 { 3567 report_prefix_pushf("CR3 target count 0x%x", i); 3568 vmcs_write(CR3_TARGET_COUNT, i); 3569 if (i <= max) 3570 test_vmx_valid_controls(); 3571 else 3572 test_vmx_invalid_controls(); 3573 report_prefix_pop(); 3574 } 3575 3576 /* 3577 * The CR3-target count must not be greater than 4. Future processors 3578 * may support a different number of CR3-target values. Software 3579 * should read the VMX capability MSR IA32_VMX_MISC to determine the 3580 * number of values supported. 3581 * [Intel SDM] 3582 */ 3583 static void test_cr3_targets(void) 3584 { 3585 unsigned supported_targets = (rdmsr(MSR_IA32_VMX_MISC) >> 16) & 0x1ff; 3586 u32 cr3_targets = vmcs_read(CR3_TARGET_COUNT); 3587 unsigned i; 3588 3589 printf("\nSupported CR3 targets: %d\n", supported_targets); 3590 TEST_ASSERT(supported_targets <= 256); 3591 3592 try_cr3_target_count(-1u, supported_targets); 3593 try_cr3_target_count(0x80000000, supported_targets); 3594 try_cr3_target_count(0x7fffffff, supported_targets); 3595 for (i = 0; i <= supported_targets + 1; i++) 3596 try_cr3_target_count(i, supported_targets); 3597 vmcs_write(CR3_TARGET_COUNT, cr3_targets); 3598 3599 /* VMWRITE to nonexistent target fields should fail. */ 3600 for (i = supported_targets; i < 256; i++) 3601 TEST_ASSERT(vmcs_write(CR3_TARGET_0 + i*2, 0)); 3602 } 3603 3604 /* 3605 * Test a particular address setting in the VMCS 3606 */ 3607 static void test_vmcs_addr(const char *name, 3608 enum Encoding encoding, 3609 u64 align, 3610 bool ignored, 3611 bool skip_beyond_mapped_ram, 3612 u64 addr) 3613 { 3614 report_prefix_pushf("%s = %lx", name, addr); 3615 vmcs_write(encoding, addr); 3616 if (skip_beyond_mapped_ram && 3617 addr > fwcfg_get_u64(FW_CFG_RAM_SIZE) - align && 3618 addr < (1ul << cpuid_maxphyaddr())) 3619 printf("Skipping physical address beyond mapped RAM\n"); 3620 else if (ignored || (IS_ALIGNED(addr, align) && 3621 addr < (1ul << cpuid_maxphyaddr()))) 3622 test_vmx_valid_controls(); 3623 else 3624 test_vmx_invalid_controls(); 3625 report_prefix_pop(); 3626 } 3627 3628 /* 3629 * Test interesting values for a VMCS address 3630 */ 3631 static void test_vmcs_addr_values(const char *name, 3632 enum Encoding encoding, 3633 u64 align, 3634 bool ignored, 3635 bool skip_beyond_mapped_ram, 3636 u32 bit_start, u32 bit_end) 3637 { 3638 unsigned i; 3639 u64 orig_val = vmcs_read(encoding); 3640 3641 for (i = bit_start; i <= bit_end; i++) 3642 test_vmcs_addr(name, encoding, align, ignored, 3643 skip_beyond_mapped_ram, 1ul << i); 3644 3645 test_vmcs_addr(name, encoding, align, ignored, 3646 skip_beyond_mapped_ram, PAGE_SIZE - 1); 3647 test_vmcs_addr(name, encoding, align, ignored, 3648 skip_beyond_mapped_ram, PAGE_SIZE); 3649 test_vmcs_addr(name, encoding, align, ignored, 3650 skip_beyond_mapped_ram, 3651 (1ul << cpuid_maxphyaddr()) - PAGE_SIZE); 3652 test_vmcs_addr(name, encoding, align, ignored, 3653 skip_beyond_mapped_ram, -1ul); 3654 3655 vmcs_write(encoding, orig_val); 3656 } 3657 3658 /* 3659 * Test a physical address reference in the VMCS, when the corresponding 3660 * feature is enabled and when the corresponding feature is disabled. 3661 */ 3662 static void test_vmcs_addr_reference(u32 control_bit, enum Encoding field, 3663 const char *field_name, 3664 const char *control_name, u64 align, 3665 bool skip_beyond_mapped_ram, 3666 bool control_primary) 3667 { 3668 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 3669 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 3670 u64 page_addr; 3671 3672 if (control_primary) { 3673 if (!(ctrl_cpu_rev[0].clr & control_bit)) 3674 return; 3675 } else { 3676 if (!(ctrl_cpu_rev[1].clr & control_bit)) 3677 return; 3678 } 3679 3680 page_addr = vmcs_read(field); 3681 3682 report_prefix_pushf("%s enabled", control_name); 3683 if (control_primary) { 3684 vmcs_write(CPU_EXEC_CTRL0, primary | control_bit); 3685 } else { 3686 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3687 vmcs_write(CPU_EXEC_CTRL1, secondary | control_bit); 3688 } 3689 3690 test_vmcs_addr_values(field_name, field, align, false, 3691 skip_beyond_mapped_ram, 0, 63); 3692 report_prefix_pop(); 3693 3694 report_prefix_pushf("%s disabled", control_name); 3695 if (control_primary) { 3696 vmcs_write(CPU_EXEC_CTRL0, primary & ~control_bit); 3697 } else { 3698 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3699 vmcs_write(CPU_EXEC_CTRL1, secondary & ~control_bit); 3700 } 3701 3702 test_vmcs_addr_values(field_name, field, align, true, false, 0, 63); 3703 report_prefix_pop(); 3704 3705 vmcs_write(field, page_addr); 3706 vmcs_write(CPU_EXEC_CTRL0, primary); 3707 vmcs_write(CPU_EXEC_CTRL1, secondary); 3708 } 3709 3710 /* 3711 * If the "use I/O bitmaps" VM-execution control is 1, bits 11:0 of 3712 * each I/O-bitmap address must be 0. Neither address should set any 3713 * bits beyond the processor's physical-address width. 3714 * [Intel SDM] 3715 */ 3716 static void test_io_bitmaps(void) 3717 { 3718 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_A, 3719 "I/O bitmap A", "Use I/O bitmaps", 3720 PAGE_SIZE, false, true); 3721 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_B, 3722 "I/O bitmap B", "Use I/O bitmaps", 3723 PAGE_SIZE, false, true); 3724 } 3725 3726 /* 3727 * If the "use MSR bitmaps" VM-execution control is 1, bits 11:0 of 3728 * the MSR-bitmap address must be 0. The address should not set any 3729 * bits beyond the processor's physical-address width. 3730 * [Intel SDM] 3731 */ 3732 static void test_msr_bitmap(void) 3733 { 3734 test_vmcs_addr_reference(CPU_MSR_BITMAP, MSR_BITMAP, 3735 "MSR bitmap", "Use MSR bitmaps", 3736 PAGE_SIZE, false, true); 3737 } 3738 3739 /* 3740 * If the "use TPR shadow" VM-execution control is 1, the virtual-APIC 3741 * address must satisfy the following checks: 3742 * - Bits 11:0 of the address must be 0. 3743 * - The address should not set any bits beyond the processor's 3744 * physical-address width. 3745 * [Intel SDM] 3746 */ 3747 static void test_apic_virt_addr(void) 3748 { 3749 /* 3750 * Ensure the processor will never use the virtual-APIC page, since 3751 * we will point it to invalid RAM. Otherwise KVM is puzzled about 3752 * what we're trying to achieve and fails vmentry. 3753 */ 3754 u32 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 3755 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0 | CPU_CR8_LOAD | CPU_CR8_STORE); 3756 test_vmcs_addr_reference(CPU_TPR_SHADOW, APIC_VIRT_ADDR, 3757 "virtual-APIC address", "Use TPR shadow", 3758 PAGE_SIZE, false, true); 3759 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 3760 } 3761 3762 /* 3763 * If the "virtualize APIC-accesses" VM-execution control is 1, the 3764 * APIC-access address must satisfy the following checks: 3765 * - Bits 11:0 of the address must be 0. 3766 * - The address should not set any bits beyond the processor's 3767 * physical-address width. 3768 * [Intel SDM] 3769 */ 3770 static void test_apic_access_addr(void) 3771 { 3772 void *apic_access_page = alloc_page(); 3773 3774 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_page)); 3775 3776 test_vmcs_addr_reference(CPU_VIRT_APIC_ACCESSES, APIC_ACCS_ADDR, 3777 "APIC-access address", 3778 "virtualize APIC-accesses", PAGE_SIZE, 3779 true, false); 3780 } 3781 3782 static bool set_bit_pattern(u8 mask, u32 *secondary) 3783 { 3784 u8 i; 3785 bool flag = false; 3786 u32 test_bits[3] = { 3787 CPU_VIRT_X2APIC, 3788 CPU_APIC_REG_VIRT, 3789 CPU_VINTD 3790 }; 3791 3792 for (i = 0; i < ARRAY_SIZE(test_bits); i++) { 3793 if ((mask & (1u << i)) && 3794 (ctrl_cpu_rev[1].clr & test_bits[i])) { 3795 *secondary |= test_bits[i]; 3796 flag = true; 3797 } 3798 } 3799 3800 return (flag); 3801 } 3802 3803 /* 3804 * If the "use TPR shadow" VM-execution control is 0, the following 3805 * VM-execution controls must also be 0: 3806 * - virtualize x2APIC mode 3807 * - APIC-register virtualization 3808 * - virtual-interrupt delivery 3809 * [Intel SDM] 3810 * 3811 * 2. If the "virtualize x2APIC mode" VM-execution control is 1, the 3812 * "virtualize APIC accesses" VM-execution control must be 0. 3813 * [Intel SDM] 3814 */ 3815 static void test_apic_virtual_ctls(void) 3816 { 3817 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3818 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3819 u32 primary = saved_primary; 3820 u32 secondary = saved_secondary; 3821 bool is_ctrl_valid = false; 3822 char str[10] = "disabled"; 3823 u8 i = 0, j; 3824 3825 /* 3826 * First test 3827 */ 3828 if (!((ctrl_cpu_rev[0].clr & (CPU_SECONDARY | CPU_TPR_SHADOW)) == 3829 (CPU_SECONDARY | CPU_TPR_SHADOW))) 3830 return; 3831 3832 primary |= CPU_SECONDARY; 3833 primary &= ~CPU_TPR_SHADOW; 3834 vmcs_write(CPU_EXEC_CTRL0, primary); 3835 3836 while (1) { 3837 for (j = 1; j < 8; j++) { 3838 secondary &= ~(CPU_VIRT_X2APIC | CPU_APIC_REG_VIRT | CPU_VINTD); 3839 if (primary & CPU_TPR_SHADOW) { 3840 is_ctrl_valid = true; 3841 } else { 3842 if (! set_bit_pattern(j, &secondary)) 3843 is_ctrl_valid = true; 3844 else 3845 is_ctrl_valid = false; 3846 } 3847 3848 vmcs_write(CPU_EXEC_CTRL1, secondary); 3849 report_prefix_pushf("Use TPR shadow %s, virtualize x2APIC mode %s, APIC-register virtualization %s, virtual-interrupt delivery %s", 3850 str, (secondary & CPU_VIRT_X2APIC) ? "enabled" : "disabled", (secondary & CPU_APIC_REG_VIRT) ? "enabled" : "disabled", (secondary & CPU_VINTD) ? "enabled" : "disabled"); 3851 if (is_ctrl_valid) 3852 test_vmx_valid_controls(); 3853 else 3854 test_vmx_invalid_controls(); 3855 report_prefix_pop(); 3856 } 3857 3858 if (i == 1) 3859 break; 3860 i++; 3861 3862 primary |= CPU_TPR_SHADOW; 3863 vmcs_write(CPU_EXEC_CTRL0, primary); 3864 strcpy(str, "enabled"); 3865 } 3866 3867 /* 3868 * Second test 3869 */ 3870 u32 apic_virt_ctls = (CPU_VIRT_X2APIC | CPU_VIRT_APIC_ACCESSES); 3871 3872 primary = saved_primary; 3873 secondary = saved_secondary; 3874 if (!((ctrl_cpu_rev[1].clr & apic_virt_ctls) == apic_virt_ctls)) 3875 return; 3876 3877 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3878 secondary &= ~CPU_VIRT_APIC_ACCESSES; 3879 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_X2APIC); 3880 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access disabled"); 3881 test_vmx_valid_controls(); 3882 report_prefix_pop(); 3883 3884 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_APIC_ACCESSES); 3885 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access enabled"); 3886 test_vmx_valid_controls(); 3887 report_prefix_pop(); 3888 3889 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_X2APIC); 3890 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access enabled"); 3891 test_vmx_invalid_controls(); 3892 report_prefix_pop(); 3893 3894 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_APIC_ACCESSES); 3895 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access disabled"); 3896 test_vmx_valid_controls(); 3897 report_prefix_pop(); 3898 3899 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3900 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3901 } 3902 3903 /* 3904 * If the "virtual-interrupt delivery" VM-execution control is 1, the 3905 * "external-interrupt exiting" VM-execution control must be 1. 3906 * [Intel SDM] 3907 */ 3908 static void test_virtual_intr_ctls(void) 3909 { 3910 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3911 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3912 u32 saved_pin = vmcs_read(PIN_CONTROLS); 3913 u32 primary = saved_primary; 3914 u32 secondary = saved_secondary; 3915 u32 pin = saved_pin; 3916 3917 if (!((ctrl_cpu_rev[1].clr & CPU_VINTD) && 3918 (ctrl_pin_rev.clr & PIN_EXTINT))) 3919 return; 3920 3921 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 3922 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VINTD); 3923 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 3924 report_prefix_pushf("Virtualize interrupt-delivery disabled; external-interrupt exiting disabled"); 3925 test_vmx_valid_controls(); 3926 report_prefix_pop(); 3927 3928 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VINTD); 3929 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 3930 test_vmx_invalid_controls(); 3931 report_prefix_pop(); 3932 3933 vmcs_write(PIN_CONTROLS, pin | PIN_EXTINT); 3934 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting enabled"); 3935 test_vmx_valid_controls(); 3936 report_prefix_pop(); 3937 3938 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 3939 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 3940 test_vmx_invalid_controls(); 3941 report_prefix_pop(); 3942 3943 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3944 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3945 vmcs_write(PIN_CONTROLS, saved_pin); 3946 } 3947 3948 static void test_pi_desc_addr(u64 addr, bool is_ctrl_valid) 3949 { 3950 vmcs_write(POSTED_INTR_DESC_ADDR, addr); 3951 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-descriptor-address 0x%lx", addr); 3952 if (is_ctrl_valid) 3953 test_vmx_valid_controls(); 3954 else 3955 test_vmx_invalid_controls(); 3956 report_prefix_pop(); 3957 } 3958 3959 /* 3960 * If the "process posted interrupts" VM-execution control is 1, the 3961 * following must be true: 3962 * 3963 * - The "virtual-interrupt delivery" VM-execution control is 1. 3964 * - The "acknowledge interrupt on exit" VM-exit control is 1. 3965 * - The posted-interrupt notification vector has a value in the 3966 * - range 0 - 255 (bits 15:8 are all 0). 3967 * - Bits 5:0 of the posted-interrupt descriptor address are all 0. 3968 * - The posted-interrupt descriptor address does not set any bits 3969 * beyond the processor's physical-address width. 3970 * [Intel SDM] 3971 */ 3972 static void test_posted_intr(void) 3973 { 3974 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3975 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3976 u32 saved_pin = vmcs_read(PIN_CONTROLS); 3977 u32 exit_ctl_saved = vmcs_read(EXI_CONTROLS); 3978 u32 primary = saved_primary; 3979 u32 secondary = saved_secondary; 3980 u32 pin = saved_pin; 3981 u32 exit_ctl = exit_ctl_saved; 3982 u16 vec; 3983 int i; 3984 3985 if (!((ctrl_pin_rev.clr & PIN_POST_INTR) && 3986 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 3987 (ctrl_exit_rev.clr & EXI_INTA))) 3988 return; 3989 3990 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 3991 3992 /* 3993 * Test virtual-interrupt-delivery and acknowledge-interrupt-on-exit 3994 */ 3995 pin |= PIN_POST_INTR; 3996 vmcs_write(PIN_CONTROLS, pin); 3997 secondary &= ~CPU_VINTD; 3998 vmcs_write(CPU_EXEC_CTRL1, secondary); 3999 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled"); 4000 test_vmx_invalid_controls(); 4001 report_prefix_pop(); 4002 4003 secondary |= CPU_VINTD; 4004 vmcs_write(CPU_EXEC_CTRL1, secondary); 4005 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled"); 4006 test_vmx_invalid_controls(); 4007 report_prefix_pop(); 4008 4009 exit_ctl &= ~EXI_INTA; 4010 vmcs_write(EXI_CONTROLS, exit_ctl); 4011 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit disabled"); 4012 test_vmx_invalid_controls(); 4013 report_prefix_pop(); 4014 4015 exit_ctl |= EXI_INTA; 4016 vmcs_write(EXI_CONTROLS, exit_ctl); 4017 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 4018 test_vmx_valid_controls(); 4019 report_prefix_pop(); 4020 4021 secondary &= ~CPU_VINTD; 4022 vmcs_write(CPU_EXEC_CTRL1, secondary); 4023 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled; acknowledge-interrupt-on-exit enabled"); 4024 test_vmx_invalid_controls(); 4025 report_prefix_pop(); 4026 4027 secondary |= CPU_VINTD; 4028 vmcs_write(CPU_EXEC_CTRL1, secondary); 4029 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 4030 test_vmx_valid_controls(); 4031 report_prefix_pop(); 4032 4033 /* 4034 * Test posted-interrupt notification vector 4035 */ 4036 for (i = 0; i < 8; i++) { 4037 vec = (1ul << i); 4038 vmcs_write(PINV, vec); 4039 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 4040 test_vmx_valid_controls(); 4041 report_prefix_pop(); 4042 } 4043 for (i = 8; i < 16; i++) { 4044 vec = (1ul << i); 4045 vmcs_write(PINV, vec); 4046 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 4047 test_vmx_invalid_controls(); 4048 report_prefix_pop(); 4049 } 4050 4051 vec &= ~(0xff << 8); 4052 vmcs_write(PINV, vec); 4053 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 4054 test_vmx_valid_controls(); 4055 report_prefix_pop(); 4056 4057 /* 4058 * Test posted-interrupt descriptor addresss 4059 */ 4060 for (i = 0; i < 6; i++) { 4061 test_pi_desc_addr(1ul << i, false); 4062 } 4063 4064 test_pi_desc_addr(0xf0, false); 4065 test_pi_desc_addr(0xff, false); 4066 test_pi_desc_addr(0x0f, false); 4067 test_pi_desc_addr(0x8000, true); 4068 test_pi_desc_addr(0x00, true); 4069 test_pi_desc_addr(0xc000, true); 4070 4071 test_vmcs_addr_values("process-posted interrupts", 4072 POSTED_INTR_DESC_ADDR, 64, 4073 false, false, 0, 63); 4074 4075 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 4076 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 4077 vmcs_write(PIN_CONTROLS, saved_pin); 4078 } 4079 4080 static void test_apic_ctls(void) 4081 { 4082 test_apic_virt_addr(); 4083 test_apic_access_addr(); 4084 test_apic_virtual_ctls(); 4085 test_virtual_intr_ctls(); 4086 test_posted_intr(); 4087 } 4088 4089 /* 4090 * If the "enable VPID" VM-execution control is 1, the value of the 4091 * of the VPID VM-execution control field must not be 0000H. 4092 * [Intel SDM] 4093 */ 4094 static void test_vpid(void) 4095 { 4096 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 4097 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 4098 u16 vpid = 0x0000; 4099 int i; 4100 4101 if (!is_vpid_supported()) { 4102 printf("Secondary controls and/or VPID not supported\n"); 4103 return; 4104 } 4105 4106 vmcs_write(CPU_EXEC_CTRL0, saved_primary | CPU_SECONDARY); 4107 vmcs_write(CPU_EXEC_CTRL1, saved_secondary & ~CPU_VPID); 4108 vmcs_write(VPID, vpid); 4109 report_prefix_pushf("VPID disabled; VPID value %x", vpid); 4110 test_vmx_valid_controls(); 4111 report_prefix_pop(); 4112 4113 vmcs_write(CPU_EXEC_CTRL1, saved_secondary | CPU_VPID); 4114 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 4115 test_vmx_invalid_controls(); 4116 report_prefix_pop(); 4117 4118 for (i = 0; i < 16; i++) { 4119 vpid = (short)1 << i;; 4120 vmcs_write(VPID, vpid); 4121 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 4122 test_vmx_valid_controls(); 4123 report_prefix_pop(); 4124 } 4125 4126 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 4127 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 4128 } 4129 4130 static void set_vtpr(unsigned vtpr) 4131 { 4132 *(u32 *)phys_to_virt(vmcs_read(APIC_VIRT_ADDR) + APIC_TASKPRI) = vtpr; 4133 } 4134 4135 static void try_tpr_threshold_and_vtpr(unsigned threshold, unsigned vtpr) 4136 { 4137 bool valid = true; 4138 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4139 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4140 4141 if ((primary & CPU_TPR_SHADOW) && 4142 (!(primary & CPU_SECONDARY) || 4143 !(secondary & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 4144 valid = (threshold & 0xf) <= ((vtpr >> 4) & 0xf); 4145 4146 set_vtpr(vtpr); 4147 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0x%x", 4148 threshold, (vtpr >> 4) & 0xf); 4149 if (valid) 4150 test_vmx_valid_controls(); 4151 else 4152 test_vmx_invalid_controls(); 4153 report_prefix_pop(); 4154 } 4155 4156 static void test_invalid_event_injection(void) 4157 { 4158 u32 ent_intr_info_save = vmcs_read(ENT_INTR_INFO); 4159 u32 ent_intr_error_save = vmcs_read(ENT_INTR_ERROR); 4160 u32 ent_inst_len_save = vmcs_read(ENT_INST_LEN); 4161 u32 primary_save = vmcs_read(CPU_EXEC_CTRL0); 4162 u32 secondary_save = vmcs_read(CPU_EXEC_CTRL1); 4163 u64 guest_cr0_save = vmcs_read(GUEST_CR0); 4164 u32 ent_intr_info_base = INTR_INFO_VALID_MASK; 4165 u32 ent_intr_info, ent_intr_err, ent_intr_len; 4166 u32 cnt; 4167 4168 /* Setup */ 4169 report_prefix_push("invalid event injection"); 4170 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4171 vmcs_write(ENT_INST_LEN, 0x00000001); 4172 4173 /* The field's interruption type is not set to a reserved value. */ 4174 ent_intr_info = ent_intr_info_base | INTR_TYPE_RESERVED | DE_VECTOR; 4175 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4176 "RESERVED interruption type invalid [-]", 4177 ent_intr_info); 4178 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4179 test_vmx_invalid_controls(); 4180 report_prefix_pop(); 4181 4182 ent_intr_info = ent_intr_info_base | INTR_TYPE_EXT_INTR | 4183 DE_VECTOR; 4184 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4185 "RESERVED interruption type invalid [+]", 4186 ent_intr_info); 4187 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4188 test_vmx_valid_controls(); 4189 report_prefix_pop(); 4190 4191 /* If the interruption type is other event, the vector is 0. */ 4192 ent_intr_info = ent_intr_info_base | INTR_TYPE_OTHER_EVENT | DB_VECTOR; 4193 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4194 "(OTHER EVENT && vector != 0) invalid [-]", 4195 ent_intr_info); 4196 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4197 test_vmx_invalid_controls(); 4198 report_prefix_pop(); 4199 4200 /* If the interruption type is NMI, the vector is 2 (negative case). */ 4201 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | DE_VECTOR; 4202 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4203 "(NMI && vector != 2) invalid [-]", ent_intr_info); 4204 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4205 test_vmx_invalid_controls(); 4206 report_prefix_pop(); 4207 4208 /* If the interruption type is NMI, the vector is 2 (positive case). */ 4209 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | NMI_VECTOR; 4210 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4211 "(NMI && vector == 2) valid [+]", ent_intr_info); 4212 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4213 test_vmx_valid_controls(); 4214 report_prefix_pop(); 4215 4216 /* 4217 * If the interruption type 4218 * is HW exception, the vector is at most 31. 4219 */ 4220 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 0x20; 4221 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4222 "(HW exception && vector > 31) invalid [-]", 4223 ent_intr_info); 4224 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4225 test_vmx_invalid_controls(); 4226 report_prefix_pop(); 4227 4228 /* 4229 * deliver-error-code is 1 iff either 4230 * (a) the "unrestricted guest" VM-execution control is 0 4231 * (b) CR0.PE is set. 4232 */ 4233 4234 /* Assert that unrestricted guest is disabled or unsupported */ 4235 assert(!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 4236 !(secondary_save & CPU_URG)); 4237 4238 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4239 GP_VECTOR; 4240 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4241 "error code <-> (!URG || prot_mode) [-]", 4242 ent_intr_info); 4243 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4244 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4245 test_vmx_invalid_controls(); 4246 report_prefix_pop(); 4247 4248 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4249 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4250 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4251 "error code <-> (!URG || prot_mode) [+]", 4252 ent_intr_info); 4253 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4254 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4255 test_vmx_valid_controls(); 4256 report_prefix_pop(); 4257 4258 if (enable_unrestricted_guest(false)) 4259 goto skip_unrestricted_guest; 4260 4261 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4262 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4263 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4264 "error code <-> (!URG || prot_mode) [-]", 4265 ent_intr_info); 4266 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4267 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4268 test_vmx_invalid_controls(); 4269 report_prefix_pop(); 4270 4271 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4272 GP_VECTOR; 4273 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4274 "error code <-> (!URG || prot_mode) [-]", 4275 ent_intr_info); 4276 vmcs_write(GUEST_CR0, guest_cr0_save | X86_CR0_PE); 4277 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4278 test_vmx_invalid_controls(); 4279 report_prefix_pop(); 4280 4281 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4282 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4283 4284 skip_unrestricted_guest: 4285 vmcs_write(GUEST_CR0, guest_cr0_save); 4286 4287 /* deliver-error-code is 1 iff the interruption type is HW exception */ 4288 report_prefix_push("error code <-> HW exception"); 4289 for (cnt = 0; cnt < 8; cnt++) { 4290 u32 exception_type_mask = cnt << 8; 4291 u32 deliver_error_code_mask = 4292 exception_type_mask != INTR_TYPE_HARD_EXCEPTION ? 4293 INTR_INFO_DELIVER_CODE_MASK : 0; 4294 4295 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4296 exception_type_mask | GP_VECTOR; 4297 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4298 ent_intr_info); 4299 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4300 test_vmx_invalid_controls(); 4301 report_prefix_pop(); 4302 } 4303 report_prefix_pop(); 4304 4305 /* 4306 * deliver-error-code is 1 iff the the vector 4307 * indicates an exception that would normally deliver an error code 4308 */ 4309 report_prefix_push("error code <-> vector delivers error code"); 4310 for (cnt = 0; cnt < 32; cnt++) { 4311 bool has_error_code = false; 4312 u32 deliver_error_code_mask; 4313 4314 switch (cnt) { 4315 case DF_VECTOR: 4316 case TS_VECTOR: 4317 case NP_VECTOR: 4318 case SS_VECTOR: 4319 case GP_VECTOR: 4320 case PF_VECTOR: 4321 case AC_VECTOR: 4322 has_error_code = true; 4323 case CP_VECTOR: 4324 /* Some CPUs have error code and some do not, skip */ 4325 continue; 4326 } 4327 4328 /* Negative case */ 4329 deliver_error_code_mask = has_error_code ? 4330 0 : 4331 INTR_INFO_DELIVER_CODE_MASK; 4332 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4333 INTR_TYPE_HARD_EXCEPTION | cnt; 4334 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4335 ent_intr_info); 4336 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4337 test_vmx_invalid_controls(); 4338 report_prefix_pop(); 4339 4340 /* Positive case */ 4341 deliver_error_code_mask = has_error_code ? 4342 INTR_INFO_DELIVER_CODE_MASK : 4343 0; 4344 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4345 INTR_TYPE_HARD_EXCEPTION | cnt; 4346 report_prefix_pushf("VM-entry intr info=0x%x [+]", 4347 ent_intr_info); 4348 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4349 test_vmx_valid_controls(); 4350 report_prefix_pop(); 4351 } 4352 report_prefix_pop(); 4353 4354 /* Reserved bits in the field (30:12) are 0. */ 4355 report_prefix_push("reserved bits clear"); 4356 for (cnt = 12; cnt <= 30; cnt++) { 4357 ent_intr_info = ent_intr_info_base | 4358 INTR_INFO_DELIVER_CODE_MASK | 4359 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR | 4360 (1U << cnt); 4361 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4362 ent_intr_info); 4363 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4364 test_vmx_invalid_controls(); 4365 report_prefix_pop(); 4366 } 4367 report_prefix_pop(); 4368 4369 /* 4370 * If deliver-error-code is 1 4371 * bits 31:16 of the VM-entry exception error-code field are 0. 4372 */ 4373 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4374 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4375 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4376 "VM-entry exception error code[31:16] clear", 4377 ent_intr_info); 4378 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4379 for (cnt = 16; cnt <= 31; cnt++) { 4380 ent_intr_err = 1U << cnt; 4381 report_prefix_pushf("VM-entry intr error=0x%x [-]", 4382 ent_intr_err); 4383 vmcs_write(ENT_INTR_ERROR, ent_intr_err); 4384 test_vmx_invalid_controls(); 4385 report_prefix_pop(); 4386 } 4387 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4388 report_prefix_pop(); 4389 4390 /* 4391 * If the interruption type is software interrupt, software exception, 4392 * or privileged software exception, the VM-entry instruction-length 4393 * field is in the range 0 - 15. 4394 */ 4395 4396 for (cnt = 0; cnt < 3; cnt++) { 4397 switch (cnt) { 4398 case 0: 4399 ent_intr_info = ent_intr_info_base | 4400 INTR_TYPE_SOFT_INTR; 4401 break; 4402 case 1: 4403 ent_intr_info = ent_intr_info_base | 4404 INTR_TYPE_SOFT_EXCEPTION; 4405 break; 4406 case 2: 4407 ent_intr_info = ent_intr_info_base | 4408 INTR_TYPE_PRIV_SW_EXCEPTION; 4409 break; 4410 } 4411 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4412 "VM-entry instruction-length check", 4413 ent_intr_info); 4414 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4415 4416 /* Instruction length set to -1 (0xFFFFFFFF) should fail */ 4417 ent_intr_len = -1; 4418 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4419 ent_intr_len); 4420 vmcs_write(ENT_INST_LEN, ent_intr_len); 4421 test_vmx_invalid_controls(); 4422 report_prefix_pop(); 4423 4424 /* Instruction length set to 16 should fail */ 4425 ent_intr_len = 0x00000010; 4426 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4427 ent_intr_len); 4428 vmcs_write(ENT_INST_LEN, 0x00000010); 4429 test_vmx_invalid_controls(); 4430 report_prefix_pop(); 4431 4432 report_prefix_pop(); 4433 } 4434 4435 /* Cleanup */ 4436 vmcs_write(ENT_INTR_INFO, ent_intr_info_save); 4437 vmcs_write(ENT_INTR_ERROR, ent_intr_error_save); 4438 vmcs_write(ENT_INST_LEN, ent_inst_len_save); 4439 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4440 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4441 vmcs_write(GUEST_CR0, guest_cr0_save); 4442 report_prefix_pop(); 4443 } 4444 4445 /* 4446 * Test interesting vTPR values for a given TPR threshold. 4447 */ 4448 static void test_vtpr_values(unsigned threshold) 4449 { 4450 try_tpr_threshold_and_vtpr(threshold, (threshold - 1) << 4); 4451 try_tpr_threshold_and_vtpr(threshold, threshold << 4); 4452 try_tpr_threshold_and_vtpr(threshold, (threshold + 1) << 4); 4453 } 4454 4455 static void try_tpr_threshold(unsigned threshold) 4456 { 4457 bool valid = true; 4458 4459 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4460 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4461 4462 if ((primary & CPU_TPR_SHADOW) && !((primary & CPU_SECONDARY) && 4463 (secondary & CPU_VINTD))) 4464 valid = !(threshold >> 4); 4465 4466 set_vtpr(-1); 4467 vmcs_write(TPR_THRESHOLD, threshold); 4468 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0xf", threshold); 4469 if (valid) 4470 test_vmx_valid_controls(); 4471 else 4472 test_vmx_invalid_controls(); 4473 report_prefix_pop(); 4474 4475 if (valid) 4476 test_vtpr_values(threshold); 4477 } 4478 4479 /* 4480 * Test interesting TPR threshold values. 4481 */ 4482 static void test_tpr_threshold_values(void) 4483 { 4484 unsigned i; 4485 4486 for (i = 0; i < 0x10; i++) 4487 try_tpr_threshold(i); 4488 for (i = 4; i < 32; i++) 4489 try_tpr_threshold(1u << i); 4490 try_tpr_threshold(-1u); 4491 try_tpr_threshold(0x7fffffff); 4492 } 4493 4494 /* 4495 * This test covers the following two VM entry checks: 4496 * 4497 * i) If the "use TPR shadow" VM-execution control is 1 and the 4498 * "virtual-interrupt delivery" VM-execution control is 0, bits 4499 * 31:4 of the TPR threshold VM-execution control field must 4500 be 0. 4501 * [Intel SDM] 4502 * 4503 * ii) If the "use TPR shadow" VM-execution control is 1, the 4504 * "virtual-interrupt delivery" VM-execution control is 0 4505 * and the "virtualize APIC accesses" VM-execution control 4506 * is 0, the value of bits 3:0 of the TPR threshold VM-execution 4507 * control field must not be greater than the value of bits 4508 * 7:4 of VTPR. 4509 * [Intel SDM] 4510 */ 4511 static void test_tpr_threshold(void) 4512 { 4513 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4514 u64 apic_virt_addr = vmcs_read(APIC_VIRT_ADDR); 4515 u64 threshold = vmcs_read(TPR_THRESHOLD); 4516 void *virtual_apic_page; 4517 4518 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) 4519 return; 4520 4521 virtual_apic_page = alloc_page(); 4522 memset(virtual_apic_page, 0xff, PAGE_SIZE); 4523 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 4524 4525 vmcs_write(CPU_EXEC_CTRL0, primary & ~(CPU_TPR_SHADOW | CPU_SECONDARY)); 4526 report_prefix_pushf("Use TPR shadow disabled, secondary controls disabled"); 4527 test_tpr_threshold_values(); 4528 report_prefix_pop(); 4529 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_TPR_SHADOW); 4530 report_prefix_pushf("Use TPR shadow enabled, secondary controls disabled"); 4531 test_tpr_threshold_values(); 4532 report_prefix_pop(); 4533 4534 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4535 (ctrl_cpu_rev[1].clr & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 4536 goto out; 4537 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4538 4539 if (ctrl_cpu_rev[1].clr & CPU_VINTD) { 4540 vmcs_write(CPU_EXEC_CTRL1, CPU_VINTD); 4541 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4542 test_tpr_threshold_values(); 4543 report_prefix_pop(); 4544 4545 vmcs_write(CPU_EXEC_CTRL0, 4546 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4547 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4548 test_tpr_threshold_values(); 4549 report_prefix_pop(); 4550 } 4551 4552 if (ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES) { 4553 vmcs_write(CPU_EXEC_CTRL0, 4554 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4555 vmcs_write(CPU_EXEC_CTRL1, CPU_VIRT_APIC_ACCESSES); 4556 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4557 test_tpr_threshold_values(); 4558 report_prefix_pop(); 4559 4560 vmcs_write(CPU_EXEC_CTRL0, 4561 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4562 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4563 test_tpr_threshold_values(); 4564 report_prefix_pop(); 4565 } 4566 4567 if ((ctrl_cpu_rev[1].clr & 4568 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) == 4569 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) { 4570 vmcs_write(CPU_EXEC_CTRL0, 4571 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4572 vmcs_write(CPU_EXEC_CTRL1, 4573 CPU_VINTD | CPU_VIRT_APIC_ACCESSES); 4574 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4575 test_tpr_threshold_values(); 4576 report_prefix_pop(); 4577 4578 vmcs_write(CPU_EXEC_CTRL0, 4579 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4580 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4581 test_tpr_threshold_values(); 4582 report_prefix_pop(); 4583 } 4584 4585 vmcs_write(CPU_EXEC_CTRL1, secondary); 4586 out: 4587 vmcs_write(TPR_THRESHOLD, threshold); 4588 vmcs_write(APIC_VIRT_ADDR, apic_virt_addr); 4589 vmcs_write(CPU_EXEC_CTRL0, primary); 4590 } 4591 4592 /* 4593 * This test verifies the following two vmentry checks: 4594 * 4595 * If the "NMI exiting" VM-execution control is 0, "Virtual NMIs" 4596 * VM-execution control must be 0. 4597 * [Intel SDM] 4598 * 4599 * If the "virtual NMIs" VM-execution control is 0, the "NMI-window 4600 * exiting" VM-execution control must be 0. 4601 * [Intel SDM] 4602 */ 4603 static void test_nmi_ctrls(void) 4604 { 4605 u32 pin_ctrls, cpu_ctrls0, test_pin_ctrls, test_cpu_ctrls0; 4606 4607 if ((ctrl_pin_rev.clr & (PIN_NMI | PIN_VIRT_NMI)) != 4608 (PIN_NMI | PIN_VIRT_NMI)) { 4609 printf("NMI exiting and Virtual NMIs are not supported !\n"); 4610 return; 4611 } 4612 4613 /* Save the controls so that we can restore them after our tests */ 4614 pin_ctrls = vmcs_read(PIN_CONTROLS); 4615 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 4616 4617 test_pin_ctrls = pin_ctrls & ~(PIN_NMI | PIN_VIRT_NMI); 4618 test_cpu_ctrls0 = cpu_ctrls0 & ~CPU_NMI_WINDOW; 4619 4620 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4621 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs disabled"); 4622 test_vmx_valid_controls(); 4623 report_prefix_pop(); 4624 4625 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_VIRT_NMI); 4626 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs enabled"); 4627 test_vmx_invalid_controls(); 4628 report_prefix_pop(); 4629 4630 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4631 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs enabled"); 4632 test_vmx_valid_controls(); 4633 report_prefix_pop(); 4634 4635 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_NMI); 4636 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs disabled"); 4637 test_vmx_valid_controls(); 4638 report_prefix_pop(); 4639 4640 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 4641 report_info("NMI-window exiting is not supported, skipping..."); 4642 goto done; 4643 } 4644 4645 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4646 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4647 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting enabled"); 4648 test_vmx_invalid_controls(); 4649 report_prefix_pop(); 4650 4651 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4652 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4653 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting disabled"); 4654 test_vmx_valid_controls(); 4655 report_prefix_pop(); 4656 4657 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4658 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4659 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting enabled"); 4660 test_vmx_valid_controls(); 4661 report_prefix_pop(); 4662 4663 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4664 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4665 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting disabled"); 4666 test_vmx_valid_controls(); 4667 report_prefix_pop(); 4668 4669 /* Restore the controls to their original values */ 4670 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 4671 done: 4672 vmcs_write(PIN_CONTROLS, pin_ctrls); 4673 } 4674 4675 static void test_eptp_ad_bit(u64 eptp, bool is_ctrl_valid) 4676 { 4677 vmcs_write(EPTP, eptp); 4678 report_prefix_pushf("Enable-EPT enabled; EPT accessed and dirty flag %s", 4679 (eptp & EPTP_AD_FLAG) ? "1": "0"); 4680 if (is_ctrl_valid) 4681 test_vmx_valid_controls(); 4682 else 4683 test_vmx_invalid_controls(); 4684 report_prefix_pop(); 4685 4686 } 4687 4688 /* 4689 * 1. If the "enable EPT" VM-execution control is 1, the "EPTP VM-execution" 4690 * control field must satisfy the following checks: 4691 * 4692 * - The EPT memory type (bits 2:0) must be a value supported by the 4693 * processor as indicated in the IA32_VMX_EPT_VPID_CAP MSR. 4694 * - Bits 5:3 (1 less than the EPT page-walk length) must indicate a 4695 * supported EPT page-walk length. 4696 * - Bit 6 (enable bit for accessed and dirty flags for EPT) must be 4697 * 0 if bit 21 of the IA32_VMX_EPT_VPID_CAP MSR is read as 0, 4698 * indicating that the processor does not support accessed and dirty 4699 * dirty flags for EPT. 4700 * - Reserved bits 11:7 and 63:N (where N is the processor's 4701 * physical-address width) must all be 0. 4702 * 4703 * 2. If the "unrestricted guest" VM-execution control is 1, the 4704 * "enable EPT" VM-execution control must also be 1. 4705 */ 4706 static void test_ept_eptp(void) 4707 { 4708 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4709 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4710 u64 eptp_saved = vmcs_read(EPTP); 4711 u32 primary = primary_saved; 4712 u32 secondary = secondary_saved; 4713 u64 eptp = eptp_saved; 4714 u32 i, maxphysaddr; 4715 u64 j, resv_bits_mask = 0; 4716 4717 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4718 (ctrl_cpu_rev[1].clr & CPU_EPT))) { 4719 printf("\"CPU secondary\" and/or \"enable EPT\" execution controls are not supported !\n"); 4720 return; 4721 } 4722 4723 /* Support for 4-level EPT is mandatory. */ 4724 report(is_4_level_ept_supported(), "4-level EPT support check"); 4725 4726 primary |= CPU_SECONDARY; 4727 vmcs_write(CPU_EXEC_CTRL0, primary); 4728 secondary |= CPU_EPT; 4729 vmcs_write(CPU_EXEC_CTRL1, secondary); 4730 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4731 (3ul << EPTP_PG_WALK_LEN_SHIFT); 4732 vmcs_write(EPTP, eptp); 4733 4734 for (i = 0; i < 8; i++) { 4735 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | i; 4736 vmcs_write(EPTP, eptp); 4737 report_prefix_pushf("Enable-EPT enabled; EPT memory type %lu", 4738 eptp & EPT_MEM_TYPE_MASK); 4739 if (is_ept_memtype_supported(i)) 4740 test_vmx_valid_controls(); 4741 else 4742 test_vmx_invalid_controls(); 4743 report_prefix_pop(); 4744 } 4745 4746 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | 6ul; 4747 4748 /* 4749 * Page walk length (bits 5:3). Note, the value in VMCS.EPTP "is 1 4750 * less than the EPT page-walk length". 4751 */ 4752 for (i = 0; i < 8; i++) { 4753 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4754 (i << EPTP_PG_WALK_LEN_SHIFT); 4755 4756 vmcs_write(EPTP, eptp); 4757 report_prefix_pushf("Enable-EPT enabled; EPT page walk length %lu", 4758 eptp & EPTP_PG_WALK_LEN_MASK); 4759 if (i == 3 || (i == 4 && is_5_level_ept_supported())) 4760 test_vmx_valid_controls(); 4761 else 4762 test_vmx_invalid_controls(); 4763 report_prefix_pop(); 4764 } 4765 4766 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4767 3ul << EPTP_PG_WALK_LEN_SHIFT; 4768 4769 /* 4770 * Accessed and dirty flag (bit 6) 4771 */ 4772 if (ept_ad_bits_supported()) { 4773 report_info("Processor supports accessed and dirty flag"); 4774 eptp &= ~EPTP_AD_FLAG; 4775 test_eptp_ad_bit(eptp, true); 4776 4777 eptp |= EPTP_AD_FLAG; 4778 test_eptp_ad_bit(eptp, true); 4779 } else { 4780 report_info("Processor does not supports accessed and dirty flag"); 4781 eptp &= ~EPTP_AD_FLAG; 4782 test_eptp_ad_bit(eptp, true); 4783 4784 eptp |= EPTP_AD_FLAG; 4785 test_eptp_ad_bit(eptp, false); 4786 } 4787 4788 /* 4789 * Reserved bits [11:7] and [63:N] 4790 */ 4791 for (i = 0; i < 32; i++) { 4792 eptp = (eptp & 4793 ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)) | 4794 (i << EPTP_RESERV_BITS_SHIFT); 4795 vmcs_write(EPTP, eptp); 4796 report_prefix_pushf("Enable-EPT enabled; reserved bits [11:7] %lu", 4797 (eptp >> EPTP_RESERV_BITS_SHIFT) & 4798 EPTP_RESERV_BITS_MASK); 4799 if (i == 0) 4800 test_vmx_valid_controls(); 4801 else 4802 test_vmx_invalid_controls(); 4803 report_prefix_pop(); 4804 } 4805 4806 eptp = (eptp & ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)); 4807 4808 maxphysaddr = cpuid_maxphyaddr(); 4809 for (i = 0; i < (63 - maxphysaddr + 1); i++) { 4810 resv_bits_mask |= 1ul << i; 4811 } 4812 4813 for (j = maxphysaddr - 1; j <= 63; j++) { 4814 eptp = (eptp & ~(resv_bits_mask << maxphysaddr)) | 4815 (j < maxphysaddr ? 0 : 1ul << j); 4816 vmcs_write(EPTP, eptp); 4817 report_prefix_pushf("Enable-EPT enabled; reserved bits [63:N] %lu", 4818 (eptp >> maxphysaddr) & resv_bits_mask); 4819 if (j < maxphysaddr) 4820 test_vmx_valid_controls(); 4821 else 4822 test_vmx_invalid_controls(); 4823 report_prefix_pop(); 4824 } 4825 4826 secondary &= ~(CPU_EPT | CPU_URG); 4827 vmcs_write(CPU_EXEC_CTRL1, secondary); 4828 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest disabled"); 4829 test_vmx_valid_controls(); 4830 report_prefix_pop(); 4831 4832 if (!(ctrl_cpu_rev[1].clr & CPU_URG)) 4833 goto skip_unrestricted_guest; 4834 4835 secondary |= CPU_URG; 4836 vmcs_write(CPU_EXEC_CTRL1, secondary); 4837 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest enabled"); 4838 test_vmx_invalid_controls(); 4839 report_prefix_pop(); 4840 4841 secondary |= CPU_EPT; 4842 setup_dummy_ept(); 4843 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest enabled"); 4844 test_vmx_valid_controls(); 4845 report_prefix_pop(); 4846 4847 skip_unrestricted_guest: 4848 secondary &= ~CPU_URG; 4849 vmcs_write(CPU_EXEC_CTRL1, secondary); 4850 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest disabled"); 4851 test_vmx_valid_controls(); 4852 report_prefix_pop(); 4853 4854 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4855 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4856 vmcs_write(EPTP, eptp_saved); 4857 } 4858 4859 /* 4860 * If the 'enable PML' VM-execution control is 1, the 'enable EPT' 4861 * VM-execution control must also be 1. In addition, the PML address 4862 * must satisfy the following checks: 4863 * 4864 * * Bits 11:0 of the address must be 0. 4865 * * The address should not set any bits beyond the processor's 4866 * physical-address width. 4867 * 4868 * [Intel SDM] 4869 */ 4870 static void test_pml(void) 4871 { 4872 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4873 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4874 u32 primary = primary_saved; 4875 u32 secondary = secondary_saved; 4876 4877 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4878 (ctrl_cpu_rev[1].clr & CPU_EPT) && (ctrl_cpu_rev[1].clr & CPU_PML))) { 4879 printf("\"Secondary execution\" control or \"enable EPT\" control or \"enable PML\" control is not supported !\n"); 4880 return; 4881 } 4882 4883 primary |= CPU_SECONDARY; 4884 vmcs_write(CPU_EXEC_CTRL0, primary); 4885 secondary &= ~(CPU_PML | CPU_EPT); 4886 vmcs_write(CPU_EXEC_CTRL1, secondary); 4887 report_prefix_pushf("enable-PML disabled, enable-EPT disabled"); 4888 test_vmx_valid_controls(); 4889 report_prefix_pop(); 4890 4891 secondary |= CPU_PML; 4892 vmcs_write(CPU_EXEC_CTRL1, secondary); 4893 report_prefix_pushf("enable-PML enabled, enable-EPT disabled"); 4894 test_vmx_invalid_controls(); 4895 report_prefix_pop(); 4896 4897 secondary |= CPU_EPT; 4898 setup_dummy_ept(); 4899 report_prefix_pushf("enable-PML enabled, enable-EPT enabled"); 4900 test_vmx_valid_controls(); 4901 report_prefix_pop(); 4902 4903 secondary &= ~CPU_PML; 4904 vmcs_write(CPU_EXEC_CTRL1, secondary); 4905 report_prefix_pushf("enable-PML disabled, enable EPT enabled"); 4906 test_vmx_valid_controls(); 4907 report_prefix_pop(); 4908 4909 test_vmcs_addr_reference(CPU_PML, PMLADDR, "PML address", "PML", 4910 PAGE_SIZE, false, false); 4911 4912 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4913 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4914 } 4915 4916 /* 4917 * If the "activate VMX-preemption timer" VM-execution control is 0, the 4918 * the "save VMX-preemption timer value" VM-exit control must also be 0. 4919 * 4920 * [Intel SDM] 4921 */ 4922 static void test_vmx_preemption_timer(void) 4923 { 4924 u32 saved_pin = vmcs_read(PIN_CONTROLS); 4925 u32 saved_exit = vmcs_read(EXI_CONTROLS); 4926 u32 pin = saved_pin; 4927 u32 exit = saved_exit; 4928 4929 if (!((ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) || 4930 (ctrl_pin_rev.clr & PIN_PREEMPT))) { 4931 printf("\"Save-VMX-preemption-timer\" control and/or \"Enable-VMX-preemption-timer\" control is not supported\n"); 4932 return; 4933 } 4934 4935 pin |= PIN_PREEMPT; 4936 vmcs_write(PIN_CONTROLS, pin); 4937 exit &= ~EXI_SAVE_PREEMPT; 4938 vmcs_write(EXI_CONTROLS, exit); 4939 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer disabled"); 4940 test_vmx_valid_controls(); 4941 report_prefix_pop(); 4942 4943 exit |= EXI_SAVE_PREEMPT; 4944 vmcs_write(EXI_CONTROLS, exit); 4945 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer enabled"); 4946 test_vmx_valid_controls(); 4947 report_prefix_pop(); 4948 4949 pin &= ~PIN_PREEMPT; 4950 vmcs_write(PIN_CONTROLS, pin); 4951 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer enabled"); 4952 test_vmx_invalid_controls(); 4953 report_prefix_pop(); 4954 4955 exit &= ~EXI_SAVE_PREEMPT; 4956 vmcs_write(EXI_CONTROLS, exit); 4957 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer disabled"); 4958 test_vmx_valid_controls(); 4959 report_prefix_pop(); 4960 4961 vmcs_write(PIN_CONTROLS, saved_pin); 4962 vmcs_write(EXI_CONTROLS, saved_exit); 4963 } 4964 4965 extern unsigned char test_mtf1; 4966 extern unsigned char test_mtf2; 4967 extern unsigned char test_mtf3; 4968 extern unsigned char test_mtf4; 4969 4970 static void test_mtf_guest(void) 4971 { 4972 asm ("vmcall;\n\t" 4973 "out %al, $0x80;\n\t" 4974 "test_mtf1:\n\t" 4975 "vmcall;\n\t" 4976 "out %al, $0x80;\n\t" 4977 "test_mtf2:\n\t" 4978 /* 4979 * Prepare for the 'MOV CR3' test. Attempt to induce a 4980 * general-protection fault by moving a non-canonical address into 4981 * CR3. The 'MOV CR3' instruction does not take an imm64 operand, 4982 * so we must MOV the desired value into a register first. 4983 * 4984 * MOV RAX is done before the VMCALL such that MTF is only enabled 4985 * for the instruction under test. 4986 */ 4987 "mov $0xaaaaaaaaaaaaaaaa, %rax;\n\t" 4988 "vmcall;\n\t" 4989 "mov %rax, %cr3;\n\t" 4990 "test_mtf3:\n\t" 4991 "vmcall;\n\t" 4992 /* 4993 * ICEBP/INT1 instruction. Though the instruction is now 4994 * documented, don't rely on assemblers enumerating the 4995 * instruction. Resort to hand assembly. 4996 */ 4997 ".byte 0xf1;\n\t" 4998 "vmcall;\n\t" 4999 "test_mtf4:\n\t" 5000 "mov $0, %eax;\n\t"); 5001 } 5002 5003 static void test_mtf_gp_handler(struct ex_regs *regs) 5004 { 5005 regs->rip = (unsigned long) &test_mtf3; 5006 } 5007 5008 static void test_mtf_db_handler(struct ex_regs *regs) 5009 { 5010 } 5011 5012 static void enable_mtf(void) 5013 { 5014 u32 ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 5015 5016 vmcs_write(CPU_EXEC_CTRL0, ctrl0 | CPU_MTF); 5017 } 5018 5019 static void disable_mtf(void) 5020 { 5021 u32 ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 5022 5023 vmcs_write(CPU_EXEC_CTRL0, ctrl0 & ~CPU_MTF); 5024 } 5025 5026 static void enable_tf(void) 5027 { 5028 unsigned long rflags = vmcs_read(GUEST_RFLAGS); 5029 5030 vmcs_write(GUEST_RFLAGS, rflags | X86_EFLAGS_TF); 5031 } 5032 5033 static void disable_tf(void) 5034 { 5035 unsigned long rflags = vmcs_read(GUEST_RFLAGS); 5036 5037 vmcs_write(GUEST_RFLAGS, rflags & ~X86_EFLAGS_TF); 5038 } 5039 5040 static void report_mtf(const char *insn_name, unsigned long exp_rip) 5041 { 5042 unsigned long rip = vmcs_read(GUEST_RIP); 5043 5044 assert_exit_reason(VMX_MTF); 5045 report(rip == exp_rip, "MTF VM-exit after %s. RIP: 0x%lx (expected 0x%lx)", 5046 insn_name, rip, exp_rip); 5047 } 5048 5049 static void vmx_mtf_test(void) 5050 { 5051 unsigned long pending_dbg; 5052 handler old_gp, old_db; 5053 5054 if (!(ctrl_cpu_rev[0].clr & CPU_MTF)) { 5055 printf("CPU does not support the 'monitor trap flag' processor-based VM-execution control.\n"); 5056 return; 5057 } 5058 5059 test_set_guest(test_mtf_guest); 5060 5061 /* Expect an MTF VM-exit after OUT instruction */ 5062 enter_guest(); 5063 skip_exit_vmcall(); 5064 5065 enable_mtf(); 5066 enter_guest(); 5067 report_mtf("OUT", (unsigned long) &test_mtf1); 5068 disable_mtf(); 5069 5070 /* 5071 * Concurrent #DB trap and MTF on instruction boundary. Expect MTF 5072 * VM-exit with populated 'pending debug exceptions' VMCS field. 5073 */ 5074 enter_guest(); 5075 skip_exit_vmcall(); 5076 5077 enable_mtf(); 5078 enable_tf(); 5079 5080 enter_guest(); 5081 report_mtf("OUT", (unsigned long) &test_mtf2); 5082 pending_dbg = vmcs_read(GUEST_PENDING_DEBUG); 5083 report(pending_dbg & DR_STEP, 5084 "'pending debug exceptions' field after MTF VM-exit: 0x%lx (expected 0x%lx)", 5085 pending_dbg, (unsigned long) DR_STEP); 5086 5087 disable_mtf(); 5088 disable_tf(); 5089 vmcs_write(GUEST_PENDING_DEBUG, 0); 5090 5091 /* 5092 * #GP exception takes priority over MTF. Expect MTF VM-exit with RIP 5093 * advanced to first instruction of #GP handler. 5094 */ 5095 enter_guest(); 5096 skip_exit_vmcall(); 5097 5098 old_gp = handle_exception(GP_VECTOR, test_mtf_gp_handler); 5099 5100 enable_mtf(); 5101 enter_guest(); 5102 report_mtf("MOV CR3", (unsigned long) get_idt_addr(&boot_idt[GP_VECTOR])); 5103 disable_mtf(); 5104 5105 /* 5106 * Concurrent MTF and privileged software exception (i.e. ICEBP/INT1). 5107 * MTF should follow the delivery of #DB trap, though the SDM doesn't 5108 * provide clear indication of the relative priority. 5109 */ 5110 enter_guest(); 5111 skip_exit_vmcall(); 5112 5113 handle_exception(GP_VECTOR, old_gp); 5114 old_db = handle_exception(DB_VECTOR, test_mtf_db_handler); 5115 5116 enable_mtf(); 5117 enter_guest(); 5118 report_mtf("INT1", (unsigned long) get_idt_addr(&boot_idt[DB_VECTOR])); 5119 disable_mtf(); 5120 5121 enter_guest(); 5122 skip_exit_vmcall(); 5123 handle_exception(DB_VECTOR, old_db); 5124 vmcs_write(ENT_INTR_INFO, INTR_INFO_VALID_MASK | INTR_TYPE_OTHER_EVENT); 5125 enter_guest(); 5126 report_mtf("injected MTF", (unsigned long) &test_mtf4); 5127 enter_guest(); 5128 } 5129 5130 extern char vmx_mtf_pdpte_guest_begin; 5131 extern char vmx_mtf_pdpte_guest_end; 5132 5133 asm("vmx_mtf_pdpte_guest_begin:\n\t" 5134 "mov %cr0, %rax\n\t" /* save CR0 with PG=1 */ 5135 "vmcall\n\t" /* on return from this CR0.PG=0 */ 5136 "mov %rax, %cr0\n\t" /* restore CR0.PG=1 to enter PAE mode */ 5137 "vmcall\n\t" 5138 "retq\n\t" 5139 "vmx_mtf_pdpte_guest_end:"); 5140 5141 static void vmx_mtf_pdpte_test(void) 5142 { 5143 void *test_mtf_pdpte_guest; 5144 pteval_t *pdpt; 5145 u32 guest_ar_cs; 5146 u64 guest_efer; 5147 pteval_t *pte; 5148 u64 guest_cr0; 5149 u64 guest_cr3; 5150 u64 guest_cr4; 5151 u64 ent_ctls; 5152 int i; 5153 5154 if (setup_ept(false)) 5155 return; 5156 5157 if (!(ctrl_cpu_rev[0].clr & CPU_MTF)) { 5158 printf("CPU does not support 'monitor trap flag.'\n"); 5159 return; 5160 } 5161 5162 if (!(ctrl_cpu_rev[1].clr & CPU_URG)) { 5163 printf("CPU does not support 'unrestricted guest.'\n"); 5164 return; 5165 } 5166 5167 vmcs_write(EXC_BITMAP, ~0); 5168 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | CPU_URG); 5169 5170 /* 5171 * Copy the guest code to an identity-mapped page. 5172 */ 5173 test_mtf_pdpte_guest = alloc_page(); 5174 memcpy(test_mtf_pdpte_guest, &vmx_mtf_pdpte_guest_begin, 5175 &vmx_mtf_pdpte_guest_end - &vmx_mtf_pdpte_guest_begin); 5176 5177 test_set_guest(test_mtf_pdpte_guest); 5178 5179 enter_guest(); 5180 skip_exit_vmcall(); 5181 5182 /* 5183 * Put the guest in non-paged 32-bit protected mode, ready to enter 5184 * PAE mode when CR0.PG is set. CR4.PAE will already have been set 5185 * when the guest started out in long mode. 5186 */ 5187 ent_ctls = vmcs_read(ENT_CONTROLS); 5188 vmcs_write(ENT_CONTROLS, ent_ctls & ~ENT_GUEST_64); 5189 5190 guest_efer = vmcs_read(GUEST_EFER); 5191 vmcs_write(GUEST_EFER, guest_efer & ~(EFER_LMA | EFER_LME)); 5192 5193 /* 5194 * Set CS access rights bits for 32-bit protected mode: 5195 * 3:0 B execute/read/accessed 5196 * 4 1 code or data 5197 * 6:5 0 descriptor privilege level 5198 * 7 1 present 5199 * 11:8 0 reserved 5200 * 12 0 available for use by system software 5201 * 13 0 64 bit mode not active 5202 * 14 1 default operation size 32-bit segment 5203 * 15 1 page granularity: segment limit in 4K units 5204 * 16 0 segment usable 5205 * 31:17 0 reserved 5206 */ 5207 guest_ar_cs = vmcs_read(GUEST_AR_CS); 5208 vmcs_write(GUEST_AR_CS, 0xc09b); 5209 5210 guest_cr0 = vmcs_read(GUEST_CR0); 5211 vmcs_write(GUEST_CR0, guest_cr0 & ~X86_CR0_PG); 5212 5213 guest_cr4 = vmcs_read(GUEST_CR4); 5214 vmcs_write(GUEST_CR4, guest_cr4 & ~X86_CR4_PCIDE); 5215 5216 guest_cr3 = vmcs_read(GUEST_CR3); 5217 5218 /* 5219 * Turn the 4-level page table into a PAE page table by following the 0th 5220 * PML4 entry to a PDPT page, and grab the first four PDPTEs from that 5221 * page. 5222 * 5223 * Why does this work? 5224 * 5225 * PAE uses 32-bit addressing which implies: 5226 * Bits 11:0 page offset 5227 * Bits 20:12 entry into 512-entry page table 5228 * Bits 29:21 entry into a 512-entry directory table 5229 * Bits 31:30 entry into the page directory pointer table. 5230 * Bits 63:32 zero 5231 * 5232 * As only 2 bits are needed to select the PDPTEs for the entire 5233 * 32-bit address space, take the first 4 PDPTEs in the level 3 page 5234 * directory pointer table. It doesn't matter which of these PDPTEs 5235 * are present because they must cover the guest code given that it 5236 * has already run successfully. 5237 * 5238 * Get a pointer to PTE for GVA=0 in the page directory pointer table 5239 */ 5240 pte = get_pte_level( 5241 (pgd_t *)phys_to_virt(guest_cr3 & ~X86_CR3_PCID_MASK), 0, 5242 PDPT_LEVEL); 5243 5244 /* 5245 * Need some memory for the 4-entry PAE page directory pointer 5246 * table. Use the end of the identity-mapped page where the guest code 5247 * is stored. There is definitely space as the guest code is only a 5248 * few bytes. 5249 */ 5250 pdpt = test_mtf_pdpte_guest + PAGE_SIZE - 4 * sizeof(pteval_t); 5251 5252 /* 5253 * Copy the first four PDPTEs into the PAE page table with reserved 5254 * bits cleared. Note that permission bits from the PML4E and PDPTE 5255 * are not propagated. 5256 */ 5257 for (i = 0; i < 4; i++) { 5258 TEST_ASSERT_EQ_MSG(0, (pte[i] & PDPTE64_RSVD_MASK), 5259 "PDPTE has invalid reserved bits"); 5260 TEST_ASSERT_EQ_MSG(0, (pte[i] & PDPTE64_PAGE_SIZE_MASK), 5261 "Cannot use 1GB super pages for PAE"); 5262 pdpt[i] = pte[i] & ~(PAE_PDPTE_RSVD_MASK); 5263 } 5264 vmcs_write(GUEST_CR3, virt_to_phys(pdpt)); 5265 5266 enable_mtf(); 5267 enter_guest(); 5268 assert_exit_reason(VMX_MTF); 5269 disable_mtf(); 5270 5271 /* 5272 * The four PDPTEs should have been loaded into the VMCS when 5273 * the guest set CR0.PG to enter PAE mode. 5274 */ 5275 for (i = 0; i < 4; i++) { 5276 u64 pdpte = vmcs_read(GUEST_PDPTE + 2 * i); 5277 5278 report(pdpte == pdpt[i], "PDPTE%d is 0x%lx (expected 0x%lx)", 5279 i, pdpte, pdpt[i]); 5280 } 5281 5282 /* 5283 * Now, try to enter the guest in PAE mode. If the PDPTEs in the 5284 * vmcs are wrong, this will fail. 5285 */ 5286 enter_guest(); 5287 skip_exit_vmcall(); 5288 5289 /* 5290 * Return guest to 64-bit mode and wrap up. 5291 */ 5292 vmcs_write(ENT_CONTROLS, ent_ctls); 5293 vmcs_write(GUEST_EFER, guest_efer); 5294 vmcs_write(GUEST_AR_CS, guest_ar_cs); 5295 vmcs_write(GUEST_CR0, guest_cr0); 5296 vmcs_write(GUEST_CR4, guest_cr4); 5297 vmcs_write(GUEST_CR3, guest_cr3); 5298 5299 enter_guest(); 5300 } 5301 5302 /* 5303 * Tests for VM-execution control fields 5304 */ 5305 static void test_vm_execution_ctls(void) 5306 { 5307 test_pin_based_ctls(); 5308 test_primary_processor_based_ctls(); 5309 test_secondary_processor_based_ctls(); 5310 test_cr3_targets(); 5311 test_io_bitmaps(); 5312 test_msr_bitmap(); 5313 test_apic_ctls(); 5314 test_tpr_threshold(); 5315 test_nmi_ctrls(); 5316 test_pml(); 5317 test_vpid(); 5318 test_ept_eptp(); 5319 test_vmx_preemption_timer(); 5320 } 5321 5322 /* 5323 * The following checks are performed for the VM-entry MSR-load address if 5324 * the VM-entry MSR-load count field is non-zero: 5325 * 5326 * - The lower 4 bits of the VM-entry MSR-load address must be 0. 5327 * The address should not set any bits beyond the processor's 5328 * physical-address width. 5329 * 5330 * - The address of the last byte in the VM-entry MSR-load area 5331 * should not set any bits beyond the processor's physical-address 5332 * width. The address of this last byte is VM-entry MSR-load address 5333 * + (MSR count * 16) - 1. (The arithmetic used for the computation 5334 * uses more bits than the processor's physical-address width.) 5335 * 5336 * 5337 * [Intel SDM] 5338 */ 5339 static void test_entry_msr_load(void) 5340 { 5341 entry_msr_load = alloc_page(); 5342 u64 tmp; 5343 u32 entry_msr_ld_cnt = 1; 5344 int i; 5345 u32 addr_len = 64; 5346 5347 vmcs_write(ENT_MSR_LD_CNT, entry_msr_ld_cnt); 5348 5349 /* Check first 4 bits of VM-entry MSR-load address */ 5350 for (i = 0; i < 4; i++) { 5351 tmp = (u64)entry_msr_load | 1ull << i; 5352 vmcs_write(ENTER_MSR_LD_ADDR, tmp); 5353 report_prefix_pushf("VM-entry MSR-load addr [4:0] %lx", 5354 tmp & 0xf); 5355 test_vmx_invalid_controls(); 5356 report_prefix_pop(); 5357 } 5358 5359 if (basic.val & (1ul << 48)) 5360 addr_len = 32; 5361 5362 test_vmcs_addr_values("VM-entry-MSR-load address", 5363 ENTER_MSR_LD_ADDR, 16, false, false, 5364 4, addr_len - 1); 5365 5366 /* 5367 * Check last byte of VM-entry MSR-load address 5368 */ 5369 entry_msr_load = (struct vmx_msr_entry *)((u64)entry_msr_load & ~0xf); 5370 5371 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 5372 i < 64; i++) { 5373 tmp = ((u64)entry_msr_load + entry_msr_ld_cnt * 16 - 1) | 5374 1ul << i; 5375 vmcs_write(ENTER_MSR_LD_ADDR, 5376 tmp - (entry_msr_ld_cnt * 16 - 1)); 5377 test_vmx_invalid_controls(); 5378 } 5379 5380 vmcs_write(ENT_MSR_LD_CNT, 2); 5381 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 5382 test_vmx_invalid_controls(); 5383 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 5384 test_vmx_valid_controls(); 5385 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 5386 test_vmx_valid_controls(); 5387 } 5388 5389 static struct vmx_state_area_test_data { 5390 u32 msr; 5391 u64 exp; 5392 bool enabled; 5393 } vmx_state_area_test_data; 5394 5395 static void guest_state_test_main(void) 5396 { 5397 u64 obs; 5398 struct vmx_state_area_test_data *data = &vmx_state_area_test_data; 5399 5400 while (1) { 5401 if (vmx_get_test_stage() == 2) 5402 break; 5403 5404 if (data->enabled) { 5405 obs = rdmsr(data->msr); 5406 report(data->exp == obs, 5407 "Guest state is 0x%lx (expected 0x%lx)", 5408 obs, data->exp); 5409 } 5410 5411 vmcall(); 5412 } 5413 5414 asm volatile("fnop"); 5415 } 5416 5417 static void test_guest_state(const char *test, bool xfail, u64 field, 5418 const char * field_name) 5419 { 5420 struct vmentry_result result; 5421 u8 abort_flags; 5422 5423 abort_flags = ABORT_ON_EARLY_VMENTRY_FAIL; 5424 if (!xfail) 5425 abort_flags = ABORT_ON_INVALID_GUEST_STATE; 5426 5427 __enter_guest(abort_flags, &result); 5428 5429 report(result.exit_reason.failed_vmentry == xfail && 5430 ((xfail && result.exit_reason.basic == VMX_FAIL_STATE) || 5431 (!xfail && result.exit_reason.basic == VMX_VMCALL)) && 5432 (!xfail || vmcs_read(EXI_QUALIFICATION) == ENTRY_FAIL_DEFAULT), 5433 "%s, %s = %lx", test, field_name, field); 5434 5435 if (!result.exit_reason.failed_vmentry) 5436 skip_exit_insn(); 5437 } 5438 5439 /* 5440 * Tests for VM-entry control fields 5441 */ 5442 static void test_vm_entry_ctls(void) 5443 { 5444 test_invalid_event_injection(); 5445 test_entry_msr_load(); 5446 } 5447 5448 /* 5449 * The following checks are performed for the VM-exit MSR-store address if 5450 * the VM-exit MSR-store count field is non-zero: 5451 * 5452 * - The lower 4 bits of the VM-exit MSR-store address must be 0. 5453 * The address should not set any bits beyond the processor's 5454 * physical-address width. 5455 * 5456 * - The address of the last byte in the VM-exit MSR-store area 5457 * should not set any bits beyond the processor's physical-address 5458 * width. The address of this last byte is VM-exit MSR-store address 5459 * + (MSR count * 16) - 1. (The arithmetic used for the computation 5460 * uses more bits than the processor's physical-address width.) 5461 * 5462 * If IA32_VMX_BASIC[48] is read as 1, neither address should set any bits 5463 * in the range 63:32. 5464 * 5465 * [Intel SDM] 5466 */ 5467 static void test_exit_msr_store(void) 5468 { 5469 exit_msr_store = alloc_page(); 5470 u64 tmp; 5471 u32 exit_msr_st_cnt = 1; 5472 int i; 5473 u32 addr_len = 64; 5474 5475 vmcs_write(EXI_MSR_ST_CNT, exit_msr_st_cnt); 5476 5477 /* Check first 4 bits of VM-exit MSR-store address */ 5478 for (i = 0; i < 4; i++) { 5479 tmp = (u64)exit_msr_store | 1ull << i; 5480 vmcs_write(EXIT_MSR_ST_ADDR, tmp); 5481 report_prefix_pushf("VM-exit MSR-store addr [4:0] %lx", 5482 tmp & 0xf); 5483 test_vmx_invalid_controls(); 5484 report_prefix_pop(); 5485 } 5486 5487 if (basic.val & (1ul << 48)) 5488 addr_len = 32; 5489 5490 test_vmcs_addr_values("VM-exit-MSR-store address", 5491 EXIT_MSR_ST_ADDR, 16, false, false, 5492 4, addr_len - 1); 5493 5494 /* 5495 * Check last byte of VM-exit MSR-store address 5496 */ 5497 exit_msr_store = (struct vmx_msr_entry *)((u64)exit_msr_store & ~0xf); 5498 5499 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 5500 i < 64; i++) { 5501 tmp = ((u64)exit_msr_store + exit_msr_st_cnt * 16 - 1) | 5502 1ul << i; 5503 vmcs_write(EXIT_MSR_ST_ADDR, 5504 tmp - (exit_msr_st_cnt * 16 - 1)); 5505 test_vmx_invalid_controls(); 5506 } 5507 5508 vmcs_write(EXI_MSR_ST_CNT, 2); 5509 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 5510 test_vmx_invalid_controls(); 5511 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 5512 test_vmx_valid_controls(); 5513 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 5514 test_vmx_valid_controls(); 5515 } 5516 5517 /* 5518 * Tests for VM-exit controls 5519 */ 5520 static void test_vm_exit_ctls(void) 5521 { 5522 test_exit_msr_store(); 5523 } 5524 5525 /* 5526 * Check that the virtual CPU checks all of the VMX controls as 5527 * documented in the Intel SDM. 5528 */ 5529 static void vmx_controls_test(void) 5530 { 5531 /* 5532 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 5533 * fail due to invalid guest state, should we make it that 5534 * far. 5535 */ 5536 vmcs_write(GUEST_RFLAGS, 0); 5537 5538 test_vm_execution_ctls(); 5539 test_vm_exit_ctls(); 5540 test_vm_entry_ctls(); 5541 } 5542 5543 struct apic_reg_virt_config { 5544 bool apic_register_virtualization; 5545 bool use_tpr_shadow; 5546 bool virtualize_apic_accesses; 5547 bool virtualize_x2apic_mode; 5548 bool activate_secondary_controls; 5549 }; 5550 5551 struct apic_reg_test { 5552 const char *name; 5553 struct apic_reg_virt_config apic_reg_virt_config; 5554 }; 5555 5556 struct apic_reg_virt_expectation { 5557 enum Reason rd_exit_reason; 5558 enum Reason wr_exit_reason; 5559 u32 val; 5560 u32 (*virt_fn)(u32); 5561 5562 /* 5563 * If false, accessing the APIC access address from L2 is treated as a 5564 * normal memory operation, rather than triggering virtualization. 5565 */ 5566 bool virtualize_apic_accesses; 5567 }; 5568 5569 static u32 apic_virt_identity(u32 val) 5570 { 5571 return val; 5572 } 5573 5574 static u32 apic_virt_nibble1(u32 val) 5575 { 5576 return val & 0xf0; 5577 } 5578 5579 static u32 apic_virt_byte3(u32 val) 5580 { 5581 return val & (0xff << 24); 5582 } 5583 5584 static bool apic_reg_virt_exit_expectation( 5585 u32 reg, struct apic_reg_virt_config *config, 5586 struct apic_reg_virt_expectation *expectation) 5587 { 5588 /* Good configs, where some L2 APIC accesses are virtualized. */ 5589 bool virtualize_apic_accesses_only = 5590 config->virtualize_apic_accesses && 5591 !config->use_tpr_shadow && 5592 !config->apic_register_virtualization && 5593 !config->virtualize_x2apic_mode && 5594 config->activate_secondary_controls; 5595 bool virtualize_apic_accesses_and_use_tpr_shadow = 5596 config->virtualize_apic_accesses && 5597 config->use_tpr_shadow && 5598 !config->apic_register_virtualization && 5599 !config->virtualize_x2apic_mode && 5600 config->activate_secondary_controls; 5601 bool apic_register_virtualization = 5602 config->virtualize_apic_accesses && 5603 config->use_tpr_shadow && 5604 config->apic_register_virtualization && 5605 !config->virtualize_x2apic_mode && 5606 config->activate_secondary_controls; 5607 5608 expectation->val = MAGIC_VAL_1; 5609 expectation->virt_fn = apic_virt_identity; 5610 expectation->virtualize_apic_accesses = 5611 config->virtualize_apic_accesses && 5612 config->activate_secondary_controls; 5613 if (virtualize_apic_accesses_only) { 5614 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5615 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5616 } else if (virtualize_apic_accesses_and_use_tpr_shadow) { 5617 switch (reg) { 5618 case APIC_TASKPRI: 5619 expectation->rd_exit_reason = VMX_VMCALL; 5620 expectation->wr_exit_reason = VMX_VMCALL; 5621 expectation->virt_fn = apic_virt_nibble1; 5622 break; 5623 default: 5624 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5625 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5626 } 5627 } else if (apic_register_virtualization) { 5628 expectation->rd_exit_reason = VMX_VMCALL; 5629 5630 switch (reg) { 5631 case APIC_ID: 5632 case APIC_EOI: 5633 case APIC_LDR: 5634 case APIC_DFR: 5635 case APIC_SPIV: 5636 case APIC_ESR: 5637 case APIC_ICR: 5638 case APIC_LVTT: 5639 case APIC_LVTTHMR: 5640 case APIC_LVTPC: 5641 case APIC_LVT0: 5642 case APIC_LVT1: 5643 case APIC_LVTERR: 5644 case APIC_TMICT: 5645 case APIC_TDCR: 5646 expectation->wr_exit_reason = VMX_APIC_WRITE; 5647 break; 5648 case APIC_LVR: 5649 case APIC_ISR ... APIC_ISR + 0x70: 5650 case APIC_TMR ... APIC_TMR + 0x70: 5651 case APIC_IRR ... APIC_IRR + 0x70: 5652 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5653 break; 5654 case APIC_TASKPRI: 5655 expectation->wr_exit_reason = VMX_VMCALL; 5656 expectation->virt_fn = apic_virt_nibble1; 5657 break; 5658 case APIC_ICR2: 5659 expectation->wr_exit_reason = VMX_VMCALL; 5660 expectation->virt_fn = apic_virt_byte3; 5661 break; 5662 default: 5663 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5664 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5665 } 5666 } else if (!expectation->virtualize_apic_accesses) { 5667 /* 5668 * No APIC registers are directly virtualized. This includes 5669 * VTPR, which can be virtualized through MOV to/from CR8 via 5670 * the use TPR shadow control, but not through directly 5671 * accessing VTPR. 5672 */ 5673 expectation->rd_exit_reason = VMX_VMCALL; 5674 expectation->wr_exit_reason = VMX_VMCALL; 5675 } else { 5676 printf("Cannot parse APIC register virtualization config:\n" 5677 "\tvirtualize_apic_accesses: %d\n" 5678 "\tuse_tpr_shadow: %d\n" 5679 "\tapic_register_virtualization: %d\n" 5680 "\tvirtualize_x2apic_mode: %d\n" 5681 "\tactivate_secondary_controls: %d\n", 5682 config->virtualize_apic_accesses, 5683 config->use_tpr_shadow, 5684 config->apic_register_virtualization, 5685 config->virtualize_x2apic_mode, 5686 config->activate_secondary_controls); 5687 5688 return false; 5689 } 5690 5691 return true; 5692 } 5693 5694 struct apic_reg_test apic_reg_tests[] = { 5695 /* Good configs, where some L2 APIC accesses are virtualized. */ 5696 { 5697 .name = "Virtualize APIC accesses", 5698 .apic_reg_virt_config = { 5699 .virtualize_apic_accesses = true, 5700 .use_tpr_shadow = false, 5701 .apic_register_virtualization = false, 5702 .virtualize_x2apic_mode = false, 5703 .activate_secondary_controls = true, 5704 }, 5705 }, 5706 { 5707 .name = "Virtualize APIC accesses + Use TPR shadow", 5708 .apic_reg_virt_config = { 5709 .virtualize_apic_accesses = true, 5710 .use_tpr_shadow = true, 5711 .apic_register_virtualization = false, 5712 .virtualize_x2apic_mode = false, 5713 .activate_secondary_controls = true, 5714 }, 5715 }, 5716 { 5717 .name = "APIC-register virtualization", 5718 .apic_reg_virt_config = { 5719 .virtualize_apic_accesses = true, 5720 .use_tpr_shadow = true, 5721 .apic_register_virtualization = true, 5722 .virtualize_x2apic_mode = false, 5723 .activate_secondary_controls = true, 5724 }, 5725 }, 5726 5727 /* 5728 * Test that the secondary processor-based VM-execution controls are 5729 * correctly ignored when "activate secondary controls" is disabled. 5730 */ 5731 { 5732 .name = "Activate secondary controls off", 5733 .apic_reg_virt_config = { 5734 .virtualize_apic_accesses = true, 5735 .use_tpr_shadow = false, 5736 .apic_register_virtualization = true, 5737 .virtualize_x2apic_mode = true, 5738 .activate_secondary_controls = false, 5739 }, 5740 }, 5741 { 5742 .name = "Activate secondary controls off + Use TPR shadow", 5743 .apic_reg_virt_config = { 5744 .virtualize_apic_accesses = true, 5745 .use_tpr_shadow = true, 5746 .apic_register_virtualization = true, 5747 .virtualize_x2apic_mode = true, 5748 .activate_secondary_controls = false, 5749 }, 5750 }, 5751 5752 /* 5753 * Test that the APIC access address is treated like an arbitrary memory 5754 * address when "virtualize APIC accesses" is disabled. 5755 */ 5756 { 5757 .name = "Virtualize APIC accesses off + Use TPR shadow", 5758 .apic_reg_virt_config = { 5759 .virtualize_apic_accesses = false, 5760 .use_tpr_shadow = true, 5761 .apic_register_virtualization = true, 5762 .virtualize_x2apic_mode = true, 5763 .activate_secondary_controls = true, 5764 }, 5765 }, 5766 5767 /* 5768 * Test that VM entry fails due to invalid controls when 5769 * "APIC-register virtualization" is enabled while "use TPR shadow" is 5770 * disabled. 5771 */ 5772 { 5773 .name = "APIC-register virtualization + Use TPR shadow off", 5774 .apic_reg_virt_config = { 5775 .virtualize_apic_accesses = true, 5776 .use_tpr_shadow = false, 5777 .apic_register_virtualization = true, 5778 .virtualize_x2apic_mode = false, 5779 .activate_secondary_controls = true, 5780 }, 5781 }, 5782 5783 /* 5784 * Test that VM entry fails due to invalid controls when 5785 * "Virtualize x2APIC mode" is enabled while "use TPR shadow" is 5786 * disabled. 5787 */ 5788 { 5789 .name = "Virtualize x2APIC mode + Use TPR shadow off", 5790 .apic_reg_virt_config = { 5791 .virtualize_apic_accesses = false, 5792 .use_tpr_shadow = false, 5793 .apic_register_virtualization = false, 5794 .virtualize_x2apic_mode = true, 5795 .activate_secondary_controls = true, 5796 }, 5797 }, 5798 { 5799 .name = "Virtualize x2APIC mode + Use TPR shadow off v2", 5800 .apic_reg_virt_config = { 5801 .virtualize_apic_accesses = false, 5802 .use_tpr_shadow = false, 5803 .apic_register_virtualization = true, 5804 .virtualize_x2apic_mode = true, 5805 .activate_secondary_controls = true, 5806 }, 5807 }, 5808 5809 /* 5810 * Test that VM entry fails due to invalid controls when 5811 * "virtualize x2APIC mode" is enabled while "virtualize APIC accesses" 5812 * is enabled. 5813 */ 5814 { 5815 .name = "Virtualize x2APIC mode + Virtualize APIC accesses", 5816 .apic_reg_virt_config = { 5817 .virtualize_apic_accesses = true, 5818 .use_tpr_shadow = true, 5819 .apic_register_virtualization = false, 5820 .virtualize_x2apic_mode = true, 5821 .activate_secondary_controls = true, 5822 }, 5823 }, 5824 { 5825 .name = "Virtualize x2APIC mode + Virtualize APIC accesses v2", 5826 .apic_reg_virt_config = { 5827 .virtualize_apic_accesses = true, 5828 .use_tpr_shadow = true, 5829 .apic_register_virtualization = true, 5830 .virtualize_x2apic_mode = true, 5831 .activate_secondary_controls = true, 5832 }, 5833 }, 5834 }; 5835 5836 enum Apic_op { 5837 APIC_OP_XAPIC_RD, 5838 APIC_OP_XAPIC_WR, 5839 TERMINATE, 5840 }; 5841 5842 static u32 vmx_xapic_read(u32 *apic_access_address, u32 reg) 5843 { 5844 return *(volatile u32 *)((uintptr_t)apic_access_address + reg); 5845 } 5846 5847 static void vmx_xapic_write(u32 *apic_access_address, u32 reg, u32 val) 5848 { 5849 *(volatile u32 *)((uintptr_t)apic_access_address + reg) = val; 5850 } 5851 5852 struct apic_reg_virt_guest_args { 5853 enum Apic_op op; 5854 u32 *apic_access_address; 5855 u32 reg; 5856 u32 val; 5857 bool check_rd; 5858 u32 (*virt_fn)(u32); 5859 } apic_reg_virt_guest_args; 5860 5861 static void apic_reg_virt_guest(void) 5862 { 5863 volatile struct apic_reg_virt_guest_args *args = 5864 &apic_reg_virt_guest_args; 5865 5866 for (;;) { 5867 enum Apic_op op = args->op; 5868 u32 *apic_access_address = args->apic_access_address; 5869 u32 reg = args->reg; 5870 u32 val = args->val; 5871 bool check_rd = args->check_rd; 5872 u32 (*virt_fn)(u32) = args->virt_fn; 5873 5874 if (op == TERMINATE) 5875 break; 5876 5877 if (op == APIC_OP_XAPIC_RD) { 5878 u32 ret = vmx_xapic_read(apic_access_address, reg); 5879 5880 if (check_rd) { 5881 u32 want = virt_fn(val); 5882 u32 got = virt_fn(ret); 5883 5884 report(got == want, 5885 "read 0x%x, expected 0x%x.", got, want); 5886 } 5887 } else if (op == APIC_OP_XAPIC_WR) { 5888 vmx_xapic_write(apic_access_address, reg, val); 5889 } 5890 5891 /* 5892 * The L1 should always execute a vmcall after it's done testing 5893 * an individual APIC operation. This helps to validate that the 5894 * L1 and L2 are in sync with each other, as expected. 5895 */ 5896 vmcall(); 5897 } 5898 } 5899 5900 static void test_xapic_rd( 5901 u32 reg, struct apic_reg_virt_expectation *expectation, 5902 u32 *apic_access_address, u32 *virtual_apic_page) 5903 { 5904 u32 val = expectation->val; 5905 u32 exit_reason_want = expectation->rd_exit_reason; 5906 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 5907 5908 report_prefix_pushf("xapic - reading 0x%03x", reg); 5909 5910 /* Configure guest to do an xapic read */ 5911 args->op = APIC_OP_XAPIC_RD; 5912 args->apic_access_address = apic_access_address; 5913 args->reg = reg; 5914 args->val = val; 5915 args->check_rd = exit_reason_want == VMX_VMCALL; 5916 args->virt_fn = expectation->virt_fn; 5917 5918 /* Setup virtual APIC page */ 5919 if (!expectation->virtualize_apic_accesses) { 5920 apic_access_address[apic_reg_index(reg)] = val; 5921 virtual_apic_page[apic_reg_index(reg)] = 0; 5922 } else if (exit_reason_want == VMX_VMCALL) { 5923 apic_access_address[apic_reg_index(reg)] = 0; 5924 virtual_apic_page[apic_reg_index(reg)] = val; 5925 } 5926 5927 /* Enter guest */ 5928 enter_guest(); 5929 5930 /* 5931 * Validate the behavior and 5932 * pass a magic value back to the guest. 5933 */ 5934 if (exit_reason_want == VMX_APIC_ACCESS) { 5935 u32 apic_page_offset = vmcs_read(EXI_QUALIFICATION) & 0xfff; 5936 5937 assert_exit_reason(exit_reason_want); 5938 report(apic_page_offset == reg, 5939 "got APIC access exit @ page offset 0x%03x, want 0x%03x", 5940 apic_page_offset, reg); 5941 skip_exit_insn(); 5942 5943 /* Reenter guest so it can consume/check rcx and exit again. */ 5944 enter_guest(); 5945 } else if (exit_reason_want != VMX_VMCALL) { 5946 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 5947 } 5948 5949 skip_exit_vmcall(); 5950 report_prefix_pop(); 5951 } 5952 5953 static void test_xapic_wr( 5954 u32 reg, struct apic_reg_virt_expectation *expectation, 5955 u32 *apic_access_address, u32 *virtual_apic_page) 5956 { 5957 u32 val = expectation->val; 5958 u32 exit_reason_want = expectation->wr_exit_reason; 5959 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 5960 bool virtualized = 5961 expectation->virtualize_apic_accesses && 5962 (exit_reason_want == VMX_APIC_WRITE || 5963 exit_reason_want == VMX_VMCALL); 5964 bool checked = false; 5965 5966 report_prefix_pushf("xapic - writing 0x%x to 0x%03x", val, reg); 5967 5968 /* Configure guest to do an xapic read */ 5969 args->op = APIC_OP_XAPIC_WR; 5970 args->apic_access_address = apic_access_address; 5971 args->reg = reg; 5972 args->val = val; 5973 5974 /* Setup virtual APIC page */ 5975 if (virtualized || !expectation->virtualize_apic_accesses) { 5976 apic_access_address[apic_reg_index(reg)] = 0; 5977 virtual_apic_page[apic_reg_index(reg)] = 0; 5978 } 5979 5980 /* Enter guest */ 5981 enter_guest(); 5982 5983 /* 5984 * Validate the behavior and 5985 * pass a magic value back to the guest. 5986 */ 5987 if (exit_reason_want == VMX_APIC_ACCESS) { 5988 u32 apic_page_offset = vmcs_read(EXI_QUALIFICATION) & 0xfff; 5989 5990 assert_exit_reason(exit_reason_want); 5991 report(apic_page_offset == reg, 5992 "got APIC access exit @ page offset 0x%03x, want 0x%03x", 5993 apic_page_offset, reg); 5994 skip_exit_insn(); 5995 5996 /* Reenter guest so it can consume/check rcx and exit again. */ 5997 enter_guest(); 5998 } else if (exit_reason_want == VMX_APIC_WRITE) { 5999 assert_exit_reason(exit_reason_want); 6000 report(virtual_apic_page[apic_reg_index(reg)] == val, 6001 "got APIC write exit @ page offset 0x%03x; val is 0x%x, want 0x%x", 6002 apic_reg_index(reg), 6003 virtual_apic_page[apic_reg_index(reg)], val); 6004 checked = true; 6005 6006 /* Reenter guest so it can consume/check rcx and exit again. */ 6007 enter_guest(); 6008 } else if (exit_reason_want != VMX_VMCALL) { 6009 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 6010 } 6011 6012 assert_exit_reason(VMX_VMCALL); 6013 if (virtualized && !checked) { 6014 u32 want = expectation->virt_fn(val); 6015 u32 got = virtual_apic_page[apic_reg_index(reg)]; 6016 got = expectation->virt_fn(got); 6017 6018 report(got == want, "exitless write; val is 0x%x, want 0x%x", 6019 got, want); 6020 } else if (!expectation->virtualize_apic_accesses && !checked) { 6021 u32 got = apic_access_address[apic_reg_index(reg)]; 6022 6023 report(got == val, 6024 "non-virtualized write; val is 0x%x, want 0x%x", got, 6025 val); 6026 } else if (!expectation->virtualize_apic_accesses && checked) { 6027 report_fail("Non-virtualized write was prematurely checked!"); 6028 } 6029 6030 skip_exit_vmcall(); 6031 report_prefix_pop(); 6032 } 6033 6034 enum Config_type { 6035 CONFIG_TYPE_GOOD, 6036 CONFIG_TYPE_UNSUPPORTED, 6037 CONFIG_TYPE_VMENTRY_FAILS_EARLY, 6038 }; 6039 6040 static enum Config_type configure_apic_reg_virt_test( 6041 struct apic_reg_virt_config *apic_reg_virt_config) 6042 { 6043 u32 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6044 u32 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6045 /* Configs where L2 entry fails early, due to invalid controls. */ 6046 bool use_tpr_shadow_incorrectly_off = 6047 !apic_reg_virt_config->use_tpr_shadow && 6048 (apic_reg_virt_config->apic_register_virtualization || 6049 apic_reg_virt_config->virtualize_x2apic_mode) && 6050 apic_reg_virt_config->activate_secondary_controls; 6051 bool virtualize_apic_accesses_incorrectly_on = 6052 apic_reg_virt_config->virtualize_apic_accesses && 6053 apic_reg_virt_config->virtualize_x2apic_mode && 6054 apic_reg_virt_config->activate_secondary_controls; 6055 bool vmentry_fails_early = 6056 use_tpr_shadow_incorrectly_off || 6057 virtualize_apic_accesses_incorrectly_on; 6058 6059 if (apic_reg_virt_config->activate_secondary_controls) { 6060 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 6061 printf("VM-execution control \"activate secondary controls\" NOT supported.\n"); 6062 return CONFIG_TYPE_UNSUPPORTED; 6063 } 6064 cpu_exec_ctrl0 |= CPU_SECONDARY; 6065 } else { 6066 cpu_exec_ctrl0 &= ~CPU_SECONDARY; 6067 } 6068 6069 if (apic_reg_virt_config->virtualize_apic_accesses) { 6070 if (!(ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES)) { 6071 printf("VM-execution control \"virtualize APIC accesses\" NOT supported.\n"); 6072 return CONFIG_TYPE_UNSUPPORTED; 6073 } 6074 cpu_exec_ctrl1 |= CPU_VIRT_APIC_ACCESSES; 6075 } else { 6076 cpu_exec_ctrl1 &= ~CPU_VIRT_APIC_ACCESSES; 6077 } 6078 6079 if (apic_reg_virt_config->use_tpr_shadow) { 6080 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) { 6081 printf("VM-execution control \"use TPR shadow\" NOT supported.\n"); 6082 return CONFIG_TYPE_UNSUPPORTED; 6083 } 6084 cpu_exec_ctrl0 |= CPU_TPR_SHADOW; 6085 } else { 6086 cpu_exec_ctrl0 &= ~CPU_TPR_SHADOW; 6087 } 6088 6089 if (apic_reg_virt_config->apic_register_virtualization) { 6090 if (!(ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT)) { 6091 printf("VM-execution control \"APIC-register virtualization\" NOT supported.\n"); 6092 return CONFIG_TYPE_UNSUPPORTED; 6093 } 6094 cpu_exec_ctrl1 |= CPU_APIC_REG_VIRT; 6095 } else { 6096 cpu_exec_ctrl1 &= ~CPU_APIC_REG_VIRT; 6097 } 6098 6099 if (apic_reg_virt_config->virtualize_x2apic_mode) { 6100 if (!(ctrl_cpu_rev[1].clr & CPU_VIRT_X2APIC)) { 6101 printf("VM-execution control \"virtualize x2APIC mode\" NOT supported.\n"); 6102 return CONFIG_TYPE_UNSUPPORTED; 6103 } 6104 cpu_exec_ctrl1 |= CPU_VIRT_X2APIC; 6105 } else { 6106 cpu_exec_ctrl1 &= ~CPU_VIRT_X2APIC; 6107 } 6108 6109 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6110 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6111 6112 if (vmentry_fails_early) 6113 return CONFIG_TYPE_VMENTRY_FAILS_EARLY; 6114 6115 return CONFIG_TYPE_GOOD; 6116 } 6117 6118 static bool cpu_has_apicv(void) 6119 { 6120 return ((ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT) && 6121 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 6122 (ctrl_pin_rev.clr & PIN_POST_INTR)); 6123 } 6124 6125 /* Validates APIC register access across valid virtualization configurations. */ 6126 static void apic_reg_virt_test(void) 6127 { 6128 u32 *apic_access_address; 6129 u32 *virtual_apic_page; 6130 u64 control; 6131 u64 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6132 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6133 int i; 6134 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 6135 6136 if (!cpu_has_apicv()) { 6137 report_skip(__func__); 6138 return; 6139 } 6140 6141 control = cpu_exec_ctrl1; 6142 control &= ~CPU_VINTD; 6143 vmcs_write(CPU_EXEC_CTRL1, control); 6144 6145 test_set_guest(apic_reg_virt_guest); 6146 6147 /* 6148 * From the SDM: The 1-setting of the "virtualize APIC accesses" 6149 * VM-execution is guaranteed to apply only if translations to the 6150 * APIC-access address use a 4-KByte page. 6151 */ 6152 apic_access_address = alloc_page(); 6153 force_4k_page(apic_access_address); 6154 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_address)); 6155 6156 virtual_apic_page = alloc_page(); 6157 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 6158 6159 for (i = 0; i < ARRAY_SIZE(apic_reg_tests); i++) { 6160 struct apic_reg_test *apic_reg_test = &apic_reg_tests[i]; 6161 struct apic_reg_virt_config *apic_reg_virt_config = 6162 &apic_reg_test->apic_reg_virt_config; 6163 enum Config_type config_type; 6164 u32 reg; 6165 6166 printf("--- %s test ---\n", apic_reg_test->name); 6167 config_type = 6168 configure_apic_reg_virt_test(apic_reg_virt_config); 6169 if (config_type == CONFIG_TYPE_UNSUPPORTED) { 6170 printf("Skip because of missing features.\n"); 6171 continue; 6172 } 6173 6174 if (config_type == CONFIG_TYPE_VMENTRY_FAILS_EARLY) { 6175 enter_guest_with_bad_controls(); 6176 continue; 6177 } 6178 6179 for (reg = 0; reg < PAGE_SIZE / sizeof(u32); reg += 0x10) { 6180 struct apic_reg_virt_expectation expectation = {}; 6181 bool ok; 6182 6183 ok = apic_reg_virt_exit_expectation( 6184 reg, apic_reg_virt_config, &expectation); 6185 if (!ok) { 6186 report_fail("Malformed test."); 6187 break; 6188 } 6189 6190 test_xapic_rd(reg, &expectation, apic_access_address, 6191 virtual_apic_page); 6192 test_xapic_wr(reg, &expectation, apic_access_address, 6193 virtual_apic_page); 6194 } 6195 } 6196 6197 /* Terminate the guest */ 6198 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6199 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6200 args->op = TERMINATE; 6201 enter_guest(); 6202 assert_exit_reason(VMX_VMCALL); 6203 } 6204 6205 struct virt_x2apic_mode_config { 6206 struct apic_reg_virt_config apic_reg_virt_config; 6207 bool virtual_interrupt_delivery; 6208 bool use_msr_bitmaps; 6209 bool disable_x2apic_msr_intercepts; 6210 bool disable_x2apic; 6211 }; 6212 6213 struct virt_x2apic_mode_test_case { 6214 const char *name; 6215 struct virt_x2apic_mode_config virt_x2apic_mode_config; 6216 }; 6217 6218 enum Virt_x2apic_mode_behavior_type { 6219 X2APIC_ACCESS_VIRTUALIZED, 6220 X2APIC_ACCESS_PASSED_THROUGH, 6221 X2APIC_ACCESS_TRIGGERS_GP, 6222 }; 6223 6224 struct virt_x2apic_mode_expectation { 6225 enum Reason rd_exit_reason; 6226 enum Reason wr_exit_reason; 6227 6228 /* 6229 * RDMSR and WRMSR handle 64-bit values. However, except for ICR, all of 6230 * the x2APIC registers are 32 bits. Notice: 6231 * 1. vmx_x2apic_read() clears the upper 32 bits for 32-bit registers. 6232 * 2. vmx_x2apic_write() expects the val arg to be well-formed. 6233 */ 6234 u64 rd_val; 6235 u64 wr_val; 6236 6237 /* 6238 * Compares input to virtualized output; 6239 * 1st arg is pointer to return expected virtualization output. 6240 */ 6241 u64 (*virt_fn)(u64); 6242 6243 enum Virt_x2apic_mode_behavior_type rd_behavior; 6244 enum Virt_x2apic_mode_behavior_type wr_behavior; 6245 bool wr_only; 6246 }; 6247 6248 static u64 virt_x2apic_mode_identity(u64 val) 6249 { 6250 return val; 6251 } 6252 6253 static u64 virt_x2apic_mode_nibble1(u64 val) 6254 { 6255 return val & 0xf0; 6256 } 6257 6258 static void virt_x2apic_mode_rd_expectation( 6259 u32 reg, bool virt_x2apic_mode_on, bool disable_x2apic, 6260 bool apic_register_virtualization, bool virtual_interrupt_delivery, 6261 struct virt_x2apic_mode_expectation *expectation) 6262 { 6263 bool readable = 6264 !x2apic_reg_reserved(reg) && 6265 reg != APIC_EOI; 6266 6267 expectation->rd_exit_reason = VMX_VMCALL; 6268 expectation->virt_fn = virt_x2apic_mode_identity; 6269 if (virt_x2apic_mode_on && apic_register_virtualization) { 6270 expectation->rd_val = MAGIC_VAL_1; 6271 if (reg == APIC_PROCPRI && virtual_interrupt_delivery) 6272 expectation->virt_fn = virt_x2apic_mode_nibble1; 6273 else if (reg == APIC_TASKPRI) 6274 expectation->virt_fn = virt_x2apic_mode_nibble1; 6275 expectation->rd_behavior = X2APIC_ACCESS_VIRTUALIZED; 6276 } else if (virt_x2apic_mode_on && !apic_register_virtualization && 6277 reg == APIC_TASKPRI) { 6278 expectation->rd_val = MAGIC_VAL_1; 6279 expectation->virt_fn = virt_x2apic_mode_nibble1; 6280 expectation->rd_behavior = X2APIC_ACCESS_VIRTUALIZED; 6281 } else if (!disable_x2apic && readable) { 6282 expectation->rd_val = apic_read(reg); 6283 expectation->rd_behavior = X2APIC_ACCESS_PASSED_THROUGH; 6284 } else { 6285 expectation->rd_behavior = X2APIC_ACCESS_TRIGGERS_GP; 6286 } 6287 } 6288 6289 /* 6290 * get_x2apic_wr_val() creates an innocuous write value for an x2APIC register. 6291 * 6292 * For writable registers, get_x2apic_wr_val() deposits the write value into the 6293 * val pointer arg and returns true. For non-writable registers, val is not 6294 * modified and get_x2apic_wr_val() returns false. 6295 */ 6296 static bool get_x2apic_wr_val(u32 reg, u64 *val) 6297 { 6298 switch (reg) { 6299 case APIC_TASKPRI: 6300 /* Bits 31:8 are reserved. */ 6301 *val &= 0xff; 6302 break; 6303 case APIC_EOI: 6304 case APIC_ESR: 6305 case APIC_TMICT: 6306 /* 6307 * EOI, ESR: WRMSR of a non-zero value causes #GP(0). 6308 * TMICT: A write of 0 to the initial-count register effectively 6309 * stops the local APIC timer, in both one-shot and 6310 * periodic mode. 6311 */ 6312 *val = 0; 6313 break; 6314 case APIC_SPIV: 6315 case APIC_LVTT: 6316 case APIC_LVTTHMR: 6317 case APIC_LVTPC: 6318 case APIC_LVT0: 6319 case APIC_LVT1: 6320 case APIC_LVTERR: 6321 case APIC_TDCR: 6322 /* 6323 * To avoid writing a 1 to a reserved bit or causing some other 6324 * unintended side effect, read the current value and use it as 6325 * the write value. 6326 */ 6327 *val = apic_read(reg); 6328 break; 6329 case APIC_CMCI: 6330 if (!apic_lvt_entry_supported(6)) 6331 return false; 6332 *val = apic_read(reg); 6333 break; 6334 case APIC_ICR: 6335 *val = 0x40000 | 0xf1; 6336 break; 6337 case APIC_SELF_IPI: 6338 /* 6339 * With special processing (i.e., virtualize x2APIC mode + 6340 * virtual interrupt delivery), writing zero causes an 6341 * APIC-write VM exit. We plan to add a test for enabling 6342 * "virtual-interrupt delivery" in VMCS12, and that's where we 6343 * will test a self IPI with special processing. 6344 */ 6345 *val = 0x0; 6346 break; 6347 default: 6348 return false; 6349 } 6350 6351 return true; 6352 } 6353 6354 static bool special_processing_applies(u32 reg, u64 *val, 6355 bool virt_int_delivery) 6356 { 6357 bool special_processing = 6358 (reg == APIC_TASKPRI) || 6359 (virt_int_delivery && 6360 (reg == APIC_EOI || reg == APIC_SELF_IPI)); 6361 6362 if (special_processing) { 6363 TEST_ASSERT(get_x2apic_wr_val(reg, val)); 6364 return true; 6365 } 6366 6367 return false; 6368 } 6369 6370 static void virt_x2apic_mode_wr_expectation( 6371 u32 reg, bool virt_x2apic_mode_on, bool disable_x2apic, 6372 bool virt_int_delivery, 6373 struct virt_x2apic_mode_expectation *expectation) 6374 { 6375 expectation->wr_exit_reason = VMX_VMCALL; 6376 expectation->wr_val = MAGIC_VAL_1; 6377 expectation->wr_only = false; 6378 6379 if (virt_x2apic_mode_on && 6380 special_processing_applies(reg, &expectation->wr_val, 6381 virt_int_delivery)) { 6382 expectation->wr_behavior = X2APIC_ACCESS_VIRTUALIZED; 6383 if (reg == APIC_SELF_IPI) 6384 expectation->wr_exit_reason = VMX_APIC_WRITE; 6385 } else if (!disable_x2apic && 6386 get_x2apic_wr_val(reg, &expectation->wr_val)) { 6387 expectation->wr_behavior = X2APIC_ACCESS_PASSED_THROUGH; 6388 if (reg == APIC_EOI || reg == APIC_SELF_IPI) 6389 expectation->wr_only = true; 6390 if (reg == APIC_ICR) 6391 expectation->wr_exit_reason = VMX_EXTINT; 6392 } else { 6393 expectation->wr_behavior = X2APIC_ACCESS_TRIGGERS_GP; 6394 /* 6395 * Writing 1 to a reserved bit triggers a #GP. 6396 * Thus, set the write value to 0, which seems 6397 * the most likely to detect a missed #GP. 6398 */ 6399 expectation->wr_val = 0; 6400 } 6401 } 6402 6403 static void virt_x2apic_mode_exit_expectation( 6404 u32 reg, struct virt_x2apic_mode_config *config, 6405 struct virt_x2apic_mode_expectation *expectation) 6406 { 6407 struct apic_reg_virt_config *base_config = 6408 &config->apic_reg_virt_config; 6409 bool virt_x2apic_mode_on = 6410 base_config->virtualize_x2apic_mode && 6411 config->use_msr_bitmaps && 6412 config->disable_x2apic_msr_intercepts && 6413 base_config->activate_secondary_controls; 6414 6415 virt_x2apic_mode_wr_expectation( 6416 reg, virt_x2apic_mode_on, config->disable_x2apic, 6417 config->virtual_interrupt_delivery, expectation); 6418 virt_x2apic_mode_rd_expectation( 6419 reg, virt_x2apic_mode_on, config->disable_x2apic, 6420 base_config->apic_register_virtualization, 6421 config->virtual_interrupt_delivery, expectation); 6422 } 6423 6424 struct virt_x2apic_mode_test_case virt_x2apic_mode_tests[] = { 6425 /* 6426 * Baseline "virtualize x2APIC mode" configuration: 6427 * - virtualize x2APIC mode 6428 * - virtual-interrupt delivery 6429 * - APIC-register virtualization 6430 * - x2APIC MSR intercepts disabled 6431 * 6432 * Reads come from virtual APIC page, special processing applies to 6433 * VTPR, EOI, and SELF IPI, and all other writes pass through to L1 6434 * APIC. 6435 */ 6436 { 6437 .name = "Baseline", 6438 .virt_x2apic_mode_config = { 6439 .virtual_interrupt_delivery = true, 6440 .use_msr_bitmaps = true, 6441 .disable_x2apic_msr_intercepts = true, 6442 .disable_x2apic = false, 6443 .apic_reg_virt_config = { 6444 .apic_register_virtualization = true, 6445 .use_tpr_shadow = true, 6446 .virtualize_apic_accesses = false, 6447 .virtualize_x2apic_mode = true, 6448 .activate_secondary_controls = true, 6449 }, 6450 }, 6451 }, 6452 { 6453 .name = "Baseline w/ x2apic disabled", 6454 .virt_x2apic_mode_config = { 6455 .virtual_interrupt_delivery = true, 6456 .use_msr_bitmaps = true, 6457 .disable_x2apic_msr_intercepts = true, 6458 .disable_x2apic = true, 6459 .apic_reg_virt_config = { 6460 .apic_register_virtualization = true, 6461 .use_tpr_shadow = true, 6462 .virtualize_apic_accesses = false, 6463 .virtualize_x2apic_mode = true, 6464 .activate_secondary_controls = true, 6465 }, 6466 }, 6467 }, 6468 6469 /* 6470 * Baseline, minus virtual-interrupt delivery. Reads come from virtual 6471 * APIC page, special processing applies to VTPR, and all other writes 6472 * pass through to L1 APIC. 6473 */ 6474 { 6475 .name = "Baseline - virtual interrupt delivery", 6476 .virt_x2apic_mode_config = { 6477 .virtual_interrupt_delivery = false, 6478 .use_msr_bitmaps = true, 6479 .disable_x2apic_msr_intercepts = true, 6480 .disable_x2apic = false, 6481 .apic_reg_virt_config = { 6482 .apic_register_virtualization = true, 6483 .use_tpr_shadow = true, 6484 .virtualize_apic_accesses = false, 6485 .virtualize_x2apic_mode = true, 6486 .activate_secondary_controls = true, 6487 }, 6488 }, 6489 }, 6490 6491 /* 6492 * Baseline, minus APIC-register virtualization. x2APIC reads pass 6493 * through to L1's APIC, unless reading VTPR 6494 */ 6495 { 6496 .name = "Virtualize x2APIC mode, no APIC reg virt", 6497 .virt_x2apic_mode_config = { 6498 .virtual_interrupt_delivery = true, 6499 .use_msr_bitmaps = true, 6500 .disable_x2apic_msr_intercepts = true, 6501 .disable_x2apic = false, 6502 .apic_reg_virt_config = { 6503 .apic_register_virtualization = false, 6504 .use_tpr_shadow = true, 6505 .virtualize_apic_accesses = false, 6506 .virtualize_x2apic_mode = true, 6507 .activate_secondary_controls = true, 6508 }, 6509 }, 6510 }, 6511 { 6512 .name = "Virtualize x2APIC mode, no APIC reg virt, x2APIC off", 6513 .virt_x2apic_mode_config = { 6514 .virtual_interrupt_delivery = true, 6515 .use_msr_bitmaps = true, 6516 .disable_x2apic_msr_intercepts = true, 6517 .disable_x2apic = true, 6518 .apic_reg_virt_config = { 6519 .apic_register_virtualization = false, 6520 .use_tpr_shadow = true, 6521 .virtualize_apic_accesses = false, 6522 .virtualize_x2apic_mode = true, 6523 .activate_secondary_controls = true, 6524 }, 6525 }, 6526 }, 6527 6528 /* 6529 * Enable "virtualize x2APIC mode" and "APIC-register virtualization", 6530 * and disable intercepts for the x2APIC MSRs, but fail to enable 6531 * "activate secondary controls" (i.e. L2 gets access to L1's x2APIC 6532 * MSRs). 6533 */ 6534 { 6535 .name = "Fail to enable activate secondary controls", 6536 .virt_x2apic_mode_config = { 6537 .virtual_interrupt_delivery = true, 6538 .use_msr_bitmaps = true, 6539 .disable_x2apic_msr_intercepts = true, 6540 .disable_x2apic = false, 6541 .apic_reg_virt_config = { 6542 .apic_register_virtualization = true, 6543 .use_tpr_shadow = true, 6544 .virtualize_apic_accesses = false, 6545 .virtualize_x2apic_mode = true, 6546 .activate_secondary_controls = false, 6547 }, 6548 }, 6549 }, 6550 6551 /* 6552 * Enable "APIC-register virtualization" and enable "activate secondary 6553 * controls" and disable intercepts for the x2APIC MSRs, but do not 6554 * enable the "virtualize x2APIC mode" VM-execution control (i.e. L2 6555 * gets access to L1's x2APIC MSRs). 6556 */ 6557 { 6558 .name = "Fail to enable virtualize x2APIC mode", 6559 .virt_x2apic_mode_config = { 6560 .virtual_interrupt_delivery = true, 6561 .use_msr_bitmaps = true, 6562 .disable_x2apic_msr_intercepts = true, 6563 .disable_x2apic = false, 6564 .apic_reg_virt_config = { 6565 .apic_register_virtualization = true, 6566 .use_tpr_shadow = true, 6567 .virtualize_apic_accesses = false, 6568 .virtualize_x2apic_mode = false, 6569 .activate_secondary_controls = true, 6570 }, 6571 }, 6572 }, 6573 6574 /* 6575 * Disable "Virtualize x2APIC mode", disable x2APIC MSR intercepts, and 6576 * enable "APIC-register virtualization" --> L2 gets L1's x2APIC MSRs. 6577 */ 6578 { 6579 .name = "Baseline", 6580 .virt_x2apic_mode_config = { 6581 .virtual_interrupt_delivery = true, 6582 .use_msr_bitmaps = true, 6583 .disable_x2apic_msr_intercepts = true, 6584 .disable_x2apic = false, 6585 .apic_reg_virt_config = { 6586 .apic_register_virtualization = true, 6587 .use_tpr_shadow = true, 6588 .virtualize_apic_accesses = false, 6589 .virtualize_x2apic_mode = false, 6590 .activate_secondary_controls = true, 6591 }, 6592 }, 6593 }, 6594 }; 6595 6596 enum X2apic_op { 6597 X2APIC_OP_RD, 6598 X2APIC_OP_WR, 6599 X2APIC_TERMINATE, 6600 }; 6601 6602 static u64 vmx_x2apic_read(u32 reg) 6603 { 6604 u32 msr_addr = x2apic_msr(reg); 6605 u64 val; 6606 6607 val = rdmsr(msr_addr); 6608 6609 return val; 6610 } 6611 6612 static void vmx_x2apic_write(u32 reg, u64 val) 6613 { 6614 u32 msr_addr = x2apic_msr(reg); 6615 6616 wrmsr(msr_addr, val); 6617 } 6618 6619 struct virt_x2apic_mode_guest_args { 6620 enum X2apic_op op; 6621 u32 reg; 6622 u64 val; 6623 bool should_gp; 6624 u64 (*virt_fn)(u64); 6625 } virt_x2apic_mode_guest_args; 6626 6627 static volatile bool handle_x2apic_gp_ran; 6628 static volatile u32 handle_x2apic_gp_insn_len; 6629 static void handle_x2apic_gp(struct ex_regs *regs) 6630 { 6631 handle_x2apic_gp_ran = true; 6632 regs->rip += handle_x2apic_gp_insn_len; 6633 } 6634 6635 static handler setup_x2apic_gp_handler(void) 6636 { 6637 handler old_handler; 6638 6639 old_handler = handle_exception(GP_VECTOR, handle_x2apic_gp); 6640 /* RDMSR and WRMSR are both 2 bytes, assuming no prefixes. */ 6641 handle_x2apic_gp_insn_len = 2; 6642 6643 return old_handler; 6644 } 6645 6646 static void teardown_x2apic_gp_handler(handler old_handler) 6647 { 6648 handle_exception(GP_VECTOR, old_handler); 6649 6650 /* 6651 * Defensively reset instruction length, so that if the handler is 6652 * incorrectly used, it will loop infinitely, rather than run off into 6653 * la la land. 6654 */ 6655 handle_x2apic_gp_insn_len = 0; 6656 handle_x2apic_gp_ran = false; 6657 } 6658 6659 static void virt_x2apic_mode_guest(void) 6660 { 6661 volatile struct virt_x2apic_mode_guest_args *args = 6662 &virt_x2apic_mode_guest_args; 6663 6664 for (;;) { 6665 enum X2apic_op op = args->op; 6666 u32 reg = args->reg; 6667 u64 val = args->val; 6668 bool should_gp = args->should_gp; 6669 u64 (*virt_fn)(u64) = args->virt_fn; 6670 handler old_handler; 6671 6672 if (op == X2APIC_TERMINATE) 6673 break; 6674 6675 if (should_gp) { 6676 TEST_ASSERT(!handle_x2apic_gp_ran); 6677 old_handler = setup_x2apic_gp_handler(); 6678 } 6679 6680 if (op == X2APIC_OP_RD) { 6681 u64 ret = vmx_x2apic_read(reg); 6682 6683 if (!should_gp) { 6684 u64 want = virt_fn(val); 6685 u64 got = virt_fn(ret); 6686 6687 report(got == want, 6688 "APIC read; got 0x%lx, want 0x%lx.", 6689 got, want); 6690 } 6691 } else if (op == X2APIC_OP_WR) { 6692 vmx_x2apic_write(reg, val); 6693 } 6694 6695 if (should_gp) { 6696 report(handle_x2apic_gp_ran, 6697 "x2APIC op triggered GP."); 6698 teardown_x2apic_gp_handler(old_handler); 6699 } 6700 6701 /* 6702 * The L1 should always execute a vmcall after it's done testing 6703 * an individual APIC operation. This helps to validate that the 6704 * L1 and L2 are in sync with each other, as expected. 6705 */ 6706 vmcall(); 6707 } 6708 } 6709 6710 static void test_x2apic_rd( 6711 u32 reg, struct virt_x2apic_mode_expectation *expectation, 6712 u32 *virtual_apic_page) 6713 { 6714 u64 val = expectation->rd_val; 6715 u32 exit_reason_want = expectation->rd_exit_reason; 6716 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6717 6718 report_prefix_pushf("x2apic - reading 0x%03x", reg); 6719 6720 /* Configure guest to do an x2apic read */ 6721 args->op = X2APIC_OP_RD; 6722 args->reg = reg; 6723 args->val = val; 6724 args->should_gp = expectation->rd_behavior == X2APIC_ACCESS_TRIGGERS_GP; 6725 args->virt_fn = expectation->virt_fn; 6726 6727 /* Setup virtual APIC page */ 6728 if (expectation->rd_behavior == X2APIC_ACCESS_VIRTUALIZED) 6729 virtual_apic_page[apic_reg_index(reg)] = (u32)val; 6730 6731 /* Enter guest */ 6732 enter_guest(); 6733 6734 if (exit_reason_want != VMX_VMCALL) { 6735 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 6736 } 6737 6738 skip_exit_vmcall(); 6739 report_prefix_pop(); 6740 } 6741 6742 static volatile bool handle_x2apic_ipi_ran; 6743 static void handle_x2apic_ipi(isr_regs_t *regs) 6744 { 6745 handle_x2apic_ipi_ran = true; 6746 eoi(); 6747 } 6748 6749 static void test_x2apic_wr( 6750 u32 reg, struct virt_x2apic_mode_expectation *expectation, 6751 u32 *virtual_apic_page) 6752 { 6753 u64 val = expectation->wr_val; 6754 u32 exit_reason_want = expectation->wr_exit_reason; 6755 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6756 int ipi_vector = 0xf1; 6757 u32 restore_val = 0; 6758 6759 report_prefix_pushf("x2apic - writing 0x%lx to 0x%03x", val, reg); 6760 6761 /* Configure guest to do an x2apic read */ 6762 args->op = X2APIC_OP_WR; 6763 args->reg = reg; 6764 args->val = val; 6765 args->should_gp = expectation->wr_behavior == X2APIC_ACCESS_TRIGGERS_GP; 6766 6767 /* Setup virtual APIC page */ 6768 if (expectation->wr_behavior == X2APIC_ACCESS_VIRTUALIZED) 6769 virtual_apic_page[apic_reg_index(reg)] = 0; 6770 if (expectation->wr_behavior == X2APIC_ACCESS_PASSED_THROUGH && !expectation->wr_only) 6771 restore_val = apic_read(reg); 6772 6773 /* Setup IPI handler */ 6774 handle_x2apic_ipi_ran = false; 6775 handle_irq(ipi_vector, handle_x2apic_ipi); 6776 6777 /* Enter guest */ 6778 enter_guest(); 6779 6780 /* 6781 * Validate the behavior and 6782 * pass a magic value back to the guest. 6783 */ 6784 if (exit_reason_want == VMX_EXTINT) { 6785 assert_exit_reason(exit_reason_want); 6786 6787 /* Clear the external interrupt. */ 6788 irq_enable(); 6789 asm volatile ("nop"); 6790 irq_disable(); 6791 report(handle_x2apic_ipi_ran, 6792 "Got pending interrupt after IRQ enabled."); 6793 6794 enter_guest(); 6795 } else if (exit_reason_want == VMX_APIC_WRITE) { 6796 assert_exit_reason(exit_reason_want); 6797 report(virtual_apic_page[apic_reg_index(reg)] == val, 6798 "got APIC write exit @ page offset 0x%03x; val is 0x%x, want 0x%lx", 6799 apic_reg_index(reg), 6800 virtual_apic_page[apic_reg_index(reg)], val); 6801 6802 /* Reenter guest so it can consume/check rcx and exit again. */ 6803 enter_guest(); 6804 } else if (exit_reason_want != VMX_VMCALL) { 6805 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 6806 } 6807 6808 assert_exit_reason(VMX_VMCALL); 6809 if (expectation->wr_behavior == X2APIC_ACCESS_VIRTUALIZED) { 6810 u64 want = val; 6811 u32 got = virtual_apic_page[apic_reg_index(reg)]; 6812 6813 report(got == want, "x2APIC write; got 0x%x, want 0x%lx", got, 6814 want); 6815 } else if (expectation->wr_behavior == X2APIC_ACCESS_PASSED_THROUGH) { 6816 if (!expectation->wr_only) { 6817 u32 got = apic_read(reg); 6818 bool ok; 6819 6820 /* 6821 * When L1's TPR is passed through to L2, the lower 6822 * nibble can be lost. For example, if L2 executes 6823 * WRMSR(0x808, 0x78), then, L1 might read 0x70. 6824 * 6825 * Here's how the lower nibble can get lost: 6826 * 1. L2 executes WRMSR(0x808, 0x78). 6827 * 2. L2 exits to L0 with a WRMSR exit. 6828 * 3. L0 emulates WRMSR, by writing L1's TPR. 6829 * 4. L0 re-enters L2. 6830 * 5. L2 exits to L0 (reason doesn't matter). 6831 * 6. L0 reflects L2's exit to L1. 6832 * 7. Before entering L1, L0 exits to user-space 6833 * (e.g., to satisfy TPR access reporting). 6834 * 8. User-space executes KVM_SET_REGS ioctl, which 6835 * clears the lower nibble of L1's TPR. 6836 */ 6837 if (reg == APIC_TASKPRI) { 6838 got = apic_virt_nibble1(got); 6839 val = apic_virt_nibble1(val); 6840 } 6841 6842 ok = got == val; 6843 report(ok, 6844 "non-virtualized write; val is 0x%x, want 0x%lx", 6845 got, val); 6846 apic_write(reg, restore_val); 6847 } else { 6848 report_pass("non-virtualized and write-only OK"); 6849 } 6850 } 6851 skip_exit_insn(); 6852 6853 report_prefix_pop(); 6854 } 6855 6856 static enum Config_type configure_virt_x2apic_mode_test( 6857 struct virt_x2apic_mode_config *virt_x2apic_mode_config, 6858 u8 *msr_bitmap_page) 6859 { 6860 int msr; 6861 u32 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6862 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6863 6864 /* x2apic-specific VMCS config */ 6865 if (virt_x2apic_mode_config->use_msr_bitmaps) { 6866 /* virt_x2apic_mode_test() checks for MSR bitmaps support */ 6867 cpu_exec_ctrl0 |= CPU_MSR_BITMAP; 6868 } else { 6869 cpu_exec_ctrl0 &= ~CPU_MSR_BITMAP; 6870 } 6871 6872 if (virt_x2apic_mode_config->virtual_interrupt_delivery) { 6873 if (!(ctrl_cpu_rev[1].clr & CPU_VINTD)) { 6874 report_skip("VM-execution control \"virtual-interrupt delivery\" NOT supported.\n"); 6875 return CONFIG_TYPE_UNSUPPORTED; 6876 } 6877 cpu_exec_ctrl1 |= CPU_VINTD; 6878 } else { 6879 cpu_exec_ctrl1 &= ~CPU_VINTD; 6880 } 6881 6882 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6883 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6884 6885 /* x2APIC MSR intercepts are usually off for "Virtualize x2APIC mode" */ 6886 for (msr = 0x800; msr <= 0x8ff; msr++) { 6887 if (virt_x2apic_mode_config->disable_x2apic_msr_intercepts) { 6888 clear_bit(msr, msr_bitmap_page + 0x000); 6889 clear_bit(msr, msr_bitmap_page + 0x800); 6890 } else { 6891 set_bit(msr, msr_bitmap_page + 0x000); 6892 set_bit(msr, msr_bitmap_page + 0x800); 6893 } 6894 } 6895 6896 /* x2APIC mode can impact virtualization */ 6897 reset_apic(); 6898 if (!virt_x2apic_mode_config->disable_x2apic) 6899 enable_x2apic(); 6900 6901 return configure_apic_reg_virt_test( 6902 &virt_x2apic_mode_config->apic_reg_virt_config); 6903 } 6904 6905 static void virt_x2apic_mode_test(void) 6906 { 6907 u32 *virtual_apic_page; 6908 u8 *msr_bitmap_page; 6909 u64 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6910 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6911 int i; 6912 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6913 6914 if (!cpu_has_apicv()) { 6915 report_skip(__func__); 6916 return; 6917 } 6918 6919 /* 6920 * This is to exercise an issue in KVM's logic to merge L0's and L1's 6921 * MSR bitmaps. Previously, an L1 could get at L0's x2APIC MSRs by 6922 * writing the IA32_SPEC_CTRL MSR or the IA32_PRED_CMD MSRs. KVM would 6923 * then proceed to manipulate the MSR bitmaps, as if VMCS12 had the 6924 * "Virtualize x2APIC mod" control set, even when it didn't. 6925 */ 6926 if (has_spec_ctrl()) 6927 wrmsr(MSR_IA32_SPEC_CTRL, 1); 6928 6929 /* 6930 * Check that VMCS12 supports: 6931 * - "Virtual-APIC address", indicated by "use TPR shadow" 6932 * - "MSR-bitmap address", indicated by "use MSR bitmaps" 6933 */ 6934 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) { 6935 report_skip("VM-execution control \"use TPR shadow\" NOT supported.\n"); 6936 return; 6937 } else if (!(ctrl_cpu_rev[0].clr & CPU_MSR_BITMAP)) { 6938 report_skip("VM-execution control \"use MSR bitmaps\" NOT supported.\n"); 6939 return; 6940 } 6941 6942 test_set_guest(virt_x2apic_mode_guest); 6943 6944 virtual_apic_page = alloc_page(); 6945 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 6946 6947 msr_bitmap_page = alloc_page(); 6948 memset(msr_bitmap_page, 0xff, PAGE_SIZE); 6949 vmcs_write(MSR_BITMAP, virt_to_phys(msr_bitmap_page)); 6950 6951 for (i = 0; i < ARRAY_SIZE(virt_x2apic_mode_tests); i++) { 6952 struct virt_x2apic_mode_test_case *virt_x2apic_mode_test_case = 6953 &virt_x2apic_mode_tests[i]; 6954 struct virt_x2apic_mode_config *virt_x2apic_mode_config = 6955 &virt_x2apic_mode_test_case->virt_x2apic_mode_config; 6956 enum Config_type config_type; 6957 u32 reg; 6958 6959 printf("--- %s test ---\n", virt_x2apic_mode_test_case->name); 6960 config_type = 6961 configure_virt_x2apic_mode_test(virt_x2apic_mode_config, 6962 msr_bitmap_page); 6963 if (config_type == CONFIG_TYPE_UNSUPPORTED) { 6964 report_skip("Skip because of missing features.\n"); 6965 continue; 6966 } else if (config_type == CONFIG_TYPE_VMENTRY_FAILS_EARLY) { 6967 enter_guest_with_bad_controls(); 6968 continue; 6969 } 6970 6971 for (reg = 0; reg < PAGE_SIZE / sizeof(u32); reg += 0x10) { 6972 struct virt_x2apic_mode_expectation expectation; 6973 6974 virt_x2apic_mode_exit_expectation( 6975 reg, virt_x2apic_mode_config, &expectation); 6976 6977 test_x2apic_rd(reg, &expectation, virtual_apic_page); 6978 test_x2apic_wr(reg, &expectation, virtual_apic_page); 6979 } 6980 } 6981 6982 6983 /* Terminate the guest */ 6984 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6985 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6986 args->op = X2APIC_TERMINATE; 6987 enter_guest(); 6988 assert_exit_reason(VMX_VMCALL); 6989 } 6990 6991 static void test_ctl_reg(const char *cr_name, u64 cr, u64 fixed0, u64 fixed1) 6992 { 6993 u64 val; 6994 u64 cr_saved = vmcs_read(cr); 6995 int i; 6996 6997 val = fixed0 & fixed1; 6998 if (cr == HOST_CR4) 6999 vmcs_write(cr, val | X86_CR4_PAE); 7000 else 7001 vmcs_write(cr, val); 7002 report_prefix_pushf("%s %lx", cr_name, val); 7003 if (val == fixed0) 7004 test_vmx_vmlaunch(0); 7005 else 7006 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7007 report_prefix_pop(); 7008 7009 for (i = 0; i < 64; i++) { 7010 7011 /* Set a bit when the corresponding bit in fixed1 is 0 */ 7012 if ((fixed1 & (1ull << i)) == 0) { 7013 if (cr == HOST_CR4 && ((1ull << i) & X86_CR4_SMEP || 7014 (1ull << i) & X86_CR4_SMAP)) 7015 continue; 7016 7017 vmcs_write(cr, cr_saved | (1ull << i)); 7018 report_prefix_pushf("%s %llx", cr_name, 7019 cr_saved | (1ull << i)); 7020 test_vmx_vmlaunch( 7021 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7022 report_prefix_pop(); 7023 } 7024 7025 /* Unset a bit when the corresponding bit in fixed0 is 1 */ 7026 if (fixed0 & (1ull << i)) { 7027 vmcs_write(cr, cr_saved & ~(1ull << i)); 7028 report_prefix_pushf("%s %llx", cr_name, 7029 cr_saved & ~(1ull << i)); 7030 test_vmx_vmlaunch( 7031 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7032 report_prefix_pop(); 7033 } 7034 } 7035 7036 vmcs_write(cr, cr_saved); 7037 } 7038 7039 /* 7040 * 1. The CR0 field must not set any bit to a value not supported in VMX 7041 * operation. 7042 * 2. The CR4 field must not set any bit to a value not supported in VMX 7043 * operation. 7044 * 3. On processors that support Intel 64 architecture, the CR3 field must 7045 * be such that bits 63:52 and bits in the range 51:32 beyond the 7046 * processor's physical-address width must be 0. 7047 * 7048 * [Intel SDM] 7049 */ 7050 static void test_host_ctl_regs(void) 7051 { 7052 u64 fixed0, fixed1, cr3, cr3_saved; 7053 int i; 7054 7055 /* Test CR0 */ 7056 fixed0 = rdmsr(MSR_IA32_VMX_CR0_FIXED0); 7057 fixed1 = rdmsr(MSR_IA32_VMX_CR0_FIXED1); 7058 test_ctl_reg("HOST_CR0", HOST_CR0, fixed0, fixed1); 7059 7060 /* Test CR4 */ 7061 fixed0 = rdmsr(MSR_IA32_VMX_CR4_FIXED0); 7062 fixed1 = rdmsr(MSR_IA32_VMX_CR4_FIXED1) & 7063 ~(X86_CR4_SMEP | X86_CR4_SMAP); 7064 test_ctl_reg("HOST_CR4", HOST_CR4, fixed0, fixed1); 7065 7066 /* Test CR3 */ 7067 cr3_saved = vmcs_read(HOST_CR3); 7068 for (i = cpuid_maxphyaddr(); i < 64; i++) { 7069 cr3 = cr3_saved | (1ul << i); 7070 vmcs_write(HOST_CR3, cr3); 7071 report_prefix_pushf("HOST_CR3 %lx", cr3); 7072 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7073 report_prefix_pop(); 7074 } 7075 7076 vmcs_write(HOST_CR3, cr3_saved); 7077 } 7078 7079 static void test_efer_vmlaunch(u32 fld, bool ok) 7080 { 7081 if (fld == HOST_EFER) { 7082 if (ok) 7083 test_vmx_vmlaunch(0); 7084 else 7085 test_vmx_vmlaunch2(VMXERR_ENTRY_INVALID_CONTROL_FIELD, 7086 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7087 } else { 7088 test_guest_state("EFER test", !ok, GUEST_EFER, "GUEST_EFER"); 7089 } 7090 } 7091 7092 static void test_efer_one(u32 fld, const char * fld_name, u64 efer, 7093 u32 ctrl_fld, u64 ctrl, 7094 int i, const char *efer_bit_name) 7095 { 7096 bool ok; 7097 7098 ok = true; 7099 if (ctrl_fld == EXI_CONTROLS && (ctrl & EXI_LOAD_EFER)) { 7100 if (!!(efer & EFER_LMA) != !!(ctrl & EXI_HOST_64)) 7101 ok = false; 7102 if (!!(efer & EFER_LME) != !!(ctrl & EXI_HOST_64)) 7103 ok = false; 7104 } 7105 if (ctrl_fld == ENT_CONTROLS && (ctrl & ENT_LOAD_EFER)) { 7106 /* Check LMA too since CR0.PG is set. */ 7107 if (!!(efer & EFER_LMA) != !!(ctrl & ENT_GUEST_64)) 7108 ok = false; 7109 if (!!(efer & EFER_LME) != !!(ctrl & ENT_GUEST_64)) 7110 ok = false; 7111 } 7112 7113 /* 7114 * Skip the test if it would enter the guest in 32-bit mode. 7115 * Perhaps write the test in assembly and make sure it 7116 * can be run in either mode? 7117 */ 7118 if (fld == GUEST_EFER && ok && !(ctrl & ENT_GUEST_64)) 7119 return; 7120 7121 vmcs_write(ctrl_fld, ctrl); 7122 vmcs_write(fld, efer); 7123 report_prefix_pushf("%s %s bit turned %s, controls %s", 7124 fld_name, efer_bit_name, 7125 (i & 1) ? "on" : "off", 7126 (i & 2) ? "on" : "off"); 7127 7128 test_efer_vmlaunch(fld, ok); 7129 report_prefix_pop(); 7130 } 7131 7132 static void test_efer_bit(u32 fld, const char * fld_name, 7133 u32 ctrl_fld, u64 ctrl_bit, u64 efer_bit, 7134 const char *efer_bit_name) 7135 { 7136 u64 efer_saved = vmcs_read(fld); 7137 u32 ctrl_saved = vmcs_read(ctrl_fld); 7138 int i; 7139 7140 for (i = 0; i < 4; i++) { 7141 u64 efer = efer_saved & ~efer_bit; 7142 u64 ctrl = ctrl_saved & ~ctrl_bit; 7143 7144 if (i & 1) 7145 efer |= efer_bit; 7146 if (i & 2) 7147 ctrl |= ctrl_bit; 7148 7149 test_efer_one(fld, fld_name, efer, ctrl_fld, ctrl, 7150 i, efer_bit_name); 7151 } 7152 7153 vmcs_write(ctrl_fld, ctrl_saved); 7154 vmcs_write(fld, efer_saved); 7155 } 7156 7157 static void test_efer(u32 fld, const char * fld_name, u32 ctrl_fld, 7158 u64 ctrl_bit1, u64 ctrl_bit2) 7159 { 7160 u64 efer_saved = vmcs_read(fld); 7161 u32 ctrl_saved = vmcs_read(ctrl_fld); 7162 u64 efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 7163 u64 i; 7164 u64 efer; 7165 7166 if (cpu_has_efer_nx()) 7167 efer_reserved_bits &= ~EFER_NX; 7168 7169 if (!ctrl_bit1) { 7170 printf("\"Load-IA32-EFER\" exit control not supported\n"); 7171 goto test_entry_exit_mode; 7172 } 7173 7174 report_prefix_pushf("%s %lx", fld_name, efer_saved); 7175 test_efer_vmlaunch(fld, true); 7176 report_prefix_pop(); 7177 7178 /* 7179 * Check reserved bits 7180 */ 7181 vmcs_write(ctrl_fld, ctrl_saved & ~ctrl_bit1); 7182 for (i = 0; i < 64; i++) { 7183 if ((1ull << i) & efer_reserved_bits) { 7184 efer = efer_saved | (1ull << i); 7185 vmcs_write(fld, efer); 7186 report_prefix_pushf("%s %lx", fld_name, efer); 7187 test_efer_vmlaunch(fld, true); 7188 report_prefix_pop(); 7189 } 7190 } 7191 7192 vmcs_write(ctrl_fld, ctrl_saved | ctrl_bit1); 7193 for (i = 0; i < 64; i++) { 7194 if ((1ull << i) & efer_reserved_bits) { 7195 efer = efer_saved | (1ull << i); 7196 vmcs_write(fld, efer); 7197 report_prefix_pushf("%s %lx", fld_name, efer); 7198 test_efer_vmlaunch(fld, false); 7199 report_prefix_pop(); 7200 } 7201 } 7202 7203 vmcs_write(ctrl_fld, ctrl_saved); 7204 vmcs_write(fld, efer_saved); 7205 7206 /* 7207 * Check LMA and LME bits 7208 */ 7209 test_efer_bit(fld, fld_name, 7210 ctrl_fld, ctrl_bit1, 7211 EFER_LMA, 7212 "EFER_LMA"); 7213 test_efer_bit(fld, fld_name, 7214 ctrl_fld, ctrl_bit1, 7215 EFER_LME, 7216 "EFER_LME"); 7217 7218 test_entry_exit_mode: 7219 test_efer_bit(fld, fld_name, 7220 ctrl_fld, ctrl_bit2, 7221 EFER_LMA, 7222 "EFER_LMA"); 7223 test_efer_bit(fld, fld_name, 7224 ctrl_fld, ctrl_bit2, 7225 EFER_LME, 7226 "EFER_LME"); 7227 } 7228 7229 /* 7230 * If the 'load IA32_EFER' VM-exit control is 1, bits reserved in the 7231 * IA32_EFER MSR must be 0 in the field for that register. In addition, 7232 * the values of the LMA and LME bits in the field must each be that of 7233 * the 'host address-space size' VM-exit control. 7234 * 7235 * [Intel SDM] 7236 */ 7237 static void test_host_efer(void) 7238 { 7239 test_efer(HOST_EFER, "HOST_EFER", EXI_CONTROLS, 7240 ctrl_exit_rev.clr & EXI_LOAD_EFER, 7241 EXI_HOST_64); 7242 } 7243 7244 /* 7245 * If the 'load IA32_EFER' VM-enter control is 1, bits reserved in the 7246 * IA32_EFER MSR must be 0 in the field for that register. In addition, 7247 * the values of the LMA and LME bits in the field must each be that of 7248 * the 'IA32e-mode guest' VM-exit control. 7249 */ 7250 static void test_guest_efer(void) 7251 { 7252 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) { 7253 printf("\"Load-IA32-EFER\" entry control not supported\n"); 7254 return; 7255 } 7256 7257 vmcs_write(GUEST_EFER, rdmsr(MSR_EFER)); 7258 test_efer(GUEST_EFER, "GUEST_EFER", ENT_CONTROLS, 7259 ctrl_enter_rev.clr & ENT_LOAD_EFER, 7260 ENT_GUEST_64); 7261 } 7262 7263 /* 7264 * PAT values higher than 8 are uninteresting since they're likely lumped 7265 * in with "8". We only test values above 8 one bit at a time, 7266 * in order to reduce the number of VM-Entries and keep the runtime reasonable. 7267 */ 7268 #define PAT_VAL_LIMIT 8 7269 7270 static void test_pat(u32 field, const char * field_name, u32 ctrl_field, 7271 u64 ctrl_bit) 7272 { 7273 u32 ctrl_saved = vmcs_read(ctrl_field); 7274 u64 pat_saved = vmcs_read(field); 7275 u64 i, val; 7276 u32 j; 7277 int error; 7278 7279 vmcs_clear_bits(ctrl_field, ctrl_bit); 7280 7281 for (i = 0; i < 256; i = (i < PAT_VAL_LIMIT) ? i + 1 : i * 2) { 7282 /* Test PAT0..PAT7 fields */ 7283 for (j = 0; j < (i ? 8 : 1); j++) { 7284 val = i << j * 8; 7285 vmcs_write(field, val); 7286 if (field == HOST_PAT) { 7287 report_prefix_pushf("%s %lx", field_name, val); 7288 test_vmx_vmlaunch(0); 7289 report_prefix_pop(); 7290 7291 } else { // GUEST_PAT 7292 test_guest_state("ENT_LOAD_PAT enabled", false, 7293 val, "GUEST_PAT"); 7294 } 7295 } 7296 } 7297 7298 vmcs_set_bits(ctrl_field, ctrl_bit); 7299 for (i = 0; i < 256; i = (i < PAT_VAL_LIMIT) ? i + 1 : i * 2) { 7300 /* Test PAT0..PAT7 fields */ 7301 for (j = 0; j < (i ? 8 : 1); j++) { 7302 val = i << j * 8; 7303 vmcs_write(field, val); 7304 7305 if (field == HOST_PAT) { 7306 report_prefix_pushf("%s %lx", field_name, val); 7307 if (i == 0x2 || i == 0x3 || i >= 0x8) 7308 error = 7309 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD; 7310 else 7311 error = 0; 7312 7313 test_vmx_vmlaunch(error); 7314 report_prefix_pop(); 7315 7316 } else { // GUEST_PAT 7317 error = (i == 0x2 || i == 0x3 || i >= 0x8); 7318 test_guest_state("ENT_LOAD_PAT enabled", !!error, 7319 val, "GUEST_PAT"); 7320 } 7321 7322 } 7323 } 7324 7325 vmcs_write(ctrl_field, ctrl_saved); 7326 vmcs_write(field, pat_saved); 7327 } 7328 7329 /* 7330 * If the "load IA32_PAT" VM-exit control is 1, the value of the field 7331 * for the IA32_PAT MSR must be one that could be written by WRMSR 7332 * without fault at CPL 0. Specifically, each of the 8 bytes in the 7333 * field must have one of the values 0 (UC), 1 (WC), 4 (WT), 5 (WP), 7334 * 6 (WB), or 7 (UC-). 7335 * 7336 * [Intel SDM] 7337 */ 7338 static void test_load_host_pat(void) 7339 { 7340 /* 7341 * "load IA32_PAT" VM-exit control 7342 */ 7343 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) { 7344 printf("\"Load-IA32-PAT\" exit control not supported\n"); 7345 return; 7346 } 7347 7348 test_pat(HOST_PAT, "HOST_PAT", EXI_CONTROLS, EXI_LOAD_PAT); 7349 } 7350 7351 union cpuidA_eax { 7352 struct { 7353 unsigned int version_id:8; 7354 unsigned int num_counters_gp:8; 7355 unsigned int bit_width:8; 7356 unsigned int mask_length:8; 7357 } split; 7358 unsigned int full; 7359 }; 7360 7361 union cpuidA_edx { 7362 struct { 7363 unsigned int num_counters_fixed:5; 7364 unsigned int bit_width_fixed:8; 7365 unsigned int reserved:9; 7366 } split; 7367 unsigned int full; 7368 }; 7369 7370 static bool valid_pgc(u64 val) 7371 { 7372 struct cpuid id; 7373 union cpuidA_eax eax; 7374 union cpuidA_edx edx; 7375 u64 mask; 7376 7377 id = cpuid(0xA); 7378 eax.full = id.a; 7379 edx.full = id.d; 7380 mask = ~(((1ull << eax.split.num_counters_gp) - 1) | 7381 (((1ull << edx.split.num_counters_fixed) - 1) << 32)); 7382 7383 return !(val & mask); 7384 } 7385 7386 static void test_pgc_vmlaunch(u32 xerror, u32 xreason, bool xfail, bool host) 7387 { 7388 u32 inst_err; 7389 u64 obs; 7390 bool success; 7391 struct vmx_state_area_test_data *data = &vmx_state_area_test_data; 7392 7393 if (host) { 7394 success = vmlaunch_succeeds(); 7395 obs = rdmsr(data->msr); 7396 if (!success) { 7397 inst_err = vmcs_read(VMX_INST_ERROR); 7398 report(xerror == inst_err, "vmlaunch failed, " 7399 "VMX Inst Error is %d (expected %d)", 7400 inst_err, xerror); 7401 } else { 7402 report(!data->enabled || data->exp == obs, 7403 "Host state is 0x%lx (expected 0x%lx)", 7404 obs, data->exp); 7405 report(success != xfail, "vmlaunch succeeded"); 7406 } 7407 } else { 7408 test_guest_state("load GUEST_PERF_GLOBAL_CTRL", xfail, 7409 GUEST_PERF_GLOBAL_CTRL, 7410 "GUEST_PERF_GLOBAL_CTRL"); 7411 } 7412 } 7413 7414 /* 7415 * test_load_perf_global_ctrl is a generic function for testing the 7416 * "load IA32_PERF_GLOBAL_CTRL" VM-{Entry,Exit} controls. This test function 7417 * tests the provided ctrl_val when disabled and enabled. 7418 * 7419 * @nr: VMCS field number corresponding to the host/guest state field 7420 * @name: Name of the above VMCS field for printing in test report 7421 * @ctrl_nr: VMCS field number corresponding to the VM-{Entry,Exit} control 7422 * @ctrl_val: Bit to set on the ctrl_field 7423 */ 7424 static void test_perf_global_ctrl(u32 nr, const char *name, u32 ctrl_nr, 7425 const char *ctrl_name, u64 ctrl_val) 7426 { 7427 u64 ctrl_saved = vmcs_read(ctrl_nr); 7428 u64 pgc_saved = vmcs_read(nr); 7429 u64 i, val; 7430 bool host = nr == HOST_PERF_GLOBAL_CTRL; 7431 struct vmx_state_area_test_data *data = &vmx_state_area_test_data; 7432 7433 data->msr = MSR_CORE_PERF_GLOBAL_CTRL; 7434 msr_bmp_init(); 7435 vmcs_write(ctrl_nr, ctrl_saved & ~ctrl_val); 7436 data->enabled = false; 7437 report_prefix_pushf("\"load IA32_PERF_GLOBAL_CTRL\"=0 on %s", 7438 ctrl_name); 7439 7440 for (i = 0; i < 64; i++) { 7441 val = 1ull << i; 7442 vmcs_write(nr, val); 7443 report_prefix_pushf("%s = 0x%lx", name, val); 7444 test_pgc_vmlaunch(0, VMX_VMCALL, false, host); 7445 report_prefix_pop(); 7446 } 7447 report_prefix_pop(); 7448 7449 vmcs_write(ctrl_nr, ctrl_saved | ctrl_val); 7450 data->enabled = true; 7451 report_prefix_pushf("\"load IA32_PERF_GLOBAL_CTRL\"=1 on %s", 7452 ctrl_name); 7453 for (i = 0; i < 64; i++) { 7454 val = 1ull << i; 7455 data->exp = val; 7456 vmcs_write(nr, val); 7457 report_prefix_pushf("%s = 0x%lx", name, val); 7458 if (valid_pgc(val)) { 7459 test_pgc_vmlaunch(0, VMX_VMCALL, false, host); 7460 } else { 7461 if (host) 7462 test_pgc_vmlaunch( 7463 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, 7464 0, 7465 true, 7466 host); 7467 else 7468 test_pgc_vmlaunch( 7469 0, 7470 VMX_ENTRY_FAILURE | VMX_FAIL_STATE, 7471 true, 7472 host); 7473 } 7474 report_prefix_pop(); 7475 } 7476 7477 data->enabled = false; 7478 report_prefix_pop(); 7479 vmcs_write(ctrl_nr, ctrl_saved); 7480 vmcs_write(nr, pgc_saved); 7481 } 7482 7483 static void test_load_host_perf_global_ctrl(void) 7484 { 7485 if (!(ctrl_exit_rev.clr & EXI_LOAD_PERF)) { 7486 printf("\"load IA32_PERF_GLOBAL_CTRL\" exit control not supported\n"); 7487 return; 7488 } 7489 7490 test_perf_global_ctrl(HOST_PERF_GLOBAL_CTRL, "HOST_PERF_GLOBAL_CTRL", 7491 EXI_CONTROLS, "EXI_CONTROLS", EXI_LOAD_PERF); 7492 } 7493 7494 7495 static void test_load_guest_perf_global_ctrl(void) 7496 { 7497 if (!(ctrl_enter_rev.clr & ENT_LOAD_PERF)) { 7498 printf("\"load IA32_PERF_GLOBAL_CTRL\" entry control not supported\n"); 7499 return; 7500 } 7501 7502 test_perf_global_ctrl(GUEST_PERF_GLOBAL_CTRL, "GUEST_PERF_GLOBAL_CTRL", 7503 ENT_CONTROLS, "ENT_CONTROLS", ENT_LOAD_PERF); 7504 } 7505 7506 7507 /* 7508 * test_vmcs_field - test a value for the given VMCS field 7509 * @field: VMCS field 7510 * @field_name: string name of VMCS field 7511 * @bit_start: starting bit 7512 * @bit_end: ending bit 7513 * @val: value that the bit range must or must not contain 7514 * @valid_val: whether value given in 'val' must be valid or not 7515 * @error: expected VMCS error when vmentry fails for an invalid value 7516 */ 7517 static void test_vmcs_field(u64 field, const char *field_name, u32 bit_start, 7518 u32 bit_end, u64 val, bool valid_val, u32 error) 7519 { 7520 u64 field_saved = vmcs_read(field); 7521 u32 i; 7522 u64 tmp; 7523 u32 bit_on; 7524 u64 mask = ~0ull; 7525 7526 mask = (mask >> bit_end) << bit_end; 7527 mask = mask | ((1 << bit_start) - 1); 7528 tmp = (field_saved & mask) | (val << bit_start); 7529 7530 vmcs_write(field, tmp); 7531 report_prefix_pushf("%s %lx", field_name, tmp); 7532 if (valid_val) 7533 test_vmx_vmlaunch(0); 7534 else 7535 test_vmx_vmlaunch(error); 7536 report_prefix_pop(); 7537 7538 for (i = bit_start; i <= bit_end; i = i + 2) { 7539 bit_on = ((1ull < i) & (val << bit_start)) ? 0 : 1; 7540 if (bit_on) 7541 tmp = field_saved | (1ull << i); 7542 else 7543 tmp = field_saved & ~(1ull << i); 7544 vmcs_write(field, tmp); 7545 report_prefix_pushf("%s %lx", field_name, tmp); 7546 if (valid_val) 7547 test_vmx_vmlaunch(error); 7548 else 7549 test_vmx_vmlaunch(0); 7550 report_prefix_pop(); 7551 } 7552 7553 vmcs_write(field, field_saved); 7554 } 7555 7556 static void test_canonical(u64 field, const char * field_name, bool host) 7557 { 7558 u64 addr_saved = vmcs_read(field); 7559 7560 /* 7561 * Use the existing value if possible. Writing a random canonical 7562 * value is not an option as doing so would corrupt the field being 7563 * tested and likely hose the test. 7564 */ 7565 if (is_canonical(addr_saved)) { 7566 if (host) { 7567 report_prefix_pushf("%s %lx", field_name, addr_saved); 7568 test_vmx_vmlaunch(0); 7569 report_prefix_pop(); 7570 } else { 7571 test_guest_state("Test canonical address", false, 7572 addr_saved, field_name); 7573 } 7574 } 7575 7576 vmcs_write(field, NONCANONICAL); 7577 7578 if (host) { 7579 report_prefix_pushf("%s %llx", field_name, NONCANONICAL); 7580 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7581 report_prefix_pop(); 7582 } else { 7583 test_guest_state("Test non-canonical address", true, 7584 NONCANONICAL, field_name); 7585 } 7586 7587 vmcs_write(field, addr_saved); 7588 } 7589 7590 #define TEST_RPL_TI_FLAGS(reg, name) \ 7591 test_vmcs_field(reg, name, 0, 2, 0x0, true, \ 7592 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7593 7594 #define TEST_CS_TR_FLAGS(reg, name) \ 7595 test_vmcs_field(reg, name, 3, 15, 0x0000, false, \ 7596 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7597 7598 /* 7599 * 1. In the selector field for each of CS, SS, DS, ES, FS, GS and TR, the 7600 * RPL (bits 1:0) and the TI flag (bit 2) must be 0. 7601 * 2. The selector fields for CS and TR cannot be 0000H. 7602 * 3. The selector field for SS cannot be 0000H if the "host address-space 7603 * size" VM-exit control is 0. 7604 * 4. On processors that support Intel 64 architecture, the base-address 7605 * fields for FS, GS and TR must contain canonical addresses. 7606 */ 7607 static void test_host_segment_regs(void) 7608 { 7609 u16 selector_saved; 7610 7611 /* 7612 * Test RPL and TI flags 7613 */ 7614 TEST_RPL_TI_FLAGS(HOST_SEL_CS, "HOST_SEL_CS"); 7615 TEST_RPL_TI_FLAGS(HOST_SEL_SS, "HOST_SEL_SS"); 7616 TEST_RPL_TI_FLAGS(HOST_SEL_DS, "HOST_SEL_DS"); 7617 TEST_RPL_TI_FLAGS(HOST_SEL_ES, "HOST_SEL_ES"); 7618 TEST_RPL_TI_FLAGS(HOST_SEL_FS, "HOST_SEL_FS"); 7619 TEST_RPL_TI_FLAGS(HOST_SEL_GS, "HOST_SEL_GS"); 7620 TEST_RPL_TI_FLAGS(HOST_SEL_TR, "HOST_SEL_TR"); 7621 7622 /* 7623 * Test that CS and TR fields can not be 0x0000 7624 */ 7625 TEST_CS_TR_FLAGS(HOST_SEL_CS, "HOST_SEL_CS"); 7626 TEST_CS_TR_FLAGS(HOST_SEL_TR, "HOST_SEL_TR"); 7627 7628 /* 7629 * SS field can not be 0x0000 if "host address-space size" VM-exit 7630 * control is 0 7631 */ 7632 selector_saved = vmcs_read(HOST_SEL_SS); 7633 vmcs_write(HOST_SEL_SS, 0); 7634 report_prefix_pushf("HOST_SEL_SS 0"); 7635 if (vmcs_read(EXI_CONTROLS) & EXI_HOST_64) { 7636 test_vmx_vmlaunch(0); 7637 } else { 7638 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7639 } 7640 report_prefix_pop(); 7641 7642 vmcs_write(HOST_SEL_SS, selector_saved); 7643 7644 /* 7645 * Base address for FS, GS and TR must be canonical 7646 */ 7647 test_canonical(HOST_BASE_FS, "HOST_BASE_FS", true); 7648 test_canonical(HOST_BASE_GS, "HOST_BASE_GS", true); 7649 test_canonical(HOST_BASE_TR, "HOST_BASE_TR", true); 7650 } 7651 7652 /* 7653 * On processors that support Intel 64 architecture, the base-address 7654 * fields for GDTR and IDTR must contain canonical addresses. 7655 */ 7656 static void test_host_desc_tables(void) 7657 { 7658 test_canonical(HOST_BASE_GDTR, "HOST_BASE_GDTR", true); 7659 test_canonical(HOST_BASE_IDTR, "HOST_BASE_IDTR", true); 7660 } 7661 7662 /* 7663 * If the "host address-space size" VM-exit control is 0, the following must 7664 * hold: 7665 * - The "IA-32e mode guest" VM-entry control is 0. 7666 * - Bit 17 of the CR4 field (corresponding to CR4.PCIDE) is 0. 7667 * - Bits 63:32 in the RIP field are 0. 7668 * 7669 * If the "host address-space size" VM-exit control is 1, the following must 7670 * hold: 7671 * - Bit 5 of the CR4 field (corresponding to CR4.PAE) is 1. 7672 * - The RIP field contains a canonical address. 7673 * 7674 */ 7675 static void test_host_addr_size(void) 7676 { 7677 u64 cr4_saved = vmcs_read(HOST_CR4); 7678 u64 rip_saved = vmcs_read(HOST_RIP); 7679 u64 entry_ctrl_saved = vmcs_read(ENT_CONTROLS); 7680 int i; 7681 u64 tmp; 7682 7683 if (vmcs_read(EXI_CONTROLS) & EXI_HOST_64) { 7684 vmcs_write(ENT_CONTROLS, entry_ctrl_saved | ENT_GUEST_64); 7685 report_prefix_pushf("\"IA-32e mode guest\" enabled"); 7686 test_vmx_vmlaunch(0); 7687 report_prefix_pop(); 7688 7689 vmcs_write(HOST_CR4, cr4_saved | X86_CR4_PCIDE); 7690 report_prefix_pushf("\"CR4.PCIDE\" set"); 7691 test_vmx_vmlaunch(0); 7692 report_prefix_pop(); 7693 7694 for (i = 32; i <= 63; i = i + 4) { 7695 tmp = rip_saved | 1ull << i; 7696 vmcs_write(HOST_RIP, tmp); 7697 report_prefix_pushf("HOST_RIP %lx", tmp); 7698 test_vmx_vmlaunch(0); 7699 report_prefix_pop(); 7700 } 7701 7702 if (cr4_saved & X86_CR4_PAE) { 7703 vmcs_write(HOST_CR4, cr4_saved & ~X86_CR4_PAE); 7704 report_prefix_pushf("\"CR4.PAE\" unset"); 7705 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7706 } else { 7707 report_prefix_pushf("\"CR4.PAE\" set"); 7708 test_vmx_vmlaunch(0); 7709 } 7710 report_prefix_pop(); 7711 7712 vmcs_write(HOST_RIP, NONCANONICAL); 7713 report_prefix_pushf("HOST_RIP %llx", NONCANONICAL); 7714 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7715 report_prefix_pop(); 7716 7717 vmcs_write(ENT_CONTROLS, entry_ctrl_saved | ENT_GUEST_64); 7718 vmcs_write(HOST_RIP, rip_saved); 7719 vmcs_write(HOST_CR4, cr4_saved); 7720 7721 /* Restore host's active RIP and CR4 values. */ 7722 report_prefix_pushf("restore host state"); 7723 test_vmx_vmlaunch(0); 7724 report_prefix_pop(); 7725 } 7726 } 7727 7728 /* 7729 * Check that the virtual CPU checks the VMX Host State Area as 7730 * documented in the Intel SDM. 7731 */ 7732 static void vmx_host_state_area_test(void) 7733 { 7734 /* 7735 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 7736 * fail due to invalid guest state, should we make it that 7737 * far. 7738 */ 7739 vmcs_write(GUEST_RFLAGS, 0); 7740 7741 test_host_ctl_regs(); 7742 7743 test_canonical(HOST_SYSENTER_ESP, "HOST_SYSENTER_ESP", true); 7744 test_canonical(HOST_SYSENTER_EIP, "HOST_SYSENTER_EIP", true); 7745 7746 test_host_efer(); 7747 test_load_host_pat(); 7748 test_host_segment_regs(); 7749 test_host_desc_tables(); 7750 test_host_addr_size(); 7751 test_load_host_perf_global_ctrl(); 7752 } 7753 7754 /* 7755 * If the "load debug controls" VM-entry control is 1, bits 63:32 in 7756 * the DR7 field must be 0. 7757 * 7758 * [Intel SDM] 7759 */ 7760 static void test_guest_dr7(void) 7761 { 7762 u32 ent_saved = vmcs_read(ENT_CONTROLS); 7763 u64 dr7_saved = vmcs_read(GUEST_DR7); 7764 u64 val; 7765 int i; 7766 7767 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS) { 7768 vmcs_clear_bits(ENT_CONTROLS, ENT_LOAD_DBGCTLS); 7769 for (i = 0; i < 64; i++) { 7770 val = 1ull << i; 7771 vmcs_write(GUEST_DR7, val); 7772 test_guest_state("ENT_LOAD_DBGCTLS disabled", false, 7773 val, "GUEST_DR7"); 7774 } 7775 } 7776 if (ctrl_enter_rev.clr & ENT_LOAD_DBGCTLS) { 7777 vmcs_set_bits(ENT_CONTROLS, ENT_LOAD_DBGCTLS); 7778 for (i = 0; i < 64; i++) { 7779 val = 1ull << i; 7780 vmcs_write(GUEST_DR7, val); 7781 test_guest_state("ENT_LOAD_DBGCTLS enabled", i >= 32, 7782 val, "GUEST_DR7"); 7783 } 7784 } 7785 vmcs_write(GUEST_DR7, dr7_saved); 7786 vmcs_write(ENT_CONTROLS, ent_saved); 7787 } 7788 7789 /* 7790 * If the "load IA32_PAT" VM-entry control is 1, the value of the field 7791 * for the IA32_PAT MSR must be one that could be written by WRMSR 7792 * without fault at CPL 0. Specifically, each of the 8 bytes in the 7793 * field must have one of the values 0 (UC), 1 (WC), 4 (WT), 5 (WP), 7794 * 6 (WB), or 7 (UC-). 7795 * 7796 * [Intel SDM] 7797 */ 7798 static void test_load_guest_pat(void) 7799 { 7800 /* 7801 * "load IA32_PAT" VM-entry control 7802 */ 7803 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 7804 printf("\"Load-IA32-PAT\" entry control not supported\n"); 7805 return; 7806 } 7807 7808 test_pat(GUEST_PAT, "GUEST_PAT", ENT_CONTROLS, ENT_LOAD_PAT); 7809 } 7810 7811 #define MSR_IA32_BNDCFGS_RSVD_MASK 0x00000ffc 7812 7813 /* 7814 * If the "load IA32_BNDCFGS" VM-entry control is 1, the following 7815 * checks are performed on the field for the IA32_BNDCFGS MSR: 7816 * 7817 * - Bits reserved in the IA32_BNDCFGS MSR must be 0. 7818 * - The linear address in bits 63:12 must be canonical. 7819 * 7820 * [Intel SDM] 7821 */ 7822 static void test_load_guest_bndcfgs(void) 7823 { 7824 u64 bndcfgs_saved = vmcs_read(GUEST_BNDCFGS); 7825 u64 bndcfgs; 7826 7827 if (!(ctrl_enter_rev.clr & ENT_LOAD_BNDCFGS)) { 7828 printf("\"Load-IA32-BNDCFGS\" entry control not supported\n"); 7829 return; 7830 } 7831 7832 vmcs_clear_bits(ENT_CONTROLS, ENT_LOAD_BNDCFGS); 7833 7834 vmcs_write(GUEST_BNDCFGS, NONCANONICAL); 7835 test_guest_state("ENT_LOAD_BNDCFGS disabled", false, 7836 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7837 bndcfgs = bndcfgs_saved | MSR_IA32_BNDCFGS_RSVD_MASK; 7838 vmcs_write(GUEST_BNDCFGS, bndcfgs); 7839 test_guest_state("ENT_LOAD_BNDCFGS disabled", false, 7840 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7841 7842 vmcs_set_bits(ENT_CONTROLS, ENT_LOAD_BNDCFGS); 7843 7844 vmcs_write(GUEST_BNDCFGS, NONCANONICAL); 7845 test_guest_state("ENT_LOAD_BNDCFGS enabled", true, 7846 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7847 bndcfgs = bndcfgs_saved | MSR_IA32_BNDCFGS_RSVD_MASK; 7848 vmcs_write(GUEST_BNDCFGS, bndcfgs); 7849 test_guest_state("ENT_LOAD_BNDCFGS enabled", true, 7850 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7851 7852 vmcs_write(GUEST_BNDCFGS, bndcfgs_saved); 7853 } 7854 7855 #define GUEST_SEG_UNUSABLE_MASK (1u << 16) 7856 #define GUEST_SEG_SEL_TI_MASK (1u << 2) 7857 7858 7859 #define TEST_SEGMENT_SEL(test, xfail, sel, val) \ 7860 do { \ 7861 vmcs_write(sel, val); \ 7862 test_guest_state(test " segment", xfail, val, xstr(sel)); \ 7863 } while (0) 7864 7865 #define TEST_INVALID_SEG_SEL(sel, val) \ 7866 TEST_SEGMENT_SEL("Invalid: " xstr(val), true, sel, val); 7867 7868 #define TEST_VALID_SEG_SEL(sel, val) \ 7869 TEST_SEGMENT_SEL("Valid: " xstr(val), false, sel, val); 7870 7871 /* 7872 * The following checks are done on the Selector field of the Guest Segment 7873 * Registers: 7874 * - TR. The TI flag (bit 2) must be 0. 7875 * - LDTR. If LDTR is usable, the TI flag (bit 2) must be 0. 7876 * - SS. If the guest will not be virtual-8086 and the "unrestricted 7877 * guest" VM-execution control is 0, the RPL (bits 1:0) must equal 7878 * the RPL of the selector field for CS. 7879 * 7880 * [Intel SDM] 7881 */ 7882 static void test_guest_segment_sel_fields(void) 7883 { 7884 u16 sel_saved; 7885 u32 ar_saved; 7886 u32 cpu_ctrl0_saved; 7887 u32 cpu_ctrl1_saved; 7888 u16 cs_rpl_bits; 7889 7890 /* 7891 * Test for GUEST_SEL_TR 7892 */ 7893 sel_saved = vmcs_read(GUEST_SEL_TR); 7894 TEST_INVALID_SEG_SEL(GUEST_SEL_TR, sel_saved | GUEST_SEG_SEL_TI_MASK); 7895 vmcs_write(GUEST_SEL_TR, sel_saved); 7896 7897 /* 7898 * Test for GUEST_SEL_LDTR 7899 */ 7900 sel_saved = vmcs_read(GUEST_SEL_LDTR); 7901 ar_saved = vmcs_read(GUEST_AR_LDTR); 7902 /* LDTR is set unusable */ 7903 vmcs_write(GUEST_AR_LDTR, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7904 TEST_VALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved | GUEST_SEG_SEL_TI_MASK); 7905 TEST_VALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved & ~GUEST_SEG_SEL_TI_MASK); 7906 /* LDTR is set usable */ 7907 vmcs_write(GUEST_AR_LDTR, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7908 TEST_INVALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved | GUEST_SEG_SEL_TI_MASK); 7909 7910 TEST_VALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved & ~GUEST_SEG_SEL_TI_MASK); 7911 7912 vmcs_write(GUEST_AR_LDTR, ar_saved); 7913 vmcs_write(GUEST_SEL_LDTR, sel_saved); 7914 7915 /* 7916 * Test for GUEST_SEL_SS 7917 */ 7918 cpu_ctrl0_saved = vmcs_read(CPU_EXEC_CTRL0); 7919 cpu_ctrl1_saved = vmcs_read(CPU_EXEC_CTRL1); 7920 ar_saved = vmcs_read(GUEST_AR_SS); 7921 /* Turn off "unrestricted guest" vm-execution control */ 7922 vmcs_write(CPU_EXEC_CTRL1, cpu_ctrl1_saved & ~CPU_URG); 7923 cs_rpl_bits = vmcs_read(GUEST_SEL_CS) & 0x3; 7924 sel_saved = vmcs_read(GUEST_SEL_SS); 7925 TEST_INVALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 7926 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 7927 /* Make SS usable if it's unusable or vice-versa */ 7928 if (ar_saved & GUEST_SEG_UNUSABLE_MASK) 7929 vmcs_write(GUEST_AR_SS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7930 else 7931 vmcs_write(GUEST_AR_SS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7932 TEST_INVALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 7933 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 7934 7935 /* Need a valid EPTP as the passing case fully enters the guest. */ 7936 if (enable_unrestricted_guest(true)) 7937 goto skip_ss_tests; 7938 7939 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 7940 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 7941 7942 /* Make SS usable if it's unusable or vice-versa */ 7943 if (vmcs_read(GUEST_AR_SS) & GUEST_SEG_UNUSABLE_MASK) 7944 vmcs_write(GUEST_AR_SS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7945 else 7946 vmcs_write(GUEST_AR_SS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7947 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 7948 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 7949 skip_ss_tests: 7950 7951 vmcs_write(GUEST_AR_SS, ar_saved); 7952 vmcs_write(GUEST_SEL_SS, sel_saved); 7953 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrl0_saved); 7954 vmcs_write(CPU_EXEC_CTRL1, cpu_ctrl1_saved); 7955 } 7956 7957 #define TEST_SEGMENT_BASE_ADDR_UPPER_BITS(xfail, seg_base) \ 7958 do { \ 7959 addr_saved = vmcs_read(seg_base); \ 7960 for (i = 32; i < 63; i = i + 4) { \ 7961 addr = addr_saved | 1ull << i; \ 7962 vmcs_write(seg_base, addr); \ 7963 test_guest_state("seg.BASE[63:32] != 0, usable = " xstr(xfail), \ 7964 xfail, addr, xstr(seg_base)); \ 7965 } \ 7966 vmcs_write(seg_base, addr_saved); \ 7967 } while (0) 7968 7969 #define TEST_SEGMENT_BASE_ADDR_CANONICAL(xfail, seg_base) \ 7970 do { \ 7971 addr_saved = vmcs_read(seg_base); \ 7972 vmcs_write(seg_base, NONCANONICAL); \ 7973 test_guest_state("seg.BASE non-canonical, usable = " xstr(xfail), \ 7974 xfail, NONCANONICAL, xstr(seg_base)); \ 7975 vmcs_write(seg_base, addr_saved); \ 7976 } while (0) 7977 7978 /* 7979 * The following checks are done on the Base Address field of the Guest 7980 * Segment Registers on processors that support Intel 64 architecture: 7981 * - TR, FS, GS : The address must be canonical. 7982 * - LDTR : If LDTR is usable, the address must be canonical. 7983 * - CS : Bits 63:32 of the address must be zero. 7984 * - SS, DS, ES : If the register is usable, bits 63:32 of the address 7985 * must be zero. 7986 * 7987 * [Intel SDM] 7988 */ 7989 static void test_guest_segment_base_addr_fields(void) 7990 { 7991 u64 addr_saved; 7992 u64 addr; 7993 u32 ar_saved; 7994 int i; 7995 7996 /* 7997 * The address of TR, FS, GS and LDTR must be canonical. 7998 */ 7999 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_TR); 8000 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_FS); 8001 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_GS); 8002 ar_saved = vmcs_read(GUEST_AR_LDTR); 8003 /* Make LDTR unusable */ 8004 vmcs_write(GUEST_AR_LDTR, ar_saved | GUEST_SEG_UNUSABLE_MASK); 8005 TEST_SEGMENT_BASE_ADDR_CANONICAL(false, GUEST_BASE_LDTR); 8006 /* Make LDTR usable */ 8007 vmcs_write(GUEST_AR_LDTR, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 8008 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_LDTR); 8009 8010 vmcs_write(GUEST_AR_LDTR, ar_saved); 8011 8012 /* 8013 * Bits 63:32 in CS, SS, DS and ES base address must be zero 8014 */ 8015 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_CS); 8016 ar_saved = vmcs_read(GUEST_AR_SS); 8017 /* Make SS unusable */ 8018 vmcs_write(GUEST_AR_SS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 8019 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(false, GUEST_BASE_SS); 8020 /* Make SS usable */ 8021 vmcs_write(GUEST_AR_SS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 8022 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_SS); 8023 vmcs_write(GUEST_AR_SS, ar_saved); 8024 8025 ar_saved = vmcs_read(GUEST_AR_DS); 8026 /* Make DS unusable */ 8027 vmcs_write(GUEST_AR_DS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 8028 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(false, GUEST_BASE_DS); 8029 /* Make DS usable */ 8030 vmcs_write(GUEST_AR_DS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 8031 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_DS); 8032 vmcs_write(GUEST_AR_DS, ar_saved); 8033 8034 ar_saved = vmcs_read(GUEST_AR_ES); 8035 /* Make ES unusable */ 8036 vmcs_write(GUEST_AR_ES, ar_saved | GUEST_SEG_UNUSABLE_MASK); 8037 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(false, GUEST_BASE_ES); 8038 /* Make ES usable */ 8039 vmcs_write(GUEST_AR_ES, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 8040 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_ES); 8041 vmcs_write(GUEST_AR_ES, ar_saved); 8042 } 8043 8044 /* 8045 * Check that the virtual CPU checks the VMX Guest State Area as 8046 * documented in the Intel SDM. 8047 */ 8048 static void vmx_guest_state_area_test(void) 8049 { 8050 vmx_set_test_stage(1); 8051 test_set_guest(guest_state_test_main); 8052 8053 /* 8054 * The IA32_SYSENTER_ESP field and the IA32_SYSENTER_EIP field 8055 * must each contain a canonical address. 8056 */ 8057 test_canonical(GUEST_SYSENTER_ESP, "GUEST_SYSENTER_ESP", false); 8058 test_canonical(GUEST_SYSENTER_EIP, "GUEST_SYSENTER_EIP", false); 8059 8060 test_guest_dr7(); 8061 test_load_guest_pat(); 8062 test_guest_efer(); 8063 test_load_guest_perf_global_ctrl(); 8064 test_load_guest_bndcfgs(); 8065 8066 test_guest_segment_sel_fields(); 8067 test_guest_segment_base_addr_fields(); 8068 8069 test_canonical(GUEST_BASE_GDTR, "GUEST_BASE_GDTR", false); 8070 test_canonical(GUEST_BASE_IDTR, "GUEST_BASE_IDTR", false); 8071 8072 u32 guest_desc_limit_saved = vmcs_read(GUEST_LIMIT_GDTR); 8073 int i; 8074 for (i = 16; i <= 31; i++) { 8075 u32 tmp = guest_desc_limit_saved | (1ull << i); 8076 vmcs_write(GUEST_LIMIT_GDTR, tmp); 8077 test_guest_state("GDT.limit > 0xffff", true, tmp, "GUEST_LIMIT_GDTR"); 8078 } 8079 vmcs_write(GUEST_LIMIT_GDTR, guest_desc_limit_saved); 8080 8081 guest_desc_limit_saved = vmcs_read(GUEST_LIMIT_IDTR); 8082 for (i = 16; i <= 31; i++) { 8083 u32 tmp = guest_desc_limit_saved | (1ull << i); 8084 vmcs_write(GUEST_LIMIT_IDTR, tmp); 8085 test_guest_state("IDT.limit > 0xffff", true, tmp, "GUEST_LIMIT_IDTR"); 8086 } 8087 vmcs_write(GUEST_LIMIT_IDTR, guest_desc_limit_saved); 8088 8089 /* 8090 * Let the guest finish execution 8091 */ 8092 vmx_set_test_stage(2); 8093 enter_guest(); 8094 } 8095 8096 extern void unrestricted_guest_main(void); 8097 asm (".code32\n" 8098 "unrestricted_guest_main:\n" 8099 "vmcall\n" 8100 "nop\n" 8101 "mov $1, %edi\n" 8102 "call hypercall\n" 8103 ".code64\n"); 8104 8105 static void setup_unrestricted_guest(void) 8106 { 8107 vmcs_write(GUEST_CR0, vmcs_read(GUEST_CR0) & ~(X86_CR0_PG)); 8108 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) & ~ENT_GUEST_64); 8109 vmcs_write(GUEST_EFER, vmcs_read(GUEST_EFER) & ~EFER_LMA); 8110 vmcs_write(GUEST_RIP, virt_to_phys(unrestricted_guest_main)); 8111 } 8112 8113 static void unsetup_unrestricted_guest(void) 8114 { 8115 vmcs_write(GUEST_CR0, vmcs_read(GUEST_CR0) | X86_CR0_PG); 8116 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) | ENT_GUEST_64); 8117 vmcs_write(GUEST_EFER, vmcs_read(GUEST_EFER) | EFER_LMA); 8118 vmcs_write(GUEST_RIP, (u64) phys_to_virt(vmcs_read(GUEST_RIP))); 8119 vmcs_write(GUEST_RSP, (u64) phys_to_virt(vmcs_read(GUEST_RSP))); 8120 } 8121 8122 /* 8123 * If "unrestricted guest" secondary VM-execution control is set, guests 8124 * can run in unpaged protected mode. 8125 */ 8126 static void vmentry_unrestricted_guest_test(void) 8127 { 8128 if (enable_unrestricted_guest(true)) { 8129 report_skip("Unrestricted guest not supported"); 8130 return; 8131 } 8132 8133 test_set_guest(unrestricted_guest_main); 8134 setup_unrestricted_guest(); 8135 test_guest_state("Unrestricted guest test", false, CPU_URG, "CPU_URG"); 8136 8137 /* 8138 * Let the guest finish execution as a regular guest 8139 */ 8140 unsetup_unrestricted_guest(); 8141 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) & ~CPU_URG); 8142 enter_guest(); 8143 } 8144 8145 static bool valid_vmcs_for_vmentry(void) 8146 { 8147 struct vmcs *current_vmcs = NULL; 8148 8149 if (vmcs_save(¤t_vmcs)) 8150 return false; 8151 8152 return current_vmcs && !current_vmcs->hdr.shadow_vmcs; 8153 } 8154 8155 static void try_vmentry_in_movss_shadow(void) 8156 { 8157 u32 vm_inst_err; 8158 u32 flags; 8159 bool early_failure = false; 8160 u32 expected_flags = X86_EFLAGS_FIXED; 8161 bool valid_vmcs = valid_vmcs_for_vmentry(); 8162 8163 expected_flags |= valid_vmcs ? X86_EFLAGS_ZF : X86_EFLAGS_CF; 8164 8165 /* 8166 * Indirectly set VM_INST_ERR to 12 ("VMREAD/VMWRITE from/to 8167 * unsupported VMCS component"). 8168 */ 8169 vmcs_write(~0u, 0); 8170 8171 __asm__ __volatile__ ("mov %[host_rsp], %%edx;" 8172 "vmwrite %%rsp, %%rdx;" 8173 "mov 0f, %%rax;" 8174 "mov %[host_rip], %%edx;" 8175 "vmwrite %%rax, %%rdx;" 8176 "mov $-1, %%ah;" 8177 "sahf;" 8178 "mov %%ss, %%ax;" 8179 "mov %%ax, %%ss;" 8180 "vmlaunch;" 8181 "mov $1, %[early_failure];" 8182 "0: lahf;" 8183 "movzbl %%ah, %[flags]" 8184 : [early_failure] "+r" (early_failure), 8185 [flags] "=&a" (flags) 8186 : [host_rsp] "i" (HOST_RSP), 8187 [host_rip] "i" (HOST_RIP) 8188 : "rdx", "cc", "memory"); 8189 vm_inst_err = vmcs_read(VMX_INST_ERROR); 8190 8191 report(early_failure, "Early VM-entry failure"); 8192 report(flags == expected_flags, "RFLAGS[8:0] is %x (actual %x)", 8193 expected_flags, flags); 8194 if (valid_vmcs) 8195 report(vm_inst_err == VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, 8196 "VM-instruction error is %d (actual %d)", 8197 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, vm_inst_err); 8198 } 8199 8200 static void vmentry_movss_shadow_test(void) 8201 { 8202 struct vmcs *orig_vmcs; 8203 8204 TEST_ASSERT(!vmcs_save(&orig_vmcs)); 8205 8206 /* 8207 * Set the launched flag on the current VMCS to verify the correct 8208 * error priority, below. 8209 */ 8210 test_set_guest(v2_null_test_guest); 8211 enter_guest(); 8212 8213 /* 8214 * With bit 1 of the guest's RFLAGS clear, VM-entry should 8215 * fail due to invalid guest state (if we make it that far). 8216 */ 8217 vmcs_write(GUEST_RFLAGS, 0); 8218 8219 /* 8220 * "VM entry with events blocked by MOV SS" takes precedence over 8221 * "VMLAUNCH with non-clear VMCS." 8222 */ 8223 report_prefix_push("valid current-VMCS"); 8224 try_vmentry_in_movss_shadow(); 8225 report_prefix_pop(); 8226 8227 /* 8228 * VMfailInvalid takes precedence over "VM entry with events 8229 * blocked by MOV SS." 8230 */ 8231 TEST_ASSERT(!vmcs_clear(orig_vmcs)); 8232 report_prefix_push("no current-VMCS"); 8233 try_vmentry_in_movss_shadow(); 8234 report_prefix_pop(); 8235 8236 TEST_ASSERT(!make_vmcs_current(orig_vmcs)); 8237 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 8238 } 8239 8240 static void vmx_ldtr_test_guest(void) 8241 { 8242 u16 ldtr = sldt(); 8243 8244 report(ldtr == NP_SEL, "Expected %x for L2 LDTR selector (got %x)", 8245 NP_SEL, ldtr); 8246 } 8247 8248 /* 8249 * Ensure that the L1 LDTR is set to 0 on VM-exit. 8250 */ 8251 static void vmx_ldtr_test(void) 8252 { 8253 const u8 ldt_ar = 0x82; /* Present LDT */ 8254 u16 sel = FIRST_SPARE_SEL; 8255 8256 /* Set up a non-zero L1 LDTR prior to VM-entry. */ 8257 set_gdt_entry(sel, 0, 0, ldt_ar, 0); 8258 lldt(sel); 8259 8260 test_set_guest(vmx_ldtr_test_guest); 8261 /* 8262 * Set up a different LDTR for L2. The actual GDT contents are 8263 * irrelevant, since we stuff the hidden descriptor state 8264 * straight into the VMCS rather than reading it from the GDT. 8265 */ 8266 vmcs_write(GUEST_SEL_LDTR, NP_SEL); 8267 vmcs_write(GUEST_AR_LDTR, ldt_ar); 8268 enter_guest(); 8269 8270 /* 8271 * VM-exit should clear LDTR (and make it unusable, but we 8272 * won't verify that here). 8273 */ 8274 sel = sldt(); 8275 report(!sel, "Expected 0 for L1 LDTR selector (got %x)", sel); 8276 } 8277 8278 static void vmx_single_vmcall_guest(void) 8279 { 8280 vmcall(); 8281 } 8282 8283 static void vmx_cr_load_test(void) 8284 { 8285 unsigned long cr3, cr4, orig_cr3, orig_cr4; 8286 u32 ctrls[2] = {0}; 8287 pgd_t *pml5; 8288 8289 orig_cr4 = read_cr4(); 8290 orig_cr3 = read_cr3(); 8291 8292 if (!this_cpu_has(X86_FEATURE_PCID)) { 8293 report_skip("PCID not detected"); 8294 return; 8295 } 8296 if (!this_cpu_has(X86_FEATURE_MCE)) { 8297 report_skip("MCE not detected"); 8298 return; 8299 } 8300 8301 TEST_ASSERT(!(orig_cr3 & X86_CR3_PCID_MASK)); 8302 8303 /* Enable PCID for L1. */ 8304 cr4 = orig_cr4 | X86_CR4_PCIDE; 8305 cr3 = orig_cr3 | 0x1; 8306 TEST_ASSERT(!write_cr4_checking(cr4)); 8307 write_cr3(cr3); 8308 8309 test_set_guest(vmx_single_vmcall_guest); 8310 vmcs_write(HOST_CR4, cr4); 8311 vmcs_write(HOST_CR3, cr3); 8312 enter_guest(); 8313 8314 /* 8315 * No exception is expected. 8316 * 8317 * NB. KVM loads the last guest write to CR4 into CR4 read 8318 * shadow. In order to trigger an exit to KVM, we can toggle a 8319 * bit that is owned by KVM. We use CR4.MCE, which shall 8320 * have no side effect because normally no guest MCE (e.g., as the 8321 * result of bad memory) would happen during this test. 8322 */ 8323 TEST_ASSERT(!write_cr4_checking(cr4 ^ X86_CR4_MCE)); 8324 8325 /* Cleanup L1 state. */ 8326 write_cr3(orig_cr3); 8327 TEST_ASSERT(!write_cr4_checking(orig_cr4)); 8328 8329 if (!this_cpu_has(X86_FEATURE_LA57)) 8330 goto done; 8331 8332 /* 8333 * Allocate a full page for PML5 to guarantee alignment, though only 8334 * the first entry needs to be filled (the test's virtual addresses 8335 * most definitely do not have any of bits 56:48 set). 8336 */ 8337 pml5 = alloc_page(); 8338 *pml5 = orig_cr3 | PT_PRESENT_MASK | PT_WRITABLE_MASK; 8339 8340 /* 8341 * Transition to/from 5-level paging in the host via VM-Exit. CR4.LA57 8342 * can't be toggled while long is active via MOV CR4, but there are no 8343 * such restrictions on VM-Exit. 8344 */ 8345 lol_5level: 8346 vmcs_write(HOST_CR4, orig_cr4 | X86_CR4_LA57); 8347 vmcs_write(HOST_CR3, virt_to_phys(pml5)); 8348 enter_guest(); 8349 8350 /* 8351 * VMREAD with a memory operand to verify KVM detects the LA57 change, 8352 * e.g. uses the correct guest root level in gva_to_gpa(). 8353 */ 8354 TEST_ASSERT(vmcs_readm(HOST_CR3) == virt_to_phys(pml5)); 8355 TEST_ASSERT(vmcs_readm(HOST_CR4) == (orig_cr4 | X86_CR4_LA57)); 8356 8357 vmcs_write(HOST_CR4, orig_cr4); 8358 vmcs_write(HOST_CR3, orig_cr3); 8359 enter_guest(); 8360 8361 TEST_ASSERT(vmcs_readm(HOST_CR3) == orig_cr3); 8362 TEST_ASSERT(vmcs_readm(HOST_CR4) == orig_cr4); 8363 8364 /* 8365 * And now do the same LA57 shenanigans with EPT enabled. KVM uses 8366 * two separate MMUs when L1 uses TDP, whereas the above shadow paging 8367 * version shares an MMU between L1 and L2. 8368 * 8369 * If the saved execution controls are non-zero then the EPT version 8370 * has already run. In that case, restore the old controls. If EPT 8371 * setup fails, e.g. EPT isn't supported, fall through and finish up. 8372 */ 8373 if (ctrls[0]) { 8374 vmcs_write(CPU_EXEC_CTRL0, ctrls[0]); 8375 vmcs_write(CPU_EXEC_CTRL1, ctrls[1]); 8376 } else if (!setup_ept(false)) { 8377 ctrls[0] = vmcs_read(CPU_EXEC_CTRL0); 8378 ctrls[1] = vmcs_read(CPU_EXEC_CTRL1); 8379 goto lol_5level; 8380 } 8381 8382 free_page(pml5); 8383 8384 done: 8385 skip_exit_vmcall(); 8386 enter_guest(); 8387 } 8388 8389 static void vmx_cr4_osxsave_test_guest(void) 8390 { 8391 write_cr4(read_cr4() & ~X86_CR4_OSXSAVE); 8392 } 8393 8394 /* 8395 * Ensure that kvm recalculates the L1 guest's CPUID.01H:ECX.OSXSAVE 8396 * after VM-exit from an L2 guest that sets CR4.OSXSAVE to a different 8397 * value than in L1. 8398 */ 8399 static void vmx_cr4_osxsave_test(void) 8400 { 8401 if (!this_cpu_has(X86_FEATURE_XSAVE)) { 8402 report_skip("XSAVE not detected"); 8403 return; 8404 } 8405 8406 if (!(read_cr4() & X86_CR4_OSXSAVE)) { 8407 unsigned long cr4 = read_cr4() | X86_CR4_OSXSAVE; 8408 8409 write_cr4(cr4); 8410 vmcs_write(GUEST_CR4, cr4); 8411 vmcs_write(HOST_CR4, cr4); 8412 } 8413 8414 TEST_ASSERT(cpuid_osxsave()); 8415 8416 test_set_guest(vmx_cr4_osxsave_test_guest); 8417 enter_guest(); 8418 8419 TEST_ASSERT(cpuid_osxsave()); 8420 } 8421 8422 static void vmx_nm_test_guest(void) 8423 { 8424 write_cr0(read_cr0() | X86_CR0_TS); 8425 asm volatile("fnop"); 8426 } 8427 8428 static void check_nm_exit(const char *test) 8429 { 8430 u32 reason = vmcs_read(EXI_REASON); 8431 u32 intr_info = vmcs_read(EXI_INTR_INFO); 8432 const u32 expected = INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 8433 NM_VECTOR; 8434 8435 report(reason == VMX_EXC_NMI && intr_info == expected, "%s", test); 8436 } 8437 8438 /* 8439 * This test checks that: 8440 * 8441 * (a) If L2 launches with CR0.TS clear, but later sets CR0.TS, then 8442 * a subsequent #NM VM-exit is reflected to L1. 8443 * 8444 * (b) If L2 launches with CR0.TS clear and CR0.EM set, then a 8445 * subsequent #NM VM-exit is reflected to L1. 8446 */ 8447 static void vmx_nm_test(void) 8448 { 8449 unsigned long cr0 = read_cr0(); 8450 8451 test_set_guest(vmx_nm_test_guest); 8452 8453 /* 8454 * L1 wants to intercept #NM exceptions encountered in L2. 8455 */ 8456 vmcs_write(EXC_BITMAP, 1 << NM_VECTOR); 8457 8458 /* 8459 * Launch L2 with CR0.TS clear, but don't claim host ownership of 8460 * any CR0 bits. L2 will set CR0.TS and then try to execute fnop, 8461 * which will raise #NM. L0 should reflect the #NM VM-exit to L1. 8462 */ 8463 vmcs_write(CR0_MASK, 0); 8464 vmcs_write(GUEST_CR0, cr0 & ~X86_CR0_TS); 8465 enter_guest(); 8466 check_nm_exit("fnop with CR0.TS set in L2 triggers #NM VM-exit to L1"); 8467 8468 /* 8469 * Re-enter L2 at the fnop instruction, with CR0.TS clear but 8470 * CR0.EM set. The fnop will still raise #NM, and L0 should 8471 * reflect the #NM VM-exit to L1. 8472 */ 8473 vmcs_write(GUEST_CR0, (cr0 & ~X86_CR0_TS) | X86_CR0_EM); 8474 enter_guest(); 8475 check_nm_exit("fnop with CR0.EM set in L2 triggers #NM VM-exit to L1"); 8476 8477 /* 8478 * Re-enter L2 at the fnop instruction, with both CR0.TS and 8479 * CR0.EM clear. There will be no #NM, and the L2 guest should 8480 * exit normally. 8481 */ 8482 vmcs_write(GUEST_CR0, cr0 & ~(X86_CR0_TS | X86_CR0_EM)); 8483 enter_guest(); 8484 } 8485 8486 bool vmx_pending_event_ipi_fired; 8487 static void vmx_pending_event_ipi_isr(isr_regs_t *regs) 8488 { 8489 vmx_pending_event_ipi_fired = true; 8490 eoi(); 8491 } 8492 8493 bool vmx_pending_event_guest_run; 8494 static void vmx_pending_event_guest(void) 8495 { 8496 vmcall(); 8497 vmx_pending_event_guest_run = true; 8498 } 8499 8500 static void vmx_pending_event_test_core(bool guest_hlt) 8501 { 8502 int ipi_vector = 0xf1; 8503 8504 vmx_pending_event_ipi_fired = false; 8505 handle_irq(ipi_vector, vmx_pending_event_ipi_isr); 8506 8507 vmx_pending_event_guest_run = false; 8508 test_set_guest(vmx_pending_event_guest); 8509 8510 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 8511 8512 enter_guest(); 8513 skip_exit_vmcall(); 8514 8515 if (guest_hlt) 8516 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8517 8518 irq_disable(); 8519 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | 8520 APIC_DM_FIXED | ipi_vector, 8521 0); 8522 8523 enter_guest(); 8524 8525 assert_exit_reason(VMX_EXTINT); 8526 report(!vmx_pending_event_guest_run, 8527 "Guest did not run before host received IPI"); 8528 8529 irq_enable(); 8530 asm volatile ("nop"); 8531 irq_disable(); 8532 report(vmx_pending_event_ipi_fired, 8533 "Got pending interrupt after IRQ enabled"); 8534 8535 if (guest_hlt) 8536 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 8537 8538 enter_guest(); 8539 report(vmx_pending_event_guest_run, 8540 "Guest finished running when no interrupt"); 8541 } 8542 8543 static void vmx_pending_event_test(void) 8544 { 8545 vmx_pending_event_test_core(false); 8546 } 8547 8548 static void vmx_pending_event_hlt_test(void) 8549 { 8550 vmx_pending_event_test_core(true); 8551 } 8552 8553 static int vmx_window_test_db_count; 8554 8555 static void vmx_window_test_db_handler(struct ex_regs *regs) 8556 { 8557 vmx_window_test_db_count++; 8558 } 8559 8560 static void vmx_nmi_window_test_guest(void) 8561 { 8562 handle_exception(DB_VECTOR, vmx_window_test_db_handler); 8563 8564 asm volatile("vmcall\n\t" 8565 "nop\n\t"); 8566 8567 handle_exception(DB_VECTOR, NULL); 8568 } 8569 8570 static void verify_nmi_window_exit(u64 rip) 8571 { 8572 u32 exit_reason = vmcs_read(EXI_REASON); 8573 8574 report(exit_reason == VMX_NMI_WINDOW, 8575 "Exit reason (%d) is 'NMI window'", exit_reason); 8576 report(vmcs_read(GUEST_RIP) == rip, "RIP (%#lx) is %#lx", 8577 vmcs_read(GUEST_RIP), rip); 8578 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 8579 } 8580 8581 static void vmx_nmi_window_test(void) 8582 { 8583 u64 nop_addr; 8584 void *db_fault_addr = get_idt_addr(&boot_idt[DB_VECTOR]); 8585 8586 if (!(ctrl_pin_rev.clr & PIN_VIRT_NMI)) { 8587 report_skip("CPU does not support the \"Virtual NMIs\" VM-execution control."); 8588 return; 8589 } 8590 8591 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 8592 report_skip("CPU does not support the \"NMI-window exiting\" VM-execution control."); 8593 return; 8594 } 8595 8596 vmx_window_test_db_count = 0; 8597 8598 report_prefix_push("NMI-window"); 8599 test_set_guest(vmx_nmi_window_test_guest); 8600 vmcs_set_bits(PIN_CONTROLS, PIN_VIRT_NMI); 8601 enter_guest(); 8602 skip_exit_vmcall(); 8603 nop_addr = vmcs_read(GUEST_RIP); 8604 8605 /* 8606 * Ask for "NMI-window exiting," and expect an immediate VM-exit. 8607 * RIP will not advance. 8608 */ 8609 report_prefix_push("active, no blocking"); 8610 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 8611 enter_guest(); 8612 verify_nmi_window_exit(nop_addr); 8613 report_prefix_pop(); 8614 8615 /* 8616 * Ask for "NMI-window exiting" in a MOV-SS shadow, and expect 8617 * a VM-exit on the next instruction after the nop. (The nop 8618 * is one byte.) 8619 */ 8620 report_prefix_push("active, blocking by MOV-SS"); 8621 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 8622 enter_guest(); 8623 verify_nmi_window_exit(nop_addr + 1); 8624 report_prefix_pop(); 8625 8626 /* 8627 * Ask for "NMI-window exiting" (with event injection), and 8628 * expect a VM-exit after the event is injected. (RIP should 8629 * be at the address specified in the IDT entry for #DB.) 8630 */ 8631 report_prefix_push("active, no blocking, injecting #DB"); 8632 vmcs_write(ENT_INTR_INFO, 8633 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 8634 enter_guest(); 8635 verify_nmi_window_exit((u64)db_fault_addr); 8636 report_prefix_pop(); 8637 8638 /* 8639 * Ask for "NMI-window exiting" with NMI blocking, and expect 8640 * a VM-exit after the next IRET (i.e. after the #DB handler 8641 * returns). So, RIP should be back at one byte past the nop. 8642 */ 8643 report_prefix_push("active, blocking by NMI"); 8644 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_NMI); 8645 enter_guest(); 8646 verify_nmi_window_exit(nop_addr + 1); 8647 report(vmx_window_test_db_count == 1, 8648 "#DB handler executed once (actual %d times)", 8649 vmx_window_test_db_count); 8650 report_prefix_pop(); 8651 8652 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 8653 report_skip("CPU does not support activity state HLT."); 8654 } else { 8655 /* 8656 * Ask for "NMI-window exiting" when entering activity 8657 * state HLT, and expect an immediate VM-exit. RIP is 8658 * still one byte past the nop. 8659 */ 8660 report_prefix_push("halted, no blocking"); 8661 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8662 enter_guest(); 8663 verify_nmi_window_exit(nop_addr + 1); 8664 report_prefix_pop(); 8665 8666 /* 8667 * Ask for "NMI-window exiting" when entering activity 8668 * state HLT (with event injection), and expect a 8669 * VM-exit after the event is injected. (RIP should be 8670 * at the address specified in the IDT entry for #DB.) 8671 */ 8672 report_prefix_push("halted, no blocking, injecting #DB"); 8673 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8674 vmcs_write(ENT_INTR_INFO, 8675 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 8676 DB_VECTOR); 8677 enter_guest(); 8678 verify_nmi_window_exit((u64)db_fault_addr); 8679 report_prefix_pop(); 8680 } 8681 8682 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 8683 enter_guest(); 8684 report_prefix_pop(); 8685 } 8686 8687 static void vmx_intr_window_test_guest(void) 8688 { 8689 handle_exception(DB_VECTOR, vmx_window_test_db_handler); 8690 8691 /* 8692 * The two consecutive STIs are to ensure that only the first 8693 * one has a shadow. Note that NOP and STI are one byte 8694 * instructions. 8695 */ 8696 asm volatile("vmcall\n\t" 8697 "nop\n\t" 8698 "sti\n\t" 8699 "sti\n\t"); 8700 8701 handle_exception(DB_VECTOR, NULL); 8702 } 8703 8704 static void verify_intr_window_exit(u64 rip) 8705 { 8706 u32 exit_reason = vmcs_read(EXI_REASON); 8707 8708 report(exit_reason == VMX_INTR_WINDOW, 8709 "Exit reason (%d) is 'interrupt window'", exit_reason); 8710 report(vmcs_read(GUEST_RIP) == rip, "RIP (%#lx) is %#lx", 8711 vmcs_read(GUEST_RIP), rip); 8712 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 8713 } 8714 8715 static void vmx_intr_window_test(void) 8716 { 8717 u64 vmcall_addr; 8718 u64 nop_addr; 8719 unsigned int orig_db_gate_type; 8720 void *db_fault_addr = get_idt_addr(&boot_idt[DB_VECTOR]); 8721 8722 if (!(ctrl_cpu_rev[0].clr & CPU_INTR_WINDOW)) { 8723 report_skip("CPU does not support the \"interrupt-window exiting\" VM-execution control."); 8724 return; 8725 } 8726 8727 /* 8728 * Change the IDT entry for #DB from interrupt gate to trap gate, 8729 * so that it won't clear RFLAGS.IF. We don't want interrupts to 8730 * be disabled after vectoring a #DB. 8731 */ 8732 orig_db_gate_type = boot_idt[DB_VECTOR].type; 8733 boot_idt[DB_VECTOR].type = 15; 8734 8735 report_prefix_push("interrupt-window"); 8736 test_set_guest(vmx_intr_window_test_guest); 8737 enter_guest(); 8738 assert_exit_reason(VMX_VMCALL); 8739 vmcall_addr = vmcs_read(GUEST_RIP); 8740 8741 /* 8742 * Ask for "interrupt-window exiting" with RFLAGS.IF set and 8743 * no blocking; expect an immediate VM-exit. Note that we have 8744 * not advanced past the vmcall instruction yet, so RIP should 8745 * point to the vmcall instruction. 8746 */ 8747 report_prefix_push("active, no blocking, RFLAGS.IF=1"); 8748 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8749 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_IF); 8750 enter_guest(); 8751 verify_intr_window_exit(vmcall_addr); 8752 report_prefix_pop(); 8753 8754 /* 8755 * Ask for "interrupt-window exiting" (with event injection) 8756 * with RFLAGS.IF set and no blocking; expect a VM-exit after 8757 * the event is injected. That is, RIP should should be at the 8758 * address specified in the IDT entry for #DB. 8759 */ 8760 report_prefix_push("active, no blocking, RFLAGS.IF=1, injecting #DB"); 8761 vmcs_write(ENT_INTR_INFO, 8762 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 8763 vmcall_addr = vmcs_read(GUEST_RIP); 8764 enter_guest(); 8765 verify_intr_window_exit((u64)db_fault_addr); 8766 report_prefix_pop(); 8767 8768 /* 8769 * Let the L2 guest run through the IRET, back to the VMCALL. 8770 * We have to clear the "interrupt-window exiting" 8771 * VM-execution control, or it would just keep causing 8772 * VM-exits. Then, advance past the VMCALL and set the 8773 * "interrupt-window exiting" VM-execution control again. 8774 */ 8775 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8776 enter_guest(); 8777 skip_exit_vmcall(); 8778 nop_addr = vmcs_read(GUEST_RIP); 8779 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8780 8781 /* 8782 * Ask for "interrupt-window exiting" in a MOV-SS shadow with 8783 * RFLAGS.IF set, and expect a VM-exit on the next 8784 * instruction. (NOP is one byte.) 8785 */ 8786 report_prefix_push("active, blocking by MOV-SS, RFLAGS.IF=1"); 8787 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 8788 enter_guest(); 8789 verify_intr_window_exit(nop_addr + 1); 8790 report_prefix_pop(); 8791 8792 /* 8793 * Back up to the NOP and ask for "interrupt-window exiting" 8794 * in an STI shadow with RFLAGS.IF set, and expect a VM-exit 8795 * on the next instruction. (NOP is one byte.) 8796 */ 8797 report_prefix_push("active, blocking by STI, RFLAGS.IF=1"); 8798 vmcs_write(GUEST_RIP, nop_addr); 8799 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_STI); 8800 enter_guest(); 8801 verify_intr_window_exit(nop_addr + 1); 8802 report_prefix_pop(); 8803 8804 /* 8805 * Ask for "interrupt-window exiting" with RFLAGS.IF clear, 8806 * and expect a VM-exit on the instruction following the STI 8807 * shadow. Only the first STI (which is one byte past the NOP) 8808 * should have a shadow. The second STI (which is two bytes 8809 * past the NOP) has no shadow. Therefore, the interrupt 8810 * window opens at three bytes past the NOP. 8811 */ 8812 report_prefix_push("active, RFLAGS.IF = 0"); 8813 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 8814 enter_guest(); 8815 verify_intr_window_exit(nop_addr + 3); 8816 report_prefix_pop(); 8817 8818 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 8819 report_skip("CPU does not support activity state HLT."); 8820 } else { 8821 /* 8822 * Ask for "interrupt-window exiting" when entering 8823 * activity state HLT, and expect an immediate 8824 * VM-exit. RIP is still three bytes past the nop. 8825 */ 8826 report_prefix_push("halted, no blocking"); 8827 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8828 enter_guest(); 8829 verify_intr_window_exit(nop_addr + 3); 8830 report_prefix_pop(); 8831 8832 /* 8833 * Ask for "interrupt-window exiting" when entering 8834 * activity state HLT (with event injection), and 8835 * expect a VM-exit after the event is injected. That 8836 * is, RIP should should be at the address specified 8837 * in the IDT entry for #DB. 8838 */ 8839 report_prefix_push("halted, no blocking, injecting #DB"); 8840 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8841 vmcs_write(ENT_INTR_INFO, 8842 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 8843 DB_VECTOR); 8844 enter_guest(); 8845 verify_intr_window_exit((u64)db_fault_addr); 8846 report_prefix_pop(); 8847 } 8848 8849 boot_idt[DB_VECTOR].type = orig_db_gate_type; 8850 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8851 enter_guest(); 8852 report_prefix_pop(); 8853 } 8854 8855 #define GUEST_TSC_OFFSET (1u << 30) 8856 8857 static u64 guest_tsc; 8858 8859 static void vmx_store_tsc_test_guest(void) 8860 { 8861 guest_tsc = rdtsc(); 8862 } 8863 8864 /* 8865 * This test ensures that when IA32_TSC is in the VM-exit MSR-store 8866 * list, the value saved is not subject to the TSC offset that is 8867 * applied to RDTSC/RDTSCP/RDMSR(IA32_TSC) in guest execution. 8868 */ 8869 static void vmx_store_tsc_test(void) 8870 { 8871 struct vmx_msr_entry msr_entry = { .index = MSR_IA32_TSC }; 8872 u64 low, high; 8873 8874 if (!(ctrl_cpu_rev[0].clr & CPU_USE_TSC_OFFSET)) { 8875 report_skip("'Use TSC offsetting' not supported"); 8876 return; 8877 } 8878 8879 test_set_guest(vmx_store_tsc_test_guest); 8880 8881 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_USE_TSC_OFFSET); 8882 vmcs_write(EXI_MSR_ST_CNT, 1); 8883 vmcs_write(EXIT_MSR_ST_ADDR, virt_to_phys(&msr_entry)); 8884 vmcs_write(TSC_OFFSET, GUEST_TSC_OFFSET); 8885 8886 low = rdtsc(); 8887 enter_guest(); 8888 high = rdtsc(); 8889 8890 report(low + GUEST_TSC_OFFSET <= guest_tsc && 8891 guest_tsc <= high + GUEST_TSC_OFFSET, 8892 "RDTSC value in the guest (%lu) is in range [%lu, %lu]", 8893 guest_tsc, low + GUEST_TSC_OFFSET, high + GUEST_TSC_OFFSET); 8894 report(low <= msr_entry.value && msr_entry.value <= high, 8895 "IA32_TSC value saved in the VM-exit MSR-store list (%lu) is in range [%lu, %lu]", 8896 msr_entry.value, low, high); 8897 } 8898 8899 static void vmx_preemption_timer_zero_test_db_handler(struct ex_regs *regs) 8900 { 8901 } 8902 8903 static void vmx_preemption_timer_zero_test_guest(void) 8904 { 8905 while (vmx_get_test_stage() < 3) 8906 vmcall(); 8907 } 8908 8909 static void vmx_preemption_timer_zero_activate_preemption_timer(void) 8910 { 8911 vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT); 8912 vmcs_write(PREEMPT_TIMER_VALUE, 0); 8913 } 8914 8915 static void vmx_preemption_timer_zero_advance_past_vmcall(void) 8916 { 8917 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 8918 enter_guest(); 8919 skip_exit_vmcall(); 8920 } 8921 8922 static void vmx_preemption_timer_zero_inject_db(bool intercept_db) 8923 { 8924 vmx_preemption_timer_zero_activate_preemption_timer(); 8925 vmcs_write(ENT_INTR_INFO, INTR_INFO_VALID_MASK | 8926 INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 8927 vmcs_write(EXC_BITMAP, intercept_db ? 1 << DB_VECTOR : 0); 8928 enter_guest(); 8929 } 8930 8931 static void vmx_preemption_timer_zero_set_pending_dbg(u32 exception_bitmap) 8932 { 8933 vmx_preemption_timer_zero_activate_preemption_timer(); 8934 vmcs_write(GUEST_PENDING_DEBUG, BIT(12) | DR_TRAP1); 8935 vmcs_write(EXC_BITMAP, exception_bitmap); 8936 enter_guest(); 8937 } 8938 8939 static void vmx_preemption_timer_zero_expect_preempt_at_rip(u64 expected_rip) 8940 { 8941 u32 reason = (u32)vmcs_read(EXI_REASON); 8942 u64 guest_rip = vmcs_read(GUEST_RIP); 8943 8944 report(reason == VMX_PREEMPT && guest_rip == expected_rip, 8945 "Exit reason is 0x%x (expected 0x%x) and guest RIP is %lx (0x%lx expected).", 8946 reason, VMX_PREEMPT, guest_rip, expected_rip); 8947 } 8948 8949 /* 8950 * This test ensures that when the VMX preemption timer is zero at 8951 * VM-entry, a VM-exit occurs after any event injection and after any 8952 * pending debug exceptions are raised, but before execution of any 8953 * guest instructions. 8954 */ 8955 static void vmx_preemption_timer_zero_test(void) 8956 { 8957 u64 db_fault_address = (u64)get_idt_addr(&boot_idt[DB_VECTOR]); 8958 handler old_db; 8959 u32 reason; 8960 8961 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 8962 report_skip("'Activate VMX-preemption timer' not supported"); 8963 return; 8964 } 8965 8966 /* 8967 * Install a custom #DB handler that doesn't abort. 8968 */ 8969 old_db = handle_exception(DB_VECTOR, 8970 vmx_preemption_timer_zero_test_db_handler); 8971 8972 test_set_guest(vmx_preemption_timer_zero_test_guest); 8973 8974 /* 8975 * VMX-preemption timer should fire after event injection. 8976 */ 8977 vmx_set_test_stage(0); 8978 vmx_preemption_timer_zero_inject_db(0); 8979 vmx_preemption_timer_zero_expect_preempt_at_rip(db_fault_address); 8980 vmx_preemption_timer_zero_advance_past_vmcall(); 8981 8982 /* 8983 * VMX-preemption timer should fire after event injection. 8984 * Exception bitmap is irrelevant, since you can't intercept 8985 * an event that you injected. 8986 */ 8987 vmx_set_test_stage(1); 8988 vmx_preemption_timer_zero_inject_db(true); 8989 vmx_preemption_timer_zero_expect_preempt_at_rip(db_fault_address); 8990 vmx_preemption_timer_zero_advance_past_vmcall(); 8991 8992 /* 8993 * VMX-preemption timer should fire after pending debug exceptions 8994 * have delivered a #DB trap. 8995 */ 8996 vmx_set_test_stage(2); 8997 vmx_preemption_timer_zero_set_pending_dbg(0); 8998 vmx_preemption_timer_zero_expect_preempt_at_rip(db_fault_address); 8999 vmx_preemption_timer_zero_advance_past_vmcall(); 9000 9001 /* 9002 * VMX-preemption timer would fire after pending debug exceptions 9003 * have delivered a #DB trap, but in this case, the #DB trap is 9004 * intercepted. 9005 */ 9006 vmx_set_test_stage(3); 9007 vmx_preemption_timer_zero_set_pending_dbg(1 << DB_VECTOR); 9008 reason = (u32)vmcs_read(EXI_REASON); 9009 report(reason == VMX_EXC_NMI, "Exit reason is 0x%x (expected 0x%x)", 9010 reason, VMX_EXC_NMI); 9011 9012 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 9013 enter_guest(); 9014 9015 handle_exception(DB_VECTOR, old_db); 9016 } 9017 9018 static u64 vmx_preemption_timer_tf_test_prev_rip; 9019 9020 static void vmx_preemption_timer_tf_test_db_handler(struct ex_regs *regs) 9021 { 9022 extern char vmx_preemption_timer_tf_test_endloop; 9023 9024 if (vmx_get_test_stage() == 2) { 9025 /* 9026 * Stage 2 means that we're done, one way or another. 9027 * Arrange for the iret to drop us out of the wbinvd 9028 * loop and stop single-stepping. 9029 */ 9030 regs->rip = (u64)&vmx_preemption_timer_tf_test_endloop; 9031 regs->rflags &= ~X86_EFLAGS_TF; 9032 } else if (regs->rip == vmx_preemption_timer_tf_test_prev_rip) { 9033 /* 9034 * The RIP should alternate between the wbinvd and the 9035 * jmp instruction in the code below. If we ever see 9036 * the same instruction twice in a row, that means a 9037 * single-step trap has been dropped. Let the 9038 * hypervisor know about the failure by executing a 9039 * VMCALL. 9040 */ 9041 vmcall(); 9042 } 9043 vmx_preemption_timer_tf_test_prev_rip = regs->rip; 9044 } 9045 9046 static void vmx_preemption_timer_tf_test_guest(void) 9047 { 9048 /* 9049 * The hypervisor doesn't intercept WBINVD, so the loop below 9050 * shouldn't be a problem--it's just two instructions 9051 * executing in VMX non-root mode. However, when the 9052 * hypervisor is running in a virtual environment, the parent 9053 * hypervisor might intercept WBINVD and emulate it. If the 9054 * parent hypervisor is broken, the single-step trap after the 9055 * WBINVD might be lost. 9056 */ 9057 asm volatile("vmcall\n\t" 9058 "0: wbinvd\n\t" 9059 "1: jmp 0b\n\t" 9060 "vmx_preemption_timer_tf_test_endloop:"); 9061 } 9062 9063 /* 9064 * Ensure that the delivery of a "VMX-preemption timer expired" 9065 * VM-exit doesn't disrupt single-stepping in the guest. Note that 9066 * passing this test doesn't ensure correctness, because the test will 9067 * only fail if the VMX-preemtion timer fires at the right time (or 9068 * the wrong time, as it were). 9069 */ 9070 static void vmx_preemption_timer_tf_test(void) 9071 { 9072 handler old_db; 9073 u32 reason; 9074 int i; 9075 9076 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 9077 report_skip("'Activate VMX-preemption timer' not supported"); 9078 return; 9079 } 9080 9081 old_db = handle_exception(DB_VECTOR, 9082 vmx_preemption_timer_tf_test_db_handler); 9083 9084 test_set_guest(vmx_preemption_timer_tf_test_guest); 9085 9086 enter_guest(); 9087 skip_exit_vmcall(); 9088 9089 vmx_set_test_stage(1); 9090 vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT); 9091 vmcs_write(PREEMPT_TIMER_VALUE, 50000); 9092 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_TF); 9093 9094 /* 9095 * The only exit we should see is "VMX-preemption timer 9096 * expired." If we get a VMCALL exit, that means the #DB 9097 * handler has detected a missing single-step trap. It doesn't 9098 * matter where the guest RIP is when the VMX-preemption timer 9099 * expires (whether it's in the WBINVD loop or in the #DB 9100 * handler)--a single-step trap should never be discarded. 9101 */ 9102 for (i = 0; i < 10000; i++) { 9103 enter_guest(); 9104 reason = (u32)vmcs_read(EXI_REASON); 9105 if (reason == VMX_PREEMPT) 9106 continue; 9107 TEST_ASSERT(reason == VMX_VMCALL); 9108 skip_exit_insn(); 9109 break; 9110 } 9111 9112 report(reason == VMX_PREEMPT, "No single-step traps skipped"); 9113 9114 vmx_set_test_stage(2); 9115 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 9116 enter_guest(); 9117 9118 handle_exception(DB_VECTOR, old_db); 9119 } 9120 9121 #define VMX_PREEMPTION_TIMER_EXPIRY_CYCLES 1000000 9122 9123 static u64 vmx_preemption_timer_expiry_start; 9124 static u64 vmx_preemption_timer_expiry_finish; 9125 9126 static void vmx_preemption_timer_expiry_test_guest(void) 9127 { 9128 vmcall(); 9129 vmx_preemption_timer_expiry_start = fenced_rdtsc(); 9130 9131 while (vmx_get_test_stage() == 0) 9132 vmx_preemption_timer_expiry_finish = fenced_rdtsc(); 9133 } 9134 9135 /* 9136 * Test that the VMX-preemption timer is not excessively delayed. 9137 * 9138 * Per the SDM, volume 3, VM-entry starts the VMX-preemption timer 9139 * with the unsigned value in the VMX-preemption timer-value field, 9140 * and the VMX-preemption timer counts down by 1 every time bit X in 9141 * the TSC changes due to a TSC increment (where X is 9142 * IA32_VMX_MISC[4:0]). If the timer counts down to zero in any state 9143 * other than the wait-for-SIPI state, the logical processor 9144 * transitions to the C0 C-state and causes a VM-exit. 9145 * 9146 * The guest code above reads the starting TSC after VM-entry. At this 9147 * point, the VMX-preemption timer has already been activated. Next, 9148 * the guest code reads the current TSC in a loop, storing the value 9149 * read to memory. 9150 * 9151 * If the RDTSC in the loop reads a value past the VMX-preemption 9152 * timer deadline, then the VMX-preemption timer VM-exit must be 9153 * delivered before the next instruction retires. Even if a higher 9154 * priority SMI is delivered first, the VMX-preemption timer VM-exit 9155 * must be delivered before the next instruction retires. Hence, a TSC 9156 * value past the VMX-preemption timer deadline might be read, but it 9157 * cannot be stored. If a TSC value past the deadline *is* stored, 9158 * then the architectural specification has been violated. 9159 */ 9160 static void vmx_preemption_timer_expiry_test(void) 9161 { 9162 u32 preemption_timer_value; 9163 union vmx_misc misc; 9164 u64 tsc_deadline; 9165 u32 reason; 9166 9167 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 9168 report_skip("'Activate VMX-preemption timer' not supported"); 9169 return; 9170 } 9171 9172 test_set_guest(vmx_preemption_timer_expiry_test_guest); 9173 9174 enter_guest(); 9175 skip_exit_vmcall(); 9176 9177 misc.val = rdmsr(MSR_IA32_VMX_MISC); 9178 preemption_timer_value = 9179 VMX_PREEMPTION_TIMER_EXPIRY_CYCLES >> misc.pt_bit; 9180 9181 vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT); 9182 vmcs_write(PREEMPT_TIMER_VALUE, preemption_timer_value); 9183 vmx_set_test_stage(0); 9184 9185 enter_guest(); 9186 reason = (u32)vmcs_read(EXI_REASON); 9187 TEST_ASSERT(reason == VMX_PREEMPT); 9188 9189 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 9190 vmx_set_test_stage(1); 9191 enter_guest(); 9192 9193 tsc_deadline = ((vmx_preemption_timer_expiry_start >> misc.pt_bit) << 9194 misc.pt_bit) + (preemption_timer_value << misc.pt_bit); 9195 9196 report(vmx_preemption_timer_expiry_finish < tsc_deadline, 9197 "Last stored guest TSC (%lu) < TSC deadline (%lu)", 9198 vmx_preemption_timer_expiry_finish, tsc_deadline); 9199 } 9200 9201 static void vmx_db_test_guest(void) 9202 { 9203 /* 9204 * For a hardware generated single-step #DB. 9205 */ 9206 asm volatile("vmcall;" 9207 "nop;" 9208 ".Lpost_nop:"); 9209 /* 9210 * ...in a MOVSS shadow, with pending debug exceptions. 9211 */ 9212 asm volatile("vmcall;" 9213 "nop;" 9214 ".Lpost_movss_nop:"); 9215 /* 9216 * For an L0 synthesized single-step #DB. (L0 intercepts WBINVD and 9217 * emulates it in software.) 9218 */ 9219 asm volatile("vmcall;" 9220 "wbinvd;" 9221 ".Lpost_wbinvd:"); 9222 /* 9223 * ...in a MOVSS shadow, with pending debug exceptions. 9224 */ 9225 asm volatile("vmcall;" 9226 "wbinvd;" 9227 ".Lpost_movss_wbinvd:"); 9228 /* 9229 * For a hardware generated single-step #DB in a transactional region. 9230 */ 9231 asm volatile("vmcall;" 9232 ".Lxbegin: xbegin .Lskip_rtm;" 9233 "xend;" 9234 ".Lskip_rtm:"); 9235 } 9236 9237 /* 9238 * Clear the pending debug exceptions and RFLAGS.TF and re-enter 9239 * L2. No #DB is delivered and L2 continues to the next point of 9240 * interest. 9241 */ 9242 static void dismiss_db(void) 9243 { 9244 vmcs_write(GUEST_PENDING_DEBUG, 0); 9245 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 9246 enter_guest(); 9247 } 9248 9249 /* 9250 * Check a variety of VMCS fields relevant to an intercepted #DB exception. 9251 * Then throw away the #DB exception and resume L2. 9252 */ 9253 static void check_db_exit(bool xfail_qual, bool xfail_dr6, bool xfail_pdbg, 9254 void *expected_rip, u64 expected_exit_qual, 9255 u64 expected_dr6) 9256 { 9257 u32 reason = vmcs_read(EXI_REASON); 9258 u32 intr_info = vmcs_read(EXI_INTR_INFO); 9259 u64 exit_qual = vmcs_read(EXI_QUALIFICATION); 9260 u64 guest_rip = vmcs_read(GUEST_RIP); 9261 u64 guest_pending_dbg = vmcs_read(GUEST_PENDING_DEBUG); 9262 u64 dr6 = read_dr6(); 9263 const u32 expected_intr_info = INTR_INFO_VALID_MASK | 9264 INTR_TYPE_HARD_EXCEPTION | DB_VECTOR; 9265 9266 report(reason == VMX_EXC_NMI && intr_info == expected_intr_info, 9267 "Expected #DB VM-exit"); 9268 report((u64)expected_rip == guest_rip, "Expected RIP %p (actual %lx)", 9269 expected_rip, guest_rip); 9270 report_xfail(xfail_pdbg, 0 == guest_pending_dbg, 9271 "Expected pending debug exceptions 0 (actual %lx)", 9272 guest_pending_dbg); 9273 report_xfail(xfail_qual, expected_exit_qual == exit_qual, 9274 "Expected exit qualification %lx (actual %lx)", 9275 expected_exit_qual, exit_qual); 9276 report_xfail(xfail_dr6, expected_dr6 == dr6, 9277 "Expected DR6 %lx (actual %lx)", expected_dr6, dr6); 9278 dismiss_db(); 9279 } 9280 9281 /* 9282 * Assuming the guest has just exited on a VMCALL instruction, skip 9283 * over the vmcall, and set the guest's RFLAGS.TF in the VMCS. If 9284 * pending debug exceptions are non-zero, set the VMCS up as if the 9285 * previous instruction was a MOVSS that generated the indicated 9286 * pending debug exceptions. Then enter L2. 9287 */ 9288 static void single_step_guest(const char *test_name, u64 starting_dr6, 9289 u64 pending_debug_exceptions) 9290 { 9291 printf("\n%s\n", test_name); 9292 skip_exit_vmcall(); 9293 write_dr6(starting_dr6); 9294 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_TF); 9295 if (pending_debug_exceptions) { 9296 vmcs_write(GUEST_PENDING_DEBUG, pending_debug_exceptions); 9297 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 9298 } 9299 enter_guest(); 9300 } 9301 9302 /* 9303 * When L1 intercepts #DB, verify that a single-step trap clears 9304 * pending debug exceptions, populates the exit qualification field 9305 * properly, and that DR6 is not prematurely clobbered. In a 9306 * (simulated) MOVSS shadow, make sure that the pending debug 9307 * exception bits are properly accumulated into the exit qualification 9308 * field. 9309 */ 9310 static void vmx_db_test(void) 9311 { 9312 /* 9313 * We are going to set a few arbitrary bits in DR6 to verify that 9314 * (a) DR6 is not modified by an intercepted #DB, and 9315 * (b) stale bits in DR6 (DR6.BD, in particular) don't leak into 9316 * the exit qualification field for a subsequent #DB exception. 9317 */ 9318 const u64 starting_dr6 = DR6_RESERVED | BIT(13) | DR_TRAP3 | DR_TRAP1; 9319 extern char post_nop asm(".Lpost_nop"); 9320 extern char post_movss_nop asm(".Lpost_movss_nop"); 9321 extern char post_wbinvd asm(".Lpost_wbinvd"); 9322 extern char post_movss_wbinvd asm(".Lpost_movss_wbinvd"); 9323 extern char xbegin asm(".Lxbegin"); 9324 extern char skip_rtm asm(".Lskip_rtm"); 9325 9326 /* 9327 * L1 wants to intercept #DB exceptions encountered in L2. 9328 */ 9329 vmcs_write(EXC_BITMAP, BIT(DB_VECTOR)); 9330 9331 /* 9332 * Start L2 and run it up to the first point of interest. 9333 */ 9334 test_set_guest(vmx_db_test_guest); 9335 enter_guest(); 9336 9337 /* 9338 * Hardware-delivered #DB trap for single-step sets the 9339 * standard that L0 has to follow for emulated instructions. 9340 */ 9341 single_step_guest("Hardware delivered single-step", starting_dr6, 0); 9342 check_db_exit(false, false, false, &post_nop, DR_STEP, starting_dr6); 9343 9344 /* 9345 * Hardware-delivered #DB trap for single-step in MOVSS shadow 9346 * also sets the standard that L0 has to follow for emulated 9347 * instructions. Here, we establish the VMCS pending debug 9348 * exceptions to indicate that the simulated MOVSS triggered a 9349 * data breakpoint as well as the single-step trap. 9350 */ 9351 single_step_guest("Hardware delivered single-step in MOVSS shadow", 9352 starting_dr6, BIT(12) | DR_STEP | DR_TRAP0 ); 9353 check_db_exit(false, false, false, &post_movss_nop, DR_STEP | DR_TRAP0, 9354 starting_dr6); 9355 9356 /* 9357 * L0 synthesized #DB trap for single-step is buggy, because 9358 * kvm (a) clobbers DR6 too early, and (b) tries its best to 9359 * reconstitute the exit qualification from the prematurely 9360 * modified DR6, but fails miserably. 9361 */ 9362 single_step_guest("Software synthesized single-step", starting_dr6, 0); 9363 check_db_exit(false, false, false, &post_wbinvd, DR_STEP, starting_dr6); 9364 9365 /* 9366 * L0 synthesized #DB trap for single-step in MOVSS shadow is 9367 * even worse, because L0 also leaves the pending debug 9368 * exceptions in the VMCS instead of accumulating them into 9369 * the exit qualification field for the #DB exception. 9370 */ 9371 single_step_guest("Software synthesized single-step in MOVSS shadow", 9372 starting_dr6, BIT(12) | DR_STEP | DR_TRAP0); 9373 check_db_exit(true, false, true, &post_movss_wbinvd, DR_STEP | DR_TRAP0, 9374 starting_dr6); 9375 9376 /* 9377 * Optional RTM test for hardware that supports RTM, to 9378 * demonstrate that the current volume 3 of the SDM 9379 * (325384-067US), table 27-1 is incorrect. Bit 16 of the exit 9380 * qualification for debug exceptions is not reserved. It is 9381 * set to 1 if a debug exception (#DB) or a breakpoint 9382 * exception (#BP) occurs inside an RTM region while advanced 9383 * debugging of RTM transactional regions is enabled. 9384 */ 9385 if (this_cpu_has(X86_FEATURE_RTM)) { 9386 vmcs_write(ENT_CONTROLS, 9387 vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 9388 /* 9389 * Set DR7.RTM[bit 11] and IA32_DEBUGCTL.RTM[bit 15] 9390 * in the guest to enable advanced debugging of RTM 9391 * transactional regions. 9392 */ 9393 vmcs_write(GUEST_DR7, BIT(11)); 9394 vmcs_write(GUEST_DEBUGCTL, BIT(15)); 9395 single_step_guest("Hardware delivered single-step in " 9396 "transactional region", starting_dr6, 0); 9397 check_db_exit(false, false, false, &xbegin, BIT(16), 9398 starting_dr6); 9399 } else { 9400 vmcs_write(GUEST_RIP, (u64)&skip_rtm); 9401 enter_guest(); 9402 } 9403 } 9404 9405 static void enable_vid(void) 9406 { 9407 void *virtual_apic_page; 9408 9409 assert(cpu_has_apicv()); 9410 9411 disable_intercept_for_x2apic_msrs(); 9412 9413 virtual_apic_page = alloc_page(); 9414 vmcs_write(APIC_VIRT_ADDR, (u64)virtual_apic_page); 9415 9416 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 9417 9418 vmcs_write(EOI_EXIT_BITMAP0, 0x0); 9419 vmcs_write(EOI_EXIT_BITMAP1, 0x0); 9420 vmcs_write(EOI_EXIT_BITMAP2, 0x0); 9421 vmcs_write(EOI_EXIT_BITMAP3, 0x0); 9422 9423 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY | CPU_TPR_SHADOW); 9424 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_VINTD | CPU_VIRT_X2APIC); 9425 } 9426 9427 static void trigger_ioapic_scan_thread(void *data) 9428 { 9429 /* Wait until other CPU entered L2 */ 9430 while (vmx_get_test_stage() != 1) 9431 ; 9432 9433 /* Trigger ioapic scan */ 9434 ioapic_set_redir(0xf, 0x79, TRIGGER_LEVEL); 9435 vmx_set_test_stage(2); 9436 } 9437 9438 static void irq_79_handler_guest(isr_regs_t *regs) 9439 { 9440 eoi(); 9441 9442 /* L1 expects vmexit on VMX_VMCALL and not VMX_EOI_INDUCED */ 9443 vmcall(); 9444 } 9445 9446 /* 9447 * Constant for num of busy-loop iterations after which 9448 * a timer interrupt should have happened in host 9449 */ 9450 #define TIMER_INTERRUPT_DELAY 100000000 9451 9452 static void vmx_eoi_bitmap_ioapic_scan_test_guest(void) 9453 { 9454 handle_irq(0x79, irq_79_handler_guest); 9455 irq_enable(); 9456 9457 /* Signal to L1 CPU to trigger ioapic scan */ 9458 vmx_set_test_stage(1); 9459 /* Wait until L1 CPU to trigger ioapic scan */ 9460 while (vmx_get_test_stage() != 2) 9461 ; 9462 9463 /* 9464 * Wait for L0 timer interrupt to be raised while we run in L2 9465 * such that L0 will process the IOAPIC scan request before 9466 * resuming L2 9467 */ 9468 delay(TIMER_INTERRUPT_DELAY); 9469 9470 asm volatile ("int $0x79"); 9471 } 9472 9473 static void vmx_eoi_bitmap_ioapic_scan_test(void) 9474 { 9475 if (!cpu_has_apicv() || (cpu_count() < 2)) { 9476 report_skip(__func__); 9477 return; 9478 } 9479 9480 enable_vid(); 9481 9482 on_cpu_async(1, trigger_ioapic_scan_thread, NULL); 9483 test_set_guest(vmx_eoi_bitmap_ioapic_scan_test_guest); 9484 9485 /* 9486 * Launch L2. 9487 * We expect the exit reason to be VMX_VMCALL (and not EOI INDUCED). 9488 * In case the reason isn't VMX_VMCALL, the asserion inside 9489 * skip_exit_vmcall() will fail. 9490 */ 9491 enter_guest(); 9492 skip_exit_vmcall(); 9493 9494 /* Let L2 finish */ 9495 enter_guest(); 9496 report_pass(__func__); 9497 } 9498 9499 #define HLT_WITH_RVI_VECTOR (0xf1) 9500 9501 bool vmx_hlt_with_rvi_guest_isr_fired; 9502 static void vmx_hlt_with_rvi_guest_isr(isr_regs_t *regs) 9503 { 9504 vmx_hlt_with_rvi_guest_isr_fired = true; 9505 eoi(); 9506 } 9507 9508 static void vmx_hlt_with_rvi_guest(void) 9509 { 9510 handle_irq(HLT_WITH_RVI_VECTOR, vmx_hlt_with_rvi_guest_isr); 9511 9512 irq_enable(); 9513 asm volatile ("nop"); 9514 9515 vmcall(); 9516 } 9517 9518 static void vmx_hlt_with_rvi_test(void) 9519 { 9520 if (!cpu_has_apicv()) { 9521 report_skip(__func__); 9522 return; 9523 } 9524 9525 enable_vid(); 9526 9527 vmx_hlt_with_rvi_guest_isr_fired = false; 9528 test_set_guest(vmx_hlt_with_rvi_guest); 9529 9530 enter_guest(); 9531 skip_exit_vmcall(); 9532 9533 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 9534 vmcs_write(GUEST_INT_STATUS, HLT_WITH_RVI_VECTOR); 9535 enter_guest(); 9536 9537 report(vmx_hlt_with_rvi_guest_isr_fired, "Interrupt raised in guest"); 9538 } 9539 9540 static void set_irq_line_thread(void *data) 9541 { 9542 /* Wait until other CPU entered L2 */ 9543 while (vmx_get_test_stage() != 1) 9544 ; 9545 9546 /* Set irq-line 0xf to raise vector 0x78 for vCPU 0 */ 9547 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 9548 vmx_set_test_stage(2); 9549 } 9550 9551 static bool irq_78_handler_vmcall_before_eoi; 9552 static void irq_78_handler_guest(isr_regs_t *regs) 9553 { 9554 set_irq_line(0xf, 0); 9555 if (irq_78_handler_vmcall_before_eoi) 9556 vmcall(); 9557 eoi(); 9558 vmcall(); 9559 } 9560 9561 static void vmx_apic_passthrough_guest(void) 9562 { 9563 handle_irq(0x78, irq_78_handler_guest); 9564 irq_enable(); 9565 9566 /* If requested, wait for other CPU to trigger ioapic scan */ 9567 if (vmx_get_test_stage() < 1) { 9568 vmx_set_test_stage(1); 9569 while (vmx_get_test_stage() != 2) 9570 ; 9571 } 9572 9573 set_irq_line(0xf, 1); 9574 } 9575 9576 static void vmx_apic_passthrough(bool set_irq_line_from_thread) 9577 { 9578 if (set_irq_line_from_thread && (cpu_count() < 2)) { 9579 report_skip(__func__); 9580 return; 9581 } 9582 9583 /* Test device is required for generating IRQs */ 9584 if (!test_device_enabled()) { 9585 report_skip(__func__); 9586 return; 9587 } 9588 u64 cpu_ctrl_0 = CPU_SECONDARY; 9589 u64 cpu_ctrl_1 = 0; 9590 9591 disable_intercept_for_x2apic_msrs(); 9592 9593 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 9594 9595 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 9596 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 9597 9598 if (set_irq_line_from_thread) { 9599 irq_78_handler_vmcall_before_eoi = false; 9600 on_cpu_async(1, set_irq_line_thread, NULL); 9601 } else { 9602 irq_78_handler_vmcall_before_eoi = true; 9603 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 9604 vmx_set_test_stage(2); 9605 } 9606 test_set_guest(vmx_apic_passthrough_guest); 9607 9608 if (irq_78_handler_vmcall_before_eoi) { 9609 /* Before EOI remote_irr should still be set */ 9610 enter_guest(); 9611 skip_exit_vmcall(); 9612 TEST_ASSERT_EQ_MSG(1, (int)ioapic_read_redir(0xf).remote_irr, 9613 "IOAPIC pass-through: remote_irr=1 before EOI"); 9614 } 9615 9616 /* After EOI remote_irr should be cleared */ 9617 enter_guest(); 9618 skip_exit_vmcall(); 9619 TEST_ASSERT_EQ_MSG(0, (int)ioapic_read_redir(0xf).remote_irr, 9620 "IOAPIC pass-through: remote_irr=0 after EOI"); 9621 9622 /* Let L2 finish */ 9623 enter_guest(); 9624 report_pass(__func__); 9625 } 9626 9627 static void vmx_apic_passthrough_test(void) 9628 { 9629 vmx_apic_passthrough(false); 9630 } 9631 9632 static void vmx_apic_passthrough_thread_test(void) 9633 { 9634 vmx_apic_passthrough(true); 9635 } 9636 9637 static void vmx_apic_passthrough_tpr_threshold_guest(void) 9638 { 9639 cli(); 9640 apic_set_tpr(0); 9641 } 9642 9643 static bool vmx_apic_passthrough_tpr_threshold_ipi_isr_fired; 9644 static void vmx_apic_passthrough_tpr_threshold_ipi_isr(isr_regs_t *regs) 9645 { 9646 vmx_apic_passthrough_tpr_threshold_ipi_isr_fired = true; 9647 eoi(); 9648 } 9649 9650 static void vmx_apic_passthrough_tpr_threshold_test(void) 9651 { 9652 int ipi_vector = 0xe1; 9653 9654 disable_intercept_for_x2apic_msrs(); 9655 vmcs_clear_bits(PIN_CONTROLS, PIN_EXTINT); 9656 9657 /* Raise L0 TPR-threshold by queueing vector in LAPIC IRR */ 9658 cli(); 9659 apic_set_tpr((ipi_vector >> 4) + 1); 9660 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | 9661 APIC_DM_FIXED | ipi_vector, 9662 0); 9663 9664 test_set_guest(vmx_apic_passthrough_tpr_threshold_guest); 9665 enter_guest(); 9666 9667 report(apic_get_tpr() == 0, "TPR was zero by guest"); 9668 9669 /* Clean pending self-IPI */ 9670 vmx_apic_passthrough_tpr_threshold_ipi_isr_fired = false; 9671 handle_irq(ipi_vector, vmx_apic_passthrough_tpr_threshold_ipi_isr); 9672 sti(); 9673 asm volatile ("nop"); 9674 report(vmx_apic_passthrough_tpr_threshold_ipi_isr_fired, "self-IPI fired"); 9675 9676 report_pass(__func__); 9677 } 9678 9679 static u64 init_signal_test_exit_reason; 9680 static bool init_signal_test_thread_continued; 9681 9682 static void init_signal_test_thread(void *data) 9683 { 9684 struct vmcs *test_vmcs = data; 9685 9686 /* Enter VMX operation (i.e. exec VMXON) */ 9687 u64 *ap_vmxon_region = alloc_page(); 9688 enable_vmx(); 9689 init_vmx(ap_vmxon_region); 9690 _vmx_on(ap_vmxon_region); 9691 9692 /* Signal CPU have entered VMX operation */ 9693 vmx_set_test_stage(1); 9694 9695 /* Wait for BSP CPU to send INIT signal */ 9696 while (vmx_get_test_stage() != 2) 9697 ; 9698 9699 /* 9700 * Signal that we continue as usual as INIT signal 9701 * should be blocked while CPU is in VMX operation 9702 */ 9703 vmx_set_test_stage(3); 9704 9705 /* Wait for signal to enter VMX non-root mode */ 9706 while (vmx_get_test_stage() != 4) 9707 ; 9708 9709 /* Enter VMX non-root mode */ 9710 test_set_guest(v2_null_test_guest); 9711 make_vmcs_current(test_vmcs); 9712 enter_guest(); 9713 /* Save exit reason for BSP CPU to compare to expected result */ 9714 init_signal_test_exit_reason = vmcs_read(EXI_REASON); 9715 /* VMCLEAR test-vmcs so it could be loaded by BSP CPU */ 9716 vmcs_clear(test_vmcs); 9717 launched = false; 9718 /* Signal that CPU exited to VMX root mode */ 9719 vmx_set_test_stage(5); 9720 9721 /* Wait for BSP CPU to signal to exit VMX operation */ 9722 while (vmx_get_test_stage() != 6) 9723 ; 9724 9725 /* Exit VMX operation (i.e. exec VMXOFF) */ 9726 vmx_off(); 9727 9728 /* 9729 * Signal to BSP CPU that we continue as usual as INIT signal 9730 * should have been consumed by VMX_INIT exit from guest 9731 */ 9732 vmx_set_test_stage(7); 9733 9734 /* Wait for BSP CPU to signal to enter VMX operation */ 9735 while (vmx_get_test_stage() != 8) 9736 ; 9737 /* Enter VMX operation (i.e. exec VMXON) */ 9738 _vmx_on(ap_vmxon_region); 9739 /* Signal to BSP we are in VMX operation */ 9740 vmx_set_test_stage(9); 9741 9742 /* Wait for BSP CPU to send INIT signal */ 9743 while (vmx_get_test_stage() != 10) 9744 ; 9745 9746 /* Exit VMX operation (i.e. exec VMXOFF) */ 9747 vmx_off(); 9748 9749 /* 9750 * Exiting VMX operation should result in latched 9751 * INIT signal being processed. Therefore, we should 9752 * never reach the below code. Thus, signal to BSP 9753 * CPU if we have reached here so it is able to 9754 * report an issue if it happens. 9755 */ 9756 init_signal_test_thread_continued = true; 9757 } 9758 9759 #define INIT_SIGNAL_TEST_DELAY 100000000ULL 9760 9761 static void vmx_init_signal_test(void) 9762 { 9763 struct vmcs *test_vmcs; 9764 9765 if (cpu_count() < 2) { 9766 report_skip(__func__); 9767 return; 9768 } 9769 9770 /* VMCLEAR test-vmcs so it could be loaded by other CPU */ 9771 vmcs_save(&test_vmcs); 9772 vmcs_clear(test_vmcs); 9773 9774 vmx_set_test_stage(0); 9775 on_cpu_async(1, init_signal_test_thread, test_vmcs); 9776 9777 /* Wait for other CPU to enter VMX operation */ 9778 while (vmx_get_test_stage() != 1) 9779 ; 9780 9781 /* Send INIT signal to other CPU */ 9782 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_INIT | APIC_INT_ASSERT, 9783 id_map[1]); 9784 /* Signal other CPU we have sent INIT signal */ 9785 vmx_set_test_stage(2); 9786 9787 /* 9788 * Wait reasonable amount of time for INIT signal to 9789 * be received on other CPU and verify that other CPU 9790 * have proceed as usual to next test stage as INIT 9791 * signal should be blocked while other CPU in 9792 * VMX operation 9793 */ 9794 delay(INIT_SIGNAL_TEST_DELAY); 9795 report(vmx_get_test_stage() == 3, 9796 "INIT signal blocked when CPU in VMX operation"); 9797 /* No point to continue if we failed at this point */ 9798 if (vmx_get_test_stage() != 3) 9799 return; 9800 9801 /* Signal other CPU to enter VMX non-root mode */ 9802 init_signal_test_exit_reason = -1ull; 9803 vmx_set_test_stage(4); 9804 /* 9805 * Wait reasonable amont of time for other CPU 9806 * to exit to VMX root mode 9807 */ 9808 delay(INIT_SIGNAL_TEST_DELAY); 9809 if (vmx_get_test_stage() != 5) { 9810 report_fail("Pending INIT signal didn't result in VMX exit"); 9811 return; 9812 } 9813 report(init_signal_test_exit_reason == VMX_INIT, 9814 "INIT signal during VMX non-root mode result in exit-reason %s (%lu)", 9815 exit_reason_description(init_signal_test_exit_reason), 9816 init_signal_test_exit_reason); 9817 9818 /* Run guest to completion */ 9819 make_vmcs_current(test_vmcs); 9820 enter_guest(); 9821 9822 /* Signal other CPU to exit VMX operation */ 9823 init_signal_test_thread_continued = false; 9824 vmx_set_test_stage(6); 9825 9826 /* Wait reasonable amount of time for other CPU to exit VMX operation */ 9827 delay(INIT_SIGNAL_TEST_DELAY); 9828 report(vmx_get_test_stage() == 7, 9829 "INIT signal consumed on VMX_INIT exit"); 9830 /* No point to continue if we failed at this point */ 9831 if (vmx_get_test_stage() != 7) 9832 return; 9833 9834 /* Signal other CPU to enter VMX operation */ 9835 vmx_set_test_stage(8); 9836 /* Wait for other CPU to enter VMX operation */ 9837 while (vmx_get_test_stage() != 9) 9838 ; 9839 9840 /* Send INIT signal to other CPU */ 9841 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_INIT | APIC_INT_ASSERT, 9842 id_map[1]); 9843 /* Signal other CPU we have sent INIT signal */ 9844 vmx_set_test_stage(10); 9845 9846 /* 9847 * Wait reasonable amount of time for other CPU 9848 * to exit VMX operation and process INIT signal 9849 */ 9850 delay(INIT_SIGNAL_TEST_DELAY); 9851 report(!init_signal_test_thread_continued, 9852 "INIT signal processed after exit VMX operation"); 9853 9854 /* 9855 * TODO: Send SIPI to other CPU to sipi_entry (See x86/cstart64.S) 9856 * to re-init it to kvm-unit-tests standard environment. 9857 * Somehow (?) verify that SIPI was indeed received. 9858 */ 9859 } 9860 9861 #define SIPI_SIGNAL_TEST_DELAY 100000000ULL 9862 9863 static void vmx_sipi_test_guest(void) 9864 { 9865 if (apic_id() == 0) { 9866 /* wait AP enter guest with activity=WAIT_SIPI */ 9867 while (vmx_get_test_stage() != 1) 9868 ; 9869 delay(SIPI_SIGNAL_TEST_DELAY); 9870 9871 /* First SIPI signal */ 9872 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_STARTUP | APIC_INT_ASSERT, id_map[1]); 9873 report_pass("BSP(L2): Send first SIPI to cpu[%d]", id_map[1]); 9874 9875 /* wait AP enter guest */ 9876 while (vmx_get_test_stage() != 2) 9877 ; 9878 delay(SIPI_SIGNAL_TEST_DELAY); 9879 9880 /* Second SIPI signal should be ignored since AP is not in WAIT_SIPI state */ 9881 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_STARTUP | APIC_INT_ASSERT, id_map[1]); 9882 report_pass("BSP(L2): Send second SIPI to cpu[%d]", id_map[1]); 9883 9884 /* Delay a while to check whether second SIPI would cause VMExit */ 9885 delay(SIPI_SIGNAL_TEST_DELAY); 9886 9887 /* Test is done, notify AP to exit test */ 9888 vmx_set_test_stage(3); 9889 9890 /* wait AP exit non-root mode */ 9891 while (vmx_get_test_stage() != 5) 9892 ; 9893 } else { 9894 /* wait BSP notify test is done */ 9895 while (vmx_get_test_stage() != 3) 9896 ; 9897 9898 /* AP exit guest */ 9899 vmx_set_test_stage(4); 9900 } 9901 } 9902 9903 static void sipi_test_ap_thread(void *data) 9904 { 9905 struct vmcs *ap_vmcs; 9906 u64 *ap_vmxon_region; 9907 void *ap_stack, *ap_syscall_stack; 9908 u64 cpu_ctrl_0 = CPU_SECONDARY; 9909 u64 cpu_ctrl_1 = 0; 9910 9911 /* Enter VMX operation (i.e. exec VMXON) */ 9912 ap_vmxon_region = alloc_page(); 9913 enable_vmx(); 9914 init_vmx(ap_vmxon_region); 9915 _vmx_on(ap_vmxon_region); 9916 init_vmcs(&ap_vmcs); 9917 make_vmcs_current(ap_vmcs); 9918 9919 /* Set stack for AP */ 9920 ap_stack = alloc_page(); 9921 ap_syscall_stack = alloc_page(); 9922 vmcs_write(GUEST_RSP, (u64)(ap_stack + PAGE_SIZE - 1)); 9923 vmcs_write(GUEST_SYSENTER_ESP, (u64)(ap_syscall_stack + PAGE_SIZE - 1)); 9924 9925 /* passthrough lapic to L2 */ 9926 disable_intercept_for_x2apic_msrs(); 9927 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 9928 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 9929 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 9930 9931 /* Set guest activity state to wait-for-SIPI state */ 9932 vmcs_write(GUEST_ACTV_STATE, ACTV_WAIT_SIPI); 9933 9934 vmx_set_test_stage(1); 9935 9936 /* AP enter guest */ 9937 enter_guest(); 9938 9939 if (vmcs_read(EXI_REASON) == VMX_SIPI) { 9940 report_pass("AP: Handle SIPI VMExit"); 9941 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 9942 vmx_set_test_stage(2); 9943 } else { 9944 report_fail("AP: Unexpected VMExit, reason=%ld", vmcs_read(EXI_REASON)); 9945 vmx_off(); 9946 return; 9947 } 9948 9949 /* AP enter guest */ 9950 enter_guest(); 9951 9952 report(vmcs_read(EXI_REASON) != VMX_SIPI, 9953 "AP: should no SIPI VMExit since activity is not in WAIT_SIPI state"); 9954 9955 /* notify BSP that AP is already exit from non-root mode */ 9956 vmx_set_test_stage(5); 9957 9958 /* Leave VMX operation */ 9959 vmx_off(); 9960 } 9961 9962 static void vmx_sipi_signal_test(void) 9963 { 9964 if (!(rdmsr(MSR_IA32_VMX_MISC) & MSR_IA32_VMX_MISC_ACTIVITY_WAIT_SIPI)) { 9965 printf("\tACTIVITY_WAIT_SIPI state is not supported.\n"); 9966 return; 9967 } 9968 9969 if (cpu_count() < 2) { 9970 report_skip(__func__); 9971 return; 9972 } 9973 9974 u64 cpu_ctrl_0 = CPU_SECONDARY; 9975 u64 cpu_ctrl_1 = 0; 9976 9977 /* passthrough lapic to L2 */ 9978 disable_intercept_for_x2apic_msrs(); 9979 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 9980 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 9981 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 9982 9983 test_set_guest(vmx_sipi_test_guest); 9984 9985 /* update CR3 on AP */ 9986 on_cpu(1, update_cr3, (void *)read_cr3()); 9987 9988 /* start AP */ 9989 on_cpu_async(1, sipi_test_ap_thread, NULL); 9990 9991 vmx_set_test_stage(0); 9992 9993 /* BSP enter guest */ 9994 enter_guest(); 9995 } 9996 9997 9998 enum vmcs_access { 9999 ACCESS_VMREAD, 10000 ACCESS_VMWRITE, 10001 ACCESS_NONE, 10002 }; 10003 10004 struct vmcs_shadow_test_common { 10005 enum vmcs_access op; 10006 enum Reason reason; 10007 u64 field; 10008 u64 value; 10009 u64 flags; 10010 u64 time; 10011 } l1_l2_common; 10012 10013 static inline u64 vmread_flags(u64 field, u64 *val) 10014 { 10015 u64 flags; 10016 10017 asm volatile ("vmread %2, %1; pushf; pop %0" 10018 : "=r" (flags), "=rm" (*val) : "r" (field) : "cc"); 10019 return flags & X86_EFLAGS_ALU; 10020 } 10021 10022 static inline u64 vmwrite_flags(u64 field, u64 val) 10023 { 10024 u64 flags; 10025 10026 asm volatile ("vmwrite %1, %2; pushf; pop %0" 10027 : "=r"(flags) : "rm" (val), "r" (field) : "cc"); 10028 return flags & X86_EFLAGS_ALU; 10029 } 10030 10031 static void vmx_vmcs_shadow_test_guest(void) 10032 { 10033 struct vmcs_shadow_test_common *c = &l1_l2_common; 10034 u64 start; 10035 10036 while (c->op != ACCESS_NONE) { 10037 start = rdtsc(); 10038 switch (c->op) { 10039 default: 10040 c->flags = -1ull; 10041 break; 10042 case ACCESS_VMREAD: 10043 c->flags = vmread_flags(c->field, &c->value); 10044 break; 10045 case ACCESS_VMWRITE: 10046 c->flags = vmwrite_flags(c->field, 0); 10047 break; 10048 } 10049 c->time = rdtsc() - start; 10050 vmcall(); 10051 } 10052 } 10053 10054 static u64 vmread_from_shadow(u64 field) 10055 { 10056 struct vmcs *primary; 10057 struct vmcs *shadow; 10058 u64 value; 10059 10060 TEST_ASSERT(!vmcs_save(&primary)); 10061 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 10062 TEST_ASSERT(!make_vmcs_current(shadow)); 10063 value = vmcs_read(field); 10064 TEST_ASSERT(!make_vmcs_current(primary)); 10065 return value; 10066 } 10067 10068 static u64 vmwrite_to_shadow(u64 field, u64 value) 10069 { 10070 struct vmcs *primary; 10071 struct vmcs *shadow; 10072 10073 TEST_ASSERT(!vmcs_save(&primary)); 10074 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 10075 TEST_ASSERT(!make_vmcs_current(shadow)); 10076 vmcs_write(field, value); 10077 value = vmcs_read(field); 10078 TEST_ASSERT(!make_vmcs_current(primary)); 10079 return value; 10080 } 10081 10082 static void vmcs_shadow_test_access(u8 *bitmap[2], enum vmcs_access access) 10083 { 10084 struct vmcs_shadow_test_common *c = &l1_l2_common; 10085 10086 c->op = access; 10087 vmcs_write(VMX_INST_ERROR, 0); 10088 enter_guest(); 10089 c->reason = vmcs_read(EXI_REASON) & 0xffff; 10090 if (c->reason != VMX_VMCALL) { 10091 skip_exit_insn(); 10092 enter_guest(); 10093 } 10094 skip_exit_vmcall(); 10095 } 10096 10097 static void vmcs_shadow_test_field(u8 *bitmap[2], u64 field) 10098 { 10099 struct vmcs_shadow_test_common *c = &l1_l2_common; 10100 struct vmcs *shadow; 10101 u64 value; 10102 uintptr_t flags[2]; 10103 bool good_shadow; 10104 u32 vmx_inst_error; 10105 10106 report_prefix_pushf("field %lx", field); 10107 c->field = field; 10108 10109 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 10110 if (shadow != (struct vmcs *)-1ull) { 10111 flags[ACCESS_VMREAD] = vmread_flags(field, &value); 10112 flags[ACCESS_VMWRITE] = vmwrite_flags(field, value); 10113 good_shadow = !flags[ACCESS_VMREAD] && !flags[ACCESS_VMWRITE]; 10114 } else { 10115 /* 10116 * When VMCS link pointer is -1ull, VMWRITE/VMREAD on 10117 * shadowed-fields should fail with setting RFLAGS.CF. 10118 */ 10119 flags[ACCESS_VMREAD] = X86_EFLAGS_CF; 10120 flags[ACCESS_VMWRITE] = X86_EFLAGS_CF; 10121 good_shadow = false; 10122 } 10123 10124 /* Intercept both VMREAD and VMWRITE. */ 10125 report_prefix_push("no VMREAD/VMWRITE permission"); 10126 /* VMWRITE/VMREAD done on reserved-bit should always intercept */ 10127 if (!(field >> VMCS_FIELD_RESERVED_SHIFT)) { 10128 set_bit(field, bitmap[ACCESS_VMREAD]); 10129 set_bit(field, bitmap[ACCESS_VMWRITE]); 10130 } 10131 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10132 report(c->reason == VMX_VMWRITE, "not shadowed for VMWRITE"); 10133 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10134 report(c->reason == VMX_VMREAD, "not shadowed for VMREAD"); 10135 report_prefix_pop(); 10136 10137 if (field >> VMCS_FIELD_RESERVED_SHIFT) 10138 goto out; 10139 10140 /* Permit shadowed VMREAD. */ 10141 report_prefix_push("VMREAD permission only"); 10142 clear_bit(field, bitmap[ACCESS_VMREAD]); 10143 set_bit(field, bitmap[ACCESS_VMWRITE]); 10144 if (good_shadow) 10145 value = vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 10146 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10147 report(c->reason == VMX_VMWRITE, "not shadowed for VMWRITE"); 10148 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10149 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10150 report(c->reason == VMX_VMCALL, "shadowed for VMREAD (in %ld cycles)", 10151 c->time); 10152 report(c->flags == flags[ACCESS_VMREAD], 10153 "ALU flags after VMREAD (%lx) are as expected (%lx)", 10154 c->flags, flags[ACCESS_VMREAD]); 10155 if (good_shadow) 10156 report(c->value == value, 10157 "value read from shadow (%lx) is as expected (%lx)", 10158 c->value, value); 10159 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 10160 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10161 "VMX_INST_ERROR (%d) is as expected (%d)", 10162 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10163 report_prefix_pop(); 10164 10165 /* Permit shadowed VMWRITE. */ 10166 report_prefix_push("VMWRITE permission only"); 10167 set_bit(field, bitmap[ACCESS_VMREAD]); 10168 clear_bit(field, bitmap[ACCESS_VMWRITE]); 10169 if (good_shadow) 10170 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 10171 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10172 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10173 report(c->reason == VMX_VMCALL, 10174 "shadowed for VMWRITE (in %ld cycles)", 10175 c->time); 10176 report(c->flags == flags[ACCESS_VMREAD], 10177 "ALU flags after VMWRITE (%lx) are as expected (%lx)", 10178 c->flags, flags[ACCESS_VMREAD]); 10179 if (good_shadow) { 10180 value = vmread_from_shadow(field); 10181 report(value == 0, 10182 "shadow VMCS value (%lx) is as expected (%lx)", value, 10183 0ul); 10184 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 10185 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10186 "VMX_INST_ERROR (%d) is as expected (%d)", 10187 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10188 } 10189 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10190 report(c->reason == VMX_VMREAD, "not shadowed for VMREAD"); 10191 report_prefix_pop(); 10192 10193 /* Permit shadowed VMREAD and VMWRITE. */ 10194 report_prefix_push("VMREAD and VMWRITE permission"); 10195 clear_bit(field, bitmap[ACCESS_VMREAD]); 10196 clear_bit(field, bitmap[ACCESS_VMWRITE]); 10197 if (good_shadow) 10198 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 10199 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10200 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10201 report(c->reason == VMX_VMCALL, 10202 "shadowed for VMWRITE (in %ld cycles)", 10203 c->time); 10204 report(c->flags == flags[ACCESS_VMREAD], 10205 "ALU flags after VMWRITE (%lx) are as expected (%lx)", 10206 c->flags, flags[ACCESS_VMREAD]); 10207 if (good_shadow) { 10208 value = vmread_from_shadow(field); 10209 report(value == 0, 10210 "shadow VMCS value (%lx) is as expected (%lx)", value, 10211 0ul); 10212 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 10213 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10214 "VMX_INST_ERROR (%d) is as expected (%d)", 10215 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10216 } 10217 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10218 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10219 report(c->reason == VMX_VMCALL, "shadowed for VMREAD (in %ld cycles)", 10220 c->time); 10221 report(c->flags == flags[ACCESS_VMREAD], 10222 "ALU flags after VMREAD (%lx) are as expected (%lx)", 10223 c->flags, flags[ACCESS_VMREAD]); 10224 if (good_shadow) 10225 report(c->value == 0, 10226 "value read from shadow (%lx) is as expected (%lx)", 10227 c->value, 0ul); 10228 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 10229 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10230 "VMX_INST_ERROR (%d) is as expected (%d)", 10231 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10232 report_prefix_pop(); 10233 10234 out: 10235 report_prefix_pop(); 10236 } 10237 10238 static void vmx_vmcs_shadow_test_body(u8 *bitmap[2]) 10239 { 10240 unsigned base; 10241 unsigned index; 10242 unsigned bit; 10243 unsigned highest_index = rdmsr(MSR_IA32_VMX_VMCS_ENUM); 10244 10245 /* Run test on all possible valid VMCS fields */ 10246 for (base = 0; 10247 base < (1 << VMCS_FIELD_RESERVED_SHIFT); 10248 base += (1 << VMCS_FIELD_TYPE_SHIFT)) 10249 for (index = 0; index <= highest_index; index++) 10250 vmcs_shadow_test_field(bitmap, base + index); 10251 10252 /* 10253 * Run tests on some invalid VMCS fields 10254 * (Have reserved bit set). 10255 */ 10256 for (bit = VMCS_FIELD_RESERVED_SHIFT; bit < VMCS_FIELD_BIT_SIZE; bit++) 10257 vmcs_shadow_test_field(bitmap, (1ull << bit)); 10258 } 10259 10260 static void vmx_vmcs_shadow_test(void) 10261 { 10262 u8 *bitmap[2]; 10263 struct vmcs *shadow; 10264 10265 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 10266 printf("\t'Activate secondary controls' not supported.\n"); 10267 return; 10268 } 10269 10270 if (!(ctrl_cpu_rev[1].clr & CPU_SHADOW_VMCS)) { 10271 printf("\t'VMCS shadowing' not supported.\n"); 10272 return; 10273 } 10274 10275 if (!(rdmsr(MSR_IA32_VMX_MISC) & 10276 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS)) { 10277 printf("\tVMWRITE can't modify VM-exit information fields.\n"); 10278 return; 10279 } 10280 10281 test_set_guest(vmx_vmcs_shadow_test_guest); 10282 10283 bitmap[ACCESS_VMREAD] = alloc_page(); 10284 bitmap[ACCESS_VMWRITE] = alloc_page(); 10285 10286 vmcs_write(VMREAD_BITMAP, virt_to_phys(bitmap[ACCESS_VMREAD])); 10287 vmcs_write(VMWRITE_BITMAP, virt_to_phys(bitmap[ACCESS_VMWRITE])); 10288 10289 shadow = alloc_page(); 10290 shadow->hdr.revision_id = basic.revision; 10291 shadow->hdr.shadow_vmcs = 1; 10292 TEST_ASSERT(!vmcs_clear(shadow)); 10293 10294 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_RDTSC); 10295 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY); 10296 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_SHADOW_VMCS); 10297 10298 vmcs_write(VMCS_LINK_PTR, virt_to_phys(shadow)); 10299 report_prefix_push("valid link pointer"); 10300 vmx_vmcs_shadow_test_body(bitmap); 10301 report_prefix_pop(); 10302 10303 vmcs_write(VMCS_LINK_PTR, -1ull); 10304 report_prefix_push("invalid link pointer"); 10305 vmx_vmcs_shadow_test_body(bitmap); 10306 report_prefix_pop(); 10307 10308 l1_l2_common.op = ACCESS_NONE; 10309 enter_guest(); 10310 } 10311 10312 /* 10313 * This test monitors the difference between a guest RDTSC instruction 10314 * and the IA32_TIME_STAMP_COUNTER MSR value stored in the VMCS12 10315 * VM-exit MSR-store list when taking a VM-exit on the instruction 10316 * following RDTSC. 10317 */ 10318 #define RDTSC_DIFF_ITERS 100000 10319 #define RDTSC_DIFF_FAILS 100 10320 #define HOST_CAPTURED_GUEST_TSC_DIFF_THRESHOLD 750 10321 10322 /* 10323 * Set 'use TSC offsetting' and set the guest offset to the 10324 * inverse of the host's current TSC value, so that the guest starts running 10325 * with an effective TSC value of 0. 10326 */ 10327 static void reset_guest_tsc_to_zero(void) 10328 { 10329 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_USE_TSC_OFFSET); 10330 vmcs_write(TSC_OFFSET, -rdtsc()); 10331 } 10332 10333 static void rdtsc_vmexit_diff_test_guest(void) 10334 { 10335 int i; 10336 10337 for (i = 0; i < RDTSC_DIFF_ITERS; i++) 10338 /* Ensure rdtsc is the last instruction before the vmcall. */ 10339 asm volatile("rdtsc; vmcall" : : : "eax", "edx"); 10340 } 10341 10342 /* 10343 * This function only considers the "use TSC offsetting" VM-execution 10344 * control. It does not handle "use TSC scaling" (because the latter 10345 * isn't available to the host today.) 10346 */ 10347 static unsigned long long host_time_to_guest_time(unsigned long long t) 10348 { 10349 TEST_ASSERT(!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 10350 !(vmcs_read(CPU_EXEC_CTRL1) & CPU_USE_TSC_SCALING)); 10351 10352 if (vmcs_read(CPU_EXEC_CTRL0) & CPU_USE_TSC_OFFSET) 10353 t += vmcs_read(TSC_OFFSET); 10354 10355 return t; 10356 } 10357 10358 static unsigned long long rdtsc_vmexit_diff_test_iteration(void) 10359 { 10360 unsigned long long guest_tsc, host_to_guest_tsc; 10361 10362 enter_guest(); 10363 skip_exit_vmcall(); 10364 guest_tsc = (u32) regs.rax + (regs.rdx << 32); 10365 host_to_guest_tsc = host_time_to_guest_time(exit_msr_store[0].value); 10366 10367 return host_to_guest_tsc - guest_tsc; 10368 } 10369 10370 static void rdtsc_vmexit_diff_test(void) 10371 { 10372 unsigned long long delta; 10373 int fail = 0; 10374 int i; 10375 10376 if (!(ctrl_cpu_rev[0].clr & CPU_USE_TSC_OFFSET)) 10377 test_skip("CPU doesn't support the 'use TSC offsetting' processor-based VM-execution control.\n"); 10378 10379 test_set_guest(rdtsc_vmexit_diff_test_guest); 10380 10381 reset_guest_tsc_to_zero(); 10382 10383 /* 10384 * Set up the VMCS12 VM-exit MSR-store list to store just one 10385 * MSR: IA32_TIME_STAMP_COUNTER. Note that the value stored is 10386 * in the host time domain (i.e., it is not adjusted according 10387 * to the TSC multiplier and TSC offset fields in the VMCS12, 10388 * as a guest RDTSC would be.) 10389 */ 10390 exit_msr_store = alloc_page(); 10391 exit_msr_store[0].index = MSR_IA32_TSC; 10392 vmcs_write(EXI_MSR_ST_CNT, 1); 10393 vmcs_write(EXIT_MSR_ST_ADDR, virt_to_phys(exit_msr_store)); 10394 10395 for (i = 0; i < RDTSC_DIFF_ITERS && fail < RDTSC_DIFF_FAILS; i++) { 10396 delta = rdtsc_vmexit_diff_test_iteration(); 10397 if (delta >= HOST_CAPTURED_GUEST_TSC_DIFF_THRESHOLD) 10398 fail++; 10399 } 10400 10401 enter_guest(); 10402 10403 report(fail < RDTSC_DIFF_FAILS, 10404 "RDTSC to VM-exit delta too high in %d of %d iterations, last = %llu", 10405 fail, i, delta); 10406 } 10407 10408 static int invalid_msr_init(struct vmcs *vmcs) 10409 { 10410 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 10411 printf("\tPreemption timer is not supported\n"); 10412 return VMX_TEST_EXIT; 10413 } 10414 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 10415 preempt_val = 10000000; 10416 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 10417 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 10418 10419 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 10420 printf("\tSave preemption value is not supported\n"); 10421 10422 vmcs_write(ENT_MSR_LD_CNT, 1); 10423 vmcs_write(ENTER_MSR_LD_ADDR, (u64)0x13370000); 10424 10425 return VMX_TEST_START; 10426 } 10427 10428 10429 static void invalid_msr_main(void) 10430 { 10431 report_fail("Invalid MSR load"); 10432 } 10433 10434 static int invalid_msr_exit_handler(union exit_reason exit_reason) 10435 { 10436 report_fail("Invalid MSR load"); 10437 print_vmexit_info(exit_reason); 10438 return VMX_TEST_EXIT; 10439 } 10440 10441 static int invalid_msr_entry_failure(struct vmentry_result *result) 10442 { 10443 report(result->exit_reason.failed_vmentry && 10444 result->exit_reason.basic == VMX_FAIL_MSR, "Invalid MSR load"); 10445 return VMX_TEST_VMEXIT; 10446 } 10447 10448 /* 10449 * The max number of MSRs in an atomic switch MSR list is: 10450 * (111B + 1) * 512 = 4096 10451 * 10452 * Each list entry consumes: 10453 * 4-byte MSR index + 4 bytes reserved + 8-byte data = 16 bytes 10454 * 10455 * Allocate 128 kB to cover max_msr_list_size (i.e., 64 kB) and then some. 10456 */ 10457 static const u32 msr_list_page_order = 5; 10458 10459 static void atomic_switch_msr_limit_test_guest(void) 10460 { 10461 vmcall(); 10462 } 10463 10464 static void populate_msr_list(struct vmx_msr_entry *msr_list, 10465 size_t byte_capacity, int count) 10466 { 10467 int i; 10468 10469 for (i = 0; i < count; i++) { 10470 msr_list[i].index = MSR_IA32_TSC; 10471 msr_list[i].reserved = 0; 10472 msr_list[i].value = 0x1234567890abcdef; 10473 } 10474 10475 memset(msr_list + count, 0xff, 10476 byte_capacity - count * sizeof(*msr_list)); 10477 } 10478 10479 static int max_msr_list_size(void) 10480 { 10481 u32 vmx_misc = rdmsr(MSR_IA32_VMX_MISC); 10482 u32 factor = ((vmx_misc & GENMASK(27, 25)) >> 25) + 1; 10483 10484 return factor * 512; 10485 } 10486 10487 static void atomic_switch_msrs_test(int count) 10488 { 10489 struct vmx_msr_entry *vm_enter_load; 10490 struct vmx_msr_entry *vm_exit_load; 10491 struct vmx_msr_entry *vm_exit_store; 10492 int max_allowed = max_msr_list_size(); 10493 int byte_capacity = 1ul << (msr_list_page_order + PAGE_SHIFT); 10494 /* Exceeding the max MSR list size at exit trigers KVM to abort. */ 10495 int exit_count = count > max_allowed ? max_allowed : count; 10496 int cleanup_count = count > max_allowed ? 2 : 1; 10497 int i; 10498 10499 /* 10500 * Check for the IA32_TSC MSR, 10501 * available with the "TSC flag" and used to populate the MSR lists. 10502 */ 10503 if (!(cpuid(1).d & (1 << 4))) { 10504 report_skip(__func__); 10505 return; 10506 } 10507 10508 /* Set L2 guest. */ 10509 test_set_guest(atomic_switch_msr_limit_test_guest); 10510 10511 /* Setup atomic MSR switch lists. */ 10512 vm_enter_load = alloc_pages(msr_list_page_order); 10513 vm_exit_load = alloc_pages(msr_list_page_order); 10514 vm_exit_store = alloc_pages(msr_list_page_order); 10515 10516 vmcs_write(ENTER_MSR_LD_ADDR, (u64)vm_enter_load); 10517 vmcs_write(EXIT_MSR_LD_ADDR, (u64)vm_exit_load); 10518 vmcs_write(EXIT_MSR_ST_ADDR, (u64)vm_exit_store); 10519 10520 /* 10521 * VM-Enter should succeed up to the max number of MSRs per list, and 10522 * should not consume junk beyond the last entry. 10523 */ 10524 populate_msr_list(vm_enter_load, byte_capacity, count); 10525 populate_msr_list(vm_exit_load, byte_capacity, exit_count); 10526 populate_msr_list(vm_exit_store, byte_capacity, exit_count); 10527 10528 vmcs_write(ENT_MSR_LD_CNT, count); 10529 vmcs_write(EXI_MSR_LD_CNT, exit_count); 10530 vmcs_write(EXI_MSR_ST_CNT, exit_count); 10531 10532 if (count <= max_allowed) { 10533 enter_guest(); 10534 assert_exit_reason(VMX_VMCALL); 10535 skip_exit_vmcall(); 10536 } else { 10537 u32 exit_qual; 10538 10539 test_guest_state("Invalid MSR Load Count", true, count, 10540 "ENT_MSR_LD_CNT"); 10541 10542 exit_qual = vmcs_read(EXI_QUALIFICATION); 10543 report(exit_qual == max_allowed + 1, "exit_qual, %u, is %u.", 10544 exit_qual, max_allowed + 1); 10545 } 10546 10547 /* Cleanup. */ 10548 vmcs_write(ENT_MSR_LD_CNT, 0); 10549 vmcs_write(EXI_MSR_LD_CNT, 0); 10550 vmcs_write(EXI_MSR_ST_CNT, 0); 10551 for (i = 0; i < cleanup_count; i++) { 10552 enter_guest(); 10553 skip_exit_vmcall(); 10554 } 10555 free_pages_by_order(vm_enter_load, msr_list_page_order); 10556 free_pages_by_order(vm_exit_load, msr_list_page_order); 10557 free_pages_by_order(vm_exit_store, msr_list_page_order); 10558 } 10559 10560 static void atomic_switch_max_msrs_test(void) 10561 { 10562 atomic_switch_msrs_test(max_msr_list_size()); 10563 } 10564 10565 static void atomic_switch_overflow_msrs_test(void) 10566 { 10567 if (test_device_enabled()) 10568 atomic_switch_msrs_test(max_msr_list_size() + 1); 10569 else 10570 test_skip("Test is only supported on KVM"); 10571 } 10572 10573 static void vmx_pf_exception_test_guest(void) 10574 { 10575 ac_test_run(PT_LEVEL_PML4); 10576 } 10577 10578 static void vmx_pf_exception_test(void) 10579 { 10580 u64 efer; 10581 struct cpuid cpuid; 10582 10583 test_set_guest(vmx_pf_exception_test_guest); 10584 10585 enter_guest(); 10586 10587 while (vmcs_read(EXI_REASON) != VMX_VMCALL) { 10588 switch (vmcs_read(EXI_REASON)) { 10589 case VMX_RDMSR: 10590 assert(regs.rcx == MSR_EFER); 10591 efer = vmcs_read(GUEST_EFER); 10592 regs.rdx = efer >> 32; 10593 regs.rax = efer & 0xffffffff; 10594 break; 10595 case VMX_WRMSR: 10596 assert(regs.rcx == MSR_EFER); 10597 efer = regs.rdx << 32 | (regs.rax & 0xffffffff); 10598 vmcs_write(GUEST_EFER, efer); 10599 break; 10600 case VMX_CPUID: 10601 cpuid = (struct cpuid) {0, 0, 0, 0}; 10602 cpuid = raw_cpuid(regs.rax, regs.rcx); 10603 regs.rax = cpuid.a; 10604 regs.rbx = cpuid.b; 10605 regs.rcx = cpuid.c; 10606 regs.rdx = cpuid.d; 10607 break; 10608 default: 10609 assert_msg(false, 10610 "Unexpected exit to L1, exit_reason: %s (0x%lx)", 10611 exit_reason_description(vmcs_read(EXI_REASON)), 10612 vmcs_read(EXI_REASON)); 10613 } 10614 skip_exit_insn(); 10615 enter_guest(); 10616 } 10617 10618 assert_exit_reason(VMX_VMCALL); 10619 } 10620 #define TEST(name) { #name, .v2 = name } 10621 10622 /* name/init/guest_main/exit_handler/syscall_handler/guest_regs */ 10623 struct vmx_test vmx_tests[] = { 10624 { "null", NULL, basic_guest_main, basic_exit_handler, NULL, {0} }, 10625 { "vmenter", NULL, vmenter_main, vmenter_exit_handler, NULL, {0} }, 10626 { "preemption timer", preemption_timer_init, preemption_timer_main, 10627 preemption_timer_exit_handler, NULL, {0} }, 10628 { "control field PAT", test_ctrl_pat_init, test_ctrl_pat_main, 10629 test_ctrl_pat_exit_handler, NULL, {0} }, 10630 { "control field EFER", test_ctrl_efer_init, test_ctrl_efer_main, 10631 test_ctrl_efer_exit_handler, NULL, {0} }, 10632 { "CR shadowing", NULL, cr_shadowing_main, 10633 cr_shadowing_exit_handler, NULL, {0} }, 10634 { "I/O bitmap", iobmp_init, iobmp_main, iobmp_exit_handler, 10635 NULL, {0} }, 10636 { "instruction intercept", insn_intercept_init, insn_intercept_main, 10637 insn_intercept_exit_handler, NULL, {0} }, 10638 { "EPT A/D disabled", ept_init, ept_main, ept_exit_handler, NULL, {0} }, 10639 { "EPT A/D enabled", eptad_init, eptad_main, eptad_exit_handler, NULL, {0} }, 10640 { "PML", pml_init, pml_main, pml_exit_handler, NULL, {0} }, 10641 { "interrupt", interrupt_init, interrupt_main, 10642 interrupt_exit_handler, NULL, {0} }, 10643 { "nmi_hlt", nmi_hlt_init, nmi_hlt_main, 10644 nmi_hlt_exit_handler, NULL, {0} }, 10645 { "debug controls", dbgctls_init, dbgctls_main, dbgctls_exit_handler, 10646 NULL, {0} }, 10647 { "MSR switch", msr_switch_init, msr_switch_main, 10648 msr_switch_exit_handler, NULL, {0}, msr_switch_entry_failure }, 10649 { "vmmcall", vmmcall_init, vmmcall_main, vmmcall_exit_handler, NULL, {0} }, 10650 { "disable RDTSCP", disable_rdtscp_init, disable_rdtscp_main, 10651 disable_rdtscp_exit_handler, NULL, {0} }, 10652 { "int3", int3_init, int3_guest_main, int3_exit_handler, NULL, {0} }, 10653 { "into", into_init, into_guest_main, into_exit_handler, NULL, {0} }, 10654 { "exit_monitor_from_l2_test", NULL, exit_monitor_from_l2_main, 10655 exit_monitor_from_l2_handler, NULL, {0} }, 10656 { "invalid_msr", invalid_msr_init, invalid_msr_main, 10657 invalid_msr_exit_handler, NULL, {0}, invalid_msr_entry_failure}, 10658 /* Basic V2 tests. */ 10659 TEST(v2_null_test), 10660 TEST(v2_multiple_entries_test), 10661 TEST(fixture_test_case1), 10662 TEST(fixture_test_case2), 10663 /* Opcode tests. */ 10664 TEST(invvpid_test), 10665 /* VM-entry tests */ 10666 TEST(vmx_controls_test), 10667 TEST(vmx_host_state_area_test), 10668 TEST(vmx_guest_state_area_test), 10669 TEST(vmentry_movss_shadow_test), 10670 TEST(vmentry_unrestricted_guest_test), 10671 /* APICv tests */ 10672 TEST(vmx_eoi_bitmap_ioapic_scan_test), 10673 TEST(vmx_hlt_with_rvi_test), 10674 TEST(apic_reg_virt_test), 10675 TEST(virt_x2apic_mode_test), 10676 /* APIC pass-through tests */ 10677 TEST(vmx_apic_passthrough_test), 10678 TEST(vmx_apic_passthrough_thread_test), 10679 TEST(vmx_apic_passthrough_tpr_threshold_test), 10680 TEST(vmx_init_signal_test), 10681 TEST(vmx_sipi_signal_test), 10682 /* VMCS Shadowing tests */ 10683 TEST(vmx_vmcs_shadow_test), 10684 /* Regression tests */ 10685 TEST(vmx_ldtr_test), 10686 TEST(vmx_cr_load_test), 10687 TEST(vmx_cr4_osxsave_test), 10688 TEST(vmx_nm_test), 10689 TEST(vmx_db_test), 10690 TEST(vmx_nmi_window_test), 10691 TEST(vmx_intr_window_test), 10692 TEST(vmx_pending_event_test), 10693 TEST(vmx_pending_event_hlt_test), 10694 TEST(vmx_store_tsc_test), 10695 TEST(vmx_preemption_timer_zero_test), 10696 TEST(vmx_preemption_timer_tf_test), 10697 TEST(vmx_preemption_timer_expiry_test), 10698 /* EPT access tests. */ 10699 TEST(ept_access_test_not_present), 10700 TEST(ept_access_test_read_only), 10701 TEST(ept_access_test_write_only), 10702 TEST(ept_access_test_read_write), 10703 TEST(ept_access_test_execute_only), 10704 TEST(ept_access_test_read_execute), 10705 TEST(ept_access_test_write_execute), 10706 TEST(ept_access_test_read_write_execute), 10707 TEST(ept_access_test_reserved_bits), 10708 TEST(ept_access_test_ignored_bits), 10709 TEST(ept_access_test_paddr_not_present_ad_disabled), 10710 TEST(ept_access_test_paddr_not_present_ad_enabled), 10711 TEST(ept_access_test_paddr_read_only_ad_disabled), 10712 TEST(ept_access_test_paddr_read_only_ad_enabled), 10713 TEST(ept_access_test_paddr_read_write), 10714 TEST(ept_access_test_paddr_read_write_execute), 10715 TEST(ept_access_test_paddr_read_execute_ad_disabled), 10716 TEST(ept_access_test_paddr_read_execute_ad_enabled), 10717 TEST(ept_access_test_paddr_not_present_page_fault), 10718 TEST(ept_access_test_force_2m_page), 10719 /* Atomic MSR switch tests. */ 10720 TEST(atomic_switch_max_msrs_test), 10721 TEST(atomic_switch_overflow_msrs_test), 10722 TEST(rdtsc_vmexit_diff_test), 10723 TEST(vmx_mtf_test), 10724 TEST(vmx_mtf_pdpte_test), 10725 TEST(vmx_pf_exception_test), 10726 { NULL, NULL, NULL, NULL, NULL, {0} }, 10727 }; 10728