1 /* 2 * All test cases of nested virtualization should be in this file 3 * 4 * Author : Arthur Chunqi Li <yzt356@gmail.com> 5 */ 6 7 #include <asm/debugreg.h> 8 9 #include "vmx.h" 10 #include "msr.h" 11 #include "processor.h" 12 #include "pmu.h" 13 #include "vm.h" 14 #include "pci.h" 15 #include "fwcfg.h" 16 #include "isr.h" 17 #include "desc.h" 18 #include "apic.h" 19 #include "vmalloc.h" 20 #include "alloc_page.h" 21 #include "smp.h" 22 #include "delay.h" 23 #include "access.h" 24 #include "x86/usermode.h" 25 26 /* 27 * vmcs.GUEST_PENDING_DEBUG has the same format as DR6, although some bits that 28 * are legal in DR6 are reserved in vmcs.GUEST_PENDING_DEBUG. And if any data 29 * or I/O breakpoint matches *and* was enabled, bit 12 is also set. 30 */ 31 #define PENDING_DBG_TRAP BIT(12) 32 33 #define VPID_CAP_INVVPID_TYPES_SHIFT 40 34 35 u64 ia32_pat; 36 u64 ia32_efer; 37 void *io_bitmap_a, *io_bitmap_b; 38 u16 ioport; 39 40 unsigned long *pml4; 41 u64 eptp; 42 void *data_page1, *data_page2; 43 44 phys_addr_t pci_physaddr; 45 46 void *pml_log; 47 #define PML_INDEX 512 48 49 static inline unsigned ffs(unsigned x) 50 { 51 int pos = -1; 52 53 __asm__ __volatile__("bsf %1, %%eax; cmovnz %%eax, %0" 54 : "+r"(pos) : "rm"(x) : "eax"); 55 return pos + 1; 56 } 57 58 static inline void vmcall(void) 59 { 60 asm volatile("vmcall"); 61 } 62 63 static void basic_guest_main(void) 64 { 65 report_pass("Basic VMX test"); 66 } 67 68 static int basic_exit_handler(union exit_reason exit_reason) 69 { 70 report_fail("Basic VMX test"); 71 print_vmexit_info(exit_reason); 72 return VMX_TEST_EXIT; 73 } 74 75 static void vmenter_main(void) 76 { 77 u64 rax; 78 u64 rsp, resume_rsp; 79 80 report_pass("test vmlaunch"); 81 82 asm volatile( 83 "mov %%rsp, %0\n\t" 84 "mov %3, %%rax\n\t" 85 "vmcall\n\t" 86 "mov %%rax, %1\n\t" 87 "mov %%rsp, %2\n\t" 88 : "=r"(rsp), "=r"(rax), "=r"(resume_rsp) 89 : "g"(0xABCD)); 90 report((rax == 0xFFFF) && (rsp == resume_rsp), "test vmresume"); 91 } 92 93 static int vmenter_exit_handler(union exit_reason exit_reason) 94 { 95 u64 guest_rip = vmcs_read(GUEST_RIP); 96 97 switch (exit_reason.basic) { 98 case VMX_VMCALL: 99 if (regs.rax != 0xABCD) { 100 report_fail("test vmresume"); 101 return VMX_TEST_VMEXIT; 102 } 103 regs.rax = 0xFFFF; 104 vmcs_write(GUEST_RIP, guest_rip + 3); 105 return VMX_TEST_RESUME; 106 default: 107 report_fail("test vmresume"); 108 print_vmexit_info(exit_reason); 109 } 110 return VMX_TEST_VMEXIT; 111 } 112 113 u32 preempt_scale; 114 volatile unsigned long long tsc_val; 115 volatile u32 preempt_val; 116 u64 saved_rip; 117 118 static int preemption_timer_init(struct vmcs *vmcs) 119 { 120 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 121 printf("\tPreemption timer is not supported\n"); 122 return VMX_TEST_EXIT; 123 } 124 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 125 preempt_val = 10000000; 126 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 127 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 128 129 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 130 printf("\tSave preemption value is not supported\n"); 131 132 return VMX_TEST_START; 133 } 134 135 static void preemption_timer_main(void) 136 { 137 tsc_val = rdtsc(); 138 if (ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) { 139 vmx_set_test_stage(0); 140 vmcall(); 141 if (vmx_get_test_stage() == 1) 142 vmcall(); 143 } 144 vmx_set_test_stage(1); 145 while (vmx_get_test_stage() == 1) { 146 if (((rdtsc() - tsc_val) >> preempt_scale) 147 > 10 * preempt_val) { 148 vmx_set_test_stage(2); 149 vmcall(); 150 } 151 } 152 tsc_val = rdtsc(); 153 asm volatile ("hlt"); 154 vmcall(); 155 vmx_set_test_stage(5); 156 vmcall(); 157 } 158 159 static int preemption_timer_exit_handler(union exit_reason exit_reason) 160 { 161 bool guest_halted; 162 u64 guest_rip; 163 u32 insn_len; 164 u32 ctrl_exit; 165 166 guest_rip = vmcs_read(GUEST_RIP); 167 insn_len = vmcs_read(EXI_INST_LEN); 168 switch (exit_reason.basic) { 169 case VMX_PREEMPT: 170 switch (vmx_get_test_stage()) { 171 case 1: 172 case 2: 173 report(((rdtsc() - tsc_val) >> preempt_scale) >= preempt_val, 174 "busy-wait for preemption timer"); 175 vmx_set_test_stage(3); 176 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 177 return VMX_TEST_RESUME; 178 case 3: 179 guest_halted = 180 (vmcs_read(GUEST_ACTV_STATE) == ACTV_HLT); 181 report(((rdtsc() - tsc_val) >> preempt_scale) >= preempt_val 182 && guest_halted, 183 "preemption timer during hlt"); 184 vmx_set_test_stage(4); 185 vmcs_write(PIN_CONTROLS, 186 vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 187 vmcs_write(EXI_CONTROLS, 188 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_PREEMPT); 189 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 190 return VMX_TEST_RESUME; 191 case 4: 192 report(saved_rip == guest_rip, 193 "preemption timer with 0 value"); 194 break; 195 default: 196 report_fail("Invalid stage."); 197 print_vmexit_info(exit_reason); 198 break; 199 } 200 break; 201 case VMX_VMCALL: 202 vmcs_write(GUEST_RIP, guest_rip + insn_len); 203 switch (vmx_get_test_stage()) { 204 case 0: 205 report(vmcs_read(PREEMPT_TIMER_VALUE) == preempt_val, 206 "Keep preemption value"); 207 vmx_set_test_stage(1); 208 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 209 ctrl_exit = (vmcs_read(EXI_CONTROLS) | 210 EXI_SAVE_PREEMPT) & ctrl_exit_rev.clr; 211 vmcs_write(EXI_CONTROLS, ctrl_exit); 212 return VMX_TEST_RESUME; 213 case 1: 214 report(vmcs_read(PREEMPT_TIMER_VALUE) < preempt_val, 215 "Save preemption value"); 216 return VMX_TEST_RESUME; 217 case 2: 218 report_fail("busy-wait for preemption timer"); 219 vmx_set_test_stage(3); 220 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 221 return VMX_TEST_RESUME; 222 case 3: 223 report_fail("preemption timer during hlt"); 224 vmx_set_test_stage(4); 225 /* fall through */ 226 case 4: 227 vmcs_write(PIN_CONTROLS, 228 vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 229 vmcs_write(PREEMPT_TIMER_VALUE, 0); 230 saved_rip = guest_rip + insn_len; 231 return VMX_TEST_RESUME; 232 case 5: 233 report_fail("preemption timer with 0 value (vmcall stage 5)"); 234 break; 235 default: 236 // Should not reach here 237 report_fail("unexpected stage, %d", 238 vmx_get_test_stage()); 239 print_vmexit_info(exit_reason); 240 return VMX_TEST_VMEXIT; 241 } 242 break; 243 default: 244 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 245 print_vmexit_info(exit_reason); 246 } 247 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 248 return VMX_TEST_VMEXIT; 249 } 250 251 static void msr_bmp_init(void) 252 { 253 void *msr_bitmap; 254 u32 ctrl_cpu0; 255 256 msr_bitmap = alloc_page(); 257 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 258 ctrl_cpu0 |= CPU_MSR_BITMAP; 259 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 260 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 261 } 262 263 static void *get_msr_bitmap(void) 264 { 265 void *msr_bitmap; 266 267 if (vmcs_read(CPU_EXEC_CTRL0) & CPU_MSR_BITMAP) { 268 msr_bitmap = (void *)vmcs_read(MSR_BITMAP); 269 } else { 270 msr_bitmap = alloc_page(); 271 memset(msr_bitmap, 0xff, PAGE_SIZE); 272 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 273 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_MSR_BITMAP); 274 } 275 276 return msr_bitmap; 277 } 278 279 static void disable_intercept_for_x2apic_msrs(void) 280 { 281 unsigned long *msr_bitmap = (unsigned long *)get_msr_bitmap(); 282 u32 msr; 283 284 for (msr = APIC_BASE_MSR; 285 msr < (APIC_BASE_MSR+0xff); 286 msr += BITS_PER_LONG) { 287 unsigned int word = msr / BITS_PER_LONG; 288 289 msr_bitmap[word] = 0; 290 msr_bitmap[word + (0x800 / sizeof(long))] = 0; 291 } 292 } 293 294 static int test_ctrl_pat_init(struct vmcs *vmcs) 295 { 296 u64 ctrl_ent; 297 u64 ctrl_exi; 298 299 msr_bmp_init(); 300 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT) && 301 !(ctrl_exit_rev.clr & EXI_LOAD_PAT) && 302 !(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 303 printf("\tSave/load PAT is not supported\n"); 304 return 1; 305 } 306 307 ctrl_ent = vmcs_read(ENT_CONTROLS); 308 ctrl_exi = vmcs_read(EXI_CONTROLS); 309 ctrl_ent |= ctrl_enter_rev.clr & ENT_LOAD_PAT; 310 ctrl_exi |= ctrl_exit_rev.clr & (EXI_SAVE_PAT | EXI_LOAD_PAT); 311 vmcs_write(ENT_CONTROLS, ctrl_ent); 312 vmcs_write(EXI_CONTROLS, ctrl_exi); 313 ia32_pat = rdmsr(MSR_IA32_CR_PAT); 314 vmcs_write(GUEST_PAT, 0x0); 315 vmcs_write(HOST_PAT, ia32_pat); 316 return VMX_TEST_START; 317 } 318 319 static void test_ctrl_pat_main(void) 320 { 321 u64 guest_ia32_pat; 322 323 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 324 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) 325 printf("\tENT_LOAD_PAT is not supported.\n"); 326 else { 327 if (guest_ia32_pat != 0) { 328 report_fail("Entry load PAT"); 329 return; 330 } 331 } 332 wrmsr(MSR_IA32_CR_PAT, 0x6); 333 vmcall(); 334 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 335 if (ctrl_enter_rev.clr & ENT_LOAD_PAT) 336 report(guest_ia32_pat == ia32_pat, "Entry load PAT"); 337 } 338 339 static int test_ctrl_pat_exit_handler(union exit_reason exit_reason) 340 { 341 u64 guest_rip; 342 u64 guest_pat; 343 344 guest_rip = vmcs_read(GUEST_RIP); 345 switch (exit_reason.basic) { 346 case VMX_VMCALL: 347 guest_pat = vmcs_read(GUEST_PAT); 348 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT)) { 349 printf("\tEXI_SAVE_PAT is not supported\n"); 350 vmcs_write(GUEST_PAT, 0x6); 351 } else { 352 report(guest_pat == 0x6, "Exit save PAT"); 353 } 354 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) 355 printf("\tEXI_LOAD_PAT is not supported\n"); 356 else 357 report(rdmsr(MSR_IA32_CR_PAT) == ia32_pat, 358 "Exit load PAT"); 359 vmcs_write(GUEST_PAT, ia32_pat); 360 vmcs_write(GUEST_RIP, guest_rip + 3); 361 return VMX_TEST_RESUME; 362 default: 363 printf("ERROR : Unknown exit reason, 0x%x.\n", exit_reason.full); 364 break; 365 } 366 return VMX_TEST_VMEXIT; 367 } 368 369 static int test_ctrl_efer_init(struct vmcs *vmcs) 370 { 371 u64 ctrl_ent; 372 u64 ctrl_exi; 373 374 msr_bmp_init(); 375 ctrl_ent = vmcs_read(ENT_CONTROLS) | ENT_LOAD_EFER; 376 ctrl_exi = vmcs_read(EXI_CONTROLS) | EXI_SAVE_EFER | EXI_LOAD_EFER; 377 vmcs_write(ENT_CONTROLS, ctrl_ent & ctrl_enter_rev.clr); 378 vmcs_write(EXI_CONTROLS, ctrl_exi & ctrl_exit_rev.clr); 379 ia32_efer = rdmsr(MSR_EFER); 380 vmcs_write(GUEST_EFER, ia32_efer ^ EFER_NX); 381 vmcs_write(HOST_EFER, ia32_efer ^ EFER_NX); 382 return VMX_TEST_START; 383 } 384 385 static void test_ctrl_efer_main(void) 386 { 387 u64 guest_ia32_efer; 388 389 guest_ia32_efer = rdmsr(MSR_EFER); 390 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) 391 printf("\tENT_LOAD_EFER is not supported.\n"); 392 else { 393 if (guest_ia32_efer != (ia32_efer ^ EFER_NX)) { 394 report_fail("Entry load EFER"); 395 return; 396 } 397 } 398 wrmsr(MSR_EFER, ia32_efer); 399 vmcall(); 400 guest_ia32_efer = rdmsr(MSR_EFER); 401 if (ctrl_enter_rev.clr & ENT_LOAD_EFER) 402 report(guest_ia32_efer == ia32_efer, "Entry load EFER"); 403 } 404 405 static int test_ctrl_efer_exit_handler(union exit_reason exit_reason) 406 { 407 u64 guest_rip; 408 u64 guest_efer; 409 410 guest_rip = vmcs_read(GUEST_RIP); 411 switch (exit_reason.basic) { 412 case VMX_VMCALL: 413 guest_efer = vmcs_read(GUEST_EFER); 414 if (!(ctrl_exit_rev.clr & EXI_SAVE_EFER)) { 415 printf("\tEXI_SAVE_EFER is not supported\n"); 416 vmcs_write(GUEST_EFER, ia32_efer); 417 } else { 418 report(guest_efer == ia32_efer, "Exit save EFER"); 419 } 420 if (!(ctrl_exit_rev.clr & EXI_LOAD_EFER)) { 421 printf("\tEXI_LOAD_EFER is not supported\n"); 422 wrmsr(MSR_EFER, ia32_efer ^ EFER_NX); 423 } else { 424 report(rdmsr(MSR_EFER) == (ia32_efer ^ EFER_NX), 425 "Exit load EFER"); 426 } 427 vmcs_write(GUEST_PAT, ia32_efer); 428 vmcs_write(GUEST_RIP, guest_rip + 3); 429 return VMX_TEST_RESUME; 430 default: 431 printf("ERROR : Unknown exit reason, 0x%x.\n", exit_reason.full); 432 break; 433 } 434 return VMX_TEST_VMEXIT; 435 } 436 437 u32 guest_cr0, guest_cr4; 438 439 static void cr_shadowing_main(void) 440 { 441 u32 cr0, cr4, tmp; 442 443 // Test read through 444 vmx_set_test_stage(0); 445 guest_cr0 = read_cr0(); 446 if (vmx_get_test_stage() == 1) 447 report_fail("Read through CR0"); 448 else 449 vmcall(); 450 vmx_set_test_stage(1); 451 guest_cr4 = read_cr4(); 452 if (vmx_get_test_stage() == 2) 453 report_fail("Read through CR4"); 454 else 455 vmcall(); 456 // Test write through 457 guest_cr0 = guest_cr0 ^ (X86_CR0_TS | X86_CR0_MP); 458 guest_cr4 = guest_cr4 ^ (X86_CR4_TSD | X86_CR4_DE); 459 vmx_set_test_stage(2); 460 write_cr0(guest_cr0); 461 if (vmx_get_test_stage() == 3) 462 report_fail("Write through CR0"); 463 else 464 vmcall(); 465 vmx_set_test_stage(3); 466 write_cr4(guest_cr4); 467 if (vmx_get_test_stage() == 4) 468 report_fail("Write through CR4"); 469 else 470 vmcall(); 471 // Test read shadow 472 vmx_set_test_stage(4); 473 vmcall(); 474 cr0 = read_cr0(); 475 if (vmx_get_test_stage() != 5) 476 report(cr0 == guest_cr0, "Read shadowing CR0"); 477 vmx_set_test_stage(5); 478 cr4 = read_cr4(); 479 if (vmx_get_test_stage() != 6) 480 report(cr4 == guest_cr4, "Read shadowing CR4"); 481 // Test write shadow (same value with shadow) 482 vmx_set_test_stage(6); 483 write_cr0(guest_cr0); 484 if (vmx_get_test_stage() == 7) 485 report_fail("Write shadowing CR0 (same value with shadow)"); 486 else 487 vmcall(); 488 vmx_set_test_stage(7); 489 write_cr4(guest_cr4); 490 if (vmx_get_test_stage() == 8) 491 report_fail("Write shadowing CR4 (same value with shadow)"); 492 else 493 vmcall(); 494 // Test write shadow (different value) 495 vmx_set_test_stage(8); 496 tmp = guest_cr0 ^ X86_CR0_TS; 497 asm volatile("mov %0, %%rsi\n\t" 498 "mov %%rsi, %%cr0\n\t" 499 ::"m"(tmp) 500 :"rsi", "memory", "cc"); 501 report(vmx_get_test_stage() == 9, 502 "Write shadowing different X86_CR0_TS"); 503 vmx_set_test_stage(9); 504 tmp = guest_cr0 ^ X86_CR0_MP; 505 asm volatile("mov %0, %%rsi\n\t" 506 "mov %%rsi, %%cr0\n\t" 507 ::"m"(tmp) 508 :"rsi", "memory", "cc"); 509 report(vmx_get_test_stage() == 10, 510 "Write shadowing different X86_CR0_MP"); 511 vmx_set_test_stage(10); 512 tmp = guest_cr4 ^ X86_CR4_TSD; 513 asm volatile("mov %0, %%rsi\n\t" 514 "mov %%rsi, %%cr4\n\t" 515 ::"m"(tmp) 516 :"rsi", "memory", "cc"); 517 report(vmx_get_test_stage() == 11, 518 "Write shadowing different X86_CR4_TSD"); 519 vmx_set_test_stage(11); 520 tmp = guest_cr4 ^ X86_CR4_DE; 521 asm volatile("mov %0, %%rsi\n\t" 522 "mov %%rsi, %%cr4\n\t" 523 ::"m"(tmp) 524 :"rsi", "memory", "cc"); 525 report(vmx_get_test_stage() == 12, 526 "Write shadowing different X86_CR4_DE"); 527 } 528 529 static int cr_shadowing_exit_handler(union exit_reason exit_reason) 530 { 531 u64 guest_rip; 532 u32 insn_len; 533 u32 exit_qual; 534 535 guest_rip = vmcs_read(GUEST_RIP); 536 insn_len = vmcs_read(EXI_INST_LEN); 537 exit_qual = vmcs_read(EXI_QUALIFICATION); 538 switch (exit_reason.basic) { 539 case VMX_VMCALL: 540 switch (vmx_get_test_stage()) { 541 case 0: 542 report(guest_cr0 == vmcs_read(GUEST_CR0), 543 "Read through CR0"); 544 break; 545 case 1: 546 report(guest_cr4 == vmcs_read(GUEST_CR4), 547 "Read through CR4"); 548 break; 549 case 2: 550 report(guest_cr0 == vmcs_read(GUEST_CR0), 551 "Write through CR0"); 552 break; 553 case 3: 554 report(guest_cr4 == vmcs_read(GUEST_CR4), 555 "Write through CR4"); 556 break; 557 case 4: 558 guest_cr0 = vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP); 559 guest_cr4 = vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE); 560 vmcs_write(CR0_MASK, X86_CR0_TS | X86_CR0_MP); 561 vmcs_write(CR0_READ_SHADOW, guest_cr0 & (X86_CR0_TS | X86_CR0_MP)); 562 vmcs_write(CR4_MASK, X86_CR4_TSD | X86_CR4_DE); 563 vmcs_write(CR4_READ_SHADOW, guest_cr4 & (X86_CR4_TSD | X86_CR4_DE)); 564 break; 565 case 6: 566 report(guest_cr0 == (vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP)), 567 "Write shadowing CR0 (same value)"); 568 break; 569 case 7: 570 report(guest_cr4 == (vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE)), 571 "Write shadowing CR4 (same value)"); 572 break; 573 default: 574 // Should not reach here 575 report_fail("unexpected stage, %d", 576 vmx_get_test_stage()); 577 print_vmexit_info(exit_reason); 578 return VMX_TEST_VMEXIT; 579 } 580 vmcs_write(GUEST_RIP, guest_rip + insn_len); 581 return VMX_TEST_RESUME; 582 case VMX_CR: 583 switch (vmx_get_test_stage()) { 584 case 4: 585 report_fail("Read shadowing CR0"); 586 vmx_inc_test_stage(); 587 break; 588 case 5: 589 report_fail("Read shadowing CR4"); 590 vmx_inc_test_stage(); 591 break; 592 case 6: 593 report_fail("Write shadowing CR0 (same value)"); 594 vmx_inc_test_stage(); 595 break; 596 case 7: 597 report_fail("Write shadowing CR4 (same value)"); 598 vmx_inc_test_stage(); 599 break; 600 case 8: 601 case 9: 602 // 0x600 encodes "mov %esi, %cr0" 603 if (exit_qual == 0x600) 604 vmx_inc_test_stage(); 605 break; 606 case 10: 607 case 11: 608 // 0x604 encodes "mov %esi, %cr4" 609 if (exit_qual == 0x604) 610 vmx_inc_test_stage(); 611 break; 612 default: 613 // Should not reach here 614 report_fail("unexpected stage, %d", 615 vmx_get_test_stage()); 616 print_vmexit_info(exit_reason); 617 return VMX_TEST_VMEXIT; 618 } 619 vmcs_write(GUEST_RIP, guest_rip + insn_len); 620 return VMX_TEST_RESUME; 621 default: 622 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 623 print_vmexit_info(exit_reason); 624 } 625 return VMX_TEST_VMEXIT; 626 } 627 628 static int iobmp_init(struct vmcs *vmcs) 629 { 630 u32 ctrl_cpu0; 631 632 io_bitmap_a = alloc_page(); 633 io_bitmap_b = alloc_page(); 634 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 635 ctrl_cpu0 |= CPU_IO_BITMAP; 636 ctrl_cpu0 &= (~CPU_IO); 637 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 638 vmcs_write(IO_BITMAP_A, (u64)io_bitmap_a); 639 vmcs_write(IO_BITMAP_B, (u64)io_bitmap_b); 640 return VMX_TEST_START; 641 } 642 643 static void iobmp_main(void) 644 { 645 // stage 0, test IO pass 646 vmx_set_test_stage(0); 647 inb(0x5000); 648 outb(0x0, 0x5000); 649 report(vmx_get_test_stage() == 0, "I/O bitmap - I/O pass"); 650 // test IO width, in/out 651 ((u8 *)io_bitmap_a)[0] = 0xFF; 652 vmx_set_test_stage(2); 653 inb(0x0); 654 report(vmx_get_test_stage() == 3, "I/O bitmap - trap in"); 655 vmx_set_test_stage(3); 656 outw(0x0, 0x0); 657 report(vmx_get_test_stage() == 4, "I/O bitmap - trap out"); 658 vmx_set_test_stage(4); 659 inl(0x0); 660 report(vmx_get_test_stage() == 5, "I/O bitmap - I/O width, long"); 661 // test low/high IO port 662 vmx_set_test_stage(5); 663 ((u8 *)io_bitmap_a)[0x5000 / 8] = (1 << (0x5000 % 8)); 664 inb(0x5000); 665 report(vmx_get_test_stage() == 6, "I/O bitmap - I/O port, low part"); 666 vmx_set_test_stage(6); 667 ((u8 *)io_bitmap_b)[0x1000 / 8] = (1 << (0x1000 % 8)); 668 inb(0x9000); 669 report(vmx_get_test_stage() == 7, "I/O bitmap - I/O port, high part"); 670 // test partial pass 671 vmx_set_test_stage(7); 672 inl(0x4FFF); 673 report(vmx_get_test_stage() == 8, "I/O bitmap - partial pass"); 674 // test overrun 675 vmx_set_test_stage(8); 676 memset(io_bitmap_a, 0x0, PAGE_SIZE); 677 memset(io_bitmap_b, 0x0, PAGE_SIZE); 678 inl(0xFFFF); 679 report(vmx_get_test_stage() == 9, "I/O bitmap - overrun"); 680 vmx_set_test_stage(9); 681 vmcall(); 682 outb(0x0, 0x0); 683 report(vmx_get_test_stage() == 9, 684 "I/O bitmap - ignore unconditional exiting"); 685 vmx_set_test_stage(10); 686 vmcall(); 687 outb(0x0, 0x0); 688 report(vmx_get_test_stage() == 11, 689 "I/O bitmap - unconditional exiting"); 690 } 691 692 static int iobmp_exit_handler(union exit_reason exit_reason) 693 { 694 u64 guest_rip; 695 ulong exit_qual; 696 u32 insn_len, ctrl_cpu0; 697 698 guest_rip = vmcs_read(GUEST_RIP); 699 exit_qual = vmcs_read(EXI_QUALIFICATION); 700 insn_len = vmcs_read(EXI_INST_LEN); 701 switch (exit_reason.basic) { 702 case VMX_IO: 703 switch (vmx_get_test_stage()) { 704 case 0: 705 case 1: 706 vmx_inc_test_stage(); 707 break; 708 case 2: 709 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_BYTE, 710 "I/O bitmap - I/O width, byte"); 711 report(exit_qual & VMX_IO_IN, 712 "I/O bitmap - I/O direction, in"); 713 vmx_inc_test_stage(); 714 break; 715 case 3: 716 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_WORD, 717 "I/O bitmap - I/O width, word"); 718 report(!(exit_qual & VMX_IO_IN), 719 "I/O bitmap - I/O direction, out"); 720 vmx_inc_test_stage(); 721 break; 722 case 4: 723 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_LONG, 724 "I/O bitmap - I/O width, long"); 725 vmx_inc_test_stage(); 726 break; 727 case 5: 728 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x5000) 729 vmx_inc_test_stage(); 730 break; 731 case 6: 732 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x9000) 733 vmx_inc_test_stage(); 734 break; 735 case 7: 736 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x4FFF) 737 vmx_inc_test_stage(); 738 break; 739 case 8: 740 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0xFFFF) 741 vmx_inc_test_stage(); 742 break; 743 case 9: 744 case 10: 745 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 746 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0 & ~CPU_IO); 747 vmx_inc_test_stage(); 748 break; 749 default: 750 // Should not reach here 751 report_fail("unexpected stage, %d", 752 vmx_get_test_stage()); 753 print_vmexit_info(exit_reason); 754 return VMX_TEST_VMEXIT; 755 } 756 vmcs_write(GUEST_RIP, guest_rip + insn_len); 757 return VMX_TEST_RESUME; 758 case VMX_VMCALL: 759 switch (vmx_get_test_stage()) { 760 case 9: 761 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 762 ctrl_cpu0 |= CPU_IO | CPU_IO_BITMAP; 763 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 764 break; 765 case 10: 766 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 767 ctrl_cpu0 = (ctrl_cpu0 & ~CPU_IO_BITMAP) | CPU_IO; 768 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 769 break; 770 default: 771 // Should not reach here 772 report_fail("unexpected stage, %d", 773 vmx_get_test_stage()); 774 print_vmexit_info(exit_reason); 775 return VMX_TEST_VMEXIT; 776 } 777 vmcs_write(GUEST_RIP, guest_rip + insn_len); 778 return VMX_TEST_RESUME; 779 default: 780 printf("guest_rip = %#lx\n", guest_rip); 781 printf("\tERROR : Unknown exit reason, 0x%x\n", exit_reason.full); 782 break; 783 } 784 return VMX_TEST_VMEXIT; 785 } 786 787 #define INSN_CPU0 0 788 #define INSN_CPU1 1 789 #define INSN_ALWAYS_TRAP 2 790 791 #define FIELD_EXIT_QUAL (1 << 0) 792 #define FIELD_INSN_INFO (1 << 1) 793 794 asm( 795 "insn_hlt: hlt;ret\n\t" 796 "insn_invlpg: invlpg 0x12345678;ret\n\t" 797 "insn_mwait: xor %eax, %eax; xor %ecx, %ecx; mwait;ret\n\t" 798 "insn_rdpmc: xor %ecx, %ecx; rdpmc;ret\n\t" 799 "insn_rdtsc: rdtsc;ret\n\t" 800 "insn_cr3_load: mov cr3,%rax; mov %rax,%cr3;ret\n\t" 801 "insn_cr3_store: mov %cr3,%rax;ret\n\t" 802 "insn_cr8_load: xor %eax, %eax; mov %rax,%cr8;ret\n\t" 803 "insn_cr8_store: mov %cr8,%rax;ret\n\t" 804 "insn_monitor: xor %eax, %eax; xor %ecx, %ecx; xor %edx, %edx; monitor;ret\n\t" 805 "insn_pause: pause;ret\n\t" 806 "insn_wbinvd: wbinvd;ret\n\t" 807 "insn_cpuid: mov $10, %eax; cpuid;ret\n\t" 808 "insn_invd: invd;ret\n\t" 809 "insn_sgdt: sgdt gdt_descr;ret\n\t" 810 "insn_lgdt: lgdt gdt_descr;ret\n\t" 811 "insn_sidt: sidt idt_descr;ret\n\t" 812 "insn_lidt: lidt idt_descr;ret\n\t" 813 "insn_sldt: sldt %ax;ret\n\t" 814 "insn_lldt: xor %eax, %eax; lldt %ax;ret\n\t" 815 "insn_str: str %ax;ret\n\t" 816 "insn_rdrand: rdrand %rax;ret\n\t" 817 "insn_rdseed: rdseed %rax;ret\n\t" 818 ); 819 extern void insn_hlt(void); 820 extern void insn_invlpg(void); 821 extern void insn_mwait(void); 822 extern void insn_rdpmc(void); 823 extern void insn_rdtsc(void); 824 extern void insn_cr3_load(void); 825 extern void insn_cr3_store(void); 826 extern void insn_cr8_load(void); 827 extern void insn_cr8_store(void); 828 extern void insn_monitor(void); 829 extern void insn_pause(void); 830 extern void insn_wbinvd(void); 831 extern void insn_sgdt(void); 832 extern void insn_lgdt(void); 833 extern void insn_sidt(void); 834 extern void insn_lidt(void); 835 extern void insn_sldt(void); 836 extern void insn_lldt(void); 837 extern void insn_str(void); 838 extern void insn_cpuid(void); 839 extern void insn_invd(void); 840 extern void insn_rdrand(void); 841 extern void insn_rdseed(void); 842 843 u32 cur_insn; 844 u64 cr3; 845 846 typedef bool (*supported_fn)(void); 847 848 static bool this_cpu_has_mwait(void) 849 { 850 return this_cpu_has(X86_FEATURE_MWAIT); 851 } 852 853 struct insn_table { 854 const char *name; 855 u32 flag; 856 void (*insn_func)(void); 857 u32 type; 858 u32 reason; 859 ulong exit_qual; 860 u32 insn_info; 861 // Use FIELD_EXIT_QUAL and FIELD_INSN_INFO to define 862 // which field need to be tested, reason is always tested 863 u32 test_field; 864 const supported_fn supported_fn; 865 u8 disabled; 866 }; 867 868 /* 869 * Add more test cases of instruction intercept here. Elements in this 870 * table is: 871 * name/control flag/insn function/type/exit reason/exit qulification/ 872 * instruction info/field to test 873 * The last field defines which fields (exit_qual and insn_info) need to be 874 * tested in exit handler. If set to 0, only "reason" is checked. 875 */ 876 static struct insn_table insn_table[] = { 877 // Flags for Primary Processor-Based VM-Execution Controls 878 {"HLT", CPU_HLT, insn_hlt, INSN_CPU0, 12, 0, 0, 0}, 879 {"INVLPG", CPU_INVLPG, insn_invlpg, INSN_CPU0, 14, 880 0x12345678, 0, FIELD_EXIT_QUAL}, 881 {"MWAIT", CPU_MWAIT, insn_mwait, INSN_CPU0, 36, 0, 0, 0, this_cpu_has_mwait}, 882 {"RDPMC", CPU_RDPMC, insn_rdpmc, INSN_CPU0, 15, 0, 0, 0, this_cpu_has_pmu}, 883 {"RDTSC", CPU_RDTSC, insn_rdtsc, INSN_CPU0, 16, 0, 0, 0}, 884 {"CR3 load", CPU_CR3_LOAD, insn_cr3_load, INSN_CPU0, 28, 0x3, 0, 885 FIELD_EXIT_QUAL}, 886 {"CR3 store", CPU_CR3_STORE, insn_cr3_store, INSN_CPU0, 28, 0x13, 0, 887 FIELD_EXIT_QUAL}, 888 {"CR8 load", CPU_CR8_LOAD, insn_cr8_load, INSN_CPU0, 28, 0x8, 0, 889 FIELD_EXIT_QUAL}, 890 {"CR8 store", CPU_CR8_STORE, insn_cr8_store, INSN_CPU0, 28, 0x18, 0, 891 FIELD_EXIT_QUAL}, 892 {"MONITOR", CPU_MONITOR, insn_monitor, INSN_CPU0, 39, 0, 0, 0, this_cpu_has_mwait}, 893 {"PAUSE", CPU_PAUSE, insn_pause, INSN_CPU0, 40, 0, 0, 0}, 894 // Flags for Secondary Processor-Based VM-Execution Controls 895 {"WBINVD", CPU_WBINVD, insn_wbinvd, INSN_CPU1, 54, 0, 0, 0}, 896 {"DESC_TABLE (SGDT)", CPU_DESC_TABLE, insn_sgdt, INSN_CPU1, 46, 0, 0, 0}, 897 {"DESC_TABLE (LGDT)", CPU_DESC_TABLE, insn_lgdt, INSN_CPU1, 46, 0, 0, 0}, 898 {"DESC_TABLE (SIDT)", CPU_DESC_TABLE, insn_sidt, INSN_CPU1, 46, 0, 0, 0}, 899 {"DESC_TABLE (LIDT)", CPU_DESC_TABLE, insn_lidt, INSN_CPU1, 46, 0, 0, 0}, 900 {"DESC_TABLE (SLDT)", CPU_DESC_TABLE, insn_sldt, INSN_CPU1, 47, 0, 0, 0}, 901 {"DESC_TABLE (LLDT)", CPU_DESC_TABLE, insn_lldt, INSN_CPU1, 47, 0, 0, 0}, 902 {"DESC_TABLE (STR)", CPU_DESC_TABLE, insn_str, INSN_CPU1, 47, 0, 0, 0}, 903 /* LTR causes a #GP if done with a busy selector, so it is not tested. */ 904 {"RDRAND", CPU_RDRAND, insn_rdrand, INSN_CPU1, VMX_RDRAND, 0, 0, 0}, 905 {"RDSEED", CPU_RDSEED, insn_rdseed, INSN_CPU1, VMX_RDSEED, 0, 0, 0}, 906 // Instructions always trap 907 {"CPUID", 0, insn_cpuid, INSN_ALWAYS_TRAP, 10, 0, 0, 0}, 908 {"INVD", 0, insn_invd, INSN_ALWAYS_TRAP, 13, 0, 0, 0}, 909 // Instructions never trap 910 {NULL}, 911 }; 912 913 static int insn_intercept_init(struct vmcs *vmcs) 914 { 915 u32 ctrl_cpu, cur_insn; 916 917 ctrl_cpu = ctrl_cpu_rev[0].set | CPU_SECONDARY; 918 ctrl_cpu &= ctrl_cpu_rev[0].clr; 919 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu); 920 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu_rev[1].set); 921 cr3 = read_cr3(); 922 923 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 924 if (insn_table[cur_insn].supported_fn == NULL) 925 continue; 926 insn_table[cur_insn].disabled = !insn_table[cur_insn].supported_fn(); 927 } 928 return VMX_TEST_START; 929 } 930 931 static void insn_intercept_main(void) 932 { 933 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 934 vmx_set_test_stage(cur_insn * 2); 935 if ((insn_table[cur_insn].type == INSN_CPU0 && 936 !(ctrl_cpu_rev[0].clr & insn_table[cur_insn].flag)) || 937 (insn_table[cur_insn].type == INSN_CPU1 && 938 !(ctrl_cpu_rev[1].clr & insn_table[cur_insn].flag))) { 939 printf("\tCPU_CTRL%d.CPU_%s is not supported.\n", 940 insn_table[cur_insn].type - INSN_CPU0, 941 insn_table[cur_insn].name); 942 continue; 943 } 944 945 if (insn_table[cur_insn].disabled) { 946 printf("\tFeature required for %s is not supported.\n", 947 insn_table[cur_insn].name); 948 continue; 949 } 950 951 if ((insn_table[cur_insn].type == INSN_CPU0 && 952 !(ctrl_cpu_rev[0].set & insn_table[cur_insn].flag)) || 953 (insn_table[cur_insn].type == INSN_CPU1 && 954 !(ctrl_cpu_rev[1].set & insn_table[cur_insn].flag))) { 955 /* skip hlt, it stalls the guest and is tested below */ 956 if (insn_table[cur_insn].insn_func != insn_hlt) 957 insn_table[cur_insn].insn_func(); 958 report(vmx_get_test_stage() == cur_insn * 2, 959 "execute %s", 960 insn_table[cur_insn].name); 961 } else if (insn_table[cur_insn].type != INSN_ALWAYS_TRAP) 962 printf("\tCPU_CTRL%d.CPU_%s always traps.\n", 963 insn_table[cur_insn].type - INSN_CPU0, 964 insn_table[cur_insn].name); 965 966 vmcall(); 967 968 insn_table[cur_insn].insn_func(); 969 report(vmx_get_test_stage() == cur_insn * 2 + 1, 970 "intercept %s", 971 insn_table[cur_insn].name); 972 973 vmx_set_test_stage(cur_insn * 2 + 1); 974 vmcall(); 975 } 976 } 977 978 static int insn_intercept_exit_handler(union exit_reason exit_reason) 979 { 980 u64 guest_rip; 981 ulong exit_qual; 982 u32 insn_len; 983 u32 insn_info; 984 bool pass; 985 986 guest_rip = vmcs_read(GUEST_RIP); 987 exit_qual = vmcs_read(EXI_QUALIFICATION); 988 insn_len = vmcs_read(EXI_INST_LEN); 989 insn_info = vmcs_read(EXI_INST_INFO); 990 991 if (exit_reason.basic == VMX_VMCALL) { 992 u32 val = 0; 993 994 if (insn_table[cur_insn].type == INSN_CPU0) 995 val = vmcs_read(CPU_EXEC_CTRL0); 996 else if (insn_table[cur_insn].type == INSN_CPU1) 997 val = vmcs_read(CPU_EXEC_CTRL1); 998 999 if (vmx_get_test_stage() & 1) 1000 val &= ~insn_table[cur_insn].flag; 1001 else 1002 val |= insn_table[cur_insn].flag; 1003 1004 if (insn_table[cur_insn].type == INSN_CPU0) 1005 vmcs_write(CPU_EXEC_CTRL0, val | ctrl_cpu_rev[0].set); 1006 else if (insn_table[cur_insn].type == INSN_CPU1) 1007 vmcs_write(CPU_EXEC_CTRL1, val | ctrl_cpu_rev[1].set); 1008 } else { 1009 pass = (cur_insn * 2 == vmx_get_test_stage()) && 1010 insn_table[cur_insn].reason == exit_reason.full; 1011 if (insn_table[cur_insn].test_field & FIELD_EXIT_QUAL && 1012 insn_table[cur_insn].exit_qual != exit_qual) 1013 pass = false; 1014 if (insn_table[cur_insn].test_field & FIELD_INSN_INFO && 1015 insn_table[cur_insn].insn_info != insn_info) 1016 pass = false; 1017 if (pass) 1018 vmx_inc_test_stage(); 1019 } 1020 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1021 return VMX_TEST_RESUME; 1022 } 1023 1024 /** 1025 * __setup_ept - Setup the VMCS fields to enable Extended Page Tables (EPT) 1026 * @hpa: Host physical address of the top-level, a.k.a. root, EPT table 1027 * @enable_ad: Whether or not to enable Access/Dirty bits for EPT entries 1028 * 1029 * Returns 0 on success, 1 on failure. 1030 * 1031 * Note that @hpa doesn't need to point at actual memory if VM-Launch is 1032 * expected to fail, e.g. setup_dummy_ept() arbitrarily passes '0' to satisfy 1033 * the various EPTP consistency checks, but doesn't ensure backing for HPA '0'. 1034 */ 1035 static int __setup_ept(u64 hpa, bool enable_ad) 1036 { 1037 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1038 !(ctrl_cpu_rev[1].clr & CPU_EPT)) { 1039 printf("\tEPT is not supported\n"); 1040 return 1; 1041 } 1042 if (!is_ept_memtype_supported(EPT_MEM_TYPE_WB)) { 1043 printf("\tWB memtype for EPT walks not supported\n"); 1044 return 1; 1045 } 1046 1047 if (!is_4_level_ept_supported()) { 1048 /* Support for 4-level EPT is mandatory. */ 1049 report(false, "4-level EPT support check"); 1050 printf("\tPWL4 is not supported\n"); 1051 return 1; 1052 } 1053 1054 eptp = EPT_MEM_TYPE_WB; 1055 eptp |= (3 << EPTP_PG_WALK_LEN_SHIFT); 1056 eptp |= hpa; 1057 if (enable_ad) 1058 eptp |= EPTP_AD_FLAG; 1059 1060 vmcs_write(EPTP, eptp); 1061 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0)| CPU_SECONDARY); 1062 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1)| CPU_EPT); 1063 1064 return 0; 1065 } 1066 1067 /** 1068 * setup_ept - Enable Extended Page Tables (EPT) and setup an identity map 1069 * @enable_ad: Whether or not to enable Access/Dirty bits for EPT entries 1070 * 1071 * Returns 0 on success, 1 on failure. 1072 * 1073 * This is the "real" function for setting up EPT tables, i.e. use this for 1074 * tests that need to run code in the guest with EPT enabled. 1075 */ 1076 static int setup_ept(bool enable_ad) 1077 { 1078 unsigned long end_of_memory; 1079 1080 pml4 = alloc_page(); 1081 1082 if (__setup_ept(virt_to_phys(pml4), enable_ad)) 1083 return 1; 1084 1085 end_of_memory = fwcfg_get_u64(FW_CFG_RAM_SIZE); 1086 if (end_of_memory < (1ul << 32)) 1087 end_of_memory = (1ul << 32); 1088 /* Cannot use large EPT pages if we need to track EPT 1089 * accessed/dirty bits at 4K granularity. 1090 */ 1091 setup_ept_range(pml4, 0, end_of_memory, 0, 1092 !enable_ad && ept_2m_supported(), 1093 EPT_WA | EPT_RA | EPT_EA); 1094 return 0; 1095 } 1096 1097 /** 1098 * setup_dummy_ept - Enable Extended Page Tables (EPT) with a dummy root HPA 1099 * 1100 * Setup EPT using a semi-arbitrary dummy root HPA. This function is intended 1101 * for use by tests that need EPT enabled to verify dependent VMCS controls 1102 * but never expect to fully enter the guest, i.e. don't need setup the actual 1103 * EPT tables. 1104 */ 1105 static void setup_dummy_ept(void) 1106 { 1107 if (__setup_ept(0, false)) 1108 report_abort("EPT setup unexpectedly failed"); 1109 } 1110 1111 static int enable_unrestricted_guest(bool need_valid_ept) 1112 { 1113 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1114 !(ctrl_cpu_rev[1].clr & CPU_URG) || 1115 !(ctrl_cpu_rev[1].clr & CPU_EPT)) 1116 return 1; 1117 1118 if (need_valid_ept) 1119 setup_ept(false); 1120 else 1121 setup_dummy_ept(); 1122 1123 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 1124 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | CPU_URG); 1125 1126 return 0; 1127 } 1128 1129 static void ept_enable_ad_bits(void) 1130 { 1131 eptp |= EPTP_AD_FLAG; 1132 vmcs_write(EPTP, eptp); 1133 } 1134 1135 static void ept_disable_ad_bits(void) 1136 { 1137 eptp &= ~EPTP_AD_FLAG; 1138 vmcs_write(EPTP, eptp); 1139 } 1140 1141 static int ept_ad_enabled(void) 1142 { 1143 return eptp & EPTP_AD_FLAG; 1144 } 1145 1146 static void ept_enable_ad_bits_or_skip_test(void) 1147 { 1148 if (!ept_ad_bits_supported()) 1149 test_skip("EPT AD bits not supported."); 1150 ept_enable_ad_bits(); 1151 } 1152 1153 static int apic_version; 1154 1155 static int ept_init_common(bool have_ad) 1156 { 1157 int ret; 1158 struct pci_dev pcidev; 1159 1160 /* INVEPT is required by the EPT violation handler. */ 1161 if (!is_invept_type_supported(INVEPT_SINGLE)) 1162 return VMX_TEST_EXIT; 1163 1164 if (setup_ept(have_ad)) 1165 return VMX_TEST_EXIT; 1166 1167 data_page1 = alloc_page(); 1168 data_page2 = alloc_page(); 1169 *((u32 *)data_page1) = MAGIC_VAL_1; 1170 *((u32 *)data_page2) = MAGIC_VAL_2; 1171 install_ept(pml4, (unsigned long)data_page1, (unsigned long)data_page2, 1172 EPT_RA | EPT_WA | EPT_EA); 1173 1174 apic_version = apic_read(APIC_LVR); 1175 1176 ret = pci_find_dev(PCI_VENDOR_ID_REDHAT, PCI_DEVICE_ID_REDHAT_TEST); 1177 if (ret != PCIDEVADDR_INVALID) { 1178 pci_dev_init(&pcidev, ret); 1179 pci_physaddr = pcidev.resource[PCI_TESTDEV_BAR_MEM]; 1180 } 1181 1182 return VMX_TEST_START; 1183 } 1184 1185 static int ept_init(struct vmcs *vmcs) 1186 { 1187 return ept_init_common(false); 1188 } 1189 1190 static void ept_common(void) 1191 { 1192 vmx_set_test_stage(0); 1193 if (*((u32 *)data_page2) != MAGIC_VAL_1 || 1194 *((u32 *)data_page1) != MAGIC_VAL_1) 1195 report_fail("EPT basic framework - read"); 1196 else { 1197 *((u32 *)data_page2) = MAGIC_VAL_3; 1198 vmcall(); 1199 if (vmx_get_test_stage() == 1) { 1200 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1201 *((u32 *)data_page2) == MAGIC_VAL_2) 1202 report_pass("EPT basic framework"); 1203 else 1204 report_pass("EPT basic framework - remap"); 1205 } 1206 } 1207 // Test EPT Misconfigurations 1208 vmx_set_test_stage(1); 1209 vmcall(); 1210 *((u32 *)data_page1) = MAGIC_VAL_1; 1211 if (vmx_get_test_stage() != 2) { 1212 report_fail("EPT misconfigurations"); 1213 goto t1; 1214 } 1215 vmx_set_test_stage(2); 1216 vmcall(); 1217 *((u32 *)data_page1) = MAGIC_VAL_1; 1218 report(vmx_get_test_stage() == 3, "EPT misconfigurations"); 1219 t1: 1220 // Test EPT violation 1221 vmx_set_test_stage(3); 1222 vmcall(); 1223 *((u32 *)data_page1) = MAGIC_VAL_1; 1224 report(vmx_get_test_stage() == 4, "EPT violation - page permission"); 1225 // Violation caused by EPT paging structure 1226 vmx_set_test_stage(4); 1227 vmcall(); 1228 *((u32 *)data_page1) = MAGIC_VAL_2; 1229 report(vmx_get_test_stage() == 5, "EPT violation - paging structure"); 1230 1231 // MMIO Read/Write 1232 vmx_set_test_stage(5); 1233 vmcall(); 1234 1235 *(u32 volatile *)pci_physaddr; 1236 report(vmx_get_test_stage() == 6, "MMIO EPT violation - read"); 1237 1238 *(u32 volatile *)pci_physaddr = MAGIC_VAL_1; 1239 report(vmx_get_test_stage() == 7, "MMIO EPT violation - write"); 1240 } 1241 1242 static void ept_main(void) 1243 { 1244 ept_common(); 1245 1246 // Test EPT access to L1 MMIO 1247 vmx_set_test_stage(7); 1248 report(*((u32 *)0xfee00030UL) == apic_version, "EPT - MMIO access"); 1249 1250 // Test invalid operand for INVEPT 1251 vmcall(); 1252 report(vmx_get_test_stage() == 8, "EPT - unsupported INVEPT"); 1253 } 1254 1255 static bool invept_test(int type, u64 eptp) 1256 { 1257 bool ret, supported; 1258 1259 supported = ept_vpid.val & (EPT_CAP_INVEPT_SINGLE >> INVEPT_SINGLE << type); 1260 ret = __invept(type, eptp); 1261 1262 if (ret == !supported) 1263 return false; 1264 1265 if (!supported) 1266 printf("WARNING: unsupported invept passed!\n"); 1267 else 1268 printf("WARNING: invept failed!\n"); 1269 1270 return true; 1271 } 1272 1273 static int pml_exit_handler(union exit_reason exit_reason) 1274 { 1275 u16 index, count; 1276 u64 *pmlbuf = pml_log; 1277 u64 guest_rip = vmcs_read(GUEST_RIP);; 1278 u64 guest_cr3 = vmcs_read(GUEST_CR3); 1279 u32 insn_len = vmcs_read(EXI_INST_LEN); 1280 1281 switch (exit_reason.basic) { 1282 case VMX_VMCALL: 1283 switch (vmx_get_test_stage()) { 1284 case 0: 1285 index = vmcs_read(GUEST_PML_INDEX); 1286 for (count = index + 1; count < PML_INDEX; count++) { 1287 if (pmlbuf[count] == (u64)data_page2) { 1288 vmx_inc_test_stage(); 1289 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1290 break; 1291 } 1292 } 1293 break; 1294 case 1: 1295 index = vmcs_read(GUEST_PML_INDEX); 1296 /* Keep clearing the dirty bit till a overflow */ 1297 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1298 break; 1299 default: 1300 report_fail("unexpected stage, %d.", 1301 vmx_get_test_stage()); 1302 print_vmexit_info(exit_reason); 1303 return VMX_TEST_VMEXIT; 1304 } 1305 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1306 return VMX_TEST_RESUME; 1307 case VMX_PML_FULL: 1308 vmx_inc_test_stage(); 1309 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1310 return VMX_TEST_RESUME; 1311 default: 1312 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 1313 print_vmexit_info(exit_reason); 1314 } 1315 return VMX_TEST_VMEXIT; 1316 } 1317 1318 static int ept_exit_handler_common(union exit_reason exit_reason, bool have_ad) 1319 { 1320 u64 guest_rip; 1321 u64 guest_cr3; 1322 u32 insn_len; 1323 u32 exit_qual; 1324 static unsigned long data_page1_pte, data_page1_pte_pte, memaddr_pte, 1325 guest_pte_addr; 1326 1327 guest_rip = vmcs_read(GUEST_RIP); 1328 guest_cr3 = vmcs_read(GUEST_CR3); 1329 insn_len = vmcs_read(EXI_INST_LEN); 1330 exit_qual = vmcs_read(EXI_QUALIFICATION); 1331 pteval_t *ptep; 1332 switch (exit_reason.basic) { 1333 case VMX_VMCALL: 1334 switch (vmx_get_test_stage()) { 1335 case 0: 1336 check_ept_ad(pml4, guest_cr3, 1337 (unsigned long)data_page1, 1338 have_ad ? EPT_ACCESS_FLAG : 0, 1339 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1340 check_ept_ad(pml4, guest_cr3, 1341 (unsigned long)data_page2, 1342 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0, 1343 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1344 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1345 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1346 if (have_ad) 1347 invept(INVEPT_SINGLE, eptp); 1348 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1349 *((u32 *)data_page2) == MAGIC_VAL_2) { 1350 vmx_inc_test_stage(); 1351 install_ept(pml4, (unsigned long)data_page2, 1352 (unsigned long)data_page2, 1353 EPT_RA | EPT_WA | EPT_EA); 1354 } else 1355 report_fail("EPT basic framework - write"); 1356 break; 1357 case 1: 1358 install_ept(pml4, (unsigned long)data_page1, 1359 (unsigned long)data_page1, EPT_WA); 1360 invept(INVEPT_SINGLE, eptp); 1361 break; 1362 case 2: 1363 install_ept(pml4, (unsigned long)data_page1, 1364 (unsigned long)data_page1, 1365 EPT_RA | EPT_WA | EPT_EA | 1366 (2 << EPT_MEM_TYPE_SHIFT)); 1367 invept(INVEPT_SINGLE, eptp); 1368 break; 1369 case 3: 1370 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1371 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)data_page1, 1372 1, &data_page1_pte)); 1373 set_ept_pte(pml4, (unsigned long)data_page1, 1374 1, data_page1_pte & ~EPT_PRESENT); 1375 invept(INVEPT_SINGLE, eptp); 1376 break; 1377 case 4: 1378 ptep = get_pte_level((pgd_t *)guest_cr3, data_page1, /*level=*/2); 1379 guest_pte_addr = virt_to_phys(ptep) & PAGE_MASK; 1380 1381 TEST_ASSERT(get_ept_pte(pml4, guest_pte_addr, 2, &data_page1_pte_pte)); 1382 set_ept_pte(pml4, guest_pte_addr, 2, 1383 data_page1_pte_pte & ~EPT_PRESENT); 1384 invept(INVEPT_SINGLE, eptp); 1385 break; 1386 case 5: 1387 install_ept(pml4, (unsigned long)pci_physaddr, 1388 (unsigned long)pci_physaddr, 0); 1389 invept(INVEPT_SINGLE, eptp); 1390 break; 1391 case 7: 1392 if (!invept_test(0, eptp)) 1393 vmx_inc_test_stage(); 1394 break; 1395 // Should not reach here 1396 default: 1397 report_fail("ERROR - unexpected stage, %d.", 1398 vmx_get_test_stage()); 1399 print_vmexit_info(exit_reason); 1400 return VMX_TEST_VMEXIT; 1401 } 1402 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1403 return VMX_TEST_RESUME; 1404 case VMX_EPT_MISCONFIG: 1405 switch (vmx_get_test_stage()) { 1406 case 1: 1407 case 2: 1408 vmx_inc_test_stage(); 1409 install_ept(pml4, (unsigned long)data_page1, 1410 (unsigned long)data_page1, 1411 EPT_RA | EPT_WA | EPT_EA); 1412 invept(INVEPT_SINGLE, eptp); 1413 break; 1414 // Should not reach here 1415 default: 1416 report_fail("ERROR - unexpected stage, %d.", 1417 vmx_get_test_stage()); 1418 print_vmexit_info(exit_reason); 1419 return VMX_TEST_VMEXIT; 1420 } 1421 return VMX_TEST_RESUME; 1422 case VMX_EPT_VIOLATION: 1423 /* 1424 * Exit-qualifications are masked not to account for advanced 1425 * VM-exit information. Once KVM supports this feature, this 1426 * masking should be removed. 1427 */ 1428 exit_qual &= ~EPT_VLT_GUEST_MASK; 1429 1430 switch(vmx_get_test_stage()) { 1431 case 3: 1432 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1433 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1434 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1435 if (exit_qual == (EPT_VLT_WR | EPT_VLT_LADDR_VLD | 1436 EPT_VLT_PADDR)) 1437 vmx_inc_test_stage(); 1438 set_ept_pte(pml4, (unsigned long)data_page1, 1439 1, data_page1_pte | (EPT_PRESENT)); 1440 invept(INVEPT_SINGLE, eptp); 1441 break; 1442 case 4: 1443 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1444 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1445 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1446 if (exit_qual == (EPT_VLT_RD | 1447 (have_ad ? EPT_VLT_WR : 0) | 1448 EPT_VLT_LADDR_VLD)) 1449 vmx_inc_test_stage(); 1450 set_ept_pte(pml4, guest_pte_addr, 2, 1451 data_page1_pte_pte | (EPT_PRESENT)); 1452 invept(INVEPT_SINGLE, eptp); 1453 break; 1454 case 5: 1455 if (exit_qual & EPT_VLT_RD) 1456 vmx_inc_test_stage(); 1457 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1458 1, &memaddr_pte)); 1459 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA); 1460 invept(INVEPT_SINGLE, eptp); 1461 break; 1462 case 6: 1463 if (exit_qual & EPT_VLT_WR) 1464 vmx_inc_test_stage(); 1465 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1466 1, &memaddr_pte)); 1467 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA | EPT_WA); 1468 invept(INVEPT_SINGLE, eptp); 1469 break; 1470 default: 1471 // Should not reach here 1472 report_fail("ERROR : unexpected stage, %d", 1473 vmx_get_test_stage()); 1474 print_vmexit_info(exit_reason); 1475 return VMX_TEST_VMEXIT; 1476 } 1477 return VMX_TEST_RESUME; 1478 default: 1479 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 1480 print_vmexit_info(exit_reason); 1481 } 1482 return VMX_TEST_VMEXIT; 1483 } 1484 1485 static int ept_exit_handler(union exit_reason exit_reason) 1486 { 1487 return ept_exit_handler_common(exit_reason, false); 1488 } 1489 1490 static int eptad_init(struct vmcs *vmcs) 1491 { 1492 int r = ept_init_common(true); 1493 1494 if (r == VMX_TEST_EXIT) 1495 return r; 1496 1497 if (!ept_ad_bits_supported()) { 1498 printf("\tEPT A/D bits are not supported"); 1499 return VMX_TEST_EXIT; 1500 } 1501 1502 return r; 1503 } 1504 1505 static int pml_init(struct vmcs *vmcs) 1506 { 1507 u32 ctrl_cpu; 1508 int r = eptad_init(vmcs); 1509 1510 if (r == VMX_TEST_EXIT) 1511 return r; 1512 1513 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1514 !(ctrl_cpu_rev[1].clr & CPU_PML)) { 1515 printf("\tPML is not supported"); 1516 return VMX_TEST_EXIT; 1517 } 1518 1519 pml_log = alloc_page(); 1520 vmcs_write(PMLADDR, (u64)pml_log); 1521 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1522 1523 ctrl_cpu = vmcs_read(CPU_EXEC_CTRL1) | CPU_PML; 1524 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu); 1525 1526 return VMX_TEST_START; 1527 } 1528 1529 static void pml_main(void) 1530 { 1531 int count = 0; 1532 1533 vmx_set_test_stage(0); 1534 *((u32 *)data_page2) = 0x1; 1535 vmcall(); 1536 report(vmx_get_test_stage() == 1, "PML - Dirty GPA Logging"); 1537 1538 while (vmx_get_test_stage() == 1) { 1539 vmcall(); 1540 *((u32 *)data_page2) = 0x1; 1541 if (count++ > PML_INDEX) 1542 break; 1543 } 1544 report(vmx_get_test_stage() == 2, "PML Full Event"); 1545 } 1546 1547 static void eptad_main(void) 1548 { 1549 ept_common(); 1550 } 1551 1552 static int eptad_exit_handler(union exit_reason exit_reason) 1553 { 1554 return ept_exit_handler_common(exit_reason, true); 1555 } 1556 1557 #define TIMER_VECTOR 222 1558 1559 static volatile bool timer_fired; 1560 1561 static void timer_isr(isr_regs_t *regs) 1562 { 1563 timer_fired = true; 1564 apic_write(APIC_EOI, 0); 1565 } 1566 1567 static int interrupt_init(struct vmcs *vmcs) 1568 { 1569 msr_bmp_init(); 1570 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1571 handle_irq(TIMER_VECTOR, timer_isr); 1572 return VMX_TEST_START; 1573 } 1574 1575 static void interrupt_main(void) 1576 { 1577 long long start, loops; 1578 1579 vmx_set_test_stage(0); 1580 1581 apic_write(APIC_LVTT, TIMER_VECTOR); 1582 sti(); 1583 1584 apic_write(APIC_TMICT, 1); 1585 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1586 asm volatile ("nop"); 1587 report(timer_fired, "direct interrupt while running guest"); 1588 1589 apic_write(APIC_TMICT, 0); 1590 cli(); 1591 vmcall(); 1592 timer_fired = false; 1593 apic_write(APIC_TMICT, 1); 1594 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1595 asm volatile ("nop"); 1596 report(timer_fired, "intercepted interrupt while running guest"); 1597 1598 sti(); 1599 apic_write(APIC_TMICT, 0); 1600 cli(); 1601 vmcall(); 1602 timer_fired = false; 1603 start = rdtsc(); 1604 apic_write(APIC_TMICT, 1000000); 1605 1606 safe_halt(); 1607 1608 report(rdtsc() - start > 1000000 && timer_fired, 1609 "direct interrupt + hlt"); 1610 1611 apic_write(APIC_TMICT, 0); 1612 cli(); 1613 vmcall(); 1614 timer_fired = false; 1615 start = rdtsc(); 1616 apic_write(APIC_TMICT, 1000000); 1617 1618 safe_halt(); 1619 1620 report(rdtsc() - start > 10000 && timer_fired, 1621 "intercepted interrupt + hlt"); 1622 1623 apic_write(APIC_TMICT, 0); 1624 cli(); 1625 vmcall(); 1626 timer_fired = false; 1627 start = rdtsc(); 1628 apic_write(APIC_TMICT, 1000000); 1629 1630 sti_nop(); 1631 vmcall(); 1632 1633 report(rdtsc() - start > 10000 && timer_fired, 1634 "direct interrupt + activity state hlt"); 1635 1636 apic_write(APIC_TMICT, 0); 1637 cli(); 1638 vmcall(); 1639 timer_fired = false; 1640 start = rdtsc(); 1641 apic_write(APIC_TMICT, 1000000); 1642 1643 sti_nop(); 1644 vmcall(); 1645 1646 report(rdtsc() - start > 10000 && timer_fired, 1647 "intercepted interrupt + activity state hlt"); 1648 1649 apic_write(APIC_TMICT, 0); 1650 cli(); 1651 vmx_set_test_stage(7); 1652 vmcall(); 1653 timer_fired = false; 1654 apic_write(APIC_TMICT, 1); 1655 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1656 asm volatile ("nop"); 1657 report(timer_fired, 1658 "running a guest with interrupt acknowledgement set"); 1659 1660 apic_write(APIC_TMICT, 0); 1661 sti(); 1662 timer_fired = false; 1663 vmcall(); 1664 report(timer_fired, "Inject an event to a halted guest"); 1665 } 1666 1667 static int interrupt_exit_handler(union exit_reason exit_reason) 1668 { 1669 u64 guest_rip = vmcs_read(GUEST_RIP); 1670 u32 insn_len = vmcs_read(EXI_INST_LEN); 1671 1672 switch (exit_reason.basic) { 1673 case VMX_VMCALL: 1674 switch (vmx_get_test_stage()) { 1675 case 0: 1676 case 2: 1677 case 5: 1678 vmcs_write(PIN_CONTROLS, 1679 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1680 break; 1681 case 7: 1682 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_INTA); 1683 vmcs_write(PIN_CONTROLS, 1684 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1685 break; 1686 case 1: 1687 case 3: 1688 vmcs_write(PIN_CONTROLS, 1689 vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1690 break; 1691 case 4: 1692 case 6: 1693 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1694 break; 1695 1696 case 8: 1697 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1698 vmcs_write(ENT_INTR_INFO, 1699 TIMER_VECTOR | 1700 (VMX_INTR_TYPE_EXT_INTR << INTR_INFO_INTR_TYPE_SHIFT) | 1701 INTR_INFO_VALID_MASK); 1702 break; 1703 } 1704 vmx_inc_test_stage(); 1705 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1706 return VMX_TEST_RESUME; 1707 case VMX_EXTINT: 1708 if (vmcs_read(EXI_CONTROLS) & EXI_INTA) { 1709 int vector = vmcs_read(EXI_INTR_INFO) & 0xff; 1710 handle_external_interrupt(vector); 1711 } else { 1712 sti_nop_cli(); 1713 } 1714 if (vmx_get_test_stage() >= 2) 1715 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 1716 return VMX_TEST_RESUME; 1717 default: 1718 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 1719 print_vmexit_info(exit_reason); 1720 } 1721 1722 return VMX_TEST_VMEXIT; 1723 } 1724 1725 1726 static volatile int nmi_fired; 1727 1728 #define NMI_DELAY 100000000ULL 1729 1730 static void nmi_isr(isr_regs_t *regs) 1731 { 1732 nmi_fired = true; 1733 } 1734 1735 static int nmi_hlt_init(struct vmcs *vmcs) 1736 { 1737 msr_bmp_init(); 1738 handle_irq(NMI_VECTOR, nmi_isr); 1739 vmcs_write(PIN_CONTROLS, 1740 vmcs_read(PIN_CONTROLS) & ~PIN_NMI); 1741 vmcs_write(PIN_CONTROLS, 1742 vmcs_read(PIN_CONTROLS) & ~PIN_VIRT_NMI); 1743 return VMX_TEST_START; 1744 } 1745 1746 static void nmi_message_thread(void *data) 1747 { 1748 while (vmx_get_test_stage() != 1) 1749 pause(); 1750 1751 delay(NMI_DELAY); 1752 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_NMI | APIC_INT_ASSERT, id_map[0]); 1753 1754 while (vmx_get_test_stage() != 2) 1755 pause(); 1756 1757 delay(NMI_DELAY); 1758 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_NMI | APIC_INT_ASSERT, id_map[0]); 1759 } 1760 1761 static void nmi_hlt_main(void) 1762 { 1763 long long start; 1764 1765 if (cpu_count() < 2) { 1766 report_skip("%s : CPU count < 2", __func__); 1767 vmx_set_test_stage(-1); 1768 return; 1769 } 1770 1771 vmx_set_test_stage(0); 1772 on_cpu_async(1, nmi_message_thread, NULL); 1773 start = rdtsc(); 1774 vmx_set_test_stage(1); 1775 asm volatile ("hlt"); 1776 report((rdtsc() - start > NMI_DELAY) && nmi_fired, 1777 "direct NMI + hlt"); 1778 if (!nmi_fired) 1779 vmx_set_test_stage(-1); 1780 nmi_fired = false; 1781 1782 vmcall(); 1783 1784 start = rdtsc(); 1785 vmx_set_test_stage(2); 1786 asm volatile ("hlt"); 1787 report((rdtsc() - start > NMI_DELAY) && !nmi_fired, 1788 "intercepted NMI + hlt"); 1789 if (nmi_fired) { 1790 report(!nmi_fired, "intercepted NMI was dispatched"); 1791 vmx_set_test_stage(-1); 1792 return; 1793 } 1794 vmx_set_test_stage(3); 1795 } 1796 1797 static int nmi_hlt_exit_handler(union exit_reason exit_reason) 1798 { 1799 u64 guest_rip = vmcs_read(GUEST_RIP); 1800 u32 insn_len = vmcs_read(EXI_INST_LEN); 1801 1802 switch (vmx_get_test_stage()) { 1803 case 1: 1804 if (exit_reason.basic != VMX_VMCALL) { 1805 report_fail("VMEXIT not due to vmcall. Exit reason 0x%x", 1806 exit_reason.full); 1807 print_vmexit_info(exit_reason); 1808 return VMX_TEST_VMEXIT; 1809 } 1810 1811 vmcs_write(PIN_CONTROLS, 1812 vmcs_read(PIN_CONTROLS) | PIN_NMI); 1813 vmcs_write(PIN_CONTROLS, 1814 vmcs_read(PIN_CONTROLS) | PIN_VIRT_NMI); 1815 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1816 break; 1817 1818 case 2: 1819 if (exit_reason.basic != VMX_EXC_NMI) { 1820 report_fail("VMEXIT not due to NMI intercept. Exit reason 0x%x", 1821 exit_reason.full); 1822 print_vmexit_info(exit_reason); 1823 return VMX_TEST_VMEXIT; 1824 } 1825 report_pass("NMI intercept while running guest"); 1826 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 1827 break; 1828 1829 case 3: 1830 break; 1831 1832 default: 1833 return VMX_TEST_VMEXIT; 1834 } 1835 1836 if (vmx_get_test_stage() == 3) 1837 return VMX_TEST_VMEXIT; 1838 1839 return VMX_TEST_RESUME; 1840 } 1841 1842 1843 static int dbgctls_init(struct vmcs *vmcs) 1844 { 1845 u64 dr7 = 0x402; 1846 u64 zero = 0; 1847 1848 msr_bmp_init(); 1849 asm volatile( 1850 "mov %0,%%dr0\n\t" 1851 "mov %0,%%dr1\n\t" 1852 "mov %0,%%dr2\n\t" 1853 "mov %1,%%dr7\n\t" 1854 : : "r" (zero), "r" (dr7)); 1855 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1856 vmcs_write(GUEST_DR7, 0x404); 1857 vmcs_write(GUEST_DEBUGCTL, 0x2); 1858 1859 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 1860 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_SAVE_DBGCTLS); 1861 1862 return VMX_TEST_START; 1863 } 1864 1865 static void dbgctls_main(void) 1866 { 1867 u64 dr7, debugctl; 1868 1869 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1870 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1871 /* Commented out: KVM does not support DEBUGCTL so far */ 1872 (void)debugctl; 1873 report(dr7 == 0x404, "Load debug controls" /* && debugctl == 0x2 */); 1874 1875 dr7 = 0x408; 1876 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1877 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1878 1879 vmx_set_test_stage(0); 1880 vmcall(); 1881 report(vmx_get_test_stage() == 1, "Save debug controls"); 1882 1883 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS || 1884 ctrl_exit_rev.set & EXI_SAVE_DBGCTLS) { 1885 printf("\tDebug controls are always loaded/saved\n"); 1886 return; 1887 } 1888 vmx_set_test_stage(2); 1889 vmcall(); 1890 1891 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1892 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1893 /* Commented out: KVM does not support DEBUGCTL so far */ 1894 (void)debugctl; 1895 report(dr7 == 0x402, 1896 "Guest=host debug controls" /* && debugctl == 0x1 */); 1897 1898 dr7 = 0x408; 1899 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1900 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1901 1902 vmx_set_test_stage(3); 1903 vmcall(); 1904 report(vmx_get_test_stage() == 4, "Don't save debug controls"); 1905 } 1906 1907 static int dbgctls_exit_handler(union exit_reason exit_reason) 1908 { 1909 u32 insn_len = vmcs_read(EXI_INST_LEN); 1910 u64 guest_rip = vmcs_read(GUEST_RIP); 1911 u64 dr7, debugctl; 1912 1913 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1914 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1915 1916 switch (exit_reason.basic) { 1917 case VMX_VMCALL: 1918 switch (vmx_get_test_stage()) { 1919 case 0: 1920 if (dr7 == 0x400 && debugctl == 0 && 1921 vmcs_read(GUEST_DR7) == 0x408 /* && 1922 Commented out: KVM does not support DEBUGCTL so far 1923 vmcs_read(GUEST_DEBUGCTL) == 0x3 */) 1924 vmx_inc_test_stage(); 1925 break; 1926 case 2: 1927 dr7 = 0x402; 1928 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1929 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1930 vmcs_write(GUEST_DR7, 0x404); 1931 vmcs_write(GUEST_DEBUGCTL, 0x2); 1932 1933 vmcs_write(ENT_CONTROLS, 1934 vmcs_read(ENT_CONTROLS) & ~ENT_LOAD_DBGCTLS); 1935 vmcs_write(EXI_CONTROLS, 1936 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_DBGCTLS); 1937 break; 1938 case 3: 1939 if (dr7 == 0x400 && debugctl == 0 && 1940 vmcs_read(GUEST_DR7) == 0x404 /* && 1941 Commented out: KVM does not support DEBUGCTL so far 1942 vmcs_read(GUEST_DEBUGCTL) == 0x2 */) 1943 vmx_inc_test_stage(); 1944 break; 1945 } 1946 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1947 return VMX_TEST_RESUME; 1948 default: 1949 report_fail("Unknown exit reason, %d", exit_reason.full); 1950 print_vmexit_info(exit_reason); 1951 } 1952 return VMX_TEST_VMEXIT; 1953 } 1954 1955 struct vmx_msr_entry { 1956 u32 index; 1957 u32 reserved; 1958 u64 value; 1959 } __attribute__((packed)); 1960 1961 #define MSR_MAGIC 0x31415926 1962 struct vmx_msr_entry *exit_msr_store, *entry_msr_load, *exit_msr_load; 1963 1964 static int msr_switch_init(struct vmcs *vmcs) 1965 { 1966 msr_bmp_init(); 1967 exit_msr_store = alloc_page(); 1968 exit_msr_load = alloc_page(); 1969 entry_msr_load = alloc_page(); 1970 entry_msr_load[0].index = MSR_KERNEL_GS_BASE; 1971 entry_msr_load[0].value = MSR_MAGIC; 1972 1973 vmx_set_test_stage(1); 1974 vmcs_write(ENT_MSR_LD_CNT, 1); 1975 vmcs_write(ENTER_MSR_LD_ADDR, (u64)entry_msr_load); 1976 vmcs_write(EXI_MSR_ST_CNT, 1); 1977 vmcs_write(EXIT_MSR_ST_ADDR, (u64)exit_msr_store); 1978 vmcs_write(EXI_MSR_LD_CNT, 1); 1979 vmcs_write(EXIT_MSR_LD_ADDR, (u64)exit_msr_load); 1980 return VMX_TEST_START; 1981 } 1982 1983 static void msr_switch_main(void) 1984 { 1985 if (vmx_get_test_stage() == 1) { 1986 report(rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC, 1987 "VM entry MSR load"); 1988 vmx_set_test_stage(2); 1989 wrmsr(MSR_KERNEL_GS_BASE, MSR_MAGIC + 1); 1990 exit_msr_store[0].index = MSR_KERNEL_GS_BASE; 1991 exit_msr_load[0].index = MSR_KERNEL_GS_BASE; 1992 exit_msr_load[0].value = MSR_MAGIC + 2; 1993 } 1994 vmcall(); 1995 } 1996 1997 static int msr_switch_exit_handler(union exit_reason exit_reason) 1998 { 1999 if (exit_reason.basic == VMX_VMCALL && vmx_get_test_stage() == 2) { 2000 report(exit_msr_store[0].value == MSR_MAGIC + 1, 2001 "VM exit MSR store"); 2002 report(rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC + 2, 2003 "VM exit MSR load"); 2004 vmx_set_test_stage(3); 2005 entry_msr_load[0].index = MSR_FS_BASE; 2006 return VMX_TEST_RESUME; 2007 } 2008 printf("ERROR %s: unexpected stage=%u or reason=0x%x\n", 2009 __func__, vmx_get_test_stage(), exit_reason.full); 2010 return VMX_TEST_EXIT; 2011 } 2012 2013 static int msr_switch_entry_failure(struct vmentry_result *result) 2014 { 2015 if (result->vm_fail) { 2016 printf("ERROR %s: VM-Fail on %s\n", __func__, result->instr); 2017 return VMX_TEST_EXIT; 2018 } 2019 2020 if (result->exit_reason.failed_vmentry && 2021 result->exit_reason.basic == VMX_FAIL_MSR && 2022 vmx_get_test_stage() == 3) { 2023 report(vmcs_read(EXI_QUALIFICATION) == 1, 2024 "VM entry MSR load: try to load FS_BASE"); 2025 return VMX_TEST_VMEXIT; 2026 } 2027 printf("ERROR %s: unexpected stage=%u or reason=%x\n", 2028 __func__, vmx_get_test_stage(), result->exit_reason.full); 2029 return VMX_TEST_EXIT; 2030 } 2031 2032 static int vmmcall_init(struct vmcs *vmcs) 2033 { 2034 vmcs_write(EXC_BITMAP, 1 << UD_VECTOR); 2035 return VMX_TEST_START; 2036 } 2037 2038 static void vmmcall_main(void) 2039 { 2040 asm volatile( 2041 "mov $0xABCD, %%rax\n\t" 2042 "vmmcall\n\t" 2043 ::: "rax"); 2044 2045 report_fail("VMMCALL"); 2046 } 2047 2048 static int vmmcall_exit_handler(union exit_reason exit_reason) 2049 { 2050 switch (exit_reason.basic) { 2051 case VMX_VMCALL: 2052 printf("here\n"); 2053 report_fail("VMMCALL triggers #UD"); 2054 break; 2055 case VMX_EXC_NMI: 2056 report((vmcs_read(EXI_INTR_INFO) & 0xff) == UD_VECTOR, 2057 "VMMCALL triggers #UD"); 2058 break; 2059 default: 2060 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 2061 print_vmexit_info(exit_reason); 2062 } 2063 2064 return VMX_TEST_VMEXIT; 2065 } 2066 2067 static int disable_rdtscp_init(struct vmcs *vmcs) 2068 { 2069 u32 ctrl_cpu1; 2070 2071 if (ctrl_cpu_rev[0].clr & CPU_SECONDARY) { 2072 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 2073 ctrl_cpu1 &= ~CPU_RDTSCP; 2074 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 2075 } 2076 2077 return VMX_TEST_START; 2078 } 2079 2080 static void disable_rdtscp_ud_handler(struct ex_regs *regs) 2081 { 2082 switch (vmx_get_test_stage()) { 2083 case 0: 2084 report_pass("RDTSCP triggers #UD"); 2085 vmx_inc_test_stage(); 2086 regs->rip += 3; 2087 break; 2088 case 2: 2089 report_pass("RDPID triggers #UD"); 2090 vmx_inc_test_stage(); 2091 regs->rip += 4; 2092 break; 2093 } 2094 return; 2095 2096 } 2097 2098 static void disable_rdtscp_main(void) 2099 { 2100 /* Test that #UD is properly injected in L2. */ 2101 handle_exception(UD_VECTOR, disable_rdtscp_ud_handler); 2102 2103 vmx_set_test_stage(0); 2104 asm volatile("rdtscp" : : : "eax", "ecx", "edx"); 2105 vmcall(); 2106 asm volatile(".byte 0xf3, 0x0f, 0xc7, 0xf8" : : : "eax"); 2107 2108 handle_exception(UD_VECTOR, 0); 2109 vmcall(); 2110 } 2111 2112 static int disable_rdtscp_exit_handler(union exit_reason exit_reason) 2113 { 2114 switch (exit_reason.basic) { 2115 case VMX_VMCALL: 2116 switch (vmx_get_test_stage()) { 2117 case 0: 2118 report_fail("RDTSCP triggers #UD"); 2119 vmx_inc_test_stage(); 2120 /* fallthrough */ 2121 case 1: 2122 vmx_inc_test_stage(); 2123 vmcs_write(GUEST_RIP, vmcs_read(GUEST_RIP) + 3); 2124 return VMX_TEST_RESUME; 2125 case 2: 2126 report_fail("RDPID triggers #UD"); 2127 break; 2128 } 2129 break; 2130 2131 default: 2132 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 2133 print_vmexit_info(exit_reason); 2134 } 2135 return VMX_TEST_VMEXIT; 2136 } 2137 2138 static void exit_monitor_from_l2_main(void) 2139 { 2140 printf("Calling exit(0) from l2...\n"); 2141 exit(0); 2142 } 2143 2144 static int exit_monitor_from_l2_handler(union exit_reason exit_reason) 2145 { 2146 report_fail("The guest should have killed the VMM"); 2147 return VMX_TEST_EXIT; 2148 } 2149 2150 static void assert_exit_reason(u64 expected) 2151 { 2152 u64 actual = vmcs_read(EXI_REASON); 2153 2154 TEST_ASSERT_EQ_MSG(expected, actual, "Expected %s, got %s.", 2155 exit_reason_description(expected), 2156 exit_reason_description(actual)); 2157 } 2158 2159 static void skip_exit_insn(void) 2160 { 2161 u64 guest_rip = vmcs_read(GUEST_RIP); 2162 u32 insn_len = vmcs_read(EXI_INST_LEN); 2163 vmcs_write(GUEST_RIP, guest_rip + insn_len); 2164 } 2165 2166 static void skip_exit_vmcall(void) 2167 { 2168 assert_exit_reason(VMX_VMCALL); 2169 skip_exit_insn(); 2170 } 2171 2172 static void v2_null_test_guest(void) 2173 { 2174 } 2175 2176 static void v2_null_test(void) 2177 { 2178 test_set_guest(v2_null_test_guest); 2179 enter_guest(); 2180 report_pass(__func__); 2181 } 2182 2183 static void v2_multiple_entries_test_guest(void) 2184 { 2185 vmx_set_test_stage(1); 2186 vmcall(); 2187 vmx_set_test_stage(2); 2188 } 2189 2190 static void v2_multiple_entries_test(void) 2191 { 2192 test_set_guest(v2_multiple_entries_test_guest); 2193 enter_guest(); 2194 TEST_ASSERT_EQ(vmx_get_test_stage(), 1); 2195 skip_exit_vmcall(); 2196 enter_guest(); 2197 TEST_ASSERT_EQ(vmx_get_test_stage(), 2); 2198 report_pass(__func__); 2199 } 2200 2201 static int fixture_test_data = 1; 2202 2203 static void fixture_test_teardown(void *data) 2204 { 2205 *((int *) data) = 1; 2206 } 2207 2208 static void fixture_test_guest(void) 2209 { 2210 fixture_test_data++; 2211 } 2212 2213 2214 static void fixture_test_setup(void) 2215 { 2216 TEST_ASSERT_EQ_MSG(1, fixture_test_data, 2217 "fixture_test_teardown didn't run?!"); 2218 fixture_test_data = 2; 2219 test_add_teardown(fixture_test_teardown, &fixture_test_data); 2220 test_set_guest(fixture_test_guest); 2221 } 2222 2223 static void fixture_test_case1(void) 2224 { 2225 fixture_test_setup(); 2226 TEST_ASSERT_EQ(2, fixture_test_data); 2227 enter_guest(); 2228 TEST_ASSERT_EQ(3, fixture_test_data); 2229 report_pass(__func__); 2230 } 2231 2232 static void fixture_test_case2(void) 2233 { 2234 fixture_test_setup(); 2235 TEST_ASSERT_EQ(2, fixture_test_data); 2236 enter_guest(); 2237 TEST_ASSERT_EQ(3, fixture_test_data); 2238 report_pass(__func__); 2239 } 2240 2241 enum ept_access_op { 2242 OP_READ, 2243 OP_WRITE, 2244 OP_EXEC, 2245 OP_FLUSH_TLB, 2246 OP_EXIT, 2247 }; 2248 2249 static struct ept_access_test_data { 2250 unsigned long gpa; 2251 unsigned long *gva; 2252 unsigned long hpa; 2253 unsigned long *hva; 2254 enum ept_access_op op; 2255 } ept_access_test_data; 2256 2257 extern unsigned char ret42_start; 2258 extern unsigned char ret42_end; 2259 2260 /* Returns 42. */ 2261 asm( 2262 ".align 64\n" 2263 "ret42_start:\n" 2264 "mov $42, %eax\n" 2265 "ret\n" 2266 "ret42_end:\n" 2267 ); 2268 2269 static void 2270 diagnose_ept_violation_qual(u64 expected, u64 actual) 2271 { 2272 2273 #define DIAGNOSE(flag) \ 2274 do { \ 2275 if ((expected & flag) != (actual & flag)) \ 2276 printf(#flag " %sexpected\n", \ 2277 (expected & flag) ? "" : "un"); \ 2278 } while (0) 2279 2280 DIAGNOSE(EPT_VLT_RD); 2281 DIAGNOSE(EPT_VLT_WR); 2282 DIAGNOSE(EPT_VLT_FETCH); 2283 DIAGNOSE(EPT_VLT_PERM_RD); 2284 DIAGNOSE(EPT_VLT_PERM_WR); 2285 DIAGNOSE(EPT_VLT_PERM_EX); 2286 DIAGNOSE(EPT_VLT_LADDR_VLD); 2287 DIAGNOSE(EPT_VLT_PADDR); 2288 2289 #undef DIAGNOSE 2290 } 2291 2292 static void do_ept_access_op(enum ept_access_op op) 2293 { 2294 ept_access_test_data.op = op; 2295 enter_guest(); 2296 } 2297 2298 /* 2299 * Force the guest to flush its TLB (i.e., flush gva -> gpa mappings). Only 2300 * needed by tests that modify guest PTEs. 2301 */ 2302 static void ept_access_test_guest_flush_tlb(void) 2303 { 2304 do_ept_access_op(OP_FLUSH_TLB); 2305 skip_exit_vmcall(); 2306 } 2307 2308 /* 2309 * Modifies the EPT entry at @level in the mapping of @gpa. First clears the 2310 * bits in @clear then sets the bits in @set. @mkhuge transforms the entry into 2311 * a huge page. 2312 */ 2313 static unsigned long ept_twiddle(unsigned long gpa, bool mkhuge, int level, 2314 unsigned long clear, unsigned long set) 2315 { 2316 struct ept_access_test_data *data = &ept_access_test_data; 2317 unsigned long orig_pte; 2318 unsigned long pte; 2319 2320 /* Screw with the mapping at the requested level. */ 2321 TEST_ASSERT(get_ept_pte(pml4, gpa, level, &orig_pte)); 2322 pte = orig_pte; 2323 if (mkhuge) 2324 pte = (orig_pte & ~EPT_ADDR_MASK) | data->hpa | EPT_LARGE_PAGE; 2325 else 2326 pte = orig_pte; 2327 pte = (pte & ~clear) | set; 2328 set_ept_pte(pml4, gpa, level, pte); 2329 invept(INVEPT_SINGLE, eptp); 2330 2331 return orig_pte; 2332 } 2333 2334 static void ept_untwiddle(unsigned long gpa, int level, unsigned long orig_pte) 2335 { 2336 set_ept_pte(pml4, gpa, level, orig_pte); 2337 invept(INVEPT_SINGLE, eptp); 2338 } 2339 2340 static void do_ept_violation(bool leaf, enum ept_access_op op, 2341 u64 expected_qual, u64 expected_paddr) 2342 { 2343 u64 qual; 2344 2345 /* Try the access and observe the violation. */ 2346 do_ept_access_op(op); 2347 2348 assert_exit_reason(VMX_EPT_VIOLATION); 2349 2350 qual = vmcs_read(EXI_QUALIFICATION); 2351 2352 /* Mask undefined bits (which may later be defined in certain cases). */ 2353 qual &= ~(EPT_VLT_GUEST_USER | EPT_VLT_GUEST_RW | EPT_VLT_GUEST_EX | 2354 EPT_VLT_PERM_USER_EX); 2355 2356 diagnose_ept_violation_qual(expected_qual, qual); 2357 TEST_EXPECT_EQ(expected_qual, qual); 2358 2359 #if 0 2360 /* Disable for now otherwise every test will fail */ 2361 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2362 (unsigned long) ( 2363 op == OP_EXEC ? data->gva + 1 : data->gva)); 2364 #endif 2365 /* 2366 * TODO: tests that probe expected_paddr in pages other than the one at 2367 * the beginning of the 1g region. 2368 */ 2369 TEST_EXPECT_EQ(vmcs_read(INFO_PHYS_ADDR), expected_paddr); 2370 } 2371 2372 static void 2373 ept_violation_at_level_mkhuge(bool mkhuge, int level, unsigned long clear, 2374 unsigned long set, enum ept_access_op op, 2375 u64 expected_qual) 2376 { 2377 struct ept_access_test_data *data = &ept_access_test_data; 2378 unsigned long orig_pte; 2379 2380 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2381 2382 do_ept_violation(level == 1 || mkhuge, op, expected_qual, 2383 op == OP_EXEC ? data->gpa + sizeof(unsigned long) : 2384 data->gpa); 2385 2386 /* Fix the violation and resume the op loop. */ 2387 ept_untwiddle(data->gpa, level, orig_pte); 2388 enter_guest(); 2389 skip_exit_vmcall(); 2390 } 2391 2392 static void 2393 ept_violation_at_level(int level, unsigned long clear, unsigned long set, 2394 enum ept_access_op op, u64 expected_qual) 2395 { 2396 ept_violation_at_level_mkhuge(false, level, clear, set, op, 2397 expected_qual); 2398 if (ept_huge_pages_supported(level)) 2399 ept_violation_at_level_mkhuge(true, level, clear, set, op, 2400 expected_qual); 2401 } 2402 2403 static void ept_violation(unsigned long clear, unsigned long set, 2404 enum ept_access_op op, u64 expected_qual) 2405 { 2406 ept_violation_at_level(1, clear, set, op, expected_qual); 2407 ept_violation_at_level(2, clear, set, op, expected_qual); 2408 ept_violation_at_level(3, clear, set, op, expected_qual); 2409 ept_violation_at_level(4, clear, set, op, expected_qual); 2410 } 2411 2412 static void ept_access_violation(unsigned long access, enum ept_access_op op, 2413 u64 expected_qual) 2414 { 2415 ept_violation(EPT_PRESENT, access, op, 2416 expected_qual | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2417 } 2418 2419 /* 2420 * For translations that don't involve a GVA, that is physical address (paddr) 2421 * accesses, EPT violations don't set the flag EPT_VLT_PADDR. For a typical 2422 * guest memory access, the hardware does GVA -> GPA -> HPA. However, certain 2423 * translations don't involve GVAs, such as when the hardware does the guest 2424 * page table walk. For example, in translating GVA_1 -> GPA_1, the guest MMU 2425 * might try to set an A bit on a guest PTE. If the GPA_2 that the PTE resides 2426 * on isn't present in the EPT, then the EPT violation will be for GPA_2 and 2427 * the EPT_VLT_PADDR bit will be clear in the exit qualification. 2428 * 2429 * Note that paddr violations can also be triggered by loading PAE page tables 2430 * with wonky addresses. We don't test that yet. 2431 * 2432 * This function modifies the EPT entry that maps the GPA that the guest page 2433 * table entry mapping ept_access_test_data.gva resides on. 2434 * 2435 * @ept_access EPT permissions to set. Other permissions are cleared. 2436 * 2437 * @pte_ad Set the A/D bits on the guest PTE accordingly. 2438 * 2439 * @op Guest operation to perform with 2440 * ept_access_test_data.gva. 2441 * 2442 * @expect_violation 2443 * Is a violation expected during the paddr access? 2444 * 2445 * @expected_qual Expected qualification for the EPT violation. 2446 * EPT_VLT_PADDR should be clear. 2447 */ 2448 static void ept_access_paddr(unsigned long ept_access, unsigned long pte_ad, 2449 enum ept_access_op op, bool expect_violation, 2450 u64 expected_qual) 2451 { 2452 struct ept_access_test_data *data = &ept_access_test_data; 2453 unsigned long *ptep; 2454 unsigned long gpa; 2455 unsigned long orig_epte; 2456 unsigned long epte; 2457 int i; 2458 2459 /* Modify the guest PTE mapping data->gva according to @pte_ad. */ 2460 ptep = get_pte_level(current_page_table(), data->gva, /*level=*/1); 2461 TEST_ASSERT(ptep); 2462 TEST_ASSERT_EQ(*ptep & PT_ADDR_MASK, data->gpa); 2463 *ptep = (*ptep & ~PT_AD_MASK) | pte_ad; 2464 ept_access_test_guest_flush_tlb(); 2465 2466 /* 2467 * Now modify the access bits on the EPT entry for the GPA that the 2468 * guest PTE resides on. Note that by modifying a single EPT entry, 2469 * we're potentially affecting 512 guest PTEs. However, we've carefully 2470 * constructed our test such that those other 511 PTEs aren't used by 2471 * the guest: data->gva is at the beginning of a 1G huge page, thus the 2472 * PTE we're modifying is at the beginning of a 4K page and the 2473 * following 511 entries are also under our control (and not touched by 2474 * the guest). 2475 */ 2476 gpa = virt_to_phys(ptep); 2477 TEST_ASSERT_EQ(gpa & ~PAGE_MASK, 0); 2478 /* 2479 * Make sure the guest page table page is mapped with a 4K EPT entry, 2480 * otherwise our level=1 twiddling below will fail. We use the 2481 * identity map (gpa = gpa) since page tables are shared with the host. 2482 */ 2483 install_ept(pml4, gpa, gpa, EPT_PRESENT); 2484 orig_epte = ept_twiddle(gpa, /*mkhuge=*/0, /*level=*/1, 2485 /*clear=*/EPT_PRESENT, /*set=*/ept_access); 2486 2487 if (expect_violation) { 2488 do_ept_violation(/*leaf=*/true, op, 2489 expected_qual | EPT_VLT_LADDR_VLD, gpa); 2490 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2491 do_ept_access_op(op); 2492 } else { 2493 do_ept_access_op(op); 2494 if (ept_ad_enabled()) { 2495 for (i = EPT_PAGE_LEVEL; i > 0; i--) { 2496 TEST_ASSERT(get_ept_pte(pml4, gpa, i, &epte)); 2497 TEST_ASSERT(epte & EPT_ACCESS_FLAG); 2498 if (i == 1) 2499 TEST_ASSERT(epte & EPT_DIRTY_FLAG); 2500 else 2501 TEST_ASSERT_EQ(epte & EPT_DIRTY_FLAG, 0); 2502 } 2503 } 2504 2505 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2506 } 2507 2508 TEST_ASSERT(*ptep & PT_ACCESSED_MASK); 2509 if ((pte_ad & PT_DIRTY_MASK) || op == OP_WRITE) 2510 TEST_ASSERT(*ptep & PT_DIRTY_MASK); 2511 2512 skip_exit_vmcall(); 2513 } 2514 2515 static void ept_access_allowed_paddr(unsigned long ept_access, 2516 unsigned long pte_ad, 2517 enum ept_access_op op) 2518 { 2519 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/false, 2520 /*expected_qual=*/-1); 2521 } 2522 2523 static void ept_access_violation_paddr(unsigned long ept_access, 2524 unsigned long pte_ad, 2525 enum ept_access_op op, 2526 u64 expected_qual) 2527 { 2528 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/true, 2529 expected_qual); 2530 } 2531 2532 2533 static void ept_allowed_at_level_mkhuge(bool mkhuge, int level, 2534 unsigned long clear, 2535 unsigned long set, 2536 enum ept_access_op op) 2537 { 2538 struct ept_access_test_data *data = &ept_access_test_data; 2539 unsigned long orig_pte; 2540 2541 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2542 2543 /* No violation. Should proceed to vmcall. */ 2544 do_ept_access_op(op); 2545 skip_exit_vmcall(); 2546 2547 ept_untwiddle(data->gpa, level, orig_pte); 2548 } 2549 2550 static void ept_allowed_at_level(int level, unsigned long clear, 2551 unsigned long set, enum ept_access_op op) 2552 { 2553 ept_allowed_at_level_mkhuge(false, level, clear, set, op); 2554 if (ept_huge_pages_supported(level)) 2555 ept_allowed_at_level_mkhuge(true, level, clear, set, op); 2556 } 2557 2558 static void ept_allowed(unsigned long clear, unsigned long set, 2559 enum ept_access_op op) 2560 { 2561 ept_allowed_at_level(1, clear, set, op); 2562 ept_allowed_at_level(2, clear, set, op); 2563 ept_allowed_at_level(3, clear, set, op); 2564 ept_allowed_at_level(4, clear, set, op); 2565 } 2566 2567 static void ept_ignored_bit(int bit) 2568 { 2569 /* Set the bit. */ 2570 ept_allowed(0, 1ul << bit, OP_READ); 2571 ept_allowed(0, 1ul << bit, OP_WRITE); 2572 ept_allowed(0, 1ul << bit, OP_EXEC); 2573 2574 /* Clear the bit. */ 2575 ept_allowed(1ul << bit, 0, OP_READ); 2576 ept_allowed(1ul << bit, 0, OP_WRITE); 2577 ept_allowed(1ul << bit, 0, OP_EXEC); 2578 } 2579 2580 static void ept_access_allowed(unsigned long access, enum ept_access_op op) 2581 { 2582 ept_allowed(EPT_PRESENT, access, op); 2583 } 2584 2585 2586 static void ept_misconfig_at_level_mkhuge_op(bool mkhuge, int level, 2587 unsigned long clear, 2588 unsigned long set, 2589 enum ept_access_op op) 2590 { 2591 struct ept_access_test_data *data = &ept_access_test_data; 2592 unsigned long orig_pte; 2593 2594 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2595 2596 do_ept_access_op(op); 2597 assert_exit_reason(VMX_EPT_MISCONFIG); 2598 2599 /* Intel 27.2.1, "For all other VM exits, this field is cleared." */ 2600 #if 0 2601 /* broken: */ 2602 TEST_EXPECT_EQ_MSG(vmcs_read(EXI_QUALIFICATION), 0); 2603 #endif 2604 #if 0 2605 /* 2606 * broken: 2607 * According to description of exit qual for EPT violation, 2608 * EPT_VLT_LADDR_VLD indicates if GUEST_LINEAR_ADDRESS is valid. 2609 * However, I can't find anything that says GUEST_LINEAR_ADDRESS ought 2610 * to be set for msiconfig. 2611 */ 2612 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2613 (unsigned long) ( 2614 op == OP_EXEC ? data->gva + 1 : data->gva)); 2615 #endif 2616 2617 /* Fix the violation and resume the op loop. */ 2618 ept_untwiddle(data->gpa, level, orig_pte); 2619 enter_guest(); 2620 skip_exit_vmcall(); 2621 } 2622 2623 static void ept_misconfig_at_level_mkhuge(bool mkhuge, int level, 2624 unsigned long clear, 2625 unsigned long set) 2626 { 2627 /* The op shouldn't matter (read, write, exec), so try them all! */ 2628 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_READ); 2629 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_WRITE); 2630 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_EXEC); 2631 } 2632 2633 static void ept_misconfig_at_level(int level, unsigned long clear, 2634 unsigned long set) 2635 { 2636 ept_misconfig_at_level_mkhuge(false, level, clear, set); 2637 if (ept_huge_pages_supported(level)) 2638 ept_misconfig_at_level_mkhuge(true, level, clear, set); 2639 } 2640 2641 static void ept_misconfig(unsigned long clear, unsigned long set) 2642 { 2643 ept_misconfig_at_level(1, clear, set); 2644 ept_misconfig_at_level(2, clear, set); 2645 ept_misconfig_at_level(3, clear, set); 2646 ept_misconfig_at_level(4, clear, set); 2647 } 2648 2649 static void ept_access_misconfig(unsigned long access) 2650 { 2651 ept_misconfig(EPT_PRESENT, access); 2652 } 2653 2654 static void ept_reserved_bit_at_level_nohuge(int level, int bit) 2655 { 2656 /* Setting the bit causes a misconfig. */ 2657 ept_misconfig_at_level_mkhuge(false, level, 0, 1ul << bit); 2658 2659 /* Making the entry non-present turns reserved bits into ignored. */ 2660 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2661 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2662 } 2663 2664 static void ept_reserved_bit_at_level_huge(int level, int bit) 2665 { 2666 /* Setting the bit causes a misconfig. */ 2667 ept_misconfig_at_level_mkhuge(true, level, 0, 1ul << bit); 2668 2669 /* Making the entry non-present turns reserved bits into ignored. */ 2670 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2671 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2672 } 2673 2674 static void ept_reserved_bit_at_level(int level, int bit) 2675 { 2676 /* Setting the bit causes a misconfig. */ 2677 ept_misconfig_at_level(level, 0, 1ul << bit); 2678 2679 /* Making the entry non-present turns reserved bits into ignored. */ 2680 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2681 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2682 } 2683 2684 static void ept_reserved_bit(int bit) 2685 { 2686 ept_reserved_bit_at_level(1, bit); 2687 ept_reserved_bit_at_level(2, bit); 2688 ept_reserved_bit_at_level(3, bit); 2689 ept_reserved_bit_at_level(4, bit); 2690 } 2691 2692 #define PAGE_2M_ORDER 9 2693 #define PAGE_1G_ORDER 18 2694 2695 static void *get_1g_page(void) 2696 { 2697 static void *alloc; 2698 2699 if (!alloc) 2700 alloc = alloc_pages(PAGE_1G_ORDER); 2701 return alloc; 2702 } 2703 2704 static void ept_access_test_teardown(void *unused) 2705 { 2706 /* Exit the guest cleanly. */ 2707 do_ept_access_op(OP_EXIT); 2708 } 2709 2710 static void ept_access_test_guest(void) 2711 { 2712 struct ept_access_test_data *data = &ept_access_test_data; 2713 int (*code)(void) = (int (*)(void)) &data->gva[1]; 2714 2715 while (true) { 2716 switch (data->op) { 2717 case OP_READ: 2718 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_1); 2719 break; 2720 case OP_WRITE: 2721 *data->gva = MAGIC_VAL_2; 2722 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_2); 2723 *data->gva = MAGIC_VAL_1; 2724 break; 2725 case OP_EXEC: 2726 TEST_ASSERT_EQ(42, code()); 2727 break; 2728 case OP_FLUSH_TLB: 2729 write_cr3(read_cr3()); 2730 break; 2731 case OP_EXIT: 2732 return; 2733 default: 2734 TEST_ASSERT_MSG(false, "Unknown op %d", data->op); 2735 } 2736 vmcall(); 2737 } 2738 } 2739 2740 static void ept_access_test_setup(void) 2741 { 2742 struct ept_access_test_data *data = &ept_access_test_data; 2743 unsigned long npages = 1ul << PAGE_1G_ORDER; 2744 unsigned long size = npages * PAGE_SIZE; 2745 unsigned long *page_table = current_page_table(); 2746 unsigned long pte; 2747 2748 if (setup_ept(false)) 2749 test_skip("EPT not supported"); 2750 2751 /* We use data->gpa = 1 << 39 so that test data has a separate pml4 entry */ 2752 if (cpuid_maxphyaddr() < 40) 2753 test_skip("Test needs MAXPHYADDR >= 40"); 2754 2755 test_set_guest(ept_access_test_guest); 2756 test_add_teardown(ept_access_test_teardown, NULL); 2757 2758 data->hva = get_1g_page(); 2759 TEST_ASSERT(data->hva); 2760 data->hpa = virt_to_phys(data->hva); 2761 2762 data->gpa = 1ul << 39; 2763 data->gva = (void *) ALIGN((unsigned long) alloc_vpages(npages * 2), 2764 size); 2765 TEST_ASSERT(!any_present_pages(page_table, data->gva, size)); 2766 install_pages(page_table, data->gpa, size, data->gva); 2767 2768 /* 2769 * Make sure nothing's mapped here so the tests that screw with the 2770 * pml4 entry don't inadvertently break something. 2771 */ 2772 TEST_ASSERT(get_ept_pte(pml4, data->gpa, 4, &pte) && pte == 0); 2773 TEST_ASSERT(get_ept_pte(pml4, data->gpa + size - 1, 4, &pte) && pte == 0); 2774 install_ept(pml4, data->hpa, data->gpa, EPT_PRESENT); 2775 2776 data->hva[0] = MAGIC_VAL_1; 2777 memcpy(&data->hva[1], &ret42_start, &ret42_end - &ret42_start); 2778 } 2779 2780 static void ept_access_test_not_present(void) 2781 { 2782 ept_access_test_setup(); 2783 /* --- */ 2784 ept_access_violation(0, OP_READ, EPT_VLT_RD); 2785 ept_access_violation(0, OP_WRITE, EPT_VLT_WR); 2786 ept_access_violation(0, OP_EXEC, EPT_VLT_FETCH); 2787 } 2788 2789 static void ept_access_test_read_only(void) 2790 { 2791 ept_access_test_setup(); 2792 2793 /* r-- */ 2794 ept_access_allowed(EPT_RA, OP_READ); 2795 ept_access_violation(EPT_RA, OP_WRITE, EPT_VLT_WR | EPT_VLT_PERM_RD); 2796 ept_access_violation(EPT_RA, OP_EXEC, EPT_VLT_FETCH | EPT_VLT_PERM_RD); 2797 } 2798 2799 static void ept_access_test_write_only(void) 2800 { 2801 ept_access_test_setup(); 2802 /* -w- */ 2803 ept_access_misconfig(EPT_WA); 2804 } 2805 2806 static void ept_access_test_read_write(void) 2807 { 2808 ept_access_test_setup(); 2809 /* rw- */ 2810 ept_access_allowed(EPT_RA | EPT_WA, OP_READ); 2811 ept_access_allowed(EPT_RA | EPT_WA, OP_WRITE); 2812 ept_access_violation(EPT_RA | EPT_WA, OP_EXEC, 2813 EPT_VLT_FETCH | EPT_VLT_PERM_RD | EPT_VLT_PERM_WR); 2814 } 2815 2816 2817 static void ept_access_test_execute_only(void) 2818 { 2819 ept_access_test_setup(); 2820 /* --x */ 2821 if (ept_execute_only_supported()) { 2822 ept_access_violation(EPT_EA, OP_READ, 2823 EPT_VLT_RD | EPT_VLT_PERM_EX); 2824 ept_access_violation(EPT_EA, OP_WRITE, 2825 EPT_VLT_WR | EPT_VLT_PERM_EX); 2826 ept_access_allowed(EPT_EA, OP_EXEC); 2827 } else { 2828 ept_access_misconfig(EPT_EA); 2829 } 2830 } 2831 2832 static void ept_access_test_read_execute(void) 2833 { 2834 ept_access_test_setup(); 2835 /* r-x */ 2836 ept_access_allowed(EPT_RA | EPT_EA, OP_READ); 2837 ept_access_violation(EPT_RA | EPT_EA, OP_WRITE, 2838 EPT_VLT_WR | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX); 2839 ept_access_allowed(EPT_RA | EPT_EA, OP_EXEC); 2840 } 2841 2842 static void ept_access_test_write_execute(void) 2843 { 2844 ept_access_test_setup(); 2845 /* -wx */ 2846 ept_access_misconfig(EPT_WA | EPT_EA); 2847 } 2848 2849 static void ept_access_test_read_write_execute(void) 2850 { 2851 ept_access_test_setup(); 2852 /* rwx */ 2853 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_READ); 2854 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_WRITE); 2855 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_EXEC); 2856 } 2857 2858 static void ept_access_test_reserved_bits(void) 2859 { 2860 int i; 2861 int maxphyaddr; 2862 2863 ept_access_test_setup(); 2864 2865 /* Reserved bits above maxphyaddr. */ 2866 maxphyaddr = cpuid_maxphyaddr(); 2867 for (i = maxphyaddr; i <= 51; i++) { 2868 report_prefix_pushf("reserved_bit=%d", i); 2869 ept_reserved_bit(i); 2870 report_prefix_pop(); 2871 } 2872 2873 /* Level-specific reserved bits. */ 2874 ept_reserved_bit_at_level_nohuge(2, 3); 2875 ept_reserved_bit_at_level_nohuge(2, 4); 2876 ept_reserved_bit_at_level_nohuge(2, 5); 2877 ept_reserved_bit_at_level_nohuge(2, 6); 2878 /* 2M alignment. */ 2879 for (i = 12; i < 20; i++) { 2880 report_prefix_pushf("reserved_bit=%d", i); 2881 ept_reserved_bit_at_level_huge(2, i); 2882 report_prefix_pop(); 2883 } 2884 ept_reserved_bit_at_level_nohuge(3, 3); 2885 ept_reserved_bit_at_level_nohuge(3, 4); 2886 ept_reserved_bit_at_level_nohuge(3, 5); 2887 ept_reserved_bit_at_level_nohuge(3, 6); 2888 /* 1G alignment. */ 2889 for (i = 12; i < 29; i++) { 2890 report_prefix_pushf("reserved_bit=%d", i); 2891 ept_reserved_bit_at_level_huge(3, i); 2892 report_prefix_pop(); 2893 } 2894 ept_reserved_bit_at_level(4, 3); 2895 ept_reserved_bit_at_level(4, 4); 2896 ept_reserved_bit_at_level(4, 5); 2897 ept_reserved_bit_at_level(4, 6); 2898 ept_reserved_bit_at_level(4, 7); 2899 } 2900 2901 static void ept_access_test_ignored_bits(void) 2902 { 2903 ept_access_test_setup(); 2904 /* 2905 * Bits ignored at every level. Bits 8 and 9 (A and D) are ignored as 2906 * far as translation is concerned even if AD bits are enabled in the 2907 * EPTP. Bit 63 is ignored because "EPT-violation #VE" VM-execution 2908 * control is 0. 2909 */ 2910 ept_ignored_bit(8); 2911 ept_ignored_bit(9); 2912 ept_ignored_bit(10); 2913 ept_ignored_bit(11); 2914 ept_ignored_bit(52); 2915 ept_ignored_bit(53); 2916 ept_ignored_bit(54); 2917 ept_ignored_bit(55); 2918 ept_ignored_bit(56); 2919 ept_ignored_bit(57); 2920 ept_ignored_bit(58); 2921 ept_ignored_bit(59); 2922 ept_ignored_bit(60); 2923 ept_ignored_bit(61); 2924 ept_ignored_bit(62); 2925 ept_ignored_bit(63); 2926 } 2927 2928 static void ept_access_test_paddr_not_present_ad_disabled(void) 2929 { 2930 ept_access_test_setup(); 2931 ept_disable_ad_bits(); 2932 2933 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, EPT_VLT_RD); 2934 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, EPT_VLT_RD); 2935 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, EPT_VLT_RD); 2936 } 2937 2938 static void ept_access_test_paddr_not_present_ad_enabled(void) 2939 { 2940 u64 qual = EPT_VLT_RD | EPT_VLT_WR; 2941 2942 ept_access_test_setup(); 2943 ept_enable_ad_bits_or_skip_test(); 2944 2945 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, qual); 2946 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, qual); 2947 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, qual); 2948 } 2949 2950 static void ept_access_test_paddr_read_only_ad_disabled(void) 2951 { 2952 /* 2953 * When EPT AD bits are disabled, all accesses to guest paging 2954 * structures are reported separately as a read and (after 2955 * translation of the GPA to host physical address) a read+write 2956 * if the A/D bits have to be set. 2957 */ 2958 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 2959 2960 ept_access_test_setup(); 2961 ept_disable_ad_bits(); 2962 2963 /* Can't update A bit, so all accesses fail. */ 2964 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 2965 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 2966 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 2967 /* AD bits disabled, so only writes try to update the D bit. */ 2968 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ); 2969 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 2970 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC); 2971 /* Both A and D already set, so read-only is OK. */ 2972 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_READ); 2973 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_WRITE); 2974 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_EXEC); 2975 } 2976 2977 static void ept_access_test_paddr_read_only_ad_enabled(void) 2978 { 2979 /* 2980 * When EPT AD bits are enabled, all accesses to guest paging 2981 * structures are considered writes as far as EPT translation 2982 * is concerned. 2983 */ 2984 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 2985 2986 ept_access_test_setup(); 2987 ept_enable_ad_bits_or_skip_test(); 2988 2989 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 2990 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 2991 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 2992 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ, qual); 2993 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 2994 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC, qual); 2995 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_READ, qual); 2996 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_WRITE, qual); 2997 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_EXEC, qual); 2998 } 2999 3000 static void ept_access_test_paddr_read_write(void) 3001 { 3002 ept_access_test_setup(); 3003 /* Read-write access to paging structure. */ 3004 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_READ); 3005 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_WRITE); 3006 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_EXEC); 3007 } 3008 3009 static void ept_access_test_paddr_read_write_execute(void) 3010 { 3011 ept_access_test_setup(); 3012 /* RWX access to paging structure. */ 3013 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_READ); 3014 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_WRITE); 3015 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_EXEC); 3016 } 3017 3018 static void ept_access_test_paddr_read_execute_ad_disabled(void) 3019 { 3020 /* 3021 * When EPT AD bits are disabled, all accesses to guest paging 3022 * structures are reported separately as a read and (after 3023 * translation of the GPA to host physical address) a read+write 3024 * if the A/D bits have to be set. 3025 */ 3026 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3027 3028 ept_access_test_setup(); 3029 ept_disable_ad_bits(); 3030 3031 /* Can't update A bit, so all accesses fail. */ 3032 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3033 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3034 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3035 /* AD bits disabled, so only writes try to update the D bit. */ 3036 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ); 3037 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3038 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC); 3039 /* Both A and D already set, so read-only is OK. */ 3040 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ); 3041 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE); 3042 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC); 3043 } 3044 3045 static void ept_access_test_paddr_read_execute_ad_enabled(void) 3046 { 3047 /* 3048 * When EPT AD bits are enabled, all accesses to guest paging 3049 * structures are considered writes as far as EPT translation 3050 * is concerned. 3051 */ 3052 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3053 3054 ept_access_test_setup(); 3055 ept_enable_ad_bits_or_skip_test(); 3056 3057 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3058 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3059 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3060 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ, qual); 3061 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3062 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC, qual); 3063 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ, qual); 3064 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE, qual); 3065 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC, qual); 3066 } 3067 3068 static void ept_access_test_paddr_not_present_page_fault(void) 3069 { 3070 ept_access_test_setup(); 3071 /* 3072 * TODO: test no EPT violation as long as guest PF occurs. e.g., GPA is 3073 * page is read-only in EPT but GVA is also mapped read only in PT. 3074 * Thus guest page fault before host takes EPT violation for trying to 3075 * update A bit. 3076 */ 3077 } 3078 3079 static void ept_access_test_force_2m_page(void) 3080 { 3081 ept_access_test_setup(); 3082 3083 TEST_ASSERT_EQ(ept_2m_supported(), true); 3084 ept_allowed_at_level_mkhuge(true, 2, 0, 0, OP_READ); 3085 ept_violation_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_RA, OP_WRITE, 3086 EPT_VLT_WR | EPT_VLT_PERM_RD | 3087 EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 3088 ept_misconfig_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_WA); 3089 } 3090 3091 static bool invvpid_valid(u64 type, u64 vpid, u64 gla) 3092 { 3093 if (!is_invvpid_type_supported(type)) 3094 return false; 3095 3096 if (vpid >> 16) 3097 return false; 3098 3099 if (type != INVVPID_ALL && !vpid) 3100 return false; 3101 3102 if (type == INVVPID_ADDR && !is_canonical(gla)) 3103 return false; 3104 3105 return true; 3106 } 3107 3108 static void try_invvpid(u64 type, u64 vpid, u64 gla) 3109 { 3110 int rc; 3111 bool valid = invvpid_valid(type, vpid, gla); 3112 u64 expected = valid ? VMXERR_UNSUPPORTED_VMCS_COMPONENT 3113 : VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID; 3114 /* 3115 * Set VMX_INST_ERROR to VMXERR_UNVALID_VMCS_COMPONENT, so 3116 * that we can tell if it is updated by INVVPID. 3117 */ 3118 vmcs_read(~0); 3119 rc = __invvpid(type, vpid, gla); 3120 report(!rc == valid, "INVVPID type %ld VPID %lx GLA %lx %s", type, 3121 vpid, gla, 3122 valid ? "passes" : "fails"); 3123 report(vmcs_read(VMX_INST_ERROR) == expected, 3124 "After %s INVVPID, VMX_INST_ERR is %ld (actual %ld)", 3125 rc ? "failed" : "successful", 3126 expected, vmcs_read(VMX_INST_ERROR)); 3127 } 3128 3129 static inline unsigned long get_first_supported_invvpid_type(void) 3130 { 3131 u64 type = ffs(ept_vpid.val >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 3132 3133 __TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 3134 return type; 3135 } 3136 3137 static void ds_invvpid(void *data) 3138 { 3139 asm volatile("invvpid %0, %1" 3140 : 3141 : "m"(*(struct invvpid_operand *)data), 3142 "r"(get_first_supported_invvpid_type())); 3143 } 3144 3145 /* 3146 * The SS override is ignored in 64-bit mode, so we use an addressing 3147 * mode with %rsp as the base register to generate an implicit SS 3148 * reference. 3149 */ 3150 static void ss_invvpid(void *data) 3151 { 3152 asm volatile("sub %%rsp,%0; invvpid (%%rsp,%0,1), %1" 3153 : "+r"(data) 3154 : "r"(get_first_supported_invvpid_type())); 3155 } 3156 3157 static void invvpid_test_gp(void) 3158 { 3159 bool fault; 3160 3161 fault = test_for_exception(GP_VECTOR, &ds_invvpid, 3162 (void *)NONCANONICAL); 3163 report(fault, "INVVPID with non-canonical DS operand raises #GP"); 3164 } 3165 3166 static void invvpid_test_ss(void) 3167 { 3168 bool fault; 3169 3170 fault = test_for_exception(SS_VECTOR, &ss_invvpid, 3171 (void *)NONCANONICAL); 3172 report(fault, "INVVPID with non-canonical SS operand raises #SS"); 3173 } 3174 3175 static void invvpid_test_pf(void) 3176 { 3177 void *vpage = alloc_vpage(); 3178 bool fault; 3179 3180 fault = test_for_exception(PF_VECTOR, &ds_invvpid, vpage); 3181 report(fault, "INVVPID with unmapped operand raises #PF"); 3182 } 3183 3184 static void try_compat_invvpid(void *unused) 3185 { 3186 struct far_pointer32 fp = { 3187 .offset = (uintptr_t)&&invvpid, 3188 .selector = KERNEL_CS32, 3189 }; 3190 uintptr_t rsp; 3191 3192 asm volatile ("mov %%rsp, %0" : "=r"(rsp)); 3193 3194 TEST_ASSERT_MSG(fp.offset == (uintptr_t)&&invvpid, 3195 "Code address too high."); 3196 TEST_ASSERT_MSG(rsp == (u32)rsp, "Stack address too high."); 3197 3198 asm goto ("lcall *%0" : : "m" (fp) : "rax" : invvpid); 3199 return; 3200 invvpid: 3201 asm volatile (".code32;" 3202 "invvpid (%eax), %eax;" 3203 "lret;" 3204 ".code64"); 3205 __builtin_unreachable(); 3206 } 3207 3208 static void invvpid_test_compatibility_mode(void) 3209 { 3210 bool fault; 3211 3212 fault = test_for_exception(UD_VECTOR, &try_compat_invvpid, NULL); 3213 report(fault, "Compatibility mode INVVPID raises #UD"); 3214 } 3215 3216 static void invvpid_test_not_in_vmx_operation(void) 3217 { 3218 bool fault; 3219 3220 TEST_ASSERT(!vmx_off()); 3221 fault = test_for_exception(UD_VECTOR, &ds_invvpid, NULL); 3222 report(fault, "INVVPID outside of VMX operation raises #UD"); 3223 TEST_ASSERT(!vmx_on()); 3224 } 3225 3226 /* 3227 * This does not test real-address mode, virtual-8086 mode, protected mode, 3228 * or CPL > 0. 3229 */ 3230 static void invvpid_test(void) 3231 { 3232 int i; 3233 unsigned types = 0; 3234 unsigned type; 3235 3236 if (!is_vpid_supported()) 3237 test_skip("VPID not supported"); 3238 3239 if (!is_invvpid_supported()) 3240 test_skip("INVVPID not supported.\n"); 3241 3242 if (is_invvpid_type_supported(INVVPID_ADDR)) 3243 types |= 1u << INVVPID_ADDR; 3244 if (is_invvpid_type_supported(INVVPID_CONTEXT_GLOBAL)) 3245 types |= 1u << INVVPID_CONTEXT_GLOBAL; 3246 if (is_invvpid_type_supported(INVVPID_ALL)) 3247 types |= 1u << INVVPID_ALL; 3248 if (is_invvpid_type_supported(INVVPID_CONTEXT_LOCAL)) 3249 types |= 1u << INVVPID_CONTEXT_LOCAL; 3250 3251 if (!types) 3252 test_skip("No INVVPID types supported.\n"); 3253 3254 for (i = -127; i < 128; i++) 3255 try_invvpid(i, 0xffff, 0); 3256 3257 /* 3258 * VPID must not be more than 16 bits. 3259 */ 3260 for (i = 0; i < 64; i++) 3261 for (type = 0; type < 4; type++) 3262 if (types & (1u << type)) 3263 try_invvpid(type, 1ul << i, 0); 3264 3265 /* 3266 * VPID must not be zero, except for "all contexts." 3267 */ 3268 for (type = 0; type < 4; type++) 3269 if (types & (1u << type)) 3270 try_invvpid(type, 0, 0); 3271 3272 /* 3273 * The gla operand is only validated for single-address INVVPID. 3274 */ 3275 if (types & (1u << INVVPID_ADDR)) 3276 try_invvpid(INVVPID_ADDR, 0xffff, NONCANONICAL); 3277 3278 invvpid_test_gp(); 3279 invvpid_test_ss(); 3280 invvpid_test_pf(); 3281 invvpid_test_compatibility_mode(); 3282 invvpid_test_not_in_vmx_operation(); 3283 } 3284 3285 static void test_assert_vmlaunch_inst_error(u32 expected_error) 3286 { 3287 u32 vmx_inst_err = vmcs_read(VMX_INST_ERROR); 3288 3289 report(vmx_inst_err == expected_error, 3290 "VMX inst error is %d (actual %d)", expected_error, vmx_inst_err); 3291 } 3292 3293 /* 3294 * This version is wildly unsafe and should _only_ be used to test VM-Fail 3295 * scenarios involving HOST_RIP. 3296 */ 3297 static void test_vmx_vmlaunch_must_fail(u32 expected_error) 3298 { 3299 /* Read the function name. */ 3300 TEST_ASSERT(expected_error); 3301 3302 /* 3303 * Don't bother with any prep work, if VMLAUNCH passes the VM-Fail 3304 * consistency checks and generates a VM-Exit, then the test is doomed 3305 * no matter what as it will jump to a garbage RIP. 3306 */ 3307 __asm__ __volatile__ ("vmlaunch"); 3308 test_assert_vmlaunch_inst_error(expected_error); 3309 } 3310 3311 /* 3312 * Test for early VMLAUNCH failure. Returns true if VMLAUNCH makes it 3313 * at least as far as the guest-state checks. Returns false if the 3314 * VMLAUNCH fails early and execution falls through to the next 3315 * instruction. 3316 */ 3317 static bool vmlaunch(void) 3318 { 3319 u32 exit_reason; 3320 3321 /* 3322 * Indirectly set VMX_INST_ERR to 12 ("VMREAD/VMWRITE from/to 3323 * unsupported VMCS component"). The caller can then check 3324 * to see if a failed VM-entry sets VMX_INST_ERR as expected. 3325 */ 3326 vmcs_write(~0u, 0); 3327 3328 vmcs_write(HOST_RIP, (uintptr_t)&&success); 3329 __asm__ __volatile__ goto ("vmwrite %%rsp, %0; vmlaunch" 3330 : 3331 : "r" ((u64)HOST_RSP) 3332 : "cc", "memory" 3333 : success); 3334 return false; 3335 success: 3336 exit_reason = vmcs_read(EXI_REASON); 3337 TEST_ASSERT(exit_reason == (VMX_FAIL_STATE | VMX_ENTRY_FAILURE) || 3338 exit_reason == (VMX_FAIL_MSR | VMX_ENTRY_FAILURE)); 3339 return true; 3340 } 3341 3342 /* 3343 * Try to launch the current VMCS. 3344 */ 3345 static void test_vmx_vmlaunch(u32 xerror) 3346 { 3347 bool success = vmlaunch(); 3348 3349 report(success == !xerror, "vmlaunch %s", 3350 !xerror ? "succeeds" : "fails"); 3351 if (!success && xerror) 3352 test_assert_vmlaunch_inst_error(xerror); 3353 } 3354 3355 /* 3356 * Try to launch the current VMCS, and expect one of two possible 3357 * errors (or success) codes. 3358 */ 3359 static void test_vmx_vmlaunch2(u32 xerror1, u32 xerror2) 3360 { 3361 bool success = vmlaunch(); 3362 u32 vmx_inst_err; 3363 3364 if (!xerror1 == !xerror2) 3365 report(success == !xerror1, "vmlaunch %s", 3366 !xerror1 ? "succeeds" : "fails"); 3367 3368 if (!success && (xerror1 || xerror2)) { 3369 vmx_inst_err = vmcs_read(VMX_INST_ERROR); 3370 report(vmx_inst_err == xerror1 || vmx_inst_err == xerror2, 3371 "VMX inst error is %d or %d (actual %d)", xerror1, 3372 xerror2, vmx_inst_err); 3373 } 3374 } 3375 3376 static void test_vmx_invalid_controls(void) 3377 { 3378 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_CONTROL_FIELD); 3379 } 3380 3381 static void test_vmx_valid_controls(void) 3382 { 3383 test_vmx_vmlaunch(0); 3384 } 3385 3386 /* 3387 * Test a particular value of a VM-execution control bit, if the value 3388 * is required or if the value is zero. 3389 */ 3390 static void test_rsvd_ctl_bit_value(const char *name, union vmx_ctrl_msr msr, 3391 enum Encoding encoding, unsigned bit, 3392 unsigned val) 3393 { 3394 u32 mask = 1u << bit; 3395 bool expected; 3396 u32 controls; 3397 3398 if (msr.set & mask) 3399 TEST_ASSERT(msr.clr & mask); 3400 3401 /* 3402 * We can't arbitrarily turn on a control bit, because it may 3403 * introduce dependencies on other VMCS fields. So, we only 3404 * test turning on bits that have a required setting. 3405 */ 3406 if (val && (msr.clr & mask) && !(msr.set & mask)) 3407 return; 3408 3409 report_prefix_pushf("%s %s bit %d", 3410 val ? "Set" : "Clear", name, bit); 3411 3412 controls = vmcs_read(encoding); 3413 if (val) { 3414 vmcs_write(encoding, msr.set | mask); 3415 expected = (msr.clr & mask); 3416 } else { 3417 vmcs_write(encoding, msr.set & ~mask); 3418 expected = !(msr.set & mask); 3419 } 3420 if (expected) 3421 test_vmx_valid_controls(); 3422 else 3423 test_vmx_invalid_controls(); 3424 vmcs_write(encoding, controls); 3425 report_prefix_pop(); 3426 } 3427 3428 /* 3429 * Test reserved values of a VM-execution control bit, based on the 3430 * allowed bit settings from the corresponding VMX capability MSR. 3431 */ 3432 static void test_rsvd_ctl_bit(const char *name, union vmx_ctrl_msr msr, 3433 enum Encoding encoding, unsigned bit) 3434 { 3435 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 0); 3436 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 1); 3437 } 3438 3439 /* 3440 * Reserved bits in the pin-based VM-execution controls must be set 3441 * properly. Software may consult the VMX capability MSRs to determine 3442 * the proper settings. 3443 * [Intel SDM] 3444 */ 3445 static void test_pin_based_ctls(void) 3446 { 3447 unsigned bit; 3448 3449 printf("%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PIN" : 3450 "MSR_IA32_VMX_PINBASED_CTLS", ctrl_pin_rev.val); 3451 for (bit = 0; bit < 32; bit++) 3452 test_rsvd_ctl_bit("pin-based controls", 3453 ctrl_pin_rev, PIN_CONTROLS, bit); 3454 } 3455 3456 /* 3457 * Reserved bits in the primary processor-based VM-execution controls 3458 * must be set properly. Software may consult the VMX capability MSRs 3459 * to determine the proper settings. 3460 * [Intel SDM] 3461 */ 3462 static void test_primary_processor_based_ctls(void) 3463 { 3464 unsigned bit; 3465 3466 printf("\n%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PROC" : 3467 "MSR_IA32_VMX_PROCBASED_CTLS", ctrl_cpu_rev[0].val); 3468 for (bit = 0; bit < 32; bit++) 3469 test_rsvd_ctl_bit("primary processor-based controls", 3470 ctrl_cpu_rev[0], CPU_EXEC_CTRL0, bit); 3471 } 3472 3473 /* 3474 * If the "activate secondary controls" primary processor-based 3475 * VM-execution control is 1, reserved bits in the secondary 3476 * processor-based VM-execution controls must be cleared. Software may 3477 * consult the VMX capability MSRs to determine which bits are 3478 * reserved. 3479 * If the "activate secondary controls" primary processor-based 3480 * VM-execution control is 0 (or if the processor does not support the 3481 * 1-setting of that control), no checks are performed on the 3482 * secondary processor-based VM-execution controls. 3483 * [Intel SDM] 3484 */ 3485 static void test_secondary_processor_based_ctls(void) 3486 { 3487 u32 primary; 3488 u32 secondary; 3489 unsigned bit; 3490 3491 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) 3492 return; 3493 3494 primary = vmcs_read(CPU_EXEC_CTRL0); 3495 secondary = vmcs_read(CPU_EXEC_CTRL1); 3496 3497 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3498 printf("\nMSR_IA32_VMX_PROCBASED_CTLS2: %lx\n", ctrl_cpu_rev[1].val); 3499 for (bit = 0; bit < 32; bit++) 3500 test_rsvd_ctl_bit("secondary processor-based controls", 3501 ctrl_cpu_rev[1], CPU_EXEC_CTRL1, bit); 3502 3503 /* 3504 * When the "activate secondary controls" VM-execution control 3505 * is clear, there are no checks on the secondary controls. 3506 */ 3507 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3508 vmcs_write(CPU_EXEC_CTRL1, ~0); 3509 report(vmlaunch(), 3510 "Secondary processor-based controls ignored"); 3511 vmcs_write(CPU_EXEC_CTRL1, secondary); 3512 vmcs_write(CPU_EXEC_CTRL0, primary); 3513 } 3514 3515 static void try_cr3_target_count(unsigned i, unsigned max) 3516 { 3517 report_prefix_pushf("CR3 target count 0x%x", i); 3518 vmcs_write(CR3_TARGET_COUNT, i); 3519 if (i <= max) 3520 test_vmx_valid_controls(); 3521 else 3522 test_vmx_invalid_controls(); 3523 report_prefix_pop(); 3524 } 3525 3526 /* 3527 * The CR3-target count must not be greater than 4. Future processors 3528 * may support a different number of CR3-target values. Software 3529 * should read the VMX capability MSR IA32_VMX_MISC to determine the 3530 * number of values supported. 3531 * [Intel SDM] 3532 */ 3533 static void test_cr3_targets(void) 3534 { 3535 unsigned supported_targets = (rdmsr(MSR_IA32_VMX_MISC) >> 16) & 0x1ff; 3536 u32 cr3_targets = vmcs_read(CR3_TARGET_COUNT); 3537 unsigned i; 3538 3539 printf("\nSupported CR3 targets: %d\n", supported_targets); 3540 TEST_ASSERT(supported_targets <= 256); 3541 3542 try_cr3_target_count(-1u, supported_targets); 3543 try_cr3_target_count(0x80000000, supported_targets); 3544 try_cr3_target_count(0x7fffffff, supported_targets); 3545 for (i = 0; i <= supported_targets + 1; i++) 3546 try_cr3_target_count(i, supported_targets); 3547 vmcs_write(CR3_TARGET_COUNT, cr3_targets); 3548 3549 /* VMWRITE to nonexistent target fields should fail. */ 3550 for (i = supported_targets; i < 256; i++) 3551 TEST_ASSERT(vmcs_write(CR3_TARGET_0 + i*2, 0)); 3552 } 3553 3554 /* 3555 * Test a particular address setting in the VMCS 3556 */ 3557 static void test_vmcs_addr(const char *name, 3558 enum Encoding encoding, 3559 u64 align, 3560 bool ignored, 3561 bool skip_beyond_mapped_ram, 3562 u64 addr) 3563 { 3564 report_prefix_pushf("%s = %lx", name, addr); 3565 vmcs_write(encoding, addr); 3566 if (skip_beyond_mapped_ram && 3567 addr > fwcfg_get_u64(FW_CFG_RAM_SIZE) - align && 3568 addr < (1ul << cpuid_maxphyaddr())) 3569 printf("Skipping physical address beyond mapped RAM\n"); 3570 else if (ignored || (IS_ALIGNED(addr, align) && 3571 addr < (1ul << cpuid_maxphyaddr()))) 3572 test_vmx_valid_controls(); 3573 else 3574 test_vmx_invalid_controls(); 3575 report_prefix_pop(); 3576 } 3577 3578 /* 3579 * Test interesting values for a VMCS address 3580 */ 3581 static void test_vmcs_addr_values(const char *name, 3582 enum Encoding encoding, 3583 u64 align, 3584 bool ignored, 3585 bool skip_beyond_mapped_ram, 3586 u32 bit_start, u32 bit_end) 3587 { 3588 unsigned i; 3589 u64 orig_val = vmcs_read(encoding); 3590 3591 for (i = bit_start; i <= bit_end; i++) 3592 test_vmcs_addr(name, encoding, align, ignored, 3593 skip_beyond_mapped_ram, 1ul << i); 3594 3595 test_vmcs_addr(name, encoding, align, ignored, 3596 skip_beyond_mapped_ram, PAGE_SIZE - 1); 3597 test_vmcs_addr(name, encoding, align, ignored, 3598 skip_beyond_mapped_ram, PAGE_SIZE); 3599 test_vmcs_addr(name, encoding, align, ignored, 3600 skip_beyond_mapped_ram, 3601 (1ul << cpuid_maxphyaddr()) - PAGE_SIZE); 3602 test_vmcs_addr(name, encoding, align, ignored, 3603 skip_beyond_mapped_ram, -1ul); 3604 3605 vmcs_write(encoding, orig_val); 3606 } 3607 3608 /* 3609 * Test a physical address reference in the VMCS, when the corresponding 3610 * feature is enabled and when the corresponding feature is disabled. 3611 */ 3612 static void test_vmcs_addr_reference(u32 control_bit, enum Encoding field, 3613 const char *field_name, 3614 const char *control_name, u64 align, 3615 bool skip_beyond_mapped_ram, 3616 bool control_primary) 3617 { 3618 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 3619 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 3620 u64 page_addr; 3621 3622 if (control_primary) { 3623 if (!(ctrl_cpu_rev[0].clr & control_bit)) 3624 return; 3625 } else { 3626 if (!(ctrl_cpu_rev[1].clr & control_bit)) 3627 return; 3628 } 3629 3630 page_addr = vmcs_read(field); 3631 3632 report_prefix_pushf("%s enabled", control_name); 3633 if (control_primary) { 3634 vmcs_write(CPU_EXEC_CTRL0, primary | control_bit); 3635 } else { 3636 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3637 vmcs_write(CPU_EXEC_CTRL1, secondary | control_bit); 3638 } 3639 3640 test_vmcs_addr_values(field_name, field, align, false, 3641 skip_beyond_mapped_ram, 0, 63); 3642 report_prefix_pop(); 3643 3644 report_prefix_pushf("%s disabled", control_name); 3645 if (control_primary) { 3646 vmcs_write(CPU_EXEC_CTRL0, primary & ~control_bit); 3647 } else { 3648 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3649 vmcs_write(CPU_EXEC_CTRL1, secondary & ~control_bit); 3650 } 3651 3652 test_vmcs_addr_values(field_name, field, align, true, false, 0, 63); 3653 report_prefix_pop(); 3654 3655 vmcs_write(field, page_addr); 3656 vmcs_write(CPU_EXEC_CTRL0, primary); 3657 vmcs_write(CPU_EXEC_CTRL1, secondary); 3658 } 3659 3660 /* 3661 * If the "use I/O bitmaps" VM-execution control is 1, bits 11:0 of 3662 * each I/O-bitmap address must be 0. Neither address should set any 3663 * bits beyond the processor's physical-address width. 3664 * [Intel SDM] 3665 */ 3666 static void test_io_bitmaps(void) 3667 { 3668 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_A, 3669 "I/O bitmap A", "Use I/O bitmaps", 3670 PAGE_SIZE, false, true); 3671 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_B, 3672 "I/O bitmap B", "Use I/O bitmaps", 3673 PAGE_SIZE, false, true); 3674 } 3675 3676 /* 3677 * If the "use MSR bitmaps" VM-execution control is 1, bits 11:0 of 3678 * the MSR-bitmap address must be 0. The address should not set any 3679 * bits beyond the processor's physical-address width. 3680 * [Intel SDM] 3681 */ 3682 static void test_msr_bitmap(void) 3683 { 3684 test_vmcs_addr_reference(CPU_MSR_BITMAP, MSR_BITMAP, 3685 "MSR bitmap", "Use MSR bitmaps", 3686 PAGE_SIZE, false, true); 3687 } 3688 3689 /* 3690 * If the "use TPR shadow" VM-execution control is 1, the virtual-APIC 3691 * address must satisfy the following checks: 3692 * - Bits 11:0 of the address must be 0. 3693 * - The address should not set any bits beyond the processor's 3694 * physical-address width. 3695 * [Intel SDM] 3696 */ 3697 static void test_apic_virt_addr(void) 3698 { 3699 /* 3700 * Ensure the processor will never use the virtual-APIC page, since 3701 * we will point it to invalid RAM. Otherwise KVM is puzzled about 3702 * what we're trying to achieve and fails vmentry. 3703 */ 3704 u32 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 3705 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0 | CPU_CR8_LOAD | CPU_CR8_STORE); 3706 test_vmcs_addr_reference(CPU_TPR_SHADOW, APIC_VIRT_ADDR, 3707 "virtual-APIC address", "Use TPR shadow", 3708 PAGE_SIZE, false, true); 3709 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 3710 } 3711 3712 /* 3713 * If the "virtualize APIC-accesses" VM-execution control is 1, the 3714 * APIC-access address must satisfy the following checks: 3715 * - Bits 11:0 of the address must be 0. 3716 * - The address should not set any bits beyond the processor's 3717 * physical-address width. 3718 * [Intel SDM] 3719 */ 3720 static void test_apic_access_addr(void) 3721 { 3722 void *apic_access_page = alloc_page(); 3723 3724 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_page)); 3725 3726 test_vmcs_addr_reference(CPU_VIRT_APIC_ACCESSES, APIC_ACCS_ADDR, 3727 "APIC-access address", 3728 "virtualize APIC-accesses", PAGE_SIZE, 3729 true, false); 3730 } 3731 3732 static bool set_bit_pattern(u8 mask, u32 *secondary) 3733 { 3734 u8 i; 3735 bool flag = false; 3736 u32 test_bits[3] = { 3737 CPU_VIRT_X2APIC, 3738 CPU_APIC_REG_VIRT, 3739 CPU_VINTD 3740 }; 3741 3742 for (i = 0; i < ARRAY_SIZE(test_bits); i++) { 3743 if ((mask & (1u << i)) && 3744 (ctrl_cpu_rev[1].clr & test_bits[i])) { 3745 *secondary |= test_bits[i]; 3746 flag = true; 3747 } 3748 } 3749 3750 return (flag); 3751 } 3752 3753 /* 3754 * If the "use TPR shadow" VM-execution control is 0, the following 3755 * VM-execution controls must also be 0: 3756 * - virtualize x2APIC mode 3757 * - APIC-register virtualization 3758 * - virtual-interrupt delivery 3759 * [Intel SDM] 3760 * 3761 * 2. If the "virtualize x2APIC mode" VM-execution control is 1, the 3762 * "virtualize APIC accesses" VM-execution control must be 0. 3763 * [Intel SDM] 3764 */ 3765 static void test_apic_virtual_ctls(void) 3766 { 3767 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3768 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3769 u32 primary = saved_primary; 3770 u32 secondary = saved_secondary; 3771 bool is_ctrl_valid = false; 3772 char str[10] = "disabled"; 3773 u8 i = 0, j; 3774 3775 /* 3776 * First test 3777 */ 3778 if (!((ctrl_cpu_rev[0].clr & (CPU_SECONDARY | CPU_TPR_SHADOW)) == 3779 (CPU_SECONDARY | CPU_TPR_SHADOW))) 3780 return; 3781 3782 primary |= CPU_SECONDARY; 3783 primary &= ~CPU_TPR_SHADOW; 3784 vmcs_write(CPU_EXEC_CTRL0, primary); 3785 3786 while (1) { 3787 for (j = 1; j < 8; j++) { 3788 secondary &= ~(CPU_VIRT_X2APIC | CPU_APIC_REG_VIRT | CPU_VINTD); 3789 if (primary & CPU_TPR_SHADOW) { 3790 is_ctrl_valid = true; 3791 } else { 3792 if (! set_bit_pattern(j, &secondary)) 3793 is_ctrl_valid = true; 3794 else 3795 is_ctrl_valid = false; 3796 } 3797 3798 vmcs_write(CPU_EXEC_CTRL1, secondary); 3799 report_prefix_pushf("Use TPR shadow %s, virtualize x2APIC mode %s, APIC-register virtualization %s, virtual-interrupt delivery %s", 3800 str, (secondary & CPU_VIRT_X2APIC) ? "enabled" : "disabled", (secondary & CPU_APIC_REG_VIRT) ? "enabled" : "disabled", (secondary & CPU_VINTD) ? "enabled" : "disabled"); 3801 if (is_ctrl_valid) 3802 test_vmx_valid_controls(); 3803 else 3804 test_vmx_invalid_controls(); 3805 report_prefix_pop(); 3806 } 3807 3808 if (i == 1) 3809 break; 3810 i++; 3811 3812 primary |= CPU_TPR_SHADOW; 3813 vmcs_write(CPU_EXEC_CTRL0, primary); 3814 strcpy(str, "enabled"); 3815 } 3816 3817 /* 3818 * Second test 3819 */ 3820 u32 apic_virt_ctls = (CPU_VIRT_X2APIC | CPU_VIRT_APIC_ACCESSES); 3821 3822 primary = saved_primary; 3823 secondary = saved_secondary; 3824 if (!((ctrl_cpu_rev[1].clr & apic_virt_ctls) == apic_virt_ctls)) 3825 return; 3826 3827 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3828 secondary &= ~CPU_VIRT_APIC_ACCESSES; 3829 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_X2APIC); 3830 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access disabled"); 3831 test_vmx_valid_controls(); 3832 report_prefix_pop(); 3833 3834 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_APIC_ACCESSES); 3835 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access enabled"); 3836 test_vmx_valid_controls(); 3837 report_prefix_pop(); 3838 3839 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_X2APIC); 3840 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access enabled"); 3841 test_vmx_invalid_controls(); 3842 report_prefix_pop(); 3843 3844 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_APIC_ACCESSES); 3845 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access disabled"); 3846 test_vmx_valid_controls(); 3847 report_prefix_pop(); 3848 3849 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3850 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3851 } 3852 3853 /* 3854 * If the "virtual-interrupt delivery" VM-execution control is 1, the 3855 * "external-interrupt exiting" VM-execution control must be 1. 3856 * [Intel SDM] 3857 */ 3858 static void test_virtual_intr_ctls(void) 3859 { 3860 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3861 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3862 u32 saved_pin = vmcs_read(PIN_CONTROLS); 3863 u32 primary = saved_primary; 3864 u32 secondary = saved_secondary; 3865 u32 pin = saved_pin; 3866 3867 if (!((ctrl_cpu_rev[1].clr & CPU_VINTD) && 3868 (ctrl_pin_rev.clr & PIN_EXTINT))) 3869 return; 3870 3871 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 3872 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VINTD); 3873 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 3874 report_prefix_pushf("Virtualize interrupt-delivery disabled; external-interrupt exiting disabled"); 3875 test_vmx_valid_controls(); 3876 report_prefix_pop(); 3877 3878 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VINTD); 3879 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 3880 test_vmx_invalid_controls(); 3881 report_prefix_pop(); 3882 3883 vmcs_write(PIN_CONTROLS, pin | PIN_EXTINT); 3884 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting enabled"); 3885 test_vmx_valid_controls(); 3886 report_prefix_pop(); 3887 3888 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 3889 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 3890 test_vmx_invalid_controls(); 3891 report_prefix_pop(); 3892 3893 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3894 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3895 vmcs_write(PIN_CONTROLS, saved_pin); 3896 } 3897 3898 static void test_pi_desc_addr(u64 addr, bool is_ctrl_valid) 3899 { 3900 vmcs_write(POSTED_INTR_DESC_ADDR, addr); 3901 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-descriptor-address 0x%lx", addr); 3902 if (is_ctrl_valid) 3903 test_vmx_valid_controls(); 3904 else 3905 test_vmx_invalid_controls(); 3906 report_prefix_pop(); 3907 } 3908 3909 /* 3910 * If the "process posted interrupts" VM-execution control is 1, the 3911 * following must be true: 3912 * 3913 * - The "virtual-interrupt delivery" VM-execution control is 1. 3914 * - The "acknowledge interrupt on exit" VM-exit control is 1. 3915 * - The posted-interrupt notification vector has a value in the 3916 * - range 0 - 255 (bits 15:8 are all 0). 3917 * - Bits 5:0 of the posted-interrupt descriptor address are all 0. 3918 * - The posted-interrupt descriptor address does not set any bits 3919 * beyond the processor's physical-address width. 3920 * [Intel SDM] 3921 */ 3922 static void test_posted_intr(void) 3923 { 3924 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3925 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3926 u32 saved_pin = vmcs_read(PIN_CONTROLS); 3927 u32 exit_ctl_saved = vmcs_read(EXI_CONTROLS); 3928 u32 primary = saved_primary; 3929 u32 secondary = saved_secondary; 3930 u32 pin = saved_pin; 3931 u32 exit_ctl = exit_ctl_saved; 3932 u16 vec; 3933 int i; 3934 3935 if (!((ctrl_pin_rev.clr & PIN_POST_INTR) && 3936 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 3937 (ctrl_exit_rev.clr & EXI_INTA))) 3938 return; 3939 3940 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 3941 3942 /* 3943 * Test virtual-interrupt-delivery and acknowledge-interrupt-on-exit 3944 */ 3945 pin |= PIN_POST_INTR; 3946 vmcs_write(PIN_CONTROLS, pin); 3947 secondary &= ~CPU_VINTD; 3948 vmcs_write(CPU_EXEC_CTRL1, secondary); 3949 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled"); 3950 test_vmx_invalid_controls(); 3951 report_prefix_pop(); 3952 3953 secondary |= CPU_VINTD; 3954 vmcs_write(CPU_EXEC_CTRL1, secondary); 3955 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled"); 3956 test_vmx_invalid_controls(); 3957 report_prefix_pop(); 3958 3959 exit_ctl &= ~EXI_INTA; 3960 vmcs_write(EXI_CONTROLS, exit_ctl); 3961 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit disabled"); 3962 test_vmx_invalid_controls(); 3963 report_prefix_pop(); 3964 3965 exit_ctl |= EXI_INTA; 3966 vmcs_write(EXI_CONTROLS, exit_ctl); 3967 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 3968 test_vmx_valid_controls(); 3969 report_prefix_pop(); 3970 3971 secondary &= ~CPU_VINTD; 3972 vmcs_write(CPU_EXEC_CTRL1, secondary); 3973 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled; acknowledge-interrupt-on-exit enabled"); 3974 test_vmx_invalid_controls(); 3975 report_prefix_pop(); 3976 3977 secondary |= CPU_VINTD; 3978 vmcs_write(CPU_EXEC_CTRL1, secondary); 3979 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 3980 test_vmx_valid_controls(); 3981 report_prefix_pop(); 3982 3983 /* 3984 * Test posted-interrupt notification vector 3985 */ 3986 for (i = 0; i < 8; i++) { 3987 vec = (1ul << i); 3988 vmcs_write(PINV, vec); 3989 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 3990 test_vmx_valid_controls(); 3991 report_prefix_pop(); 3992 } 3993 for (i = 8; i < 16; i++) { 3994 vec = (1ul << i); 3995 vmcs_write(PINV, vec); 3996 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 3997 test_vmx_invalid_controls(); 3998 report_prefix_pop(); 3999 } 4000 4001 vec &= ~(0xff << 8); 4002 vmcs_write(PINV, vec); 4003 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 4004 test_vmx_valid_controls(); 4005 report_prefix_pop(); 4006 4007 /* 4008 * Test posted-interrupt descriptor address 4009 */ 4010 for (i = 0; i < 6; i++) { 4011 test_pi_desc_addr(1ul << i, false); 4012 } 4013 4014 test_pi_desc_addr(0xf0, false); 4015 test_pi_desc_addr(0xff, false); 4016 test_pi_desc_addr(0x0f, false); 4017 test_pi_desc_addr(0x8000, true); 4018 test_pi_desc_addr(0x00, true); 4019 test_pi_desc_addr(0xc000, true); 4020 4021 test_vmcs_addr_values("process-posted interrupts", 4022 POSTED_INTR_DESC_ADDR, 64, 4023 false, false, 0, 63); 4024 4025 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 4026 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 4027 vmcs_write(PIN_CONTROLS, saved_pin); 4028 } 4029 4030 static void test_apic_ctls(void) 4031 { 4032 test_apic_virt_addr(); 4033 test_apic_access_addr(); 4034 test_apic_virtual_ctls(); 4035 test_virtual_intr_ctls(); 4036 test_posted_intr(); 4037 } 4038 4039 /* 4040 * If the "enable VPID" VM-execution control is 1, the value of the 4041 * of the VPID VM-execution control field must not be 0000H. 4042 * [Intel SDM] 4043 */ 4044 static void test_vpid(void) 4045 { 4046 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 4047 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 4048 u16 vpid = 0x0000; 4049 int i; 4050 4051 if (!is_vpid_supported()) { 4052 report_skip("%s : Secondary controls and/or VPID not supported", __func__); 4053 return; 4054 } 4055 4056 vmcs_write(CPU_EXEC_CTRL0, saved_primary | CPU_SECONDARY); 4057 vmcs_write(CPU_EXEC_CTRL1, saved_secondary & ~CPU_VPID); 4058 vmcs_write(VPID, vpid); 4059 report_prefix_pushf("VPID disabled; VPID value %x", vpid); 4060 test_vmx_valid_controls(); 4061 report_prefix_pop(); 4062 4063 vmcs_write(CPU_EXEC_CTRL1, saved_secondary | CPU_VPID); 4064 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 4065 test_vmx_invalid_controls(); 4066 report_prefix_pop(); 4067 4068 for (i = 0; i < 16; i++) { 4069 vpid = (short)1 << i;; 4070 vmcs_write(VPID, vpid); 4071 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 4072 test_vmx_valid_controls(); 4073 report_prefix_pop(); 4074 } 4075 4076 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 4077 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 4078 } 4079 4080 static void set_vtpr(unsigned vtpr) 4081 { 4082 *(u32 *)phys_to_virt(vmcs_read(APIC_VIRT_ADDR) + APIC_TASKPRI) = vtpr; 4083 } 4084 4085 static void try_tpr_threshold_and_vtpr(unsigned threshold, unsigned vtpr) 4086 { 4087 bool valid = true; 4088 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4089 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4090 4091 if ((primary & CPU_TPR_SHADOW) && 4092 (!(primary & CPU_SECONDARY) || 4093 !(secondary & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 4094 valid = (threshold & 0xf) <= ((vtpr >> 4) & 0xf); 4095 4096 set_vtpr(vtpr); 4097 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0x%x", 4098 threshold, (vtpr >> 4) & 0xf); 4099 if (valid) 4100 test_vmx_valid_controls(); 4101 else 4102 test_vmx_invalid_controls(); 4103 report_prefix_pop(); 4104 } 4105 4106 static void test_invalid_event_injection(void) 4107 { 4108 u32 ent_intr_info_save = vmcs_read(ENT_INTR_INFO); 4109 u32 ent_intr_error_save = vmcs_read(ENT_INTR_ERROR); 4110 u32 ent_inst_len_save = vmcs_read(ENT_INST_LEN); 4111 u32 primary_save = vmcs_read(CPU_EXEC_CTRL0); 4112 u32 secondary_save = vmcs_read(CPU_EXEC_CTRL1); 4113 u64 guest_cr0_save = vmcs_read(GUEST_CR0); 4114 u32 ent_intr_info_base = INTR_INFO_VALID_MASK; 4115 u32 ent_intr_info, ent_intr_err, ent_intr_len; 4116 u32 cnt; 4117 4118 /* Setup */ 4119 report_prefix_push("invalid event injection"); 4120 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4121 vmcs_write(ENT_INST_LEN, 0x00000001); 4122 4123 /* The field's interruption type is not set to a reserved value. */ 4124 ent_intr_info = ent_intr_info_base | INTR_TYPE_RESERVED | DE_VECTOR; 4125 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4126 "RESERVED interruption type invalid [-]", 4127 ent_intr_info); 4128 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4129 test_vmx_invalid_controls(); 4130 report_prefix_pop(); 4131 4132 ent_intr_info = ent_intr_info_base | INTR_TYPE_EXT_INTR | 4133 DE_VECTOR; 4134 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4135 "RESERVED interruption type invalid [+]", 4136 ent_intr_info); 4137 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4138 test_vmx_valid_controls(); 4139 report_prefix_pop(); 4140 4141 /* If the interruption type is other event, the vector is 0. */ 4142 ent_intr_info = ent_intr_info_base | INTR_TYPE_OTHER_EVENT | DB_VECTOR; 4143 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4144 "(OTHER EVENT && vector != 0) invalid [-]", 4145 ent_intr_info); 4146 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4147 test_vmx_invalid_controls(); 4148 report_prefix_pop(); 4149 4150 /* If the interruption type is NMI, the vector is 2 (negative case). */ 4151 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | DE_VECTOR; 4152 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4153 "(NMI && vector != 2) invalid [-]", ent_intr_info); 4154 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4155 test_vmx_invalid_controls(); 4156 report_prefix_pop(); 4157 4158 /* If the interruption type is NMI, the vector is 2 (positive case). */ 4159 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | NMI_VECTOR; 4160 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4161 "(NMI && vector == 2) valid [+]", ent_intr_info); 4162 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4163 test_vmx_valid_controls(); 4164 report_prefix_pop(); 4165 4166 /* 4167 * If the interruption type 4168 * is HW exception, the vector is at most 31. 4169 */ 4170 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 0x20; 4171 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4172 "(HW exception && vector > 31) invalid [-]", 4173 ent_intr_info); 4174 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4175 test_vmx_invalid_controls(); 4176 report_prefix_pop(); 4177 4178 /* 4179 * deliver-error-code is 1 iff either 4180 * (a) the "unrestricted guest" VM-execution control is 0 4181 * (b) CR0.PE is set. 4182 */ 4183 4184 /* Assert that unrestricted guest is disabled or unsupported */ 4185 assert(!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 4186 !(secondary_save & CPU_URG)); 4187 4188 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4189 GP_VECTOR; 4190 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4191 "error code <-> (!URG || prot_mode) [-]", 4192 ent_intr_info); 4193 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4194 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4195 test_vmx_invalid_controls(); 4196 report_prefix_pop(); 4197 4198 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4199 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4200 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4201 "error code <-> (!URG || prot_mode) [+]", 4202 ent_intr_info); 4203 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4204 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4205 test_vmx_valid_controls(); 4206 report_prefix_pop(); 4207 4208 if (enable_unrestricted_guest(false)) 4209 goto skip_unrestricted_guest; 4210 4211 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4212 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4213 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4214 "error code <-> (!URG || prot_mode) [-]", 4215 ent_intr_info); 4216 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4217 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4218 test_vmx_invalid_controls(); 4219 report_prefix_pop(); 4220 4221 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4222 GP_VECTOR; 4223 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4224 "error code <-> (!URG || prot_mode) [-]", 4225 ent_intr_info); 4226 vmcs_write(GUEST_CR0, guest_cr0_save | X86_CR0_PE); 4227 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4228 test_vmx_invalid_controls(); 4229 report_prefix_pop(); 4230 4231 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4232 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4233 4234 skip_unrestricted_guest: 4235 vmcs_write(GUEST_CR0, guest_cr0_save); 4236 4237 /* deliver-error-code is 1 iff the interruption type is HW exception */ 4238 report_prefix_push("error code <-> HW exception"); 4239 for (cnt = 0; cnt < 8; cnt++) { 4240 u32 exception_type_mask = cnt << 8; 4241 u32 deliver_error_code_mask = 4242 exception_type_mask != INTR_TYPE_HARD_EXCEPTION ? 4243 INTR_INFO_DELIVER_CODE_MASK : 0; 4244 4245 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4246 exception_type_mask | GP_VECTOR; 4247 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4248 ent_intr_info); 4249 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4250 test_vmx_invalid_controls(); 4251 report_prefix_pop(); 4252 } 4253 report_prefix_pop(); 4254 4255 /* 4256 * deliver-error-code is 1 iff the the vector 4257 * indicates an exception that would normally deliver an error code 4258 */ 4259 report_prefix_push("error code <-> vector delivers error code"); 4260 for (cnt = 0; cnt < 32; cnt++) { 4261 bool has_error_code = false; 4262 u32 deliver_error_code_mask; 4263 4264 switch (cnt) { 4265 case DF_VECTOR: 4266 case TS_VECTOR: 4267 case NP_VECTOR: 4268 case SS_VECTOR: 4269 case GP_VECTOR: 4270 case PF_VECTOR: 4271 case AC_VECTOR: 4272 has_error_code = true; 4273 case CP_VECTOR: 4274 /* Some CPUs have error code and some do not, skip */ 4275 continue; 4276 } 4277 4278 /* Negative case */ 4279 deliver_error_code_mask = has_error_code ? 4280 0 : 4281 INTR_INFO_DELIVER_CODE_MASK; 4282 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4283 INTR_TYPE_HARD_EXCEPTION | cnt; 4284 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4285 ent_intr_info); 4286 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4287 test_vmx_invalid_controls(); 4288 report_prefix_pop(); 4289 4290 /* Positive case */ 4291 deliver_error_code_mask = has_error_code ? 4292 INTR_INFO_DELIVER_CODE_MASK : 4293 0; 4294 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4295 INTR_TYPE_HARD_EXCEPTION | cnt; 4296 report_prefix_pushf("VM-entry intr info=0x%x [+]", 4297 ent_intr_info); 4298 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4299 test_vmx_valid_controls(); 4300 report_prefix_pop(); 4301 } 4302 report_prefix_pop(); 4303 4304 /* Reserved bits in the field (30:12) are 0. */ 4305 report_prefix_push("reserved bits clear"); 4306 for (cnt = 12; cnt <= 30; cnt++) { 4307 ent_intr_info = ent_intr_info_base | 4308 INTR_INFO_DELIVER_CODE_MASK | 4309 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR | 4310 (1U << cnt); 4311 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4312 ent_intr_info); 4313 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4314 test_vmx_invalid_controls(); 4315 report_prefix_pop(); 4316 } 4317 report_prefix_pop(); 4318 4319 /* 4320 * If deliver-error-code is 1 4321 * bits 31:16 of the VM-entry exception error-code field are 0. 4322 */ 4323 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4324 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4325 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4326 "VM-entry exception error code[31:16] clear", 4327 ent_intr_info); 4328 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4329 for (cnt = 16; cnt <= 31; cnt++) { 4330 ent_intr_err = 1U << cnt; 4331 report_prefix_pushf("VM-entry intr error=0x%x [-]", 4332 ent_intr_err); 4333 vmcs_write(ENT_INTR_ERROR, ent_intr_err); 4334 test_vmx_invalid_controls(); 4335 report_prefix_pop(); 4336 } 4337 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4338 report_prefix_pop(); 4339 4340 /* 4341 * If the interruption type is software interrupt, software exception, 4342 * or privileged software exception, the VM-entry instruction-length 4343 * field is in the range 0 - 15. 4344 */ 4345 4346 for (cnt = 0; cnt < 3; cnt++) { 4347 switch (cnt) { 4348 case 0: 4349 ent_intr_info = ent_intr_info_base | 4350 INTR_TYPE_SOFT_INTR; 4351 break; 4352 case 1: 4353 ent_intr_info = ent_intr_info_base | 4354 INTR_TYPE_SOFT_EXCEPTION; 4355 break; 4356 case 2: 4357 ent_intr_info = ent_intr_info_base | 4358 INTR_TYPE_PRIV_SW_EXCEPTION; 4359 break; 4360 } 4361 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4362 "VM-entry instruction-length check", 4363 ent_intr_info); 4364 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4365 4366 /* Instruction length set to -1 (0xFFFFFFFF) should fail */ 4367 ent_intr_len = -1; 4368 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4369 ent_intr_len); 4370 vmcs_write(ENT_INST_LEN, ent_intr_len); 4371 test_vmx_invalid_controls(); 4372 report_prefix_pop(); 4373 4374 /* Instruction length set to 16 should fail */ 4375 ent_intr_len = 0x00000010; 4376 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4377 ent_intr_len); 4378 vmcs_write(ENT_INST_LEN, 0x00000010); 4379 test_vmx_invalid_controls(); 4380 report_prefix_pop(); 4381 4382 report_prefix_pop(); 4383 } 4384 4385 /* Cleanup */ 4386 vmcs_write(ENT_INTR_INFO, ent_intr_info_save); 4387 vmcs_write(ENT_INTR_ERROR, ent_intr_error_save); 4388 vmcs_write(ENT_INST_LEN, ent_inst_len_save); 4389 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4390 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4391 vmcs_write(GUEST_CR0, guest_cr0_save); 4392 report_prefix_pop(); 4393 } 4394 4395 /* 4396 * Test interesting vTPR values for a given TPR threshold. 4397 */ 4398 static void test_vtpr_values(unsigned threshold) 4399 { 4400 try_tpr_threshold_and_vtpr(threshold, (threshold - 1) << 4); 4401 try_tpr_threshold_and_vtpr(threshold, threshold << 4); 4402 try_tpr_threshold_and_vtpr(threshold, (threshold + 1) << 4); 4403 } 4404 4405 static void try_tpr_threshold(unsigned threshold) 4406 { 4407 bool valid = true; 4408 4409 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4410 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4411 4412 if ((primary & CPU_TPR_SHADOW) && !((primary & CPU_SECONDARY) && 4413 (secondary & CPU_VINTD))) 4414 valid = !(threshold >> 4); 4415 4416 set_vtpr(-1); 4417 vmcs_write(TPR_THRESHOLD, threshold); 4418 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0xf", threshold); 4419 if (valid) 4420 test_vmx_valid_controls(); 4421 else 4422 test_vmx_invalid_controls(); 4423 report_prefix_pop(); 4424 4425 if (valid) 4426 test_vtpr_values(threshold); 4427 } 4428 4429 /* 4430 * Test interesting TPR threshold values. 4431 */ 4432 static void test_tpr_threshold_values(void) 4433 { 4434 unsigned i; 4435 4436 for (i = 0; i < 0x10; i++) 4437 try_tpr_threshold(i); 4438 for (i = 4; i < 32; i++) 4439 try_tpr_threshold(1u << i); 4440 try_tpr_threshold(-1u); 4441 try_tpr_threshold(0x7fffffff); 4442 } 4443 4444 /* 4445 * This test covers the following two VM entry checks: 4446 * 4447 * i) If the "use TPR shadow" VM-execution control is 1 and the 4448 * "virtual-interrupt delivery" VM-execution control is 0, bits 4449 * 31:4 of the TPR threshold VM-execution control field must 4450 be 0. 4451 * [Intel SDM] 4452 * 4453 * ii) If the "use TPR shadow" VM-execution control is 1, the 4454 * "virtual-interrupt delivery" VM-execution control is 0 4455 * and the "virtualize APIC accesses" VM-execution control 4456 * is 0, the value of bits 3:0 of the TPR threshold VM-execution 4457 * control field must not be greater than the value of bits 4458 * 7:4 of VTPR. 4459 * [Intel SDM] 4460 */ 4461 static void test_tpr_threshold(void) 4462 { 4463 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4464 u64 apic_virt_addr = vmcs_read(APIC_VIRT_ADDR); 4465 u64 threshold = vmcs_read(TPR_THRESHOLD); 4466 void *virtual_apic_page; 4467 4468 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) 4469 return; 4470 4471 virtual_apic_page = alloc_page(); 4472 memset(virtual_apic_page, 0xff, PAGE_SIZE); 4473 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 4474 4475 vmcs_write(CPU_EXEC_CTRL0, primary & ~(CPU_TPR_SHADOW | CPU_SECONDARY)); 4476 report_prefix_pushf("Use TPR shadow disabled, secondary controls disabled"); 4477 test_tpr_threshold_values(); 4478 report_prefix_pop(); 4479 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_TPR_SHADOW); 4480 report_prefix_pushf("Use TPR shadow enabled, secondary controls disabled"); 4481 test_tpr_threshold_values(); 4482 report_prefix_pop(); 4483 4484 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4485 (ctrl_cpu_rev[1].clr & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 4486 goto out; 4487 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4488 4489 if (ctrl_cpu_rev[1].clr & CPU_VINTD) { 4490 vmcs_write(CPU_EXEC_CTRL1, CPU_VINTD); 4491 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4492 test_tpr_threshold_values(); 4493 report_prefix_pop(); 4494 4495 vmcs_write(CPU_EXEC_CTRL0, 4496 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4497 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4498 test_tpr_threshold_values(); 4499 report_prefix_pop(); 4500 } 4501 4502 if (ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES) { 4503 vmcs_write(CPU_EXEC_CTRL0, 4504 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4505 vmcs_write(CPU_EXEC_CTRL1, CPU_VIRT_APIC_ACCESSES); 4506 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4507 test_tpr_threshold_values(); 4508 report_prefix_pop(); 4509 4510 vmcs_write(CPU_EXEC_CTRL0, 4511 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4512 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4513 test_tpr_threshold_values(); 4514 report_prefix_pop(); 4515 } 4516 4517 if ((ctrl_cpu_rev[1].clr & 4518 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) == 4519 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) { 4520 vmcs_write(CPU_EXEC_CTRL0, 4521 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4522 vmcs_write(CPU_EXEC_CTRL1, 4523 CPU_VINTD | CPU_VIRT_APIC_ACCESSES); 4524 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4525 test_tpr_threshold_values(); 4526 report_prefix_pop(); 4527 4528 vmcs_write(CPU_EXEC_CTRL0, 4529 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4530 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4531 test_tpr_threshold_values(); 4532 report_prefix_pop(); 4533 } 4534 4535 vmcs_write(CPU_EXEC_CTRL1, secondary); 4536 out: 4537 vmcs_write(TPR_THRESHOLD, threshold); 4538 vmcs_write(APIC_VIRT_ADDR, apic_virt_addr); 4539 vmcs_write(CPU_EXEC_CTRL0, primary); 4540 } 4541 4542 /* 4543 * This test verifies the following two vmentry checks: 4544 * 4545 * If the "NMI exiting" VM-execution control is 0, "Virtual NMIs" 4546 * VM-execution control must be 0. 4547 * [Intel SDM] 4548 * 4549 * If the "virtual NMIs" VM-execution control is 0, the "NMI-window 4550 * exiting" VM-execution control must be 0. 4551 * [Intel SDM] 4552 */ 4553 static void test_nmi_ctrls(void) 4554 { 4555 u32 pin_ctrls, cpu_ctrls0, test_pin_ctrls, test_cpu_ctrls0; 4556 4557 if ((ctrl_pin_rev.clr & (PIN_NMI | PIN_VIRT_NMI)) != 4558 (PIN_NMI | PIN_VIRT_NMI)) { 4559 report_skip("%s : NMI exiting and/or Virtual NMIs not supported", __func__); 4560 return; 4561 } 4562 4563 /* Save the controls so that we can restore them after our tests */ 4564 pin_ctrls = vmcs_read(PIN_CONTROLS); 4565 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 4566 4567 test_pin_ctrls = pin_ctrls & ~(PIN_NMI | PIN_VIRT_NMI); 4568 test_cpu_ctrls0 = cpu_ctrls0 & ~CPU_NMI_WINDOW; 4569 4570 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4571 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs disabled"); 4572 test_vmx_valid_controls(); 4573 report_prefix_pop(); 4574 4575 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_VIRT_NMI); 4576 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs enabled"); 4577 test_vmx_invalid_controls(); 4578 report_prefix_pop(); 4579 4580 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4581 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs enabled"); 4582 test_vmx_valid_controls(); 4583 report_prefix_pop(); 4584 4585 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_NMI); 4586 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs disabled"); 4587 test_vmx_valid_controls(); 4588 report_prefix_pop(); 4589 4590 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 4591 report_info("NMI-window exiting is not supported, skipping..."); 4592 goto done; 4593 } 4594 4595 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4596 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4597 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting enabled"); 4598 test_vmx_invalid_controls(); 4599 report_prefix_pop(); 4600 4601 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4602 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4603 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting disabled"); 4604 test_vmx_valid_controls(); 4605 report_prefix_pop(); 4606 4607 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4608 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4609 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting enabled"); 4610 test_vmx_valid_controls(); 4611 report_prefix_pop(); 4612 4613 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4614 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4615 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting disabled"); 4616 test_vmx_valid_controls(); 4617 report_prefix_pop(); 4618 4619 /* Restore the controls to their original values */ 4620 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 4621 done: 4622 vmcs_write(PIN_CONTROLS, pin_ctrls); 4623 } 4624 4625 static void test_eptp_ad_bit(u64 eptp, bool is_ctrl_valid) 4626 { 4627 vmcs_write(EPTP, eptp); 4628 report_prefix_pushf("Enable-EPT enabled; EPT accessed and dirty flag %s", 4629 (eptp & EPTP_AD_FLAG) ? "1": "0"); 4630 if (is_ctrl_valid) 4631 test_vmx_valid_controls(); 4632 else 4633 test_vmx_invalid_controls(); 4634 report_prefix_pop(); 4635 4636 } 4637 4638 /* 4639 * 1. If the "enable EPT" VM-execution control is 1, the "EPTP VM-execution" 4640 * control field must satisfy the following checks: 4641 * 4642 * - The EPT memory type (bits 2:0) must be a value supported by the 4643 * processor as indicated in the IA32_VMX_EPT_VPID_CAP MSR. 4644 * - Bits 5:3 (1 less than the EPT page-walk length) must indicate a 4645 * supported EPT page-walk length. 4646 * - Bit 6 (enable bit for accessed and dirty flags for EPT) must be 4647 * 0 if bit 21 of the IA32_VMX_EPT_VPID_CAP MSR is read as 0, 4648 * indicating that the processor does not support accessed and dirty 4649 * dirty flags for EPT. 4650 * - Reserved bits 11:7 and 63:N (where N is the processor's 4651 * physical-address width) must all be 0. 4652 * 4653 * 2. If the "unrestricted guest" VM-execution control is 1, the 4654 * "enable EPT" VM-execution control must also be 1. 4655 */ 4656 static void test_ept_eptp(void) 4657 { 4658 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4659 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4660 u64 eptp_saved = vmcs_read(EPTP); 4661 u32 secondary; 4662 u64 eptp; 4663 u32 i, maxphysaddr; 4664 u64 j, resv_bits_mask = 0; 4665 4666 report(is_4_level_ept_supported(), "4-level EPT support check"); 4667 4668 setup_dummy_ept(); 4669 4670 secondary = vmcs_read(CPU_EXEC_CTRL1); 4671 eptp = vmcs_read(EPTP); 4672 4673 for (i = 0; i < 8; i++) { 4674 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | i; 4675 vmcs_write(EPTP, eptp); 4676 report_prefix_pushf("Enable-EPT enabled; EPT memory type %lu", 4677 eptp & EPT_MEM_TYPE_MASK); 4678 if (is_ept_memtype_supported(i)) 4679 test_vmx_valid_controls(); 4680 else 4681 test_vmx_invalid_controls(); 4682 report_prefix_pop(); 4683 } 4684 4685 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | 6ul; 4686 4687 /* 4688 * Page walk length (bits 5:3). Note, the value in VMCS.EPTP "is 1 4689 * less than the EPT page-walk length". 4690 */ 4691 for (i = 0; i < 8; i++) { 4692 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4693 (i << EPTP_PG_WALK_LEN_SHIFT); 4694 4695 vmcs_write(EPTP, eptp); 4696 report_prefix_pushf("Enable-EPT enabled; EPT page walk length %lu", 4697 eptp & EPTP_PG_WALK_LEN_MASK); 4698 if (i == 3 || (i == 4 && is_5_level_ept_supported())) 4699 test_vmx_valid_controls(); 4700 else 4701 test_vmx_invalid_controls(); 4702 report_prefix_pop(); 4703 } 4704 4705 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4706 3ul << EPTP_PG_WALK_LEN_SHIFT; 4707 4708 /* 4709 * Accessed and dirty flag (bit 6) 4710 */ 4711 if (ept_ad_bits_supported()) { 4712 report_info("Processor supports accessed and dirty flag"); 4713 eptp &= ~EPTP_AD_FLAG; 4714 test_eptp_ad_bit(eptp, true); 4715 4716 eptp |= EPTP_AD_FLAG; 4717 test_eptp_ad_bit(eptp, true); 4718 } else { 4719 report_info("Processor does not supports accessed and dirty flag"); 4720 eptp &= ~EPTP_AD_FLAG; 4721 test_eptp_ad_bit(eptp, true); 4722 4723 eptp |= EPTP_AD_FLAG; 4724 test_eptp_ad_bit(eptp, false); 4725 } 4726 4727 /* 4728 * Reserved bits [11:7] and [63:N] 4729 */ 4730 for (i = 0; i < 32; i++) { 4731 eptp = (eptp & 4732 ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)) | 4733 (i << EPTP_RESERV_BITS_SHIFT); 4734 vmcs_write(EPTP, eptp); 4735 report_prefix_pushf("Enable-EPT enabled; reserved bits [11:7] %lu", 4736 (eptp >> EPTP_RESERV_BITS_SHIFT) & 4737 EPTP_RESERV_BITS_MASK); 4738 if (i == 0) 4739 test_vmx_valid_controls(); 4740 else 4741 test_vmx_invalid_controls(); 4742 report_prefix_pop(); 4743 } 4744 4745 eptp = (eptp & ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)); 4746 4747 maxphysaddr = cpuid_maxphyaddr(); 4748 for (i = 0; i < (63 - maxphysaddr + 1); i++) { 4749 resv_bits_mask |= 1ul << i; 4750 } 4751 4752 for (j = maxphysaddr - 1; j <= 63; j++) { 4753 eptp = (eptp & ~(resv_bits_mask << maxphysaddr)) | 4754 (j < maxphysaddr ? 0 : 1ul << j); 4755 vmcs_write(EPTP, eptp); 4756 report_prefix_pushf("Enable-EPT enabled; reserved bits [63:N] %lu", 4757 (eptp >> maxphysaddr) & resv_bits_mask); 4758 if (j < maxphysaddr) 4759 test_vmx_valid_controls(); 4760 else 4761 test_vmx_invalid_controls(); 4762 report_prefix_pop(); 4763 } 4764 4765 secondary &= ~(CPU_EPT | CPU_URG); 4766 vmcs_write(CPU_EXEC_CTRL1, secondary); 4767 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest disabled"); 4768 test_vmx_valid_controls(); 4769 report_prefix_pop(); 4770 4771 if (!(ctrl_cpu_rev[1].clr & CPU_URG)) 4772 goto skip_unrestricted_guest; 4773 4774 secondary |= CPU_URG; 4775 vmcs_write(CPU_EXEC_CTRL1, secondary); 4776 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest enabled"); 4777 test_vmx_invalid_controls(); 4778 report_prefix_pop(); 4779 4780 secondary |= CPU_EPT; 4781 setup_dummy_ept(); 4782 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest enabled"); 4783 test_vmx_valid_controls(); 4784 report_prefix_pop(); 4785 4786 skip_unrestricted_guest: 4787 secondary &= ~CPU_URG; 4788 vmcs_write(CPU_EXEC_CTRL1, secondary); 4789 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest disabled"); 4790 test_vmx_valid_controls(); 4791 report_prefix_pop(); 4792 4793 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4794 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4795 vmcs_write(EPTP, eptp_saved); 4796 } 4797 4798 /* 4799 * If the 'enable PML' VM-execution control is 1, the 'enable EPT' 4800 * VM-execution control must also be 1. In addition, the PML address 4801 * must satisfy the following checks: 4802 * 4803 * * Bits 11:0 of the address must be 0. 4804 * * The address should not set any bits beyond the processor's 4805 * physical-address width. 4806 * 4807 * [Intel SDM] 4808 */ 4809 static void test_pml(void) 4810 { 4811 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4812 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4813 u32 primary = primary_saved; 4814 u32 secondary = secondary_saved; 4815 4816 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4817 (ctrl_cpu_rev[1].clr & CPU_EPT) && (ctrl_cpu_rev[1].clr & CPU_PML))) { 4818 report_skip("%s : \"Secondary execution\" or \"enable EPT\" or \"enable PML\" control not supported", __func__); 4819 return; 4820 } 4821 4822 primary |= CPU_SECONDARY; 4823 vmcs_write(CPU_EXEC_CTRL0, primary); 4824 secondary &= ~(CPU_PML | CPU_EPT); 4825 vmcs_write(CPU_EXEC_CTRL1, secondary); 4826 report_prefix_pushf("enable-PML disabled, enable-EPT disabled"); 4827 test_vmx_valid_controls(); 4828 report_prefix_pop(); 4829 4830 secondary |= CPU_PML; 4831 vmcs_write(CPU_EXEC_CTRL1, secondary); 4832 report_prefix_pushf("enable-PML enabled, enable-EPT disabled"); 4833 test_vmx_invalid_controls(); 4834 report_prefix_pop(); 4835 4836 secondary |= CPU_EPT; 4837 setup_dummy_ept(); 4838 report_prefix_pushf("enable-PML enabled, enable-EPT enabled"); 4839 test_vmx_valid_controls(); 4840 report_prefix_pop(); 4841 4842 secondary &= ~CPU_PML; 4843 vmcs_write(CPU_EXEC_CTRL1, secondary); 4844 report_prefix_pushf("enable-PML disabled, enable EPT enabled"); 4845 test_vmx_valid_controls(); 4846 report_prefix_pop(); 4847 4848 test_vmcs_addr_reference(CPU_PML, PMLADDR, "PML address", "PML", 4849 PAGE_SIZE, false, false); 4850 4851 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4852 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4853 } 4854 4855 /* 4856 * If the "activate VMX-preemption timer" VM-execution control is 0, the 4857 * the "save VMX-preemption timer value" VM-exit control must also be 0. 4858 * 4859 * [Intel SDM] 4860 */ 4861 static void test_vmx_preemption_timer(void) 4862 { 4863 u32 saved_pin = vmcs_read(PIN_CONTROLS); 4864 u32 saved_exit = vmcs_read(EXI_CONTROLS); 4865 u32 pin = saved_pin; 4866 u32 exit = saved_exit; 4867 4868 if (!((ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) || 4869 (ctrl_pin_rev.clr & PIN_PREEMPT))) { 4870 report_skip("%s : \"Save-VMX-preemption-timer\" and/or \"Enable-VMX-preemption-timer\" control not supported", __func__); 4871 return; 4872 } 4873 4874 pin |= PIN_PREEMPT; 4875 vmcs_write(PIN_CONTROLS, pin); 4876 exit &= ~EXI_SAVE_PREEMPT; 4877 vmcs_write(EXI_CONTROLS, exit); 4878 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer disabled"); 4879 test_vmx_valid_controls(); 4880 report_prefix_pop(); 4881 4882 exit |= EXI_SAVE_PREEMPT; 4883 vmcs_write(EXI_CONTROLS, exit); 4884 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer enabled"); 4885 test_vmx_valid_controls(); 4886 report_prefix_pop(); 4887 4888 pin &= ~PIN_PREEMPT; 4889 vmcs_write(PIN_CONTROLS, pin); 4890 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer enabled"); 4891 test_vmx_invalid_controls(); 4892 report_prefix_pop(); 4893 4894 exit &= ~EXI_SAVE_PREEMPT; 4895 vmcs_write(EXI_CONTROLS, exit); 4896 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer disabled"); 4897 test_vmx_valid_controls(); 4898 report_prefix_pop(); 4899 4900 vmcs_write(PIN_CONTROLS, saved_pin); 4901 vmcs_write(EXI_CONTROLS, saved_exit); 4902 } 4903 4904 extern unsigned char test_mtf1; 4905 extern unsigned char test_mtf2; 4906 extern unsigned char test_mtf3; 4907 extern unsigned char test_mtf4; 4908 4909 static void test_mtf_guest(void) 4910 { 4911 asm ("vmcall;\n\t" 4912 "out %al, $0x80;\n\t" 4913 "test_mtf1:\n\t" 4914 "vmcall;\n\t" 4915 "out %al, $0x80;\n\t" 4916 "test_mtf2:\n\t" 4917 /* 4918 * Prepare for the 'MOV CR3' test. Attempt to induce a 4919 * general-protection fault by moving a non-canonical address into 4920 * CR3. The 'MOV CR3' instruction does not take an imm64 operand, 4921 * so we must MOV the desired value into a register first. 4922 * 4923 * MOV RAX is done before the VMCALL such that MTF is only enabled 4924 * for the instruction under test. 4925 */ 4926 "mov $0xaaaaaaaaaaaaaaaa, %rax;\n\t" 4927 "vmcall;\n\t" 4928 "mov %rax, %cr3;\n\t" 4929 "test_mtf3:\n\t" 4930 "vmcall;\n\t" 4931 /* 4932 * ICEBP/INT1 instruction. Though the instruction is now 4933 * documented, don't rely on assemblers enumerating the 4934 * instruction. Resort to hand assembly. 4935 */ 4936 ".byte 0xf1;\n\t" 4937 "vmcall;\n\t" 4938 "test_mtf4:\n\t" 4939 "mov $0, %eax;\n\t"); 4940 } 4941 4942 static void test_mtf_gp_handler(struct ex_regs *regs) 4943 { 4944 regs->rip = (unsigned long) &test_mtf3; 4945 } 4946 4947 static void test_mtf_db_handler(struct ex_regs *regs) 4948 { 4949 } 4950 4951 static void enable_mtf(void) 4952 { 4953 u32 ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 4954 4955 vmcs_write(CPU_EXEC_CTRL0, ctrl0 | CPU_MTF); 4956 } 4957 4958 static void disable_mtf(void) 4959 { 4960 u32 ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 4961 4962 vmcs_write(CPU_EXEC_CTRL0, ctrl0 & ~CPU_MTF); 4963 } 4964 4965 static void enable_tf(void) 4966 { 4967 unsigned long rflags = vmcs_read(GUEST_RFLAGS); 4968 4969 vmcs_write(GUEST_RFLAGS, rflags | X86_EFLAGS_TF); 4970 } 4971 4972 static void disable_tf(void) 4973 { 4974 unsigned long rflags = vmcs_read(GUEST_RFLAGS); 4975 4976 vmcs_write(GUEST_RFLAGS, rflags & ~X86_EFLAGS_TF); 4977 } 4978 4979 static void report_mtf(const char *insn_name, unsigned long exp_rip) 4980 { 4981 unsigned long rip = vmcs_read(GUEST_RIP); 4982 4983 assert_exit_reason(VMX_MTF); 4984 report(rip == exp_rip, "MTF VM-exit after %s. RIP: 0x%lx (expected 0x%lx)", 4985 insn_name, rip, exp_rip); 4986 } 4987 4988 static void vmx_mtf_test(void) 4989 { 4990 unsigned long pending_dbg; 4991 handler old_gp, old_db; 4992 4993 if (!(ctrl_cpu_rev[0].clr & CPU_MTF)) { 4994 report_skip("%s : \"Monitor trap flag\" exec control not supported", __func__); 4995 return; 4996 } 4997 4998 test_set_guest(test_mtf_guest); 4999 5000 /* Expect an MTF VM-exit after OUT instruction */ 5001 enter_guest(); 5002 skip_exit_vmcall(); 5003 5004 enable_mtf(); 5005 enter_guest(); 5006 report_mtf("OUT", (unsigned long) &test_mtf1); 5007 disable_mtf(); 5008 5009 /* 5010 * Concurrent #DB trap and MTF on instruction boundary. Expect MTF 5011 * VM-exit with populated 'pending debug exceptions' VMCS field. 5012 */ 5013 enter_guest(); 5014 skip_exit_vmcall(); 5015 5016 enable_mtf(); 5017 enable_tf(); 5018 5019 enter_guest(); 5020 report_mtf("OUT", (unsigned long) &test_mtf2); 5021 pending_dbg = vmcs_read(GUEST_PENDING_DEBUG); 5022 report(pending_dbg & DR6_BS, 5023 "'pending debug exceptions' field after MTF VM-exit: 0x%lx (expected 0x%lx)", 5024 pending_dbg, (unsigned long) DR6_BS); 5025 5026 disable_mtf(); 5027 disable_tf(); 5028 vmcs_write(GUEST_PENDING_DEBUG, 0); 5029 5030 /* 5031 * #GP exception takes priority over MTF. Expect MTF VM-exit with RIP 5032 * advanced to first instruction of #GP handler. 5033 */ 5034 enter_guest(); 5035 skip_exit_vmcall(); 5036 5037 old_gp = handle_exception(GP_VECTOR, test_mtf_gp_handler); 5038 5039 enable_mtf(); 5040 enter_guest(); 5041 report_mtf("MOV CR3", (unsigned long) get_idt_addr(&boot_idt[GP_VECTOR])); 5042 disable_mtf(); 5043 5044 /* 5045 * Concurrent MTF and privileged software exception (i.e. ICEBP/INT1). 5046 * MTF should follow the delivery of #DB trap, though the SDM doesn't 5047 * provide clear indication of the relative priority. 5048 */ 5049 enter_guest(); 5050 skip_exit_vmcall(); 5051 5052 handle_exception(GP_VECTOR, old_gp); 5053 old_db = handle_exception(DB_VECTOR, test_mtf_db_handler); 5054 5055 enable_mtf(); 5056 enter_guest(); 5057 report_mtf("INT1", (unsigned long) get_idt_addr(&boot_idt[DB_VECTOR])); 5058 disable_mtf(); 5059 5060 enter_guest(); 5061 skip_exit_vmcall(); 5062 handle_exception(DB_VECTOR, old_db); 5063 vmcs_write(ENT_INTR_INFO, INTR_INFO_VALID_MASK | INTR_TYPE_OTHER_EVENT); 5064 enter_guest(); 5065 report_mtf("injected MTF", (unsigned long) &test_mtf4); 5066 enter_guest(); 5067 } 5068 5069 extern char vmx_mtf_pdpte_guest_begin; 5070 extern char vmx_mtf_pdpte_guest_end; 5071 5072 asm("vmx_mtf_pdpte_guest_begin:\n\t" 5073 "mov %cr0, %rax\n\t" /* save CR0 with PG=1 */ 5074 "vmcall\n\t" /* on return from this CR0.PG=0 */ 5075 "mov %rax, %cr0\n\t" /* restore CR0.PG=1 to enter PAE mode */ 5076 "vmcall\n\t" 5077 "retq\n\t" 5078 "vmx_mtf_pdpte_guest_end:"); 5079 5080 static void vmx_mtf_pdpte_test(void) 5081 { 5082 void *test_mtf_pdpte_guest; 5083 pteval_t *pdpt; 5084 u32 guest_ar_cs; 5085 u64 guest_efer; 5086 pteval_t *pte; 5087 u64 guest_cr0; 5088 u64 guest_cr3; 5089 u64 guest_cr4; 5090 u64 ent_ctls; 5091 int i; 5092 5093 if (setup_ept(false)) 5094 return; 5095 5096 if (!(ctrl_cpu_rev[0].clr & CPU_MTF)) { 5097 report_skip("%s : \"Monitor trap flag\" exec control not supported", __func__); 5098 return; 5099 } 5100 5101 if (!(ctrl_cpu_rev[1].clr & CPU_URG)) { 5102 report_skip("%s : \"Unrestricted guest\" exec control not supported", __func__); 5103 return; 5104 } 5105 5106 vmcs_write(EXC_BITMAP, ~0); 5107 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | CPU_URG); 5108 5109 /* 5110 * Copy the guest code to an identity-mapped page. 5111 */ 5112 test_mtf_pdpte_guest = alloc_page(); 5113 memcpy(test_mtf_pdpte_guest, &vmx_mtf_pdpte_guest_begin, 5114 &vmx_mtf_pdpte_guest_end - &vmx_mtf_pdpte_guest_begin); 5115 5116 test_set_guest(test_mtf_pdpte_guest); 5117 5118 enter_guest(); 5119 skip_exit_vmcall(); 5120 5121 /* 5122 * Put the guest in non-paged 32-bit protected mode, ready to enter 5123 * PAE mode when CR0.PG is set. CR4.PAE will already have been set 5124 * when the guest started out in long mode. 5125 */ 5126 ent_ctls = vmcs_read(ENT_CONTROLS); 5127 vmcs_write(ENT_CONTROLS, ent_ctls & ~ENT_GUEST_64); 5128 5129 guest_efer = vmcs_read(GUEST_EFER); 5130 vmcs_write(GUEST_EFER, guest_efer & ~(EFER_LMA | EFER_LME)); 5131 5132 /* 5133 * Set CS access rights bits for 32-bit protected mode: 5134 * 3:0 B execute/read/accessed 5135 * 4 1 code or data 5136 * 6:5 0 descriptor privilege level 5137 * 7 1 present 5138 * 11:8 0 reserved 5139 * 12 0 available for use by system software 5140 * 13 0 64 bit mode not active 5141 * 14 1 default operation size 32-bit segment 5142 * 15 1 page granularity: segment limit in 4K units 5143 * 16 0 segment usable 5144 * 31:17 0 reserved 5145 */ 5146 guest_ar_cs = vmcs_read(GUEST_AR_CS); 5147 vmcs_write(GUEST_AR_CS, 0xc09b); 5148 5149 guest_cr0 = vmcs_read(GUEST_CR0); 5150 vmcs_write(GUEST_CR0, guest_cr0 & ~X86_CR0_PG); 5151 5152 guest_cr4 = vmcs_read(GUEST_CR4); 5153 vmcs_write(GUEST_CR4, guest_cr4 & ~X86_CR4_PCIDE); 5154 5155 guest_cr3 = vmcs_read(GUEST_CR3); 5156 5157 /* 5158 * Turn the 4-level page table into a PAE page table by following the 0th 5159 * PML4 entry to a PDPT page, and grab the first four PDPTEs from that 5160 * page. 5161 * 5162 * Why does this work? 5163 * 5164 * PAE uses 32-bit addressing which implies: 5165 * Bits 11:0 page offset 5166 * Bits 20:12 entry into 512-entry page table 5167 * Bits 29:21 entry into a 512-entry directory table 5168 * Bits 31:30 entry into the page directory pointer table. 5169 * Bits 63:32 zero 5170 * 5171 * As only 2 bits are needed to select the PDPTEs for the entire 5172 * 32-bit address space, take the first 4 PDPTEs in the level 3 page 5173 * directory pointer table. It doesn't matter which of these PDPTEs 5174 * are present because they must cover the guest code given that it 5175 * has already run successfully. 5176 * 5177 * Get a pointer to PTE for GVA=0 in the page directory pointer table 5178 */ 5179 pte = get_pte_level( 5180 (pgd_t *)phys_to_virt(guest_cr3 & ~X86_CR3_PCID_MASK), 0, 5181 PDPT_LEVEL); 5182 5183 /* 5184 * Need some memory for the 4-entry PAE page directory pointer 5185 * table. Use the end of the identity-mapped page where the guest code 5186 * is stored. There is definitely space as the guest code is only a 5187 * few bytes. 5188 */ 5189 pdpt = test_mtf_pdpte_guest + PAGE_SIZE - 4 * sizeof(pteval_t); 5190 5191 /* 5192 * Copy the first four PDPTEs into the PAE page table with reserved 5193 * bits cleared. Note that permission bits from the PML4E and PDPTE 5194 * are not propagated. 5195 */ 5196 for (i = 0; i < 4; i++) { 5197 TEST_ASSERT_EQ_MSG(0, (pte[i] & PDPTE64_RSVD_MASK), 5198 "PDPTE has invalid reserved bits"); 5199 TEST_ASSERT_EQ_MSG(0, (pte[i] & PDPTE64_PAGE_SIZE_MASK), 5200 "Cannot use 1GB super pages for PAE"); 5201 pdpt[i] = pte[i] & ~(PAE_PDPTE_RSVD_MASK); 5202 } 5203 vmcs_write(GUEST_CR3, virt_to_phys(pdpt)); 5204 5205 enable_mtf(); 5206 enter_guest(); 5207 assert_exit_reason(VMX_MTF); 5208 disable_mtf(); 5209 5210 /* 5211 * The four PDPTEs should have been loaded into the VMCS when 5212 * the guest set CR0.PG to enter PAE mode. 5213 */ 5214 for (i = 0; i < 4; i++) { 5215 u64 pdpte = vmcs_read(GUEST_PDPTE + 2 * i); 5216 5217 report(pdpte == pdpt[i], "PDPTE%d is 0x%lx (expected 0x%lx)", 5218 i, pdpte, pdpt[i]); 5219 } 5220 5221 /* 5222 * Now, try to enter the guest in PAE mode. If the PDPTEs in the 5223 * vmcs are wrong, this will fail. 5224 */ 5225 enter_guest(); 5226 skip_exit_vmcall(); 5227 5228 /* 5229 * Return guest to 64-bit mode and wrap up. 5230 */ 5231 vmcs_write(ENT_CONTROLS, ent_ctls); 5232 vmcs_write(GUEST_EFER, guest_efer); 5233 vmcs_write(GUEST_AR_CS, guest_ar_cs); 5234 vmcs_write(GUEST_CR0, guest_cr0); 5235 vmcs_write(GUEST_CR4, guest_cr4); 5236 vmcs_write(GUEST_CR3, guest_cr3); 5237 5238 enter_guest(); 5239 } 5240 5241 /* 5242 * Tests for VM-execution control fields 5243 */ 5244 static void test_vm_execution_ctls(void) 5245 { 5246 test_pin_based_ctls(); 5247 test_primary_processor_based_ctls(); 5248 test_secondary_processor_based_ctls(); 5249 test_cr3_targets(); 5250 test_io_bitmaps(); 5251 test_msr_bitmap(); 5252 test_apic_ctls(); 5253 test_tpr_threshold(); 5254 test_nmi_ctrls(); 5255 test_pml(); 5256 test_vpid(); 5257 test_ept_eptp(); 5258 test_vmx_preemption_timer(); 5259 } 5260 5261 /* 5262 * The following checks are performed for the VM-entry MSR-load address if 5263 * the VM-entry MSR-load count field is non-zero: 5264 * 5265 * - The lower 4 bits of the VM-entry MSR-load address must be 0. 5266 * The address should not set any bits beyond the processor's 5267 * physical-address width. 5268 * 5269 * - The address of the last byte in the VM-entry MSR-load area 5270 * should not set any bits beyond the processor's physical-address 5271 * width. The address of this last byte is VM-entry MSR-load address 5272 * + (MSR count * 16) - 1. (The arithmetic used for the computation 5273 * uses more bits than the processor's physical-address width.) 5274 * 5275 * 5276 * [Intel SDM] 5277 */ 5278 static void test_entry_msr_load(void) 5279 { 5280 entry_msr_load = alloc_page(); 5281 u64 tmp; 5282 u32 entry_msr_ld_cnt = 1; 5283 int i; 5284 u32 addr_len = 64; 5285 5286 vmcs_write(ENT_MSR_LD_CNT, entry_msr_ld_cnt); 5287 5288 /* Check first 4 bits of VM-entry MSR-load address */ 5289 for (i = 0; i < 4; i++) { 5290 tmp = (u64)entry_msr_load | 1ull << i; 5291 vmcs_write(ENTER_MSR_LD_ADDR, tmp); 5292 report_prefix_pushf("VM-entry MSR-load addr [4:0] %lx", 5293 tmp & 0xf); 5294 test_vmx_invalid_controls(); 5295 report_prefix_pop(); 5296 } 5297 5298 if (basic.val & (1ul << 48)) 5299 addr_len = 32; 5300 5301 test_vmcs_addr_values("VM-entry-MSR-load address", 5302 ENTER_MSR_LD_ADDR, 16, false, false, 5303 4, addr_len - 1); 5304 5305 /* 5306 * Check last byte of VM-entry MSR-load address 5307 */ 5308 entry_msr_load = (struct vmx_msr_entry *)((u64)entry_msr_load & ~0xf); 5309 5310 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 5311 i < 64; i++) { 5312 tmp = ((u64)entry_msr_load + entry_msr_ld_cnt * 16 - 1) | 5313 1ul << i; 5314 vmcs_write(ENTER_MSR_LD_ADDR, 5315 tmp - (entry_msr_ld_cnt * 16 - 1)); 5316 test_vmx_invalid_controls(); 5317 } 5318 5319 vmcs_write(ENT_MSR_LD_CNT, 2); 5320 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 5321 test_vmx_invalid_controls(); 5322 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 5323 test_vmx_valid_controls(); 5324 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 5325 test_vmx_valid_controls(); 5326 } 5327 5328 static struct vmx_state_area_test_data { 5329 u32 msr; 5330 u64 exp; 5331 bool enabled; 5332 } vmx_state_area_test_data; 5333 5334 static void guest_state_test_main(void) 5335 { 5336 u64 obs; 5337 struct vmx_state_area_test_data *data = &vmx_state_area_test_data; 5338 5339 while (1) { 5340 if (vmx_get_test_stage() == 2) 5341 break; 5342 5343 if (data->enabled) { 5344 obs = rdmsr(data->msr); 5345 report(data->exp == obs, 5346 "Guest state is 0x%lx (expected 0x%lx)", 5347 obs, data->exp); 5348 } 5349 5350 vmcall(); 5351 } 5352 5353 asm volatile("fnop"); 5354 } 5355 5356 static void test_guest_state(const char *test, bool xfail, u64 field, 5357 const char * field_name) 5358 { 5359 struct vmentry_result result; 5360 u8 abort_flags; 5361 5362 abort_flags = ABORT_ON_EARLY_VMENTRY_FAIL; 5363 if (!xfail) 5364 abort_flags = ABORT_ON_INVALID_GUEST_STATE; 5365 5366 __enter_guest(abort_flags, &result); 5367 5368 report(result.exit_reason.failed_vmentry == xfail && 5369 ((xfail && result.exit_reason.basic == VMX_FAIL_STATE) || 5370 (!xfail && result.exit_reason.basic == VMX_VMCALL)) && 5371 (!xfail || vmcs_read(EXI_QUALIFICATION) == ENTRY_FAIL_DEFAULT), 5372 "%s, %s = %lx", test, field_name, field); 5373 5374 if (!result.exit_reason.failed_vmentry) 5375 skip_exit_insn(); 5376 } 5377 5378 /* 5379 * Tests for VM-entry control fields 5380 */ 5381 static void test_vm_entry_ctls(void) 5382 { 5383 test_invalid_event_injection(); 5384 test_entry_msr_load(); 5385 } 5386 5387 /* 5388 * The following checks are performed for the VM-exit MSR-store address if 5389 * the VM-exit MSR-store count field is non-zero: 5390 * 5391 * - The lower 4 bits of the VM-exit MSR-store address must be 0. 5392 * The address should not set any bits beyond the processor's 5393 * physical-address width. 5394 * 5395 * - The address of the last byte in the VM-exit MSR-store area 5396 * should not set any bits beyond the processor's physical-address 5397 * width. The address of this last byte is VM-exit MSR-store address 5398 * + (MSR count * 16) - 1. (The arithmetic used for the computation 5399 * uses more bits than the processor's physical-address width.) 5400 * 5401 * If IA32_VMX_BASIC[48] is read as 1, neither address should set any bits 5402 * in the range 63:32. 5403 * 5404 * [Intel SDM] 5405 */ 5406 static void test_exit_msr_store(void) 5407 { 5408 exit_msr_store = alloc_page(); 5409 u64 tmp; 5410 u32 exit_msr_st_cnt = 1; 5411 int i; 5412 u32 addr_len = 64; 5413 5414 vmcs_write(EXI_MSR_ST_CNT, exit_msr_st_cnt); 5415 5416 /* Check first 4 bits of VM-exit MSR-store address */ 5417 for (i = 0; i < 4; i++) { 5418 tmp = (u64)exit_msr_store | 1ull << i; 5419 vmcs_write(EXIT_MSR_ST_ADDR, tmp); 5420 report_prefix_pushf("VM-exit MSR-store addr [4:0] %lx", 5421 tmp & 0xf); 5422 test_vmx_invalid_controls(); 5423 report_prefix_pop(); 5424 } 5425 5426 if (basic.val & (1ul << 48)) 5427 addr_len = 32; 5428 5429 test_vmcs_addr_values("VM-exit-MSR-store address", 5430 EXIT_MSR_ST_ADDR, 16, false, false, 5431 4, addr_len - 1); 5432 5433 /* 5434 * Check last byte of VM-exit MSR-store address 5435 */ 5436 exit_msr_store = (struct vmx_msr_entry *)((u64)exit_msr_store & ~0xf); 5437 5438 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 5439 i < 64; i++) { 5440 tmp = ((u64)exit_msr_store + exit_msr_st_cnt * 16 - 1) | 5441 1ul << i; 5442 vmcs_write(EXIT_MSR_ST_ADDR, 5443 tmp - (exit_msr_st_cnt * 16 - 1)); 5444 test_vmx_invalid_controls(); 5445 } 5446 5447 vmcs_write(EXI_MSR_ST_CNT, 2); 5448 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 5449 test_vmx_invalid_controls(); 5450 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 5451 test_vmx_valid_controls(); 5452 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 5453 test_vmx_valid_controls(); 5454 } 5455 5456 /* 5457 * Tests for VM-exit controls 5458 */ 5459 static void test_vm_exit_ctls(void) 5460 { 5461 test_exit_msr_store(); 5462 } 5463 5464 /* 5465 * Check that the virtual CPU checks all of the VMX controls as 5466 * documented in the Intel SDM. 5467 */ 5468 static void vmx_controls_test(void) 5469 { 5470 /* 5471 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 5472 * fail due to invalid guest state, should we make it that 5473 * far. 5474 */ 5475 vmcs_write(GUEST_RFLAGS, 0); 5476 5477 test_vm_execution_ctls(); 5478 test_vm_exit_ctls(); 5479 test_vm_entry_ctls(); 5480 } 5481 5482 struct apic_reg_virt_config { 5483 bool apic_register_virtualization; 5484 bool use_tpr_shadow; 5485 bool virtualize_apic_accesses; 5486 bool virtualize_x2apic_mode; 5487 bool activate_secondary_controls; 5488 }; 5489 5490 struct apic_reg_test { 5491 const char *name; 5492 struct apic_reg_virt_config apic_reg_virt_config; 5493 }; 5494 5495 struct apic_reg_virt_expectation { 5496 enum Reason rd_exit_reason; 5497 enum Reason wr_exit_reason; 5498 u32 val; 5499 u32 (*virt_fn)(u32); 5500 5501 /* 5502 * If false, accessing the APIC access address from L2 is treated as a 5503 * normal memory operation, rather than triggering virtualization. 5504 */ 5505 bool virtualize_apic_accesses; 5506 }; 5507 5508 static u32 apic_virt_identity(u32 val) 5509 { 5510 return val; 5511 } 5512 5513 static u32 apic_virt_nibble1(u32 val) 5514 { 5515 return val & 0xf0; 5516 } 5517 5518 static u32 apic_virt_byte3(u32 val) 5519 { 5520 return val & (0xff << 24); 5521 } 5522 5523 static bool apic_reg_virt_exit_expectation( 5524 u32 reg, struct apic_reg_virt_config *config, 5525 struct apic_reg_virt_expectation *expectation) 5526 { 5527 /* Good configs, where some L2 APIC accesses are virtualized. */ 5528 bool virtualize_apic_accesses_only = 5529 config->virtualize_apic_accesses && 5530 !config->use_tpr_shadow && 5531 !config->apic_register_virtualization && 5532 !config->virtualize_x2apic_mode && 5533 config->activate_secondary_controls; 5534 bool virtualize_apic_accesses_and_use_tpr_shadow = 5535 config->virtualize_apic_accesses && 5536 config->use_tpr_shadow && 5537 !config->apic_register_virtualization && 5538 !config->virtualize_x2apic_mode && 5539 config->activate_secondary_controls; 5540 bool apic_register_virtualization = 5541 config->virtualize_apic_accesses && 5542 config->use_tpr_shadow && 5543 config->apic_register_virtualization && 5544 !config->virtualize_x2apic_mode && 5545 config->activate_secondary_controls; 5546 5547 expectation->val = MAGIC_VAL_1; 5548 expectation->virt_fn = apic_virt_identity; 5549 expectation->virtualize_apic_accesses = 5550 config->virtualize_apic_accesses && 5551 config->activate_secondary_controls; 5552 if (virtualize_apic_accesses_only) { 5553 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5554 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5555 } else if (virtualize_apic_accesses_and_use_tpr_shadow) { 5556 switch (reg) { 5557 case APIC_TASKPRI: 5558 expectation->rd_exit_reason = VMX_VMCALL; 5559 expectation->wr_exit_reason = VMX_VMCALL; 5560 expectation->virt_fn = apic_virt_nibble1; 5561 break; 5562 default: 5563 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5564 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5565 } 5566 } else if (apic_register_virtualization) { 5567 expectation->rd_exit_reason = VMX_VMCALL; 5568 5569 switch (reg) { 5570 case APIC_ID: 5571 case APIC_EOI: 5572 case APIC_LDR: 5573 case APIC_DFR: 5574 case APIC_SPIV: 5575 case APIC_ESR: 5576 case APIC_ICR: 5577 case APIC_LVTT: 5578 case APIC_LVTTHMR: 5579 case APIC_LVTPC: 5580 case APIC_LVT0: 5581 case APIC_LVT1: 5582 case APIC_LVTERR: 5583 case APIC_TMICT: 5584 case APIC_TDCR: 5585 expectation->wr_exit_reason = VMX_APIC_WRITE; 5586 break; 5587 case APIC_LVR: 5588 case APIC_ISR ... APIC_ISR + 0x70: 5589 case APIC_TMR ... APIC_TMR + 0x70: 5590 case APIC_IRR ... APIC_IRR + 0x70: 5591 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5592 break; 5593 case APIC_TASKPRI: 5594 expectation->wr_exit_reason = VMX_VMCALL; 5595 expectation->virt_fn = apic_virt_nibble1; 5596 break; 5597 case APIC_ICR2: 5598 expectation->wr_exit_reason = VMX_VMCALL; 5599 expectation->virt_fn = apic_virt_byte3; 5600 break; 5601 default: 5602 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5603 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5604 } 5605 } else if (!expectation->virtualize_apic_accesses) { 5606 /* 5607 * No APIC registers are directly virtualized. This includes 5608 * VTPR, which can be virtualized through MOV to/from CR8 via 5609 * the use TPR shadow control, but not through directly 5610 * accessing VTPR. 5611 */ 5612 expectation->rd_exit_reason = VMX_VMCALL; 5613 expectation->wr_exit_reason = VMX_VMCALL; 5614 } else { 5615 printf("Cannot parse APIC register virtualization config:\n" 5616 "\tvirtualize_apic_accesses: %d\n" 5617 "\tuse_tpr_shadow: %d\n" 5618 "\tapic_register_virtualization: %d\n" 5619 "\tvirtualize_x2apic_mode: %d\n" 5620 "\tactivate_secondary_controls: %d\n", 5621 config->virtualize_apic_accesses, 5622 config->use_tpr_shadow, 5623 config->apic_register_virtualization, 5624 config->virtualize_x2apic_mode, 5625 config->activate_secondary_controls); 5626 5627 return false; 5628 } 5629 5630 return true; 5631 } 5632 5633 struct apic_reg_test apic_reg_tests[] = { 5634 /* Good configs, where some L2 APIC accesses are virtualized. */ 5635 { 5636 .name = "Virtualize APIC accesses", 5637 .apic_reg_virt_config = { 5638 .virtualize_apic_accesses = true, 5639 .use_tpr_shadow = false, 5640 .apic_register_virtualization = false, 5641 .virtualize_x2apic_mode = false, 5642 .activate_secondary_controls = true, 5643 }, 5644 }, 5645 { 5646 .name = "Virtualize APIC accesses + Use TPR shadow", 5647 .apic_reg_virt_config = { 5648 .virtualize_apic_accesses = true, 5649 .use_tpr_shadow = true, 5650 .apic_register_virtualization = false, 5651 .virtualize_x2apic_mode = false, 5652 .activate_secondary_controls = true, 5653 }, 5654 }, 5655 { 5656 .name = "APIC-register virtualization", 5657 .apic_reg_virt_config = { 5658 .virtualize_apic_accesses = true, 5659 .use_tpr_shadow = true, 5660 .apic_register_virtualization = true, 5661 .virtualize_x2apic_mode = false, 5662 .activate_secondary_controls = true, 5663 }, 5664 }, 5665 5666 /* 5667 * Test that the secondary processor-based VM-execution controls are 5668 * correctly ignored when "activate secondary controls" is disabled. 5669 */ 5670 { 5671 .name = "Activate secondary controls off", 5672 .apic_reg_virt_config = { 5673 .virtualize_apic_accesses = true, 5674 .use_tpr_shadow = false, 5675 .apic_register_virtualization = true, 5676 .virtualize_x2apic_mode = true, 5677 .activate_secondary_controls = false, 5678 }, 5679 }, 5680 { 5681 .name = "Activate secondary controls off + Use TPR shadow", 5682 .apic_reg_virt_config = { 5683 .virtualize_apic_accesses = true, 5684 .use_tpr_shadow = true, 5685 .apic_register_virtualization = true, 5686 .virtualize_x2apic_mode = true, 5687 .activate_secondary_controls = false, 5688 }, 5689 }, 5690 5691 /* 5692 * Test that the APIC access address is treated like an arbitrary memory 5693 * address when "virtualize APIC accesses" is disabled. 5694 */ 5695 { 5696 .name = "Virtualize APIC accesses off + Use TPR shadow", 5697 .apic_reg_virt_config = { 5698 .virtualize_apic_accesses = false, 5699 .use_tpr_shadow = true, 5700 .apic_register_virtualization = true, 5701 .virtualize_x2apic_mode = true, 5702 .activate_secondary_controls = true, 5703 }, 5704 }, 5705 5706 /* 5707 * Test that VM entry fails due to invalid controls when 5708 * "APIC-register virtualization" is enabled while "use TPR shadow" is 5709 * disabled. 5710 */ 5711 { 5712 .name = "APIC-register virtualization + Use TPR shadow off", 5713 .apic_reg_virt_config = { 5714 .virtualize_apic_accesses = true, 5715 .use_tpr_shadow = false, 5716 .apic_register_virtualization = true, 5717 .virtualize_x2apic_mode = false, 5718 .activate_secondary_controls = true, 5719 }, 5720 }, 5721 5722 /* 5723 * Test that VM entry fails due to invalid controls when 5724 * "Virtualize x2APIC mode" is enabled while "use TPR shadow" is 5725 * disabled. 5726 */ 5727 { 5728 .name = "Virtualize x2APIC mode + Use TPR shadow off", 5729 .apic_reg_virt_config = { 5730 .virtualize_apic_accesses = false, 5731 .use_tpr_shadow = false, 5732 .apic_register_virtualization = false, 5733 .virtualize_x2apic_mode = true, 5734 .activate_secondary_controls = true, 5735 }, 5736 }, 5737 { 5738 .name = "Virtualize x2APIC mode + Use TPR shadow off v2", 5739 .apic_reg_virt_config = { 5740 .virtualize_apic_accesses = false, 5741 .use_tpr_shadow = false, 5742 .apic_register_virtualization = true, 5743 .virtualize_x2apic_mode = true, 5744 .activate_secondary_controls = true, 5745 }, 5746 }, 5747 5748 /* 5749 * Test that VM entry fails due to invalid controls when 5750 * "virtualize x2APIC mode" is enabled while "virtualize APIC accesses" 5751 * is enabled. 5752 */ 5753 { 5754 .name = "Virtualize x2APIC mode + Virtualize APIC accesses", 5755 .apic_reg_virt_config = { 5756 .virtualize_apic_accesses = true, 5757 .use_tpr_shadow = true, 5758 .apic_register_virtualization = false, 5759 .virtualize_x2apic_mode = true, 5760 .activate_secondary_controls = true, 5761 }, 5762 }, 5763 { 5764 .name = "Virtualize x2APIC mode + Virtualize APIC accesses v2", 5765 .apic_reg_virt_config = { 5766 .virtualize_apic_accesses = true, 5767 .use_tpr_shadow = true, 5768 .apic_register_virtualization = true, 5769 .virtualize_x2apic_mode = true, 5770 .activate_secondary_controls = true, 5771 }, 5772 }, 5773 }; 5774 5775 enum Apic_op { 5776 APIC_OP_XAPIC_RD, 5777 APIC_OP_XAPIC_WR, 5778 TERMINATE, 5779 }; 5780 5781 static u32 vmx_xapic_read(u32 *apic_access_address, u32 reg) 5782 { 5783 return *(volatile u32 *)((uintptr_t)apic_access_address + reg); 5784 } 5785 5786 static void vmx_xapic_write(u32 *apic_access_address, u32 reg, u32 val) 5787 { 5788 *(volatile u32 *)((uintptr_t)apic_access_address + reg) = val; 5789 } 5790 5791 struct apic_reg_virt_guest_args { 5792 enum Apic_op op; 5793 u32 *apic_access_address; 5794 u32 reg; 5795 u32 val; 5796 bool check_rd; 5797 u32 (*virt_fn)(u32); 5798 } apic_reg_virt_guest_args; 5799 5800 static void apic_reg_virt_guest(void) 5801 { 5802 volatile struct apic_reg_virt_guest_args *args = 5803 &apic_reg_virt_guest_args; 5804 5805 for (;;) { 5806 enum Apic_op op = args->op; 5807 u32 *apic_access_address = args->apic_access_address; 5808 u32 reg = args->reg; 5809 u32 val = args->val; 5810 bool check_rd = args->check_rd; 5811 u32 (*virt_fn)(u32) = args->virt_fn; 5812 5813 if (op == TERMINATE) 5814 break; 5815 5816 if (op == APIC_OP_XAPIC_RD) { 5817 u32 ret = vmx_xapic_read(apic_access_address, reg); 5818 5819 if (check_rd) { 5820 u32 want = virt_fn(val); 5821 u32 got = virt_fn(ret); 5822 5823 report(got == want, 5824 "read 0x%x, expected 0x%x.", got, want); 5825 } 5826 } else if (op == APIC_OP_XAPIC_WR) { 5827 vmx_xapic_write(apic_access_address, reg, val); 5828 } 5829 5830 /* 5831 * The L1 should always execute a vmcall after it's done testing 5832 * an individual APIC operation. This helps to validate that the 5833 * L1 and L2 are in sync with each other, as expected. 5834 */ 5835 vmcall(); 5836 } 5837 } 5838 5839 static void test_xapic_rd( 5840 u32 reg, struct apic_reg_virt_expectation *expectation, 5841 u32 *apic_access_address, u32 *virtual_apic_page) 5842 { 5843 u32 val = expectation->val; 5844 u32 exit_reason_want = expectation->rd_exit_reason; 5845 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 5846 5847 report_prefix_pushf("xapic - reading 0x%03x", reg); 5848 5849 /* Configure guest to do an xapic read */ 5850 args->op = APIC_OP_XAPIC_RD; 5851 args->apic_access_address = apic_access_address; 5852 args->reg = reg; 5853 args->val = val; 5854 args->check_rd = exit_reason_want == VMX_VMCALL; 5855 args->virt_fn = expectation->virt_fn; 5856 5857 /* Setup virtual APIC page */ 5858 if (!expectation->virtualize_apic_accesses) { 5859 apic_access_address[apic_reg_index(reg)] = val; 5860 virtual_apic_page[apic_reg_index(reg)] = 0; 5861 } else if (exit_reason_want == VMX_VMCALL) { 5862 apic_access_address[apic_reg_index(reg)] = 0; 5863 virtual_apic_page[apic_reg_index(reg)] = val; 5864 } 5865 5866 /* Enter guest */ 5867 enter_guest(); 5868 5869 /* 5870 * Validate the behavior and 5871 * pass a magic value back to the guest. 5872 */ 5873 if (exit_reason_want == VMX_APIC_ACCESS) { 5874 u32 apic_page_offset = vmcs_read(EXI_QUALIFICATION) & 0xfff; 5875 5876 assert_exit_reason(exit_reason_want); 5877 report(apic_page_offset == reg, 5878 "got APIC access exit @ page offset 0x%03x, want 0x%03x", 5879 apic_page_offset, reg); 5880 skip_exit_insn(); 5881 5882 /* Reenter guest so it can consume/check rcx and exit again. */ 5883 enter_guest(); 5884 } else if (exit_reason_want != VMX_VMCALL) { 5885 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 5886 } 5887 5888 skip_exit_vmcall(); 5889 report_prefix_pop(); 5890 } 5891 5892 static void test_xapic_wr( 5893 u32 reg, struct apic_reg_virt_expectation *expectation, 5894 u32 *apic_access_address, u32 *virtual_apic_page) 5895 { 5896 u32 val = expectation->val; 5897 u32 exit_reason_want = expectation->wr_exit_reason; 5898 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 5899 bool virtualized = 5900 expectation->virtualize_apic_accesses && 5901 (exit_reason_want == VMX_APIC_WRITE || 5902 exit_reason_want == VMX_VMCALL); 5903 bool checked = false; 5904 5905 report_prefix_pushf("xapic - writing 0x%x to 0x%03x", val, reg); 5906 5907 /* Configure guest to do an xapic read */ 5908 args->op = APIC_OP_XAPIC_WR; 5909 args->apic_access_address = apic_access_address; 5910 args->reg = reg; 5911 args->val = val; 5912 5913 /* Setup virtual APIC page */ 5914 if (virtualized || !expectation->virtualize_apic_accesses) { 5915 apic_access_address[apic_reg_index(reg)] = 0; 5916 virtual_apic_page[apic_reg_index(reg)] = 0; 5917 } 5918 5919 /* Enter guest */ 5920 enter_guest(); 5921 5922 /* 5923 * Validate the behavior and 5924 * pass a magic value back to the guest. 5925 */ 5926 if (exit_reason_want == VMX_APIC_ACCESS) { 5927 u32 apic_page_offset = vmcs_read(EXI_QUALIFICATION) & 0xfff; 5928 5929 assert_exit_reason(exit_reason_want); 5930 report(apic_page_offset == reg, 5931 "got APIC access exit @ page offset 0x%03x, want 0x%03x", 5932 apic_page_offset, reg); 5933 skip_exit_insn(); 5934 5935 /* Reenter guest so it can consume/check rcx and exit again. */ 5936 enter_guest(); 5937 } else if (exit_reason_want == VMX_APIC_WRITE) { 5938 assert_exit_reason(exit_reason_want); 5939 report(virtual_apic_page[apic_reg_index(reg)] == val, 5940 "got APIC write exit @ page offset 0x%03x; val is 0x%x, want 0x%x", 5941 apic_reg_index(reg), 5942 virtual_apic_page[apic_reg_index(reg)], val); 5943 checked = true; 5944 5945 /* Reenter guest so it can consume/check rcx and exit again. */ 5946 enter_guest(); 5947 } else if (exit_reason_want != VMX_VMCALL) { 5948 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 5949 } 5950 5951 assert_exit_reason(VMX_VMCALL); 5952 if (virtualized && !checked) { 5953 u32 want = expectation->virt_fn(val); 5954 u32 got = virtual_apic_page[apic_reg_index(reg)]; 5955 got = expectation->virt_fn(got); 5956 5957 report(got == want, "exitless write; val is 0x%x, want 0x%x", 5958 got, want); 5959 } else if (!expectation->virtualize_apic_accesses && !checked) { 5960 u32 got = apic_access_address[apic_reg_index(reg)]; 5961 5962 report(got == val, 5963 "non-virtualized write; val is 0x%x, want 0x%x", got, 5964 val); 5965 } else if (!expectation->virtualize_apic_accesses && checked) { 5966 report_fail("Non-virtualized write was prematurely checked!"); 5967 } 5968 5969 skip_exit_vmcall(); 5970 report_prefix_pop(); 5971 } 5972 5973 enum Config_type { 5974 CONFIG_TYPE_GOOD, 5975 CONFIG_TYPE_UNSUPPORTED, 5976 CONFIG_TYPE_VMENTRY_FAILS_EARLY, 5977 }; 5978 5979 static enum Config_type configure_apic_reg_virt_test( 5980 struct apic_reg_virt_config *apic_reg_virt_config) 5981 { 5982 u32 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 5983 u32 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 5984 /* Configs where L2 entry fails early, due to invalid controls. */ 5985 bool use_tpr_shadow_incorrectly_off = 5986 !apic_reg_virt_config->use_tpr_shadow && 5987 (apic_reg_virt_config->apic_register_virtualization || 5988 apic_reg_virt_config->virtualize_x2apic_mode) && 5989 apic_reg_virt_config->activate_secondary_controls; 5990 bool virtualize_apic_accesses_incorrectly_on = 5991 apic_reg_virt_config->virtualize_apic_accesses && 5992 apic_reg_virt_config->virtualize_x2apic_mode && 5993 apic_reg_virt_config->activate_secondary_controls; 5994 bool vmentry_fails_early = 5995 use_tpr_shadow_incorrectly_off || 5996 virtualize_apic_accesses_incorrectly_on; 5997 5998 if (apic_reg_virt_config->activate_secondary_controls) { 5999 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 6000 printf("VM-execution control \"activate secondary controls\" NOT supported.\n"); 6001 return CONFIG_TYPE_UNSUPPORTED; 6002 } 6003 cpu_exec_ctrl0 |= CPU_SECONDARY; 6004 } else { 6005 cpu_exec_ctrl0 &= ~CPU_SECONDARY; 6006 } 6007 6008 if (apic_reg_virt_config->virtualize_apic_accesses) { 6009 if (!(ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES)) { 6010 printf("VM-execution control \"virtualize APIC accesses\" NOT supported.\n"); 6011 return CONFIG_TYPE_UNSUPPORTED; 6012 } 6013 cpu_exec_ctrl1 |= CPU_VIRT_APIC_ACCESSES; 6014 } else { 6015 cpu_exec_ctrl1 &= ~CPU_VIRT_APIC_ACCESSES; 6016 } 6017 6018 if (apic_reg_virt_config->use_tpr_shadow) { 6019 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) { 6020 printf("VM-execution control \"use TPR shadow\" NOT supported.\n"); 6021 return CONFIG_TYPE_UNSUPPORTED; 6022 } 6023 cpu_exec_ctrl0 |= CPU_TPR_SHADOW; 6024 } else { 6025 cpu_exec_ctrl0 &= ~CPU_TPR_SHADOW; 6026 } 6027 6028 if (apic_reg_virt_config->apic_register_virtualization) { 6029 if (!(ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT)) { 6030 printf("VM-execution control \"APIC-register virtualization\" NOT supported.\n"); 6031 return CONFIG_TYPE_UNSUPPORTED; 6032 } 6033 cpu_exec_ctrl1 |= CPU_APIC_REG_VIRT; 6034 } else { 6035 cpu_exec_ctrl1 &= ~CPU_APIC_REG_VIRT; 6036 } 6037 6038 if (apic_reg_virt_config->virtualize_x2apic_mode) { 6039 if (!(ctrl_cpu_rev[1].clr & CPU_VIRT_X2APIC)) { 6040 printf("VM-execution control \"virtualize x2APIC mode\" NOT supported.\n"); 6041 return CONFIG_TYPE_UNSUPPORTED; 6042 } 6043 cpu_exec_ctrl1 |= CPU_VIRT_X2APIC; 6044 } else { 6045 cpu_exec_ctrl1 &= ~CPU_VIRT_X2APIC; 6046 } 6047 6048 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6049 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6050 6051 if (vmentry_fails_early) 6052 return CONFIG_TYPE_VMENTRY_FAILS_EARLY; 6053 6054 return CONFIG_TYPE_GOOD; 6055 } 6056 6057 static bool cpu_has_apicv(void) 6058 { 6059 return ((ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT) && 6060 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 6061 (ctrl_pin_rev.clr & PIN_POST_INTR)); 6062 } 6063 6064 /* Validates APIC register access across valid virtualization configurations. */ 6065 static void apic_reg_virt_test(void) 6066 { 6067 u32 *apic_access_address; 6068 u32 *virtual_apic_page; 6069 u64 control; 6070 u64 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6071 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6072 int i; 6073 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 6074 6075 if (!cpu_has_apicv()) { 6076 report_skip("%s : Not all required APICv bits supported", __func__); 6077 return; 6078 } 6079 6080 control = cpu_exec_ctrl1; 6081 control &= ~CPU_VINTD; 6082 vmcs_write(CPU_EXEC_CTRL1, control); 6083 6084 test_set_guest(apic_reg_virt_guest); 6085 6086 /* 6087 * From the SDM: The 1-setting of the "virtualize APIC accesses" 6088 * VM-execution is guaranteed to apply only if translations to the 6089 * APIC-access address use a 4-KByte page. 6090 */ 6091 apic_access_address = alloc_page(); 6092 force_4k_page(apic_access_address); 6093 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_address)); 6094 6095 virtual_apic_page = alloc_page(); 6096 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 6097 6098 for (i = 0; i < ARRAY_SIZE(apic_reg_tests); i++) { 6099 struct apic_reg_test *apic_reg_test = &apic_reg_tests[i]; 6100 struct apic_reg_virt_config *apic_reg_virt_config = 6101 &apic_reg_test->apic_reg_virt_config; 6102 enum Config_type config_type; 6103 u32 reg; 6104 6105 printf("--- %s test ---\n", apic_reg_test->name); 6106 config_type = 6107 configure_apic_reg_virt_test(apic_reg_virt_config); 6108 if (config_type == CONFIG_TYPE_UNSUPPORTED) { 6109 printf("Skip because of missing features.\n"); 6110 continue; 6111 } 6112 6113 if (config_type == CONFIG_TYPE_VMENTRY_FAILS_EARLY) { 6114 enter_guest_with_bad_controls(); 6115 continue; 6116 } 6117 6118 for (reg = 0; reg < PAGE_SIZE / sizeof(u32); reg += 0x10) { 6119 struct apic_reg_virt_expectation expectation = {}; 6120 bool ok; 6121 6122 ok = apic_reg_virt_exit_expectation( 6123 reg, apic_reg_virt_config, &expectation); 6124 if (!ok) { 6125 report_fail("Malformed test."); 6126 break; 6127 } 6128 6129 test_xapic_rd(reg, &expectation, apic_access_address, 6130 virtual_apic_page); 6131 test_xapic_wr(reg, &expectation, apic_access_address, 6132 virtual_apic_page); 6133 } 6134 } 6135 6136 /* Terminate the guest */ 6137 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6138 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6139 args->op = TERMINATE; 6140 enter_guest(); 6141 assert_exit_reason(VMX_VMCALL); 6142 } 6143 6144 struct virt_x2apic_mode_config { 6145 struct apic_reg_virt_config apic_reg_virt_config; 6146 bool virtual_interrupt_delivery; 6147 bool use_msr_bitmaps; 6148 bool disable_x2apic_msr_intercepts; 6149 bool disable_x2apic; 6150 }; 6151 6152 struct virt_x2apic_mode_test_case { 6153 const char *name; 6154 struct virt_x2apic_mode_config virt_x2apic_mode_config; 6155 }; 6156 6157 enum Virt_x2apic_mode_behavior_type { 6158 X2APIC_ACCESS_VIRTUALIZED, 6159 X2APIC_ACCESS_PASSED_THROUGH, 6160 X2APIC_ACCESS_TRIGGERS_GP, 6161 }; 6162 6163 struct virt_x2apic_mode_expectation { 6164 enum Reason rd_exit_reason; 6165 enum Reason wr_exit_reason; 6166 6167 /* 6168 * RDMSR and WRMSR handle 64-bit values. However, except for ICR, all of 6169 * the x2APIC registers are 32 bits. Notice: 6170 * 1. vmx_x2apic_read() clears the upper 32 bits for 32-bit registers. 6171 * 2. vmx_x2apic_write() expects the val arg to be well-formed. 6172 */ 6173 u64 rd_val; 6174 u64 wr_val; 6175 6176 /* 6177 * Compares input to virtualized output; 6178 * 1st arg is pointer to return expected virtualization output. 6179 */ 6180 u64 (*virt_fn)(u64); 6181 6182 enum Virt_x2apic_mode_behavior_type rd_behavior; 6183 enum Virt_x2apic_mode_behavior_type wr_behavior; 6184 bool wr_only; 6185 }; 6186 6187 static u64 virt_x2apic_mode_identity(u64 val) 6188 { 6189 return val; 6190 } 6191 6192 static u64 virt_x2apic_mode_nibble1(u64 val) 6193 { 6194 return val & 0xf0; 6195 } 6196 6197 static void virt_x2apic_mode_rd_expectation( 6198 u32 reg, bool virt_x2apic_mode_on, bool disable_x2apic, 6199 bool apic_register_virtualization, bool virtual_interrupt_delivery, 6200 struct virt_x2apic_mode_expectation *expectation) 6201 { 6202 enum x2apic_reg_semantics semantics = get_x2apic_reg_semantics(reg); 6203 6204 expectation->rd_exit_reason = VMX_VMCALL; 6205 expectation->virt_fn = virt_x2apic_mode_identity; 6206 if (virt_x2apic_mode_on && apic_register_virtualization) { 6207 expectation->rd_val = MAGIC_VAL_1; 6208 if (reg == APIC_PROCPRI && virtual_interrupt_delivery) 6209 expectation->virt_fn = virt_x2apic_mode_nibble1; 6210 else if (reg == APIC_TASKPRI) 6211 expectation->virt_fn = virt_x2apic_mode_nibble1; 6212 expectation->rd_behavior = X2APIC_ACCESS_VIRTUALIZED; 6213 } else if (virt_x2apic_mode_on && !apic_register_virtualization && 6214 reg == APIC_TASKPRI) { 6215 expectation->rd_val = MAGIC_VAL_1; 6216 expectation->virt_fn = virt_x2apic_mode_nibble1; 6217 expectation->rd_behavior = X2APIC_ACCESS_VIRTUALIZED; 6218 } else if (!disable_x2apic && (semantics & X2APIC_READABLE)) { 6219 expectation->rd_val = apic_read(reg); 6220 expectation->rd_behavior = X2APIC_ACCESS_PASSED_THROUGH; 6221 } else { 6222 expectation->rd_behavior = X2APIC_ACCESS_TRIGGERS_GP; 6223 } 6224 } 6225 6226 /* 6227 * get_x2apic_wr_val() creates an innocuous write value for an x2APIC register. 6228 * 6229 * For writable registers, get_x2apic_wr_val() deposits the write value into the 6230 * val pointer arg and returns true. For non-writable registers, val is not 6231 * modified and get_x2apic_wr_val() returns false. 6232 */ 6233 static bool get_x2apic_wr_val(u32 reg, u64 *val) 6234 { 6235 switch (reg) { 6236 case APIC_TASKPRI: 6237 /* Bits 31:8 are reserved. */ 6238 *val &= 0xff; 6239 break; 6240 case APIC_EOI: 6241 case APIC_ESR: 6242 case APIC_TMICT: 6243 /* 6244 * EOI, ESR: WRMSR of a non-zero value causes #GP(0). 6245 * TMICT: A write of 0 to the initial-count register effectively 6246 * stops the local APIC timer, in both one-shot and 6247 * periodic mode. 6248 */ 6249 *val = 0; 6250 break; 6251 case APIC_SPIV: 6252 case APIC_LVTT: 6253 case APIC_LVTTHMR: 6254 case APIC_LVTPC: 6255 case APIC_LVT0: 6256 case APIC_LVT1: 6257 case APIC_LVTERR: 6258 case APIC_TDCR: 6259 /* 6260 * To avoid writing a 1 to a reserved bit or causing some other 6261 * unintended side effect, read the current value and use it as 6262 * the write value. 6263 */ 6264 *val = apic_read(reg); 6265 break; 6266 case APIC_CMCI: 6267 if (!apic_lvt_entry_supported(6)) 6268 return false; 6269 *val = apic_read(reg); 6270 break; 6271 case APIC_ICR: 6272 *val = 0x40000 | 0xf1; 6273 break; 6274 case APIC_SELF_IPI: 6275 /* 6276 * With special processing (i.e., virtualize x2APIC mode + 6277 * virtual interrupt delivery), writing zero causes an 6278 * APIC-write VM exit. We plan to add a test for enabling 6279 * "virtual-interrupt delivery" in VMCS12, and that's where we 6280 * will test a self IPI with special processing. 6281 */ 6282 *val = 0x0; 6283 break; 6284 default: 6285 return false; 6286 } 6287 6288 return true; 6289 } 6290 6291 static bool special_processing_applies(u32 reg, u64 *val, 6292 bool virt_int_delivery) 6293 { 6294 bool special_processing = 6295 (reg == APIC_TASKPRI) || 6296 (virt_int_delivery && 6297 (reg == APIC_EOI || reg == APIC_SELF_IPI)); 6298 6299 if (special_processing) { 6300 TEST_ASSERT(get_x2apic_wr_val(reg, val)); 6301 return true; 6302 } 6303 6304 return false; 6305 } 6306 6307 static void virt_x2apic_mode_wr_expectation( 6308 u32 reg, bool virt_x2apic_mode_on, bool disable_x2apic, 6309 bool virt_int_delivery, 6310 struct virt_x2apic_mode_expectation *expectation) 6311 { 6312 expectation->wr_exit_reason = VMX_VMCALL; 6313 expectation->wr_val = MAGIC_VAL_1; 6314 expectation->wr_only = false; 6315 6316 if (virt_x2apic_mode_on && 6317 special_processing_applies(reg, &expectation->wr_val, 6318 virt_int_delivery)) { 6319 expectation->wr_behavior = X2APIC_ACCESS_VIRTUALIZED; 6320 if (reg == APIC_SELF_IPI) 6321 expectation->wr_exit_reason = VMX_APIC_WRITE; 6322 } else if (!disable_x2apic && 6323 get_x2apic_wr_val(reg, &expectation->wr_val)) { 6324 expectation->wr_behavior = X2APIC_ACCESS_PASSED_THROUGH; 6325 if (reg == APIC_EOI || reg == APIC_SELF_IPI) 6326 expectation->wr_only = true; 6327 if (reg == APIC_ICR) 6328 expectation->wr_exit_reason = VMX_EXTINT; 6329 } else { 6330 expectation->wr_behavior = X2APIC_ACCESS_TRIGGERS_GP; 6331 /* 6332 * Writing 1 to a reserved bit triggers a #GP. 6333 * Thus, set the write value to 0, which seems 6334 * the most likely to detect a missed #GP. 6335 */ 6336 expectation->wr_val = 0; 6337 } 6338 } 6339 6340 static void virt_x2apic_mode_exit_expectation( 6341 u32 reg, struct virt_x2apic_mode_config *config, 6342 struct virt_x2apic_mode_expectation *expectation) 6343 { 6344 struct apic_reg_virt_config *base_config = 6345 &config->apic_reg_virt_config; 6346 bool virt_x2apic_mode_on = 6347 base_config->virtualize_x2apic_mode && 6348 config->use_msr_bitmaps && 6349 config->disable_x2apic_msr_intercepts && 6350 base_config->activate_secondary_controls; 6351 6352 virt_x2apic_mode_wr_expectation( 6353 reg, virt_x2apic_mode_on, config->disable_x2apic, 6354 config->virtual_interrupt_delivery, expectation); 6355 virt_x2apic_mode_rd_expectation( 6356 reg, virt_x2apic_mode_on, config->disable_x2apic, 6357 base_config->apic_register_virtualization, 6358 config->virtual_interrupt_delivery, expectation); 6359 } 6360 6361 struct virt_x2apic_mode_test_case virt_x2apic_mode_tests[] = { 6362 /* 6363 * Baseline "virtualize x2APIC mode" configuration: 6364 * - virtualize x2APIC mode 6365 * - virtual-interrupt delivery 6366 * - APIC-register virtualization 6367 * - x2APIC MSR intercepts disabled 6368 * 6369 * Reads come from virtual APIC page, special processing applies to 6370 * VTPR, EOI, and SELF IPI, and all other writes pass through to L1 6371 * APIC. 6372 */ 6373 { 6374 .name = "Baseline", 6375 .virt_x2apic_mode_config = { 6376 .virtual_interrupt_delivery = true, 6377 .use_msr_bitmaps = true, 6378 .disable_x2apic_msr_intercepts = true, 6379 .disable_x2apic = false, 6380 .apic_reg_virt_config = { 6381 .apic_register_virtualization = true, 6382 .use_tpr_shadow = true, 6383 .virtualize_apic_accesses = false, 6384 .virtualize_x2apic_mode = true, 6385 .activate_secondary_controls = true, 6386 }, 6387 }, 6388 }, 6389 { 6390 .name = "Baseline w/ x2apic disabled", 6391 .virt_x2apic_mode_config = { 6392 .virtual_interrupt_delivery = true, 6393 .use_msr_bitmaps = true, 6394 .disable_x2apic_msr_intercepts = true, 6395 .disable_x2apic = true, 6396 .apic_reg_virt_config = { 6397 .apic_register_virtualization = true, 6398 .use_tpr_shadow = true, 6399 .virtualize_apic_accesses = false, 6400 .virtualize_x2apic_mode = true, 6401 .activate_secondary_controls = true, 6402 }, 6403 }, 6404 }, 6405 6406 /* 6407 * Baseline, minus virtual-interrupt delivery. Reads come from virtual 6408 * APIC page, special processing applies to VTPR, and all other writes 6409 * pass through to L1 APIC. 6410 */ 6411 { 6412 .name = "Baseline - virtual interrupt delivery", 6413 .virt_x2apic_mode_config = { 6414 .virtual_interrupt_delivery = false, 6415 .use_msr_bitmaps = true, 6416 .disable_x2apic_msr_intercepts = true, 6417 .disable_x2apic = false, 6418 .apic_reg_virt_config = { 6419 .apic_register_virtualization = true, 6420 .use_tpr_shadow = true, 6421 .virtualize_apic_accesses = false, 6422 .virtualize_x2apic_mode = true, 6423 .activate_secondary_controls = true, 6424 }, 6425 }, 6426 }, 6427 6428 /* 6429 * Baseline, minus APIC-register virtualization. x2APIC reads pass 6430 * through to L1's APIC, unless reading VTPR 6431 */ 6432 { 6433 .name = "Virtualize x2APIC mode, no APIC reg virt", 6434 .virt_x2apic_mode_config = { 6435 .virtual_interrupt_delivery = true, 6436 .use_msr_bitmaps = true, 6437 .disable_x2apic_msr_intercepts = true, 6438 .disable_x2apic = false, 6439 .apic_reg_virt_config = { 6440 .apic_register_virtualization = false, 6441 .use_tpr_shadow = true, 6442 .virtualize_apic_accesses = false, 6443 .virtualize_x2apic_mode = true, 6444 .activate_secondary_controls = true, 6445 }, 6446 }, 6447 }, 6448 { 6449 .name = "Virtualize x2APIC mode, no APIC reg virt, x2APIC off", 6450 .virt_x2apic_mode_config = { 6451 .virtual_interrupt_delivery = true, 6452 .use_msr_bitmaps = true, 6453 .disable_x2apic_msr_intercepts = true, 6454 .disable_x2apic = true, 6455 .apic_reg_virt_config = { 6456 .apic_register_virtualization = false, 6457 .use_tpr_shadow = true, 6458 .virtualize_apic_accesses = false, 6459 .virtualize_x2apic_mode = true, 6460 .activate_secondary_controls = true, 6461 }, 6462 }, 6463 }, 6464 6465 /* 6466 * Enable "virtualize x2APIC mode" and "APIC-register virtualization", 6467 * and disable intercepts for the x2APIC MSRs, but fail to enable 6468 * "activate secondary controls" (i.e. L2 gets access to L1's x2APIC 6469 * MSRs). 6470 */ 6471 { 6472 .name = "Fail to enable activate secondary controls", 6473 .virt_x2apic_mode_config = { 6474 .virtual_interrupt_delivery = true, 6475 .use_msr_bitmaps = true, 6476 .disable_x2apic_msr_intercepts = true, 6477 .disable_x2apic = false, 6478 .apic_reg_virt_config = { 6479 .apic_register_virtualization = true, 6480 .use_tpr_shadow = true, 6481 .virtualize_apic_accesses = false, 6482 .virtualize_x2apic_mode = true, 6483 .activate_secondary_controls = false, 6484 }, 6485 }, 6486 }, 6487 6488 /* 6489 * Enable "APIC-register virtualization" and enable "activate secondary 6490 * controls" and disable intercepts for the x2APIC MSRs, but do not 6491 * enable the "virtualize x2APIC mode" VM-execution control (i.e. L2 6492 * gets access to L1's x2APIC MSRs). 6493 */ 6494 { 6495 .name = "Fail to enable virtualize x2APIC mode", 6496 .virt_x2apic_mode_config = { 6497 .virtual_interrupt_delivery = true, 6498 .use_msr_bitmaps = true, 6499 .disable_x2apic_msr_intercepts = true, 6500 .disable_x2apic = false, 6501 .apic_reg_virt_config = { 6502 .apic_register_virtualization = true, 6503 .use_tpr_shadow = true, 6504 .virtualize_apic_accesses = false, 6505 .virtualize_x2apic_mode = false, 6506 .activate_secondary_controls = true, 6507 }, 6508 }, 6509 }, 6510 6511 /* 6512 * Disable "Virtualize x2APIC mode", disable x2APIC MSR intercepts, and 6513 * enable "APIC-register virtualization" --> L2 gets L1's x2APIC MSRs. 6514 */ 6515 { 6516 .name = "Baseline", 6517 .virt_x2apic_mode_config = { 6518 .virtual_interrupt_delivery = true, 6519 .use_msr_bitmaps = true, 6520 .disable_x2apic_msr_intercepts = true, 6521 .disable_x2apic = false, 6522 .apic_reg_virt_config = { 6523 .apic_register_virtualization = true, 6524 .use_tpr_shadow = true, 6525 .virtualize_apic_accesses = false, 6526 .virtualize_x2apic_mode = false, 6527 .activate_secondary_controls = true, 6528 }, 6529 }, 6530 }, 6531 }; 6532 6533 enum X2apic_op { 6534 X2APIC_OP_RD, 6535 X2APIC_OP_WR, 6536 X2APIC_TERMINATE, 6537 }; 6538 6539 static u64 vmx_x2apic_read(u32 reg) 6540 { 6541 u32 msr_addr = x2apic_msr(reg); 6542 u64 val; 6543 6544 val = rdmsr(msr_addr); 6545 6546 return val; 6547 } 6548 6549 static void vmx_x2apic_write(u32 reg, u64 val) 6550 { 6551 u32 msr_addr = x2apic_msr(reg); 6552 6553 wrmsr(msr_addr, val); 6554 } 6555 6556 struct virt_x2apic_mode_guest_args { 6557 enum X2apic_op op; 6558 u32 reg; 6559 u64 val; 6560 bool should_gp; 6561 u64 (*virt_fn)(u64); 6562 } virt_x2apic_mode_guest_args; 6563 6564 static volatile bool handle_x2apic_gp_ran; 6565 static volatile u32 handle_x2apic_gp_insn_len; 6566 static void handle_x2apic_gp(struct ex_regs *regs) 6567 { 6568 handle_x2apic_gp_ran = true; 6569 regs->rip += handle_x2apic_gp_insn_len; 6570 } 6571 6572 static handler setup_x2apic_gp_handler(void) 6573 { 6574 handler old_handler; 6575 6576 old_handler = handle_exception(GP_VECTOR, handle_x2apic_gp); 6577 /* RDMSR and WRMSR are both 2 bytes, assuming no prefixes. */ 6578 handle_x2apic_gp_insn_len = 2; 6579 6580 return old_handler; 6581 } 6582 6583 static void teardown_x2apic_gp_handler(handler old_handler) 6584 { 6585 handle_exception(GP_VECTOR, old_handler); 6586 6587 /* 6588 * Defensively reset instruction length, so that if the handler is 6589 * incorrectly used, it will loop infinitely, rather than run off into 6590 * la la land. 6591 */ 6592 handle_x2apic_gp_insn_len = 0; 6593 handle_x2apic_gp_ran = false; 6594 } 6595 6596 static void virt_x2apic_mode_guest(void) 6597 { 6598 volatile struct virt_x2apic_mode_guest_args *args = 6599 &virt_x2apic_mode_guest_args; 6600 6601 for (;;) { 6602 enum X2apic_op op = args->op; 6603 u32 reg = args->reg; 6604 u64 val = args->val; 6605 bool should_gp = args->should_gp; 6606 u64 (*virt_fn)(u64) = args->virt_fn; 6607 handler old_handler; 6608 6609 if (op == X2APIC_TERMINATE) 6610 break; 6611 6612 if (should_gp) { 6613 TEST_ASSERT(!handle_x2apic_gp_ran); 6614 old_handler = setup_x2apic_gp_handler(); 6615 } 6616 6617 if (op == X2APIC_OP_RD) { 6618 u64 ret = vmx_x2apic_read(reg); 6619 6620 if (!should_gp) { 6621 u64 want = virt_fn(val); 6622 u64 got = virt_fn(ret); 6623 6624 report(got == want, 6625 "APIC read; got 0x%lx, want 0x%lx.", 6626 got, want); 6627 } 6628 } else if (op == X2APIC_OP_WR) { 6629 vmx_x2apic_write(reg, val); 6630 } 6631 6632 if (should_gp) { 6633 report(handle_x2apic_gp_ran, 6634 "x2APIC op triggered GP."); 6635 teardown_x2apic_gp_handler(old_handler); 6636 } 6637 6638 /* 6639 * The L1 should always execute a vmcall after it's done testing 6640 * an individual APIC operation. This helps to validate that the 6641 * L1 and L2 are in sync with each other, as expected. 6642 */ 6643 vmcall(); 6644 } 6645 } 6646 6647 static void test_x2apic_rd( 6648 u32 reg, struct virt_x2apic_mode_expectation *expectation, 6649 u32 *virtual_apic_page) 6650 { 6651 u64 val = expectation->rd_val; 6652 u32 exit_reason_want = expectation->rd_exit_reason; 6653 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6654 6655 report_prefix_pushf("x2apic - reading 0x%03x", reg); 6656 6657 /* Configure guest to do an x2apic read */ 6658 args->op = X2APIC_OP_RD; 6659 args->reg = reg; 6660 args->val = val; 6661 args->should_gp = expectation->rd_behavior == X2APIC_ACCESS_TRIGGERS_GP; 6662 args->virt_fn = expectation->virt_fn; 6663 6664 /* Setup virtual APIC page */ 6665 if (expectation->rd_behavior == X2APIC_ACCESS_VIRTUALIZED) 6666 virtual_apic_page[apic_reg_index(reg)] = (u32)val; 6667 6668 /* Enter guest */ 6669 enter_guest(); 6670 6671 if (exit_reason_want != VMX_VMCALL) { 6672 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 6673 } 6674 6675 skip_exit_vmcall(); 6676 report_prefix_pop(); 6677 } 6678 6679 static volatile bool handle_x2apic_ipi_ran; 6680 static void handle_x2apic_ipi(isr_regs_t *regs) 6681 { 6682 handle_x2apic_ipi_ran = true; 6683 eoi(); 6684 } 6685 6686 static void test_x2apic_wr( 6687 u32 reg, struct virt_x2apic_mode_expectation *expectation, 6688 u32 *virtual_apic_page) 6689 { 6690 u64 val = expectation->wr_val; 6691 u32 exit_reason_want = expectation->wr_exit_reason; 6692 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6693 int ipi_vector = 0xf1; 6694 u32 restore_val = 0; 6695 6696 report_prefix_pushf("x2apic - writing 0x%lx to 0x%03x", val, reg); 6697 6698 /* Configure guest to do an x2apic read */ 6699 args->op = X2APIC_OP_WR; 6700 args->reg = reg; 6701 args->val = val; 6702 args->should_gp = expectation->wr_behavior == X2APIC_ACCESS_TRIGGERS_GP; 6703 6704 /* Setup virtual APIC page */ 6705 if (expectation->wr_behavior == X2APIC_ACCESS_VIRTUALIZED) 6706 virtual_apic_page[apic_reg_index(reg)] = 0; 6707 if (expectation->wr_behavior == X2APIC_ACCESS_PASSED_THROUGH && !expectation->wr_only) 6708 restore_val = apic_read(reg); 6709 6710 /* Setup IPI handler */ 6711 handle_x2apic_ipi_ran = false; 6712 handle_irq(ipi_vector, handle_x2apic_ipi); 6713 6714 /* Enter guest */ 6715 enter_guest(); 6716 6717 /* 6718 * Validate the behavior and 6719 * pass a magic value back to the guest. 6720 */ 6721 if (exit_reason_want == VMX_EXTINT) { 6722 assert_exit_reason(exit_reason_want); 6723 6724 /* Clear the external interrupt. */ 6725 sti_nop_cli(); 6726 report(handle_x2apic_ipi_ran, 6727 "Got pending interrupt after IRQ enabled."); 6728 6729 enter_guest(); 6730 } else if (exit_reason_want == VMX_APIC_WRITE) { 6731 assert_exit_reason(exit_reason_want); 6732 report(virtual_apic_page[apic_reg_index(reg)] == val, 6733 "got APIC write exit @ page offset 0x%03x; val is 0x%x, want 0x%lx", 6734 apic_reg_index(reg), 6735 virtual_apic_page[apic_reg_index(reg)], val); 6736 6737 /* Reenter guest so it can consume/check rcx and exit again. */ 6738 enter_guest(); 6739 } else if (exit_reason_want != VMX_VMCALL) { 6740 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 6741 } 6742 6743 assert_exit_reason(VMX_VMCALL); 6744 if (expectation->wr_behavior == X2APIC_ACCESS_VIRTUALIZED) { 6745 u64 want = val; 6746 u32 got = virtual_apic_page[apic_reg_index(reg)]; 6747 6748 report(got == want, "x2APIC write; got 0x%x, want 0x%lx", got, 6749 want); 6750 } else if (expectation->wr_behavior == X2APIC_ACCESS_PASSED_THROUGH) { 6751 if (!expectation->wr_only) { 6752 u32 got = apic_read(reg); 6753 bool ok; 6754 6755 /* 6756 * When L1's TPR is passed through to L2, the lower 6757 * nibble can be lost. For example, if L2 executes 6758 * WRMSR(0x808, 0x78), then, L1 might read 0x70. 6759 * 6760 * Here's how the lower nibble can get lost: 6761 * 1. L2 executes WRMSR(0x808, 0x78). 6762 * 2. L2 exits to L0 with a WRMSR exit. 6763 * 3. L0 emulates WRMSR, by writing L1's TPR. 6764 * 4. L0 re-enters L2. 6765 * 5. L2 exits to L0 (reason doesn't matter). 6766 * 6. L0 reflects L2's exit to L1. 6767 * 7. Before entering L1, L0 exits to user-space 6768 * (e.g., to satisfy TPR access reporting). 6769 * 8. User-space executes KVM_SET_REGS ioctl, which 6770 * clears the lower nibble of L1's TPR. 6771 */ 6772 if (reg == APIC_TASKPRI) { 6773 got = apic_virt_nibble1(got); 6774 val = apic_virt_nibble1(val); 6775 } 6776 6777 ok = got == val; 6778 report(ok, 6779 "non-virtualized write; val is 0x%x, want 0x%lx", 6780 got, val); 6781 apic_write(reg, restore_val); 6782 } else { 6783 report_pass("non-virtualized and write-only OK"); 6784 } 6785 } 6786 skip_exit_insn(); 6787 6788 report_prefix_pop(); 6789 } 6790 6791 static enum Config_type configure_virt_x2apic_mode_test( 6792 struct virt_x2apic_mode_config *virt_x2apic_mode_config, 6793 u8 *msr_bitmap_page) 6794 { 6795 int msr; 6796 u32 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6797 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6798 6799 /* x2apic-specific VMCS config */ 6800 if (virt_x2apic_mode_config->use_msr_bitmaps) { 6801 /* virt_x2apic_mode_test() checks for MSR bitmaps support */ 6802 cpu_exec_ctrl0 |= CPU_MSR_BITMAP; 6803 } else { 6804 cpu_exec_ctrl0 &= ~CPU_MSR_BITMAP; 6805 } 6806 6807 if (virt_x2apic_mode_config->virtual_interrupt_delivery) { 6808 if (!(ctrl_cpu_rev[1].clr & CPU_VINTD)) { 6809 report_skip("%s : \"virtual-interrupt delivery\" exec control not supported", __func__); 6810 return CONFIG_TYPE_UNSUPPORTED; 6811 } 6812 cpu_exec_ctrl1 |= CPU_VINTD; 6813 } else { 6814 cpu_exec_ctrl1 &= ~CPU_VINTD; 6815 } 6816 6817 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6818 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6819 6820 /* x2APIC MSR intercepts are usually off for "Virtualize x2APIC mode" */ 6821 for (msr = 0x800; msr <= 0x8ff; msr++) { 6822 if (virt_x2apic_mode_config->disable_x2apic_msr_intercepts) { 6823 clear_bit(msr, msr_bitmap_page + 0x000); 6824 clear_bit(msr, msr_bitmap_page + 0x800); 6825 } else { 6826 set_bit(msr, msr_bitmap_page + 0x000); 6827 set_bit(msr, msr_bitmap_page + 0x800); 6828 } 6829 } 6830 6831 /* x2APIC mode can impact virtualization */ 6832 reset_apic(); 6833 if (!virt_x2apic_mode_config->disable_x2apic) 6834 enable_x2apic(); 6835 6836 return configure_apic_reg_virt_test( 6837 &virt_x2apic_mode_config->apic_reg_virt_config); 6838 } 6839 6840 static void virt_x2apic_mode_test(void) 6841 { 6842 u32 *virtual_apic_page; 6843 u8 *msr_bitmap_page; 6844 u64 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6845 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6846 int i; 6847 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6848 6849 if (!cpu_has_apicv()) { 6850 report_skip("%s : Not all required APICv bits supported", __func__); 6851 return; 6852 } 6853 6854 /* 6855 * This is to exercise an issue in KVM's logic to merge L0's and L1's 6856 * MSR bitmaps. Previously, an L1 could get at L0's x2APIC MSRs by 6857 * writing the IA32_SPEC_CTRL MSR or the IA32_PRED_CMD MSRs. KVM would 6858 * then proceed to manipulate the MSR bitmaps, as if VMCS12 had the 6859 * "Virtualize x2APIC mod" control set, even when it didn't. 6860 */ 6861 if (this_cpu_has(X86_FEATURE_SPEC_CTRL)) 6862 wrmsr(MSR_IA32_SPEC_CTRL, 1); 6863 6864 /* 6865 * Check that VMCS12 supports: 6866 * - "Virtual-APIC address", indicated by "use TPR shadow" 6867 * - "MSR-bitmap address", indicated by "use MSR bitmaps" 6868 */ 6869 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) { 6870 report_skip("%s : \"Use TPR shadow\" exec control not supported", __func__); 6871 return; 6872 } else if (!(ctrl_cpu_rev[0].clr & CPU_MSR_BITMAP)) { 6873 report_skip("%s : \"Use MSR bitmaps\" exec control not supported", __func__); 6874 return; 6875 } 6876 6877 test_set_guest(virt_x2apic_mode_guest); 6878 6879 virtual_apic_page = alloc_page(); 6880 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 6881 6882 msr_bitmap_page = alloc_page(); 6883 memset(msr_bitmap_page, 0xff, PAGE_SIZE); 6884 vmcs_write(MSR_BITMAP, virt_to_phys(msr_bitmap_page)); 6885 6886 for (i = 0; i < ARRAY_SIZE(virt_x2apic_mode_tests); i++) { 6887 struct virt_x2apic_mode_test_case *virt_x2apic_mode_test_case = 6888 &virt_x2apic_mode_tests[i]; 6889 struct virt_x2apic_mode_config *virt_x2apic_mode_config = 6890 &virt_x2apic_mode_test_case->virt_x2apic_mode_config; 6891 enum Config_type config_type; 6892 u32 reg; 6893 6894 printf("--- %s test ---\n", virt_x2apic_mode_test_case->name); 6895 config_type = 6896 configure_virt_x2apic_mode_test(virt_x2apic_mode_config, 6897 msr_bitmap_page); 6898 if (config_type == CONFIG_TYPE_UNSUPPORTED) { 6899 report_skip("Skip because of missing features."); 6900 continue; 6901 } else if (config_type == CONFIG_TYPE_VMENTRY_FAILS_EARLY) { 6902 enter_guest_with_bad_controls(); 6903 continue; 6904 } 6905 6906 for (reg = 0; reg < PAGE_SIZE / sizeof(u32); reg += 0x10) { 6907 struct virt_x2apic_mode_expectation expectation; 6908 6909 virt_x2apic_mode_exit_expectation( 6910 reg, virt_x2apic_mode_config, &expectation); 6911 6912 test_x2apic_rd(reg, &expectation, virtual_apic_page); 6913 test_x2apic_wr(reg, &expectation, virtual_apic_page); 6914 } 6915 } 6916 6917 6918 /* Terminate the guest */ 6919 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6920 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6921 args->op = X2APIC_TERMINATE; 6922 enter_guest(); 6923 assert_exit_reason(VMX_VMCALL); 6924 } 6925 6926 static void test_ctl_reg(const char *cr_name, u64 cr, u64 fixed0, u64 fixed1) 6927 { 6928 u64 val; 6929 u64 cr_saved = vmcs_read(cr); 6930 int i; 6931 6932 val = fixed0 & fixed1; 6933 if (cr == HOST_CR4) 6934 vmcs_write(cr, val | X86_CR4_PAE); 6935 else 6936 vmcs_write(cr, val); 6937 report_prefix_pushf("%s %lx", cr_name, val); 6938 if (val == fixed0) 6939 test_vmx_vmlaunch(0); 6940 else 6941 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 6942 report_prefix_pop(); 6943 6944 for (i = 0; i < 64; i++) { 6945 6946 /* Set a bit when the corresponding bit in fixed1 is 0 */ 6947 if ((fixed1 & (1ull << i)) == 0) { 6948 if (cr == HOST_CR4 && ((1ull << i) & X86_CR4_SMEP || 6949 (1ull << i) & X86_CR4_SMAP)) 6950 continue; 6951 6952 vmcs_write(cr, cr_saved | (1ull << i)); 6953 report_prefix_pushf("%s %llx", cr_name, 6954 cr_saved | (1ull << i)); 6955 test_vmx_vmlaunch( 6956 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 6957 report_prefix_pop(); 6958 } 6959 6960 /* Unset a bit when the corresponding bit in fixed0 is 1 */ 6961 if (fixed0 & (1ull << i)) { 6962 vmcs_write(cr, cr_saved & ~(1ull << i)); 6963 report_prefix_pushf("%s %llx", cr_name, 6964 cr_saved & ~(1ull << i)); 6965 test_vmx_vmlaunch( 6966 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 6967 report_prefix_pop(); 6968 } 6969 } 6970 6971 vmcs_write(cr, cr_saved); 6972 } 6973 6974 /* 6975 * 1. The CR0 field must not set any bit to a value not supported in VMX 6976 * operation. 6977 * 2. The CR4 field must not set any bit to a value not supported in VMX 6978 * operation. 6979 * 3. On processors that support Intel 64 architecture, the CR3 field must 6980 * be such that bits 63:52 and bits in the range 51:32 beyond the 6981 * processor's physical-address width must be 0. 6982 * 6983 * [Intel SDM] 6984 */ 6985 static void test_host_ctl_regs(void) 6986 { 6987 u64 fixed0, fixed1, cr3, cr3_saved; 6988 int i; 6989 6990 /* Test CR0 */ 6991 fixed0 = rdmsr(MSR_IA32_VMX_CR0_FIXED0); 6992 fixed1 = rdmsr(MSR_IA32_VMX_CR0_FIXED1); 6993 test_ctl_reg("HOST_CR0", HOST_CR0, fixed0, fixed1); 6994 6995 /* Test CR4 */ 6996 fixed0 = rdmsr(MSR_IA32_VMX_CR4_FIXED0); 6997 fixed1 = rdmsr(MSR_IA32_VMX_CR4_FIXED1) & 6998 ~(X86_CR4_SMEP | X86_CR4_SMAP); 6999 test_ctl_reg("HOST_CR4", HOST_CR4, fixed0, fixed1); 7000 7001 /* Test CR3 */ 7002 cr3_saved = vmcs_read(HOST_CR3); 7003 for (i = cpuid_maxphyaddr(); i < 64; i++) { 7004 cr3 = cr3_saved | (1ul << i); 7005 vmcs_write(HOST_CR3, cr3); 7006 report_prefix_pushf("HOST_CR3 %lx", cr3); 7007 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7008 report_prefix_pop(); 7009 } 7010 7011 vmcs_write(HOST_CR3, cr3_saved); 7012 } 7013 7014 static void test_efer_vmlaunch(u32 fld, bool ok) 7015 { 7016 if (fld == HOST_EFER) { 7017 if (ok) 7018 test_vmx_vmlaunch(0); 7019 else 7020 test_vmx_vmlaunch2(VMXERR_ENTRY_INVALID_CONTROL_FIELD, 7021 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7022 } else { 7023 test_guest_state("EFER test", !ok, GUEST_EFER, "GUEST_EFER"); 7024 } 7025 } 7026 7027 static void test_efer_one(u32 fld, const char * fld_name, u64 efer, 7028 u32 ctrl_fld, u64 ctrl, 7029 int i, const char *efer_bit_name) 7030 { 7031 bool ok; 7032 7033 ok = true; 7034 if (ctrl_fld == EXI_CONTROLS && (ctrl & EXI_LOAD_EFER)) { 7035 if (!!(efer & EFER_LMA) != !!(ctrl & EXI_HOST_64)) 7036 ok = false; 7037 if (!!(efer & EFER_LME) != !!(ctrl & EXI_HOST_64)) 7038 ok = false; 7039 } 7040 if (ctrl_fld == ENT_CONTROLS && (ctrl & ENT_LOAD_EFER)) { 7041 /* Check LMA too since CR0.PG is set. */ 7042 if (!!(efer & EFER_LMA) != !!(ctrl & ENT_GUEST_64)) 7043 ok = false; 7044 if (!!(efer & EFER_LME) != !!(ctrl & ENT_GUEST_64)) 7045 ok = false; 7046 } 7047 7048 /* 7049 * Skip the test if it would enter the guest in 32-bit mode. 7050 * Perhaps write the test in assembly and make sure it 7051 * can be run in either mode? 7052 */ 7053 if (fld == GUEST_EFER && ok && !(ctrl & ENT_GUEST_64)) 7054 return; 7055 7056 vmcs_write(ctrl_fld, ctrl); 7057 vmcs_write(fld, efer); 7058 report_prefix_pushf("%s %s bit turned %s, controls %s", 7059 fld_name, efer_bit_name, 7060 (i & 1) ? "on" : "off", 7061 (i & 2) ? "on" : "off"); 7062 7063 test_efer_vmlaunch(fld, ok); 7064 report_prefix_pop(); 7065 } 7066 7067 static void test_efer_bit(u32 fld, const char * fld_name, 7068 u32 ctrl_fld, u64 ctrl_bit, u64 efer_bit, 7069 const char *efer_bit_name) 7070 { 7071 u64 efer_saved = vmcs_read(fld); 7072 u32 ctrl_saved = vmcs_read(ctrl_fld); 7073 int i; 7074 7075 for (i = 0; i < 4; i++) { 7076 u64 efer = efer_saved & ~efer_bit; 7077 u64 ctrl = ctrl_saved & ~ctrl_bit; 7078 7079 if (i & 1) 7080 efer |= efer_bit; 7081 if (i & 2) 7082 ctrl |= ctrl_bit; 7083 7084 test_efer_one(fld, fld_name, efer, ctrl_fld, ctrl, 7085 i, efer_bit_name); 7086 } 7087 7088 vmcs_write(ctrl_fld, ctrl_saved); 7089 vmcs_write(fld, efer_saved); 7090 } 7091 7092 static void test_efer(u32 fld, const char * fld_name, u32 ctrl_fld, 7093 u64 ctrl_bit1, u64 ctrl_bit2) 7094 { 7095 u64 efer_saved = vmcs_read(fld); 7096 u32 ctrl_saved = vmcs_read(ctrl_fld); 7097 u64 efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 7098 u64 i; 7099 u64 efer; 7100 7101 if (this_cpu_has(X86_FEATURE_NX)) 7102 efer_reserved_bits &= ~EFER_NX; 7103 7104 if (!ctrl_bit1) { 7105 report_skip("%s : \"Load-IA32-EFER\" exit control not supported", __func__); 7106 goto test_entry_exit_mode; 7107 } 7108 7109 report_prefix_pushf("%s %lx", fld_name, efer_saved); 7110 test_efer_vmlaunch(fld, true); 7111 report_prefix_pop(); 7112 7113 /* 7114 * Check reserved bits 7115 */ 7116 vmcs_write(ctrl_fld, ctrl_saved & ~ctrl_bit1); 7117 for (i = 0; i < 64; i++) { 7118 if ((1ull << i) & efer_reserved_bits) { 7119 efer = efer_saved | (1ull << i); 7120 vmcs_write(fld, efer); 7121 report_prefix_pushf("%s %lx", fld_name, efer); 7122 test_efer_vmlaunch(fld, true); 7123 report_prefix_pop(); 7124 } 7125 } 7126 7127 vmcs_write(ctrl_fld, ctrl_saved | ctrl_bit1); 7128 for (i = 0; i < 64; i++) { 7129 if ((1ull << i) & efer_reserved_bits) { 7130 efer = efer_saved | (1ull << i); 7131 vmcs_write(fld, efer); 7132 report_prefix_pushf("%s %lx", fld_name, efer); 7133 test_efer_vmlaunch(fld, false); 7134 report_prefix_pop(); 7135 } 7136 } 7137 7138 vmcs_write(ctrl_fld, ctrl_saved); 7139 vmcs_write(fld, efer_saved); 7140 7141 /* 7142 * Check LMA and LME bits 7143 */ 7144 test_efer_bit(fld, fld_name, 7145 ctrl_fld, ctrl_bit1, 7146 EFER_LMA, 7147 "EFER_LMA"); 7148 test_efer_bit(fld, fld_name, 7149 ctrl_fld, ctrl_bit1, 7150 EFER_LME, 7151 "EFER_LME"); 7152 7153 test_entry_exit_mode: 7154 test_efer_bit(fld, fld_name, 7155 ctrl_fld, ctrl_bit2, 7156 EFER_LMA, 7157 "EFER_LMA"); 7158 test_efer_bit(fld, fld_name, 7159 ctrl_fld, ctrl_bit2, 7160 EFER_LME, 7161 "EFER_LME"); 7162 } 7163 7164 /* 7165 * If the 'load IA32_EFER' VM-exit control is 1, bits reserved in the 7166 * IA32_EFER MSR must be 0 in the field for that register. In addition, 7167 * the values of the LMA and LME bits in the field must each be that of 7168 * the 'host address-space size' VM-exit control. 7169 * 7170 * [Intel SDM] 7171 */ 7172 static void test_host_efer(void) 7173 { 7174 test_efer(HOST_EFER, "HOST_EFER", EXI_CONTROLS, 7175 ctrl_exit_rev.clr & EXI_LOAD_EFER, 7176 EXI_HOST_64); 7177 } 7178 7179 /* 7180 * If the 'load IA32_EFER' VM-enter control is 1, bits reserved in the 7181 * IA32_EFER MSR must be 0 in the field for that register. In addition, 7182 * the values of the LMA and LME bits in the field must each be that of 7183 * the 'IA32e-mode guest' VM-exit control. 7184 */ 7185 static void test_guest_efer(void) 7186 { 7187 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) { 7188 report_skip("%s : \"Load-IA32-EFER\" entry control not supported", __func__); 7189 return; 7190 } 7191 7192 vmcs_write(GUEST_EFER, rdmsr(MSR_EFER)); 7193 test_efer(GUEST_EFER, "GUEST_EFER", ENT_CONTROLS, 7194 ctrl_enter_rev.clr & ENT_LOAD_EFER, 7195 ENT_GUEST_64); 7196 } 7197 7198 /* 7199 * PAT values higher than 8 are uninteresting since they're likely lumped 7200 * in with "8". We only test values above 8 one bit at a time, 7201 * in order to reduce the number of VM-Entries and keep the runtime reasonable. 7202 */ 7203 #define PAT_VAL_LIMIT 8 7204 7205 static void test_pat(u32 field, const char * field_name, u32 ctrl_field, 7206 u64 ctrl_bit) 7207 { 7208 u32 ctrl_saved = vmcs_read(ctrl_field); 7209 u64 pat_saved = vmcs_read(field); 7210 u64 i, val; 7211 u32 j; 7212 int error; 7213 7214 vmcs_clear_bits(ctrl_field, ctrl_bit); 7215 7216 for (i = 0; i < 256; i = (i < PAT_VAL_LIMIT) ? i + 1 : i * 2) { 7217 /* Test PAT0..PAT7 fields */ 7218 for (j = 0; j < (i ? 8 : 1); j++) { 7219 val = i << j * 8; 7220 vmcs_write(field, val); 7221 if (field == HOST_PAT) { 7222 report_prefix_pushf("%s %lx", field_name, val); 7223 test_vmx_vmlaunch(0); 7224 report_prefix_pop(); 7225 7226 } else { // GUEST_PAT 7227 test_guest_state("ENT_LOAD_PAT enabled", false, 7228 val, "GUEST_PAT"); 7229 } 7230 } 7231 } 7232 7233 vmcs_set_bits(ctrl_field, ctrl_bit); 7234 for (i = 0; i < 256; i = (i < PAT_VAL_LIMIT) ? i + 1 : i * 2) { 7235 /* Test PAT0..PAT7 fields */ 7236 for (j = 0; j < (i ? 8 : 1); j++) { 7237 val = i << j * 8; 7238 vmcs_write(field, val); 7239 7240 if (field == HOST_PAT) { 7241 report_prefix_pushf("%s %lx", field_name, val); 7242 if (i == 0x2 || i == 0x3 || i >= 0x8) 7243 error = 7244 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD; 7245 else 7246 error = 0; 7247 7248 test_vmx_vmlaunch(error); 7249 report_prefix_pop(); 7250 7251 } else { // GUEST_PAT 7252 error = (i == 0x2 || i == 0x3 || i >= 0x8); 7253 test_guest_state("ENT_LOAD_PAT enabled", !!error, 7254 val, "GUEST_PAT"); 7255 } 7256 7257 } 7258 } 7259 7260 vmcs_write(ctrl_field, ctrl_saved); 7261 vmcs_write(field, pat_saved); 7262 } 7263 7264 /* 7265 * If the "load IA32_PAT" VM-exit control is 1, the value of the field 7266 * for the IA32_PAT MSR must be one that could be written by WRMSR 7267 * without fault at CPL 0. Specifically, each of the 8 bytes in the 7268 * field must have one of the values 0 (UC), 1 (WC), 4 (WT), 5 (WP), 7269 * 6 (WB), or 7 (UC-). 7270 * 7271 * [Intel SDM] 7272 */ 7273 static void test_load_host_pat(void) 7274 { 7275 /* 7276 * "load IA32_PAT" VM-exit control 7277 */ 7278 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) { 7279 report_skip("%s : \"Load-IA32-PAT\" exit control not supported", __func__); 7280 return; 7281 } 7282 7283 test_pat(HOST_PAT, "HOST_PAT", EXI_CONTROLS, EXI_LOAD_PAT); 7284 } 7285 7286 union cpuidA_eax { 7287 struct { 7288 unsigned int version_id:8; 7289 unsigned int num_counters_gp:8; 7290 unsigned int bit_width:8; 7291 unsigned int mask_length:8; 7292 } split; 7293 unsigned int full; 7294 }; 7295 7296 union cpuidA_edx { 7297 struct { 7298 unsigned int num_counters_fixed:5; 7299 unsigned int bit_width_fixed:8; 7300 unsigned int reserved:9; 7301 } split; 7302 unsigned int full; 7303 }; 7304 7305 static bool valid_pgc(u64 val) 7306 { 7307 struct cpuid id; 7308 union cpuidA_eax eax; 7309 union cpuidA_edx edx; 7310 u64 mask; 7311 7312 id = cpuid(0xA); 7313 eax.full = id.a; 7314 edx.full = id.d; 7315 mask = ~(((1ull << eax.split.num_counters_gp) - 1) | 7316 (((1ull << edx.split.num_counters_fixed) - 1) << 32)); 7317 7318 return !(val & mask); 7319 } 7320 7321 static void test_pgc_vmlaunch(u32 xerror, u32 xreason, bool xfail, bool host) 7322 { 7323 u32 inst_err; 7324 u64 obs; 7325 bool success; 7326 struct vmx_state_area_test_data *data = &vmx_state_area_test_data; 7327 7328 if (host) { 7329 success = vmlaunch(); 7330 obs = rdmsr(data->msr); 7331 if (!success) { 7332 inst_err = vmcs_read(VMX_INST_ERROR); 7333 report(xerror == inst_err, "vmlaunch failed, " 7334 "VMX Inst Error is %d (expected %d)", 7335 inst_err, xerror); 7336 } else { 7337 report(!data->enabled || data->exp == obs, 7338 "Host state is 0x%lx (expected 0x%lx)", 7339 obs, data->exp); 7340 report(success != xfail, "vmlaunch succeeded"); 7341 } 7342 } else { 7343 test_guest_state("load GUEST_PERF_GLOBAL_CTRL", xfail, 7344 GUEST_PERF_GLOBAL_CTRL, 7345 "GUEST_PERF_GLOBAL_CTRL"); 7346 } 7347 } 7348 7349 /* 7350 * test_load_perf_global_ctrl is a generic function for testing the 7351 * "load IA32_PERF_GLOBAL_CTRL" VM-{Entry,Exit} controls. This test function 7352 * tests the provided ctrl_val when disabled and enabled. 7353 * 7354 * @nr: VMCS field number corresponding to the host/guest state field 7355 * @name: Name of the above VMCS field for printing in test report 7356 * @ctrl_nr: VMCS field number corresponding to the VM-{Entry,Exit} control 7357 * @ctrl_val: Bit to set on the ctrl_field 7358 */ 7359 static void test_perf_global_ctrl(u32 nr, const char *name, u32 ctrl_nr, 7360 const char *ctrl_name, u64 ctrl_val) 7361 { 7362 u64 ctrl_saved = vmcs_read(ctrl_nr); 7363 u64 pgc_saved = vmcs_read(nr); 7364 u64 i, val; 7365 bool host = nr == HOST_PERF_GLOBAL_CTRL; 7366 struct vmx_state_area_test_data *data = &vmx_state_area_test_data; 7367 7368 data->msr = MSR_CORE_PERF_GLOBAL_CTRL; 7369 msr_bmp_init(); 7370 vmcs_write(ctrl_nr, ctrl_saved & ~ctrl_val); 7371 data->enabled = false; 7372 report_prefix_pushf("\"load IA32_PERF_GLOBAL_CTRL\"=0 on %s", 7373 ctrl_name); 7374 7375 for (i = 0; i < 64; i++) { 7376 val = 1ull << i; 7377 vmcs_write(nr, val); 7378 report_prefix_pushf("%s = 0x%lx", name, val); 7379 test_pgc_vmlaunch(0, VMX_VMCALL, false, host); 7380 report_prefix_pop(); 7381 } 7382 report_prefix_pop(); 7383 7384 vmcs_write(ctrl_nr, ctrl_saved | ctrl_val); 7385 data->enabled = true; 7386 report_prefix_pushf("\"load IA32_PERF_GLOBAL_CTRL\"=1 on %s", 7387 ctrl_name); 7388 for (i = 0; i < 64; i++) { 7389 val = 1ull << i; 7390 data->exp = val; 7391 vmcs_write(nr, val); 7392 report_prefix_pushf("%s = 0x%lx", name, val); 7393 if (valid_pgc(val)) { 7394 test_pgc_vmlaunch(0, VMX_VMCALL, false, host); 7395 } else { 7396 if (host) 7397 test_pgc_vmlaunch( 7398 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, 7399 0, 7400 true, 7401 host); 7402 else 7403 test_pgc_vmlaunch( 7404 0, 7405 VMX_ENTRY_FAILURE | VMX_FAIL_STATE, 7406 true, 7407 host); 7408 } 7409 report_prefix_pop(); 7410 } 7411 7412 data->enabled = false; 7413 report_prefix_pop(); 7414 vmcs_write(ctrl_nr, ctrl_saved); 7415 vmcs_write(nr, pgc_saved); 7416 } 7417 7418 static void test_load_host_perf_global_ctrl(void) 7419 { 7420 if (!this_cpu_has_perf_global_ctrl()) { 7421 report_skip("%s : \"IA32_PERF_GLOBAL_CTRL\" MSR not supported", __func__); 7422 return; 7423 } 7424 7425 if (!(ctrl_exit_rev.clr & EXI_LOAD_PERF)) { 7426 report_skip("%s : \"Load IA32_PERF_GLOBAL_CTRL\" exit control not supported", __func__); 7427 return; 7428 } 7429 7430 test_perf_global_ctrl(HOST_PERF_GLOBAL_CTRL, "HOST_PERF_GLOBAL_CTRL", 7431 EXI_CONTROLS, "EXI_CONTROLS", EXI_LOAD_PERF); 7432 } 7433 7434 7435 static void test_load_guest_perf_global_ctrl(void) 7436 { 7437 if (!this_cpu_has_perf_global_ctrl()) { 7438 report_skip("%s : \"IA32_PERF_GLOBAL_CTRL\" MSR not supported", __func__); 7439 return; 7440 } 7441 7442 if (!(ctrl_enter_rev.clr & ENT_LOAD_PERF)) { 7443 report_skip("%s : \"Load IA32_PERF_GLOBAL_CTRL\" entry control not supported", __func__); 7444 return; 7445 } 7446 7447 test_perf_global_ctrl(GUEST_PERF_GLOBAL_CTRL, "GUEST_PERF_GLOBAL_CTRL", 7448 ENT_CONTROLS, "ENT_CONTROLS", ENT_LOAD_PERF); 7449 } 7450 7451 7452 /* 7453 * test_vmcs_field - test a value for the given VMCS field 7454 * @field: VMCS field 7455 * @field_name: string name of VMCS field 7456 * @bit_start: starting bit 7457 * @bit_end: ending bit 7458 * @val: value that the bit range must or must not contain 7459 * @valid_val: whether value given in 'val' must be valid or not 7460 * @error: expected VMCS error when vmentry fails for an invalid value 7461 */ 7462 static void test_vmcs_field(u64 field, const char *field_name, u32 bit_start, 7463 u32 bit_end, u64 val, bool valid_val, u32 error) 7464 { 7465 u64 field_saved = vmcs_read(field); 7466 u32 i; 7467 u64 tmp; 7468 u32 bit_on; 7469 u64 mask = ~0ull; 7470 7471 mask = (mask >> bit_end) << bit_end; 7472 mask = mask | ((1 << bit_start) - 1); 7473 tmp = (field_saved & mask) | (val << bit_start); 7474 7475 vmcs_write(field, tmp); 7476 report_prefix_pushf("%s %lx", field_name, tmp); 7477 if (valid_val) 7478 test_vmx_vmlaunch(0); 7479 else 7480 test_vmx_vmlaunch(error); 7481 report_prefix_pop(); 7482 7483 for (i = bit_start; i <= bit_end; i = i + 2) { 7484 bit_on = ((1ull < i) & (val << bit_start)) ? 0 : 1; 7485 if (bit_on) 7486 tmp = field_saved | (1ull << i); 7487 else 7488 tmp = field_saved & ~(1ull << i); 7489 vmcs_write(field, tmp); 7490 report_prefix_pushf("%s %lx", field_name, tmp); 7491 if (valid_val) 7492 test_vmx_vmlaunch(error); 7493 else 7494 test_vmx_vmlaunch(0); 7495 report_prefix_pop(); 7496 } 7497 7498 vmcs_write(field, field_saved); 7499 } 7500 7501 static void test_canonical(u64 field, const char * field_name, bool host) 7502 { 7503 u64 addr_saved = vmcs_read(field); 7504 7505 /* 7506 * Use the existing value if possible. Writing a random canonical 7507 * value is not an option as doing so would corrupt the field being 7508 * tested and likely hose the test. 7509 */ 7510 if (is_canonical(addr_saved)) { 7511 if (host) { 7512 report_prefix_pushf("%s %lx", field_name, addr_saved); 7513 test_vmx_vmlaunch(0); 7514 report_prefix_pop(); 7515 } else { 7516 test_guest_state("Test canonical address", false, 7517 addr_saved, field_name); 7518 } 7519 } 7520 7521 vmcs_write(field, NONCANONICAL); 7522 7523 if (host) { 7524 report_prefix_pushf("%s %llx", field_name, NONCANONICAL); 7525 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7526 report_prefix_pop(); 7527 } else { 7528 test_guest_state("Test non-canonical address", true, 7529 NONCANONICAL, field_name); 7530 } 7531 7532 vmcs_write(field, addr_saved); 7533 } 7534 7535 #define TEST_RPL_TI_FLAGS(reg, name) \ 7536 test_vmcs_field(reg, name, 0, 2, 0x0, true, \ 7537 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7538 7539 #define TEST_CS_TR_FLAGS(reg, name) \ 7540 test_vmcs_field(reg, name, 3, 15, 0x0000, false, \ 7541 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7542 7543 /* 7544 * 1. In the selector field for each of CS, SS, DS, ES, FS, GS and TR, the 7545 * RPL (bits 1:0) and the TI flag (bit 2) must be 0. 7546 * 2. The selector fields for CS and TR cannot be 0000H. 7547 * 3. The selector field for SS cannot be 0000H if the "host address-space 7548 * size" VM-exit control is 0. 7549 * 4. On processors that support Intel 64 architecture, the base-address 7550 * fields for FS, GS and TR must contain canonical addresses. 7551 */ 7552 static void test_host_segment_regs(void) 7553 { 7554 u16 selector_saved; 7555 7556 /* 7557 * Test RPL and TI flags 7558 */ 7559 TEST_RPL_TI_FLAGS(HOST_SEL_CS, "HOST_SEL_CS"); 7560 TEST_RPL_TI_FLAGS(HOST_SEL_SS, "HOST_SEL_SS"); 7561 TEST_RPL_TI_FLAGS(HOST_SEL_DS, "HOST_SEL_DS"); 7562 TEST_RPL_TI_FLAGS(HOST_SEL_ES, "HOST_SEL_ES"); 7563 TEST_RPL_TI_FLAGS(HOST_SEL_FS, "HOST_SEL_FS"); 7564 TEST_RPL_TI_FLAGS(HOST_SEL_GS, "HOST_SEL_GS"); 7565 TEST_RPL_TI_FLAGS(HOST_SEL_TR, "HOST_SEL_TR"); 7566 7567 /* 7568 * Test that CS and TR fields can not be 0x0000 7569 */ 7570 TEST_CS_TR_FLAGS(HOST_SEL_CS, "HOST_SEL_CS"); 7571 TEST_CS_TR_FLAGS(HOST_SEL_TR, "HOST_SEL_TR"); 7572 7573 /* 7574 * SS field can not be 0x0000 if "host address-space size" VM-exit 7575 * control is 0 7576 */ 7577 selector_saved = vmcs_read(HOST_SEL_SS); 7578 vmcs_write(HOST_SEL_SS, 0); 7579 report_prefix_pushf("HOST_SEL_SS 0"); 7580 if (vmcs_read(EXI_CONTROLS) & EXI_HOST_64) { 7581 test_vmx_vmlaunch(0); 7582 } else { 7583 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7584 } 7585 report_prefix_pop(); 7586 7587 vmcs_write(HOST_SEL_SS, selector_saved); 7588 7589 /* 7590 * Base address for FS, GS and TR must be canonical 7591 */ 7592 test_canonical(HOST_BASE_FS, "HOST_BASE_FS", true); 7593 test_canonical(HOST_BASE_GS, "HOST_BASE_GS", true); 7594 test_canonical(HOST_BASE_TR, "HOST_BASE_TR", true); 7595 } 7596 7597 /* 7598 * On processors that support Intel 64 architecture, the base-address 7599 * fields for GDTR and IDTR must contain canonical addresses. 7600 */ 7601 static void test_host_desc_tables(void) 7602 { 7603 test_canonical(HOST_BASE_GDTR, "HOST_BASE_GDTR", true); 7604 test_canonical(HOST_BASE_IDTR, "HOST_BASE_IDTR", true); 7605 } 7606 7607 /* 7608 * If the "host address-space size" VM-exit control is 0, the following must 7609 * hold: 7610 * - The "IA-32e mode guest" VM-entry control is 0. 7611 * - Bit 17 of the CR4 field (corresponding to CR4.PCIDE) is 0. 7612 * - Bits 63:32 in the RIP field are 0. 7613 * 7614 * If the "host address-space size" VM-exit control is 1, the following must 7615 * hold: 7616 * - Bit 5 of the CR4 field (corresponding to CR4.PAE) is 1. 7617 * - The RIP field contains a canonical address. 7618 * 7619 */ 7620 static void test_host_addr_size(void) 7621 { 7622 u64 cr4_saved = vmcs_read(HOST_CR4); 7623 u64 rip_saved = vmcs_read(HOST_RIP); 7624 u64 entry_ctrl_saved = vmcs_read(ENT_CONTROLS); 7625 7626 assert(vmcs_read(EXI_CONTROLS) & EXI_HOST_64); 7627 assert(cr4_saved & X86_CR4_PAE); 7628 7629 vmcs_write(ENT_CONTROLS, entry_ctrl_saved | ENT_GUEST_64); 7630 report_prefix_pushf("\"IA-32e mode guest\" enabled"); 7631 test_vmx_vmlaunch(0); 7632 report_prefix_pop(); 7633 7634 if (this_cpu_has(X86_FEATURE_PCID)) { 7635 vmcs_write(HOST_CR4, cr4_saved | X86_CR4_PCIDE); 7636 report_prefix_pushf("\"CR4.PCIDE\" set"); 7637 test_vmx_vmlaunch(0); 7638 report_prefix_pop(); 7639 } 7640 7641 vmcs_write(HOST_CR4, cr4_saved & ~X86_CR4_PAE); 7642 report_prefix_pushf("\"CR4.PAE\" unset"); 7643 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7644 vmcs_write(HOST_CR4, cr4_saved); 7645 report_prefix_pop(); 7646 7647 vmcs_write(HOST_RIP, NONCANONICAL); 7648 report_prefix_pushf("HOST_RIP %llx", NONCANONICAL); 7649 test_vmx_vmlaunch_must_fail(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7650 report_prefix_pop(); 7651 7652 vmcs_write(ENT_CONTROLS, entry_ctrl_saved | ENT_GUEST_64); 7653 vmcs_write(HOST_RIP, rip_saved); 7654 vmcs_write(HOST_CR4, cr4_saved); 7655 7656 /* 7657 * Restore host's active CR4 and RIP values by triggering a VM-Exit. 7658 * The original CR4 and RIP values in the VMCS are restored between 7659 * testcases as needed, but don't guarantee a VM-Exit and so the active 7660 * CR4 and RIP may still hold a test value. Running with the test CR4 7661 * and RIP values at some point is unavoidable, and the active values 7662 * are unlikely to affect VM-Enter, so the above doesn't force a VM-exit 7663 * between testcases. Note, if VM-Enter is surrounded by CALL+RET then 7664 * the active RIP will already be restored, but that's also not 7665 * guaranteed, and CR4 needs to be restored regardless. 7666 */ 7667 report_prefix_pushf("restore host state"); 7668 test_vmx_vmlaunch(0); 7669 report_prefix_pop(); 7670 } 7671 7672 /* 7673 * Check that the virtual CPU checks the VMX Host State Area as 7674 * documented in the Intel SDM. 7675 */ 7676 static void vmx_host_state_area_test(void) 7677 { 7678 /* 7679 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 7680 * fail due to invalid guest state, should we make it that 7681 * far. 7682 */ 7683 vmcs_write(GUEST_RFLAGS, 0); 7684 7685 test_host_ctl_regs(); 7686 7687 test_canonical(HOST_SYSENTER_ESP, "HOST_SYSENTER_ESP", true); 7688 test_canonical(HOST_SYSENTER_EIP, "HOST_SYSENTER_EIP", true); 7689 7690 test_host_efer(); 7691 test_load_host_pat(); 7692 test_host_segment_regs(); 7693 test_host_desc_tables(); 7694 test_host_addr_size(); 7695 test_load_host_perf_global_ctrl(); 7696 } 7697 7698 /* 7699 * If the "load debug controls" VM-entry control is 1, bits 63:32 in 7700 * the DR7 field must be 0. 7701 * 7702 * [Intel SDM] 7703 */ 7704 static void test_guest_dr7(void) 7705 { 7706 u32 ent_saved = vmcs_read(ENT_CONTROLS); 7707 u64 dr7_saved = vmcs_read(GUEST_DR7); 7708 u64 val; 7709 int i; 7710 7711 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS) { 7712 vmcs_clear_bits(ENT_CONTROLS, ENT_LOAD_DBGCTLS); 7713 for (i = 0; i < 64; i++) { 7714 val = 1ull << i; 7715 vmcs_write(GUEST_DR7, val); 7716 test_guest_state("ENT_LOAD_DBGCTLS disabled", false, 7717 val, "GUEST_DR7"); 7718 } 7719 } 7720 if (ctrl_enter_rev.clr & ENT_LOAD_DBGCTLS) { 7721 vmcs_set_bits(ENT_CONTROLS, ENT_LOAD_DBGCTLS); 7722 for (i = 0; i < 64; i++) { 7723 val = 1ull << i; 7724 vmcs_write(GUEST_DR7, val); 7725 test_guest_state("ENT_LOAD_DBGCTLS enabled", i >= 32, 7726 val, "GUEST_DR7"); 7727 } 7728 } 7729 vmcs_write(GUEST_DR7, dr7_saved); 7730 vmcs_write(ENT_CONTROLS, ent_saved); 7731 } 7732 7733 /* 7734 * If the "load IA32_PAT" VM-entry control is 1, the value of the field 7735 * for the IA32_PAT MSR must be one that could be written by WRMSR 7736 * without fault at CPL 0. Specifically, each of the 8 bytes in the 7737 * field must have one of the values 0 (UC), 1 (WC), 4 (WT), 5 (WP), 7738 * 6 (WB), or 7 (UC-). 7739 * 7740 * [Intel SDM] 7741 */ 7742 static void test_load_guest_pat(void) 7743 { 7744 /* 7745 * "load IA32_PAT" VM-entry control 7746 */ 7747 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 7748 report_skip("%s : \"Load-IA32-PAT\" entry control not supported", __func__); 7749 return; 7750 } 7751 7752 test_pat(GUEST_PAT, "GUEST_PAT", ENT_CONTROLS, ENT_LOAD_PAT); 7753 } 7754 7755 #define MSR_IA32_BNDCFGS_RSVD_MASK 0x00000ffc 7756 7757 /* 7758 * If the "load IA32_BNDCFGS" VM-entry control is 1, the following 7759 * checks are performed on the field for the IA32_BNDCFGS MSR: 7760 * 7761 * - Bits reserved in the IA32_BNDCFGS MSR must be 0. 7762 * - The linear address in bits 63:12 must be canonical. 7763 * 7764 * [Intel SDM] 7765 */ 7766 static void test_load_guest_bndcfgs(void) 7767 { 7768 u64 bndcfgs_saved = vmcs_read(GUEST_BNDCFGS); 7769 u64 bndcfgs; 7770 7771 if (!(ctrl_enter_rev.clr & ENT_LOAD_BNDCFGS)) { 7772 report_skip("%s : \"Load-IA32-BNDCFGS\" entry control not supported", __func__); 7773 return; 7774 } 7775 7776 vmcs_clear_bits(ENT_CONTROLS, ENT_LOAD_BNDCFGS); 7777 7778 vmcs_write(GUEST_BNDCFGS, NONCANONICAL); 7779 test_guest_state("ENT_LOAD_BNDCFGS disabled", false, 7780 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7781 bndcfgs = bndcfgs_saved | MSR_IA32_BNDCFGS_RSVD_MASK; 7782 vmcs_write(GUEST_BNDCFGS, bndcfgs); 7783 test_guest_state("ENT_LOAD_BNDCFGS disabled", false, 7784 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7785 7786 vmcs_set_bits(ENT_CONTROLS, ENT_LOAD_BNDCFGS); 7787 7788 vmcs_write(GUEST_BNDCFGS, NONCANONICAL); 7789 test_guest_state("ENT_LOAD_BNDCFGS enabled", true, 7790 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7791 bndcfgs = bndcfgs_saved | MSR_IA32_BNDCFGS_RSVD_MASK; 7792 vmcs_write(GUEST_BNDCFGS, bndcfgs); 7793 test_guest_state("ENT_LOAD_BNDCFGS enabled", true, 7794 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7795 7796 vmcs_write(GUEST_BNDCFGS, bndcfgs_saved); 7797 } 7798 7799 #define GUEST_SEG_UNUSABLE_MASK (1u << 16) 7800 #define GUEST_SEG_SEL_TI_MASK (1u << 2) 7801 7802 7803 #define TEST_SEGMENT_SEL(test, xfail, sel, val) \ 7804 do { \ 7805 vmcs_write(sel, val); \ 7806 test_guest_state(test " segment", xfail, val, xstr(sel)); \ 7807 } while (0) 7808 7809 #define TEST_INVALID_SEG_SEL(sel, val) \ 7810 TEST_SEGMENT_SEL("Invalid: " xstr(val), true, sel, val); 7811 7812 #define TEST_VALID_SEG_SEL(sel, val) \ 7813 TEST_SEGMENT_SEL("Valid: " xstr(val), false, sel, val); 7814 7815 /* 7816 * The following checks are done on the Selector field of the Guest Segment 7817 * Registers: 7818 * - TR. The TI flag (bit 2) must be 0. 7819 * - LDTR. If LDTR is usable, the TI flag (bit 2) must be 0. 7820 * - SS. If the guest will not be virtual-8086 and the "unrestricted 7821 * guest" VM-execution control is 0, the RPL (bits 1:0) must equal 7822 * the RPL of the selector field for CS. 7823 * 7824 * [Intel SDM] 7825 */ 7826 static void test_guest_segment_sel_fields(void) 7827 { 7828 u16 sel_saved; 7829 u32 ar_saved; 7830 u32 cpu_ctrl0_saved; 7831 u32 cpu_ctrl1_saved; 7832 u16 cs_rpl_bits; 7833 7834 /* 7835 * Test for GUEST_SEL_TR 7836 */ 7837 sel_saved = vmcs_read(GUEST_SEL_TR); 7838 TEST_INVALID_SEG_SEL(GUEST_SEL_TR, sel_saved | GUEST_SEG_SEL_TI_MASK); 7839 vmcs_write(GUEST_SEL_TR, sel_saved); 7840 7841 /* 7842 * Test for GUEST_SEL_LDTR 7843 */ 7844 sel_saved = vmcs_read(GUEST_SEL_LDTR); 7845 ar_saved = vmcs_read(GUEST_AR_LDTR); 7846 /* LDTR is set unusable */ 7847 vmcs_write(GUEST_AR_LDTR, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7848 TEST_VALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved | GUEST_SEG_SEL_TI_MASK); 7849 TEST_VALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved & ~GUEST_SEG_SEL_TI_MASK); 7850 /* LDTR is set usable */ 7851 vmcs_write(GUEST_AR_LDTR, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7852 TEST_INVALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved | GUEST_SEG_SEL_TI_MASK); 7853 7854 TEST_VALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved & ~GUEST_SEG_SEL_TI_MASK); 7855 7856 vmcs_write(GUEST_AR_LDTR, ar_saved); 7857 vmcs_write(GUEST_SEL_LDTR, sel_saved); 7858 7859 /* 7860 * Test for GUEST_SEL_SS 7861 */ 7862 cpu_ctrl0_saved = vmcs_read(CPU_EXEC_CTRL0); 7863 cpu_ctrl1_saved = vmcs_read(CPU_EXEC_CTRL1); 7864 ar_saved = vmcs_read(GUEST_AR_SS); 7865 /* Turn off "unrestricted guest" vm-execution control */ 7866 vmcs_write(CPU_EXEC_CTRL1, cpu_ctrl1_saved & ~CPU_URG); 7867 cs_rpl_bits = vmcs_read(GUEST_SEL_CS) & 0x3; 7868 sel_saved = vmcs_read(GUEST_SEL_SS); 7869 TEST_INVALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 7870 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 7871 /* Make SS usable if it's unusable or vice-versa */ 7872 if (ar_saved & GUEST_SEG_UNUSABLE_MASK) 7873 vmcs_write(GUEST_AR_SS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7874 else 7875 vmcs_write(GUEST_AR_SS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7876 TEST_INVALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 7877 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 7878 7879 /* Need a valid EPTP as the passing case fully enters the guest. */ 7880 if (enable_unrestricted_guest(true)) 7881 goto skip_ss_tests; 7882 7883 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 7884 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 7885 7886 /* Make SS usable if it's unusable or vice-versa */ 7887 if (vmcs_read(GUEST_AR_SS) & GUEST_SEG_UNUSABLE_MASK) 7888 vmcs_write(GUEST_AR_SS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7889 else 7890 vmcs_write(GUEST_AR_SS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7891 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 7892 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 7893 skip_ss_tests: 7894 7895 vmcs_write(GUEST_AR_SS, ar_saved); 7896 vmcs_write(GUEST_SEL_SS, sel_saved); 7897 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrl0_saved); 7898 vmcs_write(CPU_EXEC_CTRL1, cpu_ctrl1_saved); 7899 } 7900 7901 #define TEST_SEGMENT_BASE_ADDR_UPPER_BITS(xfail, seg_base) \ 7902 do { \ 7903 addr_saved = vmcs_read(seg_base); \ 7904 for (i = 32; i < 63; i = i + 4) { \ 7905 addr = addr_saved | 1ull << i; \ 7906 vmcs_write(seg_base, addr); \ 7907 test_guest_state("seg.BASE[63:32] != 0, usable = " xstr(xfail), \ 7908 xfail, addr, xstr(seg_base)); \ 7909 } \ 7910 vmcs_write(seg_base, addr_saved); \ 7911 } while (0) 7912 7913 #define TEST_SEGMENT_BASE_ADDR_CANONICAL(xfail, seg_base) \ 7914 do { \ 7915 addr_saved = vmcs_read(seg_base); \ 7916 vmcs_write(seg_base, NONCANONICAL); \ 7917 test_guest_state("seg.BASE non-canonical, usable = " xstr(xfail), \ 7918 xfail, NONCANONICAL, xstr(seg_base)); \ 7919 vmcs_write(seg_base, addr_saved); \ 7920 } while (0) 7921 7922 /* 7923 * The following checks are done on the Base Address field of the Guest 7924 * Segment Registers on processors that support Intel 64 architecture: 7925 * - TR, FS, GS : The address must be canonical. 7926 * - LDTR : If LDTR is usable, the address must be canonical. 7927 * - CS : Bits 63:32 of the address must be zero. 7928 * - SS, DS, ES : If the register is usable, bits 63:32 of the address 7929 * must be zero. 7930 * 7931 * [Intel SDM] 7932 */ 7933 static void test_guest_segment_base_addr_fields(void) 7934 { 7935 u64 addr_saved; 7936 u64 addr; 7937 u32 ar_saved; 7938 int i; 7939 7940 /* 7941 * The address of TR, FS, GS and LDTR must be canonical. 7942 */ 7943 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_TR); 7944 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_FS); 7945 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_GS); 7946 ar_saved = vmcs_read(GUEST_AR_LDTR); 7947 /* Make LDTR unusable */ 7948 vmcs_write(GUEST_AR_LDTR, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7949 TEST_SEGMENT_BASE_ADDR_CANONICAL(false, GUEST_BASE_LDTR); 7950 /* Make LDTR usable */ 7951 vmcs_write(GUEST_AR_LDTR, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7952 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_LDTR); 7953 7954 vmcs_write(GUEST_AR_LDTR, ar_saved); 7955 7956 /* 7957 * Bits 63:32 in CS, SS, DS and ES base address must be zero 7958 */ 7959 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_CS); 7960 ar_saved = vmcs_read(GUEST_AR_SS); 7961 /* Make SS unusable */ 7962 vmcs_write(GUEST_AR_SS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7963 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(false, GUEST_BASE_SS); 7964 /* Make SS usable */ 7965 vmcs_write(GUEST_AR_SS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7966 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_SS); 7967 vmcs_write(GUEST_AR_SS, ar_saved); 7968 7969 ar_saved = vmcs_read(GUEST_AR_DS); 7970 /* Make DS unusable */ 7971 vmcs_write(GUEST_AR_DS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7972 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(false, GUEST_BASE_DS); 7973 /* Make DS usable */ 7974 vmcs_write(GUEST_AR_DS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7975 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_DS); 7976 vmcs_write(GUEST_AR_DS, ar_saved); 7977 7978 ar_saved = vmcs_read(GUEST_AR_ES); 7979 /* Make ES unusable */ 7980 vmcs_write(GUEST_AR_ES, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7981 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(false, GUEST_BASE_ES); 7982 /* Make ES usable */ 7983 vmcs_write(GUEST_AR_ES, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7984 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_ES); 7985 vmcs_write(GUEST_AR_ES, ar_saved); 7986 } 7987 7988 /* 7989 * Check that the virtual CPU checks the VMX Guest State Area as 7990 * documented in the Intel SDM. 7991 */ 7992 static void vmx_guest_state_area_test(void) 7993 { 7994 vmx_set_test_stage(1); 7995 test_set_guest(guest_state_test_main); 7996 7997 /* 7998 * The IA32_SYSENTER_ESP field and the IA32_SYSENTER_EIP field 7999 * must each contain a canonical address. 8000 */ 8001 test_canonical(GUEST_SYSENTER_ESP, "GUEST_SYSENTER_ESP", false); 8002 test_canonical(GUEST_SYSENTER_EIP, "GUEST_SYSENTER_EIP", false); 8003 8004 test_guest_dr7(); 8005 test_load_guest_pat(); 8006 test_guest_efer(); 8007 test_load_guest_perf_global_ctrl(); 8008 test_load_guest_bndcfgs(); 8009 8010 test_guest_segment_sel_fields(); 8011 test_guest_segment_base_addr_fields(); 8012 8013 test_canonical(GUEST_BASE_GDTR, "GUEST_BASE_GDTR", false); 8014 test_canonical(GUEST_BASE_IDTR, "GUEST_BASE_IDTR", false); 8015 8016 u32 guest_desc_limit_saved = vmcs_read(GUEST_LIMIT_GDTR); 8017 int i; 8018 for (i = 16; i <= 31; i++) { 8019 u32 tmp = guest_desc_limit_saved | (1ull << i); 8020 vmcs_write(GUEST_LIMIT_GDTR, tmp); 8021 test_guest_state("GDT.limit > 0xffff", true, tmp, "GUEST_LIMIT_GDTR"); 8022 } 8023 vmcs_write(GUEST_LIMIT_GDTR, guest_desc_limit_saved); 8024 8025 guest_desc_limit_saved = vmcs_read(GUEST_LIMIT_IDTR); 8026 for (i = 16; i <= 31; i++) { 8027 u32 tmp = guest_desc_limit_saved | (1ull << i); 8028 vmcs_write(GUEST_LIMIT_IDTR, tmp); 8029 test_guest_state("IDT.limit > 0xffff", true, tmp, "GUEST_LIMIT_IDTR"); 8030 } 8031 vmcs_write(GUEST_LIMIT_IDTR, guest_desc_limit_saved); 8032 8033 /* 8034 * Let the guest finish execution 8035 */ 8036 vmx_set_test_stage(2); 8037 enter_guest(); 8038 } 8039 8040 extern void unrestricted_guest_main(void); 8041 asm (".code32\n" 8042 "unrestricted_guest_main:\n" 8043 "vmcall\n" 8044 "nop\n" 8045 "mov $1, %edi\n" 8046 "call hypercall\n" 8047 ".code64\n"); 8048 8049 static void setup_unrestricted_guest(void) 8050 { 8051 vmcs_write(GUEST_CR0, vmcs_read(GUEST_CR0) & ~(X86_CR0_PG)); 8052 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) & ~ENT_GUEST_64); 8053 vmcs_write(GUEST_EFER, vmcs_read(GUEST_EFER) & ~EFER_LMA); 8054 vmcs_write(GUEST_RIP, virt_to_phys(unrestricted_guest_main)); 8055 } 8056 8057 static void unsetup_unrestricted_guest(void) 8058 { 8059 vmcs_write(GUEST_CR0, vmcs_read(GUEST_CR0) | X86_CR0_PG); 8060 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) | ENT_GUEST_64); 8061 vmcs_write(GUEST_EFER, vmcs_read(GUEST_EFER) | EFER_LMA); 8062 vmcs_write(GUEST_RIP, (u64) phys_to_virt(vmcs_read(GUEST_RIP))); 8063 vmcs_write(GUEST_RSP, (u64) phys_to_virt(vmcs_read(GUEST_RSP))); 8064 } 8065 8066 /* 8067 * If "unrestricted guest" secondary VM-execution control is set, guests 8068 * can run in unpaged protected mode. 8069 */ 8070 static void vmentry_unrestricted_guest_test(void) 8071 { 8072 if (enable_unrestricted_guest(true)) { 8073 report_skip("%s: \"Unrestricted guest\" exec control not supported", __func__); 8074 return; 8075 } 8076 8077 test_set_guest(unrestricted_guest_main); 8078 setup_unrestricted_guest(); 8079 test_guest_state("Unrestricted guest test", false, CPU_URG, "CPU_URG"); 8080 8081 /* 8082 * Let the guest finish execution as a regular guest 8083 */ 8084 unsetup_unrestricted_guest(); 8085 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) & ~CPU_URG); 8086 enter_guest(); 8087 } 8088 8089 static bool valid_vmcs_for_vmentry(void) 8090 { 8091 struct vmcs *current_vmcs = NULL; 8092 8093 if (vmcs_save(¤t_vmcs)) 8094 return false; 8095 8096 return current_vmcs && !current_vmcs->hdr.shadow_vmcs; 8097 } 8098 8099 static void try_vmentry_in_movss_shadow(void) 8100 { 8101 u32 vm_inst_err; 8102 u32 flags; 8103 bool early_failure = false; 8104 u32 expected_flags = X86_EFLAGS_FIXED; 8105 bool valid_vmcs = valid_vmcs_for_vmentry(); 8106 8107 expected_flags |= valid_vmcs ? X86_EFLAGS_ZF : X86_EFLAGS_CF; 8108 8109 /* 8110 * Indirectly set VM_INST_ERR to 12 ("VMREAD/VMWRITE from/to 8111 * unsupported VMCS component"). 8112 */ 8113 vmcs_write(~0u, 0); 8114 8115 __asm__ __volatile__ ("mov %[host_rsp], %%edx;" 8116 "vmwrite %%rsp, %%rdx;" 8117 "mov 0f, %%rax;" 8118 "mov %[host_rip], %%edx;" 8119 "vmwrite %%rax, %%rdx;" 8120 "mov $-1, %%ah;" 8121 "sahf;" 8122 "mov %%ss, %%ax;" 8123 "mov %%ax, %%ss;" 8124 "vmlaunch;" 8125 "mov $1, %[early_failure];" 8126 "0: lahf;" 8127 "movzbl %%ah, %[flags]" 8128 : [early_failure] "+r" (early_failure), 8129 [flags] "=&a" (flags) 8130 : [host_rsp] "i" (HOST_RSP), 8131 [host_rip] "i" (HOST_RIP) 8132 : "rdx", "cc", "memory"); 8133 vm_inst_err = vmcs_read(VMX_INST_ERROR); 8134 8135 report(early_failure, "Early VM-entry failure"); 8136 report(flags == expected_flags, "RFLAGS[8:0] is %x (actual %x)", 8137 expected_flags, flags); 8138 if (valid_vmcs) 8139 report(vm_inst_err == VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, 8140 "VM-instruction error is %d (actual %d)", 8141 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, vm_inst_err); 8142 } 8143 8144 static void vmentry_movss_shadow_test(void) 8145 { 8146 struct vmcs *orig_vmcs; 8147 8148 TEST_ASSERT(!vmcs_save(&orig_vmcs)); 8149 8150 /* 8151 * Set the launched flag on the current VMCS to verify the correct 8152 * error priority, below. 8153 */ 8154 test_set_guest(v2_null_test_guest); 8155 enter_guest(); 8156 8157 /* 8158 * With bit 1 of the guest's RFLAGS clear, VM-entry should 8159 * fail due to invalid guest state (if we make it that far). 8160 */ 8161 vmcs_write(GUEST_RFLAGS, 0); 8162 8163 /* 8164 * "VM entry with events blocked by MOV SS" takes precedence over 8165 * "VMLAUNCH with non-clear VMCS." 8166 */ 8167 report_prefix_push("valid current-VMCS"); 8168 try_vmentry_in_movss_shadow(); 8169 report_prefix_pop(); 8170 8171 /* 8172 * VMfailInvalid takes precedence over "VM entry with events 8173 * blocked by MOV SS." 8174 */ 8175 TEST_ASSERT(!vmcs_clear(orig_vmcs)); 8176 report_prefix_push("no current-VMCS"); 8177 try_vmentry_in_movss_shadow(); 8178 report_prefix_pop(); 8179 8180 TEST_ASSERT(!make_vmcs_current(orig_vmcs)); 8181 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 8182 } 8183 8184 static void vmx_ldtr_test_guest(void) 8185 { 8186 u16 ldtr = sldt(); 8187 8188 report(ldtr == NP_SEL, "Expected %x for L2 LDTR selector (got %x)", 8189 NP_SEL, ldtr); 8190 } 8191 8192 /* 8193 * Ensure that the L1 LDTR is set to 0 on VM-exit. 8194 */ 8195 static void vmx_ldtr_test(void) 8196 { 8197 const u8 ldt_ar = 0x82; /* Present LDT */ 8198 u16 sel = FIRST_SPARE_SEL; 8199 8200 /* Set up a non-zero L1 LDTR prior to VM-entry. */ 8201 set_gdt_entry(sel, 0, 0, ldt_ar, 0); 8202 lldt(sel); 8203 8204 test_set_guest(vmx_ldtr_test_guest); 8205 /* 8206 * Set up a different LDTR for L2. The actual GDT contents are 8207 * irrelevant, since we stuff the hidden descriptor state 8208 * straight into the VMCS rather than reading it from the GDT. 8209 */ 8210 vmcs_write(GUEST_SEL_LDTR, NP_SEL); 8211 vmcs_write(GUEST_AR_LDTR, ldt_ar); 8212 enter_guest(); 8213 8214 /* 8215 * VM-exit should clear LDTR (and make it unusable, but we 8216 * won't verify that here). 8217 */ 8218 sel = sldt(); 8219 report(!sel, "Expected 0 for L1 LDTR selector (got %x)", sel); 8220 } 8221 8222 static void vmx_single_vmcall_guest(void) 8223 { 8224 vmcall(); 8225 } 8226 8227 static void vmx_cr_load_test(void) 8228 { 8229 unsigned long cr3, cr4, orig_cr3, orig_cr4; 8230 u32 ctrls[2] = {0}; 8231 pgd_t *pml5; 8232 8233 orig_cr4 = read_cr4(); 8234 orig_cr3 = read_cr3(); 8235 8236 if (!this_cpu_has(X86_FEATURE_PCID)) { 8237 report_skip("%s : PCID not detected", __func__); 8238 return; 8239 } 8240 if (!this_cpu_has(X86_FEATURE_MCE)) { 8241 report_skip("%s : MCE not detected", __func__); 8242 return; 8243 } 8244 8245 TEST_ASSERT(!(orig_cr3 & X86_CR3_PCID_MASK)); 8246 8247 /* Enable PCID for L1. */ 8248 cr4 = orig_cr4 | X86_CR4_PCIDE; 8249 cr3 = orig_cr3 | 0x1; 8250 TEST_ASSERT(!write_cr4_safe(cr4)); 8251 write_cr3(cr3); 8252 8253 test_set_guest(vmx_single_vmcall_guest); 8254 vmcs_write(HOST_CR4, cr4); 8255 vmcs_write(HOST_CR3, cr3); 8256 enter_guest(); 8257 8258 /* 8259 * No exception is expected. 8260 * 8261 * NB. KVM loads the last guest write to CR4 into CR4 read 8262 * shadow. In order to trigger an exit to KVM, we can toggle a 8263 * bit that is owned by KVM. We use CR4.MCE, which shall 8264 * have no side effect because normally no guest MCE (e.g., as the 8265 * result of bad memory) would happen during this test. 8266 */ 8267 TEST_ASSERT(!write_cr4_safe(cr4 ^ X86_CR4_MCE)); 8268 8269 /* Cleanup L1 state. */ 8270 write_cr3(orig_cr3); 8271 TEST_ASSERT(!write_cr4_safe(orig_cr4)); 8272 8273 if (!this_cpu_has(X86_FEATURE_LA57)) 8274 goto done; 8275 8276 /* 8277 * Allocate a full page for PML5 to guarantee alignment, though only 8278 * the first entry needs to be filled (the test's virtual addresses 8279 * most definitely do not have any of bits 56:48 set). 8280 */ 8281 pml5 = alloc_page(); 8282 *pml5 = orig_cr3 | PT_PRESENT_MASK | PT_WRITABLE_MASK; 8283 8284 /* 8285 * Transition to/from 5-level paging in the host via VM-Exit. CR4.LA57 8286 * can't be toggled while long is active via MOV CR4, but there are no 8287 * such restrictions on VM-Exit. 8288 */ 8289 lol_5level: 8290 vmcs_write(HOST_CR4, orig_cr4 | X86_CR4_LA57); 8291 vmcs_write(HOST_CR3, virt_to_phys(pml5)); 8292 enter_guest(); 8293 8294 /* 8295 * VMREAD with a memory operand to verify KVM detects the LA57 change, 8296 * e.g. uses the correct guest root level in gva_to_gpa(). 8297 */ 8298 TEST_ASSERT(vmcs_readm(HOST_CR3) == virt_to_phys(pml5)); 8299 TEST_ASSERT(vmcs_readm(HOST_CR4) == (orig_cr4 | X86_CR4_LA57)); 8300 8301 vmcs_write(HOST_CR4, orig_cr4); 8302 vmcs_write(HOST_CR3, orig_cr3); 8303 enter_guest(); 8304 8305 TEST_ASSERT(vmcs_readm(HOST_CR3) == orig_cr3); 8306 TEST_ASSERT(vmcs_readm(HOST_CR4) == orig_cr4); 8307 8308 /* 8309 * And now do the same LA57 shenanigans with EPT enabled. KVM uses 8310 * two separate MMUs when L1 uses TDP, whereas the above shadow paging 8311 * version shares an MMU between L1 and L2. 8312 * 8313 * If the saved execution controls are non-zero then the EPT version 8314 * has already run. In that case, restore the old controls. If EPT 8315 * setup fails, e.g. EPT isn't supported, fall through and finish up. 8316 */ 8317 if (ctrls[0]) { 8318 vmcs_write(CPU_EXEC_CTRL0, ctrls[0]); 8319 vmcs_write(CPU_EXEC_CTRL1, ctrls[1]); 8320 } else if (!setup_ept(false)) { 8321 ctrls[0] = vmcs_read(CPU_EXEC_CTRL0); 8322 ctrls[1] = vmcs_read(CPU_EXEC_CTRL1); 8323 goto lol_5level; 8324 } 8325 8326 free_page(pml5); 8327 8328 done: 8329 skip_exit_vmcall(); 8330 enter_guest(); 8331 } 8332 8333 static void vmx_cr4_osxsave_test_guest(void) 8334 { 8335 write_cr4(read_cr4() & ~X86_CR4_OSXSAVE); 8336 } 8337 8338 /* 8339 * Ensure that kvm recalculates the L1 guest's CPUID.01H:ECX.OSXSAVE 8340 * after VM-exit from an L2 guest that sets CR4.OSXSAVE to a different 8341 * value than in L1. 8342 */ 8343 static void vmx_cr4_osxsave_test(void) 8344 { 8345 if (!this_cpu_has(X86_FEATURE_XSAVE)) { 8346 report_skip("%s : XSAVE not detected", __func__); 8347 return; 8348 } 8349 8350 if (!(read_cr4() & X86_CR4_OSXSAVE)) { 8351 unsigned long cr4 = read_cr4() | X86_CR4_OSXSAVE; 8352 8353 write_cr4(cr4); 8354 vmcs_write(GUEST_CR4, cr4); 8355 vmcs_write(HOST_CR4, cr4); 8356 } 8357 8358 TEST_ASSERT(this_cpu_has(X86_FEATURE_OSXSAVE)); 8359 8360 test_set_guest(vmx_cr4_osxsave_test_guest); 8361 enter_guest(); 8362 8363 TEST_ASSERT(this_cpu_has(X86_FEATURE_OSXSAVE)); 8364 } 8365 8366 /* 8367 * FNOP with both CR0.TS and CR0.EM clear should not generate #NM, and the L2 8368 * guest should exit normally. 8369 */ 8370 static void vmx_no_nm_test(void) 8371 { 8372 test_set_guest(fnop); 8373 vmcs_write(GUEST_CR0, read_cr0() & ~(X86_CR0_TS | X86_CR0_EM)); 8374 enter_guest(); 8375 } 8376 8377 bool vmx_pending_event_ipi_fired; 8378 static void vmx_pending_event_ipi_isr(isr_regs_t *regs) 8379 { 8380 vmx_pending_event_ipi_fired = true; 8381 eoi(); 8382 } 8383 8384 bool vmx_pending_event_guest_run; 8385 static void vmx_pending_event_guest(void) 8386 { 8387 vmcall(); 8388 vmx_pending_event_guest_run = true; 8389 } 8390 8391 static void vmx_pending_event_test_core(bool guest_hlt) 8392 { 8393 int ipi_vector = 0xf1; 8394 8395 vmx_pending_event_ipi_fired = false; 8396 handle_irq(ipi_vector, vmx_pending_event_ipi_isr); 8397 8398 vmx_pending_event_guest_run = false; 8399 test_set_guest(vmx_pending_event_guest); 8400 8401 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 8402 8403 enter_guest(); 8404 skip_exit_vmcall(); 8405 8406 if (guest_hlt) 8407 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8408 8409 cli(); 8410 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | 8411 APIC_DM_FIXED | ipi_vector, 8412 0); 8413 8414 enter_guest(); 8415 8416 assert_exit_reason(VMX_EXTINT); 8417 report(!vmx_pending_event_guest_run, 8418 "Guest did not run before host received IPI"); 8419 8420 sti_nop_cli(); 8421 report(vmx_pending_event_ipi_fired, 8422 "Got pending interrupt after IRQ enabled"); 8423 8424 if (guest_hlt) 8425 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 8426 8427 enter_guest(); 8428 report(vmx_pending_event_guest_run, 8429 "Guest finished running when no interrupt"); 8430 } 8431 8432 static void vmx_pending_event_test(void) 8433 { 8434 vmx_pending_event_test_core(false); 8435 } 8436 8437 static void vmx_pending_event_hlt_test(void) 8438 { 8439 vmx_pending_event_test_core(true); 8440 } 8441 8442 static int vmx_window_test_db_count; 8443 8444 static void vmx_window_test_db_handler(struct ex_regs *regs) 8445 { 8446 vmx_window_test_db_count++; 8447 } 8448 8449 static void vmx_nmi_window_test_guest(void) 8450 { 8451 handle_exception(DB_VECTOR, vmx_window_test_db_handler); 8452 8453 asm volatile("vmcall\n\t" 8454 "nop\n\t"); 8455 8456 handle_exception(DB_VECTOR, NULL); 8457 } 8458 8459 static void verify_nmi_window_exit(u64 rip) 8460 { 8461 u32 exit_reason = vmcs_read(EXI_REASON); 8462 8463 report(exit_reason == VMX_NMI_WINDOW, 8464 "Exit reason (%d) is 'NMI window'", exit_reason); 8465 report(vmcs_read(GUEST_RIP) == rip, "RIP (%#lx) is %#lx", 8466 vmcs_read(GUEST_RIP), rip); 8467 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 8468 } 8469 8470 static void vmx_nmi_window_test(void) 8471 { 8472 u64 nop_addr; 8473 void *db_fault_addr = get_idt_addr(&boot_idt[DB_VECTOR]); 8474 8475 if (!(ctrl_pin_rev.clr & PIN_VIRT_NMI)) { 8476 report_skip("%s : \"Virtual NMIs\" exec control not supported", __func__); 8477 return; 8478 } 8479 8480 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 8481 report_skip("%s : \"NMI-window exiting\" exec control not supported", __func__); 8482 return; 8483 } 8484 8485 vmx_window_test_db_count = 0; 8486 8487 report_prefix_push("NMI-window"); 8488 test_set_guest(vmx_nmi_window_test_guest); 8489 vmcs_set_bits(PIN_CONTROLS, PIN_VIRT_NMI); 8490 enter_guest(); 8491 skip_exit_vmcall(); 8492 nop_addr = vmcs_read(GUEST_RIP); 8493 8494 /* 8495 * Ask for "NMI-window exiting," and expect an immediate VM-exit. 8496 * RIP will not advance. 8497 */ 8498 report_prefix_push("active, no blocking"); 8499 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 8500 enter_guest(); 8501 verify_nmi_window_exit(nop_addr); 8502 report_prefix_pop(); 8503 8504 /* 8505 * Ask for "NMI-window exiting" in a MOV-SS shadow, and expect 8506 * a VM-exit on the next instruction after the nop. (The nop 8507 * is one byte.) 8508 */ 8509 report_prefix_push("active, blocking by MOV-SS"); 8510 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 8511 enter_guest(); 8512 verify_nmi_window_exit(nop_addr + 1); 8513 report_prefix_pop(); 8514 8515 /* 8516 * Ask for "NMI-window exiting" (with event injection), and 8517 * expect a VM-exit after the event is injected. (RIP should 8518 * be at the address specified in the IDT entry for #DB.) 8519 */ 8520 report_prefix_push("active, no blocking, injecting #DB"); 8521 vmcs_write(ENT_INTR_INFO, 8522 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 8523 enter_guest(); 8524 verify_nmi_window_exit((u64)db_fault_addr); 8525 report_prefix_pop(); 8526 8527 /* 8528 * Ask for "NMI-window exiting" with NMI blocking, and expect 8529 * a VM-exit after the next IRET (i.e. after the #DB handler 8530 * returns). So, RIP should be back at one byte past the nop. 8531 */ 8532 report_prefix_push("active, blocking by NMI"); 8533 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_NMI); 8534 enter_guest(); 8535 verify_nmi_window_exit(nop_addr + 1); 8536 report(vmx_window_test_db_count == 1, 8537 "#DB handler executed once (actual %d times)", 8538 vmx_window_test_db_count); 8539 report_prefix_pop(); 8540 8541 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 8542 report_skip("CPU does not support activity state HLT."); 8543 } else { 8544 /* 8545 * Ask for "NMI-window exiting" when entering activity 8546 * state HLT, and expect an immediate VM-exit. RIP is 8547 * still one byte past the nop. 8548 */ 8549 report_prefix_push("halted, no blocking"); 8550 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8551 enter_guest(); 8552 verify_nmi_window_exit(nop_addr + 1); 8553 report_prefix_pop(); 8554 8555 /* 8556 * Ask for "NMI-window exiting" when entering activity 8557 * state HLT (with event injection), and expect a 8558 * VM-exit after the event is injected. (RIP should be 8559 * at the address specified in the IDT entry for #DB.) 8560 */ 8561 report_prefix_push("halted, no blocking, injecting #DB"); 8562 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8563 vmcs_write(ENT_INTR_INFO, 8564 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 8565 DB_VECTOR); 8566 enter_guest(); 8567 verify_nmi_window_exit((u64)db_fault_addr); 8568 report_prefix_pop(); 8569 } 8570 8571 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 8572 enter_guest(); 8573 report_prefix_pop(); 8574 } 8575 8576 static void vmx_intr_window_test_guest(void) 8577 { 8578 handle_exception(DB_VECTOR, vmx_window_test_db_handler); 8579 8580 /* 8581 * The two consecutive STIs are to ensure that only the first 8582 * one has a shadow. Note that NOP and STI are one byte 8583 * instructions. 8584 */ 8585 asm volatile("vmcall\n\t" 8586 "nop\n\t" 8587 "sti\n\t" 8588 "sti\n\t"); 8589 8590 handle_exception(DB_VECTOR, NULL); 8591 } 8592 8593 static void verify_intr_window_exit(u64 rip) 8594 { 8595 u32 exit_reason = vmcs_read(EXI_REASON); 8596 8597 report(exit_reason == VMX_INTR_WINDOW, 8598 "Exit reason (%d) is 'interrupt window'", exit_reason); 8599 report(vmcs_read(GUEST_RIP) == rip, "RIP (%#lx) is %#lx", 8600 vmcs_read(GUEST_RIP), rip); 8601 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 8602 } 8603 8604 static void vmx_intr_window_test(void) 8605 { 8606 u64 vmcall_addr; 8607 u64 nop_addr; 8608 unsigned int orig_db_gate_type; 8609 void *db_fault_addr = get_idt_addr(&boot_idt[DB_VECTOR]); 8610 8611 if (!(ctrl_cpu_rev[0].clr & CPU_INTR_WINDOW)) { 8612 report_skip("%s : \"Interrupt-window exiting\" exec control not supported", __func__); 8613 return; 8614 } 8615 8616 /* 8617 * Change the IDT entry for #DB from interrupt gate to trap gate, 8618 * so that it won't clear RFLAGS.IF. We don't want interrupts to 8619 * be disabled after vectoring a #DB. 8620 */ 8621 orig_db_gate_type = boot_idt[DB_VECTOR].type; 8622 boot_idt[DB_VECTOR].type = 15; 8623 8624 report_prefix_push("interrupt-window"); 8625 test_set_guest(vmx_intr_window_test_guest); 8626 enter_guest(); 8627 assert_exit_reason(VMX_VMCALL); 8628 vmcall_addr = vmcs_read(GUEST_RIP); 8629 8630 /* 8631 * Ask for "interrupt-window exiting" with RFLAGS.IF set and 8632 * no blocking; expect an immediate VM-exit. Note that we have 8633 * not advanced past the vmcall instruction yet, so RIP should 8634 * point to the vmcall instruction. 8635 */ 8636 report_prefix_push("active, no blocking, RFLAGS.IF=1"); 8637 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8638 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_IF); 8639 enter_guest(); 8640 verify_intr_window_exit(vmcall_addr); 8641 report_prefix_pop(); 8642 8643 /* 8644 * Ask for "interrupt-window exiting" (with event injection) 8645 * with RFLAGS.IF set and no blocking; expect a VM-exit after 8646 * the event is injected. That is, RIP should should be at the 8647 * address specified in the IDT entry for #DB. 8648 */ 8649 report_prefix_push("active, no blocking, RFLAGS.IF=1, injecting #DB"); 8650 vmcs_write(ENT_INTR_INFO, 8651 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 8652 vmcall_addr = vmcs_read(GUEST_RIP); 8653 enter_guest(); 8654 verify_intr_window_exit((u64)db_fault_addr); 8655 report_prefix_pop(); 8656 8657 /* 8658 * Let the L2 guest run through the IRET, back to the VMCALL. 8659 * We have to clear the "interrupt-window exiting" 8660 * VM-execution control, or it would just keep causing 8661 * VM-exits. Then, advance past the VMCALL and set the 8662 * "interrupt-window exiting" VM-execution control again. 8663 */ 8664 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8665 enter_guest(); 8666 skip_exit_vmcall(); 8667 nop_addr = vmcs_read(GUEST_RIP); 8668 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8669 8670 /* 8671 * Ask for "interrupt-window exiting" in a MOV-SS shadow with 8672 * RFLAGS.IF set, and expect a VM-exit on the next 8673 * instruction. (NOP is one byte.) 8674 */ 8675 report_prefix_push("active, blocking by MOV-SS, RFLAGS.IF=1"); 8676 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 8677 enter_guest(); 8678 verify_intr_window_exit(nop_addr + 1); 8679 report_prefix_pop(); 8680 8681 /* 8682 * Back up to the NOP and ask for "interrupt-window exiting" 8683 * in an STI shadow with RFLAGS.IF set, and expect a VM-exit 8684 * on the next instruction. (NOP is one byte.) 8685 */ 8686 report_prefix_push("active, blocking by STI, RFLAGS.IF=1"); 8687 vmcs_write(GUEST_RIP, nop_addr); 8688 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_STI); 8689 enter_guest(); 8690 verify_intr_window_exit(nop_addr + 1); 8691 report_prefix_pop(); 8692 8693 /* 8694 * Ask for "interrupt-window exiting" with RFLAGS.IF clear, 8695 * and expect a VM-exit on the instruction following the STI 8696 * shadow. Only the first STI (which is one byte past the NOP) 8697 * should have a shadow. The second STI (which is two bytes 8698 * past the NOP) has no shadow. Therefore, the interrupt 8699 * window opens at three bytes past the NOP. 8700 */ 8701 report_prefix_push("active, RFLAGS.IF = 0"); 8702 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 8703 enter_guest(); 8704 verify_intr_window_exit(nop_addr + 3); 8705 report_prefix_pop(); 8706 8707 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 8708 report_skip("CPU does not support activity state HLT."); 8709 } else { 8710 /* 8711 * Ask for "interrupt-window exiting" when entering 8712 * activity state HLT, and expect an immediate 8713 * VM-exit. RIP is still three bytes past the nop. 8714 */ 8715 report_prefix_push("halted, no blocking"); 8716 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8717 enter_guest(); 8718 verify_intr_window_exit(nop_addr + 3); 8719 report_prefix_pop(); 8720 8721 /* 8722 * Ask for "interrupt-window exiting" when entering 8723 * activity state HLT (with event injection), and 8724 * expect a VM-exit after the event is injected. That 8725 * is, RIP should should be at the address specified 8726 * in the IDT entry for #DB. 8727 */ 8728 report_prefix_push("halted, no blocking, injecting #DB"); 8729 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8730 vmcs_write(ENT_INTR_INFO, 8731 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 8732 DB_VECTOR); 8733 enter_guest(); 8734 verify_intr_window_exit((u64)db_fault_addr); 8735 report_prefix_pop(); 8736 } 8737 8738 boot_idt[DB_VECTOR].type = orig_db_gate_type; 8739 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8740 enter_guest(); 8741 report_prefix_pop(); 8742 } 8743 8744 #define GUEST_TSC_OFFSET (1u << 30) 8745 8746 static u64 guest_tsc; 8747 8748 static void vmx_store_tsc_test_guest(void) 8749 { 8750 guest_tsc = rdtsc(); 8751 } 8752 8753 /* 8754 * This test ensures that when IA32_TSC is in the VM-exit MSR-store 8755 * list, the value saved is not subject to the TSC offset that is 8756 * applied to RDTSC/RDTSCP/RDMSR(IA32_TSC) in guest execution. 8757 */ 8758 static void vmx_store_tsc_test(void) 8759 { 8760 struct vmx_msr_entry msr_entry = { .index = MSR_IA32_TSC }; 8761 u64 low, high; 8762 8763 if (!(ctrl_cpu_rev[0].clr & CPU_USE_TSC_OFFSET)) { 8764 report_skip("%s : \"Use TSC offsetting\" exec control not supported", __func__); 8765 return; 8766 } 8767 8768 test_set_guest(vmx_store_tsc_test_guest); 8769 8770 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_USE_TSC_OFFSET); 8771 vmcs_write(EXI_MSR_ST_CNT, 1); 8772 vmcs_write(EXIT_MSR_ST_ADDR, virt_to_phys(&msr_entry)); 8773 vmcs_write(TSC_OFFSET, GUEST_TSC_OFFSET); 8774 8775 low = rdtsc(); 8776 enter_guest(); 8777 high = rdtsc(); 8778 8779 report(low + GUEST_TSC_OFFSET <= guest_tsc && 8780 guest_tsc <= high + GUEST_TSC_OFFSET, 8781 "RDTSC value in the guest (%lu) is in range [%lu, %lu]", 8782 guest_tsc, low + GUEST_TSC_OFFSET, high + GUEST_TSC_OFFSET); 8783 report(low <= msr_entry.value && msr_entry.value <= high, 8784 "IA32_TSC value saved in the VM-exit MSR-store list (%lu) is in range [%lu, %lu]", 8785 msr_entry.value, low, high); 8786 } 8787 8788 static void vmx_preemption_timer_zero_test_db_handler(struct ex_regs *regs) 8789 { 8790 } 8791 8792 static void vmx_preemption_timer_zero_test_guest(void) 8793 { 8794 while (vmx_get_test_stage() < 3) 8795 vmcall(); 8796 } 8797 8798 static void vmx_preemption_timer_zero_activate_preemption_timer(void) 8799 { 8800 vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT); 8801 vmcs_write(PREEMPT_TIMER_VALUE, 0); 8802 } 8803 8804 static void vmx_preemption_timer_zero_advance_past_vmcall(void) 8805 { 8806 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 8807 enter_guest(); 8808 skip_exit_vmcall(); 8809 } 8810 8811 static void vmx_preemption_timer_zero_inject_db(bool intercept_db) 8812 { 8813 vmx_preemption_timer_zero_activate_preemption_timer(); 8814 vmcs_write(ENT_INTR_INFO, INTR_INFO_VALID_MASK | 8815 INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 8816 vmcs_write(EXC_BITMAP, intercept_db ? 1 << DB_VECTOR : 0); 8817 enter_guest(); 8818 } 8819 8820 static void vmx_preemption_timer_zero_set_pending_dbg(u32 exception_bitmap) 8821 { 8822 vmx_preemption_timer_zero_activate_preemption_timer(); 8823 vmcs_write(GUEST_PENDING_DEBUG, PENDING_DBG_TRAP | DR6_TRAP1); 8824 vmcs_write(EXC_BITMAP, exception_bitmap); 8825 enter_guest(); 8826 } 8827 8828 static void vmx_preemption_timer_zero_expect_preempt_at_rip(u64 expected_rip) 8829 { 8830 u32 reason = (u32)vmcs_read(EXI_REASON); 8831 u64 guest_rip = vmcs_read(GUEST_RIP); 8832 8833 report(reason == VMX_PREEMPT && guest_rip == expected_rip, 8834 "Exit reason is 0x%x (expected 0x%x) and guest RIP is %lx (0x%lx expected).", 8835 reason, VMX_PREEMPT, guest_rip, expected_rip); 8836 } 8837 8838 /* 8839 * This test ensures that when the VMX preemption timer is zero at 8840 * VM-entry, a VM-exit occurs after any event injection and after any 8841 * pending debug exceptions are raised, but before execution of any 8842 * guest instructions. 8843 */ 8844 static void vmx_preemption_timer_zero_test(void) 8845 { 8846 u64 db_fault_address = (u64)get_idt_addr(&boot_idt[DB_VECTOR]); 8847 handler old_db; 8848 u32 reason; 8849 8850 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 8851 report_skip("%s : \"Activate VMX-preemption timer\" pin control not supported", __func__); 8852 return; 8853 } 8854 8855 /* 8856 * Install a custom #DB handler that doesn't abort. 8857 */ 8858 old_db = handle_exception(DB_VECTOR, 8859 vmx_preemption_timer_zero_test_db_handler); 8860 8861 test_set_guest(vmx_preemption_timer_zero_test_guest); 8862 8863 /* 8864 * VMX-preemption timer should fire after event injection. 8865 */ 8866 vmx_set_test_stage(0); 8867 vmx_preemption_timer_zero_inject_db(0); 8868 vmx_preemption_timer_zero_expect_preempt_at_rip(db_fault_address); 8869 vmx_preemption_timer_zero_advance_past_vmcall(); 8870 8871 /* 8872 * VMX-preemption timer should fire after event injection. 8873 * Exception bitmap is irrelevant, since you can't intercept 8874 * an event that you injected. 8875 */ 8876 vmx_set_test_stage(1); 8877 vmx_preemption_timer_zero_inject_db(true); 8878 vmx_preemption_timer_zero_expect_preempt_at_rip(db_fault_address); 8879 vmx_preemption_timer_zero_advance_past_vmcall(); 8880 8881 /* 8882 * VMX-preemption timer should fire after pending debug exceptions 8883 * have delivered a #DB trap. 8884 */ 8885 vmx_set_test_stage(2); 8886 vmx_preemption_timer_zero_set_pending_dbg(0); 8887 vmx_preemption_timer_zero_expect_preempt_at_rip(db_fault_address); 8888 vmx_preemption_timer_zero_advance_past_vmcall(); 8889 8890 /* 8891 * VMX-preemption timer would fire after pending debug exceptions 8892 * have delivered a #DB trap, but in this case, the #DB trap is 8893 * intercepted. 8894 */ 8895 vmx_set_test_stage(3); 8896 vmx_preemption_timer_zero_set_pending_dbg(1 << DB_VECTOR); 8897 reason = (u32)vmcs_read(EXI_REASON); 8898 report(reason == VMX_EXC_NMI, "Exit reason is 0x%x (expected 0x%x)", 8899 reason, VMX_EXC_NMI); 8900 8901 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 8902 enter_guest(); 8903 8904 handle_exception(DB_VECTOR, old_db); 8905 } 8906 8907 static u64 vmx_preemption_timer_tf_test_prev_rip; 8908 8909 static void vmx_preemption_timer_tf_test_db_handler(struct ex_regs *regs) 8910 { 8911 extern char vmx_preemption_timer_tf_test_endloop; 8912 8913 if (vmx_get_test_stage() == 2) { 8914 /* 8915 * Stage 2 means that we're done, one way or another. 8916 * Arrange for the iret to drop us out of the wbinvd 8917 * loop and stop single-stepping. 8918 */ 8919 regs->rip = (u64)&vmx_preemption_timer_tf_test_endloop; 8920 regs->rflags &= ~X86_EFLAGS_TF; 8921 } else if (regs->rip == vmx_preemption_timer_tf_test_prev_rip) { 8922 /* 8923 * The RIP should alternate between the wbinvd and the 8924 * jmp instruction in the code below. If we ever see 8925 * the same instruction twice in a row, that means a 8926 * single-step trap has been dropped. Let the 8927 * hypervisor know about the failure by executing a 8928 * VMCALL. 8929 */ 8930 vmcall(); 8931 } 8932 vmx_preemption_timer_tf_test_prev_rip = regs->rip; 8933 } 8934 8935 static void vmx_preemption_timer_tf_test_guest(void) 8936 { 8937 /* 8938 * The hypervisor doesn't intercept WBINVD, so the loop below 8939 * shouldn't be a problem--it's just two instructions 8940 * executing in VMX non-root mode. However, when the 8941 * hypervisor is running in a virtual environment, the parent 8942 * hypervisor might intercept WBINVD and emulate it. If the 8943 * parent hypervisor is broken, the single-step trap after the 8944 * WBINVD might be lost. 8945 */ 8946 asm volatile("vmcall\n\t" 8947 "0: wbinvd\n\t" 8948 "1: jmp 0b\n\t" 8949 "vmx_preemption_timer_tf_test_endloop:"); 8950 } 8951 8952 /* 8953 * Ensure that the delivery of a "VMX-preemption timer expired" 8954 * VM-exit doesn't disrupt single-stepping in the guest. Note that 8955 * passing this test doesn't ensure correctness, because the test will 8956 * only fail if the VMX-preemtion timer fires at the right time (or 8957 * the wrong time, as it were). 8958 */ 8959 static void vmx_preemption_timer_tf_test(void) 8960 { 8961 handler old_db; 8962 u32 reason; 8963 int i; 8964 8965 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 8966 report_skip("%s : \"Activate VMX-preemption timer\" pin control not supported", __func__); 8967 return; 8968 } 8969 8970 old_db = handle_exception(DB_VECTOR, 8971 vmx_preemption_timer_tf_test_db_handler); 8972 8973 test_set_guest(vmx_preemption_timer_tf_test_guest); 8974 8975 enter_guest(); 8976 skip_exit_vmcall(); 8977 8978 vmx_set_test_stage(1); 8979 vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT); 8980 vmcs_write(PREEMPT_TIMER_VALUE, 50000); 8981 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_TF); 8982 8983 /* 8984 * The only exit we should see is "VMX-preemption timer 8985 * expired." If we get a VMCALL exit, that means the #DB 8986 * handler has detected a missing single-step trap. It doesn't 8987 * matter where the guest RIP is when the VMX-preemption timer 8988 * expires (whether it's in the WBINVD loop or in the #DB 8989 * handler)--a single-step trap should never be discarded. 8990 */ 8991 for (i = 0; i < 10000; i++) { 8992 enter_guest(); 8993 reason = (u32)vmcs_read(EXI_REASON); 8994 if (reason == VMX_PREEMPT) 8995 continue; 8996 TEST_ASSERT(reason == VMX_VMCALL); 8997 skip_exit_insn(); 8998 break; 8999 } 9000 9001 report(reason == VMX_PREEMPT, "No single-step traps skipped"); 9002 9003 vmx_set_test_stage(2); 9004 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 9005 enter_guest(); 9006 9007 handle_exception(DB_VECTOR, old_db); 9008 } 9009 9010 #define VMX_PREEMPTION_TIMER_EXPIRY_CYCLES 1000000 9011 9012 static u64 vmx_preemption_timer_expiry_start; 9013 static u64 vmx_preemption_timer_expiry_finish; 9014 9015 static void vmx_preemption_timer_expiry_test_guest(void) 9016 { 9017 vmcall(); 9018 vmx_preemption_timer_expiry_start = fenced_rdtsc(); 9019 9020 while (vmx_get_test_stage() == 0) 9021 vmx_preemption_timer_expiry_finish = fenced_rdtsc(); 9022 } 9023 9024 /* 9025 * Test that the VMX-preemption timer is not excessively delayed. 9026 * 9027 * Per the SDM, volume 3, VM-entry starts the VMX-preemption timer 9028 * with the unsigned value in the VMX-preemption timer-value field, 9029 * and the VMX-preemption timer counts down by 1 every time bit X in 9030 * the TSC changes due to a TSC increment (where X is 9031 * IA32_VMX_MISC[4:0]). If the timer counts down to zero in any state 9032 * other than the wait-for-SIPI state, the logical processor 9033 * transitions to the C0 C-state and causes a VM-exit. 9034 * 9035 * The guest code above reads the starting TSC after VM-entry. At this 9036 * point, the VMX-preemption timer has already been activated. Next, 9037 * the guest code reads the current TSC in a loop, storing the value 9038 * read to memory. 9039 * 9040 * If the RDTSC in the loop reads a value past the VMX-preemption 9041 * timer deadline, then the VMX-preemption timer VM-exit must be 9042 * delivered before the next instruction retires. Even if a higher 9043 * priority SMI is delivered first, the VMX-preemption timer VM-exit 9044 * must be delivered before the next instruction retires. Hence, a TSC 9045 * value past the VMX-preemption timer deadline might be read, but it 9046 * cannot be stored. If a TSC value past the deadline *is* stored, 9047 * then the architectural specification has been violated. 9048 */ 9049 static void vmx_preemption_timer_expiry_test(void) 9050 { 9051 u32 preemption_timer_value; 9052 union vmx_misc misc; 9053 u64 tsc_deadline; 9054 u32 reason; 9055 9056 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 9057 report_skip("%s : \"Activate VMX-preemption timer\" pin control not supported", __func__); 9058 return; 9059 } 9060 9061 test_set_guest(vmx_preemption_timer_expiry_test_guest); 9062 9063 enter_guest(); 9064 skip_exit_vmcall(); 9065 9066 misc.val = rdmsr(MSR_IA32_VMX_MISC); 9067 preemption_timer_value = 9068 VMX_PREEMPTION_TIMER_EXPIRY_CYCLES >> misc.pt_bit; 9069 9070 vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT); 9071 vmcs_write(PREEMPT_TIMER_VALUE, preemption_timer_value); 9072 vmx_set_test_stage(0); 9073 9074 enter_guest(); 9075 reason = (u32)vmcs_read(EXI_REASON); 9076 TEST_ASSERT(reason == VMX_PREEMPT); 9077 9078 tsc_deadline = ((vmx_preemption_timer_expiry_start >> misc.pt_bit) << 9079 misc.pt_bit) + (preemption_timer_value << misc.pt_bit); 9080 9081 report(vmx_preemption_timer_expiry_finish < tsc_deadline, 9082 "Last stored guest TSC (%lu) < TSC deadline (%lu)", 9083 vmx_preemption_timer_expiry_finish, tsc_deadline); 9084 9085 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 9086 vmx_set_test_stage(1); 9087 enter_guest(); 9088 } 9089 9090 static void vmx_db_test_guest(void) 9091 { 9092 /* 9093 * For a hardware generated single-step #DB. 9094 */ 9095 asm volatile("vmcall;" 9096 "nop;" 9097 ".Lpost_nop:"); 9098 /* 9099 * ...in a MOVSS shadow, with pending debug exceptions. 9100 */ 9101 asm volatile("vmcall;" 9102 "nop;" 9103 ".Lpost_movss_nop:"); 9104 /* 9105 * For an L0 synthesized single-step #DB. (L0 intercepts WBINVD and 9106 * emulates it in software.) 9107 */ 9108 asm volatile("vmcall;" 9109 "wbinvd;" 9110 ".Lpost_wbinvd:"); 9111 /* 9112 * ...in a MOVSS shadow, with pending debug exceptions. 9113 */ 9114 asm volatile("vmcall;" 9115 "wbinvd;" 9116 ".Lpost_movss_wbinvd:"); 9117 /* 9118 * For a hardware generated single-step #DB in a transactional region. 9119 */ 9120 asm volatile("vmcall;" 9121 ".Lxbegin: xbegin .Lskip_rtm;" 9122 "xend;" 9123 ".Lskip_rtm:"); 9124 } 9125 9126 /* 9127 * Clear the pending debug exceptions and RFLAGS.TF and re-enter 9128 * L2. No #DB is delivered and L2 continues to the next point of 9129 * interest. 9130 */ 9131 static void dismiss_db(void) 9132 { 9133 vmcs_write(GUEST_PENDING_DEBUG, 0); 9134 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 9135 enter_guest(); 9136 } 9137 9138 /* 9139 * Check a variety of VMCS fields relevant to an intercepted #DB exception. 9140 * Then throw away the #DB exception and resume L2. 9141 */ 9142 static void check_db_exit(bool xfail_qual, bool xfail_dr6, bool xfail_pdbg, 9143 void *expected_rip, u64 expected_exit_qual, 9144 u64 expected_dr6) 9145 { 9146 u32 reason = vmcs_read(EXI_REASON); 9147 u32 intr_info = vmcs_read(EXI_INTR_INFO); 9148 u64 exit_qual = vmcs_read(EXI_QUALIFICATION); 9149 u64 guest_rip = vmcs_read(GUEST_RIP); 9150 u64 guest_pending_dbg = vmcs_read(GUEST_PENDING_DEBUG); 9151 u64 dr6 = read_dr6(); 9152 const u32 expected_intr_info = INTR_INFO_VALID_MASK | 9153 INTR_TYPE_HARD_EXCEPTION | DB_VECTOR; 9154 9155 report(reason == VMX_EXC_NMI && intr_info == expected_intr_info, 9156 "Expected #DB VM-exit"); 9157 report((u64)expected_rip == guest_rip, "Expected RIP %p (actual %lx)", 9158 expected_rip, guest_rip); 9159 report_xfail(xfail_pdbg, 0 == guest_pending_dbg, 9160 "Expected pending debug exceptions 0 (actual %lx)", 9161 guest_pending_dbg); 9162 report_xfail(xfail_qual, expected_exit_qual == exit_qual, 9163 "Expected exit qualification %lx (actual %lx)", 9164 expected_exit_qual, exit_qual); 9165 report_xfail(xfail_dr6, expected_dr6 == dr6, 9166 "Expected DR6 %lx (actual %lx)", expected_dr6, dr6); 9167 dismiss_db(); 9168 } 9169 9170 /* 9171 * Assuming the guest has just exited on a VMCALL instruction, skip 9172 * over the vmcall, and set the guest's RFLAGS.TF in the VMCS. If 9173 * pending debug exceptions are non-zero, set the VMCS up as if the 9174 * previous instruction was a MOVSS that generated the indicated 9175 * pending debug exceptions. Then enter L2. 9176 */ 9177 static void single_step_guest(const char *test_name, u64 starting_dr6, 9178 u64 pending_debug_exceptions) 9179 { 9180 printf("\n%s\n", test_name); 9181 skip_exit_vmcall(); 9182 write_dr6(starting_dr6); 9183 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_TF); 9184 if (pending_debug_exceptions) { 9185 vmcs_write(GUEST_PENDING_DEBUG, pending_debug_exceptions); 9186 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 9187 } 9188 enter_guest(); 9189 } 9190 9191 /* 9192 * When L1 intercepts #DB, verify that a single-step trap clears 9193 * pending debug exceptions, populates the exit qualification field 9194 * properly, and that DR6 is not prematurely clobbered. In a 9195 * (simulated) MOVSS shadow, make sure that the pending debug 9196 * exception bits are properly accumulated into the exit qualification 9197 * field. 9198 */ 9199 static void vmx_db_test(void) 9200 { 9201 /* 9202 * We are going to set a few arbitrary bits in DR6 to verify that 9203 * (a) DR6 is not modified by an intercepted #DB, and 9204 * (b) stale bits in DR6 (DR6.BD, in particular) don't leak into 9205 * the exit qualification field for a subsequent #DB exception. 9206 */ 9207 const u64 starting_dr6 = DR6_ACTIVE_LOW | DR6_BS | DR6_TRAP3 | DR6_TRAP1; 9208 extern char post_nop asm(".Lpost_nop"); 9209 extern char post_movss_nop asm(".Lpost_movss_nop"); 9210 extern char post_wbinvd asm(".Lpost_wbinvd"); 9211 extern char post_movss_wbinvd asm(".Lpost_movss_wbinvd"); 9212 extern char xbegin asm(".Lxbegin"); 9213 extern char skip_rtm asm(".Lskip_rtm"); 9214 9215 /* 9216 * L1 wants to intercept #DB exceptions encountered in L2. 9217 */ 9218 vmcs_write(EXC_BITMAP, BIT(DB_VECTOR)); 9219 9220 /* 9221 * Start L2 and run it up to the first point of interest. 9222 */ 9223 test_set_guest(vmx_db_test_guest); 9224 enter_guest(); 9225 9226 /* 9227 * Hardware-delivered #DB trap for single-step sets the 9228 * standard that L0 has to follow for emulated instructions. 9229 */ 9230 single_step_guest("Hardware delivered single-step", starting_dr6, 0); 9231 check_db_exit(false, false, false, &post_nop, DR6_BS, starting_dr6); 9232 9233 /* 9234 * Hardware-delivered #DB trap for single-step in MOVSS shadow 9235 * also sets the standard that L0 has to follow for emulated 9236 * instructions. Here, we establish the VMCS pending debug 9237 * exceptions to indicate that the simulated MOVSS triggered a 9238 * data breakpoint as well as the single-step trap. 9239 */ 9240 single_step_guest("Hardware delivered single-step in MOVSS shadow", 9241 starting_dr6, DR6_BS | PENDING_DBG_TRAP | DR6_TRAP0); 9242 check_db_exit(false, false, false, &post_movss_nop, DR6_BS | DR6_TRAP0, 9243 starting_dr6); 9244 9245 /* 9246 * L0 synthesized #DB trap for single-step is buggy, because 9247 * kvm (a) clobbers DR6 too early, and (b) tries its best to 9248 * reconstitute the exit qualification from the prematurely 9249 * modified DR6, but fails miserably. 9250 */ 9251 single_step_guest("Software synthesized single-step", starting_dr6, 0); 9252 check_db_exit(false, false, false, &post_wbinvd, DR6_BS, starting_dr6); 9253 9254 /* 9255 * L0 synthesized #DB trap for single-step in MOVSS shadow is 9256 * even worse, because L0 also leaves the pending debug 9257 * exceptions in the VMCS instead of accumulating them into 9258 * the exit qualification field for the #DB exception. 9259 */ 9260 single_step_guest("Software synthesized single-step in MOVSS shadow", 9261 starting_dr6, DR6_BS | PENDING_DBG_TRAP | DR6_TRAP0); 9262 check_db_exit(true, false, true, &post_movss_wbinvd, DR6_BS | DR6_TRAP0, 9263 starting_dr6); 9264 9265 /* 9266 * Optional RTM test for hardware that supports RTM, to 9267 * demonstrate that the current volume 3 of the SDM 9268 * (325384-067US), table 27-1 is incorrect. Bit 16 of the exit 9269 * qualification for debug exceptions is not reserved. It is 9270 * set to 1 if a debug exception (#DB) or a breakpoint 9271 * exception (#BP) occurs inside an RTM region while advanced 9272 * debugging of RTM transactional regions is enabled. 9273 */ 9274 if (this_cpu_has(X86_FEATURE_RTM)) { 9275 vmcs_write(ENT_CONTROLS, 9276 vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 9277 /* 9278 * Set DR7.RTM[bit 11] and IA32_DEBUGCTL.RTM[bit 15] 9279 * in the guest to enable advanced debugging of RTM 9280 * transactional regions. 9281 */ 9282 vmcs_write(GUEST_DR7, BIT(11)); 9283 vmcs_write(GUEST_DEBUGCTL, BIT(15)); 9284 single_step_guest("Hardware delivered single-step in " 9285 "transactional region", starting_dr6, 0); 9286 check_db_exit(false, false, false, &xbegin, BIT(16), 9287 starting_dr6); 9288 } else { 9289 vmcs_write(GUEST_RIP, (u64)&skip_rtm); 9290 enter_guest(); 9291 } 9292 } 9293 9294 static void enable_vid(void) 9295 { 9296 void *virtual_apic_page; 9297 9298 assert(cpu_has_apicv()); 9299 9300 disable_intercept_for_x2apic_msrs(); 9301 9302 virtual_apic_page = alloc_page(); 9303 vmcs_write(APIC_VIRT_ADDR, (u64)virtual_apic_page); 9304 9305 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 9306 9307 vmcs_write(EOI_EXIT_BITMAP0, 0x0); 9308 vmcs_write(EOI_EXIT_BITMAP1, 0x0); 9309 vmcs_write(EOI_EXIT_BITMAP2, 0x0); 9310 vmcs_write(EOI_EXIT_BITMAP3, 0x0); 9311 9312 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY | CPU_TPR_SHADOW); 9313 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_VINTD | CPU_VIRT_X2APIC); 9314 } 9315 9316 static void trigger_ioapic_scan_thread(void *data) 9317 { 9318 /* Wait until other CPU entered L2 */ 9319 while (vmx_get_test_stage() != 1) 9320 ; 9321 9322 /* Trigger ioapic scan */ 9323 ioapic_set_redir(0xf, 0x79, TRIGGER_LEVEL); 9324 vmx_set_test_stage(2); 9325 } 9326 9327 static void irq_79_handler_guest(isr_regs_t *regs) 9328 { 9329 eoi(); 9330 9331 /* L1 expects vmexit on VMX_VMCALL and not VMX_EOI_INDUCED */ 9332 vmcall(); 9333 } 9334 9335 /* 9336 * Constant for num of busy-loop iterations after which 9337 * a timer interrupt should have happened in host 9338 */ 9339 #define TIMER_INTERRUPT_DELAY 100000000 9340 9341 static void vmx_eoi_bitmap_ioapic_scan_test_guest(void) 9342 { 9343 handle_irq(0x79, irq_79_handler_guest); 9344 sti(); 9345 9346 /* Signal to L1 CPU to trigger ioapic scan */ 9347 vmx_set_test_stage(1); 9348 /* Wait until L1 CPU to trigger ioapic scan */ 9349 while (vmx_get_test_stage() != 2) 9350 ; 9351 9352 /* 9353 * Wait for L0 timer interrupt to be raised while we run in L2 9354 * such that L0 will process the IOAPIC scan request before 9355 * resuming L2 9356 */ 9357 delay(TIMER_INTERRUPT_DELAY); 9358 9359 asm volatile ("int $0x79"); 9360 } 9361 9362 static void vmx_eoi_bitmap_ioapic_scan_test(void) 9363 { 9364 if (!cpu_has_apicv() || (cpu_count() < 2)) { 9365 report_skip("%s : Not all required APICv bits supported or CPU count < 2", __func__); 9366 return; 9367 } 9368 9369 enable_vid(); 9370 9371 on_cpu_async(1, trigger_ioapic_scan_thread, NULL); 9372 test_set_guest(vmx_eoi_bitmap_ioapic_scan_test_guest); 9373 9374 /* 9375 * Launch L2. 9376 * We expect the exit reason to be VMX_VMCALL (and not EOI INDUCED). 9377 * In case the reason isn't VMX_VMCALL, the assertion inside 9378 * skip_exit_vmcall() will fail. 9379 */ 9380 enter_guest(); 9381 skip_exit_vmcall(); 9382 9383 /* Let L2 finish */ 9384 enter_guest(); 9385 report_pass(__func__); 9386 } 9387 9388 #define HLT_WITH_RVI_VECTOR (0xf1) 9389 9390 bool vmx_hlt_with_rvi_guest_isr_fired; 9391 static void vmx_hlt_with_rvi_guest_isr(isr_regs_t *regs) 9392 { 9393 vmx_hlt_with_rvi_guest_isr_fired = true; 9394 eoi(); 9395 } 9396 9397 static void vmx_hlt_with_rvi_guest(void) 9398 { 9399 handle_irq(HLT_WITH_RVI_VECTOR, vmx_hlt_with_rvi_guest_isr); 9400 9401 sti_nop(); 9402 asm volatile ("nop"); 9403 9404 vmcall(); 9405 } 9406 9407 static void vmx_hlt_with_rvi_test(void) 9408 { 9409 if (!cpu_has_apicv()) { 9410 report_skip("%s : Not all required APICv bits supported", __func__); 9411 return; 9412 } 9413 9414 enable_vid(); 9415 9416 vmx_hlt_with_rvi_guest_isr_fired = false; 9417 test_set_guest(vmx_hlt_with_rvi_guest); 9418 9419 enter_guest(); 9420 skip_exit_vmcall(); 9421 9422 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 9423 vmcs_write(GUEST_INT_STATUS, HLT_WITH_RVI_VECTOR); 9424 enter_guest(); 9425 9426 report(vmx_hlt_with_rvi_guest_isr_fired, "Interrupt raised in guest"); 9427 } 9428 9429 static void set_irq_line_thread(void *data) 9430 { 9431 /* Wait until other CPU entered L2 */ 9432 while (vmx_get_test_stage() != 1) 9433 ; 9434 9435 /* Set irq-line 0xf to raise vector 0x78 for vCPU 0 */ 9436 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 9437 vmx_set_test_stage(2); 9438 } 9439 9440 static bool irq_78_handler_vmcall_before_eoi; 9441 static void irq_78_handler_guest(isr_regs_t *regs) 9442 { 9443 set_irq_line(0xf, 0); 9444 if (irq_78_handler_vmcall_before_eoi) 9445 vmcall(); 9446 eoi(); 9447 vmcall(); 9448 } 9449 9450 static void vmx_apic_passthrough_guest(void) 9451 { 9452 handle_irq(0x78, irq_78_handler_guest); 9453 sti(); 9454 9455 /* If requested, wait for other CPU to trigger ioapic scan */ 9456 if (vmx_get_test_stage() < 1) { 9457 vmx_set_test_stage(1); 9458 while (vmx_get_test_stage() != 2) 9459 ; 9460 } 9461 9462 set_irq_line(0xf, 1); 9463 } 9464 9465 static void vmx_apic_passthrough(bool set_irq_line_from_thread) 9466 { 9467 if (set_irq_line_from_thread && (cpu_count() < 2)) { 9468 report_skip("%s : CPU count < 2", __func__); 9469 return; 9470 } 9471 9472 /* Test device is required for generating IRQs */ 9473 if (!test_device_enabled()) { 9474 report_skip("%s : No test device enabled", __func__); 9475 return; 9476 } 9477 u64 cpu_ctrl_0 = CPU_SECONDARY; 9478 u64 cpu_ctrl_1 = 0; 9479 9480 disable_intercept_for_x2apic_msrs(); 9481 9482 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 9483 9484 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 9485 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 9486 9487 if (set_irq_line_from_thread) { 9488 irq_78_handler_vmcall_before_eoi = false; 9489 on_cpu_async(1, set_irq_line_thread, NULL); 9490 } else { 9491 irq_78_handler_vmcall_before_eoi = true; 9492 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 9493 vmx_set_test_stage(2); 9494 } 9495 test_set_guest(vmx_apic_passthrough_guest); 9496 9497 if (irq_78_handler_vmcall_before_eoi) { 9498 /* Before EOI remote_irr should still be set */ 9499 enter_guest(); 9500 skip_exit_vmcall(); 9501 TEST_ASSERT_EQ_MSG(1, (int)ioapic_read_redir(0xf).remote_irr, 9502 "IOAPIC pass-through: remote_irr=1 before EOI"); 9503 } 9504 9505 /* After EOI remote_irr should be cleared */ 9506 enter_guest(); 9507 skip_exit_vmcall(); 9508 TEST_ASSERT_EQ_MSG(0, (int)ioapic_read_redir(0xf).remote_irr, 9509 "IOAPIC pass-through: remote_irr=0 after EOI"); 9510 9511 /* Let L2 finish */ 9512 enter_guest(); 9513 report_pass(__func__); 9514 } 9515 9516 static void vmx_apic_passthrough_test(void) 9517 { 9518 vmx_apic_passthrough(false); 9519 } 9520 9521 static void vmx_apic_passthrough_thread_test(void) 9522 { 9523 vmx_apic_passthrough(true); 9524 } 9525 9526 static void vmx_apic_passthrough_tpr_threshold_guest(void) 9527 { 9528 cli(); 9529 apic_set_tpr(0); 9530 } 9531 9532 static bool vmx_apic_passthrough_tpr_threshold_ipi_isr_fired; 9533 static void vmx_apic_passthrough_tpr_threshold_ipi_isr(isr_regs_t *regs) 9534 { 9535 vmx_apic_passthrough_tpr_threshold_ipi_isr_fired = true; 9536 eoi(); 9537 } 9538 9539 static void vmx_apic_passthrough_tpr_threshold_test(void) 9540 { 9541 int ipi_vector = 0xe1; 9542 9543 disable_intercept_for_x2apic_msrs(); 9544 vmcs_clear_bits(PIN_CONTROLS, PIN_EXTINT); 9545 9546 /* Raise L0 TPR-threshold by queueing vector in LAPIC IRR */ 9547 cli(); 9548 apic_set_tpr((ipi_vector >> 4) + 1); 9549 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | 9550 APIC_DM_FIXED | ipi_vector, 9551 0); 9552 9553 test_set_guest(vmx_apic_passthrough_tpr_threshold_guest); 9554 enter_guest(); 9555 9556 report(apic_get_tpr() == 0, "TPR was zero by guest"); 9557 9558 /* Clean pending self-IPI */ 9559 vmx_apic_passthrough_tpr_threshold_ipi_isr_fired = false; 9560 handle_irq(ipi_vector, vmx_apic_passthrough_tpr_threshold_ipi_isr); 9561 sti_nop(); 9562 report(vmx_apic_passthrough_tpr_threshold_ipi_isr_fired, "self-IPI fired"); 9563 9564 report_pass(__func__); 9565 } 9566 9567 static u64 init_signal_test_exit_reason; 9568 static bool init_signal_test_thread_continued; 9569 9570 static void init_signal_test_thread(void *data) 9571 { 9572 struct vmcs *test_vmcs = data; 9573 9574 /* Enter VMX operation (i.e. exec VMXON) */ 9575 u64 *ap_vmxon_region = alloc_page(); 9576 enable_vmx(); 9577 init_vmx(ap_vmxon_region); 9578 TEST_ASSERT(!__vmxon_safe(ap_vmxon_region)); 9579 9580 /* Signal CPU have entered VMX operation */ 9581 vmx_set_test_stage(1); 9582 9583 /* Wait for BSP CPU to send INIT signal */ 9584 while (vmx_get_test_stage() != 2) 9585 ; 9586 9587 /* 9588 * Signal that we continue as usual as INIT signal 9589 * should be blocked while CPU is in VMX operation 9590 */ 9591 vmx_set_test_stage(3); 9592 9593 /* Wait for signal to enter VMX non-root mode */ 9594 while (vmx_get_test_stage() != 4) 9595 ; 9596 9597 /* Enter VMX non-root mode */ 9598 test_set_guest(v2_null_test_guest); 9599 make_vmcs_current(test_vmcs); 9600 enter_guest(); 9601 /* Save exit reason for BSP CPU to compare to expected result */ 9602 init_signal_test_exit_reason = vmcs_read(EXI_REASON); 9603 /* VMCLEAR test-vmcs so it could be loaded by BSP CPU */ 9604 vmcs_clear(test_vmcs); 9605 launched = false; 9606 /* Signal that CPU exited to VMX root mode */ 9607 vmx_set_test_stage(5); 9608 9609 /* Wait for BSP CPU to signal to exit VMX operation */ 9610 while (vmx_get_test_stage() != 6) 9611 ; 9612 9613 /* Exit VMX operation (i.e. exec VMXOFF) */ 9614 vmx_off(); 9615 9616 /* 9617 * Signal to BSP CPU that we continue as usual as INIT signal 9618 * should have been consumed by VMX_INIT exit from guest 9619 */ 9620 vmx_set_test_stage(7); 9621 9622 /* Wait for BSP CPU to signal to enter VMX operation */ 9623 while (vmx_get_test_stage() != 8) 9624 ; 9625 /* Enter VMX operation (i.e. exec VMXON) */ 9626 TEST_ASSERT(!__vmxon_safe(ap_vmxon_region)); 9627 /* Signal to BSP we are in VMX operation */ 9628 vmx_set_test_stage(9); 9629 9630 /* Wait for BSP CPU to send INIT signal */ 9631 while (vmx_get_test_stage() != 10) 9632 ; 9633 9634 /* Exit VMX operation (i.e. exec VMXOFF) */ 9635 vmx_off(); 9636 9637 /* 9638 * Exiting VMX operation should result in latched 9639 * INIT signal being processed. Therefore, we should 9640 * never reach the below code. Thus, signal to BSP 9641 * CPU if we have reached here so it is able to 9642 * report an issue if it happens. 9643 */ 9644 init_signal_test_thread_continued = true; 9645 } 9646 9647 #define INIT_SIGNAL_TEST_DELAY 100000000ULL 9648 9649 static void vmx_init_signal_test(void) 9650 { 9651 struct vmcs *test_vmcs; 9652 9653 if (cpu_count() < 2) { 9654 report_skip("%s : CPU count < 2", __func__); 9655 return; 9656 } 9657 9658 /* VMCLEAR test-vmcs so it could be loaded by other CPU */ 9659 vmcs_save(&test_vmcs); 9660 vmcs_clear(test_vmcs); 9661 9662 vmx_set_test_stage(0); 9663 on_cpu_async(1, init_signal_test_thread, test_vmcs); 9664 9665 /* Wait for other CPU to enter VMX operation */ 9666 while (vmx_get_test_stage() != 1) 9667 ; 9668 9669 /* Send INIT signal to other CPU */ 9670 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_INIT | APIC_INT_ASSERT, 9671 id_map[1]); 9672 /* Signal other CPU we have sent INIT signal */ 9673 vmx_set_test_stage(2); 9674 9675 /* 9676 * Wait reasonable amount of time for INIT signal to 9677 * be received on other CPU and verify that other CPU 9678 * have proceed as usual to next test stage as INIT 9679 * signal should be blocked while other CPU in 9680 * VMX operation 9681 */ 9682 delay(INIT_SIGNAL_TEST_DELAY); 9683 report(vmx_get_test_stage() == 3, 9684 "INIT signal blocked when CPU in VMX operation"); 9685 /* No point to continue if we failed at this point */ 9686 if (vmx_get_test_stage() != 3) 9687 return; 9688 9689 /* Signal other CPU to enter VMX non-root mode */ 9690 init_signal_test_exit_reason = -1ull; 9691 vmx_set_test_stage(4); 9692 /* 9693 * Wait reasonable amount of time for other CPU 9694 * to exit to VMX root mode 9695 */ 9696 delay(INIT_SIGNAL_TEST_DELAY); 9697 if (vmx_get_test_stage() != 5) { 9698 report_fail("Pending INIT signal didn't result in VMX exit"); 9699 return; 9700 } 9701 report(init_signal_test_exit_reason == VMX_INIT, 9702 "INIT signal during VMX non-root mode result in exit-reason %s (%lu)", 9703 exit_reason_description(init_signal_test_exit_reason), 9704 init_signal_test_exit_reason); 9705 9706 /* Run guest to completion */ 9707 make_vmcs_current(test_vmcs); 9708 enter_guest(); 9709 9710 /* Signal other CPU to exit VMX operation */ 9711 init_signal_test_thread_continued = false; 9712 vmx_set_test_stage(6); 9713 9714 /* Wait reasonable amount of time for other CPU to exit VMX operation */ 9715 delay(INIT_SIGNAL_TEST_DELAY); 9716 report(vmx_get_test_stage() == 7, 9717 "INIT signal consumed on VMX_INIT exit"); 9718 /* No point to continue if we failed at this point */ 9719 if (vmx_get_test_stage() != 7) 9720 return; 9721 9722 /* Signal other CPU to enter VMX operation */ 9723 vmx_set_test_stage(8); 9724 /* Wait for other CPU to enter VMX operation */ 9725 while (vmx_get_test_stage() != 9) 9726 ; 9727 9728 /* Send INIT signal to other CPU */ 9729 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_INIT | APIC_INT_ASSERT, 9730 id_map[1]); 9731 /* Signal other CPU we have sent INIT signal */ 9732 vmx_set_test_stage(10); 9733 9734 /* 9735 * Wait reasonable amount of time for other CPU 9736 * to exit VMX operation and process INIT signal 9737 */ 9738 delay(INIT_SIGNAL_TEST_DELAY); 9739 report(!init_signal_test_thread_continued, 9740 "INIT signal processed after exit VMX operation"); 9741 9742 /* 9743 * TODO: Send SIPI to other CPU to sipi_entry (See x86/cstart64.S) 9744 * to re-init it to kvm-unit-tests standard environment. 9745 * Somehow (?) verify that SIPI was indeed received. 9746 */ 9747 } 9748 9749 #define SIPI_SIGNAL_TEST_DELAY 100000000ULL 9750 9751 static void vmx_sipi_test_guest(void) 9752 { 9753 if (apic_id() == 0) { 9754 /* wait AP enter guest with activity=WAIT_SIPI */ 9755 while (vmx_get_test_stage() != 1) 9756 ; 9757 delay(SIPI_SIGNAL_TEST_DELAY); 9758 9759 /* First SIPI signal */ 9760 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_STARTUP | APIC_INT_ASSERT, id_map[1]); 9761 report_pass("BSP(L2): Send first SIPI to cpu[%d]", id_map[1]); 9762 9763 /* wait AP enter guest */ 9764 while (vmx_get_test_stage() != 2) 9765 ; 9766 delay(SIPI_SIGNAL_TEST_DELAY); 9767 9768 /* Second SIPI signal should be ignored since AP is not in WAIT_SIPI state */ 9769 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_STARTUP | APIC_INT_ASSERT, id_map[1]); 9770 report_pass("BSP(L2): Send second SIPI to cpu[%d]", id_map[1]); 9771 9772 /* Delay a while to check whether second SIPI would cause VMExit */ 9773 delay(SIPI_SIGNAL_TEST_DELAY); 9774 9775 /* Test is done, notify AP to exit test */ 9776 vmx_set_test_stage(3); 9777 9778 /* wait AP exit non-root mode */ 9779 while (vmx_get_test_stage() != 5) 9780 ; 9781 } else { 9782 /* wait BSP notify test is done */ 9783 while (vmx_get_test_stage() != 3) 9784 ; 9785 9786 /* AP exit guest */ 9787 vmx_set_test_stage(4); 9788 } 9789 } 9790 9791 static void sipi_test_ap_thread(void *data) 9792 { 9793 struct vmcs *ap_vmcs; 9794 u64 *ap_vmxon_region; 9795 void *ap_stack, *ap_syscall_stack; 9796 u64 cpu_ctrl_0 = CPU_SECONDARY; 9797 u64 cpu_ctrl_1 = 0; 9798 9799 /* Enter VMX operation (i.e. exec VMXON) */ 9800 ap_vmxon_region = alloc_page(); 9801 enable_vmx(); 9802 init_vmx(ap_vmxon_region); 9803 TEST_ASSERT(!__vmxon_safe(ap_vmxon_region)); 9804 init_vmcs(&ap_vmcs); 9805 make_vmcs_current(ap_vmcs); 9806 9807 /* Set stack for AP */ 9808 ap_stack = alloc_page(); 9809 ap_syscall_stack = alloc_page(); 9810 vmcs_write(GUEST_RSP, (u64)(ap_stack + PAGE_SIZE - 1)); 9811 vmcs_write(GUEST_SYSENTER_ESP, (u64)(ap_syscall_stack + PAGE_SIZE - 1)); 9812 9813 /* passthrough lapic to L2 */ 9814 disable_intercept_for_x2apic_msrs(); 9815 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 9816 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 9817 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 9818 9819 /* Set guest activity state to wait-for-SIPI state */ 9820 vmcs_write(GUEST_ACTV_STATE, ACTV_WAIT_SIPI); 9821 9822 vmx_set_test_stage(1); 9823 9824 /* AP enter guest */ 9825 enter_guest(); 9826 9827 if (vmcs_read(EXI_REASON) == VMX_SIPI) { 9828 report_pass("AP: Handle SIPI VMExit"); 9829 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 9830 vmx_set_test_stage(2); 9831 } else { 9832 report_fail("AP: Unexpected VMExit, reason=%ld", vmcs_read(EXI_REASON)); 9833 vmx_off(); 9834 return; 9835 } 9836 9837 /* AP enter guest */ 9838 enter_guest(); 9839 9840 report(vmcs_read(EXI_REASON) != VMX_SIPI, 9841 "AP: should no SIPI VMExit since activity is not in WAIT_SIPI state"); 9842 9843 /* notify BSP that AP is already exit from non-root mode */ 9844 vmx_set_test_stage(5); 9845 9846 /* Leave VMX operation */ 9847 vmx_off(); 9848 } 9849 9850 static void vmx_sipi_signal_test(void) 9851 { 9852 if (!(rdmsr(MSR_IA32_VMX_MISC) & MSR_IA32_VMX_MISC_ACTIVITY_WAIT_SIPI)) { 9853 report_skip("%s : \"ACTIVITY_WAIT_SIPI state\" not supported", __func__); 9854 return; 9855 } 9856 9857 if (cpu_count() < 2) { 9858 report_skip("%s : CPU count < 2", __func__); 9859 return; 9860 } 9861 9862 u64 cpu_ctrl_0 = CPU_SECONDARY; 9863 u64 cpu_ctrl_1 = 0; 9864 9865 /* passthrough lapic to L2 */ 9866 disable_intercept_for_x2apic_msrs(); 9867 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 9868 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 9869 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 9870 9871 test_set_guest(vmx_sipi_test_guest); 9872 9873 /* update CR3 on AP */ 9874 on_cpu(1, update_cr3, (void *)read_cr3()); 9875 9876 /* start AP */ 9877 on_cpu_async(1, sipi_test_ap_thread, NULL); 9878 9879 vmx_set_test_stage(0); 9880 9881 /* BSP enter guest */ 9882 enter_guest(); 9883 } 9884 9885 9886 enum vmcs_access { 9887 ACCESS_VMREAD, 9888 ACCESS_VMWRITE, 9889 ACCESS_NONE, 9890 }; 9891 9892 struct vmcs_shadow_test_common { 9893 enum vmcs_access op; 9894 enum Reason reason; 9895 u64 field; 9896 u64 value; 9897 u64 flags; 9898 u64 time; 9899 } l1_l2_common; 9900 9901 static inline u64 vmread_flags(u64 field, u64 *val) 9902 { 9903 u64 flags; 9904 9905 asm volatile ("vmread %2, %1; pushf; pop %0" 9906 : "=r" (flags), "=rm" (*val) : "r" (field) : "cc"); 9907 return flags & X86_EFLAGS_ALU; 9908 } 9909 9910 static inline u64 vmwrite_flags(u64 field, u64 val) 9911 { 9912 u64 flags; 9913 9914 asm volatile ("vmwrite %1, %2; pushf; pop %0" 9915 : "=r"(flags) : "rm" (val), "r" (field) : "cc"); 9916 return flags & X86_EFLAGS_ALU; 9917 } 9918 9919 static void vmx_vmcs_shadow_test_guest(void) 9920 { 9921 struct vmcs_shadow_test_common *c = &l1_l2_common; 9922 u64 start; 9923 9924 while (c->op != ACCESS_NONE) { 9925 start = rdtsc(); 9926 switch (c->op) { 9927 default: 9928 c->flags = -1ull; 9929 break; 9930 case ACCESS_VMREAD: 9931 c->flags = vmread_flags(c->field, &c->value); 9932 break; 9933 case ACCESS_VMWRITE: 9934 c->flags = vmwrite_flags(c->field, 0); 9935 break; 9936 } 9937 c->time = rdtsc() - start; 9938 vmcall(); 9939 } 9940 } 9941 9942 static u64 vmread_from_shadow(u64 field) 9943 { 9944 struct vmcs *primary; 9945 struct vmcs *shadow; 9946 u64 value; 9947 9948 TEST_ASSERT(!vmcs_save(&primary)); 9949 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 9950 TEST_ASSERT(!make_vmcs_current(shadow)); 9951 value = vmcs_read(field); 9952 TEST_ASSERT(!make_vmcs_current(primary)); 9953 return value; 9954 } 9955 9956 static u64 vmwrite_to_shadow(u64 field, u64 value) 9957 { 9958 struct vmcs *primary; 9959 struct vmcs *shadow; 9960 9961 TEST_ASSERT(!vmcs_save(&primary)); 9962 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 9963 TEST_ASSERT(!make_vmcs_current(shadow)); 9964 vmcs_write(field, value); 9965 value = vmcs_read(field); 9966 TEST_ASSERT(!make_vmcs_current(primary)); 9967 return value; 9968 } 9969 9970 static void vmcs_shadow_test_access(u8 *bitmap[2], enum vmcs_access access) 9971 { 9972 struct vmcs_shadow_test_common *c = &l1_l2_common; 9973 9974 c->op = access; 9975 vmcs_write(VMX_INST_ERROR, 0); 9976 enter_guest(); 9977 c->reason = vmcs_read(EXI_REASON) & 0xffff; 9978 if (c->reason != VMX_VMCALL) { 9979 skip_exit_insn(); 9980 enter_guest(); 9981 } 9982 skip_exit_vmcall(); 9983 } 9984 9985 static void vmcs_shadow_test_field(u8 *bitmap[2], u64 field) 9986 { 9987 struct vmcs_shadow_test_common *c = &l1_l2_common; 9988 struct vmcs *shadow; 9989 u64 value; 9990 uintptr_t flags[2]; 9991 bool good_shadow; 9992 u32 vmx_inst_error; 9993 9994 report_prefix_pushf("field %lx", field); 9995 c->field = field; 9996 9997 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 9998 if (shadow != (struct vmcs *)-1ull) { 9999 flags[ACCESS_VMREAD] = vmread_flags(field, &value); 10000 flags[ACCESS_VMWRITE] = vmwrite_flags(field, value); 10001 good_shadow = !flags[ACCESS_VMREAD] && !flags[ACCESS_VMWRITE]; 10002 } else { 10003 /* 10004 * When VMCS link pointer is -1ull, VMWRITE/VMREAD on 10005 * shadowed-fields should fail with setting RFLAGS.CF. 10006 */ 10007 flags[ACCESS_VMREAD] = X86_EFLAGS_CF; 10008 flags[ACCESS_VMWRITE] = X86_EFLAGS_CF; 10009 good_shadow = false; 10010 } 10011 10012 /* Intercept both VMREAD and VMWRITE. */ 10013 report_prefix_push("no VMREAD/VMWRITE permission"); 10014 /* VMWRITE/VMREAD done on reserved-bit should always intercept */ 10015 if (!(field >> VMCS_FIELD_RESERVED_SHIFT)) { 10016 set_bit(field, bitmap[ACCESS_VMREAD]); 10017 set_bit(field, bitmap[ACCESS_VMWRITE]); 10018 } 10019 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10020 report(c->reason == VMX_VMWRITE, "not shadowed for VMWRITE"); 10021 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10022 report(c->reason == VMX_VMREAD, "not shadowed for VMREAD"); 10023 report_prefix_pop(); 10024 10025 if (field >> VMCS_FIELD_RESERVED_SHIFT) 10026 goto out; 10027 10028 /* Permit shadowed VMREAD. */ 10029 report_prefix_push("VMREAD permission only"); 10030 clear_bit(field, bitmap[ACCESS_VMREAD]); 10031 set_bit(field, bitmap[ACCESS_VMWRITE]); 10032 if (good_shadow) 10033 value = vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 10034 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10035 report(c->reason == VMX_VMWRITE, "not shadowed for VMWRITE"); 10036 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10037 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10038 report(c->reason == VMX_VMCALL, "shadowed for VMREAD (in %ld cycles)", 10039 c->time); 10040 report(c->flags == flags[ACCESS_VMREAD], 10041 "ALU flags after VMREAD (%lx) are as expected (%lx)", 10042 c->flags, flags[ACCESS_VMREAD]); 10043 if (good_shadow) 10044 report(c->value == value, 10045 "value read from shadow (%lx) is as expected (%lx)", 10046 c->value, value); 10047 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 10048 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10049 "VMX_INST_ERROR (%d) is as expected (%d)", 10050 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10051 report_prefix_pop(); 10052 10053 /* Permit shadowed VMWRITE. */ 10054 report_prefix_push("VMWRITE permission only"); 10055 set_bit(field, bitmap[ACCESS_VMREAD]); 10056 clear_bit(field, bitmap[ACCESS_VMWRITE]); 10057 if (good_shadow) 10058 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 10059 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10060 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10061 report(c->reason == VMX_VMCALL, 10062 "shadowed for VMWRITE (in %ld cycles)", 10063 c->time); 10064 report(c->flags == flags[ACCESS_VMREAD], 10065 "ALU flags after VMWRITE (%lx) are as expected (%lx)", 10066 c->flags, flags[ACCESS_VMREAD]); 10067 if (good_shadow) { 10068 value = vmread_from_shadow(field); 10069 report(value == 0, 10070 "shadow VMCS value (%lx) is as expected (%lx)", value, 10071 0ul); 10072 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 10073 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10074 "VMX_INST_ERROR (%d) is as expected (%d)", 10075 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10076 } 10077 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10078 report(c->reason == VMX_VMREAD, "not shadowed for VMREAD"); 10079 report_prefix_pop(); 10080 10081 /* Permit shadowed VMREAD and VMWRITE. */ 10082 report_prefix_push("VMREAD and VMWRITE permission"); 10083 clear_bit(field, bitmap[ACCESS_VMREAD]); 10084 clear_bit(field, bitmap[ACCESS_VMWRITE]); 10085 if (good_shadow) 10086 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 10087 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10088 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10089 report(c->reason == VMX_VMCALL, 10090 "shadowed for VMWRITE (in %ld cycles)", 10091 c->time); 10092 report(c->flags == flags[ACCESS_VMREAD], 10093 "ALU flags after VMWRITE (%lx) are as expected (%lx)", 10094 c->flags, flags[ACCESS_VMREAD]); 10095 if (good_shadow) { 10096 value = vmread_from_shadow(field); 10097 report(value == 0, 10098 "shadow VMCS value (%lx) is as expected (%lx)", value, 10099 0ul); 10100 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 10101 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10102 "VMX_INST_ERROR (%d) is as expected (%d)", 10103 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10104 } 10105 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10106 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10107 report(c->reason == VMX_VMCALL, "shadowed for VMREAD (in %ld cycles)", 10108 c->time); 10109 report(c->flags == flags[ACCESS_VMREAD], 10110 "ALU flags after VMREAD (%lx) are as expected (%lx)", 10111 c->flags, flags[ACCESS_VMREAD]); 10112 if (good_shadow) 10113 report(c->value == 0, 10114 "value read from shadow (%lx) is as expected (%lx)", 10115 c->value, 0ul); 10116 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 10117 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10118 "VMX_INST_ERROR (%d) is as expected (%d)", 10119 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10120 report_prefix_pop(); 10121 10122 out: 10123 report_prefix_pop(); 10124 } 10125 10126 static void vmx_vmcs_shadow_test_body(u8 *bitmap[2]) 10127 { 10128 unsigned base; 10129 unsigned index; 10130 unsigned bit; 10131 unsigned highest_index = rdmsr(MSR_IA32_VMX_VMCS_ENUM); 10132 10133 /* Run test on all possible valid VMCS fields */ 10134 for (base = 0; 10135 base < (1 << VMCS_FIELD_RESERVED_SHIFT); 10136 base += (1 << VMCS_FIELD_TYPE_SHIFT)) 10137 for (index = 0; index <= highest_index; index++) 10138 vmcs_shadow_test_field(bitmap, base + index); 10139 10140 /* 10141 * Run tests on some invalid VMCS fields 10142 * (Have reserved bit set). 10143 */ 10144 for (bit = VMCS_FIELD_RESERVED_SHIFT; bit < VMCS_FIELD_BIT_SIZE; bit++) 10145 vmcs_shadow_test_field(bitmap, (1ull << bit)); 10146 } 10147 10148 static void vmx_vmcs_shadow_test(void) 10149 { 10150 u8 *bitmap[2]; 10151 struct vmcs *shadow; 10152 10153 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 10154 report_skip("%s : \"Activate secondary controls\" not supported", __func__); 10155 return; 10156 } 10157 10158 if (!(ctrl_cpu_rev[1].clr & CPU_SHADOW_VMCS)) { 10159 report_skip("%s : \"VMCS shadowing\" not supported", __func__); 10160 return; 10161 } 10162 10163 if (!(rdmsr(MSR_IA32_VMX_MISC) & 10164 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS)) { 10165 report_skip("%s : VMWRITE can't modify VM-exit information fields.", __func__); 10166 return; 10167 } 10168 10169 test_set_guest(vmx_vmcs_shadow_test_guest); 10170 10171 bitmap[ACCESS_VMREAD] = alloc_page(); 10172 bitmap[ACCESS_VMWRITE] = alloc_page(); 10173 10174 vmcs_write(VMREAD_BITMAP, virt_to_phys(bitmap[ACCESS_VMREAD])); 10175 vmcs_write(VMWRITE_BITMAP, virt_to_phys(bitmap[ACCESS_VMWRITE])); 10176 10177 shadow = alloc_page(); 10178 shadow->hdr.revision_id = basic.revision; 10179 shadow->hdr.shadow_vmcs = 1; 10180 TEST_ASSERT(!vmcs_clear(shadow)); 10181 10182 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_RDTSC); 10183 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY); 10184 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_SHADOW_VMCS); 10185 10186 vmcs_write(VMCS_LINK_PTR, virt_to_phys(shadow)); 10187 report_prefix_push("valid link pointer"); 10188 vmx_vmcs_shadow_test_body(bitmap); 10189 report_prefix_pop(); 10190 10191 vmcs_write(VMCS_LINK_PTR, -1ull); 10192 report_prefix_push("invalid link pointer"); 10193 vmx_vmcs_shadow_test_body(bitmap); 10194 report_prefix_pop(); 10195 10196 l1_l2_common.op = ACCESS_NONE; 10197 enter_guest(); 10198 } 10199 10200 /* 10201 * This test monitors the difference between a guest RDTSC instruction 10202 * and the IA32_TIME_STAMP_COUNTER MSR value stored in the VMCS12 10203 * VM-exit MSR-store list when taking a VM-exit on the instruction 10204 * following RDTSC. 10205 */ 10206 #define RDTSC_DIFF_ITERS 100000 10207 #define RDTSC_DIFF_FAILS 100 10208 #define HOST_CAPTURED_GUEST_TSC_DIFF_THRESHOLD 750 10209 10210 /* 10211 * Set 'use TSC offsetting' and set the guest offset to the 10212 * inverse of the host's current TSC value, so that the guest starts running 10213 * with an effective TSC value of 0. 10214 */ 10215 static void reset_guest_tsc_to_zero(void) 10216 { 10217 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_USE_TSC_OFFSET); 10218 vmcs_write(TSC_OFFSET, -rdtsc()); 10219 } 10220 10221 static void rdtsc_vmexit_diff_test_guest(void) 10222 { 10223 int i; 10224 10225 for (i = 0; i < RDTSC_DIFF_ITERS; i++) 10226 /* Ensure rdtsc is the last instruction before the vmcall. */ 10227 asm volatile("rdtsc; vmcall" : : : "eax", "edx"); 10228 } 10229 10230 /* 10231 * This function only considers the "use TSC offsetting" VM-execution 10232 * control. It does not handle "use TSC scaling" (because the latter 10233 * isn't available to the host today.) 10234 */ 10235 static unsigned long long host_time_to_guest_time(unsigned long long t) 10236 { 10237 TEST_ASSERT(!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 10238 !(vmcs_read(CPU_EXEC_CTRL1) & CPU_USE_TSC_SCALING)); 10239 10240 if (vmcs_read(CPU_EXEC_CTRL0) & CPU_USE_TSC_OFFSET) 10241 t += vmcs_read(TSC_OFFSET); 10242 10243 return t; 10244 } 10245 10246 static unsigned long long rdtsc_vmexit_diff_test_iteration(void) 10247 { 10248 unsigned long long guest_tsc, host_to_guest_tsc; 10249 10250 enter_guest(); 10251 skip_exit_vmcall(); 10252 guest_tsc = (u32) regs.rax + (regs.rdx << 32); 10253 host_to_guest_tsc = host_time_to_guest_time(exit_msr_store[0].value); 10254 10255 return host_to_guest_tsc - guest_tsc; 10256 } 10257 10258 static void rdtsc_vmexit_diff_test(void) 10259 { 10260 unsigned long long delta; 10261 int fail = 0; 10262 int i; 10263 10264 if (!(ctrl_cpu_rev[0].clr & CPU_USE_TSC_OFFSET)) 10265 test_skip("CPU doesn't support the 'use TSC offsetting' processor-based VM-execution control.\n"); 10266 10267 test_set_guest(rdtsc_vmexit_diff_test_guest); 10268 10269 reset_guest_tsc_to_zero(); 10270 10271 /* 10272 * Set up the VMCS12 VM-exit MSR-store list to store just one 10273 * MSR: IA32_TIME_STAMP_COUNTER. Note that the value stored is 10274 * in the host time domain (i.e., it is not adjusted according 10275 * to the TSC multiplier and TSC offset fields in the VMCS12, 10276 * as a guest RDTSC would be.) 10277 */ 10278 exit_msr_store = alloc_page(); 10279 exit_msr_store[0].index = MSR_IA32_TSC; 10280 vmcs_write(EXI_MSR_ST_CNT, 1); 10281 vmcs_write(EXIT_MSR_ST_ADDR, virt_to_phys(exit_msr_store)); 10282 10283 for (i = 0; i < RDTSC_DIFF_ITERS && fail < RDTSC_DIFF_FAILS; i++) { 10284 delta = rdtsc_vmexit_diff_test_iteration(); 10285 if (delta >= HOST_CAPTURED_GUEST_TSC_DIFF_THRESHOLD) 10286 fail++; 10287 } 10288 10289 enter_guest(); 10290 10291 report(fail < RDTSC_DIFF_FAILS, 10292 "RDTSC to VM-exit delta too high in %d of %d iterations, last = %llu", 10293 fail, i, delta); 10294 } 10295 10296 static int invalid_msr_init(struct vmcs *vmcs) 10297 { 10298 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 10299 printf("\tPreemption timer is not supported\n"); 10300 return VMX_TEST_EXIT; 10301 } 10302 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 10303 preempt_val = 10000000; 10304 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 10305 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 10306 10307 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 10308 printf("\tSave preemption value is not supported\n"); 10309 10310 vmcs_write(ENT_MSR_LD_CNT, 1); 10311 vmcs_write(ENTER_MSR_LD_ADDR, (u64)0x13370000); 10312 10313 return VMX_TEST_START; 10314 } 10315 10316 10317 static void invalid_msr_main(void) 10318 { 10319 report_fail("Invalid MSR load"); 10320 } 10321 10322 static int invalid_msr_exit_handler(union exit_reason exit_reason) 10323 { 10324 report_fail("Invalid MSR load"); 10325 print_vmexit_info(exit_reason); 10326 return VMX_TEST_EXIT; 10327 } 10328 10329 static int invalid_msr_entry_failure(struct vmentry_result *result) 10330 { 10331 report(result->exit_reason.failed_vmentry && 10332 result->exit_reason.basic == VMX_FAIL_MSR, "Invalid MSR load"); 10333 return VMX_TEST_VMEXIT; 10334 } 10335 10336 /* 10337 * The max number of MSRs in an atomic switch MSR list is: 10338 * (111B + 1) * 512 = 4096 10339 * 10340 * Each list entry consumes: 10341 * 4-byte MSR index + 4 bytes reserved + 8-byte data = 16 bytes 10342 * 10343 * Allocate 128 kB to cover max_msr_list_size (i.e., 64 kB) and then some. 10344 */ 10345 static const u32 msr_list_page_order = 5; 10346 10347 static void atomic_switch_msr_limit_test_guest(void) 10348 { 10349 vmcall(); 10350 } 10351 10352 static void populate_msr_list(struct vmx_msr_entry *msr_list, 10353 size_t byte_capacity, int count) 10354 { 10355 int i; 10356 10357 for (i = 0; i < count; i++) { 10358 msr_list[i].index = MSR_IA32_TSC; 10359 msr_list[i].reserved = 0; 10360 msr_list[i].value = 0x1234567890abcdef; 10361 } 10362 10363 memset(msr_list + count, 0xff, 10364 byte_capacity - count * sizeof(*msr_list)); 10365 } 10366 10367 static int max_msr_list_size(void) 10368 { 10369 u32 vmx_misc = rdmsr(MSR_IA32_VMX_MISC); 10370 u32 factor = ((vmx_misc & GENMASK(27, 25)) >> 25) + 1; 10371 10372 return factor * 512; 10373 } 10374 10375 static void atomic_switch_msrs_test(int count) 10376 { 10377 struct vmx_msr_entry *vm_enter_load; 10378 struct vmx_msr_entry *vm_exit_load; 10379 struct vmx_msr_entry *vm_exit_store; 10380 int max_allowed = max_msr_list_size(); 10381 int byte_capacity = 1ul << (msr_list_page_order + PAGE_SHIFT); 10382 /* Exceeding the max MSR list size at exit triggers KVM to abort. */ 10383 int exit_count = count > max_allowed ? max_allowed : count; 10384 int cleanup_count = count > max_allowed ? 2 : 1; 10385 int i; 10386 10387 /* 10388 * Check for the IA32_TSC MSR, 10389 * available with the "TSC flag" and used to populate the MSR lists. 10390 */ 10391 if (!(cpuid(1).d & (1 << 4))) { 10392 report_skip("%s : \"Time Stamp Counter\" not supported", __func__); 10393 return; 10394 } 10395 10396 /* Set L2 guest. */ 10397 test_set_guest(atomic_switch_msr_limit_test_guest); 10398 10399 /* Setup atomic MSR switch lists. */ 10400 vm_enter_load = alloc_pages(msr_list_page_order); 10401 vm_exit_load = alloc_pages(msr_list_page_order); 10402 vm_exit_store = alloc_pages(msr_list_page_order); 10403 10404 vmcs_write(ENTER_MSR_LD_ADDR, (u64)vm_enter_load); 10405 vmcs_write(EXIT_MSR_LD_ADDR, (u64)vm_exit_load); 10406 vmcs_write(EXIT_MSR_ST_ADDR, (u64)vm_exit_store); 10407 10408 /* 10409 * VM-Enter should succeed up to the max number of MSRs per list, and 10410 * should not consume junk beyond the last entry. 10411 */ 10412 populate_msr_list(vm_enter_load, byte_capacity, count); 10413 populate_msr_list(vm_exit_load, byte_capacity, exit_count); 10414 populate_msr_list(vm_exit_store, byte_capacity, exit_count); 10415 10416 vmcs_write(ENT_MSR_LD_CNT, count); 10417 vmcs_write(EXI_MSR_LD_CNT, exit_count); 10418 vmcs_write(EXI_MSR_ST_CNT, exit_count); 10419 10420 if (count <= max_allowed) { 10421 enter_guest(); 10422 assert_exit_reason(VMX_VMCALL); 10423 skip_exit_vmcall(); 10424 } else { 10425 u32 exit_qual; 10426 10427 test_guest_state("Invalid MSR Load Count", true, count, 10428 "ENT_MSR_LD_CNT"); 10429 10430 exit_qual = vmcs_read(EXI_QUALIFICATION); 10431 report(exit_qual == max_allowed + 1, "exit_qual, %u, is %u.", 10432 exit_qual, max_allowed + 1); 10433 } 10434 10435 /* Cleanup. */ 10436 vmcs_write(ENT_MSR_LD_CNT, 0); 10437 vmcs_write(EXI_MSR_LD_CNT, 0); 10438 vmcs_write(EXI_MSR_ST_CNT, 0); 10439 for (i = 0; i < cleanup_count; i++) { 10440 enter_guest(); 10441 skip_exit_vmcall(); 10442 } 10443 free_pages_by_order(vm_enter_load, msr_list_page_order); 10444 free_pages_by_order(vm_exit_load, msr_list_page_order); 10445 free_pages_by_order(vm_exit_store, msr_list_page_order); 10446 } 10447 10448 static void atomic_switch_max_msrs_test(void) 10449 { 10450 atomic_switch_msrs_test(max_msr_list_size()); 10451 } 10452 10453 static void atomic_switch_overflow_msrs_test(void) 10454 { 10455 if (test_device_enabled()) 10456 atomic_switch_msrs_test(max_msr_list_size() + 1); 10457 else 10458 test_skip("Test is only supported on KVM"); 10459 } 10460 10461 static void vmx_pf_exception_test_guest(void) 10462 { 10463 ac_test_run(PT_LEVEL_PML4, false); 10464 } 10465 10466 static void vmx_pf_exception_forced_emulation_test_guest(void) 10467 { 10468 ac_test_run(PT_LEVEL_PML4, true); 10469 } 10470 10471 typedef void (*invalidate_tlb_t)(void *data); 10472 typedef void (*pf_exception_test_guest_t)(void); 10473 10474 10475 static void __vmx_pf_exception_test(invalidate_tlb_t inv_fn, void *data, 10476 pf_exception_test_guest_t guest_fn) 10477 { 10478 u64 efer; 10479 struct cpuid cpuid; 10480 10481 test_set_guest(guest_fn); 10482 10483 /* Intercept INVLPG when to perform TLB invalidation from L1 (this). */ 10484 if (inv_fn) 10485 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INVLPG); 10486 else 10487 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INVLPG); 10488 10489 enter_guest(); 10490 10491 while (vmcs_read(EXI_REASON) != VMX_VMCALL) { 10492 switch (vmcs_read(EXI_REASON)) { 10493 case VMX_RDMSR: 10494 assert(regs.rcx == MSR_EFER); 10495 efer = vmcs_read(GUEST_EFER); 10496 regs.rdx = efer >> 32; 10497 regs.rax = efer & 0xffffffff; 10498 break; 10499 case VMX_WRMSR: 10500 assert(regs.rcx == MSR_EFER); 10501 efer = regs.rdx << 32 | (regs.rax & 0xffffffff); 10502 vmcs_write(GUEST_EFER, efer); 10503 break; 10504 case VMX_CPUID: 10505 cpuid = (struct cpuid) {0, 0, 0, 0}; 10506 cpuid = raw_cpuid(regs.rax, regs.rcx); 10507 regs.rax = cpuid.a; 10508 regs.rbx = cpuid.b; 10509 regs.rcx = cpuid.c; 10510 regs.rdx = cpuid.d; 10511 break; 10512 case VMX_INVLPG: 10513 inv_fn(data); 10514 break; 10515 default: 10516 assert_msg(false, 10517 "Unexpected exit to L1, exit_reason: %s (0x%lx)", 10518 exit_reason_description(vmcs_read(EXI_REASON)), 10519 vmcs_read(EXI_REASON)); 10520 } 10521 skip_exit_insn(); 10522 enter_guest(); 10523 } 10524 10525 assert_exit_reason(VMX_VMCALL); 10526 } 10527 10528 static void vmx_pf_exception_test(void) 10529 { 10530 __vmx_pf_exception_test(NULL, NULL, vmx_pf_exception_test_guest); 10531 } 10532 10533 static void vmx_pf_exception_forced_emulation_test(void) 10534 { 10535 __vmx_pf_exception_test(NULL, NULL, vmx_pf_exception_forced_emulation_test_guest); 10536 } 10537 10538 static void invalidate_tlb_no_vpid(void *data) 10539 { 10540 /* If VPID is disabled, the TLB is flushed on VM-Enter and VM-Exit. */ 10541 } 10542 10543 static void vmx_pf_no_vpid_test(void) 10544 { 10545 if (is_vpid_supported()) 10546 vmcs_clear_bits(CPU_EXEC_CTRL1, CPU_VPID); 10547 10548 __vmx_pf_exception_test(invalidate_tlb_no_vpid, NULL, 10549 vmx_pf_exception_test_guest); 10550 } 10551 10552 static void invalidate_tlb_invvpid_addr(void *data) 10553 { 10554 invvpid(INVVPID_ALL, *(u16 *)data, vmcs_read(EXI_QUALIFICATION)); 10555 } 10556 10557 static void invalidate_tlb_new_vpid(void *data) 10558 { 10559 u16 *vpid = data; 10560 10561 /* 10562 * Bump VPID to effectively flush L2's TLB from L0's perspective. 10563 * Invalidate all VPIDs when the VPID wraps to zero as hardware/KVM is 10564 * architecturally allowed to keep TLB entries indefinitely. 10565 */ 10566 ++(*vpid); 10567 if (*vpid == 0) { 10568 ++(*vpid); 10569 invvpid(INVVPID_ALL, 0, 0); 10570 } 10571 vmcs_write(VPID, *vpid); 10572 } 10573 10574 static void __vmx_pf_vpid_test(invalidate_tlb_t inv_fn, u16 vpid) 10575 { 10576 if (!is_vpid_supported()) 10577 test_skip("VPID unsupported"); 10578 10579 if (!is_invvpid_supported()) 10580 test_skip("INVVPID unsupported"); 10581 10582 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY); 10583 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_VPID); 10584 vmcs_write(VPID, vpid); 10585 10586 __vmx_pf_exception_test(inv_fn, &vpid, vmx_pf_exception_test_guest); 10587 } 10588 10589 static void vmx_pf_invvpid_test(void) 10590 { 10591 if (!is_invvpid_type_supported(INVVPID_ADDR)) 10592 test_skip("INVVPID ADDR unsupported"); 10593 10594 __vmx_pf_vpid_test(invalidate_tlb_invvpid_addr, 0xaaaa); 10595 } 10596 10597 static void vmx_pf_vpid_test(void) 10598 { 10599 /* Need INVVPID(ALL) to flush VPIDs upon wrap/reuse. */ 10600 if (!is_invvpid_type_supported(INVVPID_ALL)) 10601 test_skip("INVVPID ALL unsupported"); 10602 10603 __vmx_pf_vpid_test(invalidate_tlb_new_vpid, 1); 10604 } 10605 10606 static void vmx_l2_ac_test(void) 10607 { 10608 bool hit_ac = false; 10609 10610 write_cr0(read_cr0() | X86_CR0_AM); 10611 write_rflags(read_rflags() | X86_EFLAGS_AC); 10612 10613 run_in_user(generate_usermode_ac, AC_VECTOR, 0, 0, 0, 0, &hit_ac); 10614 report(hit_ac, "Usermode #AC handled in L2"); 10615 vmcall(); 10616 } 10617 10618 struct vmx_exception_test { 10619 u8 vector; 10620 void (*guest_code)(void); 10621 }; 10622 10623 struct vmx_exception_test vmx_exception_tests[] = { 10624 { GP_VECTOR, generate_non_canonical_gp }, 10625 { UD_VECTOR, generate_ud }, 10626 { DE_VECTOR, generate_de }, 10627 { DB_VECTOR, generate_single_step_db }, 10628 { BP_VECTOR, generate_bp }, 10629 { AC_VECTOR, vmx_l2_ac_test }, 10630 { OF_VECTOR, generate_of }, 10631 { NM_VECTOR, generate_cr0_ts_nm }, 10632 { NM_VECTOR, generate_cr0_em_nm }, 10633 }; 10634 10635 static u8 vmx_exception_test_vector; 10636 10637 static void vmx_exception_handler(struct ex_regs *regs) 10638 { 10639 report(regs->vector == vmx_exception_test_vector, 10640 "Handling %s in L2's exception handler", 10641 exception_mnemonic(vmx_exception_test_vector)); 10642 vmcall(); 10643 } 10644 10645 static void handle_exception_in_l2(u8 vector) 10646 { 10647 handler old_handler = handle_exception(vector, vmx_exception_handler); 10648 10649 vmx_exception_test_vector = vector; 10650 10651 enter_guest(); 10652 report(vmcs_read(EXI_REASON) == VMX_VMCALL, 10653 "%s handled by L2", exception_mnemonic(vector)); 10654 10655 handle_exception(vector, old_handler); 10656 } 10657 10658 static void handle_exception_in_l1(u32 vector) 10659 { 10660 u32 old_eb = vmcs_read(EXC_BITMAP); 10661 u32 intr_type; 10662 u32 intr_info; 10663 10664 vmcs_write(EXC_BITMAP, old_eb | (1u << vector)); 10665 10666 enter_guest(); 10667 10668 if (vector == BP_VECTOR || vector == OF_VECTOR) 10669 intr_type = VMX_INTR_TYPE_SOFT_EXCEPTION; 10670 else 10671 intr_type = VMX_INTR_TYPE_HARD_EXCEPTION; 10672 10673 intr_info = vmcs_read(EXI_INTR_INFO); 10674 report((vmcs_read(EXI_REASON) == VMX_EXC_NMI) && 10675 (intr_info & INTR_INFO_VALID_MASK) && 10676 (intr_info & INTR_INFO_VECTOR_MASK) == vector && 10677 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> INTR_INFO_INTR_TYPE_SHIFT) == intr_type, 10678 "%s correctly routed to L1", exception_mnemonic(vector)); 10679 10680 vmcs_write(EXC_BITMAP, old_eb); 10681 } 10682 10683 static void vmx_exception_test(void) 10684 { 10685 struct vmx_exception_test *t; 10686 int i; 10687 10688 for (i = 0; i < ARRAY_SIZE(vmx_exception_tests); i++) { 10689 t = &vmx_exception_tests[i]; 10690 10691 /* 10692 * Override the guest code before each run even though it's the 10693 * same code, the VMCS guest state needs to be reinitialized. 10694 */ 10695 test_override_guest(t->guest_code); 10696 handle_exception_in_l2(t->vector); 10697 10698 test_override_guest(t->guest_code); 10699 handle_exception_in_l1(t->vector); 10700 } 10701 10702 test_set_guest_finished(); 10703 } 10704 10705 #define TEST(name) { #name, .v2 = name } 10706 10707 /* name/init/guest_main/exit_handler/syscall_handler/guest_regs */ 10708 struct vmx_test vmx_tests[] = { 10709 { "null", NULL, basic_guest_main, basic_exit_handler, NULL, {0} }, 10710 { "vmenter", NULL, vmenter_main, vmenter_exit_handler, NULL, {0} }, 10711 { "preemption timer", preemption_timer_init, preemption_timer_main, 10712 preemption_timer_exit_handler, NULL, {0} }, 10713 { "control field PAT", test_ctrl_pat_init, test_ctrl_pat_main, 10714 test_ctrl_pat_exit_handler, NULL, {0} }, 10715 { "control field EFER", test_ctrl_efer_init, test_ctrl_efer_main, 10716 test_ctrl_efer_exit_handler, NULL, {0} }, 10717 { "CR shadowing", NULL, cr_shadowing_main, 10718 cr_shadowing_exit_handler, NULL, {0} }, 10719 { "I/O bitmap", iobmp_init, iobmp_main, iobmp_exit_handler, 10720 NULL, {0} }, 10721 { "instruction intercept", insn_intercept_init, insn_intercept_main, 10722 insn_intercept_exit_handler, NULL, {0} }, 10723 { "EPT A/D disabled", ept_init, ept_main, ept_exit_handler, NULL, {0} }, 10724 { "EPT A/D enabled", eptad_init, eptad_main, eptad_exit_handler, NULL, {0} }, 10725 { "PML", pml_init, pml_main, pml_exit_handler, NULL, {0} }, 10726 { "interrupt", interrupt_init, interrupt_main, 10727 interrupt_exit_handler, NULL, {0} }, 10728 { "nmi_hlt", nmi_hlt_init, nmi_hlt_main, 10729 nmi_hlt_exit_handler, NULL, {0} }, 10730 { "debug controls", dbgctls_init, dbgctls_main, dbgctls_exit_handler, 10731 NULL, {0} }, 10732 { "MSR switch", msr_switch_init, msr_switch_main, 10733 msr_switch_exit_handler, NULL, {0}, msr_switch_entry_failure }, 10734 { "vmmcall", vmmcall_init, vmmcall_main, vmmcall_exit_handler, NULL, {0} }, 10735 { "disable RDTSCP", disable_rdtscp_init, disable_rdtscp_main, 10736 disable_rdtscp_exit_handler, NULL, {0} }, 10737 { "exit_monitor_from_l2_test", NULL, exit_monitor_from_l2_main, 10738 exit_monitor_from_l2_handler, NULL, {0} }, 10739 { "invalid_msr", invalid_msr_init, invalid_msr_main, 10740 invalid_msr_exit_handler, NULL, {0}, invalid_msr_entry_failure}, 10741 /* Basic V2 tests. */ 10742 TEST(v2_null_test), 10743 TEST(v2_multiple_entries_test), 10744 TEST(fixture_test_case1), 10745 TEST(fixture_test_case2), 10746 /* Opcode tests. */ 10747 TEST(invvpid_test), 10748 /* VM-entry tests */ 10749 TEST(vmx_controls_test), 10750 TEST(vmx_host_state_area_test), 10751 TEST(vmx_guest_state_area_test), 10752 TEST(vmentry_movss_shadow_test), 10753 TEST(vmentry_unrestricted_guest_test), 10754 /* APICv tests */ 10755 TEST(vmx_eoi_bitmap_ioapic_scan_test), 10756 TEST(vmx_hlt_with_rvi_test), 10757 TEST(apic_reg_virt_test), 10758 TEST(virt_x2apic_mode_test), 10759 /* APIC pass-through tests */ 10760 TEST(vmx_apic_passthrough_test), 10761 TEST(vmx_apic_passthrough_thread_test), 10762 TEST(vmx_apic_passthrough_tpr_threshold_test), 10763 TEST(vmx_init_signal_test), 10764 TEST(vmx_sipi_signal_test), 10765 /* VMCS Shadowing tests */ 10766 TEST(vmx_vmcs_shadow_test), 10767 /* Regression tests */ 10768 TEST(vmx_ldtr_test), 10769 TEST(vmx_cr_load_test), 10770 TEST(vmx_cr4_osxsave_test), 10771 TEST(vmx_no_nm_test), 10772 TEST(vmx_db_test), 10773 TEST(vmx_nmi_window_test), 10774 TEST(vmx_intr_window_test), 10775 TEST(vmx_pending_event_test), 10776 TEST(vmx_pending_event_hlt_test), 10777 TEST(vmx_store_tsc_test), 10778 TEST(vmx_preemption_timer_zero_test), 10779 TEST(vmx_preemption_timer_tf_test), 10780 TEST(vmx_preemption_timer_expiry_test), 10781 /* EPT access tests. */ 10782 TEST(ept_access_test_not_present), 10783 TEST(ept_access_test_read_only), 10784 TEST(ept_access_test_write_only), 10785 TEST(ept_access_test_read_write), 10786 TEST(ept_access_test_execute_only), 10787 TEST(ept_access_test_read_execute), 10788 TEST(ept_access_test_write_execute), 10789 TEST(ept_access_test_read_write_execute), 10790 TEST(ept_access_test_reserved_bits), 10791 TEST(ept_access_test_ignored_bits), 10792 TEST(ept_access_test_paddr_not_present_ad_disabled), 10793 TEST(ept_access_test_paddr_not_present_ad_enabled), 10794 TEST(ept_access_test_paddr_read_only_ad_disabled), 10795 TEST(ept_access_test_paddr_read_only_ad_enabled), 10796 TEST(ept_access_test_paddr_read_write), 10797 TEST(ept_access_test_paddr_read_write_execute), 10798 TEST(ept_access_test_paddr_read_execute_ad_disabled), 10799 TEST(ept_access_test_paddr_read_execute_ad_enabled), 10800 TEST(ept_access_test_paddr_not_present_page_fault), 10801 TEST(ept_access_test_force_2m_page), 10802 /* Atomic MSR switch tests. */ 10803 TEST(atomic_switch_max_msrs_test), 10804 TEST(atomic_switch_overflow_msrs_test), 10805 TEST(rdtsc_vmexit_diff_test), 10806 TEST(vmx_mtf_test), 10807 TEST(vmx_mtf_pdpte_test), 10808 TEST(vmx_pf_exception_test), 10809 TEST(vmx_pf_exception_forced_emulation_test), 10810 TEST(vmx_pf_no_vpid_test), 10811 TEST(vmx_pf_invvpid_test), 10812 TEST(vmx_pf_vpid_test), 10813 TEST(vmx_exception_test), 10814 { NULL, NULL, NULL, NULL, NULL, {0} }, 10815 }; 10816