1 /* 2 * All test cases of nested virtualization should be in this file 3 * 4 * Author : Arthur Chunqi Li <yzt356@gmail.com> 5 */ 6 7 #include <asm/debugreg.h> 8 9 #include "vmx.h" 10 #include "msr.h" 11 #include "processor.h" 12 #include "vm.h" 13 #include "pci.h" 14 #include "fwcfg.h" 15 #include "isr.h" 16 #include "desc.h" 17 #include "apic.h" 18 #include "types.h" 19 #include "vmalloc.h" 20 #include "alloc_page.h" 21 #include "smp.h" 22 #include "delay.h" 23 #include "access.h" 24 #include "x86/usermode.h" 25 26 /* 27 * vmcs.GUEST_PENDING_DEBUG has the same format as DR6, although some bits that 28 * are legal in DR6 are reserved in vmcs.GUEST_PENDING_DEBUG. And if any data 29 * or I/O breakpoint matches *and* was enabled, bit 12 is also set. 30 */ 31 #define PENDING_DBG_TRAP BIT(12) 32 33 #define VPID_CAP_INVVPID_TYPES_SHIFT 40 34 35 u64 ia32_pat; 36 u64 ia32_efer; 37 void *io_bitmap_a, *io_bitmap_b; 38 u16 ioport; 39 40 unsigned long *pml4; 41 u64 eptp; 42 void *data_page1, *data_page2; 43 44 phys_addr_t pci_physaddr; 45 46 void *pml_log; 47 #define PML_INDEX 512 48 49 static inline unsigned ffs(unsigned x) 50 { 51 int pos = -1; 52 53 __asm__ __volatile__("bsf %1, %%eax; cmovnz %%eax, %0" 54 : "+r"(pos) : "rm"(x) : "eax"); 55 return pos + 1; 56 } 57 58 static inline void vmcall(void) 59 { 60 asm volatile("vmcall"); 61 } 62 63 static void basic_guest_main(void) 64 { 65 report_pass("Basic VMX test"); 66 } 67 68 static int basic_exit_handler(union exit_reason exit_reason) 69 { 70 report_fail("Basic VMX test"); 71 print_vmexit_info(exit_reason); 72 return VMX_TEST_EXIT; 73 } 74 75 static void vmenter_main(void) 76 { 77 u64 rax; 78 u64 rsp, resume_rsp; 79 80 report_pass("test vmlaunch"); 81 82 asm volatile( 83 "mov %%rsp, %0\n\t" 84 "mov %3, %%rax\n\t" 85 "vmcall\n\t" 86 "mov %%rax, %1\n\t" 87 "mov %%rsp, %2\n\t" 88 : "=r"(rsp), "=r"(rax), "=r"(resume_rsp) 89 : "g"(0xABCD)); 90 report((rax == 0xFFFF) && (rsp == resume_rsp), "test vmresume"); 91 } 92 93 static int vmenter_exit_handler(union exit_reason exit_reason) 94 { 95 u64 guest_rip = vmcs_read(GUEST_RIP); 96 97 switch (exit_reason.basic) { 98 case VMX_VMCALL: 99 if (regs.rax != 0xABCD) { 100 report_fail("test vmresume"); 101 return VMX_TEST_VMEXIT; 102 } 103 regs.rax = 0xFFFF; 104 vmcs_write(GUEST_RIP, guest_rip + 3); 105 return VMX_TEST_RESUME; 106 default: 107 report_fail("test vmresume"); 108 print_vmexit_info(exit_reason); 109 } 110 return VMX_TEST_VMEXIT; 111 } 112 113 u32 preempt_scale; 114 volatile unsigned long long tsc_val; 115 volatile u32 preempt_val; 116 u64 saved_rip; 117 118 static int preemption_timer_init(struct vmcs *vmcs) 119 { 120 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 121 printf("\tPreemption timer is not supported\n"); 122 return VMX_TEST_EXIT; 123 } 124 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 125 preempt_val = 10000000; 126 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 127 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 128 129 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 130 printf("\tSave preemption value is not supported\n"); 131 132 return VMX_TEST_START; 133 } 134 135 static void preemption_timer_main(void) 136 { 137 tsc_val = rdtsc(); 138 if (ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) { 139 vmx_set_test_stage(0); 140 vmcall(); 141 if (vmx_get_test_stage() == 1) 142 vmcall(); 143 } 144 vmx_set_test_stage(1); 145 while (vmx_get_test_stage() == 1) { 146 if (((rdtsc() - tsc_val) >> preempt_scale) 147 > 10 * preempt_val) { 148 vmx_set_test_stage(2); 149 vmcall(); 150 } 151 } 152 tsc_val = rdtsc(); 153 asm volatile ("hlt"); 154 vmcall(); 155 vmx_set_test_stage(5); 156 vmcall(); 157 } 158 159 static int preemption_timer_exit_handler(union exit_reason exit_reason) 160 { 161 bool guest_halted; 162 u64 guest_rip; 163 u32 insn_len; 164 u32 ctrl_exit; 165 166 guest_rip = vmcs_read(GUEST_RIP); 167 insn_len = vmcs_read(EXI_INST_LEN); 168 switch (exit_reason.basic) { 169 case VMX_PREEMPT: 170 switch (vmx_get_test_stage()) { 171 case 1: 172 case 2: 173 report(((rdtsc() - tsc_val) >> preempt_scale) >= preempt_val, 174 "busy-wait for preemption timer"); 175 vmx_set_test_stage(3); 176 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 177 return VMX_TEST_RESUME; 178 case 3: 179 guest_halted = 180 (vmcs_read(GUEST_ACTV_STATE) == ACTV_HLT); 181 report(((rdtsc() - tsc_val) >> preempt_scale) >= preempt_val 182 && guest_halted, 183 "preemption timer during hlt"); 184 vmx_set_test_stage(4); 185 vmcs_write(PIN_CONTROLS, 186 vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 187 vmcs_write(EXI_CONTROLS, 188 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_PREEMPT); 189 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 190 return VMX_TEST_RESUME; 191 case 4: 192 report(saved_rip == guest_rip, 193 "preemption timer with 0 value"); 194 break; 195 default: 196 report_fail("Invalid stage."); 197 print_vmexit_info(exit_reason); 198 break; 199 } 200 break; 201 case VMX_VMCALL: 202 vmcs_write(GUEST_RIP, guest_rip + insn_len); 203 switch (vmx_get_test_stage()) { 204 case 0: 205 report(vmcs_read(PREEMPT_TIMER_VALUE) == preempt_val, 206 "Keep preemption value"); 207 vmx_set_test_stage(1); 208 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 209 ctrl_exit = (vmcs_read(EXI_CONTROLS) | 210 EXI_SAVE_PREEMPT) & ctrl_exit_rev.clr; 211 vmcs_write(EXI_CONTROLS, ctrl_exit); 212 return VMX_TEST_RESUME; 213 case 1: 214 report(vmcs_read(PREEMPT_TIMER_VALUE) < preempt_val, 215 "Save preemption value"); 216 return VMX_TEST_RESUME; 217 case 2: 218 report_fail("busy-wait for preemption timer"); 219 vmx_set_test_stage(3); 220 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 221 return VMX_TEST_RESUME; 222 case 3: 223 report_fail("preemption timer during hlt"); 224 vmx_set_test_stage(4); 225 /* fall through */ 226 case 4: 227 vmcs_write(PIN_CONTROLS, 228 vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 229 vmcs_write(PREEMPT_TIMER_VALUE, 0); 230 saved_rip = guest_rip + insn_len; 231 return VMX_TEST_RESUME; 232 case 5: 233 report_fail("preemption timer with 0 value (vmcall stage 5)"); 234 break; 235 default: 236 // Should not reach here 237 report_fail("unexpected stage, %d", 238 vmx_get_test_stage()); 239 print_vmexit_info(exit_reason); 240 return VMX_TEST_VMEXIT; 241 } 242 break; 243 default: 244 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 245 print_vmexit_info(exit_reason); 246 } 247 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 248 return VMX_TEST_VMEXIT; 249 } 250 251 static void msr_bmp_init(void) 252 { 253 void *msr_bitmap; 254 u32 ctrl_cpu0; 255 256 msr_bitmap = alloc_page(); 257 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 258 ctrl_cpu0 |= CPU_MSR_BITMAP; 259 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 260 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 261 } 262 263 static void *get_msr_bitmap(void) 264 { 265 void *msr_bitmap; 266 267 if (vmcs_read(CPU_EXEC_CTRL0) & CPU_MSR_BITMAP) { 268 msr_bitmap = (void *)vmcs_read(MSR_BITMAP); 269 } else { 270 msr_bitmap = alloc_page(); 271 memset(msr_bitmap, 0xff, PAGE_SIZE); 272 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 273 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_MSR_BITMAP); 274 } 275 276 return msr_bitmap; 277 } 278 279 static void disable_intercept_for_x2apic_msrs(void) 280 { 281 unsigned long *msr_bitmap = (unsigned long *)get_msr_bitmap(); 282 u32 msr; 283 284 for (msr = APIC_BASE_MSR; 285 msr < (APIC_BASE_MSR+0xff); 286 msr += BITS_PER_LONG) { 287 unsigned int word = msr / BITS_PER_LONG; 288 289 msr_bitmap[word] = 0; 290 msr_bitmap[word + (0x800 / sizeof(long))] = 0; 291 } 292 } 293 294 static int test_ctrl_pat_init(struct vmcs *vmcs) 295 { 296 u64 ctrl_ent; 297 u64 ctrl_exi; 298 299 msr_bmp_init(); 300 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT) && 301 !(ctrl_exit_rev.clr & EXI_LOAD_PAT) && 302 !(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 303 printf("\tSave/load PAT is not supported\n"); 304 return 1; 305 } 306 307 ctrl_ent = vmcs_read(ENT_CONTROLS); 308 ctrl_exi = vmcs_read(EXI_CONTROLS); 309 ctrl_ent |= ctrl_enter_rev.clr & ENT_LOAD_PAT; 310 ctrl_exi |= ctrl_exit_rev.clr & (EXI_SAVE_PAT | EXI_LOAD_PAT); 311 vmcs_write(ENT_CONTROLS, ctrl_ent); 312 vmcs_write(EXI_CONTROLS, ctrl_exi); 313 ia32_pat = rdmsr(MSR_IA32_CR_PAT); 314 vmcs_write(GUEST_PAT, 0x0); 315 vmcs_write(HOST_PAT, ia32_pat); 316 return VMX_TEST_START; 317 } 318 319 static void test_ctrl_pat_main(void) 320 { 321 u64 guest_ia32_pat; 322 323 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 324 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) 325 printf("\tENT_LOAD_PAT is not supported.\n"); 326 else { 327 if (guest_ia32_pat != 0) { 328 report_fail("Entry load PAT"); 329 return; 330 } 331 } 332 wrmsr(MSR_IA32_CR_PAT, 0x6); 333 vmcall(); 334 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 335 if (ctrl_enter_rev.clr & ENT_LOAD_PAT) 336 report(guest_ia32_pat == ia32_pat, "Entry load PAT"); 337 } 338 339 static int test_ctrl_pat_exit_handler(union exit_reason exit_reason) 340 { 341 u64 guest_rip; 342 u64 guest_pat; 343 344 guest_rip = vmcs_read(GUEST_RIP); 345 switch (exit_reason.basic) { 346 case VMX_VMCALL: 347 guest_pat = vmcs_read(GUEST_PAT); 348 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT)) { 349 printf("\tEXI_SAVE_PAT is not supported\n"); 350 vmcs_write(GUEST_PAT, 0x6); 351 } else { 352 report(guest_pat == 0x6, "Exit save PAT"); 353 } 354 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) 355 printf("\tEXI_LOAD_PAT is not supported\n"); 356 else 357 report(rdmsr(MSR_IA32_CR_PAT) == ia32_pat, 358 "Exit load PAT"); 359 vmcs_write(GUEST_PAT, ia32_pat); 360 vmcs_write(GUEST_RIP, guest_rip + 3); 361 return VMX_TEST_RESUME; 362 default: 363 printf("ERROR : Unknown exit reason, 0x%x.\n", exit_reason.full); 364 break; 365 } 366 return VMX_TEST_VMEXIT; 367 } 368 369 static int test_ctrl_efer_init(struct vmcs *vmcs) 370 { 371 u64 ctrl_ent; 372 u64 ctrl_exi; 373 374 msr_bmp_init(); 375 ctrl_ent = vmcs_read(ENT_CONTROLS) | ENT_LOAD_EFER; 376 ctrl_exi = vmcs_read(EXI_CONTROLS) | EXI_SAVE_EFER | EXI_LOAD_EFER; 377 vmcs_write(ENT_CONTROLS, ctrl_ent & ctrl_enter_rev.clr); 378 vmcs_write(EXI_CONTROLS, ctrl_exi & ctrl_exit_rev.clr); 379 ia32_efer = rdmsr(MSR_EFER); 380 vmcs_write(GUEST_EFER, ia32_efer ^ EFER_NX); 381 vmcs_write(HOST_EFER, ia32_efer ^ EFER_NX); 382 return VMX_TEST_START; 383 } 384 385 static void test_ctrl_efer_main(void) 386 { 387 u64 guest_ia32_efer; 388 389 guest_ia32_efer = rdmsr(MSR_EFER); 390 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) 391 printf("\tENT_LOAD_EFER is not supported.\n"); 392 else { 393 if (guest_ia32_efer != (ia32_efer ^ EFER_NX)) { 394 report_fail("Entry load EFER"); 395 return; 396 } 397 } 398 wrmsr(MSR_EFER, ia32_efer); 399 vmcall(); 400 guest_ia32_efer = rdmsr(MSR_EFER); 401 if (ctrl_enter_rev.clr & ENT_LOAD_EFER) 402 report(guest_ia32_efer == ia32_efer, "Entry load EFER"); 403 } 404 405 static int test_ctrl_efer_exit_handler(union exit_reason exit_reason) 406 { 407 u64 guest_rip; 408 u64 guest_efer; 409 410 guest_rip = vmcs_read(GUEST_RIP); 411 switch (exit_reason.basic) { 412 case VMX_VMCALL: 413 guest_efer = vmcs_read(GUEST_EFER); 414 if (!(ctrl_exit_rev.clr & EXI_SAVE_EFER)) { 415 printf("\tEXI_SAVE_EFER is not supported\n"); 416 vmcs_write(GUEST_EFER, ia32_efer); 417 } else { 418 report(guest_efer == ia32_efer, "Exit save EFER"); 419 } 420 if (!(ctrl_exit_rev.clr & EXI_LOAD_EFER)) { 421 printf("\tEXI_LOAD_EFER is not supported\n"); 422 wrmsr(MSR_EFER, ia32_efer ^ EFER_NX); 423 } else { 424 report(rdmsr(MSR_EFER) == (ia32_efer ^ EFER_NX), 425 "Exit load EFER"); 426 } 427 vmcs_write(GUEST_PAT, ia32_efer); 428 vmcs_write(GUEST_RIP, guest_rip + 3); 429 return VMX_TEST_RESUME; 430 default: 431 printf("ERROR : Unknown exit reason, 0x%x.\n", exit_reason.full); 432 break; 433 } 434 return VMX_TEST_VMEXIT; 435 } 436 437 u32 guest_cr0, guest_cr4; 438 439 static void cr_shadowing_main(void) 440 { 441 u32 cr0, cr4, tmp; 442 443 // Test read through 444 vmx_set_test_stage(0); 445 guest_cr0 = read_cr0(); 446 if (vmx_get_test_stage() == 1) 447 report_fail("Read through CR0"); 448 else 449 vmcall(); 450 vmx_set_test_stage(1); 451 guest_cr4 = read_cr4(); 452 if (vmx_get_test_stage() == 2) 453 report_fail("Read through CR4"); 454 else 455 vmcall(); 456 // Test write through 457 guest_cr0 = guest_cr0 ^ (X86_CR0_TS | X86_CR0_MP); 458 guest_cr4 = guest_cr4 ^ (X86_CR4_TSD | X86_CR4_DE); 459 vmx_set_test_stage(2); 460 write_cr0(guest_cr0); 461 if (vmx_get_test_stage() == 3) 462 report_fail("Write through CR0"); 463 else 464 vmcall(); 465 vmx_set_test_stage(3); 466 write_cr4(guest_cr4); 467 if (vmx_get_test_stage() == 4) 468 report_fail("Write through CR4"); 469 else 470 vmcall(); 471 // Test read shadow 472 vmx_set_test_stage(4); 473 vmcall(); 474 cr0 = read_cr0(); 475 if (vmx_get_test_stage() != 5) 476 report(cr0 == guest_cr0, "Read shadowing CR0"); 477 vmx_set_test_stage(5); 478 cr4 = read_cr4(); 479 if (vmx_get_test_stage() != 6) 480 report(cr4 == guest_cr4, "Read shadowing CR4"); 481 // Test write shadow (same value with shadow) 482 vmx_set_test_stage(6); 483 write_cr0(guest_cr0); 484 if (vmx_get_test_stage() == 7) 485 report_fail("Write shadowing CR0 (same value with shadow)"); 486 else 487 vmcall(); 488 vmx_set_test_stage(7); 489 write_cr4(guest_cr4); 490 if (vmx_get_test_stage() == 8) 491 report_fail("Write shadowing CR4 (same value with shadow)"); 492 else 493 vmcall(); 494 // Test write shadow (different value) 495 vmx_set_test_stage(8); 496 tmp = guest_cr0 ^ X86_CR0_TS; 497 asm volatile("mov %0, %%rsi\n\t" 498 "mov %%rsi, %%cr0\n\t" 499 ::"m"(tmp) 500 :"rsi", "memory", "cc"); 501 report(vmx_get_test_stage() == 9, 502 "Write shadowing different X86_CR0_TS"); 503 vmx_set_test_stage(9); 504 tmp = guest_cr0 ^ X86_CR0_MP; 505 asm volatile("mov %0, %%rsi\n\t" 506 "mov %%rsi, %%cr0\n\t" 507 ::"m"(tmp) 508 :"rsi", "memory", "cc"); 509 report(vmx_get_test_stage() == 10, 510 "Write shadowing different X86_CR0_MP"); 511 vmx_set_test_stage(10); 512 tmp = guest_cr4 ^ X86_CR4_TSD; 513 asm volatile("mov %0, %%rsi\n\t" 514 "mov %%rsi, %%cr4\n\t" 515 ::"m"(tmp) 516 :"rsi", "memory", "cc"); 517 report(vmx_get_test_stage() == 11, 518 "Write shadowing different X86_CR4_TSD"); 519 vmx_set_test_stage(11); 520 tmp = guest_cr4 ^ X86_CR4_DE; 521 asm volatile("mov %0, %%rsi\n\t" 522 "mov %%rsi, %%cr4\n\t" 523 ::"m"(tmp) 524 :"rsi", "memory", "cc"); 525 report(vmx_get_test_stage() == 12, 526 "Write shadowing different X86_CR4_DE"); 527 } 528 529 static int cr_shadowing_exit_handler(union exit_reason exit_reason) 530 { 531 u64 guest_rip; 532 u32 insn_len; 533 u32 exit_qual; 534 535 guest_rip = vmcs_read(GUEST_RIP); 536 insn_len = vmcs_read(EXI_INST_LEN); 537 exit_qual = vmcs_read(EXI_QUALIFICATION); 538 switch (exit_reason.basic) { 539 case VMX_VMCALL: 540 switch (vmx_get_test_stage()) { 541 case 0: 542 report(guest_cr0 == vmcs_read(GUEST_CR0), 543 "Read through CR0"); 544 break; 545 case 1: 546 report(guest_cr4 == vmcs_read(GUEST_CR4), 547 "Read through CR4"); 548 break; 549 case 2: 550 report(guest_cr0 == vmcs_read(GUEST_CR0), 551 "Write through CR0"); 552 break; 553 case 3: 554 report(guest_cr4 == vmcs_read(GUEST_CR4), 555 "Write through CR4"); 556 break; 557 case 4: 558 guest_cr0 = vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP); 559 guest_cr4 = vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE); 560 vmcs_write(CR0_MASK, X86_CR0_TS | X86_CR0_MP); 561 vmcs_write(CR0_READ_SHADOW, guest_cr0 & (X86_CR0_TS | X86_CR0_MP)); 562 vmcs_write(CR4_MASK, X86_CR4_TSD | X86_CR4_DE); 563 vmcs_write(CR4_READ_SHADOW, guest_cr4 & (X86_CR4_TSD | X86_CR4_DE)); 564 break; 565 case 6: 566 report(guest_cr0 == (vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP)), 567 "Write shadowing CR0 (same value)"); 568 break; 569 case 7: 570 report(guest_cr4 == (vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE)), 571 "Write shadowing CR4 (same value)"); 572 break; 573 default: 574 // Should not reach here 575 report_fail("unexpected stage, %d", 576 vmx_get_test_stage()); 577 print_vmexit_info(exit_reason); 578 return VMX_TEST_VMEXIT; 579 } 580 vmcs_write(GUEST_RIP, guest_rip + insn_len); 581 return VMX_TEST_RESUME; 582 case VMX_CR: 583 switch (vmx_get_test_stage()) { 584 case 4: 585 report_fail("Read shadowing CR0"); 586 vmx_inc_test_stage(); 587 break; 588 case 5: 589 report_fail("Read shadowing CR4"); 590 vmx_inc_test_stage(); 591 break; 592 case 6: 593 report_fail("Write shadowing CR0 (same value)"); 594 vmx_inc_test_stage(); 595 break; 596 case 7: 597 report_fail("Write shadowing CR4 (same value)"); 598 vmx_inc_test_stage(); 599 break; 600 case 8: 601 case 9: 602 // 0x600 encodes "mov %esi, %cr0" 603 if (exit_qual == 0x600) 604 vmx_inc_test_stage(); 605 break; 606 case 10: 607 case 11: 608 // 0x604 encodes "mov %esi, %cr4" 609 if (exit_qual == 0x604) 610 vmx_inc_test_stage(); 611 break; 612 default: 613 // Should not reach here 614 report_fail("unexpected stage, %d", 615 vmx_get_test_stage()); 616 print_vmexit_info(exit_reason); 617 return VMX_TEST_VMEXIT; 618 } 619 vmcs_write(GUEST_RIP, guest_rip + insn_len); 620 return VMX_TEST_RESUME; 621 default: 622 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 623 print_vmexit_info(exit_reason); 624 } 625 return VMX_TEST_VMEXIT; 626 } 627 628 static int iobmp_init(struct vmcs *vmcs) 629 { 630 u32 ctrl_cpu0; 631 632 io_bitmap_a = alloc_page(); 633 io_bitmap_b = alloc_page(); 634 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 635 ctrl_cpu0 |= CPU_IO_BITMAP; 636 ctrl_cpu0 &= (~CPU_IO); 637 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 638 vmcs_write(IO_BITMAP_A, (u64)io_bitmap_a); 639 vmcs_write(IO_BITMAP_B, (u64)io_bitmap_b); 640 return VMX_TEST_START; 641 } 642 643 static void iobmp_main(void) 644 { 645 // stage 0, test IO pass 646 vmx_set_test_stage(0); 647 inb(0x5000); 648 outb(0x0, 0x5000); 649 report(vmx_get_test_stage() == 0, "I/O bitmap - I/O pass"); 650 // test IO width, in/out 651 ((u8 *)io_bitmap_a)[0] = 0xFF; 652 vmx_set_test_stage(2); 653 inb(0x0); 654 report(vmx_get_test_stage() == 3, "I/O bitmap - trap in"); 655 vmx_set_test_stage(3); 656 outw(0x0, 0x0); 657 report(vmx_get_test_stage() == 4, "I/O bitmap - trap out"); 658 vmx_set_test_stage(4); 659 inl(0x0); 660 report(vmx_get_test_stage() == 5, "I/O bitmap - I/O width, long"); 661 // test low/high IO port 662 vmx_set_test_stage(5); 663 ((u8 *)io_bitmap_a)[0x5000 / 8] = (1 << (0x5000 % 8)); 664 inb(0x5000); 665 report(vmx_get_test_stage() == 6, "I/O bitmap - I/O port, low part"); 666 vmx_set_test_stage(6); 667 ((u8 *)io_bitmap_b)[0x1000 / 8] = (1 << (0x1000 % 8)); 668 inb(0x9000); 669 report(vmx_get_test_stage() == 7, "I/O bitmap - I/O port, high part"); 670 // test partial pass 671 vmx_set_test_stage(7); 672 inl(0x4FFF); 673 report(vmx_get_test_stage() == 8, "I/O bitmap - partial pass"); 674 // test overrun 675 vmx_set_test_stage(8); 676 memset(io_bitmap_a, 0x0, PAGE_SIZE); 677 memset(io_bitmap_b, 0x0, PAGE_SIZE); 678 inl(0xFFFF); 679 report(vmx_get_test_stage() == 9, "I/O bitmap - overrun"); 680 vmx_set_test_stage(9); 681 vmcall(); 682 outb(0x0, 0x0); 683 report(vmx_get_test_stage() == 9, 684 "I/O bitmap - ignore unconditional exiting"); 685 vmx_set_test_stage(10); 686 vmcall(); 687 outb(0x0, 0x0); 688 report(vmx_get_test_stage() == 11, 689 "I/O bitmap - unconditional exiting"); 690 } 691 692 static int iobmp_exit_handler(union exit_reason exit_reason) 693 { 694 u64 guest_rip; 695 ulong exit_qual; 696 u32 insn_len, ctrl_cpu0; 697 698 guest_rip = vmcs_read(GUEST_RIP); 699 exit_qual = vmcs_read(EXI_QUALIFICATION); 700 insn_len = vmcs_read(EXI_INST_LEN); 701 switch (exit_reason.basic) { 702 case VMX_IO: 703 switch (vmx_get_test_stage()) { 704 case 0: 705 case 1: 706 vmx_inc_test_stage(); 707 break; 708 case 2: 709 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_BYTE, 710 "I/O bitmap - I/O width, byte"); 711 report(exit_qual & VMX_IO_IN, 712 "I/O bitmap - I/O direction, in"); 713 vmx_inc_test_stage(); 714 break; 715 case 3: 716 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_WORD, 717 "I/O bitmap - I/O width, word"); 718 report(!(exit_qual & VMX_IO_IN), 719 "I/O bitmap - I/O direction, out"); 720 vmx_inc_test_stage(); 721 break; 722 case 4: 723 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_LONG, 724 "I/O bitmap - I/O width, long"); 725 vmx_inc_test_stage(); 726 break; 727 case 5: 728 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x5000) 729 vmx_inc_test_stage(); 730 break; 731 case 6: 732 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x9000) 733 vmx_inc_test_stage(); 734 break; 735 case 7: 736 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x4FFF) 737 vmx_inc_test_stage(); 738 break; 739 case 8: 740 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0xFFFF) 741 vmx_inc_test_stage(); 742 break; 743 case 9: 744 case 10: 745 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 746 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0 & ~CPU_IO); 747 vmx_inc_test_stage(); 748 break; 749 default: 750 // Should not reach here 751 report_fail("unexpected stage, %d", 752 vmx_get_test_stage()); 753 print_vmexit_info(exit_reason); 754 return VMX_TEST_VMEXIT; 755 } 756 vmcs_write(GUEST_RIP, guest_rip + insn_len); 757 return VMX_TEST_RESUME; 758 case VMX_VMCALL: 759 switch (vmx_get_test_stage()) { 760 case 9: 761 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 762 ctrl_cpu0 |= CPU_IO | CPU_IO_BITMAP; 763 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 764 break; 765 case 10: 766 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 767 ctrl_cpu0 = (ctrl_cpu0 & ~CPU_IO_BITMAP) | CPU_IO; 768 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 769 break; 770 default: 771 // Should not reach here 772 report_fail("unexpected stage, %d", 773 vmx_get_test_stage()); 774 print_vmexit_info(exit_reason); 775 return VMX_TEST_VMEXIT; 776 } 777 vmcs_write(GUEST_RIP, guest_rip + insn_len); 778 return VMX_TEST_RESUME; 779 default: 780 printf("guest_rip = %#lx\n", guest_rip); 781 printf("\tERROR : Unknown exit reason, 0x%x\n", exit_reason.full); 782 break; 783 } 784 return VMX_TEST_VMEXIT; 785 } 786 787 #define INSN_CPU0 0 788 #define INSN_CPU1 1 789 #define INSN_ALWAYS_TRAP 2 790 791 #define FIELD_EXIT_QUAL (1 << 0) 792 #define FIELD_INSN_INFO (1 << 1) 793 794 asm( 795 "insn_hlt: hlt;ret\n\t" 796 "insn_invlpg: invlpg 0x12345678;ret\n\t" 797 "insn_mwait: xor %eax, %eax; xor %ecx, %ecx; mwait;ret\n\t" 798 "insn_rdpmc: xor %ecx, %ecx; rdpmc;ret\n\t" 799 "insn_rdtsc: rdtsc;ret\n\t" 800 "insn_cr3_load: mov cr3,%rax; mov %rax,%cr3;ret\n\t" 801 "insn_cr3_store: mov %cr3,%rax;ret\n\t" 802 "insn_cr8_load: xor %eax, %eax; mov %rax,%cr8;ret\n\t" 803 "insn_cr8_store: mov %cr8,%rax;ret\n\t" 804 "insn_monitor: xor %eax, %eax; xor %ecx, %ecx; xor %edx, %edx; monitor;ret\n\t" 805 "insn_pause: pause;ret\n\t" 806 "insn_wbinvd: wbinvd;ret\n\t" 807 "insn_cpuid: mov $10, %eax; cpuid;ret\n\t" 808 "insn_invd: invd;ret\n\t" 809 "insn_sgdt: sgdt gdt_descr;ret\n\t" 810 "insn_lgdt: lgdt gdt_descr;ret\n\t" 811 "insn_sidt: sidt idt_descr;ret\n\t" 812 "insn_lidt: lidt idt_descr;ret\n\t" 813 "insn_sldt: sldt %ax;ret\n\t" 814 "insn_lldt: xor %eax, %eax; lldt %ax;ret\n\t" 815 "insn_str: str %ax;ret\n\t" 816 "insn_rdrand: rdrand %rax;ret\n\t" 817 "insn_rdseed: rdseed %rax;ret\n\t" 818 ); 819 extern void insn_hlt(void); 820 extern void insn_invlpg(void); 821 extern void insn_mwait(void); 822 extern void insn_rdpmc(void); 823 extern void insn_rdtsc(void); 824 extern void insn_cr3_load(void); 825 extern void insn_cr3_store(void); 826 extern void insn_cr8_load(void); 827 extern void insn_cr8_store(void); 828 extern void insn_monitor(void); 829 extern void insn_pause(void); 830 extern void insn_wbinvd(void); 831 extern void insn_sgdt(void); 832 extern void insn_lgdt(void); 833 extern void insn_sidt(void); 834 extern void insn_lidt(void); 835 extern void insn_sldt(void); 836 extern void insn_lldt(void); 837 extern void insn_str(void); 838 extern void insn_cpuid(void); 839 extern void insn_invd(void); 840 extern void insn_rdrand(void); 841 extern void insn_rdseed(void); 842 843 u32 cur_insn; 844 u64 cr3; 845 846 typedef bool (*supported_fn)(void); 847 848 static bool this_cpu_has_mwait(void) 849 { 850 return this_cpu_has(X86_FEATURE_MWAIT); 851 } 852 853 struct insn_table { 854 const char *name; 855 u32 flag; 856 void (*insn_func)(void); 857 u32 type; 858 u32 reason; 859 ulong exit_qual; 860 u32 insn_info; 861 // Use FIELD_EXIT_QUAL and FIELD_INSN_INFO to define 862 // which field need to be tested, reason is always tested 863 u32 test_field; 864 const supported_fn supported_fn; 865 u8 disabled; 866 }; 867 868 /* 869 * Add more test cases of instruction intercept here. Elements in this 870 * table is: 871 * name/control flag/insn function/type/exit reason/exit qulification/ 872 * instruction info/field to test 873 * The last field defines which fields (exit_qual and insn_info) need to be 874 * tested in exit handler. If set to 0, only "reason" is checked. 875 */ 876 static struct insn_table insn_table[] = { 877 // Flags for Primary Processor-Based VM-Execution Controls 878 {"HLT", CPU_HLT, insn_hlt, INSN_CPU0, 12, 0, 0, 0}, 879 {"INVLPG", CPU_INVLPG, insn_invlpg, INSN_CPU0, 14, 880 0x12345678, 0, FIELD_EXIT_QUAL}, 881 {"MWAIT", CPU_MWAIT, insn_mwait, INSN_CPU0, 36, 0, 0, 0, this_cpu_has_mwait}, 882 {"RDPMC", CPU_RDPMC, insn_rdpmc, INSN_CPU0, 15, 0, 0, 0, this_cpu_has_pmu}, 883 {"RDTSC", CPU_RDTSC, insn_rdtsc, INSN_CPU0, 16, 0, 0, 0}, 884 {"CR3 load", CPU_CR3_LOAD, insn_cr3_load, INSN_CPU0, 28, 0x3, 0, 885 FIELD_EXIT_QUAL}, 886 {"CR3 store", CPU_CR3_STORE, insn_cr3_store, INSN_CPU0, 28, 0x13, 0, 887 FIELD_EXIT_QUAL}, 888 {"CR8 load", CPU_CR8_LOAD, insn_cr8_load, INSN_CPU0, 28, 0x8, 0, 889 FIELD_EXIT_QUAL}, 890 {"CR8 store", CPU_CR8_STORE, insn_cr8_store, INSN_CPU0, 28, 0x18, 0, 891 FIELD_EXIT_QUAL}, 892 {"MONITOR", CPU_MONITOR, insn_monitor, INSN_CPU0, 39, 0, 0, 0, this_cpu_has_mwait}, 893 {"PAUSE", CPU_PAUSE, insn_pause, INSN_CPU0, 40, 0, 0, 0}, 894 // Flags for Secondary Processor-Based VM-Execution Controls 895 {"WBINVD", CPU_WBINVD, insn_wbinvd, INSN_CPU1, 54, 0, 0, 0}, 896 {"DESC_TABLE (SGDT)", CPU_DESC_TABLE, insn_sgdt, INSN_CPU1, 46, 0, 0, 0}, 897 {"DESC_TABLE (LGDT)", CPU_DESC_TABLE, insn_lgdt, INSN_CPU1, 46, 0, 0, 0}, 898 {"DESC_TABLE (SIDT)", CPU_DESC_TABLE, insn_sidt, INSN_CPU1, 46, 0, 0, 0}, 899 {"DESC_TABLE (LIDT)", CPU_DESC_TABLE, insn_lidt, INSN_CPU1, 46, 0, 0, 0}, 900 {"DESC_TABLE (SLDT)", CPU_DESC_TABLE, insn_sldt, INSN_CPU1, 47, 0, 0, 0}, 901 {"DESC_TABLE (LLDT)", CPU_DESC_TABLE, insn_lldt, INSN_CPU1, 47, 0, 0, 0}, 902 {"DESC_TABLE (STR)", CPU_DESC_TABLE, insn_str, INSN_CPU1, 47, 0, 0, 0}, 903 /* LTR causes a #GP if done with a busy selector, so it is not tested. */ 904 {"RDRAND", CPU_RDRAND, insn_rdrand, INSN_CPU1, VMX_RDRAND, 0, 0, 0}, 905 {"RDSEED", CPU_RDSEED, insn_rdseed, INSN_CPU1, VMX_RDSEED, 0, 0, 0}, 906 // Instructions always trap 907 {"CPUID", 0, insn_cpuid, INSN_ALWAYS_TRAP, 10, 0, 0, 0}, 908 {"INVD", 0, insn_invd, INSN_ALWAYS_TRAP, 13, 0, 0, 0}, 909 // Instructions never trap 910 {NULL}, 911 }; 912 913 static int insn_intercept_init(struct vmcs *vmcs) 914 { 915 u32 ctrl_cpu, cur_insn; 916 917 ctrl_cpu = ctrl_cpu_rev[0].set | CPU_SECONDARY; 918 ctrl_cpu &= ctrl_cpu_rev[0].clr; 919 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu); 920 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu_rev[1].set); 921 cr3 = read_cr3(); 922 923 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 924 if (insn_table[cur_insn].supported_fn == NULL) 925 continue; 926 insn_table[cur_insn].disabled = !insn_table[cur_insn].supported_fn(); 927 } 928 return VMX_TEST_START; 929 } 930 931 static void insn_intercept_main(void) 932 { 933 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 934 vmx_set_test_stage(cur_insn * 2); 935 if ((insn_table[cur_insn].type == INSN_CPU0 && 936 !(ctrl_cpu_rev[0].clr & insn_table[cur_insn].flag)) || 937 (insn_table[cur_insn].type == INSN_CPU1 && 938 !(ctrl_cpu_rev[1].clr & insn_table[cur_insn].flag))) { 939 printf("\tCPU_CTRL%d.CPU_%s is not supported.\n", 940 insn_table[cur_insn].type - INSN_CPU0, 941 insn_table[cur_insn].name); 942 continue; 943 } 944 945 if (insn_table[cur_insn].disabled) { 946 printf("\tFeature required for %s is not supported.\n", 947 insn_table[cur_insn].name); 948 continue; 949 } 950 951 if ((insn_table[cur_insn].type == INSN_CPU0 && 952 !(ctrl_cpu_rev[0].set & insn_table[cur_insn].flag)) || 953 (insn_table[cur_insn].type == INSN_CPU1 && 954 !(ctrl_cpu_rev[1].set & insn_table[cur_insn].flag))) { 955 /* skip hlt, it stalls the guest and is tested below */ 956 if (insn_table[cur_insn].insn_func != insn_hlt) 957 insn_table[cur_insn].insn_func(); 958 report(vmx_get_test_stage() == cur_insn * 2, 959 "execute %s", 960 insn_table[cur_insn].name); 961 } else if (insn_table[cur_insn].type != INSN_ALWAYS_TRAP) 962 printf("\tCPU_CTRL%d.CPU_%s always traps.\n", 963 insn_table[cur_insn].type - INSN_CPU0, 964 insn_table[cur_insn].name); 965 966 vmcall(); 967 968 insn_table[cur_insn].insn_func(); 969 report(vmx_get_test_stage() == cur_insn * 2 + 1, 970 "intercept %s", 971 insn_table[cur_insn].name); 972 973 vmx_set_test_stage(cur_insn * 2 + 1); 974 vmcall(); 975 } 976 } 977 978 static int insn_intercept_exit_handler(union exit_reason exit_reason) 979 { 980 u64 guest_rip; 981 ulong exit_qual; 982 u32 insn_len; 983 u32 insn_info; 984 bool pass; 985 986 guest_rip = vmcs_read(GUEST_RIP); 987 exit_qual = vmcs_read(EXI_QUALIFICATION); 988 insn_len = vmcs_read(EXI_INST_LEN); 989 insn_info = vmcs_read(EXI_INST_INFO); 990 991 if (exit_reason.basic == VMX_VMCALL) { 992 u32 val = 0; 993 994 if (insn_table[cur_insn].type == INSN_CPU0) 995 val = vmcs_read(CPU_EXEC_CTRL0); 996 else if (insn_table[cur_insn].type == INSN_CPU1) 997 val = vmcs_read(CPU_EXEC_CTRL1); 998 999 if (vmx_get_test_stage() & 1) 1000 val &= ~insn_table[cur_insn].flag; 1001 else 1002 val |= insn_table[cur_insn].flag; 1003 1004 if (insn_table[cur_insn].type == INSN_CPU0) 1005 vmcs_write(CPU_EXEC_CTRL0, val | ctrl_cpu_rev[0].set); 1006 else if (insn_table[cur_insn].type == INSN_CPU1) 1007 vmcs_write(CPU_EXEC_CTRL1, val | ctrl_cpu_rev[1].set); 1008 } else { 1009 pass = (cur_insn * 2 == vmx_get_test_stage()) && 1010 insn_table[cur_insn].reason == exit_reason.full; 1011 if (insn_table[cur_insn].test_field & FIELD_EXIT_QUAL && 1012 insn_table[cur_insn].exit_qual != exit_qual) 1013 pass = false; 1014 if (insn_table[cur_insn].test_field & FIELD_INSN_INFO && 1015 insn_table[cur_insn].insn_info != insn_info) 1016 pass = false; 1017 if (pass) 1018 vmx_inc_test_stage(); 1019 } 1020 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1021 return VMX_TEST_RESUME; 1022 } 1023 1024 /** 1025 * __setup_ept - Setup the VMCS fields to enable Extended Page Tables (EPT) 1026 * @hpa: Host physical address of the top-level, a.k.a. root, EPT table 1027 * @enable_ad: Whether or not to enable Access/Dirty bits for EPT entries 1028 * 1029 * Returns 0 on success, 1 on failure. 1030 * 1031 * Note that @hpa doesn't need to point at actual memory if VM-Launch is 1032 * expected to fail, e.g. setup_dummy_ept() arbitrarily passes '0' to satisfy 1033 * the various EPTP consistency checks, but doesn't ensure backing for HPA '0'. 1034 */ 1035 static int __setup_ept(u64 hpa, bool enable_ad) 1036 { 1037 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1038 !(ctrl_cpu_rev[1].clr & CPU_EPT)) { 1039 printf("\tEPT is not supported\n"); 1040 return 1; 1041 } 1042 if (!(ept_vpid.val & EPT_CAP_WB)) { 1043 printf("\tWB memtype for EPT walks not supported\n"); 1044 return 1; 1045 } 1046 if (!(ept_vpid.val & EPT_CAP_PWL4)) { 1047 printf("\tPWL4 is not supported\n"); 1048 return 1; 1049 } 1050 1051 eptp = EPT_MEM_TYPE_WB; 1052 eptp |= (3 << EPTP_PG_WALK_LEN_SHIFT); 1053 eptp |= hpa; 1054 if (enable_ad) 1055 eptp |= EPTP_AD_FLAG; 1056 1057 vmcs_write(EPTP, eptp); 1058 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0)| CPU_SECONDARY); 1059 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1)| CPU_EPT); 1060 1061 return 0; 1062 } 1063 1064 /** 1065 * setup_ept - Enable Extended Page Tables (EPT) and setup an identity map 1066 * @enable_ad: Whether or not to enable Access/Dirty bits for EPT entries 1067 * 1068 * Returns 0 on success, 1 on failure. 1069 * 1070 * This is the "real" function for setting up EPT tables, i.e. use this for 1071 * tests that need to run code in the guest with EPT enabled. 1072 */ 1073 static int setup_ept(bool enable_ad) 1074 { 1075 unsigned long end_of_memory; 1076 1077 pml4 = alloc_page(); 1078 1079 if (__setup_ept(virt_to_phys(pml4), enable_ad)) 1080 return 1; 1081 1082 end_of_memory = fwcfg_get_u64(FW_CFG_RAM_SIZE); 1083 if (end_of_memory < (1ul << 32)) 1084 end_of_memory = (1ul << 32); 1085 /* Cannot use large EPT pages if we need to track EPT 1086 * accessed/dirty bits at 4K granularity. 1087 */ 1088 setup_ept_range(pml4, 0, end_of_memory, 0, 1089 !enable_ad && ept_2m_supported(), 1090 EPT_WA | EPT_RA | EPT_EA); 1091 return 0; 1092 } 1093 1094 /** 1095 * setup_dummy_ept - Enable Extended Page Tables (EPT) with a dummy root HPA 1096 * 1097 * Setup EPT using a semi-arbitrary dummy root HPA. This function is intended 1098 * for use by tests that need EPT enabled to verify dependent VMCS controls 1099 * but never expect to fully enter the guest, i.e. don't need setup the actual 1100 * EPT tables. 1101 */ 1102 static void setup_dummy_ept(void) 1103 { 1104 if (__setup_ept(0, false)) 1105 report_abort("EPT setup unexpectedly failed"); 1106 } 1107 1108 static int enable_unrestricted_guest(bool need_valid_ept) 1109 { 1110 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1111 !(ctrl_cpu_rev[1].clr & CPU_URG) || 1112 !(ctrl_cpu_rev[1].clr & CPU_EPT)) 1113 return 1; 1114 1115 if (need_valid_ept) 1116 setup_ept(false); 1117 else 1118 setup_dummy_ept(); 1119 1120 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 1121 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | CPU_URG); 1122 1123 return 0; 1124 } 1125 1126 static void ept_enable_ad_bits(void) 1127 { 1128 eptp |= EPTP_AD_FLAG; 1129 vmcs_write(EPTP, eptp); 1130 } 1131 1132 static void ept_disable_ad_bits(void) 1133 { 1134 eptp &= ~EPTP_AD_FLAG; 1135 vmcs_write(EPTP, eptp); 1136 } 1137 1138 static int ept_ad_enabled(void) 1139 { 1140 return eptp & EPTP_AD_FLAG; 1141 } 1142 1143 static void ept_enable_ad_bits_or_skip_test(void) 1144 { 1145 if (!ept_ad_bits_supported()) 1146 test_skip("EPT AD bits not supported."); 1147 ept_enable_ad_bits(); 1148 } 1149 1150 static int apic_version; 1151 1152 static int ept_init_common(bool have_ad) 1153 { 1154 int ret; 1155 struct pci_dev pcidev; 1156 1157 /* INVEPT is required by the EPT violation handler. */ 1158 if (!is_invept_type_supported(INVEPT_SINGLE)) 1159 return VMX_TEST_EXIT; 1160 1161 if (setup_ept(have_ad)) 1162 return VMX_TEST_EXIT; 1163 1164 data_page1 = alloc_page(); 1165 data_page2 = alloc_page(); 1166 *((u32 *)data_page1) = MAGIC_VAL_1; 1167 *((u32 *)data_page2) = MAGIC_VAL_2; 1168 install_ept(pml4, (unsigned long)data_page1, (unsigned long)data_page2, 1169 EPT_RA | EPT_WA | EPT_EA); 1170 1171 apic_version = apic_read(APIC_LVR); 1172 1173 ret = pci_find_dev(PCI_VENDOR_ID_REDHAT, PCI_DEVICE_ID_REDHAT_TEST); 1174 if (ret != PCIDEVADDR_INVALID) { 1175 pci_dev_init(&pcidev, ret); 1176 pci_physaddr = pcidev.resource[PCI_TESTDEV_BAR_MEM]; 1177 } 1178 1179 return VMX_TEST_START; 1180 } 1181 1182 static int ept_init(struct vmcs *vmcs) 1183 { 1184 return ept_init_common(false); 1185 } 1186 1187 static void ept_common(void) 1188 { 1189 vmx_set_test_stage(0); 1190 if (*((u32 *)data_page2) != MAGIC_VAL_1 || 1191 *((u32 *)data_page1) != MAGIC_VAL_1) 1192 report_fail("EPT basic framework - read"); 1193 else { 1194 *((u32 *)data_page2) = MAGIC_VAL_3; 1195 vmcall(); 1196 if (vmx_get_test_stage() == 1) { 1197 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1198 *((u32 *)data_page2) == MAGIC_VAL_2) 1199 report_pass("EPT basic framework"); 1200 else 1201 report_pass("EPT basic framework - remap"); 1202 } 1203 } 1204 // Test EPT Misconfigurations 1205 vmx_set_test_stage(1); 1206 vmcall(); 1207 *((u32 *)data_page1) = MAGIC_VAL_1; 1208 if (vmx_get_test_stage() != 2) { 1209 report_fail("EPT misconfigurations"); 1210 goto t1; 1211 } 1212 vmx_set_test_stage(2); 1213 vmcall(); 1214 *((u32 *)data_page1) = MAGIC_VAL_1; 1215 report(vmx_get_test_stage() == 3, "EPT misconfigurations"); 1216 t1: 1217 // Test EPT violation 1218 vmx_set_test_stage(3); 1219 vmcall(); 1220 *((u32 *)data_page1) = MAGIC_VAL_1; 1221 report(vmx_get_test_stage() == 4, "EPT violation - page permission"); 1222 // Violation caused by EPT paging structure 1223 vmx_set_test_stage(4); 1224 vmcall(); 1225 *((u32 *)data_page1) = MAGIC_VAL_2; 1226 report(vmx_get_test_stage() == 5, "EPT violation - paging structure"); 1227 1228 // MMIO Read/Write 1229 vmx_set_test_stage(5); 1230 vmcall(); 1231 1232 *(u32 volatile *)pci_physaddr; 1233 report(vmx_get_test_stage() == 6, "MMIO EPT violation - read"); 1234 1235 *(u32 volatile *)pci_physaddr = MAGIC_VAL_1; 1236 report(vmx_get_test_stage() == 7, "MMIO EPT violation - write"); 1237 } 1238 1239 static void ept_main(void) 1240 { 1241 ept_common(); 1242 1243 // Test EPT access to L1 MMIO 1244 vmx_set_test_stage(7); 1245 report(*((u32 *)0xfee00030UL) == apic_version, "EPT - MMIO access"); 1246 1247 // Test invalid operand for INVEPT 1248 vmcall(); 1249 report(vmx_get_test_stage() == 8, "EPT - unsupported INVEPT"); 1250 } 1251 1252 static bool invept_test(int type, u64 eptp) 1253 { 1254 bool ret, supported; 1255 1256 supported = ept_vpid.val & (EPT_CAP_INVEPT_SINGLE >> INVEPT_SINGLE << type); 1257 ret = __invept(type, eptp); 1258 1259 if (ret == !supported) 1260 return false; 1261 1262 if (!supported) 1263 printf("WARNING: unsupported invept passed!\n"); 1264 else 1265 printf("WARNING: invept failed!\n"); 1266 1267 return true; 1268 } 1269 1270 static int pml_exit_handler(union exit_reason exit_reason) 1271 { 1272 u16 index, count; 1273 u64 *pmlbuf = pml_log; 1274 u64 guest_rip = vmcs_read(GUEST_RIP);; 1275 u64 guest_cr3 = vmcs_read(GUEST_CR3); 1276 u32 insn_len = vmcs_read(EXI_INST_LEN); 1277 1278 switch (exit_reason.basic) { 1279 case VMX_VMCALL: 1280 switch (vmx_get_test_stage()) { 1281 case 0: 1282 index = vmcs_read(GUEST_PML_INDEX); 1283 for (count = index + 1; count < PML_INDEX; count++) { 1284 if (pmlbuf[count] == (u64)data_page2) { 1285 vmx_inc_test_stage(); 1286 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1287 break; 1288 } 1289 } 1290 break; 1291 case 1: 1292 index = vmcs_read(GUEST_PML_INDEX); 1293 /* Keep clearing the dirty bit till a overflow */ 1294 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1295 break; 1296 default: 1297 report_fail("unexpected stage, %d.", 1298 vmx_get_test_stage()); 1299 print_vmexit_info(exit_reason); 1300 return VMX_TEST_VMEXIT; 1301 } 1302 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1303 return VMX_TEST_RESUME; 1304 case VMX_PML_FULL: 1305 vmx_inc_test_stage(); 1306 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1307 return VMX_TEST_RESUME; 1308 default: 1309 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 1310 print_vmexit_info(exit_reason); 1311 } 1312 return VMX_TEST_VMEXIT; 1313 } 1314 1315 static int ept_exit_handler_common(union exit_reason exit_reason, bool have_ad) 1316 { 1317 u64 guest_rip; 1318 u64 guest_cr3; 1319 u32 insn_len; 1320 u32 exit_qual; 1321 static unsigned long data_page1_pte, data_page1_pte_pte, memaddr_pte, 1322 guest_pte_addr; 1323 1324 guest_rip = vmcs_read(GUEST_RIP); 1325 guest_cr3 = vmcs_read(GUEST_CR3); 1326 insn_len = vmcs_read(EXI_INST_LEN); 1327 exit_qual = vmcs_read(EXI_QUALIFICATION); 1328 pteval_t *ptep; 1329 switch (exit_reason.basic) { 1330 case VMX_VMCALL: 1331 switch (vmx_get_test_stage()) { 1332 case 0: 1333 check_ept_ad(pml4, guest_cr3, 1334 (unsigned long)data_page1, 1335 have_ad ? EPT_ACCESS_FLAG : 0, 1336 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1337 check_ept_ad(pml4, guest_cr3, 1338 (unsigned long)data_page2, 1339 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0, 1340 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1341 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1342 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1343 if (have_ad) 1344 invept(INVEPT_SINGLE, eptp); 1345 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1346 *((u32 *)data_page2) == MAGIC_VAL_2) { 1347 vmx_inc_test_stage(); 1348 install_ept(pml4, (unsigned long)data_page2, 1349 (unsigned long)data_page2, 1350 EPT_RA | EPT_WA | EPT_EA); 1351 } else 1352 report_fail("EPT basic framework - write"); 1353 break; 1354 case 1: 1355 install_ept(pml4, (unsigned long)data_page1, 1356 (unsigned long)data_page1, EPT_WA); 1357 invept(INVEPT_SINGLE, eptp); 1358 break; 1359 case 2: 1360 install_ept(pml4, (unsigned long)data_page1, 1361 (unsigned long)data_page1, 1362 EPT_RA | EPT_WA | EPT_EA | 1363 (2 << EPT_MEM_TYPE_SHIFT)); 1364 invept(INVEPT_SINGLE, eptp); 1365 break; 1366 case 3: 1367 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1368 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)data_page1, 1369 1, &data_page1_pte)); 1370 set_ept_pte(pml4, (unsigned long)data_page1, 1371 1, data_page1_pte & ~EPT_PRESENT); 1372 invept(INVEPT_SINGLE, eptp); 1373 break; 1374 case 4: 1375 ptep = get_pte_level((pgd_t *)guest_cr3, data_page1, /*level=*/2); 1376 guest_pte_addr = virt_to_phys(ptep) & PAGE_MASK; 1377 1378 TEST_ASSERT(get_ept_pte(pml4, guest_pte_addr, 2, &data_page1_pte_pte)); 1379 set_ept_pte(pml4, guest_pte_addr, 2, 1380 data_page1_pte_pte & ~EPT_PRESENT); 1381 invept(INVEPT_SINGLE, eptp); 1382 break; 1383 case 5: 1384 install_ept(pml4, (unsigned long)pci_physaddr, 1385 (unsigned long)pci_physaddr, 0); 1386 invept(INVEPT_SINGLE, eptp); 1387 break; 1388 case 7: 1389 if (!invept_test(0, eptp)) 1390 vmx_inc_test_stage(); 1391 break; 1392 // Should not reach here 1393 default: 1394 report_fail("ERROR - unexpected stage, %d.", 1395 vmx_get_test_stage()); 1396 print_vmexit_info(exit_reason); 1397 return VMX_TEST_VMEXIT; 1398 } 1399 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1400 return VMX_TEST_RESUME; 1401 case VMX_EPT_MISCONFIG: 1402 switch (vmx_get_test_stage()) { 1403 case 1: 1404 case 2: 1405 vmx_inc_test_stage(); 1406 install_ept(pml4, (unsigned long)data_page1, 1407 (unsigned long)data_page1, 1408 EPT_RA | EPT_WA | EPT_EA); 1409 invept(INVEPT_SINGLE, eptp); 1410 break; 1411 // Should not reach here 1412 default: 1413 report_fail("ERROR - unexpected stage, %d.", 1414 vmx_get_test_stage()); 1415 print_vmexit_info(exit_reason); 1416 return VMX_TEST_VMEXIT; 1417 } 1418 return VMX_TEST_RESUME; 1419 case VMX_EPT_VIOLATION: 1420 /* 1421 * Exit-qualifications are masked not to account for advanced 1422 * VM-exit information. Once KVM supports this feature, this 1423 * masking should be removed. 1424 */ 1425 exit_qual &= ~EPT_VLT_GUEST_MASK; 1426 1427 switch(vmx_get_test_stage()) { 1428 case 3: 1429 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1430 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1431 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1432 if (exit_qual == (EPT_VLT_WR | EPT_VLT_LADDR_VLD | 1433 EPT_VLT_PADDR)) 1434 vmx_inc_test_stage(); 1435 set_ept_pte(pml4, (unsigned long)data_page1, 1436 1, data_page1_pte | (EPT_PRESENT)); 1437 invept(INVEPT_SINGLE, eptp); 1438 break; 1439 case 4: 1440 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1441 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1442 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1443 if (exit_qual == (EPT_VLT_RD | 1444 (have_ad ? EPT_VLT_WR : 0) | 1445 EPT_VLT_LADDR_VLD)) 1446 vmx_inc_test_stage(); 1447 set_ept_pte(pml4, guest_pte_addr, 2, 1448 data_page1_pte_pte | (EPT_PRESENT)); 1449 invept(INVEPT_SINGLE, eptp); 1450 break; 1451 case 5: 1452 if (exit_qual & EPT_VLT_RD) 1453 vmx_inc_test_stage(); 1454 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1455 1, &memaddr_pte)); 1456 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA); 1457 invept(INVEPT_SINGLE, eptp); 1458 break; 1459 case 6: 1460 if (exit_qual & EPT_VLT_WR) 1461 vmx_inc_test_stage(); 1462 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1463 1, &memaddr_pte)); 1464 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA | EPT_WA); 1465 invept(INVEPT_SINGLE, eptp); 1466 break; 1467 default: 1468 // Should not reach here 1469 report_fail("ERROR : unexpected stage, %d", 1470 vmx_get_test_stage()); 1471 print_vmexit_info(exit_reason); 1472 return VMX_TEST_VMEXIT; 1473 } 1474 return VMX_TEST_RESUME; 1475 default: 1476 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 1477 print_vmexit_info(exit_reason); 1478 } 1479 return VMX_TEST_VMEXIT; 1480 } 1481 1482 static int ept_exit_handler(union exit_reason exit_reason) 1483 { 1484 return ept_exit_handler_common(exit_reason, false); 1485 } 1486 1487 static int eptad_init(struct vmcs *vmcs) 1488 { 1489 int r = ept_init_common(true); 1490 1491 if (r == VMX_TEST_EXIT) 1492 return r; 1493 1494 if (!ept_ad_bits_supported()) { 1495 printf("\tEPT A/D bits are not supported"); 1496 return VMX_TEST_EXIT; 1497 } 1498 1499 return r; 1500 } 1501 1502 static int pml_init(struct vmcs *vmcs) 1503 { 1504 u32 ctrl_cpu; 1505 int r = eptad_init(vmcs); 1506 1507 if (r == VMX_TEST_EXIT) 1508 return r; 1509 1510 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1511 !(ctrl_cpu_rev[1].clr & CPU_PML)) { 1512 printf("\tPML is not supported"); 1513 return VMX_TEST_EXIT; 1514 } 1515 1516 pml_log = alloc_page(); 1517 vmcs_write(PMLADDR, (u64)pml_log); 1518 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1519 1520 ctrl_cpu = vmcs_read(CPU_EXEC_CTRL1) | CPU_PML; 1521 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu); 1522 1523 return VMX_TEST_START; 1524 } 1525 1526 static void pml_main(void) 1527 { 1528 int count = 0; 1529 1530 vmx_set_test_stage(0); 1531 *((u32 *)data_page2) = 0x1; 1532 vmcall(); 1533 report(vmx_get_test_stage() == 1, "PML - Dirty GPA Logging"); 1534 1535 while (vmx_get_test_stage() == 1) { 1536 vmcall(); 1537 *((u32 *)data_page2) = 0x1; 1538 if (count++ > PML_INDEX) 1539 break; 1540 } 1541 report(vmx_get_test_stage() == 2, "PML Full Event"); 1542 } 1543 1544 static void eptad_main(void) 1545 { 1546 ept_common(); 1547 } 1548 1549 static int eptad_exit_handler(union exit_reason exit_reason) 1550 { 1551 return ept_exit_handler_common(exit_reason, true); 1552 } 1553 1554 #define TIMER_VECTOR 222 1555 1556 static volatile bool timer_fired; 1557 1558 static void timer_isr(isr_regs_t *regs) 1559 { 1560 timer_fired = true; 1561 apic_write(APIC_EOI, 0); 1562 } 1563 1564 static int interrupt_init(struct vmcs *vmcs) 1565 { 1566 msr_bmp_init(); 1567 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1568 handle_irq(TIMER_VECTOR, timer_isr); 1569 return VMX_TEST_START; 1570 } 1571 1572 static void interrupt_main(void) 1573 { 1574 long long start, loops; 1575 1576 vmx_set_test_stage(0); 1577 1578 apic_write(APIC_LVTT, TIMER_VECTOR); 1579 irq_enable(); 1580 1581 apic_write(APIC_TMICT, 1); 1582 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1583 asm volatile ("nop"); 1584 report(timer_fired, "direct interrupt while running guest"); 1585 1586 apic_write(APIC_TMICT, 0); 1587 irq_disable(); 1588 vmcall(); 1589 timer_fired = false; 1590 apic_write(APIC_TMICT, 1); 1591 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1592 asm volatile ("nop"); 1593 report(timer_fired, "intercepted interrupt while running guest"); 1594 1595 irq_enable(); 1596 apic_write(APIC_TMICT, 0); 1597 irq_disable(); 1598 vmcall(); 1599 timer_fired = false; 1600 start = rdtsc(); 1601 apic_write(APIC_TMICT, 1000000); 1602 1603 safe_halt(); 1604 1605 report(rdtsc() - start > 1000000 && timer_fired, 1606 "direct interrupt + hlt"); 1607 1608 apic_write(APIC_TMICT, 0); 1609 irq_disable(); 1610 vmcall(); 1611 timer_fired = false; 1612 start = rdtsc(); 1613 apic_write(APIC_TMICT, 1000000); 1614 1615 safe_halt(); 1616 1617 report(rdtsc() - start > 10000 && timer_fired, 1618 "intercepted interrupt + hlt"); 1619 1620 apic_write(APIC_TMICT, 0); 1621 irq_disable(); 1622 vmcall(); 1623 timer_fired = false; 1624 start = rdtsc(); 1625 apic_write(APIC_TMICT, 1000000); 1626 1627 irq_enable(); 1628 asm volatile ("nop"); 1629 vmcall(); 1630 1631 report(rdtsc() - start > 10000 && timer_fired, 1632 "direct interrupt + activity state hlt"); 1633 1634 apic_write(APIC_TMICT, 0); 1635 irq_disable(); 1636 vmcall(); 1637 timer_fired = false; 1638 start = rdtsc(); 1639 apic_write(APIC_TMICT, 1000000); 1640 1641 irq_enable(); 1642 asm volatile ("nop"); 1643 vmcall(); 1644 1645 report(rdtsc() - start > 10000 && timer_fired, 1646 "intercepted interrupt + activity state hlt"); 1647 1648 apic_write(APIC_TMICT, 0); 1649 irq_disable(); 1650 vmx_set_test_stage(7); 1651 vmcall(); 1652 timer_fired = false; 1653 apic_write(APIC_TMICT, 1); 1654 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1655 asm volatile ("nop"); 1656 report(timer_fired, 1657 "running a guest with interrupt acknowledgement set"); 1658 1659 apic_write(APIC_TMICT, 0); 1660 irq_enable(); 1661 timer_fired = false; 1662 vmcall(); 1663 report(timer_fired, "Inject an event to a halted guest"); 1664 } 1665 1666 static int interrupt_exit_handler(union exit_reason exit_reason) 1667 { 1668 u64 guest_rip = vmcs_read(GUEST_RIP); 1669 u32 insn_len = vmcs_read(EXI_INST_LEN); 1670 1671 switch (exit_reason.basic) { 1672 case VMX_VMCALL: 1673 switch (vmx_get_test_stage()) { 1674 case 0: 1675 case 2: 1676 case 5: 1677 vmcs_write(PIN_CONTROLS, 1678 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1679 break; 1680 case 7: 1681 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_INTA); 1682 vmcs_write(PIN_CONTROLS, 1683 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1684 break; 1685 case 1: 1686 case 3: 1687 vmcs_write(PIN_CONTROLS, 1688 vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1689 break; 1690 case 4: 1691 case 6: 1692 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1693 break; 1694 1695 case 8: 1696 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1697 vmcs_write(ENT_INTR_INFO, 1698 TIMER_VECTOR | 1699 (VMX_INTR_TYPE_EXT_INTR << INTR_INFO_INTR_TYPE_SHIFT) | 1700 INTR_INFO_VALID_MASK); 1701 break; 1702 } 1703 vmx_inc_test_stage(); 1704 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1705 return VMX_TEST_RESUME; 1706 case VMX_EXTINT: 1707 if (vmcs_read(EXI_CONTROLS) & EXI_INTA) { 1708 int vector = vmcs_read(EXI_INTR_INFO) & 0xff; 1709 handle_external_interrupt(vector); 1710 } else { 1711 irq_enable(); 1712 asm volatile ("nop"); 1713 irq_disable(); 1714 } 1715 if (vmx_get_test_stage() >= 2) 1716 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 1717 return VMX_TEST_RESUME; 1718 default: 1719 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 1720 print_vmexit_info(exit_reason); 1721 } 1722 1723 return VMX_TEST_VMEXIT; 1724 } 1725 1726 1727 static volatile int nmi_fired; 1728 1729 #define NMI_DELAY 100000000ULL 1730 1731 static void nmi_isr(isr_regs_t *regs) 1732 { 1733 nmi_fired = true; 1734 } 1735 1736 static int nmi_hlt_init(struct vmcs *vmcs) 1737 { 1738 msr_bmp_init(); 1739 handle_irq(NMI_VECTOR, nmi_isr); 1740 vmcs_write(PIN_CONTROLS, 1741 vmcs_read(PIN_CONTROLS) & ~PIN_NMI); 1742 vmcs_write(PIN_CONTROLS, 1743 vmcs_read(PIN_CONTROLS) & ~PIN_VIRT_NMI); 1744 return VMX_TEST_START; 1745 } 1746 1747 static void nmi_message_thread(void *data) 1748 { 1749 while (vmx_get_test_stage() != 1) 1750 pause(); 1751 1752 delay(NMI_DELAY); 1753 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_NMI | APIC_INT_ASSERT, id_map[0]); 1754 1755 while (vmx_get_test_stage() != 2) 1756 pause(); 1757 1758 delay(NMI_DELAY); 1759 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_NMI | APIC_INT_ASSERT, id_map[0]); 1760 } 1761 1762 static void nmi_hlt_main(void) 1763 { 1764 long long start; 1765 1766 if (cpu_count() < 2) { 1767 report_skip("%s : CPU count < 2", __func__); 1768 vmx_set_test_stage(-1); 1769 return; 1770 } 1771 1772 vmx_set_test_stage(0); 1773 on_cpu_async(1, nmi_message_thread, NULL); 1774 start = rdtsc(); 1775 vmx_set_test_stage(1); 1776 asm volatile ("hlt"); 1777 report((rdtsc() - start > NMI_DELAY) && nmi_fired, 1778 "direct NMI + hlt"); 1779 if (!nmi_fired) 1780 vmx_set_test_stage(-1); 1781 nmi_fired = false; 1782 1783 vmcall(); 1784 1785 start = rdtsc(); 1786 vmx_set_test_stage(2); 1787 asm volatile ("hlt"); 1788 report((rdtsc() - start > NMI_DELAY) && !nmi_fired, 1789 "intercepted NMI + hlt"); 1790 if (nmi_fired) { 1791 report(!nmi_fired, "intercepted NMI was dispatched"); 1792 vmx_set_test_stage(-1); 1793 return; 1794 } 1795 vmx_set_test_stage(3); 1796 } 1797 1798 static int nmi_hlt_exit_handler(union exit_reason exit_reason) 1799 { 1800 u64 guest_rip = vmcs_read(GUEST_RIP); 1801 u32 insn_len = vmcs_read(EXI_INST_LEN); 1802 1803 switch (vmx_get_test_stage()) { 1804 case 1: 1805 if (exit_reason.basic != VMX_VMCALL) { 1806 report_fail("VMEXIT not due to vmcall. Exit reason 0x%x", 1807 exit_reason.full); 1808 print_vmexit_info(exit_reason); 1809 return VMX_TEST_VMEXIT; 1810 } 1811 1812 vmcs_write(PIN_CONTROLS, 1813 vmcs_read(PIN_CONTROLS) | PIN_NMI); 1814 vmcs_write(PIN_CONTROLS, 1815 vmcs_read(PIN_CONTROLS) | PIN_VIRT_NMI); 1816 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1817 break; 1818 1819 case 2: 1820 if (exit_reason.basic != VMX_EXC_NMI) { 1821 report_fail("VMEXIT not due to NMI intercept. Exit reason 0x%x", 1822 exit_reason.full); 1823 print_vmexit_info(exit_reason); 1824 return VMX_TEST_VMEXIT; 1825 } 1826 report_pass("NMI intercept while running guest"); 1827 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 1828 break; 1829 1830 case 3: 1831 break; 1832 1833 default: 1834 return VMX_TEST_VMEXIT; 1835 } 1836 1837 if (vmx_get_test_stage() == 3) 1838 return VMX_TEST_VMEXIT; 1839 1840 return VMX_TEST_RESUME; 1841 } 1842 1843 1844 static int dbgctls_init(struct vmcs *vmcs) 1845 { 1846 u64 dr7 = 0x402; 1847 u64 zero = 0; 1848 1849 msr_bmp_init(); 1850 asm volatile( 1851 "mov %0,%%dr0\n\t" 1852 "mov %0,%%dr1\n\t" 1853 "mov %0,%%dr2\n\t" 1854 "mov %1,%%dr7\n\t" 1855 : : "r" (zero), "r" (dr7)); 1856 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1857 vmcs_write(GUEST_DR7, 0x404); 1858 vmcs_write(GUEST_DEBUGCTL, 0x2); 1859 1860 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 1861 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_SAVE_DBGCTLS); 1862 1863 return VMX_TEST_START; 1864 } 1865 1866 static void dbgctls_main(void) 1867 { 1868 u64 dr7, debugctl; 1869 1870 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1871 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1872 /* Commented out: KVM does not support DEBUGCTL so far */ 1873 (void)debugctl; 1874 report(dr7 == 0x404, "Load debug controls" /* && debugctl == 0x2 */); 1875 1876 dr7 = 0x408; 1877 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1878 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1879 1880 vmx_set_test_stage(0); 1881 vmcall(); 1882 report(vmx_get_test_stage() == 1, "Save debug controls"); 1883 1884 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS || 1885 ctrl_exit_rev.set & EXI_SAVE_DBGCTLS) { 1886 printf("\tDebug controls are always loaded/saved\n"); 1887 return; 1888 } 1889 vmx_set_test_stage(2); 1890 vmcall(); 1891 1892 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1893 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1894 /* Commented out: KVM does not support DEBUGCTL so far */ 1895 (void)debugctl; 1896 report(dr7 == 0x402, 1897 "Guest=host debug controls" /* && debugctl == 0x1 */); 1898 1899 dr7 = 0x408; 1900 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1901 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1902 1903 vmx_set_test_stage(3); 1904 vmcall(); 1905 report(vmx_get_test_stage() == 4, "Don't save debug controls"); 1906 } 1907 1908 static int dbgctls_exit_handler(union exit_reason exit_reason) 1909 { 1910 u32 insn_len = vmcs_read(EXI_INST_LEN); 1911 u64 guest_rip = vmcs_read(GUEST_RIP); 1912 u64 dr7, debugctl; 1913 1914 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1915 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1916 1917 switch (exit_reason.basic) { 1918 case VMX_VMCALL: 1919 switch (vmx_get_test_stage()) { 1920 case 0: 1921 if (dr7 == 0x400 && debugctl == 0 && 1922 vmcs_read(GUEST_DR7) == 0x408 /* && 1923 Commented out: KVM does not support DEBUGCTL so far 1924 vmcs_read(GUEST_DEBUGCTL) == 0x3 */) 1925 vmx_inc_test_stage(); 1926 break; 1927 case 2: 1928 dr7 = 0x402; 1929 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1930 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1931 vmcs_write(GUEST_DR7, 0x404); 1932 vmcs_write(GUEST_DEBUGCTL, 0x2); 1933 1934 vmcs_write(ENT_CONTROLS, 1935 vmcs_read(ENT_CONTROLS) & ~ENT_LOAD_DBGCTLS); 1936 vmcs_write(EXI_CONTROLS, 1937 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_DBGCTLS); 1938 break; 1939 case 3: 1940 if (dr7 == 0x400 && debugctl == 0 && 1941 vmcs_read(GUEST_DR7) == 0x404 /* && 1942 Commented out: KVM does not support DEBUGCTL so far 1943 vmcs_read(GUEST_DEBUGCTL) == 0x2 */) 1944 vmx_inc_test_stage(); 1945 break; 1946 } 1947 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1948 return VMX_TEST_RESUME; 1949 default: 1950 report_fail("Unknown exit reason, %d", exit_reason.full); 1951 print_vmexit_info(exit_reason); 1952 } 1953 return VMX_TEST_VMEXIT; 1954 } 1955 1956 struct vmx_msr_entry { 1957 u32 index; 1958 u32 reserved; 1959 u64 value; 1960 } __attribute__((packed)); 1961 1962 #define MSR_MAGIC 0x31415926 1963 struct vmx_msr_entry *exit_msr_store, *entry_msr_load, *exit_msr_load; 1964 1965 static int msr_switch_init(struct vmcs *vmcs) 1966 { 1967 msr_bmp_init(); 1968 exit_msr_store = alloc_page(); 1969 exit_msr_load = alloc_page(); 1970 entry_msr_load = alloc_page(); 1971 entry_msr_load[0].index = MSR_KERNEL_GS_BASE; 1972 entry_msr_load[0].value = MSR_MAGIC; 1973 1974 vmx_set_test_stage(1); 1975 vmcs_write(ENT_MSR_LD_CNT, 1); 1976 vmcs_write(ENTER_MSR_LD_ADDR, (u64)entry_msr_load); 1977 vmcs_write(EXI_MSR_ST_CNT, 1); 1978 vmcs_write(EXIT_MSR_ST_ADDR, (u64)exit_msr_store); 1979 vmcs_write(EXI_MSR_LD_CNT, 1); 1980 vmcs_write(EXIT_MSR_LD_ADDR, (u64)exit_msr_load); 1981 return VMX_TEST_START; 1982 } 1983 1984 static void msr_switch_main(void) 1985 { 1986 if (vmx_get_test_stage() == 1) { 1987 report(rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC, 1988 "VM entry MSR load"); 1989 vmx_set_test_stage(2); 1990 wrmsr(MSR_KERNEL_GS_BASE, MSR_MAGIC + 1); 1991 exit_msr_store[0].index = MSR_KERNEL_GS_BASE; 1992 exit_msr_load[0].index = MSR_KERNEL_GS_BASE; 1993 exit_msr_load[0].value = MSR_MAGIC + 2; 1994 } 1995 vmcall(); 1996 } 1997 1998 static int msr_switch_exit_handler(union exit_reason exit_reason) 1999 { 2000 if (exit_reason.basic == VMX_VMCALL && vmx_get_test_stage() == 2) { 2001 report(exit_msr_store[0].value == MSR_MAGIC + 1, 2002 "VM exit MSR store"); 2003 report(rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC + 2, 2004 "VM exit MSR load"); 2005 vmx_set_test_stage(3); 2006 entry_msr_load[0].index = MSR_FS_BASE; 2007 return VMX_TEST_RESUME; 2008 } 2009 printf("ERROR %s: unexpected stage=%u or reason=0x%x\n", 2010 __func__, vmx_get_test_stage(), exit_reason.full); 2011 return VMX_TEST_EXIT; 2012 } 2013 2014 static int msr_switch_entry_failure(struct vmentry_result *result) 2015 { 2016 if (result->vm_fail) { 2017 printf("ERROR %s: VM-Fail on %s\n", __func__, result->instr); 2018 return VMX_TEST_EXIT; 2019 } 2020 2021 if (result->exit_reason.failed_vmentry && 2022 result->exit_reason.basic == VMX_FAIL_MSR && 2023 vmx_get_test_stage() == 3) { 2024 report(vmcs_read(EXI_QUALIFICATION) == 1, 2025 "VM entry MSR load: try to load FS_BASE"); 2026 return VMX_TEST_VMEXIT; 2027 } 2028 printf("ERROR %s: unexpected stage=%u or reason=%x\n", 2029 __func__, vmx_get_test_stage(), result->exit_reason.full); 2030 return VMX_TEST_EXIT; 2031 } 2032 2033 static int vmmcall_init(struct vmcs *vmcs) 2034 { 2035 vmcs_write(EXC_BITMAP, 1 << UD_VECTOR); 2036 return VMX_TEST_START; 2037 } 2038 2039 static void vmmcall_main(void) 2040 { 2041 asm volatile( 2042 "mov $0xABCD, %%rax\n\t" 2043 "vmmcall\n\t" 2044 ::: "rax"); 2045 2046 report_fail("VMMCALL"); 2047 } 2048 2049 static int vmmcall_exit_handler(union exit_reason exit_reason) 2050 { 2051 switch (exit_reason.basic) { 2052 case VMX_VMCALL: 2053 printf("here\n"); 2054 report_fail("VMMCALL triggers #UD"); 2055 break; 2056 case VMX_EXC_NMI: 2057 report((vmcs_read(EXI_INTR_INFO) & 0xff) == UD_VECTOR, 2058 "VMMCALL triggers #UD"); 2059 break; 2060 default: 2061 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 2062 print_vmexit_info(exit_reason); 2063 } 2064 2065 return VMX_TEST_VMEXIT; 2066 } 2067 2068 static int disable_rdtscp_init(struct vmcs *vmcs) 2069 { 2070 u32 ctrl_cpu1; 2071 2072 if (ctrl_cpu_rev[0].clr & CPU_SECONDARY) { 2073 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 2074 ctrl_cpu1 &= ~CPU_RDTSCP; 2075 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 2076 } 2077 2078 return VMX_TEST_START; 2079 } 2080 2081 static void disable_rdtscp_ud_handler(struct ex_regs *regs) 2082 { 2083 switch (vmx_get_test_stage()) { 2084 case 0: 2085 report_pass("RDTSCP triggers #UD"); 2086 vmx_inc_test_stage(); 2087 regs->rip += 3; 2088 break; 2089 case 2: 2090 report_pass("RDPID triggers #UD"); 2091 vmx_inc_test_stage(); 2092 regs->rip += 4; 2093 break; 2094 } 2095 return; 2096 2097 } 2098 2099 static void disable_rdtscp_main(void) 2100 { 2101 /* Test that #UD is properly injected in L2. */ 2102 handle_exception(UD_VECTOR, disable_rdtscp_ud_handler); 2103 2104 vmx_set_test_stage(0); 2105 asm volatile("rdtscp" : : : "eax", "ecx", "edx"); 2106 vmcall(); 2107 asm volatile(".byte 0xf3, 0x0f, 0xc7, 0xf8" : : : "eax"); 2108 2109 handle_exception(UD_VECTOR, 0); 2110 vmcall(); 2111 } 2112 2113 static int disable_rdtscp_exit_handler(union exit_reason exit_reason) 2114 { 2115 switch (exit_reason.basic) { 2116 case VMX_VMCALL: 2117 switch (vmx_get_test_stage()) { 2118 case 0: 2119 report_fail("RDTSCP triggers #UD"); 2120 vmx_inc_test_stage(); 2121 /* fallthrough */ 2122 case 1: 2123 vmx_inc_test_stage(); 2124 vmcs_write(GUEST_RIP, vmcs_read(GUEST_RIP) + 3); 2125 return VMX_TEST_RESUME; 2126 case 2: 2127 report_fail("RDPID triggers #UD"); 2128 break; 2129 } 2130 break; 2131 2132 default: 2133 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 2134 print_vmexit_info(exit_reason); 2135 } 2136 return VMX_TEST_VMEXIT; 2137 } 2138 2139 static int int3_init(struct vmcs *vmcs) 2140 { 2141 vmcs_write(EXC_BITMAP, ~0u); 2142 return VMX_TEST_START; 2143 } 2144 2145 static void int3_guest_main(void) 2146 { 2147 asm volatile ("int3"); 2148 } 2149 2150 static int int3_exit_handler(union exit_reason exit_reason) 2151 { 2152 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2153 2154 report(exit_reason.basic == VMX_EXC_NMI && 2155 (intr_info & INTR_INFO_VALID_MASK) && 2156 (intr_info & INTR_INFO_VECTOR_MASK) == BP_VECTOR && 2157 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2158 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION, 2159 "L1 intercepts #BP"); 2160 2161 return VMX_TEST_VMEXIT; 2162 } 2163 2164 static int into_init(struct vmcs *vmcs) 2165 { 2166 vmcs_write(EXC_BITMAP, ~0u); 2167 return VMX_TEST_START; 2168 } 2169 2170 static void into_guest_main(void) 2171 { 2172 struct far_pointer32 fp = { 2173 .offset = (uintptr_t)&&into, 2174 .selector = KERNEL_CS32, 2175 }; 2176 uintptr_t rsp; 2177 2178 asm volatile ("mov %%rsp, %0" : "=r"(rsp)); 2179 2180 if (fp.offset != (uintptr_t)&&into) { 2181 printf("Code address too high.\n"); 2182 return; 2183 } 2184 if ((u32)rsp != rsp) { 2185 printf("Stack address too high.\n"); 2186 return; 2187 } 2188 2189 asm goto ("lcall *%0" : : "m" (fp) : "rax" : into); 2190 return; 2191 into: 2192 asm volatile (".code32;" 2193 "movl $0x7fffffff, %eax;" 2194 "addl %eax, %eax;" 2195 "into;" 2196 "lret;" 2197 ".code64"); 2198 __builtin_unreachable(); 2199 } 2200 2201 static int into_exit_handler(union exit_reason exit_reason) 2202 { 2203 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2204 2205 report(exit_reason.basic == VMX_EXC_NMI && 2206 (intr_info & INTR_INFO_VALID_MASK) && 2207 (intr_info & INTR_INFO_VECTOR_MASK) == OF_VECTOR && 2208 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2209 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION, 2210 "L1 intercepts #OF"); 2211 2212 return VMX_TEST_VMEXIT; 2213 } 2214 2215 static void exit_monitor_from_l2_main(void) 2216 { 2217 printf("Calling exit(0) from l2...\n"); 2218 exit(0); 2219 } 2220 2221 static int exit_monitor_from_l2_handler(union exit_reason exit_reason) 2222 { 2223 report_fail("The guest should have killed the VMM"); 2224 return VMX_TEST_EXIT; 2225 } 2226 2227 static void assert_exit_reason(u64 expected) 2228 { 2229 u64 actual = vmcs_read(EXI_REASON); 2230 2231 TEST_ASSERT_EQ_MSG(expected, actual, "Expected %s, got %s.", 2232 exit_reason_description(expected), 2233 exit_reason_description(actual)); 2234 } 2235 2236 static void skip_exit_insn(void) 2237 { 2238 u64 guest_rip = vmcs_read(GUEST_RIP); 2239 u32 insn_len = vmcs_read(EXI_INST_LEN); 2240 vmcs_write(GUEST_RIP, guest_rip + insn_len); 2241 } 2242 2243 static void skip_exit_vmcall(void) 2244 { 2245 assert_exit_reason(VMX_VMCALL); 2246 skip_exit_insn(); 2247 } 2248 2249 static void v2_null_test_guest(void) 2250 { 2251 } 2252 2253 static void v2_null_test(void) 2254 { 2255 test_set_guest(v2_null_test_guest); 2256 enter_guest(); 2257 report_pass(__func__); 2258 } 2259 2260 static void v2_multiple_entries_test_guest(void) 2261 { 2262 vmx_set_test_stage(1); 2263 vmcall(); 2264 vmx_set_test_stage(2); 2265 } 2266 2267 static void v2_multiple_entries_test(void) 2268 { 2269 test_set_guest(v2_multiple_entries_test_guest); 2270 enter_guest(); 2271 TEST_ASSERT_EQ(vmx_get_test_stage(), 1); 2272 skip_exit_vmcall(); 2273 enter_guest(); 2274 TEST_ASSERT_EQ(vmx_get_test_stage(), 2); 2275 report_pass(__func__); 2276 } 2277 2278 static int fixture_test_data = 1; 2279 2280 static void fixture_test_teardown(void *data) 2281 { 2282 *((int *) data) = 1; 2283 } 2284 2285 static void fixture_test_guest(void) 2286 { 2287 fixture_test_data++; 2288 } 2289 2290 2291 static void fixture_test_setup(void) 2292 { 2293 TEST_ASSERT_EQ_MSG(1, fixture_test_data, 2294 "fixture_test_teardown didn't run?!"); 2295 fixture_test_data = 2; 2296 test_add_teardown(fixture_test_teardown, &fixture_test_data); 2297 test_set_guest(fixture_test_guest); 2298 } 2299 2300 static void fixture_test_case1(void) 2301 { 2302 fixture_test_setup(); 2303 TEST_ASSERT_EQ(2, fixture_test_data); 2304 enter_guest(); 2305 TEST_ASSERT_EQ(3, fixture_test_data); 2306 report_pass(__func__); 2307 } 2308 2309 static void fixture_test_case2(void) 2310 { 2311 fixture_test_setup(); 2312 TEST_ASSERT_EQ(2, fixture_test_data); 2313 enter_guest(); 2314 TEST_ASSERT_EQ(3, fixture_test_data); 2315 report_pass(__func__); 2316 } 2317 2318 enum ept_access_op { 2319 OP_READ, 2320 OP_WRITE, 2321 OP_EXEC, 2322 OP_FLUSH_TLB, 2323 OP_EXIT, 2324 }; 2325 2326 static struct ept_access_test_data { 2327 unsigned long gpa; 2328 unsigned long *gva; 2329 unsigned long hpa; 2330 unsigned long *hva; 2331 enum ept_access_op op; 2332 } ept_access_test_data; 2333 2334 extern unsigned char ret42_start; 2335 extern unsigned char ret42_end; 2336 2337 /* Returns 42. */ 2338 asm( 2339 ".align 64\n" 2340 "ret42_start:\n" 2341 "mov $42, %eax\n" 2342 "ret\n" 2343 "ret42_end:\n" 2344 ); 2345 2346 static void 2347 diagnose_ept_violation_qual(u64 expected, u64 actual) 2348 { 2349 2350 #define DIAGNOSE(flag) \ 2351 do { \ 2352 if ((expected & flag) != (actual & flag)) \ 2353 printf(#flag " %sexpected\n", \ 2354 (expected & flag) ? "" : "un"); \ 2355 } while (0) 2356 2357 DIAGNOSE(EPT_VLT_RD); 2358 DIAGNOSE(EPT_VLT_WR); 2359 DIAGNOSE(EPT_VLT_FETCH); 2360 DIAGNOSE(EPT_VLT_PERM_RD); 2361 DIAGNOSE(EPT_VLT_PERM_WR); 2362 DIAGNOSE(EPT_VLT_PERM_EX); 2363 DIAGNOSE(EPT_VLT_LADDR_VLD); 2364 DIAGNOSE(EPT_VLT_PADDR); 2365 2366 #undef DIAGNOSE 2367 } 2368 2369 static void do_ept_access_op(enum ept_access_op op) 2370 { 2371 ept_access_test_data.op = op; 2372 enter_guest(); 2373 } 2374 2375 /* 2376 * Force the guest to flush its TLB (i.e., flush gva -> gpa mappings). Only 2377 * needed by tests that modify guest PTEs. 2378 */ 2379 static void ept_access_test_guest_flush_tlb(void) 2380 { 2381 do_ept_access_op(OP_FLUSH_TLB); 2382 skip_exit_vmcall(); 2383 } 2384 2385 /* 2386 * Modifies the EPT entry at @level in the mapping of @gpa. First clears the 2387 * bits in @clear then sets the bits in @set. @mkhuge transforms the entry into 2388 * a huge page. 2389 */ 2390 static unsigned long ept_twiddle(unsigned long gpa, bool mkhuge, int level, 2391 unsigned long clear, unsigned long set) 2392 { 2393 struct ept_access_test_data *data = &ept_access_test_data; 2394 unsigned long orig_pte; 2395 unsigned long pte; 2396 2397 /* Screw with the mapping at the requested level. */ 2398 TEST_ASSERT(get_ept_pte(pml4, gpa, level, &orig_pte)); 2399 pte = orig_pte; 2400 if (mkhuge) 2401 pte = (orig_pte & ~EPT_ADDR_MASK) | data->hpa | EPT_LARGE_PAGE; 2402 else 2403 pte = orig_pte; 2404 pte = (pte & ~clear) | set; 2405 set_ept_pte(pml4, gpa, level, pte); 2406 invept(INVEPT_SINGLE, eptp); 2407 2408 return orig_pte; 2409 } 2410 2411 static void ept_untwiddle(unsigned long gpa, int level, unsigned long orig_pte) 2412 { 2413 set_ept_pte(pml4, gpa, level, orig_pte); 2414 invept(INVEPT_SINGLE, eptp); 2415 } 2416 2417 static void do_ept_violation(bool leaf, enum ept_access_op op, 2418 u64 expected_qual, u64 expected_paddr) 2419 { 2420 u64 qual; 2421 2422 /* Try the access and observe the violation. */ 2423 do_ept_access_op(op); 2424 2425 assert_exit_reason(VMX_EPT_VIOLATION); 2426 2427 qual = vmcs_read(EXI_QUALIFICATION); 2428 2429 /* Mask undefined bits (which may later be defined in certain cases). */ 2430 qual &= ~(EPT_VLT_GUEST_USER | EPT_VLT_GUEST_RW | EPT_VLT_GUEST_EX | 2431 EPT_VLT_PERM_USER_EX); 2432 2433 diagnose_ept_violation_qual(expected_qual, qual); 2434 TEST_EXPECT_EQ(expected_qual, qual); 2435 2436 #if 0 2437 /* Disable for now otherwise every test will fail */ 2438 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2439 (unsigned long) ( 2440 op == OP_EXEC ? data->gva + 1 : data->gva)); 2441 #endif 2442 /* 2443 * TODO: tests that probe expected_paddr in pages other than the one at 2444 * the beginning of the 1g region. 2445 */ 2446 TEST_EXPECT_EQ(vmcs_read(INFO_PHYS_ADDR), expected_paddr); 2447 } 2448 2449 static void 2450 ept_violation_at_level_mkhuge(bool mkhuge, int level, unsigned long clear, 2451 unsigned long set, enum ept_access_op op, 2452 u64 expected_qual) 2453 { 2454 struct ept_access_test_data *data = &ept_access_test_data; 2455 unsigned long orig_pte; 2456 2457 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2458 2459 do_ept_violation(level == 1 || mkhuge, op, expected_qual, 2460 op == OP_EXEC ? data->gpa + sizeof(unsigned long) : 2461 data->gpa); 2462 2463 /* Fix the violation and resume the op loop. */ 2464 ept_untwiddle(data->gpa, level, orig_pte); 2465 enter_guest(); 2466 skip_exit_vmcall(); 2467 } 2468 2469 static void 2470 ept_violation_at_level(int level, unsigned long clear, unsigned long set, 2471 enum ept_access_op op, u64 expected_qual) 2472 { 2473 ept_violation_at_level_mkhuge(false, level, clear, set, op, 2474 expected_qual); 2475 if (ept_huge_pages_supported(level)) 2476 ept_violation_at_level_mkhuge(true, level, clear, set, op, 2477 expected_qual); 2478 } 2479 2480 static void ept_violation(unsigned long clear, unsigned long set, 2481 enum ept_access_op op, u64 expected_qual) 2482 { 2483 ept_violation_at_level(1, clear, set, op, expected_qual); 2484 ept_violation_at_level(2, clear, set, op, expected_qual); 2485 ept_violation_at_level(3, clear, set, op, expected_qual); 2486 ept_violation_at_level(4, clear, set, op, expected_qual); 2487 } 2488 2489 static void ept_access_violation(unsigned long access, enum ept_access_op op, 2490 u64 expected_qual) 2491 { 2492 ept_violation(EPT_PRESENT, access, op, 2493 expected_qual | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2494 } 2495 2496 /* 2497 * For translations that don't involve a GVA, that is physical address (paddr) 2498 * accesses, EPT violations don't set the flag EPT_VLT_PADDR. For a typical 2499 * guest memory access, the hardware does GVA -> GPA -> HPA. However, certain 2500 * translations don't involve GVAs, such as when the hardware does the guest 2501 * page table walk. For example, in translating GVA_1 -> GPA_1, the guest MMU 2502 * might try to set an A bit on a guest PTE. If the GPA_2 that the PTE resides 2503 * on isn't present in the EPT, then the EPT violation will be for GPA_2 and 2504 * the EPT_VLT_PADDR bit will be clear in the exit qualification. 2505 * 2506 * Note that paddr violations can also be triggered by loading PAE page tables 2507 * with wonky addresses. We don't test that yet. 2508 * 2509 * This function modifies the EPT entry that maps the GPA that the guest page 2510 * table entry mapping ept_access_test_data.gva resides on. 2511 * 2512 * @ept_access EPT permissions to set. Other permissions are cleared. 2513 * 2514 * @pte_ad Set the A/D bits on the guest PTE accordingly. 2515 * 2516 * @op Guest operation to perform with 2517 * ept_access_test_data.gva. 2518 * 2519 * @expect_violation 2520 * Is a violation expected during the paddr access? 2521 * 2522 * @expected_qual Expected qualification for the EPT violation. 2523 * EPT_VLT_PADDR should be clear. 2524 */ 2525 static void ept_access_paddr(unsigned long ept_access, unsigned long pte_ad, 2526 enum ept_access_op op, bool expect_violation, 2527 u64 expected_qual) 2528 { 2529 struct ept_access_test_data *data = &ept_access_test_data; 2530 unsigned long *ptep; 2531 unsigned long gpa; 2532 unsigned long orig_epte; 2533 unsigned long epte; 2534 int i; 2535 2536 /* Modify the guest PTE mapping data->gva according to @pte_ad. */ 2537 ptep = get_pte_level(current_page_table(), data->gva, /*level=*/1); 2538 TEST_ASSERT(ptep); 2539 TEST_ASSERT_EQ(*ptep & PT_ADDR_MASK, data->gpa); 2540 *ptep = (*ptep & ~PT_AD_MASK) | pte_ad; 2541 ept_access_test_guest_flush_tlb(); 2542 2543 /* 2544 * Now modify the access bits on the EPT entry for the GPA that the 2545 * guest PTE resides on. Note that by modifying a single EPT entry, 2546 * we're potentially affecting 512 guest PTEs. However, we've carefully 2547 * constructed our test such that those other 511 PTEs aren't used by 2548 * the guest: data->gva is at the beginning of a 1G huge page, thus the 2549 * PTE we're modifying is at the beginning of a 4K page and the 2550 * following 511 entries are also under our control (and not touched by 2551 * the guest). 2552 */ 2553 gpa = virt_to_phys(ptep); 2554 TEST_ASSERT_EQ(gpa & ~PAGE_MASK, 0); 2555 /* 2556 * Make sure the guest page table page is mapped with a 4K EPT entry, 2557 * otherwise our level=1 twiddling below will fail. We use the 2558 * identity map (gpa = gpa) since page tables are shared with the host. 2559 */ 2560 install_ept(pml4, gpa, gpa, EPT_PRESENT); 2561 orig_epte = ept_twiddle(gpa, /*mkhuge=*/0, /*level=*/1, 2562 /*clear=*/EPT_PRESENT, /*set=*/ept_access); 2563 2564 if (expect_violation) { 2565 do_ept_violation(/*leaf=*/true, op, 2566 expected_qual | EPT_VLT_LADDR_VLD, gpa); 2567 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2568 do_ept_access_op(op); 2569 } else { 2570 do_ept_access_op(op); 2571 if (ept_ad_enabled()) { 2572 for (i = EPT_PAGE_LEVEL; i > 0; i--) { 2573 TEST_ASSERT(get_ept_pte(pml4, gpa, i, &epte)); 2574 TEST_ASSERT(epte & EPT_ACCESS_FLAG); 2575 if (i == 1) 2576 TEST_ASSERT(epte & EPT_DIRTY_FLAG); 2577 else 2578 TEST_ASSERT_EQ(epte & EPT_DIRTY_FLAG, 0); 2579 } 2580 } 2581 2582 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2583 } 2584 2585 TEST_ASSERT(*ptep & PT_ACCESSED_MASK); 2586 if ((pte_ad & PT_DIRTY_MASK) || op == OP_WRITE) 2587 TEST_ASSERT(*ptep & PT_DIRTY_MASK); 2588 2589 skip_exit_vmcall(); 2590 } 2591 2592 static void ept_access_allowed_paddr(unsigned long ept_access, 2593 unsigned long pte_ad, 2594 enum ept_access_op op) 2595 { 2596 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/false, 2597 /*expected_qual=*/-1); 2598 } 2599 2600 static void ept_access_violation_paddr(unsigned long ept_access, 2601 unsigned long pte_ad, 2602 enum ept_access_op op, 2603 u64 expected_qual) 2604 { 2605 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/true, 2606 expected_qual); 2607 } 2608 2609 2610 static void ept_allowed_at_level_mkhuge(bool mkhuge, int level, 2611 unsigned long clear, 2612 unsigned long set, 2613 enum ept_access_op op) 2614 { 2615 struct ept_access_test_data *data = &ept_access_test_data; 2616 unsigned long orig_pte; 2617 2618 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2619 2620 /* No violation. Should proceed to vmcall. */ 2621 do_ept_access_op(op); 2622 skip_exit_vmcall(); 2623 2624 ept_untwiddle(data->gpa, level, orig_pte); 2625 } 2626 2627 static void ept_allowed_at_level(int level, unsigned long clear, 2628 unsigned long set, enum ept_access_op op) 2629 { 2630 ept_allowed_at_level_mkhuge(false, level, clear, set, op); 2631 if (ept_huge_pages_supported(level)) 2632 ept_allowed_at_level_mkhuge(true, level, clear, set, op); 2633 } 2634 2635 static void ept_allowed(unsigned long clear, unsigned long set, 2636 enum ept_access_op op) 2637 { 2638 ept_allowed_at_level(1, clear, set, op); 2639 ept_allowed_at_level(2, clear, set, op); 2640 ept_allowed_at_level(3, clear, set, op); 2641 ept_allowed_at_level(4, clear, set, op); 2642 } 2643 2644 static void ept_ignored_bit(int bit) 2645 { 2646 /* Set the bit. */ 2647 ept_allowed(0, 1ul << bit, OP_READ); 2648 ept_allowed(0, 1ul << bit, OP_WRITE); 2649 ept_allowed(0, 1ul << bit, OP_EXEC); 2650 2651 /* Clear the bit. */ 2652 ept_allowed(1ul << bit, 0, OP_READ); 2653 ept_allowed(1ul << bit, 0, OP_WRITE); 2654 ept_allowed(1ul << bit, 0, OP_EXEC); 2655 } 2656 2657 static void ept_access_allowed(unsigned long access, enum ept_access_op op) 2658 { 2659 ept_allowed(EPT_PRESENT, access, op); 2660 } 2661 2662 2663 static void ept_misconfig_at_level_mkhuge_op(bool mkhuge, int level, 2664 unsigned long clear, 2665 unsigned long set, 2666 enum ept_access_op op) 2667 { 2668 struct ept_access_test_data *data = &ept_access_test_data; 2669 unsigned long orig_pte; 2670 2671 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2672 2673 do_ept_access_op(op); 2674 assert_exit_reason(VMX_EPT_MISCONFIG); 2675 2676 /* Intel 27.2.1, "For all other VM exits, this field is cleared." */ 2677 #if 0 2678 /* broken: */ 2679 TEST_EXPECT_EQ_MSG(vmcs_read(EXI_QUALIFICATION), 0); 2680 #endif 2681 #if 0 2682 /* 2683 * broken: 2684 * According to description of exit qual for EPT violation, 2685 * EPT_VLT_LADDR_VLD indicates if GUEST_LINEAR_ADDRESS is valid. 2686 * However, I can't find anything that says GUEST_LINEAR_ADDRESS ought 2687 * to be set for msiconfig. 2688 */ 2689 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2690 (unsigned long) ( 2691 op == OP_EXEC ? data->gva + 1 : data->gva)); 2692 #endif 2693 2694 /* Fix the violation and resume the op loop. */ 2695 ept_untwiddle(data->gpa, level, orig_pte); 2696 enter_guest(); 2697 skip_exit_vmcall(); 2698 } 2699 2700 static void ept_misconfig_at_level_mkhuge(bool mkhuge, int level, 2701 unsigned long clear, 2702 unsigned long set) 2703 { 2704 /* The op shouldn't matter (read, write, exec), so try them all! */ 2705 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_READ); 2706 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_WRITE); 2707 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_EXEC); 2708 } 2709 2710 static void ept_misconfig_at_level(int level, unsigned long clear, 2711 unsigned long set) 2712 { 2713 ept_misconfig_at_level_mkhuge(false, level, clear, set); 2714 if (ept_huge_pages_supported(level)) 2715 ept_misconfig_at_level_mkhuge(true, level, clear, set); 2716 } 2717 2718 static void ept_misconfig(unsigned long clear, unsigned long set) 2719 { 2720 ept_misconfig_at_level(1, clear, set); 2721 ept_misconfig_at_level(2, clear, set); 2722 ept_misconfig_at_level(3, clear, set); 2723 ept_misconfig_at_level(4, clear, set); 2724 } 2725 2726 static void ept_access_misconfig(unsigned long access) 2727 { 2728 ept_misconfig(EPT_PRESENT, access); 2729 } 2730 2731 static void ept_reserved_bit_at_level_nohuge(int level, int bit) 2732 { 2733 /* Setting the bit causes a misconfig. */ 2734 ept_misconfig_at_level_mkhuge(false, level, 0, 1ul << bit); 2735 2736 /* Making the entry non-present turns reserved bits into ignored. */ 2737 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2738 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2739 } 2740 2741 static void ept_reserved_bit_at_level_huge(int level, int bit) 2742 { 2743 /* Setting the bit causes a misconfig. */ 2744 ept_misconfig_at_level_mkhuge(true, level, 0, 1ul << bit); 2745 2746 /* Making the entry non-present turns reserved bits into ignored. */ 2747 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2748 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2749 } 2750 2751 static void ept_reserved_bit_at_level(int level, int bit) 2752 { 2753 /* Setting the bit causes a misconfig. */ 2754 ept_misconfig_at_level(level, 0, 1ul << bit); 2755 2756 /* Making the entry non-present turns reserved bits into ignored. */ 2757 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2758 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2759 } 2760 2761 static void ept_reserved_bit(int bit) 2762 { 2763 ept_reserved_bit_at_level(1, bit); 2764 ept_reserved_bit_at_level(2, bit); 2765 ept_reserved_bit_at_level(3, bit); 2766 ept_reserved_bit_at_level(4, bit); 2767 } 2768 2769 #define PAGE_2M_ORDER 9 2770 #define PAGE_1G_ORDER 18 2771 2772 static void *get_1g_page(void) 2773 { 2774 static void *alloc; 2775 2776 if (!alloc) 2777 alloc = alloc_pages(PAGE_1G_ORDER); 2778 return alloc; 2779 } 2780 2781 static void ept_access_test_teardown(void *unused) 2782 { 2783 /* Exit the guest cleanly. */ 2784 do_ept_access_op(OP_EXIT); 2785 } 2786 2787 static void ept_access_test_guest(void) 2788 { 2789 struct ept_access_test_data *data = &ept_access_test_data; 2790 int (*code)(void) = (int (*)(void)) &data->gva[1]; 2791 2792 while (true) { 2793 switch (data->op) { 2794 case OP_READ: 2795 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_1); 2796 break; 2797 case OP_WRITE: 2798 *data->gva = MAGIC_VAL_2; 2799 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_2); 2800 *data->gva = MAGIC_VAL_1; 2801 break; 2802 case OP_EXEC: 2803 TEST_ASSERT_EQ(42, code()); 2804 break; 2805 case OP_FLUSH_TLB: 2806 write_cr3(read_cr3()); 2807 break; 2808 case OP_EXIT: 2809 return; 2810 default: 2811 TEST_ASSERT_MSG(false, "Unknown op %d", data->op); 2812 } 2813 vmcall(); 2814 } 2815 } 2816 2817 static void ept_access_test_setup(void) 2818 { 2819 struct ept_access_test_data *data = &ept_access_test_data; 2820 unsigned long npages = 1ul << PAGE_1G_ORDER; 2821 unsigned long size = npages * PAGE_SIZE; 2822 unsigned long *page_table = current_page_table(); 2823 unsigned long pte; 2824 2825 if (setup_ept(false)) 2826 test_skip("EPT not supported"); 2827 2828 /* We use data->gpa = 1 << 39 so that test data has a separate pml4 entry */ 2829 if (cpuid_maxphyaddr() < 40) 2830 test_skip("Test needs MAXPHYADDR >= 40"); 2831 2832 test_set_guest(ept_access_test_guest); 2833 test_add_teardown(ept_access_test_teardown, NULL); 2834 2835 data->hva = get_1g_page(); 2836 TEST_ASSERT(data->hva); 2837 data->hpa = virt_to_phys(data->hva); 2838 2839 data->gpa = 1ul << 39; 2840 data->gva = (void *) ALIGN((unsigned long) alloc_vpages(npages * 2), 2841 size); 2842 TEST_ASSERT(!any_present_pages(page_table, data->gva, size)); 2843 install_pages(page_table, data->gpa, size, data->gva); 2844 2845 /* 2846 * Make sure nothing's mapped here so the tests that screw with the 2847 * pml4 entry don't inadvertently break something. 2848 */ 2849 TEST_ASSERT(get_ept_pte(pml4, data->gpa, 4, &pte) && pte == 0); 2850 TEST_ASSERT(get_ept_pte(pml4, data->gpa + size - 1, 4, &pte) && pte == 0); 2851 install_ept(pml4, data->hpa, data->gpa, EPT_PRESENT); 2852 2853 data->hva[0] = MAGIC_VAL_1; 2854 memcpy(&data->hva[1], &ret42_start, &ret42_end - &ret42_start); 2855 } 2856 2857 static void ept_access_test_not_present(void) 2858 { 2859 ept_access_test_setup(); 2860 /* --- */ 2861 ept_access_violation(0, OP_READ, EPT_VLT_RD); 2862 ept_access_violation(0, OP_WRITE, EPT_VLT_WR); 2863 ept_access_violation(0, OP_EXEC, EPT_VLT_FETCH); 2864 } 2865 2866 static void ept_access_test_read_only(void) 2867 { 2868 ept_access_test_setup(); 2869 2870 /* r-- */ 2871 ept_access_allowed(EPT_RA, OP_READ); 2872 ept_access_violation(EPT_RA, OP_WRITE, EPT_VLT_WR | EPT_VLT_PERM_RD); 2873 ept_access_violation(EPT_RA, OP_EXEC, EPT_VLT_FETCH | EPT_VLT_PERM_RD); 2874 } 2875 2876 static void ept_access_test_write_only(void) 2877 { 2878 ept_access_test_setup(); 2879 /* -w- */ 2880 ept_access_misconfig(EPT_WA); 2881 } 2882 2883 static void ept_access_test_read_write(void) 2884 { 2885 ept_access_test_setup(); 2886 /* rw- */ 2887 ept_access_allowed(EPT_RA | EPT_WA, OP_READ); 2888 ept_access_allowed(EPT_RA | EPT_WA, OP_WRITE); 2889 ept_access_violation(EPT_RA | EPT_WA, OP_EXEC, 2890 EPT_VLT_FETCH | EPT_VLT_PERM_RD | EPT_VLT_PERM_WR); 2891 } 2892 2893 2894 static void ept_access_test_execute_only(void) 2895 { 2896 ept_access_test_setup(); 2897 /* --x */ 2898 if (ept_execute_only_supported()) { 2899 ept_access_violation(EPT_EA, OP_READ, 2900 EPT_VLT_RD | EPT_VLT_PERM_EX); 2901 ept_access_violation(EPT_EA, OP_WRITE, 2902 EPT_VLT_WR | EPT_VLT_PERM_EX); 2903 ept_access_allowed(EPT_EA, OP_EXEC); 2904 } else { 2905 ept_access_misconfig(EPT_EA); 2906 } 2907 } 2908 2909 static void ept_access_test_read_execute(void) 2910 { 2911 ept_access_test_setup(); 2912 /* r-x */ 2913 ept_access_allowed(EPT_RA | EPT_EA, OP_READ); 2914 ept_access_violation(EPT_RA | EPT_EA, OP_WRITE, 2915 EPT_VLT_WR | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX); 2916 ept_access_allowed(EPT_RA | EPT_EA, OP_EXEC); 2917 } 2918 2919 static void ept_access_test_write_execute(void) 2920 { 2921 ept_access_test_setup(); 2922 /* -wx */ 2923 ept_access_misconfig(EPT_WA | EPT_EA); 2924 } 2925 2926 static void ept_access_test_read_write_execute(void) 2927 { 2928 ept_access_test_setup(); 2929 /* rwx */ 2930 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_READ); 2931 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_WRITE); 2932 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_EXEC); 2933 } 2934 2935 static void ept_access_test_reserved_bits(void) 2936 { 2937 int i; 2938 int maxphyaddr; 2939 2940 ept_access_test_setup(); 2941 2942 /* Reserved bits above maxphyaddr. */ 2943 maxphyaddr = cpuid_maxphyaddr(); 2944 for (i = maxphyaddr; i <= 51; i++) { 2945 report_prefix_pushf("reserved_bit=%d", i); 2946 ept_reserved_bit(i); 2947 report_prefix_pop(); 2948 } 2949 2950 /* Level-specific reserved bits. */ 2951 ept_reserved_bit_at_level_nohuge(2, 3); 2952 ept_reserved_bit_at_level_nohuge(2, 4); 2953 ept_reserved_bit_at_level_nohuge(2, 5); 2954 ept_reserved_bit_at_level_nohuge(2, 6); 2955 /* 2M alignment. */ 2956 for (i = 12; i < 20; i++) { 2957 report_prefix_pushf("reserved_bit=%d", i); 2958 ept_reserved_bit_at_level_huge(2, i); 2959 report_prefix_pop(); 2960 } 2961 ept_reserved_bit_at_level_nohuge(3, 3); 2962 ept_reserved_bit_at_level_nohuge(3, 4); 2963 ept_reserved_bit_at_level_nohuge(3, 5); 2964 ept_reserved_bit_at_level_nohuge(3, 6); 2965 /* 1G alignment. */ 2966 for (i = 12; i < 29; i++) { 2967 report_prefix_pushf("reserved_bit=%d", i); 2968 ept_reserved_bit_at_level_huge(3, i); 2969 report_prefix_pop(); 2970 } 2971 ept_reserved_bit_at_level(4, 3); 2972 ept_reserved_bit_at_level(4, 4); 2973 ept_reserved_bit_at_level(4, 5); 2974 ept_reserved_bit_at_level(4, 6); 2975 ept_reserved_bit_at_level(4, 7); 2976 } 2977 2978 static void ept_access_test_ignored_bits(void) 2979 { 2980 ept_access_test_setup(); 2981 /* 2982 * Bits ignored at every level. Bits 8 and 9 (A and D) are ignored as 2983 * far as translation is concerned even if AD bits are enabled in the 2984 * EPTP. Bit 63 is ignored because "EPT-violation #VE" VM-execution 2985 * control is 0. 2986 */ 2987 ept_ignored_bit(8); 2988 ept_ignored_bit(9); 2989 ept_ignored_bit(10); 2990 ept_ignored_bit(11); 2991 ept_ignored_bit(52); 2992 ept_ignored_bit(53); 2993 ept_ignored_bit(54); 2994 ept_ignored_bit(55); 2995 ept_ignored_bit(56); 2996 ept_ignored_bit(57); 2997 ept_ignored_bit(58); 2998 ept_ignored_bit(59); 2999 ept_ignored_bit(60); 3000 ept_ignored_bit(61); 3001 ept_ignored_bit(62); 3002 ept_ignored_bit(63); 3003 } 3004 3005 static void ept_access_test_paddr_not_present_ad_disabled(void) 3006 { 3007 ept_access_test_setup(); 3008 ept_disable_ad_bits(); 3009 3010 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, EPT_VLT_RD); 3011 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, EPT_VLT_RD); 3012 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, EPT_VLT_RD); 3013 } 3014 3015 static void ept_access_test_paddr_not_present_ad_enabled(void) 3016 { 3017 u64 qual = EPT_VLT_RD | EPT_VLT_WR; 3018 3019 ept_access_test_setup(); 3020 ept_enable_ad_bits_or_skip_test(); 3021 3022 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, qual); 3023 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, qual); 3024 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, qual); 3025 } 3026 3027 static void ept_access_test_paddr_read_only_ad_disabled(void) 3028 { 3029 /* 3030 * When EPT AD bits are disabled, all accesses to guest paging 3031 * structures are reported separately as a read and (after 3032 * translation of the GPA to host physical address) a read+write 3033 * if the A/D bits have to be set. 3034 */ 3035 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 3036 3037 ept_access_test_setup(); 3038 ept_disable_ad_bits(); 3039 3040 /* Can't update A bit, so all accesses fail. */ 3041 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 3042 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 3043 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 3044 /* AD bits disabled, so only writes try to update the D bit. */ 3045 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ); 3046 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 3047 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC); 3048 /* Both A and D already set, so read-only is OK. */ 3049 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_READ); 3050 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_WRITE); 3051 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_EXEC); 3052 } 3053 3054 static void ept_access_test_paddr_read_only_ad_enabled(void) 3055 { 3056 /* 3057 * When EPT AD bits are enabled, all accesses to guest paging 3058 * structures are considered writes as far as EPT translation 3059 * is concerned. 3060 */ 3061 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 3062 3063 ept_access_test_setup(); 3064 ept_enable_ad_bits_or_skip_test(); 3065 3066 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 3067 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 3068 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 3069 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ, qual); 3070 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 3071 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC, qual); 3072 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_READ, qual); 3073 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_WRITE, qual); 3074 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_EXEC, qual); 3075 } 3076 3077 static void ept_access_test_paddr_read_write(void) 3078 { 3079 ept_access_test_setup(); 3080 /* Read-write access to paging structure. */ 3081 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_READ); 3082 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_WRITE); 3083 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_EXEC); 3084 } 3085 3086 static void ept_access_test_paddr_read_write_execute(void) 3087 { 3088 ept_access_test_setup(); 3089 /* RWX access to paging structure. */ 3090 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_READ); 3091 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_WRITE); 3092 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_EXEC); 3093 } 3094 3095 static void ept_access_test_paddr_read_execute_ad_disabled(void) 3096 { 3097 /* 3098 * When EPT AD bits are disabled, all accesses to guest paging 3099 * structures are reported separately as a read and (after 3100 * translation of the GPA to host physical address) a read+write 3101 * if the A/D bits have to be set. 3102 */ 3103 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3104 3105 ept_access_test_setup(); 3106 ept_disable_ad_bits(); 3107 3108 /* Can't update A bit, so all accesses fail. */ 3109 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3110 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3111 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3112 /* AD bits disabled, so only writes try to update the D bit. */ 3113 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ); 3114 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3115 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC); 3116 /* Both A and D already set, so read-only is OK. */ 3117 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ); 3118 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE); 3119 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC); 3120 } 3121 3122 static void ept_access_test_paddr_read_execute_ad_enabled(void) 3123 { 3124 /* 3125 * When EPT AD bits are enabled, all accesses to guest paging 3126 * structures are considered writes as far as EPT translation 3127 * is concerned. 3128 */ 3129 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3130 3131 ept_access_test_setup(); 3132 ept_enable_ad_bits_or_skip_test(); 3133 3134 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3135 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3136 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3137 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ, qual); 3138 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3139 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC, qual); 3140 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ, qual); 3141 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE, qual); 3142 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC, qual); 3143 } 3144 3145 static void ept_access_test_paddr_not_present_page_fault(void) 3146 { 3147 ept_access_test_setup(); 3148 /* 3149 * TODO: test no EPT violation as long as guest PF occurs. e.g., GPA is 3150 * page is read-only in EPT but GVA is also mapped read only in PT. 3151 * Thus guest page fault before host takes EPT violation for trying to 3152 * update A bit. 3153 */ 3154 } 3155 3156 static void ept_access_test_force_2m_page(void) 3157 { 3158 ept_access_test_setup(); 3159 3160 TEST_ASSERT_EQ(ept_2m_supported(), true); 3161 ept_allowed_at_level_mkhuge(true, 2, 0, 0, OP_READ); 3162 ept_violation_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_RA, OP_WRITE, 3163 EPT_VLT_WR | EPT_VLT_PERM_RD | 3164 EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 3165 ept_misconfig_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_WA); 3166 } 3167 3168 static bool invvpid_valid(u64 type, u64 vpid, u64 gla) 3169 { 3170 if (!is_invvpid_type_supported(type)) 3171 return false; 3172 3173 if (vpid >> 16) 3174 return false; 3175 3176 if (type != INVVPID_ALL && !vpid) 3177 return false; 3178 3179 if (type == INVVPID_ADDR && !is_canonical(gla)) 3180 return false; 3181 3182 return true; 3183 } 3184 3185 static void try_invvpid(u64 type, u64 vpid, u64 gla) 3186 { 3187 int rc; 3188 bool valid = invvpid_valid(type, vpid, gla); 3189 u64 expected = valid ? VMXERR_UNSUPPORTED_VMCS_COMPONENT 3190 : VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID; 3191 /* 3192 * Set VMX_INST_ERROR to VMXERR_UNVALID_VMCS_COMPONENT, so 3193 * that we can tell if it is updated by INVVPID. 3194 */ 3195 vmcs_read(~0); 3196 rc = __invvpid(type, vpid, gla); 3197 report(!rc == valid, "INVVPID type %ld VPID %lx GLA %lx %s", type, 3198 vpid, gla, 3199 valid ? "passes" : "fails"); 3200 report(vmcs_read(VMX_INST_ERROR) == expected, 3201 "After %s INVVPID, VMX_INST_ERR is %ld (actual %ld)", 3202 rc ? "failed" : "successful", 3203 expected, vmcs_read(VMX_INST_ERROR)); 3204 } 3205 3206 static inline unsigned long get_first_supported_invvpid_type(void) 3207 { 3208 u64 type = ffs(ept_vpid.val >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 3209 3210 __TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 3211 return type; 3212 } 3213 3214 static void ds_invvpid(void *data) 3215 { 3216 asm volatile("invvpid %0, %1" 3217 : 3218 : "m"(*(struct invvpid_operand *)data), 3219 "r"(get_first_supported_invvpid_type())); 3220 } 3221 3222 /* 3223 * The SS override is ignored in 64-bit mode, so we use an addressing 3224 * mode with %rsp as the base register to generate an implicit SS 3225 * reference. 3226 */ 3227 static void ss_invvpid(void *data) 3228 { 3229 asm volatile("sub %%rsp,%0; invvpid (%%rsp,%0,1), %1" 3230 : "+r"(data) 3231 : "r"(get_first_supported_invvpid_type())); 3232 } 3233 3234 static void invvpid_test_gp(void) 3235 { 3236 bool fault; 3237 3238 fault = test_for_exception(GP_VECTOR, &ds_invvpid, 3239 (void *)NONCANONICAL); 3240 report(fault, "INVVPID with non-canonical DS operand raises #GP"); 3241 } 3242 3243 static void invvpid_test_ss(void) 3244 { 3245 bool fault; 3246 3247 fault = test_for_exception(SS_VECTOR, &ss_invvpid, 3248 (void *)NONCANONICAL); 3249 report(fault, "INVVPID with non-canonical SS operand raises #SS"); 3250 } 3251 3252 static void invvpid_test_pf(void) 3253 { 3254 void *vpage = alloc_vpage(); 3255 bool fault; 3256 3257 fault = test_for_exception(PF_VECTOR, &ds_invvpid, vpage); 3258 report(fault, "INVVPID with unmapped operand raises #PF"); 3259 } 3260 3261 static void try_compat_invvpid(void *unused) 3262 { 3263 struct far_pointer32 fp = { 3264 .offset = (uintptr_t)&&invvpid, 3265 .selector = KERNEL_CS32, 3266 }; 3267 uintptr_t rsp; 3268 3269 asm volatile ("mov %%rsp, %0" : "=r"(rsp)); 3270 3271 TEST_ASSERT_MSG(fp.offset == (uintptr_t)&&invvpid, 3272 "Code address too high."); 3273 TEST_ASSERT_MSG(rsp == (u32)rsp, "Stack address too high."); 3274 3275 asm goto ("lcall *%0" : : "m" (fp) : "rax" : invvpid); 3276 return; 3277 invvpid: 3278 asm volatile (".code32;" 3279 "invvpid (%eax), %eax;" 3280 "lret;" 3281 ".code64"); 3282 __builtin_unreachable(); 3283 } 3284 3285 static void invvpid_test_compatibility_mode(void) 3286 { 3287 bool fault; 3288 3289 fault = test_for_exception(UD_VECTOR, &try_compat_invvpid, NULL); 3290 report(fault, "Compatibility mode INVVPID raises #UD"); 3291 } 3292 3293 static void invvpid_test_not_in_vmx_operation(void) 3294 { 3295 bool fault; 3296 3297 TEST_ASSERT(!vmx_off()); 3298 fault = test_for_exception(UD_VECTOR, &ds_invvpid, NULL); 3299 report(fault, "INVVPID outside of VMX operation raises #UD"); 3300 TEST_ASSERT(!vmx_on()); 3301 } 3302 3303 /* 3304 * This does not test real-address mode, virtual-8086 mode, protected mode, 3305 * or CPL > 0. 3306 */ 3307 static void invvpid_test(void) 3308 { 3309 int i; 3310 unsigned types = 0; 3311 unsigned type; 3312 3313 if (!is_vpid_supported()) 3314 test_skip("VPID not supported"); 3315 3316 if (!is_invvpid_supported()) 3317 test_skip("INVVPID not supported.\n"); 3318 3319 if (is_invvpid_type_supported(INVVPID_ADDR)) 3320 types |= 1u << INVVPID_ADDR; 3321 if (is_invvpid_type_supported(INVVPID_CONTEXT_GLOBAL)) 3322 types |= 1u << INVVPID_CONTEXT_GLOBAL; 3323 if (is_invvpid_type_supported(INVVPID_ALL)) 3324 types |= 1u << INVVPID_ALL; 3325 if (is_invvpid_type_supported(INVVPID_CONTEXT_LOCAL)) 3326 types |= 1u << INVVPID_CONTEXT_LOCAL; 3327 3328 if (!types) 3329 test_skip("No INVVPID types supported.\n"); 3330 3331 for (i = -127; i < 128; i++) 3332 try_invvpid(i, 0xffff, 0); 3333 3334 /* 3335 * VPID must not be more than 16 bits. 3336 */ 3337 for (i = 0; i < 64; i++) 3338 for (type = 0; type < 4; type++) 3339 if (types & (1u << type)) 3340 try_invvpid(type, 1ul << i, 0); 3341 3342 /* 3343 * VPID must not be zero, except for "all contexts." 3344 */ 3345 for (type = 0; type < 4; type++) 3346 if (types & (1u << type)) 3347 try_invvpid(type, 0, 0); 3348 3349 /* 3350 * The gla operand is only validated for single-address INVVPID. 3351 */ 3352 if (types & (1u << INVVPID_ADDR)) 3353 try_invvpid(INVVPID_ADDR, 0xffff, NONCANONICAL); 3354 3355 invvpid_test_gp(); 3356 invvpid_test_ss(); 3357 invvpid_test_pf(); 3358 invvpid_test_compatibility_mode(); 3359 invvpid_test_not_in_vmx_operation(); 3360 } 3361 3362 /* 3363 * Test for early VMLAUNCH failure. Returns true if VMLAUNCH makes it 3364 * at least as far as the guest-state checks. Returns false if the 3365 * VMLAUNCH fails early and execution falls through to the next 3366 * instruction. 3367 */ 3368 static bool vmlaunch_succeeds(void) 3369 { 3370 u32 exit_reason; 3371 3372 /* 3373 * Indirectly set VMX_INST_ERR to 12 ("VMREAD/VMWRITE from/to 3374 * unsupported VMCS component"). The caller can then check 3375 * to see if a failed VM-entry sets VMX_INST_ERR as expected. 3376 */ 3377 vmcs_write(~0u, 0); 3378 3379 vmcs_write(HOST_RIP, (uintptr_t)&&success); 3380 __asm__ __volatile__ goto ("vmwrite %%rsp, %0; vmlaunch" 3381 : 3382 : "r" ((u64)HOST_RSP) 3383 : "cc", "memory" 3384 : success); 3385 return false; 3386 success: 3387 exit_reason = vmcs_read(EXI_REASON); 3388 TEST_ASSERT(exit_reason == (VMX_FAIL_STATE | VMX_ENTRY_FAILURE) || 3389 exit_reason == (VMX_FAIL_MSR | VMX_ENTRY_FAILURE)); 3390 return true; 3391 } 3392 3393 /* 3394 * Try to launch the current VMCS. 3395 */ 3396 static void test_vmx_vmlaunch(u32 xerror) 3397 { 3398 bool success = vmlaunch_succeeds(); 3399 u32 vmx_inst_err; 3400 3401 report(success == !xerror, "vmlaunch %s", 3402 !xerror ? "succeeds" : "fails"); 3403 if (!success && xerror) { 3404 vmx_inst_err = vmcs_read(VMX_INST_ERROR); 3405 report(vmx_inst_err == xerror, 3406 "VMX inst error is %d (actual %d)", xerror, 3407 vmx_inst_err); 3408 } 3409 } 3410 3411 /* 3412 * Try to launch the current VMCS, and expect one of two possible 3413 * errors (or success) codes. 3414 */ 3415 static void test_vmx_vmlaunch2(u32 xerror1, u32 xerror2) 3416 { 3417 bool success = vmlaunch_succeeds(); 3418 u32 vmx_inst_err; 3419 3420 if (!xerror1 == !xerror2) 3421 report(success == !xerror1, "vmlaunch %s", 3422 !xerror1 ? "succeeds" : "fails"); 3423 3424 if (!success && (xerror1 || xerror2)) { 3425 vmx_inst_err = vmcs_read(VMX_INST_ERROR); 3426 report(vmx_inst_err == xerror1 || vmx_inst_err == xerror2, 3427 "VMX inst error is %d or %d (actual %d)", xerror1, 3428 xerror2, vmx_inst_err); 3429 } 3430 } 3431 3432 static void test_vmx_invalid_controls(void) 3433 { 3434 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_CONTROL_FIELD); 3435 } 3436 3437 static void test_vmx_valid_controls(void) 3438 { 3439 test_vmx_vmlaunch(0); 3440 } 3441 3442 /* 3443 * Test a particular value of a VM-execution control bit, if the value 3444 * is required or if the value is zero. 3445 */ 3446 static void test_rsvd_ctl_bit_value(const char *name, union vmx_ctrl_msr msr, 3447 enum Encoding encoding, unsigned bit, 3448 unsigned val) 3449 { 3450 u32 mask = 1u << bit; 3451 bool expected; 3452 u32 controls; 3453 3454 if (msr.set & mask) 3455 TEST_ASSERT(msr.clr & mask); 3456 3457 /* 3458 * We can't arbitrarily turn on a control bit, because it may 3459 * introduce dependencies on other VMCS fields. So, we only 3460 * test turning on bits that have a required setting. 3461 */ 3462 if (val && (msr.clr & mask) && !(msr.set & mask)) 3463 return; 3464 3465 report_prefix_pushf("%s %s bit %d", 3466 val ? "Set" : "Clear", name, bit); 3467 3468 controls = vmcs_read(encoding); 3469 if (val) { 3470 vmcs_write(encoding, msr.set | mask); 3471 expected = (msr.clr & mask); 3472 } else { 3473 vmcs_write(encoding, msr.set & ~mask); 3474 expected = !(msr.set & mask); 3475 } 3476 if (expected) 3477 test_vmx_valid_controls(); 3478 else 3479 test_vmx_invalid_controls(); 3480 vmcs_write(encoding, controls); 3481 report_prefix_pop(); 3482 } 3483 3484 /* 3485 * Test reserved values of a VM-execution control bit, based on the 3486 * allowed bit settings from the corresponding VMX capability MSR. 3487 */ 3488 static void test_rsvd_ctl_bit(const char *name, union vmx_ctrl_msr msr, 3489 enum Encoding encoding, unsigned bit) 3490 { 3491 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 0); 3492 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 1); 3493 } 3494 3495 /* 3496 * Reserved bits in the pin-based VM-execution controls must be set 3497 * properly. Software may consult the VMX capability MSRs to determine 3498 * the proper settings. 3499 * [Intel SDM] 3500 */ 3501 static void test_pin_based_ctls(void) 3502 { 3503 unsigned bit; 3504 3505 printf("%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PIN" : 3506 "MSR_IA32_VMX_PINBASED_CTLS", ctrl_pin_rev.val); 3507 for (bit = 0; bit < 32; bit++) 3508 test_rsvd_ctl_bit("pin-based controls", 3509 ctrl_pin_rev, PIN_CONTROLS, bit); 3510 } 3511 3512 /* 3513 * Reserved bits in the primary processor-based VM-execution controls 3514 * must be set properly. Software may consult the VMX capability MSRs 3515 * to determine the proper settings. 3516 * [Intel SDM] 3517 */ 3518 static void test_primary_processor_based_ctls(void) 3519 { 3520 unsigned bit; 3521 3522 printf("\n%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PROC" : 3523 "MSR_IA32_VMX_PROCBASED_CTLS", ctrl_cpu_rev[0].val); 3524 for (bit = 0; bit < 32; bit++) 3525 test_rsvd_ctl_bit("primary processor-based controls", 3526 ctrl_cpu_rev[0], CPU_EXEC_CTRL0, bit); 3527 } 3528 3529 /* 3530 * If the "activate secondary controls" primary processor-based 3531 * VM-execution control is 1, reserved bits in the secondary 3532 * processor-based VM-execution controls must be cleared. Software may 3533 * consult the VMX capability MSRs to determine which bits are 3534 * reserved. 3535 * If the "activate secondary controls" primary processor-based 3536 * VM-execution control is 0 (or if the processor does not support the 3537 * 1-setting of that control), no checks are performed on the 3538 * secondary processor-based VM-execution controls. 3539 * [Intel SDM] 3540 */ 3541 static void test_secondary_processor_based_ctls(void) 3542 { 3543 u32 primary; 3544 u32 secondary; 3545 unsigned bit; 3546 3547 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) 3548 return; 3549 3550 primary = vmcs_read(CPU_EXEC_CTRL0); 3551 secondary = vmcs_read(CPU_EXEC_CTRL1); 3552 3553 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3554 printf("\nMSR_IA32_VMX_PROCBASED_CTLS2: %lx\n", ctrl_cpu_rev[1].val); 3555 for (bit = 0; bit < 32; bit++) 3556 test_rsvd_ctl_bit("secondary processor-based controls", 3557 ctrl_cpu_rev[1], CPU_EXEC_CTRL1, bit); 3558 3559 /* 3560 * When the "activate secondary controls" VM-execution control 3561 * is clear, there are no checks on the secondary controls. 3562 */ 3563 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3564 vmcs_write(CPU_EXEC_CTRL1, ~0); 3565 report(vmlaunch_succeeds(), 3566 "Secondary processor-based controls ignored"); 3567 vmcs_write(CPU_EXEC_CTRL1, secondary); 3568 vmcs_write(CPU_EXEC_CTRL0, primary); 3569 } 3570 3571 static void try_cr3_target_count(unsigned i, unsigned max) 3572 { 3573 report_prefix_pushf("CR3 target count 0x%x", i); 3574 vmcs_write(CR3_TARGET_COUNT, i); 3575 if (i <= max) 3576 test_vmx_valid_controls(); 3577 else 3578 test_vmx_invalid_controls(); 3579 report_prefix_pop(); 3580 } 3581 3582 /* 3583 * The CR3-target count must not be greater than 4. Future processors 3584 * may support a different number of CR3-target values. Software 3585 * should read the VMX capability MSR IA32_VMX_MISC to determine the 3586 * number of values supported. 3587 * [Intel SDM] 3588 */ 3589 static void test_cr3_targets(void) 3590 { 3591 unsigned supported_targets = (rdmsr(MSR_IA32_VMX_MISC) >> 16) & 0x1ff; 3592 u32 cr3_targets = vmcs_read(CR3_TARGET_COUNT); 3593 unsigned i; 3594 3595 printf("\nSupported CR3 targets: %d\n", supported_targets); 3596 TEST_ASSERT(supported_targets <= 256); 3597 3598 try_cr3_target_count(-1u, supported_targets); 3599 try_cr3_target_count(0x80000000, supported_targets); 3600 try_cr3_target_count(0x7fffffff, supported_targets); 3601 for (i = 0; i <= supported_targets + 1; i++) 3602 try_cr3_target_count(i, supported_targets); 3603 vmcs_write(CR3_TARGET_COUNT, cr3_targets); 3604 3605 /* VMWRITE to nonexistent target fields should fail. */ 3606 for (i = supported_targets; i < 256; i++) 3607 TEST_ASSERT(vmcs_write(CR3_TARGET_0 + i*2, 0)); 3608 } 3609 3610 /* 3611 * Test a particular address setting in the VMCS 3612 */ 3613 static void test_vmcs_addr(const char *name, 3614 enum Encoding encoding, 3615 u64 align, 3616 bool ignored, 3617 bool skip_beyond_mapped_ram, 3618 u64 addr) 3619 { 3620 report_prefix_pushf("%s = %lx", name, addr); 3621 vmcs_write(encoding, addr); 3622 if (skip_beyond_mapped_ram && 3623 addr > fwcfg_get_u64(FW_CFG_RAM_SIZE) - align && 3624 addr < (1ul << cpuid_maxphyaddr())) 3625 printf("Skipping physical address beyond mapped RAM\n"); 3626 else if (ignored || (IS_ALIGNED(addr, align) && 3627 addr < (1ul << cpuid_maxphyaddr()))) 3628 test_vmx_valid_controls(); 3629 else 3630 test_vmx_invalid_controls(); 3631 report_prefix_pop(); 3632 } 3633 3634 /* 3635 * Test interesting values for a VMCS address 3636 */ 3637 static void test_vmcs_addr_values(const char *name, 3638 enum Encoding encoding, 3639 u64 align, 3640 bool ignored, 3641 bool skip_beyond_mapped_ram, 3642 u32 bit_start, u32 bit_end) 3643 { 3644 unsigned i; 3645 u64 orig_val = vmcs_read(encoding); 3646 3647 for (i = bit_start; i <= bit_end; i++) 3648 test_vmcs_addr(name, encoding, align, ignored, 3649 skip_beyond_mapped_ram, 1ul << i); 3650 3651 test_vmcs_addr(name, encoding, align, ignored, 3652 skip_beyond_mapped_ram, PAGE_SIZE - 1); 3653 test_vmcs_addr(name, encoding, align, ignored, 3654 skip_beyond_mapped_ram, PAGE_SIZE); 3655 test_vmcs_addr(name, encoding, align, ignored, 3656 skip_beyond_mapped_ram, 3657 (1ul << cpuid_maxphyaddr()) - PAGE_SIZE); 3658 test_vmcs_addr(name, encoding, align, ignored, 3659 skip_beyond_mapped_ram, -1ul); 3660 3661 vmcs_write(encoding, orig_val); 3662 } 3663 3664 /* 3665 * Test a physical address reference in the VMCS, when the corresponding 3666 * feature is enabled and when the corresponding feature is disabled. 3667 */ 3668 static void test_vmcs_addr_reference(u32 control_bit, enum Encoding field, 3669 const char *field_name, 3670 const char *control_name, u64 align, 3671 bool skip_beyond_mapped_ram, 3672 bool control_primary) 3673 { 3674 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 3675 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 3676 u64 page_addr; 3677 3678 if (control_primary) { 3679 if (!(ctrl_cpu_rev[0].clr & control_bit)) 3680 return; 3681 } else { 3682 if (!(ctrl_cpu_rev[1].clr & control_bit)) 3683 return; 3684 } 3685 3686 page_addr = vmcs_read(field); 3687 3688 report_prefix_pushf("%s enabled", control_name); 3689 if (control_primary) { 3690 vmcs_write(CPU_EXEC_CTRL0, primary | control_bit); 3691 } else { 3692 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3693 vmcs_write(CPU_EXEC_CTRL1, secondary | control_bit); 3694 } 3695 3696 test_vmcs_addr_values(field_name, field, align, false, 3697 skip_beyond_mapped_ram, 0, 63); 3698 report_prefix_pop(); 3699 3700 report_prefix_pushf("%s disabled", control_name); 3701 if (control_primary) { 3702 vmcs_write(CPU_EXEC_CTRL0, primary & ~control_bit); 3703 } else { 3704 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3705 vmcs_write(CPU_EXEC_CTRL1, secondary & ~control_bit); 3706 } 3707 3708 test_vmcs_addr_values(field_name, field, align, true, false, 0, 63); 3709 report_prefix_pop(); 3710 3711 vmcs_write(field, page_addr); 3712 vmcs_write(CPU_EXEC_CTRL0, primary); 3713 vmcs_write(CPU_EXEC_CTRL1, secondary); 3714 } 3715 3716 /* 3717 * If the "use I/O bitmaps" VM-execution control is 1, bits 11:0 of 3718 * each I/O-bitmap address must be 0. Neither address should set any 3719 * bits beyond the processor's physical-address width. 3720 * [Intel SDM] 3721 */ 3722 static void test_io_bitmaps(void) 3723 { 3724 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_A, 3725 "I/O bitmap A", "Use I/O bitmaps", 3726 PAGE_SIZE, false, true); 3727 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_B, 3728 "I/O bitmap B", "Use I/O bitmaps", 3729 PAGE_SIZE, false, true); 3730 } 3731 3732 /* 3733 * If the "use MSR bitmaps" VM-execution control is 1, bits 11:0 of 3734 * the MSR-bitmap address must be 0. The address should not set any 3735 * bits beyond the processor's physical-address width. 3736 * [Intel SDM] 3737 */ 3738 static void test_msr_bitmap(void) 3739 { 3740 test_vmcs_addr_reference(CPU_MSR_BITMAP, MSR_BITMAP, 3741 "MSR bitmap", "Use MSR bitmaps", 3742 PAGE_SIZE, false, true); 3743 } 3744 3745 /* 3746 * If the "use TPR shadow" VM-execution control is 1, the virtual-APIC 3747 * address must satisfy the following checks: 3748 * - Bits 11:0 of the address must be 0. 3749 * - The address should not set any bits beyond the processor's 3750 * physical-address width. 3751 * [Intel SDM] 3752 */ 3753 static void test_apic_virt_addr(void) 3754 { 3755 /* 3756 * Ensure the processor will never use the virtual-APIC page, since 3757 * we will point it to invalid RAM. Otherwise KVM is puzzled about 3758 * what we're trying to achieve and fails vmentry. 3759 */ 3760 u32 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 3761 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0 | CPU_CR8_LOAD | CPU_CR8_STORE); 3762 test_vmcs_addr_reference(CPU_TPR_SHADOW, APIC_VIRT_ADDR, 3763 "virtual-APIC address", "Use TPR shadow", 3764 PAGE_SIZE, false, true); 3765 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 3766 } 3767 3768 /* 3769 * If the "virtualize APIC-accesses" VM-execution control is 1, the 3770 * APIC-access address must satisfy the following checks: 3771 * - Bits 11:0 of the address must be 0. 3772 * - The address should not set any bits beyond the processor's 3773 * physical-address width. 3774 * [Intel SDM] 3775 */ 3776 static void test_apic_access_addr(void) 3777 { 3778 void *apic_access_page = alloc_page(); 3779 3780 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_page)); 3781 3782 test_vmcs_addr_reference(CPU_VIRT_APIC_ACCESSES, APIC_ACCS_ADDR, 3783 "APIC-access address", 3784 "virtualize APIC-accesses", PAGE_SIZE, 3785 true, false); 3786 } 3787 3788 static bool set_bit_pattern(u8 mask, u32 *secondary) 3789 { 3790 u8 i; 3791 bool flag = false; 3792 u32 test_bits[3] = { 3793 CPU_VIRT_X2APIC, 3794 CPU_APIC_REG_VIRT, 3795 CPU_VINTD 3796 }; 3797 3798 for (i = 0; i < ARRAY_SIZE(test_bits); i++) { 3799 if ((mask & (1u << i)) && 3800 (ctrl_cpu_rev[1].clr & test_bits[i])) { 3801 *secondary |= test_bits[i]; 3802 flag = true; 3803 } 3804 } 3805 3806 return (flag); 3807 } 3808 3809 /* 3810 * If the "use TPR shadow" VM-execution control is 0, the following 3811 * VM-execution controls must also be 0: 3812 * - virtualize x2APIC mode 3813 * - APIC-register virtualization 3814 * - virtual-interrupt delivery 3815 * [Intel SDM] 3816 * 3817 * 2. If the "virtualize x2APIC mode" VM-execution control is 1, the 3818 * "virtualize APIC accesses" VM-execution control must be 0. 3819 * [Intel SDM] 3820 */ 3821 static void test_apic_virtual_ctls(void) 3822 { 3823 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3824 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3825 u32 primary = saved_primary; 3826 u32 secondary = saved_secondary; 3827 bool is_ctrl_valid = false; 3828 char str[10] = "disabled"; 3829 u8 i = 0, j; 3830 3831 /* 3832 * First test 3833 */ 3834 if (!((ctrl_cpu_rev[0].clr & (CPU_SECONDARY | CPU_TPR_SHADOW)) == 3835 (CPU_SECONDARY | CPU_TPR_SHADOW))) 3836 return; 3837 3838 primary |= CPU_SECONDARY; 3839 primary &= ~CPU_TPR_SHADOW; 3840 vmcs_write(CPU_EXEC_CTRL0, primary); 3841 3842 while (1) { 3843 for (j = 1; j < 8; j++) { 3844 secondary &= ~(CPU_VIRT_X2APIC | CPU_APIC_REG_VIRT | CPU_VINTD); 3845 if (primary & CPU_TPR_SHADOW) { 3846 is_ctrl_valid = true; 3847 } else { 3848 if (! set_bit_pattern(j, &secondary)) 3849 is_ctrl_valid = true; 3850 else 3851 is_ctrl_valid = false; 3852 } 3853 3854 vmcs_write(CPU_EXEC_CTRL1, secondary); 3855 report_prefix_pushf("Use TPR shadow %s, virtualize x2APIC mode %s, APIC-register virtualization %s, virtual-interrupt delivery %s", 3856 str, (secondary & CPU_VIRT_X2APIC) ? "enabled" : "disabled", (secondary & CPU_APIC_REG_VIRT) ? "enabled" : "disabled", (secondary & CPU_VINTD) ? "enabled" : "disabled"); 3857 if (is_ctrl_valid) 3858 test_vmx_valid_controls(); 3859 else 3860 test_vmx_invalid_controls(); 3861 report_prefix_pop(); 3862 } 3863 3864 if (i == 1) 3865 break; 3866 i++; 3867 3868 primary |= CPU_TPR_SHADOW; 3869 vmcs_write(CPU_EXEC_CTRL0, primary); 3870 strcpy(str, "enabled"); 3871 } 3872 3873 /* 3874 * Second test 3875 */ 3876 u32 apic_virt_ctls = (CPU_VIRT_X2APIC | CPU_VIRT_APIC_ACCESSES); 3877 3878 primary = saved_primary; 3879 secondary = saved_secondary; 3880 if (!((ctrl_cpu_rev[1].clr & apic_virt_ctls) == apic_virt_ctls)) 3881 return; 3882 3883 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3884 secondary &= ~CPU_VIRT_APIC_ACCESSES; 3885 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_X2APIC); 3886 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access disabled"); 3887 test_vmx_valid_controls(); 3888 report_prefix_pop(); 3889 3890 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_APIC_ACCESSES); 3891 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access enabled"); 3892 test_vmx_valid_controls(); 3893 report_prefix_pop(); 3894 3895 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_X2APIC); 3896 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access enabled"); 3897 test_vmx_invalid_controls(); 3898 report_prefix_pop(); 3899 3900 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_APIC_ACCESSES); 3901 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access disabled"); 3902 test_vmx_valid_controls(); 3903 report_prefix_pop(); 3904 3905 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3906 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3907 } 3908 3909 /* 3910 * If the "virtual-interrupt delivery" VM-execution control is 1, the 3911 * "external-interrupt exiting" VM-execution control must be 1. 3912 * [Intel SDM] 3913 */ 3914 static void test_virtual_intr_ctls(void) 3915 { 3916 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3917 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3918 u32 saved_pin = vmcs_read(PIN_CONTROLS); 3919 u32 primary = saved_primary; 3920 u32 secondary = saved_secondary; 3921 u32 pin = saved_pin; 3922 3923 if (!((ctrl_cpu_rev[1].clr & CPU_VINTD) && 3924 (ctrl_pin_rev.clr & PIN_EXTINT))) 3925 return; 3926 3927 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 3928 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VINTD); 3929 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 3930 report_prefix_pushf("Virtualize interrupt-delivery disabled; external-interrupt exiting disabled"); 3931 test_vmx_valid_controls(); 3932 report_prefix_pop(); 3933 3934 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VINTD); 3935 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 3936 test_vmx_invalid_controls(); 3937 report_prefix_pop(); 3938 3939 vmcs_write(PIN_CONTROLS, pin | PIN_EXTINT); 3940 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting enabled"); 3941 test_vmx_valid_controls(); 3942 report_prefix_pop(); 3943 3944 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 3945 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 3946 test_vmx_invalid_controls(); 3947 report_prefix_pop(); 3948 3949 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3950 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3951 vmcs_write(PIN_CONTROLS, saved_pin); 3952 } 3953 3954 static void test_pi_desc_addr(u64 addr, bool is_ctrl_valid) 3955 { 3956 vmcs_write(POSTED_INTR_DESC_ADDR, addr); 3957 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-descriptor-address 0x%lx", addr); 3958 if (is_ctrl_valid) 3959 test_vmx_valid_controls(); 3960 else 3961 test_vmx_invalid_controls(); 3962 report_prefix_pop(); 3963 } 3964 3965 /* 3966 * If the "process posted interrupts" VM-execution control is 1, the 3967 * following must be true: 3968 * 3969 * - The "virtual-interrupt delivery" VM-execution control is 1. 3970 * - The "acknowledge interrupt on exit" VM-exit control is 1. 3971 * - The posted-interrupt notification vector has a value in the 3972 * - range 0 - 255 (bits 15:8 are all 0). 3973 * - Bits 5:0 of the posted-interrupt descriptor address are all 0. 3974 * - The posted-interrupt descriptor address does not set any bits 3975 * beyond the processor's physical-address width. 3976 * [Intel SDM] 3977 */ 3978 static void test_posted_intr(void) 3979 { 3980 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3981 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3982 u32 saved_pin = vmcs_read(PIN_CONTROLS); 3983 u32 exit_ctl_saved = vmcs_read(EXI_CONTROLS); 3984 u32 primary = saved_primary; 3985 u32 secondary = saved_secondary; 3986 u32 pin = saved_pin; 3987 u32 exit_ctl = exit_ctl_saved; 3988 u16 vec; 3989 int i; 3990 3991 if (!((ctrl_pin_rev.clr & PIN_POST_INTR) && 3992 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 3993 (ctrl_exit_rev.clr & EXI_INTA))) 3994 return; 3995 3996 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 3997 3998 /* 3999 * Test virtual-interrupt-delivery and acknowledge-interrupt-on-exit 4000 */ 4001 pin |= PIN_POST_INTR; 4002 vmcs_write(PIN_CONTROLS, pin); 4003 secondary &= ~CPU_VINTD; 4004 vmcs_write(CPU_EXEC_CTRL1, secondary); 4005 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled"); 4006 test_vmx_invalid_controls(); 4007 report_prefix_pop(); 4008 4009 secondary |= CPU_VINTD; 4010 vmcs_write(CPU_EXEC_CTRL1, secondary); 4011 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled"); 4012 test_vmx_invalid_controls(); 4013 report_prefix_pop(); 4014 4015 exit_ctl &= ~EXI_INTA; 4016 vmcs_write(EXI_CONTROLS, exit_ctl); 4017 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit disabled"); 4018 test_vmx_invalid_controls(); 4019 report_prefix_pop(); 4020 4021 exit_ctl |= EXI_INTA; 4022 vmcs_write(EXI_CONTROLS, exit_ctl); 4023 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 4024 test_vmx_valid_controls(); 4025 report_prefix_pop(); 4026 4027 secondary &= ~CPU_VINTD; 4028 vmcs_write(CPU_EXEC_CTRL1, secondary); 4029 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled; acknowledge-interrupt-on-exit enabled"); 4030 test_vmx_invalid_controls(); 4031 report_prefix_pop(); 4032 4033 secondary |= CPU_VINTD; 4034 vmcs_write(CPU_EXEC_CTRL1, secondary); 4035 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 4036 test_vmx_valid_controls(); 4037 report_prefix_pop(); 4038 4039 /* 4040 * Test posted-interrupt notification vector 4041 */ 4042 for (i = 0; i < 8; i++) { 4043 vec = (1ul << i); 4044 vmcs_write(PINV, vec); 4045 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 4046 test_vmx_valid_controls(); 4047 report_prefix_pop(); 4048 } 4049 for (i = 8; i < 16; i++) { 4050 vec = (1ul << i); 4051 vmcs_write(PINV, vec); 4052 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 4053 test_vmx_invalid_controls(); 4054 report_prefix_pop(); 4055 } 4056 4057 vec &= ~(0xff << 8); 4058 vmcs_write(PINV, vec); 4059 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 4060 test_vmx_valid_controls(); 4061 report_prefix_pop(); 4062 4063 /* 4064 * Test posted-interrupt descriptor address 4065 */ 4066 for (i = 0; i < 6; i++) { 4067 test_pi_desc_addr(1ul << i, false); 4068 } 4069 4070 test_pi_desc_addr(0xf0, false); 4071 test_pi_desc_addr(0xff, false); 4072 test_pi_desc_addr(0x0f, false); 4073 test_pi_desc_addr(0x8000, true); 4074 test_pi_desc_addr(0x00, true); 4075 test_pi_desc_addr(0xc000, true); 4076 4077 test_vmcs_addr_values("process-posted interrupts", 4078 POSTED_INTR_DESC_ADDR, 64, 4079 false, false, 0, 63); 4080 4081 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 4082 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 4083 vmcs_write(PIN_CONTROLS, saved_pin); 4084 } 4085 4086 static void test_apic_ctls(void) 4087 { 4088 test_apic_virt_addr(); 4089 test_apic_access_addr(); 4090 test_apic_virtual_ctls(); 4091 test_virtual_intr_ctls(); 4092 test_posted_intr(); 4093 } 4094 4095 /* 4096 * If the "enable VPID" VM-execution control is 1, the value of the 4097 * of the VPID VM-execution control field must not be 0000H. 4098 * [Intel SDM] 4099 */ 4100 static void test_vpid(void) 4101 { 4102 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 4103 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 4104 u16 vpid = 0x0000; 4105 int i; 4106 4107 if (!is_vpid_supported()) { 4108 report_skip("%s : Secondary controls and/or VPID not supported", __func__); 4109 return; 4110 } 4111 4112 vmcs_write(CPU_EXEC_CTRL0, saved_primary | CPU_SECONDARY); 4113 vmcs_write(CPU_EXEC_CTRL1, saved_secondary & ~CPU_VPID); 4114 vmcs_write(VPID, vpid); 4115 report_prefix_pushf("VPID disabled; VPID value %x", vpid); 4116 test_vmx_valid_controls(); 4117 report_prefix_pop(); 4118 4119 vmcs_write(CPU_EXEC_CTRL1, saved_secondary | CPU_VPID); 4120 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 4121 test_vmx_invalid_controls(); 4122 report_prefix_pop(); 4123 4124 for (i = 0; i < 16; i++) { 4125 vpid = (short)1 << i;; 4126 vmcs_write(VPID, vpid); 4127 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 4128 test_vmx_valid_controls(); 4129 report_prefix_pop(); 4130 } 4131 4132 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 4133 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 4134 } 4135 4136 static void set_vtpr(unsigned vtpr) 4137 { 4138 *(u32 *)phys_to_virt(vmcs_read(APIC_VIRT_ADDR) + APIC_TASKPRI) = vtpr; 4139 } 4140 4141 static void try_tpr_threshold_and_vtpr(unsigned threshold, unsigned vtpr) 4142 { 4143 bool valid = true; 4144 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4145 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4146 4147 if ((primary & CPU_TPR_SHADOW) && 4148 (!(primary & CPU_SECONDARY) || 4149 !(secondary & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 4150 valid = (threshold & 0xf) <= ((vtpr >> 4) & 0xf); 4151 4152 set_vtpr(vtpr); 4153 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0x%x", 4154 threshold, (vtpr >> 4) & 0xf); 4155 if (valid) 4156 test_vmx_valid_controls(); 4157 else 4158 test_vmx_invalid_controls(); 4159 report_prefix_pop(); 4160 } 4161 4162 static void test_invalid_event_injection(void) 4163 { 4164 u32 ent_intr_info_save = vmcs_read(ENT_INTR_INFO); 4165 u32 ent_intr_error_save = vmcs_read(ENT_INTR_ERROR); 4166 u32 ent_inst_len_save = vmcs_read(ENT_INST_LEN); 4167 u32 primary_save = vmcs_read(CPU_EXEC_CTRL0); 4168 u32 secondary_save = vmcs_read(CPU_EXEC_CTRL1); 4169 u64 guest_cr0_save = vmcs_read(GUEST_CR0); 4170 u32 ent_intr_info_base = INTR_INFO_VALID_MASK; 4171 u32 ent_intr_info, ent_intr_err, ent_intr_len; 4172 u32 cnt; 4173 4174 /* Setup */ 4175 report_prefix_push("invalid event injection"); 4176 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4177 vmcs_write(ENT_INST_LEN, 0x00000001); 4178 4179 /* The field's interruption type is not set to a reserved value. */ 4180 ent_intr_info = ent_intr_info_base | INTR_TYPE_RESERVED | DE_VECTOR; 4181 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4182 "RESERVED interruption type invalid [-]", 4183 ent_intr_info); 4184 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4185 test_vmx_invalid_controls(); 4186 report_prefix_pop(); 4187 4188 ent_intr_info = ent_intr_info_base | INTR_TYPE_EXT_INTR | 4189 DE_VECTOR; 4190 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4191 "RESERVED interruption type invalid [+]", 4192 ent_intr_info); 4193 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4194 test_vmx_valid_controls(); 4195 report_prefix_pop(); 4196 4197 /* If the interruption type is other event, the vector is 0. */ 4198 ent_intr_info = ent_intr_info_base | INTR_TYPE_OTHER_EVENT | DB_VECTOR; 4199 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4200 "(OTHER EVENT && vector != 0) invalid [-]", 4201 ent_intr_info); 4202 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4203 test_vmx_invalid_controls(); 4204 report_prefix_pop(); 4205 4206 /* If the interruption type is NMI, the vector is 2 (negative case). */ 4207 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | DE_VECTOR; 4208 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4209 "(NMI && vector != 2) invalid [-]", ent_intr_info); 4210 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4211 test_vmx_invalid_controls(); 4212 report_prefix_pop(); 4213 4214 /* If the interruption type is NMI, the vector is 2 (positive case). */ 4215 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | NMI_VECTOR; 4216 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4217 "(NMI && vector == 2) valid [+]", ent_intr_info); 4218 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4219 test_vmx_valid_controls(); 4220 report_prefix_pop(); 4221 4222 /* 4223 * If the interruption type 4224 * is HW exception, the vector is at most 31. 4225 */ 4226 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 0x20; 4227 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4228 "(HW exception && vector > 31) invalid [-]", 4229 ent_intr_info); 4230 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4231 test_vmx_invalid_controls(); 4232 report_prefix_pop(); 4233 4234 /* 4235 * deliver-error-code is 1 iff either 4236 * (a) the "unrestricted guest" VM-execution control is 0 4237 * (b) CR0.PE is set. 4238 */ 4239 4240 /* Assert that unrestricted guest is disabled or unsupported */ 4241 assert(!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 4242 !(secondary_save & CPU_URG)); 4243 4244 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4245 GP_VECTOR; 4246 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4247 "error code <-> (!URG || prot_mode) [-]", 4248 ent_intr_info); 4249 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4250 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4251 test_vmx_invalid_controls(); 4252 report_prefix_pop(); 4253 4254 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4255 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4256 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4257 "error code <-> (!URG || prot_mode) [+]", 4258 ent_intr_info); 4259 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4260 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4261 test_vmx_valid_controls(); 4262 report_prefix_pop(); 4263 4264 if (enable_unrestricted_guest(false)) 4265 goto skip_unrestricted_guest; 4266 4267 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4268 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4269 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4270 "error code <-> (!URG || prot_mode) [-]", 4271 ent_intr_info); 4272 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4273 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4274 test_vmx_invalid_controls(); 4275 report_prefix_pop(); 4276 4277 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4278 GP_VECTOR; 4279 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4280 "error code <-> (!URG || prot_mode) [-]", 4281 ent_intr_info); 4282 vmcs_write(GUEST_CR0, guest_cr0_save | X86_CR0_PE); 4283 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4284 test_vmx_invalid_controls(); 4285 report_prefix_pop(); 4286 4287 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4288 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4289 4290 skip_unrestricted_guest: 4291 vmcs_write(GUEST_CR0, guest_cr0_save); 4292 4293 /* deliver-error-code is 1 iff the interruption type is HW exception */ 4294 report_prefix_push("error code <-> HW exception"); 4295 for (cnt = 0; cnt < 8; cnt++) { 4296 u32 exception_type_mask = cnt << 8; 4297 u32 deliver_error_code_mask = 4298 exception_type_mask != INTR_TYPE_HARD_EXCEPTION ? 4299 INTR_INFO_DELIVER_CODE_MASK : 0; 4300 4301 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4302 exception_type_mask | GP_VECTOR; 4303 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4304 ent_intr_info); 4305 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4306 test_vmx_invalid_controls(); 4307 report_prefix_pop(); 4308 } 4309 report_prefix_pop(); 4310 4311 /* 4312 * deliver-error-code is 1 iff the the vector 4313 * indicates an exception that would normally deliver an error code 4314 */ 4315 report_prefix_push("error code <-> vector delivers error code"); 4316 for (cnt = 0; cnt < 32; cnt++) { 4317 bool has_error_code = false; 4318 u32 deliver_error_code_mask; 4319 4320 switch (cnt) { 4321 case DF_VECTOR: 4322 case TS_VECTOR: 4323 case NP_VECTOR: 4324 case SS_VECTOR: 4325 case GP_VECTOR: 4326 case PF_VECTOR: 4327 case AC_VECTOR: 4328 has_error_code = true; 4329 case CP_VECTOR: 4330 /* Some CPUs have error code and some do not, skip */ 4331 continue; 4332 } 4333 4334 /* Negative case */ 4335 deliver_error_code_mask = has_error_code ? 4336 0 : 4337 INTR_INFO_DELIVER_CODE_MASK; 4338 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4339 INTR_TYPE_HARD_EXCEPTION | cnt; 4340 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4341 ent_intr_info); 4342 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4343 test_vmx_invalid_controls(); 4344 report_prefix_pop(); 4345 4346 /* Positive case */ 4347 deliver_error_code_mask = has_error_code ? 4348 INTR_INFO_DELIVER_CODE_MASK : 4349 0; 4350 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4351 INTR_TYPE_HARD_EXCEPTION | cnt; 4352 report_prefix_pushf("VM-entry intr info=0x%x [+]", 4353 ent_intr_info); 4354 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4355 test_vmx_valid_controls(); 4356 report_prefix_pop(); 4357 } 4358 report_prefix_pop(); 4359 4360 /* Reserved bits in the field (30:12) are 0. */ 4361 report_prefix_push("reserved bits clear"); 4362 for (cnt = 12; cnt <= 30; cnt++) { 4363 ent_intr_info = ent_intr_info_base | 4364 INTR_INFO_DELIVER_CODE_MASK | 4365 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR | 4366 (1U << cnt); 4367 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4368 ent_intr_info); 4369 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4370 test_vmx_invalid_controls(); 4371 report_prefix_pop(); 4372 } 4373 report_prefix_pop(); 4374 4375 /* 4376 * If deliver-error-code is 1 4377 * bits 31:16 of the VM-entry exception error-code field are 0. 4378 */ 4379 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4380 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4381 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4382 "VM-entry exception error code[31:16] clear", 4383 ent_intr_info); 4384 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4385 for (cnt = 16; cnt <= 31; cnt++) { 4386 ent_intr_err = 1U << cnt; 4387 report_prefix_pushf("VM-entry intr error=0x%x [-]", 4388 ent_intr_err); 4389 vmcs_write(ENT_INTR_ERROR, ent_intr_err); 4390 test_vmx_invalid_controls(); 4391 report_prefix_pop(); 4392 } 4393 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4394 report_prefix_pop(); 4395 4396 /* 4397 * If the interruption type is software interrupt, software exception, 4398 * or privileged software exception, the VM-entry instruction-length 4399 * field is in the range 0 - 15. 4400 */ 4401 4402 for (cnt = 0; cnt < 3; cnt++) { 4403 switch (cnt) { 4404 case 0: 4405 ent_intr_info = ent_intr_info_base | 4406 INTR_TYPE_SOFT_INTR; 4407 break; 4408 case 1: 4409 ent_intr_info = ent_intr_info_base | 4410 INTR_TYPE_SOFT_EXCEPTION; 4411 break; 4412 case 2: 4413 ent_intr_info = ent_intr_info_base | 4414 INTR_TYPE_PRIV_SW_EXCEPTION; 4415 break; 4416 } 4417 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4418 "VM-entry instruction-length check", 4419 ent_intr_info); 4420 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4421 4422 /* Instruction length set to -1 (0xFFFFFFFF) should fail */ 4423 ent_intr_len = -1; 4424 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4425 ent_intr_len); 4426 vmcs_write(ENT_INST_LEN, ent_intr_len); 4427 test_vmx_invalid_controls(); 4428 report_prefix_pop(); 4429 4430 /* Instruction length set to 16 should fail */ 4431 ent_intr_len = 0x00000010; 4432 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4433 ent_intr_len); 4434 vmcs_write(ENT_INST_LEN, 0x00000010); 4435 test_vmx_invalid_controls(); 4436 report_prefix_pop(); 4437 4438 report_prefix_pop(); 4439 } 4440 4441 /* Cleanup */ 4442 vmcs_write(ENT_INTR_INFO, ent_intr_info_save); 4443 vmcs_write(ENT_INTR_ERROR, ent_intr_error_save); 4444 vmcs_write(ENT_INST_LEN, ent_inst_len_save); 4445 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4446 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4447 vmcs_write(GUEST_CR0, guest_cr0_save); 4448 report_prefix_pop(); 4449 } 4450 4451 /* 4452 * Test interesting vTPR values for a given TPR threshold. 4453 */ 4454 static void test_vtpr_values(unsigned threshold) 4455 { 4456 try_tpr_threshold_and_vtpr(threshold, (threshold - 1) << 4); 4457 try_tpr_threshold_and_vtpr(threshold, threshold << 4); 4458 try_tpr_threshold_and_vtpr(threshold, (threshold + 1) << 4); 4459 } 4460 4461 static void try_tpr_threshold(unsigned threshold) 4462 { 4463 bool valid = true; 4464 4465 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4466 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4467 4468 if ((primary & CPU_TPR_SHADOW) && !((primary & CPU_SECONDARY) && 4469 (secondary & CPU_VINTD))) 4470 valid = !(threshold >> 4); 4471 4472 set_vtpr(-1); 4473 vmcs_write(TPR_THRESHOLD, threshold); 4474 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0xf", threshold); 4475 if (valid) 4476 test_vmx_valid_controls(); 4477 else 4478 test_vmx_invalid_controls(); 4479 report_prefix_pop(); 4480 4481 if (valid) 4482 test_vtpr_values(threshold); 4483 } 4484 4485 /* 4486 * Test interesting TPR threshold values. 4487 */ 4488 static void test_tpr_threshold_values(void) 4489 { 4490 unsigned i; 4491 4492 for (i = 0; i < 0x10; i++) 4493 try_tpr_threshold(i); 4494 for (i = 4; i < 32; i++) 4495 try_tpr_threshold(1u << i); 4496 try_tpr_threshold(-1u); 4497 try_tpr_threshold(0x7fffffff); 4498 } 4499 4500 /* 4501 * This test covers the following two VM entry checks: 4502 * 4503 * i) If the "use TPR shadow" VM-execution control is 1 and the 4504 * "virtual-interrupt delivery" VM-execution control is 0, bits 4505 * 31:4 of the TPR threshold VM-execution control field must 4506 be 0. 4507 * [Intel SDM] 4508 * 4509 * ii) If the "use TPR shadow" VM-execution control is 1, the 4510 * "virtual-interrupt delivery" VM-execution control is 0 4511 * and the "virtualize APIC accesses" VM-execution control 4512 * is 0, the value of bits 3:0 of the TPR threshold VM-execution 4513 * control field must not be greater than the value of bits 4514 * 7:4 of VTPR. 4515 * [Intel SDM] 4516 */ 4517 static void test_tpr_threshold(void) 4518 { 4519 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4520 u64 apic_virt_addr = vmcs_read(APIC_VIRT_ADDR); 4521 u64 threshold = vmcs_read(TPR_THRESHOLD); 4522 void *virtual_apic_page; 4523 4524 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) 4525 return; 4526 4527 virtual_apic_page = alloc_page(); 4528 memset(virtual_apic_page, 0xff, PAGE_SIZE); 4529 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 4530 4531 vmcs_write(CPU_EXEC_CTRL0, primary & ~(CPU_TPR_SHADOW | CPU_SECONDARY)); 4532 report_prefix_pushf("Use TPR shadow disabled, secondary controls disabled"); 4533 test_tpr_threshold_values(); 4534 report_prefix_pop(); 4535 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_TPR_SHADOW); 4536 report_prefix_pushf("Use TPR shadow enabled, secondary controls disabled"); 4537 test_tpr_threshold_values(); 4538 report_prefix_pop(); 4539 4540 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4541 (ctrl_cpu_rev[1].clr & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 4542 goto out; 4543 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4544 4545 if (ctrl_cpu_rev[1].clr & CPU_VINTD) { 4546 vmcs_write(CPU_EXEC_CTRL1, CPU_VINTD); 4547 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4548 test_tpr_threshold_values(); 4549 report_prefix_pop(); 4550 4551 vmcs_write(CPU_EXEC_CTRL0, 4552 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4553 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4554 test_tpr_threshold_values(); 4555 report_prefix_pop(); 4556 } 4557 4558 if (ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES) { 4559 vmcs_write(CPU_EXEC_CTRL0, 4560 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4561 vmcs_write(CPU_EXEC_CTRL1, CPU_VIRT_APIC_ACCESSES); 4562 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4563 test_tpr_threshold_values(); 4564 report_prefix_pop(); 4565 4566 vmcs_write(CPU_EXEC_CTRL0, 4567 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4568 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4569 test_tpr_threshold_values(); 4570 report_prefix_pop(); 4571 } 4572 4573 if ((ctrl_cpu_rev[1].clr & 4574 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) == 4575 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) { 4576 vmcs_write(CPU_EXEC_CTRL0, 4577 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4578 vmcs_write(CPU_EXEC_CTRL1, 4579 CPU_VINTD | CPU_VIRT_APIC_ACCESSES); 4580 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4581 test_tpr_threshold_values(); 4582 report_prefix_pop(); 4583 4584 vmcs_write(CPU_EXEC_CTRL0, 4585 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4586 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4587 test_tpr_threshold_values(); 4588 report_prefix_pop(); 4589 } 4590 4591 vmcs_write(CPU_EXEC_CTRL1, secondary); 4592 out: 4593 vmcs_write(TPR_THRESHOLD, threshold); 4594 vmcs_write(APIC_VIRT_ADDR, apic_virt_addr); 4595 vmcs_write(CPU_EXEC_CTRL0, primary); 4596 } 4597 4598 /* 4599 * This test verifies the following two vmentry checks: 4600 * 4601 * If the "NMI exiting" VM-execution control is 0, "Virtual NMIs" 4602 * VM-execution control must be 0. 4603 * [Intel SDM] 4604 * 4605 * If the "virtual NMIs" VM-execution control is 0, the "NMI-window 4606 * exiting" VM-execution control must be 0. 4607 * [Intel SDM] 4608 */ 4609 static void test_nmi_ctrls(void) 4610 { 4611 u32 pin_ctrls, cpu_ctrls0, test_pin_ctrls, test_cpu_ctrls0; 4612 4613 if ((ctrl_pin_rev.clr & (PIN_NMI | PIN_VIRT_NMI)) != 4614 (PIN_NMI | PIN_VIRT_NMI)) { 4615 report_skip("%s : NMI exiting and/or Virtual NMIs not supported", __func__); 4616 return; 4617 } 4618 4619 /* Save the controls so that we can restore them after our tests */ 4620 pin_ctrls = vmcs_read(PIN_CONTROLS); 4621 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 4622 4623 test_pin_ctrls = pin_ctrls & ~(PIN_NMI | PIN_VIRT_NMI); 4624 test_cpu_ctrls0 = cpu_ctrls0 & ~CPU_NMI_WINDOW; 4625 4626 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4627 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs disabled"); 4628 test_vmx_valid_controls(); 4629 report_prefix_pop(); 4630 4631 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_VIRT_NMI); 4632 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs enabled"); 4633 test_vmx_invalid_controls(); 4634 report_prefix_pop(); 4635 4636 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4637 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs enabled"); 4638 test_vmx_valid_controls(); 4639 report_prefix_pop(); 4640 4641 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_NMI); 4642 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs disabled"); 4643 test_vmx_valid_controls(); 4644 report_prefix_pop(); 4645 4646 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 4647 report_info("NMI-window exiting is not supported, skipping..."); 4648 goto done; 4649 } 4650 4651 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4652 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4653 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting enabled"); 4654 test_vmx_invalid_controls(); 4655 report_prefix_pop(); 4656 4657 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4658 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4659 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting disabled"); 4660 test_vmx_valid_controls(); 4661 report_prefix_pop(); 4662 4663 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4664 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4665 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting enabled"); 4666 test_vmx_valid_controls(); 4667 report_prefix_pop(); 4668 4669 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4670 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4671 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting disabled"); 4672 test_vmx_valid_controls(); 4673 report_prefix_pop(); 4674 4675 /* Restore the controls to their original values */ 4676 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 4677 done: 4678 vmcs_write(PIN_CONTROLS, pin_ctrls); 4679 } 4680 4681 static void test_eptp_ad_bit(u64 eptp, bool is_ctrl_valid) 4682 { 4683 vmcs_write(EPTP, eptp); 4684 report_prefix_pushf("Enable-EPT enabled; EPT accessed and dirty flag %s", 4685 (eptp & EPTP_AD_FLAG) ? "1": "0"); 4686 if (is_ctrl_valid) 4687 test_vmx_valid_controls(); 4688 else 4689 test_vmx_invalid_controls(); 4690 report_prefix_pop(); 4691 4692 } 4693 4694 /* 4695 * 1. If the "enable EPT" VM-execution control is 1, the "EPTP VM-execution" 4696 * control field must satisfy the following checks: 4697 * 4698 * - The EPT memory type (bits 2:0) must be a value supported by the 4699 * processor as indicated in the IA32_VMX_EPT_VPID_CAP MSR. 4700 * - Bits 5:3 (1 less than the EPT page-walk length) must indicate a 4701 * supported EPT page-walk length. 4702 * - Bit 6 (enable bit for accessed and dirty flags for EPT) must be 4703 * 0 if bit 21 of the IA32_VMX_EPT_VPID_CAP MSR is read as 0, 4704 * indicating that the processor does not support accessed and dirty 4705 * dirty flags for EPT. 4706 * - Reserved bits 11:7 and 63:N (where N is the processor's 4707 * physical-address width) must all be 0. 4708 * 4709 * 2. If the "unrestricted guest" VM-execution control is 1, the 4710 * "enable EPT" VM-execution control must also be 1. 4711 */ 4712 static void test_ept_eptp(void) 4713 { 4714 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4715 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4716 u64 eptp_saved = vmcs_read(EPTP); 4717 u32 primary = primary_saved; 4718 u32 secondary = secondary_saved; 4719 u64 eptp = eptp_saved; 4720 u32 i, maxphysaddr; 4721 u64 j, resv_bits_mask = 0; 4722 4723 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4724 (ctrl_cpu_rev[1].clr & CPU_EPT))) { 4725 report_skip("%s : \"CPU secondary\" and/or \"enable EPT\" exec control not supported", __func__); 4726 return; 4727 } 4728 4729 /* Support for 4-level EPT is mandatory. */ 4730 report(is_4_level_ept_supported(), "4-level EPT support check"); 4731 4732 primary |= CPU_SECONDARY; 4733 vmcs_write(CPU_EXEC_CTRL0, primary); 4734 secondary |= CPU_EPT; 4735 vmcs_write(CPU_EXEC_CTRL1, secondary); 4736 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4737 (3ul << EPTP_PG_WALK_LEN_SHIFT); 4738 vmcs_write(EPTP, eptp); 4739 4740 for (i = 0; i < 8; i++) { 4741 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | i; 4742 vmcs_write(EPTP, eptp); 4743 report_prefix_pushf("Enable-EPT enabled; EPT memory type %lu", 4744 eptp & EPT_MEM_TYPE_MASK); 4745 if (is_ept_memtype_supported(i)) 4746 test_vmx_valid_controls(); 4747 else 4748 test_vmx_invalid_controls(); 4749 report_prefix_pop(); 4750 } 4751 4752 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | 6ul; 4753 4754 /* 4755 * Page walk length (bits 5:3). Note, the value in VMCS.EPTP "is 1 4756 * less than the EPT page-walk length". 4757 */ 4758 for (i = 0; i < 8; i++) { 4759 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4760 (i << EPTP_PG_WALK_LEN_SHIFT); 4761 4762 vmcs_write(EPTP, eptp); 4763 report_prefix_pushf("Enable-EPT enabled; EPT page walk length %lu", 4764 eptp & EPTP_PG_WALK_LEN_MASK); 4765 if (i == 3 || (i == 4 && is_5_level_ept_supported())) 4766 test_vmx_valid_controls(); 4767 else 4768 test_vmx_invalid_controls(); 4769 report_prefix_pop(); 4770 } 4771 4772 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4773 3ul << EPTP_PG_WALK_LEN_SHIFT; 4774 4775 /* 4776 * Accessed and dirty flag (bit 6) 4777 */ 4778 if (ept_ad_bits_supported()) { 4779 report_info("Processor supports accessed and dirty flag"); 4780 eptp &= ~EPTP_AD_FLAG; 4781 test_eptp_ad_bit(eptp, true); 4782 4783 eptp |= EPTP_AD_FLAG; 4784 test_eptp_ad_bit(eptp, true); 4785 } else { 4786 report_info("Processor does not supports accessed and dirty flag"); 4787 eptp &= ~EPTP_AD_FLAG; 4788 test_eptp_ad_bit(eptp, true); 4789 4790 eptp |= EPTP_AD_FLAG; 4791 test_eptp_ad_bit(eptp, false); 4792 } 4793 4794 /* 4795 * Reserved bits [11:7] and [63:N] 4796 */ 4797 for (i = 0; i < 32; i++) { 4798 eptp = (eptp & 4799 ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)) | 4800 (i << EPTP_RESERV_BITS_SHIFT); 4801 vmcs_write(EPTP, eptp); 4802 report_prefix_pushf("Enable-EPT enabled; reserved bits [11:7] %lu", 4803 (eptp >> EPTP_RESERV_BITS_SHIFT) & 4804 EPTP_RESERV_BITS_MASK); 4805 if (i == 0) 4806 test_vmx_valid_controls(); 4807 else 4808 test_vmx_invalid_controls(); 4809 report_prefix_pop(); 4810 } 4811 4812 eptp = (eptp & ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)); 4813 4814 maxphysaddr = cpuid_maxphyaddr(); 4815 for (i = 0; i < (63 - maxphysaddr + 1); i++) { 4816 resv_bits_mask |= 1ul << i; 4817 } 4818 4819 for (j = maxphysaddr - 1; j <= 63; j++) { 4820 eptp = (eptp & ~(resv_bits_mask << maxphysaddr)) | 4821 (j < maxphysaddr ? 0 : 1ul << j); 4822 vmcs_write(EPTP, eptp); 4823 report_prefix_pushf("Enable-EPT enabled; reserved bits [63:N] %lu", 4824 (eptp >> maxphysaddr) & resv_bits_mask); 4825 if (j < maxphysaddr) 4826 test_vmx_valid_controls(); 4827 else 4828 test_vmx_invalid_controls(); 4829 report_prefix_pop(); 4830 } 4831 4832 secondary &= ~(CPU_EPT | CPU_URG); 4833 vmcs_write(CPU_EXEC_CTRL1, secondary); 4834 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest disabled"); 4835 test_vmx_valid_controls(); 4836 report_prefix_pop(); 4837 4838 if (!(ctrl_cpu_rev[1].clr & CPU_URG)) 4839 goto skip_unrestricted_guest; 4840 4841 secondary |= CPU_URG; 4842 vmcs_write(CPU_EXEC_CTRL1, secondary); 4843 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest enabled"); 4844 test_vmx_invalid_controls(); 4845 report_prefix_pop(); 4846 4847 secondary |= CPU_EPT; 4848 setup_dummy_ept(); 4849 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest enabled"); 4850 test_vmx_valid_controls(); 4851 report_prefix_pop(); 4852 4853 skip_unrestricted_guest: 4854 secondary &= ~CPU_URG; 4855 vmcs_write(CPU_EXEC_CTRL1, secondary); 4856 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest disabled"); 4857 test_vmx_valid_controls(); 4858 report_prefix_pop(); 4859 4860 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4861 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4862 vmcs_write(EPTP, eptp_saved); 4863 } 4864 4865 /* 4866 * If the 'enable PML' VM-execution control is 1, the 'enable EPT' 4867 * VM-execution control must also be 1. In addition, the PML address 4868 * must satisfy the following checks: 4869 * 4870 * * Bits 11:0 of the address must be 0. 4871 * * The address should not set any bits beyond the processor's 4872 * physical-address width. 4873 * 4874 * [Intel SDM] 4875 */ 4876 static void test_pml(void) 4877 { 4878 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4879 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4880 u32 primary = primary_saved; 4881 u32 secondary = secondary_saved; 4882 4883 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4884 (ctrl_cpu_rev[1].clr & CPU_EPT) && (ctrl_cpu_rev[1].clr & CPU_PML))) { 4885 report_skip("%s : \"Secondary execution\" or \"enable EPT\" or \"enable PML\" control not supported", __func__); 4886 return; 4887 } 4888 4889 primary |= CPU_SECONDARY; 4890 vmcs_write(CPU_EXEC_CTRL0, primary); 4891 secondary &= ~(CPU_PML | CPU_EPT); 4892 vmcs_write(CPU_EXEC_CTRL1, secondary); 4893 report_prefix_pushf("enable-PML disabled, enable-EPT disabled"); 4894 test_vmx_valid_controls(); 4895 report_prefix_pop(); 4896 4897 secondary |= CPU_PML; 4898 vmcs_write(CPU_EXEC_CTRL1, secondary); 4899 report_prefix_pushf("enable-PML enabled, enable-EPT disabled"); 4900 test_vmx_invalid_controls(); 4901 report_prefix_pop(); 4902 4903 secondary |= CPU_EPT; 4904 setup_dummy_ept(); 4905 report_prefix_pushf("enable-PML enabled, enable-EPT enabled"); 4906 test_vmx_valid_controls(); 4907 report_prefix_pop(); 4908 4909 secondary &= ~CPU_PML; 4910 vmcs_write(CPU_EXEC_CTRL1, secondary); 4911 report_prefix_pushf("enable-PML disabled, enable EPT enabled"); 4912 test_vmx_valid_controls(); 4913 report_prefix_pop(); 4914 4915 test_vmcs_addr_reference(CPU_PML, PMLADDR, "PML address", "PML", 4916 PAGE_SIZE, false, false); 4917 4918 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4919 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4920 } 4921 4922 /* 4923 * If the "activate VMX-preemption timer" VM-execution control is 0, the 4924 * the "save VMX-preemption timer value" VM-exit control must also be 0. 4925 * 4926 * [Intel SDM] 4927 */ 4928 static void test_vmx_preemption_timer(void) 4929 { 4930 u32 saved_pin = vmcs_read(PIN_CONTROLS); 4931 u32 saved_exit = vmcs_read(EXI_CONTROLS); 4932 u32 pin = saved_pin; 4933 u32 exit = saved_exit; 4934 4935 if (!((ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) || 4936 (ctrl_pin_rev.clr & PIN_PREEMPT))) { 4937 report_skip("%s : \"Save-VMX-preemption-timer\" and/or \"Enable-VMX-preemption-timer\" control not supported", __func__); 4938 return; 4939 } 4940 4941 pin |= PIN_PREEMPT; 4942 vmcs_write(PIN_CONTROLS, pin); 4943 exit &= ~EXI_SAVE_PREEMPT; 4944 vmcs_write(EXI_CONTROLS, exit); 4945 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer disabled"); 4946 test_vmx_valid_controls(); 4947 report_prefix_pop(); 4948 4949 exit |= EXI_SAVE_PREEMPT; 4950 vmcs_write(EXI_CONTROLS, exit); 4951 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer enabled"); 4952 test_vmx_valid_controls(); 4953 report_prefix_pop(); 4954 4955 pin &= ~PIN_PREEMPT; 4956 vmcs_write(PIN_CONTROLS, pin); 4957 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer enabled"); 4958 test_vmx_invalid_controls(); 4959 report_prefix_pop(); 4960 4961 exit &= ~EXI_SAVE_PREEMPT; 4962 vmcs_write(EXI_CONTROLS, exit); 4963 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer disabled"); 4964 test_vmx_valid_controls(); 4965 report_prefix_pop(); 4966 4967 vmcs_write(PIN_CONTROLS, saved_pin); 4968 vmcs_write(EXI_CONTROLS, saved_exit); 4969 } 4970 4971 extern unsigned char test_mtf1; 4972 extern unsigned char test_mtf2; 4973 extern unsigned char test_mtf3; 4974 extern unsigned char test_mtf4; 4975 4976 static void test_mtf_guest(void) 4977 { 4978 asm ("vmcall;\n\t" 4979 "out %al, $0x80;\n\t" 4980 "test_mtf1:\n\t" 4981 "vmcall;\n\t" 4982 "out %al, $0x80;\n\t" 4983 "test_mtf2:\n\t" 4984 /* 4985 * Prepare for the 'MOV CR3' test. Attempt to induce a 4986 * general-protection fault by moving a non-canonical address into 4987 * CR3. The 'MOV CR3' instruction does not take an imm64 operand, 4988 * so we must MOV the desired value into a register first. 4989 * 4990 * MOV RAX is done before the VMCALL such that MTF is only enabled 4991 * for the instruction under test. 4992 */ 4993 "mov $0xaaaaaaaaaaaaaaaa, %rax;\n\t" 4994 "vmcall;\n\t" 4995 "mov %rax, %cr3;\n\t" 4996 "test_mtf3:\n\t" 4997 "vmcall;\n\t" 4998 /* 4999 * ICEBP/INT1 instruction. Though the instruction is now 5000 * documented, don't rely on assemblers enumerating the 5001 * instruction. Resort to hand assembly. 5002 */ 5003 ".byte 0xf1;\n\t" 5004 "vmcall;\n\t" 5005 "test_mtf4:\n\t" 5006 "mov $0, %eax;\n\t"); 5007 } 5008 5009 static void test_mtf_gp_handler(struct ex_regs *regs) 5010 { 5011 regs->rip = (unsigned long) &test_mtf3; 5012 } 5013 5014 static void test_mtf_db_handler(struct ex_regs *regs) 5015 { 5016 } 5017 5018 static void enable_mtf(void) 5019 { 5020 u32 ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 5021 5022 vmcs_write(CPU_EXEC_CTRL0, ctrl0 | CPU_MTF); 5023 } 5024 5025 static void disable_mtf(void) 5026 { 5027 u32 ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 5028 5029 vmcs_write(CPU_EXEC_CTRL0, ctrl0 & ~CPU_MTF); 5030 } 5031 5032 static void enable_tf(void) 5033 { 5034 unsigned long rflags = vmcs_read(GUEST_RFLAGS); 5035 5036 vmcs_write(GUEST_RFLAGS, rflags | X86_EFLAGS_TF); 5037 } 5038 5039 static void disable_tf(void) 5040 { 5041 unsigned long rflags = vmcs_read(GUEST_RFLAGS); 5042 5043 vmcs_write(GUEST_RFLAGS, rflags & ~X86_EFLAGS_TF); 5044 } 5045 5046 static void report_mtf(const char *insn_name, unsigned long exp_rip) 5047 { 5048 unsigned long rip = vmcs_read(GUEST_RIP); 5049 5050 assert_exit_reason(VMX_MTF); 5051 report(rip == exp_rip, "MTF VM-exit after %s. RIP: 0x%lx (expected 0x%lx)", 5052 insn_name, rip, exp_rip); 5053 } 5054 5055 static void vmx_mtf_test(void) 5056 { 5057 unsigned long pending_dbg; 5058 handler old_gp, old_db; 5059 5060 if (!(ctrl_cpu_rev[0].clr & CPU_MTF)) { 5061 report_skip("%s : \"Monitor trap flag\" exec control not supported", __func__); 5062 return; 5063 } 5064 5065 test_set_guest(test_mtf_guest); 5066 5067 /* Expect an MTF VM-exit after OUT instruction */ 5068 enter_guest(); 5069 skip_exit_vmcall(); 5070 5071 enable_mtf(); 5072 enter_guest(); 5073 report_mtf("OUT", (unsigned long) &test_mtf1); 5074 disable_mtf(); 5075 5076 /* 5077 * Concurrent #DB trap and MTF on instruction boundary. Expect MTF 5078 * VM-exit with populated 'pending debug exceptions' VMCS field. 5079 */ 5080 enter_guest(); 5081 skip_exit_vmcall(); 5082 5083 enable_mtf(); 5084 enable_tf(); 5085 5086 enter_guest(); 5087 report_mtf("OUT", (unsigned long) &test_mtf2); 5088 pending_dbg = vmcs_read(GUEST_PENDING_DEBUG); 5089 report(pending_dbg & DR6_BS, 5090 "'pending debug exceptions' field after MTF VM-exit: 0x%lx (expected 0x%lx)", 5091 pending_dbg, (unsigned long) DR6_BS); 5092 5093 disable_mtf(); 5094 disable_tf(); 5095 vmcs_write(GUEST_PENDING_DEBUG, 0); 5096 5097 /* 5098 * #GP exception takes priority over MTF. Expect MTF VM-exit with RIP 5099 * advanced to first instruction of #GP handler. 5100 */ 5101 enter_guest(); 5102 skip_exit_vmcall(); 5103 5104 old_gp = handle_exception(GP_VECTOR, test_mtf_gp_handler); 5105 5106 enable_mtf(); 5107 enter_guest(); 5108 report_mtf("MOV CR3", (unsigned long) get_idt_addr(&boot_idt[GP_VECTOR])); 5109 disable_mtf(); 5110 5111 /* 5112 * Concurrent MTF and privileged software exception (i.e. ICEBP/INT1). 5113 * MTF should follow the delivery of #DB trap, though the SDM doesn't 5114 * provide clear indication of the relative priority. 5115 */ 5116 enter_guest(); 5117 skip_exit_vmcall(); 5118 5119 handle_exception(GP_VECTOR, old_gp); 5120 old_db = handle_exception(DB_VECTOR, test_mtf_db_handler); 5121 5122 enable_mtf(); 5123 enter_guest(); 5124 report_mtf("INT1", (unsigned long) get_idt_addr(&boot_idt[DB_VECTOR])); 5125 disable_mtf(); 5126 5127 enter_guest(); 5128 skip_exit_vmcall(); 5129 handle_exception(DB_VECTOR, old_db); 5130 vmcs_write(ENT_INTR_INFO, INTR_INFO_VALID_MASK | INTR_TYPE_OTHER_EVENT); 5131 enter_guest(); 5132 report_mtf("injected MTF", (unsigned long) &test_mtf4); 5133 enter_guest(); 5134 } 5135 5136 extern char vmx_mtf_pdpte_guest_begin; 5137 extern char vmx_mtf_pdpte_guest_end; 5138 5139 asm("vmx_mtf_pdpte_guest_begin:\n\t" 5140 "mov %cr0, %rax\n\t" /* save CR0 with PG=1 */ 5141 "vmcall\n\t" /* on return from this CR0.PG=0 */ 5142 "mov %rax, %cr0\n\t" /* restore CR0.PG=1 to enter PAE mode */ 5143 "vmcall\n\t" 5144 "retq\n\t" 5145 "vmx_mtf_pdpte_guest_end:"); 5146 5147 static void vmx_mtf_pdpte_test(void) 5148 { 5149 void *test_mtf_pdpte_guest; 5150 pteval_t *pdpt; 5151 u32 guest_ar_cs; 5152 u64 guest_efer; 5153 pteval_t *pte; 5154 u64 guest_cr0; 5155 u64 guest_cr3; 5156 u64 guest_cr4; 5157 u64 ent_ctls; 5158 int i; 5159 5160 if (setup_ept(false)) 5161 return; 5162 5163 if (!(ctrl_cpu_rev[0].clr & CPU_MTF)) { 5164 report_skip("%s : \"Monitor trap flag\" exec control not supported", __func__); 5165 return; 5166 } 5167 5168 if (!(ctrl_cpu_rev[1].clr & CPU_URG)) { 5169 report_skip("%s : \"Unrestricted guest\" exec control not supported", __func__); 5170 return; 5171 } 5172 5173 vmcs_write(EXC_BITMAP, ~0); 5174 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | CPU_URG); 5175 5176 /* 5177 * Copy the guest code to an identity-mapped page. 5178 */ 5179 test_mtf_pdpte_guest = alloc_page(); 5180 memcpy(test_mtf_pdpte_guest, &vmx_mtf_pdpte_guest_begin, 5181 &vmx_mtf_pdpte_guest_end - &vmx_mtf_pdpte_guest_begin); 5182 5183 test_set_guest(test_mtf_pdpte_guest); 5184 5185 enter_guest(); 5186 skip_exit_vmcall(); 5187 5188 /* 5189 * Put the guest in non-paged 32-bit protected mode, ready to enter 5190 * PAE mode when CR0.PG is set. CR4.PAE will already have been set 5191 * when the guest started out in long mode. 5192 */ 5193 ent_ctls = vmcs_read(ENT_CONTROLS); 5194 vmcs_write(ENT_CONTROLS, ent_ctls & ~ENT_GUEST_64); 5195 5196 guest_efer = vmcs_read(GUEST_EFER); 5197 vmcs_write(GUEST_EFER, guest_efer & ~(EFER_LMA | EFER_LME)); 5198 5199 /* 5200 * Set CS access rights bits for 32-bit protected mode: 5201 * 3:0 B execute/read/accessed 5202 * 4 1 code or data 5203 * 6:5 0 descriptor privilege level 5204 * 7 1 present 5205 * 11:8 0 reserved 5206 * 12 0 available for use by system software 5207 * 13 0 64 bit mode not active 5208 * 14 1 default operation size 32-bit segment 5209 * 15 1 page granularity: segment limit in 4K units 5210 * 16 0 segment usable 5211 * 31:17 0 reserved 5212 */ 5213 guest_ar_cs = vmcs_read(GUEST_AR_CS); 5214 vmcs_write(GUEST_AR_CS, 0xc09b); 5215 5216 guest_cr0 = vmcs_read(GUEST_CR0); 5217 vmcs_write(GUEST_CR0, guest_cr0 & ~X86_CR0_PG); 5218 5219 guest_cr4 = vmcs_read(GUEST_CR4); 5220 vmcs_write(GUEST_CR4, guest_cr4 & ~X86_CR4_PCIDE); 5221 5222 guest_cr3 = vmcs_read(GUEST_CR3); 5223 5224 /* 5225 * Turn the 4-level page table into a PAE page table by following the 0th 5226 * PML4 entry to a PDPT page, and grab the first four PDPTEs from that 5227 * page. 5228 * 5229 * Why does this work? 5230 * 5231 * PAE uses 32-bit addressing which implies: 5232 * Bits 11:0 page offset 5233 * Bits 20:12 entry into 512-entry page table 5234 * Bits 29:21 entry into a 512-entry directory table 5235 * Bits 31:30 entry into the page directory pointer table. 5236 * Bits 63:32 zero 5237 * 5238 * As only 2 bits are needed to select the PDPTEs for the entire 5239 * 32-bit address space, take the first 4 PDPTEs in the level 3 page 5240 * directory pointer table. It doesn't matter which of these PDPTEs 5241 * are present because they must cover the guest code given that it 5242 * has already run successfully. 5243 * 5244 * Get a pointer to PTE for GVA=0 in the page directory pointer table 5245 */ 5246 pte = get_pte_level( 5247 (pgd_t *)phys_to_virt(guest_cr3 & ~X86_CR3_PCID_MASK), 0, 5248 PDPT_LEVEL); 5249 5250 /* 5251 * Need some memory for the 4-entry PAE page directory pointer 5252 * table. Use the end of the identity-mapped page where the guest code 5253 * is stored. There is definitely space as the guest code is only a 5254 * few bytes. 5255 */ 5256 pdpt = test_mtf_pdpte_guest + PAGE_SIZE - 4 * sizeof(pteval_t); 5257 5258 /* 5259 * Copy the first four PDPTEs into the PAE page table with reserved 5260 * bits cleared. Note that permission bits from the PML4E and PDPTE 5261 * are not propagated. 5262 */ 5263 for (i = 0; i < 4; i++) { 5264 TEST_ASSERT_EQ_MSG(0, (pte[i] & PDPTE64_RSVD_MASK), 5265 "PDPTE has invalid reserved bits"); 5266 TEST_ASSERT_EQ_MSG(0, (pte[i] & PDPTE64_PAGE_SIZE_MASK), 5267 "Cannot use 1GB super pages for PAE"); 5268 pdpt[i] = pte[i] & ~(PAE_PDPTE_RSVD_MASK); 5269 } 5270 vmcs_write(GUEST_CR3, virt_to_phys(pdpt)); 5271 5272 enable_mtf(); 5273 enter_guest(); 5274 assert_exit_reason(VMX_MTF); 5275 disable_mtf(); 5276 5277 /* 5278 * The four PDPTEs should have been loaded into the VMCS when 5279 * the guest set CR0.PG to enter PAE mode. 5280 */ 5281 for (i = 0; i < 4; i++) { 5282 u64 pdpte = vmcs_read(GUEST_PDPTE + 2 * i); 5283 5284 report(pdpte == pdpt[i], "PDPTE%d is 0x%lx (expected 0x%lx)", 5285 i, pdpte, pdpt[i]); 5286 } 5287 5288 /* 5289 * Now, try to enter the guest in PAE mode. If the PDPTEs in the 5290 * vmcs are wrong, this will fail. 5291 */ 5292 enter_guest(); 5293 skip_exit_vmcall(); 5294 5295 /* 5296 * Return guest to 64-bit mode and wrap up. 5297 */ 5298 vmcs_write(ENT_CONTROLS, ent_ctls); 5299 vmcs_write(GUEST_EFER, guest_efer); 5300 vmcs_write(GUEST_AR_CS, guest_ar_cs); 5301 vmcs_write(GUEST_CR0, guest_cr0); 5302 vmcs_write(GUEST_CR4, guest_cr4); 5303 vmcs_write(GUEST_CR3, guest_cr3); 5304 5305 enter_guest(); 5306 } 5307 5308 /* 5309 * Tests for VM-execution control fields 5310 */ 5311 static void test_vm_execution_ctls(void) 5312 { 5313 test_pin_based_ctls(); 5314 test_primary_processor_based_ctls(); 5315 test_secondary_processor_based_ctls(); 5316 test_cr3_targets(); 5317 test_io_bitmaps(); 5318 test_msr_bitmap(); 5319 test_apic_ctls(); 5320 test_tpr_threshold(); 5321 test_nmi_ctrls(); 5322 test_pml(); 5323 test_vpid(); 5324 test_ept_eptp(); 5325 test_vmx_preemption_timer(); 5326 } 5327 5328 /* 5329 * The following checks are performed for the VM-entry MSR-load address if 5330 * the VM-entry MSR-load count field is non-zero: 5331 * 5332 * - The lower 4 bits of the VM-entry MSR-load address must be 0. 5333 * The address should not set any bits beyond the processor's 5334 * physical-address width. 5335 * 5336 * - The address of the last byte in the VM-entry MSR-load area 5337 * should not set any bits beyond the processor's physical-address 5338 * width. The address of this last byte is VM-entry MSR-load address 5339 * + (MSR count * 16) - 1. (The arithmetic used for the computation 5340 * uses more bits than the processor's physical-address width.) 5341 * 5342 * 5343 * [Intel SDM] 5344 */ 5345 static void test_entry_msr_load(void) 5346 { 5347 entry_msr_load = alloc_page(); 5348 u64 tmp; 5349 u32 entry_msr_ld_cnt = 1; 5350 int i; 5351 u32 addr_len = 64; 5352 5353 vmcs_write(ENT_MSR_LD_CNT, entry_msr_ld_cnt); 5354 5355 /* Check first 4 bits of VM-entry MSR-load address */ 5356 for (i = 0; i < 4; i++) { 5357 tmp = (u64)entry_msr_load | 1ull << i; 5358 vmcs_write(ENTER_MSR_LD_ADDR, tmp); 5359 report_prefix_pushf("VM-entry MSR-load addr [4:0] %lx", 5360 tmp & 0xf); 5361 test_vmx_invalid_controls(); 5362 report_prefix_pop(); 5363 } 5364 5365 if (basic.val & (1ul << 48)) 5366 addr_len = 32; 5367 5368 test_vmcs_addr_values("VM-entry-MSR-load address", 5369 ENTER_MSR_LD_ADDR, 16, false, false, 5370 4, addr_len - 1); 5371 5372 /* 5373 * Check last byte of VM-entry MSR-load address 5374 */ 5375 entry_msr_load = (struct vmx_msr_entry *)((u64)entry_msr_load & ~0xf); 5376 5377 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 5378 i < 64; i++) { 5379 tmp = ((u64)entry_msr_load + entry_msr_ld_cnt * 16 - 1) | 5380 1ul << i; 5381 vmcs_write(ENTER_MSR_LD_ADDR, 5382 tmp - (entry_msr_ld_cnt * 16 - 1)); 5383 test_vmx_invalid_controls(); 5384 } 5385 5386 vmcs_write(ENT_MSR_LD_CNT, 2); 5387 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 5388 test_vmx_invalid_controls(); 5389 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 5390 test_vmx_valid_controls(); 5391 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 5392 test_vmx_valid_controls(); 5393 } 5394 5395 static struct vmx_state_area_test_data { 5396 u32 msr; 5397 u64 exp; 5398 bool enabled; 5399 } vmx_state_area_test_data; 5400 5401 static void guest_state_test_main(void) 5402 { 5403 u64 obs; 5404 struct vmx_state_area_test_data *data = &vmx_state_area_test_data; 5405 5406 while (1) { 5407 if (vmx_get_test_stage() == 2) 5408 break; 5409 5410 if (data->enabled) { 5411 obs = rdmsr(data->msr); 5412 report(data->exp == obs, 5413 "Guest state is 0x%lx (expected 0x%lx)", 5414 obs, data->exp); 5415 } 5416 5417 vmcall(); 5418 } 5419 5420 asm volatile("fnop"); 5421 } 5422 5423 static void test_guest_state(const char *test, bool xfail, u64 field, 5424 const char * field_name) 5425 { 5426 struct vmentry_result result; 5427 u8 abort_flags; 5428 5429 abort_flags = ABORT_ON_EARLY_VMENTRY_FAIL; 5430 if (!xfail) 5431 abort_flags = ABORT_ON_INVALID_GUEST_STATE; 5432 5433 __enter_guest(abort_flags, &result); 5434 5435 report(result.exit_reason.failed_vmentry == xfail && 5436 ((xfail && result.exit_reason.basic == VMX_FAIL_STATE) || 5437 (!xfail && result.exit_reason.basic == VMX_VMCALL)) && 5438 (!xfail || vmcs_read(EXI_QUALIFICATION) == ENTRY_FAIL_DEFAULT), 5439 "%s, %s = %lx", test, field_name, field); 5440 5441 if (!result.exit_reason.failed_vmentry) 5442 skip_exit_insn(); 5443 } 5444 5445 /* 5446 * Tests for VM-entry control fields 5447 */ 5448 static void test_vm_entry_ctls(void) 5449 { 5450 test_invalid_event_injection(); 5451 test_entry_msr_load(); 5452 } 5453 5454 /* 5455 * The following checks are performed for the VM-exit MSR-store address if 5456 * the VM-exit MSR-store count field is non-zero: 5457 * 5458 * - The lower 4 bits of the VM-exit MSR-store address must be 0. 5459 * The address should not set any bits beyond the processor's 5460 * physical-address width. 5461 * 5462 * - The address of the last byte in the VM-exit MSR-store area 5463 * should not set any bits beyond the processor's physical-address 5464 * width. The address of this last byte is VM-exit MSR-store address 5465 * + (MSR count * 16) - 1. (The arithmetic used for the computation 5466 * uses more bits than the processor's physical-address width.) 5467 * 5468 * If IA32_VMX_BASIC[48] is read as 1, neither address should set any bits 5469 * in the range 63:32. 5470 * 5471 * [Intel SDM] 5472 */ 5473 static void test_exit_msr_store(void) 5474 { 5475 exit_msr_store = alloc_page(); 5476 u64 tmp; 5477 u32 exit_msr_st_cnt = 1; 5478 int i; 5479 u32 addr_len = 64; 5480 5481 vmcs_write(EXI_MSR_ST_CNT, exit_msr_st_cnt); 5482 5483 /* Check first 4 bits of VM-exit MSR-store address */ 5484 for (i = 0; i < 4; i++) { 5485 tmp = (u64)exit_msr_store | 1ull << i; 5486 vmcs_write(EXIT_MSR_ST_ADDR, tmp); 5487 report_prefix_pushf("VM-exit MSR-store addr [4:0] %lx", 5488 tmp & 0xf); 5489 test_vmx_invalid_controls(); 5490 report_prefix_pop(); 5491 } 5492 5493 if (basic.val & (1ul << 48)) 5494 addr_len = 32; 5495 5496 test_vmcs_addr_values("VM-exit-MSR-store address", 5497 EXIT_MSR_ST_ADDR, 16, false, false, 5498 4, addr_len - 1); 5499 5500 /* 5501 * Check last byte of VM-exit MSR-store address 5502 */ 5503 exit_msr_store = (struct vmx_msr_entry *)((u64)exit_msr_store & ~0xf); 5504 5505 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 5506 i < 64; i++) { 5507 tmp = ((u64)exit_msr_store + exit_msr_st_cnt * 16 - 1) | 5508 1ul << i; 5509 vmcs_write(EXIT_MSR_ST_ADDR, 5510 tmp - (exit_msr_st_cnt * 16 - 1)); 5511 test_vmx_invalid_controls(); 5512 } 5513 5514 vmcs_write(EXI_MSR_ST_CNT, 2); 5515 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 5516 test_vmx_invalid_controls(); 5517 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 5518 test_vmx_valid_controls(); 5519 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 5520 test_vmx_valid_controls(); 5521 } 5522 5523 /* 5524 * Tests for VM-exit controls 5525 */ 5526 static void test_vm_exit_ctls(void) 5527 { 5528 test_exit_msr_store(); 5529 } 5530 5531 /* 5532 * Check that the virtual CPU checks all of the VMX controls as 5533 * documented in the Intel SDM. 5534 */ 5535 static void vmx_controls_test(void) 5536 { 5537 /* 5538 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 5539 * fail due to invalid guest state, should we make it that 5540 * far. 5541 */ 5542 vmcs_write(GUEST_RFLAGS, 0); 5543 5544 test_vm_execution_ctls(); 5545 test_vm_exit_ctls(); 5546 test_vm_entry_ctls(); 5547 } 5548 5549 struct apic_reg_virt_config { 5550 bool apic_register_virtualization; 5551 bool use_tpr_shadow; 5552 bool virtualize_apic_accesses; 5553 bool virtualize_x2apic_mode; 5554 bool activate_secondary_controls; 5555 }; 5556 5557 struct apic_reg_test { 5558 const char *name; 5559 struct apic_reg_virt_config apic_reg_virt_config; 5560 }; 5561 5562 struct apic_reg_virt_expectation { 5563 enum Reason rd_exit_reason; 5564 enum Reason wr_exit_reason; 5565 u32 val; 5566 u32 (*virt_fn)(u32); 5567 5568 /* 5569 * If false, accessing the APIC access address from L2 is treated as a 5570 * normal memory operation, rather than triggering virtualization. 5571 */ 5572 bool virtualize_apic_accesses; 5573 }; 5574 5575 static u32 apic_virt_identity(u32 val) 5576 { 5577 return val; 5578 } 5579 5580 static u32 apic_virt_nibble1(u32 val) 5581 { 5582 return val & 0xf0; 5583 } 5584 5585 static u32 apic_virt_byte3(u32 val) 5586 { 5587 return val & (0xff << 24); 5588 } 5589 5590 static bool apic_reg_virt_exit_expectation( 5591 u32 reg, struct apic_reg_virt_config *config, 5592 struct apic_reg_virt_expectation *expectation) 5593 { 5594 /* Good configs, where some L2 APIC accesses are virtualized. */ 5595 bool virtualize_apic_accesses_only = 5596 config->virtualize_apic_accesses && 5597 !config->use_tpr_shadow && 5598 !config->apic_register_virtualization && 5599 !config->virtualize_x2apic_mode && 5600 config->activate_secondary_controls; 5601 bool virtualize_apic_accesses_and_use_tpr_shadow = 5602 config->virtualize_apic_accesses && 5603 config->use_tpr_shadow && 5604 !config->apic_register_virtualization && 5605 !config->virtualize_x2apic_mode && 5606 config->activate_secondary_controls; 5607 bool apic_register_virtualization = 5608 config->virtualize_apic_accesses && 5609 config->use_tpr_shadow && 5610 config->apic_register_virtualization && 5611 !config->virtualize_x2apic_mode && 5612 config->activate_secondary_controls; 5613 5614 expectation->val = MAGIC_VAL_1; 5615 expectation->virt_fn = apic_virt_identity; 5616 expectation->virtualize_apic_accesses = 5617 config->virtualize_apic_accesses && 5618 config->activate_secondary_controls; 5619 if (virtualize_apic_accesses_only) { 5620 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5621 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5622 } else if (virtualize_apic_accesses_and_use_tpr_shadow) { 5623 switch (reg) { 5624 case APIC_TASKPRI: 5625 expectation->rd_exit_reason = VMX_VMCALL; 5626 expectation->wr_exit_reason = VMX_VMCALL; 5627 expectation->virt_fn = apic_virt_nibble1; 5628 break; 5629 default: 5630 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5631 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5632 } 5633 } else if (apic_register_virtualization) { 5634 expectation->rd_exit_reason = VMX_VMCALL; 5635 5636 switch (reg) { 5637 case APIC_ID: 5638 case APIC_EOI: 5639 case APIC_LDR: 5640 case APIC_DFR: 5641 case APIC_SPIV: 5642 case APIC_ESR: 5643 case APIC_ICR: 5644 case APIC_LVTT: 5645 case APIC_LVTTHMR: 5646 case APIC_LVTPC: 5647 case APIC_LVT0: 5648 case APIC_LVT1: 5649 case APIC_LVTERR: 5650 case APIC_TMICT: 5651 case APIC_TDCR: 5652 expectation->wr_exit_reason = VMX_APIC_WRITE; 5653 break; 5654 case APIC_LVR: 5655 case APIC_ISR ... APIC_ISR + 0x70: 5656 case APIC_TMR ... APIC_TMR + 0x70: 5657 case APIC_IRR ... APIC_IRR + 0x70: 5658 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5659 break; 5660 case APIC_TASKPRI: 5661 expectation->wr_exit_reason = VMX_VMCALL; 5662 expectation->virt_fn = apic_virt_nibble1; 5663 break; 5664 case APIC_ICR2: 5665 expectation->wr_exit_reason = VMX_VMCALL; 5666 expectation->virt_fn = apic_virt_byte3; 5667 break; 5668 default: 5669 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5670 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5671 } 5672 } else if (!expectation->virtualize_apic_accesses) { 5673 /* 5674 * No APIC registers are directly virtualized. This includes 5675 * VTPR, which can be virtualized through MOV to/from CR8 via 5676 * the use TPR shadow control, but not through directly 5677 * accessing VTPR. 5678 */ 5679 expectation->rd_exit_reason = VMX_VMCALL; 5680 expectation->wr_exit_reason = VMX_VMCALL; 5681 } else { 5682 printf("Cannot parse APIC register virtualization config:\n" 5683 "\tvirtualize_apic_accesses: %d\n" 5684 "\tuse_tpr_shadow: %d\n" 5685 "\tapic_register_virtualization: %d\n" 5686 "\tvirtualize_x2apic_mode: %d\n" 5687 "\tactivate_secondary_controls: %d\n", 5688 config->virtualize_apic_accesses, 5689 config->use_tpr_shadow, 5690 config->apic_register_virtualization, 5691 config->virtualize_x2apic_mode, 5692 config->activate_secondary_controls); 5693 5694 return false; 5695 } 5696 5697 return true; 5698 } 5699 5700 struct apic_reg_test apic_reg_tests[] = { 5701 /* Good configs, where some L2 APIC accesses are virtualized. */ 5702 { 5703 .name = "Virtualize APIC accesses", 5704 .apic_reg_virt_config = { 5705 .virtualize_apic_accesses = true, 5706 .use_tpr_shadow = false, 5707 .apic_register_virtualization = false, 5708 .virtualize_x2apic_mode = false, 5709 .activate_secondary_controls = true, 5710 }, 5711 }, 5712 { 5713 .name = "Virtualize APIC accesses + Use TPR shadow", 5714 .apic_reg_virt_config = { 5715 .virtualize_apic_accesses = true, 5716 .use_tpr_shadow = true, 5717 .apic_register_virtualization = false, 5718 .virtualize_x2apic_mode = false, 5719 .activate_secondary_controls = true, 5720 }, 5721 }, 5722 { 5723 .name = "APIC-register virtualization", 5724 .apic_reg_virt_config = { 5725 .virtualize_apic_accesses = true, 5726 .use_tpr_shadow = true, 5727 .apic_register_virtualization = true, 5728 .virtualize_x2apic_mode = false, 5729 .activate_secondary_controls = true, 5730 }, 5731 }, 5732 5733 /* 5734 * Test that the secondary processor-based VM-execution controls are 5735 * correctly ignored when "activate secondary controls" is disabled. 5736 */ 5737 { 5738 .name = "Activate secondary controls off", 5739 .apic_reg_virt_config = { 5740 .virtualize_apic_accesses = true, 5741 .use_tpr_shadow = false, 5742 .apic_register_virtualization = true, 5743 .virtualize_x2apic_mode = true, 5744 .activate_secondary_controls = false, 5745 }, 5746 }, 5747 { 5748 .name = "Activate secondary controls off + Use TPR shadow", 5749 .apic_reg_virt_config = { 5750 .virtualize_apic_accesses = true, 5751 .use_tpr_shadow = true, 5752 .apic_register_virtualization = true, 5753 .virtualize_x2apic_mode = true, 5754 .activate_secondary_controls = false, 5755 }, 5756 }, 5757 5758 /* 5759 * Test that the APIC access address is treated like an arbitrary memory 5760 * address when "virtualize APIC accesses" is disabled. 5761 */ 5762 { 5763 .name = "Virtualize APIC accesses off + Use TPR shadow", 5764 .apic_reg_virt_config = { 5765 .virtualize_apic_accesses = false, 5766 .use_tpr_shadow = true, 5767 .apic_register_virtualization = true, 5768 .virtualize_x2apic_mode = true, 5769 .activate_secondary_controls = true, 5770 }, 5771 }, 5772 5773 /* 5774 * Test that VM entry fails due to invalid controls when 5775 * "APIC-register virtualization" is enabled while "use TPR shadow" is 5776 * disabled. 5777 */ 5778 { 5779 .name = "APIC-register virtualization + Use TPR shadow off", 5780 .apic_reg_virt_config = { 5781 .virtualize_apic_accesses = true, 5782 .use_tpr_shadow = false, 5783 .apic_register_virtualization = true, 5784 .virtualize_x2apic_mode = false, 5785 .activate_secondary_controls = true, 5786 }, 5787 }, 5788 5789 /* 5790 * Test that VM entry fails due to invalid controls when 5791 * "Virtualize x2APIC mode" is enabled while "use TPR shadow" is 5792 * disabled. 5793 */ 5794 { 5795 .name = "Virtualize x2APIC mode + Use TPR shadow off", 5796 .apic_reg_virt_config = { 5797 .virtualize_apic_accesses = false, 5798 .use_tpr_shadow = false, 5799 .apic_register_virtualization = false, 5800 .virtualize_x2apic_mode = true, 5801 .activate_secondary_controls = true, 5802 }, 5803 }, 5804 { 5805 .name = "Virtualize x2APIC mode + Use TPR shadow off v2", 5806 .apic_reg_virt_config = { 5807 .virtualize_apic_accesses = false, 5808 .use_tpr_shadow = false, 5809 .apic_register_virtualization = true, 5810 .virtualize_x2apic_mode = true, 5811 .activate_secondary_controls = true, 5812 }, 5813 }, 5814 5815 /* 5816 * Test that VM entry fails due to invalid controls when 5817 * "virtualize x2APIC mode" is enabled while "virtualize APIC accesses" 5818 * is enabled. 5819 */ 5820 { 5821 .name = "Virtualize x2APIC mode + Virtualize APIC accesses", 5822 .apic_reg_virt_config = { 5823 .virtualize_apic_accesses = true, 5824 .use_tpr_shadow = true, 5825 .apic_register_virtualization = false, 5826 .virtualize_x2apic_mode = true, 5827 .activate_secondary_controls = true, 5828 }, 5829 }, 5830 { 5831 .name = "Virtualize x2APIC mode + Virtualize APIC accesses v2", 5832 .apic_reg_virt_config = { 5833 .virtualize_apic_accesses = true, 5834 .use_tpr_shadow = true, 5835 .apic_register_virtualization = true, 5836 .virtualize_x2apic_mode = true, 5837 .activate_secondary_controls = true, 5838 }, 5839 }, 5840 }; 5841 5842 enum Apic_op { 5843 APIC_OP_XAPIC_RD, 5844 APIC_OP_XAPIC_WR, 5845 TERMINATE, 5846 }; 5847 5848 static u32 vmx_xapic_read(u32 *apic_access_address, u32 reg) 5849 { 5850 return *(volatile u32 *)((uintptr_t)apic_access_address + reg); 5851 } 5852 5853 static void vmx_xapic_write(u32 *apic_access_address, u32 reg, u32 val) 5854 { 5855 *(volatile u32 *)((uintptr_t)apic_access_address + reg) = val; 5856 } 5857 5858 struct apic_reg_virt_guest_args { 5859 enum Apic_op op; 5860 u32 *apic_access_address; 5861 u32 reg; 5862 u32 val; 5863 bool check_rd; 5864 u32 (*virt_fn)(u32); 5865 } apic_reg_virt_guest_args; 5866 5867 static void apic_reg_virt_guest(void) 5868 { 5869 volatile struct apic_reg_virt_guest_args *args = 5870 &apic_reg_virt_guest_args; 5871 5872 for (;;) { 5873 enum Apic_op op = args->op; 5874 u32 *apic_access_address = args->apic_access_address; 5875 u32 reg = args->reg; 5876 u32 val = args->val; 5877 bool check_rd = args->check_rd; 5878 u32 (*virt_fn)(u32) = args->virt_fn; 5879 5880 if (op == TERMINATE) 5881 break; 5882 5883 if (op == APIC_OP_XAPIC_RD) { 5884 u32 ret = vmx_xapic_read(apic_access_address, reg); 5885 5886 if (check_rd) { 5887 u32 want = virt_fn(val); 5888 u32 got = virt_fn(ret); 5889 5890 report(got == want, 5891 "read 0x%x, expected 0x%x.", got, want); 5892 } 5893 } else if (op == APIC_OP_XAPIC_WR) { 5894 vmx_xapic_write(apic_access_address, reg, val); 5895 } 5896 5897 /* 5898 * The L1 should always execute a vmcall after it's done testing 5899 * an individual APIC operation. This helps to validate that the 5900 * L1 and L2 are in sync with each other, as expected. 5901 */ 5902 vmcall(); 5903 } 5904 } 5905 5906 static void test_xapic_rd( 5907 u32 reg, struct apic_reg_virt_expectation *expectation, 5908 u32 *apic_access_address, u32 *virtual_apic_page) 5909 { 5910 u32 val = expectation->val; 5911 u32 exit_reason_want = expectation->rd_exit_reason; 5912 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 5913 5914 report_prefix_pushf("xapic - reading 0x%03x", reg); 5915 5916 /* Configure guest to do an xapic read */ 5917 args->op = APIC_OP_XAPIC_RD; 5918 args->apic_access_address = apic_access_address; 5919 args->reg = reg; 5920 args->val = val; 5921 args->check_rd = exit_reason_want == VMX_VMCALL; 5922 args->virt_fn = expectation->virt_fn; 5923 5924 /* Setup virtual APIC page */ 5925 if (!expectation->virtualize_apic_accesses) { 5926 apic_access_address[apic_reg_index(reg)] = val; 5927 virtual_apic_page[apic_reg_index(reg)] = 0; 5928 } else if (exit_reason_want == VMX_VMCALL) { 5929 apic_access_address[apic_reg_index(reg)] = 0; 5930 virtual_apic_page[apic_reg_index(reg)] = val; 5931 } 5932 5933 /* Enter guest */ 5934 enter_guest(); 5935 5936 /* 5937 * Validate the behavior and 5938 * pass a magic value back to the guest. 5939 */ 5940 if (exit_reason_want == VMX_APIC_ACCESS) { 5941 u32 apic_page_offset = vmcs_read(EXI_QUALIFICATION) & 0xfff; 5942 5943 assert_exit_reason(exit_reason_want); 5944 report(apic_page_offset == reg, 5945 "got APIC access exit @ page offset 0x%03x, want 0x%03x", 5946 apic_page_offset, reg); 5947 skip_exit_insn(); 5948 5949 /* Reenter guest so it can consume/check rcx and exit again. */ 5950 enter_guest(); 5951 } else if (exit_reason_want != VMX_VMCALL) { 5952 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 5953 } 5954 5955 skip_exit_vmcall(); 5956 report_prefix_pop(); 5957 } 5958 5959 static void test_xapic_wr( 5960 u32 reg, struct apic_reg_virt_expectation *expectation, 5961 u32 *apic_access_address, u32 *virtual_apic_page) 5962 { 5963 u32 val = expectation->val; 5964 u32 exit_reason_want = expectation->wr_exit_reason; 5965 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 5966 bool virtualized = 5967 expectation->virtualize_apic_accesses && 5968 (exit_reason_want == VMX_APIC_WRITE || 5969 exit_reason_want == VMX_VMCALL); 5970 bool checked = false; 5971 5972 report_prefix_pushf("xapic - writing 0x%x to 0x%03x", val, reg); 5973 5974 /* Configure guest to do an xapic read */ 5975 args->op = APIC_OP_XAPIC_WR; 5976 args->apic_access_address = apic_access_address; 5977 args->reg = reg; 5978 args->val = val; 5979 5980 /* Setup virtual APIC page */ 5981 if (virtualized || !expectation->virtualize_apic_accesses) { 5982 apic_access_address[apic_reg_index(reg)] = 0; 5983 virtual_apic_page[apic_reg_index(reg)] = 0; 5984 } 5985 5986 /* Enter guest */ 5987 enter_guest(); 5988 5989 /* 5990 * Validate the behavior and 5991 * pass a magic value back to the guest. 5992 */ 5993 if (exit_reason_want == VMX_APIC_ACCESS) { 5994 u32 apic_page_offset = vmcs_read(EXI_QUALIFICATION) & 0xfff; 5995 5996 assert_exit_reason(exit_reason_want); 5997 report(apic_page_offset == reg, 5998 "got APIC access exit @ page offset 0x%03x, want 0x%03x", 5999 apic_page_offset, reg); 6000 skip_exit_insn(); 6001 6002 /* Reenter guest so it can consume/check rcx and exit again. */ 6003 enter_guest(); 6004 } else if (exit_reason_want == VMX_APIC_WRITE) { 6005 assert_exit_reason(exit_reason_want); 6006 report(virtual_apic_page[apic_reg_index(reg)] == val, 6007 "got APIC write exit @ page offset 0x%03x; val is 0x%x, want 0x%x", 6008 apic_reg_index(reg), 6009 virtual_apic_page[apic_reg_index(reg)], val); 6010 checked = true; 6011 6012 /* Reenter guest so it can consume/check rcx and exit again. */ 6013 enter_guest(); 6014 } else if (exit_reason_want != VMX_VMCALL) { 6015 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 6016 } 6017 6018 assert_exit_reason(VMX_VMCALL); 6019 if (virtualized && !checked) { 6020 u32 want = expectation->virt_fn(val); 6021 u32 got = virtual_apic_page[apic_reg_index(reg)]; 6022 got = expectation->virt_fn(got); 6023 6024 report(got == want, "exitless write; val is 0x%x, want 0x%x", 6025 got, want); 6026 } else if (!expectation->virtualize_apic_accesses && !checked) { 6027 u32 got = apic_access_address[apic_reg_index(reg)]; 6028 6029 report(got == val, 6030 "non-virtualized write; val is 0x%x, want 0x%x", got, 6031 val); 6032 } else if (!expectation->virtualize_apic_accesses && checked) { 6033 report_fail("Non-virtualized write was prematurely checked!"); 6034 } 6035 6036 skip_exit_vmcall(); 6037 report_prefix_pop(); 6038 } 6039 6040 enum Config_type { 6041 CONFIG_TYPE_GOOD, 6042 CONFIG_TYPE_UNSUPPORTED, 6043 CONFIG_TYPE_VMENTRY_FAILS_EARLY, 6044 }; 6045 6046 static enum Config_type configure_apic_reg_virt_test( 6047 struct apic_reg_virt_config *apic_reg_virt_config) 6048 { 6049 u32 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6050 u32 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6051 /* Configs where L2 entry fails early, due to invalid controls. */ 6052 bool use_tpr_shadow_incorrectly_off = 6053 !apic_reg_virt_config->use_tpr_shadow && 6054 (apic_reg_virt_config->apic_register_virtualization || 6055 apic_reg_virt_config->virtualize_x2apic_mode) && 6056 apic_reg_virt_config->activate_secondary_controls; 6057 bool virtualize_apic_accesses_incorrectly_on = 6058 apic_reg_virt_config->virtualize_apic_accesses && 6059 apic_reg_virt_config->virtualize_x2apic_mode && 6060 apic_reg_virt_config->activate_secondary_controls; 6061 bool vmentry_fails_early = 6062 use_tpr_shadow_incorrectly_off || 6063 virtualize_apic_accesses_incorrectly_on; 6064 6065 if (apic_reg_virt_config->activate_secondary_controls) { 6066 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 6067 printf("VM-execution control \"activate secondary controls\" NOT supported.\n"); 6068 return CONFIG_TYPE_UNSUPPORTED; 6069 } 6070 cpu_exec_ctrl0 |= CPU_SECONDARY; 6071 } else { 6072 cpu_exec_ctrl0 &= ~CPU_SECONDARY; 6073 } 6074 6075 if (apic_reg_virt_config->virtualize_apic_accesses) { 6076 if (!(ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES)) { 6077 printf("VM-execution control \"virtualize APIC accesses\" NOT supported.\n"); 6078 return CONFIG_TYPE_UNSUPPORTED; 6079 } 6080 cpu_exec_ctrl1 |= CPU_VIRT_APIC_ACCESSES; 6081 } else { 6082 cpu_exec_ctrl1 &= ~CPU_VIRT_APIC_ACCESSES; 6083 } 6084 6085 if (apic_reg_virt_config->use_tpr_shadow) { 6086 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) { 6087 printf("VM-execution control \"use TPR shadow\" NOT supported.\n"); 6088 return CONFIG_TYPE_UNSUPPORTED; 6089 } 6090 cpu_exec_ctrl0 |= CPU_TPR_SHADOW; 6091 } else { 6092 cpu_exec_ctrl0 &= ~CPU_TPR_SHADOW; 6093 } 6094 6095 if (apic_reg_virt_config->apic_register_virtualization) { 6096 if (!(ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT)) { 6097 printf("VM-execution control \"APIC-register virtualization\" NOT supported.\n"); 6098 return CONFIG_TYPE_UNSUPPORTED; 6099 } 6100 cpu_exec_ctrl1 |= CPU_APIC_REG_VIRT; 6101 } else { 6102 cpu_exec_ctrl1 &= ~CPU_APIC_REG_VIRT; 6103 } 6104 6105 if (apic_reg_virt_config->virtualize_x2apic_mode) { 6106 if (!(ctrl_cpu_rev[1].clr & CPU_VIRT_X2APIC)) { 6107 printf("VM-execution control \"virtualize x2APIC mode\" NOT supported.\n"); 6108 return CONFIG_TYPE_UNSUPPORTED; 6109 } 6110 cpu_exec_ctrl1 |= CPU_VIRT_X2APIC; 6111 } else { 6112 cpu_exec_ctrl1 &= ~CPU_VIRT_X2APIC; 6113 } 6114 6115 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6116 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6117 6118 if (vmentry_fails_early) 6119 return CONFIG_TYPE_VMENTRY_FAILS_EARLY; 6120 6121 return CONFIG_TYPE_GOOD; 6122 } 6123 6124 static bool cpu_has_apicv(void) 6125 { 6126 return ((ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT) && 6127 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 6128 (ctrl_pin_rev.clr & PIN_POST_INTR)); 6129 } 6130 6131 /* Validates APIC register access across valid virtualization configurations. */ 6132 static void apic_reg_virt_test(void) 6133 { 6134 u32 *apic_access_address; 6135 u32 *virtual_apic_page; 6136 u64 control; 6137 u64 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6138 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6139 int i; 6140 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 6141 6142 if (!cpu_has_apicv()) { 6143 report_skip("%s : Not all required APICv bits supported", __func__); 6144 return; 6145 } 6146 6147 control = cpu_exec_ctrl1; 6148 control &= ~CPU_VINTD; 6149 vmcs_write(CPU_EXEC_CTRL1, control); 6150 6151 test_set_guest(apic_reg_virt_guest); 6152 6153 /* 6154 * From the SDM: The 1-setting of the "virtualize APIC accesses" 6155 * VM-execution is guaranteed to apply only if translations to the 6156 * APIC-access address use a 4-KByte page. 6157 */ 6158 apic_access_address = alloc_page(); 6159 force_4k_page(apic_access_address); 6160 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_address)); 6161 6162 virtual_apic_page = alloc_page(); 6163 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 6164 6165 for (i = 0; i < ARRAY_SIZE(apic_reg_tests); i++) { 6166 struct apic_reg_test *apic_reg_test = &apic_reg_tests[i]; 6167 struct apic_reg_virt_config *apic_reg_virt_config = 6168 &apic_reg_test->apic_reg_virt_config; 6169 enum Config_type config_type; 6170 u32 reg; 6171 6172 printf("--- %s test ---\n", apic_reg_test->name); 6173 config_type = 6174 configure_apic_reg_virt_test(apic_reg_virt_config); 6175 if (config_type == CONFIG_TYPE_UNSUPPORTED) { 6176 printf("Skip because of missing features.\n"); 6177 continue; 6178 } 6179 6180 if (config_type == CONFIG_TYPE_VMENTRY_FAILS_EARLY) { 6181 enter_guest_with_bad_controls(); 6182 continue; 6183 } 6184 6185 for (reg = 0; reg < PAGE_SIZE / sizeof(u32); reg += 0x10) { 6186 struct apic_reg_virt_expectation expectation = {}; 6187 bool ok; 6188 6189 ok = apic_reg_virt_exit_expectation( 6190 reg, apic_reg_virt_config, &expectation); 6191 if (!ok) { 6192 report_fail("Malformed test."); 6193 break; 6194 } 6195 6196 test_xapic_rd(reg, &expectation, apic_access_address, 6197 virtual_apic_page); 6198 test_xapic_wr(reg, &expectation, apic_access_address, 6199 virtual_apic_page); 6200 } 6201 } 6202 6203 /* Terminate the guest */ 6204 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6205 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6206 args->op = TERMINATE; 6207 enter_guest(); 6208 assert_exit_reason(VMX_VMCALL); 6209 } 6210 6211 struct virt_x2apic_mode_config { 6212 struct apic_reg_virt_config apic_reg_virt_config; 6213 bool virtual_interrupt_delivery; 6214 bool use_msr_bitmaps; 6215 bool disable_x2apic_msr_intercepts; 6216 bool disable_x2apic; 6217 }; 6218 6219 struct virt_x2apic_mode_test_case { 6220 const char *name; 6221 struct virt_x2apic_mode_config virt_x2apic_mode_config; 6222 }; 6223 6224 enum Virt_x2apic_mode_behavior_type { 6225 X2APIC_ACCESS_VIRTUALIZED, 6226 X2APIC_ACCESS_PASSED_THROUGH, 6227 X2APIC_ACCESS_TRIGGERS_GP, 6228 }; 6229 6230 struct virt_x2apic_mode_expectation { 6231 enum Reason rd_exit_reason; 6232 enum Reason wr_exit_reason; 6233 6234 /* 6235 * RDMSR and WRMSR handle 64-bit values. However, except for ICR, all of 6236 * the x2APIC registers are 32 bits. Notice: 6237 * 1. vmx_x2apic_read() clears the upper 32 bits for 32-bit registers. 6238 * 2. vmx_x2apic_write() expects the val arg to be well-formed. 6239 */ 6240 u64 rd_val; 6241 u64 wr_val; 6242 6243 /* 6244 * Compares input to virtualized output; 6245 * 1st arg is pointer to return expected virtualization output. 6246 */ 6247 u64 (*virt_fn)(u64); 6248 6249 enum Virt_x2apic_mode_behavior_type rd_behavior; 6250 enum Virt_x2apic_mode_behavior_type wr_behavior; 6251 bool wr_only; 6252 }; 6253 6254 static u64 virt_x2apic_mode_identity(u64 val) 6255 { 6256 return val; 6257 } 6258 6259 static u64 virt_x2apic_mode_nibble1(u64 val) 6260 { 6261 return val & 0xf0; 6262 } 6263 6264 static void virt_x2apic_mode_rd_expectation( 6265 u32 reg, bool virt_x2apic_mode_on, bool disable_x2apic, 6266 bool apic_register_virtualization, bool virtual_interrupt_delivery, 6267 struct virt_x2apic_mode_expectation *expectation) 6268 { 6269 bool readable = 6270 !x2apic_reg_reserved(reg) && 6271 reg != APIC_EOI; 6272 6273 expectation->rd_exit_reason = VMX_VMCALL; 6274 expectation->virt_fn = virt_x2apic_mode_identity; 6275 if (virt_x2apic_mode_on && apic_register_virtualization) { 6276 expectation->rd_val = MAGIC_VAL_1; 6277 if (reg == APIC_PROCPRI && virtual_interrupt_delivery) 6278 expectation->virt_fn = virt_x2apic_mode_nibble1; 6279 else if (reg == APIC_TASKPRI) 6280 expectation->virt_fn = virt_x2apic_mode_nibble1; 6281 expectation->rd_behavior = X2APIC_ACCESS_VIRTUALIZED; 6282 } else if (virt_x2apic_mode_on && !apic_register_virtualization && 6283 reg == APIC_TASKPRI) { 6284 expectation->rd_val = MAGIC_VAL_1; 6285 expectation->virt_fn = virt_x2apic_mode_nibble1; 6286 expectation->rd_behavior = X2APIC_ACCESS_VIRTUALIZED; 6287 } else if (!disable_x2apic && readable) { 6288 expectation->rd_val = apic_read(reg); 6289 expectation->rd_behavior = X2APIC_ACCESS_PASSED_THROUGH; 6290 } else { 6291 expectation->rd_behavior = X2APIC_ACCESS_TRIGGERS_GP; 6292 } 6293 } 6294 6295 /* 6296 * get_x2apic_wr_val() creates an innocuous write value for an x2APIC register. 6297 * 6298 * For writable registers, get_x2apic_wr_val() deposits the write value into the 6299 * val pointer arg and returns true. For non-writable registers, val is not 6300 * modified and get_x2apic_wr_val() returns false. 6301 */ 6302 static bool get_x2apic_wr_val(u32 reg, u64 *val) 6303 { 6304 switch (reg) { 6305 case APIC_TASKPRI: 6306 /* Bits 31:8 are reserved. */ 6307 *val &= 0xff; 6308 break; 6309 case APIC_EOI: 6310 case APIC_ESR: 6311 case APIC_TMICT: 6312 /* 6313 * EOI, ESR: WRMSR of a non-zero value causes #GP(0). 6314 * TMICT: A write of 0 to the initial-count register effectively 6315 * stops the local APIC timer, in both one-shot and 6316 * periodic mode. 6317 */ 6318 *val = 0; 6319 break; 6320 case APIC_SPIV: 6321 case APIC_LVTT: 6322 case APIC_LVTTHMR: 6323 case APIC_LVTPC: 6324 case APIC_LVT0: 6325 case APIC_LVT1: 6326 case APIC_LVTERR: 6327 case APIC_TDCR: 6328 /* 6329 * To avoid writing a 1 to a reserved bit or causing some other 6330 * unintended side effect, read the current value and use it as 6331 * the write value. 6332 */ 6333 *val = apic_read(reg); 6334 break; 6335 case APIC_CMCI: 6336 if (!apic_lvt_entry_supported(6)) 6337 return false; 6338 *val = apic_read(reg); 6339 break; 6340 case APIC_ICR: 6341 *val = 0x40000 | 0xf1; 6342 break; 6343 case APIC_SELF_IPI: 6344 /* 6345 * With special processing (i.e., virtualize x2APIC mode + 6346 * virtual interrupt delivery), writing zero causes an 6347 * APIC-write VM exit. We plan to add a test for enabling 6348 * "virtual-interrupt delivery" in VMCS12, and that's where we 6349 * will test a self IPI with special processing. 6350 */ 6351 *val = 0x0; 6352 break; 6353 default: 6354 return false; 6355 } 6356 6357 return true; 6358 } 6359 6360 static bool special_processing_applies(u32 reg, u64 *val, 6361 bool virt_int_delivery) 6362 { 6363 bool special_processing = 6364 (reg == APIC_TASKPRI) || 6365 (virt_int_delivery && 6366 (reg == APIC_EOI || reg == APIC_SELF_IPI)); 6367 6368 if (special_processing) { 6369 TEST_ASSERT(get_x2apic_wr_val(reg, val)); 6370 return true; 6371 } 6372 6373 return false; 6374 } 6375 6376 static void virt_x2apic_mode_wr_expectation( 6377 u32 reg, bool virt_x2apic_mode_on, bool disable_x2apic, 6378 bool virt_int_delivery, 6379 struct virt_x2apic_mode_expectation *expectation) 6380 { 6381 expectation->wr_exit_reason = VMX_VMCALL; 6382 expectation->wr_val = MAGIC_VAL_1; 6383 expectation->wr_only = false; 6384 6385 if (virt_x2apic_mode_on && 6386 special_processing_applies(reg, &expectation->wr_val, 6387 virt_int_delivery)) { 6388 expectation->wr_behavior = X2APIC_ACCESS_VIRTUALIZED; 6389 if (reg == APIC_SELF_IPI) 6390 expectation->wr_exit_reason = VMX_APIC_WRITE; 6391 } else if (!disable_x2apic && 6392 get_x2apic_wr_val(reg, &expectation->wr_val)) { 6393 expectation->wr_behavior = X2APIC_ACCESS_PASSED_THROUGH; 6394 if (reg == APIC_EOI || reg == APIC_SELF_IPI) 6395 expectation->wr_only = true; 6396 if (reg == APIC_ICR) 6397 expectation->wr_exit_reason = VMX_EXTINT; 6398 } else { 6399 expectation->wr_behavior = X2APIC_ACCESS_TRIGGERS_GP; 6400 /* 6401 * Writing 1 to a reserved bit triggers a #GP. 6402 * Thus, set the write value to 0, which seems 6403 * the most likely to detect a missed #GP. 6404 */ 6405 expectation->wr_val = 0; 6406 } 6407 } 6408 6409 static void virt_x2apic_mode_exit_expectation( 6410 u32 reg, struct virt_x2apic_mode_config *config, 6411 struct virt_x2apic_mode_expectation *expectation) 6412 { 6413 struct apic_reg_virt_config *base_config = 6414 &config->apic_reg_virt_config; 6415 bool virt_x2apic_mode_on = 6416 base_config->virtualize_x2apic_mode && 6417 config->use_msr_bitmaps && 6418 config->disable_x2apic_msr_intercepts && 6419 base_config->activate_secondary_controls; 6420 6421 virt_x2apic_mode_wr_expectation( 6422 reg, virt_x2apic_mode_on, config->disable_x2apic, 6423 config->virtual_interrupt_delivery, expectation); 6424 virt_x2apic_mode_rd_expectation( 6425 reg, virt_x2apic_mode_on, config->disable_x2apic, 6426 base_config->apic_register_virtualization, 6427 config->virtual_interrupt_delivery, expectation); 6428 } 6429 6430 struct virt_x2apic_mode_test_case virt_x2apic_mode_tests[] = { 6431 /* 6432 * Baseline "virtualize x2APIC mode" configuration: 6433 * - virtualize x2APIC mode 6434 * - virtual-interrupt delivery 6435 * - APIC-register virtualization 6436 * - x2APIC MSR intercepts disabled 6437 * 6438 * Reads come from virtual APIC page, special processing applies to 6439 * VTPR, EOI, and SELF IPI, and all other writes pass through to L1 6440 * APIC. 6441 */ 6442 { 6443 .name = "Baseline", 6444 .virt_x2apic_mode_config = { 6445 .virtual_interrupt_delivery = true, 6446 .use_msr_bitmaps = true, 6447 .disable_x2apic_msr_intercepts = true, 6448 .disable_x2apic = false, 6449 .apic_reg_virt_config = { 6450 .apic_register_virtualization = true, 6451 .use_tpr_shadow = true, 6452 .virtualize_apic_accesses = false, 6453 .virtualize_x2apic_mode = true, 6454 .activate_secondary_controls = true, 6455 }, 6456 }, 6457 }, 6458 { 6459 .name = "Baseline w/ x2apic disabled", 6460 .virt_x2apic_mode_config = { 6461 .virtual_interrupt_delivery = true, 6462 .use_msr_bitmaps = true, 6463 .disable_x2apic_msr_intercepts = true, 6464 .disable_x2apic = true, 6465 .apic_reg_virt_config = { 6466 .apic_register_virtualization = true, 6467 .use_tpr_shadow = true, 6468 .virtualize_apic_accesses = false, 6469 .virtualize_x2apic_mode = true, 6470 .activate_secondary_controls = true, 6471 }, 6472 }, 6473 }, 6474 6475 /* 6476 * Baseline, minus virtual-interrupt delivery. Reads come from virtual 6477 * APIC page, special processing applies to VTPR, and all other writes 6478 * pass through to L1 APIC. 6479 */ 6480 { 6481 .name = "Baseline - virtual interrupt delivery", 6482 .virt_x2apic_mode_config = { 6483 .virtual_interrupt_delivery = false, 6484 .use_msr_bitmaps = true, 6485 .disable_x2apic_msr_intercepts = true, 6486 .disable_x2apic = false, 6487 .apic_reg_virt_config = { 6488 .apic_register_virtualization = true, 6489 .use_tpr_shadow = true, 6490 .virtualize_apic_accesses = false, 6491 .virtualize_x2apic_mode = true, 6492 .activate_secondary_controls = true, 6493 }, 6494 }, 6495 }, 6496 6497 /* 6498 * Baseline, minus APIC-register virtualization. x2APIC reads pass 6499 * through to L1's APIC, unless reading VTPR 6500 */ 6501 { 6502 .name = "Virtualize x2APIC mode, no APIC reg virt", 6503 .virt_x2apic_mode_config = { 6504 .virtual_interrupt_delivery = true, 6505 .use_msr_bitmaps = true, 6506 .disable_x2apic_msr_intercepts = true, 6507 .disable_x2apic = false, 6508 .apic_reg_virt_config = { 6509 .apic_register_virtualization = false, 6510 .use_tpr_shadow = true, 6511 .virtualize_apic_accesses = false, 6512 .virtualize_x2apic_mode = true, 6513 .activate_secondary_controls = true, 6514 }, 6515 }, 6516 }, 6517 { 6518 .name = "Virtualize x2APIC mode, no APIC reg virt, x2APIC off", 6519 .virt_x2apic_mode_config = { 6520 .virtual_interrupt_delivery = true, 6521 .use_msr_bitmaps = true, 6522 .disable_x2apic_msr_intercepts = true, 6523 .disable_x2apic = true, 6524 .apic_reg_virt_config = { 6525 .apic_register_virtualization = false, 6526 .use_tpr_shadow = true, 6527 .virtualize_apic_accesses = false, 6528 .virtualize_x2apic_mode = true, 6529 .activate_secondary_controls = true, 6530 }, 6531 }, 6532 }, 6533 6534 /* 6535 * Enable "virtualize x2APIC mode" and "APIC-register virtualization", 6536 * and disable intercepts for the x2APIC MSRs, but fail to enable 6537 * "activate secondary controls" (i.e. L2 gets access to L1's x2APIC 6538 * MSRs). 6539 */ 6540 { 6541 .name = "Fail to enable activate secondary controls", 6542 .virt_x2apic_mode_config = { 6543 .virtual_interrupt_delivery = true, 6544 .use_msr_bitmaps = true, 6545 .disable_x2apic_msr_intercepts = true, 6546 .disable_x2apic = false, 6547 .apic_reg_virt_config = { 6548 .apic_register_virtualization = true, 6549 .use_tpr_shadow = true, 6550 .virtualize_apic_accesses = false, 6551 .virtualize_x2apic_mode = true, 6552 .activate_secondary_controls = false, 6553 }, 6554 }, 6555 }, 6556 6557 /* 6558 * Enable "APIC-register virtualization" and enable "activate secondary 6559 * controls" and disable intercepts for the x2APIC MSRs, but do not 6560 * enable the "virtualize x2APIC mode" VM-execution control (i.e. L2 6561 * gets access to L1's x2APIC MSRs). 6562 */ 6563 { 6564 .name = "Fail to enable virtualize x2APIC mode", 6565 .virt_x2apic_mode_config = { 6566 .virtual_interrupt_delivery = true, 6567 .use_msr_bitmaps = true, 6568 .disable_x2apic_msr_intercepts = true, 6569 .disable_x2apic = false, 6570 .apic_reg_virt_config = { 6571 .apic_register_virtualization = true, 6572 .use_tpr_shadow = true, 6573 .virtualize_apic_accesses = false, 6574 .virtualize_x2apic_mode = false, 6575 .activate_secondary_controls = true, 6576 }, 6577 }, 6578 }, 6579 6580 /* 6581 * Disable "Virtualize x2APIC mode", disable x2APIC MSR intercepts, and 6582 * enable "APIC-register virtualization" --> L2 gets L1's x2APIC MSRs. 6583 */ 6584 { 6585 .name = "Baseline", 6586 .virt_x2apic_mode_config = { 6587 .virtual_interrupt_delivery = true, 6588 .use_msr_bitmaps = true, 6589 .disable_x2apic_msr_intercepts = true, 6590 .disable_x2apic = false, 6591 .apic_reg_virt_config = { 6592 .apic_register_virtualization = true, 6593 .use_tpr_shadow = true, 6594 .virtualize_apic_accesses = false, 6595 .virtualize_x2apic_mode = false, 6596 .activate_secondary_controls = true, 6597 }, 6598 }, 6599 }, 6600 }; 6601 6602 enum X2apic_op { 6603 X2APIC_OP_RD, 6604 X2APIC_OP_WR, 6605 X2APIC_TERMINATE, 6606 }; 6607 6608 static u64 vmx_x2apic_read(u32 reg) 6609 { 6610 u32 msr_addr = x2apic_msr(reg); 6611 u64 val; 6612 6613 val = rdmsr(msr_addr); 6614 6615 return val; 6616 } 6617 6618 static void vmx_x2apic_write(u32 reg, u64 val) 6619 { 6620 u32 msr_addr = x2apic_msr(reg); 6621 6622 wrmsr(msr_addr, val); 6623 } 6624 6625 struct virt_x2apic_mode_guest_args { 6626 enum X2apic_op op; 6627 u32 reg; 6628 u64 val; 6629 bool should_gp; 6630 u64 (*virt_fn)(u64); 6631 } virt_x2apic_mode_guest_args; 6632 6633 static volatile bool handle_x2apic_gp_ran; 6634 static volatile u32 handle_x2apic_gp_insn_len; 6635 static void handle_x2apic_gp(struct ex_regs *regs) 6636 { 6637 handle_x2apic_gp_ran = true; 6638 regs->rip += handle_x2apic_gp_insn_len; 6639 } 6640 6641 static handler setup_x2apic_gp_handler(void) 6642 { 6643 handler old_handler; 6644 6645 old_handler = handle_exception(GP_VECTOR, handle_x2apic_gp); 6646 /* RDMSR and WRMSR are both 2 bytes, assuming no prefixes. */ 6647 handle_x2apic_gp_insn_len = 2; 6648 6649 return old_handler; 6650 } 6651 6652 static void teardown_x2apic_gp_handler(handler old_handler) 6653 { 6654 handle_exception(GP_VECTOR, old_handler); 6655 6656 /* 6657 * Defensively reset instruction length, so that if the handler is 6658 * incorrectly used, it will loop infinitely, rather than run off into 6659 * la la land. 6660 */ 6661 handle_x2apic_gp_insn_len = 0; 6662 handle_x2apic_gp_ran = false; 6663 } 6664 6665 static void virt_x2apic_mode_guest(void) 6666 { 6667 volatile struct virt_x2apic_mode_guest_args *args = 6668 &virt_x2apic_mode_guest_args; 6669 6670 for (;;) { 6671 enum X2apic_op op = args->op; 6672 u32 reg = args->reg; 6673 u64 val = args->val; 6674 bool should_gp = args->should_gp; 6675 u64 (*virt_fn)(u64) = args->virt_fn; 6676 handler old_handler; 6677 6678 if (op == X2APIC_TERMINATE) 6679 break; 6680 6681 if (should_gp) { 6682 TEST_ASSERT(!handle_x2apic_gp_ran); 6683 old_handler = setup_x2apic_gp_handler(); 6684 } 6685 6686 if (op == X2APIC_OP_RD) { 6687 u64 ret = vmx_x2apic_read(reg); 6688 6689 if (!should_gp) { 6690 u64 want = virt_fn(val); 6691 u64 got = virt_fn(ret); 6692 6693 report(got == want, 6694 "APIC read; got 0x%lx, want 0x%lx.", 6695 got, want); 6696 } 6697 } else if (op == X2APIC_OP_WR) { 6698 vmx_x2apic_write(reg, val); 6699 } 6700 6701 if (should_gp) { 6702 report(handle_x2apic_gp_ran, 6703 "x2APIC op triggered GP."); 6704 teardown_x2apic_gp_handler(old_handler); 6705 } 6706 6707 /* 6708 * The L1 should always execute a vmcall after it's done testing 6709 * an individual APIC operation. This helps to validate that the 6710 * L1 and L2 are in sync with each other, as expected. 6711 */ 6712 vmcall(); 6713 } 6714 } 6715 6716 static void test_x2apic_rd( 6717 u32 reg, struct virt_x2apic_mode_expectation *expectation, 6718 u32 *virtual_apic_page) 6719 { 6720 u64 val = expectation->rd_val; 6721 u32 exit_reason_want = expectation->rd_exit_reason; 6722 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6723 6724 report_prefix_pushf("x2apic - reading 0x%03x", reg); 6725 6726 /* Configure guest to do an x2apic read */ 6727 args->op = X2APIC_OP_RD; 6728 args->reg = reg; 6729 args->val = val; 6730 args->should_gp = expectation->rd_behavior == X2APIC_ACCESS_TRIGGERS_GP; 6731 args->virt_fn = expectation->virt_fn; 6732 6733 /* Setup virtual APIC page */ 6734 if (expectation->rd_behavior == X2APIC_ACCESS_VIRTUALIZED) 6735 virtual_apic_page[apic_reg_index(reg)] = (u32)val; 6736 6737 /* Enter guest */ 6738 enter_guest(); 6739 6740 if (exit_reason_want != VMX_VMCALL) { 6741 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 6742 } 6743 6744 skip_exit_vmcall(); 6745 report_prefix_pop(); 6746 } 6747 6748 static volatile bool handle_x2apic_ipi_ran; 6749 static void handle_x2apic_ipi(isr_regs_t *regs) 6750 { 6751 handle_x2apic_ipi_ran = true; 6752 eoi(); 6753 } 6754 6755 static void test_x2apic_wr( 6756 u32 reg, struct virt_x2apic_mode_expectation *expectation, 6757 u32 *virtual_apic_page) 6758 { 6759 u64 val = expectation->wr_val; 6760 u32 exit_reason_want = expectation->wr_exit_reason; 6761 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6762 int ipi_vector = 0xf1; 6763 u32 restore_val = 0; 6764 6765 report_prefix_pushf("x2apic - writing 0x%lx to 0x%03x", val, reg); 6766 6767 /* Configure guest to do an x2apic read */ 6768 args->op = X2APIC_OP_WR; 6769 args->reg = reg; 6770 args->val = val; 6771 args->should_gp = expectation->wr_behavior == X2APIC_ACCESS_TRIGGERS_GP; 6772 6773 /* Setup virtual APIC page */ 6774 if (expectation->wr_behavior == X2APIC_ACCESS_VIRTUALIZED) 6775 virtual_apic_page[apic_reg_index(reg)] = 0; 6776 if (expectation->wr_behavior == X2APIC_ACCESS_PASSED_THROUGH && !expectation->wr_only) 6777 restore_val = apic_read(reg); 6778 6779 /* Setup IPI handler */ 6780 handle_x2apic_ipi_ran = false; 6781 handle_irq(ipi_vector, handle_x2apic_ipi); 6782 6783 /* Enter guest */ 6784 enter_guest(); 6785 6786 /* 6787 * Validate the behavior and 6788 * pass a magic value back to the guest. 6789 */ 6790 if (exit_reason_want == VMX_EXTINT) { 6791 assert_exit_reason(exit_reason_want); 6792 6793 /* Clear the external interrupt. */ 6794 irq_enable(); 6795 asm volatile ("nop"); 6796 irq_disable(); 6797 report(handle_x2apic_ipi_ran, 6798 "Got pending interrupt after IRQ enabled."); 6799 6800 enter_guest(); 6801 } else if (exit_reason_want == VMX_APIC_WRITE) { 6802 assert_exit_reason(exit_reason_want); 6803 report(virtual_apic_page[apic_reg_index(reg)] == val, 6804 "got APIC write exit @ page offset 0x%03x; val is 0x%x, want 0x%lx", 6805 apic_reg_index(reg), 6806 virtual_apic_page[apic_reg_index(reg)], val); 6807 6808 /* Reenter guest so it can consume/check rcx and exit again. */ 6809 enter_guest(); 6810 } else if (exit_reason_want != VMX_VMCALL) { 6811 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 6812 } 6813 6814 assert_exit_reason(VMX_VMCALL); 6815 if (expectation->wr_behavior == X2APIC_ACCESS_VIRTUALIZED) { 6816 u64 want = val; 6817 u32 got = virtual_apic_page[apic_reg_index(reg)]; 6818 6819 report(got == want, "x2APIC write; got 0x%x, want 0x%lx", got, 6820 want); 6821 } else if (expectation->wr_behavior == X2APIC_ACCESS_PASSED_THROUGH) { 6822 if (!expectation->wr_only) { 6823 u32 got = apic_read(reg); 6824 bool ok; 6825 6826 /* 6827 * When L1's TPR is passed through to L2, the lower 6828 * nibble can be lost. For example, if L2 executes 6829 * WRMSR(0x808, 0x78), then, L1 might read 0x70. 6830 * 6831 * Here's how the lower nibble can get lost: 6832 * 1. L2 executes WRMSR(0x808, 0x78). 6833 * 2. L2 exits to L0 with a WRMSR exit. 6834 * 3. L0 emulates WRMSR, by writing L1's TPR. 6835 * 4. L0 re-enters L2. 6836 * 5. L2 exits to L0 (reason doesn't matter). 6837 * 6. L0 reflects L2's exit to L1. 6838 * 7. Before entering L1, L0 exits to user-space 6839 * (e.g., to satisfy TPR access reporting). 6840 * 8. User-space executes KVM_SET_REGS ioctl, which 6841 * clears the lower nibble of L1's TPR. 6842 */ 6843 if (reg == APIC_TASKPRI) { 6844 got = apic_virt_nibble1(got); 6845 val = apic_virt_nibble1(val); 6846 } 6847 6848 ok = got == val; 6849 report(ok, 6850 "non-virtualized write; val is 0x%x, want 0x%lx", 6851 got, val); 6852 apic_write(reg, restore_val); 6853 } else { 6854 report_pass("non-virtualized and write-only OK"); 6855 } 6856 } 6857 skip_exit_insn(); 6858 6859 report_prefix_pop(); 6860 } 6861 6862 static enum Config_type configure_virt_x2apic_mode_test( 6863 struct virt_x2apic_mode_config *virt_x2apic_mode_config, 6864 u8 *msr_bitmap_page) 6865 { 6866 int msr; 6867 u32 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6868 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6869 6870 /* x2apic-specific VMCS config */ 6871 if (virt_x2apic_mode_config->use_msr_bitmaps) { 6872 /* virt_x2apic_mode_test() checks for MSR bitmaps support */ 6873 cpu_exec_ctrl0 |= CPU_MSR_BITMAP; 6874 } else { 6875 cpu_exec_ctrl0 &= ~CPU_MSR_BITMAP; 6876 } 6877 6878 if (virt_x2apic_mode_config->virtual_interrupt_delivery) { 6879 if (!(ctrl_cpu_rev[1].clr & CPU_VINTD)) { 6880 report_skip("%s : \"virtual-interrupt delivery\" exec control not supported", __func__); 6881 return CONFIG_TYPE_UNSUPPORTED; 6882 } 6883 cpu_exec_ctrl1 |= CPU_VINTD; 6884 } else { 6885 cpu_exec_ctrl1 &= ~CPU_VINTD; 6886 } 6887 6888 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6889 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6890 6891 /* x2APIC MSR intercepts are usually off for "Virtualize x2APIC mode" */ 6892 for (msr = 0x800; msr <= 0x8ff; msr++) { 6893 if (virt_x2apic_mode_config->disable_x2apic_msr_intercepts) { 6894 clear_bit(msr, msr_bitmap_page + 0x000); 6895 clear_bit(msr, msr_bitmap_page + 0x800); 6896 } else { 6897 set_bit(msr, msr_bitmap_page + 0x000); 6898 set_bit(msr, msr_bitmap_page + 0x800); 6899 } 6900 } 6901 6902 /* x2APIC mode can impact virtualization */ 6903 reset_apic(); 6904 if (!virt_x2apic_mode_config->disable_x2apic) 6905 enable_x2apic(); 6906 6907 return configure_apic_reg_virt_test( 6908 &virt_x2apic_mode_config->apic_reg_virt_config); 6909 } 6910 6911 static void virt_x2apic_mode_test(void) 6912 { 6913 u32 *virtual_apic_page; 6914 u8 *msr_bitmap_page; 6915 u64 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6916 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6917 int i; 6918 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6919 6920 if (!cpu_has_apicv()) { 6921 report_skip("%s : Not all required APICv bits supported", __func__); 6922 return; 6923 } 6924 6925 /* 6926 * This is to exercise an issue in KVM's logic to merge L0's and L1's 6927 * MSR bitmaps. Previously, an L1 could get at L0's x2APIC MSRs by 6928 * writing the IA32_SPEC_CTRL MSR or the IA32_PRED_CMD MSRs. KVM would 6929 * then proceed to manipulate the MSR bitmaps, as if VMCS12 had the 6930 * "Virtualize x2APIC mod" control set, even when it didn't. 6931 */ 6932 if (this_cpu_has(X86_FEATURE_SPEC_CTRL)) 6933 wrmsr(MSR_IA32_SPEC_CTRL, 1); 6934 6935 /* 6936 * Check that VMCS12 supports: 6937 * - "Virtual-APIC address", indicated by "use TPR shadow" 6938 * - "MSR-bitmap address", indicated by "use MSR bitmaps" 6939 */ 6940 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) { 6941 report_skip("%s : \"Use TPR shadow\" exec control not supported", __func__); 6942 return; 6943 } else if (!(ctrl_cpu_rev[0].clr & CPU_MSR_BITMAP)) { 6944 report_skip("%s : \"Use MSR bitmaps\" exec control not supported", __func__); 6945 return; 6946 } 6947 6948 test_set_guest(virt_x2apic_mode_guest); 6949 6950 virtual_apic_page = alloc_page(); 6951 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 6952 6953 msr_bitmap_page = alloc_page(); 6954 memset(msr_bitmap_page, 0xff, PAGE_SIZE); 6955 vmcs_write(MSR_BITMAP, virt_to_phys(msr_bitmap_page)); 6956 6957 for (i = 0; i < ARRAY_SIZE(virt_x2apic_mode_tests); i++) { 6958 struct virt_x2apic_mode_test_case *virt_x2apic_mode_test_case = 6959 &virt_x2apic_mode_tests[i]; 6960 struct virt_x2apic_mode_config *virt_x2apic_mode_config = 6961 &virt_x2apic_mode_test_case->virt_x2apic_mode_config; 6962 enum Config_type config_type; 6963 u32 reg; 6964 6965 printf("--- %s test ---\n", virt_x2apic_mode_test_case->name); 6966 config_type = 6967 configure_virt_x2apic_mode_test(virt_x2apic_mode_config, 6968 msr_bitmap_page); 6969 if (config_type == CONFIG_TYPE_UNSUPPORTED) { 6970 report_skip("Skip because of missing features."); 6971 continue; 6972 } else if (config_type == CONFIG_TYPE_VMENTRY_FAILS_EARLY) { 6973 enter_guest_with_bad_controls(); 6974 continue; 6975 } 6976 6977 for (reg = 0; reg < PAGE_SIZE / sizeof(u32); reg += 0x10) { 6978 struct virt_x2apic_mode_expectation expectation; 6979 6980 virt_x2apic_mode_exit_expectation( 6981 reg, virt_x2apic_mode_config, &expectation); 6982 6983 test_x2apic_rd(reg, &expectation, virtual_apic_page); 6984 test_x2apic_wr(reg, &expectation, virtual_apic_page); 6985 } 6986 } 6987 6988 6989 /* Terminate the guest */ 6990 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6991 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6992 args->op = X2APIC_TERMINATE; 6993 enter_guest(); 6994 assert_exit_reason(VMX_VMCALL); 6995 } 6996 6997 static void test_ctl_reg(const char *cr_name, u64 cr, u64 fixed0, u64 fixed1) 6998 { 6999 u64 val; 7000 u64 cr_saved = vmcs_read(cr); 7001 int i; 7002 7003 val = fixed0 & fixed1; 7004 if (cr == HOST_CR4) 7005 vmcs_write(cr, val | X86_CR4_PAE); 7006 else 7007 vmcs_write(cr, val); 7008 report_prefix_pushf("%s %lx", cr_name, val); 7009 if (val == fixed0) 7010 test_vmx_vmlaunch(0); 7011 else 7012 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7013 report_prefix_pop(); 7014 7015 for (i = 0; i < 64; i++) { 7016 7017 /* Set a bit when the corresponding bit in fixed1 is 0 */ 7018 if ((fixed1 & (1ull << i)) == 0) { 7019 if (cr == HOST_CR4 && ((1ull << i) & X86_CR4_SMEP || 7020 (1ull << i) & X86_CR4_SMAP)) 7021 continue; 7022 7023 vmcs_write(cr, cr_saved | (1ull << i)); 7024 report_prefix_pushf("%s %llx", cr_name, 7025 cr_saved | (1ull << i)); 7026 test_vmx_vmlaunch( 7027 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7028 report_prefix_pop(); 7029 } 7030 7031 /* Unset a bit when the corresponding bit in fixed0 is 1 */ 7032 if (fixed0 & (1ull << i)) { 7033 vmcs_write(cr, cr_saved & ~(1ull << i)); 7034 report_prefix_pushf("%s %llx", cr_name, 7035 cr_saved & ~(1ull << i)); 7036 test_vmx_vmlaunch( 7037 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7038 report_prefix_pop(); 7039 } 7040 } 7041 7042 vmcs_write(cr, cr_saved); 7043 } 7044 7045 /* 7046 * 1. The CR0 field must not set any bit to a value not supported in VMX 7047 * operation. 7048 * 2. The CR4 field must not set any bit to a value not supported in VMX 7049 * operation. 7050 * 3. On processors that support Intel 64 architecture, the CR3 field must 7051 * be such that bits 63:52 and bits in the range 51:32 beyond the 7052 * processor's physical-address width must be 0. 7053 * 7054 * [Intel SDM] 7055 */ 7056 static void test_host_ctl_regs(void) 7057 { 7058 u64 fixed0, fixed1, cr3, cr3_saved; 7059 int i; 7060 7061 /* Test CR0 */ 7062 fixed0 = rdmsr(MSR_IA32_VMX_CR0_FIXED0); 7063 fixed1 = rdmsr(MSR_IA32_VMX_CR0_FIXED1); 7064 test_ctl_reg("HOST_CR0", HOST_CR0, fixed0, fixed1); 7065 7066 /* Test CR4 */ 7067 fixed0 = rdmsr(MSR_IA32_VMX_CR4_FIXED0); 7068 fixed1 = rdmsr(MSR_IA32_VMX_CR4_FIXED1) & 7069 ~(X86_CR4_SMEP | X86_CR4_SMAP); 7070 test_ctl_reg("HOST_CR4", HOST_CR4, fixed0, fixed1); 7071 7072 /* Test CR3 */ 7073 cr3_saved = vmcs_read(HOST_CR3); 7074 for (i = cpuid_maxphyaddr(); i < 64; i++) { 7075 cr3 = cr3_saved | (1ul << i); 7076 vmcs_write(HOST_CR3, cr3); 7077 report_prefix_pushf("HOST_CR3 %lx", cr3); 7078 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7079 report_prefix_pop(); 7080 } 7081 7082 vmcs_write(HOST_CR3, cr3_saved); 7083 } 7084 7085 static void test_efer_vmlaunch(u32 fld, bool ok) 7086 { 7087 if (fld == HOST_EFER) { 7088 if (ok) 7089 test_vmx_vmlaunch(0); 7090 else 7091 test_vmx_vmlaunch2(VMXERR_ENTRY_INVALID_CONTROL_FIELD, 7092 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7093 } else { 7094 test_guest_state("EFER test", !ok, GUEST_EFER, "GUEST_EFER"); 7095 } 7096 } 7097 7098 static void test_efer_one(u32 fld, const char * fld_name, u64 efer, 7099 u32 ctrl_fld, u64 ctrl, 7100 int i, const char *efer_bit_name) 7101 { 7102 bool ok; 7103 7104 ok = true; 7105 if (ctrl_fld == EXI_CONTROLS && (ctrl & EXI_LOAD_EFER)) { 7106 if (!!(efer & EFER_LMA) != !!(ctrl & EXI_HOST_64)) 7107 ok = false; 7108 if (!!(efer & EFER_LME) != !!(ctrl & EXI_HOST_64)) 7109 ok = false; 7110 } 7111 if (ctrl_fld == ENT_CONTROLS && (ctrl & ENT_LOAD_EFER)) { 7112 /* Check LMA too since CR0.PG is set. */ 7113 if (!!(efer & EFER_LMA) != !!(ctrl & ENT_GUEST_64)) 7114 ok = false; 7115 if (!!(efer & EFER_LME) != !!(ctrl & ENT_GUEST_64)) 7116 ok = false; 7117 } 7118 7119 /* 7120 * Skip the test if it would enter the guest in 32-bit mode. 7121 * Perhaps write the test in assembly and make sure it 7122 * can be run in either mode? 7123 */ 7124 if (fld == GUEST_EFER && ok && !(ctrl & ENT_GUEST_64)) 7125 return; 7126 7127 vmcs_write(ctrl_fld, ctrl); 7128 vmcs_write(fld, efer); 7129 report_prefix_pushf("%s %s bit turned %s, controls %s", 7130 fld_name, efer_bit_name, 7131 (i & 1) ? "on" : "off", 7132 (i & 2) ? "on" : "off"); 7133 7134 test_efer_vmlaunch(fld, ok); 7135 report_prefix_pop(); 7136 } 7137 7138 static void test_efer_bit(u32 fld, const char * fld_name, 7139 u32 ctrl_fld, u64 ctrl_bit, u64 efer_bit, 7140 const char *efer_bit_name) 7141 { 7142 u64 efer_saved = vmcs_read(fld); 7143 u32 ctrl_saved = vmcs_read(ctrl_fld); 7144 int i; 7145 7146 for (i = 0; i < 4; i++) { 7147 u64 efer = efer_saved & ~efer_bit; 7148 u64 ctrl = ctrl_saved & ~ctrl_bit; 7149 7150 if (i & 1) 7151 efer |= efer_bit; 7152 if (i & 2) 7153 ctrl |= ctrl_bit; 7154 7155 test_efer_one(fld, fld_name, efer, ctrl_fld, ctrl, 7156 i, efer_bit_name); 7157 } 7158 7159 vmcs_write(ctrl_fld, ctrl_saved); 7160 vmcs_write(fld, efer_saved); 7161 } 7162 7163 static void test_efer(u32 fld, const char * fld_name, u32 ctrl_fld, 7164 u64 ctrl_bit1, u64 ctrl_bit2) 7165 { 7166 u64 efer_saved = vmcs_read(fld); 7167 u32 ctrl_saved = vmcs_read(ctrl_fld); 7168 u64 efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 7169 u64 i; 7170 u64 efer; 7171 7172 if (this_cpu_has(X86_FEATURE_NX)) 7173 efer_reserved_bits &= ~EFER_NX; 7174 7175 if (!ctrl_bit1) { 7176 report_skip("%s : \"Load-IA32-EFER\" exit control not supported", __func__); 7177 goto test_entry_exit_mode; 7178 } 7179 7180 report_prefix_pushf("%s %lx", fld_name, efer_saved); 7181 test_efer_vmlaunch(fld, true); 7182 report_prefix_pop(); 7183 7184 /* 7185 * Check reserved bits 7186 */ 7187 vmcs_write(ctrl_fld, ctrl_saved & ~ctrl_bit1); 7188 for (i = 0; i < 64; i++) { 7189 if ((1ull << i) & efer_reserved_bits) { 7190 efer = efer_saved | (1ull << i); 7191 vmcs_write(fld, efer); 7192 report_prefix_pushf("%s %lx", fld_name, efer); 7193 test_efer_vmlaunch(fld, true); 7194 report_prefix_pop(); 7195 } 7196 } 7197 7198 vmcs_write(ctrl_fld, ctrl_saved | ctrl_bit1); 7199 for (i = 0; i < 64; i++) { 7200 if ((1ull << i) & efer_reserved_bits) { 7201 efer = efer_saved | (1ull << i); 7202 vmcs_write(fld, efer); 7203 report_prefix_pushf("%s %lx", fld_name, efer); 7204 test_efer_vmlaunch(fld, false); 7205 report_prefix_pop(); 7206 } 7207 } 7208 7209 vmcs_write(ctrl_fld, ctrl_saved); 7210 vmcs_write(fld, efer_saved); 7211 7212 /* 7213 * Check LMA and LME bits 7214 */ 7215 test_efer_bit(fld, fld_name, 7216 ctrl_fld, ctrl_bit1, 7217 EFER_LMA, 7218 "EFER_LMA"); 7219 test_efer_bit(fld, fld_name, 7220 ctrl_fld, ctrl_bit1, 7221 EFER_LME, 7222 "EFER_LME"); 7223 7224 test_entry_exit_mode: 7225 test_efer_bit(fld, fld_name, 7226 ctrl_fld, ctrl_bit2, 7227 EFER_LMA, 7228 "EFER_LMA"); 7229 test_efer_bit(fld, fld_name, 7230 ctrl_fld, ctrl_bit2, 7231 EFER_LME, 7232 "EFER_LME"); 7233 } 7234 7235 /* 7236 * If the 'load IA32_EFER' VM-exit control is 1, bits reserved in the 7237 * IA32_EFER MSR must be 0 in the field for that register. In addition, 7238 * the values of the LMA and LME bits in the field must each be that of 7239 * the 'host address-space size' VM-exit control. 7240 * 7241 * [Intel SDM] 7242 */ 7243 static void test_host_efer(void) 7244 { 7245 test_efer(HOST_EFER, "HOST_EFER", EXI_CONTROLS, 7246 ctrl_exit_rev.clr & EXI_LOAD_EFER, 7247 EXI_HOST_64); 7248 } 7249 7250 /* 7251 * If the 'load IA32_EFER' VM-enter control is 1, bits reserved in the 7252 * IA32_EFER MSR must be 0 in the field for that register. In addition, 7253 * the values of the LMA and LME bits in the field must each be that of 7254 * the 'IA32e-mode guest' VM-exit control. 7255 */ 7256 static void test_guest_efer(void) 7257 { 7258 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) { 7259 report_skip("%s : \"Load-IA32-EFER\" entry control not supported", __func__); 7260 return; 7261 } 7262 7263 vmcs_write(GUEST_EFER, rdmsr(MSR_EFER)); 7264 test_efer(GUEST_EFER, "GUEST_EFER", ENT_CONTROLS, 7265 ctrl_enter_rev.clr & ENT_LOAD_EFER, 7266 ENT_GUEST_64); 7267 } 7268 7269 /* 7270 * PAT values higher than 8 are uninteresting since they're likely lumped 7271 * in with "8". We only test values above 8 one bit at a time, 7272 * in order to reduce the number of VM-Entries and keep the runtime reasonable. 7273 */ 7274 #define PAT_VAL_LIMIT 8 7275 7276 static void test_pat(u32 field, const char * field_name, u32 ctrl_field, 7277 u64 ctrl_bit) 7278 { 7279 u32 ctrl_saved = vmcs_read(ctrl_field); 7280 u64 pat_saved = vmcs_read(field); 7281 u64 i, val; 7282 u32 j; 7283 int error; 7284 7285 vmcs_clear_bits(ctrl_field, ctrl_bit); 7286 7287 for (i = 0; i < 256; i = (i < PAT_VAL_LIMIT) ? i + 1 : i * 2) { 7288 /* Test PAT0..PAT7 fields */ 7289 for (j = 0; j < (i ? 8 : 1); j++) { 7290 val = i << j * 8; 7291 vmcs_write(field, val); 7292 if (field == HOST_PAT) { 7293 report_prefix_pushf("%s %lx", field_name, val); 7294 test_vmx_vmlaunch(0); 7295 report_prefix_pop(); 7296 7297 } else { // GUEST_PAT 7298 test_guest_state("ENT_LOAD_PAT enabled", false, 7299 val, "GUEST_PAT"); 7300 } 7301 } 7302 } 7303 7304 vmcs_set_bits(ctrl_field, ctrl_bit); 7305 for (i = 0; i < 256; i = (i < PAT_VAL_LIMIT) ? i + 1 : i * 2) { 7306 /* Test PAT0..PAT7 fields */ 7307 for (j = 0; j < (i ? 8 : 1); j++) { 7308 val = i << j * 8; 7309 vmcs_write(field, val); 7310 7311 if (field == HOST_PAT) { 7312 report_prefix_pushf("%s %lx", field_name, val); 7313 if (i == 0x2 || i == 0x3 || i >= 0x8) 7314 error = 7315 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD; 7316 else 7317 error = 0; 7318 7319 test_vmx_vmlaunch(error); 7320 report_prefix_pop(); 7321 7322 } else { // GUEST_PAT 7323 error = (i == 0x2 || i == 0x3 || i >= 0x8); 7324 test_guest_state("ENT_LOAD_PAT enabled", !!error, 7325 val, "GUEST_PAT"); 7326 } 7327 7328 } 7329 } 7330 7331 vmcs_write(ctrl_field, ctrl_saved); 7332 vmcs_write(field, pat_saved); 7333 } 7334 7335 /* 7336 * If the "load IA32_PAT" VM-exit control is 1, the value of the field 7337 * for the IA32_PAT MSR must be one that could be written by WRMSR 7338 * without fault at CPL 0. Specifically, each of the 8 bytes in the 7339 * field must have one of the values 0 (UC), 1 (WC), 4 (WT), 5 (WP), 7340 * 6 (WB), or 7 (UC-). 7341 * 7342 * [Intel SDM] 7343 */ 7344 static void test_load_host_pat(void) 7345 { 7346 /* 7347 * "load IA32_PAT" VM-exit control 7348 */ 7349 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) { 7350 report_skip("%s : \"Load-IA32-PAT\" exit control not supported", __func__); 7351 return; 7352 } 7353 7354 test_pat(HOST_PAT, "HOST_PAT", EXI_CONTROLS, EXI_LOAD_PAT); 7355 } 7356 7357 union cpuidA_eax { 7358 struct { 7359 unsigned int version_id:8; 7360 unsigned int num_counters_gp:8; 7361 unsigned int bit_width:8; 7362 unsigned int mask_length:8; 7363 } split; 7364 unsigned int full; 7365 }; 7366 7367 union cpuidA_edx { 7368 struct { 7369 unsigned int num_counters_fixed:5; 7370 unsigned int bit_width_fixed:8; 7371 unsigned int reserved:9; 7372 } split; 7373 unsigned int full; 7374 }; 7375 7376 static bool valid_pgc(u64 val) 7377 { 7378 struct cpuid id; 7379 union cpuidA_eax eax; 7380 union cpuidA_edx edx; 7381 u64 mask; 7382 7383 id = cpuid(0xA); 7384 eax.full = id.a; 7385 edx.full = id.d; 7386 mask = ~(((1ull << eax.split.num_counters_gp) - 1) | 7387 (((1ull << edx.split.num_counters_fixed) - 1) << 32)); 7388 7389 return !(val & mask); 7390 } 7391 7392 static void test_pgc_vmlaunch(u32 xerror, u32 xreason, bool xfail, bool host) 7393 { 7394 u32 inst_err; 7395 u64 obs; 7396 bool success; 7397 struct vmx_state_area_test_data *data = &vmx_state_area_test_data; 7398 7399 if (host) { 7400 success = vmlaunch_succeeds(); 7401 obs = rdmsr(data->msr); 7402 if (!success) { 7403 inst_err = vmcs_read(VMX_INST_ERROR); 7404 report(xerror == inst_err, "vmlaunch failed, " 7405 "VMX Inst Error is %d (expected %d)", 7406 inst_err, xerror); 7407 } else { 7408 report(!data->enabled || data->exp == obs, 7409 "Host state is 0x%lx (expected 0x%lx)", 7410 obs, data->exp); 7411 report(success != xfail, "vmlaunch succeeded"); 7412 } 7413 } else { 7414 test_guest_state("load GUEST_PERF_GLOBAL_CTRL", xfail, 7415 GUEST_PERF_GLOBAL_CTRL, 7416 "GUEST_PERF_GLOBAL_CTRL"); 7417 } 7418 } 7419 7420 /* 7421 * test_load_perf_global_ctrl is a generic function for testing the 7422 * "load IA32_PERF_GLOBAL_CTRL" VM-{Entry,Exit} controls. This test function 7423 * tests the provided ctrl_val when disabled and enabled. 7424 * 7425 * @nr: VMCS field number corresponding to the host/guest state field 7426 * @name: Name of the above VMCS field for printing in test report 7427 * @ctrl_nr: VMCS field number corresponding to the VM-{Entry,Exit} control 7428 * @ctrl_val: Bit to set on the ctrl_field 7429 */ 7430 static void test_perf_global_ctrl(u32 nr, const char *name, u32 ctrl_nr, 7431 const char *ctrl_name, u64 ctrl_val) 7432 { 7433 u64 ctrl_saved = vmcs_read(ctrl_nr); 7434 u64 pgc_saved = vmcs_read(nr); 7435 u64 i, val; 7436 bool host = nr == HOST_PERF_GLOBAL_CTRL; 7437 struct vmx_state_area_test_data *data = &vmx_state_area_test_data; 7438 7439 data->msr = MSR_CORE_PERF_GLOBAL_CTRL; 7440 msr_bmp_init(); 7441 vmcs_write(ctrl_nr, ctrl_saved & ~ctrl_val); 7442 data->enabled = false; 7443 report_prefix_pushf("\"load IA32_PERF_GLOBAL_CTRL\"=0 on %s", 7444 ctrl_name); 7445 7446 for (i = 0; i < 64; i++) { 7447 val = 1ull << i; 7448 vmcs_write(nr, val); 7449 report_prefix_pushf("%s = 0x%lx", name, val); 7450 test_pgc_vmlaunch(0, VMX_VMCALL, false, host); 7451 report_prefix_pop(); 7452 } 7453 report_prefix_pop(); 7454 7455 vmcs_write(ctrl_nr, ctrl_saved | ctrl_val); 7456 data->enabled = true; 7457 report_prefix_pushf("\"load IA32_PERF_GLOBAL_CTRL\"=1 on %s", 7458 ctrl_name); 7459 for (i = 0; i < 64; i++) { 7460 val = 1ull << i; 7461 data->exp = val; 7462 vmcs_write(nr, val); 7463 report_prefix_pushf("%s = 0x%lx", name, val); 7464 if (valid_pgc(val)) { 7465 test_pgc_vmlaunch(0, VMX_VMCALL, false, host); 7466 } else { 7467 if (host) 7468 test_pgc_vmlaunch( 7469 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, 7470 0, 7471 true, 7472 host); 7473 else 7474 test_pgc_vmlaunch( 7475 0, 7476 VMX_ENTRY_FAILURE | VMX_FAIL_STATE, 7477 true, 7478 host); 7479 } 7480 report_prefix_pop(); 7481 } 7482 7483 data->enabled = false; 7484 report_prefix_pop(); 7485 vmcs_write(ctrl_nr, ctrl_saved); 7486 vmcs_write(nr, pgc_saved); 7487 } 7488 7489 static void test_load_host_perf_global_ctrl(void) 7490 { 7491 if (!this_cpu_has_perf_global_ctrl()) { 7492 report_skip("%s : \"IA32_PERF_GLOBAL_CTRL\" MSR not supported", __func__); 7493 return; 7494 } 7495 7496 if (!(ctrl_exit_rev.clr & EXI_LOAD_PERF)) { 7497 report_skip("%s : \"Load IA32_PERF_GLOBAL_CTRL\" exit control not supported", __func__); 7498 return; 7499 } 7500 7501 test_perf_global_ctrl(HOST_PERF_GLOBAL_CTRL, "HOST_PERF_GLOBAL_CTRL", 7502 EXI_CONTROLS, "EXI_CONTROLS", EXI_LOAD_PERF); 7503 } 7504 7505 7506 static void test_load_guest_perf_global_ctrl(void) 7507 { 7508 if (!this_cpu_has_perf_global_ctrl()) { 7509 report_skip("%s : \"IA32_PERF_GLOBAL_CTRL\" MSR not supported", __func__); 7510 return; 7511 } 7512 7513 if (!(ctrl_enter_rev.clr & ENT_LOAD_PERF)) { 7514 report_skip("%s : \"Load IA32_PERF_GLOBAL_CTRL\" entry control not supported", __func__); 7515 return; 7516 } 7517 7518 test_perf_global_ctrl(GUEST_PERF_GLOBAL_CTRL, "GUEST_PERF_GLOBAL_CTRL", 7519 ENT_CONTROLS, "ENT_CONTROLS", ENT_LOAD_PERF); 7520 } 7521 7522 7523 /* 7524 * test_vmcs_field - test a value for the given VMCS field 7525 * @field: VMCS field 7526 * @field_name: string name of VMCS field 7527 * @bit_start: starting bit 7528 * @bit_end: ending bit 7529 * @val: value that the bit range must or must not contain 7530 * @valid_val: whether value given in 'val' must be valid or not 7531 * @error: expected VMCS error when vmentry fails for an invalid value 7532 */ 7533 static void test_vmcs_field(u64 field, const char *field_name, u32 bit_start, 7534 u32 bit_end, u64 val, bool valid_val, u32 error) 7535 { 7536 u64 field_saved = vmcs_read(field); 7537 u32 i; 7538 u64 tmp; 7539 u32 bit_on; 7540 u64 mask = ~0ull; 7541 7542 mask = (mask >> bit_end) << bit_end; 7543 mask = mask | ((1 << bit_start) - 1); 7544 tmp = (field_saved & mask) | (val << bit_start); 7545 7546 vmcs_write(field, tmp); 7547 report_prefix_pushf("%s %lx", field_name, tmp); 7548 if (valid_val) 7549 test_vmx_vmlaunch(0); 7550 else 7551 test_vmx_vmlaunch(error); 7552 report_prefix_pop(); 7553 7554 for (i = bit_start; i <= bit_end; i = i + 2) { 7555 bit_on = ((1ull < i) & (val << bit_start)) ? 0 : 1; 7556 if (bit_on) 7557 tmp = field_saved | (1ull << i); 7558 else 7559 tmp = field_saved & ~(1ull << i); 7560 vmcs_write(field, tmp); 7561 report_prefix_pushf("%s %lx", field_name, tmp); 7562 if (valid_val) 7563 test_vmx_vmlaunch(error); 7564 else 7565 test_vmx_vmlaunch(0); 7566 report_prefix_pop(); 7567 } 7568 7569 vmcs_write(field, field_saved); 7570 } 7571 7572 static void test_canonical(u64 field, const char * field_name, bool host) 7573 { 7574 u64 addr_saved = vmcs_read(field); 7575 7576 /* 7577 * Use the existing value if possible. Writing a random canonical 7578 * value is not an option as doing so would corrupt the field being 7579 * tested and likely hose the test. 7580 */ 7581 if (is_canonical(addr_saved)) { 7582 if (host) { 7583 report_prefix_pushf("%s %lx", field_name, addr_saved); 7584 test_vmx_vmlaunch(0); 7585 report_prefix_pop(); 7586 } else { 7587 test_guest_state("Test canonical address", false, 7588 addr_saved, field_name); 7589 } 7590 } 7591 7592 vmcs_write(field, NONCANONICAL); 7593 7594 if (host) { 7595 report_prefix_pushf("%s %llx", field_name, NONCANONICAL); 7596 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7597 report_prefix_pop(); 7598 } else { 7599 test_guest_state("Test non-canonical address", true, 7600 NONCANONICAL, field_name); 7601 } 7602 7603 vmcs_write(field, addr_saved); 7604 } 7605 7606 #define TEST_RPL_TI_FLAGS(reg, name) \ 7607 test_vmcs_field(reg, name, 0, 2, 0x0, true, \ 7608 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7609 7610 #define TEST_CS_TR_FLAGS(reg, name) \ 7611 test_vmcs_field(reg, name, 3, 15, 0x0000, false, \ 7612 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7613 7614 /* 7615 * 1. In the selector field for each of CS, SS, DS, ES, FS, GS and TR, the 7616 * RPL (bits 1:0) and the TI flag (bit 2) must be 0. 7617 * 2. The selector fields for CS and TR cannot be 0000H. 7618 * 3. The selector field for SS cannot be 0000H if the "host address-space 7619 * size" VM-exit control is 0. 7620 * 4. On processors that support Intel 64 architecture, the base-address 7621 * fields for FS, GS and TR must contain canonical addresses. 7622 */ 7623 static void test_host_segment_regs(void) 7624 { 7625 u16 selector_saved; 7626 7627 /* 7628 * Test RPL and TI flags 7629 */ 7630 TEST_RPL_TI_FLAGS(HOST_SEL_CS, "HOST_SEL_CS"); 7631 TEST_RPL_TI_FLAGS(HOST_SEL_SS, "HOST_SEL_SS"); 7632 TEST_RPL_TI_FLAGS(HOST_SEL_DS, "HOST_SEL_DS"); 7633 TEST_RPL_TI_FLAGS(HOST_SEL_ES, "HOST_SEL_ES"); 7634 TEST_RPL_TI_FLAGS(HOST_SEL_FS, "HOST_SEL_FS"); 7635 TEST_RPL_TI_FLAGS(HOST_SEL_GS, "HOST_SEL_GS"); 7636 TEST_RPL_TI_FLAGS(HOST_SEL_TR, "HOST_SEL_TR"); 7637 7638 /* 7639 * Test that CS and TR fields can not be 0x0000 7640 */ 7641 TEST_CS_TR_FLAGS(HOST_SEL_CS, "HOST_SEL_CS"); 7642 TEST_CS_TR_FLAGS(HOST_SEL_TR, "HOST_SEL_TR"); 7643 7644 /* 7645 * SS field can not be 0x0000 if "host address-space size" VM-exit 7646 * control is 0 7647 */ 7648 selector_saved = vmcs_read(HOST_SEL_SS); 7649 vmcs_write(HOST_SEL_SS, 0); 7650 report_prefix_pushf("HOST_SEL_SS 0"); 7651 if (vmcs_read(EXI_CONTROLS) & EXI_HOST_64) { 7652 test_vmx_vmlaunch(0); 7653 } else { 7654 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7655 } 7656 report_prefix_pop(); 7657 7658 vmcs_write(HOST_SEL_SS, selector_saved); 7659 7660 /* 7661 * Base address for FS, GS and TR must be canonical 7662 */ 7663 test_canonical(HOST_BASE_FS, "HOST_BASE_FS", true); 7664 test_canonical(HOST_BASE_GS, "HOST_BASE_GS", true); 7665 test_canonical(HOST_BASE_TR, "HOST_BASE_TR", true); 7666 } 7667 7668 /* 7669 * On processors that support Intel 64 architecture, the base-address 7670 * fields for GDTR and IDTR must contain canonical addresses. 7671 */ 7672 static void test_host_desc_tables(void) 7673 { 7674 test_canonical(HOST_BASE_GDTR, "HOST_BASE_GDTR", true); 7675 test_canonical(HOST_BASE_IDTR, "HOST_BASE_IDTR", true); 7676 } 7677 7678 /* 7679 * If the "host address-space size" VM-exit control is 0, the following must 7680 * hold: 7681 * - The "IA-32e mode guest" VM-entry control is 0. 7682 * - Bit 17 of the CR4 field (corresponding to CR4.PCIDE) is 0. 7683 * - Bits 63:32 in the RIP field are 0. 7684 * 7685 * If the "host address-space size" VM-exit control is 1, the following must 7686 * hold: 7687 * - Bit 5 of the CR4 field (corresponding to CR4.PAE) is 1. 7688 * - The RIP field contains a canonical address. 7689 * 7690 */ 7691 static void test_host_addr_size(void) 7692 { 7693 u64 cr4_saved = vmcs_read(HOST_CR4); 7694 u64 rip_saved = vmcs_read(HOST_RIP); 7695 u64 entry_ctrl_saved = vmcs_read(ENT_CONTROLS); 7696 int i; 7697 u64 tmp; 7698 7699 if (vmcs_read(EXI_CONTROLS) & EXI_HOST_64) { 7700 vmcs_write(ENT_CONTROLS, entry_ctrl_saved | ENT_GUEST_64); 7701 report_prefix_pushf("\"IA-32e mode guest\" enabled"); 7702 test_vmx_vmlaunch(0); 7703 report_prefix_pop(); 7704 7705 vmcs_write(HOST_CR4, cr4_saved | X86_CR4_PCIDE); 7706 report_prefix_pushf("\"CR4.PCIDE\" set"); 7707 test_vmx_vmlaunch(0); 7708 report_prefix_pop(); 7709 7710 for (i = 32; i <= 63; i = i + 4) { 7711 tmp = rip_saved | 1ull << i; 7712 vmcs_write(HOST_RIP, tmp); 7713 report_prefix_pushf("HOST_RIP %lx", tmp); 7714 test_vmx_vmlaunch(0); 7715 report_prefix_pop(); 7716 } 7717 7718 if (cr4_saved & X86_CR4_PAE) { 7719 vmcs_write(HOST_CR4, cr4_saved & ~X86_CR4_PAE); 7720 report_prefix_pushf("\"CR4.PAE\" unset"); 7721 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7722 } else { 7723 report_prefix_pushf("\"CR4.PAE\" set"); 7724 test_vmx_vmlaunch(0); 7725 } 7726 report_prefix_pop(); 7727 7728 vmcs_write(HOST_RIP, NONCANONICAL); 7729 report_prefix_pushf("HOST_RIP %llx", NONCANONICAL); 7730 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7731 report_prefix_pop(); 7732 7733 vmcs_write(ENT_CONTROLS, entry_ctrl_saved | ENT_GUEST_64); 7734 vmcs_write(HOST_RIP, rip_saved); 7735 vmcs_write(HOST_CR4, cr4_saved); 7736 7737 /* Restore host's active RIP and CR4 values. */ 7738 report_prefix_pushf("restore host state"); 7739 test_vmx_vmlaunch(0); 7740 report_prefix_pop(); 7741 } 7742 } 7743 7744 /* 7745 * Check that the virtual CPU checks the VMX Host State Area as 7746 * documented in the Intel SDM. 7747 */ 7748 static void vmx_host_state_area_test(void) 7749 { 7750 /* 7751 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 7752 * fail due to invalid guest state, should we make it that 7753 * far. 7754 */ 7755 vmcs_write(GUEST_RFLAGS, 0); 7756 7757 test_host_ctl_regs(); 7758 7759 test_canonical(HOST_SYSENTER_ESP, "HOST_SYSENTER_ESP", true); 7760 test_canonical(HOST_SYSENTER_EIP, "HOST_SYSENTER_EIP", true); 7761 7762 test_host_efer(); 7763 test_load_host_pat(); 7764 test_host_segment_regs(); 7765 test_host_desc_tables(); 7766 test_host_addr_size(); 7767 test_load_host_perf_global_ctrl(); 7768 } 7769 7770 /* 7771 * If the "load debug controls" VM-entry control is 1, bits 63:32 in 7772 * the DR7 field must be 0. 7773 * 7774 * [Intel SDM] 7775 */ 7776 static void test_guest_dr7(void) 7777 { 7778 u32 ent_saved = vmcs_read(ENT_CONTROLS); 7779 u64 dr7_saved = vmcs_read(GUEST_DR7); 7780 u64 val; 7781 int i; 7782 7783 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS) { 7784 vmcs_clear_bits(ENT_CONTROLS, ENT_LOAD_DBGCTLS); 7785 for (i = 0; i < 64; i++) { 7786 val = 1ull << i; 7787 vmcs_write(GUEST_DR7, val); 7788 test_guest_state("ENT_LOAD_DBGCTLS disabled", false, 7789 val, "GUEST_DR7"); 7790 } 7791 } 7792 if (ctrl_enter_rev.clr & ENT_LOAD_DBGCTLS) { 7793 vmcs_set_bits(ENT_CONTROLS, ENT_LOAD_DBGCTLS); 7794 for (i = 0; i < 64; i++) { 7795 val = 1ull << i; 7796 vmcs_write(GUEST_DR7, val); 7797 test_guest_state("ENT_LOAD_DBGCTLS enabled", i >= 32, 7798 val, "GUEST_DR7"); 7799 } 7800 } 7801 vmcs_write(GUEST_DR7, dr7_saved); 7802 vmcs_write(ENT_CONTROLS, ent_saved); 7803 } 7804 7805 /* 7806 * If the "load IA32_PAT" VM-entry control is 1, the value of the field 7807 * for the IA32_PAT MSR must be one that could be written by WRMSR 7808 * without fault at CPL 0. Specifically, each of the 8 bytes in the 7809 * field must have one of the values 0 (UC), 1 (WC), 4 (WT), 5 (WP), 7810 * 6 (WB), or 7 (UC-). 7811 * 7812 * [Intel SDM] 7813 */ 7814 static void test_load_guest_pat(void) 7815 { 7816 /* 7817 * "load IA32_PAT" VM-entry control 7818 */ 7819 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 7820 report_skip("%s : \"Load-IA32-PAT\" entry control not supported", __func__); 7821 return; 7822 } 7823 7824 test_pat(GUEST_PAT, "GUEST_PAT", ENT_CONTROLS, ENT_LOAD_PAT); 7825 } 7826 7827 #define MSR_IA32_BNDCFGS_RSVD_MASK 0x00000ffc 7828 7829 /* 7830 * If the "load IA32_BNDCFGS" VM-entry control is 1, the following 7831 * checks are performed on the field for the IA32_BNDCFGS MSR: 7832 * 7833 * - Bits reserved in the IA32_BNDCFGS MSR must be 0. 7834 * - The linear address in bits 63:12 must be canonical. 7835 * 7836 * [Intel SDM] 7837 */ 7838 static void test_load_guest_bndcfgs(void) 7839 { 7840 u64 bndcfgs_saved = vmcs_read(GUEST_BNDCFGS); 7841 u64 bndcfgs; 7842 7843 if (!(ctrl_enter_rev.clr & ENT_LOAD_BNDCFGS)) { 7844 report_skip("%s : \"Load-IA32-BNDCFGS\" entry control not supported", __func__); 7845 return; 7846 } 7847 7848 vmcs_clear_bits(ENT_CONTROLS, ENT_LOAD_BNDCFGS); 7849 7850 vmcs_write(GUEST_BNDCFGS, NONCANONICAL); 7851 test_guest_state("ENT_LOAD_BNDCFGS disabled", false, 7852 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7853 bndcfgs = bndcfgs_saved | MSR_IA32_BNDCFGS_RSVD_MASK; 7854 vmcs_write(GUEST_BNDCFGS, bndcfgs); 7855 test_guest_state("ENT_LOAD_BNDCFGS disabled", false, 7856 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7857 7858 vmcs_set_bits(ENT_CONTROLS, ENT_LOAD_BNDCFGS); 7859 7860 vmcs_write(GUEST_BNDCFGS, NONCANONICAL); 7861 test_guest_state("ENT_LOAD_BNDCFGS enabled", true, 7862 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7863 bndcfgs = bndcfgs_saved | MSR_IA32_BNDCFGS_RSVD_MASK; 7864 vmcs_write(GUEST_BNDCFGS, bndcfgs); 7865 test_guest_state("ENT_LOAD_BNDCFGS enabled", true, 7866 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7867 7868 vmcs_write(GUEST_BNDCFGS, bndcfgs_saved); 7869 } 7870 7871 #define GUEST_SEG_UNUSABLE_MASK (1u << 16) 7872 #define GUEST_SEG_SEL_TI_MASK (1u << 2) 7873 7874 7875 #define TEST_SEGMENT_SEL(test, xfail, sel, val) \ 7876 do { \ 7877 vmcs_write(sel, val); \ 7878 test_guest_state(test " segment", xfail, val, xstr(sel)); \ 7879 } while (0) 7880 7881 #define TEST_INVALID_SEG_SEL(sel, val) \ 7882 TEST_SEGMENT_SEL("Invalid: " xstr(val), true, sel, val); 7883 7884 #define TEST_VALID_SEG_SEL(sel, val) \ 7885 TEST_SEGMENT_SEL("Valid: " xstr(val), false, sel, val); 7886 7887 /* 7888 * The following checks are done on the Selector field of the Guest Segment 7889 * Registers: 7890 * - TR. The TI flag (bit 2) must be 0. 7891 * - LDTR. If LDTR is usable, the TI flag (bit 2) must be 0. 7892 * - SS. If the guest will not be virtual-8086 and the "unrestricted 7893 * guest" VM-execution control is 0, the RPL (bits 1:0) must equal 7894 * the RPL of the selector field for CS. 7895 * 7896 * [Intel SDM] 7897 */ 7898 static void test_guest_segment_sel_fields(void) 7899 { 7900 u16 sel_saved; 7901 u32 ar_saved; 7902 u32 cpu_ctrl0_saved; 7903 u32 cpu_ctrl1_saved; 7904 u16 cs_rpl_bits; 7905 7906 /* 7907 * Test for GUEST_SEL_TR 7908 */ 7909 sel_saved = vmcs_read(GUEST_SEL_TR); 7910 TEST_INVALID_SEG_SEL(GUEST_SEL_TR, sel_saved | GUEST_SEG_SEL_TI_MASK); 7911 vmcs_write(GUEST_SEL_TR, sel_saved); 7912 7913 /* 7914 * Test for GUEST_SEL_LDTR 7915 */ 7916 sel_saved = vmcs_read(GUEST_SEL_LDTR); 7917 ar_saved = vmcs_read(GUEST_AR_LDTR); 7918 /* LDTR is set unusable */ 7919 vmcs_write(GUEST_AR_LDTR, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7920 TEST_VALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved | GUEST_SEG_SEL_TI_MASK); 7921 TEST_VALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved & ~GUEST_SEG_SEL_TI_MASK); 7922 /* LDTR is set usable */ 7923 vmcs_write(GUEST_AR_LDTR, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7924 TEST_INVALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved | GUEST_SEG_SEL_TI_MASK); 7925 7926 TEST_VALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved & ~GUEST_SEG_SEL_TI_MASK); 7927 7928 vmcs_write(GUEST_AR_LDTR, ar_saved); 7929 vmcs_write(GUEST_SEL_LDTR, sel_saved); 7930 7931 /* 7932 * Test for GUEST_SEL_SS 7933 */ 7934 cpu_ctrl0_saved = vmcs_read(CPU_EXEC_CTRL0); 7935 cpu_ctrl1_saved = vmcs_read(CPU_EXEC_CTRL1); 7936 ar_saved = vmcs_read(GUEST_AR_SS); 7937 /* Turn off "unrestricted guest" vm-execution control */ 7938 vmcs_write(CPU_EXEC_CTRL1, cpu_ctrl1_saved & ~CPU_URG); 7939 cs_rpl_bits = vmcs_read(GUEST_SEL_CS) & 0x3; 7940 sel_saved = vmcs_read(GUEST_SEL_SS); 7941 TEST_INVALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 7942 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 7943 /* Make SS usable if it's unusable or vice-versa */ 7944 if (ar_saved & GUEST_SEG_UNUSABLE_MASK) 7945 vmcs_write(GUEST_AR_SS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7946 else 7947 vmcs_write(GUEST_AR_SS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7948 TEST_INVALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 7949 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 7950 7951 /* Need a valid EPTP as the passing case fully enters the guest. */ 7952 if (enable_unrestricted_guest(true)) 7953 goto skip_ss_tests; 7954 7955 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 7956 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 7957 7958 /* Make SS usable if it's unusable or vice-versa */ 7959 if (vmcs_read(GUEST_AR_SS) & GUEST_SEG_UNUSABLE_MASK) 7960 vmcs_write(GUEST_AR_SS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7961 else 7962 vmcs_write(GUEST_AR_SS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7963 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 7964 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 7965 skip_ss_tests: 7966 7967 vmcs_write(GUEST_AR_SS, ar_saved); 7968 vmcs_write(GUEST_SEL_SS, sel_saved); 7969 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrl0_saved); 7970 vmcs_write(CPU_EXEC_CTRL1, cpu_ctrl1_saved); 7971 } 7972 7973 #define TEST_SEGMENT_BASE_ADDR_UPPER_BITS(xfail, seg_base) \ 7974 do { \ 7975 addr_saved = vmcs_read(seg_base); \ 7976 for (i = 32; i < 63; i = i + 4) { \ 7977 addr = addr_saved | 1ull << i; \ 7978 vmcs_write(seg_base, addr); \ 7979 test_guest_state("seg.BASE[63:32] != 0, usable = " xstr(xfail), \ 7980 xfail, addr, xstr(seg_base)); \ 7981 } \ 7982 vmcs_write(seg_base, addr_saved); \ 7983 } while (0) 7984 7985 #define TEST_SEGMENT_BASE_ADDR_CANONICAL(xfail, seg_base) \ 7986 do { \ 7987 addr_saved = vmcs_read(seg_base); \ 7988 vmcs_write(seg_base, NONCANONICAL); \ 7989 test_guest_state("seg.BASE non-canonical, usable = " xstr(xfail), \ 7990 xfail, NONCANONICAL, xstr(seg_base)); \ 7991 vmcs_write(seg_base, addr_saved); \ 7992 } while (0) 7993 7994 /* 7995 * The following checks are done on the Base Address field of the Guest 7996 * Segment Registers on processors that support Intel 64 architecture: 7997 * - TR, FS, GS : The address must be canonical. 7998 * - LDTR : If LDTR is usable, the address must be canonical. 7999 * - CS : Bits 63:32 of the address must be zero. 8000 * - SS, DS, ES : If the register is usable, bits 63:32 of the address 8001 * must be zero. 8002 * 8003 * [Intel SDM] 8004 */ 8005 static void test_guest_segment_base_addr_fields(void) 8006 { 8007 u64 addr_saved; 8008 u64 addr; 8009 u32 ar_saved; 8010 int i; 8011 8012 /* 8013 * The address of TR, FS, GS and LDTR must be canonical. 8014 */ 8015 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_TR); 8016 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_FS); 8017 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_GS); 8018 ar_saved = vmcs_read(GUEST_AR_LDTR); 8019 /* Make LDTR unusable */ 8020 vmcs_write(GUEST_AR_LDTR, ar_saved | GUEST_SEG_UNUSABLE_MASK); 8021 TEST_SEGMENT_BASE_ADDR_CANONICAL(false, GUEST_BASE_LDTR); 8022 /* Make LDTR usable */ 8023 vmcs_write(GUEST_AR_LDTR, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 8024 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_LDTR); 8025 8026 vmcs_write(GUEST_AR_LDTR, ar_saved); 8027 8028 /* 8029 * Bits 63:32 in CS, SS, DS and ES base address must be zero 8030 */ 8031 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_CS); 8032 ar_saved = vmcs_read(GUEST_AR_SS); 8033 /* Make SS unusable */ 8034 vmcs_write(GUEST_AR_SS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 8035 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(false, GUEST_BASE_SS); 8036 /* Make SS usable */ 8037 vmcs_write(GUEST_AR_SS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 8038 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_SS); 8039 vmcs_write(GUEST_AR_SS, ar_saved); 8040 8041 ar_saved = vmcs_read(GUEST_AR_DS); 8042 /* Make DS unusable */ 8043 vmcs_write(GUEST_AR_DS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 8044 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(false, GUEST_BASE_DS); 8045 /* Make DS usable */ 8046 vmcs_write(GUEST_AR_DS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 8047 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_DS); 8048 vmcs_write(GUEST_AR_DS, ar_saved); 8049 8050 ar_saved = vmcs_read(GUEST_AR_ES); 8051 /* Make ES unusable */ 8052 vmcs_write(GUEST_AR_ES, ar_saved | GUEST_SEG_UNUSABLE_MASK); 8053 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(false, GUEST_BASE_ES); 8054 /* Make ES usable */ 8055 vmcs_write(GUEST_AR_ES, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 8056 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_ES); 8057 vmcs_write(GUEST_AR_ES, ar_saved); 8058 } 8059 8060 /* 8061 * Check that the virtual CPU checks the VMX Guest State Area as 8062 * documented in the Intel SDM. 8063 */ 8064 static void vmx_guest_state_area_test(void) 8065 { 8066 vmx_set_test_stage(1); 8067 test_set_guest(guest_state_test_main); 8068 8069 /* 8070 * The IA32_SYSENTER_ESP field and the IA32_SYSENTER_EIP field 8071 * must each contain a canonical address. 8072 */ 8073 test_canonical(GUEST_SYSENTER_ESP, "GUEST_SYSENTER_ESP", false); 8074 test_canonical(GUEST_SYSENTER_EIP, "GUEST_SYSENTER_EIP", false); 8075 8076 test_guest_dr7(); 8077 test_load_guest_pat(); 8078 test_guest_efer(); 8079 test_load_guest_perf_global_ctrl(); 8080 test_load_guest_bndcfgs(); 8081 8082 test_guest_segment_sel_fields(); 8083 test_guest_segment_base_addr_fields(); 8084 8085 test_canonical(GUEST_BASE_GDTR, "GUEST_BASE_GDTR", false); 8086 test_canonical(GUEST_BASE_IDTR, "GUEST_BASE_IDTR", false); 8087 8088 u32 guest_desc_limit_saved = vmcs_read(GUEST_LIMIT_GDTR); 8089 int i; 8090 for (i = 16; i <= 31; i++) { 8091 u32 tmp = guest_desc_limit_saved | (1ull << i); 8092 vmcs_write(GUEST_LIMIT_GDTR, tmp); 8093 test_guest_state("GDT.limit > 0xffff", true, tmp, "GUEST_LIMIT_GDTR"); 8094 } 8095 vmcs_write(GUEST_LIMIT_GDTR, guest_desc_limit_saved); 8096 8097 guest_desc_limit_saved = vmcs_read(GUEST_LIMIT_IDTR); 8098 for (i = 16; i <= 31; i++) { 8099 u32 tmp = guest_desc_limit_saved | (1ull << i); 8100 vmcs_write(GUEST_LIMIT_IDTR, tmp); 8101 test_guest_state("IDT.limit > 0xffff", true, tmp, "GUEST_LIMIT_IDTR"); 8102 } 8103 vmcs_write(GUEST_LIMIT_IDTR, guest_desc_limit_saved); 8104 8105 /* 8106 * Let the guest finish execution 8107 */ 8108 vmx_set_test_stage(2); 8109 enter_guest(); 8110 } 8111 8112 extern void unrestricted_guest_main(void); 8113 asm (".code32\n" 8114 "unrestricted_guest_main:\n" 8115 "vmcall\n" 8116 "nop\n" 8117 "mov $1, %edi\n" 8118 "call hypercall\n" 8119 ".code64\n"); 8120 8121 static void setup_unrestricted_guest(void) 8122 { 8123 vmcs_write(GUEST_CR0, vmcs_read(GUEST_CR0) & ~(X86_CR0_PG)); 8124 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) & ~ENT_GUEST_64); 8125 vmcs_write(GUEST_EFER, vmcs_read(GUEST_EFER) & ~EFER_LMA); 8126 vmcs_write(GUEST_RIP, virt_to_phys(unrestricted_guest_main)); 8127 } 8128 8129 static void unsetup_unrestricted_guest(void) 8130 { 8131 vmcs_write(GUEST_CR0, vmcs_read(GUEST_CR0) | X86_CR0_PG); 8132 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) | ENT_GUEST_64); 8133 vmcs_write(GUEST_EFER, vmcs_read(GUEST_EFER) | EFER_LMA); 8134 vmcs_write(GUEST_RIP, (u64) phys_to_virt(vmcs_read(GUEST_RIP))); 8135 vmcs_write(GUEST_RSP, (u64) phys_to_virt(vmcs_read(GUEST_RSP))); 8136 } 8137 8138 /* 8139 * If "unrestricted guest" secondary VM-execution control is set, guests 8140 * can run in unpaged protected mode. 8141 */ 8142 static void vmentry_unrestricted_guest_test(void) 8143 { 8144 if (enable_unrestricted_guest(true)) { 8145 report_skip("%s: \"Unrestricted guest\" exec control not supported", __func__); 8146 return; 8147 } 8148 8149 test_set_guest(unrestricted_guest_main); 8150 setup_unrestricted_guest(); 8151 test_guest_state("Unrestricted guest test", false, CPU_URG, "CPU_URG"); 8152 8153 /* 8154 * Let the guest finish execution as a regular guest 8155 */ 8156 unsetup_unrestricted_guest(); 8157 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) & ~CPU_URG); 8158 enter_guest(); 8159 } 8160 8161 static bool valid_vmcs_for_vmentry(void) 8162 { 8163 struct vmcs *current_vmcs = NULL; 8164 8165 if (vmcs_save(¤t_vmcs)) 8166 return false; 8167 8168 return current_vmcs && !current_vmcs->hdr.shadow_vmcs; 8169 } 8170 8171 static void try_vmentry_in_movss_shadow(void) 8172 { 8173 u32 vm_inst_err; 8174 u32 flags; 8175 bool early_failure = false; 8176 u32 expected_flags = X86_EFLAGS_FIXED; 8177 bool valid_vmcs = valid_vmcs_for_vmentry(); 8178 8179 expected_flags |= valid_vmcs ? X86_EFLAGS_ZF : X86_EFLAGS_CF; 8180 8181 /* 8182 * Indirectly set VM_INST_ERR to 12 ("VMREAD/VMWRITE from/to 8183 * unsupported VMCS component"). 8184 */ 8185 vmcs_write(~0u, 0); 8186 8187 __asm__ __volatile__ ("mov %[host_rsp], %%edx;" 8188 "vmwrite %%rsp, %%rdx;" 8189 "mov 0f, %%rax;" 8190 "mov %[host_rip], %%edx;" 8191 "vmwrite %%rax, %%rdx;" 8192 "mov $-1, %%ah;" 8193 "sahf;" 8194 "mov %%ss, %%ax;" 8195 "mov %%ax, %%ss;" 8196 "vmlaunch;" 8197 "mov $1, %[early_failure];" 8198 "0: lahf;" 8199 "movzbl %%ah, %[flags]" 8200 : [early_failure] "+r" (early_failure), 8201 [flags] "=&a" (flags) 8202 : [host_rsp] "i" (HOST_RSP), 8203 [host_rip] "i" (HOST_RIP) 8204 : "rdx", "cc", "memory"); 8205 vm_inst_err = vmcs_read(VMX_INST_ERROR); 8206 8207 report(early_failure, "Early VM-entry failure"); 8208 report(flags == expected_flags, "RFLAGS[8:0] is %x (actual %x)", 8209 expected_flags, flags); 8210 if (valid_vmcs) 8211 report(vm_inst_err == VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, 8212 "VM-instruction error is %d (actual %d)", 8213 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, vm_inst_err); 8214 } 8215 8216 static void vmentry_movss_shadow_test(void) 8217 { 8218 struct vmcs *orig_vmcs; 8219 8220 TEST_ASSERT(!vmcs_save(&orig_vmcs)); 8221 8222 /* 8223 * Set the launched flag on the current VMCS to verify the correct 8224 * error priority, below. 8225 */ 8226 test_set_guest(v2_null_test_guest); 8227 enter_guest(); 8228 8229 /* 8230 * With bit 1 of the guest's RFLAGS clear, VM-entry should 8231 * fail due to invalid guest state (if we make it that far). 8232 */ 8233 vmcs_write(GUEST_RFLAGS, 0); 8234 8235 /* 8236 * "VM entry with events blocked by MOV SS" takes precedence over 8237 * "VMLAUNCH with non-clear VMCS." 8238 */ 8239 report_prefix_push("valid current-VMCS"); 8240 try_vmentry_in_movss_shadow(); 8241 report_prefix_pop(); 8242 8243 /* 8244 * VMfailInvalid takes precedence over "VM entry with events 8245 * blocked by MOV SS." 8246 */ 8247 TEST_ASSERT(!vmcs_clear(orig_vmcs)); 8248 report_prefix_push("no current-VMCS"); 8249 try_vmentry_in_movss_shadow(); 8250 report_prefix_pop(); 8251 8252 TEST_ASSERT(!make_vmcs_current(orig_vmcs)); 8253 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 8254 } 8255 8256 static void vmx_ldtr_test_guest(void) 8257 { 8258 u16 ldtr = sldt(); 8259 8260 report(ldtr == NP_SEL, "Expected %x for L2 LDTR selector (got %x)", 8261 NP_SEL, ldtr); 8262 } 8263 8264 /* 8265 * Ensure that the L1 LDTR is set to 0 on VM-exit. 8266 */ 8267 static void vmx_ldtr_test(void) 8268 { 8269 const u8 ldt_ar = 0x82; /* Present LDT */ 8270 u16 sel = FIRST_SPARE_SEL; 8271 8272 /* Set up a non-zero L1 LDTR prior to VM-entry. */ 8273 set_gdt_entry(sel, 0, 0, ldt_ar, 0); 8274 lldt(sel); 8275 8276 test_set_guest(vmx_ldtr_test_guest); 8277 /* 8278 * Set up a different LDTR for L2. The actual GDT contents are 8279 * irrelevant, since we stuff the hidden descriptor state 8280 * straight into the VMCS rather than reading it from the GDT. 8281 */ 8282 vmcs_write(GUEST_SEL_LDTR, NP_SEL); 8283 vmcs_write(GUEST_AR_LDTR, ldt_ar); 8284 enter_guest(); 8285 8286 /* 8287 * VM-exit should clear LDTR (and make it unusable, but we 8288 * won't verify that here). 8289 */ 8290 sel = sldt(); 8291 report(!sel, "Expected 0 for L1 LDTR selector (got %x)", sel); 8292 } 8293 8294 static void vmx_single_vmcall_guest(void) 8295 { 8296 vmcall(); 8297 } 8298 8299 static void vmx_cr_load_test(void) 8300 { 8301 unsigned long cr3, cr4, orig_cr3, orig_cr4; 8302 u32 ctrls[2] = {0}; 8303 pgd_t *pml5; 8304 8305 orig_cr4 = read_cr4(); 8306 orig_cr3 = read_cr3(); 8307 8308 if (!this_cpu_has(X86_FEATURE_PCID)) { 8309 report_skip("%s : PCID not detected", __func__); 8310 return; 8311 } 8312 if (!this_cpu_has(X86_FEATURE_MCE)) { 8313 report_skip("%s : MCE not detected", __func__); 8314 return; 8315 } 8316 8317 TEST_ASSERT(!(orig_cr3 & X86_CR3_PCID_MASK)); 8318 8319 /* Enable PCID for L1. */ 8320 cr4 = orig_cr4 | X86_CR4_PCIDE; 8321 cr3 = orig_cr3 | 0x1; 8322 TEST_ASSERT(!write_cr4_safe(cr4)); 8323 write_cr3(cr3); 8324 8325 test_set_guest(vmx_single_vmcall_guest); 8326 vmcs_write(HOST_CR4, cr4); 8327 vmcs_write(HOST_CR3, cr3); 8328 enter_guest(); 8329 8330 /* 8331 * No exception is expected. 8332 * 8333 * NB. KVM loads the last guest write to CR4 into CR4 read 8334 * shadow. In order to trigger an exit to KVM, we can toggle a 8335 * bit that is owned by KVM. We use CR4.MCE, which shall 8336 * have no side effect because normally no guest MCE (e.g., as the 8337 * result of bad memory) would happen during this test. 8338 */ 8339 TEST_ASSERT(!write_cr4_safe(cr4 ^ X86_CR4_MCE)); 8340 8341 /* Cleanup L1 state. */ 8342 write_cr3(orig_cr3); 8343 TEST_ASSERT(!write_cr4_safe(orig_cr4)); 8344 8345 if (!this_cpu_has(X86_FEATURE_LA57)) 8346 goto done; 8347 8348 /* 8349 * Allocate a full page for PML5 to guarantee alignment, though only 8350 * the first entry needs to be filled (the test's virtual addresses 8351 * most definitely do not have any of bits 56:48 set). 8352 */ 8353 pml5 = alloc_page(); 8354 *pml5 = orig_cr3 | PT_PRESENT_MASK | PT_WRITABLE_MASK; 8355 8356 /* 8357 * Transition to/from 5-level paging in the host via VM-Exit. CR4.LA57 8358 * can't be toggled while long is active via MOV CR4, but there are no 8359 * such restrictions on VM-Exit. 8360 */ 8361 lol_5level: 8362 vmcs_write(HOST_CR4, orig_cr4 | X86_CR4_LA57); 8363 vmcs_write(HOST_CR3, virt_to_phys(pml5)); 8364 enter_guest(); 8365 8366 /* 8367 * VMREAD with a memory operand to verify KVM detects the LA57 change, 8368 * e.g. uses the correct guest root level in gva_to_gpa(). 8369 */ 8370 TEST_ASSERT(vmcs_readm(HOST_CR3) == virt_to_phys(pml5)); 8371 TEST_ASSERT(vmcs_readm(HOST_CR4) == (orig_cr4 | X86_CR4_LA57)); 8372 8373 vmcs_write(HOST_CR4, orig_cr4); 8374 vmcs_write(HOST_CR3, orig_cr3); 8375 enter_guest(); 8376 8377 TEST_ASSERT(vmcs_readm(HOST_CR3) == orig_cr3); 8378 TEST_ASSERT(vmcs_readm(HOST_CR4) == orig_cr4); 8379 8380 /* 8381 * And now do the same LA57 shenanigans with EPT enabled. KVM uses 8382 * two separate MMUs when L1 uses TDP, whereas the above shadow paging 8383 * version shares an MMU between L1 and L2. 8384 * 8385 * If the saved execution controls are non-zero then the EPT version 8386 * has already run. In that case, restore the old controls. If EPT 8387 * setup fails, e.g. EPT isn't supported, fall through and finish up. 8388 */ 8389 if (ctrls[0]) { 8390 vmcs_write(CPU_EXEC_CTRL0, ctrls[0]); 8391 vmcs_write(CPU_EXEC_CTRL1, ctrls[1]); 8392 } else if (!setup_ept(false)) { 8393 ctrls[0] = vmcs_read(CPU_EXEC_CTRL0); 8394 ctrls[1] = vmcs_read(CPU_EXEC_CTRL1); 8395 goto lol_5level; 8396 } 8397 8398 free_page(pml5); 8399 8400 done: 8401 skip_exit_vmcall(); 8402 enter_guest(); 8403 } 8404 8405 static void vmx_cr4_osxsave_test_guest(void) 8406 { 8407 write_cr4(read_cr4() & ~X86_CR4_OSXSAVE); 8408 } 8409 8410 /* 8411 * Ensure that kvm recalculates the L1 guest's CPUID.01H:ECX.OSXSAVE 8412 * after VM-exit from an L2 guest that sets CR4.OSXSAVE to a different 8413 * value than in L1. 8414 */ 8415 static void vmx_cr4_osxsave_test(void) 8416 { 8417 if (!this_cpu_has(X86_FEATURE_XSAVE)) { 8418 report_skip("%s : XSAVE not detected", __func__); 8419 return; 8420 } 8421 8422 if (!(read_cr4() & X86_CR4_OSXSAVE)) { 8423 unsigned long cr4 = read_cr4() | X86_CR4_OSXSAVE; 8424 8425 write_cr4(cr4); 8426 vmcs_write(GUEST_CR4, cr4); 8427 vmcs_write(HOST_CR4, cr4); 8428 } 8429 8430 TEST_ASSERT(this_cpu_has(X86_FEATURE_OSXSAVE)); 8431 8432 test_set_guest(vmx_cr4_osxsave_test_guest); 8433 enter_guest(); 8434 8435 TEST_ASSERT(this_cpu_has(X86_FEATURE_OSXSAVE)); 8436 } 8437 8438 static void vmx_nm_test_guest(void) 8439 { 8440 write_cr0(read_cr0() | X86_CR0_TS); 8441 asm volatile("fnop"); 8442 } 8443 8444 static void check_nm_exit(const char *test) 8445 { 8446 u32 reason = vmcs_read(EXI_REASON); 8447 u32 intr_info = vmcs_read(EXI_INTR_INFO); 8448 const u32 expected = INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 8449 NM_VECTOR; 8450 8451 report(reason == VMX_EXC_NMI && intr_info == expected, "%s", test); 8452 } 8453 8454 /* 8455 * This test checks that: 8456 * 8457 * (a) If L2 launches with CR0.TS clear, but later sets CR0.TS, then 8458 * a subsequent #NM VM-exit is reflected to L1. 8459 * 8460 * (b) If L2 launches with CR0.TS clear and CR0.EM set, then a 8461 * subsequent #NM VM-exit is reflected to L1. 8462 */ 8463 static void vmx_nm_test(void) 8464 { 8465 unsigned long cr0 = read_cr0(); 8466 8467 test_set_guest(vmx_nm_test_guest); 8468 8469 /* 8470 * L1 wants to intercept #NM exceptions encountered in L2. 8471 */ 8472 vmcs_write(EXC_BITMAP, 1 << NM_VECTOR); 8473 8474 /* 8475 * Launch L2 with CR0.TS clear, but don't claim host ownership of 8476 * any CR0 bits. L2 will set CR0.TS and then try to execute fnop, 8477 * which will raise #NM. L0 should reflect the #NM VM-exit to L1. 8478 */ 8479 vmcs_write(CR0_MASK, 0); 8480 vmcs_write(GUEST_CR0, cr0 & ~X86_CR0_TS); 8481 enter_guest(); 8482 check_nm_exit("fnop with CR0.TS set in L2 triggers #NM VM-exit to L1"); 8483 8484 /* 8485 * Re-enter L2 at the fnop instruction, with CR0.TS clear but 8486 * CR0.EM set. The fnop will still raise #NM, and L0 should 8487 * reflect the #NM VM-exit to L1. 8488 */ 8489 vmcs_write(GUEST_CR0, (cr0 & ~X86_CR0_TS) | X86_CR0_EM); 8490 enter_guest(); 8491 check_nm_exit("fnop with CR0.EM set in L2 triggers #NM VM-exit to L1"); 8492 8493 /* 8494 * Re-enter L2 at the fnop instruction, with both CR0.TS and 8495 * CR0.EM clear. There will be no #NM, and the L2 guest should 8496 * exit normally. 8497 */ 8498 vmcs_write(GUEST_CR0, cr0 & ~(X86_CR0_TS | X86_CR0_EM)); 8499 enter_guest(); 8500 } 8501 8502 bool vmx_pending_event_ipi_fired; 8503 static void vmx_pending_event_ipi_isr(isr_regs_t *regs) 8504 { 8505 vmx_pending_event_ipi_fired = true; 8506 eoi(); 8507 } 8508 8509 bool vmx_pending_event_guest_run; 8510 static void vmx_pending_event_guest(void) 8511 { 8512 vmcall(); 8513 vmx_pending_event_guest_run = true; 8514 } 8515 8516 static void vmx_pending_event_test_core(bool guest_hlt) 8517 { 8518 int ipi_vector = 0xf1; 8519 8520 vmx_pending_event_ipi_fired = false; 8521 handle_irq(ipi_vector, vmx_pending_event_ipi_isr); 8522 8523 vmx_pending_event_guest_run = false; 8524 test_set_guest(vmx_pending_event_guest); 8525 8526 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 8527 8528 enter_guest(); 8529 skip_exit_vmcall(); 8530 8531 if (guest_hlt) 8532 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8533 8534 irq_disable(); 8535 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | 8536 APIC_DM_FIXED | ipi_vector, 8537 0); 8538 8539 enter_guest(); 8540 8541 assert_exit_reason(VMX_EXTINT); 8542 report(!vmx_pending_event_guest_run, 8543 "Guest did not run before host received IPI"); 8544 8545 irq_enable(); 8546 asm volatile ("nop"); 8547 irq_disable(); 8548 report(vmx_pending_event_ipi_fired, 8549 "Got pending interrupt after IRQ enabled"); 8550 8551 if (guest_hlt) 8552 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 8553 8554 enter_guest(); 8555 report(vmx_pending_event_guest_run, 8556 "Guest finished running when no interrupt"); 8557 } 8558 8559 static void vmx_pending_event_test(void) 8560 { 8561 vmx_pending_event_test_core(false); 8562 } 8563 8564 static void vmx_pending_event_hlt_test(void) 8565 { 8566 vmx_pending_event_test_core(true); 8567 } 8568 8569 static int vmx_window_test_db_count; 8570 8571 static void vmx_window_test_db_handler(struct ex_regs *regs) 8572 { 8573 vmx_window_test_db_count++; 8574 } 8575 8576 static void vmx_nmi_window_test_guest(void) 8577 { 8578 handle_exception(DB_VECTOR, vmx_window_test_db_handler); 8579 8580 asm volatile("vmcall\n\t" 8581 "nop\n\t"); 8582 8583 handle_exception(DB_VECTOR, NULL); 8584 } 8585 8586 static void verify_nmi_window_exit(u64 rip) 8587 { 8588 u32 exit_reason = vmcs_read(EXI_REASON); 8589 8590 report(exit_reason == VMX_NMI_WINDOW, 8591 "Exit reason (%d) is 'NMI window'", exit_reason); 8592 report(vmcs_read(GUEST_RIP) == rip, "RIP (%#lx) is %#lx", 8593 vmcs_read(GUEST_RIP), rip); 8594 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 8595 } 8596 8597 static void vmx_nmi_window_test(void) 8598 { 8599 u64 nop_addr; 8600 void *db_fault_addr = get_idt_addr(&boot_idt[DB_VECTOR]); 8601 8602 if (!(ctrl_pin_rev.clr & PIN_VIRT_NMI)) { 8603 report_skip("%s : \"Virtual NMIs\" exec control not supported", __func__); 8604 return; 8605 } 8606 8607 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 8608 report_skip("%s : \"NMI-window exiting\" exec control not supported", __func__); 8609 return; 8610 } 8611 8612 vmx_window_test_db_count = 0; 8613 8614 report_prefix_push("NMI-window"); 8615 test_set_guest(vmx_nmi_window_test_guest); 8616 vmcs_set_bits(PIN_CONTROLS, PIN_VIRT_NMI); 8617 enter_guest(); 8618 skip_exit_vmcall(); 8619 nop_addr = vmcs_read(GUEST_RIP); 8620 8621 /* 8622 * Ask for "NMI-window exiting," and expect an immediate VM-exit. 8623 * RIP will not advance. 8624 */ 8625 report_prefix_push("active, no blocking"); 8626 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 8627 enter_guest(); 8628 verify_nmi_window_exit(nop_addr); 8629 report_prefix_pop(); 8630 8631 /* 8632 * Ask for "NMI-window exiting" in a MOV-SS shadow, and expect 8633 * a VM-exit on the next instruction after the nop. (The nop 8634 * is one byte.) 8635 */ 8636 report_prefix_push("active, blocking by MOV-SS"); 8637 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 8638 enter_guest(); 8639 verify_nmi_window_exit(nop_addr + 1); 8640 report_prefix_pop(); 8641 8642 /* 8643 * Ask for "NMI-window exiting" (with event injection), and 8644 * expect a VM-exit after the event is injected. (RIP should 8645 * be at the address specified in the IDT entry for #DB.) 8646 */ 8647 report_prefix_push("active, no blocking, injecting #DB"); 8648 vmcs_write(ENT_INTR_INFO, 8649 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 8650 enter_guest(); 8651 verify_nmi_window_exit((u64)db_fault_addr); 8652 report_prefix_pop(); 8653 8654 /* 8655 * Ask for "NMI-window exiting" with NMI blocking, and expect 8656 * a VM-exit after the next IRET (i.e. after the #DB handler 8657 * returns). So, RIP should be back at one byte past the nop. 8658 */ 8659 report_prefix_push("active, blocking by NMI"); 8660 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_NMI); 8661 enter_guest(); 8662 verify_nmi_window_exit(nop_addr + 1); 8663 report(vmx_window_test_db_count == 1, 8664 "#DB handler executed once (actual %d times)", 8665 vmx_window_test_db_count); 8666 report_prefix_pop(); 8667 8668 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 8669 report_skip("CPU does not support activity state HLT."); 8670 } else { 8671 /* 8672 * Ask for "NMI-window exiting" when entering activity 8673 * state HLT, and expect an immediate VM-exit. RIP is 8674 * still one byte past the nop. 8675 */ 8676 report_prefix_push("halted, no blocking"); 8677 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8678 enter_guest(); 8679 verify_nmi_window_exit(nop_addr + 1); 8680 report_prefix_pop(); 8681 8682 /* 8683 * Ask for "NMI-window exiting" when entering activity 8684 * state HLT (with event injection), and expect a 8685 * VM-exit after the event is injected. (RIP should be 8686 * at the address specified in the IDT entry for #DB.) 8687 */ 8688 report_prefix_push("halted, no blocking, injecting #DB"); 8689 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8690 vmcs_write(ENT_INTR_INFO, 8691 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 8692 DB_VECTOR); 8693 enter_guest(); 8694 verify_nmi_window_exit((u64)db_fault_addr); 8695 report_prefix_pop(); 8696 } 8697 8698 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 8699 enter_guest(); 8700 report_prefix_pop(); 8701 } 8702 8703 static void vmx_intr_window_test_guest(void) 8704 { 8705 handle_exception(DB_VECTOR, vmx_window_test_db_handler); 8706 8707 /* 8708 * The two consecutive STIs are to ensure that only the first 8709 * one has a shadow. Note that NOP and STI are one byte 8710 * instructions. 8711 */ 8712 asm volatile("vmcall\n\t" 8713 "nop\n\t" 8714 "sti\n\t" 8715 "sti\n\t"); 8716 8717 handle_exception(DB_VECTOR, NULL); 8718 } 8719 8720 static void verify_intr_window_exit(u64 rip) 8721 { 8722 u32 exit_reason = vmcs_read(EXI_REASON); 8723 8724 report(exit_reason == VMX_INTR_WINDOW, 8725 "Exit reason (%d) is 'interrupt window'", exit_reason); 8726 report(vmcs_read(GUEST_RIP) == rip, "RIP (%#lx) is %#lx", 8727 vmcs_read(GUEST_RIP), rip); 8728 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 8729 } 8730 8731 static void vmx_intr_window_test(void) 8732 { 8733 u64 vmcall_addr; 8734 u64 nop_addr; 8735 unsigned int orig_db_gate_type; 8736 void *db_fault_addr = get_idt_addr(&boot_idt[DB_VECTOR]); 8737 8738 if (!(ctrl_cpu_rev[0].clr & CPU_INTR_WINDOW)) { 8739 report_skip("%s : \"Interrupt-window exiting\" exec control not supported", __func__); 8740 return; 8741 } 8742 8743 /* 8744 * Change the IDT entry for #DB from interrupt gate to trap gate, 8745 * so that it won't clear RFLAGS.IF. We don't want interrupts to 8746 * be disabled after vectoring a #DB. 8747 */ 8748 orig_db_gate_type = boot_idt[DB_VECTOR].type; 8749 boot_idt[DB_VECTOR].type = 15; 8750 8751 report_prefix_push("interrupt-window"); 8752 test_set_guest(vmx_intr_window_test_guest); 8753 enter_guest(); 8754 assert_exit_reason(VMX_VMCALL); 8755 vmcall_addr = vmcs_read(GUEST_RIP); 8756 8757 /* 8758 * Ask for "interrupt-window exiting" with RFLAGS.IF set and 8759 * no blocking; expect an immediate VM-exit. Note that we have 8760 * not advanced past the vmcall instruction yet, so RIP should 8761 * point to the vmcall instruction. 8762 */ 8763 report_prefix_push("active, no blocking, RFLAGS.IF=1"); 8764 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8765 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_IF); 8766 enter_guest(); 8767 verify_intr_window_exit(vmcall_addr); 8768 report_prefix_pop(); 8769 8770 /* 8771 * Ask for "interrupt-window exiting" (with event injection) 8772 * with RFLAGS.IF set and no blocking; expect a VM-exit after 8773 * the event is injected. That is, RIP should should be at the 8774 * address specified in the IDT entry for #DB. 8775 */ 8776 report_prefix_push("active, no blocking, RFLAGS.IF=1, injecting #DB"); 8777 vmcs_write(ENT_INTR_INFO, 8778 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 8779 vmcall_addr = vmcs_read(GUEST_RIP); 8780 enter_guest(); 8781 verify_intr_window_exit((u64)db_fault_addr); 8782 report_prefix_pop(); 8783 8784 /* 8785 * Let the L2 guest run through the IRET, back to the VMCALL. 8786 * We have to clear the "interrupt-window exiting" 8787 * VM-execution control, or it would just keep causing 8788 * VM-exits. Then, advance past the VMCALL and set the 8789 * "interrupt-window exiting" VM-execution control again. 8790 */ 8791 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8792 enter_guest(); 8793 skip_exit_vmcall(); 8794 nop_addr = vmcs_read(GUEST_RIP); 8795 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8796 8797 /* 8798 * Ask for "interrupt-window exiting" in a MOV-SS shadow with 8799 * RFLAGS.IF set, and expect a VM-exit on the next 8800 * instruction. (NOP is one byte.) 8801 */ 8802 report_prefix_push("active, blocking by MOV-SS, RFLAGS.IF=1"); 8803 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 8804 enter_guest(); 8805 verify_intr_window_exit(nop_addr + 1); 8806 report_prefix_pop(); 8807 8808 /* 8809 * Back up to the NOP and ask for "interrupt-window exiting" 8810 * in an STI shadow with RFLAGS.IF set, and expect a VM-exit 8811 * on the next instruction. (NOP is one byte.) 8812 */ 8813 report_prefix_push("active, blocking by STI, RFLAGS.IF=1"); 8814 vmcs_write(GUEST_RIP, nop_addr); 8815 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_STI); 8816 enter_guest(); 8817 verify_intr_window_exit(nop_addr + 1); 8818 report_prefix_pop(); 8819 8820 /* 8821 * Ask for "interrupt-window exiting" with RFLAGS.IF clear, 8822 * and expect a VM-exit on the instruction following the STI 8823 * shadow. Only the first STI (which is one byte past the NOP) 8824 * should have a shadow. The second STI (which is two bytes 8825 * past the NOP) has no shadow. Therefore, the interrupt 8826 * window opens at three bytes past the NOP. 8827 */ 8828 report_prefix_push("active, RFLAGS.IF = 0"); 8829 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 8830 enter_guest(); 8831 verify_intr_window_exit(nop_addr + 3); 8832 report_prefix_pop(); 8833 8834 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 8835 report_skip("CPU does not support activity state HLT."); 8836 } else { 8837 /* 8838 * Ask for "interrupt-window exiting" when entering 8839 * activity state HLT, and expect an immediate 8840 * VM-exit. RIP is still three bytes past the nop. 8841 */ 8842 report_prefix_push("halted, no blocking"); 8843 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8844 enter_guest(); 8845 verify_intr_window_exit(nop_addr + 3); 8846 report_prefix_pop(); 8847 8848 /* 8849 * Ask for "interrupt-window exiting" when entering 8850 * activity state HLT (with event injection), and 8851 * expect a VM-exit after the event is injected. That 8852 * is, RIP should should be at the address specified 8853 * in the IDT entry for #DB. 8854 */ 8855 report_prefix_push("halted, no blocking, injecting #DB"); 8856 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8857 vmcs_write(ENT_INTR_INFO, 8858 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 8859 DB_VECTOR); 8860 enter_guest(); 8861 verify_intr_window_exit((u64)db_fault_addr); 8862 report_prefix_pop(); 8863 } 8864 8865 boot_idt[DB_VECTOR].type = orig_db_gate_type; 8866 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8867 enter_guest(); 8868 report_prefix_pop(); 8869 } 8870 8871 #define GUEST_TSC_OFFSET (1u << 30) 8872 8873 static u64 guest_tsc; 8874 8875 static void vmx_store_tsc_test_guest(void) 8876 { 8877 guest_tsc = rdtsc(); 8878 } 8879 8880 /* 8881 * This test ensures that when IA32_TSC is in the VM-exit MSR-store 8882 * list, the value saved is not subject to the TSC offset that is 8883 * applied to RDTSC/RDTSCP/RDMSR(IA32_TSC) in guest execution. 8884 */ 8885 static void vmx_store_tsc_test(void) 8886 { 8887 struct vmx_msr_entry msr_entry = { .index = MSR_IA32_TSC }; 8888 u64 low, high; 8889 8890 if (!(ctrl_cpu_rev[0].clr & CPU_USE_TSC_OFFSET)) { 8891 report_skip("%s : \"Use TSC offsetting\" exec control not supported", __func__); 8892 return; 8893 } 8894 8895 test_set_guest(vmx_store_tsc_test_guest); 8896 8897 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_USE_TSC_OFFSET); 8898 vmcs_write(EXI_MSR_ST_CNT, 1); 8899 vmcs_write(EXIT_MSR_ST_ADDR, virt_to_phys(&msr_entry)); 8900 vmcs_write(TSC_OFFSET, GUEST_TSC_OFFSET); 8901 8902 low = rdtsc(); 8903 enter_guest(); 8904 high = rdtsc(); 8905 8906 report(low + GUEST_TSC_OFFSET <= guest_tsc && 8907 guest_tsc <= high + GUEST_TSC_OFFSET, 8908 "RDTSC value in the guest (%lu) is in range [%lu, %lu]", 8909 guest_tsc, low + GUEST_TSC_OFFSET, high + GUEST_TSC_OFFSET); 8910 report(low <= msr_entry.value && msr_entry.value <= high, 8911 "IA32_TSC value saved in the VM-exit MSR-store list (%lu) is in range [%lu, %lu]", 8912 msr_entry.value, low, high); 8913 } 8914 8915 static void vmx_preemption_timer_zero_test_db_handler(struct ex_regs *regs) 8916 { 8917 } 8918 8919 static void vmx_preemption_timer_zero_test_guest(void) 8920 { 8921 while (vmx_get_test_stage() < 3) 8922 vmcall(); 8923 } 8924 8925 static void vmx_preemption_timer_zero_activate_preemption_timer(void) 8926 { 8927 vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT); 8928 vmcs_write(PREEMPT_TIMER_VALUE, 0); 8929 } 8930 8931 static void vmx_preemption_timer_zero_advance_past_vmcall(void) 8932 { 8933 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 8934 enter_guest(); 8935 skip_exit_vmcall(); 8936 } 8937 8938 static void vmx_preemption_timer_zero_inject_db(bool intercept_db) 8939 { 8940 vmx_preemption_timer_zero_activate_preemption_timer(); 8941 vmcs_write(ENT_INTR_INFO, INTR_INFO_VALID_MASK | 8942 INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 8943 vmcs_write(EXC_BITMAP, intercept_db ? 1 << DB_VECTOR : 0); 8944 enter_guest(); 8945 } 8946 8947 static void vmx_preemption_timer_zero_set_pending_dbg(u32 exception_bitmap) 8948 { 8949 vmx_preemption_timer_zero_activate_preemption_timer(); 8950 vmcs_write(GUEST_PENDING_DEBUG, PENDING_DBG_TRAP | DR6_TRAP1); 8951 vmcs_write(EXC_BITMAP, exception_bitmap); 8952 enter_guest(); 8953 } 8954 8955 static void vmx_preemption_timer_zero_expect_preempt_at_rip(u64 expected_rip) 8956 { 8957 u32 reason = (u32)vmcs_read(EXI_REASON); 8958 u64 guest_rip = vmcs_read(GUEST_RIP); 8959 8960 report(reason == VMX_PREEMPT && guest_rip == expected_rip, 8961 "Exit reason is 0x%x (expected 0x%x) and guest RIP is %lx (0x%lx expected).", 8962 reason, VMX_PREEMPT, guest_rip, expected_rip); 8963 } 8964 8965 /* 8966 * This test ensures that when the VMX preemption timer is zero at 8967 * VM-entry, a VM-exit occurs after any event injection and after any 8968 * pending debug exceptions are raised, but before execution of any 8969 * guest instructions. 8970 */ 8971 static void vmx_preemption_timer_zero_test(void) 8972 { 8973 u64 db_fault_address = (u64)get_idt_addr(&boot_idt[DB_VECTOR]); 8974 handler old_db; 8975 u32 reason; 8976 8977 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 8978 report_skip("%s : \"Activate VMX-preemption timer\" pin control not supported", __func__); 8979 return; 8980 } 8981 8982 /* 8983 * Install a custom #DB handler that doesn't abort. 8984 */ 8985 old_db = handle_exception(DB_VECTOR, 8986 vmx_preemption_timer_zero_test_db_handler); 8987 8988 test_set_guest(vmx_preemption_timer_zero_test_guest); 8989 8990 /* 8991 * VMX-preemption timer should fire after event injection. 8992 */ 8993 vmx_set_test_stage(0); 8994 vmx_preemption_timer_zero_inject_db(0); 8995 vmx_preemption_timer_zero_expect_preempt_at_rip(db_fault_address); 8996 vmx_preemption_timer_zero_advance_past_vmcall(); 8997 8998 /* 8999 * VMX-preemption timer should fire after event injection. 9000 * Exception bitmap is irrelevant, since you can't intercept 9001 * an event that you injected. 9002 */ 9003 vmx_set_test_stage(1); 9004 vmx_preemption_timer_zero_inject_db(true); 9005 vmx_preemption_timer_zero_expect_preempt_at_rip(db_fault_address); 9006 vmx_preemption_timer_zero_advance_past_vmcall(); 9007 9008 /* 9009 * VMX-preemption timer should fire after pending debug exceptions 9010 * have delivered a #DB trap. 9011 */ 9012 vmx_set_test_stage(2); 9013 vmx_preemption_timer_zero_set_pending_dbg(0); 9014 vmx_preemption_timer_zero_expect_preempt_at_rip(db_fault_address); 9015 vmx_preemption_timer_zero_advance_past_vmcall(); 9016 9017 /* 9018 * VMX-preemption timer would fire after pending debug exceptions 9019 * have delivered a #DB trap, but in this case, the #DB trap is 9020 * intercepted. 9021 */ 9022 vmx_set_test_stage(3); 9023 vmx_preemption_timer_zero_set_pending_dbg(1 << DB_VECTOR); 9024 reason = (u32)vmcs_read(EXI_REASON); 9025 report(reason == VMX_EXC_NMI, "Exit reason is 0x%x (expected 0x%x)", 9026 reason, VMX_EXC_NMI); 9027 9028 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 9029 enter_guest(); 9030 9031 handle_exception(DB_VECTOR, old_db); 9032 } 9033 9034 static u64 vmx_preemption_timer_tf_test_prev_rip; 9035 9036 static void vmx_preemption_timer_tf_test_db_handler(struct ex_regs *regs) 9037 { 9038 extern char vmx_preemption_timer_tf_test_endloop; 9039 9040 if (vmx_get_test_stage() == 2) { 9041 /* 9042 * Stage 2 means that we're done, one way or another. 9043 * Arrange for the iret to drop us out of the wbinvd 9044 * loop and stop single-stepping. 9045 */ 9046 regs->rip = (u64)&vmx_preemption_timer_tf_test_endloop; 9047 regs->rflags &= ~X86_EFLAGS_TF; 9048 } else if (regs->rip == vmx_preemption_timer_tf_test_prev_rip) { 9049 /* 9050 * The RIP should alternate between the wbinvd and the 9051 * jmp instruction in the code below. If we ever see 9052 * the same instruction twice in a row, that means a 9053 * single-step trap has been dropped. Let the 9054 * hypervisor know about the failure by executing a 9055 * VMCALL. 9056 */ 9057 vmcall(); 9058 } 9059 vmx_preemption_timer_tf_test_prev_rip = regs->rip; 9060 } 9061 9062 static void vmx_preemption_timer_tf_test_guest(void) 9063 { 9064 /* 9065 * The hypervisor doesn't intercept WBINVD, so the loop below 9066 * shouldn't be a problem--it's just two instructions 9067 * executing in VMX non-root mode. However, when the 9068 * hypervisor is running in a virtual environment, the parent 9069 * hypervisor might intercept WBINVD and emulate it. If the 9070 * parent hypervisor is broken, the single-step trap after the 9071 * WBINVD might be lost. 9072 */ 9073 asm volatile("vmcall\n\t" 9074 "0: wbinvd\n\t" 9075 "1: jmp 0b\n\t" 9076 "vmx_preemption_timer_tf_test_endloop:"); 9077 } 9078 9079 /* 9080 * Ensure that the delivery of a "VMX-preemption timer expired" 9081 * VM-exit doesn't disrupt single-stepping in the guest. Note that 9082 * passing this test doesn't ensure correctness, because the test will 9083 * only fail if the VMX-preemtion timer fires at the right time (or 9084 * the wrong time, as it were). 9085 */ 9086 static void vmx_preemption_timer_tf_test(void) 9087 { 9088 handler old_db; 9089 u32 reason; 9090 int i; 9091 9092 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 9093 report_skip("%s : \"Activate VMX-preemption timer\" pin control not supported", __func__); 9094 return; 9095 } 9096 9097 old_db = handle_exception(DB_VECTOR, 9098 vmx_preemption_timer_tf_test_db_handler); 9099 9100 test_set_guest(vmx_preemption_timer_tf_test_guest); 9101 9102 enter_guest(); 9103 skip_exit_vmcall(); 9104 9105 vmx_set_test_stage(1); 9106 vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT); 9107 vmcs_write(PREEMPT_TIMER_VALUE, 50000); 9108 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_TF); 9109 9110 /* 9111 * The only exit we should see is "VMX-preemption timer 9112 * expired." If we get a VMCALL exit, that means the #DB 9113 * handler has detected a missing single-step trap. It doesn't 9114 * matter where the guest RIP is when the VMX-preemption timer 9115 * expires (whether it's in the WBINVD loop or in the #DB 9116 * handler)--a single-step trap should never be discarded. 9117 */ 9118 for (i = 0; i < 10000; i++) { 9119 enter_guest(); 9120 reason = (u32)vmcs_read(EXI_REASON); 9121 if (reason == VMX_PREEMPT) 9122 continue; 9123 TEST_ASSERT(reason == VMX_VMCALL); 9124 skip_exit_insn(); 9125 break; 9126 } 9127 9128 report(reason == VMX_PREEMPT, "No single-step traps skipped"); 9129 9130 vmx_set_test_stage(2); 9131 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 9132 enter_guest(); 9133 9134 handle_exception(DB_VECTOR, old_db); 9135 } 9136 9137 #define VMX_PREEMPTION_TIMER_EXPIRY_CYCLES 1000000 9138 9139 static u64 vmx_preemption_timer_expiry_start; 9140 static u64 vmx_preemption_timer_expiry_finish; 9141 9142 static void vmx_preemption_timer_expiry_test_guest(void) 9143 { 9144 vmcall(); 9145 vmx_preemption_timer_expiry_start = fenced_rdtsc(); 9146 9147 while (vmx_get_test_stage() == 0) 9148 vmx_preemption_timer_expiry_finish = fenced_rdtsc(); 9149 } 9150 9151 /* 9152 * Test that the VMX-preemption timer is not excessively delayed. 9153 * 9154 * Per the SDM, volume 3, VM-entry starts the VMX-preemption timer 9155 * with the unsigned value in the VMX-preemption timer-value field, 9156 * and the VMX-preemption timer counts down by 1 every time bit X in 9157 * the TSC changes due to a TSC increment (where X is 9158 * IA32_VMX_MISC[4:0]). If the timer counts down to zero in any state 9159 * other than the wait-for-SIPI state, the logical processor 9160 * transitions to the C0 C-state and causes a VM-exit. 9161 * 9162 * The guest code above reads the starting TSC after VM-entry. At this 9163 * point, the VMX-preemption timer has already been activated. Next, 9164 * the guest code reads the current TSC in a loop, storing the value 9165 * read to memory. 9166 * 9167 * If the RDTSC in the loop reads a value past the VMX-preemption 9168 * timer deadline, then the VMX-preemption timer VM-exit must be 9169 * delivered before the next instruction retires. Even if a higher 9170 * priority SMI is delivered first, the VMX-preemption timer VM-exit 9171 * must be delivered before the next instruction retires. Hence, a TSC 9172 * value past the VMX-preemption timer deadline might be read, but it 9173 * cannot be stored. If a TSC value past the deadline *is* stored, 9174 * then the architectural specification has been violated. 9175 */ 9176 static void vmx_preemption_timer_expiry_test(void) 9177 { 9178 u32 preemption_timer_value; 9179 union vmx_misc misc; 9180 u64 tsc_deadline; 9181 u32 reason; 9182 9183 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 9184 report_skip("%s : \"Activate VMX-preemption timer\" pin control not supported", __func__); 9185 return; 9186 } 9187 9188 test_set_guest(vmx_preemption_timer_expiry_test_guest); 9189 9190 enter_guest(); 9191 skip_exit_vmcall(); 9192 9193 misc.val = rdmsr(MSR_IA32_VMX_MISC); 9194 preemption_timer_value = 9195 VMX_PREEMPTION_TIMER_EXPIRY_CYCLES >> misc.pt_bit; 9196 9197 vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT); 9198 vmcs_write(PREEMPT_TIMER_VALUE, preemption_timer_value); 9199 vmx_set_test_stage(0); 9200 9201 enter_guest(); 9202 reason = (u32)vmcs_read(EXI_REASON); 9203 TEST_ASSERT(reason == VMX_PREEMPT); 9204 9205 tsc_deadline = ((vmx_preemption_timer_expiry_start >> misc.pt_bit) << 9206 misc.pt_bit) + (preemption_timer_value << misc.pt_bit); 9207 9208 report(vmx_preemption_timer_expiry_finish < tsc_deadline, 9209 "Last stored guest TSC (%lu) < TSC deadline (%lu)", 9210 vmx_preemption_timer_expiry_finish, tsc_deadline); 9211 9212 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 9213 vmx_set_test_stage(1); 9214 enter_guest(); 9215 } 9216 9217 static void vmx_db_test_guest(void) 9218 { 9219 /* 9220 * For a hardware generated single-step #DB. 9221 */ 9222 asm volatile("vmcall;" 9223 "nop;" 9224 ".Lpost_nop:"); 9225 /* 9226 * ...in a MOVSS shadow, with pending debug exceptions. 9227 */ 9228 asm volatile("vmcall;" 9229 "nop;" 9230 ".Lpost_movss_nop:"); 9231 /* 9232 * For an L0 synthesized single-step #DB. (L0 intercepts WBINVD and 9233 * emulates it in software.) 9234 */ 9235 asm volatile("vmcall;" 9236 "wbinvd;" 9237 ".Lpost_wbinvd:"); 9238 /* 9239 * ...in a MOVSS shadow, with pending debug exceptions. 9240 */ 9241 asm volatile("vmcall;" 9242 "wbinvd;" 9243 ".Lpost_movss_wbinvd:"); 9244 /* 9245 * For a hardware generated single-step #DB in a transactional region. 9246 */ 9247 asm volatile("vmcall;" 9248 ".Lxbegin: xbegin .Lskip_rtm;" 9249 "xend;" 9250 ".Lskip_rtm:"); 9251 } 9252 9253 /* 9254 * Clear the pending debug exceptions and RFLAGS.TF and re-enter 9255 * L2. No #DB is delivered and L2 continues to the next point of 9256 * interest. 9257 */ 9258 static void dismiss_db(void) 9259 { 9260 vmcs_write(GUEST_PENDING_DEBUG, 0); 9261 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 9262 enter_guest(); 9263 } 9264 9265 /* 9266 * Check a variety of VMCS fields relevant to an intercepted #DB exception. 9267 * Then throw away the #DB exception and resume L2. 9268 */ 9269 static void check_db_exit(bool xfail_qual, bool xfail_dr6, bool xfail_pdbg, 9270 void *expected_rip, u64 expected_exit_qual, 9271 u64 expected_dr6) 9272 { 9273 u32 reason = vmcs_read(EXI_REASON); 9274 u32 intr_info = vmcs_read(EXI_INTR_INFO); 9275 u64 exit_qual = vmcs_read(EXI_QUALIFICATION); 9276 u64 guest_rip = vmcs_read(GUEST_RIP); 9277 u64 guest_pending_dbg = vmcs_read(GUEST_PENDING_DEBUG); 9278 u64 dr6 = read_dr6(); 9279 const u32 expected_intr_info = INTR_INFO_VALID_MASK | 9280 INTR_TYPE_HARD_EXCEPTION | DB_VECTOR; 9281 9282 report(reason == VMX_EXC_NMI && intr_info == expected_intr_info, 9283 "Expected #DB VM-exit"); 9284 report((u64)expected_rip == guest_rip, "Expected RIP %p (actual %lx)", 9285 expected_rip, guest_rip); 9286 report_xfail(xfail_pdbg, 0 == guest_pending_dbg, 9287 "Expected pending debug exceptions 0 (actual %lx)", 9288 guest_pending_dbg); 9289 report_xfail(xfail_qual, expected_exit_qual == exit_qual, 9290 "Expected exit qualification %lx (actual %lx)", 9291 expected_exit_qual, exit_qual); 9292 report_xfail(xfail_dr6, expected_dr6 == dr6, 9293 "Expected DR6 %lx (actual %lx)", expected_dr6, dr6); 9294 dismiss_db(); 9295 } 9296 9297 /* 9298 * Assuming the guest has just exited on a VMCALL instruction, skip 9299 * over the vmcall, and set the guest's RFLAGS.TF in the VMCS. If 9300 * pending debug exceptions are non-zero, set the VMCS up as if the 9301 * previous instruction was a MOVSS that generated the indicated 9302 * pending debug exceptions. Then enter L2. 9303 */ 9304 static void single_step_guest(const char *test_name, u64 starting_dr6, 9305 u64 pending_debug_exceptions) 9306 { 9307 printf("\n%s\n", test_name); 9308 skip_exit_vmcall(); 9309 write_dr6(starting_dr6); 9310 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_TF); 9311 if (pending_debug_exceptions) { 9312 vmcs_write(GUEST_PENDING_DEBUG, pending_debug_exceptions); 9313 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 9314 } 9315 enter_guest(); 9316 } 9317 9318 /* 9319 * When L1 intercepts #DB, verify that a single-step trap clears 9320 * pending debug exceptions, populates the exit qualification field 9321 * properly, and that DR6 is not prematurely clobbered. In a 9322 * (simulated) MOVSS shadow, make sure that the pending debug 9323 * exception bits are properly accumulated into the exit qualification 9324 * field. 9325 */ 9326 static void vmx_db_test(void) 9327 { 9328 /* 9329 * We are going to set a few arbitrary bits in DR6 to verify that 9330 * (a) DR6 is not modified by an intercepted #DB, and 9331 * (b) stale bits in DR6 (DR6.BD, in particular) don't leak into 9332 * the exit qualification field for a subsequent #DB exception. 9333 */ 9334 const u64 starting_dr6 = DR6_ACTIVE_LOW | DR6_BS | DR6_TRAP3 | DR6_TRAP1; 9335 extern char post_nop asm(".Lpost_nop"); 9336 extern char post_movss_nop asm(".Lpost_movss_nop"); 9337 extern char post_wbinvd asm(".Lpost_wbinvd"); 9338 extern char post_movss_wbinvd asm(".Lpost_movss_wbinvd"); 9339 extern char xbegin asm(".Lxbegin"); 9340 extern char skip_rtm asm(".Lskip_rtm"); 9341 9342 /* 9343 * L1 wants to intercept #DB exceptions encountered in L2. 9344 */ 9345 vmcs_write(EXC_BITMAP, BIT(DB_VECTOR)); 9346 9347 /* 9348 * Start L2 and run it up to the first point of interest. 9349 */ 9350 test_set_guest(vmx_db_test_guest); 9351 enter_guest(); 9352 9353 /* 9354 * Hardware-delivered #DB trap for single-step sets the 9355 * standard that L0 has to follow for emulated instructions. 9356 */ 9357 single_step_guest("Hardware delivered single-step", starting_dr6, 0); 9358 check_db_exit(false, false, false, &post_nop, DR6_BS, starting_dr6); 9359 9360 /* 9361 * Hardware-delivered #DB trap for single-step in MOVSS shadow 9362 * also sets the standard that L0 has to follow for emulated 9363 * instructions. Here, we establish the VMCS pending debug 9364 * exceptions to indicate that the simulated MOVSS triggered a 9365 * data breakpoint as well as the single-step trap. 9366 */ 9367 single_step_guest("Hardware delivered single-step in MOVSS shadow", 9368 starting_dr6, DR6_BS | PENDING_DBG_TRAP | DR6_TRAP0); 9369 check_db_exit(false, false, false, &post_movss_nop, DR6_BS | DR6_TRAP0, 9370 starting_dr6); 9371 9372 /* 9373 * L0 synthesized #DB trap for single-step is buggy, because 9374 * kvm (a) clobbers DR6 too early, and (b) tries its best to 9375 * reconstitute the exit qualification from the prematurely 9376 * modified DR6, but fails miserably. 9377 */ 9378 single_step_guest("Software synthesized single-step", starting_dr6, 0); 9379 check_db_exit(false, false, false, &post_wbinvd, DR6_BS, starting_dr6); 9380 9381 /* 9382 * L0 synthesized #DB trap for single-step in MOVSS shadow is 9383 * even worse, because L0 also leaves the pending debug 9384 * exceptions in the VMCS instead of accumulating them into 9385 * the exit qualification field for the #DB exception. 9386 */ 9387 single_step_guest("Software synthesized single-step in MOVSS shadow", 9388 starting_dr6, DR6_BS | PENDING_DBG_TRAP | DR6_TRAP0); 9389 check_db_exit(true, false, true, &post_movss_wbinvd, DR6_BS | DR6_TRAP0, 9390 starting_dr6); 9391 9392 /* 9393 * Optional RTM test for hardware that supports RTM, to 9394 * demonstrate that the current volume 3 of the SDM 9395 * (325384-067US), table 27-1 is incorrect. Bit 16 of the exit 9396 * qualification for debug exceptions is not reserved. It is 9397 * set to 1 if a debug exception (#DB) or a breakpoint 9398 * exception (#BP) occurs inside an RTM region while advanced 9399 * debugging of RTM transactional regions is enabled. 9400 */ 9401 if (this_cpu_has(X86_FEATURE_RTM)) { 9402 vmcs_write(ENT_CONTROLS, 9403 vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 9404 /* 9405 * Set DR7.RTM[bit 11] and IA32_DEBUGCTL.RTM[bit 15] 9406 * in the guest to enable advanced debugging of RTM 9407 * transactional regions. 9408 */ 9409 vmcs_write(GUEST_DR7, BIT(11)); 9410 vmcs_write(GUEST_DEBUGCTL, BIT(15)); 9411 single_step_guest("Hardware delivered single-step in " 9412 "transactional region", starting_dr6, 0); 9413 check_db_exit(false, false, false, &xbegin, BIT(16), 9414 starting_dr6); 9415 } else { 9416 vmcs_write(GUEST_RIP, (u64)&skip_rtm); 9417 enter_guest(); 9418 } 9419 } 9420 9421 static void enable_vid(void) 9422 { 9423 void *virtual_apic_page; 9424 9425 assert(cpu_has_apicv()); 9426 9427 disable_intercept_for_x2apic_msrs(); 9428 9429 virtual_apic_page = alloc_page(); 9430 vmcs_write(APIC_VIRT_ADDR, (u64)virtual_apic_page); 9431 9432 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 9433 9434 vmcs_write(EOI_EXIT_BITMAP0, 0x0); 9435 vmcs_write(EOI_EXIT_BITMAP1, 0x0); 9436 vmcs_write(EOI_EXIT_BITMAP2, 0x0); 9437 vmcs_write(EOI_EXIT_BITMAP3, 0x0); 9438 9439 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY | CPU_TPR_SHADOW); 9440 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_VINTD | CPU_VIRT_X2APIC); 9441 } 9442 9443 static void trigger_ioapic_scan_thread(void *data) 9444 { 9445 /* Wait until other CPU entered L2 */ 9446 while (vmx_get_test_stage() != 1) 9447 ; 9448 9449 /* Trigger ioapic scan */ 9450 ioapic_set_redir(0xf, 0x79, TRIGGER_LEVEL); 9451 vmx_set_test_stage(2); 9452 } 9453 9454 static void irq_79_handler_guest(isr_regs_t *regs) 9455 { 9456 eoi(); 9457 9458 /* L1 expects vmexit on VMX_VMCALL and not VMX_EOI_INDUCED */ 9459 vmcall(); 9460 } 9461 9462 /* 9463 * Constant for num of busy-loop iterations after which 9464 * a timer interrupt should have happened in host 9465 */ 9466 #define TIMER_INTERRUPT_DELAY 100000000 9467 9468 static void vmx_eoi_bitmap_ioapic_scan_test_guest(void) 9469 { 9470 handle_irq(0x79, irq_79_handler_guest); 9471 irq_enable(); 9472 9473 /* Signal to L1 CPU to trigger ioapic scan */ 9474 vmx_set_test_stage(1); 9475 /* Wait until L1 CPU to trigger ioapic scan */ 9476 while (vmx_get_test_stage() != 2) 9477 ; 9478 9479 /* 9480 * Wait for L0 timer interrupt to be raised while we run in L2 9481 * such that L0 will process the IOAPIC scan request before 9482 * resuming L2 9483 */ 9484 delay(TIMER_INTERRUPT_DELAY); 9485 9486 asm volatile ("int $0x79"); 9487 } 9488 9489 static void vmx_eoi_bitmap_ioapic_scan_test(void) 9490 { 9491 if (!cpu_has_apicv() || (cpu_count() < 2)) { 9492 report_skip("%s : Not all required APICv bits supported or CPU count < 2", __func__); 9493 return; 9494 } 9495 9496 enable_vid(); 9497 9498 on_cpu_async(1, trigger_ioapic_scan_thread, NULL); 9499 test_set_guest(vmx_eoi_bitmap_ioapic_scan_test_guest); 9500 9501 /* 9502 * Launch L2. 9503 * We expect the exit reason to be VMX_VMCALL (and not EOI INDUCED). 9504 * In case the reason isn't VMX_VMCALL, the asserion inside 9505 * skip_exit_vmcall() will fail. 9506 */ 9507 enter_guest(); 9508 skip_exit_vmcall(); 9509 9510 /* Let L2 finish */ 9511 enter_guest(); 9512 report_pass(__func__); 9513 } 9514 9515 #define HLT_WITH_RVI_VECTOR (0xf1) 9516 9517 bool vmx_hlt_with_rvi_guest_isr_fired; 9518 static void vmx_hlt_with_rvi_guest_isr(isr_regs_t *regs) 9519 { 9520 vmx_hlt_with_rvi_guest_isr_fired = true; 9521 eoi(); 9522 } 9523 9524 static void vmx_hlt_with_rvi_guest(void) 9525 { 9526 handle_irq(HLT_WITH_RVI_VECTOR, vmx_hlt_with_rvi_guest_isr); 9527 9528 irq_enable(); 9529 asm volatile ("nop"); 9530 9531 vmcall(); 9532 } 9533 9534 static void vmx_hlt_with_rvi_test(void) 9535 { 9536 if (!cpu_has_apicv()) { 9537 report_skip("%s : Not all required APICv bits supported", __func__); 9538 return; 9539 } 9540 9541 enable_vid(); 9542 9543 vmx_hlt_with_rvi_guest_isr_fired = false; 9544 test_set_guest(vmx_hlt_with_rvi_guest); 9545 9546 enter_guest(); 9547 skip_exit_vmcall(); 9548 9549 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 9550 vmcs_write(GUEST_INT_STATUS, HLT_WITH_RVI_VECTOR); 9551 enter_guest(); 9552 9553 report(vmx_hlt_with_rvi_guest_isr_fired, "Interrupt raised in guest"); 9554 } 9555 9556 static void set_irq_line_thread(void *data) 9557 { 9558 /* Wait until other CPU entered L2 */ 9559 while (vmx_get_test_stage() != 1) 9560 ; 9561 9562 /* Set irq-line 0xf to raise vector 0x78 for vCPU 0 */ 9563 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 9564 vmx_set_test_stage(2); 9565 } 9566 9567 static bool irq_78_handler_vmcall_before_eoi; 9568 static void irq_78_handler_guest(isr_regs_t *regs) 9569 { 9570 set_irq_line(0xf, 0); 9571 if (irq_78_handler_vmcall_before_eoi) 9572 vmcall(); 9573 eoi(); 9574 vmcall(); 9575 } 9576 9577 static void vmx_apic_passthrough_guest(void) 9578 { 9579 handle_irq(0x78, irq_78_handler_guest); 9580 irq_enable(); 9581 9582 /* If requested, wait for other CPU to trigger ioapic scan */ 9583 if (vmx_get_test_stage() < 1) { 9584 vmx_set_test_stage(1); 9585 while (vmx_get_test_stage() != 2) 9586 ; 9587 } 9588 9589 set_irq_line(0xf, 1); 9590 } 9591 9592 static void vmx_apic_passthrough(bool set_irq_line_from_thread) 9593 { 9594 if (set_irq_line_from_thread && (cpu_count() < 2)) { 9595 report_skip("%s : CPU count < 2", __func__); 9596 return; 9597 } 9598 9599 /* Test device is required for generating IRQs */ 9600 if (!test_device_enabled()) { 9601 report_skip("%s : No test device enabled", __func__); 9602 return; 9603 } 9604 u64 cpu_ctrl_0 = CPU_SECONDARY; 9605 u64 cpu_ctrl_1 = 0; 9606 9607 disable_intercept_for_x2apic_msrs(); 9608 9609 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 9610 9611 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 9612 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 9613 9614 if (set_irq_line_from_thread) { 9615 irq_78_handler_vmcall_before_eoi = false; 9616 on_cpu_async(1, set_irq_line_thread, NULL); 9617 } else { 9618 irq_78_handler_vmcall_before_eoi = true; 9619 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 9620 vmx_set_test_stage(2); 9621 } 9622 test_set_guest(vmx_apic_passthrough_guest); 9623 9624 if (irq_78_handler_vmcall_before_eoi) { 9625 /* Before EOI remote_irr should still be set */ 9626 enter_guest(); 9627 skip_exit_vmcall(); 9628 TEST_ASSERT_EQ_MSG(1, (int)ioapic_read_redir(0xf).remote_irr, 9629 "IOAPIC pass-through: remote_irr=1 before EOI"); 9630 } 9631 9632 /* After EOI remote_irr should be cleared */ 9633 enter_guest(); 9634 skip_exit_vmcall(); 9635 TEST_ASSERT_EQ_MSG(0, (int)ioapic_read_redir(0xf).remote_irr, 9636 "IOAPIC pass-through: remote_irr=0 after EOI"); 9637 9638 /* Let L2 finish */ 9639 enter_guest(); 9640 report_pass(__func__); 9641 } 9642 9643 static void vmx_apic_passthrough_test(void) 9644 { 9645 vmx_apic_passthrough(false); 9646 } 9647 9648 static void vmx_apic_passthrough_thread_test(void) 9649 { 9650 vmx_apic_passthrough(true); 9651 } 9652 9653 static void vmx_apic_passthrough_tpr_threshold_guest(void) 9654 { 9655 cli(); 9656 apic_set_tpr(0); 9657 } 9658 9659 static bool vmx_apic_passthrough_tpr_threshold_ipi_isr_fired; 9660 static void vmx_apic_passthrough_tpr_threshold_ipi_isr(isr_regs_t *regs) 9661 { 9662 vmx_apic_passthrough_tpr_threshold_ipi_isr_fired = true; 9663 eoi(); 9664 } 9665 9666 static void vmx_apic_passthrough_tpr_threshold_test(void) 9667 { 9668 int ipi_vector = 0xe1; 9669 9670 disable_intercept_for_x2apic_msrs(); 9671 vmcs_clear_bits(PIN_CONTROLS, PIN_EXTINT); 9672 9673 /* Raise L0 TPR-threshold by queueing vector in LAPIC IRR */ 9674 cli(); 9675 apic_set_tpr((ipi_vector >> 4) + 1); 9676 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | 9677 APIC_DM_FIXED | ipi_vector, 9678 0); 9679 9680 test_set_guest(vmx_apic_passthrough_tpr_threshold_guest); 9681 enter_guest(); 9682 9683 report(apic_get_tpr() == 0, "TPR was zero by guest"); 9684 9685 /* Clean pending self-IPI */ 9686 vmx_apic_passthrough_tpr_threshold_ipi_isr_fired = false; 9687 handle_irq(ipi_vector, vmx_apic_passthrough_tpr_threshold_ipi_isr); 9688 sti(); 9689 asm volatile ("nop"); 9690 report(vmx_apic_passthrough_tpr_threshold_ipi_isr_fired, "self-IPI fired"); 9691 9692 report_pass(__func__); 9693 } 9694 9695 static u64 init_signal_test_exit_reason; 9696 static bool init_signal_test_thread_continued; 9697 9698 static void init_signal_test_thread(void *data) 9699 { 9700 struct vmcs *test_vmcs = data; 9701 9702 /* Enter VMX operation (i.e. exec VMXON) */ 9703 u64 *ap_vmxon_region = alloc_page(); 9704 enable_vmx(); 9705 init_vmx(ap_vmxon_region); 9706 TEST_ASSERT(!__vmxon_safe(ap_vmxon_region)); 9707 9708 /* Signal CPU have entered VMX operation */ 9709 vmx_set_test_stage(1); 9710 9711 /* Wait for BSP CPU to send INIT signal */ 9712 while (vmx_get_test_stage() != 2) 9713 ; 9714 9715 /* 9716 * Signal that we continue as usual as INIT signal 9717 * should be blocked while CPU is in VMX operation 9718 */ 9719 vmx_set_test_stage(3); 9720 9721 /* Wait for signal to enter VMX non-root mode */ 9722 while (vmx_get_test_stage() != 4) 9723 ; 9724 9725 /* Enter VMX non-root mode */ 9726 test_set_guest(v2_null_test_guest); 9727 make_vmcs_current(test_vmcs); 9728 enter_guest(); 9729 /* Save exit reason for BSP CPU to compare to expected result */ 9730 init_signal_test_exit_reason = vmcs_read(EXI_REASON); 9731 /* VMCLEAR test-vmcs so it could be loaded by BSP CPU */ 9732 vmcs_clear(test_vmcs); 9733 launched = false; 9734 /* Signal that CPU exited to VMX root mode */ 9735 vmx_set_test_stage(5); 9736 9737 /* Wait for BSP CPU to signal to exit VMX operation */ 9738 while (vmx_get_test_stage() != 6) 9739 ; 9740 9741 /* Exit VMX operation (i.e. exec VMXOFF) */ 9742 vmx_off(); 9743 9744 /* 9745 * Signal to BSP CPU that we continue as usual as INIT signal 9746 * should have been consumed by VMX_INIT exit from guest 9747 */ 9748 vmx_set_test_stage(7); 9749 9750 /* Wait for BSP CPU to signal to enter VMX operation */ 9751 while (vmx_get_test_stage() != 8) 9752 ; 9753 /* Enter VMX operation (i.e. exec VMXON) */ 9754 TEST_ASSERT(!__vmxon_safe(ap_vmxon_region)); 9755 /* Signal to BSP we are in VMX operation */ 9756 vmx_set_test_stage(9); 9757 9758 /* Wait for BSP CPU to send INIT signal */ 9759 while (vmx_get_test_stage() != 10) 9760 ; 9761 9762 /* Exit VMX operation (i.e. exec VMXOFF) */ 9763 vmx_off(); 9764 9765 /* 9766 * Exiting VMX operation should result in latched 9767 * INIT signal being processed. Therefore, we should 9768 * never reach the below code. Thus, signal to BSP 9769 * CPU if we have reached here so it is able to 9770 * report an issue if it happens. 9771 */ 9772 init_signal_test_thread_continued = true; 9773 } 9774 9775 #define INIT_SIGNAL_TEST_DELAY 100000000ULL 9776 9777 static void vmx_init_signal_test(void) 9778 { 9779 struct vmcs *test_vmcs; 9780 9781 if (cpu_count() < 2) { 9782 report_skip("%s : CPU count < 2", __func__); 9783 return; 9784 } 9785 9786 /* VMCLEAR test-vmcs so it could be loaded by other CPU */ 9787 vmcs_save(&test_vmcs); 9788 vmcs_clear(test_vmcs); 9789 9790 vmx_set_test_stage(0); 9791 on_cpu_async(1, init_signal_test_thread, test_vmcs); 9792 9793 /* Wait for other CPU to enter VMX operation */ 9794 while (vmx_get_test_stage() != 1) 9795 ; 9796 9797 /* Send INIT signal to other CPU */ 9798 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_INIT | APIC_INT_ASSERT, 9799 id_map[1]); 9800 /* Signal other CPU we have sent INIT signal */ 9801 vmx_set_test_stage(2); 9802 9803 /* 9804 * Wait reasonable amount of time for INIT signal to 9805 * be received on other CPU and verify that other CPU 9806 * have proceed as usual to next test stage as INIT 9807 * signal should be blocked while other CPU in 9808 * VMX operation 9809 */ 9810 delay(INIT_SIGNAL_TEST_DELAY); 9811 report(vmx_get_test_stage() == 3, 9812 "INIT signal blocked when CPU in VMX operation"); 9813 /* No point to continue if we failed at this point */ 9814 if (vmx_get_test_stage() != 3) 9815 return; 9816 9817 /* Signal other CPU to enter VMX non-root mode */ 9818 init_signal_test_exit_reason = -1ull; 9819 vmx_set_test_stage(4); 9820 /* 9821 * Wait reasonable amont of time for other CPU 9822 * to exit to VMX root mode 9823 */ 9824 delay(INIT_SIGNAL_TEST_DELAY); 9825 if (vmx_get_test_stage() != 5) { 9826 report_fail("Pending INIT signal didn't result in VMX exit"); 9827 return; 9828 } 9829 report(init_signal_test_exit_reason == VMX_INIT, 9830 "INIT signal during VMX non-root mode result in exit-reason %s (%lu)", 9831 exit_reason_description(init_signal_test_exit_reason), 9832 init_signal_test_exit_reason); 9833 9834 /* Run guest to completion */ 9835 make_vmcs_current(test_vmcs); 9836 enter_guest(); 9837 9838 /* Signal other CPU to exit VMX operation */ 9839 init_signal_test_thread_continued = false; 9840 vmx_set_test_stage(6); 9841 9842 /* Wait reasonable amount of time for other CPU to exit VMX operation */ 9843 delay(INIT_SIGNAL_TEST_DELAY); 9844 report(vmx_get_test_stage() == 7, 9845 "INIT signal consumed on VMX_INIT exit"); 9846 /* No point to continue if we failed at this point */ 9847 if (vmx_get_test_stage() != 7) 9848 return; 9849 9850 /* Signal other CPU to enter VMX operation */ 9851 vmx_set_test_stage(8); 9852 /* Wait for other CPU to enter VMX operation */ 9853 while (vmx_get_test_stage() != 9) 9854 ; 9855 9856 /* Send INIT signal to other CPU */ 9857 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_INIT | APIC_INT_ASSERT, 9858 id_map[1]); 9859 /* Signal other CPU we have sent INIT signal */ 9860 vmx_set_test_stage(10); 9861 9862 /* 9863 * Wait reasonable amount of time for other CPU 9864 * to exit VMX operation and process INIT signal 9865 */ 9866 delay(INIT_SIGNAL_TEST_DELAY); 9867 report(!init_signal_test_thread_continued, 9868 "INIT signal processed after exit VMX operation"); 9869 9870 /* 9871 * TODO: Send SIPI to other CPU to sipi_entry (See x86/cstart64.S) 9872 * to re-init it to kvm-unit-tests standard environment. 9873 * Somehow (?) verify that SIPI was indeed received. 9874 */ 9875 } 9876 9877 #define SIPI_SIGNAL_TEST_DELAY 100000000ULL 9878 9879 static void vmx_sipi_test_guest(void) 9880 { 9881 if (apic_id() == 0) { 9882 /* wait AP enter guest with activity=WAIT_SIPI */ 9883 while (vmx_get_test_stage() != 1) 9884 ; 9885 delay(SIPI_SIGNAL_TEST_DELAY); 9886 9887 /* First SIPI signal */ 9888 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_STARTUP | APIC_INT_ASSERT, id_map[1]); 9889 report_pass("BSP(L2): Send first SIPI to cpu[%d]", id_map[1]); 9890 9891 /* wait AP enter guest */ 9892 while (vmx_get_test_stage() != 2) 9893 ; 9894 delay(SIPI_SIGNAL_TEST_DELAY); 9895 9896 /* Second SIPI signal should be ignored since AP is not in WAIT_SIPI state */ 9897 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_STARTUP | APIC_INT_ASSERT, id_map[1]); 9898 report_pass("BSP(L2): Send second SIPI to cpu[%d]", id_map[1]); 9899 9900 /* Delay a while to check whether second SIPI would cause VMExit */ 9901 delay(SIPI_SIGNAL_TEST_DELAY); 9902 9903 /* Test is done, notify AP to exit test */ 9904 vmx_set_test_stage(3); 9905 9906 /* wait AP exit non-root mode */ 9907 while (vmx_get_test_stage() != 5) 9908 ; 9909 } else { 9910 /* wait BSP notify test is done */ 9911 while (vmx_get_test_stage() != 3) 9912 ; 9913 9914 /* AP exit guest */ 9915 vmx_set_test_stage(4); 9916 } 9917 } 9918 9919 static void sipi_test_ap_thread(void *data) 9920 { 9921 struct vmcs *ap_vmcs; 9922 u64 *ap_vmxon_region; 9923 void *ap_stack, *ap_syscall_stack; 9924 u64 cpu_ctrl_0 = CPU_SECONDARY; 9925 u64 cpu_ctrl_1 = 0; 9926 9927 /* Enter VMX operation (i.e. exec VMXON) */ 9928 ap_vmxon_region = alloc_page(); 9929 enable_vmx(); 9930 init_vmx(ap_vmxon_region); 9931 TEST_ASSERT(!__vmxon_safe(ap_vmxon_region)); 9932 init_vmcs(&ap_vmcs); 9933 make_vmcs_current(ap_vmcs); 9934 9935 /* Set stack for AP */ 9936 ap_stack = alloc_page(); 9937 ap_syscall_stack = alloc_page(); 9938 vmcs_write(GUEST_RSP, (u64)(ap_stack + PAGE_SIZE - 1)); 9939 vmcs_write(GUEST_SYSENTER_ESP, (u64)(ap_syscall_stack + PAGE_SIZE - 1)); 9940 9941 /* passthrough lapic to L2 */ 9942 disable_intercept_for_x2apic_msrs(); 9943 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 9944 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 9945 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 9946 9947 /* Set guest activity state to wait-for-SIPI state */ 9948 vmcs_write(GUEST_ACTV_STATE, ACTV_WAIT_SIPI); 9949 9950 vmx_set_test_stage(1); 9951 9952 /* AP enter guest */ 9953 enter_guest(); 9954 9955 if (vmcs_read(EXI_REASON) == VMX_SIPI) { 9956 report_pass("AP: Handle SIPI VMExit"); 9957 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 9958 vmx_set_test_stage(2); 9959 } else { 9960 report_fail("AP: Unexpected VMExit, reason=%ld", vmcs_read(EXI_REASON)); 9961 vmx_off(); 9962 return; 9963 } 9964 9965 /* AP enter guest */ 9966 enter_guest(); 9967 9968 report(vmcs_read(EXI_REASON) != VMX_SIPI, 9969 "AP: should no SIPI VMExit since activity is not in WAIT_SIPI state"); 9970 9971 /* notify BSP that AP is already exit from non-root mode */ 9972 vmx_set_test_stage(5); 9973 9974 /* Leave VMX operation */ 9975 vmx_off(); 9976 } 9977 9978 static void vmx_sipi_signal_test(void) 9979 { 9980 if (!(rdmsr(MSR_IA32_VMX_MISC) & MSR_IA32_VMX_MISC_ACTIVITY_WAIT_SIPI)) { 9981 report_skip("%s : \"ACTIVITY_WAIT_SIPI state\" not supported", __func__); 9982 return; 9983 } 9984 9985 if (cpu_count() < 2) { 9986 report_skip("%s : CPU count < 2", __func__); 9987 return; 9988 } 9989 9990 u64 cpu_ctrl_0 = CPU_SECONDARY; 9991 u64 cpu_ctrl_1 = 0; 9992 9993 /* passthrough lapic to L2 */ 9994 disable_intercept_for_x2apic_msrs(); 9995 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 9996 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 9997 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 9998 9999 test_set_guest(vmx_sipi_test_guest); 10000 10001 /* update CR3 on AP */ 10002 on_cpu(1, update_cr3, (void *)read_cr3()); 10003 10004 /* start AP */ 10005 on_cpu_async(1, sipi_test_ap_thread, NULL); 10006 10007 vmx_set_test_stage(0); 10008 10009 /* BSP enter guest */ 10010 enter_guest(); 10011 } 10012 10013 10014 enum vmcs_access { 10015 ACCESS_VMREAD, 10016 ACCESS_VMWRITE, 10017 ACCESS_NONE, 10018 }; 10019 10020 struct vmcs_shadow_test_common { 10021 enum vmcs_access op; 10022 enum Reason reason; 10023 u64 field; 10024 u64 value; 10025 u64 flags; 10026 u64 time; 10027 } l1_l2_common; 10028 10029 static inline u64 vmread_flags(u64 field, u64 *val) 10030 { 10031 u64 flags; 10032 10033 asm volatile ("vmread %2, %1; pushf; pop %0" 10034 : "=r" (flags), "=rm" (*val) : "r" (field) : "cc"); 10035 return flags & X86_EFLAGS_ALU; 10036 } 10037 10038 static inline u64 vmwrite_flags(u64 field, u64 val) 10039 { 10040 u64 flags; 10041 10042 asm volatile ("vmwrite %1, %2; pushf; pop %0" 10043 : "=r"(flags) : "rm" (val), "r" (field) : "cc"); 10044 return flags & X86_EFLAGS_ALU; 10045 } 10046 10047 static void vmx_vmcs_shadow_test_guest(void) 10048 { 10049 struct vmcs_shadow_test_common *c = &l1_l2_common; 10050 u64 start; 10051 10052 while (c->op != ACCESS_NONE) { 10053 start = rdtsc(); 10054 switch (c->op) { 10055 default: 10056 c->flags = -1ull; 10057 break; 10058 case ACCESS_VMREAD: 10059 c->flags = vmread_flags(c->field, &c->value); 10060 break; 10061 case ACCESS_VMWRITE: 10062 c->flags = vmwrite_flags(c->field, 0); 10063 break; 10064 } 10065 c->time = rdtsc() - start; 10066 vmcall(); 10067 } 10068 } 10069 10070 static u64 vmread_from_shadow(u64 field) 10071 { 10072 struct vmcs *primary; 10073 struct vmcs *shadow; 10074 u64 value; 10075 10076 TEST_ASSERT(!vmcs_save(&primary)); 10077 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 10078 TEST_ASSERT(!make_vmcs_current(shadow)); 10079 value = vmcs_read(field); 10080 TEST_ASSERT(!make_vmcs_current(primary)); 10081 return value; 10082 } 10083 10084 static u64 vmwrite_to_shadow(u64 field, u64 value) 10085 { 10086 struct vmcs *primary; 10087 struct vmcs *shadow; 10088 10089 TEST_ASSERT(!vmcs_save(&primary)); 10090 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 10091 TEST_ASSERT(!make_vmcs_current(shadow)); 10092 vmcs_write(field, value); 10093 value = vmcs_read(field); 10094 TEST_ASSERT(!make_vmcs_current(primary)); 10095 return value; 10096 } 10097 10098 static void vmcs_shadow_test_access(u8 *bitmap[2], enum vmcs_access access) 10099 { 10100 struct vmcs_shadow_test_common *c = &l1_l2_common; 10101 10102 c->op = access; 10103 vmcs_write(VMX_INST_ERROR, 0); 10104 enter_guest(); 10105 c->reason = vmcs_read(EXI_REASON) & 0xffff; 10106 if (c->reason != VMX_VMCALL) { 10107 skip_exit_insn(); 10108 enter_guest(); 10109 } 10110 skip_exit_vmcall(); 10111 } 10112 10113 static void vmcs_shadow_test_field(u8 *bitmap[2], u64 field) 10114 { 10115 struct vmcs_shadow_test_common *c = &l1_l2_common; 10116 struct vmcs *shadow; 10117 u64 value; 10118 uintptr_t flags[2]; 10119 bool good_shadow; 10120 u32 vmx_inst_error; 10121 10122 report_prefix_pushf("field %lx", field); 10123 c->field = field; 10124 10125 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 10126 if (shadow != (struct vmcs *)-1ull) { 10127 flags[ACCESS_VMREAD] = vmread_flags(field, &value); 10128 flags[ACCESS_VMWRITE] = vmwrite_flags(field, value); 10129 good_shadow = !flags[ACCESS_VMREAD] && !flags[ACCESS_VMWRITE]; 10130 } else { 10131 /* 10132 * When VMCS link pointer is -1ull, VMWRITE/VMREAD on 10133 * shadowed-fields should fail with setting RFLAGS.CF. 10134 */ 10135 flags[ACCESS_VMREAD] = X86_EFLAGS_CF; 10136 flags[ACCESS_VMWRITE] = X86_EFLAGS_CF; 10137 good_shadow = false; 10138 } 10139 10140 /* Intercept both VMREAD and VMWRITE. */ 10141 report_prefix_push("no VMREAD/VMWRITE permission"); 10142 /* VMWRITE/VMREAD done on reserved-bit should always intercept */ 10143 if (!(field >> VMCS_FIELD_RESERVED_SHIFT)) { 10144 set_bit(field, bitmap[ACCESS_VMREAD]); 10145 set_bit(field, bitmap[ACCESS_VMWRITE]); 10146 } 10147 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10148 report(c->reason == VMX_VMWRITE, "not shadowed for VMWRITE"); 10149 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10150 report(c->reason == VMX_VMREAD, "not shadowed for VMREAD"); 10151 report_prefix_pop(); 10152 10153 if (field >> VMCS_FIELD_RESERVED_SHIFT) 10154 goto out; 10155 10156 /* Permit shadowed VMREAD. */ 10157 report_prefix_push("VMREAD permission only"); 10158 clear_bit(field, bitmap[ACCESS_VMREAD]); 10159 set_bit(field, bitmap[ACCESS_VMWRITE]); 10160 if (good_shadow) 10161 value = vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 10162 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10163 report(c->reason == VMX_VMWRITE, "not shadowed for VMWRITE"); 10164 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10165 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10166 report(c->reason == VMX_VMCALL, "shadowed for VMREAD (in %ld cycles)", 10167 c->time); 10168 report(c->flags == flags[ACCESS_VMREAD], 10169 "ALU flags after VMREAD (%lx) are as expected (%lx)", 10170 c->flags, flags[ACCESS_VMREAD]); 10171 if (good_shadow) 10172 report(c->value == value, 10173 "value read from shadow (%lx) is as expected (%lx)", 10174 c->value, value); 10175 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 10176 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10177 "VMX_INST_ERROR (%d) is as expected (%d)", 10178 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10179 report_prefix_pop(); 10180 10181 /* Permit shadowed VMWRITE. */ 10182 report_prefix_push("VMWRITE permission only"); 10183 set_bit(field, bitmap[ACCESS_VMREAD]); 10184 clear_bit(field, bitmap[ACCESS_VMWRITE]); 10185 if (good_shadow) 10186 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 10187 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10188 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10189 report(c->reason == VMX_VMCALL, 10190 "shadowed for VMWRITE (in %ld cycles)", 10191 c->time); 10192 report(c->flags == flags[ACCESS_VMREAD], 10193 "ALU flags after VMWRITE (%lx) are as expected (%lx)", 10194 c->flags, flags[ACCESS_VMREAD]); 10195 if (good_shadow) { 10196 value = vmread_from_shadow(field); 10197 report(value == 0, 10198 "shadow VMCS value (%lx) is as expected (%lx)", value, 10199 0ul); 10200 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 10201 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10202 "VMX_INST_ERROR (%d) is as expected (%d)", 10203 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10204 } 10205 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10206 report(c->reason == VMX_VMREAD, "not shadowed for VMREAD"); 10207 report_prefix_pop(); 10208 10209 /* Permit shadowed VMREAD and VMWRITE. */ 10210 report_prefix_push("VMREAD and VMWRITE permission"); 10211 clear_bit(field, bitmap[ACCESS_VMREAD]); 10212 clear_bit(field, bitmap[ACCESS_VMWRITE]); 10213 if (good_shadow) 10214 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 10215 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10216 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10217 report(c->reason == VMX_VMCALL, 10218 "shadowed for VMWRITE (in %ld cycles)", 10219 c->time); 10220 report(c->flags == flags[ACCESS_VMREAD], 10221 "ALU flags after VMWRITE (%lx) are as expected (%lx)", 10222 c->flags, flags[ACCESS_VMREAD]); 10223 if (good_shadow) { 10224 value = vmread_from_shadow(field); 10225 report(value == 0, 10226 "shadow VMCS value (%lx) is as expected (%lx)", value, 10227 0ul); 10228 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 10229 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10230 "VMX_INST_ERROR (%d) is as expected (%d)", 10231 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10232 } 10233 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10234 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10235 report(c->reason == VMX_VMCALL, "shadowed for VMREAD (in %ld cycles)", 10236 c->time); 10237 report(c->flags == flags[ACCESS_VMREAD], 10238 "ALU flags after VMREAD (%lx) are as expected (%lx)", 10239 c->flags, flags[ACCESS_VMREAD]); 10240 if (good_shadow) 10241 report(c->value == 0, 10242 "value read from shadow (%lx) is as expected (%lx)", 10243 c->value, 0ul); 10244 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 10245 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10246 "VMX_INST_ERROR (%d) is as expected (%d)", 10247 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10248 report_prefix_pop(); 10249 10250 out: 10251 report_prefix_pop(); 10252 } 10253 10254 static void vmx_vmcs_shadow_test_body(u8 *bitmap[2]) 10255 { 10256 unsigned base; 10257 unsigned index; 10258 unsigned bit; 10259 unsigned highest_index = rdmsr(MSR_IA32_VMX_VMCS_ENUM); 10260 10261 /* Run test on all possible valid VMCS fields */ 10262 for (base = 0; 10263 base < (1 << VMCS_FIELD_RESERVED_SHIFT); 10264 base += (1 << VMCS_FIELD_TYPE_SHIFT)) 10265 for (index = 0; index <= highest_index; index++) 10266 vmcs_shadow_test_field(bitmap, base + index); 10267 10268 /* 10269 * Run tests on some invalid VMCS fields 10270 * (Have reserved bit set). 10271 */ 10272 for (bit = VMCS_FIELD_RESERVED_SHIFT; bit < VMCS_FIELD_BIT_SIZE; bit++) 10273 vmcs_shadow_test_field(bitmap, (1ull << bit)); 10274 } 10275 10276 static void vmx_vmcs_shadow_test(void) 10277 { 10278 u8 *bitmap[2]; 10279 struct vmcs *shadow; 10280 10281 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 10282 report_skip("%s : \"Activate secondary controls\" not supported", __func__); 10283 return; 10284 } 10285 10286 if (!(ctrl_cpu_rev[1].clr & CPU_SHADOW_VMCS)) { 10287 report_skip("%s : \"VMCS shadowing\" not supported", __func__); 10288 return; 10289 } 10290 10291 if (!(rdmsr(MSR_IA32_VMX_MISC) & 10292 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS)) { 10293 report_skip("%s : VMWRITE can't modify VM-exit information fields.", __func__); 10294 return; 10295 } 10296 10297 test_set_guest(vmx_vmcs_shadow_test_guest); 10298 10299 bitmap[ACCESS_VMREAD] = alloc_page(); 10300 bitmap[ACCESS_VMWRITE] = alloc_page(); 10301 10302 vmcs_write(VMREAD_BITMAP, virt_to_phys(bitmap[ACCESS_VMREAD])); 10303 vmcs_write(VMWRITE_BITMAP, virt_to_phys(bitmap[ACCESS_VMWRITE])); 10304 10305 shadow = alloc_page(); 10306 shadow->hdr.revision_id = basic.revision; 10307 shadow->hdr.shadow_vmcs = 1; 10308 TEST_ASSERT(!vmcs_clear(shadow)); 10309 10310 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_RDTSC); 10311 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY); 10312 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_SHADOW_VMCS); 10313 10314 vmcs_write(VMCS_LINK_PTR, virt_to_phys(shadow)); 10315 report_prefix_push("valid link pointer"); 10316 vmx_vmcs_shadow_test_body(bitmap); 10317 report_prefix_pop(); 10318 10319 vmcs_write(VMCS_LINK_PTR, -1ull); 10320 report_prefix_push("invalid link pointer"); 10321 vmx_vmcs_shadow_test_body(bitmap); 10322 report_prefix_pop(); 10323 10324 l1_l2_common.op = ACCESS_NONE; 10325 enter_guest(); 10326 } 10327 10328 /* 10329 * This test monitors the difference between a guest RDTSC instruction 10330 * and the IA32_TIME_STAMP_COUNTER MSR value stored in the VMCS12 10331 * VM-exit MSR-store list when taking a VM-exit on the instruction 10332 * following RDTSC. 10333 */ 10334 #define RDTSC_DIFF_ITERS 100000 10335 #define RDTSC_DIFF_FAILS 100 10336 #define HOST_CAPTURED_GUEST_TSC_DIFF_THRESHOLD 750 10337 10338 /* 10339 * Set 'use TSC offsetting' and set the guest offset to the 10340 * inverse of the host's current TSC value, so that the guest starts running 10341 * with an effective TSC value of 0. 10342 */ 10343 static void reset_guest_tsc_to_zero(void) 10344 { 10345 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_USE_TSC_OFFSET); 10346 vmcs_write(TSC_OFFSET, -rdtsc()); 10347 } 10348 10349 static void rdtsc_vmexit_diff_test_guest(void) 10350 { 10351 int i; 10352 10353 for (i = 0; i < RDTSC_DIFF_ITERS; i++) 10354 /* Ensure rdtsc is the last instruction before the vmcall. */ 10355 asm volatile("rdtsc; vmcall" : : : "eax", "edx"); 10356 } 10357 10358 /* 10359 * This function only considers the "use TSC offsetting" VM-execution 10360 * control. It does not handle "use TSC scaling" (because the latter 10361 * isn't available to the host today.) 10362 */ 10363 static unsigned long long host_time_to_guest_time(unsigned long long t) 10364 { 10365 TEST_ASSERT(!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 10366 !(vmcs_read(CPU_EXEC_CTRL1) & CPU_USE_TSC_SCALING)); 10367 10368 if (vmcs_read(CPU_EXEC_CTRL0) & CPU_USE_TSC_OFFSET) 10369 t += vmcs_read(TSC_OFFSET); 10370 10371 return t; 10372 } 10373 10374 static unsigned long long rdtsc_vmexit_diff_test_iteration(void) 10375 { 10376 unsigned long long guest_tsc, host_to_guest_tsc; 10377 10378 enter_guest(); 10379 skip_exit_vmcall(); 10380 guest_tsc = (u32) regs.rax + (regs.rdx << 32); 10381 host_to_guest_tsc = host_time_to_guest_time(exit_msr_store[0].value); 10382 10383 return host_to_guest_tsc - guest_tsc; 10384 } 10385 10386 static void rdtsc_vmexit_diff_test(void) 10387 { 10388 unsigned long long delta; 10389 int fail = 0; 10390 int i; 10391 10392 if (!(ctrl_cpu_rev[0].clr & CPU_USE_TSC_OFFSET)) 10393 test_skip("CPU doesn't support the 'use TSC offsetting' processor-based VM-execution control.\n"); 10394 10395 test_set_guest(rdtsc_vmexit_diff_test_guest); 10396 10397 reset_guest_tsc_to_zero(); 10398 10399 /* 10400 * Set up the VMCS12 VM-exit MSR-store list to store just one 10401 * MSR: IA32_TIME_STAMP_COUNTER. Note that the value stored is 10402 * in the host time domain (i.e., it is not adjusted according 10403 * to the TSC multiplier and TSC offset fields in the VMCS12, 10404 * as a guest RDTSC would be.) 10405 */ 10406 exit_msr_store = alloc_page(); 10407 exit_msr_store[0].index = MSR_IA32_TSC; 10408 vmcs_write(EXI_MSR_ST_CNT, 1); 10409 vmcs_write(EXIT_MSR_ST_ADDR, virt_to_phys(exit_msr_store)); 10410 10411 for (i = 0; i < RDTSC_DIFF_ITERS && fail < RDTSC_DIFF_FAILS; i++) { 10412 delta = rdtsc_vmexit_diff_test_iteration(); 10413 if (delta >= HOST_CAPTURED_GUEST_TSC_DIFF_THRESHOLD) 10414 fail++; 10415 } 10416 10417 enter_guest(); 10418 10419 report(fail < RDTSC_DIFF_FAILS, 10420 "RDTSC to VM-exit delta too high in %d of %d iterations, last = %llu", 10421 fail, i, delta); 10422 } 10423 10424 static int invalid_msr_init(struct vmcs *vmcs) 10425 { 10426 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 10427 printf("\tPreemption timer is not supported\n"); 10428 return VMX_TEST_EXIT; 10429 } 10430 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 10431 preempt_val = 10000000; 10432 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 10433 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 10434 10435 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 10436 printf("\tSave preemption value is not supported\n"); 10437 10438 vmcs_write(ENT_MSR_LD_CNT, 1); 10439 vmcs_write(ENTER_MSR_LD_ADDR, (u64)0x13370000); 10440 10441 return VMX_TEST_START; 10442 } 10443 10444 10445 static void invalid_msr_main(void) 10446 { 10447 report_fail("Invalid MSR load"); 10448 } 10449 10450 static int invalid_msr_exit_handler(union exit_reason exit_reason) 10451 { 10452 report_fail("Invalid MSR load"); 10453 print_vmexit_info(exit_reason); 10454 return VMX_TEST_EXIT; 10455 } 10456 10457 static int invalid_msr_entry_failure(struct vmentry_result *result) 10458 { 10459 report(result->exit_reason.failed_vmentry && 10460 result->exit_reason.basic == VMX_FAIL_MSR, "Invalid MSR load"); 10461 return VMX_TEST_VMEXIT; 10462 } 10463 10464 /* 10465 * The max number of MSRs in an atomic switch MSR list is: 10466 * (111B + 1) * 512 = 4096 10467 * 10468 * Each list entry consumes: 10469 * 4-byte MSR index + 4 bytes reserved + 8-byte data = 16 bytes 10470 * 10471 * Allocate 128 kB to cover max_msr_list_size (i.e., 64 kB) and then some. 10472 */ 10473 static const u32 msr_list_page_order = 5; 10474 10475 static void atomic_switch_msr_limit_test_guest(void) 10476 { 10477 vmcall(); 10478 } 10479 10480 static void populate_msr_list(struct vmx_msr_entry *msr_list, 10481 size_t byte_capacity, int count) 10482 { 10483 int i; 10484 10485 for (i = 0; i < count; i++) { 10486 msr_list[i].index = MSR_IA32_TSC; 10487 msr_list[i].reserved = 0; 10488 msr_list[i].value = 0x1234567890abcdef; 10489 } 10490 10491 memset(msr_list + count, 0xff, 10492 byte_capacity - count * sizeof(*msr_list)); 10493 } 10494 10495 static int max_msr_list_size(void) 10496 { 10497 u32 vmx_misc = rdmsr(MSR_IA32_VMX_MISC); 10498 u32 factor = ((vmx_misc & GENMASK(27, 25)) >> 25) + 1; 10499 10500 return factor * 512; 10501 } 10502 10503 static void atomic_switch_msrs_test(int count) 10504 { 10505 struct vmx_msr_entry *vm_enter_load; 10506 struct vmx_msr_entry *vm_exit_load; 10507 struct vmx_msr_entry *vm_exit_store; 10508 int max_allowed = max_msr_list_size(); 10509 int byte_capacity = 1ul << (msr_list_page_order + PAGE_SHIFT); 10510 /* Exceeding the max MSR list size at exit triggers KVM to abort. */ 10511 int exit_count = count > max_allowed ? max_allowed : count; 10512 int cleanup_count = count > max_allowed ? 2 : 1; 10513 int i; 10514 10515 /* 10516 * Check for the IA32_TSC MSR, 10517 * available with the "TSC flag" and used to populate the MSR lists. 10518 */ 10519 if (!(cpuid(1).d & (1 << 4))) { 10520 report_skip("%s : \"Time Stamp Counter\" not supported", __func__); 10521 return; 10522 } 10523 10524 /* Set L2 guest. */ 10525 test_set_guest(atomic_switch_msr_limit_test_guest); 10526 10527 /* Setup atomic MSR switch lists. */ 10528 vm_enter_load = alloc_pages(msr_list_page_order); 10529 vm_exit_load = alloc_pages(msr_list_page_order); 10530 vm_exit_store = alloc_pages(msr_list_page_order); 10531 10532 vmcs_write(ENTER_MSR_LD_ADDR, (u64)vm_enter_load); 10533 vmcs_write(EXIT_MSR_LD_ADDR, (u64)vm_exit_load); 10534 vmcs_write(EXIT_MSR_ST_ADDR, (u64)vm_exit_store); 10535 10536 /* 10537 * VM-Enter should succeed up to the max number of MSRs per list, and 10538 * should not consume junk beyond the last entry. 10539 */ 10540 populate_msr_list(vm_enter_load, byte_capacity, count); 10541 populate_msr_list(vm_exit_load, byte_capacity, exit_count); 10542 populate_msr_list(vm_exit_store, byte_capacity, exit_count); 10543 10544 vmcs_write(ENT_MSR_LD_CNT, count); 10545 vmcs_write(EXI_MSR_LD_CNT, exit_count); 10546 vmcs_write(EXI_MSR_ST_CNT, exit_count); 10547 10548 if (count <= max_allowed) { 10549 enter_guest(); 10550 assert_exit_reason(VMX_VMCALL); 10551 skip_exit_vmcall(); 10552 } else { 10553 u32 exit_qual; 10554 10555 test_guest_state("Invalid MSR Load Count", true, count, 10556 "ENT_MSR_LD_CNT"); 10557 10558 exit_qual = vmcs_read(EXI_QUALIFICATION); 10559 report(exit_qual == max_allowed + 1, "exit_qual, %u, is %u.", 10560 exit_qual, max_allowed + 1); 10561 } 10562 10563 /* Cleanup. */ 10564 vmcs_write(ENT_MSR_LD_CNT, 0); 10565 vmcs_write(EXI_MSR_LD_CNT, 0); 10566 vmcs_write(EXI_MSR_ST_CNT, 0); 10567 for (i = 0; i < cleanup_count; i++) { 10568 enter_guest(); 10569 skip_exit_vmcall(); 10570 } 10571 free_pages_by_order(vm_enter_load, msr_list_page_order); 10572 free_pages_by_order(vm_exit_load, msr_list_page_order); 10573 free_pages_by_order(vm_exit_store, msr_list_page_order); 10574 } 10575 10576 static void atomic_switch_max_msrs_test(void) 10577 { 10578 atomic_switch_msrs_test(max_msr_list_size()); 10579 } 10580 10581 static void atomic_switch_overflow_msrs_test(void) 10582 { 10583 if (test_device_enabled()) 10584 atomic_switch_msrs_test(max_msr_list_size() + 1); 10585 else 10586 test_skip("Test is only supported on KVM"); 10587 } 10588 10589 static void vmx_pf_exception_test_guest(void) 10590 { 10591 ac_test_run(PT_LEVEL_PML4); 10592 } 10593 10594 typedef void (*invalidate_tlb_t)(void *data); 10595 10596 static void __vmx_pf_exception_test(invalidate_tlb_t inv_fn, void *data) 10597 { 10598 u64 efer; 10599 struct cpuid cpuid; 10600 10601 test_set_guest(vmx_pf_exception_test_guest); 10602 10603 /* Intercept INVLPG when to perform TLB invalidation from L1 (this). */ 10604 if (inv_fn) 10605 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INVLPG); 10606 else 10607 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INVLPG); 10608 10609 enter_guest(); 10610 10611 while (vmcs_read(EXI_REASON) != VMX_VMCALL) { 10612 switch (vmcs_read(EXI_REASON)) { 10613 case VMX_RDMSR: 10614 assert(regs.rcx == MSR_EFER); 10615 efer = vmcs_read(GUEST_EFER); 10616 regs.rdx = efer >> 32; 10617 regs.rax = efer & 0xffffffff; 10618 break; 10619 case VMX_WRMSR: 10620 assert(regs.rcx == MSR_EFER); 10621 efer = regs.rdx << 32 | (regs.rax & 0xffffffff); 10622 vmcs_write(GUEST_EFER, efer); 10623 break; 10624 case VMX_CPUID: 10625 cpuid = (struct cpuid) {0, 0, 0, 0}; 10626 cpuid = raw_cpuid(regs.rax, regs.rcx); 10627 regs.rax = cpuid.a; 10628 regs.rbx = cpuid.b; 10629 regs.rcx = cpuid.c; 10630 regs.rdx = cpuid.d; 10631 break; 10632 case VMX_INVLPG: 10633 inv_fn(data); 10634 break; 10635 default: 10636 assert_msg(false, 10637 "Unexpected exit to L1, exit_reason: %s (0x%lx)", 10638 exit_reason_description(vmcs_read(EXI_REASON)), 10639 vmcs_read(EXI_REASON)); 10640 } 10641 skip_exit_insn(); 10642 enter_guest(); 10643 } 10644 10645 assert_exit_reason(VMX_VMCALL); 10646 } 10647 10648 static void vmx_pf_exception_test(void) 10649 { 10650 __vmx_pf_exception_test(NULL, NULL); 10651 } 10652 10653 static void invalidate_tlb_no_vpid(void *data) 10654 { 10655 /* If VPID is disabled, the TLB is flushed on VM-Enter and VM-Exit. */ 10656 } 10657 10658 static void vmx_pf_no_vpid_test(void) 10659 { 10660 if (is_vpid_supported()) 10661 vmcs_clear_bits(CPU_EXEC_CTRL1, CPU_VPID); 10662 10663 __vmx_pf_exception_test(invalidate_tlb_no_vpid, NULL); 10664 } 10665 10666 static void invalidate_tlb_invvpid_addr(void *data) 10667 { 10668 invvpid(INVVPID_ALL, *(u16 *)data, vmcs_read(EXI_QUALIFICATION)); 10669 } 10670 10671 static void invalidate_tlb_new_vpid(void *data) 10672 { 10673 u16 *vpid = data; 10674 10675 /* 10676 * Bump VPID to effectively flush L2's TLB from L0's perspective. 10677 * Invalidate all VPIDs when the VPID wraps to zero as hardware/KVM is 10678 * architecturally allowed to keep TLB entries indefinitely. 10679 */ 10680 ++(*vpid); 10681 if (*vpid == 0) { 10682 ++(*vpid); 10683 invvpid(INVVPID_ALL, 0, 0); 10684 } 10685 vmcs_write(VPID, *vpid); 10686 } 10687 10688 static void __vmx_pf_vpid_test(invalidate_tlb_t inv_fn, u16 vpid) 10689 { 10690 if (!is_vpid_supported()) 10691 test_skip("VPID unsupported"); 10692 10693 if (!is_invvpid_supported()) 10694 test_skip("INVVPID unsupported"); 10695 10696 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY); 10697 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_VPID); 10698 vmcs_write(VPID, vpid); 10699 10700 __vmx_pf_exception_test(inv_fn, &vpid); 10701 } 10702 10703 static void vmx_pf_invvpid_test(void) 10704 { 10705 if (!is_invvpid_type_supported(INVVPID_ADDR)) 10706 test_skip("INVVPID ADDR unsupported"); 10707 10708 __vmx_pf_vpid_test(invalidate_tlb_invvpid_addr, 0xaaaa); 10709 } 10710 10711 static void vmx_pf_vpid_test(void) 10712 { 10713 /* Need INVVPID(ALL) to flush VPIDs upon wrap/reuse. */ 10714 if (!is_invvpid_type_supported(INVVPID_ALL)) 10715 test_skip("INVVPID ALL unsupported"); 10716 10717 __vmx_pf_vpid_test(invalidate_tlb_new_vpid, 1); 10718 } 10719 10720 static void vmx_l2_gp_test(void) 10721 { 10722 *(volatile u64 *)NONCANONICAL = 0; 10723 } 10724 10725 static void vmx_l2_ud_test(void) 10726 { 10727 asm volatile ("ud2"); 10728 } 10729 10730 static void vmx_l2_de_test(void) 10731 { 10732 asm volatile ( 10733 "xor %%eax, %%eax\n\t" 10734 "xor %%ebx, %%ebx\n\t" 10735 "xor %%edx, %%edx\n\t" 10736 "idiv %%ebx\n\t" 10737 ::: "eax", "ebx", "edx"); 10738 } 10739 10740 static void vmx_l2_bp_test(void) 10741 { 10742 asm volatile ("int3"); 10743 } 10744 10745 static void vmx_l2_db_test(void) 10746 { 10747 write_rflags(read_rflags() | X86_EFLAGS_TF); 10748 } 10749 10750 static uint64_t usermode_callback(void) 10751 { 10752 /* 10753 * Trigger an #AC by writing 8 bytes to a 4-byte aligned address. 10754 * Disclaimer: It is assumed that the stack pointer is aligned 10755 * on a 16-byte boundary as x86_64 stacks should be. 10756 */ 10757 asm volatile("movq $0, -0x4(%rsp)"); 10758 10759 return 0; 10760 } 10761 10762 static void vmx_l2_ac_test(void) 10763 { 10764 bool hit_ac = false; 10765 10766 write_cr0(read_cr0() | X86_CR0_AM); 10767 write_rflags(read_rflags() | X86_EFLAGS_AC); 10768 10769 run_in_user(usermode_callback, AC_VECTOR, 0, 0, 0, 0, &hit_ac); 10770 report(hit_ac, "Usermode #AC handled in L2"); 10771 vmcall(); 10772 } 10773 10774 struct vmx_exception_test { 10775 u8 vector; 10776 void (*guest_code)(void); 10777 }; 10778 10779 struct vmx_exception_test vmx_exception_tests[] = { 10780 { GP_VECTOR, vmx_l2_gp_test }, 10781 { UD_VECTOR, vmx_l2_ud_test }, 10782 { DE_VECTOR, vmx_l2_de_test }, 10783 { DB_VECTOR, vmx_l2_db_test }, 10784 { BP_VECTOR, vmx_l2_bp_test }, 10785 { AC_VECTOR, vmx_l2_ac_test }, 10786 }; 10787 10788 static u8 vmx_exception_test_vector; 10789 10790 static void vmx_exception_handler(struct ex_regs *regs) 10791 { 10792 report(regs->vector == vmx_exception_test_vector, 10793 "Handling %s in L2's exception handler", 10794 exception_mnemonic(vmx_exception_test_vector)); 10795 vmcall(); 10796 } 10797 10798 static void handle_exception_in_l2(u8 vector) 10799 { 10800 handler old_handler = handle_exception(vector, vmx_exception_handler); 10801 10802 vmx_exception_test_vector = vector; 10803 10804 enter_guest(); 10805 report(vmcs_read(EXI_REASON) == VMX_VMCALL, 10806 "%s handled by L2", exception_mnemonic(vector)); 10807 10808 handle_exception(vector, old_handler); 10809 } 10810 10811 static void handle_exception_in_l1(u32 vector) 10812 { 10813 u32 old_eb = vmcs_read(EXC_BITMAP); 10814 10815 vmcs_write(EXC_BITMAP, old_eb | (1u << vector)); 10816 10817 enter_guest(); 10818 10819 report((vmcs_read(EXI_REASON) == VMX_EXC_NMI) && 10820 ((vmcs_read(EXI_INTR_INFO) & 0xff) == vector), 10821 "%s handled by L1", exception_mnemonic(vector)); 10822 10823 vmcs_write(EXC_BITMAP, old_eb); 10824 } 10825 10826 static void vmx_exception_test(void) 10827 { 10828 struct vmx_exception_test *t; 10829 int i; 10830 10831 for (i = 0; i < ARRAY_SIZE(vmx_exception_tests); i++) { 10832 t = &vmx_exception_tests[i]; 10833 10834 /* 10835 * Override the guest code before each run even though it's the 10836 * same code, the VMCS guest state needs to be reinitialized. 10837 */ 10838 test_override_guest(t->guest_code); 10839 handle_exception_in_l2(t->vector); 10840 10841 test_override_guest(t->guest_code); 10842 handle_exception_in_l1(t->vector); 10843 } 10844 10845 test_set_guest_finished(); 10846 } 10847 10848 #define TEST(name) { #name, .v2 = name } 10849 10850 /* name/init/guest_main/exit_handler/syscall_handler/guest_regs */ 10851 struct vmx_test vmx_tests[] = { 10852 { "null", NULL, basic_guest_main, basic_exit_handler, NULL, {0} }, 10853 { "vmenter", NULL, vmenter_main, vmenter_exit_handler, NULL, {0} }, 10854 { "preemption timer", preemption_timer_init, preemption_timer_main, 10855 preemption_timer_exit_handler, NULL, {0} }, 10856 { "control field PAT", test_ctrl_pat_init, test_ctrl_pat_main, 10857 test_ctrl_pat_exit_handler, NULL, {0} }, 10858 { "control field EFER", test_ctrl_efer_init, test_ctrl_efer_main, 10859 test_ctrl_efer_exit_handler, NULL, {0} }, 10860 { "CR shadowing", NULL, cr_shadowing_main, 10861 cr_shadowing_exit_handler, NULL, {0} }, 10862 { "I/O bitmap", iobmp_init, iobmp_main, iobmp_exit_handler, 10863 NULL, {0} }, 10864 { "instruction intercept", insn_intercept_init, insn_intercept_main, 10865 insn_intercept_exit_handler, NULL, {0} }, 10866 { "EPT A/D disabled", ept_init, ept_main, ept_exit_handler, NULL, {0} }, 10867 { "EPT A/D enabled", eptad_init, eptad_main, eptad_exit_handler, NULL, {0} }, 10868 { "PML", pml_init, pml_main, pml_exit_handler, NULL, {0} }, 10869 { "interrupt", interrupt_init, interrupt_main, 10870 interrupt_exit_handler, NULL, {0} }, 10871 { "nmi_hlt", nmi_hlt_init, nmi_hlt_main, 10872 nmi_hlt_exit_handler, NULL, {0} }, 10873 { "debug controls", dbgctls_init, dbgctls_main, dbgctls_exit_handler, 10874 NULL, {0} }, 10875 { "MSR switch", msr_switch_init, msr_switch_main, 10876 msr_switch_exit_handler, NULL, {0}, msr_switch_entry_failure }, 10877 { "vmmcall", vmmcall_init, vmmcall_main, vmmcall_exit_handler, NULL, {0} }, 10878 { "disable RDTSCP", disable_rdtscp_init, disable_rdtscp_main, 10879 disable_rdtscp_exit_handler, NULL, {0} }, 10880 { "int3", int3_init, int3_guest_main, int3_exit_handler, NULL, {0} }, 10881 { "into", into_init, into_guest_main, into_exit_handler, NULL, {0} }, 10882 { "exit_monitor_from_l2_test", NULL, exit_monitor_from_l2_main, 10883 exit_monitor_from_l2_handler, NULL, {0} }, 10884 { "invalid_msr", invalid_msr_init, invalid_msr_main, 10885 invalid_msr_exit_handler, NULL, {0}, invalid_msr_entry_failure}, 10886 /* Basic V2 tests. */ 10887 TEST(v2_null_test), 10888 TEST(v2_multiple_entries_test), 10889 TEST(fixture_test_case1), 10890 TEST(fixture_test_case2), 10891 /* Opcode tests. */ 10892 TEST(invvpid_test), 10893 /* VM-entry tests */ 10894 TEST(vmx_controls_test), 10895 TEST(vmx_host_state_area_test), 10896 TEST(vmx_guest_state_area_test), 10897 TEST(vmentry_movss_shadow_test), 10898 TEST(vmentry_unrestricted_guest_test), 10899 /* APICv tests */ 10900 TEST(vmx_eoi_bitmap_ioapic_scan_test), 10901 TEST(vmx_hlt_with_rvi_test), 10902 TEST(apic_reg_virt_test), 10903 TEST(virt_x2apic_mode_test), 10904 /* APIC pass-through tests */ 10905 TEST(vmx_apic_passthrough_test), 10906 TEST(vmx_apic_passthrough_thread_test), 10907 TEST(vmx_apic_passthrough_tpr_threshold_test), 10908 TEST(vmx_init_signal_test), 10909 TEST(vmx_sipi_signal_test), 10910 /* VMCS Shadowing tests */ 10911 TEST(vmx_vmcs_shadow_test), 10912 /* Regression tests */ 10913 TEST(vmx_ldtr_test), 10914 TEST(vmx_cr_load_test), 10915 TEST(vmx_cr4_osxsave_test), 10916 TEST(vmx_nm_test), 10917 TEST(vmx_db_test), 10918 TEST(vmx_nmi_window_test), 10919 TEST(vmx_intr_window_test), 10920 TEST(vmx_pending_event_test), 10921 TEST(vmx_pending_event_hlt_test), 10922 TEST(vmx_store_tsc_test), 10923 TEST(vmx_preemption_timer_zero_test), 10924 TEST(vmx_preemption_timer_tf_test), 10925 TEST(vmx_preemption_timer_expiry_test), 10926 /* EPT access tests. */ 10927 TEST(ept_access_test_not_present), 10928 TEST(ept_access_test_read_only), 10929 TEST(ept_access_test_write_only), 10930 TEST(ept_access_test_read_write), 10931 TEST(ept_access_test_execute_only), 10932 TEST(ept_access_test_read_execute), 10933 TEST(ept_access_test_write_execute), 10934 TEST(ept_access_test_read_write_execute), 10935 TEST(ept_access_test_reserved_bits), 10936 TEST(ept_access_test_ignored_bits), 10937 TEST(ept_access_test_paddr_not_present_ad_disabled), 10938 TEST(ept_access_test_paddr_not_present_ad_enabled), 10939 TEST(ept_access_test_paddr_read_only_ad_disabled), 10940 TEST(ept_access_test_paddr_read_only_ad_enabled), 10941 TEST(ept_access_test_paddr_read_write), 10942 TEST(ept_access_test_paddr_read_write_execute), 10943 TEST(ept_access_test_paddr_read_execute_ad_disabled), 10944 TEST(ept_access_test_paddr_read_execute_ad_enabled), 10945 TEST(ept_access_test_paddr_not_present_page_fault), 10946 TEST(ept_access_test_force_2m_page), 10947 /* Atomic MSR switch tests. */ 10948 TEST(atomic_switch_max_msrs_test), 10949 TEST(atomic_switch_overflow_msrs_test), 10950 TEST(rdtsc_vmexit_diff_test), 10951 TEST(vmx_mtf_test), 10952 TEST(vmx_mtf_pdpte_test), 10953 TEST(vmx_pf_exception_test), 10954 TEST(vmx_pf_no_vpid_test), 10955 TEST(vmx_pf_invvpid_test), 10956 TEST(vmx_pf_vpid_test), 10957 TEST(vmx_exception_test), 10958 { NULL, NULL, NULL, NULL, NULL, {0} }, 10959 }; 10960