1 /* 2 * All test cases of nested virtualization should be in this file 3 * 4 * Author : Arthur Chunqi Li <yzt356@gmail.com> 5 */ 6 7 #include <asm/debugreg.h> 8 9 #include "vmx.h" 10 #include "msr.h" 11 #include "processor.h" 12 #include "vm.h" 13 #include "pci.h" 14 #include "fwcfg.h" 15 #include "isr.h" 16 #include "desc.h" 17 #include "apic.h" 18 #include "types.h" 19 #include "vmalloc.h" 20 #include "alloc_page.h" 21 #include "smp.h" 22 #include "delay.h" 23 24 #define NONCANONICAL 0xaaaaaaaaaaaaaaaaull 25 26 #define VPID_CAP_INVVPID_TYPES_SHIFT 40 27 28 u64 ia32_pat; 29 u64 ia32_efer; 30 void *io_bitmap_a, *io_bitmap_b; 31 u16 ioport; 32 33 unsigned long *pml4; 34 u64 eptp; 35 void *data_page1, *data_page2; 36 37 phys_addr_t pci_physaddr; 38 39 void *pml_log; 40 #define PML_INDEX 512 41 42 static inline unsigned ffs(unsigned x) 43 { 44 int pos = -1; 45 46 __asm__ __volatile__("bsf %1, %%eax; cmovnz %%eax, %0" 47 : "+r"(pos) : "rm"(x) : "eax"); 48 return pos + 1; 49 } 50 51 static inline void vmcall(void) 52 { 53 asm volatile("vmcall"); 54 } 55 56 static void basic_guest_main(void) 57 { 58 report("Basic VMX test", 1); 59 } 60 61 static int basic_exit_handler(void) 62 { 63 report("Basic VMX test", 0); 64 print_vmexit_info(); 65 return VMX_TEST_EXIT; 66 } 67 68 static void vmenter_main(void) 69 { 70 u64 rax; 71 u64 rsp, resume_rsp; 72 73 report("test vmlaunch", 1); 74 75 asm volatile( 76 "mov %%rsp, %0\n\t" 77 "mov %3, %%rax\n\t" 78 "vmcall\n\t" 79 "mov %%rax, %1\n\t" 80 "mov %%rsp, %2\n\t" 81 : "=r"(rsp), "=r"(rax), "=r"(resume_rsp) 82 : "g"(0xABCD)); 83 report("test vmresume", (rax == 0xFFFF) && (rsp == resume_rsp)); 84 } 85 86 static int vmenter_exit_handler(void) 87 { 88 u64 guest_rip; 89 ulong reason; 90 91 guest_rip = vmcs_read(GUEST_RIP); 92 reason = vmcs_read(EXI_REASON) & 0xff; 93 switch (reason) { 94 case VMX_VMCALL: 95 if (regs.rax != 0xABCD) { 96 report("test vmresume", 0); 97 return VMX_TEST_VMEXIT; 98 } 99 regs.rax = 0xFFFF; 100 vmcs_write(GUEST_RIP, guest_rip + 3); 101 return VMX_TEST_RESUME; 102 default: 103 report("test vmresume", 0); 104 print_vmexit_info(); 105 } 106 return VMX_TEST_VMEXIT; 107 } 108 109 u32 preempt_scale; 110 volatile unsigned long long tsc_val; 111 volatile u32 preempt_val; 112 u64 saved_rip; 113 114 static int preemption_timer_init(struct vmcs *vmcs) 115 { 116 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 117 printf("\tPreemption timer is not supported\n"); 118 return VMX_TEST_EXIT; 119 } 120 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 121 preempt_val = 10000000; 122 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 123 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 124 125 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 126 printf("\tSave preemption value is not supported\n"); 127 128 return VMX_TEST_START; 129 } 130 131 static void preemption_timer_main(void) 132 { 133 tsc_val = rdtsc(); 134 if (ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) { 135 vmx_set_test_stage(0); 136 vmcall(); 137 if (vmx_get_test_stage() == 1) 138 vmcall(); 139 } 140 vmx_set_test_stage(1); 141 while (vmx_get_test_stage() == 1) { 142 if (((rdtsc() - tsc_val) >> preempt_scale) 143 > 10 * preempt_val) { 144 vmx_set_test_stage(2); 145 vmcall(); 146 } 147 } 148 tsc_val = rdtsc(); 149 asm volatile ("hlt"); 150 vmcall(); 151 vmx_set_test_stage(5); 152 vmcall(); 153 } 154 155 static int preemption_timer_exit_handler(void) 156 { 157 bool guest_halted; 158 u64 guest_rip; 159 ulong reason; 160 u32 insn_len; 161 u32 ctrl_exit; 162 163 guest_rip = vmcs_read(GUEST_RIP); 164 reason = vmcs_read(EXI_REASON) & 0xff; 165 insn_len = vmcs_read(EXI_INST_LEN); 166 switch (reason) { 167 case VMX_PREEMPT: 168 switch (vmx_get_test_stage()) { 169 case 1: 170 case 2: 171 report("busy-wait for preemption timer", 172 ((rdtsc() - tsc_val) >> preempt_scale) >= 173 preempt_val); 174 vmx_set_test_stage(3); 175 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 176 return VMX_TEST_RESUME; 177 case 3: 178 guest_halted = 179 (vmcs_read(GUEST_ACTV_STATE) == ACTV_HLT); 180 report("preemption timer during hlt", 181 ((rdtsc() - tsc_val) >> preempt_scale) >= 182 preempt_val && guest_halted); 183 vmx_set_test_stage(4); 184 vmcs_write(PIN_CONTROLS, 185 vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 186 vmcs_write(EXI_CONTROLS, 187 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_PREEMPT); 188 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 189 return VMX_TEST_RESUME; 190 case 4: 191 report("preemption timer with 0 value", 192 saved_rip == guest_rip); 193 break; 194 default: 195 report("Invalid stage.", false); 196 print_vmexit_info(); 197 break; 198 } 199 break; 200 case VMX_VMCALL: 201 vmcs_write(GUEST_RIP, guest_rip + insn_len); 202 switch (vmx_get_test_stage()) { 203 case 0: 204 report("Keep preemption value", 205 vmcs_read(PREEMPT_TIMER_VALUE) == preempt_val); 206 vmx_set_test_stage(1); 207 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 208 ctrl_exit = (vmcs_read(EXI_CONTROLS) | 209 EXI_SAVE_PREEMPT) & ctrl_exit_rev.clr; 210 vmcs_write(EXI_CONTROLS, ctrl_exit); 211 return VMX_TEST_RESUME; 212 case 1: 213 report("Save preemption value", 214 vmcs_read(PREEMPT_TIMER_VALUE) < preempt_val); 215 return VMX_TEST_RESUME; 216 case 2: 217 report("busy-wait for preemption timer", 0); 218 vmx_set_test_stage(3); 219 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 220 return VMX_TEST_RESUME; 221 case 3: 222 report("preemption timer during hlt", 0); 223 vmx_set_test_stage(4); 224 /* fall through */ 225 case 4: 226 vmcs_write(PIN_CONTROLS, 227 vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 228 vmcs_write(PREEMPT_TIMER_VALUE, 0); 229 saved_rip = guest_rip + insn_len; 230 return VMX_TEST_RESUME; 231 case 5: 232 report("preemption timer with 0 value (vmcall stage 5)", 0); 233 break; 234 default: 235 // Should not reach here 236 report("unexpected stage, %d", false, 237 vmx_get_test_stage()); 238 print_vmexit_info(); 239 return VMX_TEST_VMEXIT; 240 } 241 break; 242 default: 243 report("Unknown exit reason, %ld", false, reason); 244 print_vmexit_info(); 245 } 246 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 247 return VMX_TEST_VMEXIT; 248 } 249 250 static void msr_bmp_init(void) 251 { 252 void *msr_bitmap; 253 u32 ctrl_cpu0; 254 255 msr_bitmap = alloc_page(); 256 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 257 ctrl_cpu0 |= CPU_MSR_BITMAP; 258 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 259 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 260 } 261 262 static void *get_msr_bitmap(void) 263 { 264 void *msr_bitmap; 265 266 if (vmcs_read(CPU_EXEC_CTRL0) & CPU_MSR_BITMAP) { 267 msr_bitmap = (void *)vmcs_read(MSR_BITMAP); 268 } else { 269 msr_bitmap = alloc_page(); 270 memset(msr_bitmap, 0xff, PAGE_SIZE); 271 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 272 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_MSR_BITMAP); 273 } 274 275 return msr_bitmap; 276 } 277 278 static void disable_intercept_for_x2apic_msrs(void) 279 { 280 unsigned long *msr_bitmap = (unsigned long *)get_msr_bitmap(); 281 u32 msr; 282 283 for (msr = APIC_BASE_MSR; 284 msr < (APIC_BASE_MSR+0xff); 285 msr += BITS_PER_LONG) { 286 unsigned int word = msr / BITS_PER_LONG; 287 288 msr_bitmap[word] = 0; 289 msr_bitmap[word + (0x800 / sizeof(long))] = 0; 290 } 291 } 292 293 static int test_ctrl_pat_init(struct vmcs *vmcs) 294 { 295 u64 ctrl_ent; 296 u64 ctrl_exi; 297 298 msr_bmp_init(); 299 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT) && 300 !(ctrl_exit_rev.clr & EXI_LOAD_PAT) && 301 !(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 302 printf("\tSave/load PAT is not supported\n"); 303 return 1; 304 } 305 306 ctrl_ent = vmcs_read(ENT_CONTROLS); 307 ctrl_exi = vmcs_read(EXI_CONTROLS); 308 ctrl_ent |= ctrl_enter_rev.clr & ENT_LOAD_PAT; 309 ctrl_exi |= ctrl_exit_rev.clr & (EXI_SAVE_PAT | EXI_LOAD_PAT); 310 vmcs_write(ENT_CONTROLS, ctrl_ent); 311 vmcs_write(EXI_CONTROLS, ctrl_exi); 312 ia32_pat = rdmsr(MSR_IA32_CR_PAT); 313 vmcs_write(GUEST_PAT, 0x0); 314 vmcs_write(HOST_PAT, ia32_pat); 315 return VMX_TEST_START; 316 } 317 318 static void test_ctrl_pat_main(void) 319 { 320 u64 guest_ia32_pat; 321 322 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 323 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) 324 printf("\tENT_LOAD_PAT is not supported.\n"); 325 else { 326 if (guest_ia32_pat != 0) { 327 report("Entry load PAT", 0); 328 return; 329 } 330 } 331 wrmsr(MSR_IA32_CR_PAT, 0x6); 332 vmcall(); 333 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 334 if (ctrl_enter_rev.clr & ENT_LOAD_PAT) 335 report("Entry load PAT", guest_ia32_pat == ia32_pat); 336 } 337 338 static int test_ctrl_pat_exit_handler(void) 339 { 340 u64 guest_rip; 341 ulong reason; 342 u64 guest_pat; 343 344 guest_rip = vmcs_read(GUEST_RIP); 345 reason = vmcs_read(EXI_REASON) & 0xff; 346 switch (reason) { 347 case VMX_VMCALL: 348 guest_pat = vmcs_read(GUEST_PAT); 349 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT)) { 350 printf("\tEXI_SAVE_PAT is not supported\n"); 351 vmcs_write(GUEST_PAT, 0x6); 352 } else { 353 report("Exit save PAT", guest_pat == 0x6); 354 } 355 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) 356 printf("\tEXI_LOAD_PAT is not supported\n"); 357 else 358 report("Exit load PAT", rdmsr(MSR_IA32_CR_PAT) == ia32_pat); 359 vmcs_write(GUEST_PAT, ia32_pat); 360 vmcs_write(GUEST_RIP, guest_rip + 3); 361 return VMX_TEST_RESUME; 362 default: 363 printf("ERROR : Undefined exit reason, reason = %ld.\n", reason); 364 break; 365 } 366 return VMX_TEST_VMEXIT; 367 } 368 369 static int test_ctrl_efer_init(struct vmcs *vmcs) 370 { 371 u64 ctrl_ent; 372 u64 ctrl_exi; 373 374 msr_bmp_init(); 375 ctrl_ent = vmcs_read(ENT_CONTROLS) | ENT_LOAD_EFER; 376 ctrl_exi = vmcs_read(EXI_CONTROLS) | EXI_SAVE_EFER | EXI_LOAD_EFER; 377 vmcs_write(ENT_CONTROLS, ctrl_ent & ctrl_enter_rev.clr); 378 vmcs_write(EXI_CONTROLS, ctrl_exi & ctrl_exit_rev.clr); 379 ia32_efer = rdmsr(MSR_EFER); 380 vmcs_write(GUEST_EFER, ia32_efer ^ EFER_NX); 381 vmcs_write(HOST_EFER, ia32_efer ^ EFER_NX); 382 return VMX_TEST_START; 383 } 384 385 static void test_ctrl_efer_main(void) 386 { 387 u64 guest_ia32_efer; 388 389 guest_ia32_efer = rdmsr(MSR_EFER); 390 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) 391 printf("\tENT_LOAD_EFER is not supported.\n"); 392 else { 393 if (guest_ia32_efer != (ia32_efer ^ EFER_NX)) { 394 report("Entry load EFER", 0); 395 return; 396 } 397 } 398 wrmsr(MSR_EFER, ia32_efer); 399 vmcall(); 400 guest_ia32_efer = rdmsr(MSR_EFER); 401 if (ctrl_enter_rev.clr & ENT_LOAD_EFER) 402 report("Entry load EFER", guest_ia32_efer == ia32_efer); 403 } 404 405 static int test_ctrl_efer_exit_handler(void) 406 { 407 u64 guest_rip; 408 ulong reason; 409 u64 guest_efer; 410 411 guest_rip = vmcs_read(GUEST_RIP); 412 reason = vmcs_read(EXI_REASON) & 0xff; 413 switch (reason) { 414 case VMX_VMCALL: 415 guest_efer = vmcs_read(GUEST_EFER); 416 if (!(ctrl_exit_rev.clr & EXI_SAVE_EFER)) { 417 printf("\tEXI_SAVE_EFER is not supported\n"); 418 vmcs_write(GUEST_EFER, ia32_efer); 419 } else { 420 report("Exit save EFER", guest_efer == ia32_efer); 421 } 422 if (!(ctrl_exit_rev.clr & EXI_LOAD_EFER)) { 423 printf("\tEXI_LOAD_EFER is not supported\n"); 424 wrmsr(MSR_EFER, ia32_efer ^ EFER_NX); 425 } else { 426 report("Exit load EFER", rdmsr(MSR_EFER) == (ia32_efer ^ EFER_NX)); 427 } 428 vmcs_write(GUEST_PAT, ia32_efer); 429 vmcs_write(GUEST_RIP, guest_rip + 3); 430 return VMX_TEST_RESUME; 431 default: 432 printf("ERROR : Undefined exit reason, reason = %ld.\n", reason); 433 break; 434 } 435 return VMX_TEST_VMEXIT; 436 } 437 438 u32 guest_cr0, guest_cr4; 439 440 static void cr_shadowing_main(void) 441 { 442 u32 cr0, cr4, tmp; 443 444 // Test read through 445 vmx_set_test_stage(0); 446 guest_cr0 = read_cr0(); 447 if (vmx_get_test_stage() == 1) 448 report("Read through CR0", 0); 449 else 450 vmcall(); 451 vmx_set_test_stage(1); 452 guest_cr4 = read_cr4(); 453 if (vmx_get_test_stage() == 2) 454 report("Read through CR4", 0); 455 else 456 vmcall(); 457 // Test write through 458 guest_cr0 = guest_cr0 ^ (X86_CR0_TS | X86_CR0_MP); 459 guest_cr4 = guest_cr4 ^ (X86_CR4_TSD | X86_CR4_DE); 460 vmx_set_test_stage(2); 461 write_cr0(guest_cr0); 462 if (vmx_get_test_stage() == 3) 463 report("Write throuth CR0", 0); 464 else 465 vmcall(); 466 vmx_set_test_stage(3); 467 write_cr4(guest_cr4); 468 if (vmx_get_test_stage() == 4) 469 report("Write through CR4", 0); 470 else 471 vmcall(); 472 // Test read shadow 473 vmx_set_test_stage(4); 474 vmcall(); 475 cr0 = read_cr0(); 476 if (vmx_get_test_stage() != 5) 477 report("Read shadowing CR0", cr0 == guest_cr0); 478 vmx_set_test_stage(5); 479 cr4 = read_cr4(); 480 if (vmx_get_test_stage() != 6) 481 report("Read shadowing CR4", cr4 == guest_cr4); 482 // Test write shadow (same value with shadow) 483 vmx_set_test_stage(6); 484 write_cr0(guest_cr0); 485 if (vmx_get_test_stage() == 7) 486 report("Write shadowing CR0 (same value with shadow)", 0); 487 else 488 vmcall(); 489 vmx_set_test_stage(7); 490 write_cr4(guest_cr4); 491 if (vmx_get_test_stage() == 8) 492 report("Write shadowing CR4 (same value with shadow)", 0); 493 else 494 vmcall(); 495 // Test write shadow (different value) 496 vmx_set_test_stage(8); 497 tmp = guest_cr0 ^ X86_CR0_TS; 498 asm volatile("mov %0, %%rsi\n\t" 499 "mov %%rsi, %%cr0\n\t" 500 ::"m"(tmp) 501 :"rsi", "memory", "cc"); 502 report("Write shadowing different X86_CR0_TS", vmx_get_test_stage() == 9); 503 vmx_set_test_stage(9); 504 tmp = guest_cr0 ^ X86_CR0_MP; 505 asm volatile("mov %0, %%rsi\n\t" 506 "mov %%rsi, %%cr0\n\t" 507 ::"m"(tmp) 508 :"rsi", "memory", "cc"); 509 report("Write shadowing different X86_CR0_MP", vmx_get_test_stage() == 10); 510 vmx_set_test_stage(10); 511 tmp = guest_cr4 ^ X86_CR4_TSD; 512 asm volatile("mov %0, %%rsi\n\t" 513 "mov %%rsi, %%cr4\n\t" 514 ::"m"(tmp) 515 :"rsi", "memory", "cc"); 516 report("Write shadowing different X86_CR4_TSD", vmx_get_test_stage() == 11); 517 vmx_set_test_stage(11); 518 tmp = guest_cr4 ^ X86_CR4_DE; 519 asm volatile("mov %0, %%rsi\n\t" 520 "mov %%rsi, %%cr4\n\t" 521 ::"m"(tmp) 522 :"rsi", "memory", "cc"); 523 report("Write shadowing different X86_CR4_DE", vmx_get_test_stage() == 12); 524 } 525 526 static int cr_shadowing_exit_handler(void) 527 { 528 u64 guest_rip; 529 ulong reason; 530 u32 insn_len; 531 u32 exit_qual; 532 533 guest_rip = vmcs_read(GUEST_RIP); 534 reason = vmcs_read(EXI_REASON) & 0xff; 535 insn_len = vmcs_read(EXI_INST_LEN); 536 exit_qual = vmcs_read(EXI_QUALIFICATION); 537 switch (reason) { 538 case VMX_VMCALL: 539 switch (vmx_get_test_stage()) { 540 case 0: 541 report("Read through CR0", guest_cr0 == vmcs_read(GUEST_CR0)); 542 break; 543 case 1: 544 report("Read through CR4", guest_cr4 == vmcs_read(GUEST_CR4)); 545 break; 546 case 2: 547 report("Write through CR0", guest_cr0 == vmcs_read(GUEST_CR0)); 548 break; 549 case 3: 550 report("Write through CR4", guest_cr4 == vmcs_read(GUEST_CR4)); 551 break; 552 case 4: 553 guest_cr0 = vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP); 554 guest_cr4 = vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE); 555 vmcs_write(CR0_MASK, X86_CR0_TS | X86_CR0_MP); 556 vmcs_write(CR0_READ_SHADOW, guest_cr0 & (X86_CR0_TS | X86_CR0_MP)); 557 vmcs_write(CR4_MASK, X86_CR4_TSD | X86_CR4_DE); 558 vmcs_write(CR4_READ_SHADOW, guest_cr4 & (X86_CR4_TSD | X86_CR4_DE)); 559 break; 560 case 6: 561 report("Write shadowing CR0 (same value)", 562 guest_cr0 == (vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP))); 563 break; 564 case 7: 565 report("Write shadowing CR4 (same value)", 566 guest_cr4 == (vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE))); 567 break; 568 default: 569 // Should not reach here 570 report("unexpected stage, %d", false, 571 vmx_get_test_stage()); 572 print_vmexit_info(); 573 return VMX_TEST_VMEXIT; 574 } 575 vmcs_write(GUEST_RIP, guest_rip + insn_len); 576 return VMX_TEST_RESUME; 577 case VMX_CR: 578 switch (vmx_get_test_stage()) { 579 case 4: 580 report("Read shadowing CR0", 0); 581 vmx_inc_test_stage(); 582 break; 583 case 5: 584 report("Read shadowing CR4", 0); 585 vmx_inc_test_stage(); 586 break; 587 case 6: 588 report("Write shadowing CR0 (same value)", 0); 589 vmx_inc_test_stage(); 590 break; 591 case 7: 592 report("Write shadowing CR4 (same value)", 0); 593 vmx_inc_test_stage(); 594 break; 595 case 8: 596 case 9: 597 // 0x600 encodes "mov %esi, %cr0" 598 if (exit_qual == 0x600) 599 vmx_inc_test_stage(); 600 break; 601 case 10: 602 case 11: 603 // 0x604 encodes "mov %esi, %cr4" 604 if (exit_qual == 0x604) 605 vmx_inc_test_stage(); 606 break; 607 default: 608 // Should not reach here 609 report("unexpected stage, %d", false, 610 vmx_get_test_stage()); 611 print_vmexit_info(); 612 return VMX_TEST_VMEXIT; 613 } 614 vmcs_write(GUEST_RIP, guest_rip + insn_len); 615 return VMX_TEST_RESUME; 616 default: 617 report("Unknown exit reason, %ld", false, reason); 618 print_vmexit_info(); 619 } 620 return VMX_TEST_VMEXIT; 621 } 622 623 static int iobmp_init(struct vmcs *vmcs) 624 { 625 u32 ctrl_cpu0; 626 627 io_bitmap_a = alloc_page(); 628 io_bitmap_b = alloc_page(); 629 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 630 ctrl_cpu0 |= CPU_IO_BITMAP; 631 ctrl_cpu0 &= (~CPU_IO); 632 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 633 vmcs_write(IO_BITMAP_A, (u64)io_bitmap_a); 634 vmcs_write(IO_BITMAP_B, (u64)io_bitmap_b); 635 return VMX_TEST_START; 636 } 637 638 static void iobmp_main(void) 639 { 640 // stage 0, test IO pass 641 vmx_set_test_stage(0); 642 inb(0x5000); 643 outb(0x0, 0x5000); 644 report("I/O bitmap - I/O pass", vmx_get_test_stage() == 0); 645 // test IO width, in/out 646 ((u8 *)io_bitmap_a)[0] = 0xFF; 647 vmx_set_test_stage(2); 648 inb(0x0); 649 report("I/O bitmap - trap in", vmx_get_test_stage() == 3); 650 vmx_set_test_stage(3); 651 outw(0x0, 0x0); 652 report("I/O bitmap - trap out", vmx_get_test_stage() == 4); 653 vmx_set_test_stage(4); 654 inl(0x0); 655 report("I/O bitmap - I/O width, long", vmx_get_test_stage() == 5); 656 // test low/high IO port 657 vmx_set_test_stage(5); 658 ((u8 *)io_bitmap_a)[0x5000 / 8] = (1 << (0x5000 % 8)); 659 inb(0x5000); 660 report("I/O bitmap - I/O port, low part", vmx_get_test_stage() == 6); 661 vmx_set_test_stage(6); 662 ((u8 *)io_bitmap_b)[0x1000 / 8] = (1 << (0x1000 % 8)); 663 inb(0x9000); 664 report("I/O bitmap - I/O port, high part", vmx_get_test_stage() == 7); 665 // test partial pass 666 vmx_set_test_stage(7); 667 inl(0x4FFF); 668 report("I/O bitmap - partial pass", vmx_get_test_stage() == 8); 669 // test overrun 670 vmx_set_test_stage(8); 671 memset(io_bitmap_a, 0x0, PAGE_SIZE); 672 memset(io_bitmap_b, 0x0, PAGE_SIZE); 673 inl(0xFFFF); 674 report("I/O bitmap - overrun", vmx_get_test_stage() == 9); 675 vmx_set_test_stage(9); 676 vmcall(); 677 outb(0x0, 0x0); 678 report("I/O bitmap - ignore unconditional exiting", 679 vmx_get_test_stage() == 9); 680 vmx_set_test_stage(10); 681 vmcall(); 682 outb(0x0, 0x0); 683 report("I/O bitmap - unconditional exiting", 684 vmx_get_test_stage() == 11); 685 } 686 687 static int iobmp_exit_handler(void) 688 { 689 u64 guest_rip; 690 ulong reason, exit_qual; 691 u32 insn_len, ctrl_cpu0; 692 693 guest_rip = vmcs_read(GUEST_RIP); 694 reason = vmcs_read(EXI_REASON) & 0xff; 695 exit_qual = vmcs_read(EXI_QUALIFICATION); 696 insn_len = vmcs_read(EXI_INST_LEN); 697 switch (reason) { 698 case VMX_IO: 699 switch (vmx_get_test_stage()) { 700 case 0: 701 case 1: 702 vmx_inc_test_stage(); 703 break; 704 case 2: 705 report("I/O bitmap - I/O width, byte", 706 (exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_BYTE); 707 report("I/O bitmap - I/O direction, in", exit_qual & VMX_IO_IN); 708 vmx_inc_test_stage(); 709 break; 710 case 3: 711 report("I/O bitmap - I/O width, word", 712 (exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_WORD); 713 report("I/O bitmap - I/O direction, out", 714 !(exit_qual & VMX_IO_IN)); 715 vmx_inc_test_stage(); 716 break; 717 case 4: 718 report("I/O bitmap - I/O width, long", 719 (exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_LONG); 720 vmx_inc_test_stage(); 721 break; 722 case 5: 723 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x5000) 724 vmx_inc_test_stage(); 725 break; 726 case 6: 727 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x9000) 728 vmx_inc_test_stage(); 729 break; 730 case 7: 731 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x4FFF) 732 vmx_inc_test_stage(); 733 break; 734 case 8: 735 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0xFFFF) 736 vmx_inc_test_stage(); 737 break; 738 case 9: 739 case 10: 740 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 741 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0 & ~CPU_IO); 742 vmx_inc_test_stage(); 743 break; 744 default: 745 // Should not reach here 746 report("unexpected stage, %d", false, 747 vmx_get_test_stage()); 748 print_vmexit_info(); 749 return VMX_TEST_VMEXIT; 750 } 751 vmcs_write(GUEST_RIP, guest_rip + insn_len); 752 return VMX_TEST_RESUME; 753 case VMX_VMCALL: 754 switch (vmx_get_test_stage()) { 755 case 9: 756 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 757 ctrl_cpu0 |= CPU_IO | CPU_IO_BITMAP; 758 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 759 break; 760 case 10: 761 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 762 ctrl_cpu0 = (ctrl_cpu0 & ~CPU_IO_BITMAP) | CPU_IO; 763 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 764 break; 765 default: 766 // Should not reach here 767 report("unexpected stage, %d", false, 768 vmx_get_test_stage()); 769 print_vmexit_info(); 770 return VMX_TEST_VMEXIT; 771 } 772 vmcs_write(GUEST_RIP, guest_rip + insn_len); 773 return VMX_TEST_RESUME; 774 default: 775 printf("guest_rip = %#lx\n", guest_rip); 776 printf("\tERROR : Undefined exit reason, reason = %ld.\n", reason); 777 break; 778 } 779 return VMX_TEST_VMEXIT; 780 } 781 782 #define INSN_CPU0 0 783 #define INSN_CPU1 1 784 #define INSN_ALWAYS_TRAP 2 785 786 #define FIELD_EXIT_QUAL (1 << 0) 787 #define FIELD_INSN_INFO (1 << 1) 788 789 asm( 790 "insn_hlt: hlt;ret\n\t" 791 "insn_invlpg: invlpg 0x12345678;ret\n\t" 792 "insn_mwait: xor %eax, %eax; xor %ecx, %ecx; mwait;ret\n\t" 793 "insn_rdpmc: xor %ecx, %ecx; rdpmc;ret\n\t" 794 "insn_rdtsc: rdtsc;ret\n\t" 795 "insn_cr3_load: mov cr3,%rax; mov %rax,%cr3;ret\n\t" 796 "insn_cr3_store: mov %cr3,%rax;ret\n\t" 797 #ifdef __x86_64__ 798 "insn_cr8_load: xor %eax, %eax; mov %rax,%cr8;ret\n\t" 799 "insn_cr8_store: mov %cr8,%rax;ret\n\t" 800 #endif 801 "insn_monitor: xor %eax, %eax; xor %ecx, %ecx; xor %edx, %edx; monitor;ret\n\t" 802 "insn_pause: pause;ret\n\t" 803 "insn_wbinvd: wbinvd;ret\n\t" 804 "insn_cpuid: mov $10, %eax; cpuid;ret\n\t" 805 "insn_invd: invd;ret\n\t" 806 "insn_sgdt: sgdt gdt64_desc;ret\n\t" 807 "insn_lgdt: lgdt gdt64_desc;ret\n\t" 808 "insn_sidt: sidt idt_descr;ret\n\t" 809 "insn_lidt: lidt idt_descr;ret\n\t" 810 "insn_sldt: sldt %ax;ret\n\t" 811 "insn_lldt: xor %eax, %eax; lldt %ax;ret\n\t" 812 "insn_str: str %ax;ret\n\t" 813 "insn_rdrand: rdrand %rax;ret\n\t" 814 "insn_rdseed: rdseed %rax;ret\n\t" 815 ); 816 extern void insn_hlt(void); 817 extern void insn_invlpg(void); 818 extern void insn_mwait(void); 819 extern void insn_rdpmc(void); 820 extern void insn_rdtsc(void); 821 extern void insn_cr3_load(void); 822 extern void insn_cr3_store(void); 823 #ifdef __x86_64__ 824 extern void insn_cr8_load(void); 825 extern void insn_cr8_store(void); 826 #endif 827 extern void insn_monitor(void); 828 extern void insn_pause(void); 829 extern void insn_wbinvd(void); 830 extern void insn_sgdt(void); 831 extern void insn_lgdt(void); 832 extern void insn_sidt(void); 833 extern void insn_lidt(void); 834 extern void insn_sldt(void); 835 extern void insn_lldt(void); 836 extern void insn_str(void); 837 extern void insn_cpuid(void); 838 extern void insn_invd(void); 839 extern void insn_rdrand(void); 840 extern void insn_rdseed(void); 841 842 u32 cur_insn; 843 u64 cr3; 844 845 #define X86_FEATURE_MONITOR (1 << 3) 846 847 typedef bool (*supported_fn)(void); 848 849 static bool monitor_supported(void) 850 { 851 return this_cpu_has(X86_FEATURE_MWAIT); 852 } 853 854 struct insn_table { 855 const char *name; 856 u32 flag; 857 void (*insn_func)(void); 858 u32 type; 859 u32 reason; 860 ulong exit_qual; 861 u32 insn_info; 862 // Use FIELD_EXIT_QUAL and FIELD_INSN_INFO to define 863 // which field need to be tested, reason is always tested 864 u32 test_field; 865 const supported_fn supported_fn; 866 u8 disabled; 867 }; 868 869 /* 870 * Add more test cases of instruction intercept here. Elements in this 871 * table is: 872 * name/control flag/insn function/type/exit reason/exit qulification/ 873 * instruction info/field to test 874 * The last field defines which fields (exit_qual and insn_info) need to be 875 * tested in exit handler. If set to 0, only "reason" is checked. 876 */ 877 static struct insn_table insn_table[] = { 878 // Flags for Primary Processor-Based VM-Execution Controls 879 {"HLT", CPU_HLT, insn_hlt, INSN_CPU0, 12, 0, 0, 0}, 880 {"INVLPG", CPU_INVLPG, insn_invlpg, INSN_CPU0, 14, 881 0x12345678, 0, FIELD_EXIT_QUAL}, 882 {"MWAIT", CPU_MWAIT, insn_mwait, INSN_CPU0, 36, 0, 0, 0, &monitor_supported}, 883 {"RDPMC", CPU_RDPMC, insn_rdpmc, INSN_CPU0, 15, 0, 0, 0}, 884 {"RDTSC", CPU_RDTSC, insn_rdtsc, INSN_CPU0, 16, 0, 0, 0}, 885 {"CR3 load", CPU_CR3_LOAD, insn_cr3_load, INSN_CPU0, 28, 0x3, 0, 886 FIELD_EXIT_QUAL}, 887 {"CR3 store", CPU_CR3_STORE, insn_cr3_store, INSN_CPU0, 28, 0x13, 0, 888 FIELD_EXIT_QUAL}, 889 #ifdef __x86_64__ 890 {"CR8 load", CPU_CR8_LOAD, insn_cr8_load, INSN_CPU0, 28, 0x8, 0, 891 FIELD_EXIT_QUAL}, 892 {"CR8 store", CPU_CR8_STORE, insn_cr8_store, INSN_CPU0, 28, 0x18, 0, 893 FIELD_EXIT_QUAL}, 894 #endif 895 {"MONITOR", CPU_MONITOR, insn_monitor, INSN_CPU0, 39, 0, 0, 0, &monitor_supported}, 896 {"PAUSE", CPU_PAUSE, insn_pause, INSN_CPU0, 40, 0, 0, 0}, 897 // Flags for Secondary Processor-Based VM-Execution Controls 898 {"WBINVD", CPU_WBINVD, insn_wbinvd, INSN_CPU1, 54, 0, 0, 0}, 899 {"DESC_TABLE (SGDT)", CPU_DESC_TABLE, insn_sgdt, INSN_CPU1, 46, 0, 0, 0}, 900 {"DESC_TABLE (LGDT)", CPU_DESC_TABLE, insn_lgdt, INSN_CPU1, 46, 0, 0, 0}, 901 {"DESC_TABLE (SIDT)", CPU_DESC_TABLE, insn_sidt, INSN_CPU1, 46, 0, 0, 0}, 902 {"DESC_TABLE (LIDT)", CPU_DESC_TABLE, insn_lidt, INSN_CPU1, 46, 0, 0, 0}, 903 {"DESC_TABLE (SLDT)", CPU_DESC_TABLE, insn_sldt, INSN_CPU1, 47, 0, 0, 0}, 904 {"DESC_TABLE (LLDT)", CPU_DESC_TABLE, insn_lldt, INSN_CPU1, 47, 0, 0, 0}, 905 {"DESC_TABLE (STR)", CPU_DESC_TABLE, insn_str, INSN_CPU1, 47, 0, 0, 0}, 906 /* LTR causes a #GP if done with a busy selector, so it is not tested. */ 907 {"RDRAND", CPU_RDRAND, insn_rdrand, INSN_CPU1, VMX_RDRAND, 0, 0, 0}, 908 {"RDSEED", CPU_RDSEED, insn_rdseed, INSN_CPU1, VMX_RDSEED, 0, 0, 0}, 909 // Instructions always trap 910 {"CPUID", 0, insn_cpuid, INSN_ALWAYS_TRAP, 10, 0, 0, 0}, 911 {"INVD", 0, insn_invd, INSN_ALWAYS_TRAP, 13, 0, 0, 0}, 912 // Instructions never trap 913 {NULL}, 914 }; 915 916 static int insn_intercept_init(struct vmcs *vmcs) 917 { 918 u32 ctrl_cpu, cur_insn; 919 920 ctrl_cpu = ctrl_cpu_rev[0].set | CPU_SECONDARY; 921 ctrl_cpu &= ctrl_cpu_rev[0].clr; 922 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu); 923 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu_rev[1].set); 924 cr3 = read_cr3(); 925 926 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 927 if (insn_table[cur_insn].supported_fn == NULL) 928 continue; 929 insn_table[cur_insn].disabled = !insn_table[cur_insn].supported_fn(); 930 } 931 return VMX_TEST_START; 932 } 933 934 static void insn_intercept_main(void) 935 { 936 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 937 vmx_set_test_stage(cur_insn * 2); 938 if ((insn_table[cur_insn].type == INSN_CPU0 && 939 !(ctrl_cpu_rev[0].clr & insn_table[cur_insn].flag)) || 940 (insn_table[cur_insn].type == INSN_CPU1 && 941 !(ctrl_cpu_rev[1].clr & insn_table[cur_insn].flag))) { 942 printf("\tCPU_CTRL%d.CPU_%s is not supported.\n", 943 insn_table[cur_insn].type - INSN_CPU0, 944 insn_table[cur_insn].name); 945 continue; 946 } 947 948 if (insn_table[cur_insn].disabled) { 949 printf("\tFeature required for %s is not supported.\n", 950 insn_table[cur_insn].name); 951 continue; 952 } 953 954 if ((insn_table[cur_insn].type == INSN_CPU0 && 955 !(ctrl_cpu_rev[0].set & insn_table[cur_insn].flag)) || 956 (insn_table[cur_insn].type == INSN_CPU1 && 957 !(ctrl_cpu_rev[1].set & insn_table[cur_insn].flag))) { 958 /* skip hlt, it stalls the guest and is tested below */ 959 if (insn_table[cur_insn].insn_func != insn_hlt) 960 insn_table[cur_insn].insn_func(); 961 report("execute %s", vmx_get_test_stage() == cur_insn * 2, 962 insn_table[cur_insn].name); 963 } else if (insn_table[cur_insn].type != INSN_ALWAYS_TRAP) 964 printf("\tCPU_CTRL%d.CPU_%s always traps.\n", 965 insn_table[cur_insn].type - INSN_CPU0, 966 insn_table[cur_insn].name); 967 968 vmcall(); 969 970 insn_table[cur_insn].insn_func(); 971 report("intercept %s", vmx_get_test_stage() == cur_insn * 2 + 1, 972 insn_table[cur_insn].name); 973 974 vmx_set_test_stage(cur_insn * 2 + 1); 975 vmcall(); 976 } 977 } 978 979 static int insn_intercept_exit_handler(void) 980 { 981 u64 guest_rip; 982 u32 reason; 983 ulong exit_qual; 984 u32 insn_len; 985 u32 insn_info; 986 bool pass; 987 988 guest_rip = vmcs_read(GUEST_RIP); 989 reason = vmcs_read(EXI_REASON) & 0xff; 990 exit_qual = vmcs_read(EXI_QUALIFICATION); 991 insn_len = vmcs_read(EXI_INST_LEN); 992 insn_info = vmcs_read(EXI_INST_INFO); 993 994 if (reason == VMX_VMCALL) { 995 u32 val = 0; 996 997 if (insn_table[cur_insn].type == INSN_CPU0) 998 val = vmcs_read(CPU_EXEC_CTRL0); 999 else if (insn_table[cur_insn].type == INSN_CPU1) 1000 val = vmcs_read(CPU_EXEC_CTRL1); 1001 1002 if (vmx_get_test_stage() & 1) 1003 val &= ~insn_table[cur_insn].flag; 1004 else 1005 val |= insn_table[cur_insn].flag; 1006 1007 if (insn_table[cur_insn].type == INSN_CPU0) 1008 vmcs_write(CPU_EXEC_CTRL0, val | ctrl_cpu_rev[0].set); 1009 else if (insn_table[cur_insn].type == INSN_CPU1) 1010 vmcs_write(CPU_EXEC_CTRL1, val | ctrl_cpu_rev[1].set); 1011 } else { 1012 pass = (cur_insn * 2 == vmx_get_test_stage()) && 1013 insn_table[cur_insn].reason == reason; 1014 if (insn_table[cur_insn].test_field & FIELD_EXIT_QUAL && 1015 insn_table[cur_insn].exit_qual != exit_qual) 1016 pass = false; 1017 if (insn_table[cur_insn].test_field & FIELD_INSN_INFO && 1018 insn_table[cur_insn].insn_info != insn_info) 1019 pass = false; 1020 if (pass) 1021 vmx_inc_test_stage(); 1022 } 1023 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1024 return VMX_TEST_RESUME; 1025 } 1026 1027 /** 1028 * __setup_ept - Setup the VMCS fields to enable Extended Page Tables (EPT) 1029 * @hpa: Host physical address of the top-level, a.k.a. root, EPT table 1030 * @enable_ad: Whether or not to enable Access/Dirty bits for EPT entries 1031 * 1032 * Returns 0 on success, 1 on failure. 1033 * 1034 * Note that @hpa doesn't need to point at actual memory if VM-Launch is 1035 * expected to fail, e.g. setup_dummy_ept() arbitrarily passes '0' to satisfy 1036 * the various EPTP consistency checks, but doesn't ensure backing for HPA '0'. 1037 */ 1038 static int __setup_ept(u64 hpa, bool enable_ad) 1039 { 1040 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1041 !(ctrl_cpu_rev[1].clr & CPU_EPT)) { 1042 printf("\tEPT is not supported"); 1043 return 1; 1044 } 1045 if (!(ept_vpid.val & EPT_CAP_WB)) { 1046 printf("WB memtype for EPT walks not supported\n"); 1047 return 1; 1048 } 1049 if (!(ept_vpid.val & EPT_CAP_PWL4)) { 1050 printf("\tPWL4 is not supported\n"); 1051 return 1; 1052 } 1053 1054 eptp = EPT_MEM_TYPE_WB; 1055 eptp |= (3 << EPTP_PG_WALK_LEN_SHIFT); 1056 eptp |= hpa; 1057 if (enable_ad) 1058 eptp |= EPTP_AD_FLAG; 1059 1060 vmcs_write(EPTP, eptp); 1061 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0)| CPU_SECONDARY); 1062 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1)| CPU_EPT); 1063 1064 return 0; 1065 } 1066 1067 /** 1068 * setup_ept - Enable Extended Page Tables (EPT) and setup an identity map 1069 * @enable_ad: Whether or not to enable Access/Dirty bits for EPT entries 1070 * 1071 * Returns 0 on success, 1 on failure. 1072 * 1073 * This is the "real" function for setting up EPT tables, i.e. use this for 1074 * tests that need to run code in the guest with EPT enabled. 1075 */ 1076 static int setup_ept(bool enable_ad) 1077 { 1078 unsigned long end_of_memory; 1079 1080 pml4 = alloc_page(); 1081 1082 if (__setup_ept(virt_to_phys(pml4), enable_ad)) 1083 return 1; 1084 1085 end_of_memory = fwcfg_get_u64(FW_CFG_RAM_SIZE); 1086 if (end_of_memory < (1ul << 32)) 1087 end_of_memory = (1ul << 32); 1088 /* Cannot use large EPT pages if we need to track EPT 1089 * accessed/dirty bits at 4K granularity. 1090 */ 1091 setup_ept_range(pml4, 0, end_of_memory, 0, 1092 !enable_ad && ept_2m_supported(), 1093 EPT_WA | EPT_RA | EPT_EA); 1094 return 0; 1095 } 1096 1097 /** 1098 * setup_dummy_ept - Enable Extended Page Tables (EPT) with a dummy root HPA 1099 * 1100 * Setup EPT using a semi-arbitrary dummy root HPA. This function is intended 1101 * for use by tests that need EPT enabled to verify dependent VMCS controls 1102 * but never expect to fully enter the guest, i.e. don't need setup the actual 1103 * EPT tables. 1104 */ 1105 static void setup_dummy_ept(void) 1106 { 1107 if (__setup_ept(0, false)) 1108 report_abort("EPT setup unexpectedly failed"); 1109 } 1110 1111 static int enable_unrestricted_guest(void) 1112 { 1113 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1114 !(ctrl_cpu_rev[1].clr & CPU_URG) || 1115 !(ctrl_cpu_rev[1].clr & CPU_EPT)) 1116 return 1; 1117 1118 setup_dummy_ept(); 1119 1120 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 1121 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | CPU_URG); 1122 1123 return 0; 1124 } 1125 1126 static void ept_enable_ad_bits(void) 1127 { 1128 eptp |= EPTP_AD_FLAG; 1129 vmcs_write(EPTP, eptp); 1130 } 1131 1132 static void ept_disable_ad_bits(void) 1133 { 1134 eptp &= ~EPTP_AD_FLAG; 1135 vmcs_write(EPTP, eptp); 1136 } 1137 1138 static void ept_enable_ad_bits_or_skip_test(void) 1139 { 1140 if (!ept_ad_bits_supported()) 1141 test_skip("EPT AD bits not supported."); 1142 ept_enable_ad_bits(); 1143 } 1144 1145 static int apic_version; 1146 1147 static int ept_init_common(bool have_ad) 1148 { 1149 int ret; 1150 struct pci_dev pcidev; 1151 1152 if (setup_ept(have_ad)) 1153 return VMX_TEST_EXIT; 1154 data_page1 = alloc_page(); 1155 data_page2 = alloc_page(); 1156 *((u32 *)data_page1) = MAGIC_VAL_1; 1157 *((u32 *)data_page2) = MAGIC_VAL_2; 1158 install_ept(pml4, (unsigned long)data_page1, (unsigned long)data_page2, 1159 EPT_RA | EPT_WA | EPT_EA); 1160 1161 apic_version = apic_read(APIC_LVR); 1162 1163 ret = pci_find_dev(PCI_VENDOR_ID_REDHAT, PCI_DEVICE_ID_REDHAT_TEST); 1164 if (ret != PCIDEVADDR_INVALID) { 1165 pci_dev_init(&pcidev, ret); 1166 pci_physaddr = pcidev.resource[PCI_TESTDEV_BAR_MEM]; 1167 } 1168 1169 return VMX_TEST_START; 1170 } 1171 1172 static int ept_init(struct vmcs *vmcs) 1173 { 1174 return ept_init_common(false); 1175 } 1176 1177 static void ept_common(void) 1178 { 1179 vmx_set_test_stage(0); 1180 if (*((u32 *)data_page2) != MAGIC_VAL_1 || 1181 *((u32 *)data_page1) != MAGIC_VAL_1) 1182 report("EPT basic framework - read", 0); 1183 else { 1184 *((u32 *)data_page2) = MAGIC_VAL_3; 1185 vmcall(); 1186 if (vmx_get_test_stage() == 1) { 1187 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1188 *((u32 *)data_page2) == MAGIC_VAL_2) 1189 report("EPT basic framework", 1); 1190 else 1191 report("EPT basic framework - remap", 1); 1192 } 1193 } 1194 // Test EPT Misconfigurations 1195 vmx_set_test_stage(1); 1196 vmcall(); 1197 *((u32 *)data_page1) = MAGIC_VAL_1; 1198 if (vmx_get_test_stage() != 2) { 1199 report("EPT misconfigurations", 0); 1200 goto t1; 1201 } 1202 vmx_set_test_stage(2); 1203 vmcall(); 1204 *((u32 *)data_page1) = MAGIC_VAL_1; 1205 report("EPT misconfigurations", vmx_get_test_stage() == 3); 1206 t1: 1207 // Test EPT violation 1208 vmx_set_test_stage(3); 1209 vmcall(); 1210 *((u32 *)data_page1) = MAGIC_VAL_1; 1211 report("EPT violation - page permission", vmx_get_test_stage() == 4); 1212 // Violation caused by EPT paging structure 1213 vmx_set_test_stage(4); 1214 vmcall(); 1215 *((u32 *)data_page1) = MAGIC_VAL_2; 1216 report("EPT violation - paging structure", vmx_get_test_stage() == 5); 1217 1218 // MMIO Read/Write 1219 vmx_set_test_stage(5); 1220 vmcall(); 1221 1222 *(u32 volatile *)pci_physaddr; 1223 report("MMIO EPT violation - read", vmx_get_test_stage() == 6); 1224 1225 *(u32 volatile *)pci_physaddr = MAGIC_VAL_1; 1226 report("MMIO EPT violation - write", vmx_get_test_stage() == 7); 1227 } 1228 1229 static void ept_main(void) 1230 { 1231 ept_common(); 1232 1233 // Test EPT access to L1 MMIO 1234 vmx_set_test_stage(7); 1235 report("EPT - MMIO access", *((u32 *)0xfee00030UL) == apic_version); 1236 1237 // Test invalid operand for INVEPT 1238 vmcall(); 1239 report("EPT - unsupported INVEPT", vmx_get_test_stage() == 8); 1240 } 1241 1242 static bool invept_test(int type, u64 eptp) 1243 { 1244 bool ret, supported; 1245 1246 supported = ept_vpid.val & (EPT_CAP_INVEPT_SINGLE >> INVEPT_SINGLE << type); 1247 ret = invept(type, eptp); 1248 1249 if (ret == !supported) 1250 return false; 1251 1252 if (!supported) 1253 printf("WARNING: unsupported invept passed!\n"); 1254 else 1255 printf("WARNING: invept failed!\n"); 1256 1257 return true; 1258 } 1259 1260 static int pml_exit_handler(void) 1261 { 1262 u16 index, count; 1263 ulong reason = vmcs_read(EXI_REASON) & 0xff; 1264 u64 *pmlbuf = pml_log; 1265 u64 guest_rip = vmcs_read(GUEST_RIP);; 1266 u64 guest_cr3 = vmcs_read(GUEST_CR3); 1267 u32 insn_len = vmcs_read(EXI_INST_LEN); 1268 1269 switch (reason) { 1270 case VMX_VMCALL: 1271 switch (vmx_get_test_stage()) { 1272 case 0: 1273 index = vmcs_read(GUEST_PML_INDEX); 1274 for (count = index + 1; count < PML_INDEX; count++) { 1275 if (pmlbuf[count] == (u64)data_page2) { 1276 vmx_inc_test_stage(); 1277 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1278 break; 1279 } 1280 } 1281 break; 1282 case 1: 1283 index = vmcs_read(GUEST_PML_INDEX); 1284 /* Keep clearing the dirty bit till a overflow */ 1285 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1286 break; 1287 default: 1288 report("unexpected stage, %d.", false, 1289 vmx_get_test_stage()); 1290 print_vmexit_info(); 1291 return VMX_TEST_VMEXIT; 1292 } 1293 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1294 return VMX_TEST_RESUME; 1295 case VMX_PML_FULL: 1296 vmx_inc_test_stage(); 1297 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1298 return VMX_TEST_RESUME; 1299 default: 1300 report("Unknown exit reason, %ld", false, reason); 1301 print_vmexit_info(); 1302 } 1303 return VMX_TEST_VMEXIT; 1304 } 1305 1306 static int ept_exit_handler_common(bool have_ad) 1307 { 1308 u64 guest_rip; 1309 u64 guest_cr3; 1310 ulong reason; 1311 u32 insn_len; 1312 u32 exit_qual; 1313 static unsigned long data_page1_pte, data_page1_pte_pte, memaddr_pte; 1314 1315 guest_rip = vmcs_read(GUEST_RIP); 1316 guest_cr3 = vmcs_read(GUEST_CR3); 1317 reason = vmcs_read(EXI_REASON) & 0xff; 1318 insn_len = vmcs_read(EXI_INST_LEN); 1319 exit_qual = vmcs_read(EXI_QUALIFICATION); 1320 switch (reason) { 1321 case VMX_VMCALL: 1322 switch (vmx_get_test_stage()) { 1323 case 0: 1324 check_ept_ad(pml4, guest_cr3, 1325 (unsigned long)data_page1, 1326 have_ad ? EPT_ACCESS_FLAG : 0, 1327 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1328 check_ept_ad(pml4, guest_cr3, 1329 (unsigned long)data_page2, 1330 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0, 1331 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1332 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1333 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1334 if (have_ad) 1335 ept_sync(INVEPT_SINGLE, eptp);; 1336 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1337 *((u32 *)data_page2) == MAGIC_VAL_2) { 1338 vmx_inc_test_stage(); 1339 install_ept(pml4, (unsigned long)data_page2, 1340 (unsigned long)data_page2, 1341 EPT_RA | EPT_WA | EPT_EA); 1342 } else 1343 report("EPT basic framework - write", 0); 1344 break; 1345 case 1: 1346 install_ept(pml4, (unsigned long)data_page1, 1347 (unsigned long)data_page1, EPT_WA); 1348 ept_sync(INVEPT_SINGLE, eptp); 1349 break; 1350 case 2: 1351 install_ept(pml4, (unsigned long)data_page1, 1352 (unsigned long)data_page1, 1353 EPT_RA | EPT_WA | EPT_EA | 1354 (2 << EPT_MEM_TYPE_SHIFT)); 1355 ept_sync(INVEPT_SINGLE, eptp); 1356 break; 1357 case 3: 1358 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1359 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)data_page1, 1360 1, &data_page1_pte)); 1361 set_ept_pte(pml4, (unsigned long)data_page1, 1362 1, data_page1_pte & ~EPT_PRESENT); 1363 ept_sync(INVEPT_SINGLE, eptp); 1364 break; 1365 case 4: 1366 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)data_page1, 1367 2, &data_page1_pte)); 1368 data_page1_pte &= PAGE_MASK; 1369 TEST_ASSERT(get_ept_pte(pml4, data_page1_pte, 1370 2, &data_page1_pte_pte)); 1371 set_ept_pte(pml4, data_page1_pte, 2, 1372 data_page1_pte_pte & ~EPT_PRESENT); 1373 ept_sync(INVEPT_SINGLE, eptp); 1374 break; 1375 case 5: 1376 install_ept(pml4, (unsigned long)pci_physaddr, 1377 (unsigned long)pci_physaddr, 0); 1378 ept_sync(INVEPT_SINGLE, eptp); 1379 break; 1380 case 7: 1381 if (!invept_test(0, eptp)) 1382 vmx_inc_test_stage(); 1383 break; 1384 // Should not reach here 1385 default: 1386 report("ERROR - unexpected stage, %d.", false, 1387 vmx_get_test_stage()); 1388 print_vmexit_info(); 1389 return VMX_TEST_VMEXIT; 1390 } 1391 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1392 return VMX_TEST_RESUME; 1393 case VMX_EPT_MISCONFIG: 1394 switch (vmx_get_test_stage()) { 1395 case 1: 1396 case 2: 1397 vmx_inc_test_stage(); 1398 install_ept(pml4, (unsigned long)data_page1, 1399 (unsigned long)data_page1, 1400 EPT_RA | EPT_WA | EPT_EA); 1401 ept_sync(INVEPT_SINGLE, eptp); 1402 break; 1403 // Should not reach here 1404 default: 1405 report("ERROR - unexpected stage, %d.", false, 1406 vmx_get_test_stage()); 1407 print_vmexit_info(); 1408 return VMX_TEST_VMEXIT; 1409 } 1410 return VMX_TEST_RESUME; 1411 case VMX_EPT_VIOLATION: 1412 switch(vmx_get_test_stage()) { 1413 case 3: 1414 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1415 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1416 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1417 if (exit_qual == (EPT_VLT_WR | EPT_VLT_LADDR_VLD | 1418 EPT_VLT_PADDR)) 1419 vmx_inc_test_stage(); 1420 set_ept_pte(pml4, (unsigned long)data_page1, 1421 1, data_page1_pte | (EPT_PRESENT)); 1422 ept_sync(INVEPT_SINGLE, eptp); 1423 break; 1424 case 4: 1425 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1426 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1427 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1428 if (exit_qual == (EPT_VLT_RD | 1429 (have_ad ? EPT_VLT_WR : 0) | 1430 EPT_VLT_LADDR_VLD)) 1431 vmx_inc_test_stage(); 1432 set_ept_pte(pml4, data_page1_pte, 2, 1433 data_page1_pte_pte | (EPT_PRESENT)); 1434 ept_sync(INVEPT_SINGLE, eptp); 1435 break; 1436 case 5: 1437 if (exit_qual & EPT_VLT_RD) 1438 vmx_inc_test_stage(); 1439 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1440 1, &memaddr_pte)); 1441 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA); 1442 ept_sync(INVEPT_SINGLE, eptp); 1443 break; 1444 case 6: 1445 if (exit_qual & EPT_VLT_WR) 1446 vmx_inc_test_stage(); 1447 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1448 1, &memaddr_pte)); 1449 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA | EPT_WA); 1450 ept_sync(INVEPT_SINGLE, eptp); 1451 break; 1452 default: 1453 // Should not reach here 1454 report("ERROR : unexpected stage, %d", false, 1455 vmx_get_test_stage()); 1456 print_vmexit_info(); 1457 return VMX_TEST_VMEXIT; 1458 } 1459 return VMX_TEST_RESUME; 1460 default: 1461 report("Unknown exit reason, %ld", false, reason); 1462 print_vmexit_info(); 1463 } 1464 return VMX_TEST_VMEXIT; 1465 } 1466 1467 static int ept_exit_handler(void) 1468 { 1469 return ept_exit_handler_common(false); 1470 } 1471 1472 static int eptad_init(struct vmcs *vmcs) 1473 { 1474 int r = ept_init_common(true); 1475 1476 if (r == VMX_TEST_EXIT) 1477 return r; 1478 1479 if ((rdmsr(MSR_IA32_VMX_EPT_VPID_CAP) & EPT_CAP_AD_FLAG) == 0) { 1480 printf("\tEPT A/D bits are not supported"); 1481 return VMX_TEST_EXIT; 1482 } 1483 1484 return r; 1485 } 1486 1487 static int pml_init(struct vmcs *vmcs) 1488 { 1489 u32 ctrl_cpu; 1490 int r = eptad_init(vmcs); 1491 1492 if (r == VMX_TEST_EXIT) 1493 return r; 1494 1495 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1496 !(ctrl_cpu_rev[1].clr & CPU_PML)) { 1497 printf("\tPML is not supported"); 1498 return VMX_TEST_EXIT; 1499 } 1500 1501 pml_log = alloc_page(); 1502 vmcs_write(PMLADDR, (u64)pml_log); 1503 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1504 1505 ctrl_cpu = vmcs_read(CPU_EXEC_CTRL1) | CPU_PML; 1506 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu); 1507 1508 return VMX_TEST_START; 1509 } 1510 1511 static void pml_main(void) 1512 { 1513 int count = 0; 1514 1515 vmx_set_test_stage(0); 1516 *((u32 *)data_page2) = 0x1; 1517 vmcall(); 1518 report("PML - Dirty GPA Logging", vmx_get_test_stage() == 1); 1519 1520 while (vmx_get_test_stage() == 1) { 1521 vmcall(); 1522 *((u32 *)data_page2) = 0x1; 1523 if (count++ > PML_INDEX) 1524 break; 1525 } 1526 report("PML Full Event", vmx_get_test_stage() == 2); 1527 } 1528 1529 static void eptad_main(void) 1530 { 1531 ept_common(); 1532 } 1533 1534 static int eptad_exit_handler(void) 1535 { 1536 return ept_exit_handler_common(true); 1537 } 1538 1539 static bool invvpid_test(int type, u16 vpid) 1540 { 1541 bool ret, supported; 1542 1543 supported = ept_vpid.val & 1544 (VPID_CAP_INVVPID_ADDR >> INVVPID_ADDR << type); 1545 ret = invvpid(type, vpid, 0); 1546 1547 if (ret == !supported) 1548 return false; 1549 1550 if (!supported) 1551 printf("WARNING: unsupported invvpid passed!\n"); 1552 else 1553 printf("WARNING: invvpid failed!\n"); 1554 1555 return true; 1556 } 1557 1558 static int vpid_init(struct vmcs *vmcs) 1559 { 1560 u32 ctrl_cpu1; 1561 1562 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1563 !(ctrl_cpu_rev[1].clr & CPU_VPID)) { 1564 printf("\tVPID is not supported"); 1565 return VMX_TEST_EXIT; 1566 } 1567 1568 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 1569 ctrl_cpu1 |= CPU_VPID; 1570 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 1571 return VMX_TEST_START; 1572 } 1573 1574 static void vpid_main(void) 1575 { 1576 vmx_set_test_stage(0); 1577 vmcall(); 1578 report("INVVPID SINGLE ADDRESS", vmx_get_test_stage() == 1); 1579 vmx_set_test_stage(2); 1580 vmcall(); 1581 report("INVVPID SINGLE", vmx_get_test_stage() == 3); 1582 vmx_set_test_stage(4); 1583 vmcall(); 1584 report("INVVPID ALL", vmx_get_test_stage() == 5); 1585 } 1586 1587 static int vpid_exit_handler(void) 1588 { 1589 u64 guest_rip; 1590 ulong reason; 1591 u32 insn_len; 1592 1593 guest_rip = vmcs_read(GUEST_RIP); 1594 reason = vmcs_read(EXI_REASON) & 0xff; 1595 insn_len = vmcs_read(EXI_INST_LEN); 1596 1597 switch (reason) { 1598 case VMX_VMCALL: 1599 switch(vmx_get_test_stage()) { 1600 case 0: 1601 if (!invvpid_test(INVVPID_ADDR, 1)) 1602 vmx_inc_test_stage(); 1603 break; 1604 case 2: 1605 if (!invvpid_test(INVVPID_CONTEXT_GLOBAL, 1)) 1606 vmx_inc_test_stage(); 1607 break; 1608 case 4: 1609 if (!invvpid_test(INVVPID_ALL, 1)) 1610 vmx_inc_test_stage(); 1611 break; 1612 default: 1613 report("ERROR: unexpected stage, %d", false, 1614 vmx_get_test_stage()); 1615 print_vmexit_info(); 1616 return VMX_TEST_VMEXIT; 1617 } 1618 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1619 return VMX_TEST_RESUME; 1620 default: 1621 report("Unknown exit reason, %ld", false, reason); 1622 print_vmexit_info(); 1623 } 1624 return VMX_TEST_VMEXIT; 1625 } 1626 1627 #define TIMER_VECTOR 222 1628 1629 static volatile bool timer_fired; 1630 1631 static void timer_isr(isr_regs_t *regs) 1632 { 1633 timer_fired = true; 1634 apic_write(APIC_EOI, 0); 1635 } 1636 1637 static int interrupt_init(struct vmcs *vmcs) 1638 { 1639 msr_bmp_init(); 1640 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1641 handle_irq(TIMER_VECTOR, timer_isr); 1642 return VMX_TEST_START; 1643 } 1644 1645 static void interrupt_main(void) 1646 { 1647 long long start, loops; 1648 1649 vmx_set_test_stage(0); 1650 1651 apic_write(APIC_LVTT, TIMER_VECTOR); 1652 irq_enable(); 1653 1654 apic_write(APIC_TMICT, 1); 1655 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1656 asm volatile ("nop"); 1657 report("direct interrupt while running guest", timer_fired); 1658 1659 apic_write(APIC_TMICT, 0); 1660 irq_disable(); 1661 vmcall(); 1662 timer_fired = false; 1663 apic_write(APIC_TMICT, 1); 1664 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1665 asm volatile ("nop"); 1666 report("intercepted interrupt while running guest", timer_fired); 1667 1668 irq_enable(); 1669 apic_write(APIC_TMICT, 0); 1670 irq_disable(); 1671 vmcall(); 1672 timer_fired = false; 1673 start = rdtsc(); 1674 apic_write(APIC_TMICT, 1000000); 1675 1676 asm volatile ("sti; hlt"); 1677 1678 report("direct interrupt + hlt", 1679 rdtsc() - start > 1000000 && timer_fired); 1680 1681 apic_write(APIC_TMICT, 0); 1682 irq_disable(); 1683 vmcall(); 1684 timer_fired = false; 1685 start = rdtsc(); 1686 apic_write(APIC_TMICT, 1000000); 1687 1688 asm volatile ("sti; hlt"); 1689 1690 report("intercepted interrupt + hlt", 1691 rdtsc() - start > 10000 && timer_fired); 1692 1693 apic_write(APIC_TMICT, 0); 1694 irq_disable(); 1695 vmcall(); 1696 timer_fired = false; 1697 start = rdtsc(); 1698 apic_write(APIC_TMICT, 1000000); 1699 1700 irq_enable(); 1701 asm volatile ("nop"); 1702 vmcall(); 1703 1704 report("direct interrupt + activity state hlt", 1705 rdtsc() - start > 10000 && timer_fired); 1706 1707 apic_write(APIC_TMICT, 0); 1708 irq_disable(); 1709 vmcall(); 1710 timer_fired = false; 1711 start = rdtsc(); 1712 apic_write(APIC_TMICT, 1000000); 1713 1714 irq_enable(); 1715 asm volatile ("nop"); 1716 vmcall(); 1717 1718 report("intercepted interrupt + activity state hlt", 1719 rdtsc() - start > 10000 && timer_fired); 1720 1721 apic_write(APIC_TMICT, 0); 1722 irq_disable(); 1723 vmx_set_test_stage(7); 1724 vmcall(); 1725 timer_fired = false; 1726 apic_write(APIC_TMICT, 1); 1727 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1728 asm volatile ("nop"); 1729 report("running a guest with interrupt acknowledgement set", timer_fired); 1730 1731 apic_write(APIC_TMICT, 0); 1732 irq_enable(); 1733 timer_fired = false; 1734 vmcall(); 1735 report("Inject an event to a halted guest", timer_fired); 1736 } 1737 1738 static int interrupt_exit_handler(void) 1739 { 1740 u64 guest_rip = vmcs_read(GUEST_RIP); 1741 ulong reason = vmcs_read(EXI_REASON) & 0xff; 1742 u32 insn_len = vmcs_read(EXI_INST_LEN); 1743 1744 switch (reason) { 1745 case VMX_VMCALL: 1746 switch (vmx_get_test_stage()) { 1747 case 0: 1748 case 2: 1749 case 5: 1750 vmcs_write(PIN_CONTROLS, 1751 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1752 break; 1753 case 7: 1754 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_INTA); 1755 vmcs_write(PIN_CONTROLS, 1756 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1757 break; 1758 case 1: 1759 case 3: 1760 vmcs_write(PIN_CONTROLS, 1761 vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1762 break; 1763 case 4: 1764 case 6: 1765 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1766 break; 1767 1768 case 8: 1769 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1770 vmcs_write(ENT_INTR_INFO, 1771 TIMER_VECTOR | 1772 (VMX_INTR_TYPE_EXT_INTR << INTR_INFO_INTR_TYPE_SHIFT) | 1773 INTR_INFO_VALID_MASK); 1774 break; 1775 } 1776 vmx_inc_test_stage(); 1777 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1778 return VMX_TEST_RESUME; 1779 case VMX_EXTINT: 1780 if (vmcs_read(EXI_CONTROLS) & EXI_INTA) { 1781 int vector = vmcs_read(EXI_INTR_INFO) & 0xff; 1782 handle_external_interrupt(vector); 1783 } else { 1784 irq_enable(); 1785 asm volatile ("nop"); 1786 irq_disable(); 1787 } 1788 if (vmx_get_test_stage() >= 2) 1789 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 1790 return VMX_TEST_RESUME; 1791 default: 1792 report("Unknown exit reason, %ld", false, reason); 1793 print_vmexit_info(); 1794 } 1795 1796 return VMX_TEST_VMEXIT; 1797 } 1798 1799 static int dbgctls_init(struct vmcs *vmcs) 1800 { 1801 u64 dr7 = 0x402; 1802 u64 zero = 0; 1803 1804 msr_bmp_init(); 1805 asm volatile( 1806 "mov %0,%%dr0\n\t" 1807 "mov %0,%%dr1\n\t" 1808 "mov %0,%%dr2\n\t" 1809 "mov %1,%%dr7\n\t" 1810 : : "r" (zero), "r" (dr7)); 1811 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1812 vmcs_write(GUEST_DR7, 0x404); 1813 vmcs_write(GUEST_DEBUGCTL, 0x2); 1814 1815 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 1816 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_SAVE_DBGCTLS); 1817 1818 return VMX_TEST_START; 1819 } 1820 1821 static void dbgctls_main(void) 1822 { 1823 u64 dr7, debugctl; 1824 1825 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1826 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1827 /* Commented out: KVM does not support DEBUGCTL so far */ 1828 (void)debugctl; 1829 report("Load debug controls", dr7 == 0x404 /* && debugctl == 0x2 */); 1830 1831 dr7 = 0x408; 1832 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1833 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1834 1835 vmx_set_test_stage(0); 1836 vmcall(); 1837 report("Save debug controls", vmx_get_test_stage() == 1); 1838 1839 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS || 1840 ctrl_exit_rev.set & EXI_SAVE_DBGCTLS) { 1841 printf("\tDebug controls are always loaded/saved\n"); 1842 return; 1843 } 1844 vmx_set_test_stage(2); 1845 vmcall(); 1846 1847 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1848 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1849 /* Commented out: KVM does not support DEBUGCTL so far */ 1850 (void)debugctl; 1851 report("Guest=host debug controls", dr7 == 0x402 /* && debugctl == 0x1 */); 1852 1853 dr7 = 0x408; 1854 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1855 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1856 1857 vmx_set_test_stage(3); 1858 vmcall(); 1859 report("Don't save debug controls", vmx_get_test_stage() == 4); 1860 } 1861 1862 static int dbgctls_exit_handler(void) 1863 { 1864 unsigned int reason = vmcs_read(EXI_REASON) & 0xff; 1865 u32 insn_len = vmcs_read(EXI_INST_LEN); 1866 u64 guest_rip = vmcs_read(GUEST_RIP); 1867 u64 dr7, debugctl; 1868 1869 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1870 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1871 1872 switch (reason) { 1873 case VMX_VMCALL: 1874 switch (vmx_get_test_stage()) { 1875 case 0: 1876 if (dr7 == 0x400 && debugctl == 0 && 1877 vmcs_read(GUEST_DR7) == 0x408 /* && 1878 Commented out: KVM does not support DEBUGCTL so far 1879 vmcs_read(GUEST_DEBUGCTL) == 0x3 */) 1880 vmx_inc_test_stage(); 1881 break; 1882 case 2: 1883 dr7 = 0x402; 1884 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1885 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1886 vmcs_write(GUEST_DR7, 0x404); 1887 vmcs_write(GUEST_DEBUGCTL, 0x2); 1888 1889 vmcs_write(ENT_CONTROLS, 1890 vmcs_read(ENT_CONTROLS) & ~ENT_LOAD_DBGCTLS); 1891 vmcs_write(EXI_CONTROLS, 1892 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_DBGCTLS); 1893 break; 1894 case 3: 1895 if (dr7 == 0x400 && debugctl == 0 && 1896 vmcs_read(GUEST_DR7) == 0x404 /* && 1897 Commented out: KVM does not support DEBUGCTL so far 1898 vmcs_read(GUEST_DEBUGCTL) == 0x2 */) 1899 vmx_inc_test_stage(); 1900 break; 1901 } 1902 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1903 return VMX_TEST_RESUME; 1904 default: 1905 report("Unknown exit reason, %d", false, reason); 1906 print_vmexit_info(); 1907 } 1908 return VMX_TEST_VMEXIT; 1909 } 1910 1911 struct vmx_msr_entry { 1912 u32 index; 1913 u32 reserved; 1914 u64 value; 1915 } __attribute__((packed)); 1916 1917 #define MSR_MAGIC 0x31415926 1918 struct vmx_msr_entry *exit_msr_store, *entry_msr_load, *exit_msr_load; 1919 1920 static int msr_switch_init(struct vmcs *vmcs) 1921 { 1922 msr_bmp_init(); 1923 exit_msr_store = alloc_page(); 1924 exit_msr_load = alloc_page(); 1925 entry_msr_load = alloc_page(); 1926 entry_msr_load[0].index = MSR_KERNEL_GS_BASE; 1927 entry_msr_load[0].value = MSR_MAGIC; 1928 1929 vmx_set_test_stage(1); 1930 vmcs_write(ENT_MSR_LD_CNT, 1); 1931 vmcs_write(ENTER_MSR_LD_ADDR, (u64)entry_msr_load); 1932 vmcs_write(EXI_MSR_ST_CNT, 1); 1933 vmcs_write(EXIT_MSR_ST_ADDR, (u64)exit_msr_store); 1934 vmcs_write(EXI_MSR_LD_CNT, 1); 1935 vmcs_write(EXIT_MSR_LD_ADDR, (u64)exit_msr_load); 1936 return VMX_TEST_START; 1937 } 1938 1939 static void msr_switch_main(void) 1940 { 1941 if (vmx_get_test_stage() == 1) { 1942 report("VM entry MSR load", 1943 rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC); 1944 vmx_set_test_stage(2); 1945 wrmsr(MSR_KERNEL_GS_BASE, MSR_MAGIC + 1); 1946 exit_msr_store[0].index = MSR_KERNEL_GS_BASE; 1947 exit_msr_load[0].index = MSR_KERNEL_GS_BASE; 1948 exit_msr_load[0].value = MSR_MAGIC + 2; 1949 } 1950 vmcall(); 1951 } 1952 1953 static int msr_switch_exit_handler(void) 1954 { 1955 ulong reason; 1956 1957 reason = vmcs_read(EXI_REASON); 1958 if (reason == VMX_VMCALL && vmx_get_test_stage() == 2) { 1959 report("VM exit MSR store", 1960 exit_msr_store[0].value == MSR_MAGIC + 1); 1961 report("VM exit MSR load", 1962 rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC + 2); 1963 vmx_set_test_stage(3); 1964 entry_msr_load[0].index = MSR_FS_BASE; 1965 return VMX_TEST_RESUME; 1966 } 1967 printf("ERROR %s: unexpected stage=%u or reason=%lu\n", 1968 __func__, vmx_get_test_stage(), reason); 1969 return VMX_TEST_EXIT; 1970 } 1971 1972 static int msr_switch_entry_failure(struct vmentry_failure *failure) 1973 { 1974 ulong reason; 1975 1976 if (failure->early) { 1977 printf("ERROR %s: early exit\n", __func__); 1978 return VMX_TEST_EXIT; 1979 } 1980 1981 reason = vmcs_read(EXI_REASON); 1982 if (reason == (VMX_ENTRY_FAILURE | VMX_FAIL_MSR) && 1983 vmx_get_test_stage() == 3) { 1984 report("VM entry MSR load: try to load FS_BASE", 1985 vmcs_read(EXI_QUALIFICATION) == 1); 1986 return VMX_TEST_VMEXIT; 1987 } 1988 printf("ERROR %s: unexpected stage=%u or reason=%lu\n", 1989 __func__, vmx_get_test_stage(), reason); 1990 return VMX_TEST_EXIT; 1991 } 1992 1993 static int vmmcall_init(struct vmcs *vmcs) 1994 { 1995 vmcs_write(EXC_BITMAP, 1 << UD_VECTOR); 1996 return VMX_TEST_START; 1997 } 1998 1999 static void vmmcall_main(void) 2000 { 2001 asm volatile( 2002 "mov $0xABCD, %%rax\n\t" 2003 "vmmcall\n\t" 2004 ::: "rax"); 2005 2006 report("VMMCALL", 0); 2007 } 2008 2009 static int vmmcall_exit_handler(void) 2010 { 2011 ulong reason; 2012 2013 reason = vmcs_read(EXI_REASON); 2014 switch (reason) { 2015 case VMX_VMCALL: 2016 printf("here\n"); 2017 report("VMMCALL triggers #UD", 0); 2018 break; 2019 case VMX_EXC_NMI: 2020 report("VMMCALL triggers #UD", 2021 (vmcs_read(EXI_INTR_INFO) & 0xff) == UD_VECTOR); 2022 break; 2023 default: 2024 report("Unknown exit reason, %ld", false, reason); 2025 print_vmexit_info(); 2026 } 2027 2028 return VMX_TEST_VMEXIT; 2029 } 2030 2031 static int disable_rdtscp_init(struct vmcs *vmcs) 2032 { 2033 u32 ctrl_cpu1; 2034 2035 if (ctrl_cpu_rev[0].clr & CPU_SECONDARY) { 2036 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 2037 ctrl_cpu1 &= ~CPU_RDTSCP; 2038 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 2039 } 2040 2041 return VMX_TEST_START; 2042 } 2043 2044 static void disable_rdtscp_ud_handler(struct ex_regs *regs) 2045 { 2046 switch (vmx_get_test_stage()) { 2047 case 0: 2048 report("RDTSCP triggers #UD", true); 2049 vmx_inc_test_stage(); 2050 regs->rip += 3; 2051 break; 2052 case 2: 2053 report("RDPID triggers #UD", true); 2054 vmx_inc_test_stage(); 2055 regs->rip += 4; 2056 break; 2057 } 2058 return; 2059 2060 } 2061 2062 static void disable_rdtscp_main(void) 2063 { 2064 /* Test that #UD is properly injected in L2. */ 2065 handle_exception(UD_VECTOR, disable_rdtscp_ud_handler); 2066 2067 vmx_set_test_stage(0); 2068 asm volatile("rdtscp" : : : "eax", "ecx", "edx"); 2069 vmcall(); 2070 asm volatile(".byte 0xf3, 0x0f, 0xc7, 0xf8" : : : "eax"); 2071 2072 handle_exception(UD_VECTOR, 0); 2073 vmcall(); 2074 } 2075 2076 static int disable_rdtscp_exit_handler(void) 2077 { 2078 unsigned int reason = vmcs_read(EXI_REASON) & 0xff; 2079 2080 switch (reason) { 2081 case VMX_VMCALL: 2082 switch (vmx_get_test_stage()) { 2083 case 0: 2084 report("RDTSCP triggers #UD", false); 2085 vmx_inc_test_stage(); 2086 /* fallthrough */ 2087 case 1: 2088 vmx_inc_test_stage(); 2089 vmcs_write(GUEST_RIP, vmcs_read(GUEST_RIP) + 3); 2090 return VMX_TEST_RESUME; 2091 case 2: 2092 report("RDPID triggers #UD", false); 2093 break; 2094 } 2095 break; 2096 2097 default: 2098 report("Unknown exit reason, %d", false, reason); 2099 print_vmexit_info(); 2100 } 2101 return VMX_TEST_VMEXIT; 2102 } 2103 2104 static int int3_init(struct vmcs *vmcs) 2105 { 2106 vmcs_write(EXC_BITMAP, ~0u); 2107 return VMX_TEST_START; 2108 } 2109 2110 static void int3_guest_main(void) 2111 { 2112 asm volatile ("int3"); 2113 } 2114 2115 static int int3_exit_handler(void) 2116 { 2117 u32 reason = vmcs_read(EXI_REASON); 2118 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2119 2120 report("L1 intercepts #BP", reason == VMX_EXC_NMI && 2121 (intr_info & INTR_INFO_VALID_MASK) && 2122 (intr_info & INTR_INFO_VECTOR_MASK) == BP_VECTOR && 2123 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2124 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION); 2125 2126 return VMX_TEST_VMEXIT; 2127 } 2128 2129 static int into_init(struct vmcs *vmcs) 2130 { 2131 vmcs_write(EXC_BITMAP, ~0u); 2132 return VMX_TEST_START; 2133 } 2134 2135 static void into_guest_main(void) 2136 { 2137 struct far_pointer32 fp = { 2138 .offset = (uintptr_t)&&into, 2139 .selector = KERNEL_CS32, 2140 }; 2141 register uintptr_t rsp asm("rsp"); 2142 2143 if (fp.offset != (uintptr_t)&&into) { 2144 printf("Code address too high.\n"); 2145 return; 2146 } 2147 if ((u32)rsp != rsp) { 2148 printf("Stack address too high.\n"); 2149 return; 2150 } 2151 2152 asm goto ("lcall *%0" : : "m" (fp) : "rax" : into); 2153 return; 2154 into: 2155 asm volatile (".code32;" 2156 "movl $0x7fffffff, %eax;" 2157 "addl %eax, %eax;" 2158 "into;" 2159 "lret;" 2160 ".code64"); 2161 __builtin_unreachable(); 2162 } 2163 2164 static int into_exit_handler(void) 2165 { 2166 u32 reason = vmcs_read(EXI_REASON); 2167 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2168 2169 report("L1 intercepts #OF", reason == VMX_EXC_NMI && 2170 (intr_info & INTR_INFO_VALID_MASK) && 2171 (intr_info & INTR_INFO_VECTOR_MASK) == OF_VECTOR && 2172 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2173 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION); 2174 2175 return VMX_TEST_VMEXIT; 2176 } 2177 2178 static void exit_monitor_from_l2_main(void) 2179 { 2180 printf("Calling exit(0) from l2...\n"); 2181 exit(0); 2182 } 2183 2184 static int exit_monitor_from_l2_handler(void) 2185 { 2186 report("The guest should have killed the VMM", false); 2187 return VMX_TEST_EXIT; 2188 } 2189 2190 static void assert_exit_reason(u64 expected) 2191 { 2192 u64 actual = vmcs_read(EXI_REASON); 2193 2194 TEST_ASSERT_EQ_MSG(expected, actual, "Expected %s, got %s.", 2195 exit_reason_description(expected), 2196 exit_reason_description(actual)); 2197 } 2198 2199 static void skip_exit_insn(void) 2200 { 2201 u64 guest_rip = vmcs_read(GUEST_RIP); 2202 u32 insn_len = vmcs_read(EXI_INST_LEN); 2203 vmcs_write(GUEST_RIP, guest_rip + insn_len); 2204 } 2205 2206 static void skip_exit_vmcall(void) 2207 { 2208 assert_exit_reason(VMX_VMCALL); 2209 skip_exit_insn(); 2210 } 2211 2212 static void v2_null_test_guest(void) 2213 { 2214 } 2215 2216 static void v2_null_test(void) 2217 { 2218 test_set_guest(v2_null_test_guest); 2219 enter_guest(); 2220 report(__func__, 1); 2221 } 2222 2223 static void v2_multiple_entries_test_guest(void) 2224 { 2225 vmx_set_test_stage(1); 2226 vmcall(); 2227 vmx_set_test_stage(2); 2228 } 2229 2230 static void v2_multiple_entries_test(void) 2231 { 2232 test_set_guest(v2_multiple_entries_test_guest); 2233 enter_guest(); 2234 TEST_ASSERT_EQ(vmx_get_test_stage(), 1); 2235 skip_exit_vmcall(); 2236 enter_guest(); 2237 TEST_ASSERT_EQ(vmx_get_test_stage(), 2); 2238 report(__func__, 1); 2239 } 2240 2241 static int fixture_test_data = 1; 2242 2243 static void fixture_test_teardown(void *data) 2244 { 2245 *((int *) data) = 1; 2246 } 2247 2248 static void fixture_test_guest(void) 2249 { 2250 fixture_test_data++; 2251 } 2252 2253 2254 static void fixture_test_setup(void) 2255 { 2256 TEST_ASSERT_EQ_MSG(1, fixture_test_data, 2257 "fixture_test_teardown didn't run?!"); 2258 fixture_test_data = 2; 2259 test_add_teardown(fixture_test_teardown, &fixture_test_data); 2260 test_set_guest(fixture_test_guest); 2261 } 2262 2263 static void fixture_test_case1(void) 2264 { 2265 fixture_test_setup(); 2266 TEST_ASSERT_EQ(2, fixture_test_data); 2267 enter_guest(); 2268 TEST_ASSERT_EQ(3, fixture_test_data); 2269 report(__func__, 1); 2270 } 2271 2272 static void fixture_test_case2(void) 2273 { 2274 fixture_test_setup(); 2275 TEST_ASSERT_EQ(2, fixture_test_data); 2276 enter_guest(); 2277 TEST_ASSERT_EQ(3, fixture_test_data); 2278 report(__func__, 1); 2279 } 2280 2281 enum ept_access_op { 2282 OP_READ, 2283 OP_WRITE, 2284 OP_EXEC, 2285 OP_FLUSH_TLB, 2286 OP_EXIT, 2287 }; 2288 2289 static struct ept_access_test_data { 2290 unsigned long gpa; 2291 unsigned long *gva; 2292 unsigned long hpa; 2293 unsigned long *hva; 2294 enum ept_access_op op; 2295 } ept_access_test_data; 2296 2297 extern unsigned char ret42_start; 2298 extern unsigned char ret42_end; 2299 2300 /* Returns 42. */ 2301 asm( 2302 ".align 64\n" 2303 "ret42_start:\n" 2304 "mov $42, %eax\n" 2305 "ret\n" 2306 "ret42_end:\n" 2307 ); 2308 2309 static void 2310 diagnose_ept_violation_qual(u64 expected, u64 actual) 2311 { 2312 2313 #define DIAGNOSE(flag) \ 2314 do { \ 2315 if ((expected & flag) != (actual & flag)) \ 2316 printf(#flag " %sexpected\n", \ 2317 (expected & flag) ? "" : "un"); \ 2318 } while (0) 2319 2320 DIAGNOSE(EPT_VLT_RD); 2321 DIAGNOSE(EPT_VLT_WR); 2322 DIAGNOSE(EPT_VLT_FETCH); 2323 DIAGNOSE(EPT_VLT_PERM_RD); 2324 DIAGNOSE(EPT_VLT_PERM_WR); 2325 DIAGNOSE(EPT_VLT_PERM_EX); 2326 DIAGNOSE(EPT_VLT_LADDR_VLD); 2327 DIAGNOSE(EPT_VLT_PADDR); 2328 2329 #undef DIAGNOSE 2330 } 2331 2332 static void do_ept_access_op(enum ept_access_op op) 2333 { 2334 ept_access_test_data.op = op; 2335 enter_guest(); 2336 } 2337 2338 /* 2339 * Force the guest to flush its TLB (i.e., flush gva -> gpa mappings). Only 2340 * needed by tests that modify guest PTEs. 2341 */ 2342 static void ept_access_test_guest_flush_tlb(void) 2343 { 2344 do_ept_access_op(OP_FLUSH_TLB); 2345 skip_exit_vmcall(); 2346 } 2347 2348 /* 2349 * Modifies the EPT entry at @level in the mapping of @gpa. First clears the 2350 * bits in @clear then sets the bits in @set. @mkhuge transforms the entry into 2351 * a huge page. 2352 */ 2353 static unsigned long ept_twiddle(unsigned long gpa, bool mkhuge, int level, 2354 unsigned long clear, unsigned long set) 2355 { 2356 struct ept_access_test_data *data = &ept_access_test_data; 2357 unsigned long orig_pte; 2358 unsigned long pte; 2359 2360 /* Screw with the mapping at the requested level. */ 2361 TEST_ASSERT(get_ept_pte(pml4, gpa, level, &orig_pte)); 2362 pte = orig_pte; 2363 if (mkhuge) 2364 pte = (orig_pte & ~EPT_ADDR_MASK) | data->hpa | EPT_LARGE_PAGE; 2365 else 2366 pte = orig_pte; 2367 pte = (pte & ~clear) | set; 2368 set_ept_pte(pml4, gpa, level, pte); 2369 ept_sync(INVEPT_SINGLE, eptp); 2370 2371 return orig_pte; 2372 } 2373 2374 static void ept_untwiddle(unsigned long gpa, int level, unsigned long orig_pte) 2375 { 2376 set_ept_pte(pml4, gpa, level, orig_pte); 2377 ept_sync(INVEPT_SINGLE, eptp); 2378 } 2379 2380 static void do_ept_violation(bool leaf, enum ept_access_op op, 2381 u64 expected_qual, u64 expected_paddr) 2382 { 2383 u64 qual; 2384 2385 /* Try the access and observe the violation. */ 2386 do_ept_access_op(op); 2387 2388 assert_exit_reason(VMX_EPT_VIOLATION); 2389 2390 qual = vmcs_read(EXI_QUALIFICATION); 2391 2392 /* Mask undefined bits (which may later be defined in certain cases). */ 2393 qual &= ~(EPT_VLT_GUEST_USER | EPT_VLT_GUEST_RW | EPT_VLT_GUEST_EX | 2394 EPT_VLT_PERM_USER_EX); 2395 2396 diagnose_ept_violation_qual(expected_qual, qual); 2397 TEST_EXPECT_EQ(expected_qual, qual); 2398 2399 #if 0 2400 /* Disable for now otherwise every test will fail */ 2401 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2402 (unsigned long) ( 2403 op == OP_EXEC ? data->gva + 1 : data->gva)); 2404 #endif 2405 /* 2406 * TODO: tests that probe expected_paddr in pages other than the one at 2407 * the beginning of the 1g region. 2408 */ 2409 TEST_EXPECT_EQ(vmcs_read(INFO_PHYS_ADDR), expected_paddr); 2410 } 2411 2412 static void 2413 ept_violation_at_level_mkhuge(bool mkhuge, int level, unsigned long clear, 2414 unsigned long set, enum ept_access_op op, 2415 u64 expected_qual) 2416 { 2417 struct ept_access_test_data *data = &ept_access_test_data; 2418 unsigned long orig_pte; 2419 2420 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2421 2422 do_ept_violation(level == 1 || mkhuge, op, expected_qual, 2423 op == OP_EXEC ? data->gpa + sizeof(unsigned long) : 2424 data->gpa); 2425 2426 /* Fix the violation and resume the op loop. */ 2427 ept_untwiddle(data->gpa, level, orig_pte); 2428 enter_guest(); 2429 skip_exit_vmcall(); 2430 } 2431 2432 static void 2433 ept_violation_at_level(int level, unsigned long clear, unsigned long set, 2434 enum ept_access_op op, u64 expected_qual) 2435 { 2436 ept_violation_at_level_mkhuge(false, level, clear, set, op, 2437 expected_qual); 2438 if (ept_huge_pages_supported(level)) 2439 ept_violation_at_level_mkhuge(true, level, clear, set, op, 2440 expected_qual); 2441 } 2442 2443 static void ept_violation(unsigned long clear, unsigned long set, 2444 enum ept_access_op op, u64 expected_qual) 2445 { 2446 ept_violation_at_level(1, clear, set, op, expected_qual); 2447 ept_violation_at_level(2, clear, set, op, expected_qual); 2448 ept_violation_at_level(3, clear, set, op, expected_qual); 2449 ept_violation_at_level(4, clear, set, op, expected_qual); 2450 } 2451 2452 static void ept_access_violation(unsigned long access, enum ept_access_op op, 2453 u64 expected_qual) 2454 { 2455 ept_violation(EPT_PRESENT, access, op, 2456 expected_qual | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2457 } 2458 2459 /* 2460 * For translations that don't involve a GVA, that is physical address (paddr) 2461 * accesses, EPT violations don't set the flag EPT_VLT_PADDR. For a typical 2462 * guest memory access, the hardware does GVA -> GPA -> HPA. However, certain 2463 * translations don't involve GVAs, such as when the hardware does the guest 2464 * page table walk. For example, in translating GVA_1 -> GPA_1, the guest MMU 2465 * might try to set an A bit on a guest PTE. If the GPA_2 that the PTE resides 2466 * on isn't present in the EPT, then the EPT violation will be for GPA_2 and 2467 * the EPT_VLT_PADDR bit will be clear in the exit qualification. 2468 * 2469 * Note that paddr violations can also be triggered by loading PAE page tables 2470 * with wonky addresses. We don't test that yet. 2471 * 2472 * This function modifies the EPT entry that maps the GPA that the guest page 2473 * table entry mapping ept_access_test_data.gva resides on. 2474 * 2475 * @ept_access EPT permissions to set. Other permissions are cleared. 2476 * 2477 * @pte_ad Set the A/D bits on the guest PTE accordingly. 2478 * 2479 * @op Guest operation to perform with 2480 * ept_access_test_data.gva. 2481 * 2482 * @expect_violation 2483 * Is a violation expected during the paddr access? 2484 * 2485 * @expected_qual Expected qualification for the EPT violation. 2486 * EPT_VLT_PADDR should be clear. 2487 */ 2488 static void ept_access_paddr(unsigned long ept_access, unsigned long pte_ad, 2489 enum ept_access_op op, bool expect_violation, 2490 u64 expected_qual) 2491 { 2492 struct ept_access_test_data *data = &ept_access_test_data; 2493 unsigned long *ptep; 2494 unsigned long gpa; 2495 unsigned long orig_epte; 2496 2497 /* Modify the guest PTE mapping data->gva according to @pte_ad. */ 2498 ptep = get_pte_level(current_page_table(), data->gva, /*level=*/1); 2499 TEST_ASSERT(ptep); 2500 TEST_ASSERT_EQ(*ptep & PT_ADDR_MASK, data->gpa); 2501 *ptep = (*ptep & ~PT_AD_MASK) | pte_ad; 2502 ept_access_test_guest_flush_tlb(); 2503 2504 /* 2505 * Now modify the access bits on the EPT entry for the GPA that the 2506 * guest PTE resides on. Note that by modifying a single EPT entry, 2507 * we're potentially affecting 512 guest PTEs. However, we've carefully 2508 * constructed our test such that those other 511 PTEs aren't used by 2509 * the guest: data->gva is at the beginning of a 1G huge page, thus the 2510 * PTE we're modifying is at the beginning of a 4K page and the 2511 * following 511 entires are also under our control (and not touched by 2512 * the guest). 2513 */ 2514 gpa = virt_to_phys(ptep); 2515 TEST_ASSERT_EQ(gpa & ~PAGE_MASK, 0); 2516 /* 2517 * Make sure the guest page table page is mapped with a 4K EPT entry, 2518 * otherwise our level=1 twiddling below will fail. We use the 2519 * identity map (gpa = gpa) since page tables are shared with the host. 2520 */ 2521 install_ept(pml4, gpa, gpa, EPT_PRESENT); 2522 orig_epte = ept_twiddle(gpa, /*mkhuge=*/0, /*level=*/1, 2523 /*clear=*/EPT_PRESENT, /*set=*/ept_access); 2524 2525 if (expect_violation) { 2526 do_ept_violation(/*leaf=*/true, op, 2527 expected_qual | EPT_VLT_LADDR_VLD, gpa); 2528 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2529 do_ept_access_op(op); 2530 } else { 2531 do_ept_access_op(op); 2532 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2533 } 2534 2535 TEST_ASSERT(*ptep & PT_ACCESSED_MASK); 2536 if ((pte_ad & PT_DIRTY_MASK) || op == OP_WRITE) 2537 TEST_ASSERT(*ptep & PT_DIRTY_MASK); 2538 2539 skip_exit_vmcall(); 2540 } 2541 2542 static void ept_access_allowed_paddr(unsigned long ept_access, 2543 unsigned long pte_ad, 2544 enum ept_access_op op) 2545 { 2546 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/false, 2547 /*expected_qual=*/-1); 2548 } 2549 2550 static void ept_access_violation_paddr(unsigned long ept_access, 2551 unsigned long pte_ad, 2552 enum ept_access_op op, 2553 u64 expected_qual) 2554 { 2555 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/true, 2556 expected_qual); 2557 } 2558 2559 2560 static void ept_allowed_at_level_mkhuge(bool mkhuge, int level, 2561 unsigned long clear, 2562 unsigned long set, 2563 enum ept_access_op op) 2564 { 2565 struct ept_access_test_data *data = &ept_access_test_data; 2566 unsigned long orig_pte; 2567 2568 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2569 2570 /* No violation. Should proceed to vmcall. */ 2571 do_ept_access_op(op); 2572 skip_exit_vmcall(); 2573 2574 ept_untwiddle(data->gpa, level, orig_pte); 2575 } 2576 2577 static void ept_allowed_at_level(int level, unsigned long clear, 2578 unsigned long set, enum ept_access_op op) 2579 { 2580 ept_allowed_at_level_mkhuge(false, level, clear, set, op); 2581 if (ept_huge_pages_supported(level)) 2582 ept_allowed_at_level_mkhuge(true, level, clear, set, op); 2583 } 2584 2585 static void ept_allowed(unsigned long clear, unsigned long set, 2586 enum ept_access_op op) 2587 { 2588 ept_allowed_at_level(1, clear, set, op); 2589 ept_allowed_at_level(2, clear, set, op); 2590 ept_allowed_at_level(3, clear, set, op); 2591 ept_allowed_at_level(4, clear, set, op); 2592 } 2593 2594 static void ept_ignored_bit(int bit) 2595 { 2596 /* Set the bit. */ 2597 ept_allowed(0, 1ul << bit, OP_READ); 2598 ept_allowed(0, 1ul << bit, OP_WRITE); 2599 ept_allowed(0, 1ul << bit, OP_EXEC); 2600 2601 /* Clear the bit. */ 2602 ept_allowed(1ul << bit, 0, OP_READ); 2603 ept_allowed(1ul << bit, 0, OP_WRITE); 2604 ept_allowed(1ul << bit, 0, OP_EXEC); 2605 } 2606 2607 static void ept_access_allowed(unsigned long access, enum ept_access_op op) 2608 { 2609 ept_allowed(EPT_PRESENT, access, op); 2610 } 2611 2612 2613 static void ept_misconfig_at_level_mkhuge_op(bool mkhuge, int level, 2614 unsigned long clear, 2615 unsigned long set, 2616 enum ept_access_op op) 2617 { 2618 struct ept_access_test_data *data = &ept_access_test_data; 2619 unsigned long orig_pte; 2620 2621 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2622 2623 do_ept_access_op(op); 2624 assert_exit_reason(VMX_EPT_MISCONFIG); 2625 2626 /* Intel 27.2.1, "For all other VM exits, this field is cleared." */ 2627 #if 0 2628 /* broken: */ 2629 TEST_EXPECT_EQ_MSG(vmcs_read(EXI_QUALIFICATION), 0); 2630 #endif 2631 #if 0 2632 /* 2633 * broken: 2634 * According to description of exit qual for EPT violation, 2635 * EPT_VLT_LADDR_VLD indicates if GUEST_LINEAR_ADDRESS is valid. 2636 * However, I can't find anything that says GUEST_LINEAR_ADDRESS ought 2637 * to be set for msiconfig. 2638 */ 2639 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2640 (unsigned long) ( 2641 op == OP_EXEC ? data->gva + 1 : data->gva)); 2642 #endif 2643 2644 /* Fix the violation and resume the op loop. */ 2645 ept_untwiddle(data->gpa, level, orig_pte); 2646 enter_guest(); 2647 skip_exit_vmcall(); 2648 } 2649 2650 static void ept_misconfig_at_level_mkhuge(bool mkhuge, int level, 2651 unsigned long clear, 2652 unsigned long set) 2653 { 2654 /* The op shouldn't matter (read, write, exec), so try them all! */ 2655 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_READ); 2656 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_WRITE); 2657 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_EXEC); 2658 } 2659 2660 static void ept_misconfig_at_level(int level, unsigned long clear, 2661 unsigned long set) 2662 { 2663 ept_misconfig_at_level_mkhuge(false, level, clear, set); 2664 if (ept_huge_pages_supported(level)) 2665 ept_misconfig_at_level_mkhuge(true, level, clear, set); 2666 } 2667 2668 static void ept_misconfig(unsigned long clear, unsigned long set) 2669 { 2670 ept_misconfig_at_level(1, clear, set); 2671 ept_misconfig_at_level(2, clear, set); 2672 ept_misconfig_at_level(3, clear, set); 2673 ept_misconfig_at_level(4, clear, set); 2674 } 2675 2676 static void ept_access_misconfig(unsigned long access) 2677 { 2678 ept_misconfig(EPT_PRESENT, access); 2679 } 2680 2681 static void ept_reserved_bit_at_level_nohuge(int level, int bit) 2682 { 2683 /* Setting the bit causes a misconfig. */ 2684 ept_misconfig_at_level_mkhuge(false, level, 0, 1ul << bit); 2685 2686 /* Making the entry non-present turns reserved bits into ignored. */ 2687 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2688 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2689 } 2690 2691 static void ept_reserved_bit_at_level_huge(int level, int bit) 2692 { 2693 /* Setting the bit causes a misconfig. */ 2694 ept_misconfig_at_level_mkhuge(true, level, 0, 1ul << bit); 2695 2696 /* Making the entry non-present turns reserved bits into ignored. */ 2697 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2698 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2699 } 2700 2701 static void ept_reserved_bit_at_level(int level, int bit) 2702 { 2703 /* Setting the bit causes a misconfig. */ 2704 ept_misconfig_at_level(level, 0, 1ul << bit); 2705 2706 /* Making the entry non-present turns reserved bits into ignored. */ 2707 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2708 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2709 } 2710 2711 static void ept_reserved_bit(int bit) 2712 { 2713 ept_reserved_bit_at_level(1, bit); 2714 ept_reserved_bit_at_level(2, bit); 2715 ept_reserved_bit_at_level(3, bit); 2716 ept_reserved_bit_at_level(4, bit); 2717 } 2718 2719 #define PAGE_2M_ORDER 9 2720 #define PAGE_1G_ORDER 18 2721 2722 static void *get_1g_page(void) 2723 { 2724 static void *alloc; 2725 2726 if (!alloc) 2727 alloc = alloc_pages(PAGE_1G_ORDER); 2728 return alloc; 2729 } 2730 2731 static void ept_access_test_teardown(void *unused) 2732 { 2733 /* Exit the guest cleanly. */ 2734 do_ept_access_op(OP_EXIT); 2735 } 2736 2737 static void ept_access_test_guest(void) 2738 { 2739 struct ept_access_test_data *data = &ept_access_test_data; 2740 int (*code)(void) = (int (*)(void)) &data->gva[1]; 2741 2742 while (true) { 2743 switch (data->op) { 2744 case OP_READ: 2745 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_1); 2746 break; 2747 case OP_WRITE: 2748 *data->gva = MAGIC_VAL_2; 2749 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_2); 2750 *data->gva = MAGIC_VAL_1; 2751 break; 2752 case OP_EXEC: 2753 TEST_ASSERT_EQ(42, code()); 2754 break; 2755 case OP_FLUSH_TLB: 2756 write_cr3(read_cr3()); 2757 break; 2758 case OP_EXIT: 2759 return; 2760 default: 2761 TEST_ASSERT_MSG(false, "Unknown op %d", data->op); 2762 } 2763 vmcall(); 2764 } 2765 } 2766 2767 static void ept_access_test_setup(void) 2768 { 2769 struct ept_access_test_data *data = &ept_access_test_data; 2770 unsigned long npages = 1ul << PAGE_1G_ORDER; 2771 unsigned long size = npages * PAGE_SIZE; 2772 unsigned long *page_table = current_page_table(); 2773 unsigned long pte; 2774 2775 if (setup_ept(false)) 2776 test_skip("EPT not supported"); 2777 2778 /* We use data->gpa = 1 << 39 so that test data has a separate pml4 entry */ 2779 if (cpuid_maxphyaddr() < 40) 2780 test_skip("Test needs MAXPHYADDR >= 40"); 2781 2782 test_set_guest(ept_access_test_guest); 2783 test_add_teardown(ept_access_test_teardown, NULL); 2784 2785 data->hva = get_1g_page(); 2786 TEST_ASSERT(data->hva); 2787 data->hpa = virt_to_phys(data->hva); 2788 2789 data->gpa = 1ul << 39; 2790 data->gva = (void *) ALIGN((unsigned long) alloc_vpages(npages * 2), 2791 size); 2792 TEST_ASSERT(!any_present_pages(page_table, data->gva, size)); 2793 install_pages(page_table, data->gpa, size, data->gva); 2794 2795 /* 2796 * Make sure nothing's mapped here so the tests that screw with the 2797 * pml4 entry don't inadvertently break something. 2798 */ 2799 TEST_ASSERT(get_ept_pte(pml4, data->gpa, 4, &pte) && pte == 0); 2800 TEST_ASSERT(get_ept_pte(pml4, data->gpa + size - 1, 4, &pte) && pte == 0); 2801 install_ept(pml4, data->hpa, data->gpa, EPT_PRESENT); 2802 2803 data->hva[0] = MAGIC_VAL_1; 2804 memcpy(&data->hva[1], &ret42_start, &ret42_end - &ret42_start); 2805 } 2806 2807 static void ept_access_test_not_present(void) 2808 { 2809 ept_access_test_setup(); 2810 /* --- */ 2811 ept_access_violation(0, OP_READ, EPT_VLT_RD); 2812 ept_access_violation(0, OP_WRITE, EPT_VLT_WR); 2813 ept_access_violation(0, OP_EXEC, EPT_VLT_FETCH); 2814 } 2815 2816 static void ept_access_test_read_only(void) 2817 { 2818 ept_access_test_setup(); 2819 2820 /* r-- */ 2821 ept_access_allowed(EPT_RA, OP_READ); 2822 ept_access_violation(EPT_RA, OP_WRITE, EPT_VLT_WR | EPT_VLT_PERM_RD); 2823 ept_access_violation(EPT_RA, OP_EXEC, EPT_VLT_FETCH | EPT_VLT_PERM_RD); 2824 } 2825 2826 static void ept_access_test_write_only(void) 2827 { 2828 ept_access_test_setup(); 2829 /* -w- */ 2830 ept_access_misconfig(EPT_WA); 2831 } 2832 2833 static void ept_access_test_read_write(void) 2834 { 2835 ept_access_test_setup(); 2836 /* rw- */ 2837 ept_access_allowed(EPT_RA | EPT_WA, OP_READ); 2838 ept_access_allowed(EPT_RA | EPT_WA, OP_WRITE); 2839 ept_access_violation(EPT_RA | EPT_WA, OP_EXEC, 2840 EPT_VLT_FETCH | EPT_VLT_PERM_RD | EPT_VLT_PERM_WR); 2841 } 2842 2843 2844 static void ept_access_test_execute_only(void) 2845 { 2846 ept_access_test_setup(); 2847 /* --x */ 2848 if (ept_execute_only_supported()) { 2849 ept_access_violation(EPT_EA, OP_READ, 2850 EPT_VLT_RD | EPT_VLT_PERM_EX); 2851 ept_access_violation(EPT_EA, OP_WRITE, 2852 EPT_VLT_WR | EPT_VLT_PERM_EX); 2853 ept_access_allowed(EPT_EA, OP_EXEC); 2854 } else { 2855 ept_access_misconfig(EPT_EA); 2856 } 2857 } 2858 2859 static void ept_access_test_read_execute(void) 2860 { 2861 ept_access_test_setup(); 2862 /* r-x */ 2863 ept_access_allowed(EPT_RA | EPT_EA, OP_READ); 2864 ept_access_violation(EPT_RA | EPT_EA, OP_WRITE, 2865 EPT_VLT_WR | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX); 2866 ept_access_allowed(EPT_RA | EPT_EA, OP_EXEC); 2867 } 2868 2869 static void ept_access_test_write_execute(void) 2870 { 2871 ept_access_test_setup(); 2872 /* -wx */ 2873 ept_access_misconfig(EPT_WA | EPT_EA); 2874 } 2875 2876 static void ept_access_test_read_write_execute(void) 2877 { 2878 ept_access_test_setup(); 2879 /* rwx */ 2880 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_READ); 2881 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_WRITE); 2882 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_EXEC); 2883 } 2884 2885 static void ept_access_test_reserved_bits(void) 2886 { 2887 int i; 2888 int maxphyaddr; 2889 2890 ept_access_test_setup(); 2891 2892 /* Reserved bits above maxphyaddr. */ 2893 maxphyaddr = cpuid_maxphyaddr(); 2894 for (i = maxphyaddr; i <= 51; i++) { 2895 report_prefix_pushf("reserved_bit=%d", i); 2896 ept_reserved_bit(i); 2897 report_prefix_pop(); 2898 } 2899 2900 /* Level-specific reserved bits. */ 2901 ept_reserved_bit_at_level_nohuge(2, 3); 2902 ept_reserved_bit_at_level_nohuge(2, 4); 2903 ept_reserved_bit_at_level_nohuge(2, 5); 2904 ept_reserved_bit_at_level_nohuge(2, 6); 2905 /* 2M alignment. */ 2906 for (i = 12; i < 20; i++) { 2907 report_prefix_pushf("reserved_bit=%d", i); 2908 ept_reserved_bit_at_level_huge(2, i); 2909 report_prefix_pop(); 2910 } 2911 ept_reserved_bit_at_level_nohuge(3, 3); 2912 ept_reserved_bit_at_level_nohuge(3, 4); 2913 ept_reserved_bit_at_level_nohuge(3, 5); 2914 ept_reserved_bit_at_level_nohuge(3, 6); 2915 /* 1G alignment. */ 2916 for (i = 12; i < 29; i++) { 2917 report_prefix_pushf("reserved_bit=%d", i); 2918 ept_reserved_bit_at_level_huge(3, i); 2919 report_prefix_pop(); 2920 } 2921 ept_reserved_bit_at_level(4, 3); 2922 ept_reserved_bit_at_level(4, 4); 2923 ept_reserved_bit_at_level(4, 5); 2924 ept_reserved_bit_at_level(4, 6); 2925 ept_reserved_bit_at_level(4, 7); 2926 } 2927 2928 static void ept_access_test_ignored_bits(void) 2929 { 2930 ept_access_test_setup(); 2931 /* 2932 * Bits ignored at every level. Bits 8 and 9 (A and D) are ignored as 2933 * far as translation is concerned even if AD bits are enabled in the 2934 * EPTP. Bit 63 is ignored because "EPT-violation #VE" VM-execution 2935 * control is 0. 2936 */ 2937 ept_ignored_bit(8); 2938 ept_ignored_bit(9); 2939 ept_ignored_bit(10); 2940 ept_ignored_bit(11); 2941 ept_ignored_bit(52); 2942 ept_ignored_bit(53); 2943 ept_ignored_bit(54); 2944 ept_ignored_bit(55); 2945 ept_ignored_bit(56); 2946 ept_ignored_bit(57); 2947 ept_ignored_bit(58); 2948 ept_ignored_bit(59); 2949 ept_ignored_bit(60); 2950 ept_ignored_bit(61); 2951 ept_ignored_bit(62); 2952 ept_ignored_bit(63); 2953 } 2954 2955 static void ept_access_test_paddr_not_present_ad_disabled(void) 2956 { 2957 ept_access_test_setup(); 2958 ept_disable_ad_bits(); 2959 2960 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, EPT_VLT_RD); 2961 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, EPT_VLT_RD); 2962 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, EPT_VLT_RD); 2963 } 2964 2965 static void ept_access_test_paddr_not_present_ad_enabled(void) 2966 { 2967 u64 qual = EPT_VLT_RD | EPT_VLT_WR; 2968 2969 ept_access_test_setup(); 2970 ept_enable_ad_bits_or_skip_test(); 2971 2972 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, qual); 2973 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, qual); 2974 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, qual); 2975 } 2976 2977 static void ept_access_test_paddr_read_only_ad_disabled(void) 2978 { 2979 /* 2980 * When EPT AD bits are disabled, all accesses to guest paging 2981 * structures are reported separately as a read and (after 2982 * translation of the GPA to host physical address) a read+write 2983 * if the A/D bits have to be set. 2984 */ 2985 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 2986 2987 ept_access_test_setup(); 2988 ept_disable_ad_bits(); 2989 2990 /* Can't update A bit, so all accesses fail. */ 2991 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 2992 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 2993 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 2994 /* AD bits disabled, so only writes try to update the D bit. */ 2995 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ); 2996 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 2997 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC); 2998 /* Both A and D already set, so read-only is OK. */ 2999 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_READ); 3000 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_WRITE); 3001 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_EXEC); 3002 } 3003 3004 static void ept_access_test_paddr_read_only_ad_enabled(void) 3005 { 3006 /* 3007 * When EPT AD bits are enabled, all accesses to guest paging 3008 * structures are considered writes as far as EPT translation 3009 * is concerned. 3010 */ 3011 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 3012 3013 ept_access_test_setup(); 3014 ept_enable_ad_bits_or_skip_test(); 3015 3016 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 3017 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 3018 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 3019 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ, qual); 3020 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 3021 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC, qual); 3022 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_READ, qual); 3023 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_WRITE, qual); 3024 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_EXEC, qual); 3025 } 3026 3027 static void ept_access_test_paddr_read_write(void) 3028 { 3029 ept_access_test_setup(); 3030 /* Read-write access to paging structure. */ 3031 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_READ); 3032 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_WRITE); 3033 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_EXEC); 3034 } 3035 3036 static void ept_access_test_paddr_read_write_execute(void) 3037 { 3038 ept_access_test_setup(); 3039 /* RWX access to paging structure. */ 3040 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_READ); 3041 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_WRITE); 3042 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_EXEC); 3043 } 3044 3045 static void ept_access_test_paddr_read_execute_ad_disabled(void) 3046 { 3047 /* 3048 * When EPT AD bits are disabled, all accesses to guest paging 3049 * structures are reported separately as a read and (after 3050 * translation of the GPA to host physical address) a read+write 3051 * if the A/D bits have to be set. 3052 */ 3053 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3054 3055 ept_access_test_setup(); 3056 ept_disable_ad_bits(); 3057 3058 /* Can't update A bit, so all accesses fail. */ 3059 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3060 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3061 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3062 /* AD bits disabled, so only writes try to update the D bit. */ 3063 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ); 3064 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3065 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC); 3066 /* Both A and D already set, so read-only is OK. */ 3067 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ); 3068 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE); 3069 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC); 3070 } 3071 3072 static void ept_access_test_paddr_read_execute_ad_enabled(void) 3073 { 3074 /* 3075 * When EPT AD bits are enabled, all accesses to guest paging 3076 * structures are considered writes as far as EPT translation 3077 * is concerned. 3078 */ 3079 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3080 3081 ept_access_test_setup(); 3082 ept_enable_ad_bits_or_skip_test(); 3083 3084 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3085 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3086 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3087 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ, qual); 3088 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3089 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC, qual); 3090 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ, qual); 3091 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE, qual); 3092 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC, qual); 3093 } 3094 3095 static void ept_access_test_paddr_not_present_page_fault(void) 3096 { 3097 ept_access_test_setup(); 3098 /* 3099 * TODO: test no EPT violation as long as guest PF occurs. e.g., GPA is 3100 * page is read-only in EPT but GVA is also mapped read only in PT. 3101 * Thus guest page fault before host takes EPT violation for trying to 3102 * update A bit. 3103 */ 3104 } 3105 3106 static void ept_access_test_force_2m_page(void) 3107 { 3108 ept_access_test_setup(); 3109 3110 TEST_ASSERT_EQ(ept_2m_supported(), true); 3111 ept_allowed_at_level_mkhuge(true, 2, 0, 0, OP_READ); 3112 ept_violation_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_RA, OP_WRITE, 3113 EPT_VLT_WR | EPT_VLT_PERM_RD | 3114 EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 3115 ept_misconfig_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_WA); 3116 } 3117 3118 static bool invvpid_valid(u64 type, u64 vpid, u64 gla) 3119 { 3120 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3121 3122 TEST_ASSERT(msr & VPID_CAP_INVVPID); 3123 3124 if (type < INVVPID_ADDR || type > INVVPID_CONTEXT_LOCAL) 3125 return false; 3126 3127 if (!(msr & (1ull << (type + VPID_CAP_INVVPID_TYPES_SHIFT)))) 3128 return false; 3129 3130 if (vpid >> 16) 3131 return false; 3132 3133 if (type != INVVPID_ALL && !vpid) 3134 return false; 3135 3136 if (type == INVVPID_ADDR && !is_canonical(gla)) 3137 return false; 3138 3139 return true; 3140 } 3141 3142 static void try_invvpid(u64 type, u64 vpid, u64 gla) 3143 { 3144 int rc; 3145 bool valid = invvpid_valid(type, vpid, gla); 3146 u64 expected = valid ? VMXERR_UNSUPPORTED_VMCS_COMPONENT 3147 : VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID; 3148 /* 3149 * Set VMX_INST_ERROR to VMXERR_UNVALID_VMCS_COMPONENT, so 3150 * that we can tell if it is updated by INVVPID. 3151 */ 3152 vmcs_read(~0); 3153 rc = invvpid(type, vpid, gla); 3154 report("INVVPID type %ld VPID %lx GLA %lx %s", 3155 !rc == valid, type, vpid, gla, 3156 valid ? "passes" : "fails"); 3157 report("After %s INVVPID, VMX_INST_ERR is %ld (actual %ld)", 3158 vmcs_read(VMX_INST_ERROR) == expected, 3159 rc ? "failed" : "successful", 3160 expected, vmcs_read(VMX_INST_ERROR)); 3161 } 3162 3163 static void ds_invvpid(void *data) 3164 { 3165 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3166 u64 type = ffs(msr >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 3167 3168 TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 3169 asm volatile("invvpid %0, %1" 3170 : 3171 : "m"(*(struct invvpid_operand *)data), 3172 "r"(type)); 3173 } 3174 3175 /* 3176 * The SS override is ignored in 64-bit mode, so we use an addressing 3177 * mode with %rsp as the base register to generate an implicit SS 3178 * reference. 3179 */ 3180 static void ss_invvpid(void *data) 3181 { 3182 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3183 u64 type = ffs(msr >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 3184 3185 TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 3186 asm volatile("sub %%rsp,%0; invvpid (%%rsp,%0,1), %1" 3187 : "+r"(data) 3188 : "r"(type)); 3189 } 3190 3191 static void invvpid_test_gp(void) 3192 { 3193 bool fault; 3194 3195 fault = test_for_exception(GP_VECTOR, &ds_invvpid, 3196 (void *)NONCANONICAL); 3197 report("INVVPID with non-canonical DS operand raises #GP", fault); 3198 } 3199 3200 static void invvpid_test_ss(void) 3201 { 3202 bool fault; 3203 3204 fault = test_for_exception(SS_VECTOR, &ss_invvpid, 3205 (void *)NONCANONICAL); 3206 report("INVVPID with non-canonical SS operand raises #SS", fault); 3207 } 3208 3209 static void invvpid_test_pf(void) 3210 { 3211 void *vpage = alloc_vpage(); 3212 bool fault; 3213 3214 fault = test_for_exception(PF_VECTOR, &ds_invvpid, vpage); 3215 report("INVVPID with unmapped operand raises #PF", fault); 3216 } 3217 3218 static void try_compat_invvpid(void *unused) 3219 { 3220 struct far_pointer32 fp = { 3221 .offset = (uintptr_t)&&invvpid, 3222 .selector = KERNEL_CS32, 3223 }; 3224 register uintptr_t rsp asm("rsp"); 3225 3226 TEST_ASSERT_MSG(fp.offset == (uintptr_t)&&invvpid, 3227 "Code address too high."); 3228 TEST_ASSERT_MSG(rsp == (u32)rsp, "Stack address too high."); 3229 3230 asm goto ("lcall *%0" : : "m" (fp) : "rax" : invvpid); 3231 return; 3232 invvpid: 3233 asm volatile (".code32;" 3234 "invvpid (%eax), %eax;" 3235 "lret;" 3236 ".code64"); 3237 __builtin_unreachable(); 3238 } 3239 3240 static void invvpid_test_compatibility_mode(void) 3241 { 3242 bool fault; 3243 3244 fault = test_for_exception(UD_VECTOR, &try_compat_invvpid, NULL); 3245 report("Compatibility mode INVVPID raises #UD", fault); 3246 } 3247 3248 static void invvpid_test_not_in_vmx_operation(void) 3249 { 3250 bool fault; 3251 3252 TEST_ASSERT(!vmx_off()); 3253 fault = test_for_exception(UD_VECTOR, &ds_invvpid, NULL); 3254 report("INVVPID outside of VMX operation raises #UD", fault); 3255 TEST_ASSERT(!vmx_on()); 3256 } 3257 3258 /* 3259 * This does not test real-address mode, virtual-8086 mode, protected mode, 3260 * or CPL > 0. 3261 */ 3262 static void invvpid_test_v2(void) 3263 { 3264 u64 msr; 3265 int i; 3266 unsigned types = 0; 3267 unsigned type; 3268 3269 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 3270 !(ctrl_cpu_rev[1].clr & CPU_VPID)) 3271 test_skip("VPID not supported"); 3272 3273 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3274 3275 if (!(msr & VPID_CAP_INVVPID)) 3276 test_skip("INVVPID not supported.\n"); 3277 3278 if (msr & VPID_CAP_INVVPID_ADDR) 3279 types |= 1u << INVVPID_ADDR; 3280 if (msr & VPID_CAP_INVVPID_CXTGLB) 3281 types |= 1u << INVVPID_CONTEXT_GLOBAL; 3282 if (msr & VPID_CAP_INVVPID_ALL) 3283 types |= 1u << INVVPID_ALL; 3284 if (msr & VPID_CAP_INVVPID_CXTLOC) 3285 types |= 1u << INVVPID_CONTEXT_LOCAL; 3286 3287 if (!types) 3288 test_skip("No INVVPID types supported.\n"); 3289 3290 for (i = -127; i < 128; i++) 3291 try_invvpid(i, 0xffff, 0); 3292 3293 /* 3294 * VPID must not be more than 16 bits. 3295 */ 3296 for (i = 0; i < 64; i++) 3297 for (type = 0; type < 4; type++) 3298 if (types & (1u << type)) 3299 try_invvpid(type, 1ul << i, 0); 3300 3301 /* 3302 * VPID must not be zero, except for "all contexts." 3303 */ 3304 for (type = 0; type < 4; type++) 3305 if (types & (1u << type)) 3306 try_invvpid(type, 0, 0); 3307 3308 /* 3309 * The gla operand is only validated for single-address INVVPID. 3310 */ 3311 if (types & (1u << INVVPID_ADDR)) 3312 try_invvpid(INVVPID_ADDR, 0xffff, NONCANONICAL); 3313 3314 invvpid_test_gp(); 3315 invvpid_test_ss(); 3316 invvpid_test_pf(); 3317 invvpid_test_compatibility_mode(); 3318 invvpid_test_not_in_vmx_operation(); 3319 } 3320 3321 /* 3322 * Test for early VMLAUNCH failure. Returns true if VMLAUNCH makes it 3323 * at least as far as the guest-state checks. Returns false if the 3324 * VMLAUNCH fails early and execution falls through to the next 3325 * instruction. 3326 */ 3327 static bool vmlaunch_succeeds(void) 3328 { 3329 u32 exit_reason; 3330 3331 /* 3332 * Indirectly set VMX_INST_ERR to 12 ("VMREAD/VMWRITE from/to 3333 * unsupported VMCS component"). The caller can then check 3334 * to see if a failed VM-entry sets VMX_INST_ERR as expected. 3335 */ 3336 vmcs_write(~0u, 0); 3337 3338 vmcs_write(HOST_RIP, (uintptr_t)&&success); 3339 __asm__ __volatile__ goto ("vmwrite %%rsp, %0; vmlaunch" 3340 : 3341 : "r" ((u64)HOST_RSP) 3342 : "cc", "memory" 3343 : success); 3344 return false; 3345 success: 3346 exit_reason = vmcs_read(EXI_REASON); 3347 TEST_ASSERT(exit_reason == (VMX_FAIL_STATE | VMX_ENTRY_FAILURE) || 3348 exit_reason == (VMX_FAIL_MSR | VMX_ENTRY_FAILURE)); 3349 return true; 3350 } 3351 3352 /* 3353 * Try to launch the current VMCS. 3354 */ 3355 static void test_vmx_vmlaunch(u32 xerror, bool xfail) 3356 { 3357 bool success = vmlaunch_succeeds(); 3358 u32 vmx_inst_err; 3359 3360 report_xfail("vmlaunch %s", xfail, success == !xerror, 3361 !xerror ? "succeeds" : "fails"); 3362 if (!success && xerror) { 3363 vmx_inst_err = vmcs_read(VMX_INST_ERROR); 3364 report("VMX inst error is %d (actual %d)", 3365 vmx_inst_err == xerror, xerror, vmx_inst_err); 3366 } 3367 } 3368 3369 static void test_vmx_invalid_controls(bool xfail) 3370 { 3371 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_CONTROL_FIELD, xfail); 3372 } 3373 3374 static void test_vmx_valid_controls(bool xfail) 3375 { 3376 test_vmx_vmlaunch(0, xfail); 3377 } 3378 3379 /* 3380 * Test a particular value of a VM-execution control bit, if the value 3381 * is required or if the value is zero. 3382 */ 3383 static void test_rsvd_ctl_bit_value(const char *name, union vmx_ctrl_msr msr, 3384 enum Encoding encoding, unsigned bit, 3385 unsigned val) 3386 { 3387 u32 mask = 1u << bit; 3388 bool expected; 3389 u32 controls; 3390 3391 if (msr.set & mask) 3392 TEST_ASSERT(msr.clr & mask); 3393 3394 /* 3395 * We can't arbitrarily turn on a control bit, because it may 3396 * introduce dependencies on other VMCS fields. So, we only 3397 * test turning on bits that have a required setting. 3398 */ 3399 if (val && (msr.clr & mask) && !(msr.set & mask)) 3400 return; 3401 3402 report_prefix_pushf("%s %s bit %d", 3403 val ? "Set" : "Clear", name, bit); 3404 3405 controls = vmcs_read(encoding); 3406 if (val) { 3407 vmcs_write(encoding, msr.set | mask); 3408 expected = (msr.clr & mask); 3409 } else { 3410 vmcs_write(encoding, msr.set & ~mask); 3411 expected = !(msr.set & mask); 3412 } 3413 if (expected) 3414 test_vmx_valid_controls(false); 3415 else 3416 test_vmx_invalid_controls(false); 3417 vmcs_write(encoding, controls); 3418 report_prefix_pop(); 3419 } 3420 3421 /* 3422 * Test reserved values of a VM-execution control bit, based on the 3423 * allowed bit settings from the corresponding VMX capability MSR. 3424 */ 3425 static void test_rsvd_ctl_bit(const char *name, union vmx_ctrl_msr msr, 3426 enum Encoding encoding, unsigned bit) 3427 { 3428 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 0); 3429 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 1); 3430 } 3431 3432 /* 3433 * Reserved bits in the pin-based VM-execution controls must be set 3434 * properly. Software may consult the VMX capability MSRs to determine 3435 * the proper settings. 3436 * [Intel SDM] 3437 */ 3438 static void test_pin_based_ctls(void) 3439 { 3440 unsigned bit; 3441 3442 printf("%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PIN" : 3443 "MSR_IA32_VMX_PINBASED_CTLS", ctrl_pin_rev.val); 3444 for (bit = 0; bit < 32; bit++) 3445 test_rsvd_ctl_bit("pin-based controls", 3446 ctrl_pin_rev, PIN_CONTROLS, bit); 3447 } 3448 3449 /* 3450 * Reserved bits in the primary processor-based VM-execution controls 3451 * must be set properly. Software may consult the VMX capability MSRs 3452 * to determine the proper settings. 3453 * [Intel SDM] 3454 */ 3455 static void test_primary_processor_based_ctls(void) 3456 { 3457 unsigned bit; 3458 3459 printf("\n%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PROC" : 3460 "MSR_IA32_VMX_PROCBASED_CTLS", ctrl_cpu_rev[0].val); 3461 for (bit = 0; bit < 32; bit++) 3462 test_rsvd_ctl_bit("primary processor-based controls", 3463 ctrl_cpu_rev[0], CPU_EXEC_CTRL0, bit); 3464 } 3465 3466 /* 3467 * If the "activate secondary controls" primary processor-based 3468 * VM-execution control is 1, reserved bits in the secondary 3469 * processor-based VM-execution controls must be cleared. Software may 3470 * consult the VMX capability MSRs to determine which bits are 3471 * reserved. 3472 * If the "activate secondary controls" primary processor-based 3473 * VM-execution control is 0 (or if the processor does not support the 3474 * 1-setting of that control), no checks are performed on the 3475 * secondary processor-based VM-execution controls. 3476 * [Intel SDM] 3477 */ 3478 static void test_secondary_processor_based_ctls(void) 3479 { 3480 u32 primary; 3481 u32 secondary; 3482 unsigned bit; 3483 3484 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) 3485 return; 3486 3487 primary = vmcs_read(CPU_EXEC_CTRL0); 3488 secondary = vmcs_read(CPU_EXEC_CTRL1); 3489 3490 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3491 printf("\nMSR_IA32_VMX_PROCBASED_CTLS2: %lx\n", ctrl_cpu_rev[1].val); 3492 for (bit = 0; bit < 32; bit++) 3493 test_rsvd_ctl_bit("secondary processor-based controls", 3494 ctrl_cpu_rev[1], CPU_EXEC_CTRL1, bit); 3495 3496 /* 3497 * When the "activate secondary controls" VM-execution control 3498 * is clear, there are no checks on the secondary controls. 3499 */ 3500 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3501 vmcs_write(CPU_EXEC_CTRL1, ~0); 3502 report("Secondary processor-based controls ignored", 3503 vmlaunch_succeeds()); 3504 vmcs_write(CPU_EXEC_CTRL1, secondary); 3505 vmcs_write(CPU_EXEC_CTRL0, primary); 3506 } 3507 3508 static void try_cr3_target_count(unsigned i, unsigned max) 3509 { 3510 report_prefix_pushf("CR3 target count 0x%x", i); 3511 vmcs_write(CR3_TARGET_COUNT, i); 3512 if (i <= max) 3513 test_vmx_valid_controls(false); 3514 else 3515 test_vmx_invalid_controls(false); 3516 report_prefix_pop(); 3517 } 3518 3519 /* 3520 * The CR3-target count must not be greater than 4. Future processors 3521 * may support a different number of CR3-target values. Software 3522 * should read the VMX capability MSR IA32_VMX_MISC to determine the 3523 * number of values supported. 3524 * [Intel SDM] 3525 */ 3526 static void test_cr3_targets(void) 3527 { 3528 unsigned supported_targets = (rdmsr(MSR_IA32_VMX_MISC) >> 16) & 0x1ff; 3529 u32 cr3_targets = vmcs_read(CR3_TARGET_COUNT); 3530 unsigned i; 3531 3532 printf("\nSupported CR3 targets: %d\n", supported_targets); 3533 TEST_ASSERT(supported_targets <= 256); 3534 3535 try_cr3_target_count(-1u, supported_targets); 3536 try_cr3_target_count(0x80000000, supported_targets); 3537 try_cr3_target_count(0x7fffffff, supported_targets); 3538 for (i = 0; i <= supported_targets + 1; i++) 3539 try_cr3_target_count(i, supported_targets); 3540 vmcs_write(CR3_TARGET_COUNT, cr3_targets); 3541 } 3542 3543 /* 3544 * Test a particular address setting in the VMCS 3545 */ 3546 static void test_vmcs_addr(const char *name, 3547 enum Encoding encoding, 3548 u64 align, 3549 bool ignored, 3550 bool xfail_beyond_mapped_ram, 3551 u64 addr) 3552 { 3553 bool xfail = 3554 (xfail_beyond_mapped_ram && 3555 addr > fwcfg_get_u64(FW_CFG_RAM_SIZE) - align && 3556 addr < (1ul << cpuid_maxphyaddr())); 3557 3558 report_prefix_pushf("%s = %lx", name, addr); 3559 vmcs_write(encoding, addr); 3560 if (ignored || (IS_ALIGNED(addr, align) && 3561 addr < (1ul << cpuid_maxphyaddr()))) 3562 test_vmx_valid_controls(xfail); 3563 else 3564 test_vmx_invalid_controls(xfail); 3565 report_prefix_pop(); 3566 xfail = false; 3567 } 3568 3569 /* 3570 * Test interesting values for a VMCS address 3571 */ 3572 static void test_vmcs_addr_values(const char *name, 3573 enum Encoding encoding, 3574 u64 align, 3575 bool ignored, 3576 bool xfail_beyond_mapped_ram, 3577 u32 bit_start, u32 bit_end) 3578 { 3579 unsigned i; 3580 u64 orig_val = vmcs_read(encoding); 3581 3582 for (i = bit_start; i <= bit_end; i++) 3583 test_vmcs_addr(name, encoding, align, ignored, 3584 xfail_beyond_mapped_ram, 1ul << i); 3585 3586 test_vmcs_addr(name, encoding, align, ignored, 3587 xfail_beyond_mapped_ram, PAGE_SIZE - 1); 3588 test_vmcs_addr(name, encoding, align, ignored, 3589 xfail_beyond_mapped_ram, PAGE_SIZE); 3590 test_vmcs_addr(name, encoding, align, ignored, 3591 xfail_beyond_mapped_ram, 3592 (1ul << cpuid_maxphyaddr()) - PAGE_SIZE); 3593 test_vmcs_addr(name, encoding, align, ignored, 3594 xfail_beyond_mapped_ram, -1ul); 3595 3596 vmcs_write(encoding, orig_val); 3597 } 3598 3599 /* 3600 * Test a physical address reference in the VMCS, when the corresponding 3601 * feature is enabled and when the corresponding feature is disabled. 3602 */ 3603 static void test_vmcs_addr_reference(u32 control_bit, enum Encoding field, 3604 const char *field_name, 3605 const char *control_name, u64 align, 3606 bool xfail_beyond_mapped_ram, 3607 bool control_primary) 3608 { 3609 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 3610 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 3611 u64 page_addr; 3612 3613 if (control_primary) { 3614 if (!(ctrl_cpu_rev[0].clr & control_bit)) 3615 return; 3616 } else { 3617 if (!(ctrl_cpu_rev[1].clr & control_bit)) 3618 return; 3619 } 3620 3621 page_addr = vmcs_read(field); 3622 3623 report_prefix_pushf("%s enabled", control_name); 3624 if (control_primary) { 3625 vmcs_write(CPU_EXEC_CTRL0, primary | control_bit); 3626 } else { 3627 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3628 vmcs_write(CPU_EXEC_CTRL1, secondary | control_bit); 3629 } 3630 3631 test_vmcs_addr_values(field_name, field, align, false, 3632 xfail_beyond_mapped_ram, 0, 63); 3633 report_prefix_pop(); 3634 3635 report_prefix_pushf("%s disabled", control_name); 3636 if (control_primary) { 3637 vmcs_write(CPU_EXEC_CTRL0, primary & ~control_bit); 3638 } else { 3639 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3640 vmcs_write(CPU_EXEC_CTRL1, secondary & ~control_bit); 3641 } 3642 3643 test_vmcs_addr_values(field_name, field, align, true, false, 0, 63); 3644 report_prefix_pop(); 3645 3646 vmcs_write(field, page_addr); 3647 vmcs_write(CPU_EXEC_CTRL0, primary); 3648 vmcs_write(CPU_EXEC_CTRL1, secondary); 3649 } 3650 3651 /* 3652 * If the "use I/O bitmaps" VM-execution control is 1, bits 11:0 of 3653 * each I/O-bitmap address must be 0. Neither address should set any 3654 * bits beyond the processor's physical-address width. 3655 * [Intel SDM] 3656 */ 3657 static void test_io_bitmaps(void) 3658 { 3659 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_A, 3660 "I/O bitmap A", "Use I/O bitmaps", 3661 PAGE_SIZE, false, true); 3662 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_B, 3663 "I/O bitmap B", "Use I/O bitmaps", 3664 PAGE_SIZE, false, true); 3665 } 3666 3667 /* 3668 * If the "use MSR bitmaps" VM-execution control is 1, bits 11:0 of 3669 * the MSR-bitmap address must be 0. The address should not set any 3670 * bits beyond the processor's physical-address width. 3671 * [Intel SDM] 3672 */ 3673 static void test_msr_bitmap(void) 3674 { 3675 test_vmcs_addr_reference(CPU_MSR_BITMAP, MSR_BITMAP, 3676 "MSR bitmap", "Use MSR bitmaps", 3677 PAGE_SIZE, false, true); 3678 } 3679 3680 /* 3681 * If the "use TPR shadow" VM-execution control is 1, the virtual-APIC 3682 * address must satisfy the following checks: 3683 * - Bits 11:0 of the address must be 0. 3684 * - The address should not set any bits beyond the processor's 3685 * physical-address width. 3686 * [Intel SDM] 3687 */ 3688 static void test_apic_virt_addr(void) 3689 { 3690 /* 3691 * Ensure the processor will never use the virtual-APIC page, since 3692 * we will point it to invalid RAM. Otherwise KVM is puzzled about 3693 * what we're trying to achieve and fails vmentry. 3694 */ 3695 u32 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 3696 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0 | CPU_CR8_LOAD | CPU_CR8_STORE); 3697 test_vmcs_addr_reference(CPU_TPR_SHADOW, APIC_VIRT_ADDR, 3698 "virtual-APIC address", "Use TPR shadow", 3699 PAGE_SIZE, false, true); 3700 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 3701 } 3702 3703 /* 3704 * If the "virtualize APIC-accesses" VM-execution control is 1, the 3705 * APIC-access address must satisfy the following checks: 3706 * - Bits 11:0 of the address must be 0. 3707 * - The address should not set any bits beyond the processor's 3708 * physical-address width. 3709 * [Intel SDM] 3710 */ 3711 static void test_apic_access_addr(void) 3712 { 3713 void *apic_access_page = alloc_page(); 3714 3715 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_page)); 3716 3717 test_vmcs_addr_reference(CPU_VIRT_APIC_ACCESSES, APIC_ACCS_ADDR, 3718 "APIC-access address", 3719 "virtualize APIC-accesses", PAGE_SIZE, 3720 false, false); 3721 } 3722 3723 static bool set_bit_pattern(u8 mask, u32 *secondary) 3724 { 3725 u8 i; 3726 bool flag = false; 3727 u32 test_bits[3] = { 3728 CPU_VIRT_X2APIC, 3729 CPU_APIC_REG_VIRT, 3730 CPU_VINTD 3731 }; 3732 3733 for (i = 0; i < ARRAY_SIZE(test_bits); i++) { 3734 if ((mask & (1u << i)) && 3735 (ctrl_cpu_rev[1].clr & test_bits[i])) { 3736 *secondary |= test_bits[i]; 3737 flag = true; 3738 } 3739 } 3740 3741 return (flag); 3742 } 3743 3744 /* 3745 * If the "use TPR shadow" VM-execution control is 0, the following 3746 * VM-execution controls must also be 0: 3747 * - virtualize x2APIC mode 3748 * - APIC-register virtualization 3749 * - virtual-interrupt delivery 3750 * [Intel SDM] 3751 * 3752 * 2. If the "virtualize x2APIC mode" VM-execution control is 1, the 3753 * "virtualize APIC accesses" VM-execution control must be 0. 3754 * [Intel SDM] 3755 */ 3756 static void test_apic_virtual_ctls(void) 3757 { 3758 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3759 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3760 u32 primary = saved_primary; 3761 u32 secondary = saved_secondary; 3762 bool ctrl = false; 3763 char str[10] = "disabled"; 3764 u8 i = 0, j; 3765 3766 /* 3767 * First test 3768 */ 3769 if (!((ctrl_cpu_rev[0].clr & (CPU_SECONDARY | CPU_TPR_SHADOW)) == 3770 (CPU_SECONDARY | CPU_TPR_SHADOW))) 3771 return; 3772 3773 primary |= CPU_SECONDARY; 3774 primary &= ~CPU_TPR_SHADOW; 3775 vmcs_write(CPU_EXEC_CTRL0, primary); 3776 3777 while (1) { 3778 for (j = 1; j < 8; j++) { 3779 secondary &= ~(CPU_VIRT_X2APIC | CPU_APIC_REG_VIRT | CPU_VINTD); 3780 if (primary & CPU_TPR_SHADOW) { 3781 ctrl = true; 3782 } else { 3783 if (! set_bit_pattern(j, &secondary)) 3784 ctrl = true; 3785 else 3786 ctrl = false; 3787 } 3788 3789 vmcs_write(CPU_EXEC_CTRL1, secondary); 3790 report_prefix_pushf("Use TPR shadow %s, virtualize x2APIC mode %s, APIC-register virtualization %s, virtual-interrupt delivery %s", 3791 str, (secondary & CPU_VIRT_X2APIC) ? "enabled" : "disabled", (secondary & CPU_APIC_REG_VIRT) ? "enabled" : "disabled", (secondary & CPU_VINTD) ? "enabled" : "disabled"); 3792 if (ctrl) 3793 test_vmx_valid_controls(false); 3794 else 3795 test_vmx_invalid_controls(false); 3796 report_prefix_pop(); 3797 } 3798 3799 if (i == 1) 3800 break; 3801 i++; 3802 3803 primary |= CPU_TPR_SHADOW; 3804 vmcs_write(CPU_EXEC_CTRL0, primary); 3805 strcpy(str, "enabled"); 3806 } 3807 3808 /* 3809 * Second test 3810 */ 3811 u32 apic_virt_ctls = (CPU_VIRT_X2APIC | CPU_VIRT_APIC_ACCESSES); 3812 3813 primary = saved_primary; 3814 secondary = saved_secondary; 3815 if (!((ctrl_cpu_rev[1].clr & apic_virt_ctls) == apic_virt_ctls)) 3816 return; 3817 3818 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3819 secondary &= ~CPU_VIRT_APIC_ACCESSES; 3820 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_X2APIC); 3821 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access disabled"); 3822 test_vmx_valid_controls(false); 3823 report_prefix_pop(); 3824 3825 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_APIC_ACCESSES); 3826 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access enabled"); 3827 test_vmx_valid_controls(false); 3828 report_prefix_pop(); 3829 3830 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_X2APIC); 3831 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access enabled"); 3832 test_vmx_invalid_controls(false); 3833 report_prefix_pop(); 3834 3835 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_APIC_ACCESSES); 3836 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access disabled"); 3837 test_vmx_valid_controls(false); 3838 report_prefix_pop(); 3839 3840 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3841 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3842 } 3843 3844 /* 3845 * If the "virtual-interrupt delivery" VM-execution control is 1, the 3846 * "external-interrupt exiting" VM-execution control must be 1. 3847 * [Intel SDM] 3848 */ 3849 static void test_virtual_intr_ctls(void) 3850 { 3851 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3852 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3853 u32 saved_pin = vmcs_read(PIN_CONTROLS); 3854 u32 primary = saved_primary; 3855 u32 secondary = saved_secondary; 3856 u32 pin = saved_pin; 3857 3858 if (!((ctrl_cpu_rev[1].clr & CPU_VINTD) && 3859 (ctrl_pin_rev.clr & PIN_EXTINT))) 3860 return; 3861 3862 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 3863 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VINTD); 3864 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 3865 report_prefix_pushf("Virtualize interrupt-delivery disabled; external-interrupt exiting disabled"); 3866 test_vmx_valid_controls(false); 3867 report_prefix_pop(); 3868 3869 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VINTD); 3870 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 3871 test_vmx_invalid_controls(false); 3872 report_prefix_pop(); 3873 3874 vmcs_write(PIN_CONTROLS, pin | PIN_EXTINT); 3875 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting enabled"); 3876 test_vmx_valid_controls(false); 3877 report_prefix_pop(); 3878 3879 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 3880 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 3881 test_vmx_invalid_controls(false); 3882 report_prefix_pop(); 3883 3884 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3885 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3886 vmcs_write(PIN_CONTROLS, saved_pin); 3887 } 3888 3889 static void test_pi_desc_addr(u64 addr, bool ctrl) 3890 { 3891 vmcs_write(POSTED_INTR_DESC_ADDR, addr); 3892 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-descriptor-address 0x%lx", addr); 3893 if (ctrl) 3894 test_vmx_valid_controls(false); 3895 else 3896 test_vmx_invalid_controls(false); 3897 report_prefix_pop(); 3898 } 3899 3900 /* 3901 * If the “process posted interrupts†VM-execution control is 1, the 3902 * following must be true: 3903 * 3904 * - The “virtual-interrupt delivery†VM-execution control is 1. 3905 * - The “acknowledge interrupt on exit†VM-exit control is 1. 3906 * - The posted-interrupt notification vector has a value in the 3907 * - range 0–255 (bits 15:8 are all 0). 3908 * - Bits 5:0 of the posted-interrupt descriptor address are all 0. 3909 * - The posted-interrupt descriptor address does not set any bits 3910 * beyond the processor's physical-address width. 3911 * [Intel SDM] 3912 */ 3913 static void test_posted_intr(void) 3914 { 3915 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3916 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3917 u32 saved_pin = vmcs_read(PIN_CONTROLS); 3918 u32 exit_ctl_saved = vmcs_read(EXI_CONTROLS); 3919 u32 primary = saved_primary; 3920 u32 secondary = saved_secondary; 3921 u32 pin = saved_pin; 3922 u32 exit_ctl = exit_ctl_saved; 3923 u16 vec; 3924 int i; 3925 3926 if (!((ctrl_pin_rev.clr & PIN_POST_INTR) && 3927 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 3928 (ctrl_exit_rev.clr & EXI_INTA))) 3929 return; 3930 3931 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 3932 3933 /* 3934 * Test virtual-interrupt-delivery and acknowledge-interrupt-on-exit 3935 */ 3936 pin |= PIN_POST_INTR; 3937 vmcs_write(PIN_CONTROLS, pin); 3938 secondary &= ~CPU_VINTD; 3939 vmcs_write(CPU_EXEC_CTRL1, secondary); 3940 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled"); 3941 test_vmx_invalid_controls(false); 3942 report_prefix_pop(); 3943 3944 secondary |= CPU_VINTD; 3945 vmcs_write(CPU_EXEC_CTRL1, secondary); 3946 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled"); 3947 test_vmx_invalid_controls(false); 3948 report_prefix_pop(); 3949 3950 exit_ctl &= ~EXI_INTA; 3951 vmcs_write(EXI_CONTROLS, exit_ctl); 3952 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit disabled"); 3953 test_vmx_invalid_controls(false); 3954 report_prefix_pop(); 3955 3956 exit_ctl |= EXI_INTA; 3957 vmcs_write(EXI_CONTROLS, exit_ctl); 3958 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 3959 test_vmx_valid_controls(false); 3960 report_prefix_pop(); 3961 3962 secondary &= ~CPU_VINTD; 3963 vmcs_write(CPU_EXEC_CTRL1, secondary); 3964 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled; acknowledge-interrupt-on-exit enabled"); 3965 test_vmx_invalid_controls(false); 3966 report_prefix_pop(); 3967 3968 secondary |= CPU_VINTD; 3969 vmcs_write(CPU_EXEC_CTRL1, secondary); 3970 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 3971 test_vmx_valid_controls(false); 3972 report_prefix_pop(); 3973 3974 /* 3975 * Test posted-interrupt notification vector 3976 */ 3977 for (i = 0; i < 8; i++) { 3978 vec = (1ul << i); 3979 vmcs_write(PINV, vec); 3980 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 3981 test_vmx_valid_controls(false); 3982 report_prefix_pop(); 3983 } 3984 for (i = 8; i < 16; i++) { 3985 vec = (1ul << i); 3986 vmcs_write(PINV, vec); 3987 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 3988 test_vmx_invalid_controls(false); 3989 report_prefix_pop(); 3990 } 3991 3992 vec &= ~(0xff << 8); 3993 vmcs_write(PINV, vec); 3994 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 3995 test_vmx_valid_controls(false); 3996 report_prefix_pop(); 3997 3998 /* 3999 * Test posted-interrupt descriptor addresss 4000 */ 4001 for (i = 0; i < 6; i++) { 4002 test_pi_desc_addr(1ul << i, false); 4003 } 4004 4005 test_pi_desc_addr(0xf0, false); 4006 test_pi_desc_addr(0xff, false); 4007 test_pi_desc_addr(0x0f, false); 4008 test_pi_desc_addr(0x8000, true); 4009 test_pi_desc_addr(0x00, true); 4010 test_pi_desc_addr(0xc000, true); 4011 4012 test_vmcs_addr_values("process-posted interrupts", 4013 POSTED_INTR_DESC_ADDR, 64, 4014 false, false, 0, 63); 4015 4016 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 4017 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 4018 vmcs_write(PIN_CONTROLS, saved_pin); 4019 } 4020 4021 static void test_apic_ctls(void) 4022 { 4023 test_apic_virt_addr(); 4024 test_apic_access_addr(); 4025 test_apic_virtual_ctls(); 4026 test_virtual_intr_ctls(); 4027 test_posted_intr(); 4028 } 4029 4030 /* 4031 * If the “enable VPID†VM-execution control is 1, the value of the 4032 * of the VPID VM-execution control field must not be 0000H. 4033 * [Intel SDM] 4034 */ 4035 static void test_vpid(void) 4036 { 4037 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 4038 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 4039 u16 vpid = 0x0000; 4040 int i; 4041 4042 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4043 (ctrl_cpu_rev[1].clr & CPU_VPID))) { 4044 printf("Secondary controls and/or VPID not supported\n"); 4045 return; 4046 } 4047 4048 vmcs_write(CPU_EXEC_CTRL0, saved_primary | CPU_SECONDARY); 4049 vmcs_write(CPU_EXEC_CTRL1, saved_secondary & ~CPU_VPID); 4050 vmcs_write(VPID, vpid); 4051 report_prefix_pushf("VPID disabled; VPID value %x", vpid); 4052 test_vmx_valid_controls(false); 4053 report_prefix_pop(); 4054 4055 vmcs_write(CPU_EXEC_CTRL1, saved_secondary | CPU_VPID); 4056 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 4057 test_vmx_invalid_controls(false); 4058 report_prefix_pop(); 4059 4060 for (i = 0; i < 16; i++) { 4061 vpid = (short)1 << i;; 4062 vmcs_write(VPID, vpid); 4063 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 4064 test_vmx_valid_controls(false); 4065 report_prefix_pop(); 4066 } 4067 4068 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 4069 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 4070 } 4071 4072 static void set_vtpr(unsigned vtpr) 4073 { 4074 *(u32 *)phys_to_virt(vmcs_read(APIC_VIRT_ADDR) + APIC_TASKPRI) = vtpr; 4075 } 4076 4077 static void try_tpr_threshold_and_vtpr(unsigned threshold, unsigned vtpr) 4078 { 4079 bool valid = true; 4080 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4081 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4082 4083 if ((primary & CPU_TPR_SHADOW) && 4084 (!(primary & CPU_SECONDARY) || 4085 !(secondary & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 4086 valid = (threshold & 0xf) <= ((vtpr >> 4) & 0xf); 4087 4088 set_vtpr(vtpr); 4089 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0x%x", 4090 threshold, (vtpr >> 4) & 0xf); 4091 if (valid) 4092 test_vmx_valid_controls(false); 4093 else 4094 test_vmx_invalid_controls(false); 4095 report_prefix_pop(); 4096 } 4097 4098 static void test_invalid_event_injection(void) 4099 { 4100 u32 ent_intr_info_save = vmcs_read(ENT_INTR_INFO); 4101 u32 ent_intr_error_save = vmcs_read(ENT_INTR_ERROR); 4102 u32 ent_inst_len_save = vmcs_read(ENT_INST_LEN); 4103 u32 primary_save = vmcs_read(CPU_EXEC_CTRL0); 4104 u32 secondary_save = vmcs_read(CPU_EXEC_CTRL1); 4105 u64 guest_cr0_save = vmcs_read(GUEST_CR0); 4106 u32 ent_intr_info_base = INTR_INFO_VALID_MASK; 4107 u32 ent_intr_info, ent_intr_err, ent_intr_len; 4108 u32 cnt; 4109 4110 /* Setup */ 4111 report_prefix_push("invalid event injection"); 4112 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4113 vmcs_write(ENT_INST_LEN, 0x00000001); 4114 4115 /* The field’s interruption type is not set to a reserved value. */ 4116 ent_intr_info = ent_intr_info_base | INTR_TYPE_RESERVED | DE_VECTOR; 4117 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4118 "RESERVED interruption type invalid [-]", 4119 ent_intr_info); 4120 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4121 test_vmx_invalid_controls(false); 4122 report_prefix_pop(); 4123 4124 ent_intr_info = ent_intr_info_base | INTR_TYPE_EXT_INTR | 4125 DE_VECTOR; 4126 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4127 "RESERVED interruption type invalid [+]", 4128 ent_intr_info); 4129 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4130 test_vmx_valid_controls(false); 4131 report_prefix_pop(); 4132 4133 /* If the interruption type is other event, the vector is 0. */ 4134 ent_intr_info = ent_intr_info_base | INTR_TYPE_OTHER_EVENT | DB_VECTOR; 4135 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4136 "(OTHER EVENT && vector != 0) invalid [-]", 4137 ent_intr_info); 4138 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4139 test_vmx_invalid_controls(false); 4140 report_prefix_pop(); 4141 4142 /* If the interruption type is NMI, the vector is 2 (negative case). */ 4143 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | DE_VECTOR; 4144 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4145 "(NMI && vector != 2) invalid [-]", ent_intr_info); 4146 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4147 test_vmx_invalid_controls(false); 4148 report_prefix_pop(); 4149 4150 /* If the interruption type is NMI, the vector is 2 (positive case). */ 4151 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | NMI_VECTOR; 4152 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4153 "(NMI && vector == 2) valid [+]", ent_intr_info); 4154 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4155 test_vmx_valid_controls(false); 4156 report_prefix_pop(); 4157 4158 /* 4159 * If the interruption type 4160 * is HW exception, the vector is at most 31. 4161 */ 4162 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 0x20; 4163 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4164 "(HW exception && vector > 31) invalid [-]", 4165 ent_intr_info); 4166 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4167 test_vmx_invalid_controls(false); 4168 report_prefix_pop(); 4169 4170 /* 4171 * deliver-error-code is 1 iff either 4172 * (a) the "unrestricted guest" VM-execution control is 0 4173 * (b) CR0.PE is set. 4174 */ 4175 4176 /* Assert that unrestricted guest is disabled or unsupported */ 4177 assert(!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 4178 !(secondary_save & CPU_URG)); 4179 4180 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4181 GP_VECTOR; 4182 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4183 "error code <-> (!URG || prot_mode) [-]", 4184 ent_intr_info); 4185 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4186 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4187 test_vmx_invalid_controls(false); 4188 report_prefix_pop(); 4189 4190 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4191 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4192 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4193 "error code <-> (!URG || prot_mode) [+]", 4194 ent_intr_info); 4195 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4196 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4197 test_vmx_valid_controls(false); 4198 report_prefix_pop(); 4199 4200 if (enable_unrestricted_guest()) 4201 goto skip_unrestricted_guest; 4202 4203 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4204 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4205 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4206 "error code <-> (!URG || prot_mode) [-]", 4207 ent_intr_info); 4208 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4209 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4210 test_vmx_invalid_controls(false); 4211 report_prefix_pop(); 4212 4213 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4214 GP_VECTOR; 4215 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4216 "error code <-> (!URG || prot_mode) [-]", 4217 ent_intr_info); 4218 vmcs_write(GUEST_CR0, guest_cr0_save | X86_CR0_PE); 4219 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4220 test_vmx_invalid_controls(false); 4221 report_prefix_pop(); 4222 4223 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4224 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4225 4226 skip_unrestricted_guest: 4227 vmcs_write(GUEST_CR0, guest_cr0_save); 4228 4229 /* deliver-error-code is 1 iff the interruption type is HW exception */ 4230 report_prefix_push("error code <-> HW exception"); 4231 for (cnt = 0; cnt < 8; cnt++) { 4232 u32 exception_type_mask = cnt << 8; 4233 u32 deliver_error_code_mask = 4234 exception_type_mask != INTR_TYPE_HARD_EXCEPTION ? 4235 INTR_INFO_DELIVER_CODE_MASK : 0; 4236 4237 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4238 exception_type_mask | GP_VECTOR; 4239 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4240 ent_intr_info); 4241 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4242 test_vmx_invalid_controls(false); 4243 report_prefix_pop(); 4244 } 4245 report_prefix_pop(); 4246 4247 /* 4248 * deliver-error-code is 1 iff the the vector 4249 * indicates an exception that would normally deliver an error code 4250 */ 4251 report_prefix_push("error code <-> vector delivers error code"); 4252 for (cnt = 0; cnt < 32; cnt++) { 4253 bool has_error_code = false; 4254 u32 deliver_error_code_mask; 4255 4256 switch (cnt) { 4257 case DF_VECTOR: 4258 case TS_VECTOR: 4259 case NP_VECTOR: 4260 case SS_VECTOR: 4261 case GP_VECTOR: 4262 case PF_VECTOR: 4263 case AC_VECTOR: 4264 has_error_code = true; 4265 } 4266 4267 /* Negative case */ 4268 deliver_error_code_mask = has_error_code ? 4269 0 : 4270 INTR_INFO_DELIVER_CODE_MASK; 4271 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4272 INTR_TYPE_HARD_EXCEPTION | cnt; 4273 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4274 ent_intr_info); 4275 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4276 test_vmx_invalid_controls(false); 4277 report_prefix_pop(); 4278 4279 /* Positive case */ 4280 deliver_error_code_mask = has_error_code ? 4281 INTR_INFO_DELIVER_CODE_MASK : 4282 0; 4283 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4284 INTR_TYPE_HARD_EXCEPTION | cnt; 4285 report_prefix_pushf("VM-entry intr info=0x%x [+]", 4286 ent_intr_info); 4287 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4288 test_vmx_valid_controls(false); 4289 report_prefix_pop(); 4290 } 4291 report_prefix_pop(); 4292 4293 /* Reserved bits in the field (30:12) are 0. */ 4294 report_prefix_push("reserved bits clear"); 4295 for (cnt = 12; cnt <= 30; cnt++) { 4296 ent_intr_info = ent_intr_info_base | 4297 INTR_INFO_DELIVER_CODE_MASK | 4298 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR | 4299 (1U << cnt); 4300 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4301 ent_intr_info); 4302 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4303 test_vmx_invalid_controls(false); 4304 report_prefix_pop(); 4305 } 4306 report_prefix_pop(); 4307 4308 /* 4309 * If deliver-error-code is 1 4310 * bits 31:16 of the VM-entry exception error-code field are 0. 4311 */ 4312 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4313 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4314 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4315 "VM-entry exception error code[31:16] clear", 4316 ent_intr_info); 4317 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4318 for (cnt = 16; cnt <= 31; cnt++) { 4319 ent_intr_err = 1U << cnt; 4320 report_prefix_pushf("VM-entry intr error=0x%x [-]", 4321 ent_intr_err); 4322 vmcs_write(ENT_INTR_ERROR, ent_intr_err); 4323 test_vmx_invalid_controls(false); 4324 report_prefix_pop(); 4325 } 4326 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4327 report_prefix_pop(); 4328 4329 /* 4330 * If the interruption type is software interrupt, software exception, 4331 * or privileged software exception, the VM-entry instruction-length 4332 * field is in the range 0–15. 4333 */ 4334 4335 for (cnt = 0; cnt < 3; cnt++) { 4336 switch (cnt) { 4337 case 0: 4338 ent_intr_info = ent_intr_info_base | 4339 INTR_TYPE_SOFT_INTR; 4340 break; 4341 case 1: 4342 ent_intr_info = ent_intr_info_base | 4343 INTR_TYPE_SOFT_EXCEPTION; 4344 break; 4345 case 2: 4346 ent_intr_info = ent_intr_info_base | 4347 INTR_TYPE_PRIV_SW_EXCEPTION; 4348 break; 4349 } 4350 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4351 "VM-entry instruction-length check", 4352 ent_intr_info); 4353 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4354 4355 /* Instruction length set to -1 (0xFFFFFFFF) should fail */ 4356 ent_intr_len = -1; 4357 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4358 ent_intr_len); 4359 vmcs_write(ENT_INST_LEN, ent_intr_len); 4360 test_vmx_invalid_controls(false); 4361 report_prefix_pop(); 4362 4363 /* Instruction length set to 16 should fail */ 4364 ent_intr_len = 0x00000010; 4365 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4366 ent_intr_len); 4367 vmcs_write(ENT_INST_LEN, 0x00000010); 4368 test_vmx_invalid_controls(false); 4369 report_prefix_pop(); 4370 4371 report_prefix_pop(); 4372 } 4373 4374 /* Cleanup */ 4375 vmcs_write(ENT_INTR_INFO, ent_intr_info_save); 4376 vmcs_write(ENT_INTR_ERROR, ent_intr_error_save); 4377 vmcs_write(ENT_INST_LEN, ent_inst_len_save); 4378 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4379 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4380 vmcs_write(GUEST_CR0, guest_cr0_save); 4381 report_prefix_pop(); 4382 } 4383 4384 /* 4385 * Test interesting vTPR values for a given TPR threshold. 4386 */ 4387 static void test_vtpr_values(unsigned threshold) 4388 { 4389 try_tpr_threshold_and_vtpr(threshold, (threshold - 1) << 4); 4390 try_tpr_threshold_and_vtpr(threshold, threshold << 4); 4391 try_tpr_threshold_and_vtpr(threshold, (threshold + 1) << 4); 4392 } 4393 4394 static void try_tpr_threshold(unsigned threshold) 4395 { 4396 bool valid = true; 4397 4398 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4399 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4400 4401 if ((primary & CPU_TPR_SHADOW) && !((primary & CPU_SECONDARY) && 4402 (secondary & CPU_VINTD))) 4403 valid = !(threshold >> 4); 4404 4405 set_vtpr(-1); 4406 vmcs_write(TPR_THRESHOLD, threshold); 4407 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0xf", threshold); 4408 if (valid) 4409 test_vmx_valid_controls(false); 4410 else 4411 test_vmx_invalid_controls(false); 4412 report_prefix_pop(); 4413 4414 if (valid) 4415 test_vtpr_values(threshold); 4416 } 4417 4418 /* 4419 * Test interesting TPR threshold values. 4420 */ 4421 static void test_tpr_threshold_values(void) 4422 { 4423 unsigned i; 4424 4425 for (i = 0; i < 0x10; i++) 4426 try_tpr_threshold(i); 4427 for (i = 4; i < 32; i++) 4428 try_tpr_threshold(1u << i); 4429 try_tpr_threshold(-1u); 4430 try_tpr_threshold(0x7fffffff); 4431 } 4432 4433 /* 4434 * This test covers the following two VM entry checks: 4435 * 4436 * i) If the "use TPR shadow" VM-execution control is 1 and the 4437 * "virtual-interrupt delivery" VM-execution control is 0, bits 4438 * 31:4 of the TPR threshold VM-execution control field must 4439 be 0. 4440 * [Intel SDM] 4441 * 4442 * ii) If the "use TPR shadow" VM-execution control is 1, the 4443 * "virtual-interrupt delivery" VM-execution control is 0 4444 * and the "virtualize APIC accesses" VM-execution control 4445 * is 0, the value of bits 3:0 of the TPR threshold VM-execution 4446 * control field must not be greater than the value of bits 4447 * 7:4 of VTPR. 4448 * [Intel SDM] 4449 */ 4450 static void test_tpr_threshold(void) 4451 { 4452 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4453 u64 apic_virt_addr = vmcs_read(APIC_VIRT_ADDR); 4454 u64 threshold = vmcs_read(TPR_THRESHOLD); 4455 void *virtual_apic_page; 4456 4457 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) 4458 return; 4459 4460 virtual_apic_page = alloc_page(); 4461 memset(virtual_apic_page, 0xff, PAGE_SIZE); 4462 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 4463 4464 vmcs_write(CPU_EXEC_CTRL0, primary & ~(CPU_TPR_SHADOW | CPU_SECONDARY)); 4465 report_prefix_pushf("Use TPR shadow disabled, secondary controls disabled"); 4466 test_tpr_threshold_values(); 4467 report_prefix_pop(); 4468 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_TPR_SHADOW); 4469 report_prefix_pushf("Use TPR shadow enabled, secondary controls disabled"); 4470 test_tpr_threshold_values(); 4471 report_prefix_pop(); 4472 4473 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4474 (ctrl_cpu_rev[1].clr & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 4475 goto out; 4476 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4477 4478 if (ctrl_cpu_rev[1].clr & CPU_VINTD) { 4479 vmcs_write(CPU_EXEC_CTRL1, CPU_VINTD); 4480 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4481 test_tpr_threshold_values(); 4482 report_prefix_pop(); 4483 4484 vmcs_write(CPU_EXEC_CTRL0, 4485 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4486 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4487 test_tpr_threshold_values(); 4488 report_prefix_pop(); 4489 } 4490 4491 if (ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES) { 4492 vmcs_write(CPU_EXEC_CTRL0, 4493 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4494 vmcs_write(CPU_EXEC_CTRL1, CPU_VIRT_APIC_ACCESSES); 4495 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4496 test_tpr_threshold_values(); 4497 report_prefix_pop(); 4498 4499 vmcs_write(CPU_EXEC_CTRL0, 4500 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4501 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4502 test_tpr_threshold_values(); 4503 report_prefix_pop(); 4504 } 4505 4506 if ((ctrl_cpu_rev[1].clr & 4507 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) == 4508 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) { 4509 vmcs_write(CPU_EXEC_CTRL0, 4510 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4511 vmcs_write(CPU_EXEC_CTRL1, 4512 CPU_VINTD | CPU_VIRT_APIC_ACCESSES); 4513 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4514 test_tpr_threshold_values(); 4515 report_prefix_pop(); 4516 4517 vmcs_write(CPU_EXEC_CTRL0, 4518 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4519 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4520 test_tpr_threshold_values(); 4521 report_prefix_pop(); 4522 } 4523 4524 vmcs_write(CPU_EXEC_CTRL1, secondary); 4525 out: 4526 vmcs_write(TPR_THRESHOLD, threshold); 4527 vmcs_write(APIC_VIRT_ADDR, apic_virt_addr); 4528 vmcs_write(CPU_EXEC_CTRL0, primary); 4529 } 4530 4531 /* 4532 * This test verifies the following two vmentry checks: 4533 * 4534 * If the "NMI exiting" VM-execution control is 0, "Virtual NMIs" 4535 * VM-execution control must be 0. 4536 * [Intel SDM] 4537 * 4538 * If the “virtual NMIs” VM-execution control is 0, the “NMI-window 4539 * exiting” VM-execution control must be 0. 4540 * [Intel SDM] 4541 */ 4542 static void test_nmi_ctrls(void) 4543 { 4544 u32 pin_ctrls, cpu_ctrls0, test_pin_ctrls, test_cpu_ctrls0; 4545 4546 if ((ctrl_pin_rev.clr & (PIN_NMI | PIN_VIRT_NMI)) != 4547 (PIN_NMI | PIN_VIRT_NMI)) { 4548 printf("NMI exiting and Virtual NMIs are not supported !\n"); 4549 return; 4550 } 4551 4552 /* Save the controls so that we can restore them after our tests */ 4553 pin_ctrls = vmcs_read(PIN_CONTROLS); 4554 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 4555 4556 test_pin_ctrls = pin_ctrls & ~(PIN_NMI | PIN_VIRT_NMI); 4557 test_cpu_ctrls0 = cpu_ctrls0 & ~CPU_NMI_WINDOW; 4558 4559 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4560 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs disabled"); 4561 test_vmx_valid_controls(false); 4562 report_prefix_pop(); 4563 4564 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_VIRT_NMI); 4565 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs enabled"); 4566 test_vmx_invalid_controls(false); 4567 report_prefix_pop(); 4568 4569 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4570 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs enabled"); 4571 test_vmx_valid_controls(false); 4572 report_prefix_pop(); 4573 4574 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_NMI); 4575 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs disabled"); 4576 test_vmx_valid_controls(false); 4577 report_prefix_pop(); 4578 4579 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 4580 report_info("NMI-window exiting is not supported, skipping..."); 4581 goto done; 4582 } 4583 4584 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4585 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4586 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting enabled"); 4587 test_vmx_invalid_controls(false); 4588 report_prefix_pop(); 4589 4590 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4591 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4592 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting disabled"); 4593 test_vmx_valid_controls(false); 4594 report_prefix_pop(); 4595 4596 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4597 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4598 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting enabled"); 4599 test_vmx_valid_controls(false); 4600 report_prefix_pop(); 4601 4602 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4603 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4604 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting disabled"); 4605 test_vmx_valid_controls(false); 4606 report_prefix_pop(); 4607 4608 /* Restore the controls to their original values */ 4609 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 4610 done: 4611 vmcs_write(PIN_CONTROLS, pin_ctrls); 4612 } 4613 4614 static void test_eptp_ad_bit(u64 eptp, bool ctrl) 4615 { 4616 vmcs_write(EPTP, eptp); 4617 report_prefix_pushf("Enable-EPT enabled; EPT accessed and dirty flag %s", 4618 (eptp & EPTP_AD_FLAG) ? "1": "0"); 4619 if (ctrl) 4620 test_vmx_valid_controls(false); 4621 else 4622 test_vmx_invalid_controls(false); 4623 report_prefix_pop(); 4624 4625 } 4626 4627 /* 4628 * 1. If the "enable EPT" VM-execution control is 1, the "EPTP VM-execution" 4629 * control field must satisfy the following checks: 4630 * 4631 * - The EPT memory type (bits 2:0) must be a value supported by the 4632 * processor as indicated in the IA32_VMX_EPT_VPID_CAP MSR. 4633 * - Bits 5:3 (1 less than the EPT page-walk length) must be 3, 4634 * indicating an EPT page-walk length of 4. 4635 * - Bit 6 (enable bit for accessed and dirty flags for EPT) must be 4636 * 0 if bit 21 of the IA32_VMX_EPT_VPID_CAP MSR is read as 0, 4637 * indicating that the processor does not support accessed and dirty 4638 * dirty flags for EPT. 4639 * - Reserved bits 11:7 and 63:N (where N is the processor's 4640 * physical-address width) must all be 0. 4641 * 4642 * 2. If the "unrestricted guest" VM-execution control is 1, the 4643 * "enable EPT" VM-execution control must also be 1. 4644 */ 4645 static void test_ept_eptp(void) 4646 { 4647 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4648 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4649 u64 eptp_saved = vmcs_read(EPTP); 4650 u32 primary = primary_saved; 4651 u32 secondary = secondary_saved; 4652 u64 msr, eptp = eptp_saved; 4653 bool un_cache = false; 4654 bool wr_bk = false; 4655 bool ctrl; 4656 u32 i, maxphysaddr; 4657 u64 j, resv_bits_mask = 0; 4658 4659 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4660 (ctrl_cpu_rev[1].clr & CPU_EPT))) { 4661 printf("\"CPU secondary\" and/or \"enable EPT\" execution controls are not supported !\n"); 4662 return; 4663 } 4664 4665 /* 4666 * Memory type (bits 2:0) 4667 */ 4668 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 4669 if (msr & EPT_CAP_UC) 4670 un_cache = true; 4671 if (msr & EPT_CAP_WB) 4672 wr_bk = true; 4673 4674 primary |= CPU_SECONDARY; 4675 vmcs_write(CPU_EXEC_CTRL0, primary); 4676 secondary |= CPU_EPT; 4677 vmcs_write(CPU_EXEC_CTRL1, secondary); 4678 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4679 (3ul << EPTP_PG_WALK_LEN_SHIFT); 4680 vmcs_write(EPTP, eptp); 4681 4682 for (i = 0; i < 8; i++) { 4683 if (i == 0) { 4684 if (un_cache) { 4685 report_info("EPT paging structure memory-type is Un-cacheable\n"); 4686 ctrl = true; 4687 } else { 4688 ctrl = false; 4689 } 4690 } else if (i == 6) { 4691 if (wr_bk) { 4692 report_info("EPT paging structure memory-type is Write-back\n"); 4693 ctrl = true; 4694 } else { 4695 ctrl = false; 4696 } 4697 } else { 4698 ctrl = false; 4699 } 4700 4701 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | i; 4702 vmcs_write(EPTP, eptp); 4703 report_prefix_pushf("Enable-EPT enabled; EPT memory type %lu", 4704 eptp & EPT_MEM_TYPE_MASK); 4705 if (ctrl) 4706 test_vmx_valid_controls(false); 4707 else 4708 test_vmx_invalid_controls(false); 4709 report_prefix_pop(); 4710 } 4711 4712 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | 6ul; 4713 4714 /* 4715 * Page walk length (bits 5:3) 4716 */ 4717 for (i = 0; i < 8; i++) { 4718 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4719 (i << EPTP_PG_WALK_LEN_SHIFT); 4720 if (i == 3) 4721 ctrl = true; 4722 else 4723 ctrl = false; 4724 4725 vmcs_write(EPTP, eptp); 4726 report_prefix_pushf("Enable-EPT enabled; EPT page walk length %lu", 4727 eptp & EPTP_PG_WALK_LEN_MASK); 4728 if (ctrl) 4729 test_vmx_valid_controls(false); 4730 else 4731 test_vmx_invalid_controls(false); 4732 report_prefix_pop(); 4733 } 4734 4735 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4736 3ul << EPTP_PG_WALK_LEN_SHIFT; 4737 4738 /* 4739 * Accessed and dirty flag (bit 6) 4740 */ 4741 if (msr & EPT_CAP_AD_FLAG) { 4742 report_info("Processor supports accessed and dirty flag"); 4743 eptp &= ~EPTP_AD_FLAG; 4744 test_eptp_ad_bit(eptp, true); 4745 4746 eptp |= EPTP_AD_FLAG; 4747 test_eptp_ad_bit(eptp, true); 4748 } else { 4749 report_info("Processor does not supports accessed and dirty flag"); 4750 eptp &= ~EPTP_AD_FLAG; 4751 test_eptp_ad_bit(eptp, true); 4752 4753 eptp |= EPTP_AD_FLAG; 4754 test_eptp_ad_bit(eptp, false); 4755 } 4756 4757 /* 4758 * Reserved bits [11:7] and [63:N] 4759 */ 4760 for (i = 0; i < 32; i++) { 4761 eptp = (eptp & 4762 ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)) | 4763 (i << EPTP_RESERV_BITS_SHIFT); 4764 vmcs_write(EPTP, eptp); 4765 report_prefix_pushf("Enable-EPT enabled; reserved bits [11:7] %lu", 4766 (eptp >> EPTP_RESERV_BITS_SHIFT) & 4767 EPTP_RESERV_BITS_MASK); 4768 if (i == 0) 4769 test_vmx_valid_controls(false); 4770 else 4771 test_vmx_invalid_controls(false); 4772 report_prefix_pop(); 4773 } 4774 4775 eptp = (eptp & ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)); 4776 4777 maxphysaddr = cpuid_maxphyaddr(); 4778 for (i = 0; i < (63 - maxphysaddr + 1); i++) { 4779 resv_bits_mask |= 1ul << i; 4780 } 4781 4782 for (j = maxphysaddr - 1; j <= 63; j++) { 4783 eptp = (eptp & ~(resv_bits_mask << maxphysaddr)) | 4784 (j < maxphysaddr ? 0 : 1ul << j); 4785 vmcs_write(EPTP, eptp); 4786 report_prefix_pushf("Enable-EPT enabled; reserved bits [63:N] %lu", 4787 (eptp >> maxphysaddr) & resv_bits_mask); 4788 if (j < maxphysaddr) 4789 test_vmx_valid_controls(false); 4790 else 4791 test_vmx_invalid_controls(false); 4792 report_prefix_pop(); 4793 } 4794 4795 secondary &= ~(CPU_EPT | CPU_URG); 4796 vmcs_write(CPU_EXEC_CTRL1, secondary); 4797 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest disabled"); 4798 test_vmx_valid_controls(false); 4799 report_prefix_pop(); 4800 4801 if (!(ctrl_cpu_rev[1].clr & CPU_URG)) 4802 goto skip_unrestricted_guest; 4803 4804 secondary |= CPU_URG; 4805 vmcs_write(CPU_EXEC_CTRL1, secondary); 4806 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest enabled"); 4807 test_vmx_invalid_controls(false); 4808 report_prefix_pop(); 4809 4810 secondary |= CPU_EPT; 4811 setup_dummy_ept(); 4812 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest enabled"); 4813 test_vmx_valid_controls(false); 4814 report_prefix_pop(); 4815 4816 skip_unrestricted_guest: 4817 secondary &= ~CPU_URG; 4818 vmcs_write(CPU_EXEC_CTRL1, secondary); 4819 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest disabled"); 4820 test_vmx_valid_controls(false); 4821 report_prefix_pop(); 4822 4823 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4824 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4825 vmcs_write(EPTP, eptp_saved); 4826 } 4827 4828 /* 4829 * If the 'enable PML' VM-execution control is 1, the 'enable EPT' 4830 * VM-execution control must also be 1. In addition, the PML address 4831 * must satisfy the following checks: 4832 * 4833 * * Bits 11:0 of the address must be 0. 4834 * * The address should not set any bits beyond the processor's 4835 * physical-address width. 4836 * 4837 * [Intel SDM] 4838 */ 4839 static void test_pml(void) 4840 { 4841 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4842 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4843 u32 primary = primary_saved; 4844 u32 secondary = secondary_saved; 4845 4846 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4847 (ctrl_cpu_rev[1].clr & CPU_EPT) && (ctrl_cpu_rev[1].clr & CPU_PML))) { 4848 printf("\"Secondary execution\" control or \"enable EPT\" control or \"enable PML\" control is not supported !\n"); 4849 return; 4850 } 4851 4852 primary |= CPU_SECONDARY; 4853 vmcs_write(CPU_EXEC_CTRL0, primary); 4854 secondary &= ~(CPU_PML | CPU_EPT); 4855 vmcs_write(CPU_EXEC_CTRL1, secondary); 4856 report_prefix_pushf("enable-PML disabled, enable-EPT disabled"); 4857 test_vmx_valid_controls(false); 4858 report_prefix_pop(); 4859 4860 secondary |= CPU_PML; 4861 vmcs_write(CPU_EXEC_CTRL1, secondary); 4862 report_prefix_pushf("enable-PML enabled, enable-EPT disabled"); 4863 test_vmx_invalid_controls(false); 4864 report_prefix_pop(); 4865 4866 secondary |= CPU_EPT; 4867 setup_dummy_ept(); 4868 report_prefix_pushf("enable-PML enabled, enable-EPT enabled"); 4869 test_vmx_valid_controls(false); 4870 report_prefix_pop(); 4871 4872 secondary &= ~CPU_PML; 4873 vmcs_write(CPU_EXEC_CTRL1, secondary); 4874 report_prefix_pushf("enable-PML disabled, enable EPT enabled"); 4875 test_vmx_valid_controls(false); 4876 report_prefix_pop(); 4877 4878 test_vmcs_addr_reference(CPU_PML, PMLADDR, "PML address", "PML", 4879 PAGE_SIZE, false, false); 4880 4881 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4882 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4883 } 4884 4885 /* 4886 * If the "activate VMX-preemption timer" VM-execution control is 0, the 4887 * the "save VMX-preemption timer value" VM-exit control must also be 0. 4888 * 4889 * [Intel SDM] 4890 */ 4891 static void test_vmx_preemption_timer(void) 4892 { 4893 u32 saved_pin = vmcs_read(PIN_CONTROLS); 4894 u32 saved_exit = vmcs_read(EXI_CONTROLS); 4895 u32 pin = saved_pin; 4896 u32 exit = saved_exit; 4897 4898 if (!((ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) || 4899 (ctrl_pin_rev.clr & PIN_PREEMPT))) { 4900 printf("\"Save-VMX-preemption-timer\" control and/or \"Enable-VMX-preemption-timer\" control is not supported\n"); 4901 return; 4902 } 4903 4904 pin |= PIN_PREEMPT; 4905 vmcs_write(PIN_CONTROLS, pin); 4906 exit &= ~EXI_SAVE_PREEMPT; 4907 vmcs_write(EXI_CONTROLS, exit); 4908 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer disabled"); 4909 test_vmx_valid_controls(false); 4910 report_prefix_pop(); 4911 4912 exit |= EXI_SAVE_PREEMPT; 4913 vmcs_write(EXI_CONTROLS, exit); 4914 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer enabled"); 4915 test_vmx_valid_controls(false); 4916 report_prefix_pop(); 4917 4918 pin &= ~PIN_PREEMPT; 4919 vmcs_write(PIN_CONTROLS, pin); 4920 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer enabled"); 4921 test_vmx_invalid_controls(false); 4922 report_prefix_pop(); 4923 4924 exit &= ~EXI_SAVE_PREEMPT; 4925 vmcs_write(EXI_CONTROLS, exit); 4926 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer disabled"); 4927 test_vmx_valid_controls(false); 4928 report_prefix_pop(); 4929 4930 vmcs_write(PIN_CONTROLS, saved_pin); 4931 vmcs_write(EXI_CONTROLS, saved_exit); 4932 } 4933 4934 /* 4935 * Tests for VM-execution control fields 4936 */ 4937 static void test_vm_execution_ctls(void) 4938 { 4939 test_pin_based_ctls(); 4940 test_primary_processor_based_ctls(); 4941 test_secondary_processor_based_ctls(); 4942 test_cr3_targets(); 4943 test_io_bitmaps(); 4944 test_msr_bitmap(); 4945 test_apic_ctls(); 4946 test_tpr_threshold(); 4947 test_nmi_ctrls(); 4948 test_pml(); 4949 test_vpid(); 4950 test_ept_eptp(); 4951 test_vmx_preemption_timer(); 4952 } 4953 4954 /* 4955 * The following checks are performed for the VM-entry MSR-load address if 4956 * the VM-entry MSR-load count field is non-zero: 4957 * 4958 * - The lower 4 bits of the VM-entry MSR-load address must be 0. 4959 * The address should not set any bits beyond the processor’s 4960 * physical-address width. 4961 * 4962 * - The address of the last byte in the VM-entry MSR-load area 4963 * should not set any bits beyond the processor’s physical-address 4964 * width. The address of this last byte is VM-entry MSR-load address 4965 * + (MSR count * 16) - 1. (The arithmetic used for the computation 4966 * uses more bits than the processor’s physical-address width.) 4967 * 4968 * 4969 * [Intel SDM] 4970 */ 4971 static void test_entry_msr_load(void) 4972 { 4973 entry_msr_load = alloc_page(); 4974 u64 tmp; 4975 u32 entry_msr_ld_cnt = 1; 4976 int i; 4977 u32 addr_len = 64; 4978 4979 vmcs_write(ENT_MSR_LD_CNT, entry_msr_ld_cnt); 4980 4981 /* Check first 4 bits of VM-entry MSR-load address */ 4982 for (i = 0; i < 4; i++) { 4983 tmp = (u64)entry_msr_load | 1ull << i; 4984 vmcs_write(ENTER_MSR_LD_ADDR, tmp); 4985 report_prefix_pushf("VM-entry MSR-load addr [4:0] %lx", 4986 tmp & 0xf); 4987 test_vmx_invalid_controls(false); 4988 report_prefix_pop(); 4989 } 4990 4991 if (basic.val & (1ul << 48)) 4992 addr_len = 32; 4993 4994 test_vmcs_addr_values("VM-entry-MSR-load address", 4995 ENTER_MSR_LD_ADDR, 16, false, false, 4996 4, addr_len - 1); 4997 4998 /* 4999 * Check last byte of VM-entry MSR-load address 5000 */ 5001 entry_msr_load = (struct vmx_msr_entry *)((u64)entry_msr_load & ~0xf); 5002 5003 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 5004 i < 64; i++) { 5005 tmp = ((u64)entry_msr_load + entry_msr_ld_cnt * 16 - 1) | 5006 1ul << i; 5007 vmcs_write(ENTER_MSR_LD_ADDR, 5008 tmp - (entry_msr_ld_cnt * 16 - 1)); 5009 test_vmx_invalid_controls(false); 5010 } 5011 5012 vmcs_write(ENT_MSR_LD_CNT, 2); 5013 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 5014 test_vmx_invalid_controls(false); 5015 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 5016 test_vmx_valid_controls(false); 5017 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 5018 test_vmx_valid_controls(false); 5019 } 5020 5021 static void guest_state_test_main(void) 5022 { 5023 while (1) { 5024 if (vmx_get_test_stage() != 2) 5025 vmcall(); 5026 else 5027 break; 5028 } 5029 5030 asm volatile("fnop"); 5031 } 5032 5033 static void report_guest_state_test(const char *test, u32 xreason, 5034 u64 field, const char * field_name) 5035 { 5036 u32 reason = vmcs_read(EXI_REASON); 5037 u64 guest_rip; 5038 u32 insn_len; 5039 5040 report("%s, %s %lx", reason == xreason, test, field_name, field); 5041 5042 guest_rip = vmcs_read(GUEST_RIP); 5043 insn_len = vmcs_read(EXI_INST_LEN); 5044 if (! (reason & 0x80000021)) 5045 vmcs_write(GUEST_RIP, guest_rip + insn_len); 5046 } 5047 5048 /* 5049 * Tests for VM-entry control fields 5050 */ 5051 static void test_vm_entry_ctls(void) 5052 { 5053 test_invalid_event_injection(); 5054 test_entry_msr_load(); 5055 } 5056 5057 /* 5058 * The following checks are performed for the VM-exit MSR-store address if 5059 * the VM-exit MSR-store count field is non-zero: 5060 * 5061 * - The lower 4 bits of the VM-exit MSR-store address must be 0. 5062 * The address should not set any bits beyond the processor’s 5063 * physical-address width. 5064 * 5065 * - The address of the last byte in the VM-exit MSR-store area 5066 * should not set any bits beyond the processor’s physical-address 5067 * width. The address of this last byte is VM-exit MSR-store address 5068 * + (MSR count * 16) - 1. (The arithmetic used for the computation 5069 * uses more bits than the processor’s physical-address width.) 5070 * 5071 * If IA32_VMX_BASIC[48] is read as 1, neither address should set any bits 5072 * in the range 63:32. 5073 * 5074 * [Intel SDM] 5075 */ 5076 static void test_exit_msr_store(void) 5077 { 5078 exit_msr_store = alloc_page(); 5079 u64 tmp; 5080 u32 exit_msr_st_cnt = 1; 5081 int i; 5082 u32 addr_len = 64; 5083 5084 vmcs_write(EXI_MSR_ST_CNT, exit_msr_st_cnt); 5085 5086 /* Check first 4 bits of VM-exit MSR-store address */ 5087 for (i = 0; i < 4; i++) { 5088 tmp = (u64)exit_msr_store | 1ull << i; 5089 vmcs_write(EXIT_MSR_ST_ADDR, tmp); 5090 report_prefix_pushf("VM-exit MSR-store addr [4:0] %lx", 5091 tmp & 0xf); 5092 test_vmx_invalid_controls(false); 5093 report_prefix_pop(); 5094 } 5095 5096 if (basic.val & (1ul << 48)) 5097 addr_len = 32; 5098 5099 test_vmcs_addr_values("VM-exit-MSR-store address", 5100 EXIT_MSR_ST_ADDR, 16, false, false, 5101 4, addr_len - 1); 5102 5103 /* 5104 * Check last byte of VM-exit MSR-store address 5105 */ 5106 exit_msr_store = (struct vmx_msr_entry *)((u64)exit_msr_store & ~0xf); 5107 5108 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 5109 i < 64; i++) { 5110 tmp = ((u64)exit_msr_store + exit_msr_st_cnt * 16 - 1) | 5111 1ul << i; 5112 vmcs_write(EXIT_MSR_ST_ADDR, 5113 tmp - (exit_msr_st_cnt * 16 - 1)); 5114 test_vmx_invalid_controls(false); 5115 } 5116 5117 vmcs_write(EXI_MSR_ST_CNT, 2); 5118 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 5119 test_vmx_invalid_controls(false); 5120 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 5121 test_vmx_valid_controls(false); 5122 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 5123 test_vmx_valid_controls(false); 5124 } 5125 5126 /* 5127 * Tests for VM-exit controls 5128 */ 5129 static void test_vm_exit_ctls(void) 5130 { 5131 test_exit_msr_store(); 5132 } 5133 5134 /* 5135 * Check that the virtual CPU checks all of the VMX controls as 5136 * documented in the Intel SDM. 5137 */ 5138 static void vmx_controls_test(void) 5139 { 5140 /* 5141 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 5142 * fail due to invalid guest state, should we make it that 5143 * far. 5144 */ 5145 vmcs_write(GUEST_RFLAGS, 0); 5146 5147 test_vm_execution_ctls(); 5148 test_vm_exit_ctls(); 5149 test_vm_entry_ctls(); 5150 } 5151 5152 struct apic_reg_virt_config { 5153 bool apic_register_virtualization; 5154 bool use_tpr_shadow; 5155 bool virtualize_apic_accesses; 5156 bool virtualize_x2apic_mode; 5157 bool activate_secondary_controls; 5158 }; 5159 5160 struct apic_reg_test { 5161 const char *name; 5162 struct apic_reg_virt_config apic_reg_virt_config; 5163 }; 5164 5165 struct apic_reg_virt_expectation { 5166 enum Reason rd_exit_reason; 5167 enum Reason wr_exit_reason; 5168 u32 val; 5169 u32 (*virt_fn)(u32); 5170 5171 /* 5172 * If false, accessing the APIC access address from L2 is treated as a 5173 * normal memory operation, rather than triggering virtualization. 5174 */ 5175 bool virtualize_apic_accesses; 5176 }; 5177 5178 static u32 apic_virt_identity(u32 val) 5179 { 5180 return val; 5181 } 5182 5183 static u32 apic_virt_nibble1(u32 val) 5184 { 5185 return val & 0xf0; 5186 } 5187 5188 static u32 apic_virt_byte3(u32 val) 5189 { 5190 return val & (0xff << 24); 5191 } 5192 5193 static bool apic_reg_virt_exit_expectation( 5194 u32 reg, struct apic_reg_virt_config *config, 5195 struct apic_reg_virt_expectation *expectation) 5196 { 5197 /* Good configs, where some L2 APIC accesses are virtualized. */ 5198 bool virtualize_apic_accesses_only = 5199 config->virtualize_apic_accesses && 5200 !config->use_tpr_shadow && 5201 !config->apic_register_virtualization && 5202 !config->virtualize_x2apic_mode && 5203 config->activate_secondary_controls; 5204 bool virtualize_apic_accesses_and_use_tpr_shadow = 5205 config->virtualize_apic_accesses && 5206 config->use_tpr_shadow && 5207 !config->apic_register_virtualization && 5208 !config->virtualize_x2apic_mode && 5209 config->activate_secondary_controls; 5210 bool apic_register_virtualization = 5211 config->virtualize_apic_accesses && 5212 config->use_tpr_shadow && 5213 config->apic_register_virtualization && 5214 !config->virtualize_x2apic_mode && 5215 config->activate_secondary_controls; 5216 5217 expectation->val = MAGIC_VAL_1; 5218 expectation->virt_fn = apic_virt_identity; 5219 expectation->virtualize_apic_accesses = 5220 config->virtualize_apic_accesses && 5221 config->activate_secondary_controls; 5222 if (virtualize_apic_accesses_only) { 5223 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5224 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5225 } else if (virtualize_apic_accesses_and_use_tpr_shadow) { 5226 switch (reg) { 5227 case APIC_TASKPRI: 5228 expectation->rd_exit_reason = VMX_VMCALL; 5229 expectation->wr_exit_reason = VMX_VMCALL; 5230 expectation->virt_fn = apic_virt_nibble1; 5231 break; 5232 default: 5233 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5234 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5235 } 5236 } else if (apic_register_virtualization) { 5237 expectation->rd_exit_reason = VMX_VMCALL; 5238 5239 switch (reg) { 5240 case APIC_ID: 5241 case APIC_EOI: 5242 case APIC_LDR: 5243 case APIC_DFR: 5244 case APIC_SPIV: 5245 case APIC_ESR: 5246 case APIC_ICR: 5247 case APIC_LVTT: 5248 case APIC_LVTTHMR: 5249 case APIC_LVTPC: 5250 case APIC_LVT0: 5251 case APIC_LVT1: 5252 case APIC_LVTERR: 5253 case APIC_TMICT: 5254 case APIC_TDCR: 5255 expectation->wr_exit_reason = VMX_APIC_WRITE; 5256 break; 5257 case APIC_LVR: 5258 case APIC_ISR ... APIC_ISR + 0x70: 5259 case APIC_TMR ... APIC_TMR + 0x70: 5260 case APIC_IRR ... APIC_IRR + 0x70: 5261 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5262 break; 5263 case APIC_TASKPRI: 5264 expectation->wr_exit_reason = VMX_VMCALL; 5265 expectation->virt_fn = apic_virt_nibble1; 5266 break; 5267 case APIC_ICR2: 5268 expectation->wr_exit_reason = VMX_VMCALL; 5269 expectation->virt_fn = apic_virt_byte3; 5270 break; 5271 default: 5272 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5273 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5274 } 5275 } else if (!expectation->virtualize_apic_accesses) { 5276 /* 5277 * No APIC registers are directly virtualized. This includes 5278 * VTPR, which can be virtualized through MOV to/from CR8 via 5279 * the use TPR shadow control, but not through directly 5280 * accessing VTPR. 5281 */ 5282 expectation->rd_exit_reason = VMX_VMCALL; 5283 expectation->wr_exit_reason = VMX_VMCALL; 5284 } else { 5285 printf("Cannot parse APIC register virtualization config:\n" 5286 "\tvirtualize_apic_accesses: %d\n" 5287 "\tuse_tpr_shadow: %d\n" 5288 "\tapic_register_virtualization: %d\n" 5289 "\tvirtualize_x2apic_mode: %d\n" 5290 "\tactivate_secondary_controls: %d\n", 5291 config->virtualize_apic_accesses, 5292 config->use_tpr_shadow, 5293 config->apic_register_virtualization, 5294 config->virtualize_x2apic_mode, 5295 config->activate_secondary_controls); 5296 5297 return false; 5298 } 5299 5300 return true; 5301 } 5302 5303 struct apic_reg_test apic_reg_tests[] = { 5304 /* Good configs, where some L2 APIC accesses are virtualized. */ 5305 { 5306 .name = "Virtualize APIC accesses", 5307 .apic_reg_virt_config = { 5308 .virtualize_apic_accesses = true, 5309 .use_tpr_shadow = false, 5310 .apic_register_virtualization = false, 5311 .virtualize_x2apic_mode = false, 5312 .activate_secondary_controls = true, 5313 }, 5314 }, 5315 { 5316 .name = "Virtualize APIC accesses + Use TPR shadow", 5317 .apic_reg_virt_config = { 5318 .virtualize_apic_accesses = true, 5319 .use_tpr_shadow = true, 5320 .apic_register_virtualization = false, 5321 .virtualize_x2apic_mode = false, 5322 .activate_secondary_controls = true, 5323 }, 5324 }, 5325 { 5326 .name = "APIC-register virtualization", 5327 .apic_reg_virt_config = { 5328 .virtualize_apic_accesses = true, 5329 .use_tpr_shadow = true, 5330 .apic_register_virtualization = true, 5331 .virtualize_x2apic_mode = false, 5332 .activate_secondary_controls = true, 5333 }, 5334 }, 5335 5336 /* 5337 * Test that the secondary processor-based VM-execution controls are 5338 * correctly ignored when "activate secondary controls" is disabled. 5339 */ 5340 { 5341 .name = "Activate secondary controls off", 5342 .apic_reg_virt_config = { 5343 .virtualize_apic_accesses = true, 5344 .use_tpr_shadow = false, 5345 .apic_register_virtualization = true, 5346 .virtualize_x2apic_mode = true, 5347 .activate_secondary_controls = false, 5348 }, 5349 }, 5350 { 5351 .name = "Activate secondary controls off + Use TPR shadow", 5352 .apic_reg_virt_config = { 5353 .virtualize_apic_accesses = true, 5354 .use_tpr_shadow = true, 5355 .apic_register_virtualization = true, 5356 .virtualize_x2apic_mode = true, 5357 .activate_secondary_controls = false, 5358 }, 5359 }, 5360 5361 /* 5362 * Test that the APIC access address is treated like an arbitrary memory 5363 * address when "virtualize APIC accesses" is disabled. 5364 */ 5365 { 5366 .name = "Virtualize APIC accesses off + Use TPR shadow", 5367 .apic_reg_virt_config = { 5368 .virtualize_apic_accesses = false, 5369 .use_tpr_shadow = true, 5370 .apic_register_virtualization = true, 5371 .virtualize_x2apic_mode = true, 5372 .activate_secondary_controls = true, 5373 }, 5374 }, 5375 5376 /* 5377 * Test that VM entry fails due to invalid controls when 5378 * "APIC-register virtualization" is enabled while "use TPR shadow" is 5379 * disabled. 5380 */ 5381 { 5382 .name = "APIC-register virtualization + Use TPR shadow off", 5383 .apic_reg_virt_config = { 5384 .virtualize_apic_accesses = true, 5385 .use_tpr_shadow = false, 5386 .apic_register_virtualization = true, 5387 .virtualize_x2apic_mode = false, 5388 .activate_secondary_controls = true, 5389 }, 5390 }, 5391 5392 /* 5393 * Test that VM entry fails due to invalid controls when 5394 * "Virtualize x2APIC mode" is enabled while "use TPR shadow" is 5395 * disabled. 5396 */ 5397 { 5398 .name = "Virtualize x2APIC mode + Use TPR shadow off", 5399 .apic_reg_virt_config = { 5400 .virtualize_apic_accesses = false, 5401 .use_tpr_shadow = false, 5402 .apic_register_virtualization = false, 5403 .virtualize_x2apic_mode = true, 5404 .activate_secondary_controls = true, 5405 }, 5406 }, 5407 { 5408 .name = "Virtualize x2APIC mode + Use TPR shadow off v2", 5409 .apic_reg_virt_config = { 5410 .virtualize_apic_accesses = false, 5411 .use_tpr_shadow = false, 5412 .apic_register_virtualization = true, 5413 .virtualize_x2apic_mode = true, 5414 .activate_secondary_controls = true, 5415 }, 5416 }, 5417 5418 /* 5419 * Test that VM entry fails due to invalid controls when 5420 * "virtualize x2APIC mode" is enabled while "virtualize APIC accesses" 5421 * is enabled. 5422 */ 5423 { 5424 .name = "Virtualize x2APIC mode + Virtualize APIC accesses", 5425 .apic_reg_virt_config = { 5426 .virtualize_apic_accesses = true, 5427 .use_tpr_shadow = true, 5428 .apic_register_virtualization = false, 5429 .virtualize_x2apic_mode = true, 5430 .activate_secondary_controls = true, 5431 }, 5432 }, 5433 { 5434 .name = "Virtualize x2APIC mode + Virtualize APIC accesses v2", 5435 .apic_reg_virt_config = { 5436 .virtualize_apic_accesses = true, 5437 .use_tpr_shadow = true, 5438 .apic_register_virtualization = true, 5439 .virtualize_x2apic_mode = true, 5440 .activate_secondary_controls = true, 5441 }, 5442 }, 5443 }; 5444 5445 enum Apic_op { 5446 APIC_OP_XAPIC_RD, 5447 APIC_OP_XAPIC_WR, 5448 TERMINATE, 5449 }; 5450 5451 static u32 vmx_xapic_read(u32 *apic_access_address, u32 reg) 5452 { 5453 return *(volatile u32 *)((uintptr_t)apic_access_address + reg); 5454 } 5455 5456 static void vmx_xapic_write(u32 *apic_access_address, u32 reg, u32 val) 5457 { 5458 *(volatile u32 *)((uintptr_t)apic_access_address + reg) = val; 5459 } 5460 5461 struct apic_reg_virt_guest_args { 5462 enum Apic_op op; 5463 u32 *apic_access_address; 5464 u32 reg; 5465 u32 val; 5466 bool check_rd; 5467 u32 (*virt_fn)(u32); 5468 } apic_reg_virt_guest_args; 5469 5470 static void apic_reg_virt_guest(void) 5471 { 5472 volatile struct apic_reg_virt_guest_args *args = 5473 &apic_reg_virt_guest_args; 5474 5475 for (;;) { 5476 enum Apic_op op = args->op; 5477 u32 *apic_access_address = args->apic_access_address; 5478 u32 reg = args->reg; 5479 u32 val = args->val; 5480 bool check_rd = args->check_rd; 5481 u32 (*virt_fn)(u32) = args->virt_fn; 5482 5483 if (op == TERMINATE) 5484 break; 5485 5486 if (op == APIC_OP_XAPIC_RD) { 5487 u32 ret = vmx_xapic_read(apic_access_address, reg); 5488 5489 if (check_rd) { 5490 u32 want = virt_fn(val); 5491 u32 got = virt_fn(ret); 5492 5493 report("read 0x%x, expected 0x%x.", 5494 got == want, got, want); 5495 } 5496 } else if (op == APIC_OP_XAPIC_WR) { 5497 vmx_xapic_write(apic_access_address, reg, val); 5498 } 5499 5500 /* 5501 * The L1 should always execute a vmcall after it's done testing 5502 * an individual APIC operation. This helps to validate that the 5503 * L1 and L2 are in sync with each other, as expected. 5504 */ 5505 vmcall(); 5506 } 5507 } 5508 5509 static void test_xapic_rd( 5510 u32 reg, struct apic_reg_virt_expectation *expectation, 5511 u32 *apic_access_address, u32 *virtual_apic_page) 5512 { 5513 u32 val = expectation->val; 5514 u32 exit_reason_want = expectation->rd_exit_reason; 5515 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 5516 5517 report_prefix_pushf("xapic - reading 0x%03x", reg); 5518 5519 /* Configure guest to do an xapic read */ 5520 args->op = APIC_OP_XAPIC_RD; 5521 args->apic_access_address = apic_access_address; 5522 args->reg = reg; 5523 args->val = val; 5524 args->check_rd = exit_reason_want == VMX_VMCALL; 5525 args->virt_fn = expectation->virt_fn; 5526 5527 /* Setup virtual APIC page */ 5528 if (!expectation->virtualize_apic_accesses) { 5529 apic_access_address[apic_reg_index(reg)] = val; 5530 virtual_apic_page[apic_reg_index(reg)] = 0; 5531 } else if (exit_reason_want == VMX_VMCALL) { 5532 apic_access_address[apic_reg_index(reg)] = 0; 5533 virtual_apic_page[apic_reg_index(reg)] = val; 5534 } 5535 5536 /* Enter guest */ 5537 enter_guest(); 5538 5539 /* 5540 * Validate the behavior and 5541 * pass a magic value back to the guest. 5542 */ 5543 if (exit_reason_want == VMX_APIC_ACCESS) { 5544 u32 apic_page_offset = vmcs_read(EXI_QUALIFICATION) & 0xfff; 5545 5546 assert_exit_reason(exit_reason_want); 5547 report("got APIC access exit @ page offset 0x%03x, want 0x%03x", 5548 apic_page_offset == reg, apic_page_offset, reg); 5549 skip_exit_insn(); 5550 5551 /* Reenter guest so it can consume/check rcx and exit again. */ 5552 enter_guest(); 5553 } else if (exit_reason_want != VMX_VMCALL) { 5554 report("Oops, bad exit expectation: %u.", false, 5555 exit_reason_want); 5556 } 5557 5558 skip_exit_vmcall(); 5559 report_prefix_pop(); 5560 } 5561 5562 static void test_xapic_wr( 5563 u32 reg, struct apic_reg_virt_expectation *expectation, 5564 u32 *apic_access_address, u32 *virtual_apic_page) 5565 { 5566 u32 val = expectation->val; 5567 u32 exit_reason_want = expectation->wr_exit_reason; 5568 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 5569 bool virtualized = 5570 expectation->virtualize_apic_accesses && 5571 (exit_reason_want == VMX_APIC_WRITE || 5572 exit_reason_want == VMX_VMCALL); 5573 bool checked = false; 5574 5575 report_prefix_pushf("xapic - writing 0x%x to 0x%03x", val, reg); 5576 5577 /* Configure guest to do an xapic read */ 5578 args->op = APIC_OP_XAPIC_WR; 5579 args->apic_access_address = apic_access_address; 5580 args->reg = reg; 5581 args->val = val; 5582 5583 /* Setup virtual APIC page */ 5584 if (virtualized || !expectation->virtualize_apic_accesses) { 5585 apic_access_address[apic_reg_index(reg)] = 0; 5586 virtual_apic_page[apic_reg_index(reg)] = 0; 5587 } 5588 5589 /* Enter guest */ 5590 enter_guest(); 5591 5592 /* 5593 * Validate the behavior and 5594 * pass a magic value back to the guest. 5595 */ 5596 if (exit_reason_want == VMX_APIC_ACCESS) { 5597 u32 apic_page_offset = vmcs_read(EXI_QUALIFICATION) & 0xfff; 5598 5599 assert_exit_reason(exit_reason_want); 5600 report("got APIC access exit @ page offset 0x%03x, want 0x%03x", 5601 apic_page_offset == reg, apic_page_offset, reg); 5602 skip_exit_insn(); 5603 5604 /* Reenter guest so it can consume/check rcx and exit again. */ 5605 enter_guest(); 5606 } else if (exit_reason_want == VMX_APIC_WRITE) { 5607 assert_exit_reason(exit_reason_want); 5608 report("got APIC write exit @ page offset 0x%03x; val is 0x%x, want 0x%x", 5609 virtual_apic_page[apic_reg_index(reg)] == val, 5610 apic_reg_index(reg), 5611 virtual_apic_page[apic_reg_index(reg)], val); 5612 checked = true; 5613 5614 /* Reenter guest so it can consume/check rcx and exit again. */ 5615 enter_guest(); 5616 } else if (exit_reason_want != VMX_VMCALL) { 5617 report("Oops, bad exit expectation: %u.", false, 5618 exit_reason_want); 5619 } 5620 5621 assert_exit_reason(VMX_VMCALL); 5622 if (virtualized && !checked) { 5623 u32 want = expectation->virt_fn(val); 5624 u32 got = virtual_apic_page[apic_reg_index(reg)]; 5625 got = expectation->virt_fn(got); 5626 5627 report("exitless write; val is 0x%x, want 0x%x", 5628 got == want, got, want); 5629 } else if (!expectation->virtualize_apic_accesses && !checked) { 5630 u32 got = apic_access_address[apic_reg_index(reg)]; 5631 5632 report("non-virtualized write; val is 0x%x, want 0x%x", 5633 got == val, got, val); 5634 } else if (!expectation->virtualize_apic_accesses && checked) { 5635 report("Non-virtualized write was prematurely checked!", false); 5636 } 5637 5638 skip_exit_vmcall(); 5639 report_prefix_pop(); 5640 } 5641 5642 enum Config_type { 5643 CONFIG_TYPE_GOOD, 5644 CONFIG_TYPE_UNSUPPORTED, 5645 CONFIG_TYPE_VMENTRY_FAILS_EARLY, 5646 }; 5647 5648 static enum Config_type configure_apic_reg_virt_test( 5649 struct apic_reg_virt_config *apic_reg_virt_config) 5650 { 5651 u32 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 5652 u32 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 5653 /* Configs where L2 entry fails early, due to invalid controls. */ 5654 bool use_tpr_shadow_incorrectly_off = 5655 !apic_reg_virt_config->use_tpr_shadow && 5656 (apic_reg_virt_config->apic_register_virtualization || 5657 apic_reg_virt_config->virtualize_x2apic_mode) && 5658 apic_reg_virt_config->activate_secondary_controls; 5659 bool virtualize_apic_accesses_incorrectly_on = 5660 apic_reg_virt_config->virtualize_apic_accesses && 5661 apic_reg_virt_config->virtualize_x2apic_mode && 5662 apic_reg_virt_config->activate_secondary_controls; 5663 bool vmentry_fails_early = 5664 use_tpr_shadow_incorrectly_off || 5665 virtualize_apic_accesses_incorrectly_on; 5666 5667 if (apic_reg_virt_config->activate_secondary_controls) { 5668 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 5669 printf("VM-execution control \"activate secondary controls\" NOT supported.\n"); 5670 return CONFIG_TYPE_UNSUPPORTED; 5671 } 5672 cpu_exec_ctrl0 |= CPU_SECONDARY; 5673 } else { 5674 cpu_exec_ctrl0 &= ~CPU_SECONDARY; 5675 } 5676 5677 if (apic_reg_virt_config->virtualize_apic_accesses) { 5678 if (!(ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES)) { 5679 printf("VM-execution control \"virtualize APIC accesses\" NOT supported.\n"); 5680 return CONFIG_TYPE_UNSUPPORTED; 5681 } 5682 cpu_exec_ctrl1 |= CPU_VIRT_APIC_ACCESSES; 5683 } else { 5684 cpu_exec_ctrl1 &= ~CPU_VIRT_APIC_ACCESSES; 5685 } 5686 5687 if (apic_reg_virt_config->use_tpr_shadow) { 5688 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) { 5689 printf("VM-execution control \"use TPR shadow\" NOT supported.\n"); 5690 return CONFIG_TYPE_UNSUPPORTED; 5691 } 5692 cpu_exec_ctrl0 |= CPU_TPR_SHADOW; 5693 } else { 5694 cpu_exec_ctrl0 &= ~CPU_TPR_SHADOW; 5695 } 5696 5697 if (apic_reg_virt_config->apic_register_virtualization) { 5698 if (!(ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT)) { 5699 printf("VM-execution control \"APIC-register virtualization\" NOT supported.\n"); 5700 return CONFIG_TYPE_UNSUPPORTED; 5701 } 5702 cpu_exec_ctrl1 |= CPU_APIC_REG_VIRT; 5703 } else { 5704 cpu_exec_ctrl1 &= ~CPU_APIC_REG_VIRT; 5705 } 5706 5707 if (apic_reg_virt_config->virtualize_x2apic_mode) { 5708 if (!(ctrl_cpu_rev[1].clr & CPU_VIRT_X2APIC)) { 5709 printf("VM-execution control \"virtualize x2APIC mode\" NOT supported.\n"); 5710 return CONFIG_TYPE_UNSUPPORTED; 5711 } 5712 cpu_exec_ctrl1 |= CPU_VIRT_X2APIC; 5713 } else { 5714 cpu_exec_ctrl1 &= ~CPU_VIRT_X2APIC; 5715 } 5716 5717 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 5718 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 5719 5720 if (vmentry_fails_early) 5721 return CONFIG_TYPE_VMENTRY_FAILS_EARLY; 5722 5723 return CONFIG_TYPE_GOOD; 5724 } 5725 5726 static bool cpu_has_apicv(void) 5727 { 5728 return ((ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT) && 5729 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 5730 (ctrl_pin_rev.clr & PIN_POST_INTR)); 5731 } 5732 5733 /* Validates APIC register access across valid virtualization configurations. */ 5734 static void apic_reg_virt_test(void) 5735 { 5736 u32 *apic_access_address; 5737 u32 *virtual_apic_page; 5738 u64 control; 5739 u64 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 5740 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 5741 int i; 5742 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 5743 5744 if (!cpu_has_apicv()) { 5745 report_skip(__func__); 5746 return; 5747 } 5748 5749 control = cpu_exec_ctrl1; 5750 control &= ~CPU_VINTD; 5751 vmcs_write(CPU_EXEC_CTRL1, control); 5752 5753 test_set_guest(apic_reg_virt_guest); 5754 5755 /* 5756 * From the SDM: The 1-setting of the "virtualize APIC accesses" 5757 * VM-execution is guaranteed to apply only if translations to the 5758 * APIC-access address use a 4-KByte page. 5759 */ 5760 apic_access_address = alloc_page(); 5761 force_4k_page(apic_access_address); 5762 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_address)); 5763 5764 virtual_apic_page = alloc_page(); 5765 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 5766 5767 for (i = 0; i < ARRAY_SIZE(apic_reg_tests); i++) { 5768 struct apic_reg_test *apic_reg_test = &apic_reg_tests[i]; 5769 struct apic_reg_virt_config *apic_reg_virt_config = 5770 &apic_reg_test->apic_reg_virt_config; 5771 enum Config_type config_type; 5772 u32 reg; 5773 5774 printf("--- %s test ---\n", apic_reg_test->name); 5775 config_type = 5776 configure_apic_reg_virt_test(apic_reg_virt_config); 5777 if (config_type == CONFIG_TYPE_UNSUPPORTED) { 5778 printf("Skip because of missing features.\n"); 5779 continue; 5780 } 5781 5782 if (config_type == CONFIG_TYPE_VMENTRY_FAILS_EARLY) { 5783 enter_guest_with_bad_controls(); 5784 continue; 5785 } 5786 5787 for (reg = 0; reg < PAGE_SIZE / sizeof(u32); reg += 0x10) { 5788 struct apic_reg_virt_expectation expectation = {}; 5789 bool ok; 5790 5791 ok = apic_reg_virt_exit_expectation( 5792 reg, apic_reg_virt_config, &expectation); 5793 if (!ok) { 5794 report("Malformed test.", false); 5795 break; 5796 } 5797 5798 test_xapic_rd(reg, &expectation, apic_access_address, 5799 virtual_apic_page); 5800 test_xapic_wr(reg, &expectation, apic_access_address, 5801 virtual_apic_page); 5802 } 5803 } 5804 5805 /* Terminate the guest */ 5806 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 5807 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 5808 args->op = TERMINATE; 5809 enter_guest(); 5810 assert_exit_reason(VMX_VMCALL); 5811 } 5812 5813 struct virt_x2apic_mode_config { 5814 struct apic_reg_virt_config apic_reg_virt_config; 5815 bool virtual_interrupt_delivery; 5816 bool use_msr_bitmaps; 5817 bool disable_x2apic_msr_intercepts; 5818 bool disable_x2apic; 5819 }; 5820 5821 struct virt_x2apic_mode_test_case { 5822 const char *name; 5823 struct virt_x2apic_mode_config virt_x2apic_mode_config; 5824 }; 5825 5826 enum Virt_x2apic_mode_behavior_type { 5827 X2APIC_ACCESS_VIRTUALIZED, 5828 X2APIC_ACCESS_PASSED_THROUGH, 5829 X2APIC_ACCESS_TRIGGERS_GP, 5830 }; 5831 5832 struct virt_x2apic_mode_expectation { 5833 enum Reason rd_exit_reason; 5834 enum Reason wr_exit_reason; 5835 5836 /* 5837 * RDMSR and WRMSR handle 64-bit values. However, except for ICR, all of 5838 * the x2APIC registers are 32 bits. Notice: 5839 * 1. vmx_x2apic_read() clears the upper 32 bits for 32-bit registers. 5840 * 2. vmx_x2apic_write() expects the val arg to be well-formed. 5841 */ 5842 u64 rd_val; 5843 u64 wr_val; 5844 5845 /* 5846 * Compares input to virtualized output; 5847 * 1st arg is pointer to return expected virtualization output. 5848 */ 5849 u64 (*virt_fn)(u64); 5850 5851 enum Virt_x2apic_mode_behavior_type rd_behavior; 5852 enum Virt_x2apic_mode_behavior_type wr_behavior; 5853 bool wr_only; 5854 }; 5855 5856 static u64 virt_x2apic_mode_identity(u64 val) 5857 { 5858 return val; 5859 } 5860 5861 static u64 virt_x2apic_mode_nibble1(u64 val) 5862 { 5863 return val & 0xf0; 5864 } 5865 5866 static bool is_cmci_enabled(void) 5867 { 5868 return rdmsr(MSR_IA32_MCG_CAP) & BIT_ULL(10); 5869 } 5870 5871 static void virt_x2apic_mode_rd_expectation( 5872 u32 reg, bool virt_x2apic_mode_on, bool disable_x2apic, 5873 bool apic_register_virtualization, bool virtual_interrupt_delivery, 5874 struct virt_x2apic_mode_expectation *expectation) 5875 { 5876 bool readable = 5877 !x2apic_reg_reserved(reg) && 5878 reg != APIC_EOI; 5879 5880 if (reg == APIC_CMCI && !is_cmci_enabled()) 5881 readable = false; 5882 5883 expectation->rd_exit_reason = VMX_VMCALL; 5884 expectation->virt_fn = virt_x2apic_mode_identity; 5885 if (virt_x2apic_mode_on && apic_register_virtualization) { 5886 expectation->rd_val = MAGIC_VAL_1; 5887 if (reg == APIC_PROCPRI && virtual_interrupt_delivery) 5888 expectation->virt_fn = virt_x2apic_mode_nibble1; 5889 else if (reg == APIC_TASKPRI) 5890 expectation->virt_fn = virt_x2apic_mode_nibble1; 5891 expectation->rd_behavior = X2APIC_ACCESS_VIRTUALIZED; 5892 } else if (virt_x2apic_mode_on && !apic_register_virtualization && 5893 reg == APIC_TASKPRI) { 5894 expectation->rd_val = MAGIC_VAL_1; 5895 expectation->virt_fn = virt_x2apic_mode_nibble1; 5896 expectation->rd_behavior = X2APIC_ACCESS_VIRTUALIZED; 5897 } else if (!disable_x2apic && readable) { 5898 expectation->rd_val = apic_read(reg); 5899 expectation->rd_behavior = X2APIC_ACCESS_PASSED_THROUGH; 5900 } else { 5901 expectation->rd_behavior = X2APIC_ACCESS_TRIGGERS_GP; 5902 } 5903 } 5904 5905 /* 5906 * get_x2apic_wr_val() creates an innocuous write value for an x2APIC register. 5907 * 5908 * For writable registers, get_x2apic_wr_val() deposits the write value into the 5909 * val pointer arg and returns true. For non-writable registers, val is not 5910 * modified and get_x2apic_wr_val() returns false. 5911 */ 5912 static bool get_x2apic_wr_val(u32 reg, u64 *val) 5913 { 5914 switch (reg) { 5915 case APIC_TASKPRI: 5916 /* Bits 31:8 are reserved. */ 5917 *val &= 0xff; 5918 break; 5919 case APIC_EOI: 5920 case APIC_ESR: 5921 case APIC_TMICT: 5922 /* 5923 * EOI, ESR: WRMSR of a non-zero value causes #GP(0). 5924 * TMICT: A write of 0 to the initial-count register effectively 5925 * stops the local APIC timer, in both one-shot and 5926 * periodic mode. 5927 */ 5928 *val = 0; 5929 break; 5930 case APIC_SPIV: 5931 case APIC_LVTT: 5932 case APIC_LVTTHMR: 5933 case APIC_LVTPC: 5934 case APIC_LVT0: 5935 case APIC_LVT1: 5936 case APIC_LVTERR: 5937 case APIC_TDCR: 5938 /* 5939 * To avoid writing a 1 to a reserved bit or causing some other 5940 * unintended side effect, read the current value and use it as 5941 * the write value. 5942 */ 5943 *val = apic_read(reg); 5944 break; 5945 case APIC_CMCI: 5946 if (!is_cmci_enabled()) 5947 return false; 5948 *val = apic_read(reg); 5949 break; 5950 case APIC_ICR: 5951 *val = 0x40000 | 0xf1; 5952 break; 5953 case APIC_SELF_IPI: 5954 /* 5955 * With special processing (i.e., virtualize x2APIC mode + 5956 * virtual interrupt delivery), writing zero causes an 5957 * APIC-write VM exit. We plan to add a test for enabling 5958 * "virtual-interrupt delivery" in VMCS12, and that's where we 5959 * will test a self IPI with special processing. 5960 */ 5961 *val = 0x0; 5962 break; 5963 default: 5964 return false; 5965 } 5966 5967 return true; 5968 } 5969 5970 static bool special_processing_applies(u32 reg, u64 *val, 5971 bool virt_int_delivery) 5972 { 5973 bool special_processing = 5974 (reg == APIC_TASKPRI) || 5975 (virt_int_delivery && 5976 (reg == APIC_EOI || reg == APIC_SELF_IPI)); 5977 5978 if (special_processing) { 5979 TEST_ASSERT(get_x2apic_wr_val(reg, val)); 5980 return true; 5981 } 5982 5983 return false; 5984 } 5985 5986 static void virt_x2apic_mode_wr_expectation( 5987 u32 reg, bool virt_x2apic_mode_on, bool disable_x2apic, 5988 bool virt_int_delivery, 5989 struct virt_x2apic_mode_expectation *expectation) 5990 { 5991 expectation->wr_exit_reason = VMX_VMCALL; 5992 expectation->wr_val = MAGIC_VAL_1; 5993 expectation->wr_only = false; 5994 5995 if (virt_x2apic_mode_on && 5996 special_processing_applies(reg, &expectation->wr_val, 5997 virt_int_delivery)) { 5998 expectation->wr_behavior = X2APIC_ACCESS_VIRTUALIZED; 5999 if (reg == APIC_SELF_IPI) 6000 expectation->wr_exit_reason = VMX_APIC_WRITE; 6001 } else if (!disable_x2apic && 6002 get_x2apic_wr_val(reg, &expectation->wr_val)) { 6003 expectation->wr_behavior = X2APIC_ACCESS_PASSED_THROUGH; 6004 if (reg == APIC_EOI || reg == APIC_SELF_IPI) 6005 expectation->wr_only = true; 6006 if (reg == APIC_ICR) 6007 expectation->wr_exit_reason = VMX_EXTINT; 6008 } else { 6009 expectation->wr_behavior = X2APIC_ACCESS_TRIGGERS_GP; 6010 /* 6011 * Writing 1 to a reserved bit triggers a #GP. 6012 * Thus, set the write value to 0, which seems 6013 * the most likely to detect a missed #GP. 6014 */ 6015 expectation->wr_val = 0; 6016 } 6017 } 6018 6019 static void virt_x2apic_mode_exit_expectation( 6020 u32 reg, struct virt_x2apic_mode_config *config, 6021 struct virt_x2apic_mode_expectation *expectation) 6022 { 6023 struct apic_reg_virt_config *base_config = 6024 &config->apic_reg_virt_config; 6025 bool virt_x2apic_mode_on = 6026 base_config->virtualize_x2apic_mode && 6027 config->use_msr_bitmaps && 6028 config->disable_x2apic_msr_intercepts && 6029 base_config->activate_secondary_controls; 6030 6031 virt_x2apic_mode_wr_expectation( 6032 reg, virt_x2apic_mode_on, config->disable_x2apic, 6033 config->virtual_interrupt_delivery, expectation); 6034 virt_x2apic_mode_rd_expectation( 6035 reg, virt_x2apic_mode_on, config->disable_x2apic, 6036 base_config->apic_register_virtualization, 6037 config->virtual_interrupt_delivery, expectation); 6038 } 6039 6040 struct virt_x2apic_mode_test_case virt_x2apic_mode_tests[] = { 6041 /* 6042 * Baseline "virtualize x2APIC mode" configuration: 6043 * - virtualize x2APIC mode 6044 * - virtual-interrupt delivery 6045 * - APIC-register virtualization 6046 * - x2APIC MSR intercepts disabled 6047 * 6048 * Reads come from virtual APIC page, special processing applies to 6049 * VTPR, EOI, and SELF IPI, and all other writes pass through to L1 6050 * APIC. 6051 */ 6052 { 6053 .name = "Baseline", 6054 .virt_x2apic_mode_config = { 6055 .virtual_interrupt_delivery = true, 6056 .use_msr_bitmaps = true, 6057 .disable_x2apic_msr_intercepts = true, 6058 .disable_x2apic = false, 6059 .apic_reg_virt_config = { 6060 .apic_register_virtualization = true, 6061 .use_tpr_shadow = true, 6062 .virtualize_apic_accesses = false, 6063 .virtualize_x2apic_mode = true, 6064 .activate_secondary_controls = true, 6065 }, 6066 }, 6067 }, 6068 { 6069 .name = "Baseline w/ x2apic disabled", 6070 .virt_x2apic_mode_config = { 6071 .virtual_interrupt_delivery = true, 6072 .use_msr_bitmaps = true, 6073 .disable_x2apic_msr_intercepts = true, 6074 .disable_x2apic = true, 6075 .apic_reg_virt_config = { 6076 .apic_register_virtualization = true, 6077 .use_tpr_shadow = true, 6078 .virtualize_apic_accesses = false, 6079 .virtualize_x2apic_mode = true, 6080 .activate_secondary_controls = true, 6081 }, 6082 }, 6083 }, 6084 6085 /* 6086 * Baseline, minus virtual-interrupt delivery. Reads come from virtual 6087 * APIC page, special processing applies to VTPR, and all other writes 6088 * pass through to L1 APIC. 6089 */ 6090 { 6091 .name = "Baseline - virtual interrupt delivery", 6092 .virt_x2apic_mode_config = { 6093 .virtual_interrupt_delivery = false, 6094 .use_msr_bitmaps = true, 6095 .disable_x2apic_msr_intercepts = true, 6096 .disable_x2apic = false, 6097 .apic_reg_virt_config = { 6098 .apic_register_virtualization = true, 6099 .use_tpr_shadow = true, 6100 .virtualize_apic_accesses = false, 6101 .virtualize_x2apic_mode = true, 6102 .activate_secondary_controls = true, 6103 }, 6104 }, 6105 }, 6106 6107 /* 6108 * Baseline, minus APIC-register virtualization. x2APIC reads pass 6109 * through to L1's APIC, unless reading VTPR 6110 */ 6111 { 6112 .name = "Virtualize x2APIC mode, no APIC reg virt", 6113 .virt_x2apic_mode_config = { 6114 .virtual_interrupt_delivery = true, 6115 .use_msr_bitmaps = true, 6116 .disable_x2apic_msr_intercepts = true, 6117 .disable_x2apic = false, 6118 .apic_reg_virt_config = { 6119 .apic_register_virtualization = false, 6120 .use_tpr_shadow = true, 6121 .virtualize_apic_accesses = false, 6122 .virtualize_x2apic_mode = true, 6123 .activate_secondary_controls = true, 6124 }, 6125 }, 6126 }, 6127 { 6128 .name = "Virtualize x2APIC mode, no APIC reg virt, x2APIC off", 6129 .virt_x2apic_mode_config = { 6130 .virtual_interrupt_delivery = true, 6131 .use_msr_bitmaps = true, 6132 .disable_x2apic_msr_intercepts = true, 6133 .disable_x2apic = true, 6134 .apic_reg_virt_config = { 6135 .apic_register_virtualization = false, 6136 .use_tpr_shadow = true, 6137 .virtualize_apic_accesses = false, 6138 .virtualize_x2apic_mode = true, 6139 .activate_secondary_controls = true, 6140 }, 6141 }, 6142 }, 6143 6144 /* 6145 * Enable "virtualize x2APIC mode" and "APIC-register virtualization", 6146 * and disable intercepts for the x2APIC MSRs, but fail to enable 6147 * "activate secondary controls" (i.e. L2 gets access to L1's x2APIC 6148 * MSRs). 6149 */ 6150 { 6151 .name = "Fail to enable activate secondary controls", 6152 .virt_x2apic_mode_config = { 6153 .virtual_interrupt_delivery = true, 6154 .use_msr_bitmaps = true, 6155 .disable_x2apic_msr_intercepts = true, 6156 .disable_x2apic = false, 6157 .apic_reg_virt_config = { 6158 .apic_register_virtualization = true, 6159 .use_tpr_shadow = true, 6160 .virtualize_apic_accesses = false, 6161 .virtualize_x2apic_mode = true, 6162 .activate_secondary_controls = false, 6163 }, 6164 }, 6165 }, 6166 6167 /* 6168 * Enable "APIC-register virtualization" and enable "activate secondary 6169 * controls" and disable intercepts for the x2APIC MSRs, but do not 6170 * enable the "virtualize x2APIC mode" VM-execution control (i.e. L2 6171 * gets access to L1's x2APIC MSRs). 6172 */ 6173 { 6174 .name = "Fail to enable virtualize x2APIC mode", 6175 .virt_x2apic_mode_config = { 6176 .virtual_interrupt_delivery = true, 6177 .use_msr_bitmaps = true, 6178 .disable_x2apic_msr_intercepts = true, 6179 .disable_x2apic = false, 6180 .apic_reg_virt_config = { 6181 .apic_register_virtualization = true, 6182 .use_tpr_shadow = true, 6183 .virtualize_apic_accesses = false, 6184 .virtualize_x2apic_mode = false, 6185 .activate_secondary_controls = true, 6186 }, 6187 }, 6188 }, 6189 6190 /* 6191 * Disable "Virtualize x2APIC mode", disable x2APIC MSR intercepts, and 6192 * enable "APIC-register virtualization" --> L2 gets L1's x2APIC MSRs. 6193 */ 6194 { 6195 .name = "Baseline", 6196 .virt_x2apic_mode_config = { 6197 .virtual_interrupt_delivery = true, 6198 .use_msr_bitmaps = true, 6199 .disable_x2apic_msr_intercepts = true, 6200 .disable_x2apic = false, 6201 .apic_reg_virt_config = { 6202 .apic_register_virtualization = true, 6203 .use_tpr_shadow = true, 6204 .virtualize_apic_accesses = false, 6205 .virtualize_x2apic_mode = false, 6206 .activate_secondary_controls = true, 6207 }, 6208 }, 6209 }, 6210 }; 6211 6212 enum X2apic_op { 6213 X2APIC_OP_RD, 6214 X2APIC_OP_WR, 6215 X2APIC_TERMINATE, 6216 }; 6217 6218 static u64 vmx_x2apic_read(u32 reg) 6219 { 6220 u32 msr_addr = x2apic_msr(reg); 6221 u64 val; 6222 6223 val = rdmsr(msr_addr); 6224 6225 return val; 6226 } 6227 6228 static void vmx_x2apic_write(u32 reg, u64 val) 6229 { 6230 u32 msr_addr = x2apic_msr(reg); 6231 6232 wrmsr(msr_addr, val); 6233 } 6234 6235 struct virt_x2apic_mode_guest_args { 6236 enum X2apic_op op; 6237 u32 reg; 6238 u64 val; 6239 bool should_gp; 6240 u64 (*virt_fn)(u64); 6241 } virt_x2apic_mode_guest_args; 6242 6243 static volatile bool handle_x2apic_gp_ran; 6244 static volatile u32 handle_x2apic_gp_insn_len; 6245 static void handle_x2apic_gp(struct ex_regs *regs) 6246 { 6247 handle_x2apic_gp_ran = true; 6248 regs->rip += handle_x2apic_gp_insn_len; 6249 } 6250 6251 static handler setup_x2apic_gp_handler(void) 6252 { 6253 handler old_handler; 6254 6255 old_handler = handle_exception(GP_VECTOR, handle_x2apic_gp); 6256 /* RDMSR and WRMSR are both 2 bytes, assuming no prefixes. */ 6257 handle_x2apic_gp_insn_len = 2; 6258 6259 return old_handler; 6260 } 6261 6262 static void teardown_x2apic_gp_handler(handler old_handler) 6263 { 6264 handle_exception(GP_VECTOR, old_handler); 6265 6266 /* 6267 * Defensively reset instruction length, so that if the handler is 6268 * incorrectly used, it will loop infinitely, rather than run off into 6269 * la la land. 6270 */ 6271 handle_x2apic_gp_insn_len = 0; 6272 handle_x2apic_gp_ran = false; 6273 } 6274 6275 static void virt_x2apic_mode_guest(void) 6276 { 6277 volatile struct virt_x2apic_mode_guest_args *args = 6278 &virt_x2apic_mode_guest_args; 6279 6280 for (;;) { 6281 enum X2apic_op op = args->op; 6282 u32 reg = args->reg; 6283 u64 val = args->val; 6284 bool should_gp = args->should_gp; 6285 u64 (*virt_fn)(u64) = args->virt_fn; 6286 handler old_handler; 6287 6288 if (op == X2APIC_TERMINATE) 6289 break; 6290 6291 if (should_gp) { 6292 TEST_ASSERT(!handle_x2apic_gp_ran); 6293 old_handler = setup_x2apic_gp_handler(); 6294 } 6295 6296 if (op == X2APIC_OP_RD) { 6297 u64 ret = vmx_x2apic_read(reg); 6298 6299 if (!should_gp) { 6300 u64 want = virt_fn(val); 6301 u64 got = virt_fn(ret); 6302 6303 report("APIC read; got 0x%lx, want 0x%lx.", 6304 got == want, got, want); 6305 } 6306 } else if (op == X2APIC_OP_WR) { 6307 vmx_x2apic_write(reg, val); 6308 } 6309 6310 if (should_gp) { 6311 report("x2APIC op triggered GP.", 6312 handle_x2apic_gp_ran); 6313 teardown_x2apic_gp_handler(old_handler); 6314 } 6315 6316 /* 6317 * The L1 should always execute a vmcall after it's done testing 6318 * an individual APIC operation. This helps to validate that the 6319 * L1 and L2 are in sync with each other, as expected. 6320 */ 6321 vmcall(); 6322 } 6323 } 6324 6325 static void test_x2apic_rd( 6326 u32 reg, struct virt_x2apic_mode_expectation *expectation, 6327 u32 *virtual_apic_page) 6328 { 6329 u64 val = expectation->rd_val; 6330 u32 exit_reason_want = expectation->rd_exit_reason; 6331 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6332 6333 report_prefix_pushf("x2apic - reading 0x%03x", reg); 6334 6335 /* Configure guest to do an x2apic read */ 6336 args->op = X2APIC_OP_RD; 6337 args->reg = reg; 6338 args->val = val; 6339 args->should_gp = expectation->rd_behavior == X2APIC_ACCESS_TRIGGERS_GP; 6340 args->virt_fn = expectation->virt_fn; 6341 6342 /* Setup virtual APIC page */ 6343 if (expectation->rd_behavior == X2APIC_ACCESS_VIRTUALIZED) 6344 virtual_apic_page[apic_reg_index(reg)] = (u32)val; 6345 6346 /* Enter guest */ 6347 enter_guest(); 6348 6349 if (exit_reason_want != VMX_VMCALL) { 6350 report("Oops, bad exit expectation: %u.", false, 6351 exit_reason_want); 6352 } 6353 6354 skip_exit_vmcall(); 6355 report_prefix_pop(); 6356 } 6357 6358 static volatile bool handle_x2apic_ipi_ran; 6359 static void handle_x2apic_ipi(isr_regs_t *regs) 6360 { 6361 handle_x2apic_ipi_ran = true; 6362 eoi(); 6363 } 6364 6365 static void test_x2apic_wr( 6366 u32 reg, struct virt_x2apic_mode_expectation *expectation, 6367 u32 *virtual_apic_page) 6368 { 6369 u64 val = expectation->wr_val; 6370 u32 exit_reason_want = expectation->wr_exit_reason; 6371 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6372 int ipi_vector = 0xf1; 6373 u32 restore_val = 0; 6374 6375 report_prefix_pushf("x2apic - writing 0x%lx to 0x%03x", val, reg); 6376 6377 /* Configure guest to do an x2apic read */ 6378 args->op = X2APIC_OP_WR; 6379 args->reg = reg; 6380 args->val = val; 6381 args->should_gp = expectation->wr_behavior == X2APIC_ACCESS_TRIGGERS_GP; 6382 6383 /* Setup virtual APIC page */ 6384 if (expectation->wr_behavior == X2APIC_ACCESS_VIRTUALIZED) 6385 virtual_apic_page[apic_reg_index(reg)] = 0; 6386 if (expectation->wr_behavior == X2APIC_ACCESS_PASSED_THROUGH && !expectation->wr_only) 6387 restore_val = apic_read(reg); 6388 6389 /* Setup IPI handler */ 6390 handle_x2apic_ipi_ran = false; 6391 handle_irq(ipi_vector, handle_x2apic_ipi); 6392 6393 /* Enter guest */ 6394 enter_guest(); 6395 6396 /* 6397 * Validate the behavior and 6398 * pass a magic value back to the guest. 6399 */ 6400 if (exit_reason_want == VMX_EXTINT) { 6401 assert_exit_reason(exit_reason_want); 6402 6403 /* Clear the external interrupt. */ 6404 irq_enable(); 6405 asm volatile ("nop"); 6406 irq_disable(); 6407 report("Got pending interrupt after IRQ enabled.", 6408 handle_x2apic_ipi_ran); 6409 6410 enter_guest(); 6411 } else if (exit_reason_want == VMX_APIC_WRITE) { 6412 assert_exit_reason(exit_reason_want); 6413 report("got APIC write exit @ page offset 0x%03x; val is 0x%x, want 0x%lx", 6414 virtual_apic_page[apic_reg_index(reg)] == val, 6415 apic_reg_index(reg), 6416 virtual_apic_page[apic_reg_index(reg)], val); 6417 6418 /* Reenter guest so it can consume/check rcx and exit again. */ 6419 enter_guest(); 6420 } else if (exit_reason_want != VMX_VMCALL) { 6421 report("Oops, bad exit expectation: %u.", false, 6422 exit_reason_want); 6423 } 6424 6425 assert_exit_reason(VMX_VMCALL); 6426 if (expectation->wr_behavior == X2APIC_ACCESS_VIRTUALIZED) { 6427 u64 want = val; 6428 u32 got = virtual_apic_page[apic_reg_index(reg)]; 6429 6430 report("x2APIC write; got 0x%x, want 0x%lx", 6431 got == want, got, want); 6432 } else if (expectation->wr_behavior == X2APIC_ACCESS_PASSED_THROUGH) { 6433 if (!expectation->wr_only) { 6434 u32 got = apic_read(reg); 6435 bool ok; 6436 6437 /* 6438 * When L1's TPR is passed through to L2, the lower 6439 * nibble can be lost. For example, if L2 executes 6440 * WRMSR(0x808, 0x78), then, L1 might read 0x70. 6441 * 6442 * Here's how the lower nibble can get lost: 6443 * 1. L2 executes WRMSR(0x808, 0x78). 6444 * 2. L2 exits to L0 with a WRMSR exit. 6445 * 3. L0 emulates WRMSR, by writing L1's TPR. 6446 * 4. L0 re-enters L2. 6447 * 5. L2 exits to L0 (reason doesn't matter). 6448 * 6. L0 reflects L2's exit to L1. 6449 * 7. Before entering L1, L0 exits to user-space 6450 * (e.g., to satisfy TPR access reporting). 6451 * 8. User-space executes KVM_SET_REGS ioctl, which 6452 * clears the lower nibble of L1's TPR. 6453 */ 6454 if (reg == APIC_TASKPRI) { 6455 got = apic_virt_nibble1(got); 6456 val = apic_virt_nibble1(val); 6457 } 6458 6459 ok = got == val; 6460 report("non-virtualized write; val is 0x%x, want 0x%lx", 6461 ok, got, val); 6462 apic_write(reg, restore_val); 6463 } else { 6464 report("non-virtualized and write-only OK", true); 6465 } 6466 } 6467 skip_exit_insn(); 6468 6469 report_prefix_pop(); 6470 } 6471 6472 static enum Config_type configure_virt_x2apic_mode_test( 6473 struct virt_x2apic_mode_config *virt_x2apic_mode_config, 6474 u8 *msr_bitmap_page) 6475 { 6476 int msr; 6477 u32 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6478 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6479 6480 /* x2apic-specific VMCS config */ 6481 if (virt_x2apic_mode_config->use_msr_bitmaps) { 6482 /* virt_x2apic_mode_test() checks for MSR bitmaps support */ 6483 cpu_exec_ctrl0 |= CPU_MSR_BITMAP; 6484 } else { 6485 cpu_exec_ctrl0 &= ~CPU_MSR_BITMAP; 6486 } 6487 6488 if (virt_x2apic_mode_config->virtual_interrupt_delivery) { 6489 if (!(ctrl_cpu_rev[1].clr & CPU_VINTD)) { 6490 report_skip("VM-execution control \"virtual-interrupt delivery\" NOT supported.\n"); 6491 return CONFIG_TYPE_UNSUPPORTED; 6492 } 6493 cpu_exec_ctrl1 |= CPU_VINTD; 6494 } else { 6495 cpu_exec_ctrl1 &= ~CPU_VINTD; 6496 } 6497 6498 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6499 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6500 6501 /* x2APIC MSR intercepts are usually off for "Virtualize x2APIC mode" */ 6502 for (msr = 0x800; msr <= 0x8ff; msr++) { 6503 if (virt_x2apic_mode_config->disable_x2apic_msr_intercepts) { 6504 clear_bit(msr, msr_bitmap_page + 0x000); 6505 clear_bit(msr, msr_bitmap_page + 0x800); 6506 } else { 6507 set_bit(msr, msr_bitmap_page + 0x000); 6508 set_bit(msr, msr_bitmap_page + 0x800); 6509 } 6510 } 6511 6512 /* x2APIC mode can impact virtualization */ 6513 reset_apic(); 6514 if (!virt_x2apic_mode_config->disable_x2apic) 6515 enable_x2apic(); 6516 6517 return configure_apic_reg_virt_test( 6518 &virt_x2apic_mode_config->apic_reg_virt_config); 6519 } 6520 6521 static void virt_x2apic_mode_test(void) 6522 { 6523 u32 *virtual_apic_page; 6524 u8 *msr_bitmap_page; 6525 u64 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6526 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6527 int i; 6528 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6529 6530 if (!cpu_has_apicv()) { 6531 report_skip(__func__); 6532 return; 6533 } 6534 6535 /* 6536 * This is to exercise an issue in KVM's logic to merge L0's and L1's 6537 * MSR bitmaps. Previously, an L1 could get at L0's x2APIC MSRs by 6538 * writing the IA32_SPEC_CTRL MSR or the IA32_PRED_CMD MSRs. KVM would 6539 * then proceed to manipulate the MSR bitmaps, as if VMCS12 had the 6540 * "Virtualize x2APIC mod" control set, even when it didn't. 6541 */ 6542 if (has_spec_ctrl()) 6543 wrmsr(MSR_IA32_SPEC_CTRL, 1); 6544 6545 /* 6546 * Check that VMCS12 supports: 6547 * - "Virtual-APIC address", indicated by "use TPR shadow" 6548 * - "MSR-bitmap address", indicated by "use MSR bitmaps" 6549 */ 6550 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) { 6551 report_skip("VM-execution control \"use TPR shadow\" NOT supported.\n"); 6552 return; 6553 } else if (!(ctrl_cpu_rev[0].clr & CPU_MSR_BITMAP)) { 6554 report_skip("VM-execution control \"use MSR bitmaps\" NOT supported.\n"); 6555 return; 6556 } 6557 6558 test_set_guest(virt_x2apic_mode_guest); 6559 6560 virtual_apic_page = alloc_page(); 6561 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 6562 6563 msr_bitmap_page = alloc_page(); 6564 memset(msr_bitmap_page, 0xff, PAGE_SIZE); 6565 vmcs_write(MSR_BITMAP, virt_to_phys(msr_bitmap_page)); 6566 6567 for (i = 0; i < ARRAY_SIZE(virt_x2apic_mode_tests); i++) { 6568 struct virt_x2apic_mode_test_case *virt_x2apic_mode_test_case = 6569 &virt_x2apic_mode_tests[i]; 6570 struct virt_x2apic_mode_config *virt_x2apic_mode_config = 6571 &virt_x2apic_mode_test_case->virt_x2apic_mode_config; 6572 enum Config_type config_type; 6573 u32 reg; 6574 6575 printf("--- %s test ---\n", virt_x2apic_mode_test_case->name); 6576 config_type = 6577 configure_virt_x2apic_mode_test(virt_x2apic_mode_config, 6578 msr_bitmap_page); 6579 if (config_type == CONFIG_TYPE_UNSUPPORTED) { 6580 report_skip("Skip because of missing features.\n"); 6581 continue; 6582 } else if (config_type == CONFIG_TYPE_VMENTRY_FAILS_EARLY) { 6583 enter_guest_with_bad_controls(); 6584 continue; 6585 } 6586 6587 for (reg = 0; reg < PAGE_SIZE / sizeof(u32); reg += 0x10) { 6588 struct virt_x2apic_mode_expectation expectation; 6589 6590 virt_x2apic_mode_exit_expectation( 6591 reg, virt_x2apic_mode_config, &expectation); 6592 6593 test_x2apic_rd(reg, &expectation, virtual_apic_page); 6594 test_x2apic_wr(reg, &expectation, virtual_apic_page); 6595 } 6596 } 6597 6598 6599 /* Terminate the guest */ 6600 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6601 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6602 args->op = X2APIC_TERMINATE; 6603 enter_guest(); 6604 assert_exit_reason(VMX_VMCALL); 6605 } 6606 6607 /* 6608 * On processors that support Intel 64 architecture, the IA32_SYSENTER_ESP 6609 * field and the IA32_SYSENTER_EIP field must each contain a canonical 6610 * address. 6611 * 6612 * [Intel SDM] 6613 */ 6614 static void test_sysenter_field(u32 field, const char *name) 6615 { 6616 u64 addr_saved = vmcs_read(field); 6617 6618 vmcs_write(field, NONCANONICAL); 6619 report_prefix_pushf("%s non-canonical", name); 6620 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, false); 6621 report_prefix_pop(); 6622 6623 vmcs_write(field, 0xffffffff); 6624 report_prefix_pushf("%s canonical", name); 6625 test_vmx_vmlaunch(0, false); 6626 report_prefix_pop(); 6627 6628 vmcs_write(field, addr_saved); 6629 } 6630 6631 static void test_ctl_reg(const char *cr_name, u64 cr, u64 fixed0, u64 fixed1) 6632 { 6633 u64 val; 6634 u64 cr_saved = vmcs_read(cr); 6635 int i; 6636 6637 val = fixed0 & fixed1; 6638 if (cr == HOST_CR4) 6639 vmcs_write(cr, val | X86_CR4_PAE); 6640 else 6641 vmcs_write(cr, val); 6642 report_prefix_pushf("%s %lx", cr_name, val); 6643 if (val == fixed0) 6644 test_vmx_vmlaunch(0, false); 6645 else 6646 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, 6647 false); 6648 report_prefix_pop(); 6649 6650 for (i = 0; i < 64; i++) { 6651 6652 /* Set a bit when the corresponding bit in fixed1 is 0 */ 6653 if ((fixed1 & (1ull << i)) == 0) { 6654 if (cr == HOST_CR4 && ((1ull << i) & X86_CR4_SMEP || 6655 (1ull << i) & X86_CR4_SMAP)) 6656 continue; 6657 6658 vmcs_write(cr, cr_saved | (1ull << i)); 6659 report_prefix_pushf("%s %llx", cr_name, 6660 cr_saved | (1ull << i)); 6661 test_vmx_vmlaunch( 6662 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, 6663 false); 6664 report_prefix_pop(); 6665 } 6666 6667 /* Unset a bit when the corresponding bit in fixed0 is 1 */ 6668 if (fixed0 & (1ull << i)) { 6669 vmcs_write(cr, cr_saved & ~(1ull << i)); 6670 report_prefix_pushf("%s %llx", cr_name, 6671 cr_saved & ~(1ull << i)); 6672 test_vmx_vmlaunch( 6673 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, 6674 false); 6675 report_prefix_pop(); 6676 } 6677 } 6678 6679 vmcs_write(cr, cr_saved); 6680 } 6681 6682 /* 6683 * 1. The CR0 field must not set any bit to a value not supported in VMX 6684 * operation. 6685 * 2. The CR4 field must not set any bit to a value not supported in VMX 6686 * operation. 6687 * 3. On processors that support Intel 64 architecture, the CR3 field must 6688 * be such that bits 63:52 and bits in the range 51:32 beyond the 6689 * processor’s physical-address width must be 0. 6690 * 6691 * [Intel SDM] 6692 */ 6693 static void test_host_ctl_regs(void) 6694 { 6695 u64 fixed0, fixed1, cr3, cr3_saved; 6696 int i; 6697 6698 /* Test CR0 */ 6699 fixed0 = rdmsr(MSR_IA32_VMX_CR0_FIXED0); 6700 fixed1 = rdmsr(MSR_IA32_VMX_CR0_FIXED1); 6701 test_ctl_reg("HOST_CR0", HOST_CR0, fixed0, fixed1); 6702 6703 /* Test CR4 */ 6704 fixed0 = rdmsr(MSR_IA32_VMX_CR4_FIXED0); 6705 fixed1 = rdmsr(MSR_IA32_VMX_CR4_FIXED1) & 6706 ~(X86_CR4_SMEP | X86_CR4_SMAP); 6707 test_ctl_reg("HOST_CR4", HOST_CR4, fixed0, fixed1); 6708 6709 /* Test CR3 */ 6710 cr3_saved = vmcs_read(HOST_CR3); 6711 for (i = cpuid_maxphyaddr(); i < 64; i++) { 6712 cr3 = cr3_saved | (1ul << i); 6713 vmcs_write(HOST_CR3, cr3); 6714 report_prefix_pushf("HOST_CR3 %lx", cr3); 6715 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, 6716 false); 6717 report_prefix_pop(); 6718 } 6719 6720 vmcs_write(HOST_CR3, cr3_saved); 6721 } 6722 6723 static void test_efer_bit(u32 fld, const char * fld_name, u32 ctrl_fld, 6724 u64 ctrl_bit, u64 efer_bit, 6725 const char *efer_bit_name) 6726 { 6727 u64 efer_saved = vmcs_read(fld); 6728 u32 ctrl_saved = vmcs_read(ctrl_fld); 6729 u64 host_addr_size = ctrl_saved & EXI_HOST_64; 6730 u64 efer; 6731 6732 vmcs_write(ctrl_fld, ctrl_saved & ~ctrl_bit); 6733 efer = efer_saved & ~efer_bit; 6734 vmcs_write(fld, efer); 6735 report_prefix_pushf("%s bit turned off, %s %lx", efer_bit_name, 6736 fld_name, efer); 6737 test_vmx_vmlaunch(0, false); 6738 report_prefix_pop(); 6739 6740 efer = efer_saved | efer_bit; 6741 vmcs_write(fld, efer); 6742 report_prefix_pushf("%s bit turned on, %s %lx", efer_bit_name, 6743 fld_name, efer); 6744 test_vmx_vmlaunch(0, false); 6745 report_prefix_pop(); 6746 6747 vmcs_write(ctrl_fld, ctrl_saved | ctrl_bit); 6748 efer = efer_saved & ~efer_bit; 6749 vmcs_write(fld, efer); 6750 report_prefix_pushf("%s bit turned off, %s %lx", efer_bit_name, 6751 fld_name, efer); 6752 if (host_addr_size) 6753 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, 6754 false); 6755 else 6756 test_vmx_vmlaunch(0, false); 6757 report_prefix_pop(); 6758 6759 efer = efer_saved | efer_bit; 6760 vmcs_write(fld, efer); 6761 report_prefix_pushf("%s bit turned on, %s %lx", efer_bit_name, 6762 fld_name, efer); 6763 if (host_addr_size) 6764 test_vmx_vmlaunch(0, false); 6765 else 6766 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, 6767 false); 6768 report_prefix_pop(); 6769 6770 vmcs_write(ctrl_fld, ctrl_saved); 6771 vmcs_write(fld, efer_saved); 6772 } 6773 6774 static void test_efer(u32 fld, const char * fld_name, u32 ctrl_fld, 6775 u64 ctrl_bit) 6776 { 6777 u64 efer_saved = vmcs_read(fld); 6778 u32 ctrl_saved = vmcs_read(ctrl_fld); 6779 u64 efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 6780 u64 i; 6781 u64 efer; 6782 6783 if (cpu_has_efer_nx()) 6784 efer_reserved_bits &= ~EFER_NX; 6785 6786 /* 6787 * Check reserved bits 6788 */ 6789 vmcs_write(ctrl_fld, ctrl_saved & ~ctrl_bit); 6790 for (i = 0; i < 64; i++) { 6791 if ((1ull << i) & efer_reserved_bits) { 6792 efer = efer_saved | (1ull << i); 6793 vmcs_write(fld, efer); 6794 report_prefix_pushf("%s %lx", fld_name, efer); 6795 test_vmx_vmlaunch(0, false); 6796 report_prefix_pop(); 6797 } 6798 } 6799 6800 vmcs_write(ctrl_fld, ctrl_saved | ctrl_bit); 6801 for (i = 0; i < 64; i++) { 6802 if ((1ull << i) & efer_reserved_bits) { 6803 efer = efer_saved | (1ull << i); 6804 vmcs_write(fld, efer); 6805 report_prefix_pushf("%s %lx", fld_name, efer); 6806 test_vmx_vmlaunch( 6807 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, 6808 false); 6809 report_prefix_pop(); 6810 } 6811 } 6812 6813 vmcs_write(ctrl_fld, ctrl_saved); 6814 vmcs_write(fld, efer_saved); 6815 6816 /* 6817 * Check LMA and LME bits 6818 */ 6819 test_efer_bit(fld, fld_name, ctrl_fld, ctrl_bit, EFER_LMA, 6820 "EFER_LMA"); 6821 test_efer_bit(fld, fld_name, ctrl_fld, ctrl_bit, EFER_LME, 6822 "EFER_LME"); 6823 } 6824 6825 /* 6826 * If the “load IA32_EFER†VM-exit control is 1, bits reserved in the 6827 * IA32_EFER MSR must be 0 in the field for that register. In addition, 6828 * the values of the LMA and LME bits in the field must each be that of 6829 * the “host address-space size†VM-exit control. 6830 * 6831 * [Intel SDM] 6832 */ 6833 static void test_host_efer(void) 6834 { 6835 if (!(ctrl_exit_rev.clr & EXI_LOAD_EFER)) { 6836 printf("\"Load-IA32-EFER\" exit control not supported\n"); 6837 return; 6838 } 6839 6840 test_efer(HOST_EFER, "HOST_EFER", EXI_CONTROLS, EXI_LOAD_EFER); 6841 } 6842 6843 /* 6844 * PAT values higher than 8 are uninteresting since they're likely lumped 6845 * in with "8". We only test values above 8 one bit at a time, 6846 * in order to reduce the number of VM-Entries and keep the runtime reasonable. 6847 */ 6848 #define PAT_VAL_LIMIT 8 6849 6850 static void test_pat(u32 field, const char * field_name, u32 ctrl_field, 6851 u64 ctrl_bit) 6852 { 6853 u32 ctrl_saved = vmcs_read(ctrl_field); 6854 u64 pat_saved = vmcs_read(field); 6855 u64 i, val; 6856 u32 j; 6857 int error; 6858 6859 vmcs_clear_bits(ctrl_field, ctrl_bit); 6860 if (field == GUEST_PAT) { 6861 vmx_set_test_stage(1); 6862 test_set_guest(guest_state_test_main); 6863 } 6864 6865 for (i = 0; i < 256; i = (i < PAT_VAL_LIMIT) ? i + 1 : i * 2) { 6866 /* Test PAT0..PAT7 fields */ 6867 for (j = 0; j < (i ? 8 : 1); j++) { 6868 val = i << j * 8; 6869 vmcs_write(field, val); 6870 if (field == HOST_PAT) { 6871 report_prefix_pushf("%s %lx", field_name, val); 6872 test_vmx_vmlaunch(0, false); 6873 report_prefix_pop(); 6874 6875 } else { // GUEST_PAT 6876 enter_guest(); 6877 report_guest_state_test("ENT_LOAD_PAT enabled", 6878 VMX_VMCALL, val, 6879 "GUEST_PAT"); 6880 } 6881 } 6882 } 6883 6884 vmcs_set_bits(ctrl_field, ctrl_bit); 6885 for (i = 0; i < 256; i = (i < PAT_VAL_LIMIT) ? i + 1 : i * 2) { 6886 /* Test PAT0..PAT7 fields */ 6887 for (j = 0; j < (i ? 8 : 1); j++) { 6888 val = i << j * 8; 6889 vmcs_write(field, val); 6890 6891 if (field == HOST_PAT) { 6892 report_prefix_pushf("%s %lx", field_name, val); 6893 if (i == 0x2 || i == 0x3 || i >= 0x8) 6894 error = 6895 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD; 6896 else 6897 error = 0; 6898 6899 test_vmx_vmlaunch(error, false); 6900 report_prefix_pop(); 6901 6902 } else { // GUEST_PAT 6903 if (i == 0x2 || i == 0x3 || i >= 0x8) { 6904 enter_guest_with_invalid_guest_state(); 6905 report_guest_state_test("ENT_LOAD_PAT " 6906 "enabled", 6907 VMX_FAIL_STATE | VMX_ENTRY_FAILURE, 6908 val, 6909 "GUEST_PAT"); 6910 } else { 6911 enter_guest(); 6912 report_guest_state_test("ENT_LOAD_PAT " 6913 "enabled", 6914 VMX_VMCALL, 6915 val, 6916 "GUEST_PAT"); 6917 } 6918 } 6919 6920 } 6921 } 6922 6923 if (field == GUEST_PAT) { 6924 /* 6925 * Let the guest finish execution 6926 */ 6927 vmx_set_test_stage(2); 6928 vmcs_write(field, pat_saved); 6929 enter_guest(); 6930 } 6931 6932 vmcs_write(ctrl_field, ctrl_saved); 6933 vmcs_write(field, pat_saved); 6934 } 6935 6936 /* 6937 * If the "load IA32_PAT" VM-exit control is 1, the value of the field 6938 * for the IA32_PAT MSR must be one that could be written by WRMSR 6939 * without fault at CPL 0. Specifically, each of the 8 bytes in the 6940 * field must have one of the values 0 (UC), 1 (WC), 4 (WT), 5 (WP), 6941 * 6 (WB), or 7 (UC-). 6942 * 6943 * [Intel SDM] 6944 */ 6945 static void test_load_host_pat(void) 6946 { 6947 /* 6948 * "load IA32_PAT" VM-exit control 6949 */ 6950 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) { 6951 printf("\"Load-IA32-PAT\" exit control not supported\n"); 6952 return; 6953 } 6954 6955 test_pat(HOST_PAT, "HOST_PAT", EXI_CONTROLS, EXI_LOAD_PAT); 6956 } 6957 6958 /* 6959 * test_vmcs_field - test a value for the given VMCS field 6960 * @field: VMCS field 6961 * @field_name: string name of VMCS field 6962 * @bit_start: starting bit 6963 * @bit_end: ending bit 6964 * @val: value that the bit range must or must not contain 6965 * @valid_val: whether value given in 'val' must be valid or not 6966 * @error: expected VMCS error when vmentry fails for an invalid value 6967 */ 6968 static void test_vmcs_field(u64 field, const char *field_name, u32 bit_start, 6969 u32 bit_end, u64 val, bool valid_val, u32 error) 6970 { 6971 u64 field_saved = vmcs_read(field); 6972 u32 i; 6973 u64 tmp; 6974 u32 bit_on; 6975 u64 mask = ~0ull; 6976 6977 mask = (mask >> bit_end) << bit_end; 6978 mask = mask | ((1 << bit_start) - 1); 6979 tmp = (field_saved & mask) | (val << bit_start); 6980 6981 vmcs_write(field, tmp); 6982 report_prefix_pushf("%s %lx", field_name, tmp); 6983 if (valid_val) 6984 test_vmx_vmlaunch(0, false); 6985 else 6986 test_vmx_vmlaunch(error, false); 6987 report_prefix_pop(); 6988 6989 for (i = bit_start; i <= bit_end; i = i + 2) { 6990 bit_on = ((1ull < i) & (val << bit_start)) ? 0 : 1; 6991 if (bit_on) 6992 tmp = field_saved | (1ull << i); 6993 else 6994 tmp = field_saved & ~(1ull << i); 6995 vmcs_write(field, tmp); 6996 report_prefix_pushf("%s %lx", field_name, tmp); 6997 if (valid_val) 6998 test_vmx_vmlaunch(error, false); 6999 else 7000 test_vmx_vmlaunch(0, false); 7001 report_prefix_pop(); 7002 } 7003 7004 vmcs_write(field, field_saved); 7005 } 7006 7007 static void test_canonical(u64 field, const char * field_name) 7008 { 7009 u64 addr_saved = vmcs_read(field); 7010 7011 report_prefix_pushf("%s %lx", field_name, addr_saved); 7012 if (is_canonical(addr_saved)) { 7013 test_vmx_vmlaunch(0, false); 7014 report_prefix_pop(); 7015 7016 vmcs_write(field, NONCANONICAL); 7017 report_prefix_pushf("%s %llx", field_name, NONCANONICAL); 7018 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, 7019 false); 7020 7021 vmcs_write(field, addr_saved); 7022 } else { 7023 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, 7024 false); 7025 } 7026 report_prefix_pop(); 7027 } 7028 7029 #define TEST_RPL_TI_FLAGS(reg, name) \ 7030 test_vmcs_field(reg, name, 0, 2, 0x0, true, \ 7031 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7032 7033 #define TEST_CS_TR_FLAGS(reg, name) \ 7034 test_vmcs_field(reg, name, 3, 15, 0x0000, false, \ 7035 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7036 7037 /* 7038 * 1. In the selector field for each of CS, SS, DS, ES, FS, GS and TR, the 7039 * RPL (bits 1:0) and the TI flag (bit 2) must be 0. 7040 * 2. The selector fields for CS and TR cannot be 0000H. 7041 * 3. The selector field for SS cannot be 0000H if the "host address-space 7042 * size" VM-exit control is 0. 7043 * 4. On processors that support Intel 64 architecture, the base-address 7044 * fields for FS, GS and TR must contain canonical addresses. 7045 */ 7046 static void test_host_segment_regs(void) 7047 { 7048 u16 selector_saved; 7049 7050 /* 7051 * Test RPL and TI flags 7052 */ 7053 TEST_RPL_TI_FLAGS(HOST_SEL_CS, "HOST_SEL_CS"); 7054 TEST_RPL_TI_FLAGS(HOST_SEL_SS, "HOST_SEL_SS"); 7055 TEST_RPL_TI_FLAGS(HOST_SEL_DS, "HOST_SEL_DS"); 7056 TEST_RPL_TI_FLAGS(HOST_SEL_ES, "HOST_SEL_ES"); 7057 TEST_RPL_TI_FLAGS(HOST_SEL_FS, "HOST_SEL_FS"); 7058 TEST_RPL_TI_FLAGS(HOST_SEL_GS, "HOST_SEL_GS"); 7059 TEST_RPL_TI_FLAGS(HOST_SEL_TR, "HOST_SEL_TR"); 7060 7061 /* 7062 * Test that CS and TR fields can not be 0x0000 7063 */ 7064 TEST_CS_TR_FLAGS(HOST_SEL_CS, "HOST_SEL_CS"); 7065 TEST_CS_TR_FLAGS(HOST_SEL_TR, "HOST_SEL_TR"); 7066 7067 /* 7068 * SS field can not be 0x0000 if "host address-space size" VM-exit 7069 * control is 0 7070 */ 7071 selector_saved = vmcs_read(HOST_SEL_SS); 7072 vmcs_write(HOST_SEL_SS, 0); 7073 report_prefix_pushf("HOST_SEL_SS 0"); 7074 if (vmcs_read(EXI_CONTROLS) & EXI_HOST_64) { 7075 test_vmx_vmlaunch(0, false); 7076 } else { 7077 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, false); 7078 } 7079 report_prefix_pop(); 7080 7081 vmcs_write(HOST_SEL_SS, selector_saved); 7082 7083 #ifdef __x86_64__ 7084 /* 7085 * Base address for FS, GS and TR must be canonical 7086 */ 7087 test_canonical(HOST_BASE_FS, "HOST_BASE_FS"); 7088 test_canonical(HOST_BASE_GS, "HOST_BASE_GS"); 7089 test_canonical(HOST_BASE_TR, "HOST_BASE_TR"); 7090 #endif 7091 } 7092 7093 /* 7094 * On processors that support Intel 64 architecture, the base-address 7095 * fields for GDTR and IDTR must contain canonical addresses. 7096 */ 7097 static void test_host_desc_tables(void) 7098 { 7099 #ifdef __x86_64__ 7100 test_canonical(HOST_BASE_GDTR, "HOST_BASE_GDTR"); 7101 test_canonical(HOST_BASE_IDTR, "HOST_BASE_IDTR"); 7102 #endif 7103 } 7104 7105 /* 7106 * If the "host address-space size" VM-exit control is 0, the following must 7107 * hold: 7108 * - The "IA-32e mode guest" VM-entry control is 0. 7109 * - Bit 17 of the CR4 field (corresponding to CR4.PCIDE) is 0. 7110 * - Bits 63:32 in the RIP field are 0. 7111 * 7112 * If the "host address-space size" VM-exit control is 1, the following must 7113 * hold: 7114 * - Bit 5 of the CR4 field (corresponding to CR4.PAE) is 1. 7115 * - The RIP field contains a canonical address. 7116 * 7117 */ 7118 static void test_host_addr_size(void) 7119 { 7120 u64 cr4_saved = vmcs_read(HOST_CR4); 7121 u64 rip_saved = vmcs_read(HOST_RIP); 7122 u64 entry_ctrl_saved = vmcs_read(ENT_CONTROLS); 7123 int i; 7124 u64 tmp; 7125 7126 if (vmcs_read(EXI_CONTROLS) & EXI_HOST_64) { 7127 vmcs_write(ENT_CONTROLS, entry_ctrl_saved | ENT_GUEST_64); 7128 report_prefix_pushf("\"IA-32e mode guest\" enabled"); 7129 test_vmx_vmlaunch(0, false); 7130 report_prefix_pop(); 7131 7132 vmcs_write(HOST_CR4, cr4_saved | X86_CR4_PCIDE); 7133 report_prefix_pushf("\"CR4.PCIDE\" set"); 7134 test_vmx_vmlaunch(0, false); 7135 report_prefix_pop(); 7136 7137 for (i = 32; i <= 63; i = i + 4) { 7138 tmp = rip_saved | 1ull << i; 7139 vmcs_write(HOST_RIP, tmp); 7140 report_prefix_pushf("HOST_RIP %lx", tmp); 7141 test_vmx_vmlaunch(0, false); 7142 report_prefix_pop(); 7143 } 7144 7145 if (cr4_saved & X86_CR4_PAE) { 7146 vmcs_write(HOST_CR4, cr4_saved & ~X86_CR4_PAE); 7147 report_prefix_pushf("\"CR4.PAE\" unset"); 7148 test_vmx_vmlaunch( 7149 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, false); 7150 } else { 7151 report_prefix_pushf("\"CR4.PAE\" set"); 7152 test_vmx_vmlaunch(0, false); 7153 } 7154 report_prefix_pop(); 7155 7156 vmcs_write(HOST_RIP, NONCANONICAL); 7157 report_prefix_pushf("HOST_RIP %llx", NONCANONICAL); 7158 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, false); 7159 report_prefix_pop(); 7160 7161 vmcs_write(ENT_CONTROLS, entry_ctrl_saved | ENT_GUEST_64); 7162 vmcs_write(HOST_RIP, rip_saved); 7163 vmcs_write(HOST_CR4, cr4_saved); 7164 } 7165 } 7166 7167 /* 7168 * Check that the virtual CPU checks the VMX Host State Area as 7169 * documented in the Intel SDM. 7170 */ 7171 static void vmx_host_state_area_test(void) 7172 { 7173 /* 7174 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 7175 * fail due to invalid guest state, should we make it that 7176 * far. 7177 */ 7178 vmcs_write(GUEST_RFLAGS, 0); 7179 7180 test_host_ctl_regs(); 7181 7182 test_sysenter_field(HOST_SYSENTER_ESP, "HOST_SYSENTER_ESP"); 7183 test_sysenter_field(HOST_SYSENTER_EIP, "HOST_SYSENTER_EIP"); 7184 7185 test_host_efer(); 7186 test_load_host_pat(); 7187 test_host_segment_regs(); 7188 test_host_desc_tables(); 7189 test_host_addr_size(); 7190 } 7191 7192 /* 7193 * If the "load IA32_PAT" VM-entry control is 1, the value of the field 7194 * for the IA32_PAT MSR must be one that could be written by WRMSR 7195 * without fault at CPL 0. Specifically, each of the 8 bytes in the 7196 * field must have one of the values 0 (UC), 1 (WC), 4 (WT), 5 (WP), 7197 * 6 (WB), or 7 (UC-). 7198 * 7199 * [Intel SDM] 7200 */ 7201 static void test_load_guest_pat(void) 7202 { 7203 /* 7204 * "load IA32_PAT" VM-entry control 7205 */ 7206 if (!(ctrl_exit_rev.clr & ENT_LOAD_PAT)) { 7207 printf("\"Load-IA32-PAT\" entry control not supported\n"); 7208 return; 7209 } 7210 7211 test_pat(GUEST_PAT, "GUEST_PAT", ENT_CONTROLS, ENT_LOAD_PAT); 7212 } 7213 7214 /* 7215 * Check that the virtual CPU checks the VMX Guest State Area as 7216 * documented in the Intel SDM. 7217 */ 7218 static void vmx_guest_state_area_test(void) 7219 { 7220 test_load_guest_pat(); 7221 } 7222 7223 static bool valid_vmcs_for_vmentry(void) 7224 { 7225 struct vmcs *current_vmcs = NULL; 7226 7227 if (vmcs_save(¤t_vmcs)) 7228 return false; 7229 7230 return current_vmcs && !current_vmcs->hdr.shadow_vmcs; 7231 } 7232 7233 static void try_vmentry_in_movss_shadow(void) 7234 { 7235 u32 vm_inst_err; 7236 u32 flags; 7237 bool early_failure = false; 7238 u32 expected_flags = X86_EFLAGS_FIXED; 7239 bool valid_vmcs = valid_vmcs_for_vmentry(); 7240 7241 expected_flags |= valid_vmcs ? X86_EFLAGS_ZF : X86_EFLAGS_CF; 7242 7243 /* 7244 * Indirectly set VM_INST_ERR to 12 ("VMREAD/VMWRITE from/to 7245 * unsupported VMCS component"). 7246 */ 7247 vmcs_write(~0u, 0); 7248 7249 __asm__ __volatile__ ("mov %[host_rsp], %%edx;" 7250 "vmwrite %%rsp, %%rdx;" 7251 "mov 0f, %%rax;" 7252 "mov %[host_rip], %%edx;" 7253 "vmwrite %%rax, %%rdx;" 7254 "mov $-1, %%ah;" 7255 "sahf;" 7256 "mov %%ss, %%ax;" 7257 "mov %%ax, %%ss;" 7258 "vmlaunch;" 7259 "mov $1, %[early_failure];" 7260 "0: lahf;" 7261 "movzbl %%ah, %[flags]" 7262 : [early_failure] "+r" (early_failure), 7263 [flags] "=&a" (flags) 7264 : [host_rsp] "i" (HOST_RSP), 7265 [host_rip] "i" (HOST_RIP) 7266 : "rdx", "cc", "memory"); 7267 vm_inst_err = vmcs_read(VMX_INST_ERROR); 7268 7269 report("Early VM-entry failure", early_failure); 7270 report("RFLAGS[8:0] is %x (actual %x)", flags == expected_flags, 7271 expected_flags, flags); 7272 if (valid_vmcs) 7273 report("VM-instruction error is %d (actual %d)", 7274 vm_inst_err == VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, 7275 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, vm_inst_err); 7276 } 7277 7278 static void vmentry_movss_shadow_test(void) 7279 { 7280 struct vmcs *orig_vmcs; 7281 7282 TEST_ASSERT(!vmcs_save(&orig_vmcs)); 7283 7284 /* 7285 * Set the launched flag on the current VMCS to verify the correct 7286 * error priority, below. 7287 */ 7288 test_set_guest(v2_null_test_guest); 7289 enter_guest(); 7290 7291 /* 7292 * With bit 1 of the guest's RFLAGS clear, VM-entry should 7293 * fail due to invalid guest state (if we make it that far). 7294 */ 7295 vmcs_write(GUEST_RFLAGS, 0); 7296 7297 /* 7298 * "VM entry with events blocked by MOV SS" takes precedence over 7299 * "VMLAUNCH with non-clear VMCS." 7300 */ 7301 report_prefix_push("valid current-VMCS"); 7302 try_vmentry_in_movss_shadow(); 7303 report_prefix_pop(); 7304 7305 /* 7306 * VMfailInvalid takes precedence over "VM entry with events 7307 * blocked by MOV SS." 7308 */ 7309 TEST_ASSERT(!vmcs_clear(orig_vmcs)); 7310 report_prefix_push("no current-VMCS"); 7311 try_vmentry_in_movss_shadow(); 7312 report_prefix_pop(); 7313 7314 TEST_ASSERT(!make_vmcs_current(orig_vmcs)); 7315 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 7316 } 7317 7318 static void vmx_cr_load_test(void) 7319 { 7320 unsigned long cr3, cr4, orig_cr3, orig_cr4; 7321 7322 orig_cr4 = read_cr4(); 7323 orig_cr3 = read_cr3(); 7324 7325 if (!this_cpu_has(X86_FEATURE_PCID)) { 7326 report_skip("PCID not detected"); 7327 return; 7328 } 7329 if (!this_cpu_has(X86_FEATURE_MCE)) { 7330 report_skip("MCE not detected"); 7331 return; 7332 } 7333 7334 TEST_ASSERT(!(orig_cr3 & X86_CR3_PCID_MASK)); 7335 7336 /* Enable PCID for L1. */ 7337 cr4 = orig_cr4 | X86_CR4_PCIDE; 7338 cr3 = orig_cr3 | 0x1; 7339 TEST_ASSERT(!write_cr4_checking(cr4)); 7340 write_cr3(cr3); 7341 7342 test_set_guest(v2_null_test_guest); 7343 vmcs_write(HOST_CR4, cr4); 7344 vmcs_write(HOST_CR3, cr3); 7345 enter_guest(); 7346 7347 /* 7348 * No exception is expected. 7349 * 7350 * NB. KVM loads the last guest write to CR4 into CR4 read 7351 * shadow. In order to trigger an exit to KVM, we can toggle a 7352 * bit that is owned by KVM. We use CR4.MCE, which shall 7353 * have no side effect because normally no guest MCE (e.g., as the 7354 * result of bad memory) would happen during this test. 7355 */ 7356 TEST_ASSERT(!write_cr4_checking(cr4 ^ X86_CR4_MCE)); 7357 7358 /* Cleanup L1 state. */ 7359 write_cr3(orig_cr3); 7360 TEST_ASSERT(!write_cr4_checking(orig_cr4)); 7361 } 7362 7363 static void vmx_nm_test_guest(void) 7364 { 7365 write_cr0(read_cr0() | X86_CR0_TS); 7366 asm volatile("fnop"); 7367 } 7368 7369 static void check_nm_exit(const char *test) 7370 { 7371 u32 reason = vmcs_read(EXI_REASON); 7372 u32 intr_info = vmcs_read(EXI_INTR_INFO); 7373 const u32 expected = INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 7374 NM_VECTOR; 7375 7376 report("%s", reason == VMX_EXC_NMI && intr_info == expected, test); 7377 } 7378 7379 /* 7380 * This test checks that: 7381 * 7382 * (a) If L2 launches with CR0.TS clear, but later sets CR0.TS, then 7383 * a subsequent #NM VM-exit is reflected to L1. 7384 * 7385 * (b) If L2 launches with CR0.TS clear and CR0.EM set, then a 7386 * subsequent #NM VM-exit is reflected to L1. 7387 */ 7388 static void vmx_nm_test(void) 7389 { 7390 unsigned long cr0 = read_cr0(); 7391 7392 test_set_guest(vmx_nm_test_guest); 7393 7394 /* 7395 * L1 wants to intercept #NM exceptions encountered in L2. 7396 */ 7397 vmcs_write(EXC_BITMAP, 1 << NM_VECTOR); 7398 7399 /* 7400 * Launch L2 with CR0.TS clear, but don't claim host ownership of 7401 * any CR0 bits. L2 will set CR0.TS and then try to execute fnop, 7402 * which will raise #NM. L0 should reflect the #NM VM-exit to L1. 7403 */ 7404 vmcs_write(CR0_MASK, 0); 7405 vmcs_write(GUEST_CR0, cr0 & ~X86_CR0_TS); 7406 enter_guest(); 7407 check_nm_exit("fnop with CR0.TS set in L2 triggers #NM VM-exit to L1"); 7408 7409 /* 7410 * Re-enter L2 at the fnop instruction, with CR0.TS clear but 7411 * CR0.EM set. The fnop will still raise #NM, and L0 should 7412 * reflect the #NM VM-exit to L1. 7413 */ 7414 vmcs_write(GUEST_CR0, (cr0 & ~X86_CR0_TS) | X86_CR0_EM); 7415 enter_guest(); 7416 check_nm_exit("fnop with CR0.EM set in L2 triggers #NM VM-exit to L1"); 7417 7418 /* 7419 * Re-enter L2 at the fnop instruction, with both CR0.TS and 7420 * CR0.EM clear. There will be no #NM, and the L2 guest should 7421 * exit normally. 7422 */ 7423 vmcs_write(GUEST_CR0, cr0 & ~(X86_CR0_TS | X86_CR0_EM)); 7424 enter_guest(); 7425 } 7426 7427 bool vmx_pending_event_ipi_fired; 7428 static void vmx_pending_event_ipi_isr(isr_regs_t *regs) 7429 { 7430 vmx_pending_event_ipi_fired = true; 7431 eoi(); 7432 } 7433 7434 bool vmx_pending_event_guest_run; 7435 static void vmx_pending_event_guest(void) 7436 { 7437 vmcall(); 7438 vmx_pending_event_guest_run = true; 7439 } 7440 7441 static void vmx_pending_event_test_core(bool guest_hlt) 7442 { 7443 int ipi_vector = 0xf1; 7444 7445 vmx_pending_event_ipi_fired = false; 7446 handle_irq(ipi_vector, vmx_pending_event_ipi_isr); 7447 7448 vmx_pending_event_guest_run = false; 7449 test_set_guest(vmx_pending_event_guest); 7450 7451 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 7452 7453 enter_guest(); 7454 skip_exit_vmcall(); 7455 7456 if (guest_hlt) 7457 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 7458 7459 irq_disable(); 7460 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | 7461 APIC_DM_FIXED | ipi_vector, 7462 0); 7463 7464 enter_guest(); 7465 7466 assert_exit_reason(VMX_EXTINT); 7467 report("Guest did not run before host received IPI", 7468 !vmx_pending_event_guest_run); 7469 7470 irq_enable(); 7471 asm volatile ("nop"); 7472 irq_disable(); 7473 report("Got pending interrupt after IRQ enabled", 7474 vmx_pending_event_ipi_fired); 7475 7476 if (guest_hlt) 7477 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 7478 7479 enter_guest(); 7480 report("Guest finished running when no interrupt", 7481 vmx_pending_event_guest_run); 7482 } 7483 7484 static void vmx_pending_event_test(void) 7485 { 7486 vmx_pending_event_test_core(false); 7487 } 7488 7489 static void vmx_pending_event_hlt_test(void) 7490 { 7491 vmx_pending_event_test_core(true); 7492 } 7493 7494 static int vmx_window_test_db_count; 7495 7496 static void vmx_window_test_db_handler(struct ex_regs *regs) 7497 { 7498 vmx_window_test_db_count++; 7499 } 7500 7501 static void vmx_nmi_window_test_guest(void) 7502 { 7503 handle_exception(DB_VECTOR, vmx_window_test_db_handler); 7504 7505 asm volatile("vmcall\n\t" 7506 "nop\n\t"); 7507 7508 handle_exception(DB_VECTOR, NULL); 7509 } 7510 7511 static void verify_nmi_window_exit(u64 rip) 7512 { 7513 u32 exit_reason = vmcs_read(EXI_REASON); 7514 7515 report("Exit reason (%d) is 'NMI window'", 7516 exit_reason == VMX_NMI_WINDOW, exit_reason); 7517 report("RIP (%#lx) is %#lx", vmcs_read(GUEST_RIP) == rip, 7518 vmcs_read(GUEST_RIP), rip); 7519 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 7520 } 7521 7522 static void vmx_nmi_window_test(void) 7523 { 7524 u64 nop_addr; 7525 void *db_fault_addr = get_idt_addr(&boot_idt[DB_VECTOR]); 7526 7527 if (!(ctrl_pin_rev.clr & PIN_VIRT_NMI)) { 7528 report_skip("CPU does not support the \"Virtual NMIs\" VM-execution control."); 7529 return; 7530 } 7531 7532 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 7533 report_skip("CPU does not support the \"NMI-window exiting\" VM-execution control."); 7534 return; 7535 } 7536 7537 vmx_window_test_db_count = 0; 7538 7539 report_prefix_push("NMI-window"); 7540 test_set_guest(vmx_nmi_window_test_guest); 7541 vmcs_set_bits(PIN_CONTROLS, PIN_VIRT_NMI); 7542 enter_guest(); 7543 skip_exit_vmcall(); 7544 nop_addr = vmcs_read(GUEST_RIP); 7545 7546 /* 7547 * Ask for "NMI-window exiting," and expect an immediate VM-exit. 7548 * RIP will not advance. 7549 */ 7550 report_prefix_push("active, no blocking"); 7551 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 7552 enter_guest(); 7553 verify_nmi_window_exit(nop_addr); 7554 report_prefix_pop(); 7555 7556 /* 7557 * Ask for "NMI-window exiting" in a MOV-SS shadow, and expect 7558 * a VM-exit on the next instruction after the nop. (The nop 7559 * is one byte.) 7560 */ 7561 report_prefix_push("active, blocking by MOV-SS"); 7562 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 7563 enter_guest(); 7564 verify_nmi_window_exit(nop_addr + 1); 7565 report_prefix_pop(); 7566 7567 /* 7568 * Ask for "NMI-window exiting" (with event injection), and 7569 * expect a VM-exit after the event is injected. (RIP should 7570 * be at the address specified in the IDT entry for #DB.) 7571 */ 7572 report_prefix_push("active, no blocking, injecting #DB"); 7573 vmcs_write(ENT_INTR_INFO, 7574 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 7575 enter_guest(); 7576 verify_nmi_window_exit((u64)db_fault_addr); 7577 report_prefix_pop(); 7578 7579 /* 7580 * Ask for "NMI-window exiting" with NMI blocking, and expect 7581 * a VM-exit after the next IRET (i.e. after the #DB handler 7582 * returns). So, RIP should be back at one byte past the nop. 7583 */ 7584 report_prefix_push("active, blocking by NMI"); 7585 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_NMI); 7586 enter_guest(); 7587 verify_nmi_window_exit(nop_addr + 1); 7588 report("#DB handler executed once (actual %d times)", 7589 vmx_window_test_db_count == 1, 7590 vmx_window_test_db_count); 7591 report_prefix_pop(); 7592 7593 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 7594 report_skip("CPU does not support activity state HLT."); 7595 } else { 7596 /* 7597 * Ask for "NMI-window exiting" when entering activity 7598 * state HLT, and expect an immediate VM-exit. RIP is 7599 * still one byte past the nop. 7600 */ 7601 report_prefix_push("halted, no blocking"); 7602 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 7603 enter_guest(); 7604 verify_nmi_window_exit(nop_addr + 1); 7605 report_prefix_pop(); 7606 7607 /* 7608 * Ask for "NMI-window exiting" when entering activity 7609 * state HLT (with event injection), and expect a 7610 * VM-exit after the event is injected. (RIP should be 7611 * at the address specified in the IDT entry for #DB.) 7612 */ 7613 report_prefix_push("halted, no blocking, injecting #DB"); 7614 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 7615 vmcs_write(ENT_INTR_INFO, 7616 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 7617 DB_VECTOR); 7618 enter_guest(); 7619 verify_nmi_window_exit((u64)db_fault_addr); 7620 report_prefix_pop(); 7621 } 7622 7623 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 7624 enter_guest(); 7625 report_prefix_pop(); 7626 } 7627 7628 static void vmx_intr_window_test_guest(void) 7629 { 7630 handle_exception(DB_VECTOR, vmx_window_test_db_handler); 7631 7632 /* 7633 * The two consecutive STIs are to ensure that only the first 7634 * one has a shadow. Note that NOP and STI are one byte 7635 * instructions. 7636 */ 7637 asm volatile("vmcall\n\t" 7638 "nop\n\t" 7639 "sti\n\t" 7640 "sti\n\t"); 7641 7642 handle_exception(DB_VECTOR, NULL); 7643 } 7644 7645 static void verify_intr_window_exit(u64 rip) 7646 { 7647 u32 exit_reason = vmcs_read(EXI_REASON); 7648 7649 report("Exit reason (%d) is 'interrupt window'", 7650 exit_reason == VMX_INTR_WINDOW, exit_reason); 7651 report("RIP (%#lx) is %#lx", vmcs_read(GUEST_RIP) == rip, 7652 vmcs_read(GUEST_RIP), rip); 7653 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 7654 } 7655 7656 static void vmx_intr_window_test(void) 7657 { 7658 u64 vmcall_addr; 7659 u64 nop_addr; 7660 unsigned int orig_db_gate_type; 7661 void *db_fault_addr = get_idt_addr(&boot_idt[DB_VECTOR]); 7662 7663 if (!(ctrl_cpu_rev[0].clr & CPU_INTR_WINDOW)) { 7664 report_skip("CPU does not support the \"interrupt-window exiting\" VM-execution control."); 7665 return; 7666 } 7667 7668 /* 7669 * Change the IDT entry for #DB from interrupt gate to trap gate, 7670 * so that it won't clear RFLAGS.IF. We don't want interrupts to 7671 * be disabled after vectoring a #DB. 7672 */ 7673 orig_db_gate_type = boot_idt[DB_VECTOR].type; 7674 boot_idt[DB_VECTOR].type = 15; 7675 7676 report_prefix_push("interrupt-window"); 7677 test_set_guest(vmx_intr_window_test_guest); 7678 enter_guest(); 7679 assert_exit_reason(VMX_VMCALL); 7680 vmcall_addr = vmcs_read(GUEST_RIP); 7681 7682 /* 7683 * Ask for "interrupt-window exiting" with RFLAGS.IF set and 7684 * no blocking; expect an immediate VM-exit. Note that we have 7685 * not advanced past the vmcall instruction yet, so RIP should 7686 * point to the vmcall instruction. 7687 */ 7688 report_prefix_push("active, no blocking, RFLAGS.IF=1"); 7689 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 7690 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_IF); 7691 enter_guest(); 7692 verify_intr_window_exit(vmcall_addr); 7693 report_prefix_pop(); 7694 7695 /* 7696 * Ask for "interrupt-window exiting" (with event injection) 7697 * with RFLAGS.IF set and no blocking; expect a VM-exit after 7698 * the event is injected. That is, RIP should should be at the 7699 * address specified in the IDT entry for #DB. 7700 */ 7701 report_prefix_push("active, no blocking, RFLAGS.IF=1, injecting #DB"); 7702 vmcs_write(ENT_INTR_INFO, 7703 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 7704 vmcall_addr = vmcs_read(GUEST_RIP); 7705 enter_guest(); 7706 verify_intr_window_exit((u64)db_fault_addr); 7707 report_prefix_pop(); 7708 7709 /* 7710 * Let the L2 guest run through the IRET, back to the VMCALL. 7711 * We have to clear the "interrupt-window exiting" 7712 * VM-execution control, or it would just keep causing 7713 * VM-exits. Then, advance past the VMCALL and set the 7714 * "interrupt-window exiting" VM-execution control again. 7715 */ 7716 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 7717 enter_guest(); 7718 skip_exit_vmcall(); 7719 nop_addr = vmcs_read(GUEST_RIP); 7720 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 7721 7722 /* 7723 * Ask for "interrupt-window exiting" in a MOV-SS shadow with 7724 * RFLAGS.IF set, and expect a VM-exit on the next 7725 * instruction. (NOP is one byte.) 7726 */ 7727 report_prefix_push("active, blocking by MOV-SS, RFLAGS.IF=1"); 7728 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 7729 enter_guest(); 7730 verify_intr_window_exit(nop_addr + 1); 7731 report_prefix_pop(); 7732 7733 /* 7734 * Back up to the NOP and ask for "interrupt-window exiting" 7735 * in an STI shadow with RFLAGS.IF set, and expect a VM-exit 7736 * on the next instruction. (NOP is one byte.) 7737 */ 7738 report_prefix_push("active, blocking by STI, RFLAGS.IF=1"); 7739 vmcs_write(GUEST_RIP, nop_addr); 7740 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_STI); 7741 enter_guest(); 7742 verify_intr_window_exit(nop_addr + 1); 7743 report_prefix_pop(); 7744 7745 /* 7746 * Ask for "interrupt-window exiting" with RFLAGS.IF clear, 7747 * and expect a VM-exit on the instruction following the STI 7748 * shadow. Only the first STI (which is one byte past the NOP) 7749 * should have a shadow. The second STI (which is two bytes 7750 * past the NOP) has no shadow. Therefore, the interrupt 7751 * window opens at three bytes past the NOP. 7752 */ 7753 report_prefix_push("active, RFLAGS.IF = 0"); 7754 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 7755 enter_guest(); 7756 verify_intr_window_exit(nop_addr + 3); 7757 report_prefix_pop(); 7758 7759 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 7760 report_skip("CPU does not support activity state HLT."); 7761 } else { 7762 /* 7763 * Ask for "interrupt-window exiting" when entering 7764 * activity state HLT, and expect an immediate 7765 * VM-exit. RIP is still three bytes past the nop. 7766 */ 7767 report_prefix_push("halted, no blocking"); 7768 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 7769 enter_guest(); 7770 verify_intr_window_exit(nop_addr + 3); 7771 report_prefix_pop(); 7772 7773 /* 7774 * Ask for "interrupt-window exiting" when entering 7775 * activity state HLT (with event injection), and 7776 * expect a VM-exit after the event is injected. That 7777 * is, RIP should should be at the address specified 7778 * in the IDT entry for #DB. 7779 */ 7780 report_prefix_push("halted, no blocking, injecting #DB"); 7781 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 7782 vmcs_write(ENT_INTR_INFO, 7783 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 7784 DB_VECTOR); 7785 enter_guest(); 7786 verify_intr_window_exit((u64)db_fault_addr); 7787 report_prefix_pop(); 7788 } 7789 7790 boot_idt[DB_VECTOR].type = orig_db_gate_type; 7791 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 7792 enter_guest(); 7793 report_prefix_pop(); 7794 } 7795 7796 #define GUEST_TSC_OFFSET (1u << 30) 7797 7798 static u64 guest_tsc; 7799 7800 static void vmx_store_tsc_test_guest(void) 7801 { 7802 guest_tsc = rdtsc(); 7803 } 7804 7805 /* 7806 * This test ensures that when IA32_TSC is in the VM-exit MSR-store 7807 * list, the value saved is not subject to the TSC offset that is 7808 * applied to RDTSC/RDTSCP/RDMSR(IA32_TSC) in guest execution. 7809 */ 7810 static void vmx_store_tsc_test(void) 7811 { 7812 struct vmx_msr_entry msr_entry = { .index = MSR_IA32_TSC }; 7813 u64 low, high; 7814 7815 if (!(ctrl_cpu_rev[0].clr & CPU_USE_TSC_OFFSET)) { 7816 report_skip("'Use TSC offsetting' not supported"); 7817 return; 7818 } 7819 7820 test_set_guest(vmx_store_tsc_test_guest); 7821 7822 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_USE_TSC_OFFSET); 7823 vmcs_write(EXI_MSR_ST_CNT, 1); 7824 vmcs_write(EXIT_MSR_ST_ADDR, virt_to_phys(&msr_entry)); 7825 vmcs_write(TSC_OFFSET, GUEST_TSC_OFFSET); 7826 7827 low = rdtsc(); 7828 enter_guest(); 7829 high = rdtsc(); 7830 7831 report("RDTSC value in the guest (%lu) is in range [%lu, %lu]", 7832 low + GUEST_TSC_OFFSET <= guest_tsc && 7833 guest_tsc <= high + GUEST_TSC_OFFSET, 7834 guest_tsc, low + GUEST_TSC_OFFSET, high + GUEST_TSC_OFFSET); 7835 report("IA32_TSC value saved in the VM-exit MSR-store list (%lu) is in range [%lu, %lu]", 7836 low <= msr_entry.value && msr_entry.value <= high, 7837 msr_entry.value, low, high); 7838 } 7839 7840 static void vmx_db_test_guest(void) 7841 { 7842 /* 7843 * For a hardware generated single-step #DB. 7844 */ 7845 asm volatile("vmcall;" 7846 "nop;" 7847 ".Lpost_nop:"); 7848 /* 7849 * ...in a MOVSS shadow, with pending debug exceptions. 7850 */ 7851 asm volatile("vmcall;" 7852 "nop;" 7853 ".Lpost_movss_nop:"); 7854 /* 7855 * For an L0 synthesized single-step #DB. (L0 intercepts WBINVD and 7856 * emulates it in software.) 7857 */ 7858 asm volatile("vmcall;" 7859 "wbinvd;" 7860 ".Lpost_wbinvd:"); 7861 /* 7862 * ...in a MOVSS shadow, with pending debug exceptions. 7863 */ 7864 asm volatile("vmcall;" 7865 "wbinvd;" 7866 ".Lpost_movss_wbinvd:"); 7867 /* 7868 * For a hardware generated single-step #DB in a transactional region. 7869 */ 7870 asm volatile("vmcall;" 7871 ".Lxbegin: xbegin .Lskip_rtm;" 7872 "xend;" 7873 ".Lskip_rtm:"); 7874 } 7875 7876 /* 7877 * Clear the pending debug exceptions and RFLAGS.TF and re-enter 7878 * L2. No #DB is delivered and L2 continues to the next point of 7879 * interest. 7880 */ 7881 static void dismiss_db(void) 7882 { 7883 vmcs_write(GUEST_PENDING_DEBUG, 0); 7884 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 7885 enter_guest(); 7886 } 7887 7888 /* 7889 * Check a variety of VMCS fields relevant to an intercepted #DB exception. 7890 * Then throw away the #DB exception and resume L2. 7891 */ 7892 static void check_db_exit(bool xfail_qual, bool xfail_dr6, bool xfail_pdbg, 7893 void *expected_rip, u64 expected_exit_qual, 7894 u64 expected_dr6) 7895 { 7896 u32 reason = vmcs_read(EXI_REASON); 7897 u32 intr_info = vmcs_read(EXI_INTR_INFO); 7898 u64 exit_qual = vmcs_read(EXI_QUALIFICATION); 7899 u64 guest_rip = vmcs_read(GUEST_RIP); 7900 u64 guest_pending_dbg = vmcs_read(GUEST_PENDING_DEBUG); 7901 u64 dr6 = read_dr6(); 7902 const u32 expected_intr_info = INTR_INFO_VALID_MASK | 7903 INTR_TYPE_HARD_EXCEPTION | DB_VECTOR; 7904 7905 report("Expected #DB VM-exit", 7906 reason == VMX_EXC_NMI && intr_info == expected_intr_info); 7907 report("Expected RIP %p (actual %lx)", (u64)expected_rip == guest_rip, 7908 expected_rip, guest_rip); 7909 report_xfail("Expected pending debug exceptions 0 (actual %lx)", 7910 xfail_pdbg, 0 == guest_pending_dbg, guest_pending_dbg); 7911 report_xfail("Expected exit qualification %lx (actual %lx)", xfail_qual, 7912 expected_exit_qual == exit_qual, 7913 expected_exit_qual, exit_qual); 7914 report_xfail("Expected DR6 %lx (actual %lx)", xfail_dr6, 7915 expected_dr6 == dr6, expected_dr6, dr6); 7916 dismiss_db(); 7917 } 7918 7919 /* 7920 * Assuming the guest has just exited on a VMCALL instruction, skip 7921 * over the vmcall, and set the guest's RFLAGS.TF in the VMCS. If 7922 * pending debug exceptions are non-zero, set the VMCS up as if the 7923 * previous instruction was a MOVSS that generated the indicated 7924 * pending debug exceptions. Then enter L2. 7925 */ 7926 static void single_step_guest(const char *test_name, u64 starting_dr6, 7927 u64 pending_debug_exceptions) 7928 { 7929 printf("\n%s\n", test_name); 7930 skip_exit_vmcall(); 7931 write_dr6(starting_dr6); 7932 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_TF); 7933 if (pending_debug_exceptions) { 7934 vmcs_write(GUEST_PENDING_DEBUG, pending_debug_exceptions); 7935 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 7936 } 7937 enter_guest(); 7938 } 7939 7940 /* 7941 * When L1 intercepts #DB, verify that a single-step trap clears 7942 * pending debug exceptions, populates the exit qualification field 7943 * properly, and that DR6 is not prematurely clobbered. In a 7944 * (simulated) MOVSS shadow, make sure that the pending debug 7945 * exception bits are properly accumulated into the exit qualification 7946 * field. 7947 */ 7948 static void vmx_db_test(void) 7949 { 7950 /* 7951 * We are going to set a few arbitrary bits in DR6 to verify that 7952 * (a) DR6 is not modified by an intercepted #DB, and 7953 * (b) stale bits in DR6 (DR6.BD, in particular) don't leak into 7954 * the exit qualification field for a subsequent #DB exception. 7955 */ 7956 const u64 starting_dr6 = DR6_RESERVED | BIT(13) | DR_TRAP3 | DR_TRAP1; 7957 extern char post_nop asm(".Lpost_nop"); 7958 extern char post_movss_nop asm(".Lpost_movss_nop"); 7959 extern char post_wbinvd asm(".Lpost_wbinvd"); 7960 extern char post_movss_wbinvd asm(".Lpost_movss_wbinvd"); 7961 extern char xbegin asm(".Lxbegin"); 7962 extern char skip_rtm asm(".Lskip_rtm"); 7963 7964 /* 7965 * L1 wants to intercept #DB exceptions encountered in L2. 7966 */ 7967 vmcs_write(EXC_BITMAP, BIT(DB_VECTOR)); 7968 7969 /* 7970 * Start L2 and run it up to the first point of interest. 7971 */ 7972 test_set_guest(vmx_db_test_guest); 7973 enter_guest(); 7974 7975 /* 7976 * Hardware-delivered #DB trap for single-step sets the 7977 * standard that L0 has to follow for emulated instructions. 7978 */ 7979 single_step_guest("Hardware delivered single-step", starting_dr6, 0); 7980 check_db_exit(false, false, false, &post_nop, DR_STEP, starting_dr6); 7981 7982 /* 7983 * Hardware-delivered #DB trap for single-step in MOVSS shadow 7984 * also sets the standard that L0 has to follow for emulated 7985 * instructions. Here, we establish the VMCS pending debug 7986 * exceptions to indicate that the simulated MOVSS triggered a 7987 * data breakpoint as well as the single-step trap. 7988 */ 7989 single_step_guest("Hardware delivered single-step in MOVSS shadow", 7990 starting_dr6, BIT(12) | DR_STEP | DR_TRAP0 ); 7991 check_db_exit(false, false, false, &post_movss_nop, DR_STEP | DR_TRAP0, 7992 starting_dr6); 7993 7994 /* 7995 * L0 synthesized #DB trap for single-step is buggy, because 7996 * kvm (a) clobbers DR6 too early, and (b) tries its best to 7997 * reconstitute the exit qualification from the prematurely 7998 * modified DR6, but fails miserably. 7999 */ 8000 single_step_guest("Software synthesized single-step", starting_dr6, 0); 8001 check_db_exit(true, true, false, &post_wbinvd, DR_STEP, starting_dr6); 8002 8003 /* 8004 * L0 synthesized #DB trap for single-step in MOVSS shadow is 8005 * even worse, because L0 also leaves the pending debug 8006 * exceptions in the VMCS instead of accumulating them into 8007 * the exit qualification field for the #DB exception. 8008 */ 8009 single_step_guest("Software synthesized single-step in MOVSS shadow", 8010 starting_dr6, BIT(12) | DR_STEP | DR_TRAP0); 8011 check_db_exit(true, true, true, &post_movss_wbinvd, DR_STEP | DR_TRAP0, 8012 starting_dr6); 8013 8014 /* 8015 * Optional RTM test for hardware that supports RTM, to 8016 * demonstrate that the current volume 3 of the SDM 8017 * (325384-067US), table 27-1 is incorrect. Bit 16 of the exit 8018 * qualification for debug exceptions is not reserved. It is 8019 * set to 1 if a debug exception (#DB) or a breakpoint 8020 * exception (#BP) occurs inside an RTM region while advanced 8021 * debugging of RTM transactional regions is enabled. 8022 */ 8023 if (this_cpu_has(X86_FEATURE_RTM)) { 8024 vmcs_write(ENT_CONTROLS, 8025 vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 8026 /* 8027 * Set DR7.RTM[bit 11] and IA32_DEBUGCTL.RTM[bit 15] 8028 * in the guest to enable advanced debugging of RTM 8029 * transactional regions. 8030 */ 8031 vmcs_write(GUEST_DR7, BIT(11)); 8032 vmcs_write(GUEST_DEBUGCTL, BIT(15)); 8033 single_step_guest("Hardware delivered single-step in " 8034 "transactional region", starting_dr6, 0); 8035 check_db_exit(false, false, false, &xbegin, BIT(16), 8036 starting_dr6); 8037 } else { 8038 vmcs_write(GUEST_RIP, (u64)&skip_rtm); 8039 enter_guest(); 8040 } 8041 } 8042 8043 static void enable_vid(void) 8044 { 8045 void *virtual_apic_page; 8046 8047 assert(cpu_has_apicv()); 8048 8049 disable_intercept_for_x2apic_msrs(); 8050 8051 virtual_apic_page = alloc_page(); 8052 vmcs_write(APIC_VIRT_ADDR, (u64)virtual_apic_page); 8053 8054 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 8055 8056 vmcs_write(EOI_EXIT_BITMAP0, 0x0); 8057 vmcs_write(EOI_EXIT_BITMAP1, 0x0); 8058 vmcs_write(EOI_EXIT_BITMAP2, 0x0); 8059 vmcs_write(EOI_EXIT_BITMAP3, 0x0); 8060 8061 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY | CPU_TPR_SHADOW); 8062 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_VINTD | CPU_VIRT_X2APIC); 8063 } 8064 8065 static void trigger_ioapic_scan_thread(void *data) 8066 { 8067 /* Wait until other CPU entered L2 */ 8068 while (vmx_get_test_stage() != 1) 8069 ; 8070 8071 /* Trigger ioapic scan */ 8072 ioapic_set_redir(0xf, 0x79, TRIGGER_LEVEL); 8073 vmx_set_test_stage(2); 8074 } 8075 8076 static void irq_79_handler_guest(isr_regs_t *regs) 8077 { 8078 eoi(); 8079 8080 /* L1 expects vmexit on VMX_VMCALL and not VMX_EOI_INDUCED */ 8081 vmcall(); 8082 } 8083 8084 /* 8085 * Constant for num of busy-loop iterations after which 8086 * a timer interrupt should have happened in host 8087 */ 8088 #define TIMER_INTERRUPT_DELAY 100000000 8089 8090 static void vmx_eoi_bitmap_ioapic_scan_test_guest(void) 8091 { 8092 handle_irq(0x79, irq_79_handler_guest); 8093 irq_enable(); 8094 8095 /* Signal to L1 CPU to trigger ioapic scan */ 8096 vmx_set_test_stage(1); 8097 /* Wait until L1 CPU to trigger ioapic scan */ 8098 while (vmx_get_test_stage() != 2) 8099 ; 8100 8101 /* 8102 * Wait for L0 timer interrupt to be raised while we run in L2 8103 * such that L0 will process the IOAPIC scan request before 8104 * resuming L2 8105 */ 8106 delay(TIMER_INTERRUPT_DELAY); 8107 8108 asm volatile ("int $0x79"); 8109 } 8110 8111 static void vmx_eoi_bitmap_ioapic_scan_test(void) 8112 { 8113 if (!cpu_has_apicv() || (cpu_count() < 2)) { 8114 report_skip(__func__); 8115 return; 8116 } 8117 8118 enable_vid(); 8119 8120 on_cpu_async(1, trigger_ioapic_scan_thread, NULL); 8121 test_set_guest(vmx_eoi_bitmap_ioapic_scan_test_guest); 8122 8123 /* 8124 * Launch L2. 8125 * We expect the exit reason to be VMX_VMCALL (and not EOI INDUCED). 8126 * In case the reason isn't VMX_VMCALL, the asserion inside 8127 * skip_exit_vmcall() will fail. 8128 */ 8129 enter_guest(); 8130 skip_exit_vmcall(); 8131 8132 /* Let L2 finish */ 8133 enter_guest(); 8134 report(__func__, 1); 8135 } 8136 8137 #define HLT_WITH_RVI_VECTOR (0xf1) 8138 8139 bool vmx_hlt_with_rvi_guest_isr_fired; 8140 static void vmx_hlt_with_rvi_guest_isr(isr_regs_t *regs) 8141 { 8142 vmx_hlt_with_rvi_guest_isr_fired = true; 8143 eoi(); 8144 } 8145 8146 static void vmx_hlt_with_rvi_guest(void) 8147 { 8148 handle_irq(HLT_WITH_RVI_VECTOR, vmx_hlt_with_rvi_guest_isr); 8149 8150 irq_enable(); 8151 asm volatile ("nop"); 8152 8153 vmcall(); 8154 } 8155 8156 static void vmx_hlt_with_rvi_test(void) 8157 { 8158 if (!cpu_has_apicv()) { 8159 report_skip(__func__); 8160 return; 8161 } 8162 8163 enable_vid(); 8164 8165 vmx_hlt_with_rvi_guest_isr_fired = false; 8166 test_set_guest(vmx_hlt_with_rvi_guest); 8167 8168 enter_guest(); 8169 skip_exit_vmcall(); 8170 8171 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8172 vmcs_write(GUEST_INT_STATUS, HLT_WITH_RVI_VECTOR); 8173 enter_guest(); 8174 8175 report("Interrupt raised in guest", vmx_hlt_with_rvi_guest_isr_fired); 8176 } 8177 8178 static void set_irq_line_thread(void *data) 8179 { 8180 /* Wait until other CPU entered L2 */ 8181 while (vmx_get_test_stage() != 1) 8182 ; 8183 8184 /* Set irq-line 0xf to raise vector 0x78 for vCPU 0 */ 8185 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 8186 vmx_set_test_stage(2); 8187 } 8188 8189 static bool irq_78_handler_vmcall_before_eoi; 8190 static void irq_78_handler_guest(isr_regs_t *regs) 8191 { 8192 set_irq_line(0xf, 0); 8193 if (irq_78_handler_vmcall_before_eoi) 8194 vmcall(); 8195 eoi(); 8196 vmcall(); 8197 } 8198 8199 static void vmx_apic_passthrough_guest(void) 8200 { 8201 handle_irq(0x78, irq_78_handler_guest); 8202 irq_enable(); 8203 8204 /* If requested, wait for other CPU to trigger ioapic scan */ 8205 if (vmx_get_test_stage() < 1) { 8206 vmx_set_test_stage(1); 8207 while (vmx_get_test_stage() != 2) 8208 ; 8209 } 8210 8211 set_irq_line(0xf, 1); 8212 } 8213 8214 static void vmx_apic_passthrough(bool set_irq_line_from_thread) 8215 { 8216 if (set_irq_line_from_thread && (cpu_count() < 2)) { 8217 report_skip(__func__); 8218 return; 8219 } 8220 8221 /* Test device is required for generating IRQs */ 8222 if (!test_device_enabled()) { 8223 report_skip(__func__); 8224 return; 8225 } 8226 u64 cpu_ctrl_0 = CPU_SECONDARY; 8227 u64 cpu_ctrl_1 = 0; 8228 8229 disable_intercept_for_x2apic_msrs(); 8230 8231 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 8232 8233 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 8234 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 8235 8236 if (set_irq_line_from_thread) { 8237 irq_78_handler_vmcall_before_eoi = false; 8238 on_cpu_async(1, set_irq_line_thread, NULL); 8239 } else { 8240 irq_78_handler_vmcall_before_eoi = true; 8241 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 8242 vmx_set_test_stage(2); 8243 } 8244 test_set_guest(vmx_apic_passthrough_guest); 8245 8246 if (irq_78_handler_vmcall_before_eoi) { 8247 /* Before EOI remote_irr should still be set */ 8248 enter_guest(); 8249 skip_exit_vmcall(); 8250 TEST_ASSERT_EQ_MSG(1, (int)ioapic_read_redir(0xf).remote_irr, 8251 "IOAPIC pass-through: remote_irr=1 before EOI"); 8252 } 8253 8254 /* After EOI remote_irr should be cleared */ 8255 enter_guest(); 8256 skip_exit_vmcall(); 8257 TEST_ASSERT_EQ_MSG(0, (int)ioapic_read_redir(0xf).remote_irr, 8258 "IOAPIC pass-through: remote_irr=0 after EOI"); 8259 8260 /* Let L2 finish */ 8261 enter_guest(); 8262 report(__func__, 1); 8263 } 8264 8265 static void vmx_apic_passthrough_test(void) 8266 { 8267 vmx_apic_passthrough(false); 8268 } 8269 8270 static void vmx_apic_passthrough_thread_test(void) 8271 { 8272 vmx_apic_passthrough(true); 8273 } 8274 8275 static u64 init_signal_test_exit_reason; 8276 static bool init_signal_test_thread_continued; 8277 8278 static void init_signal_test_thread(void *data) 8279 { 8280 struct vmcs *test_vmcs = data; 8281 8282 /* Enter VMX operation (i.e. exec VMXON) */ 8283 u64 *ap_vmxon_region = alloc_page(); 8284 enable_vmx(); 8285 init_vmx(ap_vmxon_region); 8286 _vmx_on(ap_vmxon_region); 8287 8288 /* Signal CPU have entered VMX operation */ 8289 vmx_set_test_stage(1); 8290 8291 /* Wait for BSP CPU to send INIT signal */ 8292 while (vmx_get_test_stage() != 2) 8293 ; 8294 8295 /* 8296 * Signal that we continue as usual as INIT signal 8297 * should be blocked while CPU is in VMX operation 8298 */ 8299 vmx_set_test_stage(3); 8300 8301 /* Wait for signal to enter VMX non-root mode */ 8302 while (vmx_get_test_stage() != 4) 8303 ; 8304 8305 /* Enter VMX non-root mode */ 8306 test_set_guest(v2_null_test_guest); 8307 make_vmcs_current(test_vmcs); 8308 enter_guest(); 8309 /* Save exit reason for BSP CPU to compare to expected result */ 8310 init_signal_test_exit_reason = vmcs_read(EXI_REASON); 8311 /* VMCLEAR test-vmcs so it could be loaded by BSP CPU */ 8312 vmcs_clear(test_vmcs); 8313 launched = false; 8314 /* Signal that CPU exited to VMX root mode */ 8315 vmx_set_test_stage(5); 8316 8317 /* Wait for signal to exit VMX operation */ 8318 while (vmx_get_test_stage() != 6) 8319 ; 8320 8321 /* Exit VMX operation (i.e. exec VMXOFF) */ 8322 vmx_off(); 8323 8324 /* 8325 * Exiting VMX operation should result in latched 8326 * INIT signal being processed. Therefore, we should 8327 * never reach the below code. Thus, signal to BSP 8328 * CPU if we have reached here so it is able to 8329 * report an issue if it happens. 8330 */ 8331 init_signal_test_thread_continued = true; 8332 } 8333 8334 #define INIT_SIGNAL_TEST_DELAY 100000000ULL 8335 8336 static void vmx_init_signal_test(void) 8337 { 8338 struct vmcs *test_vmcs; 8339 8340 if (cpu_count() < 2) { 8341 report_skip(__func__); 8342 return; 8343 } 8344 8345 /* VMCLEAR test-vmcs so it could be loaded by other CPU */ 8346 vmcs_save(&test_vmcs); 8347 vmcs_clear(test_vmcs); 8348 8349 vmx_set_test_stage(0); 8350 on_cpu_async(1, init_signal_test_thread, test_vmcs); 8351 8352 /* Wait for other CPU to enter VMX operation */ 8353 while (vmx_get_test_stage() != 1) 8354 ; 8355 8356 /* Send INIT signal to other CPU */ 8357 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_INIT | APIC_INT_ASSERT, 8358 id_map[1]); 8359 /* Signal other CPU we have sent INIT signal */ 8360 vmx_set_test_stage(2); 8361 8362 /* 8363 * Wait reasonable amount of time for INIT signal to 8364 * be received on other CPU and verify that other CPU 8365 * have proceed as usual to next test stage as INIT 8366 * signal should be blocked while other CPU in 8367 * VMX operation 8368 */ 8369 delay(INIT_SIGNAL_TEST_DELAY); 8370 report("INIT signal blocked when CPU in VMX operation", 8371 vmx_get_test_stage() == 3); 8372 /* No point to continue if we failed at this point */ 8373 if (vmx_get_test_stage() != 3) 8374 return; 8375 8376 /* Signal other CPU to enter VMX non-root mode */ 8377 init_signal_test_exit_reason = -1ull; 8378 vmx_set_test_stage(4); 8379 /* 8380 * Wait reasonable amont of time for other CPU 8381 * to exit to VMX root mode 8382 */ 8383 delay(INIT_SIGNAL_TEST_DELAY); 8384 if (vmx_get_test_stage() != 5) { 8385 report("Pending INIT signal didn't result in VMX exit", false); 8386 return; 8387 } 8388 report("INIT signal during VMX non-root mode result in exit-reason %s (%lu)", 8389 init_signal_test_exit_reason == VMX_INIT, 8390 exit_reason_description(init_signal_test_exit_reason), 8391 init_signal_test_exit_reason); 8392 8393 /* Run guest to completion */ 8394 make_vmcs_current(test_vmcs); 8395 enter_guest(); 8396 8397 /* Signal other CPU to exit VMX operation */ 8398 init_signal_test_thread_continued = false; 8399 vmx_set_test_stage(6); 8400 8401 /* 8402 * Wait reasonable amount of time for other CPU 8403 * to run after INIT signal was processed 8404 */ 8405 delay(INIT_SIGNAL_TEST_DELAY); 8406 report("INIT signal processed after exit VMX operation", 8407 !init_signal_test_thread_continued); 8408 8409 /* 8410 * TODO: Send SIPI to other CPU to sipi_entry (See x86/cstart64.S) 8411 * to re-init it to kvm-unit-tests standard environment. 8412 * Somehow (?) verify that SIPI was indeed received. 8413 */ 8414 } 8415 8416 enum vmcs_access { 8417 ACCESS_VMREAD, 8418 ACCESS_VMWRITE, 8419 ACCESS_NONE, 8420 }; 8421 8422 struct vmcs_shadow_test_common { 8423 enum vmcs_access op; 8424 enum Reason reason; 8425 u64 field; 8426 u64 value; 8427 u64 flags; 8428 u64 time; 8429 } l1_l2_common; 8430 8431 static inline u64 vmread_flags(u64 field, u64 *val) 8432 { 8433 u64 flags; 8434 8435 asm volatile ("vmread %2, %1; pushf; pop %0" 8436 : "=r" (flags), "=rm" (*val) : "r" (field) : "cc"); 8437 return flags & X86_EFLAGS_ALU; 8438 } 8439 8440 static inline u64 vmwrite_flags(u64 field, u64 val) 8441 { 8442 u64 flags; 8443 8444 asm volatile ("vmwrite %1, %2; pushf; pop %0" 8445 : "=r"(flags) : "rm" (val), "r" (field) : "cc"); 8446 return flags & X86_EFLAGS_ALU; 8447 } 8448 8449 static void vmx_vmcs_shadow_test_guest(void) 8450 { 8451 struct vmcs_shadow_test_common *c = &l1_l2_common; 8452 u64 start; 8453 8454 while (c->op != ACCESS_NONE) { 8455 start = rdtsc(); 8456 switch (c->op) { 8457 default: 8458 c->flags = -1ull; 8459 break; 8460 case ACCESS_VMREAD: 8461 c->flags = vmread_flags(c->field, &c->value); 8462 break; 8463 case ACCESS_VMWRITE: 8464 c->flags = vmwrite_flags(c->field, 0); 8465 break; 8466 } 8467 c->time = rdtsc() - start; 8468 vmcall(); 8469 } 8470 } 8471 8472 static u64 vmread_from_shadow(u64 field) 8473 { 8474 struct vmcs *primary; 8475 struct vmcs *shadow; 8476 u64 value; 8477 8478 TEST_ASSERT(!vmcs_save(&primary)); 8479 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 8480 TEST_ASSERT(!make_vmcs_current(shadow)); 8481 value = vmcs_read(field); 8482 TEST_ASSERT(!make_vmcs_current(primary)); 8483 return value; 8484 } 8485 8486 static u64 vmwrite_to_shadow(u64 field, u64 value) 8487 { 8488 struct vmcs *primary; 8489 struct vmcs *shadow; 8490 8491 TEST_ASSERT(!vmcs_save(&primary)); 8492 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 8493 TEST_ASSERT(!make_vmcs_current(shadow)); 8494 vmcs_write(field, value); 8495 value = vmcs_read(field); 8496 TEST_ASSERT(!make_vmcs_current(primary)); 8497 return value; 8498 } 8499 8500 static void vmcs_shadow_test_access(u8 *bitmap[2], enum vmcs_access access) 8501 { 8502 struct vmcs_shadow_test_common *c = &l1_l2_common; 8503 8504 c->op = access; 8505 vmcs_write(VMX_INST_ERROR, 0); 8506 enter_guest(); 8507 c->reason = vmcs_read(EXI_REASON) & 0xffff; 8508 if (c->reason != VMX_VMCALL) { 8509 skip_exit_insn(); 8510 enter_guest(); 8511 } 8512 skip_exit_vmcall(); 8513 } 8514 8515 static void vmcs_shadow_test_field(u8 *bitmap[2], u64 field) 8516 { 8517 struct vmcs_shadow_test_common *c = &l1_l2_common; 8518 struct vmcs *shadow; 8519 u64 value; 8520 uintptr_t flags[2]; 8521 bool good_shadow; 8522 u32 vmx_inst_error; 8523 8524 report_prefix_pushf("field %lx", field); 8525 c->field = field; 8526 8527 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 8528 if (shadow != (struct vmcs *)-1ull) { 8529 flags[ACCESS_VMREAD] = vmread_flags(field, &value); 8530 flags[ACCESS_VMWRITE] = vmwrite_flags(field, value); 8531 good_shadow = !flags[ACCESS_VMREAD] && !flags[ACCESS_VMWRITE]; 8532 } else { 8533 /* 8534 * When VMCS link pointer is -1ull, VMWRITE/VMREAD on 8535 * shadowed-fields should fail with setting RFLAGS.CF. 8536 */ 8537 flags[ACCESS_VMREAD] = X86_EFLAGS_CF; 8538 flags[ACCESS_VMWRITE] = X86_EFLAGS_CF; 8539 good_shadow = false; 8540 } 8541 8542 /* Intercept both VMREAD and VMWRITE. */ 8543 report_prefix_push("no VMREAD/VMWRITE permission"); 8544 /* VMWRITE/VMREAD done on reserved-bit should always intercept */ 8545 if (!(field >> VMCS_FIELD_RESERVED_SHIFT)) { 8546 set_bit(field, bitmap[ACCESS_VMREAD]); 8547 set_bit(field, bitmap[ACCESS_VMWRITE]); 8548 } 8549 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 8550 report("not shadowed for VMWRITE", c->reason == VMX_VMWRITE); 8551 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 8552 report("not shadowed for VMREAD", c->reason == VMX_VMREAD); 8553 report_prefix_pop(); 8554 8555 if (field >> VMCS_FIELD_RESERVED_SHIFT) 8556 goto out; 8557 8558 /* Permit shadowed VMREAD. */ 8559 report_prefix_push("VMREAD permission only"); 8560 clear_bit(field, bitmap[ACCESS_VMREAD]); 8561 set_bit(field, bitmap[ACCESS_VMWRITE]); 8562 if (good_shadow) 8563 value = vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 8564 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 8565 report("not shadowed for VMWRITE", c->reason == VMX_VMWRITE); 8566 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 8567 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 8568 report("shadowed for VMREAD (in %ld cycles)", c->reason == VMX_VMCALL, 8569 c->time); 8570 report("ALU flags after VMREAD (%lx) are as expected (%lx)", 8571 c->flags == flags[ACCESS_VMREAD], 8572 c->flags, flags[ACCESS_VMREAD]); 8573 if (good_shadow) 8574 report("value read from shadow (%lx) is as expected (%lx)", 8575 c->value == value, c->value, value); 8576 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 8577 report("VMX_INST_ERROR (%d) is as expected (%d)", 8578 vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 8579 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 8580 report_prefix_pop(); 8581 8582 /* Permit shadowed VMWRITE. */ 8583 report_prefix_push("VMWRITE permission only"); 8584 set_bit(field, bitmap[ACCESS_VMREAD]); 8585 clear_bit(field, bitmap[ACCESS_VMWRITE]); 8586 if (good_shadow) 8587 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 8588 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 8589 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 8590 report("shadowed for VMWRITE (in %ld cycles)", c->reason == VMX_VMCALL, 8591 c->time); 8592 report("ALU flags after VMWRITE (%lx) are as expected (%lx)", 8593 c->flags == flags[ACCESS_VMREAD], 8594 c->flags, flags[ACCESS_VMREAD]); 8595 if (good_shadow) { 8596 value = vmread_from_shadow(field); 8597 report("shadow VMCS value (%lx) is as expected (%lx)", 8598 value == 0, value, 0ul); 8599 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 8600 report("VMX_INST_ERROR (%d) is as expected (%d)", 8601 vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 8602 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 8603 } 8604 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 8605 report("not shadowed for VMREAD", c->reason == VMX_VMREAD); 8606 report_prefix_pop(); 8607 8608 /* Permit shadowed VMREAD and VMWRITE. */ 8609 report_prefix_push("VMREAD and VMWRITE permission"); 8610 clear_bit(field, bitmap[ACCESS_VMREAD]); 8611 clear_bit(field, bitmap[ACCESS_VMWRITE]); 8612 if (good_shadow) 8613 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 8614 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 8615 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 8616 report("shadowed for VMWRITE (in %ld cycles)", c->reason == VMX_VMCALL, 8617 c->time); 8618 report("ALU flags after VMWRITE (%lx) are as expected (%lx)", 8619 c->flags == flags[ACCESS_VMREAD], 8620 c->flags, flags[ACCESS_VMREAD]); 8621 if (good_shadow) { 8622 value = vmread_from_shadow(field); 8623 report("shadow VMCS value (%lx) is as expected (%lx)", 8624 value == 0, value, 0ul); 8625 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 8626 report("VMX_INST_ERROR (%d) is as expected (%d)", 8627 vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 8628 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 8629 } 8630 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 8631 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 8632 report("shadowed for VMREAD (in %ld cycles)", c->reason == VMX_VMCALL, 8633 c->time); 8634 report("ALU flags after VMREAD (%lx) are as expected (%lx)", 8635 c->flags == flags[ACCESS_VMREAD], 8636 c->flags, flags[ACCESS_VMREAD]); 8637 if (good_shadow) 8638 report("value read from shadow (%lx) is as expected (%lx)", 8639 c->value == 0, c->value, 0ul); 8640 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 8641 report("VMX_INST_ERROR (%d) is as expected (%d)", 8642 vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 8643 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 8644 report_prefix_pop(); 8645 8646 out: 8647 report_prefix_pop(); 8648 } 8649 8650 static void vmx_vmcs_shadow_test_body(u8 *bitmap[2]) 8651 { 8652 unsigned base; 8653 unsigned index; 8654 unsigned bit; 8655 unsigned highest_index = rdmsr(MSR_IA32_VMX_VMCS_ENUM); 8656 8657 /* Run test on all possible valid VMCS fields */ 8658 for (base = 0; 8659 base < (1 << VMCS_FIELD_RESERVED_SHIFT); 8660 base += (1 << VMCS_FIELD_TYPE_SHIFT)) 8661 for (index = 0; index <= highest_index; index++) 8662 vmcs_shadow_test_field(bitmap, base + index); 8663 8664 /* 8665 * Run tests on some invalid VMCS fields 8666 * (Have reserved bit set). 8667 */ 8668 for (bit = VMCS_FIELD_RESERVED_SHIFT; bit < VMCS_FIELD_BIT_SIZE; bit++) 8669 vmcs_shadow_test_field(bitmap, (1ull << bit)); 8670 } 8671 8672 static void vmx_vmcs_shadow_test(void) 8673 { 8674 u8 *bitmap[2]; 8675 struct vmcs *shadow; 8676 8677 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 8678 printf("\t'Activate secondary controls' not supported.\n"); 8679 return; 8680 } 8681 8682 if (!(ctrl_cpu_rev[1].clr & CPU_SHADOW_VMCS)) { 8683 printf("\t'VMCS shadowing' not supported.\n"); 8684 return; 8685 } 8686 8687 if (!(rdmsr(MSR_IA32_VMX_MISC) & 8688 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS)) { 8689 printf("\tVMWRITE can't modify VM-exit information fields.\n"); 8690 return; 8691 } 8692 8693 test_set_guest(vmx_vmcs_shadow_test_guest); 8694 8695 bitmap[ACCESS_VMREAD] = alloc_page(); 8696 bitmap[ACCESS_VMWRITE] = alloc_page(); 8697 8698 vmcs_write(VMREAD_BITMAP, virt_to_phys(bitmap[ACCESS_VMREAD])); 8699 vmcs_write(VMWRITE_BITMAP, virt_to_phys(bitmap[ACCESS_VMWRITE])); 8700 8701 shadow = alloc_page(); 8702 shadow->hdr.revision_id = basic.revision; 8703 shadow->hdr.shadow_vmcs = 1; 8704 TEST_ASSERT(!vmcs_clear(shadow)); 8705 8706 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_RDTSC); 8707 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY); 8708 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_SHADOW_VMCS); 8709 8710 vmcs_write(VMCS_LINK_PTR, virt_to_phys(shadow)); 8711 report_prefix_push("valid link pointer"); 8712 vmx_vmcs_shadow_test_body(bitmap); 8713 report_prefix_pop(); 8714 8715 vmcs_write(VMCS_LINK_PTR, -1ull); 8716 report_prefix_push("invalid link pointer"); 8717 vmx_vmcs_shadow_test_body(bitmap); 8718 report_prefix_pop(); 8719 8720 l1_l2_common.op = ACCESS_NONE; 8721 enter_guest(); 8722 } 8723 8724 8725 8726 static int invalid_msr_init(struct vmcs *vmcs) 8727 { 8728 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 8729 printf("\tPreemption timer is not supported\n"); 8730 return VMX_TEST_EXIT; 8731 } 8732 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 8733 preempt_val = 10000000; 8734 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 8735 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 8736 8737 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 8738 printf("\tSave preemption value is not supported\n"); 8739 8740 vmcs_write(ENT_MSR_LD_CNT, 1); 8741 vmcs_write(ENTER_MSR_LD_ADDR, (u64)0x13370000); 8742 8743 return VMX_TEST_START; 8744 } 8745 8746 8747 static void invalid_msr_main(void) 8748 { 8749 report("Invalid MSR load", 0); 8750 } 8751 8752 static int invalid_msr_exit_handler(void) 8753 { 8754 report("Invalid MSR load", 0); 8755 print_vmexit_info(); 8756 return VMX_TEST_EXIT; 8757 } 8758 8759 static int invalid_msr_entry_failure(struct vmentry_failure *failure) 8760 { 8761 ulong reason; 8762 8763 reason = vmcs_read(EXI_REASON); 8764 report("Invalid MSR load", reason == (0x80000000u | VMX_FAIL_MSR)); 8765 return VMX_TEST_VMEXIT; 8766 } 8767 8768 /* 8769 * The max number of MSRs in an atomic switch MSR list is: 8770 * (111B + 1) * 512 = 4096 8771 * 8772 * Each list entry consumes: 8773 * 4-byte MSR index + 4 bytes reserved + 8-byte data = 16 bytes 8774 * 8775 * Allocate 128 kB to cover max_msr_list_size (i.e., 64 kB) and then some. 8776 */ 8777 static const u32 msr_list_page_order = 5; 8778 8779 static void atomic_switch_msr_limit_test_guest(void) 8780 { 8781 vmcall(); 8782 } 8783 8784 static void populate_msr_list(struct vmx_msr_entry *msr_list, 8785 size_t byte_capacity, int count) 8786 { 8787 int i; 8788 8789 for (i = 0; i < count; i++) { 8790 msr_list[i].index = MSR_IA32_TSC; 8791 msr_list[i].reserved = 0; 8792 msr_list[i].value = 0x1234567890abcdef; 8793 } 8794 8795 memset(msr_list + count, 0xff, 8796 byte_capacity - count * sizeof(*msr_list)); 8797 } 8798 8799 static int max_msr_list_size(void) 8800 { 8801 u32 vmx_misc = rdmsr(MSR_IA32_VMX_MISC); 8802 u32 factor = ((vmx_misc & GENMASK(27, 25)) >> 25) + 1; 8803 8804 return factor * 512; 8805 } 8806 8807 static void atomic_switch_msrs_test(int count) 8808 { 8809 struct vmx_msr_entry *vm_enter_load; 8810 struct vmx_msr_entry *vm_exit_load; 8811 struct vmx_msr_entry *vm_exit_store; 8812 int max_allowed = max_msr_list_size(); 8813 int byte_capacity = 1ul << (msr_list_page_order + PAGE_SHIFT); 8814 /* Exceeding the max MSR list size at exit trigers KVM to abort. */ 8815 int exit_count = count > max_allowed ? max_allowed : count; 8816 int cleanup_count = count > max_allowed ? 2 : 1; 8817 int i; 8818 8819 /* 8820 * Check for the IA32_TSC MSR, 8821 * available with the "TSC flag" and used to populate the MSR lists. 8822 */ 8823 if (!(cpuid(1).d & (1 << 4))) { 8824 report_skip(__func__); 8825 return; 8826 } 8827 8828 /* Set L2 guest. */ 8829 test_set_guest(atomic_switch_msr_limit_test_guest); 8830 8831 /* Setup atomic MSR switch lists. */ 8832 vm_enter_load = alloc_pages(msr_list_page_order); 8833 vm_exit_load = alloc_pages(msr_list_page_order); 8834 vm_exit_store = alloc_pages(msr_list_page_order); 8835 8836 vmcs_write(ENTER_MSR_LD_ADDR, (u64)vm_enter_load); 8837 vmcs_write(EXIT_MSR_LD_ADDR, (u64)vm_exit_load); 8838 vmcs_write(EXIT_MSR_ST_ADDR, (u64)vm_exit_store); 8839 8840 /* 8841 * VM-Enter should succeed up to the max number of MSRs per list, and 8842 * should not consume junk beyond the last entry. 8843 */ 8844 populate_msr_list(vm_enter_load, byte_capacity, count); 8845 populate_msr_list(vm_exit_load, byte_capacity, exit_count); 8846 populate_msr_list(vm_exit_store, byte_capacity, exit_count); 8847 8848 vmcs_write(ENT_MSR_LD_CNT, count); 8849 vmcs_write(EXI_MSR_LD_CNT, exit_count); 8850 vmcs_write(EXI_MSR_ST_CNT, exit_count); 8851 8852 if (count <= max_allowed) { 8853 enter_guest(); 8854 assert_exit_reason(VMX_VMCALL); 8855 skip_exit_vmcall(); 8856 } else { 8857 u32 exit_reason; 8858 u32 exit_reason_want; 8859 u32 exit_qual; 8860 8861 enter_guest_with_invalid_guest_state(); 8862 8863 exit_reason = vmcs_read(EXI_REASON); 8864 exit_reason_want = VMX_FAIL_MSR | VMX_ENTRY_FAILURE; 8865 report("exit_reason, %u, is %u.", 8866 exit_reason == exit_reason_want, exit_reason, 8867 exit_reason_want); 8868 8869 exit_qual = vmcs_read(EXI_QUALIFICATION); 8870 report("exit_qual, %u, is %u.", exit_qual == max_allowed + 1, 8871 exit_qual, max_allowed + 1); 8872 } 8873 8874 /* Cleanup. */ 8875 vmcs_write(ENT_MSR_LD_CNT, 0); 8876 vmcs_write(EXI_MSR_LD_CNT, 0); 8877 vmcs_write(EXI_MSR_ST_CNT, 0); 8878 for (i = 0; i < cleanup_count; i++) { 8879 enter_guest(); 8880 skip_exit_vmcall(); 8881 } 8882 free_pages_by_order(vm_enter_load, msr_list_page_order); 8883 free_pages_by_order(vm_exit_load, msr_list_page_order); 8884 free_pages_by_order(vm_exit_store, msr_list_page_order); 8885 } 8886 8887 static void atomic_switch_max_msrs_test(void) 8888 { 8889 atomic_switch_msrs_test(max_msr_list_size()); 8890 } 8891 8892 static void atomic_switch_overflow_msrs_test(void) 8893 { 8894 atomic_switch_msrs_test(max_msr_list_size() + 1); 8895 } 8896 8897 #define TEST(name) { #name, .v2 = name } 8898 8899 /* name/init/guest_main/exit_handler/syscall_handler/guest_regs */ 8900 struct vmx_test vmx_tests[] = { 8901 { "null", NULL, basic_guest_main, basic_exit_handler, NULL, {0} }, 8902 { "vmenter", NULL, vmenter_main, vmenter_exit_handler, NULL, {0} }, 8903 { "preemption timer", preemption_timer_init, preemption_timer_main, 8904 preemption_timer_exit_handler, NULL, {0} }, 8905 { "control field PAT", test_ctrl_pat_init, test_ctrl_pat_main, 8906 test_ctrl_pat_exit_handler, NULL, {0} }, 8907 { "control field EFER", test_ctrl_efer_init, test_ctrl_efer_main, 8908 test_ctrl_efer_exit_handler, NULL, {0} }, 8909 { "CR shadowing", NULL, cr_shadowing_main, 8910 cr_shadowing_exit_handler, NULL, {0} }, 8911 { "I/O bitmap", iobmp_init, iobmp_main, iobmp_exit_handler, 8912 NULL, {0} }, 8913 { "instruction intercept", insn_intercept_init, insn_intercept_main, 8914 insn_intercept_exit_handler, NULL, {0} }, 8915 { "EPT A/D disabled", ept_init, ept_main, ept_exit_handler, NULL, {0} }, 8916 { "EPT A/D enabled", eptad_init, eptad_main, eptad_exit_handler, NULL, {0} }, 8917 { "PML", pml_init, pml_main, pml_exit_handler, NULL, {0} }, 8918 { "VPID", vpid_init, vpid_main, vpid_exit_handler, NULL, {0} }, 8919 { "interrupt", interrupt_init, interrupt_main, 8920 interrupt_exit_handler, NULL, {0} }, 8921 { "debug controls", dbgctls_init, dbgctls_main, dbgctls_exit_handler, 8922 NULL, {0} }, 8923 { "MSR switch", msr_switch_init, msr_switch_main, 8924 msr_switch_exit_handler, NULL, {0}, msr_switch_entry_failure }, 8925 { "vmmcall", vmmcall_init, vmmcall_main, vmmcall_exit_handler, NULL, {0} }, 8926 { "disable RDTSCP", disable_rdtscp_init, disable_rdtscp_main, 8927 disable_rdtscp_exit_handler, NULL, {0} }, 8928 { "int3", int3_init, int3_guest_main, int3_exit_handler, NULL, {0} }, 8929 { "into", into_init, into_guest_main, into_exit_handler, NULL, {0} }, 8930 { "exit_monitor_from_l2_test", NULL, exit_monitor_from_l2_main, 8931 exit_monitor_from_l2_handler, NULL, {0} }, 8932 { "invalid_msr", invalid_msr_init, invalid_msr_main, 8933 invalid_msr_exit_handler, NULL, {0}, invalid_msr_entry_failure}, 8934 /* Basic V2 tests. */ 8935 TEST(v2_null_test), 8936 TEST(v2_multiple_entries_test), 8937 TEST(fixture_test_case1), 8938 TEST(fixture_test_case2), 8939 /* Opcode tests. */ 8940 TEST(invvpid_test_v2), 8941 /* VM-entry tests */ 8942 TEST(vmx_controls_test), 8943 TEST(vmx_host_state_area_test), 8944 TEST(vmx_guest_state_area_test), 8945 TEST(vmentry_movss_shadow_test), 8946 /* APICv tests */ 8947 TEST(vmx_eoi_bitmap_ioapic_scan_test), 8948 TEST(vmx_hlt_with_rvi_test), 8949 TEST(apic_reg_virt_test), 8950 TEST(virt_x2apic_mode_test), 8951 /* APIC pass-through tests */ 8952 TEST(vmx_apic_passthrough_test), 8953 TEST(vmx_apic_passthrough_thread_test), 8954 TEST(vmx_init_signal_test), 8955 /* VMCS Shadowing tests */ 8956 TEST(vmx_vmcs_shadow_test), 8957 /* Regression tests */ 8958 TEST(vmx_cr_load_test), 8959 TEST(vmx_nm_test), 8960 TEST(vmx_db_test), 8961 TEST(vmx_nmi_window_test), 8962 TEST(vmx_intr_window_test), 8963 TEST(vmx_pending_event_test), 8964 TEST(vmx_pending_event_hlt_test), 8965 TEST(vmx_store_tsc_test), 8966 /* EPT access tests. */ 8967 TEST(ept_access_test_not_present), 8968 TEST(ept_access_test_read_only), 8969 TEST(ept_access_test_write_only), 8970 TEST(ept_access_test_read_write), 8971 TEST(ept_access_test_execute_only), 8972 TEST(ept_access_test_read_execute), 8973 TEST(ept_access_test_write_execute), 8974 TEST(ept_access_test_read_write_execute), 8975 TEST(ept_access_test_reserved_bits), 8976 TEST(ept_access_test_ignored_bits), 8977 TEST(ept_access_test_paddr_not_present_ad_disabled), 8978 TEST(ept_access_test_paddr_not_present_ad_enabled), 8979 TEST(ept_access_test_paddr_read_only_ad_disabled), 8980 TEST(ept_access_test_paddr_read_only_ad_enabled), 8981 TEST(ept_access_test_paddr_read_write), 8982 TEST(ept_access_test_paddr_read_write_execute), 8983 TEST(ept_access_test_paddr_read_execute_ad_disabled), 8984 TEST(ept_access_test_paddr_read_execute_ad_enabled), 8985 TEST(ept_access_test_paddr_not_present_page_fault), 8986 TEST(ept_access_test_force_2m_page), 8987 /* Atomic MSR switch tests. */ 8988 TEST(atomic_switch_max_msrs_test), 8989 TEST(atomic_switch_overflow_msrs_test), 8990 { NULL, NULL, NULL, NULL, NULL, {0} }, 8991 }; 8992