1 /* 2 * All test cases of nested virtualization should be in this file 3 * 4 * Author : Arthur Chunqi Li <yzt356@gmail.com> 5 */ 6 7 #include <asm/debugreg.h> 8 9 #include "vmx.h" 10 #include "msr.h" 11 #include "processor.h" 12 #include "vm.h" 13 #include "pci.h" 14 #include "fwcfg.h" 15 #include "isr.h" 16 #include "desc.h" 17 #include "apic.h" 18 #include "types.h" 19 #include "vmalloc.h" 20 #include "alloc_page.h" 21 #include "smp.h" 22 #include "delay.h" 23 24 #define NONCANONICAL 0xaaaaaaaaaaaaaaaaull 25 26 #define VPID_CAP_INVVPID_TYPES_SHIFT 40 27 28 u64 ia32_pat; 29 u64 ia32_efer; 30 void *io_bitmap_a, *io_bitmap_b; 31 u16 ioport; 32 33 unsigned long *pml4; 34 u64 eptp; 35 void *data_page1, *data_page2; 36 37 phys_addr_t pci_physaddr; 38 39 void *pml_log; 40 #define PML_INDEX 512 41 42 static inline unsigned ffs(unsigned x) 43 { 44 int pos = -1; 45 46 __asm__ __volatile__("bsf %1, %%eax; cmovnz %%eax, %0" 47 : "+r"(pos) : "rm"(x) : "eax"); 48 return pos + 1; 49 } 50 51 static inline void vmcall(void) 52 { 53 asm volatile("vmcall"); 54 } 55 56 static void basic_guest_main(void) 57 { 58 report("Basic VMX test", 1); 59 } 60 61 static int basic_exit_handler(void) 62 { 63 report("Basic VMX test", 0); 64 print_vmexit_info(); 65 return VMX_TEST_EXIT; 66 } 67 68 static void vmenter_main(void) 69 { 70 u64 rax; 71 u64 rsp, resume_rsp; 72 73 report("test vmlaunch", 1); 74 75 asm volatile( 76 "mov %%rsp, %0\n\t" 77 "mov %3, %%rax\n\t" 78 "vmcall\n\t" 79 "mov %%rax, %1\n\t" 80 "mov %%rsp, %2\n\t" 81 : "=r"(rsp), "=r"(rax), "=r"(resume_rsp) 82 : "g"(0xABCD)); 83 report("test vmresume", (rax == 0xFFFF) && (rsp == resume_rsp)); 84 } 85 86 static int vmenter_exit_handler(void) 87 { 88 u64 guest_rip; 89 ulong reason; 90 91 guest_rip = vmcs_read(GUEST_RIP); 92 reason = vmcs_read(EXI_REASON) & 0xff; 93 switch (reason) { 94 case VMX_VMCALL: 95 if (regs.rax != 0xABCD) { 96 report("test vmresume", 0); 97 return VMX_TEST_VMEXIT; 98 } 99 regs.rax = 0xFFFF; 100 vmcs_write(GUEST_RIP, guest_rip + 3); 101 return VMX_TEST_RESUME; 102 default: 103 report("test vmresume", 0); 104 print_vmexit_info(); 105 } 106 return VMX_TEST_VMEXIT; 107 } 108 109 u32 preempt_scale; 110 volatile unsigned long long tsc_val; 111 volatile u32 preempt_val; 112 u64 saved_rip; 113 114 static int preemption_timer_init(struct vmcs *vmcs) 115 { 116 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 117 printf("\tPreemption timer is not supported\n"); 118 return VMX_TEST_EXIT; 119 } 120 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 121 preempt_val = 10000000; 122 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 123 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 124 125 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 126 printf("\tSave preemption value is not supported\n"); 127 128 return VMX_TEST_START; 129 } 130 131 static void preemption_timer_main(void) 132 { 133 tsc_val = rdtsc(); 134 if (ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) { 135 vmx_set_test_stage(0); 136 vmcall(); 137 if (vmx_get_test_stage() == 1) 138 vmcall(); 139 } 140 vmx_set_test_stage(1); 141 while (vmx_get_test_stage() == 1) { 142 if (((rdtsc() - tsc_val) >> preempt_scale) 143 > 10 * preempt_val) { 144 vmx_set_test_stage(2); 145 vmcall(); 146 } 147 } 148 tsc_val = rdtsc(); 149 asm volatile ("hlt"); 150 vmcall(); 151 vmx_set_test_stage(5); 152 vmcall(); 153 } 154 155 static int preemption_timer_exit_handler(void) 156 { 157 bool guest_halted; 158 u64 guest_rip; 159 ulong reason; 160 u32 insn_len; 161 u32 ctrl_exit; 162 163 guest_rip = vmcs_read(GUEST_RIP); 164 reason = vmcs_read(EXI_REASON) & 0xff; 165 insn_len = vmcs_read(EXI_INST_LEN); 166 switch (reason) { 167 case VMX_PREEMPT: 168 switch (vmx_get_test_stage()) { 169 case 1: 170 case 2: 171 report("busy-wait for preemption timer", 172 ((rdtsc() - tsc_val) >> preempt_scale) >= 173 preempt_val); 174 vmx_set_test_stage(3); 175 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 176 return VMX_TEST_RESUME; 177 case 3: 178 guest_halted = 179 (vmcs_read(GUEST_ACTV_STATE) == ACTV_HLT); 180 report("preemption timer during hlt", 181 ((rdtsc() - tsc_val) >> preempt_scale) >= 182 preempt_val && guest_halted); 183 vmx_set_test_stage(4); 184 vmcs_write(PIN_CONTROLS, 185 vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 186 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 187 return VMX_TEST_RESUME; 188 case 4: 189 report("preemption timer with 0 value", 190 saved_rip == guest_rip); 191 break; 192 default: 193 report("Invalid stage.", false); 194 print_vmexit_info(); 195 break; 196 } 197 break; 198 case VMX_VMCALL: 199 vmcs_write(GUEST_RIP, guest_rip + insn_len); 200 switch (vmx_get_test_stage()) { 201 case 0: 202 report("Keep preemption value", 203 vmcs_read(PREEMPT_TIMER_VALUE) == preempt_val); 204 vmx_set_test_stage(1); 205 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 206 ctrl_exit = (vmcs_read(EXI_CONTROLS) | 207 EXI_SAVE_PREEMPT) & ctrl_exit_rev.clr; 208 vmcs_write(EXI_CONTROLS, ctrl_exit); 209 return VMX_TEST_RESUME; 210 case 1: 211 report("Save preemption value", 212 vmcs_read(PREEMPT_TIMER_VALUE) < preempt_val); 213 return VMX_TEST_RESUME; 214 case 2: 215 report("busy-wait for preemption timer", 0); 216 vmx_set_test_stage(3); 217 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 218 return VMX_TEST_RESUME; 219 case 3: 220 report("preemption timer during hlt", 0); 221 vmx_set_test_stage(4); 222 /* fall through */ 223 case 4: 224 vmcs_write(PIN_CONTROLS, 225 vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 226 vmcs_write(PREEMPT_TIMER_VALUE, 0); 227 saved_rip = guest_rip + insn_len; 228 return VMX_TEST_RESUME; 229 case 5: 230 report("preemption timer with 0 value (vmcall stage 5)", 0); 231 break; 232 default: 233 // Should not reach here 234 report("unexpected stage, %d", false, 235 vmx_get_test_stage()); 236 print_vmexit_info(); 237 return VMX_TEST_VMEXIT; 238 } 239 break; 240 default: 241 report("Unknown exit reason, %ld", false, reason); 242 print_vmexit_info(); 243 } 244 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 245 return VMX_TEST_VMEXIT; 246 } 247 248 static void msr_bmp_init(void) 249 { 250 void *msr_bitmap; 251 u32 ctrl_cpu0; 252 253 msr_bitmap = alloc_page(); 254 memset(msr_bitmap, 0x0, PAGE_SIZE); 255 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 256 ctrl_cpu0 |= CPU_MSR_BITMAP; 257 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 258 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 259 } 260 261 static void *get_msr_bitmap(void) 262 { 263 void *msr_bitmap; 264 265 if (vmcs_read(CPU_EXEC_CTRL0) & CPU_MSR_BITMAP) { 266 msr_bitmap = (void *)vmcs_read(MSR_BITMAP); 267 } else { 268 msr_bitmap = alloc_page(); 269 memset(msr_bitmap, 0xff, PAGE_SIZE); 270 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 271 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_MSR_BITMAP); 272 } 273 274 return msr_bitmap; 275 } 276 277 static void disable_intercept_for_x2apic_msrs(void) 278 { 279 unsigned long *msr_bitmap = (unsigned long *)get_msr_bitmap(); 280 u32 msr; 281 282 for (msr = APIC_BASE_MSR; 283 msr < (APIC_BASE_MSR+0xff); 284 msr += BITS_PER_LONG) { 285 unsigned int word = msr / BITS_PER_LONG; 286 287 msr_bitmap[word] = 0; 288 msr_bitmap[word + (0x800 / sizeof(long))] = 0; 289 } 290 } 291 292 static int test_ctrl_pat_init(struct vmcs *vmcs) 293 { 294 u64 ctrl_ent; 295 u64 ctrl_exi; 296 297 msr_bmp_init(); 298 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT) && 299 !(ctrl_exit_rev.clr & EXI_LOAD_PAT) && 300 !(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 301 printf("\tSave/load PAT is not supported\n"); 302 return 1; 303 } 304 305 ctrl_ent = vmcs_read(ENT_CONTROLS); 306 ctrl_exi = vmcs_read(EXI_CONTROLS); 307 ctrl_ent |= ctrl_enter_rev.clr & ENT_LOAD_PAT; 308 ctrl_exi |= ctrl_exit_rev.clr & (EXI_SAVE_PAT | EXI_LOAD_PAT); 309 vmcs_write(ENT_CONTROLS, ctrl_ent); 310 vmcs_write(EXI_CONTROLS, ctrl_exi); 311 ia32_pat = rdmsr(MSR_IA32_CR_PAT); 312 vmcs_write(GUEST_PAT, 0x0); 313 vmcs_write(HOST_PAT, ia32_pat); 314 return VMX_TEST_START; 315 } 316 317 static void test_ctrl_pat_main(void) 318 { 319 u64 guest_ia32_pat; 320 321 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 322 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) 323 printf("\tENT_LOAD_PAT is not supported.\n"); 324 else { 325 if (guest_ia32_pat != 0) { 326 report("Entry load PAT", 0); 327 return; 328 } 329 } 330 wrmsr(MSR_IA32_CR_PAT, 0x6); 331 vmcall(); 332 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 333 if (ctrl_enter_rev.clr & ENT_LOAD_PAT) 334 report("Entry load PAT", guest_ia32_pat == ia32_pat); 335 } 336 337 static int test_ctrl_pat_exit_handler(void) 338 { 339 u64 guest_rip; 340 ulong reason; 341 u64 guest_pat; 342 343 guest_rip = vmcs_read(GUEST_RIP); 344 reason = vmcs_read(EXI_REASON) & 0xff; 345 switch (reason) { 346 case VMX_VMCALL: 347 guest_pat = vmcs_read(GUEST_PAT); 348 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT)) { 349 printf("\tEXI_SAVE_PAT is not supported\n"); 350 vmcs_write(GUEST_PAT, 0x6); 351 } else { 352 report("Exit save PAT", guest_pat == 0x6); 353 } 354 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) 355 printf("\tEXI_LOAD_PAT is not supported\n"); 356 else 357 report("Exit load PAT", rdmsr(MSR_IA32_CR_PAT) == ia32_pat); 358 vmcs_write(GUEST_PAT, ia32_pat); 359 vmcs_write(GUEST_RIP, guest_rip + 3); 360 return VMX_TEST_RESUME; 361 default: 362 printf("ERROR : Undefined exit reason, reason = %ld.\n", reason); 363 break; 364 } 365 return VMX_TEST_VMEXIT; 366 } 367 368 static int test_ctrl_efer_init(struct vmcs *vmcs) 369 { 370 u64 ctrl_ent; 371 u64 ctrl_exi; 372 373 msr_bmp_init(); 374 ctrl_ent = vmcs_read(ENT_CONTROLS) | ENT_LOAD_EFER; 375 ctrl_exi = vmcs_read(EXI_CONTROLS) | EXI_SAVE_EFER | EXI_LOAD_EFER; 376 vmcs_write(ENT_CONTROLS, ctrl_ent & ctrl_enter_rev.clr); 377 vmcs_write(EXI_CONTROLS, ctrl_exi & ctrl_exit_rev.clr); 378 ia32_efer = rdmsr(MSR_EFER); 379 vmcs_write(GUEST_EFER, ia32_efer ^ EFER_NX); 380 vmcs_write(HOST_EFER, ia32_efer ^ EFER_NX); 381 return VMX_TEST_START; 382 } 383 384 static void test_ctrl_efer_main(void) 385 { 386 u64 guest_ia32_efer; 387 388 guest_ia32_efer = rdmsr(MSR_EFER); 389 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) 390 printf("\tENT_LOAD_EFER is not supported.\n"); 391 else { 392 if (guest_ia32_efer != (ia32_efer ^ EFER_NX)) { 393 report("Entry load EFER", 0); 394 return; 395 } 396 } 397 wrmsr(MSR_EFER, ia32_efer); 398 vmcall(); 399 guest_ia32_efer = rdmsr(MSR_EFER); 400 if (ctrl_enter_rev.clr & ENT_LOAD_EFER) 401 report("Entry load EFER", guest_ia32_efer == ia32_efer); 402 } 403 404 static int test_ctrl_efer_exit_handler(void) 405 { 406 u64 guest_rip; 407 ulong reason; 408 u64 guest_efer; 409 410 guest_rip = vmcs_read(GUEST_RIP); 411 reason = vmcs_read(EXI_REASON) & 0xff; 412 switch (reason) { 413 case VMX_VMCALL: 414 guest_efer = vmcs_read(GUEST_EFER); 415 if (!(ctrl_exit_rev.clr & EXI_SAVE_EFER)) { 416 printf("\tEXI_SAVE_EFER is not supported\n"); 417 vmcs_write(GUEST_EFER, ia32_efer); 418 } else { 419 report("Exit save EFER", guest_efer == ia32_efer); 420 } 421 if (!(ctrl_exit_rev.clr & EXI_LOAD_EFER)) { 422 printf("\tEXI_LOAD_EFER is not supported\n"); 423 wrmsr(MSR_EFER, ia32_efer ^ EFER_NX); 424 } else { 425 report("Exit load EFER", rdmsr(MSR_EFER) == (ia32_efer ^ EFER_NX)); 426 } 427 vmcs_write(GUEST_PAT, ia32_efer); 428 vmcs_write(GUEST_RIP, guest_rip + 3); 429 return VMX_TEST_RESUME; 430 default: 431 printf("ERROR : Undefined exit reason, reason = %ld.\n", reason); 432 break; 433 } 434 return VMX_TEST_VMEXIT; 435 } 436 437 u32 guest_cr0, guest_cr4; 438 439 static void cr_shadowing_main(void) 440 { 441 u32 cr0, cr4, tmp; 442 443 // Test read through 444 vmx_set_test_stage(0); 445 guest_cr0 = read_cr0(); 446 if (vmx_get_test_stage() == 1) 447 report("Read through CR0", 0); 448 else 449 vmcall(); 450 vmx_set_test_stage(1); 451 guest_cr4 = read_cr4(); 452 if (vmx_get_test_stage() == 2) 453 report("Read through CR4", 0); 454 else 455 vmcall(); 456 // Test write through 457 guest_cr0 = guest_cr0 ^ (X86_CR0_TS | X86_CR0_MP); 458 guest_cr4 = guest_cr4 ^ (X86_CR4_TSD | X86_CR4_DE); 459 vmx_set_test_stage(2); 460 write_cr0(guest_cr0); 461 if (vmx_get_test_stage() == 3) 462 report("Write throuth CR0", 0); 463 else 464 vmcall(); 465 vmx_set_test_stage(3); 466 write_cr4(guest_cr4); 467 if (vmx_get_test_stage() == 4) 468 report("Write through CR4", 0); 469 else 470 vmcall(); 471 // Test read shadow 472 vmx_set_test_stage(4); 473 vmcall(); 474 cr0 = read_cr0(); 475 if (vmx_get_test_stage() != 5) 476 report("Read shadowing CR0", cr0 == guest_cr0); 477 vmx_set_test_stage(5); 478 cr4 = read_cr4(); 479 if (vmx_get_test_stage() != 6) 480 report("Read shadowing CR4", cr4 == guest_cr4); 481 // Test write shadow (same value with shadow) 482 vmx_set_test_stage(6); 483 write_cr0(guest_cr0); 484 if (vmx_get_test_stage() == 7) 485 report("Write shadowing CR0 (same value with shadow)", 0); 486 else 487 vmcall(); 488 vmx_set_test_stage(7); 489 write_cr4(guest_cr4); 490 if (vmx_get_test_stage() == 8) 491 report("Write shadowing CR4 (same value with shadow)", 0); 492 else 493 vmcall(); 494 // Test write shadow (different value) 495 vmx_set_test_stage(8); 496 tmp = guest_cr0 ^ X86_CR0_TS; 497 asm volatile("mov %0, %%rsi\n\t" 498 "mov %%rsi, %%cr0\n\t" 499 ::"m"(tmp) 500 :"rsi", "memory", "cc"); 501 report("Write shadowing different X86_CR0_TS", vmx_get_test_stage() == 9); 502 vmx_set_test_stage(9); 503 tmp = guest_cr0 ^ X86_CR0_MP; 504 asm volatile("mov %0, %%rsi\n\t" 505 "mov %%rsi, %%cr0\n\t" 506 ::"m"(tmp) 507 :"rsi", "memory", "cc"); 508 report("Write shadowing different X86_CR0_MP", vmx_get_test_stage() == 10); 509 vmx_set_test_stage(10); 510 tmp = guest_cr4 ^ X86_CR4_TSD; 511 asm volatile("mov %0, %%rsi\n\t" 512 "mov %%rsi, %%cr4\n\t" 513 ::"m"(tmp) 514 :"rsi", "memory", "cc"); 515 report("Write shadowing different X86_CR4_TSD", vmx_get_test_stage() == 11); 516 vmx_set_test_stage(11); 517 tmp = guest_cr4 ^ X86_CR4_DE; 518 asm volatile("mov %0, %%rsi\n\t" 519 "mov %%rsi, %%cr4\n\t" 520 ::"m"(tmp) 521 :"rsi", "memory", "cc"); 522 report("Write shadowing different X86_CR4_DE", vmx_get_test_stage() == 12); 523 } 524 525 static int cr_shadowing_exit_handler(void) 526 { 527 u64 guest_rip; 528 ulong reason; 529 u32 insn_len; 530 u32 exit_qual; 531 532 guest_rip = vmcs_read(GUEST_RIP); 533 reason = vmcs_read(EXI_REASON) & 0xff; 534 insn_len = vmcs_read(EXI_INST_LEN); 535 exit_qual = vmcs_read(EXI_QUALIFICATION); 536 switch (reason) { 537 case VMX_VMCALL: 538 switch (vmx_get_test_stage()) { 539 case 0: 540 report("Read through CR0", guest_cr0 == vmcs_read(GUEST_CR0)); 541 break; 542 case 1: 543 report("Read through CR4", guest_cr4 == vmcs_read(GUEST_CR4)); 544 break; 545 case 2: 546 report("Write through CR0", guest_cr0 == vmcs_read(GUEST_CR0)); 547 break; 548 case 3: 549 report("Write through CR4", guest_cr4 == vmcs_read(GUEST_CR4)); 550 break; 551 case 4: 552 guest_cr0 = vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP); 553 guest_cr4 = vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE); 554 vmcs_write(CR0_MASK, X86_CR0_TS | X86_CR0_MP); 555 vmcs_write(CR0_READ_SHADOW, guest_cr0 & (X86_CR0_TS | X86_CR0_MP)); 556 vmcs_write(CR4_MASK, X86_CR4_TSD | X86_CR4_DE); 557 vmcs_write(CR4_READ_SHADOW, guest_cr4 & (X86_CR4_TSD | X86_CR4_DE)); 558 break; 559 case 6: 560 report("Write shadowing CR0 (same value)", 561 guest_cr0 == (vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP))); 562 break; 563 case 7: 564 report("Write shadowing CR4 (same value)", 565 guest_cr4 == (vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE))); 566 break; 567 default: 568 // Should not reach here 569 report("unexpected stage, %d", false, 570 vmx_get_test_stage()); 571 print_vmexit_info(); 572 return VMX_TEST_VMEXIT; 573 } 574 vmcs_write(GUEST_RIP, guest_rip + insn_len); 575 return VMX_TEST_RESUME; 576 case VMX_CR: 577 switch (vmx_get_test_stage()) { 578 case 4: 579 report("Read shadowing CR0", 0); 580 vmx_inc_test_stage(); 581 break; 582 case 5: 583 report("Read shadowing CR4", 0); 584 vmx_inc_test_stage(); 585 break; 586 case 6: 587 report("Write shadowing CR0 (same value)", 0); 588 vmx_inc_test_stage(); 589 break; 590 case 7: 591 report("Write shadowing CR4 (same value)", 0); 592 vmx_inc_test_stage(); 593 break; 594 case 8: 595 case 9: 596 // 0x600 encodes "mov %esi, %cr0" 597 if (exit_qual == 0x600) 598 vmx_inc_test_stage(); 599 break; 600 case 10: 601 case 11: 602 // 0x604 encodes "mov %esi, %cr4" 603 if (exit_qual == 0x604) 604 vmx_inc_test_stage(); 605 break; 606 default: 607 // Should not reach here 608 report("unexpected stage, %d", false, 609 vmx_get_test_stage()); 610 print_vmexit_info(); 611 return VMX_TEST_VMEXIT; 612 } 613 vmcs_write(GUEST_RIP, guest_rip + insn_len); 614 return VMX_TEST_RESUME; 615 default: 616 report("Unknown exit reason, %ld", false, reason); 617 print_vmexit_info(); 618 } 619 return VMX_TEST_VMEXIT; 620 } 621 622 static int iobmp_init(struct vmcs *vmcs) 623 { 624 u32 ctrl_cpu0; 625 626 io_bitmap_a = alloc_page(); 627 io_bitmap_b = alloc_page(); 628 memset(io_bitmap_a, 0x0, PAGE_SIZE); 629 memset(io_bitmap_b, 0x0, PAGE_SIZE); 630 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 631 ctrl_cpu0 |= CPU_IO_BITMAP; 632 ctrl_cpu0 &= (~CPU_IO); 633 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 634 vmcs_write(IO_BITMAP_A, (u64)io_bitmap_a); 635 vmcs_write(IO_BITMAP_B, (u64)io_bitmap_b); 636 return VMX_TEST_START; 637 } 638 639 static void iobmp_main(void) 640 { 641 // stage 0, test IO pass 642 vmx_set_test_stage(0); 643 inb(0x5000); 644 outb(0x0, 0x5000); 645 report("I/O bitmap - I/O pass", vmx_get_test_stage() == 0); 646 // test IO width, in/out 647 ((u8 *)io_bitmap_a)[0] = 0xFF; 648 vmx_set_test_stage(2); 649 inb(0x0); 650 report("I/O bitmap - trap in", vmx_get_test_stage() == 3); 651 vmx_set_test_stage(3); 652 outw(0x0, 0x0); 653 report("I/O bitmap - trap out", vmx_get_test_stage() == 4); 654 vmx_set_test_stage(4); 655 inl(0x0); 656 report("I/O bitmap - I/O width, long", vmx_get_test_stage() == 5); 657 // test low/high IO port 658 vmx_set_test_stage(5); 659 ((u8 *)io_bitmap_a)[0x5000 / 8] = (1 << (0x5000 % 8)); 660 inb(0x5000); 661 report("I/O bitmap - I/O port, low part", vmx_get_test_stage() == 6); 662 vmx_set_test_stage(6); 663 ((u8 *)io_bitmap_b)[0x1000 / 8] = (1 << (0x1000 % 8)); 664 inb(0x9000); 665 report("I/O bitmap - I/O port, high part", vmx_get_test_stage() == 7); 666 // test partial pass 667 vmx_set_test_stage(7); 668 inl(0x4FFF); 669 report("I/O bitmap - partial pass", vmx_get_test_stage() == 8); 670 // test overrun 671 vmx_set_test_stage(8); 672 memset(io_bitmap_a, 0x0, PAGE_SIZE); 673 memset(io_bitmap_b, 0x0, PAGE_SIZE); 674 inl(0xFFFF); 675 report("I/O bitmap - overrun", vmx_get_test_stage() == 9); 676 vmx_set_test_stage(9); 677 vmcall(); 678 outb(0x0, 0x0); 679 report("I/O bitmap - ignore unconditional exiting", 680 vmx_get_test_stage() == 9); 681 vmx_set_test_stage(10); 682 vmcall(); 683 outb(0x0, 0x0); 684 report("I/O bitmap - unconditional exiting", 685 vmx_get_test_stage() == 11); 686 } 687 688 static int iobmp_exit_handler(void) 689 { 690 u64 guest_rip; 691 ulong reason, exit_qual; 692 u32 insn_len, ctrl_cpu0; 693 694 guest_rip = vmcs_read(GUEST_RIP); 695 reason = vmcs_read(EXI_REASON) & 0xff; 696 exit_qual = vmcs_read(EXI_QUALIFICATION); 697 insn_len = vmcs_read(EXI_INST_LEN); 698 switch (reason) { 699 case VMX_IO: 700 switch (vmx_get_test_stage()) { 701 case 0: 702 case 1: 703 vmx_inc_test_stage(); 704 break; 705 case 2: 706 report("I/O bitmap - I/O width, byte", 707 (exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_BYTE); 708 report("I/O bitmap - I/O direction, in", exit_qual & VMX_IO_IN); 709 vmx_inc_test_stage(); 710 break; 711 case 3: 712 report("I/O bitmap - I/O width, word", 713 (exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_WORD); 714 report("I/O bitmap - I/O direction, out", 715 !(exit_qual & VMX_IO_IN)); 716 vmx_inc_test_stage(); 717 break; 718 case 4: 719 report("I/O bitmap - I/O width, long", 720 (exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_LONG); 721 vmx_inc_test_stage(); 722 break; 723 case 5: 724 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x5000) 725 vmx_inc_test_stage(); 726 break; 727 case 6: 728 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x9000) 729 vmx_inc_test_stage(); 730 break; 731 case 7: 732 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x4FFF) 733 vmx_inc_test_stage(); 734 break; 735 case 8: 736 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0xFFFF) 737 vmx_inc_test_stage(); 738 break; 739 case 9: 740 case 10: 741 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 742 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0 & ~CPU_IO); 743 vmx_inc_test_stage(); 744 break; 745 default: 746 // Should not reach here 747 report("unexpected stage, %d", false, 748 vmx_get_test_stage()); 749 print_vmexit_info(); 750 return VMX_TEST_VMEXIT; 751 } 752 vmcs_write(GUEST_RIP, guest_rip + insn_len); 753 return VMX_TEST_RESUME; 754 case VMX_VMCALL: 755 switch (vmx_get_test_stage()) { 756 case 9: 757 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 758 ctrl_cpu0 |= CPU_IO | CPU_IO_BITMAP; 759 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 760 break; 761 case 10: 762 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 763 ctrl_cpu0 = (ctrl_cpu0 & ~CPU_IO_BITMAP) | CPU_IO; 764 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 765 break; 766 default: 767 // Should not reach here 768 report("unexpected stage, %d", false, 769 vmx_get_test_stage()); 770 print_vmexit_info(); 771 return VMX_TEST_VMEXIT; 772 } 773 vmcs_write(GUEST_RIP, guest_rip + insn_len); 774 return VMX_TEST_RESUME; 775 default: 776 printf("guest_rip = %#lx\n", guest_rip); 777 printf("\tERROR : Undefined exit reason, reason = %ld.\n", reason); 778 break; 779 } 780 return VMX_TEST_VMEXIT; 781 } 782 783 #define INSN_CPU0 0 784 #define INSN_CPU1 1 785 #define INSN_ALWAYS_TRAP 2 786 787 #define FIELD_EXIT_QUAL (1 << 0) 788 #define FIELD_INSN_INFO (1 << 1) 789 790 asm( 791 "insn_hlt: hlt;ret\n\t" 792 "insn_invlpg: invlpg 0x12345678;ret\n\t" 793 "insn_mwait: xor %eax, %eax; xor %ecx, %ecx; mwait;ret\n\t" 794 "insn_rdpmc: xor %ecx, %ecx; rdpmc;ret\n\t" 795 "insn_rdtsc: rdtsc;ret\n\t" 796 "insn_cr3_load: mov cr3,%rax; mov %rax,%cr3;ret\n\t" 797 "insn_cr3_store: mov %cr3,%rax;ret\n\t" 798 #ifdef __x86_64__ 799 "insn_cr8_load: xor %eax, %eax; mov %rax,%cr8;ret\n\t" 800 "insn_cr8_store: mov %cr8,%rax;ret\n\t" 801 #endif 802 "insn_monitor: xor %eax, %eax; xor %ecx, %ecx; xor %edx, %edx; monitor;ret\n\t" 803 "insn_pause: pause;ret\n\t" 804 "insn_wbinvd: wbinvd;ret\n\t" 805 "insn_cpuid: mov $10, %eax; cpuid;ret\n\t" 806 "insn_invd: invd;ret\n\t" 807 "insn_sgdt: sgdt gdt64_desc;ret\n\t" 808 "insn_lgdt: lgdt gdt64_desc;ret\n\t" 809 "insn_sidt: sidt idt_descr;ret\n\t" 810 "insn_lidt: lidt idt_descr;ret\n\t" 811 "insn_sldt: sldt %ax;ret\n\t" 812 "insn_lldt: xor %eax, %eax; lldt %ax;ret\n\t" 813 "insn_str: str %ax;ret\n\t" 814 "insn_rdrand: rdrand %rax;ret\n\t" 815 "insn_rdseed: rdseed %rax;ret\n\t" 816 ); 817 extern void insn_hlt(void); 818 extern void insn_invlpg(void); 819 extern void insn_mwait(void); 820 extern void insn_rdpmc(void); 821 extern void insn_rdtsc(void); 822 extern void insn_cr3_load(void); 823 extern void insn_cr3_store(void); 824 #ifdef __x86_64__ 825 extern void insn_cr8_load(void); 826 extern void insn_cr8_store(void); 827 #endif 828 extern void insn_monitor(void); 829 extern void insn_pause(void); 830 extern void insn_wbinvd(void); 831 extern void insn_sgdt(void); 832 extern void insn_lgdt(void); 833 extern void insn_sidt(void); 834 extern void insn_lidt(void); 835 extern void insn_sldt(void); 836 extern void insn_lldt(void); 837 extern void insn_str(void); 838 extern void insn_cpuid(void); 839 extern void insn_invd(void); 840 extern void insn_rdrand(void); 841 extern void insn_rdseed(void); 842 843 u32 cur_insn; 844 u64 cr3; 845 846 struct insn_table { 847 const char *name; 848 u32 flag; 849 void (*insn_func)(void); 850 u32 type; 851 u32 reason; 852 ulong exit_qual; 853 u32 insn_info; 854 // Use FIELD_EXIT_QUAL and FIELD_INSN_INFO to define 855 // which field need to be tested, reason is always tested 856 u32 test_field; 857 }; 858 859 /* 860 * Add more test cases of instruction intercept here. Elements in this 861 * table is: 862 * name/control flag/insn function/type/exit reason/exit qulification/ 863 * instruction info/field to test 864 * The last field defines which fields (exit_qual and insn_info) need to be 865 * tested in exit handler. If set to 0, only "reason" is checked. 866 */ 867 static struct insn_table insn_table[] = { 868 // Flags for Primary Processor-Based VM-Execution Controls 869 {"HLT", CPU_HLT, insn_hlt, INSN_CPU0, 12, 0, 0, 0}, 870 {"INVLPG", CPU_INVLPG, insn_invlpg, INSN_CPU0, 14, 871 0x12345678, 0, FIELD_EXIT_QUAL}, 872 {"MWAIT", CPU_MWAIT, insn_mwait, INSN_CPU0, 36, 0, 0, 0}, 873 {"RDPMC", CPU_RDPMC, insn_rdpmc, INSN_CPU0, 15, 0, 0, 0}, 874 {"RDTSC", CPU_RDTSC, insn_rdtsc, INSN_CPU0, 16, 0, 0, 0}, 875 {"CR3 load", CPU_CR3_LOAD, insn_cr3_load, INSN_CPU0, 28, 0x3, 0, 876 FIELD_EXIT_QUAL}, 877 {"CR3 store", CPU_CR3_STORE, insn_cr3_store, INSN_CPU0, 28, 0x13, 0, 878 FIELD_EXIT_QUAL}, 879 #ifdef __x86_64__ 880 {"CR8 load", CPU_CR8_LOAD, insn_cr8_load, INSN_CPU0, 28, 0x8, 0, 881 FIELD_EXIT_QUAL}, 882 {"CR8 store", CPU_CR8_STORE, insn_cr8_store, INSN_CPU0, 28, 0x18, 0, 883 FIELD_EXIT_QUAL}, 884 #endif 885 {"MONITOR", CPU_MONITOR, insn_monitor, INSN_CPU0, 39, 0, 0, 0}, 886 {"PAUSE", CPU_PAUSE, insn_pause, INSN_CPU0, 40, 0, 0, 0}, 887 // Flags for Secondary Processor-Based VM-Execution Controls 888 {"WBINVD", CPU_WBINVD, insn_wbinvd, INSN_CPU1, 54, 0, 0, 0}, 889 {"DESC_TABLE (SGDT)", CPU_DESC_TABLE, insn_sgdt, INSN_CPU1, 46, 0, 0, 0}, 890 {"DESC_TABLE (LGDT)", CPU_DESC_TABLE, insn_lgdt, INSN_CPU1, 46, 0, 0, 0}, 891 {"DESC_TABLE (SIDT)", CPU_DESC_TABLE, insn_sidt, INSN_CPU1, 46, 0, 0, 0}, 892 {"DESC_TABLE (LIDT)", CPU_DESC_TABLE, insn_lidt, INSN_CPU1, 46, 0, 0, 0}, 893 {"DESC_TABLE (SLDT)", CPU_DESC_TABLE, insn_sldt, INSN_CPU1, 47, 0, 0, 0}, 894 {"DESC_TABLE (LLDT)", CPU_DESC_TABLE, insn_lldt, INSN_CPU1, 47, 0, 0, 0}, 895 {"DESC_TABLE (STR)", CPU_DESC_TABLE, insn_str, INSN_CPU1, 47, 0, 0, 0}, 896 /* LTR causes a #GP if done with a busy selector, so it is not tested. */ 897 {"RDRAND", CPU_RDRAND, insn_rdrand, INSN_CPU1, VMX_RDRAND, 0, 0, 0}, 898 {"RDSEED", CPU_RDSEED, insn_rdseed, INSN_CPU1, VMX_RDSEED, 0, 0, 0}, 899 // Instructions always trap 900 {"CPUID", 0, insn_cpuid, INSN_ALWAYS_TRAP, 10, 0, 0, 0}, 901 {"INVD", 0, insn_invd, INSN_ALWAYS_TRAP, 13, 0, 0, 0}, 902 // Instructions never trap 903 {NULL}, 904 }; 905 906 static int insn_intercept_init(struct vmcs *vmcs) 907 { 908 u32 ctrl_cpu; 909 910 ctrl_cpu = ctrl_cpu_rev[0].set | CPU_SECONDARY; 911 ctrl_cpu &= ctrl_cpu_rev[0].clr; 912 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu); 913 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu_rev[1].set); 914 cr3 = read_cr3(); 915 return VMX_TEST_START; 916 } 917 918 static void insn_intercept_main(void) 919 { 920 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 921 vmx_set_test_stage(cur_insn * 2); 922 if ((insn_table[cur_insn].type == INSN_CPU0 && 923 !(ctrl_cpu_rev[0].clr & insn_table[cur_insn].flag)) || 924 (insn_table[cur_insn].type == INSN_CPU1 && 925 !(ctrl_cpu_rev[1].clr & insn_table[cur_insn].flag))) { 926 printf("\tCPU_CTRL%d.CPU_%s is not supported.\n", 927 insn_table[cur_insn].type - INSN_CPU0, 928 insn_table[cur_insn].name); 929 continue; 930 } 931 932 if ((insn_table[cur_insn].type == INSN_CPU0 && 933 !(ctrl_cpu_rev[0].set & insn_table[cur_insn].flag)) || 934 (insn_table[cur_insn].type == INSN_CPU1 && 935 !(ctrl_cpu_rev[1].set & insn_table[cur_insn].flag))) { 936 /* skip hlt, it stalls the guest and is tested below */ 937 if (insn_table[cur_insn].insn_func != insn_hlt) 938 insn_table[cur_insn].insn_func(); 939 report("execute %s", vmx_get_test_stage() == cur_insn * 2, 940 insn_table[cur_insn].name); 941 } else if (insn_table[cur_insn].type != INSN_ALWAYS_TRAP) 942 printf("\tCPU_CTRL%d.CPU_%s always traps.\n", 943 insn_table[cur_insn].type - INSN_CPU0, 944 insn_table[cur_insn].name); 945 946 vmcall(); 947 948 insn_table[cur_insn].insn_func(); 949 report("intercept %s", vmx_get_test_stage() == cur_insn * 2 + 1, 950 insn_table[cur_insn].name); 951 952 vmx_set_test_stage(cur_insn * 2 + 1); 953 vmcall(); 954 } 955 } 956 957 static int insn_intercept_exit_handler(void) 958 { 959 u64 guest_rip; 960 u32 reason; 961 ulong exit_qual; 962 u32 insn_len; 963 u32 insn_info; 964 bool pass; 965 966 guest_rip = vmcs_read(GUEST_RIP); 967 reason = vmcs_read(EXI_REASON) & 0xff; 968 exit_qual = vmcs_read(EXI_QUALIFICATION); 969 insn_len = vmcs_read(EXI_INST_LEN); 970 insn_info = vmcs_read(EXI_INST_INFO); 971 972 if (reason == VMX_VMCALL) { 973 u32 val = 0; 974 975 if (insn_table[cur_insn].type == INSN_CPU0) 976 val = vmcs_read(CPU_EXEC_CTRL0); 977 else if (insn_table[cur_insn].type == INSN_CPU1) 978 val = vmcs_read(CPU_EXEC_CTRL1); 979 980 if (vmx_get_test_stage() & 1) 981 val &= ~insn_table[cur_insn].flag; 982 else 983 val |= insn_table[cur_insn].flag; 984 985 if (insn_table[cur_insn].type == INSN_CPU0) 986 vmcs_write(CPU_EXEC_CTRL0, val | ctrl_cpu_rev[0].set); 987 else if (insn_table[cur_insn].type == INSN_CPU1) 988 vmcs_write(CPU_EXEC_CTRL1, val | ctrl_cpu_rev[1].set); 989 } else { 990 pass = (cur_insn * 2 == vmx_get_test_stage()) && 991 insn_table[cur_insn].reason == reason; 992 if (insn_table[cur_insn].test_field & FIELD_EXIT_QUAL && 993 insn_table[cur_insn].exit_qual != exit_qual) 994 pass = false; 995 if (insn_table[cur_insn].test_field & FIELD_INSN_INFO && 996 insn_table[cur_insn].insn_info != insn_info) 997 pass = false; 998 if (pass) 999 vmx_inc_test_stage(); 1000 } 1001 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1002 return VMX_TEST_RESUME; 1003 } 1004 1005 1006 /* Enables EPT and sets up the identity map. */ 1007 static int setup_ept(bool enable_ad) 1008 { 1009 unsigned long end_of_memory; 1010 u32 ctrl_cpu[2]; 1011 1012 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1013 !(ctrl_cpu_rev[1].clr & CPU_EPT)) { 1014 printf("\tEPT is not supported"); 1015 return 1; 1016 } 1017 1018 1019 if (!(ept_vpid.val & EPT_CAP_UC) && 1020 !(ept_vpid.val & EPT_CAP_WB)) { 1021 printf("\tEPT paging-structure memory type " 1022 "UC&WB are not supported\n"); 1023 return 1; 1024 } 1025 if (ept_vpid.val & EPT_CAP_UC) 1026 eptp = EPT_MEM_TYPE_UC; 1027 else 1028 eptp = EPT_MEM_TYPE_WB; 1029 if (!(ept_vpid.val & EPT_CAP_PWL4)) { 1030 printf("\tPWL4 is not supported\n"); 1031 return 1; 1032 } 1033 ctrl_cpu[0] = vmcs_read(CPU_EXEC_CTRL0); 1034 ctrl_cpu[1] = vmcs_read(CPU_EXEC_CTRL1); 1035 ctrl_cpu[0] = (ctrl_cpu[0] | CPU_SECONDARY) 1036 & ctrl_cpu_rev[0].clr; 1037 ctrl_cpu[1] = (ctrl_cpu[1] | CPU_EPT) 1038 & ctrl_cpu_rev[1].clr; 1039 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu[0]); 1040 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu[1]); 1041 eptp |= (3 << EPTP_PG_WALK_LEN_SHIFT); 1042 pml4 = alloc_page(); 1043 memset(pml4, 0, PAGE_SIZE); 1044 eptp |= virt_to_phys(pml4); 1045 if (enable_ad) 1046 eptp |= EPTP_AD_FLAG; 1047 vmcs_write(EPTP, eptp); 1048 end_of_memory = fwcfg_get_u64(FW_CFG_RAM_SIZE); 1049 if (end_of_memory < (1ul << 32)) 1050 end_of_memory = (1ul << 32); 1051 /* Cannot use large EPT pages if we need to track EPT 1052 * accessed/dirty bits at 4K granularity. 1053 */ 1054 setup_ept_range(pml4, 0, end_of_memory, 0, 1055 !enable_ad && ept_2m_supported(), 1056 EPT_WA | EPT_RA | EPT_EA); 1057 return 0; 1058 } 1059 1060 static void ept_enable_ad_bits(void) 1061 { 1062 eptp |= EPTP_AD_FLAG; 1063 vmcs_write(EPTP, eptp); 1064 } 1065 1066 static void ept_disable_ad_bits(void) 1067 { 1068 eptp &= ~EPTP_AD_FLAG; 1069 vmcs_write(EPTP, eptp); 1070 } 1071 1072 static void ept_enable_ad_bits_or_skip_test(void) 1073 { 1074 if (!ept_ad_bits_supported()) 1075 test_skip("EPT AD bits not supported."); 1076 ept_enable_ad_bits(); 1077 } 1078 1079 static int apic_version; 1080 1081 static int ept_init_common(bool have_ad) 1082 { 1083 int ret; 1084 struct pci_dev pcidev; 1085 1086 if (setup_ept(have_ad)) 1087 return VMX_TEST_EXIT; 1088 data_page1 = alloc_page(); 1089 data_page2 = alloc_page(); 1090 memset(data_page1, 0x0, PAGE_SIZE); 1091 memset(data_page2, 0x0, PAGE_SIZE); 1092 *((u32 *)data_page1) = MAGIC_VAL_1; 1093 *((u32 *)data_page2) = MAGIC_VAL_2; 1094 install_ept(pml4, (unsigned long)data_page1, (unsigned long)data_page2, 1095 EPT_RA | EPT_WA | EPT_EA); 1096 1097 apic_version = apic_read(APIC_LVR); 1098 1099 ret = pci_find_dev(PCI_VENDOR_ID_REDHAT, PCI_DEVICE_ID_REDHAT_TEST); 1100 if (ret != PCIDEVADDR_INVALID) { 1101 pci_dev_init(&pcidev, ret); 1102 pci_physaddr = pcidev.resource[PCI_TESTDEV_BAR_MEM]; 1103 } 1104 1105 return VMX_TEST_START; 1106 } 1107 1108 static int ept_init(struct vmcs *vmcs) 1109 { 1110 return ept_init_common(false); 1111 } 1112 1113 static void ept_common(void) 1114 { 1115 vmx_set_test_stage(0); 1116 if (*((u32 *)data_page2) != MAGIC_VAL_1 || 1117 *((u32 *)data_page1) != MAGIC_VAL_1) 1118 report("EPT basic framework - read", 0); 1119 else { 1120 *((u32 *)data_page2) = MAGIC_VAL_3; 1121 vmcall(); 1122 if (vmx_get_test_stage() == 1) { 1123 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1124 *((u32 *)data_page2) == MAGIC_VAL_2) 1125 report("EPT basic framework", 1); 1126 else 1127 report("EPT basic framework - remap", 1); 1128 } 1129 } 1130 // Test EPT Misconfigurations 1131 vmx_set_test_stage(1); 1132 vmcall(); 1133 *((u32 *)data_page1) = MAGIC_VAL_1; 1134 if (vmx_get_test_stage() != 2) { 1135 report("EPT misconfigurations", 0); 1136 goto t1; 1137 } 1138 vmx_set_test_stage(2); 1139 vmcall(); 1140 *((u32 *)data_page1) = MAGIC_VAL_1; 1141 report("EPT misconfigurations", vmx_get_test_stage() == 3); 1142 t1: 1143 // Test EPT violation 1144 vmx_set_test_stage(3); 1145 vmcall(); 1146 *((u32 *)data_page1) = MAGIC_VAL_1; 1147 report("EPT violation - page permission", vmx_get_test_stage() == 4); 1148 // Violation caused by EPT paging structure 1149 vmx_set_test_stage(4); 1150 vmcall(); 1151 *((u32 *)data_page1) = MAGIC_VAL_2; 1152 report("EPT violation - paging structure", vmx_get_test_stage() == 5); 1153 1154 // MMIO Read/Write 1155 vmx_set_test_stage(5); 1156 vmcall(); 1157 1158 *(u32 volatile *)pci_physaddr; 1159 report("MMIO EPT violation - read", vmx_get_test_stage() == 6); 1160 1161 *(u32 volatile *)pci_physaddr = MAGIC_VAL_1; 1162 report("MMIO EPT violation - write", vmx_get_test_stage() == 7); 1163 } 1164 1165 static void ept_main(void) 1166 { 1167 ept_common(); 1168 1169 // Test EPT access to L1 MMIO 1170 vmx_set_test_stage(7); 1171 report("EPT - MMIO access", *((u32 *)0xfee00030UL) == apic_version); 1172 1173 // Test invalid operand for INVEPT 1174 vmcall(); 1175 report("EPT - unsupported INVEPT", vmx_get_test_stage() == 8); 1176 } 1177 1178 static bool invept_test(int type, u64 eptp) 1179 { 1180 bool ret, supported; 1181 1182 supported = ept_vpid.val & (EPT_CAP_INVEPT_SINGLE >> INVEPT_SINGLE << type); 1183 ret = invept(type, eptp); 1184 1185 if (ret == !supported) 1186 return false; 1187 1188 if (!supported) 1189 printf("WARNING: unsupported invept passed!\n"); 1190 else 1191 printf("WARNING: invept failed!\n"); 1192 1193 return true; 1194 } 1195 1196 static int pml_exit_handler(void) 1197 { 1198 u16 index, count; 1199 ulong reason = vmcs_read(EXI_REASON) & 0xff; 1200 u64 *pmlbuf = pml_log; 1201 u64 guest_rip = vmcs_read(GUEST_RIP);; 1202 u64 guest_cr3 = vmcs_read(GUEST_CR3); 1203 u32 insn_len = vmcs_read(EXI_INST_LEN); 1204 1205 switch (reason) { 1206 case VMX_VMCALL: 1207 switch (vmx_get_test_stage()) { 1208 case 0: 1209 index = vmcs_read(GUEST_PML_INDEX); 1210 for (count = index + 1; count < PML_INDEX; count++) { 1211 if (pmlbuf[count] == (u64)data_page2) { 1212 vmx_inc_test_stage(); 1213 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1214 break; 1215 } 1216 } 1217 break; 1218 case 1: 1219 index = vmcs_read(GUEST_PML_INDEX); 1220 /* Keep clearing the dirty bit till a overflow */ 1221 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1222 break; 1223 default: 1224 report("unexpected stage, %d.", false, 1225 vmx_get_test_stage()); 1226 print_vmexit_info(); 1227 return VMX_TEST_VMEXIT; 1228 } 1229 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1230 return VMX_TEST_RESUME; 1231 case VMX_PML_FULL: 1232 vmx_inc_test_stage(); 1233 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1234 return VMX_TEST_RESUME; 1235 default: 1236 report("Unknown exit reason, %ld", false, reason); 1237 print_vmexit_info(); 1238 } 1239 return VMX_TEST_VMEXIT; 1240 } 1241 1242 static int ept_exit_handler_common(bool have_ad) 1243 { 1244 u64 guest_rip; 1245 u64 guest_cr3; 1246 ulong reason; 1247 u32 insn_len; 1248 u32 exit_qual; 1249 static unsigned long data_page1_pte, data_page1_pte_pte, memaddr_pte; 1250 1251 guest_rip = vmcs_read(GUEST_RIP); 1252 guest_cr3 = vmcs_read(GUEST_CR3); 1253 reason = vmcs_read(EXI_REASON) & 0xff; 1254 insn_len = vmcs_read(EXI_INST_LEN); 1255 exit_qual = vmcs_read(EXI_QUALIFICATION); 1256 switch (reason) { 1257 case VMX_VMCALL: 1258 switch (vmx_get_test_stage()) { 1259 case 0: 1260 check_ept_ad(pml4, guest_cr3, 1261 (unsigned long)data_page1, 1262 have_ad ? EPT_ACCESS_FLAG : 0, 1263 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1264 check_ept_ad(pml4, guest_cr3, 1265 (unsigned long)data_page2, 1266 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0, 1267 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1268 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1269 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1270 if (have_ad) 1271 ept_sync(INVEPT_SINGLE, eptp);; 1272 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1273 *((u32 *)data_page2) == MAGIC_VAL_2) { 1274 vmx_inc_test_stage(); 1275 install_ept(pml4, (unsigned long)data_page2, 1276 (unsigned long)data_page2, 1277 EPT_RA | EPT_WA | EPT_EA); 1278 } else 1279 report("EPT basic framework - write", 0); 1280 break; 1281 case 1: 1282 install_ept(pml4, (unsigned long)data_page1, 1283 (unsigned long)data_page1, EPT_WA); 1284 ept_sync(INVEPT_SINGLE, eptp); 1285 break; 1286 case 2: 1287 install_ept(pml4, (unsigned long)data_page1, 1288 (unsigned long)data_page1, 1289 EPT_RA | EPT_WA | EPT_EA | 1290 (2 << EPT_MEM_TYPE_SHIFT)); 1291 ept_sync(INVEPT_SINGLE, eptp); 1292 break; 1293 case 3: 1294 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1295 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)data_page1, 1296 1, &data_page1_pte)); 1297 set_ept_pte(pml4, (unsigned long)data_page1, 1298 1, data_page1_pte & ~EPT_PRESENT); 1299 ept_sync(INVEPT_SINGLE, eptp); 1300 break; 1301 case 4: 1302 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)data_page1, 1303 2, &data_page1_pte)); 1304 data_page1_pte &= PAGE_MASK; 1305 TEST_ASSERT(get_ept_pte(pml4, data_page1_pte, 1306 2, &data_page1_pte_pte)); 1307 set_ept_pte(pml4, data_page1_pte, 2, 1308 data_page1_pte_pte & ~EPT_PRESENT); 1309 ept_sync(INVEPT_SINGLE, eptp); 1310 break; 1311 case 5: 1312 install_ept(pml4, (unsigned long)pci_physaddr, 1313 (unsigned long)pci_physaddr, 0); 1314 ept_sync(INVEPT_SINGLE, eptp); 1315 break; 1316 case 7: 1317 if (!invept_test(0, eptp)) 1318 vmx_inc_test_stage(); 1319 break; 1320 // Should not reach here 1321 default: 1322 report("ERROR - unexpected stage, %d.", false, 1323 vmx_get_test_stage()); 1324 print_vmexit_info(); 1325 return VMX_TEST_VMEXIT; 1326 } 1327 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1328 return VMX_TEST_RESUME; 1329 case VMX_EPT_MISCONFIG: 1330 switch (vmx_get_test_stage()) { 1331 case 1: 1332 case 2: 1333 vmx_inc_test_stage(); 1334 install_ept(pml4, (unsigned long)data_page1, 1335 (unsigned long)data_page1, 1336 EPT_RA | EPT_WA | EPT_EA); 1337 ept_sync(INVEPT_SINGLE, eptp); 1338 break; 1339 // Should not reach here 1340 default: 1341 report("ERROR - unexpected stage, %d.", false, 1342 vmx_get_test_stage()); 1343 print_vmexit_info(); 1344 return VMX_TEST_VMEXIT; 1345 } 1346 return VMX_TEST_RESUME; 1347 case VMX_EPT_VIOLATION: 1348 switch(vmx_get_test_stage()) { 1349 case 3: 1350 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1351 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1352 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1353 if (exit_qual == (EPT_VLT_WR | EPT_VLT_LADDR_VLD | 1354 EPT_VLT_PADDR)) 1355 vmx_inc_test_stage(); 1356 set_ept_pte(pml4, (unsigned long)data_page1, 1357 1, data_page1_pte | (EPT_PRESENT)); 1358 ept_sync(INVEPT_SINGLE, eptp); 1359 break; 1360 case 4: 1361 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1362 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1363 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1364 if (exit_qual == (EPT_VLT_RD | 1365 (have_ad ? EPT_VLT_WR : 0) | 1366 EPT_VLT_LADDR_VLD)) 1367 vmx_inc_test_stage(); 1368 set_ept_pte(pml4, data_page1_pte, 2, 1369 data_page1_pte_pte | (EPT_PRESENT)); 1370 ept_sync(INVEPT_SINGLE, eptp); 1371 break; 1372 case 5: 1373 if (exit_qual & EPT_VLT_RD) 1374 vmx_inc_test_stage(); 1375 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1376 1, &memaddr_pte)); 1377 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA); 1378 ept_sync(INVEPT_SINGLE, eptp); 1379 break; 1380 case 6: 1381 if (exit_qual & EPT_VLT_WR) 1382 vmx_inc_test_stage(); 1383 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1384 1, &memaddr_pte)); 1385 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA | EPT_WA); 1386 ept_sync(INVEPT_SINGLE, eptp); 1387 break; 1388 default: 1389 // Should not reach here 1390 report("ERROR : unexpected stage, %d", false, 1391 vmx_get_test_stage()); 1392 print_vmexit_info(); 1393 return VMX_TEST_VMEXIT; 1394 } 1395 return VMX_TEST_RESUME; 1396 default: 1397 report("Unknown exit reason, %ld", false, reason); 1398 print_vmexit_info(); 1399 } 1400 return VMX_TEST_VMEXIT; 1401 } 1402 1403 static int ept_exit_handler(void) 1404 { 1405 return ept_exit_handler_common(false); 1406 } 1407 1408 static int eptad_init(struct vmcs *vmcs) 1409 { 1410 int r = ept_init_common(true); 1411 1412 if (r == VMX_TEST_EXIT) 1413 return r; 1414 1415 if ((rdmsr(MSR_IA32_VMX_EPT_VPID_CAP) & EPT_CAP_AD_FLAG) == 0) { 1416 printf("\tEPT A/D bits are not supported"); 1417 return VMX_TEST_EXIT; 1418 } 1419 1420 return r; 1421 } 1422 1423 static int pml_init(struct vmcs *vmcs) 1424 { 1425 u32 ctrl_cpu; 1426 int r = eptad_init(vmcs); 1427 1428 if (r == VMX_TEST_EXIT) 1429 return r; 1430 1431 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1432 !(ctrl_cpu_rev[1].clr & CPU_PML)) { 1433 printf("\tPML is not supported"); 1434 return VMX_TEST_EXIT; 1435 } 1436 1437 pml_log = alloc_page(); 1438 memset(pml_log, 0x0, PAGE_SIZE); 1439 vmcs_write(PMLADDR, (u64)pml_log); 1440 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1441 1442 ctrl_cpu = vmcs_read(CPU_EXEC_CTRL1) | CPU_PML; 1443 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu); 1444 1445 return VMX_TEST_START; 1446 } 1447 1448 static void pml_main(void) 1449 { 1450 int count = 0; 1451 1452 vmx_set_test_stage(0); 1453 *((u32 *)data_page2) = 0x1; 1454 vmcall(); 1455 report("PML - Dirty GPA Logging", vmx_get_test_stage() == 1); 1456 1457 while (vmx_get_test_stage() == 1) { 1458 vmcall(); 1459 *((u32 *)data_page2) = 0x1; 1460 if (count++ > PML_INDEX) 1461 break; 1462 } 1463 report("PML Full Event", vmx_get_test_stage() == 2); 1464 } 1465 1466 static void eptad_main(void) 1467 { 1468 ept_common(); 1469 } 1470 1471 static int eptad_exit_handler(void) 1472 { 1473 return ept_exit_handler_common(true); 1474 } 1475 1476 static bool invvpid_test(int type, u16 vpid) 1477 { 1478 bool ret, supported; 1479 1480 supported = ept_vpid.val & 1481 (VPID_CAP_INVVPID_ADDR >> INVVPID_ADDR << type); 1482 ret = invvpid(type, vpid, 0); 1483 1484 if (ret == !supported) 1485 return false; 1486 1487 if (!supported) 1488 printf("WARNING: unsupported invvpid passed!\n"); 1489 else 1490 printf("WARNING: invvpid failed!\n"); 1491 1492 return true; 1493 } 1494 1495 static int vpid_init(struct vmcs *vmcs) 1496 { 1497 u32 ctrl_cpu1; 1498 1499 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1500 !(ctrl_cpu_rev[1].clr & CPU_VPID)) { 1501 printf("\tVPID is not supported"); 1502 return VMX_TEST_EXIT; 1503 } 1504 1505 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 1506 ctrl_cpu1 |= CPU_VPID; 1507 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 1508 return VMX_TEST_START; 1509 } 1510 1511 static void vpid_main(void) 1512 { 1513 vmx_set_test_stage(0); 1514 vmcall(); 1515 report("INVVPID SINGLE ADDRESS", vmx_get_test_stage() == 1); 1516 vmx_set_test_stage(2); 1517 vmcall(); 1518 report("INVVPID SINGLE", vmx_get_test_stage() == 3); 1519 vmx_set_test_stage(4); 1520 vmcall(); 1521 report("INVVPID ALL", vmx_get_test_stage() == 5); 1522 } 1523 1524 static int vpid_exit_handler(void) 1525 { 1526 u64 guest_rip; 1527 ulong reason; 1528 u32 insn_len; 1529 1530 guest_rip = vmcs_read(GUEST_RIP); 1531 reason = vmcs_read(EXI_REASON) & 0xff; 1532 insn_len = vmcs_read(EXI_INST_LEN); 1533 1534 switch (reason) { 1535 case VMX_VMCALL: 1536 switch(vmx_get_test_stage()) { 1537 case 0: 1538 if (!invvpid_test(INVVPID_ADDR, 1)) 1539 vmx_inc_test_stage(); 1540 break; 1541 case 2: 1542 if (!invvpid_test(INVVPID_CONTEXT_GLOBAL, 1)) 1543 vmx_inc_test_stage(); 1544 break; 1545 case 4: 1546 if (!invvpid_test(INVVPID_ALL, 1)) 1547 vmx_inc_test_stage(); 1548 break; 1549 default: 1550 report("ERROR: unexpected stage, %d", false, 1551 vmx_get_test_stage()); 1552 print_vmexit_info(); 1553 return VMX_TEST_VMEXIT; 1554 } 1555 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1556 return VMX_TEST_RESUME; 1557 default: 1558 report("Unknown exit reason, %ld", false, reason); 1559 print_vmexit_info(); 1560 } 1561 return VMX_TEST_VMEXIT; 1562 } 1563 1564 #define TIMER_VECTOR 222 1565 1566 static volatile bool timer_fired; 1567 1568 static void timer_isr(isr_regs_t *regs) 1569 { 1570 timer_fired = true; 1571 apic_write(APIC_EOI, 0); 1572 } 1573 1574 static int interrupt_init(struct vmcs *vmcs) 1575 { 1576 msr_bmp_init(); 1577 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1578 handle_irq(TIMER_VECTOR, timer_isr); 1579 return VMX_TEST_START; 1580 } 1581 1582 static void interrupt_main(void) 1583 { 1584 long long start, loops; 1585 1586 vmx_set_test_stage(0); 1587 1588 apic_write(APIC_LVTT, TIMER_VECTOR); 1589 irq_enable(); 1590 1591 apic_write(APIC_TMICT, 1); 1592 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1593 asm volatile ("nop"); 1594 report("direct interrupt while running guest", timer_fired); 1595 1596 apic_write(APIC_TMICT, 0); 1597 irq_disable(); 1598 vmcall(); 1599 timer_fired = false; 1600 apic_write(APIC_TMICT, 1); 1601 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1602 asm volatile ("nop"); 1603 report("intercepted interrupt while running guest", timer_fired); 1604 1605 irq_enable(); 1606 apic_write(APIC_TMICT, 0); 1607 irq_disable(); 1608 vmcall(); 1609 timer_fired = false; 1610 start = rdtsc(); 1611 apic_write(APIC_TMICT, 1000000); 1612 1613 asm volatile ("sti; hlt"); 1614 1615 report("direct interrupt + hlt", 1616 rdtsc() - start > 1000000 && timer_fired); 1617 1618 apic_write(APIC_TMICT, 0); 1619 irq_disable(); 1620 vmcall(); 1621 timer_fired = false; 1622 start = rdtsc(); 1623 apic_write(APIC_TMICT, 1000000); 1624 1625 asm volatile ("sti; hlt"); 1626 1627 report("intercepted interrupt + hlt", 1628 rdtsc() - start > 10000 && timer_fired); 1629 1630 apic_write(APIC_TMICT, 0); 1631 irq_disable(); 1632 vmcall(); 1633 timer_fired = false; 1634 start = rdtsc(); 1635 apic_write(APIC_TMICT, 1000000); 1636 1637 irq_enable(); 1638 asm volatile ("nop"); 1639 vmcall(); 1640 1641 report("direct interrupt + activity state hlt", 1642 rdtsc() - start > 10000 && timer_fired); 1643 1644 apic_write(APIC_TMICT, 0); 1645 irq_disable(); 1646 vmcall(); 1647 timer_fired = false; 1648 start = rdtsc(); 1649 apic_write(APIC_TMICT, 1000000); 1650 1651 irq_enable(); 1652 asm volatile ("nop"); 1653 vmcall(); 1654 1655 report("intercepted interrupt + activity state hlt", 1656 rdtsc() - start > 10000 && timer_fired); 1657 1658 apic_write(APIC_TMICT, 0); 1659 irq_disable(); 1660 vmx_set_test_stage(7); 1661 vmcall(); 1662 timer_fired = false; 1663 apic_write(APIC_TMICT, 1); 1664 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1665 asm volatile ("nop"); 1666 report("running a guest with interrupt acknowledgement set", timer_fired); 1667 1668 apic_write(APIC_TMICT, 0); 1669 irq_enable(); 1670 timer_fired = false; 1671 vmcall(); 1672 report("Inject an event to a halted guest", timer_fired); 1673 } 1674 1675 static int interrupt_exit_handler(void) 1676 { 1677 u64 guest_rip = vmcs_read(GUEST_RIP); 1678 ulong reason = vmcs_read(EXI_REASON) & 0xff; 1679 u32 insn_len = vmcs_read(EXI_INST_LEN); 1680 1681 switch (reason) { 1682 case VMX_VMCALL: 1683 switch (vmx_get_test_stage()) { 1684 case 0: 1685 case 2: 1686 case 5: 1687 vmcs_write(PIN_CONTROLS, 1688 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1689 break; 1690 case 7: 1691 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_INTA); 1692 vmcs_write(PIN_CONTROLS, 1693 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1694 break; 1695 case 1: 1696 case 3: 1697 vmcs_write(PIN_CONTROLS, 1698 vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1699 break; 1700 case 4: 1701 case 6: 1702 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1703 break; 1704 1705 case 8: 1706 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1707 vmcs_write(ENT_INTR_INFO, 1708 TIMER_VECTOR | 1709 (VMX_INTR_TYPE_EXT_INTR << INTR_INFO_INTR_TYPE_SHIFT) | 1710 INTR_INFO_VALID_MASK); 1711 break; 1712 } 1713 vmx_inc_test_stage(); 1714 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1715 return VMX_TEST_RESUME; 1716 case VMX_EXTINT: 1717 if (vmcs_read(EXI_CONTROLS) & EXI_INTA) { 1718 int vector = vmcs_read(EXI_INTR_INFO) & 0xff; 1719 handle_external_interrupt(vector); 1720 } else { 1721 irq_enable(); 1722 asm volatile ("nop"); 1723 irq_disable(); 1724 } 1725 if (vmx_get_test_stage() >= 2) 1726 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 1727 return VMX_TEST_RESUME; 1728 default: 1729 report("Unknown exit reason, %ld", false, reason); 1730 print_vmexit_info(); 1731 } 1732 1733 return VMX_TEST_VMEXIT; 1734 } 1735 1736 static int dbgctls_init(struct vmcs *vmcs) 1737 { 1738 u64 dr7 = 0x402; 1739 u64 zero = 0; 1740 1741 msr_bmp_init(); 1742 asm volatile( 1743 "mov %0,%%dr0\n\t" 1744 "mov %0,%%dr1\n\t" 1745 "mov %0,%%dr2\n\t" 1746 "mov %1,%%dr7\n\t" 1747 : : "r" (zero), "r" (dr7)); 1748 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1749 vmcs_write(GUEST_DR7, 0x404); 1750 vmcs_write(GUEST_DEBUGCTL, 0x2); 1751 1752 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 1753 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_SAVE_DBGCTLS); 1754 1755 return VMX_TEST_START; 1756 } 1757 1758 static void dbgctls_main(void) 1759 { 1760 u64 dr7, debugctl; 1761 1762 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1763 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1764 /* Commented out: KVM does not support DEBUGCTL so far */ 1765 (void)debugctl; 1766 report("Load debug controls", dr7 == 0x404 /* && debugctl == 0x2 */); 1767 1768 dr7 = 0x408; 1769 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1770 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1771 1772 vmx_set_test_stage(0); 1773 vmcall(); 1774 report("Save debug controls", vmx_get_test_stage() == 1); 1775 1776 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS || 1777 ctrl_exit_rev.set & EXI_SAVE_DBGCTLS) { 1778 printf("\tDebug controls are always loaded/saved\n"); 1779 return; 1780 } 1781 vmx_set_test_stage(2); 1782 vmcall(); 1783 1784 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1785 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1786 /* Commented out: KVM does not support DEBUGCTL so far */ 1787 (void)debugctl; 1788 report("Guest=host debug controls", dr7 == 0x402 /* && debugctl == 0x1 */); 1789 1790 dr7 = 0x408; 1791 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1792 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1793 1794 vmx_set_test_stage(3); 1795 vmcall(); 1796 report("Don't save debug controls", vmx_get_test_stage() == 4); 1797 } 1798 1799 static int dbgctls_exit_handler(void) 1800 { 1801 unsigned int reason = vmcs_read(EXI_REASON) & 0xff; 1802 u32 insn_len = vmcs_read(EXI_INST_LEN); 1803 u64 guest_rip = vmcs_read(GUEST_RIP); 1804 u64 dr7, debugctl; 1805 1806 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1807 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1808 1809 switch (reason) { 1810 case VMX_VMCALL: 1811 switch (vmx_get_test_stage()) { 1812 case 0: 1813 if (dr7 == 0x400 && debugctl == 0 && 1814 vmcs_read(GUEST_DR7) == 0x408 /* && 1815 Commented out: KVM does not support DEBUGCTL so far 1816 vmcs_read(GUEST_DEBUGCTL) == 0x3 */) 1817 vmx_inc_test_stage(); 1818 break; 1819 case 2: 1820 dr7 = 0x402; 1821 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1822 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1823 vmcs_write(GUEST_DR7, 0x404); 1824 vmcs_write(GUEST_DEBUGCTL, 0x2); 1825 1826 vmcs_write(ENT_CONTROLS, 1827 vmcs_read(ENT_CONTROLS) & ~ENT_LOAD_DBGCTLS); 1828 vmcs_write(EXI_CONTROLS, 1829 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_DBGCTLS); 1830 break; 1831 case 3: 1832 if (dr7 == 0x400 && debugctl == 0 && 1833 vmcs_read(GUEST_DR7) == 0x404 /* && 1834 Commented out: KVM does not support DEBUGCTL so far 1835 vmcs_read(GUEST_DEBUGCTL) == 0x2 */) 1836 vmx_inc_test_stage(); 1837 break; 1838 } 1839 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1840 return VMX_TEST_RESUME; 1841 default: 1842 report("Unknown exit reason, %d", false, reason); 1843 print_vmexit_info(); 1844 } 1845 return VMX_TEST_VMEXIT; 1846 } 1847 1848 struct vmx_msr_entry { 1849 u32 index; 1850 u32 reserved; 1851 u64 value; 1852 } __attribute__((packed)); 1853 1854 #define MSR_MAGIC 0x31415926 1855 struct vmx_msr_entry *exit_msr_store, *entry_msr_load, *exit_msr_load; 1856 1857 static int msr_switch_init(struct vmcs *vmcs) 1858 { 1859 msr_bmp_init(); 1860 exit_msr_store = alloc_page(); 1861 exit_msr_load = alloc_page(); 1862 entry_msr_load = alloc_page(); 1863 memset(exit_msr_store, 0, PAGE_SIZE); 1864 memset(exit_msr_load, 0, PAGE_SIZE); 1865 memset(entry_msr_load, 0, PAGE_SIZE); 1866 entry_msr_load[0].index = MSR_KERNEL_GS_BASE; 1867 entry_msr_load[0].value = MSR_MAGIC; 1868 1869 vmx_set_test_stage(1); 1870 vmcs_write(ENT_MSR_LD_CNT, 1); 1871 vmcs_write(ENTER_MSR_LD_ADDR, (u64)entry_msr_load); 1872 vmcs_write(EXI_MSR_ST_CNT, 1); 1873 vmcs_write(EXIT_MSR_ST_ADDR, (u64)exit_msr_store); 1874 vmcs_write(EXI_MSR_LD_CNT, 1); 1875 vmcs_write(EXIT_MSR_LD_ADDR, (u64)exit_msr_load); 1876 return VMX_TEST_START; 1877 } 1878 1879 static void msr_switch_main(void) 1880 { 1881 if (vmx_get_test_stage() == 1) { 1882 report("VM entry MSR load", 1883 rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC); 1884 vmx_set_test_stage(2); 1885 wrmsr(MSR_KERNEL_GS_BASE, MSR_MAGIC + 1); 1886 exit_msr_store[0].index = MSR_KERNEL_GS_BASE; 1887 exit_msr_load[0].index = MSR_KERNEL_GS_BASE; 1888 exit_msr_load[0].value = MSR_MAGIC + 2; 1889 } 1890 vmcall(); 1891 } 1892 1893 static int msr_switch_exit_handler(void) 1894 { 1895 ulong reason; 1896 1897 reason = vmcs_read(EXI_REASON); 1898 if (reason == VMX_VMCALL && vmx_get_test_stage() == 2) { 1899 report("VM exit MSR store", 1900 exit_msr_store[0].value == MSR_MAGIC + 1); 1901 report("VM exit MSR load", 1902 rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC + 2); 1903 vmx_set_test_stage(3); 1904 entry_msr_load[0].index = MSR_FS_BASE; 1905 return VMX_TEST_RESUME; 1906 } 1907 printf("ERROR %s: unexpected stage=%u or reason=%lu\n", 1908 __func__, vmx_get_test_stage(), reason); 1909 return VMX_TEST_EXIT; 1910 } 1911 1912 static int msr_switch_entry_failure(struct vmentry_failure *failure) 1913 { 1914 ulong reason; 1915 1916 if (failure->early) { 1917 printf("ERROR %s: early exit\n", __func__); 1918 return VMX_TEST_EXIT; 1919 } 1920 1921 reason = vmcs_read(EXI_REASON); 1922 if (reason == (VMX_ENTRY_FAILURE | VMX_FAIL_MSR) && 1923 vmx_get_test_stage() == 3) { 1924 report("VM entry MSR load: try to load FS_BASE", 1925 vmcs_read(EXI_QUALIFICATION) == 1); 1926 return VMX_TEST_VMEXIT; 1927 } 1928 printf("ERROR %s: unexpected stage=%u or reason=%lu\n", 1929 __func__, vmx_get_test_stage(), reason); 1930 return VMX_TEST_EXIT; 1931 } 1932 1933 static int vmmcall_init(struct vmcs *vmcs) 1934 { 1935 vmcs_write(EXC_BITMAP, 1 << UD_VECTOR); 1936 return VMX_TEST_START; 1937 } 1938 1939 static void vmmcall_main(void) 1940 { 1941 asm volatile( 1942 "mov $0xABCD, %%rax\n\t" 1943 "vmmcall\n\t" 1944 ::: "rax"); 1945 1946 report("VMMCALL", 0); 1947 } 1948 1949 static int vmmcall_exit_handler(void) 1950 { 1951 ulong reason; 1952 1953 reason = vmcs_read(EXI_REASON); 1954 switch (reason) { 1955 case VMX_VMCALL: 1956 printf("here\n"); 1957 report("VMMCALL triggers #UD", 0); 1958 break; 1959 case VMX_EXC_NMI: 1960 report("VMMCALL triggers #UD", 1961 (vmcs_read(EXI_INTR_INFO) & 0xff) == UD_VECTOR); 1962 break; 1963 default: 1964 report("Unknown exit reason, %ld", false, reason); 1965 print_vmexit_info(); 1966 } 1967 1968 return VMX_TEST_VMEXIT; 1969 } 1970 1971 static int disable_rdtscp_init(struct vmcs *vmcs) 1972 { 1973 u32 ctrl_cpu1; 1974 1975 if (ctrl_cpu_rev[0].clr & CPU_SECONDARY) { 1976 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 1977 ctrl_cpu1 &= ~CPU_RDTSCP; 1978 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 1979 } 1980 1981 return VMX_TEST_START; 1982 } 1983 1984 static void disable_rdtscp_ud_handler(struct ex_regs *regs) 1985 { 1986 switch (vmx_get_test_stage()) { 1987 case 0: 1988 report("RDTSCP triggers #UD", true); 1989 vmx_inc_test_stage(); 1990 regs->rip += 3; 1991 break; 1992 case 2: 1993 report("RDPID triggers #UD", true); 1994 vmx_inc_test_stage(); 1995 regs->rip += 4; 1996 break; 1997 } 1998 return; 1999 2000 } 2001 2002 static void disable_rdtscp_main(void) 2003 { 2004 /* Test that #UD is properly injected in L2. */ 2005 handle_exception(UD_VECTOR, disable_rdtscp_ud_handler); 2006 2007 vmx_set_test_stage(0); 2008 asm volatile("rdtscp" : : : "eax", "ecx", "edx"); 2009 vmcall(); 2010 asm volatile(".byte 0xf3, 0x0f, 0xc7, 0xf8" : : : "eax"); 2011 2012 handle_exception(UD_VECTOR, 0); 2013 vmcall(); 2014 } 2015 2016 static int disable_rdtscp_exit_handler(void) 2017 { 2018 unsigned int reason = vmcs_read(EXI_REASON) & 0xff; 2019 2020 switch (reason) { 2021 case VMX_VMCALL: 2022 switch (vmx_get_test_stage()) { 2023 case 0: 2024 report("RDTSCP triggers #UD", false); 2025 vmx_inc_test_stage(); 2026 /* fallthrough */ 2027 case 1: 2028 vmx_inc_test_stage(); 2029 vmcs_write(GUEST_RIP, vmcs_read(GUEST_RIP) + 3); 2030 return VMX_TEST_RESUME; 2031 case 2: 2032 report("RDPID triggers #UD", false); 2033 break; 2034 } 2035 break; 2036 2037 default: 2038 report("Unknown exit reason, %d", false, reason); 2039 print_vmexit_info(); 2040 } 2041 return VMX_TEST_VMEXIT; 2042 } 2043 2044 static int int3_init(struct vmcs *vmcs) 2045 { 2046 vmcs_write(EXC_BITMAP, ~0u); 2047 return VMX_TEST_START; 2048 } 2049 2050 static void int3_guest_main(void) 2051 { 2052 asm volatile ("int3"); 2053 } 2054 2055 static int int3_exit_handler(void) 2056 { 2057 u32 reason = vmcs_read(EXI_REASON); 2058 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2059 2060 report("L1 intercepts #BP", reason == VMX_EXC_NMI && 2061 (intr_info & INTR_INFO_VALID_MASK) && 2062 (intr_info & INTR_INFO_VECTOR_MASK) == BP_VECTOR && 2063 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2064 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION); 2065 2066 return VMX_TEST_VMEXIT; 2067 } 2068 2069 static int into_init(struct vmcs *vmcs) 2070 { 2071 vmcs_write(EXC_BITMAP, ~0u); 2072 return VMX_TEST_START; 2073 } 2074 2075 static void into_guest_main(void) 2076 { 2077 struct far_pointer32 fp = { 2078 .offset = (uintptr_t)&&into, 2079 .selector = KERNEL_CS32, 2080 }; 2081 register uintptr_t rsp asm("rsp"); 2082 2083 if (fp.offset != (uintptr_t)&&into) { 2084 printf("Code address too high.\n"); 2085 return; 2086 } 2087 if ((u32)rsp != rsp) { 2088 printf("Stack address too high.\n"); 2089 return; 2090 } 2091 2092 asm goto ("lcall *%0" : : "m" (fp) : "rax" : into); 2093 return; 2094 into: 2095 asm volatile (".code32;" 2096 "movl $0x7fffffff, %eax;" 2097 "addl %eax, %eax;" 2098 "into;" 2099 "lret;" 2100 ".code64"); 2101 __builtin_unreachable(); 2102 } 2103 2104 static int into_exit_handler(void) 2105 { 2106 u32 reason = vmcs_read(EXI_REASON); 2107 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2108 2109 report("L1 intercepts #OF", reason == VMX_EXC_NMI && 2110 (intr_info & INTR_INFO_VALID_MASK) && 2111 (intr_info & INTR_INFO_VECTOR_MASK) == OF_VECTOR && 2112 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2113 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION); 2114 2115 return VMX_TEST_VMEXIT; 2116 } 2117 2118 static void exit_monitor_from_l2_main(void) 2119 { 2120 printf("Calling exit(0) from l2...\n"); 2121 exit(0); 2122 } 2123 2124 static int exit_monitor_from_l2_handler(void) 2125 { 2126 report("The guest should have killed the VMM", false); 2127 return VMX_TEST_EXIT; 2128 } 2129 2130 static void assert_exit_reason(u64 expected) 2131 { 2132 u64 actual = vmcs_read(EXI_REASON); 2133 2134 TEST_ASSERT_EQ_MSG(expected, actual, "Expected %s, got %s.", 2135 exit_reason_description(expected), 2136 exit_reason_description(actual)); 2137 } 2138 2139 static void skip_exit_insn(void) 2140 { 2141 u64 guest_rip = vmcs_read(GUEST_RIP); 2142 u32 insn_len = vmcs_read(EXI_INST_LEN); 2143 vmcs_write(GUEST_RIP, guest_rip + insn_len); 2144 } 2145 2146 static void skip_exit_vmcall(void) 2147 { 2148 assert_exit_reason(VMX_VMCALL); 2149 skip_exit_insn(); 2150 } 2151 2152 static void v2_null_test_guest(void) 2153 { 2154 } 2155 2156 static void v2_null_test(void) 2157 { 2158 test_set_guest(v2_null_test_guest); 2159 enter_guest(); 2160 report(__func__, 1); 2161 } 2162 2163 static void v2_multiple_entries_test_guest(void) 2164 { 2165 vmx_set_test_stage(1); 2166 vmcall(); 2167 vmx_set_test_stage(2); 2168 } 2169 2170 static void v2_multiple_entries_test(void) 2171 { 2172 test_set_guest(v2_multiple_entries_test_guest); 2173 enter_guest(); 2174 TEST_ASSERT_EQ(vmx_get_test_stage(), 1); 2175 skip_exit_vmcall(); 2176 enter_guest(); 2177 TEST_ASSERT_EQ(vmx_get_test_stage(), 2); 2178 report(__func__, 1); 2179 } 2180 2181 static int fixture_test_data = 1; 2182 2183 static void fixture_test_teardown(void *data) 2184 { 2185 *((int *) data) = 1; 2186 } 2187 2188 static void fixture_test_guest(void) 2189 { 2190 fixture_test_data++; 2191 } 2192 2193 2194 static void fixture_test_setup(void) 2195 { 2196 TEST_ASSERT_EQ_MSG(1, fixture_test_data, 2197 "fixture_test_teardown didn't run?!"); 2198 fixture_test_data = 2; 2199 test_add_teardown(fixture_test_teardown, &fixture_test_data); 2200 test_set_guest(fixture_test_guest); 2201 } 2202 2203 static void fixture_test_case1(void) 2204 { 2205 fixture_test_setup(); 2206 TEST_ASSERT_EQ(2, fixture_test_data); 2207 enter_guest(); 2208 TEST_ASSERT_EQ(3, fixture_test_data); 2209 report(__func__, 1); 2210 } 2211 2212 static void fixture_test_case2(void) 2213 { 2214 fixture_test_setup(); 2215 TEST_ASSERT_EQ(2, fixture_test_data); 2216 enter_guest(); 2217 TEST_ASSERT_EQ(3, fixture_test_data); 2218 report(__func__, 1); 2219 } 2220 2221 enum ept_access_op { 2222 OP_READ, 2223 OP_WRITE, 2224 OP_EXEC, 2225 OP_FLUSH_TLB, 2226 OP_EXIT, 2227 }; 2228 2229 static struct ept_access_test_data { 2230 unsigned long gpa; 2231 unsigned long *gva; 2232 unsigned long hpa; 2233 unsigned long *hva; 2234 enum ept_access_op op; 2235 } ept_access_test_data; 2236 2237 extern unsigned char ret42_start; 2238 extern unsigned char ret42_end; 2239 2240 /* Returns 42. */ 2241 asm( 2242 ".align 64\n" 2243 "ret42_start:\n" 2244 "mov $42, %eax\n" 2245 "ret\n" 2246 "ret42_end:\n" 2247 ); 2248 2249 static void 2250 diagnose_ept_violation_qual(u64 expected, u64 actual) 2251 { 2252 2253 #define DIAGNOSE(flag) \ 2254 do { \ 2255 if ((expected & flag) != (actual & flag)) \ 2256 printf(#flag " %sexpected\n", \ 2257 (expected & flag) ? "" : "un"); \ 2258 } while (0) 2259 2260 DIAGNOSE(EPT_VLT_RD); 2261 DIAGNOSE(EPT_VLT_WR); 2262 DIAGNOSE(EPT_VLT_FETCH); 2263 DIAGNOSE(EPT_VLT_PERM_RD); 2264 DIAGNOSE(EPT_VLT_PERM_WR); 2265 DIAGNOSE(EPT_VLT_PERM_EX); 2266 DIAGNOSE(EPT_VLT_LADDR_VLD); 2267 DIAGNOSE(EPT_VLT_PADDR); 2268 2269 #undef DIAGNOSE 2270 } 2271 2272 static void do_ept_access_op(enum ept_access_op op) 2273 { 2274 ept_access_test_data.op = op; 2275 enter_guest(); 2276 } 2277 2278 /* 2279 * Force the guest to flush its TLB (i.e., flush gva -> gpa mappings). Only 2280 * needed by tests that modify guest PTEs. 2281 */ 2282 static void ept_access_test_guest_flush_tlb(void) 2283 { 2284 do_ept_access_op(OP_FLUSH_TLB); 2285 skip_exit_vmcall(); 2286 } 2287 2288 /* 2289 * Modifies the EPT entry at @level in the mapping of @gpa. First clears the 2290 * bits in @clear then sets the bits in @set. @mkhuge transforms the entry into 2291 * a huge page. 2292 */ 2293 static unsigned long ept_twiddle(unsigned long gpa, bool mkhuge, int level, 2294 unsigned long clear, unsigned long set) 2295 { 2296 struct ept_access_test_data *data = &ept_access_test_data; 2297 unsigned long orig_pte; 2298 unsigned long pte; 2299 2300 /* Screw with the mapping at the requested level. */ 2301 TEST_ASSERT(get_ept_pte(pml4, gpa, level, &orig_pte)); 2302 pte = orig_pte; 2303 if (mkhuge) 2304 pte = (orig_pte & ~EPT_ADDR_MASK) | data->hpa | EPT_LARGE_PAGE; 2305 else 2306 pte = orig_pte; 2307 pte = (pte & ~clear) | set; 2308 set_ept_pte(pml4, gpa, level, pte); 2309 ept_sync(INVEPT_SINGLE, eptp); 2310 2311 return orig_pte; 2312 } 2313 2314 static void ept_untwiddle(unsigned long gpa, int level, unsigned long orig_pte) 2315 { 2316 set_ept_pte(pml4, gpa, level, orig_pte); 2317 } 2318 2319 static void do_ept_violation(bool leaf, enum ept_access_op op, 2320 u64 expected_qual, u64 expected_paddr) 2321 { 2322 u64 qual; 2323 2324 /* Try the access and observe the violation. */ 2325 do_ept_access_op(op); 2326 2327 assert_exit_reason(VMX_EPT_VIOLATION); 2328 2329 qual = vmcs_read(EXI_QUALIFICATION); 2330 2331 diagnose_ept_violation_qual(expected_qual, qual); 2332 TEST_EXPECT_EQ(expected_qual, qual); 2333 2334 #if 0 2335 /* Disable for now otherwise every test will fail */ 2336 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2337 (unsigned long) ( 2338 op == OP_EXEC ? data->gva + 1 : data->gva)); 2339 #endif 2340 /* 2341 * TODO: tests that probe expected_paddr in pages other than the one at 2342 * the beginning of the 1g region. 2343 */ 2344 TEST_EXPECT_EQ(vmcs_read(INFO_PHYS_ADDR), expected_paddr); 2345 } 2346 2347 static void 2348 ept_violation_at_level_mkhuge(bool mkhuge, int level, unsigned long clear, 2349 unsigned long set, enum ept_access_op op, 2350 u64 expected_qual) 2351 { 2352 struct ept_access_test_data *data = &ept_access_test_data; 2353 unsigned long orig_pte; 2354 2355 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2356 2357 do_ept_violation(level == 1 || mkhuge, op, expected_qual, 2358 op == OP_EXEC ? data->gpa + sizeof(unsigned long) : 2359 data->gpa); 2360 2361 /* Fix the violation and resume the op loop. */ 2362 ept_untwiddle(data->gpa, level, orig_pte); 2363 enter_guest(); 2364 skip_exit_vmcall(); 2365 } 2366 2367 static void 2368 ept_violation_at_level(int level, unsigned long clear, unsigned long set, 2369 enum ept_access_op op, u64 expected_qual) 2370 { 2371 ept_violation_at_level_mkhuge(false, level, clear, set, op, 2372 expected_qual); 2373 if (ept_huge_pages_supported(level)) 2374 ept_violation_at_level_mkhuge(true, level, clear, set, op, 2375 expected_qual); 2376 } 2377 2378 static void ept_violation(unsigned long clear, unsigned long set, 2379 enum ept_access_op op, u64 expected_qual) 2380 { 2381 ept_violation_at_level(1, clear, set, op, expected_qual); 2382 ept_violation_at_level(2, clear, set, op, expected_qual); 2383 ept_violation_at_level(3, clear, set, op, expected_qual); 2384 ept_violation_at_level(4, clear, set, op, expected_qual); 2385 } 2386 2387 static void ept_access_violation(unsigned long access, enum ept_access_op op, 2388 u64 expected_qual) 2389 { 2390 ept_violation(EPT_PRESENT, access, op, 2391 expected_qual | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2392 } 2393 2394 /* 2395 * For translations that don't involve a GVA, that is physical address (paddr) 2396 * accesses, EPT violations don't set the flag EPT_VLT_PADDR. For a typical 2397 * guest memory access, the hardware does GVA -> GPA -> HPA. However, certain 2398 * translations don't involve GVAs, such as when the hardware does the guest 2399 * page table walk. For example, in translating GVA_1 -> GPA_1, the guest MMU 2400 * might try to set an A bit on a guest PTE. If the GPA_2 that the PTE resides 2401 * on isn't present in the EPT, then the EPT violation will be for GPA_2 and 2402 * the EPT_VLT_PADDR bit will be clear in the exit qualification. 2403 * 2404 * Note that paddr violations can also be triggered by loading PAE page tables 2405 * with wonky addresses. We don't test that yet. 2406 * 2407 * This function modifies the EPT entry that maps the GPA that the guest page 2408 * table entry mapping ept_access_data.gva resides on. 2409 * 2410 * @ept_access EPT permissions to set. Other permissions are cleared. 2411 * 2412 * @pte_ad Set the A/D bits on the guest PTE accordingly. 2413 * 2414 * @op Guest operation to perform with ept_access_data.gva. 2415 * 2416 * @expect_violation 2417 * Is a violation expected during the paddr access? 2418 * 2419 * @expected_qual Expected qualification for the EPT violation. 2420 * EPT_VLT_PADDR should be clear. 2421 */ 2422 static void ept_access_paddr(unsigned long ept_access, unsigned long pte_ad, 2423 enum ept_access_op op, bool expect_violation, 2424 u64 expected_qual) 2425 { 2426 struct ept_access_test_data *data = &ept_access_test_data; 2427 unsigned long *ptep; 2428 unsigned long gpa; 2429 unsigned long orig_epte; 2430 2431 /* Modify the guest PTE mapping data->gva according to @pte_ad. */ 2432 ptep = get_pte_level(current_page_table(), data->gva, /*level=*/1); 2433 TEST_ASSERT(ptep); 2434 TEST_ASSERT_EQ(*ptep & PT_ADDR_MASK, data->gpa); 2435 *ptep = (*ptep & ~PT_AD_MASK) | pte_ad; 2436 ept_access_test_guest_flush_tlb(); 2437 2438 /* 2439 * Now modify the access bits on the EPT entry for the GPA that the 2440 * guest PTE resides on. Note that by modifying a single EPT entry, 2441 * we're potentially affecting 512 guest PTEs. However, we've carefully 2442 * constructed our test such that those other 511 PTEs aren't used by 2443 * the guest: data->gva is at the beginning of a 1G huge page, thus the 2444 * PTE we're modifying is at the beginning of a 4K page and the 2445 * following 511 entires are also under our control (and not touched by 2446 * the guest). 2447 */ 2448 gpa = virt_to_phys(ptep); 2449 TEST_ASSERT_EQ(gpa & ~PAGE_MASK, 0); 2450 /* 2451 * Make sure the guest page table page is mapped with a 4K EPT entry, 2452 * otherwise our level=1 twiddling below will fail. We use the 2453 * identity map (gpa = gpa) since page tables are shared with the host. 2454 */ 2455 install_ept(pml4, gpa, gpa, EPT_PRESENT); 2456 orig_epte = ept_twiddle(gpa, /*mkhuge=*/0, /*level=*/1, 2457 /*clear=*/EPT_PRESENT, /*set=*/ept_access); 2458 2459 if (expect_violation) { 2460 do_ept_violation(/*leaf=*/true, op, 2461 expected_qual | EPT_VLT_LADDR_VLD, gpa); 2462 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2463 do_ept_access_op(op); 2464 } else { 2465 do_ept_access_op(op); 2466 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2467 } 2468 2469 TEST_ASSERT(*ptep & PT_ACCESSED_MASK); 2470 if ((pte_ad & PT_DIRTY_MASK) || op == OP_WRITE) 2471 TEST_ASSERT(*ptep & PT_DIRTY_MASK); 2472 2473 skip_exit_vmcall(); 2474 } 2475 2476 static void ept_access_allowed_paddr(unsigned long ept_access, 2477 unsigned long pte_ad, 2478 enum ept_access_op op) 2479 { 2480 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/false, 2481 /*expected_qual=*/-1); 2482 } 2483 2484 static void ept_access_violation_paddr(unsigned long ept_access, 2485 unsigned long pte_ad, 2486 enum ept_access_op op, 2487 u64 expected_qual) 2488 { 2489 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/true, 2490 expected_qual); 2491 } 2492 2493 2494 static void ept_allowed_at_level_mkhuge(bool mkhuge, int level, 2495 unsigned long clear, 2496 unsigned long set, 2497 enum ept_access_op op) 2498 { 2499 struct ept_access_test_data *data = &ept_access_test_data; 2500 unsigned long orig_pte; 2501 2502 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2503 2504 /* No violation. Should proceed to vmcall. */ 2505 do_ept_access_op(op); 2506 skip_exit_vmcall(); 2507 2508 ept_untwiddle(data->gpa, level, orig_pte); 2509 } 2510 2511 static void ept_allowed_at_level(int level, unsigned long clear, 2512 unsigned long set, enum ept_access_op op) 2513 { 2514 ept_allowed_at_level_mkhuge(false, level, clear, set, op); 2515 if (ept_huge_pages_supported(level)) 2516 ept_allowed_at_level_mkhuge(true, level, clear, set, op); 2517 } 2518 2519 static void ept_allowed(unsigned long clear, unsigned long set, 2520 enum ept_access_op op) 2521 { 2522 ept_allowed_at_level(1, clear, set, op); 2523 ept_allowed_at_level(2, clear, set, op); 2524 ept_allowed_at_level(3, clear, set, op); 2525 ept_allowed_at_level(4, clear, set, op); 2526 } 2527 2528 static void ept_ignored_bit(int bit) 2529 { 2530 /* Set the bit. */ 2531 ept_allowed(0, 1ul << bit, OP_READ); 2532 ept_allowed(0, 1ul << bit, OP_WRITE); 2533 ept_allowed(0, 1ul << bit, OP_EXEC); 2534 2535 /* Clear the bit. */ 2536 ept_allowed(1ul << bit, 0, OP_READ); 2537 ept_allowed(1ul << bit, 0, OP_WRITE); 2538 ept_allowed(1ul << bit, 0, OP_EXEC); 2539 } 2540 2541 static void ept_access_allowed(unsigned long access, enum ept_access_op op) 2542 { 2543 ept_allowed(EPT_PRESENT, access, op); 2544 } 2545 2546 2547 static void ept_misconfig_at_level_mkhuge_op(bool mkhuge, int level, 2548 unsigned long clear, 2549 unsigned long set, 2550 enum ept_access_op op) 2551 { 2552 struct ept_access_test_data *data = &ept_access_test_data; 2553 unsigned long orig_pte; 2554 2555 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2556 2557 do_ept_access_op(op); 2558 assert_exit_reason(VMX_EPT_MISCONFIG); 2559 2560 /* Intel 27.2.1, "For all other VM exits, this field is cleared." */ 2561 #if 0 2562 /* broken: */ 2563 TEST_EXPECT_EQ_MSG(vmcs_read(EXI_QUALIFICATION), 0); 2564 #endif 2565 #if 0 2566 /* 2567 * broken: 2568 * According to description of exit qual for EPT violation, 2569 * EPT_VLT_LADDR_VLD indicates if GUEST_LINEAR_ADDRESS is valid. 2570 * However, I can't find anything that says GUEST_LINEAR_ADDRESS ought 2571 * to be set for msiconfig. 2572 */ 2573 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2574 (unsigned long) ( 2575 op == OP_EXEC ? data->gva + 1 : data->gva)); 2576 #endif 2577 2578 /* Fix the violation and resume the op loop. */ 2579 ept_untwiddle(data->gpa, level, orig_pte); 2580 enter_guest(); 2581 skip_exit_vmcall(); 2582 } 2583 2584 static void ept_misconfig_at_level_mkhuge(bool mkhuge, int level, 2585 unsigned long clear, 2586 unsigned long set) 2587 { 2588 /* The op shouldn't matter (read, write, exec), so try them all! */ 2589 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_READ); 2590 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_WRITE); 2591 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_EXEC); 2592 } 2593 2594 static void ept_misconfig_at_level(int level, unsigned long clear, 2595 unsigned long set) 2596 { 2597 ept_misconfig_at_level_mkhuge(false, level, clear, set); 2598 if (ept_huge_pages_supported(level)) 2599 ept_misconfig_at_level_mkhuge(true, level, clear, set); 2600 } 2601 2602 static void ept_misconfig(unsigned long clear, unsigned long set) 2603 { 2604 ept_misconfig_at_level(1, clear, set); 2605 ept_misconfig_at_level(2, clear, set); 2606 ept_misconfig_at_level(3, clear, set); 2607 ept_misconfig_at_level(4, clear, set); 2608 } 2609 2610 static void ept_access_misconfig(unsigned long access) 2611 { 2612 ept_misconfig(EPT_PRESENT, access); 2613 } 2614 2615 static void ept_reserved_bit_at_level_nohuge(int level, int bit) 2616 { 2617 /* Setting the bit causes a misconfig. */ 2618 ept_misconfig_at_level_mkhuge(false, level, 0, 1ul << bit); 2619 2620 /* Making the entry non-present turns reserved bits into ignored. */ 2621 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2622 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2623 } 2624 2625 static void ept_reserved_bit_at_level_huge(int level, int bit) 2626 { 2627 /* Setting the bit causes a misconfig. */ 2628 ept_misconfig_at_level_mkhuge(true, level, 0, 1ul << bit); 2629 2630 /* Making the entry non-present turns reserved bits into ignored. */ 2631 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2632 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2633 } 2634 2635 static void ept_reserved_bit_at_level(int level, int bit) 2636 { 2637 /* Setting the bit causes a misconfig. */ 2638 ept_misconfig_at_level(level, 0, 1ul << bit); 2639 2640 /* Making the entry non-present turns reserved bits into ignored. */ 2641 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2642 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2643 } 2644 2645 static void ept_reserved_bit(int bit) 2646 { 2647 ept_reserved_bit_at_level(1, bit); 2648 ept_reserved_bit_at_level(2, bit); 2649 ept_reserved_bit_at_level(3, bit); 2650 ept_reserved_bit_at_level(4, bit); 2651 } 2652 2653 #define PAGE_2M_ORDER 9 2654 #define PAGE_1G_ORDER 18 2655 2656 static void *get_1g_page(void) 2657 { 2658 static void *alloc; 2659 2660 if (!alloc) 2661 alloc = alloc_pages(PAGE_1G_ORDER); 2662 return alloc; 2663 } 2664 2665 static void ept_access_test_teardown(void *unused) 2666 { 2667 /* Exit the guest cleanly. */ 2668 do_ept_access_op(OP_EXIT); 2669 } 2670 2671 static void ept_access_test_guest(void) 2672 { 2673 struct ept_access_test_data *data = &ept_access_test_data; 2674 int (*code)(void) = (int (*)(void)) &data->gva[1]; 2675 2676 while (true) { 2677 switch (data->op) { 2678 case OP_READ: 2679 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_1); 2680 break; 2681 case OP_WRITE: 2682 *data->gva = MAGIC_VAL_2; 2683 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_2); 2684 *data->gva = MAGIC_VAL_1; 2685 break; 2686 case OP_EXEC: 2687 TEST_ASSERT_EQ(42, code()); 2688 break; 2689 case OP_FLUSH_TLB: 2690 write_cr3(read_cr3()); 2691 break; 2692 case OP_EXIT: 2693 return; 2694 default: 2695 TEST_ASSERT_MSG(false, "Unknown op %d", data->op); 2696 } 2697 vmcall(); 2698 } 2699 } 2700 2701 static void ept_access_test_setup(void) 2702 { 2703 struct ept_access_test_data *data = &ept_access_test_data; 2704 unsigned long npages = 1ul << PAGE_1G_ORDER; 2705 unsigned long size = npages * PAGE_SIZE; 2706 unsigned long *page_table = current_page_table(); 2707 unsigned long pte; 2708 2709 if (setup_ept(false)) 2710 test_skip("EPT not supported"); 2711 2712 /* We use data->gpa = 1 << 39 so that test data has a separate pml4 entry */ 2713 if (cpuid_maxphyaddr() < 40) 2714 test_skip("Test needs MAXPHYADDR >= 40"); 2715 2716 test_set_guest(ept_access_test_guest); 2717 test_add_teardown(ept_access_test_teardown, NULL); 2718 2719 data->hva = get_1g_page(); 2720 TEST_ASSERT(data->hva); 2721 data->hpa = virt_to_phys(data->hva); 2722 2723 data->gpa = 1ul << 39; 2724 data->gva = (void *) ALIGN((unsigned long) alloc_vpages(npages * 2), 2725 size); 2726 TEST_ASSERT(!any_present_pages(page_table, data->gva, size)); 2727 install_pages(page_table, data->gpa, size, data->gva); 2728 2729 /* 2730 * Make sure nothing's mapped here so the tests that screw with the 2731 * pml4 entry don't inadvertently break something. 2732 */ 2733 TEST_ASSERT(get_ept_pte(pml4, data->gpa, 4, &pte) && pte == 0); 2734 TEST_ASSERT(get_ept_pte(pml4, data->gpa + size - 1, 4, &pte) && pte == 0); 2735 install_ept(pml4, data->hpa, data->gpa, EPT_PRESENT); 2736 2737 data->hva[0] = MAGIC_VAL_1; 2738 memcpy(&data->hva[1], &ret42_start, &ret42_end - &ret42_start); 2739 } 2740 2741 static void ept_access_test_not_present(void) 2742 { 2743 ept_access_test_setup(); 2744 /* --- */ 2745 ept_access_violation(0, OP_READ, EPT_VLT_RD); 2746 ept_access_violation(0, OP_WRITE, EPT_VLT_WR); 2747 ept_access_violation(0, OP_EXEC, EPT_VLT_FETCH); 2748 } 2749 2750 static void ept_access_test_read_only(void) 2751 { 2752 ept_access_test_setup(); 2753 2754 /* r-- */ 2755 ept_access_allowed(EPT_RA, OP_READ); 2756 ept_access_violation(EPT_RA, OP_WRITE, EPT_VLT_WR | EPT_VLT_PERM_RD); 2757 ept_access_violation(EPT_RA, OP_EXEC, EPT_VLT_FETCH | EPT_VLT_PERM_RD); 2758 } 2759 2760 static void ept_access_test_write_only(void) 2761 { 2762 ept_access_test_setup(); 2763 /* -w- */ 2764 ept_access_misconfig(EPT_WA); 2765 } 2766 2767 static void ept_access_test_read_write(void) 2768 { 2769 ept_access_test_setup(); 2770 /* rw- */ 2771 ept_access_allowed(EPT_RA | EPT_WA, OP_READ); 2772 ept_access_allowed(EPT_RA | EPT_WA, OP_WRITE); 2773 ept_access_violation(EPT_RA | EPT_WA, OP_EXEC, 2774 EPT_VLT_FETCH | EPT_VLT_PERM_RD | EPT_VLT_PERM_WR); 2775 } 2776 2777 2778 static void ept_access_test_execute_only(void) 2779 { 2780 ept_access_test_setup(); 2781 /* --x */ 2782 if (ept_execute_only_supported()) { 2783 ept_access_violation(EPT_EA, OP_READ, 2784 EPT_VLT_RD | EPT_VLT_PERM_EX); 2785 ept_access_violation(EPT_EA, OP_WRITE, 2786 EPT_VLT_WR | EPT_VLT_PERM_EX); 2787 ept_access_allowed(EPT_EA, OP_EXEC); 2788 } else { 2789 ept_access_misconfig(EPT_EA); 2790 } 2791 } 2792 2793 static void ept_access_test_read_execute(void) 2794 { 2795 ept_access_test_setup(); 2796 /* r-x */ 2797 ept_access_allowed(EPT_RA | EPT_EA, OP_READ); 2798 ept_access_violation(EPT_RA | EPT_EA, OP_WRITE, 2799 EPT_VLT_WR | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX); 2800 ept_access_allowed(EPT_RA | EPT_EA, OP_EXEC); 2801 } 2802 2803 static void ept_access_test_write_execute(void) 2804 { 2805 ept_access_test_setup(); 2806 /* -wx */ 2807 ept_access_misconfig(EPT_WA | EPT_EA); 2808 } 2809 2810 static void ept_access_test_read_write_execute(void) 2811 { 2812 ept_access_test_setup(); 2813 /* rwx */ 2814 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_READ); 2815 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_WRITE); 2816 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_EXEC); 2817 } 2818 2819 static void ept_access_test_reserved_bits(void) 2820 { 2821 int i; 2822 int maxphyaddr; 2823 2824 ept_access_test_setup(); 2825 2826 /* Reserved bits above maxphyaddr. */ 2827 maxphyaddr = cpuid_maxphyaddr(); 2828 for (i = maxphyaddr; i <= 51; i++) { 2829 report_prefix_pushf("reserved_bit=%d", i); 2830 ept_reserved_bit(i); 2831 report_prefix_pop(); 2832 } 2833 2834 /* Level-specific reserved bits. */ 2835 ept_reserved_bit_at_level_nohuge(2, 3); 2836 ept_reserved_bit_at_level_nohuge(2, 4); 2837 ept_reserved_bit_at_level_nohuge(2, 5); 2838 ept_reserved_bit_at_level_nohuge(2, 6); 2839 /* 2M alignment. */ 2840 for (i = 12; i < 20; i++) { 2841 report_prefix_pushf("reserved_bit=%d", i); 2842 ept_reserved_bit_at_level_huge(2, i); 2843 report_prefix_pop(); 2844 } 2845 ept_reserved_bit_at_level_nohuge(3, 3); 2846 ept_reserved_bit_at_level_nohuge(3, 4); 2847 ept_reserved_bit_at_level_nohuge(3, 5); 2848 ept_reserved_bit_at_level_nohuge(3, 6); 2849 /* 1G alignment. */ 2850 for (i = 12; i < 29; i++) { 2851 report_prefix_pushf("reserved_bit=%d", i); 2852 ept_reserved_bit_at_level_huge(3, i); 2853 report_prefix_pop(); 2854 } 2855 ept_reserved_bit_at_level(4, 3); 2856 ept_reserved_bit_at_level(4, 4); 2857 ept_reserved_bit_at_level(4, 5); 2858 ept_reserved_bit_at_level(4, 6); 2859 ept_reserved_bit_at_level(4, 7); 2860 } 2861 2862 static void ept_access_test_ignored_bits(void) 2863 { 2864 ept_access_test_setup(); 2865 /* 2866 * Bits ignored at every level. Bits 8 and 9 (A and D) are ignored as 2867 * far as translation is concerned even if AD bits are enabled in the 2868 * EPTP. Bit 63 is ignored because "EPT-violation #VE" VM-execution 2869 * control is 0. 2870 */ 2871 ept_ignored_bit(8); 2872 ept_ignored_bit(9); 2873 ept_ignored_bit(10); 2874 ept_ignored_bit(11); 2875 ept_ignored_bit(52); 2876 ept_ignored_bit(53); 2877 ept_ignored_bit(54); 2878 ept_ignored_bit(55); 2879 ept_ignored_bit(56); 2880 ept_ignored_bit(57); 2881 ept_ignored_bit(58); 2882 ept_ignored_bit(59); 2883 ept_ignored_bit(60); 2884 ept_ignored_bit(61); 2885 ept_ignored_bit(62); 2886 ept_ignored_bit(63); 2887 } 2888 2889 static void ept_access_test_paddr_not_present_ad_disabled(void) 2890 { 2891 ept_access_test_setup(); 2892 ept_disable_ad_bits(); 2893 2894 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, EPT_VLT_RD); 2895 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, EPT_VLT_RD); 2896 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, EPT_VLT_RD); 2897 } 2898 2899 static void ept_access_test_paddr_not_present_ad_enabled(void) 2900 { 2901 u64 qual = EPT_VLT_RD | EPT_VLT_WR; 2902 2903 ept_access_test_setup(); 2904 ept_enable_ad_bits_or_skip_test(); 2905 2906 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, qual); 2907 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, qual); 2908 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, qual); 2909 } 2910 2911 static void ept_access_test_paddr_read_only_ad_disabled(void) 2912 { 2913 /* 2914 * When EPT AD bits are disabled, all accesses to guest paging 2915 * structures are reported separately as a read and (after 2916 * translation of the GPA to host physical address) a read+write 2917 * if the A/D bits have to be set. 2918 */ 2919 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 2920 2921 ept_access_test_setup(); 2922 ept_disable_ad_bits(); 2923 2924 /* Can't update A bit, so all accesses fail. */ 2925 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 2926 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 2927 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 2928 /* AD bits disabled, so only writes try to update the D bit. */ 2929 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ); 2930 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 2931 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC); 2932 /* Both A and D already set, so read-only is OK. */ 2933 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_READ); 2934 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_WRITE); 2935 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_EXEC); 2936 } 2937 2938 static void ept_access_test_paddr_read_only_ad_enabled(void) 2939 { 2940 /* 2941 * When EPT AD bits are enabled, all accesses to guest paging 2942 * structures are considered writes as far as EPT translation 2943 * is concerned. 2944 */ 2945 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 2946 2947 ept_access_test_setup(); 2948 ept_enable_ad_bits_or_skip_test(); 2949 2950 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 2951 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 2952 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 2953 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ, qual); 2954 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 2955 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC, qual); 2956 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_READ, qual); 2957 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_WRITE, qual); 2958 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_EXEC, qual); 2959 } 2960 2961 static void ept_access_test_paddr_read_write(void) 2962 { 2963 ept_access_test_setup(); 2964 /* Read-write access to paging structure. */ 2965 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_READ); 2966 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_WRITE); 2967 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_EXEC); 2968 } 2969 2970 static void ept_access_test_paddr_read_write_execute(void) 2971 { 2972 ept_access_test_setup(); 2973 /* RWX access to paging structure. */ 2974 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_READ); 2975 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_WRITE); 2976 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_EXEC); 2977 } 2978 2979 static void ept_access_test_paddr_read_execute_ad_disabled(void) 2980 { 2981 /* 2982 * When EPT AD bits are disabled, all accesses to guest paging 2983 * structures are reported separately as a read and (after 2984 * translation of the GPA to host physical address) a read+write 2985 * if the A/D bits have to be set. 2986 */ 2987 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 2988 2989 ept_access_test_setup(); 2990 ept_disable_ad_bits(); 2991 2992 /* Can't update A bit, so all accesses fail. */ 2993 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 2994 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 2995 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 2996 /* AD bits disabled, so only writes try to update the D bit. */ 2997 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ); 2998 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 2999 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC); 3000 /* Both A and D already set, so read-only is OK. */ 3001 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ); 3002 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE); 3003 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC); 3004 } 3005 3006 static void ept_access_test_paddr_read_execute_ad_enabled(void) 3007 { 3008 /* 3009 * When EPT AD bits are enabled, all accesses to guest paging 3010 * structures are considered writes as far as EPT translation 3011 * is concerned. 3012 */ 3013 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3014 3015 ept_access_test_setup(); 3016 ept_enable_ad_bits_or_skip_test(); 3017 3018 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3019 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3020 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3021 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ, qual); 3022 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3023 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC, qual); 3024 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ, qual); 3025 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE, qual); 3026 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC, qual); 3027 } 3028 3029 static void ept_access_test_paddr_not_present_page_fault(void) 3030 { 3031 ept_access_test_setup(); 3032 /* 3033 * TODO: test no EPT violation as long as guest PF occurs. e.g., GPA is 3034 * page is read-only in EPT but GVA is also mapped read only in PT. 3035 * Thus guest page fault before host takes EPT violation for trying to 3036 * update A bit. 3037 */ 3038 } 3039 3040 static void ept_access_test_force_2m_page(void) 3041 { 3042 ept_access_test_setup(); 3043 3044 TEST_ASSERT_EQ(ept_2m_supported(), true); 3045 ept_allowed_at_level_mkhuge(true, 2, 0, 0, OP_READ); 3046 ept_violation_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_RA, OP_WRITE, 3047 EPT_VLT_WR | EPT_VLT_PERM_RD | 3048 EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 3049 ept_misconfig_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_WA); 3050 } 3051 3052 static bool invvpid_valid(u64 type, u64 vpid, u64 gla) 3053 { 3054 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3055 3056 TEST_ASSERT(msr & VPID_CAP_INVVPID); 3057 3058 if (type < INVVPID_ADDR || type > INVVPID_CONTEXT_LOCAL) 3059 return false; 3060 3061 if (!(msr & (1ull << (type + VPID_CAP_INVVPID_TYPES_SHIFT)))) 3062 return false; 3063 3064 if (vpid >> 16) 3065 return false; 3066 3067 if (type != INVVPID_ALL && !vpid) 3068 return false; 3069 3070 if (type == INVVPID_ADDR && !is_canonical(gla)) 3071 return false; 3072 3073 return true; 3074 } 3075 3076 static void try_invvpid(u64 type, u64 vpid, u64 gla) 3077 { 3078 int rc; 3079 bool valid = invvpid_valid(type, vpid, gla); 3080 u64 expected = valid ? VMXERR_UNSUPPORTED_VMCS_COMPONENT 3081 : VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID; 3082 /* 3083 * Set VMX_INST_ERROR to VMXERR_UNVALID_VMCS_COMPONENT, so 3084 * that we can tell if it is updated by INVVPID. 3085 */ 3086 vmcs_read(~0); 3087 rc = invvpid(type, vpid, gla); 3088 report("INVVPID type %ld VPID %lx GLA %lx %s", 3089 !rc == valid, type, vpid, gla, 3090 valid ? "passes" : "fails"); 3091 report("After %s INVVPID, VMX_INST_ERR is %ld (actual %ld)", 3092 vmcs_read(VMX_INST_ERROR) == expected, 3093 rc ? "failed" : "successful", 3094 expected, vmcs_read(VMX_INST_ERROR)); 3095 } 3096 3097 static void ds_invvpid(void *data) 3098 { 3099 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3100 u64 type = ffs(msr >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 3101 3102 TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 3103 asm volatile("invvpid %0, %1" 3104 : 3105 : "m"(*(struct invvpid_operand *)data), 3106 "r"(type)); 3107 } 3108 3109 /* 3110 * The SS override is ignored in 64-bit mode, so we use an addressing 3111 * mode with %rsp as the base register to generate an implicit SS 3112 * reference. 3113 */ 3114 static void ss_invvpid(void *data) 3115 { 3116 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3117 u64 type = ffs(msr >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 3118 3119 TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 3120 asm volatile("sub %%rsp,%0; invvpid (%%rsp,%0,1), %1" 3121 : "+r"(data) 3122 : "r"(type)); 3123 } 3124 3125 static void invvpid_test_gp(void) 3126 { 3127 bool fault; 3128 3129 fault = test_for_exception(GP_VECTOR, &ds_invvpid, 3130 (void *)NONCANONICAL); 3131 report("INVVPID with non-canonical DS operand raises #GP", fault); 3132 } 3133 3134 static void invvpid_test_ss(void) 3135 { 3136 bool fault; 3137 3138 fault = test_for_exception(SS_VECTOR, &ss_invvpid, 3139 (void *)NONCANONICAL); 3140 report("INVVPID with non-canonical SS operand raises #SS", fault); 3141 } 3142 3143 static void invvpid_test_pf(void) 3144 { 3145 void *vpage = alloc_vpage(); 3146 bool fault; 3147 3148 fault = test_for_exception(PF_VECTOR, &ds_invvpid, vpage); 3149 report("INVVPID with unmapped operand raises #PF", fault); 3150 } 3151 3152 static void try_compat_invvpid(void *unused) 3153 { 3154 struct far_pointer32 fp = { 3155 .offset = (uintptr_t)&&invvpid, 3156 .selector = KERNEL_CS32, 3157 }; 3158 register uintptr_t rsp asm("rsp"); 3159 3160 TEST_ASSERT_MSG(fp.offset == (uintptr_t)&&invvpid, 3161 "Code address too high."); 3162 TEST_ASSERT_MSG(rsp == (u32)rsp, "Stack address too high."); 3163 3164 asm goto ("lcall *%0" : : "m" (fp) : "rax" : invvpid); 3165 return; 3166 invvpid: 3167 asm volatile (".code32;" 3168 "invvpid (%eax), %eax;" 3169 "lret;" 3170 ".code64"); 3171 __builtin_unreachable(); 3172 } 3173 3174 static void invvpid_test_compatibility_mode(void) 3175 { 3176 bool fault; 3177 3178 fault = test_for_exception(UD_VECTOR, &try_compat_invvpid, NULL); 3179 report("Compatibility mode INVVPID raises #UD", fault); 3180 } 3181 3182 static void invvpid_test_not_in_vmx_operation(void) 3183 { 3184 bool fault; 3185 3186 TEST_ASSERT(!vmx_off()); 3187 fault = test_for_exception(UD_VECTOR, &ds_invvpid, NULL); 3188 report("INVVPID outside of VMX operation raises #UD", fault); 3189 TEST_ASSERT(!vmx_on()); 3190 } 3191 3192 /* 3193 * This does not test real-address mode, virtual-8086 mode, protected mode, 3194 * or CPL > 0. 3195 */ 3196 static void invvpid_test_v2(void) 3197 { 3198 u64 msr; 3199 int i; 3200 unsigned types = 0; 3201 unsigned type; 3202 3203 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 3204 !(ctrl_cpu_rev[1].clr & CPU_VPID)) 3205 test_skip("VPID not supported"); 3206 3207 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3208 3209 if (!(msr & VPID_CAP_INVVPID)) 3210 test_skip("INVVPID not supported.\n"); 3211 3212 if (msr & VPID_CAP_INVVPID_ADDR) 3213 types |= 1u << INVVPID_ADDR; 3214 if (msr & VPID_CAP_INVVPID_CXTGLB) 3215 types |= 1u << INVVPID_CONTEXT_GLOBAL; 3216 if (msr & VPID_CAP_INVVPID_ALL) 3217 types |= 1u << INVVPID_ALL; 3218 if (msr & VPID_CAP_INVVPID_CXTLOC) 3219 types |= 1u << INVVPID_CONTEXT_LOCAL; 3220 3221 if (!types) 3222 test_skip("No INVVPID types supported.\n"); 3223 3224 for (i = -127; i < 128; i++) 3225 try_invvpid(i, 0xffff, 0); 3226 3227 /* 3228 * VPID must not be more than 16 bits. 3229 */ 3230 for (i = 0; i < 64; i++) 3231 for (type = 0; type < 4; type++) 3232 if (types & (1u << type)) 3233 try_invvpid(type, 1ul << i, 0); 3234 3235 /* 3236 * VPID must not be zero, except for "all contexts." 3237 */ 3238 for (type = 0; type < 4; type++) 3239 if (types & (1u << type)) 3240 try_invvpid(type, 0, 0); 3241 3242 /* 3243 * The gla operand is only validated for single-address INVVPID. 3244 */ 3245 if (types & (1u << INVVPID_ADDR)) 3246 try_invvpid(INVVPID_ADDR, 0xffff, NONCANONICAL); 3247 3248 invvpid_test_gp(); 3249 invvpid_test_ss(); 3250 invvpid_test_pf(); 3251 invvpid_test_compatibility_mode(); 3252 invvpid_test_not_in_vmx_operation(); 3253 } 3254 3255 /* 3256 * Test for early VMLAUNCH failure. Returns true if VMLAUNCH makes it 3257 * at least as far as the guest-state checks. Returns false if the 3258 * VMLAUNCH fails early and execution falls through to the next 3259 * instruction. 3260 */ 3261 static bool vmlaunch_succeeds(void) 3262 { 3263 /* 3264 * Indirectly set VMX_INST_ERR to 12 ("VMREAD/VMWRITE from/to 3265 * unsupported VMCS component"). The caller can then check 3266 * to see if a failed VM-entry sets VMX_INST_ERR as expected. 3267 */ 3268 vmcs_write(~0u, 0); 3269 3270 vmcs_write(HOST_RIP, (uintptr_t)&&success); 3271 __asm__ __volatile__ goto ("vmwrite %%rsp, %0; vmlaunch" 3272 : 3273 : "r" ((u64)HOST_RSP) 3274 : "cc", "memory" 3275 : success); 3276 return false; 3277 success: 3278 TEST_ASSERT(vmcs_read(EXI_REASON) == 3279 (VMX_FAIL_STATE | VMX_ENTRY_FAILURE)); 3280 return true; 3281 } 3282 3283 /* 3284 * Try to launch the current VMCS. 3285 */ 3286 static void test_vmx_controls(bool controls_valid, bool xfail) 3287 { 3288 bool success = vmlaunch_succeeds(); 3289 u32 vmx_inst_err; 3290 3291 report_xfail("vmlaunch %s", xfail, success == controls_valid, 3292 controls_valid ? "succeeds" : "fails"); 3293 if (!success) { 3294 vmx_inst_err = vmcs_read(VMX_INST_ERROR); 3295 report("VMX inst error is %d (actual %d)", 3296 vmx_inst_err == VMXERR_ENTRY_INVALID_CONTROL_FIELD, 3297 VMXERR_ENTRY_INVALID_CONTROL_FIELD, vmx_inst_err); 3298 } 3299 } 3300 3301 /* 3302 * Test a particular value of a VM-execution control bit, if the value 3303 * is required or if the value is zero. 3304 */ 3305 static void test_rsvd_ctl_bit_value(const char *name, union vmx_ctrl_msr msr, 3306 enum Encoding encoding, unsigned bit, 3307 unsigned val) 3308 { 3309 u32 mask = 1u << bit; 3310 bool expected; 3311 u32 controls; 3312 3313 if (msr.set & mask) 3314 TEST_ASSERT(msr.clr & mask); 3315 3316 /* 3317 * We can't arbitrarily turn on a control bit, because it may 3318 * introduce dependencies on other VMCS fields. So, we only 3319 * test turning on bits that have a required setting. 3320 */ 3321 if (val && (msr.clr & mask) && !(msr.set & mask)) 3322 return; 3323 3324 report_prefix_pushf("%s %s bit %d", 3325 val ? "Set" : "Clear", name, bit); 3326 3327 controls = vmcs_read(encoding); 3328 if (val) { 3329 vmcs_write(encoding, msr.set | mask); 3330 expected = (msr.clr & mask); 3331 } else { 3332 vmcs_write(encoding, msr.set & ~mask); 3333 expected = !(msr.set & mask); 3334 } 3335 test_vmx_controls(expected, false); 3336 vmcs_write(encoding, controls); 3337 report_prefix_pop(); 3338 } 3339 3340 /* 3341 * Test reserved values of a VM-execution control bit, based on the 3342 * allowed bit settings from the corresponding VMX capability MSR. 3343 */ 3344 static void test_rsvd_ctl_bit(const char *name, union vmx_ctrl_msr msr, 3345 enum Encoding encoding, unsigned bit) 3346 { 3347 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 0); 3348 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 1); 3349 } 3350 3351 /* 3352 * Reserved bits in the pin-based VM-execution controls must be set 3353 * properly. Software may consult the VMX capability MSRs to determine 3354 * the proper settings. 3355 * [Intel SDM] 3356 */ 3357 static void test_pin_based_ctls(void) 3358 { 3359 unsigned bit; 3360 3361 printf("%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PIN" : 3362 "MSR_IA32_VMX_PINBASED_CTLS", ctrl_pin_rev.val); 3363 for (bit = 0; bit < 32; bit++) 3364 test_rsvd_ctl_bit("pin-based controls", 3365 ctrl_pin_rev, PIN_CONTROLS, bit); 3366 } 3367 3368 /* 3369 * Reserved bits in the primary processor-based VM-execution controls 3370 * must be set properly. Software may consult the VMX capability MSRs 3371 * to determine the proper settings. 3372 * [Intel SDM] 3373 */ 3374 static void test_primary_processor_based_ctls(void) 3375 { 3376 unsigned bit; 3377 3378 printf("\n%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PROC" : 3379 "MSR_IA32_VMX_PROCBASED_CTLS", ctrl_cpu_rev[0].val); 3380 for (bit = 0; bit < 32; bit++) 3381 test_rsvd_ctl_bit("primary processor-based controls", 3382 ctrl_cpu_rev[0], CPU_EXEC_CTRL0, bit); 3383 } 3384 3385 /* 3386 * If the "activate secondary controls" primary processor-based 3387 * VM-execution control is 1, reserved bits in the secondary 3388 * processor-based VM-execution controls must be cleared. Software may 3389 * consult the VMX capability MSRs to determine which bits are 3390 * reserved. 3391 * If the "activate secondary controls" primary processor-based 3392 * VM-execution control is 0 (or if the processor does not support the 3393 * 1-setting of that control), no checks are performed on the 3394 * secondary processor-based VM-execution controls. 3395 * [Intel SDM] 3396 */ 3397 static void test_secondary_processor_based_ctls(void) 3398 { 3399 u32 primary; 3400 u32 secondary; 3401 unsigned bit; 3402 3403 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) 3404 return; 3405 3406 primary = vmcs_read(CPU_EXEC_CTRL0); 3407 secondary = vmcs_read(CPU_EXEC_CTRL1); 3408 3409 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3410 printf("\nMSR_IA32_VMX_PROCBASED_CTLS2: %lx\n", ctrl_cpu_rev[1].val); 3411 for (bit = 0; bit < 32; bit++) 3412 test_rsvd_ctl_bit("secondary processor-based controls", 3413 ctrl_cpu_rev[1], CPU_EXEC_CTRL1, bit); 3414 3415 /* 3416 * When the "activate secondary controls" VM-execution control 3417 * is clear, there are no checks on the secondary controls. 3418 */ 3419 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3420 vmcs_write(CPU_EXEC_CTRL1, ~0); 3421 report("Secondary processor-based controls ignored", 3422 vmlaunch_succeeds()); 3423 vmcs_write(CPU_EXEC_CTRL1, secondary); 3424 vmcs_write(CPU_EXEC_CTRL0, primary); 3425 } 3426 3427 static void try_cr3_target_count(unsigned i, unsigned max) 3428 { 3429 report_prefix_pushf("CR3 target count 0x%x", i); 3430 vmcs_write(CR3_TARGET_COUNT, i); 3431 test_vmx_controls(i <= max, false); 3432 report_prefix_pop(); 3433 } 3434 3435 /* 3436 * The CR3-target count must not be greater than 4. Future processors 3437 * may support a different number of CR3-target values. Software 3438 * should read the VMX capability MSR IA32_VMX_MISC to determine the 3439 * number of values supported. 3440 * [Intel SDM] 3441 */ 3442 static void test_cr3_targets(void) 3443 { 3444 unsigned supported_targets = (rdmsr(MSR_IA32_VMX_MISC) >> 16) & 0x1ff; 3445 u32 cr3_targets = vmcs_read(CR3_TARGET_COUNT); 3446 unsigned i; 3447 3448 printf("\nSupported CR3 targets: %d\n", supported_targets); 3449 TEST_ASSERT(supported_targets <= 256); 3450 3451 try_cr3_target_count(-1u, supported_targets); 3452 try_cr3_target_count(0x80000000, supported_targets); 3453 try_cr3_target_count(0x7fffffff, supported_targets); 3454 for (i = 0; i <= supported_targets + 1; i++) 3455 try_cr3_target_count(i, supported_targets); 3456 vmcs_write(CR3_TARGET_COUNT, cr3_targets); 3457 } 3458 3459 /* 3460 * Test a particular address setting for a physical page reference in 3461 * the VMCS. 3462 */ 3463 static void test_vmcs_page_addr(const char *name, 3464 enum Encoding encoding, 3465 bool ignored, 3466 bool xfail_beyond_mapped_ram, 3467 u64 addr) 3468 { 3469 bool xfail = 3470 (xfail_beyond_mapped_ram && 3471 addr > fwcfg_get_u64(FW_CFG_RAM_SIZE) - PAGE_SIZE && 3472 addr < (1ul << cpuid_maxphyaddr())); 3473 3474 report_prefix_pushf("%s = %lx", name, addr); 3475 vmcs_write(encoding, addr); 3476 test_vmx_controls(ignored || (IS_ALIGNED(addr, PAGE_SIZE) && 3477 addr < (1ul << cpuid_maxphyaddr())), 3478 xfail); 3479 report_prefix_pop(); 3480 xfail = false; 3481 } 3482 3483 /* 3484 * Test interesting values for a physical page reference in the VMCS. 3485 */ 3486 static void test_vmcs_page_values(const char *name, 3487 enum Encoding encoding, 3488 bool ignored, 3489 bool xfail_beyond_mapped_ram) 3490 { 3491 unsigned i; 3492 u64 orig_val = vmcs_read(encoding); 3493 3494 for (i = 0; i < 64; i++) 3495 test_vmcs_page_addr(name, encoding, ignored, 3496 xfail_beyond_mapped_ram, 1ul << i); 3497 3498 test_vmcs_page_addr(name, encoding, ignored, 3499 xfail_beyond_mapped_ram, PAGE_SIZE - 1); 3500 test_vmcs_page_addr(name, encoding, ignored, 3501 xfail_beyond_mapped_ram, PAGE_SIZE); 3502 test_vmcs_page_addr(name, encoding, ignored, 3503 xfail_beyond_mapped_ram, 3504 (1ul << cpuid_maxphyaddr()) - PAGE_SIZE); 3505 test_vmcs_page_addr(name, encoding, ignored, 3506 xfail_beyond_mapped_ram, 3507 -1ul); 3508 3509 vmcs_write(encoding, orig_val); 3510 } 3511 3512 /* 3513 * Test a physical page reference in the VMCS, when the corresponding 3514 * feature is enabled and when the corresponding feature is disabled. 3515 */ 3516 static void test_vmcs_page_reference(u32 control_bit, enum Encoding field, 3517 const char *field_name, 3518 const char *control_name, 3519 bool xfail_beyond_mapped_ram, 3520 bool control_primary) 3521 { 3522 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 3523 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 3524 u64 page_addr; 3525 3526 if (control_primary) { 3527 if (!(ctrl_cpu_rev[0].clr & control_bit)) 3528 return; 3529 } else { 3530 if (!(ctrl_cpu_rev[1].clr & control_bit)) 3531 return; 3532 } 3533 3534 page_addr = vmcs_read(field); 3535 3536 report_prefix_pushf("%s enabled", control_name); 3537 if (control_primary) { 3538 vmcs_write(CPU_EXEC_CTRL0, primary | control_bit); 3539 } else { 3540 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3541 vmcs_write(CPU_EXEC_CTRL1, secondary | control_bit); 3542 } 3543 test_vmcs_page_values(field_name, field, false, xfail_beyond_mapped_ram); 3544 report_prefix_pop(); 3545 3546 report_prefix_pushf("%s disabled", control_name); 3547 if (control_primary) { 3548 vmcs_write(CPU_EXEC_CTRL0, primary & ~control_bit); 3549 } else { 3550 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3551 vmcs_write(CPU_EXEC_CTRL1, secondary & ~control_bit); 3552 } 3553 test_vmcs_page_values(field_name, field, true, false); 3554 report_prefix_pop(); 3555 3556 vmcs_write(field, page_addr); 3557 vmcs_write(CPU_EXEC_CTRL0, primary); 3558 } 3559 3560 /* 3561 * If the "use I/O bitmaps" VM-execution control is 1, bits 11:0 of 3562 * each I/O-bitmap address must be 0. Neither address should set any 3563 * bits beyond the processor's physical-address width. 3564 * [Intel SDM] 3565 */ 3566 static void test_io_bitmaps(void) 3567 { 3568 test_vmcs_page_reference(CPU_IO_BITMAP, IO_BITMAP_A, 3569 "I/O bitmap A", "Use I/O bitmaps", false, 3570 true); 3571 test_vmcs_page_reference(CPU_IO_BITMAP, IO_BITMAP_B, 3572 "I/O bitmap B", "Use I/O bitmaps", false, 3573 true); 3574 } 3575 3576 /* 3577 * If the "use MSR bitmaps" VM-execution control is 1, bits 11:0 of 3578 * the MSR-bitmap address must be 0. The address should not set any 3579 * bits beyond the processor's physical-address width. 3580 * [Intel SDM] 3581 */ 3582 static void test_msr_bitmap(void) 3583 { 3584 test_vmcs_page_reference(CPU_MSR_BITMAP, MSR_BITMAP, 3585 "MSR bitmap", "Use MSR bitmaps", false, 3586 true); 3587 } 3588 3589 /* 3590 * If the "use TPR shadow" VM-execution control is 1, the virtual-APIC 3591 * address must satisfy the following checks: 3592 * - Bits 11:0 of the address must be 0. 3593 * - The address should not set any bits beyond the processor's 3594 * physical-address width. 3595 * [Intel SDM] 3596 */ 3597 static void test_apic_virt_addr(void) 3598 { 3599 test_vmcs_page_reference(CPU_TPR_SHADOW, APIC_VIRT_ADDR, 3600 "virtual-APIC address", "Use TPR shadow", 3601 true, true); 3602 } 3603 3604 /* 3605 * If the "virtualize APIC-accesses" VM-execution control is 1, the 3606 * APIC-access address must satisfy the following checks: 3607 * - Bits 11:0 of the address must be 0. 3608 * - The address should not set any bits beyond the processor's 3609 * physical-address width. 3610 * [Intel SDM] 3611 */ 3612 static void test_apic_access_addr(void) 3613 { 3614 void *apic_access_page = alloc_page(); 3615 3616 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_page)); 3617 3618 test_vmcs_page_reference(CPU_VIRT_APIC_ACCESSES, APIC_ACCS_ADDR, 3619 "APIC-access address", 3620 "virtualize APIC-accesses", false, false); 3621 } 3622 3623 static bool set_bit_pattern(u8 mask, u32 *secondary) 3624 { 3625 u8 i; 3626 bool flag = false; 3627 u32 test_bits[3] = { 3628 CPU_VIRT_X2APIC, 3629 CPU_APIC_REG_VIRT, 3630 CPU_VINTD 3631 }; 3632 3633 for (i = 0; i < ARRAY_SIZE(test_bits); i++) { 3634 if ((mask & (1u << i)) && 3635 (ctrl_cpu_rev[1].clr & test_bits[i])) { 3636 *secondary |= test_bits[i]; 3637 flag = true; 3638 } 3639 } 3640 3641 return (flag); 3642 } 3643 3644 /* 3645 * If the "use TPR shadow" VM-execution control is 0, the following 3646 * VM-execution controls must also be 0: 3647 * - virtualize x2APIC mode 3648 * - APIC-register virtualization 3649 * - virtual-interrupt delivery 3650 * [Intel SDM] 3651 * 3652 * 2. If the "virtualize x2APIC mode" VM-execution control is 1, the 3653 * "virtualize APIC accesses" VM-execution control must be 0. 3654 * [Intel SDM] 3655 */ 3656 static void test_apic_virtual_ctls(void) 3657 { 3658 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3659 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3660 u32 primary = saved_primary; 3661 u32 secondary = saved_secondary; 3662 bool ctrl = false; 3663 char str[10] = "disabled"; 3664 u8 i = 0, j; 3665 3666 /* 3667 * First test 3668 */ 3669 if (!((ctrl_cpu_rev[0].clr & (CPU_SECONDARY | CPU_TPR_SHADOW)) == 3670 (CPU_SECONDARY | CPU_TPR_SHADOW))) 3671 return; 3672 3673 primary |= CPU_SECONDARY; 3674 primary &= ~CPU_TPR_SHADOW; 3675 vmcs_write(CPU_EXEC_CTRL0, primary); 3676 3677 while (1) { 3678 for (j = 1; j < 8; j++) { 3679 secondary &= ~(CPU_VIRT_X2APIC | CPU_APIC_REG_VIRT | CPU_VINTD); 3680 if (primary & CPU_TPR_SHADOW) { 3681 ctrl = true; 3682 } else { 3683 if (! set_bit_pattern(j, &secondary)) 3684 ctrl = true; 3685 else 3686 ctrl = false; 3687 } 3688 3689 vmcs_write(CPU_EXEC_CTRL1, secondary); 3690 report_prefix_pushf("Use TPR shadow %s, virtualize x2APIC mode %s, APIC-register virtualization %s, virtual-interrupt delivery %s", 3691 str, (secondary & CPU_VIRT_X2APIC) ? "enabled" : "disabled", (secondary & CPU_APIC_REG_VIRT) ? "enabled" : "disabled", (secondary & CPU_VINTD) ? "enabled" : "disabled"); 3692 test_vmx_controls(ctrl, false); 3693 report_prefix_pop(); 3694 } 3695 3696 if (i == 1) 3697 break; 3698 i++; 3699 3700 primary |= CPU_TPR_SHADOW; 3701 vmcs_write(CPU_EXEC_CTRL0, primary); 3702 strcpy(str, "enabled"); 3703 } 3704 3705 /* 3706 * Second test 3707 */ 3708 u32 apic_virt_ctls = (CPU_VIRT_X2APIC | CPU_VIRT_APIC_ACCESSES); 3709 3710 primary = saved_primary; 3711 secondary = saved_secondary; 3712 if (!((ctrl_cpu_rev[1].clr & apic_virt_ctls) == apic_virt_ctls)) 3713 return; 3714 3715 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3716 secondary &= ~CPU_VIRT_APIC_ACCESSES; 3717 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_X2APIC); 3718 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access disabled"); 3719 test_vmx_controls(true, false); 3720 report_prefix_pop(); 3721 3722 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_APIC_ACCESSES); 3723 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access enabled"); 3724 test_vmx_controls(true, false); 3725 report_prefix_pop(); 3726 3727 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_X2APIC); 3728 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access enabled"); 3729 test_vmx_controls(false, false); 3730 report_prefix_pop(); 3731 3732 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_APIC_ACCESSES); 3733 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access disabled"); 3734 test_vmx_controls(true, false); 3735 report_prefix_pop(); 3736 3737 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3738 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3739 } 3740 3741 /* 3742 * If the "virtual-interrupt delivery" VM-execution control is 1, the 3743 * "external-interrupt exiting" VM-execution control must be 1. 3744 * [Intel SDM] 3745 */ 3746 static void test_virtual_intr_ctls(void) 3747 { 3748 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3749 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3750 u32 saved_pin = vmcs_read(PIN_CONTROLS); 3751 u32 primary = saved_primary; 3752 u32 secondary = saved_secondary; 3753 u32 pin = saved_pin; 3754 3755 if (!((ctrl_cpu_rev[1].clr & CPU_VINTD) && 3756 (ctrl_pin_rev.clr & PIN_EXTINT))) 3757 return; 3758 3759 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 3760 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VINTD); 3761 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 3762 report_prefix_pushf("Virtualize interrupt-delivery disabled; external-interrupt exiting disabled"); 3763 test_vmx_controls(true, false); 3764 report_prefix_pop(); 3765 3766 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VINTD); 3767 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 3768 test_vmx_controls(false, false); 3769 report_prefix_pop(); 3770 3771 vmcs_write(PIN_CONTROLS, pin | PIN_EXTINT); 3772 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting enabled"); 3773 test_vmx_controls(true, false); 3774 report_prefix_pop(); 3775 3776 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 3777 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 3778 test_vmx_controls(false, false); 3779 report_prefix_pop(); 3780 3781 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3782 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3783 vmcs_write(PIN_CONTROLS, saved_pin); 3784 } 3785 3786 static void test_pi_desc_addr(u64 addr, bool ctrl) 3787 { 3788 vmcs_write(POSTED_INTR_DESC_ADDR, addr); 3789 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-descriptor-address 0x%lx", addr); 3790 test_vmx_controls(ctrl, false); 3791 report_prefix_pop(); 3792 } 3793 3794 /* 3795 * If the “process posted interrupts†VM-execution control is 1, the 3796 * following must be true: 3797 * 3798 * - The “virtual-interrupt delivery†VM-execution control is 1. 3799 * - The “acknowledge interrupt on exit†VM-exit control is 1. 3800 * - The posted-interrupt notification vector has a value in the 3801 * - range 0–255 (bits 15:8 are all 0). 3802 * - Bits 5:0 of the posted-interrupt descriptor address are all 0. 3803 * - The posted-interrupt descriptor address does not set any bits 3804 * beyond the processor's physical-address width. 3805 * [Intel SDM] 3806 */ 3807 static void test_posted_intr(void) 3808 { 3809 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3810 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3811 u32 saved_pin = vmcs_read(PIN_CONTROLS); 3812 u32 exit_ctl_saved = vmcs_read(EXI_CONTROLS); 3813 u32 primary = saved_primary; 3814 u32 secondary = saved_secondary; 3815 u32 pin = saved_pin; 3816 u32 exit_ctl = exit_ctl_saved; 3817 u16 vec; 3818 int i; 3819 3820 if (!((ctrl_pin_rev.clr & PIN_POST_INTR) && 3821 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 3822 (ctrl_exit_rev.clr & EXI_INTA))) 3823 return; 3824 3825 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 3826 3827 /* 3828 * Test virtual-interrupt-delivery and acknowledge-interrupt-on-exit 3829 */ 3830 pin |= PIN_POST_INTR; 3831 vmcs_write(PIN_CONTROLS, pin); 3832 secondary &= ~CPU_VINTD; 3833 vmcs_write(CPU_EXEC_CTRL1, secondary); 3834 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled"); 3835 test_vmx_controls(false, false); 3836 report_prefix_pop(); 3837 3838 secondary |= CPU_VINTD; 3839 vmcs_write(CPU_EXEC_CTRL1, secondary); 3840 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled"); 3841 test_vmx_controls(false, false); 3842 report_prefix_pop(); 3843 3844 exit_ctl &= ~EXI_INTA; 3845 vmcs_write(EXI_CONTROLS, exit_ctl); 3846 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit disabled"); 3847 test_vmx_controls(false, false); 3848 report_prefix_pop(); 3849 3850 exit_ctl |= EXI_INTA; 3851 vmcs_write(EXI_CONTROLS, exit_ctl); 3852 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 3853 test_vmx_controls(true, false); 3854 report_prefix_pop(); 3855 3856 secondary &= ~CPU_VINTD; 3857 vmcs_write(CPU_EXEC_CTRL1, secondary); 3858 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled; acknowledge-interrupt-on-exit enabled"); 3859 test_vmx_controls(false, false); 3860 report_prefix_pop(); 3861 3862 secondary |= CPU_VINTD; 3863 vmcs_write(CPU_EXEC_CTRL1, secondary); 3864 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 3865 test_vmx_controls(true, false); 3866 report_prefix_pop(); 3867 3868 /* 3869 * Test posted-interrupt notification vector 3870 */ 3871 for (i = 0; i < 8; i++) { 3872 vec = (1ul << i); 3873 vmcs_write(PINV, vec); 3874 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 3875 test_vmx_controls(true, false); 3876 report_prefix_pop(); 3877 } 3878 for (i = 8; i < 16; i++) { 3879 vec = (1ul << i); 3880 vmcs_write(PINV, vec); 3881 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 3882 test_vmx_controls(false, false); 3883 report_prefix_pop(); 3884 } 3885 3886 vec &= ~(0xff << 8); 3887 vmcs_write(PINV, vec); 3888 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 3889 test_vmx_controls(true, false); 3890 report_prefix_pop(); 3891 3892 /* 3893 * Test posted-interrupt descriptor addresss 3894 */ 3895 for (i = 0; i < 6; i++) { 3896 test_pi_desc_addr(1ul << i, false); 3897 } 3898 3899 test_pi_desc_addr(0xf0, false); 3900 test_pi_desc_addr(0xff, false); 3901 test_pi_desc_addr(0x0f, false); 3902 test_pi_desc_addr(0x8000, true); 3903 test_pi_desc_addr(0x00, true); 3904 test_pi_desc_addr(0xc000, true); 3905 3906 test_vmcs_page_values("process-posted interrupts", 3907 POSTED_INTR_DESC_ADDR, false, false); 3908 3909 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3910 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3911 vmcs_write(PIN_CONTROLS, saved_pin); 3912 } 3913 3914 static void test_apic_ctls(void) 3915 { 3916 test_apic_virt_addr(); 3917 test_apic_access_addr(); 3918 test_apic_virtual_ctls(); 3919 test_virtual_intr_ctls(); 3920 test_posted_intr(); 3921 } 3922 3923 /* 3924 * If the “enable VPID†VM-execution control is 1, the value of the 3925 * of the VPID VM-execution control field must not be 0000H. 3926 * [Intel SDM] 3927 */ 3928 static void test_vpid(void) 3929 { 3930 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3931 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3932 u16 vpid = 0x0000; 3933 int i; 3934 3935 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 3936 (ctrl_cpu_rev[1].clr & CPU_VPID))) { 3937 test_skip("Secondary controls and/or VPID not supported"); 3938 return; 3939 } 3940 3941 vmcs_write(CPU_EXEC_CTRL0, saved_primary | CPU_SECONDARY); 3942 vmcs_write(CPU_EXEC_CTRL1, saved_secondary & ~CPU_VPID); 3943 vmcs_write(VPID, vpid); 3944 report_prefix_pushf("VPID disabled; VPID value %x", vpid); 3945 test_vmx_controls(true, false); 3946 report_prefix_pop(); 3947 3948 vmcs_write(CPU_EXEC_CTRL1, saved_secondary | CPU_VPID); 3949 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 3950 test_vmx_controls(false, false); 3951 report_prefix_pop(); 3952 3953 for (i = 0; i < 16; i++) { 3954 vpid = (short)1 << i;; 3955 vmcs_write(VPID, vpid); 3956 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 3957 test_vmx_controls(true, false); 3958 report_prefix_pop(); 3959 } 3960 3961 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3962 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3963 } 3964 3965 static void set_vtpr(unsigned vtpr) 3966 { 3967 *(u32 *)phys_to_virt(vmcs_read(APIC_VIRT_ADDR) + APIC_TASKPRI) = vtpr; 3968 } 3969 3970 static void try_tpr_threshold_and_vtpr(unsigned threshold, unsigned vtpr) 3971 { 3972 bool valid = true; 3973 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 3974 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 3975 3976 if ((primary & CPU_TPR_SHADOW) && 3977 (!(primary & CPU_SECONDARY) || 3978 !(secondary & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 3979 valid = (threshold & 0xf) <= ((vtpr >> 4) & 0xf); 3980 3981 set_vtpr(vtpr); 3982 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0x%x", 3983 threshold, (vtpr >> 4) & 0xf); 3984 test_vmx_controls(valid, false); 3985 report_prefix_pop(); 3986 } 3987 3988 static void test_invalid_event_injection(void) 3989 { 3990 u32 ent_intr_info_save = vmcs_read(ENT_INTR_INFO); 3991 u32 ent_intr_error_save = vmcs_read(ENT_INTR_ERROR); 3992 u32 ent_inst_len_save = vmcs_read(ENT_INST_LEN); 3993 u32 primary_save = vmcs_read(CPU_EXEC_CTRL0); 3994 u32 secondary_save = vmcs_read(CPU_EXEC_CTRL1); 3995 u64 guest_cr0_save = vmcs_read(GUEST_CR0); 3996 u32 ent_intr_info_base = INTR_INFO_VALID_MASK; 3997 u32 ent_intr_info, ent_intr_err, ent_intr_len; 3998 u32 cnt; 3999 4000 /* Setup */ 4001 report_prefix_push("invalid event injection"); 4002 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4003 vmcs_write(ENT_INST_LEN, 0x00000001); 4004 4005 /* The field’s interruption type is not set to a reserved value. */ 4006 ent_intr_info = ent_intr_info_base | INTR_TYPE_RESERVED | DE_VECTOR; 4007 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4008 "RESERVED interruption type invalid [-]", 4009 ent_intr_info); 4010 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4011 test_vmx_controls(false, false); 4012 report_prefix_pop(); 4013 4014 ent_intr_info = ent_intr_info_base | INTR_TYPE_EXT_INTR | 4015 DE_VECTOR; 4016 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4017 "RESERVED interruption type invalid [+]", 4018 ent_intr_info); 4019 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4020 test_vmx_controls(true, false); 4021 report_prefix_pop(); 4022 4023 /* If the interruption type is other event, the vector is 0. */ 4024 ent_intr_info = ent_intr_info_base | INTR_TYPE_OTHER_EVENT | DB_VECTOR; 4025 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4026 "(OTHER EVENT && vector != 0) invalid [-]", 4027 ent_intr_info); 4028 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4029 test_vmx_controls(false, false); 4030 report_prefix_pop(); 4031 4032 /* If the interruption type is NMI, the vector is 2 (negative case). */ 4033 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | DE_VECTOR; 4034 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4035 "(NMI && vector != 2) invalid [-]", ent_intr_info); 4036 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4037 test_vmx_controls(false, false); 4038 report_prefix_pop(); 4039 4040 /* If the interruption type is NMI, the vector is 2 (positive case). */ 4041 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | NMI_VECTOR; 4042 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4043 "(NMI && vector == 2) valid [+]", ent_intr_info); 4044 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4045 test_vmx_controls(true, false); 4046 report_prefix_pop(); 4047 4048 /* 4049 * If the interruption type 4050 * is HW exception, the vector is at most 31. 4051 */ 4052 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 0x20; 4053 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4054 "(HW exception && vector > 31) invalid [-]", 4055 ent_intr_info); 4056 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4057 test_vmx_controls(false, false); 4058 report_prefix_pop(); 4059 4060 /* 4061 * deliver-error-code is 1 iff either 4062 * (a) the "unrestricted guest" VM-execution control is 0 4063 * (b) CR0.PE is set. 4064 */ 4065 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4066 GP_VECTOR; 4067 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4068 "error code <-> (!URG || prot_mode) [-]", 4069 ent_intr_info); 4070 disable_unrestricted_guest(); 4071 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4072 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4073 test_vmx_controls(false, false); 4074 report_prefix_pop(); 4075 4076 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4077 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4078 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4079 "error code <-> (!URG || prot_mode) [+]", 4080 ent_intr_info); 4081 disable_unrestricted_guest(); 4082 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4083 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4084 test_vmx_controls(true, false); 4085 report_prefix_pop(); 4086 4087 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4088 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4089 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4090 "error code <-> (!URG || prot_mode) [-]", 4091 ent_intr_info); 4092 enable_unrestricted_guest(); 4093 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4094 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4095 test_vmx_controls(false, false); 4096 report_prefix_pop(); 4097 4098 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4099 GP_VECTOR; 4100 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4101 "error code <-> (!URG || prot_mode) [-]", 4102 ent_intr_info); 4103 vmcs_write(GUEST_CR0, guest_cr0_save | X86_CR0_PE); 4104 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4105 test_vmx_controls(false, false); 4106 report_prefix_pop(); 4107 4108 /* deliver-error-code is 1 iff the interruption type is HW exception */ 4109 report_prefix_push("error code <-> HW exception"); 4110 for (cnt = 0; cnt < 8; cnt++) { 4111 u32 exception_type_mask = cnt << 8; 4112 u32 deliver_error_code_mask = 4113 exception_type_mask != INTR_TYPE_HARD_EXCEPTION ? 4114 INTR_INFO_DELIVER_CODE_MASK : 0; 4115 4116 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4117 exception_type_mask | GP_VECTOR; 4118 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4119 ent_intr_info); 4120 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4121 test_vmx_controls(false, false); 4122 report_prefix_pop(); 4123 } 4124 report_prefix_pop(); 4125 4126 /* 4127 * deliver-error-code is 1 iff the the vector 4128 * indicates an exception that would normally deliver an error code 4129 */ 4130 report_prefix_push("error code <-> vector delivers error code"); 4131 for (cnt = 0; cnt < 32; cnt++) { 4132 bool has_error_code = false; 4133 u32 deliver_error_code_mask; 4134 4135 switch (cnt) { 4136 case DF_VECTOR: 4137 case TS_VECTOR: 4138 case NP_VECTOR: 4139 case SS_VECTOR: 4140 case GP_VECTOR: 4141 case PF_VECTOR: 4142 case AC_VECTOR: 4143 has_error_code = true; 4144 } 4145 4146 /* Negative case */ 4147 deliver_error_code_mask = has_error_code ? 4148 0 : 4149 INTR_INFO_DELIVER_CODE_MASK; 4150 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4151 INTR_TYPE_HARD_EXCEPTION | cnt; 4152 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4153 ent_intr_info); 4154 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4155 test_vmx_controls(false, false); 4156 report_prefix_pop(); 4157 4158 /* Positive case */ 4159 deliver_error_code_mask = has_error_code ? 4160 INTR_INFO_DELIVER_CODE_MASK : 4161 0; 4162 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4163 INTR_TYPE_HARD_EXCEPTION | cnt; 4164 report_prefix_pushf("VM-entry intr info=0x%x [+]", 4165 ent_intr_info); 4166 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4167 test_vmx_controls(true, false); 4168 report_prefix_pop(); 4169 } 4170 report_prefix_pop(); 4171 4172 /* Reserved bits in the field (30:12) are 0. */ 4173 report_prefix_push("reserved bits clear"); 4174 for (cnt = 12; cnt <= 30; cnt++) { 4175 ent_intr_info = ent_intr_info_base | 4176 INTR_INFO_DELIVER_CODE_MASK | 4177 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR | 4178 (1U << cnt); 4179 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4180 ent_intr_info); 4181 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4182 test_vmx_controls(false, false); 4183 report_prefix_pop(); 4184 } 4185 report_prefix_pop(); 4186 4187 /* 4188 * If deliver-error-code is 1 4189 * bits 31:15 of the VM-entry exception error-code field are 0. 4190 */ 4191 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4192 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4193 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4194 "VM-entry exception error code[31:15] clear", 4195 ent_intr_info); 4196 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4197 for (cnt = 15; cnt <= 31; cnt++) { 4198 ent_intr_err = 1U << cnt; 4199 report_prefix_pushf("VM-entry intr error=0x%x [-]", 4200 ent_intr_err); 4201 vmcs_write(ENT_INTR_ERROR, ent_intr_err); 4202 test_vmx_controls(false, false); 4203 report_prefix_pop(); 4204 } 4205 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4206 report_prefix_pop(); 4207 4208 /* 4209 * If the interruption type is software interrupt, software exception, 4210 * or privileged software exception, the VM-entry instruction-length 4211 * field is in the range 0–15. 4212 */ 4213 4214 for (cnt = 0; cnt < 3; cnt++) { 4215 switch (cnt) { 4216 case 0: 4217 ent_intr_info = ent_intr_info_base | 4218 INTR_TYPE_SOFT_INTR; 4219 break; 4220 case 1: 4221 ent_intr_info = ent_intr_info_base | 4222 INTR_TYPE_SOFT_EXCEPTION; 4223 break; 4224 case 2: 4225 ent_intr_info = ent_intr_info_base | 4226 INTR_TYPE_PRIV_SW_EXCEPTION; 4227 break; 4228 } 4229 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4230 "VM-entry instruction-length check", 4231 ent_intr_info); 4232 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4233 4234 /* Instruction length set to -1 (0xFFFFFFFF) should fail */ 4235 ent_intr_len = -1; 4236 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4237 ent_intr_len); 4238 vmcs_write(ENT_INST_LEN, ent_intr_len); 4239 test_vmx_controls(false, false); 4240 report_prefix_pop(); 4241 4242 /* Instruction length set to 16 should fail */ 4243 ent_intr_len = 0x00000010; 4244 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4245 ent_intr_len); 4246 vmcs_write(ENT_INST_LEN, 0x00000010); 4247 test_vmx_controls(false, false); 4248 report_prefix_pop(); 4249 4250 report_prefix_pop(); 4251 } 4252 4253 /* Cleanup */ 4254 vmcs_write(ENT_INTR_INFO, ent_intr_info_save); 4255 vmcs_write(ENT_INTR_ERROR, ent_intr_error_save); 4256 vmcs_write(ENT_INST_LEN, ent_inst_len_save); 4257 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4258 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4259 vmcs_write(GUEST_CR0, guest_cr0_save); 4260 report_prefix_pop(); 4261 } 4262 4263 /* 4264 * Test interesting vTPR values for a given TPR threshold. 4265 */ 4266 static void test_vtpr_values(unsigned threshold) 4267 { 4268 try_tpr_threshold_and_vtpr(threshold, (threshold - 1) << 4); 4269 try_tpr_threshold_and_vtpr(threshold, threshold << 4); 4270 try_tpr_threshold_and_vtpr(threshold, (threshold + 1) << 4); 4271 } 4272 4273 static void try_tpr_threshold(unsigned threshold) 4274 { 4275 bool valid = true; 4276 4277 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4278 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4279 4280 if ((primary & CPU_TPR_SHADOW) && !((primary & CPU_SECONDARY) && 4281 (secondary & CPU_VINTD))) 4282 valid = !(threshold >> 4); 4283 4284 set_vtpr(-1); 4285 vmcs_write(TPR_THRESHOLD, threshold); 4286 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0xf", threshold); 4287 test_vmx_controls(valid, false); 4288 report_prefix_pop(); 4289 4290 if (valid) 4291 test_vtpr_values(threshold); 4292 } 4293 4294 /* 4295 * Test interesting TPR threshold values. 4296 */ 4297 static void test_tpr_threshold_values(void) 4298 { 4299 unsigned i; 4300 4301 for (i = 0; i < 0x10; i++) 4302 try_tpr_threshold(i); 4303 for (i = 4; i < 32; i++) 4304 try_tpr_threshold(1u << i); 4305 try_tpr_threshold(-1u); 4306 try_tpr_threshold(0x7fffffff); 4307 } 4308 4309 /* 4310 * This test covers the following two VM entry checks: 4311 * 4312 * i) If the "use TPR shadow" VM-execution control is 1 and the 4313 * "virtual-interrupt delivery" VM-execution control is 0, bits 4314 * 31:4 of the TPR threshold VM-execution control field must 4315 be 0. 4316 * [Intel SDM] 4317 * 4318 * ii) If the "use TPR shadow" VM-execution control is 1, the 4319 * "virtual-interrupt delivery" VM-execution control is 0 4320 * and the "virtualize APIC accesses" VM-execution control 4321 * is 0, the value of bits 3:0 of the TPR threshold VM-execution 4322 * control field must not be greater than the value of bits 4323 * 7:4 of VTPR. 4324 * [Intel SDM] 4325 */ 4326 static void test_tpr_threshold(void) 4327 { 4328 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4329 void *virtual_apic_page; 4330 4331 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) 4332 return; 4333 4334 virtual_apic_page = alloc_page(); 4335 memset(virtual_apic_page, 0xff, PAGE_SIZE); 4336 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 4337 4338 vmcs_write(CPU_EXEC_CTRL0, primary & ~(CPU_TPR_SHADOW | CPU_SECONDARY)); 4339 report_prefix_pushf("Use TPR shadow disabled, secondary controls disabled"); 4340 test_tpr_threshold_values(); 4341 report_prefix_pop(); 4342 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_TPR_SHADOW); 4343 report_prefix_pushf("Use TPR shadow enabled, secondary controls disabled"); 4344 test_tpr_threshold_values(); 4345 report_prefix_pop(); 4346 4347 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4348 (ctrl_cpu_rev[1].clr & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) { 4349 vmcs_write(CPU_EXEC_CTRL0, primary); 4350 return; 4351 } 4352 4353 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4354 4355 if (ctrl_cpu_rev[1].clr & CPU_VINTD) { 4356 vmcs_write(CPU_EXEC_CTRL1, CPU_VINTD); 4357 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4358 test_tpr_threshold_values(); 4359 report_prefix_pop(); 4360 4361 vmcs_write(CPU_EXEC_CTRL0, 4362 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4363 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4364 test_tpr_threshold_values(); 4365 report_prefix_pop(); 4366 } 4367 4368 if (ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES) { 4369 vmcs_write(CPU_EXEC_CTRL0, 4370 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4371 vmcs_write(CPU_EXEC_CTRL1, CPU_VIRT_APIC_ACCESSES); 4372 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4373 test_tpr_threshold_values(); 4374 report_prefix_pop(); 4375 4376 vmcs_write(CPU_EXEC_CTRL0, 4377 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4378 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4379 test_tpr_threshold_values(); 4380 report_prefix_pop(); 4381 } 4382 4383 if ((ctrl_cpu_rev[1].clr & 4384 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) == 4385 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) { 4386 vmcs_write(CPU_EXEC_CTRL0, 4387 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4388 vmcs_write(CPU_EXEC_CTRL1, 4389 CPU_VINTD | CPU_VIRT_APIC_ACCESSES); 4390 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4391 test_tpr_threshold_values(); 4392 report_prefix_pop(); 4393 4394 vmcs_write(CPU_EXEC_CTRL0, 4395 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4396 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4397 test_tpr_threshold_values(); 4398 report_prefix_pop(); 4399 } 4400 4401 vmcs_write(CPU_EXEC_CTRL1, secondary); 4402 vmcs_write(CPU_EXEC_CTRL0, primary); 4403 } 4404 4405 /* 4406 * This test verifies the following two vmentry checks: 4407 * 4408 * If the "NMI exiting" VM-execution control is 0, "Virtual NMIs" 4409 * VM-execution control must be 0. 4410 * [Intel SDM] 4411 * 4412 * If the “virtual NMIs” VM-execution control is 0, the “NMI-window 4413 * exiting” VM-execution control must be 0. 4414 * [Intel SDM] 4415 */ 4416 static void test_nmi_ctrls(void) 4417 { 4418 u32 pin_ctrls, cpu_ctrls0, test_pin_ctrls, test_cpu_ctrls0; 4419 4420 if ((ctrl_pin_rev.clr & (PIN_NMI | PIN_VIRT_NMI)) != 4421 (PIN_NMI | PIN_VIRT_NMI)) { 4422 test_skip("NMI exiting and Virtual NMIs are not supported !"); 4423 return; 4424 } 4425 4426 /* Save the controls so that we can restore them after our tests */ 4427 pin_ctrls = vmcs_read(PIN_CONTROLS); 4428 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 4429 4430 test_pin_ctrls = pin_ctrls & ~(PIN_NMI | PIN_VIRT_NMI); 4431 test_cpu_ctrls0 = cpu_ctrls0 & ~CPU_NMI_WINDOW; 4432 4433 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4434 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs disabled"); 4435 test_vmx_controls(true, false); 4436 report_prefix_pop(); 4437 4438 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_VIRT_NMI); 4439 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs enabled"); 4440 test_vmx_controls(false, false); 4441 report_prefix_pop(); 4442 4443 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4444 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs enabled"); 4445 test_vmx_controls(true, false); 4446 report_prefix_pop(); 4447 4448 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_NMI); 4449 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs disabled"); 4450 test_vmx_controls(true, false); 4451 report_prefix_pop(); 4452 4453 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 4454 report_info("NMI-window exiting is not supported, skipping..."); 4455 goto done; 4456 } 4457 4458 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4459 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4460 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting enabled"); 4461 test_vmx_controls(false, false); 4462 report_prefix_pop(); 4463 4464 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4465 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4466 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting disabled"); 4467 test_vmx_controls(true, false); 4468 report_prefix_pop(); 4469 4470 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4471 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4472 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting enabled"); 4473 test_vmx_controls(true, false); 4474 report_prefix_pop(); 4475 4476 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4477 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4478 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting disabled"); 4479 test_vmx_controls(true, false); 4480 report_prefix_pop(); 4481 4482 /* Restore the controls to their original values */ 4483 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 4484 done: 4485 vmcs_write(PIN_CONTROLS, pin_ctrls); 4486 } 4487 4488 static void test_eptp_ad_bit(u64 eptp, bool ctrl) 4489 { 4490 vmcs_write(EPTP, eptp); 4491 report_prefix_pushf("Enable-EPT enabled; EPT accessed and dirty flag %s", 4492 (eptp & EPTP_AD_FLAG) ? "1": "0"); 4493 test_vmx_controls(ctrl, false); 4494 report_prefix_pop(); 4495 4496 } 4497 /* 4498 * If the “enable EPT†VM-execution control is 1, the EPTP VM-execution 4499 * control field must satisfy the following checks: 4500 * 4501 * — The EPT memory type (bits 2:0) must be a value supported by the 4502 * processor as indicated in the IA32_VMX_EPT_VPID_CAP MSR. 4503 * — Bits 5:3 (1 less than the EPT page-walk length) must be 3, 4504 * indicating an EPT page-walk length of 4. 4505 * — Bit 6 (enable bit for accessed and dirty flags for EPT) must be 4506 * 0 if bit 21 of the IA32_VMX_EPT_VPID_CAP MSR is read as 0, 4507 * indicating that the processor does not support accessed and dirty 4508 * dirty flags for EPT. 4509 * — Reserved bits 11:7 and 63:N (where N is the processor’s 4510 * physical-address width) must all be 0. 4511 * 4512 * [Intel SDM] 4513 */ 4514 static void test_eptp(void) 4515 { 4516 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4517 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4518 u64 eptp_saved = vmcs_read(EPTP); 4519 u32 primary = primary_saved; 4520 u32 secondary = secondary_saved; 4521 u64 msr, eptp = eptp_saved; 4522 bool un_cache = false; 4523 bool wr_bk = false; 4524 bool ctrl; 4525 u32 i, maxphysaddr; 4526 u64 j, resv_bits_mask = 0; 4527 4528 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4529 (ctrl_cpu_rev[1].clr & CPU_EPT))) { 4530 test_skip("\"CPU secondary\" and/or \"enable EPT\" execution controls are not supported !"); 4531 return; 4532 } 4533 4534 /* 4535 * Memory type (bits 2:0) 4536 */ 4537 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 4538 if (msr & EPT_CAP_UC) 4539 un_cache = true; 4540 if (msr & EPT_CAP_WB) 4541 wr_bk = true; 4542 4543 primary |= CPU_SECONDARY; 4544 vmcs_write(CPU_EXEC_CTRL0, primary); 4545 secondary |= CPU_EPT; 4546 vmcs_write(CPU_EXEC_CTRL1, secondary); 4547 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4548 (3ul << EPTP_PG_WALK_LEN_SHIFT); 4549 vmcs_write(EPTP, eptp); 4550 4551 for (i = 0; i < 8; i++) { 4552 if (i == 0) { 4553 if (un_cache) { 4554 report_info("EPT paging structure memory-type is Un-cacheable\n"); 4555 ctrl = true; 4556 } else { 4557 ctrl = false; 4558 } 4559 } else if (i == 6) { 4560 if (wr_bk) { 4561 report_info("EPT paging structure memory-type is Write-back\n"); 4562 ctrl = true; 4563 } else { 4564 ctrl = false; 4565 } 4566 } else { 4567 ctrl = false; 4568 } 4569 4570 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | i; 4571 vmcs_write(EPTP, eptp); 4572 report_prefix_pushf("Enable-EPT enabled; EPT memory type %lu", 4573 eptp & EPT_MEM_TYPE_MASK); 4574 test_vmx_controls(ctrl, false); 4575 report_prefix_pop(); 4576 } 4577 4578 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | 6ul; 4579 4580 /* 4581 * Page walk length (bits 5:3) 4582 */ 4583 for (i = 0; i < 8; i++) { 4584 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4585 (i << EPTP_PG_WALK_LEN_SHIFT); 4586 if (i == 3) 4587 ctrl = true; 4588 else 4589 ctrl = false; 4590 4591 vmcs_write(EPTP, eptp); 4592 report_prefix_pushf("Enable-EPT enabled; EPT page walk length %lu", 4593 eptp & EPTP_PG_WALK_LEN_MASK); 4594 test_vmx_controls(ctrl, false); 4595 report_prefix_pop(); 4596 } 4597 4598 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4599 3ul << EPTP_PG_WALK_LEN_SHIFT; 4600 4601 /* 4602 * Accessed and dirty flag (bit 6) 4603 */ 4604 if (msr & EPT_CAP_AD_FLAG) { 4605 report_info("Processor supports accessed and dirty flag"); 4606 eptp &= ~EPTP_AD_FLAG; 4607 test_eptp_ad_bit(eptp, true); 4608 4609 eptp |= EPTP_AD_FLAG; 4610 test_eptp_ad_bit(eptp, true); 4611 } else { 4612 report_info("Processor does not supports accessed and dirty flag"); 4613 eptp &= ~EPTP_AD_FLAG; 4614 test_eptp_ad_bit(eptp, true); 4615 4616 eptp |= EPTP_AD_FLAG; 4617 test_eptp_ad_bit(eptp, false); 4618 } 4619 4620 /* 4621 * Reserved bits [11:7] and [63:N] 4622 */ 4623 for (i = 0; i < 32; i++) { 4624 if (i == 0) 4625 ctrl = true; 4626 else 4627 ctrl = false; 4628 4629 eptp = (eptp & 4630 ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)) | 4631 (i << EPTP_RESERV_BITS_SHIFT); 4632 vmcs_write(EPTP, eptp); 4633 report_prefix_pushf("Enable-EPT enabled; reserved bits [11:7] %lu", 4634 (eptp >> EPTP_RESERV_BITS_SHIFT) & 4635 EPTP_RESERV_BITS_MASK); 4636 test_vmx_controls(ctrl, false); 4637 report_prefix_pop(); 4638 } 4639 4640 eptp = (eptp & ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)); 4641 4642 maxphysaddr = cpuid_maxphyaddr(); 4643 for (i = 0; i < (63 - maxphysaddr + 1); i++) { 4644 resv_bits_mask |= 1ul << i; 4645 } 4646 4647 for (j = 0; j < (63 - maxphysaddr + 1); j++) { 4648 if (j == 0) 4649 ctrl = true; 4650 else 4651 ctrl = false; 4652 4653 eptp = (eptp & ~(resv_bits_mask << maxphysaddr)) | 4654 (j << maxphysaddr); 4655 vmcs_write(EPTP, eptp); 4656 report_prefix_pushf("Enable-EPT enabled; reserved bits [63:N] %lu", 4657 (eptp >> maxphysaddr) & resv_bits_mask); 4658 test_vmx_controls(ctrl, false); 4659 report_prefix_pop(); 4660 } 4661 4662 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4663 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4664 vmcs_write(EPTP, eptp_saved); 4665 } 4666 4667 /* 4668 * If the 'enable PML' VM-execution control is 1, the 'enable EPT' 4669 * VM-execution control must also be 1. In addition, the PML address 4670 * must satisfy the following checks: 4671 * 4672 * * Bits 11:0 of the address must be 0. 4673 * * The address should not set any bits beyond the processor's 4674 * physical-address width. 4675 * 4676 * [Intel SDM] 4677 */ 4678 static void test_pml(void) 4679 { 4680 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4681 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4682 u32 primary = primary_saved; 4683 u32 secondary = secondary_saved; 4684 4685 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4686 (ctrl_cpu_rev[1].clr & CPU_EPT) && (ctrl_cpu_rev[1].clr & CPU_PML))) { 4687 test_skip("\"Secondary execution\" control or \"enable EPT\" control or \"enable PML\" control is not supported !"); 4688 return; 4689 } 4690 4691 primary |= CPU_SECONDARY; 4692 vmcs_write(CPU_EXEC_CTRL0, primary); 4693 secondary &= ~(CPU_PML | CPU_EPT); 4694 vmcs_write(CPU_EXEC_CTRL1, secondary); 4695 report_prefix_pushf("enable-PML disabled, enable-EPT disabled"); 4696 test_vmx_controls(true, false); 4697 report_prefix_pop(); 4698 4699 secondary |= CPU_PML; 4700 vmcs_write(CPU_EXEC_CTRL1, secondary); 4701 report_prefix_pushf("enable-PML enabled, enable-EPT disabled"); 4702 test_vmx_controls(false, false); 4703 report_prefix_pop(); 4704 4705 secondary |= CPU_EPT; 4706 vmcs_write(CPU_EXEC_CTRL1, secondary); 4707 report_prefix_pushf("enable-PML enabled, enable-EPT enabled"); 4708 test_vmx_controls(true, false); 4709 report_prefix_pop(); 4710 4711 secondary &= ~CPU_PML; 4712 vmcs_write(CPU_EXEC_CTRL1, secondary); 4713 report_prefix_pushf("enable-PML disabled, enable EPT enabled"); 4714 test_vmx_controls(true, false); 4715 report_prefix_pop(); 4716 4717 test_vmcs_page_reference(CPU_PML, PMLADDR, "PML address", 4718 "PML", false, false); 4719 4720 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4721 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4722 } 4723 4724 /* 4725 * Check that the virtual CPU checks all of the VMX controls as 4726 * documented in the Intel SDM. 4727 */ 4728 static void vmx_controls_test(void) 4729 { 4730 /* 4731 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 4732 * fail due to invalid guest state, should we make it that 4733 * far. 4734 */ 4735 vmcs_write(GUEST_RFLAGS, 0); 4736 4737 test_pin_based_ctls(); 4738 test_primary_processor_based_ctls(); 4739 test_secondary_processor_based_ctls(); 4740 test_cr3_targets(); 4741 test_io_bitmaps(); 4742 test_msr_bitmap(); 4743 test_apic_ctls(); 4744 test_tpr_threshold(); 4745 test_nmi_ctrls(); 4746 test_pml(); 4747 test_invalid_event_injection(); 4748 test_vpid(); 4749 test_eptp(); 4750 } 4751 4752 static bool valid_vmcs_for_vmentry(void) 4753 { 4754 struct vmcs *current_vmcs = NULL; 4755 4756 if (vmcs_save(¤t_vmcs)) 4757 return false; 4758 4759 return current_vmcs && !current_vmcs->hdr.shadow_vmcs; 4760 } 4761 4762 static void try_vmentry_in_movss_shadow(void) 4763 { 4764 u32 vm_inst_err; 4765 u32 flags; 4766 bool early_failure = false; 4767 u32 expected_flags = X86_EFLAGS_FIXED; 4768 bool valid_vmcs = valid_vmcs_for_vmentry(); 4769 4770 expected_flags |= valid_vmcs ? X86_EFLAGS_ZF : X86_EFLAGS_CF; 4771 4772 /* 4773 * Indirectly set VM_INST_ERR to 12 ("VMREAD/VMWRITE from/to 4774 * unsupported VMCS component"). 4775 */ 4776 vmcs_write(~0u, 0); 4777 4778 __asm__ __volatile__ ("mov %[host_rsp], %%edx;" 4779 "vmwrite %%rsp, %%rdx;" 4780 "mov 0f, %%rax;" 4781 "mov %[host_rip], %%edx;" 4782 "vmwrite %%rax, %%rdx;" 4783 "mov $-1, %%ah;" 4784 "sahf;" 4785 "mov %%ss, %%ax;" 4786 "mov %%ax, %%ss;" 4787 "vmlaunch;" 4788 "mov $1, %[early_failure];" 4789 "0: lahf;" 4790 "movzbl %%ah, %[flags]" 4791 : [early_failure] "+r" (early_failure), 4792 [flags] "=&a" (flags) 4793 : [host_rsp] "i" (HOST_RSP), 4794 [host_rip] "i" (HOST_RIP) 4795 : "rdx", "cc", "memory"); 4796 vm_inst_err = vmcs_read(VMX_INST_ERROR); 4797 4798 report("Early VM-entry failure", early_failure); 4799 report("RFLAGS[8:0] is %x (actual %x)", flags == expected_flags, 4800 expected_flags, flags); 4801 if (valid_vmcs) 4802 report("VM-instruction error is %d (actual %d)", 4803 vm_inst_err == VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, 4804 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, vm_inst_err); 4805 } 4806 4807 static void vmentry_movss_shadow_test(void) 4808 { 4809 struct vmcs *orig_vmcs; 4810 4811 TEST_ASSERT(!vmcs_save(&orig_vmcs)); 4812 4813 /* 4814 * Set the launched flag on the current VMCS to verify the correct 4815 * error priority, below. 4816 */ 4817 test_set_guest(v2_null_test_guest); 4818 enter_guest(); 4819 4820 /* 4821 * With bit 1 of the guest's RFLAGS clear, VM-entry should 4822 * fail due to invalid guest state (if we make it that far). 4823 */ 4824 vmcs_write(GUEST_RFLAGS, 0); 4825 4826 /* 4827 * "VM entry with events blocked by MOV SS" takes precedence over 4828 * "VMLAUNCH with non-clear VMCS." 4829 */ 4830 report_prefix_push("valid current-VMCS"); 4831 try_vmentry_in_movss_shadow(); 4832 report_prefix_pop(); 4833 4834 /* 4835 * VMfailInvalid takes precedence over "VM entry with events 4836 * blocked by MOV SS." 4837 */ 4838 TEST_ASSERT(!vmcs_clear(orig_vmcs)); 4839 report_prefix_push("no current-VMCS"); 4840 try_vmentry_in_movss_shadow(); 4841 report_prefix_pop(); 4842 4843 TEST_ASSERT(!make_vmcs_current(orig_vmcs)); 4844 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 4845 } 4846 4847 #define X86_FEATURE_PCID (1 << 17) 4848 #define X86_FEATURE_MCE (1 << 7) 4849 4850 static int write_cr4_checking(unsigned long val) 4851 { 4852 asm volatile(ASM_TRY("1f") 4853 "mov %0, %%cr4\n\t" 4854 "1:": : "r" (val)); 4855 return exception_vector(); 4856 } 4857 4858 static void vmx_cr_load_test(void) 4859 { 4860 struct cpuid _cpuid = cpuid(1); 4861 unsigned long cr4 = read_cr4(), cr3 = read_cr3(); 4862 4863 if (!(_cpuid.c & X86_FEATURE_PCID)) { 4864 report_skip("PCID not detected"); 4865 return; 4866 } 4867 if (!(_cpuid.d & X86_FEATURE_MCE)) { 4868 report_skip("MCE not detected"); 4869 return; 4870 } 4871 4872 TEST_ASSERT(!(cr4 & (X86_CR4_PCIDE | X86_CR4_MCE))); 4873 TEST_ASSERT(!(cr3 & X86_CR3_PCID_MASK)); 4874 4875 /* Enable PCID for L1. */ 4876 cr4 |= X86_CR4_PCIDE; 4877 cr3 |= 0x1; 4878 TEST_ASSERT(!write_cr4_checking(cr4)); 4879 write_cr3(cr3); 4880 4881 test_set_guest(v2_null_test_guest); 4882 vmcs_write(HOST_CR4, cr4); 4883 vmcs_write(HOST_CR3, cr3); 4884 enter_guest(); 4885 4886 /* 4887 * No exception is expected. 4888 * 4889 * NB. KVM loads the last guest write to CR4 into CR4 read 4890 * shadow. In order to trigger an exit to KVM, we can set a 4891 * bit that was zero in the above CR4 write and is owned by 4892 * KVM. We choose to set CR4.MCE, which shall have no side 4893 * effect because normally no guest MCE (e.g., as the result 4894 * of bad memory) would happen during this test. 4895 */ 4896 TEST_ASSERT(!write_cr4_checking(cr4 | X86_CR4_MCE)); 4897 4898 /* Cleanup L1 state: disable PCID. */ 4899 write_cr3(cr3 & ~X86_CR3_PCID_MASK); 4900 TEST_ASSERT(!write_cr4_checking(cr4 & ~X86_CR4_PCIDE)); 4901 } 4902 4903 static void vmx_nm_test_guest(void) 4904 { 4905 write_cr0(read_cr0() | X86_CR0_TS); 4906 asm volatile("fnop"); 4907 } 4908 4909 static void check_nm_exit(const char *test) 4910 { 4911 u32 reason = vmcs_read(EXI_REASON); 4912 u32 intr_info = vmcs_read(EXI_INTR_INFO); 4913 const u32 expected = INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 4914 NM_VECTOR; 4915 4916 report("%s", reason == VMX_EXC_NMI && intr_info == expected, test); 4917 } 4918 4919 /* 4920 * This test checks that: 4921 * 4922 * (a) If L2 launches with CR0.TS clear, but later sets CR0.TS, then 4923 * a subsequent #NM VM-exit is reflected to L1. 4924 * 4925 * (b) If L2 launches with CR0.TS clear and CR0.EM set, then a 4926 * subsequent #NM VM-exit is reflected to L1. 4927 */ 4928 static void vmx_nm_test(void) 4929 { 4930 unsigned long cr0 = read_cr0(); 4931 4932 test_set_guest(vmx_nm_test_guest); 4933 4934 /* 4935 * L1 wants to intercept #NM exceptions encountered in L2. 4936 */ 4937 vmcs_write(EXC_BITMAP, 1 << NM_VECTOR); 4938 4939 /* 4940 * Launch L2 with CR0.TS clear, but don't claim host ownership of 4941 * any CR0 bits. L2 will set CR0.TS and then try to execute fnop, 4942 * which will raise #NM. L0 should reflect the #NM VM-exit to L1. 4943 */ 4944 vmcs_write(CR0_MASK, 0); 4945 vmcs_write(GUEST_CR0, cr0 & ~X86_CR0_TS); 4946 enter_guest(); 4947 check_nm_exit("fnop with CR0.TS set in L2 triggers #NM VM-exit to L1"); 4948 4949 /* 4950 * Re-enter L2 at the fnop instruction, with CR0.TS clear but 4951 * CR0.EM set. The fnop will still raise #NM, and L0 should 4952 * reflect the #NM VM-exit to L1. 4953 */ 4954 vmcs_write(GUEST_CR0, (cr0 & ~X86_CR0_TS) | X86_CR0_EM); 4955 enter_guest(); 4956 check_nm_exit("fnop with CR0.EM set in L2 triggers #NM VM-exit to L1"); 4957 4958 /* 4959 * Re-enter L2 at the fnop instruction, with both CR0.TS and 4960 * CR0.EM clear. There will be no #NM, and the L2 guest should 4961 * exit normally. 4962 */ 4963 vmcs_write(GUEST_CR0, cr0 & ~(X86_CR0_TS | X86_CR0_EM)); 4964 enter_guest(); 4965 } 4966 4967 bool vmx_pending_event_ipi_fired; 4968 static void vmx_pending_event_ipi_isr(isr_regs_t *regs) 4969 { 4970 vmx_pending_event_ipi_fired = true; 4971 eoi(); 4972 } 4973 4974 bool vmx_pending_event_guest_run; 4975 static void vmx_pending_event_guest(void) 4976 { 4977 vmcall(); 4978 vmx_pending_event_guest_run = true; 4979 } 4980 4981 static void vmx_pending_event_test_core(bool guest_hlt) 4982 { 4983 int ipi_vector = 0xf1; 4984 4985 vmx_pending_event_ipi_fired = false; 4986 handle_irq(ipi_vector, vmx_pending_event_ipi_isr); 4987 4988 vmx_pending_event_guest_run = false; 4989 test_set_guest(vmx_pending_event_guest); 4990 4991 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 4992 4993 enter_guest(); 4994 skip_exit_vmcall(); 4995 4996 if (guest_hlt) 4997 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 4998 4999 irq_disable(); 5000 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | 5001 APIC_DM_FIXED | ipi_vector, 5002 0); 5003 5004 enter_guest(); 5005 5006 assert_exit_reason(VMX_EXTINT); 5007 report("Guest did not run before host received IPI", 5008 !vmx_pending_event_guest_run); 5009 5010 irq_enable(); 5011 asm volatile ("nop"); 5012 irq_disable(); 5013 report("Got pending interrupt after IRQ enabled", 5014 vmx_pending_event_ipi_fired); 5015 5016 if (guest_hlt) 5017 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 5018 5019 enter_guest(); 5020 report("Guest finished running when no interrupt", 5021 vmx_pending_event_guest_run); 5022 } 5023 5024 static void vmx_pending_event_test(void) 5025 { 5026 vmx_pending_event_test_core(false); 5027 } 5028 5029 static void vmx_pending_event_hlt_test(void) 5030 { 5031 vmx_pending_event_test_core(true); 5032 } 5033 5034 static void vmx_db_test_guest(void) 5035 { 5036 /* 5037 * For a hardware generated single-step #DB. 5038 */ 5039 asm volatile("vmcall;" 5040 "nop;" 5041 ".Lpost_nop:"); 5042 /* 5043 * ...in a MOVSS shadow, with pending debug exceptions. 5044 */ 5045 asm volatile("vmcall;" 5046 "nop;" 5047 ".Lpost_movss_nop:"); 5048 /* 5049 * For an L0 synthesized single-step #DB. (L0 intercepts WBINVD and 5050 * emulates it in software.) 5051 */ 5052 asm volatile("vmcall;" 5053 "wbinvd;" 5054 ".Lpost_wbinvd:"); 5055 /* 5056 * ...in a MOVSS shadow, with pending debug exceptions. 5057 */ 5058 asm volatile("vmcall;" 5059 "wbinvd;" 5060 ".Lpost_movss_wbinvd:"); 5061 /* 5062 * For a hardware generated single-step #DB in a transactional region. 5063 */ 5064 asm volatile("vmcall;" 5065 ".Lxbegin: xbegin .Lskip_rtm;" 5066 "xend;" 5067 ".Lskip_rtm:"); 5068 } 5069 5070 /* 5071 * Clear the pending debug exceptions and RFLAGS.TF and re-enter 5072 * L2. No #DB is delivered and L2 continues to the next point of 5073 * interest. 5074 */ 5075 static void dismiss_db(void) 5076 { 5077 vmcs_write(GUEST_PENDING_DEBUG, 0); 5078 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 5079 enter_guest(); 5080 } 5081 5082 /* 5083 * Check a variety of VMCS fields relevant to an intercepted #DB exception. 5084 * Then throw away the #DB exception and resume L2. 5085 */ 5086 static void check_db_exit(bool xfail_qual, bool xfail_dr6, bool xfail_pdbg, 5087 void *expected_rip, u64 expected_exit_qual, 5088 u64 expected_dr6) 5089 { 5090 u32 reason = vmcs_read(EXI_REASON); 5091 u32 intr_info = vmcs_read(EXI_INTR_INFO); 5092 u64 exit_qual = vmcs_read(EXI_QUALIFICATION); 5093 u64 guest_rip = vmcs_read(GUEST_RIP); 5094 u64 guest_pending_dbg = vmcs_read(GUEST_PENDING_DEBUG); 5095 u64 dr6 = read_dr6(); 5096 const u32 expected_intr_info = INTR_INFO_VALID_MASK | 5097 INTR_TYPE_HARD_EXCEPTION | DB_VECTOR; 5098 5099 report("Expected #DB VM-exit", 5100 reason == VMX_EXC_NMI && intr_info == expected_intr_info); 5101 report("Expected RIP %p (actual %lx)", (u64)expected_rip == guest_rip, 5102 expected_rip, guest_rip); 5103 report_xfail("Expected pending debug exceptions 0 (actual %lx)", 5104 xfail_pdbg, 0 == guest_pending_dbg, guest_pending_dbg); 5105 report_xfail("Expected exit qualification %lx (actual %lx)", xfail_qual, 5106 expected_exit_qual == exit_qual, 5107 expected_exit_qual, exit_qual); 5108 report_xfail("Expected DR6 %lx (actual %lx)", xfail_dr6, 5109 expected_dr6 == dr6, expected_dr6, dr6); 5110 dismiss_db(); 5111 } 5112 5113 /* 5114 * Assuming the guest has just exited on a VMCALL instruction, skip 5115 * over the vmcall, and set the guest's RFLAGS.TF in the VMCS. If 5116 * pending debug exceptions are non-zero, set the VMCS up as if the 5117 * previous instruction was a MOVSS that generated the indicated 5118 * pending debug exceptions. Then enter L2. 5119 */ 5120 static void single_step_guest(const char *test_name, u64 starting_dr6, 5121 u64 pending_debug_exceptions) 5122 { 5123 printf("\n%s\n", test_name); 5124 skip_exit_vmcall(); 5125 write_dr6(starting_dr6); 5126 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_TF); 5127 if (pending_debug_exceptions) { 5128 vmcs_write(GUEST_PENDING_DEBUG, pending_debug_exceptions); 5129 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 5130 } 5131 enter_guest(); 5132 } 5133 5134 /* 5135 * When L1 intercepts #DB, verify that a single-step trap clears 5136 * pending debug exceptions, populates the exit qualification field 5137 * properly, and that DR6 is not prematurely clobbered. In a 5138 * (simulated) MOVSS shadow, make sure that the pending debug 5139 * exception bits are properly accumulated into the exit qualification 5140 * field. 5141 */ 5142 static void vmx_db_test(void) 5143 { 5144 /* 5145 * We are going to set a few arbitrary bits in DR6 to verify that 5146 * (a) DR6 is not modified by an intercepted #DB, and 5147 * (b) stale bits in DR6 (DR6.BD, in particular) don't leak into 5148 * the exit qualification field for a subsequent #DB exception. 5149 */ 5150 const u64 starting_dr6 = DR6_RESERVED | BIT(13) | DR_TRAP3 | DR_TRAP1; 5151 extern char post_nop asm(".Lpost_nop"); 5152 extern char post_movss_nop asm(".Lpost_movss_nop"); 5153 extern char post_wbinvd asm(".Lpost_wbinvd"); 5154 extern char post_movss_wbinvd asm(".Lpost_movss_wbinvd"); 5155 extern char xbegin asm(".Lxbegin"); 5156 extern char skip_rtm asm(".Lskip_rtm"); 5157 5158 /* 5159 * L1 wants to intercept #DB exceptions encountered in L2. 5160 */ 5161 vmcs_write(EXC_BITMAP, BIT(DB_VECTOR)); 5162 5163 /* 5164 * Start L2 and run it up to the first point of interest. 5165 */ 5166 test_set_guest(vmx_db_test_guest); 5167 enter_guest(); 5168 5169 /* 5170 * Hardware-delivered #DB trap for single-step sets the 5171 * standard that L0 has to follow for emulated instructions. 5172 */ 5173 single_step_guest("Hardware delivered single-step", starting_dr6, 0); 5174 check_db_exit(false, false, false, &post_nop, DR_STEP, starting_dr6); 5175 5176 /* 5177 * Hardware-delivered #DB trap for single-step in MOVSS shadow 5178 * also sets the standard that L0 has to follow for emulated 5179 * instructions. Here, we establish the VMCS pending debug 5180 * exceptions to indicate that the simulated MOVSS triggered a 5181 * data breakpoint as well as the single-step trap. 5182 */ 5183 single_step_guest("Hardware delivered single-step in MOVSS shadow", 5184 starting_dr6, BIT(12) | DR_STEP | DR_TRAP0 ); 5185 check_db_exit(false, false, false, &post_movss_nop, DR_STEP | DR_TRAP0, 5186 starting_dr6); 5187 5188 /* 5189 * L0 synthesized #DB trap for single-step is buggy, because 5190 * kvm (a) clobbers DR6 too early, and (b) tries its best to 5191 * reconstitute the exit qualification from the prematurely 5192 * modified DR6, but fails miserably. 5193 */ 5194 single_step_guest("Software synthesized single-step", starting_dr6, 0); 5195 check_db_exit(true, true, false, &post_wbinvd, DR_STEP, starting_dr6); 5196 5197 /* 5198 * L0 synthesized #DB trap for single-step in MOVSS shadow is 5199 * even worse, because L0 also leaves the pending debug 5200 * exceptions in the VMCS instead of accumulating them into 5201 * the exit qualification field for the #DB exception. 5202 */ 5203 single_step_guest("Software synthesized single-step in MOVSS shadow", 5204 starting_dr6, BIT(12) | DR_STEP | DR_TRAP0); 5205 check_db_exit(true, true, true, &post_movss_wbinvd, DR_STEP | DR_TRAP0, 5206 starting_dr6); 5207 5208 /* 5209 * Optional RTM test for hardware that supports RTM, to 5210 * demonstrate that the current volume 3 of the SDM 5211 * (325384-067US), table 27-1 is incorrect. Bit 16 of the exit 5212 * qualification for debug exceptions is not reserved. It is 5213 * set to 1 if a debug exception (#DB) or a breakpoint 5214 * exception (#BP) occurs inside an RTM region while advanced 5215 * debugging of RTM transactional regions is enabled. 5216 */ 5217 if (cpuid(7).b & BIT(11)) { 5218 vmcs_write(ENT_CONTROLS, 5219 vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 5220 /* 5221 * Set DR7.RTM[bit 11] and IA32_DEBUGCTL.RTM[bit 15] 5222 * in the guest to enable advanced debugging of RTM 5223 * transactional regions. 5224 */ 5225 vmcs_write(GUEST_DR7, BIT(11)); 5226 vmcs_write(GUEST_DEBUGCTL, BIT(15)); 5227 single_step_guest("Hardware delivered single-step in " 5228 "transactional region", starting_dr6, 0); 5229 check_db_exit(false, false, false, &xbegin, BIT(16), 5230 starting_dr6); 5231 } else { 5232 vmcs_write(GUEST_RIP, (u64)&skip_rtm); 5233 enter_guest(); 5234 } 5235 } 5236 5237 static bool cpu_has_apicv(void) 5238 { 5239 return ((ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT) && 5240 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 5241 (ctrl_pin_rev.clr & PIN_POST_INTR)); 5242 } 5243 5244 static void enable_vid(void) 5245 { 5246 void *virtual_apic_page; 5247 5248 assert(cpu_has_apicv()); 5249 5250 disable_intercept_for_x2apic_msrs(); 5251 5252 virtual_apic_page = alloc_page(); 5253 vmcs_write(APIC_VIRT_ADDR, (u64)virtual_apic_page); 5254 5255 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 5256 5257 vmcs_write(EOI_EXIT_BITMAP0, 0x0); 5258 vmcs_write(EOI_EXIT_BITMAP1, 0x0); 5259 vmcs_write(EOI_EXIT_BITMAP2, 0x0); 5260 vmcs_write(EOI_EXIT_BITMAP3, 0x0); 5261 5262 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY | CPU_TPR_SHADOW); 5263 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_VINTD | CPU_VIRT_X2APIC); 5264 } 5265 5266 static void trigger_ioapic_scan_thread(void *data) 5267 { 5268 /* Wait until other CPU entered L2 */ 5269 while (vmx_get_test_stage() != 1) 5270 ; 5271 5272 /* Trigger ioapic scan */ 5273 ioapic_set_redir(0xf, 0x79, TRIGGER_LEVEL); 5274 vmx_set_test_stage(2); 5275 } 5276 5277 static void irq_79_handler_guest(isr_regs_t *regs) 5278 { 5279 eoi(); 5280 5281 /* L1 expects vmexit on VMX_VMCALL and not VMX_EOI_INDUCED */ 5282 vmcall(); 5283 } 5284 5285 /* 5286 * Constant for num of busy-loop iterations after which 5287 * a timer interrupt should have happened in host 5288 */ 5289 #define TIMER_INTERRUPT_DELAY 100000000 5290 5291 static void vmx_eoi_bitmap_ioapic_scan_test_guest(void) 5292 { 5293 handle_irq(0x79, irq_79_handler_guest); 5294 irq_enable(); 5295 5296 /* Signal to L1 CPU to trigger ioapic scan */ 5297 vmx_set_test_stage(1); 5298 /* Wait until L1 CPU to trigger ioapic scan */ 5299 while (vmx_get_test_stage() != 2) 5300 ; 5301 5302 /* 5303 * Wait for L0 timer interrupt to be raised while we run in L2 5304 * such that L0 will process the IOAPIC scan request before 5305 * resuming L2 5306 */ 5307 delay(TIMER_INTERRUPT_DELAY); 5308 5309 asm volatile ("int $0x79"); 5310 } 5311 5312 static void vmx_eoi_bitmap_ioapic_scan_test(void) 5313 { 5314 if (!cpu_has_apicv() || (cpu_count() < 2)) { 5315 report_skip(__func__); 5316 return; 5317 } 5318 5319 enable_vid(); 5320 5321 on_cpu_async(1, trigger_ioapic_scan_thread, NULL); 5322 test_set_guest(vmx_eoi_bitmap_ioapic_scan_test_guest); 5323 5324 /* 5325 * Launch L2. 5326 * We expect the exit reason to be VMX_VMCALL (and not EOI INDUCED). 5327 * In case the reason isn't VMX_VMCALL, the asserion inside 5328 * skip_exit_vmcall() will fail. 5329 */ 5330 enter_guest(); 5331 skip_exit_vmcall(); 5332 5333 /* Let L2 finish */ 5334 enter_guest(); 5335 report(__func__, 1); 5336 } 5337 5338 #define HLT_WITH_RVI_VECTOR (0xf1) 5339 5340 bool vmx_hlt_with_rvi_guest_isr_fired; 5341 static void vmx_hlt_with_rvi_guest_isr(isr_regs_t *regs) 5342 { 5343 vmx_hlt_with_rvi_guest_isr_fired = true; 5344 eoi(); 5345 } 5346 5347 static void vmx_hlt_with_rvi_guest(void) 5348 { 5349 handle_irq(HLT_WITH_RVI_VECTOR, vmx_hlt_with_rvi_guest_isr); 5350 5351 irq_enable(); 5352 asm volatile ("nop"); 5353 5354 vmcall(); 5355 } 5356 5357 static void vmx_hlt_with_rvi_test(void) 5358 { 5359 if (!cpu_has_apicv()) { 5360 report_skip(__func__); 5361 return; 5362 } 5363 5364 enable_vid(); 5365 5366 vmx_hlt_with_rvi_guest_isr_fired = false; 5367 test_set_guest(vmx_hlt_with_rvi_guest); 5368 5369 enter_guest(); 5370 skip_exit_vmcall(); 5371 5372 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 5373 vmcs_write(GUEST_INT_STATUS, HLT_WITH_RVI_VECTOR); 5374 enter_guest(); 5375 5376 report("Interrupt raised in guest", vmx_hlt_with_rvi_guest_isr_fired); 5377 } 5378 5379 static void set_irq_line_thread(void *data) 5380 { 5381 /* Wait until other CPU entered L2 */ 5382 while (vmx_get_test_stage() != 1) 5383 ; 5384 5385 /* Set irq-line 0xf to raise vector 0x78 for vCPU 0 */ 5386 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 5387 vmx_set_test_stage(2); 5388 } 5389 5390 static bool irq_78_handler_vmcall_before_eoi; 5391 static void irq_78_handler_guest(isr_regs_t *regs) 5392 { 5393 set_irq_line(0xf, 0); 5394 if (irq_78_handler_vmcall_before_eoi) 5395 vmcall(); 5396 eoi(); 5397 vmcall(); 5398 } 5399 5400 static void vmx_apic_passthrough_guest(void) 5401 { 5402 handle_irq(0x78, irq_78_handler_guest); 5403 irq_enable(); 5404 5405 /* If requested, wait for other CPU to trigger ioapic scan */ 5406 if (vmx_get_test_stage() < 1) { 5407 vmx_set_test_stage(1); 5408 while (vmx_get_test_stage() != 2) 5409 ; 5410 } 5411 5412 set_irq_line(0xf, 1); 5413 } 5414 5415 static void vmx_apic_passthrough(bool set_irq_line_from_thread) 5416 { 5417 if (set_irq_line_from_thread && (cpu_count() < 2)) { 5418 report_skip(__func__); 5419 return; 5420 } 5421 5422 u64 cpu_ctrl_0 = CPU_SECONDARY; 5423 u64 cpu_ctrl_1 = 0; 5424 5425 disable_intercept_for_x2apic_msrs(); 5426 5427 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 5428 5429 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 5430 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 5431 5432 if (set_irq_line_from_thread) { 5433 irq_78_handler_vmcall_before_eoi = false; 5434 on_cpu_async(1, set_irq_line_thread, NULL); 5435 } else { 5436 irq_78_handler_vmcall_before_eoi = true; 5437 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 5438 vmx_set_test_stage(2); 5439 } 5440 test_set_guest(vmx_apic_passthrough_guest); 5441 5442 if (irq_78_handler_vmcall_before_eoi) { 5443 /* Before EOI remote_irr should still be set */ 5444 enter_guest(); 5445 skip_exit_vmcall(); 5446 TEST_ASSERT_EQ_MSG(1, (int)ioapic_read_redir(0xf).remote_irr, 5447 "IOAPIC pass-through: remote_irr=1 before EOI"); 5448 } 5449 5450 /* After EOI remote_irr should be cleared */ 5451 enter_guest(); 5452 skip_exit_vmcall(); 5453 TEST_ASSERT_EQ_MSG(0, (int)ioapic_read_redir(0xf).remote_irr, 5454 "IOAPIC pass-through: remote_irr=0 after EOI"); 5455 5456 /* Let L2 finish */ 5457 enter_guest(); 5458 report(__func__, 1); 5459 } 5460 5461 static void vmx_apic_passthrough_test(void) 5462 { 5463 vmx_apic_passthrough(false); 5464 } 5465 5466 static void vmx_apic_passthrough_thread_test(void) 5467 { 5468 vmx_apic_passthrough(true); 5469 } 5470 5471 enum vmcs_access { 5472 ACCESS_VMREAD, 5473 ACCESS_VMWRITE, 5474 ACCESS_NONE, 5475 }; 5476 5477 struct vmcs_shadow_test_common { 5478 enum vmcs_access op; 5479 enum Reason reason; 5480 u64 field; 5481 u64 value; 5482 u64 flags; 5483 u64 time; 5484 } l1_l2_common; 5485 5486 static inline u64 vmread_flags(u64 field, u64 *val) 5487 { 5488 u64 flags; 5489 5490 asm volatile ("vmread %2, %1; pushf; pop %0" 5491 : "=r" (flags), "=rm" (*val) : "r" (field) : "cc"); 5492 return flags & X86_EFLAGS_ALU; 5493 } 5494 5495 static inline u64 vmwrite_flags(u64 field, u64 val) 5496 { 5497 u64 flags; 5498 5499 asm volatile ("vmwrite %1, %2; pushf; pop %0" 5500 : "=r"(flags) : "rm" (val), "r" (field) : "cc"); 5501 return flags & X86_EFLAGS_ALU; 5502 } 5503 5504 static void vmx_vmcs_shadow_test_guest(void) 5505 { 5506 struct vmcs_shadow_test_common *c = &l1_l2_common; 5507 u64 start; 5508 5509 while (c->op != ACCESS_NONE) { 5510 start = rdtsc(); 5511 switch (c->op) { 5512 default: 5513 c->flags = -1ull; 5514 break; 5515 case ACCESS_VMREAD: 5516 c->flags = vmread_flags(c->field, &c->value); 5517 break; 5518 case ACCESS_VMWRITE: 5519 c->flags = vmwrite_flags(c->field, 0); 5520 break; 5521 } 5522 c->time = rdtsc() - start; 5523 vmcall(); 5524 } 5525 } 5526 5527 static u64 vmread_from_shadow(u64 field) 5528 { 5529 struct vmcs *primary; 5530 struct vmcs *shadow; 5531 u64 value; 5532 5533 TEST_ASSERT(!vmcs_save(&primary)); 5534 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 5535 TEST_ASSERT(!make_vmcs_current(shadow)); 5536 value = vmcs_read(field); 5537 TEST_ASSERT(!make_vmcs_current(primary)); 5538 return value; 5539 } 5540 5541 static u64 vmwrite_to_shadow(u64 field, u64 value) 5542 { 5543 struct vmcs *primary; 5544 struct vmcs *shadow; 5545 5546 TEST_ASSERT(!vmcs_save(&primary)); 5547 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 5548 TEST_ASSERT(!make_vmcs_current(shadow)); 5549 vmcs_write(field, value); 5550 value = vmcs_read(field); 5551 TEST_ASSERT(!make_vmcs_current(primary)); 5552 return value; 5553 } 5554 5555 static void vmcs_shadow_test_access(u8 *bitmap[2], enum vmcs_access access) 5556 { 5557 struct vmcs_shadow_test_common *c = &l1_l2_common; 5558 5559 c->op = access; 5560 vmcs_write(VMX_INST_ERROR, 0); 5561 enter_guest(); 5562 c->reason = vmcs_read(EXI_REASON) & 0xffff; 5563 if (c->reason != VMX_VMCALL) { 5564 skip_exit_insn(); 5565 enter_guest(); 5566 } 5567 skip_exit_vmcall(); 5568 } 5569 5570 static void vmcs_shadow_test_field(u8 *bitmap[2], u64 field) 5571 { 5572 struct vmcs_shadow_test_common *c = &l1_l2_common; 5573 struct vmcs *shadow; 5574 u64 value; 5575 uintptr_t flags[2]; 5576 bool good_shadow; 5577 u32 vmx_inst_error; 5578 5579 report_prefix_pushf("field %lx", field); 5580 c->field = field; 5581 5582 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 5583 if (shadow != (struct vmcs *)-1ull) { 5584 flags[ACCESS_VMREAD] = vmread_flags(field, &value); 5585 flags[ACCESS_VMWRITE] = vmwrite_flags(field, value); 5586 good_shadow = !flags[ACCESS_VMREAD] && !flags[ACCESS_VMWRITE]; 5587 } else { 5588 /* 5589 * When VMCS link pointer is -1ull, VMWRITE/VMREAD on 5590 * shadowed-fields should fail with setting RFLAGS.CF. 5591 */ 5592 flags[ACCESS_VMREAD] = X86_EFLAGS_CF; 5593 flags[ACCESS_VMWRITE] = X86_EFLAGS_CF; 5594 good_shadow = false; 5595 } 5596 5597 /* Intercept both VMREAD and VMWRITE. */ 5598 report_prefix_push("no VMREAD/VMWRITE permission"); 5599 /* VMWRITE/VMREAD done on reserved-bit should always intercept */ 5600 if (!(field >> VMCS_FIELD_RESERVED_SHIFT)) { 5601 set_bit(field, bitmap[ACCESS_VMREAD]); 5602 set_bit(field, bitmap[ACCESS_VMWRITE]); 5603 } 5604 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 5605 report("not shadowed for VMWRITE", c->reason == VMX_VMWRITE); 5606 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 5607 report("not shadowed for VMREAD", c->reason == VMX_VMREAD); 5608 report_prefix_pop(); 5609 5610 if (field >> VMCS_FIELD_RESERVED_SHIFT) 5611 goto out; 5612 5613 /* Permit shadowed VMREAD. */ 5614 report_prefix_push("VMREAD permission only"); 5615 clear_bit(field, bitmap[ACCESS_VMREAD]); 5616 set_bit(field, bitmap[ACCESS_VMWRITE]); 5617 if (good_shadow) 5618 value = vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 5619 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 5620 report("not shadowed for VMWRITE", c->reason == VMX_VMWRITE); 5621 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 5622 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 5623 report("shadowed for VMREAD (in %ld cycles)", c->reason == VMX_VMCALL, 5624 c->time); 5625 report("ALU flags after VMREAD (%lx) are as expected (%lx)", 5626 c->flags == flags[ACCESS_VMREAD], 5627 c->flags, flags[ACCESS_VMREAD]); 5628 if (good_shadow) 5629 report("value read from shadow (%lx) is as expected (%lx)", 5630 c->value == value, c->value, value); 5631 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 5632 report("VMX_INST_ERROR (%d) is as expected (%d)", 5633 vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 5634 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 5635 report_prefix_pop(); 5636 5637 /* Permit shadowed VMWRITE. */ 5638 report_prefix_push("VMWRITE permission only"); 5639 set_bit(field, bitmap[ACCESS_VMREAD]); 5640 clear_bit(field, bitmap[ACCESS_VMWRITE]); 5641 if (good_shadow) 5642 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 5643 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 5644 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 5645 report("shadowed for VMWRITE (in %ld cycles)", c->reason == VMX_VMCALL, 5646 c->time); 5647 report("ALU flags after VMWRITE (%lx) are as expected (%lx)", 5648 c->flags == flags[ACCESS_VMREAD], 5649 c->flags, flags[ACCESS_VMREAD]); 5650 if (good_shadow) { 5651 value = vmread_from_shadow(field); 5652 report("shadow VMCS value (%lx) is as expected (%lx)", 5653 value == 0, value, 0ul); 5654 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 5655 report("VMX_INST_ERROR (%d) is as expected (%d)", 5656 vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 5657 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 5658 } 5659 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 5660 report("not shadowed for VMREAD", c->reason == VMX_VMREAD); 5661 report_prefix_pop(); 5662 5663 /* Permit shadowed VMREAD and VMWRITE. */ 5664 report_prefix_push("VMREAD and VMWRITE permission"); 5665 clear_bit(field, bitmap[ACCESS_VMREAD]); 5666 clear_bit(field, bitmap[ACCESS_VMWRITE]); 5667 if (good_shadow) 5668 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 5669 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 5670 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 5671 report("shadowed for VMWRITE (in %ld cycles)", c->reason == VMX_VMCALL, 5672 c->time); 5673 report("ALU flags after VMWRITE (%lx) are as expected (%lx)", 5674 c->flags == flags[ACCESS_VMREAD], 5675 c->flags, flags[ACCESS_VMREAD]); 5676 if (good_shadow) { 5677 value = vmread_from_shadow(field); 5678 report("shadow VMCS value (%lx) is as expected (%lx)", 5679 value == 0, value, 0ul); 5680 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 5681 report("VMX_INST_ERROR (%d) is as expected (%d)", 5682 vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 5683 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 5684 } 5685 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 5686 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 5687 report("shadowed for VMREAD (in %ld cycles)", c->reason == VMX_VMCALL, 5688 c->time); 5689 report("ALU flags after VMREAD (%lx) are as expected (%lx)", 5690 c->flags == flags[ACCESS_VMREAD], 5691 c->flags, flags[ACCESS_VMREAD]); 5692 if (good_shadow) 5693 report("value read from shadow (%lx) is as expected (%lx)", 5694 c->value == 0, c->value, 0ul); 5695 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 5696 report("VMX_INST_ERROR (%d) is as expected (%d)", 5697 vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 5698 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 5699 report_prefix_pop(); 5700 5701 out: 5702 report_prefix_pop(); 5703 } 5704 5705 static void vmx_vmcs_shadow_test_body(u8 *bitmap[2]) 5706 { 5707 unsigned base; 5708 unsigned index; 5709 unsigned bit; 5710 unsigned highest_index = rdmsr(MSR_IA32_VMX_VMCS_ENUM); 5711 5712 /* Run test on all possible valid VMCS fields */ 5713 for (base = 0; 5714 base < (1 << VMCS_FIELD_RESERVED_SHIFT); 5715 base += (1 << VMCS_FIELD_TYPE_SHIFT)) 5716 for (index = 0; index <= highest_index; index++) 5717 vmcs_shadow_test_field(bitmap, base + index); 5718 5719 /* 5720 * Run tests on some invalid VMCS fields 5721 * (Have reserved bit set). 5722 */ 5723 for (bit = VMCS_FIELD_RESERVED_SHIFT; bit < VMCS_FIELD_BIT_SIZE; bit++) 5724 vmcs_shadow_test_field(bitmap, (1ull << bit)); 5725 } 5726 5727 static void vmx_vmcs_shadow_test(void) 5728 { 5729 u8 *bitmap[2]; 5730 struct vmcs *shadow; 5731 5732 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 5733 printf("\t'Activate secondary controls' not supported.\n"); 5734 return; 5735 } 5736 5737 if (!(ctrl_cpu_rev[1].clr & CPU_SHADOW_VMCS)) { 5738 printf("\t'VMCS shadowing' not supported.\n"); 5739 return; 5740 } 5741 5742 if (!(rdmsr(MSR_IA32_VMX_MISC) & 5743 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS)) { 5744 printf("\tVMWRITE can't modify VM-exit information fields.\n"); 5745 return; 5746 } 5747 5748 test_set_guest(vmx_vmcs_shadow_test_guest); 5749 5750 bitmap[ACCESS_VMREAD] = alloc_page(); 5751 bitmap[ACCESS_VMWRITE] = alloc_page(); 5752 5753 vmcs_write(VMREAD_BITMAP, virt_to_phys(bitmap[ACCESS_VMREAD])); 5754 vmcs_write(VMWRITE_BITMAP, virt_to_phys(bitmap[ACCESS_VMWRITE])); 5755 5756 shadow = alloc_page(); 5757 shadow->hdr.revision_id = basic.revision; 5758 shadow->hdr.shadow_vmcs = 1; 5759 TEST_ASSERT(!vmcs_clear(shadow)); 5760 5761 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_RDTSC); 5762 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY); 5763 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_SHADOW_VMCS); 5764 5765 vmcs_write(VMCS_LINK_PTR, virt_to_phys(shadow)); 5766 report_prefix_push("valid link pointer"); 5767 vmx_vmcs_shadow_test_body(bitmap); 5768 report_prefix_pop(); 5769 5770 vmcs_write(VMCS_LINK_PTR, -1ull); 5771 report_prefix_push("invalid link pointer"); 5772 vmx_vmcs_shadow_test_body(bitmap); 5773 report_prefix_pop(); 5774 5775 l1_l2_common.op = ACCESS_NONE; 5776 enter_guest(); 5777 } 5778 5779 #define TEST(name) { #name, .v2 = name } 5780 5781 /* name/init/guest_main/exit_handler/syscall_handler/guest_regs */ 5782 struct vmx_test vmx_tests[] = { 5783 { "null", NULL, basic_guest_main, basic_exit_handler, NULL, {0} }, 5784 { "vmenter", NULL, vmenter_main, vmenter_exit_handler, NULL, {0} }, 5785 { "preemption timer", preemption_timer_init, preemption_timer_main, 5786 preemption_timer_exit_handler, NULL, {0} }, 5787 { "control field PAT", test_ctrl_pat_init, test_ctrl_pat_main, 5788 test_ctrl_pat_exit_handler, NULL, {0} }, 5789 { "control field EFER", test_ctrl_efer_init, test_ctrl_efer_main, 5790 test_ctrl_efer_exit_handler, NULL, {0} }, 5791 { "CR shadowing", NULL, cr_shadowing_main, 5792 cr_shadowing_exit_handler, NULL, {0} }, 5793 { "I/O bitmap", iobmp_init, iobmp_main, iobmp_exit_handler, 5794 NULL, {0} }, 5795 { "instruction intercept", insn_intercept_init, insn_intercept_main, 5796 insn_intercept_exit_handler, NULL, {0} }, 5797 { "EPT A/D disabled", ept_init, ept_main, ept_exit_handler, NULL, {0} }, 5798 { "EPT A/D enabled", eptad_init, eptad_main, eptad_exit_handler, NULL, {0} }, 5799 { "PML", pml_init, pml_main, pml_exit_handler, NULL, {0} }, 5800 { "VPID", vpid_init, vpid_main, vpid_exit_handler, NULL, {0} }, 5801 { "interrupt", interrupt_init, interrupt_main, 5802 interrupt_exit_handler, NULL, {0} }, 5803 { "debug controls", dbgctls_init, dbgctls_main, dbgctls_exit_handler, 5804 NULL, {0} }, 5805 { "MSR switch", msr_switch_init, msr_switch_main, 5806 msr_switch_exit_handler, NULL, {0}, msr_switch_entry_failure }, 5807 { "vmmcall", vmmcall_init, vmmcall_main, vmmcall_exit_handler, NULL, {0} }, 5808 { "disable RDTSCP", disable_rdtscp_init, disable_rdtscp_main, 5809 disable_rdtscp_exit_handler, NULL, {0} }, 5810 { "int3", int3_init, int3_guest_main, int3_exit_handler, NULL, {0} }, 5811 { "into", into_init, into_guest_main, into_exit_handler, NULL, {0} }, 5812 { "exit_monitor_from_l2_test", NULL, exit_monitor_from_l2_main, 5813 exit_monitor_from_l2_handler, NULL, {0} }, 5814 /* Basic V2 tests. */ 5815 TEST(v2_null_test), 5816 TEST(v2_multiple_entries_test), 5817 TEST(fixture_test_case1), 5818 TEST(fixture_test_case2), 5819 /* Opcode tests. */ 5820 TEST(invvpid_test_v2), 5821 /* VM-entry tests */ 5822 TEST(vmx_controls_test), 5823 TEST(vmentry_movss_shadow_test), 5824 /* APICv tests */ 5825 TEST(vmx_eoi_bitmap_ioapic_scan_test), 5826 TEST(vmx_hlt_with_rvi_test), 5827 /* APIC pass-through tests */ 5828 TEST(vmx_apic_passthrough_test), 5829 TEST(vmx_apic_passthrough_thread_test), 5830 /* VMCS Shadowing tests */ 5831 TEST(vmx_vmcs_shadow_test), 5832 /* Regression tests */ 5833 TEST(vmx_cr_load_test), 5834 TEST(vmx_nm_test), 5835 TEST(vmx_db_test), 5836 TEST(vmx_pending_event_test), 5837 TEST(vmx_pending_event_hlt_test), 5838 /* EPT access tests. */ 5839 TEST(ept_access_test_not_present), 5840 TEST(ept_access_test_read_only), 5841 TEST(ept_access_test_write_only), 5842 TEST(ept_access_test_read_write), 5843 TEST(ept_access_test_execute_only), 5844 TEST(ept_access_test_read_execute), 5845 TEST(ept_access_test_write_execute), 5846 TEST(ept_access_test_read_write_execute), 5847 TEST(ept_access_test_reserved_bits), 5848 TEST(ept_access_test_ignored_bits), 5849 TEST(ept_access_test_paddr_not_present_ad_disabled), 5850 TEST(ept_access_test_paddr_not_present_ad_enabled), 5851 TEST(ept_access_test_paddr_read_only_ad_disabled), 5852 TEST(ept_access_test_paddr_read_only_ad_enabled), 5853 TEST(ept_access_test_paddr_read_write), 5854 TEST(ept_access_test_paddr_read_write_execute), 5855 TEST(ept_access_test_paddr_read_execute_ad_disabled), 5856 TEST(ept_access_test_paddr_read_execute_ad_enabled), 5857 TEST(ept_access_test_paddr_not_present_page_fault), 5858 TEST(ept_access_test_force_2m_page), 5859 { NULL, NULL, NULL, NULL, NULL, {0} }, 5860 }; 5861