1 /* 2 * All test cases of nested virtualization should be in this file 3 * 4 * Author : Arthur Chunqi Li <yzt356@gmail.com> 5 */ 6 7 #include <asm/debugreg.h> 8 9 #include "vmx.h" 10 #include "msr.h" 11 #include "processor.h" 12 #include "vm.h" 13 #include "pci.h" 14 #include "fwcfg.h" 15 #include "isr.h" 16 #include "desc.h" 17 #include "apic.h" 18 #include "types.h" 19 #include "vmalloc.h" 20 #include "alloc_page.h" 21 #include "smp.h" 22 #include "delay.h" 23 #include "access.h" 24 #include "x86/usermode.h" 25 26 /* 27 * vmcs.GUEST_PENDING_DEBUG has the same format as DR6, although some bits that 28 * are legal in DR6 are reserved in vmcs.GUEST_PENDING_DEBUG. And if any data 29 * or I/O breakpoint matches *and* was enabled, bit 12 is also set. 30 */ 31 #define PENDING_DBG_TRAP BIT(12) 32 33 #define VPID_CAP_INVVPID_TYPES_SHIFT 40 34 35 u64 ia32_pat; 36 u64 ia32_efer; 37 void *io_bitmap_a, *io_bitmap_b; 38 u16 ioport; 39 40 unsigned long *pml4; 41 u64 eptp; 42 void *data_page1, *data_page2; 43 44 phys_addr_t pci_physaddr; 45 46 void *pml_log; 47 #define PML_INDEX 512 48 49 static inline unsigned ffs(unsigned x) 50 { 51 int pos = -1; 52 53 __asm__ __volatile__("bsf %1, %%eax; cmovnz %%eax, %0" 54 : "+r"(pos) : "rm"(x) : "eax"); 55 return pos + 1; 56 } 57 58 static inline void vmcall(void) 59 { 60 asm volatile("vmcall"); 61 } 62 63 static void basic_guest_main(void) 64 { 65 report_pass("Basic VMX test"); 66 } 67 68 static int basic_exit_handler(union exit_reason exit_reason) 69 { 70 report_fail("Basic VMX test"); 71 print_vmexit_info(exit_reason); 72 return VMX_TEST_EXIT; 73 } 74 75 static void vmenter_main(void) 76 { 77 u64 rax; 78 u64 rsp, resume_rsp; 79 80 report_pass("test vmlaunch"); 81 82 asm volatile( 83 "mov %%rsp, %0\n\t" 84 "mov %3, %%rax\n\t" 85 "vmcall\n\t" 86 "mov %%rax, %1\n\t" 87 "mov %%rsp, %2\n\t" 88 : "=r"(rsp), "=r"(rax), "=r"(resume_rsp) 89 : "g"(0xABCD)); 90 report((rax == 0xFFFF) && (rsp == resume_rsp), "test vmresume"); 91 } 92 93 static int vmenter_exit_handler(union exit_reason exit_reason) 94 { 95 u64 guest_rip = vmcs_read(GUEST_RIP); 96 97 switch (exit_reason.basic) { 98 case VMX_VMCALL: 99 if (regs.rax != 0xABCD) { 100 report_fail("test vmresume"); 101 return VMX_TEST_VMEXIT; 102 } 103 regs.rax = 0xFFFF; 104 vmcs_write(GUEST_RIP, guest_rip + 3); 105 return VMX_TEST_RESUME; 106 default: 107 report_fail("test vmresume"); 108 print_vmexit_info(exit_reason); 109 } 110 return VMX_TEST_VMEXIT; 111 } 112 113 u32 preempt_scale; 114 volatile unsigned long long tsc_val; 115 volatile u32 preempt_val; 116 u64 saved_rip; 117 118 static int preemption_timer_init(struct vmcs *vmcs) 119 { 120 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 121 printf("\tPreemption timer is not supported\n"); 122 return VMX_TEST_EXIT; 123 } 124 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 125 preempt_val = 10000000; 126 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 127 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 128 129 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 130 printf("\tSave preemption value is not supported\n"); 131 132 return VMX_TEST_START; 133 } 134 135 static void preemption_timer_main(void) 136 { 137 tsc_val = rdtsc(); 138 if (ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) { 139 vmx_set_test_stage(0); 140 vmcall(); 141 if (vmx_get_test_stage() == 1) 142 vmcall(); 143 } 144 vmx_set_test_stage(1); 145 while (vmx_get_test_stage() == 1) { 146 if (((rdtsc() - tsc_val) >> preempt_scale) 147 > 10 * preempt_val) { 148 vmx_set_test_stage(2); 149 vmcall(); 150 } 151 } 152 tsc_val = rdtsc(); 153 asm volatile ("hlt"); 154 vmcall(); 155 vmx_set_test_stage(5); 156 vmcall(); 157 } 158 159 static int preemption_timer_exit_handler(union exit_reason exit_reason) 160 { 161 bool guest_halted; 162 u64 guest_rip; 163 u32 insn_len; 164 u32 ctrl_exit; 165 166 guest_rip = vmcs_read(GUEST_RIP); 167 insn_len = vmcs_read(EXI_INST_LEN); 168 switch (exit_reason.basic) { 169 case VMX_PREEMPT: 170 switch (vmx_get_test_stage()) { 171 case 1: 172 case 2: 173 report(((rdtsc() - tsc_val) >> preempt_scale) >= preempt_val, 174 "busy-wait for preemption timer"); 175 vmx_set_test_stage(3); 176 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 177 return VMX_TEST_RESUME; 178 case 3: 179 guest_halted = 180 (vmcs_read(GUEST_ACTV_STATE) == ACTV_HLT); 181 report(((rdtsc() - tsc_val) >> preempt_scale) >= preempt_val 182 && guest_halted, 183 "preemption timer during hlt"); 184 vmx_set_test_stage(4); 185 vmcs_write(PIN_CONTROLS, 186 vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 187 vmcs_write(EXI_CONTROLS, 188 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_PREEMPT); 189 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 190 return VMX_TEST_RESUME; 191 case 4: 192 report(saved_rip == guest_rip, 193 "preemption timer with 0 value"); 194 break; 195 default: 196 report_fail("Invalid stage."); 197 print_vmexit_info(exit_reason); 198 break; 199 } 200 break; 201 case VMX_VMCALL: 202 vmcs_write(GUEST_RIP, guest_rip + insn_len); 203 switch (vmx_get_test_stage()) { 204 case 0: 205 report(vmcs_read(PREEMPT_TIMER_VALUE) == preempt_val, 206 "Keep preemption value"); 207 vmx_set_test_stage(1); 208 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 209 ctrl_exit = (vmcs_read(EXI_CONTROLS) | 210 EXI_SAVE_PREEMPT) & ctrl_exit_rev.clr; 211 vmcs_write(EXI_CONTROLS, ctrl_exit); 212 return VMX_TEST_RESUME; 213 case 1: 214 report(vmcs_read(PREEMPT_TIMER_VALUE) < preempt_val, 215 "Save preemption value"); 216 return VMX_TEST_RESUME; 217 case 2: 218 report_fail("busy-wait for preemption timer"); 219 vmx_set_test_stage(3); 220 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 221 return VMX_TEST_RESUME; 222 case 3: 223 report_fail("preemption timer during hlt"); 224 vmx_set_test_stage(4); 225 /* fall through */ 226 case 4: 227 vmcs_write(PIN_CONTROLS, 228 vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 229 vmcs_write(PREEMPT_TIMER_VALUE, 0); 230 saved_rip = guest_rip + insn_len; 231 return VMX_TEST_RESUME; 232 case 5: 233 report_fail("preemption timer with 0 value (vmcall stage 5)"); 234 break; 235 default: 236 // Should not reach here 237 report_fail("unexpected stage, %d", 238 vmx_get_test_stage()); 239 print_vmexit_info(exit_reason); 240 return VMX_TEST_VMEXIT; 241 } 242 break; 243 default: 244 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 245 print_vmexit_info(exit_reason); 246 } 247 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 248 return VMX_TEST_VMEXIT; 249 } 250 251 static void msr_bmp_init(void) 252 { 253 void *msr_bitmap; 254 u32 ctrl_cpu0; 255 256 msr_bitmap = alloc_page(); 257 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 258 ctrl_cpu0 |= CPU_MSR_BITMAP; 259 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 260 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 261 } 262 263 static void *get_msr_bitmap(void) 264 { 265 void *msr_bitmap; 266 267 if (vmcs_read(CPU_EXEC_CTRL0) & CPU_MSR_BITMAP) { 268 msr_bitmap = (void *)vmcs_read(MSR_BITMAP); 269 } else { 270 msr_bitmap = alloc_page(); 271 memset(msr_bitmap, 0xff, PAGE_SIZE); 272 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 273 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_MSR_BITMAP); 274 } 275 276 return msr_bitmap; 277 } 278 279 static void disable_intercept_for_x2apic_msrs(void) 280 { 281 unsigned long *msr_bitmap = (unsigned long *)get_msr_bitmap(); 282 u32 msr; 283 284 for (msr = APIC_BASE_MSR; 285 msr < (APIC_BASE_MSR+0xff); 286 msr += BITS_PER_LONG) { 287 unsigned int word = msr / BITS_PER_LONG; 288 289 msr_bitmap[word] = 0; 290 msr_bitmap[word + (0x800 / sizeof(long))] = 0; 291 } 292 } 293 294 static int test_ctrl_pat_init(struct vmcs *vmcs) 295 { 296 u64 ctrl_ent; 297 u64 ctrl_exi; 298 299 msr_bmp_init(); 300 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT) && 301 !(ctrl_exit_rev.clr & EXI_LOAD_PAT) && 302 !(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 303 printf("\tSave/load PAT is not supported\n"); 304 return 1; 305 } 306 307 ctrl_ent = vmcs_read(ENT_CONTROLS); 308 ctrl_exi = vmcs_read(EXI_CONTROLS); 309 ctrl_ent |= ctrl_enter_rev.clr & ENT_LOAD_PAT; 310 ctrl_exi |= ctrl_exit_rev.clr & (EXI_SAVE_PAT | EXI_LOAD_PAT); 311 vmcs_write(ENT_CONTROLS, ctrl_ent); 312 vmcs_write(EXI_CONTROLS, ctrl_exi); 313 ia32_pat = rdmsr(MSR_IA32_CR_PAT); 314 vmcs_write(GUEST_PAT, 0x0); 315 vmcs_write(HOST_PAT, ia32_pat); 316 return VMX_TEST_START; 317 } 318 319 static void test_ctrl_pat_main(void) 320 { 321 u64 guest_ia32_pat; 322 323 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 324 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) 325 printf("\tENT_LOAD_PAT is not supported.\n"); 326 else { 327 if (guest_ia32_pat != 0) { 328 report_fail("Entry load PAT"); 329 return; 330 } 331 } 332 wrmsr(MSR_IA32_CR_PAT, 0x6); 333 vmcall(); 334 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 335 if (ctrl_enter_rev.clr & ENT_LOAD_PAT) 336 report(guest_ia32_pat == ia32_pat, "Entry load PAT"); 337 } 338 339 static int test_ctrl_pat_exit_handler(union exit_reason exit_reason) 340 { 341 u64 guest_rip; 342 u64 guest_pat; 343 344 guest_rip = vmcs_read(GUEST_RIP); 345 switch (exit_reason.basic) { 346 case VMX_VMCALL: 347 guest_pat = vmcs_read(GUEST_PAT); 348 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT)) { 349 printf("\tEXI_SAVE_PAT is not supported\n"); 350 vmcs_write(GUEST_PAT, 0x6); 351 } else { 352 report(guest_pat == 0x6, "Exit save PAT"); 353 } 354 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) 355 printf("\tEXI_LOAD_PAT is not supported\n"); 356 else 357 report(rdmsr(MSR_IA32_CR_PAT) == ia32_pat, 358 "Exit load PAT"); 359 vmcs_write(GUEST_PAT, ia32_pat); 360 vmcs_write(GUEST_RIP, guest_rip + 3); 361 return VMX_TEST_RESUME; 362 default: 363 printf("ERROR : Unknown exit reason, 0x%x.\n", exit_reason.full); 364 break; 365 } 366 return VMX_TEST_VMEXIT; 367 } 368 369 static int test_ctrl_efer_init(struct vmcs *vmcs) 370 { 371 u64 ctrl_ent; 372 u64 ctrl_exi; 373 374 msr_bmp_init(); 375 ctrl_ent = vmcs_read(ENT_CONTROLS) | ENT_LOAD_EFER; 376 ctrl_exi = vmcs_read(EXI_CONTROLS) | EXI_SAVE_EFER | EXI_LOAD_EFER; 377 vmcs_write(ENT_CONTROLS, ctrl_ent & ctrl_enter_rev.clr); 378 vmcs_write(EXI_CONTROLS, ctrl_exi & ctrl_exit_rev.clr); 379 ia32_efer = rdmsr(MSR_EFER); 380 vmcs_write(GUEST_EFER, ia32_efer ^ EFER_NX); 381 vmcs_write(HOST_EFER, ia32_efer ^ EFER_NX); 382 return VMX_TEST_START; 383 } 384 385 static void test_ctrl_efer_main(void) 386 { 387 u64 guest_ia32_efer; 388 389 guest_ia32_efer = rdmsr(MSR_EFER); 390 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) 391 printf("\tENT_LOAD_EFER is not supported.\n"); 392 else { 393 if (guest_ia32_efer != (ia32_efer ^ EFER_NX)) { 394 report_fail("Entry load EFER"); 395 return; 396 } 397 } 398 wrmsr(MSR_EFER, ia32_efer); 399 vmcall(); 400 guest_ia32_efer = rdmsr(MSR_EFER); 401 if (ctrl_enter_rev.clr & ENT_LOAD_EFER) 402 report(guest_ia32_efer == ia32_efer, "Entry load EFER"); 403 } 404 405 static int test_ctrl_efer_exit_handler(union exit_reason exit_reason) 406 { 407 u64 guest_rip; 408 u64 guest_efer; 409 410 guest_rip = vmcs_read(GUEST_RIP); 411 switch (exit_reason.basic) { 412 case VMX_VMCALL: 413 guest_efer = vmcs_read(GUEST_EFER); 414 if (!(ctrl_exit_rev.clr & EXI_SAVE_EFER)) { 415 printf("\tEXI_SAVE_EFER is not supported\n"); 416 vmcs_write(GUEST_EFER, ia32_efer); 417 } else { 418 report(guest_efer == ia32_efer, "Exit save EFER"); 419 } 420 if (!(ctrl_exit_rev.clr & EXI_LOAD_EFER)) { 421 printf("\tEXI_LOAD_EFER is not supported\n"); 422 wrmsr(MSR_EFER, ia32_efer ^ EFER_NX); 423 } else { 424 report(rdmsr(MSR_EFER) == (ia32_efer ^ EFER_NX), 425 "Exit load EFER"); 426 } 427 vmcs_write(GUEST_PAT, ia32_efer); 428 vmcs_write(GUEST_RIP, guest_rip + 3); 429 return VMX_TEST_RESUME; 430 default: 431 printf("ERROR : Unknown exit reason, 0x%x.\n", exit_reason.full); 432 break; 433 } 434 return VMX_TEST_VMEXIT; 435 } 436 437 u32 guest_cr0, guest_cr4; 438 439 static void cr_shadowing_main(void) 440 { 441 u32 cr0, cr4, tmp; 442 443 // Test read through 444 vmx_set_test_stage(0); 445 guest_cr0 = read_cr0(); 446 if (vmx_get_test_stage() == 1) 447 report_fail("Read through CR0"); 448 else 449 vmcall(); 450 vmx_set_test_stage(1); 451 guest_cr4 = read_cr4(); 452 if (vmx_get_test_stage() == 2) 453 report_fail("Read through CR4"); 454 else 455 vmcall(); 456 // Test write through 457 guest_cr0 = guest_cr0 ^ (X86_CR0_TS | X86_CR0_MP); 458 guest_cr4 = guest_cr4 ^ (X86_CR4_TSD | X86_CR4_DE); 459 vmx_set_test_stage(2); 460 write_cr0(guest_cr0); 461 if (vmx_get_test_stage() == 3) 462 report_fail("Write through CR0"); 463 else 464 vmcall(); 465 vmx_set_test_stage(3); 466 write_cr4(guest_cr4); 467 if (vmx_get_test_stage() == 4) 468 report_fail("Write through CR4"); 469 else 470 vmcall(); 471 // Test read shadow 472 vmx_set_test_stage(4); 473 vmcall(); 474 cr0 = read_cr0(); 475 if (vmx_get_test_stage() != 5) 476 report(cr0 == guest_cr0, "Read shadowing CR0"); 477 vmx_set_test_stage(5); 478 cr4 = read_cr4(); 479 if (vmx_get_test_stage() != 6) 480 report(cr4 == guest_cr4, "Read shadowing CR4"); 481 // Test write shadow (same value with shadow) 482 vmx_set_test_stage(6); 483 write_cr0(guest_cr0); 484 if (vmx_get_test_stage() == 7) 485 report_fail("Write shadowing CR0 (same value with shadow)"); 486 else 487 vmcall(); 488 vmx_set_test_stage(7); 489 write_cr4(guest_cr4); 490 if (vmx_get_test_stage() == 8) 491 report_fail("Write shadowing CR4 (same value with shadow)"); 492 else 493 vmcall(); 494 // Test write shadow (different value) 495 vmx_set_test_stage(8); 496 tmp = guest_cr0 ^ X86_CR0_TS; 497 asm volatile("mov %0, %%rsi\n\t" 498 "mov %%rsi, %%cr0\n\t" 499 ::"m"(tmp) 500 :"rsi", "memory", "cc"); 501 report(vmx_get_test_stage() == 9, 502 "Write shadowing different X86_CR0_TS"); 503 vmx_set_test_stage(9); 504 tmp = guest_cr0 ^ X86_CR0_MP; 505 asm volatile("mov %0, %%rsi\n\t" 506 "mov %%rsi, %%cr0\n\t" 507 ::"m"(tmp) 508 :"rsi", "memory", "cc"); 509 report(vmx_get_test_stage() == 10, 510 "Write shadowing different X86_CR0_MP"); 511 vmx_set_test_stage(10); 512 tmp = guest_cr4 ^ X86_CR4_TSD; 513 asm volatile("mov %0, %%rsi\n\t" 514 "mov %%rsi, %%cr4\n\t" 515 ::"m"(tmp) 516 :"rsi", "memory", "cc"); 517 report(vmx_get_test_stage() == 11, 518 "Write shadowing different X86_CR4_TSD"); 519 vmx_set_test_stage(11); 520 tmp = guest_cr4 ^ X86_CR4_DE; 521 asm volatile("mov %0, %%rsi\n\t" 522 "mov %%rsi, %%cr4\n\t" 523 ::"m"(tmp) 524 :"rsi", "memory", "cc"); 525 report(vmx_get_test_stage() == 12, 526 "Write shadowing different X86_CR4_DE"); 527 } 528 529 static int cr_shadowing_exit_handler(union exit_reason exit_reason) 530 { 531 u64 guest_rip; 532 u32 insn_len; 533 u32 exit_qual; 534 535 guest_rip = vmcs_read(GUEST_RIP); 536 insn_len = vmcs_read(EXI_INST_LEN); 537 exit_qual = vmcs_read(EXI_QUALIFICATION); 538 switch (exit_reason.basic) { 539 case VMX_VMCALL: 540 switch (vmx_get_test_stage()) { 541 case 0: 542 report(guest_cr0 == vmcs_read(GUEST_CR0), 543 "Read through CR0"); 544 break; 545 case 1: 546 report(guest_cr4 == vmcs_read(GUEST_CR4), 547 "Read through CR4"); 548 break; 549 case 2: 550 report(guest_cr0 == vmcs_read(GUEST_CR0), 551 "Write through CR0"); 552 break; 553 case 3: 554 report(guest_cr4 == vmcs_read(GUEST_CR4), 555 "Write through CR4"); 556 break; 557 case 4: 558 guest_cr0 = vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP); 559 guest_cr4 = vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE); 560 vmcs_write(CR0_MASK, X86_CR0_TS | X86_CR0_MP); 561 vmcs_write(CR0_READ_SHADOW, guest_cr0 & (X86_CR0_TS | X86_CR0_MP)); 562 vmcs_write(CR4_MASK, X86_CR4_TSD | X86_CR4_DE); 563 vmcs_write(CR4_READ_SHADOW, guest_cr4 & (X86_CR4_TSD | X86_CR4_DE)); 564 break; 565 case 6: 566 report(guest_cr0 == (vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP)), 567 "Write shadowing CR0 (same value)"); 568 break; 569 case 7: 570 report(guest_cr4 == (vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE)), 571 "Write shadowing CR4 (same value)"); 572 break; 573 default: 574 // Should not reach here 575 report_fail("unexpected stage, %d", 576 vmx_get_test_stage()); 577 print_vmexit_info(exit_reason); 578 return VMX_TEST_VMEXIT; 579 } 580 vmcs_write(GUEST_RIP, guest_rip + insn_len); 581 return VMX_TEST_RESUME; 582 case VMX_CR: 583 switch (vmx_get_test_stage()) { 584 case 4: 585 report_fail("Read shadowing CR0"); 586 vmx_inc_test_stage(); 587 break; 588 case 5: 589 report_fail("Read shadowing CR4"); 590 vmx_inc_test_stage(); 591 break; 592 case 6: 593 report_fail("Write shadowing CR0 (same value)"); 594 vmx_inc_test_stage(); 595 break; 596 case 7: 597 report_fail("Write shadowing CR4 (same value)"); 598 vmx_inc_test_stage(); 599 break; 600 case 8: 601 case 9: 602 // 0x600 encodes "mov %esi, %cr0" 603 if (exit_qual == 0x600) 604 vmx_inc_test_stage(); 605 break; 606 case 10: 607 case 11: 608 // 0x604 encodes "mov %esi, %cr4" 609 if (exit_qual == 0x604) 610 vmx_inc_test_stage(); 611 break; 612 default: 613 // Should not reach here 614 report_fail("unexpected stage, %d", 615 vmx_get_test_stage()); 616 print_vmexit_info(exit_reason); 617 return VMX_TEST_VMEXIT; 618 } 619 vmcs_write(GUEST_RIP, guest_rip + insn_len); 620 return VMX_TEST_RESUME; 621 default: 622 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 623 print_vmexit_info(exit_reason); 624 } 625 return VMX_TEST_VMEXIT; 626 } 627 628 static int iobmp_init(struct vmcs *vmcs) 629 { 630 u32 ctrl_cpu0; 631 632 io_bitmap_a = alloc_page(); 633 io_bitmap_b = alloc_page(); 634 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 635 ctrl_cpu0 |= CPU_IO_BITMAP; 636 ctrl_cpu0 &= (~CPU_IO); 637 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 638 vmcs_write(IO_BITMAP_A, (u64)io_bitmap_a); 639 vmcs_write(IO_BITMAP_B, (u64)io_bitmap_b); 640 return VMX_TEST_START; 641 } 642 643 static void iobmp_main(void) 644 { 645 // stage 0, test IO pass 646 vmx_set_test_stage(0); 647 inb(0x5000); 648 outb(0x0, 0x5000); 649 report(vmx_get_test_stage() == 0, "I/O bitmap - I/O pass"); 650 // test IO width, in/out 651 ((u8 *)io_bitmap_a)[0] = 0xFF; 652 vmx_set_test_stage(2); 653 inb(0x0); 654 report(vmx_get_test_stage() == 3, "I/O bitmap - trap in"); 655 vmx_set_test_stage(3); 656 outw(0x0, 0x0); 657 report(vmx_get_test_stage() == 4, "I/O bitmap - trap out"); 658 vmx_set_test_stage(4); 659 inl(0x0); 660 report(vmx_get_test_stage() == 5, "I/O bitmap - I/O width, long"); 661 // test low/high IO port 662 vmx_set_test_stage(5); 663 ((u8 *)io_bitmap_a)[0x5000 / 8] = (1 << (0x5000 % 8)); 664 inb(0x5000); 665 report(vmx_get_test_stage() == 6, "I/O bitmap - I/O port, low part"); 666 vmx_set_test_stage(6); 667 ((u8 *)io_bitmap_b)[0x1000 / 8] = (1 << (0x1000 % 8)); 668 inb(0x9000); 669 report(vmx_get_test_stage() == 7, "I/O bitmap - I/O port, high part"); 670 // test partial pass 671 vmx_set_test_stage(7); 672 inl(0x4FFF); 673 report(vmx_get_test_stage() == 8, "I/O bitmap - partial pass"); 674 // test overrun 675 vmx_set_test_stage(8); 676 memset(io_bitmap_a, 0x0, PAGE_SIZE); 677 memset(io_bitmap_b, 0x0, PAGE_SIZE); 678 inl(0xFFFF); 679 report(vmx_get_test_stage() == 9, "I/O bitmap - overrun"); 680 vmx_set_test_stage(9); 681 vmcall(); 682 outb(0x0, 0x0); 683 report(vmx_get_test_stage() == 9, 684 "I/O bitmap - ignore unconditional exiting"); 685 vmx_set_test_stage(10); 686 vmcall(); 687 outb(0x0, 0x0); 688 report(vmx_get_test_stage() == 11, 689 "I/O bitmap - unconditional exiting"); 690 } 691 692 static int iobmp_exit_handler(union exit_reason exit_reason) 693 { 694 u64 guest_rip; 695 ulong exit_qual; 696 u32 insn_len, ctrl_cpu0; 697 698 guest_rip = vmcs_read(GUEST_RIP); 699 exit_qual = vmcs_read(EXI_QUALIFICATION); 700 insn_len = vmcs_read(EXI_INST_LEN); 701 switch (exit_reason.basic) { 702 case VMX_IO: 703 switch (vmx_get_test_stage()) { 704 case 0: 705 case 1: 706 vmx_inc_test_stage(); 707 break; 708 case 2: 709 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_BYTE, 710 "I/O bitmap - I/O width, byte"); 711 report(exit_qual & VMX_IO_IN, 712 "I/O bitmap - I/O direction, in"); 713 vmx_inc_test_stage(); 714 break; 715 case 3: 716 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_WORD, 717 "I/O bitmap - I/O width, word"); 718 report(!(exit_qual & VMX_IO_IN), 719 "I/O bitmap - I/O direction, out"); 720 vmx_inc_test_stage(); 721 break; 722 case 4: 723 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_LONG, 724 "I/O bitmap - I/O width, long"); 725 vmx_inc_test_stage(); 726 break; 727 case 5: 728 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x5000) 729 vmx_inc_test_stage(); 730 break; 731 case 6: 732 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x9000) 733 vmx_inc_test_stage(); 734 break; 735 case 7: 736 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x4FFF) 737 vmx_inc_test_stage(); 738 break; 739 case 8: 740 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0xFFFF) 741 vmx_inc_test_stage(); 742 break; 743 case 9: 744 case 10: 745 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 746 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0 & ~CPU_IO); 747 vmx_inc_test_stage(); 748 break; 749 default: 750 // Should not reach here 751 report_fail("unexpected stage, %d", 752 vmx_get_test_stage()); 753 print_vmexit_info(exit_reason); 754 return VMX_TEST_VMEXIT; 755 } 756 vmcs_write(GUEST_RIP, guest_rip + insn_len); 757 return VMX_TEST_RESUME; 758 case VMX_VMCALL: 759 switch (vmx_get_test_stage()) { 760 case 9: 761 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 762 ctrl_cpu0 |= CPU_IO | CPU_IO_BITMAP; 763 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 764 break; 765 case 10: 766 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 767 ctrl_cpu0 = (ctrl_cpu0 & ~CPU_IO_BITMAP) | CPU_IO; 768 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 769 break; 770 default: 771 // Should not reach here 772 report_fail("unexpected stage, %d", 773 vmx_get_test_stage()); 774 print_vmexit_info(exit_reason); 775 return VMX_TEST_VMEXIT; 776 } 777 vmcs_write(GUEST_RIP, guest_rip + insn_len); 778 return VMX_TEST_RESUME; 779 default: 780 printf("guest_rip = %#lx\n", guest_rip); 781 printf("\tERROR : Unknown exit reason, 0x%x\n", exit_reason.full); 782 break; 783 } 784 return VMX_TEST_VMEXIT; 785 } 786 787 #define INSN_CPU0 0 788 #define INSN_CPU1 1 789 #define INSN_ALWAYS_TRAP 2 790 791 #define FIELD_EXIT_QUAL (1 << 0) 792 #define FIELD_INSN_INFO (1 << 1) 793 794 asm( 795 "insn_hlt: hlt;ret\n\t" 796 "insn_invlpg: invlpg 0x12345678;ret\n\t" 797 "insn_mwait: xor %eax, %eax; xor %ecx, %ecx; mwait;ret\n\t" 798 "insn_rdpmc: xor %ecx, %ecx; rdpmc;ret\n\t" 799 "insn_rdtsc: rdtsc;ret\n\t" 800 "insn_cr3_load: mov cr3,%rax; mov %rax,%cr3;ret\n\t" 801 "insn_cr3_store: mov %cr3,%rax;ret\n\t" 802 "insn_cr8_load: xor %eax, %eax; mov %rax,%cr8;ret\n\t" 803 "insn_cr8_store: mov %cr8,%rax;ret\n\t" 804 "insn_monitor: xor %eax, %eax; xor %ecx, %ecx; xor %edx, %edx; monitor;ret\n\t" 805 "insn_pause: pause;ret\n\t" 806 "insn_wbinvd: wbinvd;ret\n\t" 807 "insn_cpuid: mov $10, %eax; cpuid;ret\n\t" 808 "insn_invd: invd;ret\n\t" 809 "insn_sgdt: sgdt gdt_descr;ret\n\t" 810 "insn_lgdt: lgdt gdt_descr;ret\n\t" 811 "insn_sidt: sidt idt_descr;ret\n\t" 812 "insn_lidt: lidt idt_descr;ret\n\t" 813 "insn_sldt: sldt %ax;ret\n\t" 814 "insn_lldt: xor %eax, %eax; lldt %ax;ret\n\t" 815 "insn_str: str %ax;ret\n\t" 816 "insn_rdrand: rdrand %rax;ret\n\t" 817 "insn_rdseed: rdseed %rax;ret\n\t" 818 ); 819 extern void insn_hlt(void); 820 extern void insn_invlpg(void); 821 extern void insn_mwait(void); 822 extern void insn_rdpmc(void); 823 extern void insn_rdtsc(void); 824 extern void insn_cr3_load(void); 825 extern void insn_cr3_store(void); 826 extern void insn_cr8_load(void); 827 extern void insn_cr8_store(void); 828 extern void insn_monitor(void); 829 extern void insn_pause(void); 830 extern void insn_wbinvd(void); 831 extern void insn_sgdt(void); 832 extern void insn_lgdt(void); 833 extern void insn_sidt(void); 834 extern void insn_lidt(void); 835 extern void insn_sldt(void); 836 extern void insn_lldt(void); 837 extern void insn_str(void); 838 extern void insn_cpuid(void); 839 extern void insn_invd(void); 840 extern void insn_rdrand(void); 841 extern void insn_rdseed(void); 842 843 u32 cur_insn; 844 u64 cr3; 845 846 #define X86_FEATURE_MONITOR (1 << 3) 847 848 typedef bool (*supported_fn)(void); 849 850 static bool monitor_supported(void) 851 { 852 return this_cpu_has(X86_FEATURE_MWAIT); 853 } 854 855 struct insn_table { 856 const char *name; 857 u32 flag; 858 void (*insn_func)(void); 859 u32 type; 860 u32 reason; 861 ulong exit_qual; 862 u32 insn_info; 863 // Use FIELD_EXIT_QUAL and FIELD_INSN_INFO to define 864 // which field need to be tested, reason is always tested 865 u32 test_field; 866 const supported_fn supported_fn; 867 u8 disabled; 868 }; 869 870 /* 871 * Add more test cases of instruction intercept here. Elements in this 872 * table is: 873 * name/control flag/insn function/type/exit reason/exit qulification/ 874 * instruction info/field to test 875 * The last field defines which fields (exit_qual and insn_info) need to be 876 * tested in exit handler. If set to 0, only "reason" is checked. 877 */ 878 static struct insn_table insn_table[] = { 879 // Flags for Primary Processor-Based VM-Execution Controls 880 {"HLT", CPU_HLT, insn_hlt, INSN_CPU0, 12, 0, 0, 0}, 881 {"INVLPG", CPU_INVLPG, insn_invlpg, INSN_CPU0, 14, 882 0x12345678, 0, FIELD_EXIT_QUAL}, 883 {"MWAIT", CPU_MWAIT, insn_mwait, INSN_CPU0, 36, 0, 0, 0, &monitor_supported}, 884 {"RDPMC", CPU_RDPMC, insn_rdpmc, INSN_CPU0, 15, 0, 0, 0}, 885 {"RDTSC", CPU_RDTSC, insn_rdtsc, INSN_CPU0, 16, 0, 0, 0}, 886 {"CR3 load", CPU_CR3_LOAD, insn_cr3_load, INSN_CPU0, 28, 0x3, 0, 887 FIELD_EXIT_QUAL}, 888 {"CR3 store", CPU_CR3_STORE, insn_cr3_store, INSN_CPU0, 28, 0x13, 0, 889 FIELD_EXIT_QUAL}, 890 {"CR8 load", CPU_CR8_LOAD, insn_cr8_load, INSN_CPU0, 28, 0x8, 0, 891 FIELD_EXIT_QUAL}, 892 {"CR8 store", CPU_CR8_STORE, insn_cr8_store, INSN_CPU0, 28, 0x18, 0, 893 FIELD_EXIT_QUAL}, 894 {"MONITOR", CPU_MONITOR, insn_monitor, INSN_CPU0, 39, 0, 0, 0, &monitor_supported}, 895 {"PAUSE", CPU_PAUSE, insn_pause, INSN_CPU0, 40, 0, 0, 0}, 896 // Flags for Secondary Processor-Based VM-Execution Controls 897 {"WBINVD", CPU_WBINVD, insn_wbinvd, INSN_CPU1, 54, 0, 0, 0}, 898 {"DESC_TABLE (SGDT)", CPU_DESC_TABLE, insn_sgdt, INSN_CPU1, 46, 0, 0, 0}, 899 {"DESC_TABLE (LGDT)", CPU_DESC_TABLE, insn_lgdt, INSN_CPU1, 46, 0, 0, 0}, 900 {"DESC_TABLE (SIDT)", CPU_DESC_TABLE, insn_sidt, INSN_CPU1, 46, 0, 0, 0}, 901 {"DESC_TABLE (LIDT)", CPU_DESC_TABLE, insn_lidt, INSN_CPU1, 46, 0, 0, 0}, 902 {"DESC_TABLE (SLDT)", CPU_DESC_TABLE, insn_sldt, INSN_CPU1, 47, 0, 0, 0}, 903 {"DESC_TABLE (LLDT)", CPU_DESC_TABLE, insn_lldt, INSN_CPU1, 47, 0, 0, 0}, 904 {"DESC_TABLE (STR)", CPU_DESC_TABLE, insn_str, INSN_CPU1, 47, 0, 0, 0}, 905 /* LTR causes a #GP if done with a busy selector, so it is not tested. */ 906 {"RDRAND", CPU_RDRAND, insn_rdrand, INSN_CPU1, VMX_RDRAND, 0, 0, 0}, 907 {"RDSEED", CPU_RDSEED, insn_rdseed, INSN_CPU1, VMX_RDSEED, 0, 0, 0}, 908 // Instructions always trap 909 {"CPUID", 0, insn_cpuid, INSN_ALWAYS_TRAP, 10, 0, 0, 0}, 910 {"INVD", 0, insn_invd, INSN_ALWAYS_TRAP, 13, 0, 0, 0}, 911 // Instructions never trap 912 {NULL}, 913 }; 914 915 static int insn_intercept_init(struct vmcs *vmcs) 916 { 917 u32 ctrl_cpu, cur_insn; 918 919 ctrl_cpu = ctrl_cpu_rev[0].set | CPU_SECONDARY; 920 ctrl_cpu &= ctrl_cpu_rev[0].clr; 921 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu); 922 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu_rev[1].set); 923 cr3 = read_cr3(); 924 925 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 926 if (insn_table[cur_insn].supported_fn == NULL) 927 continue; 928 insn_table[cur_insn].disabled = !insn_table[cur_insn].supported_fn(); 929 } 930 return VMX_TEST_START; 931 } 932 933 static void insn_intercept_main(void) 934 { 935 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 936 vmx_set_test_stage(cur_insn * 2); 937 if ((insn_table[cur_insn].type == INSN_CPU0 && 938 !(ctrl_cpu_rev[0].clr & insn_table[cur_insn].flag)) || 939 (insn_table[cur_insn].type == INSN_CPU1 && 940 !(ctrl_cpu_rev[1].clr & insn_table[cur_insn].flag))) { 941 printf("\tCPU_CTRL%d.CPU_%s is not supported.\n", 942 insn_table[cur_insn].type - INSN_CPU0, 943 insn_table[cur_insn].name); 944 continue; 945 } 946 947 if (insn_table[cur_insn].disabled) { 948 printf("\tFeature required for %s is not supported.\n", 949 insn_table[cur_insn].name); 950 continue; 951 } 952 953 if ((insn_table[cur_insn].type == INSN_CPU0 && 954 !(ctrl_cpu_rev[0].set & insn_table[cur_insn].flag)) || 955 (insn_table[cur_insn].type == INSN_CPU1 && 956 !(ctrl_cpu_rev[1].set & insn_table[cur_insn].flag))) { 957 /* skip hlt, it stalls the guest and is tested below */ 958 if (insn_table[cur_insn].insn_func != insn_hlt) 959 insn_table[cur_insn].insn_func(); 960 report(vmx_get_test_stage() == cur_insn * 2, 961 "execute %s", 962 insn_table[cur_insn].name); 963 } else if (insn_table[cur_insn].type != INSN_ALWAYS_TRAP) 964 printf("\tCPU_CTRL%d.CPU_%s always traps.\n", 965 insn_table[cur_insn].type - INSN_CPU0, 966 insn_table[cur_insn].name); 967 968 vmcall(); 969 970 insn_table[cur_insn].insn_func(); 971 report(vmx_get_test_stage() == cur_insn * 2 + 1, 972 "intercept %s", 973 insn_table[cur_insn].name); 974 975 vmx_set_test_stage(cur_insn * 2 + 1); 976 vmcall(); 977 } 978 } 979 980 static int insn_intercept_exit_handler(union exit_reason exit_reason) 981 { 982 u64 guest_rip; 983 ulong exit_qual; 984 u32 insn_len; 985 u32 insn_info; 986 bool pass; 987 988 guest_rip = vmcs_read(GUEST_RIP); 989 exit_qual = vmcs_read(EXI_QUALIFICATION); 990 insn_len = vmcs_read(EXI_INST_LEN); 991 insn_info = vmcs_read(EXI_INST_INFO); 992 993 if (exit_reason.basic == VMX_VMCALL) { 994 u32 val = 0; 995 996 if (insn_table[cur_insn].type == INSN_CPU0) 997 val = vmcs_read(CPU_EXEC_CTRL0); 998 else if (insn_table[cur_insn].type == INSN_CPU1) 999 val = vmcs_read(CPU_EXEC_CTRL1); 1000 1001 if (vmx_get_test_stage() & 1) 1002 val &= ~insn_table[cur_insn].flag; 1003 else 1004 val |= insn_table[cur_insn].flag; 1005 1006 if (insn_table[cur_insn].type == INSN_CPU0) 1007 vmcs_write(CPU_EXEC_CTRL0, val | ctrl_cpu_rev[0].set); 1008 else if (insn_table[cur_insn].type == INSN_CPU1) 1009 vmcs_write(CPU_EXEC_CTRL1, val | ctrl_cpu_rev[1].set); 1010 } else { 1011 pass = (cur_insn * 2 == vmx_get_test_stage()) && 1012 insn_table[cur_insn].reason == exit_reason.full; 1013 if (insn_table[cur_insn].test_field & FIELD_EXIT_QUAL && 1014 insn_table[cur_insn].exit_qual != exit_qual) 1015 pass = false; 1016 if (insn_table[cur_insn].test_field & FIELD_INSN_INFO && 1017 insn_table[cur_insn].insn_info != insn_info) 1018 pass = false; 1019 if (pass) 1020 vmx_inc_test_stage(); 1021 } 1022 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1023 return VMX_TEST_RESUME; 1024 } 1025 1026 /** 1027 * __setup_ept - Setup the VMCS fields to enable Extended Page Tables (EPT) 1028 * @hpa: Host physical address of the top-level, a.k.a. root, EPT table 1029 * @enable_ad: Whether or not to enable Access/Dirty bits for EPT entries 1030 * 1031 * Returns 0 on success, 1 on failure. 1032 * 1033 * Note that @hpa doesn't need to point at actual memory if VM-Launch is 1034 * expected to fail, e.g. setup_dummy_ept() arbitrarily passes '0' to satisfy 1035 * the various EPTP consistency checks, but doesn't ensure backing for HPA '0'. 1036 */ 1037 static int __setup_ept(u64 hpa, bool enable_ad) 1038 { 1039 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1040 !(ctrl_cpu_rev[1].clr & CPU_EPT)) { 1041 printf("\tEPT is not supported\n"); 1042 return 1; 1043 } 1044 if (!(ept_vpid.val & EPT_CAP_WB)) { 1045 printf("\tWB memtype for EPT walks not supported\n"); 1046 return 1; 1047 } 1048 if (!(ept_vpid.val & EPT_CAP_PWL4)) { 1049 printf("\tPWL4 is not supported\n"); 1050 return 1; 1051 } 1052 1053 eptp = EPT_MEM_TYPE_WB; 1054 eptp |= (3 << EPTP_PG_WALK_LEN_SHIFT); 1055 eptp |= hpa; 1056 if (enable_ad) 1057 eptp |= EPTP_AD_FLAG; 1058 1059 vmcs_write(EPTP, eptp); 1060 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0)| CPU_SECONDARY); 1061 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1)| CPU_EPT); 1062 1063 return 0; 1064 } 1065 1066 /** 1067 * setup_ept - Enable Extended Page Tables (EPT) and setup an identity map 1068 * @enable_ad: Whether or not to enable Access/Dirty bits for EPT entries 1069 * 1070 * Returns 0 on success, 1 on failure. 1071 * 1072 * This is the "real" function for setting up EPT tables, i.e. use this for 1073 * tests that need to run code in the guest with EPT enabled. 1074 */ 1075 static int setup_ept(bool enable_ad) 1076 { 1077 unsigned long end_of_memory; 1078 1079 pml4 = alloc_page(); 1080 1081 if (__setup_ept(virt_to_phys(pml4), enable_ad)) 1082 return 1; 1083 1084 end_of_memory = fwcfg_get_u64(FW_CFG_RAM_SIZE); 1085 if (end_of_memory < (1ul << 32)) 1086 end_of_memory = (1ul << 32); 1087 /* Cannot use large EPT pages if we need to track EPT 1088 * accessed/dirty bits at 4K granularity. 1089 */ 1090 setup_ept_range(pml4, 0, end_of_memory, 0, 1091 !enable_ad && ept_2m_supported(), 1092 EPT_WA | EPT_RA | EPT_EA); 1093 return 0; 1094 } 1095 1096 /** 1097 * setup_dummy_ept - Enable Extended Page Tables (EPT) with a dummy root HPA 1098 * 1099 * Setup EPT using a semi-arbitrary dummy root HPA. This function is intended 1100 * for use by tests that need EPT enabled to verify dependent VMCS controls 1101 * but never expect to fully enter the guest, i.e. don't need setup the actual 1102 * EPT tables. 1103 */ 1104 static void setup_dummy_ept(void) 1105 { 1106 if (__setup_ept(0, false)) 1107 report_abort("EPT setup unexpectedly failed"); 1108 } 1109 1110 static int enable_unrestricted_guest(bool need_valid_ept) 1111 { 1112 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1113 !(ctrl_cpu_rev[1].clr & CPU_URG) || 1114 !(ctrl_cpu_rev[1].clr & CPU_EPT)) 1115 return 1; 1116 1117 if (need_valid_ept) 1118 setup_ept(false); 1119 else 1120 setup_dummy_ept(); 1121 1122 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 1123 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | CPU_URG); 1124 1125 return 0; 1126 } 1127 1128 static void ept_enable_ad_bits(void) 1129 { 1130 eptp |= EPTP_AD_FLAG; 1131 vmcs_write(EPTP, eptp); 1132 } 1133 1134 static void ept_disable_ad_bits(void) 1135 { 1136 eptp &= ~EPTP_AD_FLAG; 1137 vmcs_write(EPTP, eptp); 1138 } 1139 1140 static int ept_ad_enabled(void) 1141 { 1142 return eptp & EPTP_AD_FLAG; 1143 } 1144 1145 static void ept_enable_ad_bits_or_skip_test(void) 1146 { 1147 if (!ept_ad_bits_supported()) 1148 test_skip("EPT AD bits not supported."); 1149 ept_enable_ad_bits(); 1150 } 1151 1152 static int apic_version; 1153 1154 static int ept_init_common(bool have_ad) 1155 { 1156 int ret; 1157 struct pci_dev pcidev; 1158 1159 /* INVEPT is required by the EPT violation handler. */ 1160 if (!is_invept_type_supported(INVEPT_SINGLE)) 1161 return VMX_TEST_EXIT; 1162 1163 if (setup_ept(have_ad)) 1164 return VMX_TEST_EXIT; 1165 1166 data_page1 = alloc_page(); 1167 data_page2 = alloc_page(); 1168 *((u32 *)data_page1) = MAGIC_VAL_1; 1169 *((u32 *)data_page2) = MAGIC_VAL_2; 1170 install_ept(pml4, (unsigned long)data_page1, (unsigned long)data_page2, 1171 EPT_RA | EPT_WA | EPT_EA); 1172 1173 apic_version = apic_read(APIC_LVR); 1174 1175 ret = pci_find_dev(PCI_VENDOR_ID_REDHAT, PCI_DEVICE_ID_REDHAT_TEST); 1176 if (ret != PCIDEVADDR_INVALID) { 1177 pci_dev_init(&pcidev, ret); 1178 pci_physaddr = pcidev.resource[PCI_TESTDEV_BAR_MEM]; 1179 } 1180 1181 return VMX_TEST_START; 1182 } 1183 1184 static int ept_init(struct vmcs *vmcs) 1185 { 1186 return ept_init_common(false); 1187 } 1188 1189 static void ept_common(void) 1190 { 1191 vmx_set_test_stage(0); 1192 if (*((u32 *)data_page2) != MAGIC_VAL_1 || 1193 *((u32 *)data_page1) != MAGIC_VAL_1) 1194 report_fail("EPT basic framework - read"); 1195 else { 1196 *((u32 *)data_page2) = MAGIC_VAL_3; 1197 vmcall(); 1198 if (vmx_get_test_stage() == 1) { 1199 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1200 *((u32 *)data_page2) == MAGIC_VAL_2) 1201 report_pass("EPT basic framework"); 1202 else 1203 report_pass("EPT basic framework - remap"); 1204 } 1205 } 1206 // Test EPT Misconfigurations 1207 vmx_set_test_stage(1); 1208 vmcall(); 1209 *((u32 *)data_page1) = MAGIC_VAL_1; 1210 if (vmx_get_test_stage() != 2) { 1211 report_fail("EPT misconfigurations"); 1212 goto t1; 1213 } 1214 vmx_set_test_stage(2); 1215 vmcall(); 1216 *((u32 *)data_page1) = MAGIC_VAL_1; 1217 report(vmx_get_test_stage() == 3, "EPT misconfigurations"); 1218 t1: 1219 // Test EPT violation 1220 vmx_set_test_stage(3); 1221 vmcall(); 1222 *((u32 *)data_page1) = MAGIC_VAL_1; 1223 report(vmx_get_test_stage() == 4, "EPT violation - page permission"); 1224 // Violation caused by EPT paging structure 1225 vmx_set_test_stage(4); 1226 vmcall(); 1227 *((u32 *)data_page1) = MAGIC_VAL_2; 1228 report(vmx_get_test_stage() == 5, "EPT violation - paging structure"); 1229 1230 // MMIO Read/Write 1231 vmx_set_test_stage(5); 1232 vmcall(); 1233 1234 *(u32 volatile *)pci_physaddr; 1235 report(vmx_get_test_stage() == 6, "MMIO EPT violation - read"); 1236 1237 *(u32 volatile *)pci_physaddr = MAGIC_VAL_1; 1238 report(vmx_get_test_stage() == 7, "MMIO EPT violation - write"); 1239 } 1240 1241 static void ept_main(void) 1242 { 1243 ept_common(); 1244 1245 // Test EPT access to L1 MMIO 1246 vmx_set_test_stage(7); 1247 report(*((u32 *)0xfee00030UL) == apic_version, "EPT - MMIO access"); 1248 1249 // Test invalid operand for INVEPT 1250 vmcall(); 1251 report(vmx_get_test_stage() == 8, "EPT - unsupported INVEPT"); 1252 } 1253 1254 static bool invept_test(int type, u64 eptp) 1255 { 1256 bool ret, supported; 1257 1258 supported = ept_vpid.val & (EPT_CAP_INVEPT_SINGLE >> INVEPT_SINGLE << type); 1259 ret = __invept(type, eptp); 1260 1261 if (ret == !supported) 1262 return false; 1263 1264 if (!supported) 1265 printf("WARNING: unsupported invept passed!\n"); 1266 else 1267 printf("WARNING: invept failed!\n"); 1268 1269 return true; 1270 } 1271 1272 static int pml_exit_handler(union exit_reason exit_reason) 1273 { 1274 u16 index, count; 1275 u64 *pmlbuf = pml_log; 1276 u64 guest_rip = vmcs_read(GUEST_RIP);; 1277 u64 guest_cr3 = vmcs_read(GUEST_CR3); 1278 u32 insn_len = vmcs_read(EXI_INST_LEN); 1279 1280 switch (exit_reason.basic) { 1281 case VMX_VMCALL: 1282 switch (vmx_get_test_stage()) { 1283 case 0: 1284 index = vmcs_read(GUEST_PML_INDEX); 1285 for (count = index + 1; count < PML_INDEX; count++) { 1286 if (pmlbuf[count] == (u64)data_page2) { 1287 vmx_inc_test_stage(); 1288 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1289 break; 1290 } 1291 } 1292 break; 1293 case 1: 1294 index = vmcs_read(GUEST_PML_INDEX); 1295 /* Keep clearing the dirty bit till a overflow */ 1296 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1297 break; 1298 default: 1299 report_fail("unexpected stage, %d.", 1300 vmx_get_test_stage()); 1301 print_vmexit_info(exit_reason); 1302 return VMX_TEST_VMEXIT; 1303 } 1304 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1305 return VMX_TEST_RESUME; 1306 case VMX_PML_FULL: 1307 vmx_inc_test_stage(); 1308 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1309 return VMX_TEST_RESUME; 1310 default: 1311 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 1312 print_vmexit_info(exit_reason); 1313 } 1314 return VMX_TEST_VMEXIT; 1315 } 1316 1317 static int ept_exit_handler_common(union exit_reason exit_reason, bool have_ad) 1318 { 1319 u64 guest_rip; 1320 u64 guest_cr3; 1321 u32 insn_len; 1322 u32 exit_qual; 1323 static unsigned long data_page1_pte, data_page1_pte_pte, memaddr_pte, 1324 guest_pte_addr; 1325 1326 guest_rip = vmcs_read(GUEST_RIP); 1327 guest_cr3 = vmcs_read(GUEST_CR3); 1328 insn_len = vmcs_read(EXI_INST_LEN); 1329 exit_qual = vmcs_read(EXI_QUALIFICATION); 1330 pteval_t *ptep; 1331 switch (exit_reason.basic) { 1332 case VMX_VMCALL: 1333 switch (vmx_get_test_stage()) { 1334 case 0: 1335 check_ept_ad(pml4, guest_cr3, 1336 (unsigned long)data_page1, 1337 have_ad ? EPT_ACCESS_FLAG : 0, 1338 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1339 check_ept_ad(pml4, guest_cr3, 1340 (unsigned long)data_page2, 1341 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0, 1342 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1343 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1344 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1345 if (have_ad) 1346 invept(INVEPT_SINGLE, eptp); 1347 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1348 *((u32 *)data_page2) == MAGIC_VAL_2) { 1349 vmx_inc_test_stage(); 1350 install_ept(pml4, (unsigned long)data_page2, 1351 (unsigned long)data_page2, 1352 EPT_RA | EPT_WA | EPT_EA); 1353 } else 1354 report_fail("EPT basic framework - write"); 1355 break; 1356 case 1: 1357 install_ept(pml4, (unsigned long)data_page1, 1358 (unsigned long)data_page1, EPT_WA); 1359 invept(INVEPT_SINGLE, eptp); 1360 break; 1361 case 2: 1362 install_ept(pml4, (unsigned long)data_page1, 1363 (unsigned long)data_page1, 1364 EPT_RA | EPT_WA | EPT_EA | 1365 (2 << EPT_MEM_TYPE_SHIFT)); 1366 invept(INVEPT_SINGLE, eptp); 1367 break; 1368 case 3: 1369 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1370 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)data_page1, 1371 1, &data_page1_pte)); 1372 set_ept_pte(pml4, (unsigned long)data_page1, 1373 1, data_page1_pte & ~EPT_PRESENT); 1374 invept(INVEPT_SINGLE, eptp); 1375 break; 1376 case 4: 1377 ptep = get_pte_level((pgd_t *)guest_cr3, data_page1, /*level=*/2); 1378 guest_pte_addr = virt_to_phys(ptep) & PAGE_MASK; 1379 1380 TEST_ASSERT(get_ept_pte(pml4, guest_pte_addr, 2, &data_page1_pte_pte)); 1381 set_ept_pte(pml4, guest_pte_addr, 2, 1382 data_page1_pte_pte & ~EPT_PRESENT); 1383 invept(INVEPT_SINGLE, eptp); 1384 break; 1385 case 5: 1386 install_ept(pml4, (unsigned long)pci_physaddr, 1387 (unsigned long)pci_physaddr, 0); 1388 invept(INVEPT_SINGLE, eptp); 1389 break; 1390 case 7: 1391 if (!invept_test(0, eptp)) 1392 vmx_inc_test_stage(); 1393 break; 1394 // Should not reach here 1395 default: 1396 report_fail("ERROR - unexpected stage, %d.", 1397 vmx_get_test_stage()); 1398 print_vmexit_info(exit_reason); 1399 return VMX_TEST_VMEXIT; 1400 } 1401 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1402 return VMX_TEST_RESUME; 1403 case VMX_EPT_MISCONFIG: 1404 switch (vmx_get_test_stage()) { 1405 case 1: 1406 case 2: 1407 vmx_inc_test_stage(); 1408 install_ept(pml4, (unsigned long)data_page1, 1409 (unsigned long)data_page1, 1410 EPT_RA | EPT_WA | EPT_EA); 1411 invept(INVEPT_SINGLE, eptp); 1412 break; 1413 // Should not reach here 1414 default: 1415 report_fail("ERROR - unexpected stage, %d.", 1416 vmx_get_test_stage()); 1417 print_vmexit_info(exit_reason); 1418 return VMX_TEST_VMEXIT; 1419 } 1420 return VMX_TEST_RESUME; 1421 case VMX_EPT_VIOLATION: 1422 /* 1423 * Exit-qualifications are masked not to account for advanced 1424 * VM-exit information. Once KVM supports this feature, this 1425 * masking should be removed. 1426 */ 1427 exit_qual &= ~EPT_VLT_GUEST_MASK; 1428 1429 switch(vmx_get_test_stage()) { 1430 case 3: 1431 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1432 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1433 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1434 if (exit_qual == (EPT_VLT_WR | EPT_VLT_LADDR_VLD | 1435 EPT_VLT_PADDR)) 1436 vmx_inc_test_stage(); 1437 set_ept_pte(pml4, (unsigned long)data_page1, 1438 1, data_page1_pte | (EPT_PRESENT)); 1439 invept(INVEPT_SINGLE, eptp); 1440 break; 1441 case 4: 1442 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1443 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1444 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1445 if (exit_qual == (EPT_VLT_RD | 1446 (have_ad ? EPT_VLT_WR : 0) | 1447 EPT_VLT_LADDR_VLD)) 1448 vmx_inc_test_stage(); 1449 set_ept_pte(pml4, guest_pte_addr, 2, 1450 data_page1_pte_pte | (EPT_PRESENT)); 1451 invept(INVEPT_SINGLE, eptp); 1452 break; 1453 case 5: 1454 if (exit_qual & EPT_VLT_RD) 1455 vmx_inc_test_stage(); 1456 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1457 1, &memaddr_pte)); 1458 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA); 1459 invept(INVEPT_SINGLE, eptp); 1460 break; 1461 case 6: 1462 if (exit_qual & EPT_VLT_WR) 1463 vmx_inc_test_stage(); 1464 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1465 1, &memaddr_pte)); 1466 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA | EPT_WA); 1467 invept(INVEPT_SINGLE, eptp); 1468 break; 1469 default: 1470 // Should not reach here 1471 report_fail("ERROR : unexpected stage, %d", 1472 vmx_get_test_stage()); 1473 print_vmexit_info(exit_reason); 1474 return VMX_TEST_VMEXIT; 1475 } 1476 return VMX_TEST_RESUME; 1477 default: 1478 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 1479 print_vmexit_info(exit_reason); 1480 } 1481 return VMX_TEST_VMEXIT; 1482 } 1483 1484 static int ept_exit_handler(union exit_reason exit_reason) 1485 { 1486 return ept_exit_handler_common(exit_reason, false); 1487 } 1488 1489 static int eptad_init(struct vmcs *vmcs) 1490 { 1491 int r = ept_init_common(true); 1492 1493 if (r == VMX_TEST_EXIT) 1494 return r; 1495 1496 if (!ept_ad_bits_supported()) { 1497 printf("\tEPT A/D bits are not supported"); 1498 return VMX_TEST_EXIT; 1499 } 1500 1501 return r; 1502 } 1503 1504 static int pml_init(struct vmcs *vmcs) 1505 { 1506 u32 ctrl_cpu; 1507 int r = eptad_init(vmcs); 1508 1509 if (r == VMX_TEST_EXIT) 1510 return r; 1511 1512 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1513 !(ctrl_cpu_rev[1].clr & CPU_PML)) { 1514 printf("\tPML is not supported"); 1515 return VMX_TEST_EXIT; 1516 } 1517 1518 pml_log = alloc_page(); 1519 vmcs_write(PMLADDR, (u64)pml_log); 1520 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1521 1522 ctrl_cpu = vmcs_read(CPU_EXEC_CTRL1) | CPU_PML; 1523 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu); 1524 1525 return VMX_TEST_START; 1526 } 1527 1528 static void pml_main(void) 1529 { 1530 int count = 0; 1531 1532 vmx_set_test_stage(0); 1533 *((u32 *)data_page2) = 0x1; 1534 vmcall(); 1535 report(vmx_get_test_stage() == 1, "PML - Dirty GPA Logging"); 1536 1537 while (vmx_get_test_stage() == 1) { 1538 vmcall(); 1539 *((u32 *)data_page2) = 0x1; 1540 if (count++ > PML_INDEX) 1541 break; 1542 } 1543 report(vmx_get_test_stage() == 2, "PML Full Event"); 1544 } 1545 1546 static void eptad_main(void) 1547 { 1548 ept_common(); 1549 } 1550 1551 static int eptad_exit_handler(union exit_reason exit_reason) 1552 { 1553 return ept_exit_handler_common(exit_reason, true); 1554 } 1555 1556 #define TIMER_VECTOR 222 1557 1558 static volatile bool timer_fired; 1559 1560 static void timer_isr(isr_regs_t *regs) 1561 { 1562 timer_fired = true; 1563 apic_write(APIC_EOI, 0); 1564 } 1565 1566 static int interrupt_init(struct vmcs *vmcs) 1567 { 1568 msr_bmp_init(); 1569 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1570 handle_irq(TIMER_VECTOR, timer_isr); 1571 return VMX_TEST_START; 1572 } 1573 1574 static void interrupt_main(void) 1575 { 1576 long long start, loops; 1577 1578 vmx_set_test_stage(0); 1579 1580 apic_write(APIC_LVTT, TIMER_VECTOR); 1581 irq_enable(); 1582 1583 apic_write(APIC_TMICT, 1); 1584 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1585 asm volatile ("nop"); 1586 report(timer_fired, "direct interrupt while running guest"); 1587 1588 apic_write(APIC_TMICT, 0); 1589 irq_disable(); 1590 vmcall(); 1591 timer_fired = false; 1592 apic_write(APIC_TMICT, 1); 1593 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1594 asm volatile ("nop"); 1595 report(timer_fired, "intercepted interrupt while running guest"); 1596 1597 irq_enable(); 1598 apic_write(APIC_TMICT, 0); 1599 irq_disable(); 1600 vmcall(); 1601 timer_fired = false; 1602 start = rdtsc(); 1603 apic_write(APIC_TMICT, 1000000); 1604 1605 safe_halt(); 1606 1607 report(rdtsc() - start > 1000000 && timer_fired, 1608 "direct interrupt + hlt"); 1609 1610 apic_write(APIC_TMICT, 0); 1611 irq_disable(); 1612 vmcall(); 1613 timer_fired = false; 1614 start = rdtsc(); 1615 apic_write(APIC_TMICT, 1000000); 1616 1617 safe_halt(); 1618 1619 report(rdtsc() - start > 10000 && timer_fired, 1620 "intercepted interrupt + hlt"); 1621 1622 apic_write(APIC_TMICT, 0); 1623 irq_disable(); 1624 vmcall(); 1625 timer_fired = false; 1626 start = rdtsc(); 1627 apic_write(APIC_TMICT, 1000000); 1628 1629 irq_enable(); 1630 asm volatile ("nop"); 1631 vmcall(); 1632 1633 report(rdtsc() - start > 10000 && timer_fired, 1634 "direct interrupt + activity state hlt"); 1635 1636 apic_write(APIC_TMICT, 0); 1637 irq_disable(); 1638 vmcall(); 1639 timer_fired = false; 1640 start = rdtsc(); 1641 apic_write(APIC_TMICT, 1000000); 1642 1643 irq_enable(); 1644 asm volatile ("nop"); 1645 vmcall(); 1646 1647 report(rdtsc() - start > 10000 && timer_fired, 1648 "intercepted interrupt + activity state hlt"); 1649 1650 apic_write(APIC_TMICT, 0); 1651 irq_disable(); 1652 vmx_set_test_stage(7); 1653 vmcall(); 1654 timer_fired = false; 1655 apic_write(APIC_TMICT, 1); 1656 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1657 asm volatile ("nop"); 1658 report(timer_fired, 1659 "running a guest with interrupt acknowledgement set"); 1660 1661 apic_write(APIC_TMICT, 0); 1662 irq_enable(); 1663 timer_fired = false; 1664 vmcall(); 1665 report(timer_fired, "Inject an event to a halted guest"); 1666 } 1667 1668 static int interrupt_exit_handler(union exit_reason exit_reason) 1669 { 1670 u64 guest_rip = vmcs_read(GUEST_RIP); 1671 u32 insn_len = vmcs_read(EXI_INST_LEN); 1672 1673 switch (exit_reason.basic) { 1674 case VMX_VMCALL: 1675 switch (vmx_get_test_stage()) { 1676 case 0: 1677 case 2: 1678 case 5: 1679 vmcs_write(PIN_CONTROLS, 1680 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1681 break; 1682 case 7: 1683 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_INTA); 1684 vmcs_write(PIN_CONTROLS, 1685 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1686 break; 1687 case 1: 1688 case 3: 1689 vmcs_write(PIN_CONTROLS, 1690 vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1691 break; 1692 case 4: 1693 case 6: 1694 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1695 break; 1696 1697 case 8: 1698 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1699 vmcs_write(ENT_INTR_INFO, 1700 TIMER_VECTOR | 1701 (VMX_INTR_TYPE_EXT_INTR << INTR_INFO_INTR_TYPE_SHIFT) | 1702 INTR_INFO_VALID_MASK); 1703 break; 1704 } 1705 vmx_inc_test_stage(); 1706 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1707 return VMX_TEST_RESUME; 1708 case VMX_EXTINT: 1709 if (vmcs_read(EXI_CONTROLS) & EXI_INTA) { 1710 int vector = vmcs_read(EXI_INTR_INFO) & 0xff; 1711 handle_external_interrupt(vector); 1712 } else { 1713 irq_enable(); 1714 asm volatile ("nop"); 1715 irq_disable(); 1716 } 1717 if (vmx_get_test_stage() >= 2) 1718 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 1719 return VMX_TEST_RESUME; 1720 default: 1721 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 1722 print_vmexit_info(exit_reason); 1723 } 1724 1725 return VMX_TEST_VMEXIT; 1726 } 1727 1728 1729 static volatile int nmi_fired; 1730 1731 #define NMI_DELAY 100000000ULL 1732 1733 static void nmi_isr(isr_regs_t *regs) 1734 { 1735 nmi_fired = true; 1736 } 1737 1738 static int nmi_hlt_init(struct vmcs *vmcs) 1739 { 1740 msr_bmp_init(); 1741 handle_irq(NMI_VECTOR, nmi_isr); 1742 vmcs_write(PIN_CONTROLS, 1743 vmcs_read(PIN_CONTROLS) & ~PIN_NMI); 1744 vmcs_write(PIN_CONTROLS, 1745 vmcs_read(PIN_CONTROLS) & ~PIN_VIRT_NMI); 1746 return VMX_TEST_START; 1747 } 1748 1749 static void nmi_message_thread(void *data) 1750 { 1751 while (vmx_get_test_stage() != 1) 1752 pause(); 1753 1754 delay(NMI_DELAY); 1755 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_NMI | APIC_INT_ASSERT, id_map[0]); 1756 1757 while (vmx_get_test_stage() != 2) 1758 pause(); 1759 1760 delay(NMI_DELAY); 1761 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_NMI | APIC_INT_ASSERT, id_map[0]); 1762 } 1763 1764 static void nmi_hlt_main(void) 1765 { 1766 long long start; 1767 1768 if (cpu_count() < 2) { 1769 report_skip(__func__); 1770 vmx_set_test_stage(-1); 1771 return; 1772 } 1773 1774 vmx_set_test_stage(0); 1775 on_cpu_async(1, nmi_message_thread, NULL); 1776 start = rdtsc(); 1777 vmx_set_test_stage(1); 1778 asm volatile ("hlt"); 1779 report((rdtsc() - start > NMI_DELAY) && nmi_fired, 1780 "direct NMI + hlt"); 1781 if (!nmi_fired) 1782 vmx_set_test_stage(-1); 1783 nmi_fired = false; 1784 1785 vmcall(); 1786 1787 start = rdtsc(); 1788 vmx_set_test_stage(2); 1789 asm volatile ("hlt"); 1790 report((rdtsc() - start > NMI_DELAY) && !nmi_fired, 1791 "intercepted NMI + hlt"); 1792 if (nmi_fired) { 1793 report(!nmi_fired, "intercepted NMI was dispatched"); 1794 vmx_set_test_stage(-1); 1795 return; 1796 } 1797 vmx_set_test_stage(3); 1798 } 1799 1800 static int nmi_hlt_exit_handler(union exit_reason exit_reason) 1801 { 1802 u64 guest_rip = vmcs_read(GUEST_RIP); 1803 u32 insn_len = vmcs_read(EXI_INST_LEN); 1804 1805 switch (vmx_get_test_stage()) { 1806 case 1: 1807 if (exit_reason.basic != VMX_VMCALL) { 1808 report_fail("VMEXIT not due to vmcall. Exit reason 0x%x", 1809 exit_reason.full); 1810 print_vmexit_info(exit_reason); 1811 return VMX_TEST_VMEXIT; 1812 } 1813 1814 vmcs_write(PIN_CONTROLS, 1815 vmcs_read(PIN_CONTROLS) | PIN_NMI); 1816 vmcs_write(PIN_CONTROLS, 1817 vmcs_read(PIN_CONTROLS) | PIN_VIRT_NMI); 1818 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1819 break; 1820 1821 case 2: 1822 if (exit_reason.basic != VMX_EXC_NMI) { 1823 report_fail("VMEXIT not due to NMI intercept. Exit reason 0x%x", 1824 exit_reason.full); 1825 print_vmexit_info(exit_reason); 1826 return VMX_TEST_VMEXIT; 1827 } 1828 report_pass("NMI intercept while running guest"); 1829 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 1830 break; 1831 1832 case 3: 1833 break; 1834 1835 default: 1836 return VMX_TEST_VMEXIT; 1837 } 1838 1839 if (vmx_get_test_stage() == 3) 1840 return VMX_TEST_VMEXIT; 1841 1842 return VMX_TEST_RESUME; 1843 } 1844 1845 1846 static int dbgctls_init(struct vmcs *vmcs) 1847 { 1848 u64 dr7 = 0x402; 1849 u64 zero = 0; 1850 1851 msr_bmp_init(); 1852 asm volatile( 1853 "mov %0,%%dr0\n\t" 1854 "mov %0,%%dr1\n\t" 1855 "mov %0,%%dr2\n\t" 1856 "mov %1,%%dr7\n\t" 1857 : : "r" (zero), "r" (dr7)); 1858 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1859 vmcs_write(GUEST_DR7, 0x404); 1860 vmcs_write(GUEST_DEBUGCTL, 0x2); 1861 1862 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 1863 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_SAVE_DBGCTLS); 1864 1865 return VMX_TEST_START; 1866 } 1867 1868 static void dbgctls_main(void) 1869 { 1870 u64 dr7, debugctl; 1871 1872 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1873 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1874 /* Commented out: KVM does not support DEBUGCTL so far */ 1875 (void)debugctl; 1876 report(dr7 == 0x404, "Load debug controls" /* && debugctl == 0x2 */); 1877 1878 dr7 = 0x408; 1879 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1880 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1881 1882 vmx_set_test_stage(0); 1883 vmcall(); 1884 report(vmx_get_test_stage() == 1, "Save debug controls"); 1885 1886 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS || 1887 ctrl_exit_rev.set & EXI_SAVE_DBGCTLS) { 1888 printf("\tDebug controls are always loaded/saved\n"); 1889 return; 1890 } 1891 vmx_set_test_stage(2); 1892 vmcall(); 1893 1894 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1895 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1896 /* Commented out: KVM does not support DEBUGCTL so far */ 1897 (void)debugctl; 1898 report(dr7 == 0x402, 1899 "Guest=host debug controls" /* && debugctl == 0x1 */); 1900 1901 dr7 = 0x408; 1902 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1903 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1904 1905 vmx_set_test_stage(3); 1906 vmcall(); 1907 report(vmx_get_test_stage() == 4, "Don't save debug controls"); 1908 } 1909 1910 static int dbgctls_exit_handler(union exit_reason exit_reason) 1911 { 1912 u32 insn_len = vmcs_read(EXI_INST_LEN); 1913 u64 guest_rip = vmcs_read(GUEST_RIP); 1914 u64 dr7, debugctl; 1915 1916 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1917 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1918 1919 switch (exit_reason.basic) { 1920 case VMX_VMCALL: 1921 switch (vmx_get_test_stage()) { 1922 case 0: 1923 if (dr7 == 0x400 && debugctl == 0 && 1924 vmcs_read(GUEST_DR7) == 0x408 /* && 1925 Commented out: KVM does not support DEBUGCTL so far 1926 vmcs_read(GUEST_DEBUGCTL) == 0x3 */) 1927 vmx_inc_test_stage(); 1928 break; 1929 case 2: 1930 dr7 = 0x402; 1931 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1932 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1933 vmcs_write(GUEST_DR7, 0x404); 1934 vmcs_write(GUEST_DEBUGCTL, 0x2); 1935 1936 vmcs_write(ENT_CONTROLS, 1937 vmcs_read(ENT_CONTROLS) & ~ENT_LOAD_DBGCTLS); 1938 vmcs_write(EXI_CONTROLS, 1939 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_DBGCTLS); 1940 break; 1941 case 3: 1942 if (dr7 == 0x400 && debugctl == 0 && 1943 vmcs_read(GUEST_DR7) == 0x404 /* && 1944 Commented out: KVM does not support DEBUGCTL so far 1945 vmcs_read(GUEST_DEBUGCTL) == 0x2 */) 1946 vmx_inc_test_stage(); 1947 break; 1948 } 1949 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1950 return VMX_TEST_RESUME; 1951 default: 1952 report_fail("Unknown exit reason, %d", exit_reason.full); 1953 print_vmexit_info(exit_reason); 1954 } 1955 return VMX_TEST_VMEXIT; 1956 } 1957 1958 struct vmx_msr_entry { 1959 u32 index; 1960 u32 reserved; 1961 u64 value; 1962 } __attribute__((packed)); 1963 1964 #define MSR_MAGIC 0x31415926 1965 struct vmx_msr_entry *exit_msr_store, *entry_msr_load, *exit_msr_load; 1966 1967 static int msr_switch_init(struct vmcs *vmcs) 1968 { 1969 msr_bmp_init(); 1970 exit_msr_store = alloc_page(); 1971 exit_msr_load = alloc_page(); 1972 entry_msr_load = alloc_page(); 1973 entry_msr_load[0].index = MSR_KERNEL_GS_BASE; 1974 entry_msr_load[0].value = MSR_MAGIC; 1975 1976 vmx_set_test_stage(1); 1977 vmcs_write(ENT_MSR_LD_CNT, 1); 1978 vmcs_write(ENTER_MSR_LD_ADDR, (u64)entry_msr_load); 1979 vmcs_write(EXI_MSR_ST_CNT, 1); 1980 vmcs_write(EXIT_MSR_ST_ADDR, (u64)exit_msr_store); 1981 vmcs_write(EXI_MSR_LD_CNT, 1); 1982 vmcs_write(EXIT_MSR_LD_ADDR, (u64)exit_msr_load); 1983 return VMX_TEST_START; 1984 } 1985 1986 static void msr_switch_main(void) 1987 { 1988 if (vmx_get_test_stage() == 1) { 1989 report(rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC, 1990 "VM entry MSR load"); 1991 vmx_set_test_stage(2); 1992 wrmsr(MSR_KERNEL_GS_BASE, MSR_MAGIC + 1); 1993 exit_msr_store[0].index = MSR_KERNEL_GS_BASE; 1994 exit_msr_load[0].index = MSR_KERNEL_GS_BASE; 1995 exit_msr_load[0].value = MSR_MAGIC + 2; 1996 } 1997 vmcall(); 1998 } 1999 2000 static int msr_switch_exit_handler(union exit_reason exit_reason) 2001 { 2002 if (exit_reason.basic == VMX_VMCALL && vmx_get_test_stage() == 2) { 2003 report(exit_msr_store[0].value == MSR_MAGIC + 1, 2004 "VM exit MSR store"); 2005 report(rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC + 2, 2006 "VM exit MSR load"); 2007 vmx_set_test_stage(3); 2008 entry_msr_load[0].index = MSR_FS_BASE; 2009 return VMX_TEST_RESUME; 2010 } 2011 printf("ERROR %s: unexpected stage=%u or reason=0x%x\n", 2012 __func__, vmx_get_test_stage(), exit_reason.full); 2013 return VMX_TEST_EXIT; 2014 } 2015 2016 static int msr_switch_entry_failure(struct vmentry_result *result) 2017 { 2018 if (result->vm_fail) { 2019 printf("ERROR %s: VM-Fail on %s\n", __func__, result->instr); 2020 return VMX_TEST_EXIT; 2021 } 2022 2023 if (result->exit_reason.failed_vmentry && 2024 result->exit_reason.basic == VMX_FAIL_MSR && 2025 vmx_get_test_stage() == 3) { 2026 report(vmcs_read(EXI_QUALIFICATION) == 1, 2027 "VM entry MSR load: try to load FS_BASE"); 2028 return VMX_TEST_VMEXIT; 2029 } 2030 printf("ERROR %s: unexpected stage=%u or reason=%x\n", 2031 __func__, vmx_get_test_stage(), result->exit_reason.full); 2032 return VMX_TEST_EXIT; 2033 } 2034 2035 static int vmmcall_init(struct vmcs *vmcs) 2036 { 2037 vmcs_write(EXC_BITMAP, 1 << UD_VECTOR); 2038 return VMX_TEST_START; 2039 } 2040 2041 static void vmmcall_main(void) 2042 { 2043 asm volatile( 2044 "mov $0xABCD, %%rax\n\t" 2045 "vmmcall\n\t" 2046 ::: "rax"); 2047 2048 report_fail("VMMCALL"); 2049 } 2050 2051 static int vmmcall_exit_handler(union exit_reason exit_reason) 2052 { 2053 switch (exit_reason.basic) { 2054 case VMX_VMCALL: 2055 printf("here\n"); 2056 report_fail("VMMCALL triggers #UD"); 2057 break; 2058 case VMX_EXC_NMI: 2059 report((vmcs_read(EXI_INTR_INFO) & 0xff) == UD_VECTOR, 2060 "VMMCALL triggers #UD"); 2061 break; 2062 default: 2063 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 2064 print_vmexit_info(exit_reason); 2065 } 2066 2067 return VMX_TEST_VMEXIT; 2068 } 2069 2070 static int disable_rdtscp_init(struct vmcs *vmcs) 2071 { 2072 u32 ctrl_cpu1; 2073 2074 if (ctrl_cpu_rev[0].clr & CPU_SECONDARY) { 2075 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 2076 ctrl_cpu1 &= ~CPU_RDTSCP; 2077 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 2078 } 2079 2080 return VMX_TEST_START; 2081 } 2082 2083 static void disable_rdtscp_ud_handler(struct ex_regs *regs) 2084 { 2085 switch (vmx_get_test_stage()) { 2086 case 0: 2087 report_pass("RDTSCP triggers #UD"); 2088 vmx_inc_test_stage(); 2089 regs->rip += 3; 2090 break; 2091 case 2: 2092 report_pass("RDPID triggers #UD"); 2093 vmx_inc_test_stage(); 2094 regs->rip += 4; 2095 break; 2096 } 2097 return; 2098 2099 } 2100 2101 static void disable_rdtscp_main(void) 2102 { 2103 /* Test that #UD is properly injected in L2. */ 2104 handle_exception(UD_VECTOR, disable_rdtscp_ud_handler); 2105 2106 vmx_set_test_stage(0); 2107 asm volatile("rdtscp" : : : "eax", "ecx", "edx"); 2108 vmcall(); 2109 asm volatile(".byte 0xf3, 0x0f, 0xc7, 0xf8" : : : "eax"); 2110 2111 handle_exception(UD_VECTOR, 0); 2112 vmcall(); 2113 } 2114 2115 static int disable_rdtscp_exit_handler(union exit_reason exit_reason) 2116 { 2117 switch (exit_reason.basic) { 2118 case VMX_VMCALL: 2119 switch (vmx_get_test_stage()) { 2120 case 0: 2121 report_fail("RDTSCP triggers #UD"); 2122 vmx_inc_test_stage(); 2123 /* fallthrough */ 2124 case 1: 2125 vmx_inc_test_stage(); 2126 vmcs_write(GUEST_RIP, vmcs_read(GUEST_RIP) + 3); 2127 return VMX_TEST_RESUME; 2128 case 2: 2129 report_fail("RDPID triggers #UD"); 2130 break; 2131 } 2132 break; 2133 2134 default: 2135 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 2136 print_vmexit_info(exit_reason); 2137 } 2138 return VMX_TEST_VMEXIT; 2139 } 2140 2141 static int int3_init(struct vmcs *vmcs) 2142 { 2143 vmcs_write(EXC_BITMAP, ~0u); 2144 return VMX_TEST_START; 2145 } 2146 2147 static void int3_guest_main(void) 2148 { 2149 asm volatile ("int3"); 2150 } 2151 2152 static int int3_exit_handler(union exit_reason exit_reason) 2153 { 2154 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2155 2156 report(exit_reason.basic == VMX_EXC_NMI && 2157 (intr_info & INTR_INFO_VALID_MASK) && 2158 (intr_info & INTR_INFO_VECTOR_MASK) == BP_VECTOR && 2159 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2160 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION, 2161 "L1 intercepts #BP"); 2162 2163 return VMX_TEST_VMEXIT; 2164 } 2165 2166 static int into_init(struct vmcs *vmcs) 2167 { 2168 vmcs_write(EXC_BITMAP, ~0u); 2169 return VMX_TEST_START; 2170 } 2171 2172 static void into_guest_main(void) 2173 { 2174 struct far_pointer32 fp = { 2175 .offset = (uintptr_t)&&into, 2176 .selector = KERNEL_CS32, 2177 }; 2178 uintptr_t rsp; 2179 2180 asm volatile ("mov %%rsp, %0" : "=r"(rsp)); 2181 2182 if (fp.offset != (uintptr_t)&&into) { 2183 printf("Code address too high.\n"); 2184 return; 2185 } 2186 if ((u32)rsp != rsp) { 2187 printf("Stack address too high.\n"); 2188 return; 2189 } 2190 2191 asm goto ("lcall *%0" : : "m" (fp) : "rax" : into); 2192 return; 2193 into: 2194 asm volatile (".code32;" 2195 "movl $0x7fffffff, %eax;" 2196 "addl %eax, %eax;" 2197 "into;" 2198 "lret;" 2199 ".code64"); 2200 __builtin_unreachable(); 2201 } 2202 2203 static int into_exit_handler(union exit_reason exit_reason) 2204 { 2205 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2206 2207 report(exit_reason.basic == VMX_EXC_NMI && 2208 (intr_info & INTR_INFO_VALID_MASK) && 2209 (intr_info & INTR_INFO_VECTOR_MASK) == OF_VECTOR && 2210 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2211 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION, 2212 "L1 intercepts #OF"); 2213 2214 return VMX_TEST_VMEXIT; 2215 } 2216 2217 static void exit_monitor_from_l2_main(void) 2218 { 2219 printf("Calling exit(0) from l2...\n"); 2220 exit(0); 2221 } 2222 2223 static int exit_monitor_from_l2_handler(union exit_reason exit_reason) 2224 { 2225 report_fail("The guest should have killed the VMM"); 2226 return VMX_TEST_EXIT; 2227 } 2228 2229 static void assert_exit_reason(u64 expected) 2230 { 2231 u64 actual = vmcs_read(EXI_REASON); 2232 2233 TEST_ASSERT_EQ_MSG(expected, actual, "Expected %s, got %s.", 2234 exit_reason_description(expected), 2235 exit_reason_description(actual)); 2236 } 2237 2238 static void skip_exit_insn(void) 2239 { 2240 u64 guest_rip = vmcs_read(GUEST_RIP); 2241 u32 insn_len = vmcs_read(EXI_INST_LEN); 2242 vmcs_write(GUEST_RIP, guest_rip + insn_len); 2243 } 2244 2245 static void skip_exit_vmcall(void) 2246 { 2247 assert_exit_reason(VMX_VMCALL); 2248 skip_exit_insn(); 2249 } 2250 2251 static void v2_null_test_guest(void) 2252 { 2253 } 2254 2255 static void v2_null_test(void) 2256 { 2257 test_set_guest(v2_null_test_guest); 2258 enter_guest(); 2259 report_pass(__func__); 2260 } 2261 2262 static void v2_multiple_entries_test_guest(void) 2263 { 2264 vmx_set_test_stage(1); 2265 vmcall(); 2266 vmx_set_test_stage(2); 2267 } 2268 2269 static void v2_multiple_entries_test(void) 2270 { 2271 test_set_guest(v2_multiple_entries_test_guest); 2272 enter_guest(); 2273 TEST_ASSERT_EQ(vmx_get_test_stage(), 1); 2274 skip_exit_vmcall(); 2275 enter_guest(); 2276 TEST_ASSERT_EQ(vmx_get_test_stage(), 2); 2277 report_pass(__func__); 2278 } 2279 2280 static int fixture_test_data = 1; 2281 2282 static void fixture_test_teardown(void *data) 2283 { 2284 *((int *) data) = 1; 2285 } 2286 2287 static void fixture_test_guest(void) 2288 { 2289 fixture_test_data++; 2290 } 2291 2292 2293 static void fixture_test_setup(void) 2294 { 2295 TEST_ASSERT_EQ_MSG(1, fixture_test_data, 2296 "fixture_test_teardown didn't run?!"); 2297 fixture_test_data = 2; 2298 test_add_teardown(fixture_test_teardown, &fixture_test_data); 2299 test_set_guest(fixture_test_guest); 2300 } 2301 2302 static void fixture_test_case1(void) 2303 { 2304 fixture_test_setup(); 2305 TEST_ASSERT_EQ(2, fixture_test_data); 2306 enter_guest(); 2307 TEST_ASSERT_EQ(3, fixture_test_data); 2308 report_pass(__func__); 2309 } 2310 2311 static void fixture_test_case2(void) 2312 { 2313 fixture_test_setup(); 2314 TEST_ASSERT_EQ(2, fixture_test_data); 2315 enter_guest(); 2316 TEST_ASSERT_EQ(3, fixture_test_data); 2317 report_pass(__func__); 2318 } 2319 2320 enum ept_access_op { 2321 OP_READ, 2322 OP_WRITE, 2323 OP_EXEC, 2324 OP_FLUSH_TLB, 2325 OP_EXIT, 2326 }; 2327 2328 static struct ept_access_test_data { 2329 unsigned long gpa; 2330 unsigned long *gva; 2331 unsigned long hpa; 2332 unsigned long *hva; 2333 enum ept_access_op op; 2334 } ept_access_test_data; 2335 2336 extern unsigned char ret42_start; 2337 extern unsigned char ret42_end; 2338 2339 /* Returns 42. */ 2340 asm( 2341 ".align 64\n" 2342 "ret42_start:\n" 2343 "mov $42, %eax\n" 2344 "ret\n" 2345 "ret42_end:\n" 2346 ); 2347 2348 static void 2349 diagnose_ept_violation_qual(u64 expected, u64 actual) 2350 { 2351 2352 #define DIAGNOSE(flag) \ 2353 do { \ 2354 if ((expected & flag) != (actual & flag)) \ 2355 printf(#flag " %sexpected\n", \ 2356 (expected & flag) ? "" : "un"); \ 2357 } while (0) 2358 2359 DIAGNOSE(EPT_VLT_RD); 2360 DIAGNOSE(EPT_VLT_WR); 2361 DIAGNOSE(EPT_VLT_FETCH); 2362 DIAGNOSE(EPT_VLT_PERM_RD); 2363 DIAGNOSE(EPT_VLT_PERM_WR); 2364 DIAGNOSE(EPT_VLT_PERM_EX); 2365 DIAGNOSE(EPT_VLT_LADDR_VLD); 2366 DIAGNOSE(EPT_VLT_PADDR); 2367 2368 #undef DIAGNOSE 2369 } 2370 2371 static void do_ept_access_op(enum ept_access_op op) 2372 { 2373 ept_access_test_data.op = op; 2374 enter_guest(); 2375 } 2376 2377 /* 2378 * Force the guest to flush its TLB (i.e., flush gva -> gpa mappings). Only 2379 * needed by tests that modify guest PTEs. 2380 */ 2381 static void ept_access_test_guest_flush_tlb(void) 2382 { 2383 do_ept_access_op(OP_FLUSH_TLB); 2384 skip_exit_vmcall(); 2385 } 2386 2387 /* 2388 * Modifies the EPT entry at @level in the mapping of @gpa. First clears the 2389 * bits in @clear then sets the bits in @set. @mkhuge transforms the entry into 2390 * a huge page. 2391 */ 2392 static unsigned long ept_twiddle(unsigned long gpa, bool mkhuge, int level, 2393 unsigned long clear, unsigned long set) 2394 { 2395 struct ept_access_test_data *data = &ept_access_test_data; 2396 unsigned long orig_pte; 2397 unsigned long pte; 2398 2399 /* Screw with the mapping at the requested level. */ 2400 TEST_ASSERT(get_ept_pte(pml4, gpa, level, &orig_pte)); 2401 pte = orig_pte; 2402 if (mkhuge) 2403 pte = (orig_pte & ~EPT_ADDR_MASK) | data->hpa | EPT_LARGE_PAGE; 2404 else 2405 pte = orig_pte; 2406 pte = (pte & ~clear) | set; 2407 set_ept_pte(pml4, gpa, level, pte); 2408 invept(INVEPT_SINGLE, eptp); 2409 2410 return orig_pte; 2411 } 2412 2413 static void ept_untwiddle(unsigned long gpa, int level, unsigned long orig_pte) 2414 { 2415 set_ept_pte(pml4, gpa, level, orig_pte); 2416 invept(INVEPT_SINGLE, eptp); 2417 } 2418 2419 static void do_ept_violation(bool leaf, enum ept_access_op op, 2420 u64 expected_qual, u64 expected_paddr) 2421 { 2422 u64 qual; 2423 2424 /* Try the access and observe the violation. */ 2425 do_ept_access_op(op); 2426 2427 assert_exit_reason(VMX_EPT_VIOLATION); 2428 2429 qual = vmcs_read(EXI_QUALIFICATION); 2430 2431 /* Mask undefined bits (which may later be defined in certain cases). */ 2432 qual &= ~(EPT_VLT_GUEST_USER | EPT_VLT_GUEST_RW | EPT_VLT_GUEST_EX | 2433 EPT_VLT_PERM_USER_EX); 2434 2435 diagnose_ept_violation_qual(expected_qual, qual); 2436 TEST_EXPECT_EQ(expected_qual, qual); 2437 2438 #if 0 2439 /* Disable for now otherwise every test will fail */ 2440 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2441 (unsigned long) ( 2442 op == OP_EXEC ? data->gva + 1 : data->gva)); 2443 #endif 2444 /* 2445 * TODO: tests that probe expected_paddr in pages other than the one at 2446 * the beginning of the 1g region. 2447 */ 2448 TEST_EXPECT_EQ(vmcs_read(INFO_PHYS_ADDR), expected_paddr); 2449 } 2450 2451 static void 2452 ept_violation_at_level_mkhuge(bool mkhuge, int level, unsigned long clear, 2453 unsigned long set, enum ept_access_op op, 2454 u64 expected_qual) 2455 { 2456 struct ept_access_test_data *data = &ept_access_test_data; 2457 unsigned long orig_pte; 2458 2459 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2460 2461 do_ept_violation(level == 1 || mkhuge, op, expected_qual, 2462 op == OP_EXEC ? data->gpa + sizeof(unsigned long) : 2463 data->gpa); 2464 2465 /* Fix the violation and resume the op loop. */ 2466 ept_untwiddle(data->gpa, level, orig_pte); 2467 enter_guest(); 2468 skip_exit_vmcall(); 2469 } 2470 2471 static void 2472 ept_violation_at_level(int level, unsigned long clear, unsigned long set, 2473 enum ept_access_op op, u64 expected_qual) 2474 { 2475 ept_violation_at_level_mkhuge(false, level, clear, set, op, 2476 expected_qual); 2477 if (ept_huge_pages_supported(level)) 2478 ept_violation_at_level_mkhuge(true, level, clear, set, op, 2479 expected_qual); 2480 } 2481 2482 static void ept_violation(unsigned long clear, unsigned long set, 2483 enum ept_access_op op, u64 expected_qual) 2484 { 2485 ept_violation_at_level(1, clear, set, op, expected_qual); 2486 ept_violation_at_level(2, clear, set, op, expected_qual); 2487 ept_violation_at_level(3, clear, set, op, expected_qual); 2488 ept_violation_at_level(4, clear, set, op, expected_qual); 2489 } 2490 2491 static void ept_access_violation(unsigned long access, enum ept_access_op op, 2492 u64 expected_qual) 2493 { 2494 ept_violation(EPT_PRESENT, access, op, 2495 expected_qual | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2496 } 2497 2498 /* 2499 * For translations that don't involve a GVA, that is physical address (paddr) 2500 * accesses, EPT violations don't set the flag EPT_VLT_PADDR. For a typical 2501 * guest memory access, the hardware does GVA -> GPA -> HPA. However, certain 2502 * translations don't involve GVAs, such as when the hardware does the guest 2503 * page table walk. For example, in translating GVA_1 -> GPA_1, the guest MMU 2504 * might try to set an A bit on a guest PTE. If the GPA_2 that the PTE resides 2505 * on isn't present in the EPT, then the EPT violation will be for GPA_2 and 2506 * the EPT_VLT_PADDR bit will be clear in the exit qualification. 2507 * 2508 * Note that paddr violations can also be triggered by loading PAE page tables 2509 * with wonky addresses. We don't test that yet. 2510 * 2511 * This function modifies the EPT entry that maps the GPA that the guest page 2512 * table entry mapping ept_access_test_data.gva resides on. 2513 * 2514 * @ept_access EPT permissions to set. Other permissions are cleared. 2515 * 2516 * @pte_ad Set the A/D bits on the guest PTE accordingly. 2517 * 2518 * @op Guest operation to perform with 2519 * ept_access_test_data.gva. 2520 * 2521 * @expect_violation 2522 * Is a violation expected during the paddr access? 2523 * 2524 * @expected_qual Expected qualification for the EPT violation. 2525 * EPT_VLT_PADDR should be clear. 2526 */ 2527 static void ept_access_paddr(unsigned long ept_access, unsigned long pte_ad, 2528 enum ept_access_op op, bool expect_violation, 2529 u64 expected_qual) 2530 { 2531 struct ept_access_test_data *data = &ept_access_test_data; 2532 unsigned long *ptep; 2533 unsigned long gpa; 2534 unsigned long orig_epte; 2535 unsigned long epte; 2536 int i; 2537 2538 /* Modify the guest PTE mapping data->gva according to @pte_ad. */ 2539 ptep = get_pte_level(current_page_table(), data->gva, /*level=*/1); 2540 TEST_ASSERT(ptep); 2541 TEST_ASSERT_EQ(*ptep & PT_ADDR_MASK, data->gpa); 2542 *ptep = (*ptep & ~PT_AD_MASK) | pte_ad; 2543 ept_access_test_guest_flush_tlb(); 2544 2545 /* 2546 * Now modify the access bits on the EPT entry for the GPA that the 2547 * guest PTE resides on. Note that by modifying a single EPT entry, 2548 * we're potentially affecting 512 guest PTEs. However, we've carefully 2549 * constructed our test such that those other 511 PTEs aren't used by 2550 * the guest: data->gva is at the beginning of a 1G huge page, thus the 2551 * PTE we're modifying is at the beginning of a 4K page and the 2552 * following 511 entries are also under our control (and not touched by 2553 * the guest). 2554 */ 2555 gpa = virt_to_phys(ptep); 2556 TEST_ASSERT_EQ(gpa & ~PAGE_MASK, 0); 2557 /* 2558 * Make sure the guest page table page is mapped with a 4K EPT entry, 2559 * otherwise our level=1 twiddling below will fail. We use the 2560 * identity map (gpa = gpa) since page tables are shared with the host. 2561 */ 2562 install_ept(pml4, gpa, gpa, EPT_PRESENT); 2563 orig_epte = ept_twiddle(gpa, /*mkhuge=*/0, /*level=*/1, 2564 /*clear=*/EPT_PRESENT, /*set=*/ept_access); 2565 2566 if (expect_violation) { 2567 do_ept_violation(/*leaf=*/true, op, 2568 expected_qual | EPT_VLT_LADDR_VLD, gpa); 2569 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2570 do_ept_access_op(op); 2571 } else { 2572 do_ept_access_op(op); 2573 if (ept_ad_enabled()) { 2574 for (i = EPT_PAGE_LEVEL; i > 0; i--) { 2575 TEST_ASSERT(get_ept_pte(pml4, gpa, i, &epte)); 2576 TEST_ASSERT(epte & EPT_ACCESS_FLAG); 2577 if (i == 1) 2578 TEST_ASSERT(epte & EPT_DIRTY_FLAG); 2579 else 2580 TEST_ASSERT_EQ(epte & EPT_DIRTY_FLAG, 0); 2581 } 2582 } 2583 2584 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2585 } 2586 2587 TEST_ASSERT(*ptep & PT_ACCESSED_MASK); 2588 if ((pte_ad & PT_DIRTY_MASK) || op == OP_WRITE) 2589 TEST_ASSERT(*ptep & PT_DIRTY_MASK); 2590 2591 skip_exit_vmcall(); 2592 } 2593 2594 static void ept_access_allowed_paddr(unsigned long ept_access, 2595 unsigned long pte_ad, 2596 enum ept_access_op op) 2597 { 2598 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/false, 2599 /*expected_qual=*/-1); 2600 } 2601 2602 static void ept_access_violation_paddr(unsigned long ept_access, 2603 unsigned long pte_ad, 2604 enum ept_access_op op, 2605 u64 expected_qual) 2606 { 2607 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/true, 2608 expected_qual); 2609 } 2610 2611 2612 static void ept_allowed_at_level_mkhuge(bool mkhuge, int level, 2613 unsigned long clear, 2614 unsigned long set, 2615 enum ept_access_op op) 2616 { 2617 struct ept_access_test_data *data = &ept_access_test_data; 2618 unsigned long orig_pte; 2619 2620 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2621 2622 /* No violation. Should proceed to vmcall. */ 2623 do_ept_access_op(op); 2624 skip_exit_vmcall(); 2625 2626 ept_untwiddle(data->gpa, level, orig_pte); 2627 } 2628 2629 static void ept_allowed_at_level(int level, unsigned long clear, 2630 unsigned long set, enum ept_access_op op) 2631 { 2632 ept_allowed_at_level_mkhuge(false, level, clear, set, op); 2633 if (ept_huge_pages_supported(level)) 2634 ept_allowed_at_level_mkhuge(true, level, clear, set, op); 2635 } 2636 2637 static void ept_allowed(unsigned long clear, unsigned long set, 2638 enum ept_access_op op) 2639 { 2640 ept_allowed_at_level(1, clear, set, op); 2641 ept_allowed_at_level(2, clear, set, op); 2642 ept_allowed_at_level(3, clear, set, op); 2643 ept_allowed_at_level(4, clear, set, op); 2644 } 2645 2646 static void ept_ignored_bit(int bit) 2647 { 2648 /* Set the bit. */ 2649 ept_allowed(0, 1ul << bit, OP_READ); 2650 ept_allowed(0, 1ul << bit, OP_WRITE); 2651 ept_allowed(0, 1ul << bit, OP_EXEC); 2652 2653 /* Clear the bit. */ 2654 ept_allowed(1ul << bit, 0, OP_READ); 2655 ept_allowed(1ul << bit, 0, OP_WRITE); 2656 ept_allowed(1ul << bit, 0, OP_EXEC); 2657 } 2658 2659 static void ept_access_allowed(unsigned long access, enum ept_access_op op) 2660 { 2661 ept_allowed(EPT_PRESENT, access, op); 2662 } 2663 2664 2665 static void ept_misconfig_at_level_mkhuge_op(bool mkhuge, int level, 2666 unsigned long clear, 2667 unsigned long set, 2668 enum ept_access_op op) 2669 { 2670 struct ept_access_test_data *data = &ept_access_test_data; 2671 unsigned long orig_pte; 2672 2673 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2674 2675 do_ept_access_op(op); 2676 assert_exit_reason(VMX_EPT_MISCONFIG); 2677 2678 /* Intel 27.2.1, "For all other VM exits, this field is cleared." */ 2679 #if 0 2680 /* broken: */ 2681 TEST_EXPECT_EQ_MSG(vmcs_read(EXI_QUALIFICATION), 0); 2682 #endif 2683 #if 0 2684 /* 2685 * broken: 2686 * According to description of exit qual for EPT violation, 2687 * EPT_VLT_LADDR_VLD indicates if GUEST_LINEAR_ADDRESS is valid. 2688 * However, I can't find anything that says GUEST_LINEAR_ADDRESS ought 2689 * to be set for msiconfig. 2690 */ 2691 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2692 (unsigned long) ( 2693 op == OP_EXEC ? data->gva + 1 : data->gva)); 2694 #endif 2695 2696 /* Fix the violation and resume the op loop. */ 2697 ept_untwiddle(data->gpa, level, orig_pte); 2698 enter_guest(); 2699 skip_exit_vmcall(); 2700 } 2701 2702 static void ept_misconfig_at_level_mkhuge(bool mkhuge, int level, 2703 unsigned long clear, 2704 unsigned long set) 2705 { 2706 /* The op shouldn't matter (read, write, exec), so try them all! */ 2707 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_READ); 2708 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_WRITE); 2709 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_EXEC); 2710 } 2711 2712 static void ept_misconfig_at_level(int level, unsigned long clear, 2713 unsigned long set) 2714 { 2715 ept_misconfig_at_level_mkhuge(false, level, clear, set); 2716 if (ept_huge_pages_supported(level)) 2717 ept_misconfig_at_level_mkhuge(true, level, clear, set); 2718 } 2719 2720 static void ept_misconfig(unsigned long clear, unsigned long set) 2721 { 2722 ept_misconfig_at_level(1, clear, set); 2723 ept_misconfig_at_level(2, clear, set); 2724 ept_misconfig_at_level(3, clear, set); 2725 ept_misconfig_at_level(4, clear, set); 2726 } 2727 2728 static void ept_access_misconfig(unsigned long access) 2729 { 2730 ept_misconfig(EPT_PRESENT, access); 2731 } 2732 2733 static void ept_reserved_bit_at_level_nohuge(int level, int bit) 2734 { 2735 /* Setting the bit causes a misconfig. */ 2736 ept_misconfig_at_level_mkhuge(false, level, 0, 1ul << bit); 2737 2738 /* Making the entry non-present turns reserved bits into ignored. */ 2739 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2740 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2741 } 2742 2743 static void ept_reserved_bit_at_level_huge(int level, int bit) 2744 { 2745 /* Setting the bit causes a misconfig. */ 2746 ept_misconfig_at_level_mkhuge(true, level, 0, 1ul << bit); 2747 2748 /* Making the entry non-present turns reserved bits into ignored. */ 2749 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2750 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2751 } 2752 2753 static void ept_reserved_bit_at_level(int level, int bit) 2754 { 2755 /* Setting the bit causes a misconfig. */ 2756 ept_misconfig_at_level(level, 0, 1ul << bit); 2757 2758 /* Making the entry non-present turns reserved bits into ignored. */ 2759 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2760 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2761 } 2762 2763 static void ept_reserved_bit(int bit) 2764 { 2765 ept_reserved_bit_at_level(1, bit); 2766 ept_reserved_bit_at_level(2, bit); 2767 ept_reserved_bit_at_level(3, bit); 2768 ept_reserved_bit_at_level(4, bit); 2769 } 2770 2771 #define PAGE_2M_ORDER 9 2772 #define PAGE_1G_ORDER 18 2773 2774 static void *get_1g_page(void) 2775 { 2776 static void *alloc; 2777 2778 if (!alloc) 2779 alloc = alloc_pages(PAGE_1G_ORDER); 2780 return alloc; 2781 } 2782 2783 static void ept_access_test_teardown(void *unused) 2784 { 2785 /* Exit the guest cleanly. */ 2786 do_ept_access_op(OP_EXIT); 2787 } 2788 2789 static void ept_access_test_guest(void) 2790 { 2791 struct ept_access_test_data *data = &ept_access_test_data; 2792 int (*code)(void) = (int (*)(void)) &data->gva[1]; 2793 2794 while (true) { 2795 switch (data->op) { 2796 case OP_READ: 2797 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_1); 2798 break; 2799 case OP_WRITE: 2800 *data->gva = MAGIC_VAL_2; 2801 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_2); 2802 *data->gva = MAGIC_VAL_1; 2803 break; 2804 case OP_EXEC: 2805 TEST_ASSERT_EQ(42, code()); 2806 break; 2807 case OP_FLUSH_TLB: 2808 write_cr3(read_cr3()); 2809 break; 2810 case OP_EXIT: 2811 return; 2812 default: 2813 TEST_ASSERT_MSG(false, "Unknown op %d", data->op); 2814 } 2815 vmcall(); 2816 } 2817 } 2818 2819 static void ept_access_test_setup(void) 2820 { 2821 struct ept_access_test_data *data = &ept_access_test_data; 2822 unsigned long npages = 1ul << PAGE_1G_ORDER; 2823 unsigned long size = npages * PAGE_SIZE; 2824 unsigned long *page_table = current_page_table(); 2825 unsigned long pte; 2826 2827 if (setup_ept(false)) 2828 test_skip("EPT not supported"); 2829 2830 /* We use data->gpa = 1 << 39 so that test data has a separate pml4 entry */ 2831 if (cpuid_maxphyaddr() < 40) 2832 test_skip("Test needs MAXPHYADDR >= 40"); 2833 2834 test_set_guest(ept_access_test_guest); 2835 test_add_teardown(ept_access_test_teardown, NULL); 2836 2837 data->hva = get_1g_page(); 2838 TEST_ASSERT(data->hva); 2839 data->hpa = virt_to_phys(data->hva); 2840 2841 data->gpa = 1ul << 39; 2842 data->gva = (void *) ALIGN((unsigned long) alloc_vpages(npages * 2), 2843 size); 2844 TEST_ASSERT(!any_present_pages(page_table, data->gva, size)); 2845 install_pages(page_table, data->gpa, size, data->gva); 2846 2847 /* 2848 * Make sure nothing's mapped here so the tests that screw with the 2849 * pml4 entry don't inadvertently break something. 2850 */ 2851 TEST_ASSERT(get_ept_pte(pml4, data->gpa, 4, &pte) && pte == 0); 2852 TEST_ASSERT(get_ept_pte(pml4, data->gpa + size - 1, 4, &pte) && pte == 0); 2853 install_ept(pml4, data->hpa, data->gpa, EPT_PRESENT); 2854 2855 data->hva[0] = MAGIC_VAL_1; 2856 memcpy(&data->hva[1], &ret42_start, &ret42_end - &ret42_start); 2857 } 2858 2859 static void ept_access_test_not_present(void) 2860 { 2861 ept_access_test_setup(); 2862 /* --- */ 2863 ept_access_violation(0, OP_READ, EPT_VLT_RD); 2864 ept_access_violation(0, OP_WRITE, EPT_VLT_WR); 2865 ept_access_violation(0, OP_EXEC, EPT_VLT_FETCH); 2866 } 2867 2868 static void ept_access_test_read_only(void) 2869 { 2870 ept_access_test_setup(); 2871 2872 /* r-- */ 2873 ept_access_allowed(EPT_RA, OP_READ); 2874 ept_access_violation(EPT_RA, OP_WRITE, EPT_VLT_WR | EPT_VLT_PERM_RD); 2875 ept_access_violation(EPT_RA, OP_EXEC, EPT_VLT_FETCH | EPT_VLT_PERM_RD); 2876 } 2877 2878 static void ept_access_test_write_only(void) 2879 { 2880 ept_access_test_setup(); 2881 /* -w- */ 2882 ept_access_misconfig(EPT_WA); 2883 } 2884 2885 static void ept_access_test_read_write(void) 2886 { 2887 ept_access_test_setup(); 2888 /* rw- */ 2889 ept_access_allowed(EPT_RA | EPT_WA, OP_READ); 2890 ept_access_allowed(EPT_RA | EPT_WA, OP_WRITE); 2891 ept_access_violation(EPT_RA | EPT_WA, OP_EXEC, 2892 EPT_VLT_FETCH | EPT_VLT_PERM_RD | EPT_VLT_PERM_WR); 2893 } 2894 2895 2896 static void ept_access_test_execute_only(void) 2897 { 2898 ept_access_test_setup(); 2899 /* --x */ 2900 if (ept_execute_only_supported()) { 2901 ept_access_violation(EPT_EA, OP_READ, 2902 EPT_VLT_RD | EPT_VLT_PERM_EX); 2903 ept_access_violation(EPT_EA, OP_WRITE, 2904 EPT_VLT_WR | EPT_VLT_PERM_EX); 2905 ept_access_allowed(EPT_EA, OP_EXEC); 2906 } else { 2907 ept_access_misconfig(EPT_EA); 2908 } 2909 } 2910 2911 static void ept_access_test_read_execute(void) 2912 { 2913 ept_access_test_setup(); 2914 /* r-x */ 2915 ept_access_allowed(EPT_RA | EPT_EA, OP_READ); 2916 ept_access_violation(EPT_RA | EPT_EA, OP_WRITE, 2917 EPT_VLT_WR | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX); 2918 ept_access_allowed(EPT_RA | EPT_EA, OP_EXEC); 2919 } 2920 2921 static void ept_access_test_write_execute(void) 2922 { 2923 ept_access_test_setup(); 2924 /* -wx */ 2925 ept_access_misconfig(EPT_WA | EPT_EA); 2926 } 2927 2928 static void ept_access_test_read_write_execute(void) 2929 { 2930 ept_access_test_setup(); 2931 /* rwx */ 2932 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_READ); 2933 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_WRITE); 2934 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_EXEC); 2935 } 2936 2937 static void ept_access_test_reserved_bits(void) 2938 { 2939 int i; 2940 int maxphyaddr; 2941 2942 ept_access_test_setup(); 2943 2944 /* Reserved bits above maxphyaddr. */ 2945 maxphyaddr = cpuid_maxphyaddr(); 2946 for (i = maxphyaddr; i <= 51; i++) { 2947 report_prefix_pushf("reserved_bit=%d", i); 2948 ept_reserved_bit(i); 2949 report_prefix_pop(); 2950 } 2951 2952 /* Level-specific reserved bits. */ 2953 ept_reserved_bit_at_level_nohuge(2, 3); 2954 ept_reserved_bit_at_level_nohuge(2, 4); 2955 ept_reserved_bit_at_level_nohuge(2, 5); 2956 ept_reserved_bit_at_level_nohuge(2, 6); 2957 /* 2M alignment. */ 2958 for (i = 12; i < 20; i++) { 2959 report_prefix_pushf("reserved_bit=%d", i); 2960 ept_reserved_bit_at_level_huge(2, i); 2961 report_prefix_pop(); 2962 } 2963 ept_reserved_bit_at_level_nohuge(3, 3); 2964 ept_reserved_bit_at_level_nohuge(3, 4); 2965 ept_reserved_bit_at_level_nohuge(3, 5); 2966 ept_reserved_bit_at_level_nohuge(3, 6); 2967 /* 1G alignment. */ 2968 for (i = 12; i < 29; i++) { 2969 report_prefix_pushf("reserved_bit=%d", i); 2970 ept_reserved_bit_at_level_huge(3, i); 2971 report_prefix_pop(); 2972 } 2973 ept_reserved_bit_at_level(4, 3); 2974 ept_reserved_bit_at_level(4, 4); 2975 ept_reserved_bit_at_level(4, 5); 2976 ept_reserved_bit_at_level(4, 6); 2977 ept_reserved_bit_at_level(4, 7); 2978 } 2979 2980 static void ept_access_test_ignored_bits(void) 2981 { 2982 ept_access_test_setup(); 2983 /* 2984 * Bits ignored at every level. Bits 8 and 9 (A and D) are ignored as 2985 * far as translation is concerned even if AD bits are enabled in the 2986 * EPTP. Bit 63 is ignored because "EPT-violation #VE" VM-execution 2987 * control is 0. 2988 */ 2989 ept_ignored_bit(8); 2990 ept_ignored_bit(9); 2991 ept_ignored_bit(10); 2992 ept_ignored_bit(11); 2993 ept_ignored_bit(52); 2994 ept_ignored_bit(53); 2995 ept_ignored_bit(54); 2996 ept_ignored_bit(55); 2997 ept_ignored_bit(56); 2998 ept_ignored_bit(57); 2999 ept_ignored_bit(58); 3000 ept_ignored_bit(59); 3001 ept_ignored_bit(60); 3002 ept_ignored_bit(61); 3003 ept_ignored_bit(62); 3004 ept_ignored_bit(63); 3005 } 3006 3007 static void ept_access_test_paddr_not_present_ad_disabled(void) 3008 { 3009 ept_access_test_setup(); 3010 ept_disable_ad_bits(); 3011 3012 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, EPT_VLT_RD); 3013 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, EPT_VLT_RD); 3014 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, EPT_VLT_RD); 3015 } 3016 3017 static void ept_access_test_paddr_not_present_ad_enabled(void) 3018 { 3019 u64 qual = EPT_VLT_RD | EPT_VLT_WR; 3020 3021 ept_access_test_setup(); 3022 ept_enable_ad_bits_or_skip_test(); 3023 3024 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, qual); 3025 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, qual); 3026 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, qual); 3027 } 3028 3029 static void ept_access_test_paddr_read_only_ad_disabled(void) 3030 { 3031 /* 3032 * When EPT AD bits are disabled, all accesses to guest paging 3033 * structures are reported separately as a read and (after 3034 * translation of the GPA to host physical address) a read+write 3035 * if the A/D bits have to be set. 3036 */ 3037 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 3038 3039 ept_access_test_setup(); 3040 ept_disable_ad_bits(); 3041 3042 /* Can't update A bit, so all accesses fail. */ 3043 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 3044 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 3045 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 3046 /* AD bits disabled, so only writes try to update the D bit. */ 3047 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ); 3048 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 3049 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC); 3050 /* Both A and D already set, so read-only is OK. */ 3051 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_READ); 3052 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_WRITE); 3053 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_EXEC); 3054 } 3055 3056 static void ept_access_test_paddr_read_only_ad_enabled(void) 3057 { 3058 /* 3059 * When EPT AD bits are enabled, all accesses to guest paging 3060 * structures are considered writes as far as EPT translation 3061 * is concerned. 3062 */ 3063 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 3064 3065 ept_access_test_setup(); 3066 ept_enable_ad_bits_or_skip_test(); 3067 3068 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 3069 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 3070 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 3071 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ, qual); 3072 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 3073 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC, qual); 3074 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_READ, qual); 3075 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_WRITE, qual); 3076 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_EXEC, qual); 3077 } 3078 3079 static void ept_access_test_paddr_read_write(void) 3080 { 3081 ept_access_test_setup(); 3082 /* Read-write access to paging structure. */ 3083 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_READ); 3084 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_WRITE); 3085 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_EXEC); 3086 } 3087 3088 static void ept_access_test_paddr_read_write_execute(void) 3089 { 3090 ept_access_test_setup(); 3091 /* RWX access to paging structure. */ 3092 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_READ); 3093 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_WRITE); 3094 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_EXEC); 3095 } 3096 3097 static void ept_access_test_paddr_read_execute_ad_disabled(void) 3098 { 3099 /* 3100 * When EPT AD bits are disabled, all accesses to guest paging 3101 * structures are reported separately as a read and (after 3102 * translation of the GPA to host physical address) a read+write 3103 * if the A/D bits have to be set. 3104 */ 3105 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3106 3107 ept_access_test_setup(); 3108 ept_disable_ad_bits(); 3109 3110 /* Can't update A bit, so all accesses fail. */ 3111 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3112 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3113 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3114 /* AD bits disabled, so only writes try to update the D bit. */ 3115 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ); 3116 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3117 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC); 3118 /* Both A and D already set, so read-only is OK. */ 3119 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ); 3120 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE); 3121 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC); 3122 } 3123 3124 static void ept_access_test_paddr_read_execute_ad_enabled(void) 3125 { 3126 /* 3127 * When EPT AD bits are enabled, all accesses to guest paging 3128 * structures are considered writes as far as EPT translation 3129 * is concerned. 3130 */ 3131 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3132 3133 ept_access_test_setup(); 3134 ept_enable_ad_bits_or_skip_test(); 3135 3136 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3137 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3138 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3139 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ, qual); 3140 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3141 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC, qual); 3142 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ, qual); 3143 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE, qual); 3144 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC, qual); 3145 } 3146 3147 static void ept_access_test_paddr_not_present_page_fault(void) 3148 { 3149 ept_access_test_setup(); 3150 /* 3151 * TODO: test no EPT violation as long as guest PF occurs. e.g., GPA is 3152 * page is read-only in EPT but GVA is also mapped read only in PT. 3153 * Thus guest page fault before host takes EPT violation for trying to 3154 * update A bit. 3155 */ 3156 } 3157 3158 static void ept_access_test_force_2m_page(void) 3159 { 3160 ept_access_test_setup(); 3161 3162 TEST_ASSERT_EQ(ept_2m_supported(), true); 3163 ept_allowed_at_level_mkhuge(true, 2, 0, 0, OP_READ); 3164 ept_violation_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_RA, OP_WRITE, 3165 EPT_VLT_WR | EPT_VLT_PERM_RD | 3166 EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 3167 ept_misconfig_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_WA); 3168 } 3169 3170 static bool invvpid_valid(u64 type, u64 vpid, u64 gla) 3171 { 3172 if (!is_invvpid_type_supported(type)) 3173 return false; 3174 3175 if (vpid >> 16) 3176 return false; 3177 3178 if (type != INVVPID_ALL && !vpid) 3179 return false; 3180 3181 if (type == INVVPID_ADDR && !is_canonical(gla)) 3182 return false; 3183 3184 return true; 3185 } 3186 3187 static void try_invvpid(u64 type, u64 vpid, u64 gla) 3188 { 3189 int rc; 3190 bool valid = invvpid_valid(type, vpid, gla); 3191 u64 expected = valid ? VMXERR_UNSUPPORTED_VMCS_COMPONENT 3192 : VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID; 3193 /* 3194 * Set VMX_INST_ERROR to VMXERR_UNVALID_VMCS_COMPONENT, so 3195 * that we can tell if it is updated by INVVPID. 3196 */ 3197 vmcs_read(~0); 3198 rc = __invvpid(type, vpid, gla); 3199 report(!rc == valid, "INVVPID type %ld VPID %lx GLA %lx %s", type, 3200 vpid, gla, 3201 valid ? "passes" : "fails"); 3202 report(vmcs_read(VMX_INST_ERROR) == expected, 3203 "After %s INVVPID, VMX_INST_ERR is %ld (actual %ld)", 3204 rc ? "failed" : "successful", 3205 expected, vmcs_read(VMX_INST_ERROR)); 3206 } 3207 3208 static inline unsigned long get_first_supported_invvpid_type(void) 3209 { 3210 u64 type = ffs(ept_vpid.val >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 3211 3212 __TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 3213 return type; 3214 } 3215 3216 static void ds_invvpid(void *data) 3217 { 3218 asm volatile("invvpid %0, %1" 3219 : 3220 : "m"(*(struct invvpid_operand *)data), 3221 "r"(get_first_supported_invvpid_type())); 3222 } 3223 3224 /* 3225 * The SS override is ignored in 64-bit mode, so we use an addressing 3226 * mode with %rsp as the base register to generate an implicit SS 3227 * reference. 3228 */ 3229 static void ss_invvpid(void *data) 3230 { 3231 asm volatile("sub %%rsp,%0; invvpid (%%rsp,%0,1), %1" 3232 : "+r"(data) 3233 : "r"(get_first_supported_invvpid_type())); 3234 } 3235 3236 static void invvpid_test_gp(void) 3237 { 3238 bool fault; 3239 3240 fault = test_for_exception(GP_VECTOR, &ds_invvpid, 3241 (void *)NONCANONICAL); 3242 report(fault, "INVVPID with non-canonical DS operand raises #GP"); 3243 } 3244 3245 static void invvpid_test_ss(void) 3246 { 3247 bool fault; 3248 3249 fault = test_for_exception(SS_VECTOR, &ss_invvpid, 3250 (void *)NONCANONICAL); 3251 report(fault, "INVVPID with non-canonical SS operand raises #SS"); 3252 } 3253 3254 static void invvpid_test_pf(void) 3255 { 3256 void *vpage = alloc_vpage(); 3257 bool fault; 3258 3259 fault = test_for_exception(PF_VECTOR, &ds_invvpid, vpage); 3260 report(fault, "INVVPID with unmapped operand raises #PF"); 3261 } 3262 3263 static void try_compat_invvpid(void *unused) 3264 { 3265 struct far_pointer32 fp = { 3266 .offset = (uintptr_t)&&invvpid, 3267 .selector = KERNEL_CS32, 3268 }; 3269 uintptr_t rsp; 3270 3271 asm volatile ("mov %%rsp, %0" : "=r"(rsp)); 3272 3273 TEST_ASSERT_MSG(fp.offset == (uintptr_t)&&invvpid, 3274 "Code address too high."); 3275 TEST_ASSERT_MSG(rsp == (u32)rsp, "Stack address too high."); 3276 3277 asm goto ("lcall *%0" : : "m" (fp) : "rax" : invvpid); 3278 return; 3279 invvpid: 3280 asm volatile (".code32;" 3281 "invvpid (%eax), %eax;" 3282 "lret;" 3283 ".code64"); 3284 __builtin_unreachable(); 3285 } 3286 3287 static void invvpid_test_compatibility_mode(void) 3288 { 3289 bool fault; 3290 3291 fault = test_for_exception(UD_VECTOR, &try_compat_invvpid, NULL); 3292 report(fault, "Compatibility mode INVVPID raises #UD"); 3293 } 3294 3295 static void invvpid_test_not_in_vmx_operation(void) 3296 { 3297 bool fault; 3298 3299 TEST_ASSERT(!vmx_off()); 3300 fault = test_for_exception(UD_VECTOR, &ds_invvpid, NULL); 3301 report(fault, "INVVPID outside of VMX operation raises #UD"); 3302 TEST_ASSERT(!vmx_on()); 3303 } 3304 3305 /* 3306 * This does not test real-address mode, virtual-8086 mode, protected mode, 3307 * or CPL > 0. 3308 */ 3309 static void invvpid_test(void) 3310 { 3311 int i; 3312 unsigned types = 0; 3313 unsigned type; 3314 3315 if (!is_vpid_supported()) 3316 test_skip("VPID not supported"); 3317 3318 if (!is_invvpid_supported()) 3319 test_skip("INVVPID not supported.\n"); 3320 3321 if (is_invvpid_type_supported(INVVPID_ADDR)) 3322 types |= 1u << INVVPID_ADDR; 3323 if (is_invvpid_type_supported(INVVPID_CONTEXT_GLOBAL)) 3324 types |= 1u << INVVPID_CONTEXT_GLOBAL; 3325 if (is_invvpid_type_supported(INVVPID_ALL)) 3326 types |= 1u << INVVPID_ALL; 3327 if (is_invvpid_type_supported(INVVPID_CONTEXT_LOCAL)) 3328 types |= 1u << INVVPID_CONTEXT_LOCAL; 3329 3330 if (!types) 3331 test_skip("No INVVPID types supported.\n"); 3332 3333 for (i = -127; i < 128; i++) 3334 try_invvpid(i, 0xffff, 0); 3335 3336 /* 3337 * VPID must not be more than 16 bits. 3338 */ 3339 for (i = 0; i < 64; i++) 3340 for (type = 0; type < 4; type++) 3341 if (types & (1u << type)) 3342 try_invvpid(type, 1ul << i, 0); 3343 3344 /* 3345 * VPID must not be zero, except for "all contexts." 3346 */ 3347 for (type = 0; type < 4; type++) 3348 if (types & (1u << type)) 3349 try_invvpid(type, 0, 0); 3350 3351 /* 3352 * The gla operand is only validated for single-address INVVPID. 3353 */ 3354 if (types & (1u << INVVPID_ADDR)) 3355 try_invvpid(INVVPID_ADDR, 0xffff, NONCANONICAL); 3356 3357 invvpid_test_gp(); 3358 invvpid_test_ss(); 3359 invvpid_test_pf(); 3360 invvpid_test_compatibility_mode(); 3361 invvpid_test_not_in_vmx_operation(); 3362 } 3363 3364 /* 3365 * Test for early VMLAUNCH failure. Returns true if VMLAUNCH makes it 3366 * at least as far as the guest-state checks. Returns false if the 3367 * VMLAUNCH fails early and execution falls through to the next 3368 * instruction. 3369 */ 3370 static bool vmlaunch_succeeds(void) 3371 { 3372 u32 exit_reason; 3373 3374 /* 3375 * Indirectly set VMX_INST_ERR to 12 ("VMREAD/VMWRITE from/to 3376 * unsupported VMCS component"). The caller can then check 3377 * to see if a failed VM-entry sets VMX_INST_ERR as expected. 3378 */ 3379 vmcs_write(~0u, 0); 3380 3381 vmcs_write(HOST_RIP, (uintptr_t)&&success); 3382 __asm__ __volatile__ goto ("vmwrite %%rsp, %0; vmlaunch" 3383 : 3384 : "r" ((u64)HOST_RSP) 3385 : "cc", "memory" 3386 : success); 3387 return false; 3388 success: 3389 exit_reason = vmcs_read(EXI_REASON); 3390 TEST_ASSERT(exit_reason == (VMX_FAIL_STATE | VMX_ENTRY_FAILURE) || 3391 exit_reason == (VMX_FAIL_MSR | VMX_ENTRY_FAILURE)); 3392 return true; 3393 } 3394 3395 /* 3396 * Try to launch the current VMCS. 3397 */ 3398 static void test_vmx_vmlaunch(u32 xerror) 3399 { 3400 bool success = vmlaunch_succeeds(); 3401 u32 vmx_inst_err; 3402 3403 report(success == !xerror, "vmlaunch %s", 3404 !xerror ? "succeeds" : "fails"); 3405 if (!success && xerror) { 3406 vmx_inst_err = vmcs_read(VMX_INST_ERROR); 3407 report(vmx_inst_err == xerror, 3408 "VMX inst error is %d (actual %d)", xerror, 3409 vmx_inst_err); 3410 } 3411 } 3412 3413 /* 3414 * Try to launch the current VMCS, and expect one of two possible 3415 * errors (or success) codes. 3416 */ 3417 static void test_vmx_vmlaunch2(u32 xerror1, u32 xerror2) 3418 { 3419 bool success = vmlaunch_succeeds(); 3420 u32 vmx_inst_err; 3421 3422 if (!xerror1 == !xerror2) 3423 report(success == !xerror1, "vmlaunch %s", 3424 !xerror1 ? "succeeds" : "fails"); 3425 3426 if (!success && (xerror1 || xerror2)) { 3427 vmx_inst_err = vmcs_read(VMX_INST_ERROR); 3428 report(vmx_inst_err == xerror1 || vmx_inst_err == xerror2, 3429 "VMX inst error is %d or %d (actual %d)", xerror1, 3430 xerror2, vmx_inst_err); 3431 } 3432 } 3433 3434 static void test_vmx_invalid_controls(void) 3435 { 3436 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_CONTROL_FIELD); 3437 } 3438 3439 static void test_vmx_valid_controls(void) 3440 { 3441 test_vmx_vmlaunch(0); 3442 } 3443 3444 /* 3445 * Test a particular value of a VM-execution control bit, if the value 3446 * is required or if the value is zero. 3447 */ 3448 static void test_rsvd_ctl_bit_value(const char *name, union vmx_ctrl_msr msr, 3449 enum Encoding encoding, unsigned bit, 3450 unsigned val) 3451 { 3452 u32 mask = 1u << bit; 3453 bool expected; 3454 u32 controls; 3455 3456 if (msr.set & mask) 3457 TEST_ASSERT(msr.clr & mask); 3458 3459 /* 3460 * We can't arbitrarily turn on a control bit, because it may 3461 * introduce dependencies on other VMCS fields. So, we only 3462 * test turning on bits that have a required setting. 3463 */ 3464 if (val && (msr.clr & mask) && !(msr.set & mask)) 3465 return; 3466 3467 report_prefix_pushf("%s %s bit %d", 3468 val ? "Set" : "Clear", name, bit); 3469 3470 controls = vmcs_read(encoding); 3471 if (val) { 3472 vmcs_write(encoding, msr.set | mask); 3473 expected = (msr.clr & mask); 3474 } else { 3475 vmcs_write(encoding, msr.set & ~mask); 3476 expected = !(msr.set & mask); 3477 } 3478 if (expected) 3479 test_vmx_valid_controls(); 3480 else 3481 test_vmx_invalid_controls(); 3482 vmcs_write(encoding, controls); 3483 report_prefix_pop(); 3484 } 3485 3486 /* 3487 * Test reserved values of a VM-execution control bit, based on the 3488 * allowed bit settings from the corresponding VMX capability MSR. 3489 */ 3490 static void test_rsvd_ctl_bit(const char *name, union vmx_ctrl_msr msr, 3491 enum Encoding encoding, unsigned bit) 3492 { 3493 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 0); 3494 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 1); 3495 } 3496 3497 /* 3498 * Reserved bits in the pin-based VM-execution controls must be set 3499 * properly. Software may consult the VMX capability MSRs to determine 3500 * the proper settings. 3501 * [Intel SDM] 3502 */ 3503 static void test_pin_based_ctls(void) 3504 { 3505 unsigned bit; 3506 3507 printf("%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PIN" : 3508 "MSR_IA32_VMX_PINBASED_CTLS", ctrl_pin_rev.val); 3509 for (bit = 0; bit < 32; bit++) 3510 test_rsvd_ctl_bit("pin-based controls", 3511 ctrl_pin_rev, PIN_CONTROLS, bit); 3512 } 3513 3514 /* 3515 * Reserved bits in the primary processor-based VM-execution controls 3516 * must be set properly. Software may consult the VMX capability MSRs 3517 * to determine the proper settings. 3518 * [Intel SDM] 3519 */ 3520 static void test_primary_processor_based_ctls(void) 3521 { 3522 unsigned bit; 3523 3524 printf("\n%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PROC" : 3525 "MSR_IA32_VMX_PROCBASED_CTLS", ctrl_cpu_rev[0].val); 3526 for (bit = 0; bit < 32; bit++) 3527 test_rsvd_ctl_bit("primary processor-based controls", 3528 ctrl_cpu_rev[0], CPU_EXEC_CTRL0, bit); 3529 } 3530 3531 /* 3532 * If the "activate secondary controls" primary processor-based 3533 * VM-execution control is 1, reserved bits in the secondary 3534 * processor-based VM-execution controls must be cleared. Software may 3535 * consult the VMX capability MSRs to determine which bits are 3536 * reserved. 3537 * If the "activate secondary controls" primary processor-based 3538 * VM-execution control is 0 (or if the processor does not support the 3539 * 1-setting of that control), no checks are performed on the 3540 * secondary processor-based VM-execution controls. 3541 * [Intel SDM] 3542 */ 3543 static void test_secondary_processor_based_ctls(void) 3544 { 3545 u32 primary; 3546 u32 secondary; 3547 unsigned bit; 3548 3549 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) 3550 return; 3551 3552 primary = vmcs_read(CPU_EXEC_CTRL0); 3553 secondary = vmcs_read(CPU_EXEC_CTRL1); 3554 3555 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3556 printf("\nMSR_IA32_VMX_PROCBASED_CTLS2: %lx\n", ctrl_cpu_rev[1].val); 3557 for (bit = 0; bit < 32; bit++) 3558 test_rsvd_ctl_bit("secondary processor-based controls", 3559 ctrl_cpu_rev[1], CPU_EXEC_CTRL1, bit); 3560 3561 /* 3562 * When the "activate secondary controls" VM-execution control 3563 * is clear, there are no checks on the secondary controls. 3564 */ 3565 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3566 vmcs_write(CPU_EXEC_CTRL1, ~0); 3567 report(vmlaunch_succeeds(), 3568 "Secondary processor-based controls ignored"); 3569 vmcs_write(CPU_EXEC_CTRL1, secondary); 3570 vmcs_write(CPU_EXEC_CTRL0, primary); 3571 } 3572 3573 static void try_cr3_target_count(unsigned i, unsigned max) 3574 { 3575 report_prefix_pushf("CR3 target count 0x%x", i); 3576 vmcs_write(CR3_TARGET_COUNT, i); 3577 if (i <= max) 3578 test_vmx_valid_controls(); 3579 else 3580 test_vmx_invalid_controls(); 3581 report_prefix_pop(); 3582 } 3583 3584 /* 3585 * The CR3-target count must not be greater than 4. Future processors 3586 * may support a different number of CR3-target values. Software 3587 * should read the VMX capability MSR IA32_VMX_MISC to determine the 3588 * number of values supported. 3589 * [Intel SDM] 3590 */ 3591 static void test_cr3_targets(void) 3592 { 3593 unsigned supported_targets = (rdmsr(MSR_IA32_VMX_MISC) >> 16) & 0x1ff; 3594 u32 cr3_targets = vmcs_read(CR3_TARGET_COUNT); 3595 unsigned i; 3596 3597 printf("\nSupported CR3 targets: %d\n", supported_targets); 3598 TEST_ASSERT(supported_targets <= 256); 3599 3600 try_cr3_target_count(-1u, supported_targets); 3601 try_cr3_target_count(0x80000000, supported_targets); 3602 try_cr3_target_count(0x7fffffff, supported_targets); 3603 for (i = 0; i <= supported_targets + 1; i++) 3604 try_cr3_target_count(i, supported_targets); 3605 vmcs_write(CR3_TARGET_COUNT, cr3_targets); 3606 3607 /* VMWRITE to nonexistent target fields should fail. */ 3608 for (i = supported_targets; i < 256; i++) 3609 TEST_ASSERT(vmcs_write(CR3_TARGET_0 + i*2, 0)); 3610 } 3611 3612 /* 3613 * Test a particular address setting in the VMCS 3614 */ 3615 static void test_vmcs_addr(const char *name, 3616 enum Encoding encoding, 3617 u64 align, 3618 bool ignored, 3619 bool skip_beyond_mapped_ram, 3620 u64 addr) 3621 { 3622 report_prefix_pushf("%s = %lx", name, addr); 3623 vmcs_write(encoding, addr); 3624 if (skip_beyond_mapped_ram && 3625 addr > fwcfg_get_u64(FW_CFG_RAM_SIZE) - align && 3626 addr < (1ul << cpuid_maxphyaddr())) 3627 printf("Skipping physical address beyond mapped RAM\n"); 3628 else if (ignored || (IS_ALIGNED(addr, align) && 3629 addr < (1ul << cpuid_maxphyaddr()))) 3630 test_vmx_valid_controls(); 3631 else 3632 test_vmx_invalid_controls(); 3633 report_prefix_pop(); 3634 } 3635 3636 /* 3637 * Test interesting values for a VMCS address 3638 */ 3639 static void test_vmcs_addr_values(const char *name, 3640 enum Encoding encoding, 3641 u64 align, 3642 bool ignored, 3643 bool skip_beyond_mapped_ram, 3644 u32 bit_start, u32 bit_end) 3645 { 3646 unsigned i; 3647 u64 orig_val = vmcs_read(encoding); 3648 3649 for (i = bit_start; i <= bit_end; i++) 3650 test_vmcs_addr(name, encoding, align, ignored, 3651 skip_beyond_mapped_ram, 1ul << i); 3652 3653 test_vmcs_addr(name, encoding, align, ignored, 3654 skip_beyond_mapped_ram, PAGE_SIZE - 1); 3655 test_vmcs_addr(name, encoding, align, ignored, 3656 skip_beyond_mapped_ram, PAGE_SIZE); 3657 test_vmcs_addr(name, encoding, align, ignored, 3658 skip_beyond_mapped_ram, 3659 (1ul << cpuid_maxphyaddr()) - PAGE_SIZE); 3660 test_vmcs_addr(name, encoding, align, ignored, 3661 skip_beyond_mapped_ram, -1ul); 3662 3663 vmcs_write(encoding, orig_val); 3664 } 3665 3666 /* 3667 * Test a physical address reference in the VMCS, when the corresponding 3668 * feature is enabled and when the corresponding feature is disabled. 3669 */ 3670 static void test_vmcs_addr_reference(u32 control_bit, enum Encoding field, 3671 const char *field_name, 3672 const char *control_name, u64 align, 3673 bool skip_beyond_mapped_ram, 3674 bool control_primary) 3675 { 3676 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 3677 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 3678 u64 page_addr; 3679 3680 if (control_primary) { 3681 if (!(ctrl_cpu_rev[0].clr & control_bit)) 3682 return; 3683 } else { 3684 if (!(ctrl_cpu_rev[1].clr & control_bit)) 3685 return; 3686 } 3687 3688 page_addr = vmcs_read(field); 3689 3690 report_prefix_pushf("%s enabled", control_name); 3691 if (control_primary) { 3692 vmcs_write(CPU_EXEC_CTRL0, primary | control_bit); 3693 } else { 3694 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3695 vmcs_write(CPU_EXEC_CTRL1, secondary | control_bit); 3696 } 3697 3698 test_vmcs_addr_values(field_name, field, align, false, 3699 skip_beyond_mapped_ram, 0, 63); 3700 report_prefix_pop(); 3701 3702 report_prefix_pushf("%s disabled", control_name); 3703 if (control_primary) { 3704 vmcs_write(CPU_EXEC_CTRL0, primary & ~control_bit); 3705 } else { 3706 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3707 vmcs_write(CPU_EXEC_CTRL1, secondary & ~control_bit); 3708 } 3709 3710 test_vmcs_addr_values(field_name, field, align, true, false, 0, 63); 3711 report_prefix_pop(); 3712 3713 vmcs_write(field, page_addr); 3714 vmcs_write(CPU_EXEC_CTRL0, primary); 3715 vmcs_write(CPU_EXEC_CTRL1, secondary); 3716 } 3717 3718 /* 3719 * If the "use I/O bitmaps" VM-execution control is 1, bits 11:0 of 3720 * each I/O-bitmap address must be 0. Neither address should set any 3721 * bits beyond the processor's physical-address width. 3722 * [Intel SDM] 3723 */ 3724 static void test_io_bitmaps(void) 3725 { 3726 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_A, 3727 "I/O bitmap A", "Use I/O bitmaps", 3728 PAGE_SIZE, false, true); 3729 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_B, 3730 "I/O bitmap B", "Use I/O bitmaps", 3731 PAGE_SIZE, false, true); 3732 } 3733 3734 /* 3735 * If the "use MSR bitmaps" VM-execution control is 1, bits 11:0 of 3736 * the MSR-bitmap address must be 0. The address should not set any 3737 * bits beyond the processor's physical-address width. 3738 * [Intel SDM] 3739 */ 3740 static void test_msr_bitmap(void) 3741 { 3742 test_vmcs_addr_reference(CPU_MSR_BITMAP, MSR_BITMAP, 3743 "MSR bitmap", "Use MSR bitmaps", 3744 PAGE_SIZE, false, true); 3745 } 3746 3747 /* 3748 * If the "use TPR shadow" VM-execution control is 1, the virtual-APIC 3749 * address must satisfy the following checks: 3750 * - Bits 11:0 of the address must be 0. 3751 * - The address should not set any bits beyond the processor's 3752 * physical-address width. 3753 * [Intel SDM] 3754 */ 3755 static void test_apic_virt_addr(void) 3756 { 3757 /* 3758 * Ensure the processor will never use the virtual-APIC page, since 3759 * we will point it to invalid RAM. Otherwise KVM is puzzled about 3760 * what we're trying to achieve and fails vmentry. 3761 */ 3762 u32 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 3763 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0 | CPU_CR8_LOAD | CPU_CR8_STORE); 3764 test_vmcs_addr_reference(CPU_TPR_SHADOW, APIC_VIRT_ADDR, 3765 "virtual-APIC address", "Use TPR shadow", 3766 PAGE_SIZE, false, true); 3767 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 3768 } 3769 3770 /* 3771 * If the "virtualize APIC-accesses" VM-execution control is 1, the 3772 * APIC-access address must satisfy the following checks: 3773 * - Bits 11:0 of the address must be 0. 3774 * - The address should not set any bits beyond the processor's 3775 * physical-address width. 3776 * [Intel SDM] 3777 */ 3778 static void test_apic_access_addr(void) 3779 { 3780 void *apic_access_page = alloc_page(); 3781 3782 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_page)); 3783 3784 test_vmcs_addr_reference(CPU_VIRT_APIC_ACCESSES, APIC_ACCS_ADDR, 3785 "APIC-access address", 3786 "virtualize APIC-accesses", PAGE_SIZE, 3787 true, false); 3788 } 3789 3790 static bool set_bit_pattern(u8 mask, u32 *secondary) 3791 { 3792 u8 i; 3793 bool flag = false; 3794 u32 test_bits[3] = { 3795 CPU_VIRT_X2APIC, 3796 CPU_APIC_REG_VIRT, 3797 CPU_VINTD 3798 }; 3799 3800 for (i = 0; i < ARRAY_SIZE(test_bits); i++) { 3801 if ((mask & (1u << i)) && 3802 (ctrl_cpu_rev[1].clr & test_bits[i])) { 3803 *secondary |= test_bits[i]; 3804 flag = true; 3805 } 3806 } 3807 3808 return (flag); 3809 } 3810 3811 /* 3812 * If the "use TPR shadow" VM-execution control is 0, the following 3813 * VM-execution controls must also be 0: 3814 * - virtualize x2APIC mode 3815 * - APIC-register virtualization 3816 * - virtual-interrupt delivery 3817 * [Intel SDM] 3818 * 3819 * 2. If the "virtualize x2APIC mode" VM-execution control is 1, the 3820 * "virtualize APIC accesses" VM-execution control must be 0. 3821 * [Intel SDM] 3822 */ 3823 static void test_apic_virtual_ctls(void) 3824 { 3825 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3826 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3827 u32 primary = saved_primary; 3828 u32 secondary = saved_secondary; 3829 bool is_ctrl_valid = false; 3830 char str[10] = "disabled"; 3831 u8 i = 0, j; 3832 3833 /* 3834 * First test 3835 */ 3836 if (!((ctrl_cpu_rev[0].clr & (CPU_SECONDARY | CPU_TPR_SHADOW)) == 3837 (CPU_SECONDARY | CPU_TPR_SHADOW))) 3838 return; 3839 3840 primary |= CPU_SECONDARY; 3841 primary &= ~CPU_TPR_SHADOW; 3842 vmcs_write(CPU_EXEC_CTRL0, primary); 3843 3844 while (1) { 3845 for (j = 1; j < 8; j++) { 3846 secondary &= ~(CPU_VIRT_X2APIC | CPU_APIC_REG_VIRT | CPU_VINTD); 3847 if (primary & CPU_TPR_SHADOW) { 3848 is_ctrl_valid = true; 3849 } else { 3850 if (! set_bit_pattern(j, &secondary)) 3851 is_ctrl_valid = true; 3852 else 3853 is_ctrl_valid = false; 3854 } 3855 3856 vmcs_write(CPU_EXEC_CTRL1, secondary); 3857 report_prefix_pushf("Use TPR shadow %s, virtualize x2APIC mode %s, APIC-register virtualization %s, virtual-interrupt delivery %s", 3858 str, (secondary & CPU_VIRT_X2APIC) ? "enabled" : "disabled", (secondary & CPU_APIC_REG_VIRT) ? "enabled" : "disabled", (secondary & CPU_VINTD) ? "enabled" : "disabled"); 3859 if (is_ctrl_valid) 3860 test_vmx_valid_controls(); 3861 else 3862 test_vmx_invalid_controls(); 3863 report_prefix_pop(); 3864 } 3865 3866 if (i == 1) 3867 break; 3868 i++; 3869 3870 primary |= CPU_TPR_SHADOW; 3871 vmcs_write(CPU_EXEC_CTRL0, primary); 3872 strcpy(str, "enabled"); 3873 } 3874 3875 /* 3876 * Second test 3877 */ 3878 u32 apic_virt_ctls = (CPU_VIRT_X2APIC | CPU_VIRT_APIC_ACCESSES); 3879 3880 primary = saved_primary; 3881 secondary = saved_secondary; 3882 if (!((ctrl_cpu_rev[1].clr & apic_virt_ctls) == apic_virt_ctls)) 3883 return; 3884 3885 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3886 secondary &= ~CPU_VIRT_APIC_ACCESSES; 3887 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_X2APIC); 3888 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access disabled"); 3889 test_vmx_valid_controls(); 3890 report_prefix_pop(); 3891 3892 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_APIC_ACCESSES); 3893 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access enabled"); 3894 test_vmx_valid_controls(); 3895 report_prefix_pop(); 3896 3897 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_X2APIC); 3898 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access enabled"); 3899 test_vmx_invalid_controls(); 3900 report_prefix_pop(); 3901 3902 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_APIC_ACCESSES); 3903 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access disabled"); 3904 test_vmx_valid_controls(); 3905 report_prefix_pop(); 3906 3907 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3908 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3909 } 3910 3911 /* 3912 * If the "virtual-interrupt delivery" VM-execution control is 1, the 3913 * "external-interrupt exiting" VM-execution control must be 1. 3914 * [Intel SDM] 3915 */ 3916 static void test_virtual_intr_ctls(void) 3917 { 3918 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3919 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3920 u32 saved_pin = vmcs_read(PIN_CONTROLS); 3921 u32 primary = saved_primary; 3922 u32 secondary = saved_secondary; 3923 u32 pin = saved_pin; 3924 3925 if (!((ctrl_cpu_rev[1].clr & CPU_VINTD) && 3926 (ctrl_pin_rev.clr & PIN_EXTINT))) 3927 return; 3928 3929 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 3930 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VINTD); 3931 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 3932 report_prefix_pushf("Virtualize interrupt-delivery disabled; external-interrupt exiting disabled"); 3933 test_vmx_valid_controls(); 3934 report_prefix_pop(); 3935 3936 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VINTD); 3937 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 3938 test_vmx_invalid_controls(); 3939 report_prefix_pop(); 3940 3941 vmcs_write(PIN_CONTROLS, pin | PIN_EXTINT); 3942 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting enabled"); 3943 test_vmx_valid_controls(); 3944 report_prefix_pop(); 3945 3946 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 3947 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 3948 test_vmx_invalid_controls(); 3949 report_prefix_pop(); 3950 3951 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3952 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3953 vmcs_write(PIN_CONTROLS, saved_pin); 3954 } 3955 3956 static void test_pi_desc_addr(u64 addr, bool is_ctrl_valid) 3957 { 3958 vmcs_write(POSTED_INTR_DESC_ADDR, addr); 3959 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-descriptor-address 0x%lx", addr); 3960 if (is_ctrl_valid) 3961 test_vmx_valid_controls(); 3962 else 3963 test_vmx_invalid_controls(); 3964 report_prefix_pop(); 3965 } 3966 3967 /* 3968 * If the "process posted interrupts" VM-execution control is 1, the 3969 * following must be true: 3970 * 3971 * - The "virtual-interrupt delivery" VM-execution control is 1. 3972 * - The "acknowledge interrupt on exit" VM-exit control is 1. 3973 * - The posted-interrupt notification vector has a value in the 3974 * - range 0 - 255 (bits 15:8 are all 0). 3975 * - Bits 5:0 of the posted-interrupt descriptor address are all 0. 3976 * - The posted-interrupt descriptor address does not set any bits 3977 * beyond the processor's physical-address width. 3978 * [Intel SDM] 3979 */ 3980 static void test_posted_intr(void) 3981 { 3982 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3983 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3984 u32 saved_pin = vmcs_read(PIN_CONTROLS); 3985 u32 exit_ctl_saved = vmcs_read(EXI_CONTROLS); 3986 u32 primary = saved_primary; 3987 u32 secondary = saved_secondary; 3988 u32 pin = saved_pin; 3989 u32 exit_ctl = exit_ctl_saved; 3990 u16 vec; 3991 int i; 3992 3993 if (!((ctrl_pin_rev.clr & PIN_POST_INTR) && 3994 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 3995 (ctrl_exit_rev.clr & EXI_INTA))) 3996 return; 3997 3998 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 3999 4000 /* 4001 * Test virtual-interrupt-delivery and acknowledge-interrupt-on-exit 4002 */ 4003 pin |= PIN_POST_INTR; 4004 vmcs_write(PIN_CONTROLS, pin); 4005 secondary &= ~CPU_VINTD; 4006 vmcs_write(CPU_EXEC_CTRL1, secondary); 4007 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled"); 4008 test_vmx_invalid_controls(); 4009 report_prefix_pop(); 4010 4011 secondary |= CPU_VINTD; 4012 vmcs_write(CPU_EXEC_CTRL1, secondary); 4013 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled"); 4014 test_vmx_invalid_controls(); 4015 report_prefix_pop(); 4016 4017 exit_ctl &= ~EXI_INTA; 4018 vmcs_write(EXI_CONTROLS, exit_ctl); 4019 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit disabled"); 4020 test_vmx_invalid_controls(); 4021 report_prefix_pop(); 4022 4023 exit_ctl |= EXI_INTA; 4024 vmcs_write(EXI_CONTROLS, exit_ctl); 4025 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 4026 test_vmx_valid_controls(); 4027 report_prefix_pop(); 4028 4029 secondary &= ~CPU_VINTD; 4030 vmcs_write(CPU_EXEC_CTRL1, secondary); 4031 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled; acknowledge-interrupt-on-exit enabled"); 4032 test_vmx_invalid_controls(); 4033 report_prefix_pop(); 4034 4035 secondary |= CPU_VINTD; 4036 vmcs_write(CPU_EXEC_CTRL1, secondary); 4037 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 4038 test_vmx_valid_controls(); 4039 report_prefix_pop(); 4040 4041 /* 4042 * Test posted-interrupt notification vector 4043 */ 4044 for (i = 0; i < 8; i++) { 4045 vec = (1ul << i); 4046 vmcs_write(PINV, vec); 4047 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 4048 test_vmx_valid_controls(); 4049 report_prefix_pop(); 4050 } 4051 for (i = 8; i < 16; i++) { 4052 vec = (1ul << i); 4053 vmcs_write(PINV, vec); 4054 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 4055 test_vmx_invalid_controls(); 4056 report_prefix_pop(); 4057 } 4058 4059 vec &= ~(0xff << 8); 4060 vmcs_write(PINV, vec); 4061 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 4062 test_vmx_valid_controls(); 4063 report_prefix_pop(); 4064 4065 /* 4066 * Test posted-interrupt descriptor address 4067 */ 4068 for (i = 0; i < 6; i++) { 4069 test_pi_desc_addr(1ul << i, false); 4070 } 4071 4072 test_pi_desc_addr(0xf0, false); 4073 test_pi_desc_addr(0xff, false); 4074 test_pi_desc_addr(0x0f, false); 4075 test_pi_desc_addr(0x8000, true); 4076 test_pi_desc_addr(0x00, true); 4077 test_pi_desc_addr(0xc000, true); 4078 4079 test_vmcs_addr_values("process-posted interrupts", 4080 POSTED_INTR_DESC_ADDR, 64, 4081 false, false, 0, 63); 4082 4083 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 4084 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 4085 vmcs_write(PIN_CONTROLS, saved_pin); 4086 } 4087 4088 static void test_apic_ctls(void) 4089 { 4090 test_apic_virt_addr(); 4091 test_apic_access_addr(); 4092 test_apic_virtual_ctls(); 4093 test_virtual_intr_ctls(); 4094 test_posted_intr(); 4095 } 4096 4097 /* 4098 * If the "enable VPID" VM-execution control is 1, the value of the 4099 * of the VPID VM-execution control field must not be 0000H. 4100 * [Intel SDM] 4101 */ 4102 static void test_vpid(void) 4103 { 4104 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 4105 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 4106 u16 vpid = 0x0000; 4107 int i; 4108 4109 if (!is_vpid_supported()) { 4110 printf("Secondary controls and/or VPID not supported\n"); 4111 return; 4112 } 4113 4114 vmcs_write(CPU_EXEC_CTRL0, saved_primary | CPU_SECONDARY); 4115 vmcs_write(CPU_EXEC_CTRL1, saved_secondary & ~CPU_VPID); 4116 vmcs_write(VPID, vpid); 4117 report_prefix_pushf("VPID disabled; VPID value %x", vpid); 4118 test_vmx_valid_controls(); 4119 report_prefix_pop(); 4120 4121 vmcs_write(CPU_EXEC_CTRL1, saved_secondary | CPU_VPID); 4122 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 4123 test_vmx_invalid_controls(); 4124 report_prefix_pop(); 4125 4126 for (i = 0; i < 16; i++) { 4127 vpid = (short)1 << i;; 4128 vmcs_write(VPID, vpid); 4129 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 4130 test_vmx_valid_controls(); 4131 report_prefix_pop(); 4132 } 4133 4134 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 4135 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 4136 } 4137 4138 static void set_vtpr(unsigned vtpr) 4139 { 4140 *(u32 *)phys_to_virt(vmcs_read(APIC_VIRT_ADDR) + APIC_TASKPRI) = vtpr; 4141 } 4142 4143 static void try_tpr_threshold_and_vtpr(unsigned threshold, unsigned vtpr) 4144 { 4145 bool valid = true; 4146 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4147 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4148 4149 if ((primary & CPU_TPR_SHADOW) && 4150 (!(primary & CPU_SECONDARY) || 4151 !(secondary & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 4152 valid = (threshold & 0xf) <= ((vtpr >> 4) & 0xf); 4153 4154 set_vtpr(vtpr); 4155 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0x%x", 4156 threshold, (vtpr >> 4) & 0xf); 4157 if (valid) 4158 test_vmx_valid_controls(); 4159 else 4160 test_vmx_invalid_controls(); 4161 report_prefix_pop(); 4162 } 4163 4164 static void test_invalid_event_injection(void) 4165 { 4166 u32 ent_intr_info_save = vmcs_read(ENT_INTR_INFO); 4167 u32 ent_intr_error_save = vmcs_read(ENT_INTR_ERROR); 4168 u32 ent_inst_len_save = vmcs_read(ENT_INST_LEN); 4169 u32 primary_save = vmcs_read(CPU_EXEC_CTRL0); 4170 u32 secondary_save = vmcs_read(CPU_EXEC_CTRL1); 4171 u64 guest_cr0_save = vmcs_read(GUEST_CR0); 4172 u32 ent_intr_info_base = INTR_INFO_VALID_MASK; 4173 u32 ent_intr_info, ent_intr_err, ent_intr_len; 4174 u32 cnt; 4175 4176 /* Setup */ 4177 report_prefix_push("invalid event injection"); 4178 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4179 vmcs_write(ENT_INST_LEN, 0x00000001); 4180 4181 /* The field's interruption type is not set to a reserved value. */ 4182 ent_intr_info = ent_intr_info_base | INTR_TYPE_RESERVED | DE_VECTOR; 4183 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4184 "RESERVED interruption type invalid [-]", 4185 ent_intr_info); 4186 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4187 test_vmx_invalid_controls(); 4188 report_prefix_pop(); 4189 4190 ent_intr_info = ent_intr_info_base | INTR_TYPE_EXT_INTR | 4191 DE_VECTOR; 4192 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4193 "RESERVED interruption type invalid [+]", 4194 ent_intr_info); 4195 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4196 test_vmx_valid_controls(); 4197 report_prefix_pop(); 4198 4199 /* If the interruption type is other event, the vector is 0. */ 4200 ent_intr_info = ent_intr_info_base | INTR_TYPE_OTHER_EVENT | DB_VECTOR; 4201 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4202 "(OTHER EVENT && vector != 0) invalid [-]", 4203 ent_intr_info); 4204 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4205 test_vmx_invalid_controls(); 4206 report_prefix_pop(); 4207 4208 /* If the interruption type is NMI, the vector is 2 (negative case). */ 4209 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | DE_VECTOR; 4210 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4211 "(NMI && vector != 2) invalid [-]", ent_intr_info); 4212 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4213 test_vmx_invalid_controls(); 4214 report_prefix_pop(); 4215 4216 /* If the interruption type is NMI, the vector is 2 (positive case). */ 4217 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | NMI_VECTOR; 4218 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4219 "(NMI && vector == 2) valid [+]", ent_intr_info); 4220 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4221 test_vmx_valid_controls(); 4222 report_prefix_pop(); 4223 4224 /* 4225 * If the interruption type 4226 * is HW exception, the vector is at most 31. 4227 */ 4228 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 0x20; 4229 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4230 "(HW exception && vector > 31) invalid [-]", 4231 ent_intr_info); 4232 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4233 test_vmx_invalid_controls(); 4234 report_prefix_pop(); 4235 4236 /* 4237 * deliver-error-code is 1 iff either 4238 * (a) the "unrestricted guest" VM-execution control is 0 4239 * (b) CR0.PE is set. 4240 */ 4241 4242 /* Assert that unrestricted guest is disabled or unsupported */ 4243 assert(!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 4244 !(secondary_save & CPU_URG)); 4245 4246 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4247 GP_VECTOR; 4248 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4249 "error code <-> (!URG || prot_mode) [-]", 4250 ent_intr_info); 4251 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4252 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4253 test_vmx_invalid_controls(); 4254 report_prefix_pop(); 4255 4256 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4257 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4258 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4259 "error code <-> (!URG || prot_mode) [+]", 4260 ent_intr_info); 4261 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4262 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4263 test_vmx_valid_controls(); 4264 report_prefix_pop(); 4265 4266 if (enable_unrestricted_guest(false)) 4267 goto skip_unrestricted_guest; 4268 4269 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4270 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4271 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4272 "error code <-> (!URG || prot_mode) [-]", 4273 ent_intr_info); 4274 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4275 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4276 test_vmx_invalid_controls(); 4277 report_prefix_pop(); 4278 4279 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4280 GP_VECTOR; 4281 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4282 "error code <-> (!URG || prot_mode) [-]", 4283 ent_intr_info); 4284 vmcs_write(GUEST_CR0, guest_cr0_save | X86_CR0_PE); 4285 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4286 test_vmx_invalid_controls(); 4287 report_prefix_pop(); 4288 4289 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4290 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4291 4292 skip_unrestricted_guest: 4293 vmcs_write(GUEST_CR0, guest_cr0_save); 4294 4295 /* deliver-error-code is 1 iff the interruption type is HW exception */ 4296 report_prefix_push("error code <-> HW exception"); 4297 for (cnt = 0; cnt < 8; cnt++) { 4298 u32 exception_type_mask = cnt << 8; 4299 u32 deliver_error_code_mask = 4300 exception_type_mask != INTR_TYPE_HARD_EXCEPTION ? 4301 INTR_INFO_DELIVER_CODE_MASK : 0; 4302 4303 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4304 exception_type_mask | GP_VECTOR; 4305 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4306 ent_intr_info); 4307 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4308 test_vmx_invalid_controls(); 4309 report_prefix_pop(); 4310 } 4311 report_prefix_pop(); 4312 4313 /* 4314 * deliver-error-code is 1 iff the the vector 4315 * indicates an exception that would normally deliver an error code 4316 */ 4317 report_prefix_push("error code <-> vector delivers error code"); 4318 for (cnt = 0; cnt < 32; cnt++) { 4319 bool has_error_code = false; 4320 u32 deliver_error_code_mask; 4321 4322 switch (cnt) { 4323 case DF_VECTOR: 4324 case TS_VECTOR: 4325 case NP_VECTOR: 4326 case SS_VECTOR: 4327 case GP_VECTOR: 4328 case PF_VECTOR: 4329 case AC_VECTOR: 4330 has_error_code = true; 4331 case CP_VECTOR: 4332 /* Some CPUs have error code and some do not, skip */ 4333 continue; 4334 } 4335 4336 /* Negative case */ 4337 deliver_error_code_mask = has_error_code ? 4338 0 : 4339 INTR_INFO_DELIVER_CODE_MASK; 4340 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4341 INTR_TYPE_HARD_EXCEPTION | cnt; 4342 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4343 ent_intr_info); 4344 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4345 test_vmx_invalid_controls(); 4346 report_prefix_pop(); 4347 4348 /* Positive case */ 4349 deliver_error_code_mask = has_error_code ? 4350 INTR_INFO_DELIVER_CODE_MASK : 4351 0; 4352 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4353 INTR_TYPE_HARD_EXCEPTION | cnt; 4354 report_prefix_pushf("VM-entry intr info=0x%x [+]", 4355 ent_intr_info); 4356 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4357 test_vmx_valid_controls(); 4358 report_prefix_pop(); 4359 } 4360 report_prefix_pop(); 4361 4362 /* Reserved bits in the field (30:12) are 0. */ 4363 report_prefix_push("reserved bits clear"); 4364 for (cnt = 12; cnt <= 30; cnt++) { 4365 ent_intr_info = ent_intr_info_base | 4366 INTR_INFO_DELIVER_CODE_MASK | 4367 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR | 4368 (1U << cnt); 4369 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4370 ent_intr_info); 4371 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4372 test_vmx_invalid_controls(); 4373 report_prefix_pop(); 4374 } 4375 report_prefix_pop(); 4376 4377 /* 4378 * If deliver-error-code is 1 4379 * bits 31:16 of the VM-entry exception error-code field are 0. 4380 */ 4381 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4382 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4383 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4384 "VM-entry exception error code[31:16] clear", 4385 ent_intr_info); 4386 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4387 for (cnt = 16; cnt <= 31; cnt++) { 4388 ent_intr_err = 1U << cnt; 4389 report_prefix_pushf("VM-entry intr error=0x%x [-]", 4390 ent_intr_err); 4391 vmcs_write(ENT_INTR_ERROR, ent_intr_err); 4392 test_vmx_invalid_controls(); 4393 report_prefix_pop(); 4394 } 4395 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4396 report_prefix_pop(); 4397 4398 /* 4399 * If the interruption type is software interrupt, software exception, 4400 * or privileged software exception, the VM-entry instruction-length 4401 * field is in the range 0 - 15. 4402 */ 4403 4404 for (cnt = 0; cnt < 3; cnt++) { 4405 switch (cnt) { 4406 case 0: 4407 ent_intr_info = ent_intr_info_base | 4408 INTR_TYPE_SOFT_INTR; 4409 break; 4410 case 1: 4411 ent_intr_info = ent_intr_info_base | 4412 INTR_TYPE_SOFT_EXCEPTION; 4413 break; 4414 case 2: 4415 ent_intr_info = ent_intr_info_base | 4416 INTR_TYPE_PRIV_SW_EXCEPTION; 4417 break; 4418 } 4419 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4420 "VM-entry instruction-length check", 4421 ent_intr_info); 4422 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4423 4424 /* Instruction length set to -1 (0xFFFFFFFF) should fail */ 4425 ent_intr_len = -1; 4426 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4427 ent_intr_len); 4428 vmcs_write(ENT_INST_LEN, ent_intr_len); 4429 test_vmx_invalid_controls(); 4430 report_prefix_pop(); 4431 4432 /* Instruction length set to 16 should fail */ 4433 ent_intr_len = 0x00000010; 4434 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4435 ent_intr_len); 4436 vmcs_write(ENT_INST_LEN, 0x00000010); 4437 test_vmx_invalid_controls(); 4438 report_prefix_pop(); 4439 4440 report_prefix_pop(); 4441 } 4442 4443 /* Cleanup */ 4444 vmcs_write(ENT_INTR_INFO, ent_intr_info_save); 4445 vmcs_write(ENT_INTR_ERROR, ent_intr_error_save); 4446 vmcs_write(ENT_INST_LEN, ent_inst_len_save); 4447 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4448 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4449 vmcs_write(GUEST_CR0, guest_cr0_save); 4450 report_prefix_pop(); 4451 } 4452 4453 /* 4454 * Test interesting vTPR values for a given TPR threshold. 4455 */ 4456 static void test_vtpr_values(unsigned threshold) 4457 { 4458 try_tpr_threshold_and_vtpr(threshold, (threshold - 1) << 4); 4459 try_tpr_threshold_and_vtpr(threshold, threshold << 4); 4460 try_tpr_threshold_and_vtpr(threshold, (threshold + 1) << 4); 4461 } 4462 4463 static void try_tpr_threshold(unsigned threshold) 4464 { 4465 bool valid = true; 4466 4467 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4468 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4469 4470 if ((primary & CPU_TPR_SHADOW) && !((primary & CPU_SECONDARY) && 4471 (secondary & CPU_VINTD))) 4472 valid = !(threshold >> 4); 4473 4474 set_vtpr(-1); 4475 vmcs_write(TPR_THRESHOLD, threshold); 4476 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0xf", threshold); 4477 if (valid) 4478 test_vmx_valid_controls(); 4479 else 4480 test_vmx_invalid_controls(); 4481 report_prefix_pop(); 4482 4483 if (valid) 4484 test_vtpr_values(threshold); 4485 } 4486 4487 /* 4488 * Test interesting TPR threshold values. 4489 */ 4490 static void test_tpr_threshold_values(void) 4491 { 4492 unsigned i; 4493 4494 for (i = 0; i < 0x10; i++) 4495 try_tpr_threshold(i); 4496 for (i = 4; i < 32; i++) 4497 try_tpr_threshold(1u << i); 4498 try_tpr_threshold(-1u); 4499 try_tpr_threshold(0x7fffffff); 4500 } 4501 4502 /* 4503 * This test covers the following two VM entry checks: 4504 * 4505 * i) If the "use TPR shadow" VM-execution control is 1 and the 4506 * "virtual-interrupt delivery" VM-execution control is 0, bits 4507 * 31:4 of the TPR threshold VM-execution control field must 4508 be 0. 4509 * [Intel SDM] 4510 * 4511 * ii) If the "use TPR shadow" VM-execution control is 1, the 4512 * "virtual-interrupt delivery" VM-execution control is 0 4513 * and the "virtualize APIC accesses" VM-execution control 4514 * is 0, the value of bits 3:0 of the TPR threshold VM-execution 4515 * control field must not be greater than the value of bits 4516 * 7:4 of VTPR. 4517 * [Intel SDM] 4518 */ 4519 static void test_tpr_threshold(void) 4520 { 4521 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4522 u64 apic_virt_addr = vmcs_read(APIC_VIRT_ADDR); 4523 u64 threshold = vmcs_read(TPR_THRESHOLD); 4524 void *virtual_apic_page; 4525 4526 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) 4527 return; 4528 4529 virtual_apic_page = alloc_page(); 4530 memset(virtual_apic_page, 0xff, PAGE_SIZE); 4531 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 4532 4533 vmcs_write(CPU_EXEC_CTRL0, primary & ~(CPU_TPR_SHADOW | CPU_SECONDARY)); 4534 report_prefix_pushf("Use TPR shadow disabled, secondary controls disabled"); 4535 test_tpr_threshold_values(); 4536 report_prefix_pop(); 4537 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_TPR_SHADOW); 4538 report_prefix_pushf("Use TPR shadow enabled, secondary controls disabled"); 4539 test_tpr_threshold_values(); 4540 report_prefix_pop(); 4541 4542 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4543 (ctrl_cpu_rev[1].clr & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 4544 goto out; 4545 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4546 4547 if (ctrl_cpu_rev[1].clr & CPU_VINTD) { 4548 vmcs_write(CPU_EXEC_CTRL1, CPU_VINTD); 4549 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4550 test_tpr_threshold_values(); 4551 report_prefix_pop(); 4552 4553 vmcs_write(CPU_EXEC_CTRL0, 4554 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4555 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4556 test_tpr_threshold_values(); 4557 report_prefix_pop(); 4558 } 4559 4560 if (ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES) { 4561 vmcs_write(CPU_EXEC_CTRL0, 4562 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4563 vmcs_write(CPU_EXEC_CTRL1, CPU_VIRT_APIC_ACCESSES); 4564 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4565 test_tpr_threshold_values(); 4566 report_prefix_pop(); 4567 4568 vmcs_write(CPU_EXEC_CTRL0, 4569 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4570 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4571 test_tpr_threshold_values(); 4572 report_prefix_pop(); 4573 } 4574 4575 if ((ctrl_cpu_rev[1].clr & 4576 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) == 4577 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) { 4578 vmcs_write(CPU_EXEC_CTRL0, 4579 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4580 vmcs_write(CPU_EXEC_CTRL1, 4581 CPU_VINTD | CPU_VIRT_APIC_ACCESSES); 4582 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4583 test_tpr_threshold_values(); 4584 report_prefix_pop(); 4585 4586 vmcs_write(CPU_EXEC_CTRL0, 4587 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4588 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4589 test_tpr_threshold_values(); 4590 report_prefix_pop(); 4591 } 4592 4593 vmcs_write(CPU_EXEC_CTRL1, secondary); 4594 out: 4595 vmcs_write(TPR_THRESHOLD, threshold); 4596 vmcs_write(APIC_VIRT_ADDR, apic_virt_addr); 4597 vmcs_write(CPU_EXEC_CTRL0, primary); 4598 } 4599 4600 /* 4601 * This test verifies the following two vmentry checks: 4602 * 4603 * If the "NMI exiting" VM-execution control is 0, "Virtual NMIs" 4604 * VM-execution control must be 0. 4605 * [Intel SDM] 4606 * 4607 * If the "virtual NMIs" VM-execution control is 0, the "NMI-window 4608 * exiting" VM-execution control must be 0. 4609 * [Intel SDM] 4610 */ 4611 static void test_nmi_ctrls(void) 4612 { 4613 u32 pin_ctrls, cpu_ctrls0, test_pin_ctrls, test_cpu_ctrls0; 4614 4615 if ((ctrl_pin_rev.clr & (PIN_NMI | PIN_VIRT_NMI)) != 4616 (PIN_NMI | PIN_VIRT_NMI)) { 4617 printf("NMI exiting and Virtual NMIs are not supported !\n"); 4618 return; 4619 } 4620 4621 /* Save the controls so that we can restore them after our tests */ 4622 pin_ctrls = vmcs_read(PIN_CONTROLS); 4623 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 4624 4625 test_pin_ctrls = pin_ctrls & ~(PIN_NMI | PIN_VIRT_NMI); 4626 test_cpu_ctrls0 = cpu_ctrls0 & ~CPU_NMI_WINDOW; 4627 4628 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4629 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs disabled"); 4630 test_vmx_valid_controls(); 4631 report_prefix_pop(); 4632 4633 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_VIRT_NMI); 4634 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs enabled"); 4635 test_vmx_invalid_controls(); 4636 report_prefix_pop(); 4637 4638 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4639 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs enabled"); 4640 test_vmx_valid_controls(); 4641 report_prefix_pop(); 4642 4643 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_NMI); 4644 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs disabled"); 4645 test_vmx_valid_controls(); 4646 report_prefix_pop(); 4647 4648 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 4649 report_info("NMI-window exiting is not supported, skipping..."); 4650 goto done; 4651 } 4652 4653 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4654 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4655 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting enabled"); 4656 test_vmx_invalid_controls(); 4657 report_prefix_pop(); 4658 4659 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4660 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4661 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting disabled"); 4662 test_vmx_valid_controls(); 4663 report_prefix_pop(); 4664 4665 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4666 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4667 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting enabled"); 4668 test_vmx_valid_controls(); 4669 report_prefix_pop(); 4670 4671 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4672 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4673 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting disabled"); 4674 test_vmx_valid_controls(); 4675 report_prefix_pop(); 4676 4677 /* Restore the controls to their original values */ 4678 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 4679 done: 4680 vmcs_write(PIN_CONTROLS, pin_ctrls); 4681 } 4682 4683 static void test_eptp_ad_bit(u64 eptp, bool is_ctrl_valid) 4684 { 4685 vmcs_write(EPTP, eptp); 4686 report_prefix_pushf("Enable-EPT enabled; EPT accessed and dirty flag %s", 4687 (eptp & EPTP_AD_FLAG) ? "1": "0"); 4688 if (is_ctrl_valid) 4689 test_vmx_valid_controls(); 4690 else 4691 test_vmx_invalid_controls(); 4692 report_prefix_pop(); 4693 4694 } 4695 4696 /* 4697 * 1. If the "enable EPT" VM-execution control is 1, the "EPTP VM-execution" 4698 * control field must satisfy the following checks: 4699 * 4700 * - The EPT memory type (bits 2:0) must be a value supported by the 4701 * processor as indicated in the IA32_VMX_EPT_VPID_CAP MSR. 4702 * - Bits 5:3 (1 less than the EPT page-walk length) must indicate a 4703 * supported EPT page-walk length. 4704 * - Bit 6 (enable bit for accessed and dirty flags for EPT) must be 4705 * 0 if bit 21 of the IA32_VMX_EPT_VPID_CAP MSR is read as 0, 4706 * indicating that the processor does not support accessed and dirty 4707 * dirty flags for EPT. 4708 * - Reserved bits 11:7 and 63:N (where N is the processor's 4709 * physical-address width) must all be 0. 4710 * 4711 * 2. If the "unrestricted guest" VM-execution control is 1, the 4712 * "enable EPT" VM-execution control must also be 1. 4713 */ 4714 static void test_ept_eptp(void) 4715 { 4716 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4717 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4718 u64 eptp_saved = vmcs_read(EPTP); 4719 u32 primary = primary_saved; 4720 u32 secondary = secondary_saved; 4721 u64 eptp = eptp_saved; 4722 u32 i, maxphysaddr; 4723 u64 j, resv_bits_mask = 0; 4724 4725 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4726 (ctrl_cpu_rev[1].clr & CPU_EPT))) { 4727 printf("\"CPU secondary\" and/or \"enable EPT\" execution controls are not supported !\n"); 4728 return; 4729 } 4730 4731 /* Support for 4-level EPT is mandatory. */ 4732 report(is_4_level_ept_supported(), "4-level EPT support check"); 4733 4734 primary |= CPU_SECONDARY; 4735 vmcs_write(CPU_EXEC_CTRL0, primary); 4736 secondary |= CPU_EPT; 4737 vmcs_write(CPU_EXEC_CTRL1, secondary); 4738 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4739 (3ul << EPTP_PG_WALK_LEN_SHIFT); 4740 vmcs_write(EPTP, eptp); 4741 4742 for (i = 0; i < 8; i++) { 4743 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | i; 4744 vmcs_write(EPTP, eptp); 4745 report_prefix_pushf("Enable-EPT enabled; EPT memory type %lu", 4746 eptp & EPT_MEM_TYPE_MASK); 4747 if (is_ept_memtype_supported(i)) 4748 test_vmx_valid_controls(); 4749 else 4750 test_vmx_invalid_controls(); 4751 report_prefix_pop(); 4752 } 4753 4754 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | 6ul; 4755 4756 /* 4757 * Page walk length (bits 5:3). Note, the value in VMCS.EPTP "is 1 4758 * less than the EPT page-walk length". 4759 */ 4760 for (i = 0; i < 8; i++) { 4761 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4762 (i << EPTP_PG_WALK_LEN_SHIFT); 4763 4764 vmcs_write(EPTP, eptp); 4765 report_prefix_pushf("Enable-EPT enabled; EPT page walk length %lu", 4766 eptp & EPTP_PG_WALK_LEN_MASK); 4767 if (i == 3 || (i == 4 && is_5_level_ept_supported())) 4768 test_vmx_valid_controls(); 4769 else 4770 test_vmx_invalid_controls(); 4771 report_prefix_pop(); 4772 } 4773 4774 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4775 3ul << EPTP_PG_WALK_LEN_SHIFT; 4776 4777 /* 4778 * Accessed and dirty flag (bit 6) 4779 */ 4780 if (ept_ad_bits_supported()) { 4781 report_info("Processor supports accessed and dirty flag"); 4782 eptp &= ~EPTP_AD_FLAG; 4783 test_eptp_ad_bit(eptp, true); 4784 4785 eptp |= EPTP_AD_FLAG; 4786 test_eptp_ad_bit(eptp, true); 4787 } else { 4788 report_info("Processor does not supports accessed and dirty flag"); 4789 eptp &= ~EPTP_AD_FLAG; 4790 test_eptp_ad_bit(eptp, true); 4791 4792 eptp |= EPTP_AD_FLAG; 4793 test_eptp_ad_bit(eptp, false); 4794 } 4795 4796 /* 4797 * Reserved bits [11:7] and [63:N] 4798 */ 4799 for (i = 0; i < 32; i++) { 4800 eptp = (eptp & 4801 ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)) | 4802 (i << EPTP_RESERV_BITS_SHIFT); 4803 vmcs_write(EPTP, eptp); 4804 report_prefix_pushf("Enable-EPT enabled; reserved bits [11:7] %lu", 4805 (eptp >> EPTP_RESERV_BITS_SHIFT) & 4806 EPTP_RESERV_BITS_MASK); 4807 if (i == 0) 4808 test_vmx_valid_controls(); 4809 else 4810 test_vmx_invalid_controls(); 4811 report_prefix_pop(); 4812 } 4813 4814 eptp = (eptp & ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)); 4815 4816 maxphysaddr = cpuid_maxphyaddr(); 4817 for (i = 0; i < (63 - maxphysaddr + 1); i++) { 4818 resv_bits_mask |= 1ul << i; 4819 } 4820 4821 for (j = maxphysaddr - 1; j <= 63; j++) { 4822 eptp = (eptp & ~(resv_bits_mask << maxphysaddr)) | 4823 (j < maxphysaddr ? 0 : 1ul << j); 4824 vmcs_write(EPTP, eptp); 4825 report_prefix_pushf("Enable-EPT enabled; reserved bits [63:N] %lu", 4826 (eptp >> maxphysaddr) & resv_bits_mask); 4827 if (j < maxphysaddr) 4828 test_vmx_valid_controls(); 4829 else 4830 test_vmx_invalid_controls(); 4831 report_prefix_pop(); 4832 } 4833 4834 secondary &= ~(CPU_EPT | CPU_URG); 4835 vmcs_write(CPU_EXEC_CTRL1, secondary); 4836 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest disabled"); 4837 test_vmx_valid_controls(); 4838 report_prefix_pop(); 4839 4840 if (!(ctrl_cpu_rev[1].clr & CPU_URG)) 4841 goto skip_unrestricted_guest; 4842 4843 secondary |= CPU_URG; 4844 vmcs_write(CPU_EXEC_CTRL1, secondary); 4845 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest enabled"); 4846 test_vmx_invalid_controls(); 4847 report_prefix_pop(); 4848 4849 secondary |= CPU_EPT; 4850 setup_dummy_ept(); 4851 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest enabled"); 4852 test_vmx_valid_controls(); 4853 report_prefix_pop(); 4854 4855 skip_unrestricted_guest: 4856 secondary &= ~CPU_URG; 4857 vmcs_write(CPU_EXEC_CTRL1, secondary); 4858 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest disabled"); 4859 test_vmx_valid_controls(); 4860 report_prefix_pop(); 4861 4862 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4863 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4864 vmcs_write(EPTP, eptp_saved); 4865 } 4866 4867 /* 4868 * If the 'enable PML' VM-execution control is 1, the 'enable EPT' 4869 * VM-execution control must also be 1. In addition, the PML address 4870 * must satisfy the following checks: 4871 * 4872 * * Bits 11:0 of the address must be 0. 4873 * * The address should not set any bits beyond the processor's 4874 * physical-address width. 4875 * 4876 * [Intel SDM] 4877 */ 4878 static void test_pml(void) 4879 { 4880 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4881 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4882 u32 primary = primary_saved; 4883 u32 secondary = secondary_saved; 4884 4885 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4886 (ctrl_cpu_rev[1].clr & CPU_EPT) && (ctrl_cpu_rev[1].clr & CPU_PML))) { 4887 printf("\"Secondary execution\" control or \"enable EPT\" control or \"enable PML\" control is not supported !\n"); 4888 return; 4889 } 4890 4891 primary |= CPU_SECONDARY; 4892 vmcs_write(CPU_EXEC_CTRL0, primary); 4893 secondary &= ~(CPU_PML | CPU_EPT); 4894 vmcs_write(CPU_EXEC_CTRL1, secondary); 4895 report_prefix_pushf("enable-PML disabled, enable-EPT disabled"); 4896 test_vmx_valid_controls(); 4897 report_prefix_pop(); 4898 4899 secondary |= CPU_PML; 4900 vmcs_write(CPU_EXEC_CTRL1, secondary); 4901 report_prefix_pushf("enable-PML enabled, enable-EPT disabled"); 4902 test_vmx_invalid_controls(); 4903 report_prefix_pop(); 4904 4905 secondary |= CPU_EPT; 4906 setup_dummy_ept(); 4907 report_prefix_pushf("enable-PML enabled, enable-EPT enabled"); 4908 test_vmx_valid_controls(); 4909 report_prefix_pop(); 4910 4911 secondary &= ~CPU_PML; 4912 vmcs_write(CPU_EXEC_CTRL1, secondary); 4913 report_prefix_pushf("enable-PML disabled, enable EPT enabled"); 4914 test_vmx_valid_controls(); 4915 report_prefix_pop(); 4916 4917 test_vmcs_addr_reference(CPU_PML, PMLADDR, "PML address", "PML", 4918 PAGE_SIZE, false, false); 4919 4920 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4921 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4922 } 4923 4924 /* 4925 * If the "activate VMX-preemption timer" VM-execution control is 0, the 4926 * the "save VMX-preemption timer value" VM-exit control must also be 0. 4927 * 4928 * [Intel SDM] 4929 */ 4930 static void test_vmx_preemption_timer(void) 4931 { 4932 u32 saved_pin = vmcs_read(PIN_CONTROLS); 4933 u32 saved_exit = vmcs_read(EXI_CONTROLS); 4934 u32 pin = saved_pin; 4935 u32 exit = saved_exit; 4936 4937 if (!((ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) || 4938 (ctrl_pin_rev.clr & PIN_PREEMPT))) { 4939 printf("\"Save-VMX-preemption-timer\" control and/or \"Enable-VMX-preemption-timer\" control is not supported\n"); 4940 return; 4941 } 4942 4943 pin |= PIN_PREEMPT; 4944 vmcs_write(PIN_CONTROLS, pin); 4945 exit &= ~EXI_SAVE_PREEMPT; 4946 vmcs_write(EXI_CONTROLS, exit); 4947 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer disabled"); 4948 test_vmx_valid_controls(); 4949 report_prefix_pop(); 4950 4951 exit |= EXI_SAVE_PREEMPT; 4952 vmcs_write(EXI_CONTROLS, exit); 4953 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer enabled"); 4954 test_vmx_valid_controls(); 4955 report_prefix_pop(); 4956 4957 pin &= ~PIN_PREEMPT; 4958 vmcs_write(PIN_CONTROLS, pin); 4959 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer enabled"); 4960 test_vmx_invalid_controls(); 4961 report_prefix_pop(); 4962 4963 exit &= ~EXI_SAVE_PREEMPT; 4964 vmcs_write(EXI_CONTROLS, exit); 4965 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer disabled"); 4966 test_vmx_valid_controls(); 4967 report_prefix_pop(); 4968 4969 vmcs_write(PIN_CONTROLS, saved_pin); 4970 vmcs_write(EXI_CONTROLS, saved_exit); 4971 } 4972 4973 extern unsigned char test_mtf1; 4974 extern unsigned char test_mtf2; 4975 extern unsigned char test_mtf3; 4976 extern unsigned char test_mtf4; 4977 4978 static void test_mtf_guest(void) 4979 { 4980 asm ("vmcall;\n\t" 4981 "out %al, $0x80;\n\t" 4982 "test_mtf1:\n\t" 4983 "vmcall;\n\t" 4984 "out %al, $0x80;\n\t" 4985 "test_mtf2:\n\t" 4986 /* 4987 * Prepare for the 'MOV CR3' test. Attempt to induce a 4988 * general-protection fault by moving a non-canonical address into 4989 * CR3. The 'MOV CR3' instruction does not take an imm64 operand, 4990 * so we must MOV the desired value into a register first. 4991 * 4992 * MOV RAX is done before the VMCALL such that MTF is only enabled 4993 * for the instruction under test. 4994 */ 4995 "mov $0xaaaaaaaaaaaaaaaa, %rax;\n\t" 4996 "vmcall;\n\t" 4997 "mov %rax, %cr3;\n\t" 4998 "test_mtf3:\n\t" 4999 "vmcall;\n\t" 5000 /* 5001 * ICEBP/INT1 instruction. Though the instruction is now 5002 * documented, don't rely on assemblers enumerating the 5003 * instruction. Resort to hand assembly. 5004 */ 5005 ".byte 0xf1;\n\t" 5006 "vmcall;\n\t" 5007 "test_mtf4:\n\t" 5008 "mov $0, %eax;\n\t"); 5009 } 5010 5011 static void test_mtf_gp_handler(struct ex_regs *regs) 5012 { 5013 regs->rip = (unsigned long) &test_mtf3; 5014 } 5015 5016 static void test_mtf_db_handler(struct ex_regs *regs) 5017 { 5018 } 5019 5020 static void enable_mtf(void) 5021 { 5022 u32 ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 5023 5024 vmcs_write(CPU_EXEC_CTRL0, ctrl0 | CPU_MTF); 5025 } 5026 5027 static void disable_mtf(void) 5028 { 5029 u32 ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 5030 5031 vmcs_write(CPU_EXEC_CTRL0, ctrl0 & ~CPU_MTF); 5032 } 5033 5034 static void enable_tf(void) 5035 { 5036 unsigned long rflags = vmcs_read(GUEST_RFLAGS); 5037 5038 vmcs_write(GUEST_RFLAGS, rflags | X86_EFLAGS_TF); 5039 } 5040 5041 static void disable_tf(void) 5042 { 5043 unsigned long rflags = vmcs_read(GUEST_RFLAGS); 5044 5045 vmcs_write(GUEST_RFLAGS, rflags & ~X86_EFLAGS_TF); 5046 } 5047 5048 static void report_mtf(const char *insn_name, unsigned long exp_rip) 5049 { 5050 unsigned long rip = vmcs_read(GUEST_RIP); 5051 5052 assert_exit_reason(VMX_MTF); 5053 report(rip == exp_rip, "MTF VM-exit after %s. RIP: 0x%lx (expected 0x%lx)", 5054 insn_name, rip, exp_rip); 5055 } 5056 5057 static void vmx_mtf_test(void) 5058 { 5059 unsigned long pending_dbg; 5060 handler old_gp, old_db; 5061 5062 if (!(ctrl_cpu_rev[0].clr & CPU_MTF)) { 5063 printf("CPU does not support the 'monitor trap flag' processor-based VM-execution control.\n"); 5064 return; 5065 } 5066 5067 test_set_guest(test_mtf_guest); 5068 5069 /* Expect an MTF VM-exit after OUT instruction */ 5070 enter_guest(); 5071 skip_exit_vmcall(); 5072 5073 enable_mtf(); 5074 enter_guest(); 5075 report_mtf("OUT", (unsigned long) &test_mtf1); 5076 disable_mtf(); 5077 5078 /* 5079 * Concurrent #DB trap and MTF on instruction boundary. Expect MTF 5080 * VM-exit with populated 'pending debug exceptions' VMCS field. 5081 */ 5082 enter_guest(); 5083 skip_exit_vmcall(); 5084 5085 enable_mtf(); 5086 enable_tf(); 5087 5088 enter_guest(); 5089 report_mtf("OUT", (unsigned long) &test_mtf2); 5090 pending_dbg = vmcs_read(GUEST_PENDING_DEBUG); 5091 report(pending_dbg & DR6_BS, 5092 "'pending debug exceptions' field after MTF VM-exit: 0x%lx (expected 0x%lx)", 5093 pending_dbg, (unsigned long) DR6_BS); 5094 5095 disable_mtf(); 5096 disable_tf(); 5097 vmcs_write(GUEST_PENDING_DEBUG, 0); 5098 5099 /* 5100 * #GP exception takes priority over MTF. Expect MTF VM-exit with RIP 5101 * advanced to first instruction of #GP handler. 5102 */ 5103 enter_guest(); 5104 skip_exit_vmcall(); 5105 5106 old_gp = handle_exception(GP_VECTOR, test_mtf_gp_handler); 5107 5108 enable_mtf(); 5109 enter_guest(); 5110 report_mtf("MOV CR3", (unsigned long) get_idt_addr(&boot_idt[GP_VECTOR])); 5111 disable_mtf(); 5112 5113 /* 5114 * Concurrent MTF and privileged software exception (i.e. ICEBP/INT1). 5115 * MTF should follow the delivery of #DB trap, though the SDM doesn't 5116 * provide clear indication of the relative priority. 5117 */ 5118 enter_guest(); 5119 skip_exit_vmcall(); 5120 5121 handle_exception(GP_VECTOR, old_gp); 5122 old_db = handle_exception(DB_VECTOR, test_mtf_db_handler); 5123 5124 enable_mtf(); 5125 enter_guest(); 5126 report_mtf("INT1", (unsigned long) get_idt_addr(&boot_idt[DB_VECTOR])); 5127 disable_mtf(); 5128 5129 enter_guest(); 5130 skip_exit_vmcall(); 5131 handle_exception(DB_VECTOR, old_db); 5132 vmcs_write(ENT_INTR_INFO, INTR_INFO_VALID_MASK | INTR_TYPE_OTHER_EVENT); 5133 enter_guest(); 5134 report_mtf("injected MTF", (unsigned long) &test_mtf4); 5135 enter_guest(); 5136 } 5137 5138 extern char vmx_mtf_pdpte_guest_begin; 5139 extern char vmx_mtf_pdpte_guest_end; 5140 5141 asm("vmx_mtf_pdpte_guest_begin:\n\t" 5142 "mov %cr0, %rax\n\t" /* save CR0 with PG=1 */ 5143 "vmcall\n\t" /* on return from this CR0.PG=0 */ 5144 "mov %rax, %cr0\n\t" /* restore CR0.PG=1 to enter PAE mode */ 5145 "vmcall\n\t" 5146 "retq\n\t" 5147 "vmx_mtf_pdpte_guest_end:"); 5148 5149 static void vmx_mtf_pdpte_test(void) 5150 { 5151 void *test_mtf_pdpte_guest; 5152 pteval_t *pdpt; 5153 u32 guest_ar_cs; 5154 u64 guest_efer; 5155 pteval_t *pte; 5156 u64 guest_cr0; 5157 u64 guest_cr3; 5158 u64 guest_cr4; 5159 u64 ent_ctls; 5160 int i; 5161 5162 if (setup_ept(false)) 5163 return; 5164 5165 if (!(ctrl_cpu_rev[0].clr & CPU_MTF)) { 5166 printf("CPU does not support 'monitor trap flag.'\n"); 5167 return; 5168 } 5169 5170 if (!(ctrl_cpu_rev[1].clr & CPU_URG)) { 5171 printf("CPU does not support 'unrestricted guest.'\n"); 5172 return; 5173 } 5174 5175 vmcs_write(EXC_BITMAP, ~0); 5176 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | CPU_URG); 5177 5178 /* 5179 * Copy the guest code to an identity-mapped page. 5180 */ 5181 test_mtf_pdpte_guest = alloc_page(); 5182 memcpy(test_mtf_pdpte_guest, &vmx_mtf_pdpte_guest_begin, 5183 &vmx_mtf_pdpte_guest_end - &vmx_mtf_pdpte_guest_begin); 5184 5185 test_set_guest(test_mtf_pdpte_guest); 5186 5187 enter_guest(); 5188 skip_exit_vmcall(); 5189 5190 /* 5191 * Put the guest in non-paged 32-bit protected mode, ready to enter 5192 * PAE mode when CR0.PG is set. CR4.PAE will already have been set 5193 * when the guest started out in long mode. 5194 */ 5195 ent_ctls = vmcs_read(ENT_CONTROLS); 5196 vmcs_write(ENT_CONTROLS, ent_ctls & ~ENT_GUEST_64); 5197 5198 guest_efer = vmcs_read(GUEST_EFER); 5199 vmcs_write(GUEST_EFER, guest_efer & ~(EFER_LMA | EFER_LME)); 5200 5201 /* 5202 * Set CS access rights bits for 32-bit protected mode: 5203 * 3:0 B execute/read/accessed 5204 * 4 1 code or data 5205 * 6:5 0 descriptor privilege level 5206 * 7 1 present 5207 * 11:8 0 reserved 5208 * 12 0 available for use by system software 5209 * 13 0 64 bit mode not active 5210 * 14 1 default operation size 32-bit segment 5211 * 15 1 page granularity: segment limit in 4K units 5212 * 16 0 segment usable 5213 * 31:17 0 reserved 5214 */ 5215 guest_ar_cs = vmcs_read(GUEST_AR_CS); 5216 vmcs_write(GUEST_AR_CS, 0xc09b); 5217 5218 guest_cr0 = vmcs_read(GUEST_CR0); 5219 vmcs_write(GUEST_CR0, guest_cr0 & ~X86_CR0_PG); 5220 5221 guest_cr4 = vmcs_read(GUEST_CR4); 5222 vmcs_write(GUEST_CR4, guest_cr4 & ~X86_CR4_PCIDE); 5223 5224 guest_cr3 = vmcs_read(GUEST_CR3); 5225 5226 /* 5227 * Turn the 4-level page table into a PAE page table by following the 0th 5228 * PML4 entry to a PDPT page, and grab the first four PDPTEs from that 5229 * page. 5230 * 5231 * Why does this work? 5232 * 5233 * PAE uses 32-bit addressing which implies: 5234 * Bits 11:0 page offset 5235 * Bits 20:12 entry into 512-entry page table 5236 * Bits 29:21 entry into a 512-entry directory table 5237 * Bits 31:30 entry into the page directory pointer table. 5238 * Bits 63:32 zero 5239 * 5240 * As only 2 bits are needed to select the PDPTEs for the entire 5241 * 32-bit address space, take the first 4 PDPTEs in the level 3 page 5242 * directory pointer table. It doesn't matter which of these PDPTEs 5243 * are present because they must cover the guest code given that it 5244 * has already run successfully. 5245 * 5246 * Get a pointer to PTE for GVA=0 in the page directory pointer table 5247 */ 5248 pte = get_pte_level( 5249 (pgd_t *)phys_to_virt(guest_cr3 & ~X86_CR3_PCID_MASK), 0, 5250 PDPT_LEVEL); 5251 5252 /* 5253 * Need some memory for the 4-entry PAE page directory pointer 5254 * table. Use the end of the identity-mapped page where the guest code 5255 * is stored. There is definitely space as the guest code is only a 5256 * few bytes. 5257 */ 5258 pdpt = test_mtf_pdpte_guest + PAGE_SIZE - 4 * sizeof(pteval_t); 5259 5260 /* 5261 * Copy the first four PDPTEs into the PAE page table with reserved 5262 * bits cleared. Note that permission bits from the PML4E and PDPTE 5263 * are not propagated. 5264 */ 5265 for (i = 0; i < 4; i++) { 5266 TEST_ASSERT_EQ_MSG(0, (pte[i] & PDPTE64_RSVD_MASK), 5267 "PDPTE has invalid reserved bits"); 5268 TEST_ASSERT_EQ_MSG(0, (pte[i] & PDPTE64_PAGE_SIZE_MASK), 5269 "Cannot use 1GB super pages for PAE"); 5270 pdpt[i] = pte[i] & ~(PAE_PDPTE_RSVD_MASK); 5271 } 5272 vmcs_write(GUEST_CR3, virt_to_phys(pdpt)); 5273 5274 enable_mtf(); 5275 enter_guest(); 5276 assert_exit_reason(VMX_MTF); 5277 disable_mtf(); 5278 5279 /* 5280 * The four PDPTEs should have been loaded into the VMCS when 5281 * the guest set CR0.PG to enter PAE mode. 5282 */ 5283 for (i = 0; i < 4; i++) { 5284 u64 pdpte = vmcs_read(GUEST_PDPTE + 2 * i); 5285 5286 report(pdpte == pdpt[i], "PDPTE%d is 0x%lx (expected 0x%lx)", 5287 i, pdpte, pdpt[i]); 5288 } 5289 5290 /* 5291 * Now, try to enter the guest in PAE mode. If the PDPTEs in the 5292 * vmcs are wrong, this will fail. 5293 */ 5294 enter_guest(); 5295 skip_exit_vmcall(); 5296 5297 /* 5298 * Return guest to 64-bit mode and wrap up. 5299 */ 5300 vmcs_write(ENT_CONTROLS, ent_ctls); 5301 vmcs_write(GUEST_EFER, guest_efer); 5302 vmcs_write(GUEST_AR_CS, guest_ar_cs); 5303 vmcs_write(GUEST_CR0, guest_cr0); 5304 vmcs_write(GUEST_CR4, guest_cr4); 5305 vmcs_write(GUEST_CR3, guest_cr3); 5306 5307 enter_guest(); 5308 } 5309 5310 /* 5311 * Tests for VM-execution control fields 5312 */ 5313 static void test_vm_execution_ctls(void) 5314 { 5315 test_pin_based_ctls(); 5316 test_primary_processor_based_ctls(); 5317 test_secondary_processor_based_ctls(); 5318 test_cr3_targets(); 5319 test_io_bitmaps(); 5320 test_msr_bitmap(); 5321 test_apic_ctls(); 5322 test_tpr_threshold(); 5323 test_nmi_ctrls(); 5324 test_pml(); 5325 test_vpid(); 5326 test_ept_eptp(); 5327 test_vmx_preemption_timer(); 5328 } 5329 5330 /* 5331 * The following checks are performed for the VM-entry MSR-load address if 5332 * the VM-entry MSR-load count field is non-zero: 5333 * 5334 * - The lower 4 bits of the VM-entry MSR-load address must be 0. 5335 * The address should not set any bits beyond the processor's 5336 * physical-address width. 5337 * 5338 * - The address of the last byte in the VM-entry MSR-load area 5339 * should not set any bits beyond the processor's physical-address 5340 * width. The address of this last byte is VM-entry MSR-load address 5341 * + (MSR count * 16) - 1. (The arithmetic used for the computation 5342 * uses more bits than the processor's physical-address width.) 5343 * 5344 * 5345 * [Intel SDM] 5346 */ 5347 static void test_entry_msr_load(void) 5348 { 5349 entry_msr_load = alloc_page(); 5350 u64 tmp; 5351 u32 entry_msr_ld_cnt = 1; 5352 int i; 5353 u32 addr_len = 64; 5354 5355 vmcs_write(ENT_MSR_LD_CNT, entry_msr_ld_cnt); 5356 5357 /* Check first 4 bits of VM-entry MSR-load address */ 5358 for (i = 0; i < 4; i++) { 5359 tmp = (u64)entry_msr_load | 1ull << i; 5360 vmcs_write(ENTER_MSR_LD_ADDR, tmp); 5361 report_prefix_pushf("VM-entry MSR-load addr [4:0] %lx", 5362 tmp & 0xf); 5363 test_vmx_invalid_controls(); 5364 report_prefix_pop(); 5365 } 5366 5367 if (basic.val & (1ul << 48)) 5368 addr_len = 32; 5369 5370 test_vmcs_addr_values("VM-entry-MSR-load address", 5371 ENTER_MSR_LD_ADDR, 16, false, false, 5372 4, addr_len - 1); 5373 5374 /* 5375 * Check last byte of VM-entry MSR-load address 5376 */ 5377 entry_msr_load = (struct vmx_msr_entry *)((u64)entry_msr_load & ~0xf); 5378 5379 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 5380 i < 64; i++) { 5381 tmp = ((u64)entry_msr_load + entry_msr_ld_cnt * 16 - 1) | 5382 1ul << i; 5383 vmcs_write(ENTER_MSR_LD_ADDR, 5384 tmp - (entry_msr_ld_cnt * 16 - 1)); 5385 test_vmx_invalid_controls(); 5386 } 5387 5388 vmcs_write(ENT_MSR_LD_CNT, 2); 5389 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 5390 test_vmx_invalid_controls(); 5391 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 5392 test_vmx_valid_controls(); 5393 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 5394 test_vmx_valid_controls(); 5395 } 5396 5397 static struct vmx_state_area_test_data { 5398 u32 msr; 5399 u64 exp; 5400 bool enabled; 5401 } vmx_state_area_test_data; 5402 5403 static void guest_state_test_main(void) 5404 { 5405 u64 obs; 5406 struct vmx_state_area_test_data *data = &vmx_state_area_test_data; 5407 5408 while (1) { 5409 if (vmx_get_test_stage() == 2) 5410 break; 5411 5412 if (data->enabled) { 5413 obs = rdmsr(data->msr); 5414 report(data->exp == obs, 5415 "Guest state is 0x%lx (expected 0x%lx)", 5416 obs, data->exp); 5417 } 5418 5419 vmcall(); 5420 } 5421 5422 asm volatile("fnop"); 5423 } 5424 5425 static void test_guest_state(const char *test, bool xfail, u64 field, 5426 const char * field_name) 5427 { 5428 struct vmentry_result result; 5429 u8 abort_flags; 5430 5431 abort_flags = ABORT_ON_EARLY_VMENTRY_FAIL; 5432 if (!xfail) 5433 abort_flags = ABORT_ON_INVALID_GUEST_STATE; 5434 5435 __enter_guest(abort_flags, &result); 5436 5437 report(result.exit_reason.failed_vmentry == xfail && 5438 ((xfail && result.exit_reason.basic == VMX_FAIL_STATE) || 5439 (!xfail && result.exit_reason.basic == VMX_VMCALL)) && 5440 (!xfail || vmcs_read(EXI_QUALIFICATION) == ENTRY_FAIL_DEFAULT), 5441 "%s, %s = %lx", test, field_name, field); 5442 5443 if (!result.exit_reason.failed_vmentry) 5444 skip_exit_insn(); 5445 } 5446 5447 /* 5448 * Tests for VM-entry control fields 5449 */ 5450 static void test_vm_entry_ctls(void) 5451 { 5452 test_invalid_event_injection(); 5453 test_entry_msr_load(); 5454 } 5455 5456 /* 5457 * The following checks are performed for the VM-exit MSR-store address if 5458 * the VM-exit MSR-store count field is non-zero: 5459 * 5460 * - The lower 4 bits of the VM-exit MSR-store address must be 0. 5461 * The address should not set any bits beyond the processor's 5462 * physical-address width. 5463 * 5464 * - The address of the last byte in the VM-exit MSR-store area 5465 * should not set any bits beyond the processor's physical-address 5466 * width. The address of this last byte is VM-exit MSR-store address 5467 * + (MSR count * 16) - 1. (The arithmetic used for the computation 5468 * uses more bits than the processor's physical-address width.) 5469 * 5470 * If IA32_VMX_BASIC[48] is read as 1, neither address should set any bits 5471 * in the range 63:32. 5472 * 5473 * [Intel SDM] 5474 */ 5475 static void test_exit_msr_store(void) 5476 { 5477 exit_msr_store = alloc_page(); 5478 u64 tmp; 5479 u32 exit_msr_st_cnt = 1; 5480 int i; 5481 u32 addr_len = 64; 5482 5483 vmcs_write(EXI_MSR_ST_CNT, exit_msr_st_cnt); 5484 5485 /* Check first 4 bits of VM-exit MSR-store address */ 5486 for (i = 0; i < 4; i++) { 5487 tmp = (u64)exit_msr_store | 1ull << i; 5488 vmcs_write(EXIT_MSR_ST_ADDR, tmp); 5489 report_prefix_pushf("VM-exit MSR-store addr [4:0] %lx", 5490 tmp & 0xf); 5491 test_vmx_invalid_controls(); 5492 report_prefix_pop(); 5493 } 5494 5495 if (basic.val & (1ul << 48)) 5496 addr_len = 32; 5497 5498 test_vmcs_addr_values("VM-exit-MSR-store address", 5499 EXIT_MSR_ST_ADDR, 16, false, false, 5500 4, addr_len - 1); 5501 5502 /* 5503 * Check last byte of VM-exit MSR-store address 5504 */ 5505 exit_msr_store = (struct vmx_msr_entry *)((u64)exit_msr_store & ~0xf); 5506 5507 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 5508 i < 64; i++) { 5509 tmp = ((u64)exit_msr_store + exit_msr_st_cnt * 16 - 1) | 5510 1ul << i; 5511 vmcs_write(EXIT_MSR_ST_ADDR, 5512 tmp - (exit_msr_st_cnt * 16 - 1)); 5513 test_vmx_invalid_controls(); 5514 } 5515 5516 vmcs_write(EXI_MSR_ST_CNT, 2); 5517 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 5518 test_vmx_invalid_controls(); 5519 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 5520 test_vmx_valid_controls(); 5521 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 5522 test_vmx_valid_controls(); 5523 } 5524 5525 /* 5526 * Tests for VM-exit controls 5527 */ 5528 static void test_vm_exit_ctls(void) 5529 { 5530 test_exit_msr_store(); 5531 } 5532 5533 /* 5534 * Check that the virtual CPU checks all of the VMX controls as 5535 * documented in the Intel SDM. 5536 */ 5537 static void vmx_controls_test(void) 5538 { 5539 /* 5540 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 5541 * fail due to invalid guest state, should we make it that 5542 * far. 5543 */ 5544 vmcs_write(GUEST_RFLAGS, 0); 5545 5546 test_vm_execution_ctls(); 5547 test_vm_exit_ctls(); 5548 test_vm_entry_ctls(); 5549 } 5550 5551 struct apic_reg_virt_config { 5552 bool apic_register_virtualization; 5553 bool use_tpr_shadow; 5554 bool virtualize_apic_accesses; 5555 bool virtualize_x2apic_mode; 5556 bool activate_secondary_controls; 5557 }; 5558 5559 struct apic_reg_test { 5560 const char *name; 5561 struct apic_reg_virt_config apic_reg_virt_config; 5562 }; 5563 5564 struct apic_reg_virt_expectation { 5565 enum Reason rd_exit_reason; 5566 enum Reason wr_exit_reason; 5567 u32 val; 5568 u32 (*virt_fn)(u32); 5569 5570 /* 5571 * If false, accessing the APIC access address from L2 is treated as a 5572 * normal memory operation, rather than triggering virtualization. 5573 */ 5574 bool virtualize_apic_accesses; 5575 }; 5576 5577 static u32 apic_virt_identity(u32 val) 5578 { 5579 return val; 5580 } 5581 5582 static u32 apic_virt_nibble1(u32 val) 5583 { 5584 return val & 0xf0; 5585 } 5586 5587 static u32 apic_virt_byte3(u32 val) 5588 { 5589 return val & (0xff << 24); 5590 } 5591 5592 static bool apic_reg_virt_exit_expectation( 5593 u32 reg, struct apic_reg_virt_config *config, 5594 struct apic_reg_virt_expectation *expectation) 5595 { 5596 /* Good configs, where some L2 APIC accesses are virtualized. */ 5597 bool virtualize_apic_accesses_only = 5598 config->virtualize_apic_accesses && 5599 !config->use_tpr_shadow && 5600 !config->apic_register_virtualization && 5601 !config->virtualize_x2apic_mode && 5602 config->activate_secondary_controls; 5603 bool virtualize_apic_accesses_and_use_tpr_shadow = 5604 config->virtualize_apic_accesses && 5605 config->use_tpr_shadow && 5606 !config->apic_register_virtualization && 5607 !config->virtualize_x2apic_mode && 5608 config->activate_secondary_controls; 5609 bool apic_register_virtualization = 5610 config->virtualize_apic_accesses && 5611 config->use_tpr_shadow && 5612 config->apic_register_virtualization && 5613 !config->virtualize_x2apic_mode && 5614 config->activate_secondary_controls; 5615 5616 expectation->val = MAGIC_VAL_1; 5617 expectation->virt_fn = apic_virt_identity; 5618 expectation->virtualize_apic_accesses = 5619 config->virtualize_apic_accesses && 5620 config->activate_secondary_controls; 5621 if (virtualize_apic_accesses_only) { 5622 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5623 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5624 } else if (virtualize_apic_accesses_and_use_tpr_shadow) { 5625 switch (reg) { 5626 case APIC_TASKPRI: 5627 expectation->rd_exit_reason = VMX_VMCALL; 5628 expectation->wr_exit_reason = VMX_VMCALL; 5629 expectation->virt_fn = apic_virt_nibble1; 5630 break; 5631 default: 5632 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5633 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5634 } 5635 } else if (apic_register_virtualization) { 5636 expectation->rd_exit_reason = VMX_VMCALL; 5637 5638 switch (reg) { 5639 case APIC_ID: 5640 case APIC_EOI: 5641 case APIC_LDR: 5642 case APIC_DFR: 5643 case APIC_SPIV: 5644 case APIC_ESR: 5645 case APIC_ICR: 5646 case APIC_LVTT: 5647 case APIC_LVTTHMR: 5648 case APIC_LVTPC: 5649 case APIC_LVT0: 5650 case APIC_LVT1: 5651 case APIC_LVTERR: 5652 case APIC_TMICT: 5653 case APIC_TDCR: 5654 expectation->wr_exit_reason = VMX_APIC_WRITE; 5655 break; 5656 case APIC_LVR: 5657 case APIC_ISR ... APIC_ISR + 0x70: 5658 case APIC_TMR ... APIC_TMR + 0x70: 5659 case APIC_IRR ... APIC_IRR + 0x70: 5660 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5661 break; 5662 case APIC_TASKPRI: 5663 expectation->wr_exit_reason = VMX_VMCALL; 5664 expectation->virt_fn = apic_virt_nibble1; 5665 break; 5666 case APIC_ICR2: 5667 expectation->wr_exit_reason = VMX_VMCALL; 5668 expectation->virt_fn = apic_virt_byte3; 5669 break; 5670 default: 5671 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5672 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5673 } 5674 } else if (!expectation->virtualize_apic_accesses) { 5675 /* 5676 * No APIC registers are directly virtualized. This includes 5677 * VTPR, which can be virtualized through MOV to/from CR8 via 5678 * the use TPR shadow control, but not through directly 5679 * accessing VTPR. 5680 */ 5681 expectation->rd_exit_reason = VMX_VMCALL; 5682 expectation->wr_exit_reason = VMX_VMCALL; 5683 } else { 5684 printf("Cannot parse APIC register virtualization config:\n" 5685 "\tvirtualize_apic_accesses: %d\n" 5686 "\tuse_tpr_shadow: %d\n" 5687 "\tapic_register_virtualization: %d\n" 5688 "\tvirtualize_x2apic_mode: %d\n" 5689 "\tactivate_secondary_controls: %d\n", 5690 config->virtualize_apic_accesses, 5691 config->use_tpr_shadow, 5692 config->apic_register_virtualization, 5693 config->virtualize_x2apic_mode, 5694 config->activate_secondary_controls); 5695 5696 return false; 5697 } 5698 5699 return true; 5700 } 5701 5702 struct apic_reg_test apic_reg_tests[] = { 5703 /* Good configs, where some L2 APIC accesses are virtualized. */ 5704 { 5705 .name = "Virtualize APIC accesses", 5706 .apic_reg_virt_config = { 5707 .virtualize_apic_accesses = true, 5708 .use_tpr_shadow = false, 5709 .apic_register_virtualization = false, 5710 .virtualize_x2apic_mode = false, 5711 .activate_secondary_controls = true, 5712 }, 5713 }, 5714 { 5715 .name = "Virtualize APIC accesses + Use TPR shadow", 5716 .apic_reg_virt_config = { 5717 .virtualize_apic_accesses = true, 5718 .use_tpr_shadow = true, 5719 .apic_register_virtualization = false, 5720 .virtualize_x2apic_mode = false, 5721 .activate_secondary_controls = true, 5722 }, 5723 }, 5724 { 5725 .name = "APIC-register virtualization", 5726 .apic_reg_virt_config = { 5727 .virtualize_apic_accesses = true, 5728 .use_tpr_shadow = true, 5729 .apic_register_virtualization = true, 5730 .virtualize_x2apic_mode = false, 5731 .activate_secondary_controls = true, 5732 }, 5733 }, 5734 5735 /* 5736 * Test that the secondary processor-based VM-execution controls are 5737 * correctly ignored when "activate secondary controls" is disabled. 5738 */ 5739 { 5740 .name = "Activate secondary controls off", 5741 .apic_reg_virt_config = { 5742 .virtualize_apic_accesses = true, 5743 .use_tpr_shadow = false, 5744 .apic_register_virtualization = true, 5745 .virtualize_x2apic_mode = true, 5746 .activate_secondary_controls = false, 5747 }, 5748 }, 5749 { 5750 .name = "Activate secondary controls off + Use TPR shadow", 5751 .apic_reg_virt_config = { 5752 .virtualize_apic_accesses = true, 5753 .use_tpr_shadow = true, 5754 .apic_register_virtualization = true, 5755 .virtualize_x2apic_mode = true, 5756 .activate_secondary_controls = false, 5757 }, 5758 }, 5759 5760 /* 5761 * Test that the APIC access address is treated like an arbitrary memory 5762 * address when "virtualize APIC accesses" is disabled. 5763 */ 5764 { 5765 .name = "Virtualize APIC accesses off + Use TPR shadow", 5766 .apic_reg_virt_config = { 5767 .virtualize_apic_accesses = false, 5768 .use_tpr_shadow = true, 5769 .apic_register_virtualization = true, 5770 .virtualize_x2apic_mode = true, 5771 .activate_secondary_controls = true, 5772 }, 5773 }, 5774 5775 /* 5776 * Test that VM entry fails due to invalid controls when 5777 * "APIC-register virtualization" is enabled while "use TPR shadow" is 5778 * disabled. 5779 */ 5780 { 5781 .name = "APIC-register virtualization + Use TPR shadow off", 5782 .apic_reg_virt_config = { 5783 .virtualize_apic_accesses = true, 5784 .use_tpr_shadow = false, 5785 .apic_register_virtualization = true, 5786 .virtualize_x2apic_mode = false, 5787 .activate_secondary_controls = true, 5788 }, 5789 }, 5790 5791 /* 5792 * Test that VM entry fails due to invalid controls when 5793 * "Virtualize x2APIC mode" is enabled while "use TPR shadow" is 5794 * disabled. 5795 */ 5796 { 5797 .name = "Virtualize x2APIC mode + Use TPR shadow off", 5798 .apic_reg_virt_config = { 5799 .virtualize_apic_accesses = false, 5800 .use_tpr_shadow = false, 5801 .apic_register_virtualization = false, 5802 .virtualize_x2apic_mode = true, 5803 .activate_secondary_controls = true, 5804 }, 5805 }, 5806 { 5807 .name = "Virtualize x2APIC mode + Use TPR shadow off v2", 5808 .apic_reg_virt_config = { 5809 .virtualize_apic_accesses = false, 5810 .use_tpr_shadow = false, 5811 .apic_register_virtualization = true, 5812 .virtualize_x2apic_mode = true, 5813 .activate_secondary_controls = true, 5814 }, 5815 }, 5816 5817 /* 5818 * Test that VM entry fails due to invalid controls when 5819 * "virtualize x2APIC mode" is enabled while "virtualize APIC accesses" 5820 * is enabled. 5821 */ 5822 { 5823 .name = "Virtualize x2APIC mode + Virtualize APIC accesses", 5824 .apic_reg_virt_config = { 5825 .virtualize_apic_accesses = true, 5826 .use_tpr_shadow = true, 5827 .apic_register_virtualization = false, 5828 .virtualize_x2apic_mode = true, 5829 .activate_secondary_controls = true, 5830 }, 5831 }, 5832 { 5833 .name = "Virtualize x2APIC mode + Virtualize APIC accesses v2", 5834 .apic_reg_virt_config = { 5835 .virtualize_apic_accesses = true, 5836 .use_tpr_shadow = true, 5837 .apic_register_virtualization = true, 5838 .virtualize_x2apic_mode = true, 5839 .activate_secondary_controls = true, 5840 }, 5841 }, 5842 }; 5843 5844 enum Apic_op { 5845 APIC_OP_XAPIC_RD, 5846 APIC_OP_XAPIC_WR, 5847 TERMINATE, 5848 }; 5849 5850 static u32 vmx_xapic_read(u32 *apic_access_address, u32 reg) 5851 { 5852 return *(volatile u32 *)((uintptr_t)apic_access_address + reg); 5853 } 5854 5855 static void vmx_xapic_write(u32 *apic_access_address, u32 reg, u32 val) 5856 { 5857 *(volatile u32 *)((uintptr_t)apic_access_address + reg) = val; 5858 } 5859 5860 struct apic_reg_virt_guest_args { 5861 enum Apic_op op; 5862 u32 *apic_access_address; 5863 u32 reg; 5864 u32 val; 5865 bool check_rd; 5866 u32 (*virt_fn)(u32); 5867 } apic_reg_virt_guest_args; 5868 5869 static void apic_reg_virt_guest(void) 5870 { 5871 volatile struct apic_reg_virt_guest_args *args = 5872 &apic_reg_virt_guest_args; 5873 5874 for (;;) { 5875 enum Apic_op op = args->op; 5876 u32 *apic_access_address = args->apic_access_address; 5877 u32 reg = args->reg; 5878 u32 val = args->val; 5879 bool check_rd = args->check_rd; 5880 u32 (*virt_fn)(u32) = args->virt_fn; 5881 5882 if (op == TERMINATE) 5883 break; 5884 5885 if (op == APIC_OP_XAPIC_RD) { 5886 u32 ret = vmx_xapic_read(apic_access_address, reg); 5887 5888 if (check_rd) { 5889 u32 want = virt_fn(val); 5890 u32 got = virt_fn(ret); 5891 5892 report(got == want, 5893 "read 0x%x, expected 0x%x.", got, want); 5894 } 5895 } else if (op == APIC_OP_XAPIC_WR) { 5896 vmx_xapic_write(apic_access_address, reg, val); 5897 } 5898 5899 /* 5900 * The L1 should always execute a vmcall after it's done testing 5901 * an individual APIC operation. This helps to validate that the 5902 * L1 and L2 are in sync with each other, as expected. 5903 */ 5904 vmcall(); 5905 } 5906 } 5907 5908 static void test_xapic_rd( 5909 u32 reg, struct apic_reg_virt_expectation *expectation, 5910 u32 *apic_access_address, u32 *virtual_apic_page) 5911 { 5912 u32 val = expectation->val; 5913 u32 exit_reason_want = expectation->rd_exit_reason; 5914 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 5915 5916 report_prefix_pushf("xapic - reading 0x%03x", reg); 5917 5918 /* Configure guest to do an xapic read */ 5919 args->op = APIC_OP_XAPIC_RD; 5920 args->apic_access_address = apic_access_address; 5921 args->reg = reg; 5922 args->val = val; 5923 args->check_rd = exit_reason_want == VMX_VMCALL; 5924 args->virt_fn = expectation->virt_fn; 5925 5926 /* Setup virtual APIC page */ 5927 if (!expectation->virtualize_apic_accesses) { 5928 apic_access_address[apic_reg_index(reg)] = val; 5929 virtual_apic_page[apic_reg_index(reg)] = 0; 5930 } else if (exit_reason_want == VMX_VMCALL) { 5931 apic_access_address[apic_reg_index(reg)] = 0; 5932 virtual_apic_page[apic_reg_index(reg)] = val; 5933 } 5934 5935 /* Enter guest */ 5936 enter_guest(); 5937 5938 /* 5939 * Validate the behavior and 5940 * pass a magic value back to the guest. 5941 */ 5942 if (exit_reason_want == VMX_APIC_ACCESS) { 5943 u32 apic_page_offset = vmcs_read(EXI_QUALIFICATION) & 0xfff; 5944 5945 assert_exit_reason(exit_reason_want); 5946 report(apic_page_offset == reg, 5947 "got APIC access exit @ page offset 0x%03x, want 0x%03x", 5948 apic_page_offset, reg); 5949 skip_exit_insn(); 5950 5951 /* Reenter guest so it can consume/check rcx and exit again. */ 5952 enter_guest(); 5953 } else if (exit_reason_want != VMX_VMCALL) { 5954 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 5955 } 5956 5957 skip_exit_vmcall(); 5958 report_prefix_pop(); 5959 } 5960 5961 static void test_xapic_wr( 5962 u32 reg, struct apic_reg_virt_expectation *expectation, 5963 u32 *apic_access_address, u32 *virtual_apic_page) 5964 { 5965 u32 val = expectation->val; 5966 u32 exit_reason_want = expectation->wr_exit_reason; 5967 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 5968 bool virtualized = 5969 expectation->virtualize_apic_accesses && 5970 (exit_reason_want == VMX_APIC_WRITE || 5971 exit_reason_want == VMX_VMCALL); 5972 bool checked = false; 5973 5974 report_prefix_pushf("xapic - writing 0x%x to 0x%03x", val, reg); 5975 5976 /* Configure guest to do an xapic read */ 5977 args->op = APIC_OP_XAPIC_WR; 5978 args->apic_access_address = apic_access_address; 5979 args->reg = reg; 5980 args->val = val; 5981 5982 /* Setup virtual APIC page */ 5983 if (virtualized || !expectation->virtualize_apic_accesses) { 5984 apic_access_address[apic_reg_index(reg)] = 0; 5985 virtual_apic_page[apic_reg_index(reg)] = 0; 5986 } 5987 5988 /* Enter guest */ 5989 enter_guest(); 5990 5991 /* 5992 * Validate the behavior and 5993 * pass a magic value back to the guest. 5994 */ 5995 if (exit_reason_want == VMX_APIC_ACCESS) { 5996 u32 apic_page_offset = vmcs_read(EXI_QUALIFICATION) & 0xfff; 5997 5998 assert_exit_reason(exit_reason_want); 5999 report(apic_page_offset == reg, 6000 "got APIC access exit @ page offset 0x%03x, want 0x%03x", 6001 apic_page_offset, reg); 6002 skip_exit_insn(); 6003 6004 /* Reenter guest so it can consume/check rcx and exit again. */ 6005 enter_guest(); 6006 } else if (exit_reason_want == VMX_APIC_WRITE) { 6007 assert_exit_reason(exit_reason_want); 6008 report(virtual_apic_page[apic_reg_index(reg)] == val, 6009 "got APIC write exit @ page offset 0x%03x; val is 0x%x, want 0x%x", 6010 apic_reg_index(reg), 6011 virtual_apic_page[apic_reg_index(reg)], val); 6012 checked = true; 6013 6014 /* Reenter guest so it can consume/check rcx and exit again. */ 6015 enter_guest(); 6016 } else if (exit_reason_want != VMX_VMCALL) { 6017 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 6018 } 6019 6020 assert_exit_reason(VMX_VMCALL); 6021 if (virtualized && !checked) { 6022 u32 want = expectation->virt_fn(val); 6023 u32 got = virtual_apic_page[apic_reg_index(reg)]; 6024 got = expectation->virt_fn(got); 6025 6026 report(got == want, "exitless write; val is 0x%x, want 0x%x", 6027 got, want); 6028 } else if (!expectation->virtualize_apic_accesses && !checked) { 6029 u32 got = apic_access_address[apic_reg_index(reg)]; 6030 6031 report(got == val, 6032 "non-virtualized write; val is 0x%x, want 0x%x", got, 6033 val); 6034 } else if (!expectation->virtualize_apic_accesses && checked) { 6035 report_fail("Non-virtualized write was prematurely checked!"); 6036 } 6037 6038 skip_exit_vmcall(); 6039 report_prefix_pop(); 6040 } 6041 6042 enum Config_type { 6043 CONFIG_TYPE_GOOD, 6044 CONFIG_TYPE_UNSUPPORTED, 6045 CONFIG_TYPE_VMENTRY_FAILS_EARLY, 6046 }; 6047 6048 static enum Config_type configure_apic_reg_virt_test( 6049 struct apic_reg_virt_config *apic_reg_virt_config) 6050 { 6051 u32 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6052 u32 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6053 /* Configs where L2 entry fails early, due to invalid controls. */ 6054 bool use_tpr_shadow_incorrectly_off = 6055 !apic_reg_virt_config->use_tpr_shadow && 6056 (apic_reg_virt_config->apic_register_virtualization || 6057 apic_reg_virt_config->virtualize_x2apic_mode) && 6058 apic_reg_virt_config->activate_secondary_controls; 6059 bool virtualize_apic_accesses_incorrectly_on = 6060 apic_reg_virt_config->virtualize_apic_accesses && 6061 apic_reg_virt_config->virtualize_x2apic_mode && 6062 apic_reg_virt_config->activate_secondary_controls; 6063 bool vmentry_fails_early = 6064 use_tpr_shadow_incorrectly_off || 6065 virtualize_apic_accesses_incorrectly_on; 6066 6067 if (apic_reg_virt_config->activate_secondary_controls) { 6068 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 6069 printf("VM-execution control \"activate secondary controls\" NOT supported.\n"); 6070 return CONFIG_TYPE_UNSUPPORTED; 6071 } 6072 cpu_exec_ctrl0 |= CPU_SECONDARY; 6073 } else { 6074 cpu_exec_ctrl0 &= ~CPU_SECONDARY; 6075 } 6076 6077 if (apic_reg_virt_config->virtualize_apic_accesses) { 6078 if (!(ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES)) { 6079 printf("VM-execution control \"virtualize APIC accesses\" NOT supported.\n"); 6080 return CONFIG_TYPE_UNSUPPORTED; 6081 } 6082 cpu_exec_ctrl1 |= CPU_VIRT_APIC_ACCESSES; 6083 } else { 6084 cpu_exec_ctrl1 &= ~CPU_VIRT_APIC_ACCESSES; 6085 } 6086 6087 if (apic_reg_virt_config->use_tpr_shadow) { 6088 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) { 6089 printf("VM-execution control \"use TPR shadow\" NOT supported.\n"); 6090 return CONFIG_TYPE_UNSUPPORTED; 6091 } 6092 cpu_exec_ctrl0 |= CPU_TPR_SHADOW; 6093 } else { 6094 cpu_exec_ctrl0 &= ~CPU_TPR_SHADOW; 6095 } 6096 6097 if (apic_reg_virt_config->apic_register_virtualization) { 6098 if (!(ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT)) { 6099 printf("VM-execution control \"APIC-register virtualization\" NOT supported.\n"); 6100 return CONFIG_TYPE_UNSUPPORTED; 6101 } 6102 cpu_exec_ctrl1 |= CPU_APIC_REG_VIRT; 6103 } else { 6104 cpu_exec_ctrl1 &= ~CPU_APIC_REG_VIRT; 6105 } 6106 6107 if (apic_reg_virt_config->virtualize_x2apic_mode) { 6108 if (!(ctrl_cpu_rev[1].clr & CPU_VIRT_X2APIC)) { 6109 printf("VM-execution control \"virtualize x2APIC mode\" NOT supported.\n"); 6110 return CONFIG_TYPE_UNSUPPORTED; 6111 } 6112 cpu_exec_ctrl1 |= CPU_VIRT_X2APIC; 6113 } else { 6114 cpu_exec_ctrl1 &= ~CPU_VIRT_X2APIC; 6115 } 6116 6117 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6118 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6119 6120 if (vmentry_fails_early) 6121 return CONFIG_TYPE_VMENTRY_FAILS_EARLY; 6122 6123 return CONFIG_TYPE_GOOD; 6124 } 6125 6126 static bool cpu_has_apicv(void) 6127 { 6128 return ((ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT) && 6129 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 6130 (ctrl_pin_rev.clr & PIN_POST_INTR)); 6131 } 6132 6133 /* Validates APIC register access across valid virtualization configurations. */ 6134 static void apic_reg_virt_test(void) 6135 { 6136 u32 *apic_access_address; 6137 u32 *virtual_apic_page; 6138 u64 control; 6139 u64 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6140 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6141 int i; 6142 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 6143 6144 if (!cpu_has_apicv()) { 6145 report_skip(__func__); 6146 return; 6147 } 6148 6149 control = cpu_exec_ctrl1; 6150 control &= ~CPU_VINTD; 6151 vmcs_write(CPU_EXEC_CTRL1, control); 6152 6153 test_set_guest(apic_reg_virt_guest); 6154 6155 /* 6156 * From the SDM: The 1-setting of the "virtualize APIC accesses" 6157 * VM-execution is guaranteed to apply only if translations to the 6158 * APIC-access address use a 4-KByte page. 6159 */ 6160 apic_access_address = alloc_page(); 6161 force_4k_page(apic_access_address); 6162 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_address)); 6163 6164 virtual_apic_page = alloc_page(); 6165 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 6166 6167 for (i = 0; i < ARRAY_SIZE(apic_reg_tests); i++) { 6168 struct apic_reg_test *apic_reg_test = &apic_reg_tests[i]; 6169 struct apic_reg_virt_config *apic_reg_virt_config = 6170 &apic_reg_test->apic_reg_virt_config; 6171 enum Config_type config_type; 6172 u32 reg; 6173 6174 printf("--- %s test ---\n", apic_reg_test->name); 6175 config_type = 6176 configure_apic_reg_virt_test(apic_reg_virt_config); 6177 if (config_type == CONFIG_TYPE_UNSUPPORTED) { 6178 printf("Skip because of missing features.\n"); 6179 continue; 6180 } 6181 6182 if (config_type == CONFIG_TYPE_VMENTRY_FAILS_EARLY) { 6183 enter_guest_with_bad_controls(); 6184 continue; 6185 } 6186 6187 for (reg = 0; reg < PAGE_SIZE / sizeof(u32); reg += 0x10) { 6188 struct apic_reg_virt_expectation expectation = {}; 6189 bool ok; 6190 6191 ok = apic_reg_virt_exit_expectation( 6192 reg, apic_reg_virt_config, &expectation); 6193 if (!ok) { 6194 report_fail("Malformed test."); 6195 break; 6196 } 6197 6198 test_xapic_rd(reg, &expectation, apic_access_address, 6199 virtual_apic_page); 6200 test_xapic_wr(reg, &expectation, apic_access_address, 6201 virtual_apic_page); 6202 } 6203 } 6204 6205 /* Terminate the guest */ 6206 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6207 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6208 args->op = TERMINATE; 6209 enter_guest(); 6210 assert_exit_reason(VMX_VMCALL); 6211 } 6212 6213 struct virt_x2apic_mode_config { 6214 struct apic_reg_virt_config apic_reg_virt_config; 6215 bool virtual_interrupt_delivery; 6216 bool use_msr_bitmaps; 6217 bool disable_x2apic_msr_intercepts; 6218 bool disable_x2apic; 6219 }; 6220 6221 struct virt_x2apic_mode_test_case { 6222 const char *name; 6223 struct virt_x2apic_mode_config virt_x2apic_mode_config; 6224 }; 6225 6226 enum Virt_x2apic_mode_behavior_type { 6227 X2APIC_ACCESS_VIRTUALIZED, 6228 X2APIC_ACCESS_PASSED_THROUGH, 6229 X2APIC_ACCESS_TRIGGERS_GP, 6230 }; 6231 6232 struct virt_x2apic_mode_expectation { 6233 enum Reason rd_exit_reason; 6234 enum Reason wr_exit_reason; 6235 6236 /* 6237 * RDMSR and WRMSR handle 64-bit values. However, except for ICR, all of 6238 * the x2APIC registers are 32 bits. Notice: 6239 * 1. vmx_x2apic_read() clears the upper 32 bits for 32-bit registers. 6240 * 2. vmx_x2apic_write() expects the val arg to be well-formed. 6241 */ 6242 u64 rd_val; 6243 u64 wr_val; 6244 6245 /* 6246 * Compares input to virtualized output; 6247 * 1st arg is pointer to return expected virtualization output. 6248 */ 6249 u64 (*virt_fn)(u64); 6250 6251 enum Virt_x2apic_mode_behavior_type rd_behavior; 6252 enum Virt_x2apic_mode_behavior_type wr_behavior; 6253 bool wr_only; 6254 }; 6255 6256 static u64 virt_x2apic_mode_identity(u64 val) 6257 { 6258 return val; 6259 } 6260 6261 static u64 virt_x2apic_mode_nibble1(u64 val) 6262 { 6263 return val & 0xf0; 6264 } 6265 6266 static void virt_x2apic_mode_rd_expectation( 6267 u32 reg, bool virt_x2apic_mode_on, bool disable_x2apic, 6268 bool apic_register_virtualization, bool virtual_interrupt_delivery, 6269 struct virt_x2apic_mode_expectation *expectation) 6270 { 6271 bool readable = 6272 !x2apic_reg_reserved(reg) && 6273 reg != APIC_EOI; 6274 6275 expectation->rd_exit_reason = VMX_VMCALL; 6276 expectation->virt_fn = virt_x2apic_mode_identity; 6277 if (virt_x2apic_mode_on && apic_register_virtualization) { 6278 expectation->rd_val = MAGIC_VAL_1; 6279 if (reg == APIC_PROCPRI && virtual_interrupt_delivery) 6280 expectation->virt_fn = virt_x2apic_mode_nibble1; 6281 else if (reg == APIC_TASKPRI) 6282 expectation->virt_fn = virt_x2apic_mode_nibble1; 6283 expectation->rd_behavior = X2APIC_ACCESS_VIRTUALIZED; 6284 } else if (virt_x2apic_mode_on && !apic_register_virtualization && 6285 reg == APIC_TASKPRI) { 6286 expectation->rd_val = MAGIC_VAL_1; 6287 expectation->virt_fn = virt_x2apic_mode_nibble1; 6288 expectation->rd_behavior = X2APIC_ACCESS_VIRTUALIZED; 6289 } else if (!disable_x2apic && readable) { 6290 expectation->rd_val = apic_read(reg); 6291 expectation->rd_behavior = X2APIC_ACCESS_PASSED_THROUGH; 6292 } else { 6293 expectation->rd_behavior = X2APIC_ACCESS_TRIGGERS_GP; 6294 } 6295 } 6296 6297 /* 6298 * get_x2apic_wr_val() creates an innocuous write value for an x2APIC register. 6299 * 6300 * For writable registers, get_x2apic_wr_val() deposits the write value into the 6301 * val pointer arg and returns true. For non-writable registers, val is not 6302 * modified and get_x2apic_wr_val() returns false. 6303 */ 6304 static bool get_x2apic_wr_val(u32 reg, u64 *val) 6305 { 6306 switch (reg) { 6307 case APIC_TASKPRI: 6308 /* Bits 31:8 are reserved. */ 6309 *val &= 0xff; 6310 break; 6311 case APIC_EOI: 6312 case APIC_ESR: 6313 case APIC_TMICT: 6314 /* 6315 * EOI, ESR: WRMSR of a non-zero value causes #GP(0). 6316 * TMICT: A write of 0 to the initial-count register effectively 6317 * stops the local APIC timer, in both one-shot and 6318 * periodic mode. 6319 */ 6320 *val = 0; 6321 break; 6322 case APIC_SPIV: 6323 case APIC_LVTT: 6324 case APIC_LVTTHMR: 6325 case APIC_LVTPC: 6326 case APIC_LVT0: 6327 case APIC_LVT1: 6328 case APIC_LVTERR: 6329 case APIC_TDCR: 6330 /* 6331 * To avoid writing a 1 to a reserved bit or causing some other 6332 * unintended side effect, read the current value and use it as 6333 * the write value. 6334 */ 6335 *val = apic_read(reg); 6336 break; 6337 case APIC_CMCI: 6338 if (!apic_lvt_entry_supported(6)) 6339 return false; 6340 *val = apic_read(reg); 6341 break; 6342 case APIC_ICR: 6343 *val = 0x40000 | 0xf1; 6344 break; 6345 case APIC_SELF_IPI: 6346 /* 6347 * With special processing (i.e., virtualize x2APIC mode + 6348 * virtual interrupt delivery), writing zero causes an 6349 * APIC-write VM exit. We plan to add a test for enabling 6350 * "virtual-interrupt delivery" in VMCS12, and that's where we 6351 * will test a self IPI with special processing. 6352 */ 6353 *val = 0x0; 6354 break; 6355 default: 6356 return false; 6357 } 6358 6359 return true; 6360 } 6361 6362 static bool special_processing_applies(u32 reg, u64 *val, 6363 bool virt_int_delivery) 6364 { 6365 bool special_processing = 6366 (reg == APIC_TASKPRI) || 6367 (virt_int_delivery && 6368 (reg == APIC_EOI || reg == APIC_SELF_IPI)); 6369 6370 if (special_processing) { 6371 TEST_ASSERT(get_x2apic_wr_val(reg, val)); 6372 return true; 6373 } 6374 6375 return false; 6376 } 6377 6378 static void virt_x2apic_mode_wr_expectation( 6379 u32 reg, bool virt_x2apic_mode_on, bool disable_x2apic, 6380 bool virt_int_delivery, 6381 struct virt_x2apic_mode_expectation *expectation) 6382 { 6383 expectation->wr_exit_reason = VMX_VMCALL; 6384 expectation->wr_val = MAGIC_VAL_1; 6385 expectation->wr_only = false; 6386 6387 if (virt_x2apic_mode_on && 6388 special_processing_applies(reg, &expectation->wr_val, 6389 virt_int_delivery)) { 6390 expectation->wr_behavior = X2APIC_ACCESS_VIRTUALIZED; 6391 if (reg == APIC_SELF_IPI) 6392 expectation->wr_exit_reason = VMX_APIC_WRITE; 6393 } else if (!disable_x2apic && 6394 get_x2apic_wr_val(reg, &expectation->wr_val)) { 6395 expectation->wr_behavior = X2APIC_ACCESS_PASSED_THROUGH; 6396 if (reg == APIC_EOI || reg == APIC_SELF_IPI) 6397 expectation->wr_only = true; 6398 if (reg == APIC_ICR) 6399 expectation->wr_exit_reason = VMX_EXTINT; 6400 } else { 6401 expectation->wr_behavior = X2APIC_ACCESS_TRIGGERS_GP; 6402 /* 6403 * Writing 1 to a reserved bit triggers a #GP. 6404 * Thus, set the write value to 0, which seems 6405 * the most likely to detect a missed #GP. 6406 */ 6407 expectation->wr_val = 0; 6408 } 6409 } 6410 6411 static void virt_x2apic_mode_exit_expectation( 6412 u32 reg, struct virt_x2apic_mode_config *config, 6413 struct virt_x2apic_mode_expectation *expectation) 6414 { 6415 struct apic_reg_virt_config *base_config = 6416 &config->apic_reg_virt_config; 6417 bool virt_x2apic_mode_on = 6418 base_config->virtualize_x2apic_mode && 6419 config->use_msr_bitmaps && 6420 config->disable_x2apic_msr_intercepts && 6421 base_config->activate_secondary_controls; 6422 6423 virt_x2apic_mode_wr_expectation( 6424 reg, virt_x2apic_mode_on, config->disable_x2apic, 6425 config->virtual_interrupt_delivery, expectation); 6426 virt_x2apic_mode_rd_expectation( 6427 reg, virt_x2apic_mode_on, config->disable_x2apic, 6428 base_config->apic_register_virtualization, 6429 config->virtual_interrupt_delivery, expectation); 6430 } 6431 6432 struct virt_x2apic_mode_test_case virt_x2apic_mode_tests[] = { 6433 /* 6434 * Baseline "virtualize x2APIC mode" configuration: 6435 * - virtualize x2APIC mode 6436 * - virtual-interrupt delivery 6437 * - APIC-register virtualization 6438 * - x2APIC MSR intercepts disabled 6439 * 6440 * Reads come from virtual APIC page, special processing applies to 6441 * VTPR, EOI, and SELF IPI, and all other writes pass through to L1 6442 * APIC. 6443 */ 6444 { 6445 .name = "Baseline", 6446 .virt_x2apic_mode_config = { 6447 .virtual_interrupt_delivery = true, 6448 .use_msr_bitmaps = true, 6449 .disable_x2apic_msr_intercepts = true, 6450 .disable_x2apic = false, 6451 .apic_reg_virt_config = { 6452 .apic_register_virtualization = true, 6453 .use_tpr_shadow = true, 6454 .virtualize_apic_accesses = false, 6455 .virtualize_x2apic_mode = true, 6456 .activate_secondary_controls = true, 6457 }, 6458 }, 6459 }, 6460 { 6461 .name = "Baseline w/ x2apic disabled", 6462 .virt_x2apic_mode_config = { 6463 .virtual_interrupt_delivery = true, 6464 .use_msr_bitmaps = true, 6465 .disable_x2apic_msr_intercepts = true, 6466 .disable_x2apic = true, 6467 .apic_reg_virt_config = { 6468 .apic_register_virtualization = true, 6469 .use_tpr_shadow = true, 6470 .virtualize_apic_accesses = false, 6471 .virtualize_x2apic_mode = true, 6472 .activate_secondary_controls = true, 6473 }, 6474 }, 6475 }, 6476 6477 /* 6478 * Baseline, minus virtual-interrupt delivery. Reads come from virtual 6479 * APIC page, special processing applies to VTPR, and all other writes 6480 * pass through to L1 APIC. 6481 */ 6482 { 6483 .name = "Baseline - virtual interrupt delivery", 6484 .virt_x2apic_mode_config = { 6485 .virtual_interrupt_delivery = false, 6486 .use_msr_bitmaps = true, 6487 .disable_x2apic_msr_intercepts = true, 6488 .disable_x2apic = false, 6489 .apic_reg_virt_config = { 6490 .apic_register_virtualization = true, 6491 .use_tpr_shadow = true, 6492 .virtualize_apic_accesses = false, 6493 .virtualize_x2apic_mode = true, 6494 .activate_secondary_controls = true, 6495 }, 6496 }, 6497 }, 6498 6499 /* 6500 * Baseline, minus APIC-register virtualization. x2APIC reads pass 6501 * through to L1's APIC, unless reading VTPR 6502 */ 6503 { 6504 .name = "Virtualize x2APIC mode, no APIC reg virt", 6505 .virt_x2apic_mode_config = { 6506 .virtual_interrupt_delivery = true, 6507 .use_msr_bitmaps = true, 6508 .disable_x2apic_msr_intercepts = true, 6509 .disable_x2apic = false, 6510 .apic_reg_virt_config = { 6511 .apic_register_virtualization = false, 6512 .use_tpr_shadow = true, 6513 .virtualize_apic_accesses = false, 6514 .virtualize_x2apic_mode = true, 6515 .activate_secondary_controls = true, 6516 }, 6517 }, 6518 }, 6519 { 6520 .name = "Virtualize x2APIC mode, no APIC reg virt, x2APIC off", 6521 .virt_x2apic_mode_config = { 6522 .virtual_interrupt_delivery = true, 6523 .use_msr_bitmaps = true, 6524 .disable_x2apic_msr_intercepts = true, 6525 .disable_x2apic = true, 6526 .apic_reg_virt_config = { 6527 .apic_register_virtualization = false, 6528 .use_tpr_shadow = true, 6529 .virtualize_apic_accesses = false, 6530 .virtualize_x2apic_mode = true, 6531 .activate_secondary_controls = true, 6532 }, 6533 }, 6534 }, 6535 6536 /* 6537 * Enable "virtualize x2APIC mode" and "APIC-register virtualization", 6538 * and disable intercepts for the x2APIC MSRs, but fail to enable 6539 * "activate secondary controls" (i.e. L2 gets access to L1's x2APIC 6540 * MSRs). 6541 */ 6542 { 6543 .name = "Fail to enable activate secondary controls", 6544 .virt_x2apic_mode_config = { 6545 .virtual_interrupt_delivery = true, 6546 .use_msr_bitmaps = true, 6547 .disable_x2apic_msr_intercepts = true, 6548 .disable_x2apic = false, 6549 .apic_reg_virt_config = { 6550 .apic_register_virtualization = true, 6551 .use_tpr_shadow = true, 6552 .virtualize_apic_accesses = false, 6553 .virtualize_x2apic_mode = true, 6554 .activate_secondary_controls = false, 6555 }, 6556 }, 6557 }, 6558 6559 /* 6560 * Enable "APIC-register virtualization" and enable "activate secondary 6561 * controls" and disable intercepts for the x2APIC MSRs, but do not 6562 * enable the "virtualize x2APIC mode" VM-execution control (i.e. L2 6563 * gets access to L1's x2APIC MSRs). 6564 */ 6565 { 6566 .name = "Fail to enable virtualize x2APIC mode", 6567 .virt_x2apic_mode_config = { 6568 .virtual_interrupt_delivery = true, 6569 .use_msr_bitmaps = true, 6570 .disable_x2apic_msr_intercepts = true, 6571 .disable_x2apic = false, 6572 .apic_reg_virt_config = { 6573 .apic_register_virtualization = true, 6574 .use_tpr_shadow = true, 6575 .virtualize_apic_accesses = false, 6576 .virtualize_x2apic_mode = false, 6577 .activate_secondary_controls = true, 6578 }, 6579 }, 6580 }, 6581 6582 /* 6583 * Disable "Virtualize x2APIC mode", disable x2APIC MSR intercepts, and 6584 * enable "APIC-register virtualization" --> L2 gets L1's x2APIC MSRs. 6585 */ 6586 { 6587 .name = "Baseline", 6588 .virt_x2apic_mode_config = { 6589 .virtual_interrupt_delivery = true, 6590 .use_msr_bitmaps = true, 6591 .disable_x2apic_msr_intercepts = true, 6592 .disable_x2apic = false, 6593 .apic_reg_virt_config = { 6594 .apic_register_virtualization = true, 6595 .use_tpr_shadow = true, 6596 .virtualize_apic_accesses = false, 6597 .virtualize_x2apic_mode = false, 6598 .activate_secondary_controls = true, 6599 }, 6600 }, 6601 }, 6602 }; 6603 6604 enum X2apic_op { 6605 X2APIC_OP_RD, 6606 X2APIC_OP_WR, 6607 X2APIC_TERMINATE, 6608 }; 6609 6610 static u64 vmx_x2apic_read(u32 reg) 6611 { 6612 u32 msr_addr = x2apic_msr(reg); 6613 u64 val; 6614 6615 val = rdmsr(msr_addr); 6616 6617 return val; 6618 } 6619 6620 static void vmx_x2apic_write(u32 reg, u64 val) 6621 { 6622 u32 msr_addr = x2apic_msr(reg); 6623 6624 wrmsr(msr_addr, val); 6625 } 6626 6627 struct virt_x2apic_mode_guest_args { 6628 enum X2apic_op op; 6629 u32 reg; 6630 u64 val; 6631 bool should_gp; 6632 u64 (*virt_fn)(u64); 6633 } virt_x2apic_mode_guest_args; 6634 6635 static volatile bool handle_x2apic_gp_ran; 6636 static volatile u32 handle_x2apic_gp_insn_len; 6637 static void handle_x2apic_gp(struct ex_regs *regs) 6638 { 6639 handle_x2apic_gp_ran = true; 6640 regs->rip += handle_x2apic_gp_insn_len; 6641 } 6642 6643 static handler setup_x2apic_gp_handler(void) 6644 { 6645 handler old_handler; 6646 6647 old_handler = handle_exception(GP_VECTOR, handle_x2apic_gp); 6648 /* RDMSR and WRMSR are both 2 bytes, assuming no prefixes. */ 6649 handle_x2apic_gp_insn_len = 2; 6650 6651 return old_handler; 6652 } 6653 6654 static void teardown_x2apic_gp_handler(handler old_handler) 6655 { 6656 handle_exception(GP_VECTOR, old_handler); 6657 6658 /* 6659 * Defensively reset instruction length, so that if the handler is 6660 * incorrectly used, it will loop infinitely, rather than run off into 6661 * la la land. 6662 */ 6663 handle_x2apic_gp_insn_len = 0; 6664 handle_x2apic_gp_ran = false; 6665 } 6666 6667 static void virt_x2apic_mode_guest(void) 6668 { 6669 volatile struct virt_x2apic_mode_guest_args *args = 6670 &virt_x2apic_mode_guest_args; 6671 6672 for (;;) { 6673 enum X2apic_op op = args->op; 6674 u32 reg = args->reg; 6675 u64 val = args->val; 6676 bool should_gp = args->should_gp; 6677 u64 (*virt_fn)(u64) = args->virt_fn; 6678 handler old_handler; 6679 6680 if (op == X2APIC_TERMINATE) 6681 break; 6682 6683 if (should_gp) { 6684 TEST_ASSERT(!handle_x2apic_gp_ran); 6685 old_handler = setup_x2apic_gp_handler(); 6686 } 6687 6688 if (op == X2APIC_OP_RD) { 6689 u64 ret = vmx_x2apic_read(reg); 6690 6691 if (!should_gp) { 6692 u64 want = virt_fn(val); 6693 u64 got = virt_fn(ret); 6694 6695 report(got == want, 6696 "APIC read; got 0x%lx, want 0x%lx.", 6697 got, want); 6698 } 6699 } else if (op == X2APIC_OP_WR) { 6700 vmx_x2apic_write(reg, val); 6701 } 6702 6703 if (should_gp) { 6704 report(handle_x2apic_gp_ran, 6705 "x2APIC op triggered GP."); 6706 teardown_x2apic_gp_handler(old_handler); 6707 } 6708 6709 /* 6710 * The L1 should always execute a vmcall after it's done testing 6711 * an individual APIC operation. This helps to validate that the 6712 * L1 and L2 are in sync with each other, as expected. 6713 */ 6714 vmcall(); 6715 } 6716 } 6717 6718 static void test_x2apic_rd( 6719 u32 reg, struct virt_x2apic_mode_expectation *expectation, 6720 u32 *virtual_apic_page) 6721 { 6722 u64 val = expectation->rd_val; 6723 u32 exit_reason_want = expectation->rd_exit_reason; 6724 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6725 6726 report_prefix_pushf("x2apic - reading 0x%03x", reg); 6727 6728 /* Configure guest to do an x2apic read */ 6729 args->op = X2APIC_OP_RD; 6730 args->reg = reg; 6731 args->val = val; 6732 args->should_gp = expectation->rd_behavior == X2APIC_ACCESS_TRIGGERS_GP; 6733 args->virt_fn = expectation->virt_fn; 6734 6735 /* Setup virtual APIC page */ 6736 if (expectation->rd_behavior == X2APIC_ACCESS_VIRTUALIZED) 6737 virtual_apic_page[apic_reg_index(reg)] = (u32)val; 6738 6739 /* Enter guest */ 6740 enter_guest(); 6741 6742 if (exit_reason_want != VMX_VMCALL) { 6743 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 6744 } 6745 6746 skip_exit_vmcall(); 6747 report_prefix_pop(); 6748 } 6749 6750 static volatile bool handle_x2apic_ipi_ran; 6751 static void handle_x2apic_ipi(isr_regs_t *regs) 6752 { 6753 handle_x2apic_ipi_ran = true; 6754 eoi(); 6755 } 6756 6757 static void test_x2apic_wr( 6758 u32 reg, struct virt_x2apic_mode_expectation *expectation, 6759 u32 *virtual_apic_page) 6760 { 6761 u64 val = expectation->wr_val; 6762 u32 exit_reason_want = expectation->wr_exit_reason; 6763 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6764 int ipi_vector = 0xf1; 6765 u32 restore_val = 0; 6766 6767 report_prefix_pushf("x2apic - writing 0x%lx to 0x%03x", val, reg); 6768 6769 /* Configure guest to do an x2apic read */ 6770 args->op = X2APIC_OP_WR; 6771 args->reg = reg; 6772 args->val = val; 6773 args->should_gp = expectation->wr_behavior == X2APIC_ACCESS_TRIGGERS_GP; 6774 6775 /* Setup virtual APIC page */ 6776 if (expectation->wr_behavior == X2APIC_ACCESS_VIRTUALIZED) 6777 virtual_apic_page[apic_reg_index(reg)] = 0; 6778 if (expectation->wr_behavior == X2APIC_ACCESS_PASSED_THROUGH && !expectation->wr_only) 6779 restore_val = apic_read(reg); 6780 6781 /* Setup IPI handler */ 6782 handle_x2apic_ipi_ran = false; 6783 handle_irq(ipi_vector, handle_x2apic_ipi); 6784 6785 /* Enter guest */ 6786 enter_guest(); 6787 6788 /* 6789 * Validate the behavior and 6790 * pass a magic value back to the guest. 6791 */ 6792 if (exit_reason_want == VMX_EXTINT) { 6793 assert_exit_reason(exit_reason_want); 6794 6795 /* Clear the external interrupt. */ 6796 irq_enable(); 6797 asm volatile ("nop"); 6798 irq_disable(); 6799 report(handle_x2apic_ipi_ran, 6800 "Got pending interrupt after IRQ enabled."); 6801 6802 enter_guest(); 6803 } else if (exit_reason_want == VMX_APIC_WRITE) { 6804 assert_exit_reason(exit_reason_want); 6805 report(virtual_apic_page[apic_reg_index(reg)] == val, 6806 "got APIC write exit @ page offset 0x%03x; val is 0x%x, want 0x%lx", 6807 apic_reg_index(reg), 6808 virtual_apic_page[apic_reg_index(reg)], val); 6809 6810 /* Reenter guest so it can consume/check rcx and exit again. */ 6811 enter_guest(); 6812 } else if (exit_reason_want != VMX_VMCALL) { 6813 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 6814 } 6815 6816 assert_exit_reason(VMX_VMCALL); 6817 if (expectation->wr_behavior == X2APIC_ACCESS_VIRTUALIZED) { 6818 u64 want = val; 6819 u32 got = virtual_apic_page[apic_reg_index(reg)]; 6820 6821 report(got == want, "x2APIC write; got 0x%x, want 0x%lx", got, 6822 want); 6823 } else if (expectation->wr_behavior == X2APIC_ACCESS_PASSED_THROUGH) { 6824 if (!expectation->wr_only) { 6825 u32 got = apic_read(reg); 6826 bool ok; 6827 6828 /* 6829 * When L1's TPR is passed through to L2, the lower 6830 * nibble can be lost. For example, if L2 executes 6831 * WRMSR(0x808, 0x78), then, L1 might read 0x70. 6832 * 6833 * Here's how the lower nibble can get lost: 6834 * 1. L2 executes WRMSR(0x808, 0x78). 6835 * 2. L2 exits to L0 with a WRMSR exit. 6836 * 3. L0 emulates WRMSR, by writing L1's TPR. 6837 * 4. L0 re-enters L2. 6838 * 5. L2 exits to L0 (reason doesn't matter). 6839 * 6. L0 reflects L2's exit to L1. 6840 * 7. Before entering L1, L0 exits to user-space 6841 * (e.g., to satisfy TPR access reporting). 6842 * 8. User-space executes KVM_SET_REGS ioctl, which 6843 * clears the lower nibble of L1's TPR. 6844 */ 6845 if (reg == APIC_TASKPRI) { 6846 got = apic_virt_nibble1(got); 6847 val = apic_virt_nibble1(val); 6848 } 6849 6850 ok = got == val; 6851 report(ok, 6852 "non-virtualized write; val is 0x%x, want 0x%lx", 6853 got, val); 6854 apic_write(reg, restore_val); 6855 } else { 6856 report_pass("non-virtualized and write-only OK"); 6857 } 6858 } 6859 skip_exit_insn(); 6860 6861 report_prefix_pop(); 6862 } 6863 6864 static enum Config_type configure_virt_x2apic_mode_test( 6865 struct virt_x2apic_mode_config *virt_x2apic_mode_config, 6866 u8 *msr_bitmap_page) 6867 { 6868 int msr; 6869 u32 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6870 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6871 6872 /* x2apic-specific VMCS config */ 6873 if (virt_x2apic_mode_config->use_msr_bitmaps) { 6874 /* virt_x2apic_mode_test() checks for MSR bitmaps support */ 6875 cpu_exec_ctrl0 |= CPU_MSR_BITMAP; 6876 } else { 6877 cpu_exec_ctrl0 &= ~CPU_MSR_BITMAP; 6878 } 6879 6880 if (virt_x2apic_mode_config->virtual_interrupt_delivery) { 6881 if (!(ctrl_cpu_rev[1].clr & CPU_VINTD)) { 6882 report_skip("VM-execution control \"virtual-interrupt delivery\" NOT supported.\n"); 6883 return CONFIG_TYPE_UNSUPPORTED; 6884 } 6885 cpu_exec_ctrl1 |= CPU_VINTD; 6886 } else { 6887 cpu_exec_ctrl1 &= ~CPU_VINTD; 6888 } 6889 6890 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6891 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6892 6893 /* x2APIC MSR intercepts are usually off for "Virtualize x2APIC mode" */ 6894 for (msr = 0x800; msr <= 0x8ff; msr++) { 6895 if (virt_x2apic_mode_config->disable_x2apic_msr_intercepts) { 6896 clear_bit(msr, msr_bitmap_page + 0x000); 6897 clear_bit(msr, msr_bitmap_page + 0x800); 6898 } else { 6899 set_bit(msr, msr_bitmap_page + 0x000); 6900 set_bit(msr, msr_bitmap_page + 0x800); 6901 } 6902 } 6903 6904 /* x2APIC mode can impact virtualization */ 6905 reset_apic(); 6906 if (!virt_x2apic_mode_config->disable_x2apic) 6907 enable_x2apic(); 6908 6909 return configure_apic_reg_virt_test( 6910 &virt_x2apic_mode_config->apic_reg_virt_config); 6911 } 6912 6913 static void virt_x2apic_mode_test(void) 6914 { 6915 u32 *virtual_apic_page; 6916 u8 *msr_bitmap_page; 6917 u64 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6918 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6919 int i; 6920 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6921 6922 if (!cpu_has_apicv()) { 6923 report_skip(__func__); 6924 return; 6925 } 6926 6927 /* 6928 * This is to exercise an issue in KVM's logic to merge L0's and L1's 6929 * MSR bitmaps. Previously, an L1 could get at L0's x2APIC MSRs by 6930 * writing the IA32_SPEC_CTRL MSR or the IA32_PRED_CMD MSRs. KVM would 6931 * then proceed to manipulate the MSR bitmaps, as if VMCS12 had the 6932 * "Virtualize x2APIC mod" control set, even when it didn't. 6933 */ 6934 if (has_spec_ctrl()) 6935 wrmsr(MSR_IA32_SPEC_CTRL, 1); 6936 6937 /* 6938 * Check that VMCS12 supports: 6939 * - "Virtual-APIC address", indicated by "use TPR shadow" 6940 * - "MSR-bitmap address", indicated by "use MSR bitmaps" 6941 */ 6942 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) { 6943 report_skip("VM-execution control \"use TPR shadow\" NOT supported.\n"); 6944 return; 6945 } else if (!(ctrl_cpu_rev[0].clr & CPU_MSR_BITMAP)) { 6946 report_skip("VM-execution control \"use MSR bitmaps\" NOT supported.\n"); 6947 return; 6948 } 6949 6950 test_set_guest(virt_x2apic_mode_guest); 6951 6952 virtual_apic_page = alloc_page(); 6953 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 6954 6955 msr_bitmap_page = alloc_page(); 6956 memset(msr_bitmap_page, 0xff, PAGE_SIZE); 6957 vmcs_write(MSR_BITMAP, virt_to_phys(msr_bitmap_page)); 6958 6959 for (i = 0; i < ARRAY_SIZE(virt_x2apic_mode_tests); i++) { 6960 struct virt_x2apic_mode_test_case *virt_x2apic_mode_test_case = 6961 &virt_x2apic_mode_tests[i]; 6962 struct virt_x2apic_mode_config *virt_x2apic_mode_config = 6963 &virt_x2apic_mode_test_case->virt_x2apic_mode_config; 6964 enum Config_type config_type; 6965 u32 reg; 6966 6967 printf("--- %s test ---\n", virt_x2apic_mode_test_case->name); 6968 config_type = 6969 configure_virt_x2apic_mode_test(virt_x2apic_mode_config, 6970 msr_bitmap_page); 6971 if (config_type == CONFIG_TYPE_UNSUPPORTED) { 6972 report_skip("Skip because of missing features.\n"); 6973 continue; 6974 } else if (config_type == CONFIG_TYPE_VMENTRY_FAILS_EARLY) { 6975 enter_guest_with_bad_controls(); 6976 continue; 6977 } 6978 6979 for (reg = 0; reg < PAGE_SIZE / sizeof(u32); reg += 0x10) { 6980 struct virt_x2apic_mode_expectation expectation; 6981 6982 virt_x2apic_mode_exit_expectation( 6983 reg, virt_x2apic_mode_config, &expectation); 6984 6985 test_x2apic_rd(reg, &expectation, virtual_apic_page); 6986 test_x2apic_wr(reg, &expectation, virtual_apic_page); 6987 } 6988 } 6989 6990 6991 /* Terminate the guest */ 6992 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6993 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6994 args->op = X2APIC_TERMINATE; 6995 enter_guest(); 6996 assert_exit_reason(VMX_VMCALL); 6997 } 6998 6999 static void test_ctl_reg(const char *cr_name, u64 cr, u64 fixed0, u64 fixed1) 7000 { 7001 u64 val; 7002 u64 cr_saved = vmcs_read(cr); 7003 int i; 7004 7005 val = fixed0 & fixed1; 7006 if (cr == HOST_CR4) 7007 vmcs_write(cr, val | X86_CR4_PAE); 7008 else 7009 vmcs_write(cr, val); 7010 report_prefix_pushf("%s %lx", cr_name, val); 7011 if (val == fixed0) 7012 test_vmx_vmlaunch(0); 7013 else 7014 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7015 report_prefix_pop(); 7016 7017 for (i = 0; i < 64; i++) { 7018 7019 /* Set a bit when the corresponding bit in fixed1 is 0 */ 7020 if ((fixed1 & (1ull << i)) == 0) { 7021 if (cr == HOST_CR4 && ((1ull << i) & X86_CR4_SMEP || 7022 (1ull << i) & X86_CR4_SMAP)) 7023 continue; 7024 7025 vmcs_write(cr, cr_saved | (1ull << i)); 7026 report_prefix_pushf("%s %llx", cr_name, 7027 cr_saved | (1ull << i)); 7028 test_vmx_vmlaunch( 7029 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7030 report_prefix_pop(); 7031 } 7032 7033 /* Unset a bit when the corresponding bit in fixed0 is 1 */ 7034 if (fixed0 & (1ull << i)) { 7035 vmcs_write(cr, cr_saved & ~(1ull << i)); 7036 report_prefix_pushf("%s %llx", cr_name, 7037 cr_saved & ~(1ull << i)); 7038 test_vmx_vmlaunch( 7039 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7040 report_prefix_pop(); 7041 } 7042 } 7043 7044 vmcs_write(cr, cr_saved); 7045 } 7046 7047 /* 7048 * 1. The CR0 field must not set any bit to a value not supported in VMX 7049 * operation. 7050 * 2. The CR4 field must not set any bit to a value not supported in VMX 7051 * operation. 7052 * 3. On processors that support Intel 64 architecture, the CR3 field must 7053 * be such that bits 63:52 and bits in the range 51:32 beyond the 7054 * processor's physical-address width must be 0. 7055 * 7056 * [Intel SDM] 7057 */ 7058 static void test_host_ctl_regs(void) 7059 { 7060 u64 fixed0, fixed1, cr3, cr3_saved; 7061 int i; 7062 7063 /* Test CR0 */ 7064 fixed0 = rdmsr(MSR_IA32_VMX_CR0_FIXED0); 7065 fixed1 = rdmsr(MSR_IA32_VMX_CR0_FIXED1); 7066 test_ctl_reg("HOST_CR0", HOST_CR0, fixed0, fixed1); 7067 7068 /* Test CR4 */ 7069 fixed0 = rdmsr(MSR_IA32_VMX_CR4_FIXED0); 7070 fixed1 = rdmsr(MSR_IA32_VMX_CR4_FIXED1) & 7071 ~(X86_CR4_SMEP | X86_CR4_SMAP); 7072 test_ctl_reg("HOST_CR4", HOST_CR4, fixed0, fixed1); 7073 7074 /* Test CR3 */ 7075 cr3_saved = vmcs_read(HOST_CR3); 7076 for (i = cpuid_maxphyaddr(); i < 64; i++) { 7077 cr3 = cr3_saved | (1ul << i); 7078 vmcs_write(HOST_CR3, cr3); 7079 report_prefix_pushf("HOST_CR3 %lx", cr3); 7080 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7081 report_prefix_pop(); 7082 } 7083 7084 vmcs_write(HOST_CR3, cr3_saved); 7085 } 7086 7087 static void test_efer_vmlaunch(u32 fld, bool ok) 7088 { 7089 if (fld == HOST_EFER) { 7090 if (ok) 7091 test_vmx_vmlaunch(0); 7092 else 7093 test_vmx_vmlaunch2(VMXERR_ENTRY_INVALID_CONTROL_FIELD, 7094 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7095 } else { 7096 test_guest_state("EFER test", !ok, GUEST_EFER, "GUEST_EFER"); 7097 } 7098 } 7099 7100 static void test_efer_one(u32 fld, const char * fld_name, u64 efer, 7101 u32 ctrl_fld, u64 ctrl, 7102 int i, const char *efer_bit_name) 7103 { 7104 bool ok; 7105 7106 ok = true; 7107 if (ctrl_fld == EXI_CONTROLS && (ctrl & EXI_LOAD_EFER)) { 7108 if (!!(efer & EFER_LMA) != !!(ctrl & EXI_HOST_64)) 7109 ok = false; 7110 if (!!(efer & EFER_LME) != !!(ctrl & EXI_HOST_64)) 7111 ok = false; 7112 } 7113 if (ctrl_fld == ENT_CONTROLS && (ctrl & ENT_LOAD_EFER)) { 7114 /* Check LMA too since CR0.PG is set. */ 7115 if (!!(efer & EFER_LMA) != !!(ctrl & ENT_GUEST_64)) 7116 ok = false; 7117 if (!!(efer & EFER_LME) != !!(ctrl & ENT_GUEST_64)) 7118 ok = false; 7119 } 7120 7121 /* 7122 * Skip the test if it would enter the guest in 32-bit mode. 7123 * Perhaps write the test in assembly and make sure it 7124 * can be run in either mode? 7125 */ 7126 if (fld == GUEST_EFER && ok && !(ctrl & ENT_GUEST_64)) 7127 return; 7128 7129 vmcs_write(ctrl_fld, ctrl); 7130 vmcs_write(fld, efer); 7131 report_prefix_pushf("%s %s bit turned %s, controls %s", 7132 fld_name, efer_bit_name, 7133 (i & 1) ? "on" : "off", 7134 (i & 2) ? "on" : "off"); 7135 7136 test_efer_vmlaunch(fld, ok); 7137 report_prefix_pop(); 7138 } 7139 7140 static void test_efer_bit(u32 fld, const char * fld_name, 7141 u32 ctrl_fld, u64 ctrl_bit, u64 efer_bit, 7142 const char *efer_bit_name) 7143 { 7144 u64 efer_saved = vmcs_read(fld); 7145 u32 ctrl_saved = vmcs_read(ctrl_fld); 7146 int i; 7147 7148 for (i = 0; i < 4; i++) { 7149 u64 efer = efer_saved & ~efer_bit; 7150 u64 ctrl = ctrl_saved & ~ctrl_bit; 7151 7152 if (i & 1) 7153 efer |= efer_bit; 7154 if (i & 2) 7155 ctrl |= ctrl_bit; 7156 7157 test_efer_one(fld, fld_name, efer, ctrl_fld, ctrl, 7158 i, efer_bit_name); 7159 } 7160 7161 vmcs_write(ctrl_fld, ctrl_saved); 7162 vmcs_write(fld, efer_saved); 7163 } 7164 7165 static void test_efer(u32 fld, const char * fld_name, u32 ctrl_fld, 7166 u64 ctrl_bit1, u64 ctrl_bit2) 7167 { 7168 u64 efer_saved = vmcs_read(fld); 7169 u32 ctrl_saved = vmcs_read(ctrl_fld); 7170 u64 efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 7171 u64 i; 7172 u64 efer; 7173 7174 if (cpu_has_efer_nx()) 7175 efer_reserved_bits &= ~EFER_NX; 7176 7177 if (!ctrl_bit1) { 7178 printf("\"Load-IA32-EFER\" exit control not supported\n"); 7179 goto test_entry_exit_mode; 7180 } 7181 7182 report_prefix_pushf("%s %lx", fld_name, efer_saved); 7183 test_efer_vmlaunch(fld, true); 7184 report_prefix_pop(); 7185 7186 /* 7187 * Check reserved bits 7188 */ 7189 vmcs_write(ctrl_fld, ctrl_saved & ~ctrl_bit1); 7190 for (i = 0; i < 64; i++) { 7191 if ((1ull << i) & efer_reserved_bits) { 7192 efer = efer_saved | (1ull << i); 7193 vmcs_write(fld, efer); 7194 report_prefix_pushf("%s %lx", fld_name, efer); 7195 test_efer_vmlaunch(fld, true); 7196 report_prefix_pop(); 7197 } 7198 } 7199 7200 vmcs_write(ctrl_fld, ctrl_saved | ctrl_bit1); 7201 for (i = 0; i < 64; i++) { 7202 if ((1ull << i) & efer_reserved_bits) { 7203 efer = efer_saved | (1ull << i); 7204 vmcs_write(fld, efer); 7205 report_prefix_pushf("%s %lx", fld_name, efer); 7206 test_efer_vmlaunch(fld, false); 7207 report_prefix_pop(); 7208 } 7209 } 7210 7211 vmcs_write(ctrl_fld, ctrl_saved); 7212 vmcs_write(fld, efer_saved); 7213 7214 /* 7215 * Check LMA and LME bits 7216 */ 7217 test_efer_bit(fld, fld_name, 7218 ctrl_fld, ctrl_bit1, 7219 EFER_LMA, 7220 "EFER_LMA"); 7221 test_efer_bit(fld, fld_name, 7222 ctrl_fld, ctrl_bit1, 7223 EFER_LME, 7224 "EFER_LME"); 7225 7226 test_entry_exit_mode: 7227 test_efer_bit(fld, fld_name, 7228 ctrl_fld, ctrl_bit2, 7229 EFER_LMA, 7230 "EFER_LMA"); 7231 test_efer_bit(fld, fld_name, 7232 ctrl_fld, ctrl_bit2, 7233 EFER_LME, 7234 "EFER_LME"); 7235 } 7236 7237 /* 7238 * If the 'load IA32_EFER' VM-exit control is 1, bits reserved in the 7239 * IA32_EFER MSR must be 0 in the field for that register. In addition, 7240 * the values of the LMA and LME bits in the field must each be that of 7241 * the 'host address-space size' VM-exit control. 7242 * 7243 * [Intel SDM] 7244 */ 7245 static void test_host_efer(void) 7246 { 7247 test_efer(HOST_EFER, "HOST_EFER", EXI_CONTROLS, 7248 ctrl_exit_rev.clr & EXI_LOAD_EFER, 7249 EXI_HOST_64); 7250 } 7251 7252 /* 7253 * If the 'load IA32_EFER' VM-enter control is 1, bits reserved in the 7254 * IA32_EFER MSR must be 0 in the field for that register. In addition, 7255 * the values of the LMA and LME bits in the field must each be that of 7256 * the 'IA32e-mode guest' VM-exit control. 7257 */ 7258 static void test_guest_efer(void) 7259 { 7260 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) { 7261 printf("\"Load-IA32-EFER\" entry control not supported\n"); 7262 return; 7263 } 7264 7265 vmcs_write(GUEST_EFER, rdmsr(MSR_EFER)); 7266 test_efer(GUEST_EFER, "GUEST_EFER", ENT_CONTROLS, 7267 ctrl_enter_rev.clr & ENT_LOAD_EFER, 7268 ENT_GUEST_64); 7269 } 7270 7271 /* 7272 * PAT values higher than 8 are uninteresting since they're likely lumped 7273 * in with "8". We only test values above 8 one bit at a time, 7274 * in order to reduce the number of VM-Entries and keep the runtime reasonable. 7275 */ 7276 #define PAT_VAL_LIMIT 8 7277 7278 static void test_pat(u32 field, const char * field_name, u32 ctrl_field, 7279 u64 ctrl_bit) 7280 { 7281 u32 ctrl_saved = vmcs_read(ctrl_field); 7282 u64 pat_saved = vmcs_read(field); 7283 u64 i, val; 7284 u32 j; 7285 int error; 7286 7287 vmcs_clear_bits(ctrl_field, ctrl_bit); 7288 7289 for (i = 0; i < 256; i = (i < PAT_VAL_LIMIT) ? i + 1 : i * 2) { 7290 /* Test PAT0..PAT7 fields */ 7291 for (j = 0; j < (i ? 8 : 1); j++) { 7292 val = i << j * 8; 7293 vmcs_write(field, val); 7294 if (field == HOST_PAT) { 7295 report_prefix_pushf("%s %lx", field_name, val); 7296 test_vmx_vmlaunch(0); 7297 report_prefix_pop(); 7298 7299 } else { // GUEST_PAT 7300 test_guest_state("ENT_LOAD_PAT enabled", false, 7301 val, "GUEST_PAT"); 7302 } 7303 } 7304 } 7305 7306 vmcs_set_bits(ctrl_field, ctrl_bit); 7307 for (i = 0; i < 256; i = (i < PAT_VAL_LIMIT) ? i + 1 : i * 2) { 7308 /* Test PAT0..PAT7 fields */ 7309 for (j = 0; j < (i ? 8 : 1); j++) { 7310 val = i << j * 8; 7311 vmcs_write(field, val); 7312 7313 if (field == HOST_PAT) { 7314 report_prefix_pushf("%s %lx", field_name, val); 7315 if (i == 0x2 || i == 0x3 || i >= 0x8) 7316 error = 7317 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD; 7318 else 7319 error = 0; 7320 7321 test_vmx_vmlaunch(error); 7322 report_prefix_pop(); 7323 7324 } else { // GUEST_PAT 7325 error = (i == 0x2 || i == 0x3 || i >= 0x8); 7326 test_guest_state("ENT_LOAD_PAT enabled", !!error, 7327 val, "GUEST_PAT"); 7328 } 7329 7330 } 7331 } 7332 7333 vmcs_write(ctrl_field, ctrl_saved); 7334 vmcs_write(field, pat_saved); 7335 } 7336 7337 /* 7338 * If the "load IA32_PAT" VM-exit control is 1, the value of the field 7339 * for the IA32_PAT MSR must be one that could be written by WRMSR 7340 * without fault at CPL 0. Specifically, each of the 8 bytes in the 7341 * field must have one of the values 0 (UC), 1 (WC), 4 (WT), 5 (WP), 7342 * 6 (WB), or 7 (UC-). 7343 * 7344 * [Intel SDM] 7345 */ 7346 static void test_load_host_pat(void) 7347 { 7348 /* 7349 * "load IA32_PAT" VM-exit control 7350 */ 7351 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) { 7352 printf("\"Load-IA32-PAT\" exit control not supported\n"); 7353 return; 7354 } 7355 7356 test_pat(HOST_PAT, "HOST_PAT", EXI_CONTROLS, EXI_LOAD_PAT); 7357 } 7358 7359 union cpuidA_eax { 7360 struct { 7361 unsigned int version_id:8; 7362 unsigned int num_counters_gp:8; 7363 unsigned int bit_width:8; 7364 unsigned int mask_length:8; 7365 } split; 7366 unsigned int full; 7367 }; 7368 7369 union cpuidA_edx { 7370 struct { 7371 unsigned int num_counters_fixed:5; 7372 unsigned int bit_width_fixed:8; 7373 unsigned int reserved:9; 7374 } split; 7375 unsigned int full; 7376 }; 7377 7378 static bool valid_pgc(u64 val) 7379 { 7380 struct cpuid id; 7381 union cpuidA_eax eax; 7382 union cpuidA_edx edx; 7383 u64 mask; 7384 7385 id = cpuid(0xA); 7386 eax.full = id.a; 7387 edx.full = id.d; 7388 mask = ~(((1ull << eax.split.num_counters_gp) - 1) | 7389 (((1ull << edx.split.num_counters_fixed) - 1) << 32)); 7390 7391 return !(val & mask); 7392 } 7393 7394 static void test_pgc_vmlaunch(u32 xerror, u32 xreason, bool xfail, bool host) 7395 { 7396 u32 inst_err; 7397 u64 obs; 7398 bool success; 7399 struct vmx_state_area_test_data *data = &vmx_state_area_test_data; 7400 7401 if (host) { 7402 success = vmlaunch_succeeds(); 7403 obs = rdmsr(data->msr); 7404 if (!success) { 7405 inst_err = vmcs_read(VMX_INST_ERROR); 7406 report(xerror == inst_err, "vmlaunch failed, " 7407 "VMX Inst Error is %d (expected %d)", 7408 inst_err, xerror); 7409 } else { 7410 report(!data->enabled || data->exp == obs, 7411 "Host state is 0x%lx (expected 0x%lx)", 7412 obs, data->exp); 7413 report(success != xfail, "vmlaunch succeeded"); 7414 } 7415 } else { 7416 test_guest_state("load GUEST_PERF_GLOBAL_CTRL", xfail, 7417 GUEST_PERF_GLOBAL_CTRL, 7418 "GUEST_PERF_GLOBAL_CTRL"); 7419 } 7420 } 7421 7422 /* 7423 * test_load_perf_global_ctrl is a generic function for testing the 7424 * "load IA32_PERF_GLOBAL_CTRL" VM-{Entry,Exit} controls. This test function 7425 * tests the provided ctrl_val when disabled and enabled. 7426 * 7427 * @nr: VMCS field number corresponding to the host/guest state field 7428 * @name: Name of the above VMCS field for printing in test report 7429 * @ctrl_nr: VMCS field number corresponding to the VM-{Entry,Exit} control 7430 * @ctrl_val: Bit to set on the ctrl_field 7431 */ 7432 static void test_perf_global_ctrl(u32 nr, const char *name, u32 ctrl_nr, 7433 const char *ctrl_name, u64 ctrl_val) 7434 { 7435 u64 ctrl_saved = vmcs_read(ctrl_nr); 7436 u64 pgc_saved = vmcs_read(nr); 7437 u64 i, val; 7438 bool host = nr == HOST_PERF_GLOBAL_CTRL; 7439 struct vmx_state_area_test_data *data = &vmx_state_area_test_data; 7440 7441 data->msr = MSR_CORE_PERF_GLOBAL_CTRL; 7442 msr_bmp_init(); 7443 vmcs_write(ctrl_nr, ctrl_saved & ~ctrl_val); 7444 data->enabled = false; 7445 report_prefix_pushf("\"load IA32_PERF_GLOBAL_CTRL\"=0 on %s", 7446 ctrl_name); 7447 7448 for (i = 0; i < 64; i++) { 7449 val = 1ull << i; 7450 vmcs_write(nr, val); 7451 report_prefix_pushf("%s = 0x%lx", name, val); 7452 test_pgc_vmlaunch(0, VMX_VMCALL, false, host); 7453 report_prefix_pop(); 7454 } 7455 report_prefix_pop(); 7456 7457 vmcs_write(ctrl_nr, ctrl_saved | ctrl_val); 7458 data->enabled = true; 7459 report_prefix_pushf("\"load IA32_PERF_GLOBAL_CTRL\"=1 on %s", 7460 ctrl_name); 7461 for (i = 0; i < 64; i++) { 7462 val = 1ull << i; 7463 data->exp = val; 7464 vmcs_write(nr, val); 7465 report_prefix_pushf("%s = 0x%lx", name, val); 7466 if (valid_pgc(val)) { 7467 test_pgc_vmlaunch(0, VMX_VMCALL, false, host); 7468 } else { 7469 if (host) 7470 test_pgc_vmlaunch( 7471 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, 7472 0, 7473 true, 7474 host); 7475 else 7476 test_pgc_vmlaunch( 7477 0, 7478 VMX_ENTRY_FAILURE | VMX_FAIL_STATE, 7479 true, 7480 host); 7481 } 7482 report_prefix_pop(); 7483 } 7484 7485 data->enabled = false; 7486 report_prefix_pop(); 7487 vmcs_write(ctrl_nr, ctrl_saved); 7488 vmcs_write(nr, pgc_saved); 7489 } 7490 7491 static void test_load_host_perf_global_ctrl(void) 7492 { 7493 if (!(ctrl_exit_rev.clr & EXI_LOAD_PERF)) { 7494 printf("\"load IA32_PERF_GLOBAL_CTRL\" exit control not supported\n"); 7495 return; 7496 } 7497 7498 test_perf_global_ctrl(HOST_PERF_GLOBAL_CTRL, "HOST_PERF_GLOBAL_CTRL", 7499 EXI_CONTROLS, "EXI_CONTROLS", EXI_LOAD_PERF); 7500 } 7501 7502 7503 static void test_load_guest_perf_global_ctrl(void) 7504 { 7505 if (!(ctrl_enter_rev.clr & ENT_LOAD_PERF)) { 7506 printf("\"load IA32_PERF_GLOBAL_CTRL\" entry control not supported\n"); 7507 return; 7508 } 7509 7510 test_perf_global_ctrl(GUEST_PERF_GLOBAL_CTRL, "GUEST_PERF_GLOBAL_CTRL", 7511 ENT_CONTROLS, "ENT_CONTROLS", ENT_LOAD_PERF); 7512 } 7513 7514 7515 /* 7516 * test_vmcs_field - test a value for the given VMCS field 7517 * @field: VMCS field 7518 * @field_name: string name of VMCS field 7519 * @bit_start: starting bit 7520 * @bit_end: ending bit 7521 * @val: value that the bit range must or must not contain 7522 * @valid_val: whether value given in 'val' must be valid or not 7523 * @error: expected VMCS error when vmentry fails for an invalid value 7524 */ 7525 static void test_vmcs_field(u64 field, const char *field_name, u32 bit_start, 7526 u32 bit_end, u64 val, bool valid_val, u32 error) 7527 { 7528 u64 field_saved = vmcs_read(field); 7529 u32 i; 7530 u64 tmp; 7531 u32 bit_on; 7532 u64 mask = ~0ull; 7533 7534 mask = (mask >> bit_end) << bit_end; 7535 mask = mask | ((1 << bit_start) - 1); 7536 tmp = (field_saved & mask) | (val << bit_start); 7537 7538 vmcs_write(field, tmp); 7539 report_prefix_pushf("%s %lx", field_name, tmp); 7540 if (valid_val) 7541 test_vmx_vmlaunch(0); 7542 else 7543 test_vmx_vmlaunch(error); 7544 report_prefix_pop(); 7545 7546 for (i = bit_start; i <= bit_end; i = i + 2) { 7547 bit_on = ((1ull < i) & (val << bit_start)) ? 0 : 1; 7548 if (bit_on) 7549 tmp = field_saved | (1ull << i); 7550 else 7551 tmp = field_saved & ~(1ull << i); 7552 vmcs_write(field, tmp); 7553 report_prefix_pushf("%s %lx", field_name, tmp); 7554 if (valid_val) 7555 test_vmx_vmlaunch(error); 7556 else 7557 test_vmx_vmlaunch(0); 7558 report_prefix_pop(); 7559 } 7560 7561 vmcs_write(field, field_saved); 7562 } 7563 7564 static void test_canonical(u64 field, const char * field_name, bool host) 7565 { 7566 u64 addr_saved = vmcs_read(field); 7567 7568 /* 7569 * Use the existing value if possible. Writing a random canonical 7570 * value is not an option as doing so would corrupt the field being 7571 * tested and likely hose the test. 7572 */ 7573 if (is_canonical(addr_saved)) { 7574 if (host) { 7575 report_prefix_pushf("%s %lx", field_name, addr_saved); 7576 test_vmx_vmlaunch(0); 7577 report_prefix_pop(); 7578 } else { 7579 test_guest_state("Test canonical address", false, 7580 addr_saved, field_name); 7581 } 7582 } 7583 7584 vmcs_write(field, NONCANONICAL); 7585 7586 if (host) { 7587 report_prefix_pushf("%s %llx", field_name, NONCANONICAL); 7588 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7589 report_prefix_pop(); 7590 } else { 7591 test_guest_state("Test non-canonical address", true, 7592 NONCANONICAL, field_name); 7593 } 7594 7595 vmcs_write(field, addr_saved); 7596 } 7597 7598 #define TEST_RPL_TI_FLAGS(reg, name) \ 7599 test_vmcs_field(reg, name, 0, 2, 0x0, true, \ 7600 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7601 7602 #define TEST_CS_TR_FLAGS(reg, name) \ 7603 test_vmcs_field(reg, name, 3, 15, 0x0000, false, \ 7604 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7605 7606 /* 7607 * 1. In the selector field for each of CS, SS, DS, ES, FS, GS and TR, the 7608 * RPL (bits 1:0) and the TI flag (bit 2) must be 0. 7609 * 2. The selector fields for CS and TR cannot be 0000H. 7610 * 3. The selector field for SS cannot be 0000H if the "host address-space 7611 * size" VM-exit control is 0. 7612 * 4. On processors that support Intel 64 architecture, the base-address 7613 * fields for FS, GS and TR must contain canonical addresses. 7614 */ 7615 static void test_host_segment_regs(void) 7616 { 7617 u16 selector_saved; 7618 7619 /* 7620 * Test RPL and TI flags 7621 */ 7622 TEST_RPL_TI_FLAGS(HOST_SEL_CS, "HOST_SEL_CS"); 7623 TEST_RPL_TI_FLAGS(HOST_SEL_SS, "HOST_SEL_SS"); 7624 TEST_RPL_TI_FLAGS(HOST_SEL_DS, "HOST_SEL_DS"); 7625 TEST_RPL_TI_FLAGS(HOST_SEL_ES, "HOST_SEL_ES"); 7626 TEST_RPL_TI_FLAGS(HOST_SEL_FS, "HOST_SEL_FS"); 7627 TEST_RPL_TI_FLAGS(HOST_SEL_GS, "HOST_SEL_GS"); 7628 TEST_RPL_TI_FLAGS(HOST_SEL_TR, "HOST_SEL_TR"); 7629 7630 /* 7631 * Test that CS and TR fields can not be 0x0000 7632 */ 7633 TEST_CS_TR_FLAGS(HOST_SEL_CS, "HOST_SEL_CS"); 7634 TEST_CS_TR_FLAGS(HOST_SEL_TR, "HOST_SEL_TR"); 7635 7636 /* 7637 * SS field can not be 0x0000 if "host address-space size" VM-exit 7638 * control is 0 7639 */ 7640 selector_saved = vmcs_read(HOST_SEL_SS); 7641 vmcs_write(HOST_SEL_SS, 0); 7642 report_prefix_pushf("HOST_SEL_SS 0"); 7643 if (vmcs_read(EXI_CONTROLS) & EXI_HOST_64) { 7644 test_vmx_vmlaunch(0); 7645 } else { 7646 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7647 } 7648 report_prefix_pop(); 7649 7650 vmcs_write(HOST_SEL_SS, selector_saved); 7651 7652 /* 7653 * Base address for FS, GS and TR must be canonical 7654 */ 7655 test_canonical(HOST_BASE_FS, "HOST_BASE_FS", true); 7656 test_canonical(HOST_BASE_GS, "HOST_BASE_GS", true); 7657 test_canonical(HOST_BASE_TR, "HOST_BASE_TR", true); 7658 } 7659 7660 /* 7661 * On processors that support Intel 64 architecture, the base-address 7662 * fields for GDTR and IDTR must contain canonical addresses. 7663 */ 7664 static void test_host_desc_tables(void) 7665 { 7666 test_canonical(HOST_BASE_GDTR, "HOST_BASE_GDTR", true); 7667 test_canonical(HOST_BASE_IDTR, "HOST_BASE_IDTR", true); 7668 } 7669 7670 /* 7671 * If the "host address-space size" VM-exit control is 0, the following must 7672 * hold: 7673 * - The "IA-32e mode guest" VM-entry control is 0. 7674 * - Bit 17 of the CR4 field (corresponding to CR4.PCIDE) is 0. 7675 * - Bits 63:32 in the RIP field are 0. 7676 * 7677 * If the "host address-space size" VM-exit control is 1, the following must 7678 * hold: 7679 * - Bit 5 of the CR4 field (corresponding to CR4.PAE) is 1. 7680 * - The RIP field contains a canonical address. 7681 * 7682 */ 7683 static void test_host_addr_size(void) 7684 { 7685 u64 cr4_saved = vmcs_read(HOST_CR4); 7686 u64 rip_saved = vmcs_read(HOST_RIP); 7687 u64 entry_ctrl_saved = vmcs_read(ENT_CONTROLS); 7688 int i; 7689 u64 tmp; 7690 7691 if (vmcs_read(EXI_CONTROLS) & EXI_HOST_64) { 7692 vmcs_write(ENT_CONTROLS, entry_ctrl_saved | ENT_GUEST_64); 7693 report_prefix_pushf("\"IA-32e mode guest\" enabled"); 7694 test_vmx_vmlaunch(0); 7695 report_prefix_pop(); 7696 7697 vmcs_write(HOST_CR4, cr4_saved | X86_CR4_PCIDE); 7698 report_prefix_pushf("\"CR4.PCIDE\" set"); 7699 test_vmx_vmlaunch(0); 7700 report_prefix_pop(); 7701 7702 for (i = 32; i <= 63; i = i + 4) { 7703 tmp = rip_saved | 1ull << i; 7704 vmcs_write(HOST_RIP, tmp); 7705 report_prefix_pushf("HOST_RIP %lx", tmp); 7706 test_vmx_vmlaunch(0); 7707 report_prefix_pop(); 7708 } 7709 7710 if (cr4_saved & X86_CR4_PAE) { 7711 vmcs_write(HOST_CR4, cr4_saved & ~X86_CR4_PAE); 7712 report_prefix_pushf("\"CR4.PAE\" unset"); 7713 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7714 } else { 7715 report_prefix_pushf("\"CR4.PAE\" set"); 7716 test_vmx_vmlaunch(0); 7717 } 7718 report_prefix_pop(); 7719 7720 vmcs_write(HOST_RIP, NONCANONICAL); 7721 report_prefix_pushf("HOST_RIP %llx", NONCANONICAL); 7722 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7723 report_prefix_pop(); 7724 7725 vmcs_write(ENT_CONTROLS, entry_ctrl_saved | ENT_GUEST_64); 7726 vmcs_write(HOST_RIP, rip_saved); 7727 vmcs_write(HOST_CR4, cr4_saved); 7728 7729 /* Restore host's active RIP and CR4 values. */ 7730 report_prefix_pushf("restore host state"); 7731 test_vmx_vmlaunch(0); 7732 report_prefix_pop(); 7733 } 7734 } 7735 7736 /* 7737 * Check that the virtual CPU checks the VMX Host State Area as 7738 * documented in the Intel SDM. 7739 */ 7740 static void vmx_host_state_area_test(void) 7741 { 7742 /* 7743 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 7744 * fail due to invalid guest state, should we make it that 7745 * far. 7746 */ 7747 vmcs_write(GUEST_RFLAGS, 0); 7748 7749 test_host_ctl_regs(); 7750 7751 test_canonical(HOST_SYSENTER_ESP, "HOST_SYSENTER_ESP", true); 7752 test_canonical(HOST_SYSENTER_EIP, "HOST_SYSENTER_EIP", true); 7753 7754 test_host_efer(); 7755 test_load_host_pat(); 7756 test_host_segment_regs(); 7757 test_host_desc_tables(); 7758 test_host_addr_size(); 7759 test_load_host_perf_global_ctrl(); 7760 } 7761 7762 /* 7763 * If the "load debug controls" VM-entry control is 1, bits 63:32 in 7764 * the DR7 field must be 0. 7765 * 7766 * [Intel SDM] 7767 */ 7768 static void test_guest_dr7(void) 7769 { 7770 u32 ent_saved = vmcs_read(ENT_CONTROLS); 7771 u64 dr7_saved = vmcs_read(GUEST_DR7); 7772 u64 val; 7773 int i; 7774 7775 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS) { 7776 vmcs_clear_bits(ENT_CONTROLS, ENT_LOAD_DBGCTLS); 7777 for (i = 0; i < 64; i++) { 7778 val = 1ull << i; 7779 vmcs_write(GUEST_DR7, val); 7780 test_guest_state("ENT_LOAD_DBGCTLS disabled", false, 7781 val, "GUEST_DR7"); 7782 } 7783 } 7784 if (ctrl_enter_rev.clr & ENT_LOAD_DBGCTLS) { 7785 vmcs_set_bits(ENT_CONTROLS, ENT_LOAD_DBGCTLS); 7786 for (i = 0; i < 64; i++) { 7787 val = 1ull << i; 7788 vmcs_write(GUEST_DR7, val); 7789 test_guest_state("ENT_LOAD_DBGCTLS enabled", i >= 32, 7790 val, "GUEST_DR7"); 7791 } 7792 } 7793 vmcs_write(GUEST_DR7, dr7_saved); 7794 vmcs_write(ENT_CONTROLS, ent_saved); 7795 } 7796 7797 /* 7798 * If the "load IA32_PAT" VM-entry control is 1, the value of the field 7799 * for the IA32_PAT MSR must be one that could be written by WRMSR 7800 * without fault at CPL 0. Specifically, each of the 8 bytes in the 7801 * field must have one of the values 0 (UC), 1 (WC), 4 (WT), 5 (WP), 7802 * 6 (WB), or 7 (UC-). 7803 * 7804 * [Intel SDM] 7805 */ 7806 static void test_load_guest_pat(void) 7807 { 7808 /* 7809 * "load IA32_PAT" VM-entry control 7810 */ 7811 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 7812 printf("\"Load-IA32-PAT\" entry control not supported\n"); 7813 return; 7814 } 7815 7816 test_pat(GUEST_PAT, "GUEST_PAT", ENT_CONTROLS, ENT_LOAD_PAT); 7817 } 7818 7819 #define MSR_IA32_BNDCFGS_RSVD_MASK 0x00000ffc 7820 7821 /* 7822 * If the "load IA32_BNDCFGS" VM-entry control is 1, the following 7823 * checks are performed on the field for the IA32_BNDCFGS MSR: 7824 * 7825 * - Bits reserved in the IA32_BNDCFGS MSR must be 0. 7826 * - The linear address in bits 63:12 must be canonical. 7827 * 7828 * [Intel SDM] 7829 */ 7830 static void test_load_guest_bndcfgs(void) 7831 { 7832 u64 bndcfgs_saved = vmcs_read(GUEST_BNDCFGS); 7833 u64 bndcfgs; 7834 7835 if (!(ctrl_enter_rev.clr & ENT_LOAD_BNDCFGS)) { 7836 printf("\"Load-IA32-BNDCFGS\" entry control not supported\n"); 7837 return; 7838 } 7839 7840 vmcs_clear_bits(ENT_CONTROLS, ENT_LOAD_BNDCFGS); 7841 7842 vmcs_write(GUEST_BNDCFGS, NONCANONICAL); 7843 test_guest_state("ENT_LOAD_BNDCFGS disabled", false, 7844 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7845 bndcfgs = bndcfgs_saved | MSR_IA32_BNDCFGS_RSVD_MASK; 7846 vmcs_write(GUEST_BNDCFGS, bndcfgs); 7847 test_guest_state("ENT_LOAD_BNDCFGS disabled", false, 7848 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7849 7850 vmcs_set_bits(ENT_CONTROLS, ENT_LOAD_BNDCFGS); 7851 7852 vmcs_write(GUEST_BNDCFGS, NONCANONICAL); 7853 test_guest_state("ENT_LOAD_BNDCFGS enabled", true, 7854 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7855 bndcfgs = bndcfgs_saved | MSR_IA32_BNDCFGS_RSVD_MASK; 7856 vmcs_write(GUEST_BNDCFGS, bndcfgs); 7857 test_guest_state("ENT_LOAD_BNDCFGS enabled", true, 7858 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7859 7860 vmcs_write(GUEST_BNDCFGS, bndcfgs_saved); 7861 } 7862 7863 #define GUEST_SEG_UNUSABLE_MASK (1u << 16) 7864 #define GUEST_SEG_SEL_TI_MASK (1u << 2) 7865 7866 7867 #define TEST_SEGMENT_SEL(test, xfail, sel, val) \ 7868 do { \ 7869 vmcs_write(sel, val); \ 7870 test_guest_state(test " segment", xfail, val, xstr(sel)); \ 7871 } while (0) 7872 7873 #define TEST_INVALID_SEG_SEL(sel, val) \ 7874 TEST_SEGMENT_SEL("Invalid: " xstr(val), true, sel, val); 7875 7876 #define TEST_VALID_SEG_SEL(sel, val) \ 7877 TEST_SEGMENT_SEL("Valid: " xstr(val), false, sel, val); 7878 7879 /* 7880 * The following checks are done on the Selector field of the Guest Segment 7881 * Registers: 7882 * - TR. The TI flag (bit 2) must be 0. 7883 * - LDTR. If LDTR is usable, the TI flag (bit 2) must be 0. 7884 * - SS. If the guest will not be virtual-8086 and the "unrestricted 7885 * guest" VM-execution control is 0, the RPL (bits 1:0) must equal 7886 * the RPL of the selector field for CS. 7887 * 7888 * [Intel SDM] 7889 */ 7890 static void test_guest_segment_sel_fields(void) 7891 { 7892 u16 sel_saved; 7893 u32 ar_saved; 7894 u32 cpu_ctrl0_saved; 7895 u32 cpu_ctrl1_saved; 7896 u16 cs_rpl_bits; 7897 7898 /* 7899 * Test for GUEST_SEL_TR 7900 */ 7901 sel_saved = vmcs_read(GUEST_SEL_TR); 7902 TEST_INVALID_SEG_SEL(GUEST_SEL_TR, sel_saved | GUEST_SEG_SEL_TI_MASK); 7903 vmcs_write(GUEST_SEL_TR, sel_saved); 7904 7905 /* 7906 * Test for GUEST_SEL_LDTR 7907 */ 7908 sel_saved = vmcs_read(GUEST_SEL_LDTR); 7909 ar_saved = vmcs_read(GUEST_AR_LDTR); 7910 /* LDTR is set unusable */ 7911 vmcs_write(GUEST_AR_LDTR, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7912 TEST_VALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved | GUEST_SEG_SEL_TI_MASK); 7913 TEST_VALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved & ~GUEST_SEG_SEL_TI_MASK); 7914 /* LDTR is set usable */ 7915 vmcs_write(GUEST_AR_LDTR, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7916 TEST_INVALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved | GUEST_SEG_SEL_TI_MASK); 7917 7918 TEST_VALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved & ~GUEST_SEG_SEL_TI_MASK); 7919 7920 vmcs_write(GUEST_AR_LDTR, ar_saved); 7921 vmcs_write(GUEST_SEL_LDTR, sel_saved); 7922 7923 /* 7924 * Test for GUEST_SEL_SS 7925 */ 7926 cpu_ctrl0_saved = vmcs_read(CPU_EXEC_CTRL0); 7927 cpu_ctrl1_saved = vmcs_read(CPU_EXEC_CTRL1); 7928 ar_saved = vmcs_read(GUEST_AR_SS); 7929 /* Turn off "unrestricted guest" vm-execution control */ 7930 vmcs_write(CPU_EXEC_CTRL1, cpu_ctrl1_saved & ~CPU_URG); 7931 cs_rpl_bits = vmcs_read(GUEST_SEL_CS) & 0x3; 7932 sel_saved = vmcs_read(GUEST_SEL_SS); 7933 TEST_INVALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 7934 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 7935 /* Make SS usable if it's unusable or vice-versa */ 7936 if (ar_saved & GUEST_SEG_UNUSABLE_MASK) 7937 vmcs_write(GUEST_AR_SS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7938 else 7939 vmcs_write(GUEST_AR_SS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7940 TEST_INVALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 7941 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 7942 7943 /* Need a valid EPTP as the passing case fully enters the guest. */ 7944 if (enable_unrestricted_guest(true)) 7945 goto skip_ss_tests; 7946 7947 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 7948 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 7949 7950 /* Make SS usable if it's unusable or vice-versa */ 7951 if (vmcs_read(GUEST_AR_SS) & GUEST_SEG_UNUSABLE_MASK) 7952 vmcs_write(GUEST_AR_SS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7953 else 7954 vmcs_write(GUEST_AR_SS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7955 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 7956 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 7957 skip_ss_tests: 7958 7959 vmcs_write(GUEST_AR_SS, ar_saved); 7960 vmcs_write(GUEST_SEL_SS, sel_saved); 7961 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrl0_saved); 7962 vmcs_write(CPU_EXEC_CTRL1, cpu_ctrl1_saved); 7963 } 7964 7965 #define TEST_SEGMENT_BASE_ADDR_UPPER_BITS(xfail, seg_base) \ 7966 do { \ 7967 addr_saved = vmcs_read(seg_base); \ 7968 for (i = 32; i < 63; i = i + 4) { \ 7969 addr = addr_saved | 1ull << i; \ 7970 vmcs_write(seg_base, addr); \ 7971 test_guest_state("seg.BASE[63:32] != 0, usable = " xstr(xfail), \ 7972 xfail, addr, xstr(seg_base)); \ 7973 } \ 7974 vmcs_write(seg_base, addr_saved); \ 7975 } while (0) 7976 7977 #define TEST_SEGMENT_BASE_ADDR_CANONICAL(xfail, seg_base) \ 7978 do { \ 7979 addr_saved = vmcs_read(seg_base); \ 7980 vmcs_write(seg_base, NONCANONICAL); \ 7981 test_guest_state("seg.BASE non-canonical, usable = " xstr(xfail), \ 7982 xfail, NONCANONICAL, xstr(seg_base)); \ 7983 vmcs_write(seg_base, addr_saved); \ 7984 } while (0) 7985 7986 /* 7987 * The following checks are done on the Base Address field of the Guest 7988 * Segment Registers on processors that support Intel 64 architecture: 7989 * - TR, FS, GS : The address must be canonical. 7990 * - LDTR : If LDTR is usable, the address must be canonical. 7991 * - CS : Bits 63:32 of the address must be zero. 7992 * - SS, DS, ES : If the register is usable, bits 63:32 of the address 7993 * must be zero. 7994 * 7995 * [Intel SDM] 7996 */ 7997 static void test_guest_segment_base_addr_fields(void) 7998 { 7999 u64 addr_saved; 8000 u64 addr; 8001 u32 ar_saved; 8002 int i; 8003 8004 /* 8005 * The address of TR, FS, GS and LDTR must be canonical. 8006 */ 8007 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_TR); 8008 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_FS); 8009 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_GS); 8010 ar_saved = vmcs_read(GUEST_AR_LDTR); 8011 /* Make LDTR unusable */ 8012 vmcs_write(GUEST_AR_LDTR, ar_saved | GUEST_SEG_UNUSABLE_MASK); 8013 TEST_SEGMENT_BASE_ADDR_CANONICAL(false, GUEST_BASE_LDTR); 8014 /* Make LDTR usable */ 8015 vmcs_write(GUEST_AR_LDTR, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 8016 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_LDTR); 8017 8018 vmcs_write(GUEST_AR_LDTR, ar_saved); 8019 8020 /* 8021 * Bits 63:32 in CS, SS, DS and ES base address must be zero 8022 */ 8023 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_CS); 8024 ar_saved = vmcs_read(GUEST_AR_SS); 8025 /* Make SS unusable */ 8026 vmcs_write(GUEST_AR_SS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 8027 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(false, GUEST_BASE_SS); 8028 /* Make SS usable */ 8029 vmcs_write(GUEST_AR_SS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 8030 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_SS); 8031 vmcs_write(GUEST_AR_SS, ar_saved); 8032 8033 ar_saved = vmcs_read(GUEST_AR_DS); 8034 /* Make DS unusable */ 8035 vmcs_write(GUEST_AR_DS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 8036 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(false, GUEST_BASE_DS); 8037 /* Make DS usable */ 8038 vmcs_write(GUEST_AR_DS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 8039 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_DS); 8040 vmcs_write(GUEST_AR_DS, ar_saved); 8041 8042 ar_saved = vmcs_read(GUEST_AR_ES); 8043 /* Make ES unusable */ 8044 vmcs_write(GUEST_AR_ES, ar_saved | GUEST_SEG_UNUSABLE_MASK); 8045 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(false, GUEST_BASE_ES); 8046 /* Make ES usable */ 8047 vmcs_write(GUEST_AR_ES, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 8048 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_ES); 8049 vmcs_write(GUEST_AR_ES, ar_saved); 8050 } 8051 8052 /* 8053 * Check that the virtual CPU checks the VMX Guest State Area as 8054 * documented in the Intel SDM. 8055 */ 8056 static void vmx_guest_state_area_test(void) 8057 { 8058 vmx_set_test_stage(1); 8059 test_set_guest(guest_state_test_main); 8060 8061 /* 8062 * The IA32_SYSENTER_ESP field and the IA32_SYSENTER_EIP field 8063 * must each contain a canonical address. 8064 */ 8065 test_canonical(GUEST_SYSENTER_ESP, "GUEST_SYSENTER_ESP", false); 8066 test_canonical(GUEST_SYSENTER_EIP, "GUEST_SYSENTER_EIP", false); 8067 8068 test_guest_dr7(); 8069 test_load_guest_pat(); 8070 test_guest_efer(); 8071 test_load_guest_perf_global_ctrl(); 8072 test_load_guest_bndcfgs(); 8073 8074 test_guest_segment_sel_fields(); 8075 test_guest_segment_base_addr_fields(); 8076 8077 test_canonical(GUEST_BASE_GDTR, "GUEST_BASE_GDTR", false); 8078 test_canonical(GUEST_BASE_IDTR, "GUEST_BASE_IDTR", false); 8079 8080 u32 guest_desc_limit_saved = vmcs_read(GUEST_LIMIT_GDTR); 8081 int i; 8082 for (i = 16; i <= 31; i++) { 8083 u32 tmp = guest_desc_limit_saved | (1ull << i); 8084 vmcs_write(GUEST_LIMIT_GDTR, tmp); 8085 test_guest_state("GDT.limit > 0xffff", true, tmp, "GUEST_LIMIT_GDTR"); 8086 } 8087 vmcs_write(GUEST_LIMIT_GDTR, guest_desc_limit_saved); 8088 8089 guest_desc_limit_saved = vmcs_read(GUEST_LIMIT_IDTR); 8090 for (i = 16; i <= 31; i++) { 8091 u32 tmp = guest_desc_limit_saved | (1ull << i); 8092 vmcs_write(GUEST_LIMIT_IDTR, tmp); 8093 test_guest_state("IDT.limit > 0xffff", true, tmp, "GUEST_LIMIT_IDTR"); 8094 } 8095 vmcs_write(GUEST_LIMIT_IDTR, guest_desc_limit_saved); 8096 8097 /* 8098 * Let the guest finish execution 8099 */ 8100 vmx_set_test_stage(2); 8101 enter_guest(); 8102 } 8103 8104 extern void unrestricted_guest_main(void); 8105 asm (".code32\n" 8106 "unrestricted_guest_main:\n" 8107 "vmcall\n" 8108 "nop\n" 8109 "mov $1, %edi\n" 8110 "call hypercall\n" 8111 ".code64\n"); 8112 8113 static void setup_unrestricted_guest(void) 8114 { 8115 vmcs_write(GUEST_CR0, vmcs_read(GUEST_CR0) & ~(X86_CR0_PG)); 8116 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) & ~ENT_GUEST_64); 8117 vmcs_write(GUEST_EFER, vmcs_read(GUEST_EFER) & ~EFER_LMA); 8118 vmcs_write(GUEST_RIP, virt_to_phys(unrestricted_guest_main)); 8119 } 8120 8121 static void unsetup_unrestricted_guest(void) 8122 { 8123 vmcs_write(GUEST_CR0, vmcs_read(GUEST_CR0) | X86_CR0_PG); 8124 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) | ENT_GUEST_64); 8125 vmcs_write(GUEST_EFER, vmcs_read(GUEST_EFER) | EFER_LMA); 8126 vmcs_write(GUEST_RIP, (u64) phys_to_virt(vmcs_read(GUEST_RIP))); 8127 vmcs_write(GUEST_RSP, (u64) phys_to_virt(vmcs_read(GUEST_RSP))); 8128 } 8129 8130 /* 8131 * If "unrestricted guest" secondary VM-execution control is set, guests 8132 * can run in unpaged protected mode. 8133 */ 8134 static void vmentry_unrestricted_guest_test(void) 8135 { 8136 if (enable_unrestricted_guest(true)) { 8137 report_skip("Unrestricted guest not supported"); 8138 return; 8139 } 8140 8141 test_set_guest(unrestricted_guest_main); 8142 setup_unrestricted_guest(); 8143 test_guest_state("Unrestricted guest test", false, CPU_URG, "CPU_URG"); 8144 8145 /* 8146 * Let the guest finish execution as a regular guest 8147 */ 8148 unsetup_unrestricted_guest(); 8149 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) & ~CPU_URG); 8150 enter_guest(); 8151 } 8152 8153 static bool valid_vmcs_for_vmentry(void) 8154 { 8155 struct vmcs *current_vmcs = NULL; 8156 8157 if (vmcs_save(¤t_vmcs)) 8158 return false; 8159 8160 return current_vmcs && !current_vmcs->hdr.shadow_vmcs; 8161 } 8162 8163 static void try_vmentry_in_movss_shadow(void) 8164 { 8165 u32 vm_inst_err; 8166 u32 flags; 8167 bool early_failure = false; 8168 u32 expected_flags = X86_EFLAGS_FIXED; 8169 bool valid_vmcs = valid_vmcs_for_vmentry(); 8170 8171 expected_flags |= valid_vmcs ? X86_EFLAGS_ZF : X86_EFLAGS_CF; 8172 8173 /* 8174 * Indirectly set VM_INST_ERR to 12 ("VMREAD/VMWRITE from/to 8175 * unsupported VMCS component"). 8176 */ 8177 vmcs_write(~0u, 0); 8178 8179 __asm__ __volatile__ ("mov %[host_rsp], %%edx;" 8180 "vmwrite %%rsp, %%rdx;" 8181 "mov 0f, %%rax;" 8182 "mov %[host_rip], %%edx;" 8183 "vmwrite %%rax, %%rdx;" 8184 "mov $-1, %%ah;" 8185 "sahf;" 8186 "mov %%ss, %%ax;" 8187 "mov %%ax, %%ss;" 8188 "vmlaunch;" 8189 "mov $1, %[early_failure];" 8190 "0: lahf;" 8191 "movzbl %%ah, %[flags]" 8192 : [early_failure] "+r" (early_failure), 8193 [flags] "=&a" (flags) 8194 : [host_rsp] "i" (HOST_RSP), 8195 [host_rip] "i" (HOST_RIP) 8196 : "rdx", "cc", "memory"); 8197 vm_inst_err = vmcs_read(VMX_INST_ERROR); 8198 8199 report(early_failure, "Early VM-entry failure"); 8200 report(flags == expected_flags, "RFLAGS[8:0] is %x (actual %x)", 8201 expected_flags, flags); 8202 if (valid_vmcs) 8203 report(vm_inst_err == VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, 8204 "VM-instruction error is %d (actual %d)", 8205 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, vm_inst_err); 8206 } 8207 8208 static void vmentry_movss_shadow_test(void) 8209 { 8210 struct vmcs *orig_vmcs; 8211 8212 TEST_ASSERT(!vmcs_save(&orig_vmcs)); 8213 8214 /* 8215 * Set the launched flag on the current VMCS to verify the correct 8216 * error priority, below. 8217 */ 8218 test_set_guest(v2_null_test_guest); 8219 enter_guest(); 8220 8221 /* 8222 * With bit 1 of the guest's RFLAGS clear, VM-entry should 8223 * fail due to invalid guest state (if we make it that far). 8224 */ 8225 vmcs_write(GUEST_RFLAGS, 0); 8226 8227 /* 8228 * "VM entry with events blocked by MOV SS" takes precedence over 8229 * "VMLAUNCH with non-clear VMCS." 8230 */ 8231 report_prefix_push("valid current-VMCS"); 8232 try_vmentry_in_movss_shadow(); 8233 report_prefix_pop(); 8234 8235 /* 8236 * VMfailInvalid takes precedence over "VM entry with events 8237 * blocked by MOV SS." 8238 */ 8239 TEST_ASSERT(!vmcs_clear(orig_vmcs)); 8240 report_prefix_push("no current-VMCS"); 8241 try_vmentry_in_movss_shadow(); 8242 report_prefix_pop(); 8243 8244 TEST_ASSERT(!make_vmcs_current(orig_vmcs)); 8245 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 8246 } 8247 8248 static void vmx_ldtr_test_guest(void) 8249 { 8250 u16 ldtr = sldt(); 8251 8252 report(ldtr == NP_SEL, "Expected %x for L2 LDTR selector (got %x)", 8253 NP_SEL, ldtr); 8254 } 8255 8256 /* 8257 * Ensure that the L1 LDTR is set to 0 on VM-exit. 8258 */ 8259 static void vmx_ldtr_test(void) 8260 { 8261 const u8 ldt_ar = 0x82; /* Present LDT */ 8262 u16 sel = FIRST_SPARE_SEL; 8263 8264 /* Set up a non-zero L1 LDTR prior to VM-entry. */ 8265 set_gdt_entry(sel, 0, 0, ldt_ar, 0); 8266 lldt(sel); 8267 8268 test_set_guest(vmx_ldtr_test_guest); 8269 /* 8270 * Set up a different LDTR for L2. The actual GDT contents are 8271 * irrelevant, since we stuff the hidden descriptor state 8272 * straight into the VMCS rather than reading it from the GDT. 8273 */ 8274 vmcs_write(GUEST_SEL_LDTR, NP_SEL); 8275 vmcs_write(GUEST_AR_LDTR, ldt_ar); 8276 enter_guest(); 8277 8278 /* 8279 * VM-exit should clear LDTR (and make it unusable, but we 8280 * won't verify that here). 8281 */ 8282 sel = sldt(); 8283 report(!sel, "Expected 0 for L1 LDTR selector (got %x)", sel); 8284 } 8285 8286 static void vmx_single_vmcall_guest(void) 8287 { 8288 vmcall(); 8289 } 8290 8291 static void vmx_cr_load_test(void) 8292 { 8293 unsigned long cr3, cr4, orig_cr3, orig_cr4; 8294 u32 ctrls[2] = {0}; 8295 pgd_t *pml5; 8296 8297 orig_cr4 = read_cr4(); 8298 orig_cr3 = read_cr3(); 8299 8300 if (!this_cpu_has(X86_FEATURE_PCID)) { 8301 report_skip("PCID not detected"); 8302 return; 8303 } 8304 if (!this_cpu_has(X86_FEATURE_MCE)) { 8305 report_skip("MCE not detected"); 8306 return; 8307 } 8308 8309 TEST_ASSERT(!(orig_cr3 & X86_CR3_PCID_MASK)); 8310 8311 /* Enable PCID for L1. */ 8312 cr4 = orig_cr4 | X86_CR4_PCIDE; 8313 cr3 = orig_cr3 | 0x1; 8314 TEST_ASSERT(!write_cr4_safe(cr4)); 8315 write_cr3(cr3); 8316 8317 test_set_guest(vmx_single_vmcall_guest); 8318 vmcs_write(HOST_CR4, cr4); 8319 vmcs_write(HOST_CR3, cr3); 8320 enter_guest(); 8321 8322 /* 8323 * No exception is expected. 8324 * 8325 * NB. KVM loads the last guest write to CR4 into CR4 read 8326 * shadow. In order to trigger an exit to KVM, we can toggle a 8327 * bit that is owned by KVM. We use CR4.MCE, which shall 8328 * have no side effect because normally no guest MCE (e.g., as the 8329 * result of bad memory) would happen during this test. 8330 */ 8331 TEST_ASSERT(!write_cr4_safe(cr4 ^ X86_CR4_MCE)); 8332 8333 /* Cleanup L1 state. */ 8334 write_cr3(orig_cr3); 8335 TEST_ASSERT(!write_cr4_safe(orig_cr4)); 8336 8337 if (!this_cpu_has(X86_FEATURE_LA57)) 8338 goto done; 8339 8340 /* 8341 * Allocate a full page for PML5 to guarantee alignment, though only 8342 * the first entry needs to be filled (the test's virtual addresses 8343 * most definitely do not have any of bits 56:48 set). 8344 */ 8345 pml5 = alloc_page(); 8346 *pml5 = orig_cr3 | PT_PRESENT_MASK | PT_WRITABLE_MASK; 8347 8348 /* 8349 * Transition to/from 5-level paging in the host via VM-Exit. CR4.LA57 8350 * can't be toggled while long is active via MOV CR4, but there are no 8351 * such restrictions on VM-Exit. 8352 */ 8353 lol_5level: 8354 vmcs_write(HOST_CR4, orig_cr4 | X86_CR4_LA57); 8355 vmcs_write(HOST_CR3, virt_to_phys(pml5)); 8356 enter_guest(); 8357 8358 /* 8359 * VMREAD with a memory operand to verify KVM detects the LA57 change, 8360 * e.g. uses the correct guest root level in gva_to_gpa(). 8361 */ 8362 TEST_ASSERT(vmcs_readm(HOST_CR3) == virt_to_phys(pml5)); 8363 TEST_ASSERT(vmcs_readm(HOST_CR4) == (orig_cr4 | X86_CR4_LA57)); 8364 8365 vmcs_write(HOST_CR4, orig_cr4); 8366 vmcs_write(HOST_CR3, orig_cr3); 8367 enter_guest(); 8368 8369 TEST_ASSERT(vmcs_readm(HOST_CR3) == orig_cr3); 8370 TEST_ASSERT(vmcs_readm(HOST_CR4) == orig_cr4); 8371 8372 /* 8373 * And now do the same LA57 shenanigans with EPT enabled. KVM uses 8374 * two separate MMUs when L1 uses TDP, whereas the above shadow paging 8375 * version shares an MMU between L1 and L2. 8376 * 8377 * If the saved execution controls are non-zero then the EPT version 8378 * has already run. In that case, restore the old controls. If EPT 8379 * setup fails, e.g. EPT isn't supported, fall through and finish up. 8380 */ 8381 if (ctrls[0]) { 8382 vmcs_write(CPU_EXEC_CTRL0, ctrls[0]); 8383 vmcs_write(CPU_EXEC_CTRL1, ctrls[1]); 8384 } else if (!setup_ept(false)) { 8385 ctrls[0] = vmcs_read(CPU_EXEC_CTRL0); 8386 ctrls[1] = vmcs_read(CPU_EXEC_CTRL1); 8387 goto lol_5level; 8388 } 8389 8390 free_page(pml5); 8391 8392 done: 8393 skip_exit_vmcall(); 8394 enter_guest(); 8395 } 8396 8397 static void vmx_cr4_osxsave_test_guest(void) 8398 { 8399 write_cr4(read_cr4() & ~X86_CR4_OSXSAVE); 8400 } 8401 8402 /* 8403 * Ensure that kvm recalculates the L1 guest's CPUID.01H:ECX.OSXSAVE 8404 * after VM-exit from an L2 guest that sets CR4.OSXSAVE to a different 8405 * value than in L1. 8406 */ 8407 static void vmx_cr4_osxsave_test(void) 8408 { 8409 if (!this_cpu_has(X86_FEATURE_XSAVE)) { 8410 report_skip("XSAVE not detected"); 8411 return; 8412 } 8413 8414 if (!(read_cr4() & X86_CR4_OSXSAVE)) { 8415 unsigned long cr4 = read_cr4() | X86_CR4_OSXSAVE; 8416 8417 write_cr4(cr4); 8418 vmcs_write(GUEST_CR4, cr4); 8419 vmcs_write(HOST_CR4, cr4); 8420 } 8421 8422 TEST_ASSERT(cpuid_osxsave()); 8423 8424 test_set_guest(vmx_cr4_osxsave_test_guest); 8425 enter_guest(); 8426 8427 TEST_ASSERT(cpuid_osxsave()); 8428 } 8429 8430 static void vmx_nm_test_guest(void) 8431 { 8432 write_cr0(read_cr0() | X86_CR0_TS); 8433 asm volatile("fnop"); 8434 } 8435 8436 static void check_nm_exit(const char *test) 8437 { 8438 u32 reason = vmcs_read(EXI_REASON); 8439 u32 intr_info = vmcs_read(EXI_INTR_INFO); 8440 const u32 expected = INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 8441 NM_VECTOR; 8442 8443 report(reason == VMX_EXC_NMI && intr_info == expected, "%s", test); 8444 } 8445 8446 /* 8447 * This test checks that: 8448 * 8449 * (a) If L2 launches with CR0.TS clear, but later sets CR0.TS, then 8450 * a subsequent #NM VM-exit is reflected to L1. 8451 * 8452 * (b) If L2 launches with CR0.TS clear and CR0.EM set, then a 8453 * subsequent #NM VM-exit is reflected to L1. 8454 */ 8455 static void vmx_nm_test(void) 8456 { 8457 unsigned long cr0 = read_cr0(); 8458 8459 test_set_guest(vmx_nm_test_guest); 8460 8461 /* 8462 * L1 wants to intercept #NM exceptions encountered in L2. 8463 */ 8464 vmcs_write(EXC_BITMAP, 1 << NM_VECTOR); 8465 8466 /* 8467 * Launch L2 with CR0.TS clear, but don't claim host ownership of 8468 * any CR0 bits. L2 will set CR0.TS and then try to execute fnop, 8469 * which will raise #NM. L0 should reflect the #NM VM-exit to L1. 8470 */ 8471 vmcs_write(CR0_MASK, 0); 8472 vmcs_write(GUEST_CR0, cr0 & ~X86_CR0_TS); 8473 enter_guest(); 8474 check_nm_exit("fnop with CR0.TS set in L2 triggers #NM VM-exit to L1"); 8475 8476 /* 8477 * Re-enter L2 at the fnop instruction, with CR0.TS clear but 8478 * CR0.EM set. The fnop will still raise #NM, and L0 should 8479 * reflect the #NM VM-exit to L1. 8480 */ 8481 vmcs_write(GUEST_CR0, (cr0 & ~X86_CR0_TS) | X86_CR0_EM); 8482 enter_guest(); 8483 check_nm_exit("fnop with CR0.EM set in L2 triggers #NM VM-exit to L1"); 8484 8485 /* 8486 * Re-enter L2 at the fnop instruction, with both CR0.TS and 8487 * CR0.EM clear. There will be no #NM, and the L2 guest should 8488 * exit normally. 8489 */ 8490 vmcs_write(GUEST_CR0, cr0 & ~(X86_CR0_TS | X86_CR0_EM)); 8491 enter_guest(); 8492 } 8493 8494 bool vmx_pending_event_ipi_fired; 8495 static void vmx_pending_event_ipi_isr(isr_regs_t *regs) 8496 { 8497 vmx_pending_event_ipi_fired = true; 8498 eoi(); 8499 } 8500 8501 bool vmx_pending_event_guest_run; 8502 static void vmx_pending_event_guest(void) 8503 { 8504 vmcall(); 8505 vmx_pending_event_guest_run = true; 8506 } 8507 8508 static void vmx_pending_event_test_core(bool guest_hlt) 8509 { 8510 int ipi_vector = 0xf1; 8511 8512 vmx_pending_event_ipi_fired = false; 8513 handle_irq(ipi_vector, vmx_pending_event_ipi_isr); 8514 8515 vmx_pending_event_guest_run = false; 8516 test_set_guest(vmx_pending_event_guest); 8517 8518 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 8519 8520 enter_guest(); 8521 skip_exit_vmcall(); 8522 8523 if (guest_hlt) 8524 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8525 8526 irq_disable(); 8527 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | 8528 APIC_DM_FIXED | ipi_vector, 8529 0); 8530 8531 enter_guest(); 8532 8533 assert_exit_reason(VMX_EXTINT); 8534 report(!vmx_pending_event_guest_run, 8535 "Guest did not run before host received IPI"); 8536 8537 irq_enable(); 8538 asm volatile ("nop"); 8539 irq_disable(); 8540 report(vmx_pending_event_ipi_fired, 8541 "Got pending interrupt after IRQ enabled"); 8542 8543 if (guest_hlt) 8544 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 8545 8546 enter_guest(); 8547 report(vmx_pending_event_guest_run, 8548 "Guest finished running when no interrupt"); 8549 } 8550 8551 static void vmx_pending_event_test(void) 8552 { 8553 vmx_pending_event_test_core(false); 8554 } 8555 8556 static void vmx_pending_event_hlt_test(void) 8557 { 8558 vmx_pending_event_test_core(true); 8559 } 8560 8561 static int vmx_window_test_db_count; 8562 8563 static void vmx_window_test_db_handler(struct ex_regs *regs) 8564 { 8565 vmx_window_test_db_count++; 8566 } 8567 8568 static void vmx_nmi_window_test_guest(void) 8569 { 8570 handle_exception(DB_VECTOR, vmx_window_test_db_handler); 8571 8572 asm volatile("vmcall\n\t" 8573 "nop\n\t"); 8574 8575 handle_exception(DB_VECTOR, NULL); 8576 } 8577 8578 static void verify_nmi_window_exit(u64 rip) 8579 { 8580 u32 exit_reason = vmcs_read(EXI_REASON); 8581 8582 report(exit_reason == VMX_NMI_WINDOW, 8583 "Exit reason (%d) is 'NMI window'", exit_reason); 8584 report(vmcs_read(GUEST_RIP) == rip, "RIP (%#lx) is %#lx", 8585 vmcs_read(GUEST_RIP), rip); 8586 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 8587 } 8588 8589 static void vmx_nmi_window_test(void) 8590 { 8591 u64 nop_addr; 8592 void *db_fault_addr = get_idt_addr(&boot_idt[DB_VECTOR]); 8593 8594 if (!(ctrl_pin_rev.clr & PIN_VIRT_NMI)) { 8595 report_skip("CPU does not support the \"Virtual NMIs\" VM-execution control."); 8596 return; 8597 } 8598 8599 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 8600 report_skip("CPU does not support the \"NMI-window exiting\" VM-execution control."); 8601 return; 8602 } 8603 8604 vmx_window_test_db_count = 0; 8605 8606 report_prefix_push("NMI-window"); 8607 test_set_guest(vmx_nmi_window_test_guest); 8608 vmcs_set_bits(PIN_CONTROLS, PIN_VIRT_NMI); 8609 enter_guest(); 8610 skip_exit_vmcall(); 8611 nop_addr = vmcs_read(GUEST_RIP); 8612 8613 /* 8614 * Ask for "NMI-window exiting," and expect an immediate VM-exit. 8615 * RIP will not advance. 8616 */ 8617 report_prefix_push("active, no blocking"); 8618 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 8619 enter_guest(); 8620 verify_nmi_window_exit(nop_addr); 8621 report_prefix_pop(); 8622 8623 /* 8624 * Ask for "NMI-window exiting" in a MOV-SS shadow, and expect 8625 * a VM-exit on the next instruction after the nop. (The nop 8626 * is one byte.) 8627 */ 8628 report_prefix_push("active, blocking by MOV-SS"); 8629 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 8630 enter_guest(); 8631 verify_nmi_window_exit(nop_addr + 1); 8632 report_prefix_pop(); 8633 8634 /* 8635 * Ask for "NMI-window exiting" (with event injection), and 8636 * expect a VM-exit after the event is injected. (RIP should 8637 * be at the address specified in the IDT entry for #DB.) 8638 */ 8639 report_prefix_push("active, no blocking, injecting #DB"); 8640 vmcs_write(ENT_INTR_INFO, 8641 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 8642 enter_guest(); 8643 verify_nmi_window_exit((u64)db_fault_addr); 8644 report_prefix_pop(); 8645 8646 /* 8647 * Ask for "NMI-window exiting" with NMI blocking, and expect 8648 * a VM-exit after the next IRET (i.e. after the #DB handler 8649 * returns). So, RIP should be back at one byte past the nop. 8650 */ 8651 report_prefix_push("active, blocking by NMI"); 8652 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_NMI); 8653 enter_guest(); 8654 verify_nmi_window_exit(nop_addr + 1); 8655 report(vmx_window_test_db_count == 1, 8656 "#DB handler executed once (actual %d times)", 8657 vmx_window_test_db_count); 8658 report_prefix_pop(); 8659 8660 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 8661 report_skip("CPU does not support activity state HLT."); 8662 } else { 8663 /* 8664 * Ask for "NMI-window exiting" when entering activity 8665 * state HLT, and expect an immediate VM-exit. RIP is 8666 * still one byte past the nop. 8667 */ 8668 report_prefix_push("halted, no blocking"); 8669 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8670 enter_guest(); 8671 verify_nmi_window_exit(nop_addr + 1); 8672 report_prefix_pop(); 8673 8674 /* 8675 * Ask for "NMI-window exiting" when entering activity 8676 * state HLT (with event injection), and expect a 8677 * VM-exit after the event is injected. (RIP should be 8678 * at the address specified in the IDT entry for #DB.) 8679 */ 8680 report_prefix_push("halted, no blocking, injecting #DB"); 8681 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8682 vmcs_write(ENT_INTR_INFO, 8683 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 8684 DB_VECTOR); 8685 enter_guest(); 8686 verify_nmi_window_exit((u64)db_fault_addr); 8687 report_prefix_pop(); 8688 } 8689 8690 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 8691 enter_guest(); 8692 report_prefix_pop(); 8693 } 8694 8695 static void vmx_intr_window_test_guest(void) 8696 { 8697 handle_exception(DB_VECTOR, vmx_window_test_db_handler); 8698 8699 /* 8700 * The two consecutive STIs are to ensure that only the first 8701 * one has a shadow. Note that NOP and STI are one byte 8702 * instructions. 8703 */ 8704 asm volatile("vmcall\n\t" 8705 "nop\n\t" 8706 "sti\n\t" 8707 "sti\n\t"); 8708 8709 handle_exception(DB_VECTOR, NULL); 8710 } 8711 8712 static void verify_intr_window_exit(u64 rip) 8713 { 8714 u32 exit_reason = vmcs_read(EXI_REASON); 8715 8716 report(exit_reason == VMX_INTR_WINDOW, 8717 "Exit reason (%d) is 'interrupt window'", exit_reason); 8718 report(vmcs_read(GUEST_RIP) == rip, "RIP (%#lx) is %#lx", 8719 vmcs_read(GUEST_RIP), rip); 8720 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 8721 } 8722 8723 static void vmx_intr_window_test(void) 8724 { 8725 u64 vmcall_addr; 8726 u64 nop_addr; 8727 unsigned int orig_db_gate_type; 8728 void *db_fault_addr = get_idt_addr(&boot_idt[DB_VECTOR]); 8729 8730 if (!(ctrl_cpu_rev[0].clr & CPU_INTR_WINDOW)) { 8731 report_skip("CPU does not support the \"interrupt-window exiting\" VM-execution control."); 8732 return; 8733 } 8734 8735 /* 8736 * Change the IDT entry for #DB from interrupt gate to trap gate, 8737 * so that it won't clear RFLAGS.IF. We don't want interrupts to 8738 * be disabled after vectoring a #DB. 8739 */ 8740 orig_db_gate_type = boot_idt[DB_VECTOR].type; 8741 boot_idt[DB_VECTOR].type = 15; 8742 8743 report_prefix_push("interrupt-window"); 8744 test_set_guest(vmx_intr_window_test_guest); 8745 enter_guest(); 8746 assert_exit_reason(VMX_VMCALL); 8747 vmcall_addr = vmcs_read(GUEST_RIP); 8748 8749 /* 8750 * Ask for "interrupt-window exiting" with RFLAGS.IF set and 8751 * no blocking; expect an immediate VM-exit. Note that we have 8752 * not advanced past the vmcall instruction yet, so RIP should 8753 * point to the vmcall instruction. 8754 */ 8755 report_prefix_push("active, no blocking, RFLAGS.IF=1"); 8756 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8757 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_IF); 8758 enter_guest(); 8759 verify_intr_window_exit(vmcall_addr); 8760 report_prefix_pop(); 8761 8762 /* 8763 * Ask for "interrupt-window exiting" (with event injection) 8764 * with RFLAGS.IF set and no blocking; expect a VM-exit after 8765 * the event is injected. That is, RIP should should be at the 8766 * address specified in the IDT entry for #DB. 8767 */ 8768 report_prefix_push("active, no blocking, RFLAGS.IF=1, injecting #DB"); 8769 vmcs_write(ENT_INTR_INFO, 8770 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 8771 vmcall_addr = vmcs_read(GUEST_RIP); 8772 enter_guest(); 8773 verify_intr_window_exit((u64)db_fault_addr); 8774 report_prefix_pop(); 8775 8776 /* 8777 * Let the L2 guest run through the IRET, back to the VMCALL. 8778 * We have to clear the "interrupt-window exiting" 8779 * VM-execution control, or it would just keep causing 8780 * VM-exits. Then, advance past the VMCALL and set the 8781 * "interrupt-window exiting" VM-execution control again. 8782 */ 8783 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8784 enter_guest(); 8785 skip_exit_vmcall(); 8786 nop_addr = vmcs_read(GUEST_RIP); 8787 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8788 8789 /* 8790 * Ask for "interrupt-window exiting" in a MOV-SS shadow with 8791 * RFLAGS.IF set, and expect a VM-exit on the next 8792 * instruction. (NOP is one byte.) 8793 */ 8794 report_prefix_push("active, blocking by MOV-SS, RFLAGS.IF=1"); 8795 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 8796 enter_guest(); 8797 verify_intr_window_exit(nop_addr + 1); 8798 report_prefix_pop(); 8799 8800 /* 8801 * Back up to the NOP and ask for "interrupt-window exiting" 8802 * in an STI shadow with RFLAGS.IF set, and expect a VM-exit 8803 * on the next instruction. (NOP is one byte.) 8804 */ 8805 report_prefix_push("active, blocking by STI, RFLAGS.IF=1"); 8806 vmcs_write(GUEST_RIP, nop_addr); 8807 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_STI); 8808 enter_guest(); 8809 verify_intr_window_exit(nop_addr + 1); 8810 report_prefix_pop(); 8811 8812 /* 8813 * Ask for "interrupt-window exiting" with RFLAGS.IF clear, 8814 * and expect a VM-exit on the instruction following the STI 8815 * shadow. Only the first STI (which is one byte past the NOP) 8816 * should have a shadow. The second STI (which is two bytes 8817 * past the NOP) has no shadow. Therefore, the interrupt 8818 * window opens at three bytes past the NOP. 8819 */ 8820 report_prefix_push("active, RFLAGS.IF = 0"); 8821 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 8822 enter_guest(); 8823 verify_intr_window_exit(nop_addr + 3); 8824 report_prefix_pop(); 8825 8826 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 8827 report_skip("CPU does not support activity state HLT."); 8828 } else { 8829 /* 8830 * Ask for "interrupt-window exiting" when entering 8831 * activity state HLT, and expect an immediate 8832 * VM-exit. RIP is still three bytes past the nop. 8833 */ 8834 report_prefix_push("halted, no blocking"); 8835 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8836 enter_guest(); 8837 verify_intr_window_exit(nop_addr + 3); 8838 report_prefix_pop(); 8839 8840 /* 8841 * Ask for "interrupt-window exiting" when entering 8842 * activity state HLT (with event injection), and 8843 * expect a VM-exit after the event is injected. That 8844 * is, RIP should should be at the address specified 8845 * in the IDT entry for #DB. 8846 */ 8847 report_prefix_push("halted, no blocking, injecting #DB"); 8848 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8849 vmcs_write(ENT_INTR_INFO, 8850 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 8851 DB_VECTOR); 8852 enter_guest(); 8853 verify_intr_window_exit((u64)db_fault_addr); 8854 report_prefix_pop(); 8855 } 8856 8857 boot_idt[DB_VECTOR].type = orig_db_gate_type; 8858 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8859 enter_guest(); 8860 report_prefix_pop(); 8861 } 8862 8863 #define GUEST_TSC_OFFSET (1u << 30) 8864 8865 static u64 guest_tsc; 8866 8867 static void vmx_store_tsc_test_guest(void) 8868 { 8869 guest_tsc = rdtsc(); 8870 } 8871 8872 /* 8873 * This test ensures that when IA32_TSC is in the VM-exit MSR-store 8874 * list, the value saved is not subject to the TSC offset that is 8875 * applied to RDTSC/RDTSCP/RDMSR(IA32_TSC) in guest execution. 8876 */ 8877 static void vmx_store_tsc_test(void) 8878 { 8879 struct vmx_msr_entry msr_entry = { .index = MSR_IA32_TSC }; 8880 u64 low, high; 8881 8882 if (!(ctrl_cpu_rev[0].clr & CPU_USE_TSC_OFFSET)) { 8883 report_skip("'Use TSC offsetting' not supported"); 8884 return; 8885 } 8886 8887 test_set_guest(vmx_store_tsc_test_guest); 8888 8889 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_USE_TSC_OFFSET); 8890 vmcs_write(EXI_MSR_ST_CNT, 1); 8891 vmcs_write(EXIT_MSR_ST_ADDR, virt_to_phys(&msr_entry)); 8892 vmcs_write(TSC_OFFSET, GUEST_TSC_OFFSET); 8893 8894 low = rdtsc(); 8895 enter_guest(); 8896 high = rdtsc(); 8897 8898 report(low + GUEST_TSC_OFFSET <= guest_tsc && 8899 guest_tsc <= high + GUEST_TSC_OFFSET, 8900 "RDTSC value in the guest (%lu) is in range [%lu, %lu]", 8901 guest_tsc, low + GUEST_TSC_OFFSET, high + GUEST_TSC_OFFSET); 8902 report(low <= msr_entry.value && msr_entry.value <= high, 8903 "IA32_TSC value saved in the VM-exit MSR-store list (%lu) is in range [%lu, %lu]", 8904 msr_entry.value, low, high); 8905 } 8906 8907 static void vmx_preemption_timer_zero_test_db_handler(struct ex_regs *regs) 8908 { 8909 } 8910 8911 static void vmx_preemption_timer_zero_test_guest(void) 8912 { 8913 while (vmx_get_test_stage() < 3) 8914 vmcall(); 8915 } 8916 8917 static void vmx_preemption_timer_zero_activate_preemption_timer(void) 8918 { 8919 vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT); 8920 vmcs_write(PREEMPT_TIMER_VALUE, 0); 8921 } 8922 8923 static void vmx_preemption_timer_zero_advance_past_vmcall(void) 8924 { 8925 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 8926 enter_guest(); 8927 skip_exit_vmcall(); 8928 } 8929 8930 static void vmx_preemption_timer_zero_inject_db(bool intercept_db) 8931 { 8932 vmx_preemption_timer_zero_activate_preemption_timer(); 8933 vmcs_write(ENT_INTR_INFO, INTR_INFO_VALID_MASK | 8934 INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 8935 vmcs_write(EXC_BITMAP, intercept_db ? 1 << DB_VECTOR : 0); 8936 enter_guest(); 8937 } 8938 8939 static void vmx_preemption_timer_zero_set_pending_dbg(u32 exception_bitmap) 8940 { 8941 vmx_preemption_timer_zero_activate_preemption_timer(); 8942 vmcs_write(GUEST_PENDING_DEBUG, PENDING_DBG_TRAP | DR6_TRAP1); 8943 vmcs_write(EXC_BITMAP, exception_bitmap); 8944 enter_guest(); 8945 } 8946 8947 static void vmx_preemption_timer_zero_expect_preempt_at_rip(u64 expected_rip) 8948 { 8949 u32 reason = (u32)vmcs_read(EXI_REASON); 8950 u64 guest_rip = vmcs_read(GUEST_RIP); 8951 8952 report(reason == VMX_PREEMPT && guest_rip == expected_rip, 8953 "Exit reason is 0x%x (expected 0x%x) and guest RIP is %lx (0x%lx expected).", 8954 reason, VMX_PREEMPT, guest_rip, expected_rip); 8955 } 8956 8957 /* 8958 * This test ensures that when the VMX preemption timer is zero at 8959 * VM-entry, a VM-exit occurs after any event injection and after any 8960 * pending debug exceptions are raised, but before execution of any 8961 * guest instructions. 8962 */ 8963 static void vmx_preemption_timer_zero_test(void) 8964 { 8965 u64 db_fault_address = (u64)get_idt_addr(&boot_idt[DB_VECTOR]); 8966 handler old_db; 8967 u32 reason; 8968 8969 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 8970 report_skip("'Activate VMX-preemption timer' not supported"); 8971 return; 8972 } 8973 8974 /* 8975 * Install a custom #DB handler that doesn't abort. 8976 */ 8977 old_db = handle_exception(DB_VECTOR, 8978 vmx_preemption_timer_zero_test_db_handler); 8979 8980 test_set_guest(vmx_preemption_timer_zero_test_guest); 8981 8982 /* 8983 * VMX-preemption timer should fire after event injection. 8984 */ 8985 vmx_set_test_stage(0); 8986 vmx_preemption_timer_zero_inject_db(0); 8987 vmx_preemption_timer_zero_expect_preempt_at_rip(db_fault_address); 8988 vmx_preemption_timer_zero_advance_past_vmcall(); 8989 8990 /* 8991 * VMX-preemption timer should fire after event injection. 8992 * Exception bitmap is irrelevant, since you can't intercept 8993 * an event that you injected. 8994 */ 8995 vmx_set_test_stage(1); 8996 vmx_preemption_timer_zero_inject_db(true); 8997 vmx_preemption_timer_zero_expect_preempt_at_rip(db_fault_address); 8998 vmx_preemption_timer_zero_advance_past_vmcall(); 8999 9000 /* 9001 * VMX-preemption timer should fire after pending debug exceptions 9002 * have delivered a #DB trap. 9003 */ 9004 vmx_set_test_stage(2); 9005 vmx_preemption_timer_zero_set_pending_dbg(0); 9006 vmx_preemption_timer_zero_expect_preempt_at_rip(db_fault_address); 9007 vmx_preemption_timer_zero_advance_past_vmcall(); 9008 9009 /* 9010 * VMX-preemption timer would fire after pending debug exceptions 9011 * have delivered a #DB trap, but in this case, the #DB trap is 9012 * intercepted. 9013 */ 9014 vmx_set_test_stage(3); 9015 vmx_preemption_timer_zero_set_pending_dbg(1 << DB_VECTOR); 9016 reason = (u32)vmcs_read(EXI_REASON); 9017 report(reason == VMX_EXC_NMI, "Exit reason is 0x%x (expected 0x%x)", 9018 reason, VMX_EXC_NMI); 9019 9020 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 9021 enter_guest(); 9022 9023 handle_exception(DB_VECTOR, old_db); 9024 } 9025 9026 static u64 vmx_preemption_timer_tf_test_prev_rip; 9027 9028 static void vmx_preemption_timer_tf_test_db_handler(struct ex_regs *regs) 9029 { 9030 extern char vmx_preemption_timer_tf_test_endloop; 9031 9032 if (vmx_get_test_stage() == 2) { 9033 /* 9034 * Stage 2 means that we're done, one way or another. 9035 * Arrange for the iret to drop us out of the wbinvd 9036 * loop and stop single-stepping. 9037 */ 9038 regs->rip = (u64)&vmx_preemption_timer_tf_test_endloop; 9039 regs->rflags &= ~X86_EFLAGS_TF; 9040 } else if (regs->rip == vmx_preemption_timer_tf_test_prev_rip) { 9041 /* 9042 * The RIP should alternate between the wbinvd and the 9043 * jmp instruction in the code below. If we ever see 9044 * the same instruction twice in a row, that means a 9045 * single-step trap has been dropped. Let the 9046 * hypervisor know about the failure by executing a 9047 * VMCALL. 9048 */ 9049 vmcall(); 9050 } 9051 vmx_preemption_timer_tf_test_prev_rip = regs->rip; 9052 } 9053 9054 static void vmx_preemption_timer_tf_test_guest(void) 9055 { 9056 /* 9057 * The hypervisor doesn't intercept WBINVD, so the loop below 9058 * shouldn't be a problem--it's just two instructions 9059 * executing in VMX non-root mode. However, when the 9060 * hypervisor is running in a virtual environment, the parent 9061 * hypervisor might intercept WBINVD and emulate it. If the 9062 * parent hypervisor is broken, the single-step trap after the 9063 * WBINVD might be lost. 9064 */ 9065 asm volatile("vmcall\n\t" 9066 "0: wbinvd\n\t" 9067 "1: jmp 0b\n\t" 9068 "vmx_preemption_timer_tf_test_endloop:"); 9069 } 9070 9071 /* 9072 * Ensure that the delivery of a "VMX-preemption timer expired" 9073 * VM-exit doesn't disrupt single-stepping in the guest. Note that 9074 * passing this test doesn't ensure correctness, because the test will 9075 * only fail if the VMX-preemtion timer fires at the right time (or 9076 * the wrong time, as it were). 9077 */ 9078 static void vmx_preemption_timer_tf_test(void) 9079 { 9080 handler old_db; 9081 u32 reason; 9082 int i; 9083 9084 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 9085 report_skip("'Activate VMX-preemption timer' not supported"); 9086 return; 9087 } 9088 9089 old_db = handle_exception(DB_VECTOR, 9090 vmx_preemption_timer_tf_test_db_handler); 9091 9092 test_set_guest(vmx_preemption_timer_tf_test_guest); 9093 9094 enter_guest(); 9095 skip_exit_vmcall(); 9096 9097 vmx_set_test_stage(1); 9098 vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT); 9099 vmcs_write(PREEMPT_TIMER_VALUE, 50000); 9100 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_TF); 9101 9102 /* 9103 * The only exit we should see is "VMX-preemption timer 9104 * expired." If we get a VMCALL exit, that means the #DB 9105 * handler has detected a missing single-step trap. It doesn't 9106 * matter where the guest RIP is when the VMX-preemption timer 9107 * expires (whether it's in the WBINVD loop or in the #DB 9108 * handler)--a single-step trap should never be discarded. 9109 */ 9110 for (i = 0; i < 10000; i++) { 9111 enter_guest(); 9112 reason = (u32)vmcs_read(EXI_REASON); 9113 if (reason == VMX_PREEMPT) 9114 continue; 9115 TEST_ASSERT(reason == VMX_VMCALL); 9116 skip_exit_insn(); 9117 break; 9118 } 9119 9120 report(reason == VMX_PREEMPT, "No single-step traps skipped"); 9121 9122 vmx_set_test_stage(2); 9123 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 9124 enter_guest(); 9125 9126 handle_exception(DB_VECTOR, old_db); 9127 } 9128 9129 #define VMX_PREEMPTION_TIMER_EXPIRY_CYCLES 1000000 9130 9131 static u64 vmx_preemption_timer_expiry_start; 9132 static u64 vmx_preemption_timer_expiry_finish; 9133 9134 static void vmx_preemption_timer_expiry_test_guest(void) 9135 { 9136 vmcall(); 9137 vmx_preemption_timer_expiry_start = fenced_rdtsc(); 9138 9139 while (vmx_get_test_stage() == 0) 9140 vmx_preemption_timer_expiry_finish = fenced_rdtsc(); 9141 } 9142 9143 /* 9144 * Test that the VMX-preemption timer is not excessively delayed. 9145 * 9146 * Per the SDM, volume 3, VM-entry starts the VMX-preemption timer 9147 * with the unsigned value in the VMX-preemption timer-value field, 9148 * and the VMX-preemption timer counts down by 1 every time bit X in 9149 * the TSC changes due to a TSC increment (where X is 9150 * IA32_VMX_MISC[4:0]). If the timer counts down to zero in any state 9151 * other than the wait-for-SIPI state, the logical processor 9152 * transitions to the C0 C-state and causes a VM-exit. 9153 * 9154 * The guest code above reads the starting TSC after VM-entry. At this 9155 * point, the VMX-preemption timer has already been activated. Next, 9156 * the guest code reads the current TSC in a loop, storing the value 9157 * read to memory. 9158 * 9159 * If the RDTSC in the loop reads a value past the VMX-preemption 9160 * timer deadline, then the VMX-preemption timer VM-exit must be 9161 * delivered before the next instruction retires. Even if a higher 9162 * priority SMI is delivered first, the VMX-preemption timer VM-exit 9163 * must be delivered before the next instruction retires. Hence, a TSC 9164 * value past the VMX-preemption timer deadline might be read, but it 9165 * cannot be stored. If a TSC value past the deadline *is* stored, 9166 * then the architectural specification has been violated. 9167 */ 9168 static void vmx_preemption_timer_expiry_test(void) 9169 { 9170 u32 preemption_timer_value; 9171 union vmx_misc misc; 9172 u64 tsc_deadline; 9173 u32 reason; 9174 9175 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 9176 report_skip("'Activate VMX-preemption timer' not supported"); 9177 return; 9178 } 9179 9180 test_set_guest(vmx_preemption_timer_expiry_test_guest); 9181 9182 enter_guest(); 9183 skip_exit_vmcall(); 9184 9185 misc.val = rdmsr(MSR_IA32_VMX_MISC); 9186 preemption_timer_value = 9187 VMX_PREEMPTION_TIMER_EXPIRY_CYCLES >> misc.pt_bit; 9188 9189 vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT); 9190 vmcs_write(PREEMPT_TIMER_VALUE, preemption_timer_value); 9191 vmx_set_test_stage(0); 9192 9193 enter_guest(); 9194 reason = (u32)vmcs_read(EXI_REASON); 9195 TEST_ASSERT(reason == VMX_PREEMPT); 9196 9197 tsc_deadline = ((vmx_preemption_timer_expiry_start >> misc.pt_bit) << 9198 misc.pt_bit) + (preemption_timer_value << misc.pt_bit); 9199 9200 report(vmx_preemption_timer_expiry_finish < tsc_deadline, 9201 "Last stored guest TSC (%lu) < TSC deadline (%lu)", 9202 vmx_preemption_timer_expiry_finish, tsc_deadline); 9203 9204 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 9205 vmx_set_test_stage(1); 9206 enter_guest(); 9207 } 9208 9209 static void vmx_db_test_guest(void) 9210 { 9211 /* 9212 * For a hardware generated single-step #DB. 9213 */ 9214 asm volatile("vmcall;" 9215 "nop;" 9216 ".Lpost_nop:"); 9217 /* 9218 * ...in a MOVSS shadow, with pending debug exceptions. 9219 */ 9220 asm volatile("vmcall;" 9221 "nop;" 9222 ".Lpost_movss_nop:"); 9223 /* 9224 * For an L0 synthesized single-step #DB. (L0 intercepts WBINVD and 9225 * emulates it in software.) 9226 */ 9227 asm volatile("vmcall;" 9228 "wbinvd;" 9229 ".Lpost_wbinvd:"); 9230 /* 9231 * ...in a MOVSS shadow, with pending debug exceptions. 9232 */ 9233 asm volatile("vmcall;" 9234 "wbinvd;" 9235 ".Lpost_movss_wbinvd:"); 9236 /* 9237 * For a hardware generated single-step #DB in a transactional region. 9238 */ 9239 asm volatile("vmcall;" 9240 ".Lxbegin: xbegin .Lskip_rtm;" 9241 "xend;" 9242 ".Lskip_rtm:"); 9243 } 9244 9245 /* 9246 * Clear the pending debug exceptions and RFLAGS.TF and re-enter 9247 * L2. No #DB is delivered and L2 continues to the next point of 9248 * interest. 9249 */ 9250 static void dismiss_db(void) 9251 { 9252 vmcs_write(GUEST_PENDING_DEBUG, 0); 9253 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 9254 enter_guest(); 9255 } 9256 9257 /* 9258 * Check a variety of VMCS fields relevant to an intercepted #DB exception. 9259 * Then throw away the #DB exception and resume L2. 9260 */ 9261 static void check_db_exit(bool xfail_qual, bool xfail_dr6, bool xfail_pdbg, 9262 void *expected_rip, u64 expected_exit_qual, 9263 u64 expected_dr6) 9264 { 9265 u32 reason = vmcs_read(EXI_REASON); 9266 u32 intr_info = vmcs_read(EXI_INTR_INFO); 9267 u64 exit_qual = vmcs_read(EXI_QUALIFICATION); 9268 u64 guest_rip = vmcs_read(GUEST_RIP); 9269 u64 guest_pending_dbg = vmcs_read(GUEST_PENDING_DEBUG); 9270 u64 dr6 = read_dr6(); 9271 const u32 expected_intr_info = INTR_INFO_VALID_MASK | 9272 INTR_TYPE_HARD_EXCEPTION | DB_VECTOR; 9273 9274 report(reason == VMX_EXC_NMI && intr_info == expected_intr_info, 9275 "Expected #DB VM-exit"); 9276 report((u64)expected_rip == guest_rip, "Expected RIP %p (actual %lx)", 9277 expected_rip, guest_rip); 9278 report_xfail(xfail_pdbg, 0 == guest_pending_dbg, 9279 "Expected pending debug exceptions 0 (actual %lx)", 9280 guest_pending_dbg); 9281 report_xfail(xfail_qual, expected_exit_qual == exit_qual, 9282 "Expected exit qualification %lx (actual %lx)", 9283 expected_exit_qual, exit_qual); 9284 report_xfail(xfail_dr6, expected_dr6 == dr6, 9285 "Expected DR6 %lx (actual %lx)", expected_dr6, dr6); 9286 dismiss_db(); 9287 } 9288 9289 /* 9290 * Assuming the guest has just exited on a VMCALL instruction, skip 9291 * over the vmcall, and set the guest's RFLAGS.TF in the VMCS. If 9292 * pending debug exceptions are non-zero, set the VMCS up as if the 9293 * previous instruction was a MOVSS that generated the indicated 9294 * pending debug exceptions. Then enter L2. 9295 */ 9296 static void single_step_guest(const char *test_name, u64 starting_dr6, 9297 u64 pending_debug_exceptions) 9298 { 9299 printf("\n%s\n", test_name); 9300 skip_exit_vmcall(); 9301 write_dr6(starting_dr6); 9302 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_TF); 9303 if (pending_debug_exceptions) { 9304 vmcs_write(GUEST_PENDING_DEBUG, pending_debug_exceptions); 9305 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 9306 } 9307 enter_guest(); 9308 } 9309 9310 /* 9311 * When L1 intercepts #DB, verify that a single-step trap clears 9312 * pending debug exceptions, populates the exit qualification field 9313 * properly, and that DR6 is not prematurely clobbered. In a 9314 * (simulated) MOVSS shadow, make sure that the pending debug 9315 * exception bits are properly accumulated into the exit qualification 9316 * field. 9317 */ 9318 static void vmx_db_test(void) 9319 { 9320 /* 9321 * We are going to set a few arbitrary bits in DR6 to verify that 9322 * (a) DR6 is not modified by an intercepted #DB, and 9323 * (b) stale bits in DR6 (DR6.BD, in particular) don't leak into 9324 * the exit qualification field for a subsequent #DB exception. 9325 */ 9326 const u64 starting_dr6 = DR6_ACTIVE_LOW | DR6_BS | DR6_TRAP3 | DR6_TRAP1; 9327 extern char post_nop asm(".Lpost_nop"); 9328 extern char post_movss_nop asm(".Lpost_movss_nop"); 9329 extern char post_wbinvd asm(".Lpost_wbinvd"); 9330 extern char post_movss_wbinvd asm(".Lpost_movss_wbinvd"); 9331 extern char xbegin asm(".Lxbegin"); 9332 extern char skip_rtm asm(".Lskip_rtm"); 9333 9334 /* 9335 * L1 wants to intercept #DB exceptions encountered in L2. 9336 */ 9337 vmcs_write(EXC_BITMAP, BIT(DB_VECTOR)); 9338 9339 /* 9340 * Start L2 and run it up to the first point of interest. 9341 */ 9342 test_set_guest(vmx_db_test_guest); 9343 enter_guest(); 9344 9345 /* 9346 * Hardware-delivered #DB trap for single-step sets the 9347 * standard that L0 has to follow for emulated instructions. 9348 */ 9349 single_step_guest("Hardware delivered single-step", starting_dr6, 0); 9350 check_db_exit(false, false, false, &post_nop, DR6_BS, starting_dr6); 9351 9352 /* 9353 * Hardware-delivered #DB trap for single-step in MOVSS shadow 9354 * also sets the standard that L0 has to follow for emulated 9355 * instructions. Here, we establish the VMCS pending debug 9356 * exceptions to indicate that the simulated MOVSS triggered a 9357 * data breakpoint as well as the single-step trap. 9358 */ 9359 single_step_guest("Hardware delivered single-step in MOVSS shadow", 9360 starting_dr6, DR6_BS | PENDING_DBG_TRAP | DR6_TRAP0); 9361 check_db_exit(false, false, false, &post_movss_nop, DR6_BS | DR6_TRAP0, 9362 starting_dr6); 9363 9364 /* 9365 * L0 synthesized #DB trap for single-step is buggy, because 9366 * kvm (a) clobbers DR6 too early, and (b) tries its best to 9367 * reconstitute the exit qualification from the prematurely 9368 * modified DR6, but fails miserably. 9369 */ 9370 single_step_guest("Software synthesized single-step", starting_dr6, 0); 9371 check_db_exit(false, false, false, &post_wbinvd, DR6_BS, starting_dr6); 9372 9373 /* 9374 * L0 synthesized #DB trap for single-step in MOVSS shadow is 9375 * even worse, because L0 also leaves the pending debug 9376 * exceptions in the VMCS instead of accumulating them into 9377 * the exit qualification field for the #DB exception. 9378 */ 9379 single_step_guest("Software synthesized single-step in MOVSS shadow", 9380 starting_dr6, DR6_BS | PENDING_DBG_TRAP | DR6_TRAP0); 9381 check_db_exit(true, false, true, &post_movss_wbinvd, DR6_BS | DR6_TRAP0, 9382 starting_dr6); 9383 9384 /* 9385 * Optional RTM test for hardware that supports RTM, to 9386 * demonstrate that the current volume 3 of the SDM 9387 * (325384-067US), table 27-1 is incorrect. Bit 16 of the exit 9388 * qualification for debug exceptions is not reserved. It is 9389 * set to 1 if a debug exception (#DB) or a breakpoint 9390 * exception (#BP) occurs inside an RTM region while advanced 9391 * debugging of RTM transactional regions is enabled. 9392 */ 9393 if (this_cpu_has(X86_FEATURE_RTM)) { 9394 vmcs_write(ENT_CONTROLS, 9395 vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 9396 /* 9397 * Set DR7.RTM[bit 11] and IA32_DEBUGCTL.RTM[bit 15] 9398 * in the guest to enable advanced debugging of RTM 9399 * transactional regions. 9400 */ 9401 vmcs_write(GUEST_DR7, BIT(11)); 9402 vmcs_write(GUEST_DEBUGCTL, BIT(15)); 9403 single_step_guest("Hardware delivered single-step in " 9404 "transactional region", starting_dr6, 0); 9405 check_db_exit(false, false, false, &xbegin, BIT(16), 9406 starting_dr6); 9407 } else { 9408 vmcs_write(GUEST_RIP, (u64)&skip_rtm); 9409 enter_guest(); 9410 } 9411 } 9412 9413 static void enable_vid(void) 9414 { 9415 void *virtual_apic_page; 9416 9417 assert(cpu_has_apicv()); 9418 9419 disable_intercept_for_x2apic_msrs(); 9420 9421 virtual_apic_page = alloc_page(); 9422 vmcs_write(APIC_VIRT_ADDR, (u64)virtual_apic_page); 9423 9424 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 9425 9426 vmcs_write(EOI_EXIT_BITMAP0, 0x0); 9427 vmcs_write(EOI_EXIT_BITMAP1, 0x0); 9428 vmcs_write(EOI_EXIT_BITMAP2, 0x0); 9429 vmcs_write(EOI_EXIT_BITMAP3, 0x0); 9430 9431 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY | CPU_TPR_SHADOW); 9432 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_VINTD | CPU_VIRT_X2APIC); 9433 } 9434 9435 static void trigger_ioapic_scan_thread(void *data) 9436 { 9437 /* Wait until other CPU entered L2 */ 9438 while (vmx_get_test_stage() != 1) 9439 ; 9440 9441 /* Trigger ioapic scan */ 9442 ioapic_set_redir(0xf, 0x79, TRIGGER_LEVEL); 9443 vmx_set_test_stage(2); 9444 } 9445 9446 static void irq_79_handler_guest(isr_regs_t *regs) 9447 { 9448 eoi(); 9449 9450 /* L1 expects vmexit on VMX_VMCALL and not VMX_EOI_INDUCED */ 9451 vmcall(); 9452 } 9453 9454 /* 9455 * Constant for num of busy-loop iterations after which 9456 * a timer interrupt should have happened in host 9457 */ 9458 #define TIMER_INTERRUPT_DELAY 100000000 9459 9460 static void vmx_eoi_bitmap_ioapic_scan_test_guest(void) 9461 { 9462 handle_irq(0x79, irq_79_handler_guest); 9463 irq_enable(); 9464 9465 /* Signal to L1 CPU to trigger ioapic scan */ 9466 vmx_set_test_stage(1); 9467 /* Wait until L1 CPU to trigger ioapic scan */ 9468 while (vmx_get_test_stage() != 2) 9469 ; 9470 9471 /* 9472 * Wait for L0 timer interrupt to be raised while we run in L2 9473 * such that L0 will process the IOAPIC scan request before 9474 * resuming L2 9475 */ 9476 delay(TIMER_INTERRUPT_DELAY); 9477 9478 asm volatile ("int $0x79"); 9479 } 9480 9481 static void vmx_eoi_bitmap_ioapic_scan_test(void) 9482 { 9483 if (!cpu_has_apicv() || (cpu_count() < 2)) { 9484 report_skip(__func__); 9485 return; 9486 } 9487 9488 enable_vid(); 9489 9490 on_cpu_async(1, trigger_ioapic_scan_thread, NULL); 9491 test_set_guest(vmx_eoi_bitmap_ioapic_scan_test_guest); 9492 9493 /* 9494 * Launch L2. 9495 * We expect the exit reason to be VMX_VMCALL (and not EOI INDUCED). 9496 * In case the reason isn't VMX_VMCALL, the asserion inside 9497 * skip_exit_vmcall() will fail. 9498 */ 9499 enter_guest(); 9500 skip_exit_vmcall(); 9501 9502 /* Let L2 finish */ 9503 enter_guest(); 9504 report_pass(__func__); 9505 } 9506 9507 #define HLT_WITH_RVI_VECTOR (0xf1) 9508 9509 bool vmx_hlt_with_rvi_guest_isr_fired; 9510 static void vmx_hlt_with_rvi_guest_isr(isr_regs_t *regs) 9511 { 9512 vmx_hlt_with_rvi_guest_isr_fired = true; 9513 eoi(); 9514 } 9515 9516 static void vmx_hlt_with_rvi_guest(void) 9517 { 9518 handle_irq(HLT_WITH_RVI_VECTOR, vmx_hlt_with_rvi_guest_isr); 9519 9520 irq_enable(); 9521 asm volatile ("nop"); 9522 9523 vmcall(); 9524 } 9525 9526 static void vmx_hlt_with_rvi_test(void) 9527 { 9528 if (!cpu_has_apicv()) { 9529 report_skip(__func__); 9530 return; 9531 } 9532 9533 enable_vid(); 9534 9535 vmx_hlt_with_rvi_guest_isr_fired = false; 9536 test_set_guest(vmx_hlt_with_rvi_guest); 9537 9538 enter_guest(); 9539 skip_exit_vmcall(); 9540 9541 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 9542 vmcs_write(GUEST_INT_STATUS, HLT_WITH_RVI_VECTOR); 9543 enter_guest(); 9544 9545 report(vmx_hlt_with_rvi_guest_isr_fired, "Interrupt raised in guest"); 9546 } 9547 9548 static void set_irq_line_thread(void *data) 9549 { 9550 /* Wait until other CPU entered L2 */ 9551 while (vmx_get_test_stage() != 1) 9552 ; 9553 9554 /* Set irq-line 0xf to raise vector 0x78 for vCPU 0 */ 9555 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 9556 vmx_set_test_stage(2); 9557 } 9558 9559 static bool irq_78_handler_vmcall_before_eoi; 9560 static void irq_78_handler_guest(isr_regs_t *regs) 9561 { 9562 set_irq_line(0xf, 0); 9563 if (irq_78_handler_vmcall_before_eoi) 9564 vmcall(); 9565 eoi(); 9566 vmcall(); 9567 } 9568 9569 static void vmx_apic_passthrough_guest(void) 9570 { 9571 handle_irq(0x78, irq_78_handler_guest); 9572 irq_enable(); 9573 9574 /* If requested, wait for other CPU to trigger ioapic scan */ 9575 if (vmx_get_test_stage() < 1) { 9576 vmx_set_test_stage(1); 9577 while (vmx_get_test_stage() != 2) 9578 ; 9579 } 9580 9581 set_irq_line(0xf, 1); 9582 } 9583 9584 static void vmx_apic_passthrough(bool set_irq_line_from_thread) 9585 { 9586 if (set_irq_line_from_thread && (cpu_count() < 2)) { 9587 report_skip(__func__); 9588 return; 9589 } 9590 9591 /* Test device is required for generating IRQs */ 9592 if (!test_device_enabled()) { 9593 report_skip(__func__); 9594 return; 9595 } 9596 u64 cpu_ctrl_0 = CPU_SECONDARY; 9597 u64 cpu_ctrl_1 = 0; 9598 9599 disable_intercept_for_x2apic_msrs(); 9600 9601 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 9602 9603 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 9604 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 9605 9606 if (set_irq_line_from_thread) { 9607 irq_78_handler_vmcall_before_eoi = false; 9608 on_cpu_async(1, set_irq_line_thread, NULL); 9609 } else { 9610 irq_78_handler_vmcall_before_eoi = true; 9611 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 9612 vmx_set_test_stage(2); 9613 } 9614 test_set_guest(vmx_apic_passthrough_guest); 9615 9616 if (irq_78_handler_vmcall_before_eoi) { 9617 /* Before EOI remote_irr should still be set */ 9618 enter_guest(); 9619 skip_exit_vmcall(); 9620 TEST_ASSERT_EQ_MSG(1, (int)ioapic_read_redir(0xf).remote_irr, 9621 "IOAPIC pass-through: remote_irr=1 before EOI"); 9622 } 9623 9624 /* After EOI remote_irr should be cleared */ 9625 enter_guest(); 9626 skip_exit_vmcall(); 9627 TEST_ASSERT_EQ_MSG(0, (int)ioapic_read_redir(0xf).remote_irr, 9628 "IOAPIC pass-through: remote_irr=0 after EOI"); 9629 9630 /* Let L2 finish */ 9631 enter_guest(); 9632 report_pass(__func__); 9633 } 9634 9635 static void vmx_apic_passthrough_test(void) 9636 { 9637 vmx_apic_passthrough(false); 9638 } 9639 9640 static void vmx_apic_passthrough_thread_test(void) 9641 { 9642 vmx_apic_passthrough(true); 9643 } 9644 9645 static void vmx_apic_passthrough_tpr_threshold_guest(void) 9646 { 9647 cli(); 9648 apic_set_tpr(0); 9649 } 9650 9651 static bool vmx_apic_passthrough_tpr_threshold_ipi_isr_fired; 9652 static void vmx_apic_passthrough_tpr_threshold_ipi_isr(isr_regs_t *regs) 9653 { 9654 vmx_apic_passthrough_tpr_threshold_ipi_isr_fired = true; 9655 eoi(); 9656 } 9657 9658 static void vmx_apic_passthrough_tpr_threshold_test(void) 9659 { 9660 int ipi_vector = 0xe1; 9661 9662 disable_intercept_for_x2apic_msrs(); 9663 vmcs_clear_bits(PIN_CONTROLS, PIN_EXTINT); 9664 9665 /* Raise L0 TPR-threshold by queueing vector in LAPIC IRR */ 9666 cli(); 9667 apic_set_tpr((ipi_vector >> 4) + 1); 9668 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | 9669 APIC_DM_FIXED | ipi_vector, 9670 0); 9671 9672 test_set_guest(vmx_apic_passthrough_tpr_threshold_guest); 9673 enter_guest(); 9674 9675 report(apic_get_tpr() == 0, "TPR was zero by guest"); 9676 9677 /* Clean pending self-IPI */ 9678 vmx_apic_passthrough_tpr_threshold_ipi_isr_fired = false; 9679 handle_irq(ipi_vector, vmx_apic_passthrough_tpr_threshold_ipi_isr); 9680 sti(); 9681 asm volatile ("nop"); 9682 report(vmx_apic_passthrough_tpr_threshold_ipi_isr_fired, "self-IPI fired"); 9683 9684 report_pass(__func__); 9685 } 9686 9687 static u64 init_signal_test_exit_reason; 9688 static bool init_signal_test_thread_continued; 9689 9690 static void init_signal_test_thread(void *data) 9691 { 9692 struct vmcs *test_vmcs = data; 9693 9694 /* Enter VMX operation (i.e. exec VMXON) */ 9695 u64 *ap_vmxon_region = alloc_page(); 9696 enable_vmx(); 9697 init_vmx(ap_vmxon_region); 9698 _vmx_on(ap_vmxon_region); 9699 9700 /* Signal CPU have entered VMX operation */ 9701 vmx_set_test_stage(1); 9702 9703 /* Wait for BSP CPU to send INIT signal */ 9704 while (vmx_get_test_stage() != 2) 9705 ; 9706 9707 /* 9708 * Signal that we continue as usual as INIT signal 9709 * should be blocked while CPU is in VMX operation 9710 */ 9711 vmx_set_test_stage(3); 9712 9713 /* Wait for signal to enter VMX non-root mode */ 9714 while (vmx_get_test_stage() != 4) 9715 ; 9716 9717 /* Enter VMX non-root mode */ 9718 test_set_guest(v2_null_test_guest); 9719 make_vmcs_current(test_vmcs); 9720 enter_guest(); 9721 /* Save exit reason for BSP CPU to compare to expected result */ 9722 init_signal_test_exit_reason = vmcs_read(EXI_REASON); 9723 /* VMCLEAR test-vmcs so it could be loaded by BSP CPU */ 9724 vmcs_clear(test_vmcs); 9725 launched = false; 9726 /* Signal that CPU exited to VMX root mode */ 9727 vmx_set_test_stage(5); 9728 9729 /* Wait for BSP CPU to signal to exit VMX operation */ 9730 while (vmx_get_test_stage() != 6) 9731 ; 9732 9733 /* Exit VMX operation (i.e. exec VMXOFF) */ 9734 vmx_off(); 9735 9736 /* 9737 * Signal to BSP CPU that we continue as usual as INIT signal 9738 * should have been consumed by VMX_INIT exit from guest 9739 */ 9740 vmx_set_test_stage(7); 9741 9742 /* Wait for BSP CPU to signal to enter VMX operation */ 9743 while (vmx_get_test_stage() != 8) 9744 ; 9745 /* Enter VMX operation (i.e. exec VMXON) */ 9746 _vmx_on(ap_vmxon_region); 9747 /* Signal to BSP we are in VMX operation */ 9748 vmx_set_test_stage(9); 9749 9750 /* Wait for BSP CPU to send INIT signal */ 9751 while (vmx_get_test_stage() != 10) 9752 ; 9753 9754 /* Exit VMX operation (i.e. exec VMXOFF) */ 9755 vmx_off(); 9756 9757 /* 9758 * Exiting VMX operation should result in latched 9759 * INIT signal being processed. Therefore, we should 9760 * never reach the below code. Thus, signal to BSP 9761 * CPU if we have reached here so it is able to 9762 * report an issue if it happens. 9763 */ 9764 init_signal_test_thread_continued = true; 9765 } 9766 9767 #define INIT_SIGNAL_TEST_DELAY 100000000ULL 9768 9769 static void vmx_init_signal_test(void) 9770 { 9771 struct vmcs *test_vmcs; 9772 9773 if (cpu_count() < 2) { 9774 report_skip(__func__); 9775 return; 9776 } 9777 9778 /* VMCLEAR test-vmcs so it could be loaded by other CPU */ 9779 vmcs_save(&test_vmcs); 9780 vmcs_clear(test_vmcs); 9781 9782 vmx_set_test_stage(0); 9783 on_cpu_async(1, init_signal_test_thread, test_vmcs); 9784 9785 /* Wait for other CPU to enter VMX operation */ 9786 while (vmx_get_test_stage() != 1) 9787 ; 9788 9789 /* Send INIT signal to other CPU */ 9790 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_INIT | APIC_INT_ASSERT, 9791 id_map[1]); 9792 /* Signal other CPU we have sent INIT signal */ 9793 vmx_set_test_stage(2); 9794 9795 /* 9796 * Wait reasonable amount of time for INIT signal to 9797 * be received on other CPU and verify that other CPU 9798 * have proceed as usual to next test stage as INIT 9799 * signal should be blocked while other CPU in 9800 * VMX operation 9801 */ 9802 delay(INIT_SIGNAL_TEST_DELAY); 9803 report(vmx_get_test_stage() == 3, 9804 "INIT signal blocked when CPU in VMX operation"); 9805 /* No point to continue if we failed at this point */ 9806 if (vmx_get_test_stage() != 3) 9807 return; 9808 9809 /* Signal other CPU to enter VMX non-root mode */ 9810 init_signal_test_exit_reason = -1ull; 9811 vmx_set_test_stage(4); 9812 /* 9813 * Wait reasonable amont of time for other CPU 9814 * to exit to VMX root mode 9815 */ 9816 delay(INIT_SIGNAL_TEST_DELAY); 9817 if (vmx_get_test_stage() != 5) { 9818 report_fail("Pending INIT signal didn't result in VMX exit"); 9819 return; 9820 } 9821 report(init_signal_test_exit_reason == VMX_INIT, 9822 "INIT signal during VMX non-root mode result in exit-reason %s (%lu)", 9823 exit_reason_description(init_signal_test_exit_reason), 9824 init_signal_test_exit_reason); 9825 9826 /* Run guest to completion */ 9827 make_vmcs_current(test_vmcs); 9828 enter_guest(); 9829 9830 /* Signal other CPU to exit VMX operation */ 9831 init_signal_test_thread_continued = false; 9832 vmx_set_test_stage(6); 9833 9834 /* Wait reasonable amount of time for other CPU to exit VMX operation */ 9835 delay(INIT_SIGNAL_TEST_DELAY); 9836 report(vmx_get_test_stage() == 7, 9837 "INIT signal consumed on VMX_INIT exit"); 9838 /* No point to continue if we failed at this point */ 9839 if (vmx_get_test_stage() != 7) 9840 return; 9841 9842 /* Signal other CPU to enter VMX operation */ 9843 vmx_set_test_stage(8); 9844 /* Wait for other CPU to enter VMX operation */ 9845 while (vmx_get_test_stage() != 9) 9846 ; 9847 9848 /* Send INIT signal to other CPU */ 9849 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_INIT | APIC_INT_ASSERT, 9850 id_map[1]); 9851 /* Signal other CPU we have sent INIT signal */ 9852 vmx_set_test_stage(10); 9853 9854 /* 9855 * Wait reasonable amount of time for other CPU 9856 * to exit VMX operation and process INIT signal 9857 */ 9858 delay(INIT_SIGNAL_TEST_DELAY); 9859 report(!init_signal_test_thread_continued, 9860 "INIT signal processed after exit VMX operation"); 9861 9862 /* 9863 * TODO: Send SIPI to other CPU to sipi_entry (See x86/cstart64.S) 9864 * to re-init it to kvm-unit-tests standard environment. 9865 * Somehow (?) verify that SIPI was indeed received. 9866 */ 9867 } 9868 9869 #define SIPI_SIGNAL_TEST_DELAY 100000000ULL 9870 9871 static void vmx_sipi_test_guest(void) 9872 { 9873 if (apic_id() == 0) { 9874 /* wait AP enter guest with activity=WAIT_SIPI */ 9875 while (vmx_get_test_stage() != 1) 9876 ; 9877 delay(SIPI_SIGNAL_TEST_DELAY); 9878 9879 /* First SIPI signal */ 9880 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_STARTUP | APIC_INT_ASSERT, id_map[1]); 9881 report_pass("BSP(L2): Send first SIPI to cpu[%d]", id_map[1]); 9882 9883 /* wait AP enter guest */ 9884 while (vmx_get_test_stage() != 2) 9885 ; 9886 delay(SIPI_SIGNAL_TEST_DELAY); 9887 9888 /* Second SIPI signal should be ignored since AP is not in WAIT_SIPI state */ 9889 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_STARTUP | APIC_INT_ASSERT, id_map[1]); 9890 report_pass("BSP(L2): Send second SIPI to cpu[%d]", id_map[1]); 9891 9892 /* Delay a while to check whether second SIPI would cause VMExit */ 9893 delay(SIPI_SIGNAL_TEST_DELAY); 9894 9895 /* Test is done, notify AP to exit test */ 9896 vmx_set_test_stage(3); 9897 9898 /* wait AP exit non-root mode */ 9899 while (vmx_get_test_stage() != 5) 9900 ; 9901 } else { 9902 /* wait BSP notify test is done */ 9903 while (vmx_get_test_stage() != 3) 9904 ; 9905 9906 /* AP exit guest */ 9907 vmx_set_test_stage(4); 9908 } 9909 } 9910 9911 static void sipi_test_ap_thread(void *data) 9912 { 9913 struct vmcs *ap_vmcs; 9914 u64 *ap_vmxon_region; 9915 void *ap_stack, *ap_syscall_stack; 9916 u64 cpu_ctrl_0 = CPU_SECONDARY; 9917 u64 cpu_ctrl_1 = 0; 9918 9919 /* Enter VMX operation (i.e. exec VMXON) */ 9920 ap_vmxon_region = alloc_page(); 9921 enable_vmx(); 9922 init_vmx(ap_vmxon_region); 9923 _vmx_on(ap_vmxon_region); 9924 init_vmcs(&ap_vmcs); 9925 make_vmcs_current(ap_vmcs); 9926 9927 /* Set stack for AP */ 9928 ap_stack = alloc_page(); 9929 ap_syscall_stack = alloc_page(); 9930 vmcs_write(GUEST_RSP, (u64)(ap_stack + PAGE_SIZE - 1)); 9931 vmcs_write(GUEST_SYSENTER_ESP, (u64)(ap_syscall_stack + PAGE_SIZE - 1)); 9932 9933 /* passthrough lapic to L2 */ 9934 disable_intercept_for_x2apic_msrs(); 9935 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 9936 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 9937 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 9938 9939 /* Set guest activity state to wait-for-SIPI state */ 9940 vmcs_write(GUEST_ACTV_STATE, ACTV_WAIT_SIPI); 9941 9942 vmx_set_test_stage(1); 9943 9944 /* AP enter guest */ 9945 enter_guest(); 9946 9947 if (vmcs_read(EXI_REASON) == VMX_SIPI) { 9948 report_pass("AP: Handle SIPI VMExit"); 9949 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 9950 vmx_set_test_stage(2); 9951 } else { 9952 report_fail("AP: Unexpected VMExit, reason=%ld", vmcs_read(EXI_REASON)); 9953 vmx_off(); 9954 return; 9955 } 9956 9957 /* AP enter guest */ 9958 enter_guest(); 9959 9960 report(vmcs_read(EXI_REASON) != VMX_SIPI, 9961 "AP: should no SIPI VMExit since activity is not in WAIT_SIPI state"); 9962 9963 /* notify BSP that AP is already exit from non-root mode */ 9964 vmx_set_test_stage(5); 9965 9966 /* Leave VMX operation */ 9967 vmx_off(); 9968 } 9969 9970 static void vmx_sipi_signal_test(void) 9971 { 9972 if (!(rdmsr(MSR_IA32_VMX_MISC) & MSR_IA32_VMX_MISC_ACTIVITY_WAIT_SIPI)) { 9973 printf("\tACTIVITY_WAIT_SIPI state is not supported.\n"); 9974 return; 9975 } 9976 9977 if (cpu_count() < 2) { 9978 report_skip(__func__); 9979 return; 9980 } 9981 9982 u64 cpu_ctrl_0 = CPU_SECONDARY; 9983 u64 cpu_ctrl_1 = 0; 9984 9985 /* passthrough lapic to L2 */ 9986 disable_intercept_for_x2apic_msrs(); 9987 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 9988 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 9989 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 9990 9991 test_set_guest(vmx_sipi_test_guest); 9992 9993 /* update CR3 on AP */ 9994 on_cpu(1, update_cr3, (void *)read_cr3()); 9995 9996 /* start AP */ 9997 on_cpu_async(1, sipi_test_ap_thread, NULL); 9998 9999 vmx_set_test_stage(0); 10000 10001 /* BSP enter guest */ 10002 enter_guest(); 10003 } 10004 10005 10006 enum vmcs_access { 10007 ACCESS_VMREAD, 10008 ACCESS_VMWRITE, 10009 ACCESS_NONE, 10010 }; 10011 10012 struct vmcs_shadow_test_common { 10013 enum vmcs_access op; 10014 enum Reason reason; 10015 u64 field; 10016 u64 value; 10017 u64 flags; 10018 u64 time; 10019 } l1_l2_common; 10020 10021 static inline u64 vmread_flags(u64 field, u64 *val) 10022 { 10023 u64 flags; 10024 10025 asm volatile ("vmread %2, %1; pushf; pop %0" 10026 : "=r" (flags), "=rm" (*val) : "r" (field) : "cc"); 10027 return flags & X86_EFLAGS_ALU; 10028 } 10029 10030 static inline u64 vmwrite_flags(u64 field, u64 val) 10031 { 10032 u64 flags; 10033 10034 asm volatile ("vmwrite %1, %2; pushf; pop %0" 10035 : "=r"(flags) : "rm" (val), "r" (field) : "cc"); 10036 return flags & X86_EFLAGS_ALU; 10037 } 10038 10039 static void vmx_vmcs_shadow_test_guest(void) 10040 { 10041 struct vmcs_shadow_test_common *c = &l1_l2_common; 10042 u64 start; 10043 10044 while (c->op != ACCESS_NONE) { 10045 start = rdtsc(); 10046 switch (c->op) { 10047 default: 10048 c->flags = -1ull; 10049 break; 10050 case ACCESS_VMREAD: 10051 c->flags = vmread_flags(c->field, &c->value); 10052 break; 10053 case ACCESS_VMWRITE: 10054 c->flags = vmwrite_flags(c->field, 0); 10055 break; 10056 } 10057 c->time = rdtsc() - start; 10058 vmcall(); 10059 } 10060 } 10061 10062 static u64 vmread_from_shadow(u64 field) 10063 { 10064 struct vmcs *primary; 10065 struct vmcs *shadow; 10066 u64 value; 10067 10068 TEST_ASSERT(!vmcs_save(&primary)); 10069 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 10070 TEST_ASSERT(!make_vmcs_current(shadow)); 10071 value = vmcs_read(field); 10072 TEST_ASSERT(!make_vmcs_current(primary)); 10073 return value; 10074 } 10075 10076 static u64 vmwrite_to_shadow(u64 field, u64 value) 10077 { 10078 struct vmcs *primary; 10079 struct vmcs *shadow; 10080 10081 TEST_ASSERT(!vmcs_save(&primary)); 10082 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 10083 TEST_ASSERT(!make_vmcs_current(shadow)); 10084 vmcs_write(field, value); 10085 value = vmcs_read(field); 10086 TEST_ASSERT(!make_vmcs_current(primary)); 10087 return value; 10088 } 10089 10090 static void vmcs_shadow_test_access(u8 *bitmap[2], enum vmcs_access access) 10091 { 10092 struct vmcs_shadow_test_common *c = &l1_l2_common; 10093 10094 c->op = access; 10095 vmcs_write(VMX_INST_ERROR, 0); 10096 enter_guest(); 10097 c->reason = vmcs_read(EXI_REASON) & 0xffff; 10098 if (c->reason != VMX_VMCALL) { 10099 skip_exit_insn(); 10100 enter_guest(); 10101 } 10102 skip_exit_vmcall(); 10103 } 10104 10105 static void vmcs_shadow_test_field(u8 *bitmap[2], u64 field) 10106 { 10107 struct vmcs_shadow_test_common *c = &l1_l2_common; 10108 struct vmcs *shadow; 10109 u64 value; 10110 uintptr_t flags[2]; 10111 bool good_shadow; 10112 u32 vmx_inst_error; 10113 10114 report_prefix_pushf("field %lx", field); 10115 c->field = field; 10116 10117 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 10118 if (shadow != (struct vmcs *)-1ull) { 10119 flags[ACCESS_VMREAD] = vmread_flags(field, &value); 10120 flags[ACCESS_VMWRITE] = vmwrite_flags(field, value); 10121 good_shadow = !flags[ACCESS_VMREAD] && !flags[ACCESS_VMWRITE]; 10122 } else { 10123 /* 10124 * When VMCS link pointer is -1ull, VMWRITE/VMREAD on 10125 * shadowed-fields should fail with setting RFLAGS.CF. 10126 */ 10127 flags[ACCESS_VMREAD] = X86_EFLAGS_CF; 10128 flags[ACCESS_VMWRITE] = X86_EFLAGS_CF; 10129 good_shadow = false; 10130 } 10131 10132 /* Intercept both VMREAD and VMWRITE. */ 10133 report_prefix_push("no VMREAD/VMWRITE permission"); 10134 /* VMWRITE/VMREAD done on reserved-bit should always intercept */ 10135 if (!(field >> VMCS_FIELD_RESERVED_SHIFT)) { 10136 set_bit(field, bitmap[ACCESS_VMREAD]); 10137 set_bit(field, bitmap[ACCESS_VMWRITE]); 10138 } 10139 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10140 report(c->reason == VMX_VMWRITE, "not shadowed for VMWRITE"); 10141 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10142 report(c->reason == VMX_VMREAD, "not shadowed for VMREAD"); 10143 report_prefix_pop(); 10144 10145 if (field >> VMCS_FIELD_RESERVED_SHIFT) 10146 goto out; 10147 10148 /* Permit shadowed VMREAD. */ 10149 report_prefix_push("VMREAD permission only"); 10150 clear_bit(field, bitmap[ACCESS_VMREAD]); 10151 set_bit(field, bitmap[ACCESS_VMWRITE]); 10152 if (good_shadow) 10153 value = vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 10154 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10155 report(c->reason == VMX_VMWRITE, "not shadowed for VMWRITE"); 10156 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10157 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10158 report(c->reason == VMX_VMCALL, "shadowed for VMREAD (in %ld cycles)", 10159 c->time); 10160 report(c->flags == flags[ACCESS_VMREAD], 10161 "ALU flags after VMREAD (%lx) are as expected (%lx)", 10162 c->flags, flags[ACCESS_VMREAD]); 10163 if (good_shadow) 10164 report(c->value == value, 10165 "value read from shadow (%lx) is as expected (%lx)", 10166 c->value, value); 10167 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 10168 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10169 "VMX_INST_ERROR (%d) is as expected (%d)", 10170 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10171 report_prefix_pop(); 10172 10173 /* Permit shadowed VMWRITE. */ 10174 report_prefix_push("VMWRITE permission only"); 10175 set_bit(field, bitmap[ACCESS_VMREAD]); 10176 clear_bit(field, bitmap[ACCESS_VMWRITE]); 10177 if (good_shadow) 10178 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 10179 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10180 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10181 report(c->reason == VMX_VMCALL, 10182 "shadowed for VMWRITE (in %ld cycles)", 10183 c->time); 10184 report(c->flags == flags[ACCESS_VMREAD], 10185 "ALU flags after VMWRITE (%lx) are as expected (%lx)", 10186 c->flags, flags[ACCESS_VMREAD]); 10187 if (good_shadow) { 10188 value = vmread_from_shadow(field); 10189 report(value == 0, 10190 "shadow VMCS value (%lx) is as expected (%lx)", value, 10191 0ul); 10192 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 10193 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10194 "VMX_INST_ERROR (%d) is as expected (%d)", 10195 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10196 } 10197 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10198 report(c->reason == VMX_VMREAD, "not shadowed for VMREAD"); 10199 report_prefix_pop(); 10200 10201 /* Permit shadowed VMREAD and VMWRITE. */ 10202 report_prefix_push("VMREAD and VMWRITE permission"); 10203 clear_bit(field, bitmap[ACCESS_VMREAD]); 10204 clear_bit(field, bitmap[ACCESS_VMWRITE]); 10205 if (good_shadow) 10206 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 10207 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10208 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10209 report(c->reason == VMX_VMCALL, 10210 "shadowed for VMWRITE (in %ld cycles)", 10211 c->time); 10212 report(c->flags == flags[ACCESS_VMREAD], 10213 "ALU flags after VMWRITE (%lx) are as expected (%lx)", 10214 c->flags, flags[ACCESS_VMREAD]); 10215 if (good_shadow) { 10216 value = vmread_from_shadow(field); 10217 report(value == 0, 10218 "shadow VMCS value (%lx) is as expected (%lx)", value, 10219 0ul); 10220 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 10221 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10222 "VMX_INST_ERROR (%d) is as expected (%d)", 10223 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10224 } 10225 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10226 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10227 report(c->reason == VMX_VMCALL, "shadowed for VMREAD (in %ld cycles)", 10228 c->time); 10229 report(c->flags == flags[ACCESS_VMREAD], 10230 "ALU flags after VMREAD (%lx) are as expected (%lx)", 10231 c->flags, flags[ACCESS_VMREAD]); 10232 if (good_shadow) 10233 report(c->value == 0, 10234 "value read from shadow (%lx) is as expected (%lx)", 10235 c->value, 0ul); 10236 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 10237 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10238 "VMX_INST_ERROR (%d) is as expected (%d)", 10239 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10240 report_prefix_pop(); 10241 10242 out: 10243 report_prefix_pop(); 10244 } 10245 10246 static void vmx_vmcs_shadow_test_body(u8 *bitmap[2]) 10247 { 10248 unsigned base; 10249 unsigned index; 10250 unsigned bit; 10251 unsigned highest_index = rdmsr(MSR_IA32_VMX_VMCS_ENUM); 10252 10253 /* Run test on all possible valid VMCS fields */ 10254 for (base = 0; 10255 base < (1 << VMCS_FIELD_RESERVED_SHIFT); 10256 base += (1 << VMCS_FIELD_TYPE_SHIFT)) 10257 for (index = 0; index <= highest_index; index++) 10258 vmcs_shadow_test_field(bitmap, base + index); 10259 10260 /* 10261 * Run tests on some invalid VMCS fields 10262 * (Have reserved bit set). 10263 */ 10264 for (bit = VMCS_FIELD_RESERVED_SHIFT; bit < VMCS_FIELD_BIT_SIZE; bit++) 10265 vmcs_shadow_test_field(bitmap, (1ull << bit)); 10266 } 10267 10268 static void vmx_vmcs_shadow_test(void) 10269 { 10270 u8 *bitmap[2]; 10271 struct vmcs *shadow; 10272 10273 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 10274 printf("\t'Activate secondary controls' not supported.\n"); 10275 return; 10276 } 10277 10278 if (!(ctrl_cpu_rev[1].clr & CPU_SHADOW_VMCS)) { 10279 printf("\t'VMCS shadowing' not supported.\n"); 10280 return; 10281 } 10282 10283 if (!(rdmsr(MSR_IA32_VMX_MISC) & 10284 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS)) { 10285 printf("\tVMWRITE can't modify VM-exit information fields.\n"); 10286 return; 10287 } 10288 10289 test_set_guest(vmx_vmcs_shadow_test_guest); 10290 10291 bitmap[ACCESS_VMREAD] = alloc_page(); 10292 bitmap[ACCESS_VMWRITE] = alloc_page(); 10293 10294 vmcs_write(VMREAD_BITMAP, virt_to_phys(bitmap[ACCESS_VMREAD])); 10295 vmcs_write(VMWRITE_BITMAP, virt_to_phys(bitmap[ACCESS_VMWRITE])); 10296 10297 shadow = alloc_page(); 10298 shadow->hdr.revision_id = basic.revision; 10299 shadow->hdr.shadow_vmcs = 1; 10300 TEST_ASSERT(!vmcs_clear(shadow)); 10301 10302 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_RDTSC); 10303 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY); 10304 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_SHADOW_VMCS); 10305 10306 vmcs_write(VMCS_LINK_PTR, virt_to_phys(shadow)); 10307 report_prefix_push("valid link pointer"); 10308 vmx_vmcs_shadow_test_body(bitmap); 10309 report_prefix_pop(); 10310 10311 vmcs_write(VMCS_LINK_PTR, -1ull); 10312 report_prefix_push("invalid link pointer"); 10313 vmx_vmcs_shadow_test_body(bitmap); 10314 report_prefix_pop(); 10315 10316 l1_l2_common.op = ACCESS_NONE; 10317 enter_guest(); 10318 } 10319 10320 /* 10321 * This test monitors the difference between a guest RDTSC instruction 10322 * and the IA32_TIME_STAMP_COUNTER MSR value stored in the VMCS12 10323 * VM-exit MSR-store list when taking a VM-exit on the instruction 10324 * following RDTSC. 10325 */ 10326 #define RDTSC_DIFF_ITERS 100000 10327 #define RDTSC_DIFF_FAILS 100 10328 #define HOST_CAPTURED_GUEST_TSC_DIFF_THRESHOLD 750 10329 10330 /* 10331 * Set 'use TSC offsetting' and set the guest offset to the 10332 * inverse of the host's current TSC value, so that the guest starts running 10333 * with an effective TSC value of 0. 10334 */ 10335 static void reset_guest_tsc_to_zero(void) 10336 { 10337 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_USE_TSC_OFFSET); 10338 vmcs_write(TSC_OFFSET, -rdtsc()); 10339 } 10340 10341 static void rdtsc_vmexit_diff_test_guest(void) 10342 { 10343 int i; 10344 10345 for (i = 0; i < RDTSC_DIFF_ITERS; i++) 10346 /* Ensure rdtsc is the last instruction before the vmcall. */ 10347 asm volatile("rdtsc; vmcall" : : : "eax", "edx"); 10348 } 10349 10350 /* 10351 * This function only considers the "use TSC offsetting" VM-execution 10352 * control. It does not handle "use TSC scaling" (because the latter 10353 * isn't available to the host today.) 10354 */ 10355 static unsigned long long host_time_to_guest_time(unsigned long long t) 10356 { 10357 TEST_ASSERT(!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 10358 !(vmcs_read(CPU_EXEC_CTRL1) & CPU_USE_TSC_SCALING)); 10359 10360 if (vmcs_read(CPU_EXEC_CTRL0) & CPU_USE_TSC_OFFSET) 10361 t += vmcs_read(TSC_OFFSET); 10362 10363 return t; 10364 } 10365 10366 static unsigned long long rdtsc_vmexit_diff_test_iteration(void) 10367 { 10368 unsigned long long guest_tsc, host_to_guest_tsc; 10369 10370 enter_guest(); 10371 skip_exit_vmcall(); 10372 guest_tsc = (u32) regs.rax + (regs.rdx << 32); 10373 host_to_guest_tsc = host_time_to_guest_time(exit_msr_store[0].value); 10374 10375 return host_to_guest_tsc - guest_tsc; 10376 } 10377 10378 static void rdtsc_vmexit_diff_test(void) 10379 { 10380 unsigned long long delta; 10381 int fail = 0; 10382 int i; 10383 10384 if (!(ctrl_cpu_rev[0].clr & CPU_USE_TSC_OFFSET)) 10385 test_skip("CPU doesn't support the 'use TSC offsetting' processor-based VM-execution control.\n"); 10386 10387 test_set_guest(rdtsc_vmexit_diff_test_guest); 10388 10389 reset_guest_tsc_to_zero(); 10390 10391 /* 10392 * Set up the VMCS12 VM-exit MSR-store list to store just one 10393 * MSR: IA32_TIME_STAMP_COUNTER. Note that the value stored is 10394 * in the host time domain (i.e., it is not adjusted according 10395 * to the TSC multiplier and TSC offset fields in the VMCS12, 10396 * as a guest RDTSC would be.) 10397 */ 10398 exit_msr_store = alloc_page(); 10399 exit_msr_store[0].index = MSR_IA32_TSC; 10400 vmcs_write(EXI_MSR_ST_CNT, 1); 10401 vmcs_write(EXIT_MSR_ST_ADDR, virt_to_phys(exit_msr_store)); 10402 10403 for (i = 0; i < RDTSC_DIFF_ITERS && fail < RDTSC_DIFF_FAILS; i++) { 10404 delta = rdtsc_vmexit_diff_test_iteration(); 10405 if (delta >= HOST_CAPTURED_GUEST_TSC_DIFF_THRESHOLD) 10406 fail++; 10407 } 10408 10409 enter_guest(); 10410 10411 report(fail < RDTSC_DIFF_FAILS, 10412 "RDTSC to VM-exit delta too high in %d of %d iterations, last = %llu", 10413 fail, i, delta); 10414 } 10415 10416 static int invalid_msr_init(struct vmcs *vmcs) 10417 { 10418 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 10419 printf("\tPreemption timer is not supported\n"); 10420 return VMX_TEST_EXIT; 10421 } 10422 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 10423 preempt_val = 10000000; 10424 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 10425 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 10426 10427 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 10428 printf("\tSave preemption value is not supported\n"); 10429 10430 vmcs_write(ENT_MSR_LD_CNT, 1); 10431 vmcs_write(ENTER_MSR_LD_ADDR, (u64)0x13370000); 10432 10433 return VMX_TEST_START; 10434 } 10435 10436 10437 static void invalid_msr_main(void) 10438 { 10439 report_fail("Invalid MSR load"); 10440 } 10441 10442 static int invalid_msr_exit_handler(union exit_reason exit_reason) 10443 { 10444 report_fail("Invalid MSR load"); 10445 print_vmexit_info(exit_reason); 10446 return VMX_TEST_EXIT; 10447 } 10448 10449 static int invalid_msr_entry_failure(struct vmentry_result *result) 10450 { 10451 report(result->exit_reason.failed_vmentry && 10452 result->exit_reason.basic == VMX_FAIL_MSR, "Invalid MSR load"); 10453 return VMX_TEST_VMEXIT; 10454 } 10455 10456 /* 10457 * The max number of MSRs in an atomic switch MSR list is: 10458 * (111B + 1) * 512 = 4096 10459 * 10460 * Each list entry consumes: 10461 * 4-byte MSR index + 4 bytes reserved + 8-byte data = 16 bytes 10462 * 10463 * Allocate 128 kB to cover max_msr_list_size (i.e., 64 kB) and then some. 10464 */ 10465 static const u32 msr_list_page_order = 5; 10466 10467 static void atomic_switch_msr_limit_test_guest(void) 10468 { 10469 vmcall(); 10470 } 10471 10472 static void populate_msr_list(struct vmx_msr_entry *msr_list, 10473 size_t byte_capacity, int count) 10474 { 10475 int i; 10476 10477 for (i = 0; i < count; i++) { 10478 msr_list[i].index = MSR_IA32_TSC; 10479 msr_list[i].reserved = 0; 10480 msr_list[i].value = 0x1234567890abcdef; 10481 } 10482 10483 memset(msr_list + count, 0xff, 10484 byte_capacity - count * sizeof(*msr_list)); 10485 } 10486 10487 static int max_msr_list_size(void) 10488 { 10489 u32 vmx_misc = rdmsr(MSR_IA32_VMX_MISC); 10490 u32 factor = ((vmx_misc & GENMASK(27, 25)) >> 25) + 1; 10491 10492 return factor * 512; 10493 } 10494 10495 static void atomic_switch_msrs_test(int count) 10496 { 10497 struct vmx_msr_entry *vm_enter_load; 10498 struct vmx_msr_entry *vm_exit_load; 10499 struct vmx_msr_entry *vm_exit_store; 10500 int max_allowed = max_msr_list_size(); 10501 int byte_capacity = 1ul << (msr_list_page_order + PAGE_SHIFT); 10502 /* Exceeding the max MSR list size at exit triggers KVM to abort. */ 10503 int exit_count = count > max_allowed ? max_allowed : count; 10504 int cleanup_count = count > max_allowed ? 2 : 1; 10505 int i; 10506 10507 /* 10508 * Check for the IA32_TSC MSR, 10509 * available with the "TSC flag" and used to populate the MSR lists. 10510 */ 10511 if (!(cpuid(1).d & (1 << 4))) { 10512 report_skip(__func__); 10513 return; 10514 } 10515 10516 /* Set L2 guest. */ 10517 test_set_guest(atomic_switch_msr_limit_test_guest); 10518 10519 /* Setup atomic MSR switch lists. */ 10520 vm_enter_load = alloc_pages(msr_list_page_order); 10521 vm_exit_load = alloc_pages(msr_list_page_order); 10522 vm_exit_store = alloc_pages(msr_list_page_order); 10523 10524 vmcs_write(ENTER_MSR_LD_ADDR, (u64)vm_enter_load); 10525 vmcs_write(EXIT_MSR_LD_ADDR, (u64)vm_exit_load); 10526 vmcs_write(EXIT_MSR_ST_ADDR, (u64)vm_exit_store); 10527 10528 /* 10529 * VM-Enter should succeed up to the max number of MSRs per list, and 10530 * should not consume junk beyond the last entry. 10531 */ 10532 populate_msr_list(vm_enter_load, byte_capacity, count); 10533 populate_msr_list(vm_exit_load, byte_capacity, exit_count); 10534 populate_msr_list(vm_exit_store, byte_capacity, exit_count); 10535 10536 vmcs_write(ENT_MSR_LD_CNT, count); 10537 vmcs_write(EXI_MSR_LD_CNT, exit_count); 10538 vmcs_write(EXI_MSR_ST_CNT, exit_count); 10539 10540 if (count <= max_allowed) { 10541 enter_guest(); 10542 assert_exit_reason(VMX_VMCALL); 10543 skip_exit_vmcall(); 10544 } else { 10545 u32 exit_qual; 10546 10547 test_guest_state("Invalid MSR Load Count", true, count, 10548 "ENT_MSR_LD_CNT"); 10549 10550 exit_qual = vmcs_read(EXI_QUALIFICATION); 10551 report(exit_qual == max_allowed + 1, "exit_qual, %u, is %u.", 10552 exit_qual, max_allowed + 1); 10553 } 10554 10555 /* Cleanup. */ 10556 vmcs_write(ENT_MSR_LD_CNT, 0); 10557 vmcs_write(EXI_MSR_LD_CNT, 0); 10558 vmcs_write(EXI_MSR_ST_CNT, 0); 10559 for (i = 0; i < cleanup_count; i++) { 10560 enter_guest(); 10561 skip_exit_vmcall(); 10562 } 10563 free_pages_by_order(vm_enter_load, msr_list_page_order); 10564 free_pages_by_order(vm_exit_load, msr_list_page_order); 10565 free_pages_by_order(vm_exit_store, msr_list_page_order); 10566 } 10567 10568 static void atomic_switch_max_msrs_test(void) 10569 { 10570 atomic_switch_msrs_test(max_msr_list_size()); 10571 } 10572 10573 static void atomic_switch_overflow_msrs_test(void) 10574 { 10575 if (test_device_enabled()) 10576 atomic_switch_msrs_test(max_msr_list_size() + 1); 10577 else 10578 test_skip("Test is only supported on KVM"); 10579 } 10580 10581 static void vmx_pf_exception_test_guest(void) 10582 { 10583 ac_test_run(PT_LEVEL_PML4); 10584 } 10585 10586 typedef void (*invalidate_tlb_t)(void *data); 10587 10588 static void __vmx_pf_exception_test(invalidate_tlb_t inv_fn, void *data) 10589 { 10590 u64 efer; 10591 struct cpuid cpuid; 10592 10593 test_set_guest(vmx_pf_exception_test_guest); 10594 10595 /* Intercept INVLPG when to perform TLB invalidation from L1 (this). */ 10596 if (inv_fn) 10597 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INVLPG); 10598 else 10599 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INVLPG); 10600 10601 enter_guest(); 10602 10603 while (vmcs_read(EXI_REASON) != VMX_VMCALL) { 10604 switch (vmcs_read(EXI_REASON)) { 10605 case VMX_RDMSR: 10606 assert(regs.rcx == MSR_EFER); 10607 efer = vmcs_read(GUEST_EFER); 10608 regs.rdx = efer >> 32; 10609 regs.rax = efer & 0xffffffff; 10610 break; 10611 case VMX_WRMSR: 10612 assert(regs.rcx == MSR_EFER); 10613 efer = regs.rdx << 32 | (regs.rax & 0xffffffff); 10614 vmcs_write(GUEST_EFER, efer); 10615 break; 10616 case VMX_CPUID: 10617 cpuid = (struct cpuid) {0, 0, 0, 0}; 10618 cpuid = raw_cpuid(regs.rax, regs.rcx); 10619 regs.rax = cpuid.a; 10620 regs.rbx = cpuid.b; 10621 regs.rcx = cpuid.c; 10622 regs.rdx = cpuid.d; 10623 break; 10624 case VMX_INVLPG: 10625 inv_fn(data); 10626 break; 10627 default: 10628 assert_msg(false, 10629 "Unexpected exit to L1, exit_reason: %s (0x%lx)", 10630 exit_reason_description(vmcs_read(EXI_REASON)), 10631 vmcs_read(EXI_REASON)); 10632 } 10633 skip_exit_insn(); 10634 enter_guest(); 10635 } 10636 10637 assert_exit_reason(VMX_VMCALL); 10638 } 10639 10640 static void vmx_pf_exception_test(void) 10641 { 10642 __vmx_pf_exception_test(NULL, NULL); 10643 } 10644 10645 static void invalidate_tlb_no_vpid(void *data) 10646 { 10647 /* If VPID is disabled, the TLB is flushed on VM-Enter and VM-Exit. */ 10648 } 10649 10650 static void vmx_pf_no_vpid_test(void) 10651 { 10652 if (is_vpid_supported()) 10653 vmcs_clear_bits(CPU_EXEC_CTRL1, CPU_VPID); 10654 10655 __vmx_pf_exception_test(invalidate_tlb_no_vpid, NULL); 10656 } 10657 10658 static void invalidate_tlb_invvpid_addr(void *data) 10659 { 10660 invvpid(INVVPID_ALL, *(u16 *)data, vmcs_read(EXI_QUALIFICATION)); 10661 } 10662 10663 static void invalidate_tlb_new_vpid(void *data) 10664 { 10665 u16 *vpid = data; 10666 10667 /* 10668 * Bump VPID to effectively flush L2's TLB from L0's perspective. 10669 * Invalidate all VPIDs when the VPID wraps to zero as hardware/KVM is 10670 * architecturally allowed to keep TLB entries indefinitely. 10671 */ 10672 ++(*vpid); 10673 if (*vpid == 0) { 10674 ++(*vpid); 10675 invvpid(INVVPID_ALL, 0, 0); 10676 } 10677 vmcs_write(VPID, *vpid); 10678 } 10679 10680 static void __vmx_pf_vpid_test(invalidate_tlb_t inv_fn, u16 vpid) 10681 { 10682 if (!is_vpid_supported()) 10683 test_skip("VPID unsupported"); 10684 10685 if (!is_invvpid_supported()) 10686 test_skip("INVVPID unsupported"); 10687 10688 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY); 10689 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_VPID); 10690 vmcs_write(VPID, vpid); 10691 10692 __vmx_pf_exception_test(inv_fn, &vpid); 10693 } 10694 10695 static void vmx_pf_invvpid_test(void) 10696 { 10697 if (!is_invvpid_type_supported(INVVPID_ADDR)) 10698 test_skip("INVVPID ADDR unsupported"); 10699 10700 __vmx_pf_vpid_test(invalidate_tlb_invvpid_addr, 0xaaaa); 10701 } 10702 10703 static void vmx_pf_vpid_test(void) 10704 { 10705 /* Need INVVPID(ALL) to flush VPIDs upon wrap/reuse. */ 10706 if (!is_invvpid_type_supported(INVVPID_ALL)) 10707 test_skip("INVVPID ALL unsupported"); 10708 10709 __vmx_pf_vpid_test(invalidate_tlb_new_vpid, 1); 10710 } 10711 10712 static void vmx_l2_gp_test(void) 10713 { 10714 *(volatile u64 *)NONCANONICAL = 0; 10715 } 10716 10717 static void vmx_l2_ud_test(void) 10718 { 10719 asm volatile ("ud2"); 10720 } 10721 10722 static void vmx_l2_de_test(void) 10723 { 10724 asm volatile ( 10725 "xor %%eax, %%eax\n\t" 10726 "xor %%ebx, %%ebx\n\t" 10727 "xor %%edx, %%edx\n\t" 10728 "idiv %%ebx\n\t" 10729 ::: "eax", "ebx", "edx"); 10730 } 10731 10732 static void vmx_l2_bp_test(void) 10733 { 10734 asm volatile ("int3"); 10735 } 10736 10737 static void vmx_l2_db_test(void) 10738 { 10739 write_rflags(read_rflags() | X86_EFLAGS_TF); 10740 } 10741 10742 static uint64_t usermode_callback(void) 10743 { 10744 /* 10745 * Trigger an #AC by writing 8 bytes to a 4-byte aligned address. 10746 * Disclaimer: It is assumed that the stack pointer is aligned 10747 * on a 16-byte boundary as x86_64 stacks should be. 10748 */ 10749 asm volatile("movq $0, -0x4(%rsp)"); 10750 10751 return 0; 10752 } 10753 10754 static void vmx_l2_ac_test(void) 10755 { 10756 bool hit_ac = false; 10757 10758 write_cr0(read_cr0() | X86_CR0_AM); 10759 write_rflags(read_rflags() | X86_EFLAGS_AC); 10760 10761 run_in_user(usermode_callback, AC_VECTOR, 0, 0, 0, 0, &hit_ac); 10762 report(hit_ac, "Usermode #AC handled in L2"); 10763 vmcall(); 10764 } 10765 10766 struct vmx_exception_test { 10767 u8 vector; 10768 void (*guest_code)(void); 10769 }; 10770 10771 struct vmx_exception_test vmx_exception_tests[] = { 10772 { GP_VECTOR, vmx_l2_gp_test }, 10773 { UD_VECTOR, vmx_l2_ud_test }, 10774 { DE_VECTOR, vmx_l2_de_test }, 10775 { DB_VECTOR, vmx_l2_db_test }, 10776 { BP_VECTOR, vmx_l2_bp_test }, 10777 { AC_VECTOR, vmx_l2_ac_test }, 10778 }; 10779 10780 static u8 vmx_exception_test_vector; 10781 10782 static void vmx_exception_handler(struct ex_regs *regs) 10783 { 10784 report(regs->vector == vmx_exception_test_vector, 10785 "Handling %s in L2's exception handler", 10786 exception_mnemonic(vmx_exception_test_vector)); 10787 vmcall(); 10788 } 10789 10790 static void handle_exception_in_l2(u8 vector) 10791 { 10792 handler old_handler = handle_exception(vector, vmx_exception_handler); 10793 10794 vmx_exception_test_vector = vector; 10795 10796 enter_guest(); 10797 report(vmcs_read(EXI_REASON) == VMX_VMCALL, 10798 "%s handled by L2", exception_mnemonic(vector)); 10799 10800 handle_exception(vector, old_handler); 10801 } 10802 10803 static void handle_exception_in_l1(u32 vector) 10804 { 10805 u32 old_eb = vmcs_read(EXC_BITMAP); 10806 10807 vmcs_write(EXC_BITMAP, old_eb | (1u << vector)); 10808 10809 enter_guest(); 10810 10811 report((vmcs_read(EXI_REASON) == VMX_EXC_NMI) && 10812 ((vmcs_read(EXI_INTR_INFO) & 0xff) == vector), 10813 "%s handled by L1", exception_mnemonic(vector)); 10814 10815 vmcs_write(EXC_BITMAP, old_eb); 10816 } 10817 10818 static void vmx_exception_test(void) 10819 { 10820 struct vmx_exception_test *t; 10821 int i; 10822 10823 for (i = 0; i < ARRAY_SIZE(vmx_exception_tests); i++) { 10824 t = &vmx_exception_tests[i]; 10825 10826 /* 10827 * Override the guest code before each run even though it's the 10828 * same code, the VMCS guest state needs to be reinitialized. 10829 */ 10830 test_override_guest(t->guest_code); 10831 handle_exception_in_l2(t->vector); 10832 10833 test_override_guest(t->guest_code); 10834 handle_exception_in_l1(t->vector); 10835 } 10836 10837 test_set_guest_finished(); 10838 } 10839 10840 #define TEST(name) { #name, .v2 = name } 10841 10842 /* name/init/guest_main/exit_handler/syscall_handler/guest_regs */ 10843 struct vmx_test vmx_tests[] = { 10844 { "null", NULL, basic_guest_main, basic_exit_handler, NULL, {0} }, 10845 { "vmenter", NULL, vmenter_main, vmenter_exit_handler, NULL, {0} }, 10846 { "preemption timer", preemption_timer_init, preemption_timer_main, 10847 preemption_timer_exit_handler, NULL, {0} }, 10848 { "control field PAT", test_ctrl_pat_init, test_ctrl_pat_main, 10849 test_ctrl_pat_exit_handler, NULL, {0} }, 10850 { "control field EFER", test_ctrl_efer_init, test_ctrl_efer_main, 10851 test_ctrl_efer_exit_handler, NULL, {0} }, 10852 { "CR shadowing", NULL, cr_shadowing_main, 10853 cr_shadowing_exit_handler, NULL, {0} }, 10854 { "I/O bitmap", iobmp_init, iobmp_main, iobmp_exit_handler, 10855 NULL, {0} }, 10856 { "instruction intercept", insn_intercept_init, insn_intercept_main, 10857 insn_intercept_exit_handler, NULL, {0} }, 10858 { "EPT A/D disabled", ept_init, ept_main, ept_exit_handler, NULL, {0} }, 10859 { "EPT A/D enabled", eptad_init, eptad_main, eptad_exit_handler, NULL, {0} }, 10860 { "PML", pml_init, pml_main, pml_exit_handler, NULL, {0} }, 10861 { "interrupt", interrupt_init, interrupt_main, 10862 interrupt_exit_handler, NULL, {0} }, 10863 { "nmi_hlt", nmi_hlt_init, nmi_hlt_main, 10864 nmi_hlt_exit_handler, NULL, {0} }, 10865 { "debug controls", dbgctls_init, dbgctls_main, dbgctls_exit_handler, 10866 NULL, {0} }, 10867 { "MSR switch", msr_switch_init, msr_switch_main, 10868 msr_switch_exit_handler, NULL, {0}, msr_switch_entry_failure }, 10869 { "vmmcall", vmmcall_init, vmmcall_main, vmmcall_exit_handler, NULL, {0} }, 10870 { "disable RDTSCP", disable_rdtscp_init, disable_rdtscp_main, 10871 disable_rdtscp_exit_handler, NULL, {0} }, 10872 { "int3", int3_init, int3_guest_main, int3_exit_handler, NULL, {0} }, 10873 { "into", into_init, into_guest_main, into_exit_handler, NULL, {0} }, 10874 { "exit_monitor_from_l2_test", NULL, exit_monitor_from_l2_main, 10875 exit_monitor_from_l2_handler, NULL, {0} }, 10876 { "invalid_msr", invalid_msr_init, invalid_msr_main, 10877 invalid_msr_exit_handler, NULL, {0}, invalid_msr_entry_failure}, 10878 /* Basic V2 tests. */ 10879 TEST(v2_null_test), 10880 TEST(v2_multiple_entries_test), 10881 TEST(fixture_test_case1), 10882 TEST(fixture_test_case2), 10883 /* Opcode tests. */ 10884 TEST(invvpid_test), 10885 /* VM-entry tests */ 10886 TEST(vmx_controls_test), 10887 TEST(vmx_host_state_area_test), 10888 TEST(vmx_guest_state_area_test), 10889 TEST(vmentry_movss_shadow_test), 10890 TEST(vmentry_unrestricted_guest_test), 10891 /* APICv tests */ 10892 TEST(vmx_eoi_bitmap_ioapic_scan_test), 10893 TEST(vmx_hlt_with_rvi_test), 10894 TEST(apic_reg_virt_test), 10895 TEST(virt_x2apic_mode_test), 10896 /* APIC pass-through tests */ 10897 TEST(vmx_apic_passthrough_test), 10898 TEST(vmx_apic_passthrough_thread_test), 10899 TEST(vmx_apic_passthrough_tpr_threshold_test), 10900 TEST(vmx_init_signal_test), 10901 TEST(vmx_sipi_signal_test), 10902 /* VMCS Shadowing tests */ 10903 TEST(vmx_vmcs_shadow_test), 10904 /* Regression tests */ 10905 TEST(vmx_ldtr_test), 10906 TEST(vmx_cr_load_test), 10907 TEST(vmx_cr4_osxsave_test), 10908 TEST(vmx_nm_test), 10909 TEST(vmx_db_test), 10910 TEST(vmx_nmi_window_test), 10911 TEST(vmx_intr_window_test), 10912 TEST(vmx_pending_event_test), 10913 TEST(vmx_pending_event_hlt_test), 10914 TEST(vmx_store_tsc_test), 10915 TEST(vmx_preemption_timer_zero_test), 10916 TEST(vmx_preemption_timer_tf_test), 10917 TEST(vmx_preemption_timer_expiry_test), 10918 /* EPT access tests. */ 10919 TEST(ept_access_test_not_present), 10920 TEST(ept_access_test_read_only), 10921 TEST(ept_access_test_write_only), 10922 TEST(ept_access_test_read_write), 10923 TEST(ept_access_test_execute_only), 10924 TEST(ept_access_test_read_execute), 10925 TEST(ept_access_test_write_execute), 10926 TEST(ept_access_test_read_write_execute), 10927 TEST(ept_access_test_reserved_bits), 10928 TEST(ept_access_test_ignored_bits), 10929 TEST(ept_access_test_paddr_not_present_ad_disabled), 10930 TEST(ept_access_test_paddr_not_present_ad_enabled), 10931 TEST(ept_access_test_paddr_read_only_ad_disabled), 10932 TEST(ept_access_test_paddr_read_only_ad_enabled), 10933 TEST(ept_access_test_paddr_read_write), 10934 TEST(ept_access_test_paddr_read_write_execute), 10935 TEST(ept_access_test_paddr_read_execute_ad_disabled), 10936 TEST(ept_access_test_paddr_read_execute_ad_enabled), 10937 TEST(ept_access_test_paddr_not_present_page_fault), 10938 TEST(ept_access_test_force_2m_page), 10939 /* Atomic MSR switch tests. */ 10940 TEST(atomic_switch_max_msrs_test), 10941 TEST(atomic_switch_overflow_msrs_test), 10942 TEST(rdtsc_vmexit_diff_test), 10943 TEST(vmx_mtf_test), 10944 TEST(vmx_mtf_pdpte_test), 10945 TEST(vmx_pf_exception_test), 10946 TEST(vmx_pf_no_vpid_test), 10947 TEST(vmx_pf_invvpid_test), 10948 TEST(vmx_pf_vpid_test), 10949 TEST(vmx_exception_test), 10950 { NULL, NULL, NULL, NULL, NULL, {0} }, 10951 }; 10952