1 /* 2 * All test cases of nested virtualization should be in this file 3 * 4 * Author : Arthur Chunqi Li <yzt356@gmail.com> 5 */ 6 7 #include <asm/debugreg.h> 8 9 #include "vmx.h" 10 #include "msr.h" 11 #include "processor.h" 12 #include "vm.h" 13 #include "pci.h" 14 #include "fwcfg.h" 15 #include "isr.h" 16 #include "desc.h" 17 #include "apic.h" 18 #include "types.h" 19 #include "vmalloc.h" 20 #include "alloc_page.h" 21 #include "smp.h" 22 #include "delay.h" 23 #include "access.h" 24 25 #define VPID_CAP_INVVPID_TYPES_SHIFT 40 26 27 u64 ia32_pat; 28 u64 ia32_efer; 29 void *io_bitmap_a, *io_bitmap_b; 30 u16 ioport; 31 32 unsigned long *pml4; 33 u64 eptp; 34 void *data_page1, *data_page2; 35 36 phys_addr_t pci_physaddr; 37 38 void *pml_log; 39 #define PML_INDEX 512 40 41 static inline unsigned ffs(unsigned x) 42 { 43 int pos = -1; 44 45 __asm__ __volatile__("bsf %1, %%eax; cmovnz %%eax, %0" 46 : "+r"(pos) : "rm"(x) : "eax"); 47 return pos + 1; 48 } 49 50 static inline void vmcall(void) 51 { 52 asm volatile("vmcall"); 53 } 54 55 static void basic_guest_main(void) 56 { 57 report_pass("Basic VMX test"); 58 } 59 60 static int basic_exit_handler(union exit_reason exit_reason) 61 { 62 report_fail("Basic VMX test"); 63 print_vmexit_info(exit_reason); 64 return VMX_TEST_EXIT; 65 } 66 67 static void vmenter_main(void) 68 { 69 u64 rax; 70 u64 rsp, resume_rsp; 71 72 report_pass("test vmlaunch"); 73 74 asm volatile( 75 "mov %%rsp, %0\n\t" 76 "mov %3, %%rax\n\t" 77 "vmcall\n\t" 78 "mov %%rax, %1\n\t" 79 "mov %%rsp, %2\n\t" 80 : "=r"(rsp), "=r"(rax), "=r"(resume_rsp) 81 : "g"(0xABCD)); 82 report((rax == 0xFFFF) && (rsp == resume_rsp), "test vmresume"); 83 } 84 85 static int vmenter_exit_handler(union exit_reason exit_reason) 86 { 87 u64 guest_rip = vmcs_read(GUEST_RIP); 88 89 switch (exit_reason.basic) { 90 case VMX_VMCALL: 91 if (regs.rax != 0xABCD) { 92 report_fail("test vmresume"); 93 return VMX_TEST_VMEXIT; 94 } 95 regs.rax = 0xFFFF; 96 vmcs_write(GUEST_RIP, guest_rip + 3); 97 return VMX_TEST_RESUME; 98 default: 99 report_fail("test vmresume"); 100 print_vmexit_info(exit_reason); 101 } 102 return VMX_TEST_VMEXIT; 103 } 104 105 u32 preempt_scale; 106 volatile unsigned long long tsc_val; 107 volatile u32 preempt_val; 108 u64 saved_rip; 109 110 static int preemption_timer_init(struct vmcs *vmcs) 111 { 112 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 113 printf("\tPreemption timer is not supported\n"); 114 return VMX_TEST_EXIT; 115 } 116 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 117 preempt_val = 10000000; 118 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 119 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 120 121 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 122 printf("\tSave preemption value is not supported\n"); 123 124 return VMX_TEST_START; 125 } 126 127 static void preemption_timer_main(void) 128 { 129 tsc_val = rdtsc(); 130 if (ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) { 131 vmx_set_test_stage(0); 132 vmcall(); 133 if (vmx_get_test_stage() == 1) 134 vmcall(); 135 } 136 vmx_set_test_stage(1); 137 while (vmx_get_test_stage() == 1) { 138 if (((rdtsc() - tsc_val) >> preempt_scale) 139 > 10 * preempt_val) { 140 vmx_set_test_stage(2); 141 vmcall(); 142 } 143 } 144 tsc_val = rdtsc(); 145 asm volatile ("hlt"); 146 vmcall(); 147 vmx_set_test_stage(5); 148 vmcall(); 149 } 150 151 static int preemption_timer_exit_handler(union exit_reason exit_reason) 152 { 153 bool guest_halted; 154 u64 guest_rip; 155 u32 insn_len; 156 u32 ctrl_exit; 157 158 guest_rip = vmcs_read(GUEST_RIP); 159 insn_len = vmcs_read(EXI_INST_LEN); 160 switch (exit_reason.basic) { 161 case VMX_PREEMPT: 162 switch (vmx_get_test_stage()) { 163 case 1: 164 case 2: 165 report(((rdtsc() - tsc_val) >> preempt_scale) >= preempt_val, 166 "busy-wait for preemption timer"); 167 vmx_set_test_stage(3); 168 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 169 return VMX_TEST_RESUME; 170 case 3: 171 guest_halted = 172 (vmcs_read(GUEST_ACTV_STATE) == ACTV_HLT); 173 report(((rdtsc() - tsc_val) >> preempt_scale) >= preempt_val 174 && guest_halted, 175 "preemption timer during hlt"); 176 vmx_set_test_stage(4); 177 vmcs_write(PIN_CONTROLS, 178 vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 179 vmcs_write(EXI_CONTROLS, 180 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_PREEMPT); 181 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 182 return VMX_TEST_RESUME; 183 case 4: 184 report(saved_rip == guest_rip, 185 "preemption timer with 0 value"); 186 break; 187 default: 188 report_fail("Invalid stage."); 189 print_vmexit_info(exit_reason); 190 break; 191 } 192 break; 193 case VMX_VMCALL: 194 vmcs_write(GUEST_RIP, guest_rip + insn_len); 195 switch (vmx_get_test_stage()) { 196 case 0: 197 report(vmcs_read(PREEMPT_TIMER_VALUE) == preempt_val, 198 "Keep preemption value"); 199 vmx_set_test_stage(1); 200 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 201 ctrl_exit = (vmcs_read(EXI_CONTROLS) | 202 EXI_SAVE_PREEMPT) & ctrl_exit_rev.clr; 203 vmcs_write(EXI_CONTROLS, ctrl_exit); 204 return VMX_TEST_RESUME; 205 case 1: 206 report(vmcs_read(PREEMPT_TIMER_VALUE) < preempt_val, 207 "Save preemption value"); 208 return VMX_TEST_RESUME; 209 case 2: 210 report_fail("busy-wait for preemption timer"); 211 vmx_set_test_stage(3); 212 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 213 return VMX_TEST_RESUME; 214 case 3: 215 report_fail("preemption timer during hlt"); 216 vmx_set_test_stage(4); 217 /* fall through */ 218 case 4: 219 vmcs_write(PIN_CONTROLS, 220 vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 221 vmcs_write(PREEMPT_TIMER_VALUE, 0); 222 saved_rip = guest_rip + insn_len; 223 return VMX_TEST_RESUME; 224 case 5: 225 report_fail("preemption timer with 0 value (vmcall stage 5)"); 226 break; 227 default: 228 // Should not reach here 229 report_fail("unexpected stage, %d", 230 vmx_get_test_stage()); 231 print_vmexit_info(exit_reason); 232 return VMX_TEST_VMEXIT; 233 } 234 break; 235 default: 236 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 237 print_vmexit_info(exit_reason); 238 } 239 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 240 return VMX_TEST_VMEXIT; 241 } 242 243 static void msr_bmp_init(void) 244 { 245 void *msr_bitmap; 246 u32 ctrl_cpu0; 247 248 msr_bitmap = alloc_page(); 249 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 250 ctrl_cpu0 |= CPU_MSR_BITMAP; 251 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 252 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 253 } 254 255 static void *get_msr_bitmap(void) 256 { 257 void *msr_bitmap; 258 259 if (vmcs_read(CPU_EXEC_CTRL0) & CPU_MSR_BITMAP) { 260 msr_bitmap = (void *)vmcs_read(MSR_BITMAP); 261 } else { 262 msr_bitmap = alloc_page(); 263 memset(msr_bitmap, 0xff, PAGE_SIZE); 264 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 265 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_MSR_BITMAP); 266 } 267 268 return msr_bitmap; 269 } 270 271 static void disable_intercept_for_x2apic_msrs(void) 272 { 273 unsigned long *msr_bitmap = (unsigned long *)get_msr_bitmap(); 274 u32 msr; 275 276 for (msr = APIC_BASE_MSR; 277 msr < (APIC_BASE_MSR+0xff); 278 msr += BITS_PER_LONG) { 279 unsigned int word = msr / BITS_PER_LONG; 280 281 msr_bitmap[word] = 0; 282 msr_bitmap[word + (0x800 / sizeof(long))] = 0; 283 } 284 } 285 286 static int test_ctrl_pat_init(struct vmcs *vmcs) 287 { 288 u64 ctrl_ent; 289 u64 ctrl_exi; 290 291 msr_bmp_init(); 292 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT) && 293 !(ctrl_exit_rev.clr & EXI_LOAD_PAT) && 294 !(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 295 printf("\tSave/load PAT is not supported\n"); 296 return 1; 297 } 298 299 ctrl_ent = vmcs_read(ENT_CONTROLS); 300 ctrl_exi = vmcs_read(EXI_CONTROLS); 301 ctrl_ent |= ctrl_enter_rev.clr & ENT_LOAD_PAT; 302 ctrl_exi |= ctrl_exit_rev.clr & (EXI_SAVE_PAT | EXI_LOAD_PAT); 303 vmcs_write(ENT_CONTROLS, ctrl_ent); 304 vmcs_write(EXI_CONTROLS, ctrl_exi); 305 ia32_pat = rdmsr(MSR_IA32_CR_PAT); 306 vmcs_write(GUEST_PAT, 0x0); 307 vmcs_write(HOST_PAT, ia32_pat); 308 return VMX_TEST_START; 309 } 310 311 static void test_ctrl_pat_main(void) 312 { 313 u64 guest_ia32_pat; 314 315 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 316 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) 317 printf("\tENT_LOAD_PAT is not supported.\n"); 318 else { 319 if (guest_ia32_pat != 0) { 320 report_fail("Entry load PAT"); 321 return; 322 } 323 } 324 wrmsr(MSR_IA32_CR_PAT, 0x6); 325 vmcall(); 326 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 327 if (ctrl_enter_rev.clr & ENT_LOAD_PAT) 328 report(guest_ia32_pat == ia32_pat, "Entry load PAT"); 329 } 330 331 static int test_ctrl_pat_exit_handler(union exit_reason exit_reason) 332 { 333 u64 guest_rip; 334 u64 guest_pat; 335 336 guest_rip = vmcs_read(GUEST_RIP); 337 switch (exit_reason.basic) { 338 case VMX_VMCALL: 339 guest_pat = vmcs_read(GUEST_PAT); 340 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT)) { 341 printf("\tEXI_SAVE_PAT is not supported\n"); 342 vmcs_write(GUEST_PAT, 0x6); 343 } else { 344 report(guest_pat == 0x6, "Exit save PAT"); 345 } 346 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) 347 printf("\tEXI_LOAD_PAT is not supported\n"); 348 else 349 report(rdmsr(MSR_IA32_CR_PAT) == ia32_pat, 350 "Exit load PAT"); 351 vmcs_write(GUEST_PAT, ia32_pat); 352 vmcs_write(GUEST_RIP, guest_rip + 3); 353 return VMX_TEST_RESUME; 354 default: 355 printf("ERROR : Unknown exit reason, 0x%x.\n", exit_reason.full); 356 break; 357 } 358 return VMX_TEST_VMEXIT; 359 } 360 361 static int test_ctrl_efer_init(struct vmcs *vmcs) 362 { 363 u64 ctrl_ent; 364 u64 ctrl_exi; 365 366 msr_bmp_init(); 367 ctrl_ent = vmcs_read(ENT_CONTROLS) | ENT_LOAD_EFER; 368 ctrl_exi = vmcs_read(EXI_CONTROLS) | EXI_SAVE_EFER | EXI_LOAD_EFER; 369 vmcs_write(ENT_CONTROLS, ctrl_ent & ctrl_enter_rev.clr); 370 vmcs_write(EXI_CONTROLS, ctrl_exi & ctrl_exit_rev.clr); 371 ia32_efer = rdmsr(MSR_EFER); 372 vmcs_write(GUEST_EFER, ia32_efer ^ EFER_NX); 373 vmcs_write(HOST_EFER, ia32_efer ^ EFER_NX); 374 return VMX_TEST_START; 375 } 376 377 static void test_ctrl_efer_main(void) 378 { 379 u64 guest_ia32_efer; 380 381 guest_ia32_efer = rdmsr(MSR_EFER); 382 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) 383 printf("\tENT_LOAD_EFER is not supported.\n"); 384 else { 385 if (guest_ia32_efer != (ia32_efer ^ EFER_NX)) { 386 report_fail("Entry load EFER"); 387 return; 388 } 389 } 390 wrmsr(MSR_EFER, ia32_efer); 391 vmcall(); 392 guest_ia32_efer = rdmsr(MSR_EFER); 393 if (ctrl_enter_rev.clr & ENT_LOAD_EFER) 394 report(guest_ia32_efer == ia32_efer, "Entry load EFER"); 395 } 396 397 static int test_ctrl_efer_exit_handler(union exit_reason exit_reason) 398 { 399 u64 guest_rip; 400 u64 guest_efer; 401 402 guest_rip = vmcs_read(GUEST_RIP); 403 switch (exit_reason.basic) { 404 case VMX_VMCALL: 405 guest_efer = vmcs_read(GUEST_EFER); 406 if (!(ctrl_exit_rev.clr & EXI_SAVE_EFER)) { 407 printf("\tEXI_SAVE_EFER is not supported\n"); 408 vmcs_write(GUEST_EFER, ia32_efer); 409 } else { 410 report(guest_efer == ia32_efer, "Exit save EFER"); 411 } 412 if (!(ctrl_exit_rev.clr & EXI_LOAD_EFER)) { 413 printf("\tEXI_LOAD_EFER is not supported\n"); 414 wrmsr(MSR_EFER, ia32_efer ^ EFER_NX); 415 } else { 416 report(rdmsr(MSR_EFER) == (ia32_efer ^ EFER_NX), 417 "Exit load EFER"); 418 } 419 vmcs_write(GUEST_PAT, ia32_efer); 420 vmcs_write(GUEST_RIP, guest_rip + 3); 421 return VMX_TEST_RESUME; 422 default: 423 printf("ERROR : Unknown exit reason, 0x%x.\n", exit_reason.full); 424 break; 425 } 426 return VMX_TEST_VMEXIT; 427 } 428 429 u32 guest_cr0, guest_cr4; 430 431 static void cr_shadowing_main(void) 432 { 433 u32 cr0, cr4, tmp; 434 435 // Test read through 436 vmx_set_test_stage(0); 437 guest_cr0 = read_cr0(); 438 if (vmx_get_test_stage() == 1) 439 report_fail("Read through CR0"); 440 else 441 vmcall(); 442 vmx_set_test_stage(1); 443 guest_cr4 = read_cr4(); 444 if (vmx_get_test_stage() == 2) 445 report_fail("Read through CR4"); 446 else 447 vmcall(); 448 // Test write through 449 guest_cr0 = guest_cr0 ^ (X86_CR0_TS | X86_CR0_MP); 450 guest_cr4 = guest_cr4 ^ (X86_CR4_TSD | X86_CR4_DE); 451 vmx_set_test_stage(2); 452 write_cr0(guest_cr0); 453 if (vmx_get_test_stage() == 3) 454 report_fail("Write throuth CR0"); 455 else 456 vmcall(); 457 vmx_set_test_stage(3); 458 write_cr4(guest_cr4); 459 if (vmx_get_test_stage() == 4) 460 report_fail("Write through CR4"); 461 else 462 vmcall(); 463 // Test read shadow 464 vmx_set_test_stage(4); 465 vmcall(); 466 cr0 = read_cr0(); 467 if (vmx_get_test_stage() != 5) 468 report(cr0 == guest_cr0, "Read shadowing CR0"); 469 vmx_set_test_stage(5); 470 cr4 = read_cr4(); 471 if (vmx_get_test_stage() != 6) 472 report(cr4 == guest_cr4, "Read shadowing CR4"); 473 // Test write shadow (same value with shadow) 474 vmx_set_test_stage(6); 475 write_cr0(guest_cr0); 476 if (vmx_get_test_stage() == 7) 477 report_fail("Write shadowing CR0 (same value with shadow)"); 478 else 479 vmcall(); 480 vmx_set_test_stage(7); 481 write_cr4(guest_cr4); 482 if (vmx_get_test_stage() == 8) 483 report_fail("Write shadowing CR4 (same value with shadow)"); 484 else 485 vmcall(); 486 // Test write shadow (different value) 487 vmx_set_test_stage(8); 488 tmp = guest_cr0 ^ X86_CR0_TS; 489 asm volatile("mov %0, %%rsi\n\t" 490 "mov %%rsi, %%cr0\n\t" 491 ::"m"(tmp) 492 :"rsi", "memory", "cc"); 493 report(vmx_get_test_stage() == 9, 494 "Write shadowing different X86_CR0_TS"); 495 vmx_set_test_stage(9); 496 tmp = guest_cr0 ^ X86_CR0_MP; 497 asm volatile("mov %0, %%rsi\n\t" 498 "mov %%rsi, %%cr0\n\t" 499 ::"m"(tmp) 500 :"rsi", "memory", "cc"); 501 report(vmx_get_test_stage() == 10, 502 "Write shadowing different X86_CR0_MP"); 503 vmx_set_test_stage(10); 504 tmp = guest_cr4 ^ X86_CR4_TSD; 505 asm volatile("mov %0, %%rsi\n\t" 506 "mov %%rsi, %%cr4\n\t" 507 ::"m"(tmp) 508 :"rsi", "memory", "cc"); 509 report(vmx_get_test_stage() == 11, 510 "Write shadowing different X86_CR4_TSD"); 511 vmx_set_test_stage(11); 512 tmp = guest_cr4 ^ X86_CR4_DE; 513 asm volatile("mov %0, %%rsi\n\t" 514 "mov %%rsi, %%cr4\n\t" 515 ::"m"(tmp) 516 :"rsi", "memory", "cc"); 517 report(vmx_get_test_stage() == 12, 518 "Write shadowing different X86_CR4_DE"); 519 } 520 521 static int cr_shadowing_exit_handler(union exit_reason exit_reason) 522 { 523 u64 guest_rip; 524 u32 insn_len; 525 u32 exit_qual; 526 527 guest_rip = vmcs_read(GUEST_RIP); 528 insn_len = vmcs_read(EXI_INST_LEN); 529 exit_qual = vmcs_read(EXI_QUALIFICATION); 530 switch (exit_reason.basic) { 531 case VMX_VMCALL: 532 switch (vmx_get_test_stage()) { 533 case 0: 534 report(guest_cr0 == vmcs_read(GUEST_CR0), 535 "Read through CR0"); 536 break; 537 case 1: 538 report(guest_cr4 == vmcs_read(GUEST_CR4), 539 "Read through CR4"); 540 break; 541 case 2: 542 report(guest_cr0 == vmcs_read(GUEST_CR0), 543 "Write through CR0"); 544 break; 545 case 3: 546 report(guest_cr4 == vmcs_read(GUEST_CR4), 547 "Write through CR4"); 548 break; 549 case 4: 550 guest_cr0 = vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP); 551 guest_cr4 = vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE); 552 vmcs_write(CR0_MASK, X86_CR0_TS | X86_CR0_MP); 553 vmcs_write(CR0_READ_SHADOW, guest_cr0 & (X86_CR0_TS | X86_CR0_MP)); 554 vmcs_write(CR4_MASK, X86_CR4_TSD | X86_CR4_DE); 555 vmcs_write(CR4_READ_SHADOW, guest_cr4 & (X86_CR4_TSD | X86_CR4_DE)); 556 break; 557 case 6: 558 report(guest_cr0 == (vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP)), 559 "Write shadowing CR0 (same value)"); 560 break; 561 case 7: 562 report(guest_cr4 == (vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE)), 563 "Write shadowing CR4 (same value)"); 564 break; 565 default: 566 // Should not reach here 567 report_fail("unexpected stage, %d", 568 vmx_get_test_stage()); 569 print_vmexit_info(exit_reason); 570 return VMX_TEST_VMEXIT; 571 } 572 vmcs_write(GUEST_RIP, guest_rip + insn_len); 573 return VMX_TEST_RESUME; 574 case VMX_CR: 575 switch (vmx_get_test_stage()) { 576 case 4: 577 report_fail("Read shadowing CR0"); 578 vmx_inc_test_stage(); 579 break; 580 case 5: 581 report_fail("Read shadowing CR4"); 582 vmx_inc_test_stage(); 583 break; 584 case 6: 585 report_fail("Write shadowing CR0 (same value)"); 586 vmx_inc_test_stage(); 587 break; 588 case 7: 589 report_fail("Write shadowing CR4 (same value)"); 590 vmx_inc_test_stage(); 591 break; 592 case 8: 593 case 9: 594 // 0x600 encodes "mov %esi, %cr0" 595 if (exit_qual == 0x600) 596 vmx_inc_test_stage(); 597 break; 598 case 10: 599 case 11: 600 // 0x604 encodes "mov %esi, %cr4" 601 if (exit_qual == 0x604) 602 vmx_inc_test_stage(); 603 break; 604 default: 605 // Should not reach here 606 report_fail("unexpected stage, %d", 607 vmx_get_test_stage()); 608 print_vmexit_info(exit_reason); 609 return VMX_TEST_VMEXIT; 610 } 611 vmcs_write(GUEST_RIP, guest_rip + insn_len); 612 return VMX_TEST_RESUME; 613 default: 614 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 615 print_vmexit_info(exit_reason); 616 } 617 return VMX_TEST_VMEXIT; 618 } 619 620 static int iobmp_init(struct vmcs *vmcs) 621 { 622 u32 ctrl_cpu0; 623 624 io_bitmap_a = alloc_page(); 625 io_bitmap_b = alloc_page(); 626 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 627 ctrl_cpu0 |= CPU_IO_BITMAP; 628 ctrl_cpu0 &= (~CPU_IO); 629 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 630 vmcs_write(IO_BITMAP_A, (u64)io_bitmap_a); 631 vmcs_write(IO_BITMAP_B, (u64)io_bitmap_b); 632 return VMX_TEST_START; 633 } 634 635 static void iobmp_main(void) 636 { 637 // stage 0, test IO pass 638 vmx_set_test_stage(0); 639 inb(0x5000); 640 outb(0x0, 0x5000); 641 report(vmx_get_test_stage() == 0, "I/O bitmap - I/O pass"); 642 // test IO width, in/out 643 ((u8 *)io_bitmap_a)[0] = 0xFF; 644 vmx_set_test_stage(2); 645 inb(0x0); 646 report(vmx_get_test_stage() == 3, "I/O bitmap - trap in"); 647 vmx_set_test_stage(3); 648 outw(0x0, 0x0); 649 report(vmx_get_test_stage() == 4, "I/O bitmap - trap out"); 650 vmx_set_test_stage(4); 651 inl(0x0); 652 report(vmx_get_test_stage() == 5, "I/O bitmap - I/O width, long"); 653 // test low/high IO port 654 vmx_set_test_stage(5); 655 ((u8 *)io_bitmap_a)[0x5000 / 8] = (1 << (0x5000 % 8)); 656 inb(0x5000); 657 report(vmx_get_test_stage() == 6, "I/O bitmap - I/O port, low part"); 658 vmx_set_test_stage(6); 659 ((u8 *)io_bitmap_b)[0x1000 / 8] = (1 << (0x1000 % 8)); 660 inb(0x9000); 661 report(vmx_get_test_stage() == 7, "I/O bitmap - I/O port, high part"); 662 // test partial pass 663 vmx_set_test_stage(7); 664 inl(0x4FFF); 665 report(vmx_get_test_stage() == 8, "I/O bitmap - partial pass"); 666 // test overrun 667 vmx_set_test_stage(8); 668 memset(io_bitmap_a, 0x0, PAGE_SIZE); 669 memset(io_bitmap_b, 0x0, PAGE_SIZE); 670 inl(0xFFFF); 671 report(vmx_get_test_stage() == 9, "I/O bitmap - overrun"); 672 vmx_set_test_stage(9); 673 vmcall(); 674 outb(0x0, 0x0); 675 report(vmx_get_test_stage() == 9, 676 "I/O bitmap - ignore unconditional exiting"); 677 vmx_set_test_stage(10); 678 vmcall(); 679 outb(0x0, 0x0); 680 report(vmx_get_test_stage() == 11, 681 "I/O bitmap - unconditional exiting"); 682 } 683 684 static int iobmp_exit_handler(union exit_reason exit_reason) 685 { 686 u64 guest_rip; 687 ulong exit_qual; 688 u32 insn_len, ctrl_cpu0; 689 690 guest_rip = vmcs_read(GUEST_RIP); 691 exit_qual = vmcs_read(EXI_QUALIFICATION); 692 insn_len = vmcs_read(EXI_INST_LEN); 693 switch (exit_reason.basic) { 694 case VMX_IO: 695 switch (vmx_get_test_stage()) { 696 case 0: 697 case 1: 698 vmx_inc_test_stage(); 699 break; 700 case 2: 701 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_BYTE, 702 "I/O bitmap - I/O width, byte"); 703 report(exit_qual & VMX_IO_IN, 704 "I/O bitmap - I/O direction, in"); 705 vmx_inc_test_stage(); 706 break; 707 case 3: 708 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_WORD, 709 "I/O bitmap - I/O width, word"); 710 report(!(exit_qual & VMX_IO_IN), 711 "I/O bitmap - I/O direction, out"); 712 vmx_inc_test_stage(); 713 break; 714 case 4: 715 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_LONG, 716 "I/O bitmap - I/O width, long"); 717 vmx_inc_test_stage(); 718 break; 719 case 5: 720 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x5000) 721 vmx_inc_test_stage(); 722 break; 723 case 6: 724 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x9000) 725 vmx_inc_test_stage(); 726 break; 727 case 7: 728 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x4FFF) 729 vmx_inc_test_stage(); 730 break; 731 case 8: 732 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0xFFFF) 733 vmx_inc_test_stage(); 734 break; 735 case 9: 736 case 10: 737 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 738 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0 & ~CPU_IO); 739 vmx_inc_test_stage(); 740 break; 741 default: 742 // Should not reach here 743 report_fail("unexpected stage, %d", 744 vmx_get_test_stage()); 745 print_vmexit_info(exit_reason); 746 return VMX_TEST_VMEXIT; 747 } 748 vmcs_write(GUEST_RIP, guest_rip + insn_len); 749 return VMX_TEST_RESUME; 750 case VMX_VMCALL: 751 switch (vmx_get_test_stage()) { 752 case 9: 753 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 754 ctrl_cpu0 |= CPU_IO | CPU_IO_BITMAP; 755 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 756 break; 757 case 10: 758 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 759 ctrl_cpu0 = (ctrl_cpu0 & ~CPU_IO_BITMAP) | CPU_IO; 760 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 761 break; 762 default: 763 // Should not reach here 764 report_fail("unexpected stage, %d", 765 vmx_get_test_stage()); 766 print_vmexit_info(exit_reason); 767 return VMX_TEST_VMEXIT; 768 } 769 vmcs_write(GUEST_RIP, guest_rip + insn_len); 770 return VMX_TEST_RESUME; 771 default: 772 printf("guest_rip = %#lx\n", guest_rip); 773 printf("\tERROR : Unknown exit reason, 0x%x\n", exit_reason.full); 774 break; 775 } 776 return VMX_TEST_VMEXIT; 777 } 778 779 #define INSN_CPU0 0 780 #define INSN_CPU1 1 781 #define INSN_ALWAYS_TRAP 2 782 783 #define FIELD_EXIT_QUAL (1 << 0) 784 #define FIELD_INSN_INFO (1 << 1) 785 786 asm( 787 "insn_hlt: hlt;ret\n\t" 788 "insn_invlpg: invlpg 0x12345678;ret\n\t" 789 "insn_mwait: xor %eax, %eax; xor %ecx, %ecx; mwait;ret\n\t" 790 "insn_rdpmc: xor %ecx, %ecx; rdpmc;ret\n\t" 791 "insn_rdtsc: rdtsc;ret\n\t" 792 "insn_cr3_load: mov cr3,%rax; mov %rax,%cr3;ret\n\t" 793 "insn_cr3_store: mov %cr3,%rax;ret\n\t" 794 "insn_cr8_load: xor %eax, %eax; mov %rax,%cr8;ret\n\t" 795 "insn_cr8_store: mov %cr8,%rax;ret\n\t" 796 "insn_monitor: xor %eax, %eax; xor %ecx, %ecx; xor %edx, %edx; monitor;ret\n\t" 797 "insn_pause: pause;ret\n\t" 798 "insn_wbinvd: wbinvd;ret\n\t" 799 "insn_cpuid: mov $10, %eax; cpuid;ret\n\t" 800 "insn_invd: invd;ret\n\t" 801 "insn_sgdt: sgdt gdt_descr;ret\n\t" 802 "insn_lgdt: lgdt gdt_descr;ret\n\t" 803 "insn_sidt: sidt idt_descr;ret\n\t" 804 "insn_lidt: lidt idt_descr;ret\n\t" 805 "insn_sldt: sldt %ax;ret\n\t" 806 "insn_lldt: xor %eax, %eax; lldt %ax;ret\n\t" 807 "insn_str: str %ax;ret\n\t" 808 "insn_rdrand: rdrand %rax;ret\n\t" 809 "insn_rdseed: rdseed %rax;ret\n\t" 810 ); 811 extern void insn_hlt(void); 812 extern void insn_invlpg(void); 813 extern void insn_mwait(void); 814 extern void insn_rdpmc(void); 815 extern void insn_rdtsc(void); 816 extern void insn_cr3_load(void); 817 extern void insn_cr3_store(void); 818 extern void insn_cr8_load(void); 819 extern void insn_cr8_store(void); 820 extern void insn_monitor(void); 821 extern void insn_pause(void); 822 extern void insn_wbinvd(void); 823 extern void insn_sgdt(void); 824 extern void insn_lgdt(void); 825 extern void insn_sidt(void); 826 extern void insn_lidt(void); 827 extern void insn_sldt(void); 828 extern void insn_lldt(void); 829 extern void insn_str(void); 830 extern void insn_cpuid(void); 831 extern void insn_invd(void); 832 extern void insn_rdrand(void); 833 extern void insn_rdseed(void); 834 835 u32 cur_insn; 836 u64 cr3; 837 838 #define X86_FEATURE_MONITOR (1 << 3) 839 840 typedef bool (*supported_fn)(void); 841 842 static bool monitor_supported(void) 843 { 844 return this_cpu_has(X86_FEATURE_MWAIT); 845 } 846 847 struct insn_table { 848 const char *name; 849 u32 flag; 850 void (*insn_func)(void); 851 u32 type; 852 u32 reason; 853 ulong exit_qual; 854 u32 insn_info; 855 // Use FIELD_EXIT_QUAL and FIELD_INSN_INFO to define 856 // which field need to be tested, reason is always tested 857 u32 test_field; 858 const supported_fn supported_fn; 859 u8 disabled; 860 }; 861 862 /* 863 * Add more test cases of instruction intercept here. Elements in this 864 * table is: 865 * name/control flag/insn function/type/exit reason/exit qulification/ 866 * instruction info/field to test 867 * The last field defines which fields (exit_qual and insn_info) need to be 868 * tested in exit handler. If set to 0, only "reason" is checked. 869 */ 870 static struct insn_table insn_table[] = { 871 // Flags for Primary Processor-Based VM-Execution Controls 872 {"HLT", CPU_HLT, insn_hlt, INSN_CPU0, 12, 0, 0, 0}, 873 {"INVLPG", CPU_INVLPG, insn_invlpg, INSN_CPU0, 14, 874 0x12345678, 0, FIELD_EXIT_QUAL}, 875 {"MWAIT", CPU_MWAIT, insn_mwait, INSN_CPU0, 36, 0, 0, 0, &monitor_supported}, 876 {"RDPMC", CPU_RDPMC, insn_rdpmc, INSN_CPU0, 15, 0, 0, 0}, 877 {"RDTSC", CPU_RDTSC, insn_rdtsc, INSN_CPU0, 16, 0, 0, 0}, 878 {"CR3 load", CPU_CR3_LOAD, insn_cr3_load, INSN_CPU0, 28, 0x3, 0, 879 FIELD_EXIT_QUAL}, 880 {"CR3 store", CPU_CR3_STORE, insn_cr3_store, INSN_CPU0, 28, 0x13, 0, 881 FIELD_EXIT_QUAL}, 882 {"CR8 load", CPU_CR8_LOAD, insn_cr8_load, INSN_CPU0, 28, 0x8, 0, 883 FIELD_EXIT_QUAL}, 884 {"CR8 store", CPU_CR8_STORE, insn_cr8_store, INSN_CPU0, 28, 0x18, 0, 885 FIELD_EXIT_QUAL}, 886 {"MONITOR", CPU_MONITOR, insn_monitor, INSN_CPU0, 39, 0, 0, 0, &monitor_supported}, 887 {"PAUSE", CPU_PAUSE, insn_pause, INSN_CPU0, 40, 0, 0, 0}, 888 // Flags for Secondary Processor-Based VM-Execution Controls 889 {"WBINVD", CPU_WBINVD, insn_wbinvd, INSN_CPU1, 54, 0, 0, 0}, 890 {"DESC_TABLE (SGDT)", CPU_DESC_TABLE, insn_sgdt, INSN_CPU1, 46, 0, 0, 0}, 891 {"DESC_TABLE (LGDT)", CPU_DESC_TABLE, insn_lgdt, INSN_CPU1, 46, 0, 0, 0}, 892 {"DESC_TABLE (SIDT)", CPU_DESC_TABLE, insn_sidt, INSN_CPU1, 46, 0, 0, 0}, 893 {"DESC_TABLE (LIDT)", CPU_DESC_TABLE, insn_lidt, INSN_CPU1, 46, 0, 0, 0}, 894 {"DESC_TABLE (SLDT)", CPU_DESC_TABLE, insn_sldt, INSN_CPU1, 47, 0, 0, 0}, 895 {"DESC_TABLE (LLDT)", CPU_DESC_TABLE, insn_lldt, INSN_CPU1, 47, 0, 0, 0}, 896 {"DESC_TABLE (STR)", CPU_DESC_TABLE, insn_str, INSN_CPU1, 47, 0, 0, 0}, 897 /* LTR causes a #GP if done with a busy selector, so it is not tested. */ 898 {"RDRAND", CPU_RDRAND, insn_rdrand, INSN_CPU1, VMX_RDRAND, 0, 0, 0}, 899 {"RDSEED", CPU_RDSEED, insn_rdseed, INSN_CPU1, VMX_RDSEED, 0, 0, 0}, 900 // Instructions always trap 901 {"CPUID", 0, insn_cpuid, INSN_ALWAYS_TRAP, 10, 0, 0, 0}, 902 {"INVD", 0, insn_invd, INSN_ALWAYS_TRAP, 13, 0, 0, 0}, 903 // Instructions never trap 904 {NULL}, 905 }; 906 907 static int insn_intercept_init(struct vmcs *vmcs) 908 { 909 u32 ctrl_cpu, cur_insn; 910 911 ctrl_cpu = ctrl_cpu_rev[0].set | CPU_SECONDARY; 912 ctrl_cpu &= ctrl_cpu_rev[0].clr; 913 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu); 914 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu_rev[1].set); 915 cr3 = read_cr3(); 916 917 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 918 if (insn_table[cur_insn].supported_fn == NULL) 919 continue; 920 insn_table[cur_insn].disabled = !insn_table[cur_insn].supported_fn(); 921 } 922 return VMX_TEST_START; 923 } 924 925 static void insn_intercept_main(void) 926 { 927 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 928 vmx_set_test_stage(cur_insn * 2); 929 if ((insn_table[cur_insn].type == INSN_CPU0 && 930 !(ctrl_cpu_rev[0].clr & insn_table[cur_insn].flag)) || 931 (insn_table[cur_insn].type == INSN_CPU1 && 932 !(ctrl_cpu_rev[1].clr & insn_table[cur_insn].flag))) { 933 printf("\tCPU_CTRL%d.CPU_%s is not supported.\n", 934 insn_table[cur_insn].type - INSN_CPU0, 935 insn_table[cur_insn].name); 936 continue; 937 } 938 939 if (insn_table[cur_insn].disabled) { 940 printf("\tFeature required for %s is not supported.\n", 941 insn_table[cur_insn].name); 942 continue; 943 } 944 945 if ((insn_table[cur_insn].type == INSN_CPU0 && 946 !(ctrl_cpu_rev[0].set & insn_table[cur_insn].flag)) || 947 (insn_table[cur_insn].type == INSN_CPU1 && 948 !(ctrl_cpu_rev[1].set & insn_table[cur_insn].flag))) { 949 /* skip hlt, it stalls the guest and is tested below */ 950 if (insn_table[cur_insn].insn_func != insn_hlt) 951 insn_table[cur_insn].insn_func(); 952 report(vmx_get_test_stage() == cur_insn * 2, 953 "execute %s", 954 insn_table[cur_insn].name); 955 } else if (insn_table[cur_insn].type != INSN_ALWAYS_TRAP) 956 printf("\tCPU_CTRL%d.CPU_%s always traps.\n", 957 insn_table[cur_insn].type - INSN_CPU0, 958 insn_table[cur_insn].name); 959 960 vmcall(); 961 962 insn_table[cur_insn].insn_func(); 963 report(vmx_get_test_stage() == cur_insn * 2 + 1, 964 "intercept %s", 965 insn_table[cur_insn].name); 966 967 vmx_set_test_stage(cur_insn * 2 + 1); 968 vmcall(); 969 } 970 } 971 972 static int insn_intercept_exit_handler(union exit_reason exit_reason) 973 { 974 u64 guest_rip; 975 ulong exit_qual; 976 u32 insn_len; 977 u32 insn_info; 978 bool pass; 979 980 guest_rip = vmcs_read(GUEST_RIP); 981 exit_qual = vmcs_read(EXI_QUALIFICATION); 982 insn_len = vmcs_read(EXI_INST_LEN); 983 insn_info = vmcs_read(EXI_INST_INFO); 984 985 if (exit_reason.basic == VMX_VMCALL) { 986 u32 val = 0; 987 988 if (insn_table[cur_insn].type == INSN_CPU0) 989 val = vmcs_read(CPU_EXEC_CTRL0); 990 else if (insn_table[cur_insn].type == INSN_CPU1) 991 val = vmcs_read(CPU_EXEC_CTRL1); 992 993 if (vmx_get_test_stage() & 1) 994 val &= ~insn_table[cur_insn].flag; 995 else 996 val |= insn_table[cur_insn].flag; 997 998 if (insn_table[cur_insn].type == INSN_CPU0) 999 vmcs_write(CPU_EXEC_CTRL0, val | ctrl_cpu_rev[0].set); 1000 else if (insn_table[cur_insn].type == INSN_CPU1) 1001 vmcs_write(CPU_EXEC_CTRL1, val | ctrl_cpu_rev[1].set); 1002 } else { 1003 pass = (cur_insn * 2 == vmx_get_test_stage()) && 1004 insn_table[cur_insn].reason == exit_reason.full; 1005 if (insn_table[cur_insn].test_field & FIELD_EXIT_QUAL && 1006 insn_table[cur_insn].exit_qual != exit_qual) 1007 pass = false; 1008 if (insn_table[cur_insn].test_field & FIELD_INSN_INFO && 1009 insn_table[cur_insn].insn_info != insn_info) 1010 pass = false; 1011 if (pass) 1012 vmx_inc_test_stage(); 1013 } 1014 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1015 return VMX_TEST_RESUME; 1016 } 1017 1018 /** 1019 * __setup_ept - Setup the VMCS fields to enable Extended Page Tables (EPT) 1020 * @hpa: Host physical address of the top-level, a.k.a. root, EPT table 1021 * @enable_ad: Whether or not to enable Access/Dirty bits for EPT entries 1022 * 1023 * Returns 0 on success, 1 on failure. 1024 * 1025 * Note that @hpa doesn't need to point at actual memory if VM-Launch is 1026 * expected to fail, e.g. setup_dummy_ept() arbitrarily passes '0' to satisfy 1027 * the various EPTP consistency checks, but doesn't ensure backing for HPA '0'. 1028 */ 1029 static int __setup_ept(u64 hpa, bool enable_ad) 1030 { 1031 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1032 !(ctrl_cpu_rev[1].clr & CPU_EPT)) { 1033 printf("\tEPT is not supported\n"); 1034 return 1; 1035 } 1036 if (!(ept_vpid.val & EPT_CAP_WB)) { 1037 printf("\tWB memtype for EPT walks not supported\n"); 1038 return 1; 1039 } 1040 if (!(ept_vpid.val & EPT_CAP_PWL4)) { 1041 printf("\tPWL4 is not supported\n"); 1042 return 1; 1043 } 1044 1045 eptp = EPT_MEM_TYPE_WB; 1046 eptp |= (3 << EPTP_PG_WALK_LEN_SHIFT); 1047 eptp |= hpa; 1048 if (enable_ad) 1049 eptp |= EPTP_AD_FLAG; 1050 1051 vmcs_write(EPTP, eptp); 1052 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0)| CPU_SECONDARY); 1053 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1)| CPU_EPT); 1054 1055 return 0; 1056 } 1057 1058 /** 1059 * setup_ept - Enable Extended Page Tables (EPT) and setup an identity map 1060 * @enable_ad: Whether or not to enable Access/Dirty bits for EPT entries 1061 * 1062 * Returns 0 on success, 1 on failure. 1063 * 1064 * This is the "real" function for setting up EPT tables, i.e. use this for 1065 * tests that need to run code in the guest with EPT enabled. 1066 */ 1067 static int setup_ept(bool enable_ad) 1068 { 1069 unsigned long end_of_memory; 1070 1071 pml4 = alloc_page(); 1072 1073 if (__setup_ept(virt_to_phys(pml4), enable_ad)) 1074 return 1; 1075 1076 end_of_memory = fwcfg_get_u64(FW_CFG_RAM_SIZE); 1077 if (end_of_memory < (1ul << 32)) 1078 end_of_memory = (1ul << 32); 1079 /* Cannot use large EPT pages if we need to track EPT 1080 * accessed/dirty bits at 4K granularity. 1081 */ 1082 setup_ept_range(pml4, 0, end_of_memory, 0, 1083 !enable_ad && ept_2m_supported(), 1084 EPT_WA | EPT_RA | EPT_EA); 1085 return 0; 1086 } 1087 1088 /** 1089 * setup_dummy_ept - Enable Extended Page Tables (EPT) with a dummy root HPA 1090 * 1091 * Setup EPT using a semi-arbitrary dummy root HPA. This function is intended 1092 * for use by tests that need EPT enabled to verify dependent VMCS controls 1093 * but never expect to fully enter the guest, i.e. don't need setup the actual 1094 * EPT tables. 1095 */ 1096 static void setup_dummy_ept(void) 1097 { 1098 if (__setup_ept(0, false)) 1099 report_abort("EPT setup unexpectedly failed"); 1100 } 1101 1102 static int enable_unrestricted_guest(bool need_valid_ept) 1103 { 1104 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1105 !(ctrl_cpu_rev[1].clr & CPU_URG) || 1106 !(ctrl_cpu_rev[1].clr & CPU_EPT)) 1107 return 1; 1108 1109 if (need_valid_ept) 1110 setup_ept(false); 1111 else 1112 setup_dummy_ept(); 1113 1114 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 1115 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | CPU_URG); 1116 1117 return 0; 1118 } 1119 1120 static void ept_enable_ad_bits(void) 1121 { 1122 eptp |= EPTP_AD_FLAG; 1123 vmcs_write(EPTP, eptp); 1124 } 1125 1126 static void ept_disable_ad_bits(void) 1127 { 1128 eptp &= ~EPTP_AD_FLAG; 1129 vmcs_write(EPTP, eptp); 1130 } 1131 1132 static int ept_ad_enabled(void) 1133 { 1134 return eptp & EPTP_AD_FLAG; 1135 } 1136 1137 static void ept_enable_ad_bits_or_skip_test(void) 1138 { 1139 if (!ept_ad_bits_supported()) 1140 test_skip("EPT AD bits not supported."); 1141 ept_enable_ad_bits(); 1142 } 1143 1144 static int apic_version; 1145 1146 static int ept_init_common(bool have_ad) 1147 { 1148 int ret; 1149 struct pci_dev pcidev; 1150 1151 /* INVEPT is required by the EPT violation handler. */ 1152 if (!is_invept_type_supported(INVEPT_SINGLE)) 1153 return VMX_TEST_EXIT; 1154 1155 if (setup_ept(have_ad)) 1156 return VMX_TEST_EXIT; 1157 1158 data_page1 = alloc_page(); 1159 data_page2 = alloc_page(); 1160 *((u32 *)data_page1) = MAGIC_VAL_1; 1161 *((u32 *)data_page2) = MAGIC_VAL_2; 1162 install_ept(pml4, (unsigned long)data_page1, (unsigned long)data_page2, 1163 EPT_RA | EPT_WA | EPT_EA); 1164 1165 apic_version = apic_read(APIC_LVR); 1166 1167 ret = pci_find_dev(PCI_VENDOR_ID_REDHAT, PCI_DEVICE_ID_REDHAT_TEST); 1168 if (ret != PCIDEVADDR_INVALID) { 1169 pci_dev_init(&pcidev, ret); 1170 pci_physaddr = pcidev.resource[PCI_TESTDEV_BAR_MEM]; 1171 } 1172 1173 return VMX_TEST_START; 1174 } 1175 1176 static int ept_init(struct vmcs *vmcs) 1177 { 1178 return ept_init_common(false); 1179 } 1180 1181 static void ept_common(void) 1182 { 1183 vmx_set_test_stage(0); 1184 if (*((u32 *)data_page2) != MAGIC_VAL_1 || 1185 *((u32 *)data_page1) != MAGIC_VAL_1) 1186 report_fail("EPT basic framework - read"); 1187 else { 1188 *((u32 *)data_page2) = MAGIC_VAL_3; 1189 vmcall(); 1190 if (vmx_get_test_stage() == 1) { 1191 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1192 *((u32 *)data_page2) == MAGIC_VAL_2) 1193 report_pass("EPT basic framework"); 1194 else 1195 report_pass("EPT basic framework - remap"); 1196 } 1197 } 1198 // Test EPT Misconfigurations 1199 vmx_set_test_stage(1); 1200 vmcall(); 1201 *((u32 *)data_page1) = MAGIC_VAL_1; 1202 if (vmx_get_test_stage() != 2) { 1203 report_fail("EPT misconfigurations"); 1204 goto t1; 1205 } 1206 vmx_set_test_stage(2); 1207 vmcall(); 1208 *((u32 *)data_page1) = MAGIC_VAL_1; 1209 report(vmx_get_test_stage() == 3, "EPT misconfigurations"); 1210 t1: 1211 // Test EPT violation 1212 vmx_set_test_stage(3); 1213 vmcall(); 1214 *((u32 *)data_page1) = MAGIC_VAL_1; 1215 report(vmx_get_test_stage() == 4, "EPT violation - page permission"); 1216 // Violation caused by EPT paging structure 1217 vmx_set_test_stage(4); 1218 vmcall(); 1219 *((u32 *)data_page1) = MAGIC_VAL_2; 1220 report(vmx_get_test_stage() == 5, "EPT violation - paging structure"); 1221 1222 // MMIO Read/Write 1223 vmx_set_test_stage(5); 1224 vmcall(); 1225 1226 *(u32 volatile *)pci_physaddr; 1227 report(vmx_get_test_stage() == 6, "MMIO EPT violation - read"); 1228 1229 *(u32 volatile *)pci_physaddr = MAGIC_VAL_1; 1230 report(vmx_get_test_stage() == 7, "MMIO EPT violation - write"); 1231 } 1232 1233 static void ept_main(void) 1234 { 1235 ept_common(); 1236 1237 // Test EPT access to L1 MMIO 1238 vmx_set_test_stage(7); 1239 report(*((u32 *)0xfee00030UL) == apic_version, "EPT - MMIO access"); 1240 1241 // Test invalid operand for INVEPT 1242 vmcall(); 1243 report(vmx_get_test_stage() == 8, "EPT - unsupported INVEPT"); 1244 } 1245 1246 static bool invept_test(int type, u64 eptp) 1247 { 1248 bool ret, supported; 1249 1250 supported = ept_vpid.val & (EPT_CAP_INVEPT_SINGLE >> INVEPT_SINGLE << type); 1251 ret = __invept(type, eptp); 1252 1253 if (ret == !supported) 1254 return false; 1255 1256 if (!supported) 1257 printf("WARNING: unsupported invept passed!\n"); 1258 else 1259 printf("WARNING: invept failed!\n"); 1260 1261 return true; 1262 } 1263 1264 static int pml_exit_handler(union exit_reason exit_reason) 1265 { 1266 u16 index, count; 1267 u64 *pmlbuf = pml_log; 1268 u64 guest_rip = vmcs_read(GUEST_RIP);; 1269 u64 guest_cr3 = vmcs_read(GUEST_CR3); 1270 u32 insn_len = vmcs_read(EXI_INST_LEN); 1271 1272 switch (exit_reason.basic) { 1273 case VMX_VMCALL: 1274 switch (vmx_get_test_stage()) { 1275 case 0: 1276 index = vmcs_read(GUEST_PML_INDEX); 1277 for (count = index + 1; count < PML_INDEX; count++) { 1278 if (pmlbuf[count] == (u64)data_page2) { 1279 vmx_inc_test_stage(); 1280 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1281 break; 1282 } 1283 } 1284 break; 1285 case 1: 1286 index = vmcs_read(GUEST_PML_INDEX); 1287 /* Keep clearing the dirty bit till a overflow */ 1288 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1289 break; 1290 default: 1291 report_fail("unexpected stage, %d.", 1292 vmx_get_test_stage()); 1293 print_vmexit_info(exit_reason); 1294 return VMX_TEST_VMEXIT; 1295 } 1296 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1297 return VMX_TEST_RESUME; 1298 case VMX_PML_FULL: 1299 vmx_inc_test_stage(); 1300 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1301 return VMX_TEST_RESUME; 1302 default: 1303 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 1304 print_vmexit_info(exit_reason); 1305 } 1306 return VMX_TEST_VMEXIT; 1307 } 1308 1309 static int ept_exit_handler_common(union exit_reason exit_reason, bool have_ad) 1310 { 1311 u64 guest_rip; 1312 u64 guest_cr3; 1313 u32 insn_len; 1314 u32 exit_qual; 1315 static unsigned long data_page1_pte, data_page1_pte_pte, memaddr_pte, 1316 guest_pte_addr; 1317 1318 guest_rip = vmcs_read(GUEST_RIP); 1319 guest_cr3 = vmcs_read(GUEST_CR3); 1320 insn_len = vmcs_read(EXI_INST_LEN); 1321 exit_qual = vmcs_read(EXI_QUALIFICATION); 1322 pteval_t *ptep; 1323 switch (exit_reason.basic) { 1324 case VMX_VMCALL: 1325 switch (vmx_get_test_stage()) { 1326 case 0: 1327 check_ept_ad(pml4, guest_cr3, 1328 (unsigned long)data_page1, 1329 have_ad ? EPT_ACCESS_FLAG : 0, 1330 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1331 check_ept_ad(pml4, guest_cr3, 1332 (unsigned long)data_page2, 1333 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0, 1334 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1335 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1336 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1337 if (have_ad) 1338 invept(INVEPT_SINGLE, eptp); 1339 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1340 *((u32 *)data_page2) == MAGIC_VAL_2) { 1341 vmx_inc_test_stage(); 1342 install_ept(pml4, (unsigned long)data_page2, 1343 (unsigned long)data_page2, 1344 EPT_RA | EPT_WA | EPT_EA); 1345 } else 1346 report_fail("EPT basic framework - write"); 1347 break; 1348 case 1: 1349 install_ept(pml4, (unsigned long)data_page1, 1350 (unsigned long)data_page1, EPT_WA); 1351 invept(INVEPT_SINGLE, eptp); 1352 break; 1353 case 2: 1354 install_ept(pml4, (unsigned long)data_page1, 1355 (unsigned long)data_page1, 1356 EPT_RA | EPT_WA | EPT_EA | 1357 (2 << EPT_MEM_TYPE_SHIFT)); 1358 invept(INVEPT_SINGLE, eptp); 1359 break; 1360 case 3: 1361 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1362 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)data_page1, 1363 1, &data_page1_pte)); 1364 set_ept_pte(pml4, (unsigned long)data_page1, 1365 1, data_page1_pte & ~EPT_PRESENT); 1366 invept(INVEPT_SINGLE, eptp); 1367 break; 1368 case 4: 1369 ptep = get_pte_level((pgd_t *)guest_cr3, data_page1, /*level=*/2); 1370 guest_pte_addr = virt_to_phys(ptep) & PAGE_MASK; 1371 1372 TEST_ASSERT(get_ept_pte(pml4, guest_pte_addr, 2, &data_page1_pte_pte)); 1373 set_ept_pte(pml4, guest_pte_addr, 2, 1374 data_page1_pte_pte & ~EPT_PRESENT); 1375 invept(INVEPT_SINGLE, eptp); 1376 break; 1377 case 5: 1378 install_ept(pml4, (unsigned long)pci_physaddr, 1379 (unsigned long)pci_physaddr, 0); 1380 invept(INVEPT_SINGLE, eptp); 1381 break; 1382 case 7: 1383 if (!invept_test(0, eptp)) 1384 vmx_inc_test_stage(); 1385 break; 1386 // Should not reach here 1387 default: 1388 report_fail("ERROR - unexpected stage, %d.", 1389 vmx_get_test_stage()); 1390 print_vmexit_info(exit_reason); 1391 return VMX_TEST_VMEXIT; 1392 } 1393 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1394 return VMX_TEST_RESUME; 1395 case VMX_EPT_MISCONFIG: 1396 switch (vmx_get_test_stage()) { 1397 case 1: 1398 case 2: 1399 vmx_inc_test_stage(); 1400 install_ept(pml4, (unsigned long)data_page1, 1401 (unsigned long)data_page1, 1402 EPT_RA | EPT_WA | EPT_EA); 1403 invept(INVEPT_SINGLE, eptp); 1404 break; 1405 // Should not reach here 1406 default: 1407 report_fail("ERROR - unexpected stage, %d.", 1408 vmx_get_test_stage()); 1409 print_vmexit_info(exit_reason); 1410 return VMX_TEST_VMEXIT; 1411 } 1412 return VMX_TEST_RESUME; 1413 case VMX_EPT_VIOLATION: 1414 /* 1415 * Exit-qualifications are masked not to account for advanced 1416 * VM-exit information. Once KVM supports this feature, this 1417 * masking should be removed. 1418 */ 1419 exit_qual &= ~EPT_VLT_GUEST_MASK; 1420 1421 switch(vmx_get_test_stage()) { 1422 case 3: 1423 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1424 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1425 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1426 if (exit_qual == (EPT_VLT_WR | EPT_VLT_LADDR_VLD | 1427 EPT_VLT_PADDR)) 1428 vmx_inc_test_stage(); 1429 set_ept_pte(pml4, (unsigned long)data_page1, 1430 1, data_page1_pte | (EPT_PRESENT)); 1431 invept(INVEPT_SINGLE, eptp); 1432 break; 1433 case 4: 1434 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1435 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1436 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1437 if (exit_qual == (EPT_VLT_RD | 1438 (have_ad ? EPT_VLT_WR : 0) | 1439 EPT_VLT_LADDR_VLD)) 1440 vmx_inc_test_stage(); 1441 set_ept_pte(pml4, guest_pte_addr, 2, 1442 data_page1_pte_pte | (EPT_PRESENT)); 1443 invept(INVEPT_SINGLE, eptp); 1444 break; 1445 case 5: 1446 if (exit_qual & EPT_VLT_RD) 1447 vmx_inc_test_stage(); 1448 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1449 1, &memaddr_pte)); 1450 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA); 1451 invept(INVEPT_SINGLE, eptp); 1452 break; 1453 case 6: 1454 if (exit_qual & EPT_VLT_WR) 1455 vmx_inc_test_stage(); 1456 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1457 1, &memaddr_pte)); 1458 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA | EPT_WA); 1459 invept(INVEPT_SINGLE, eptp); 1460 break; 1461 default: 1462 // Should not reach here 1463 report_fail("ERROR : unexpected stage, %d", 1464 vmx_get_test_stage()); 1465 print_vmexit_info(exit_reason); 1466 return VMX_TEST_VMEXIT; 1467 } 1468 return VMX_TEST_RESUME; 1469 default: 1470 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 1471 print_vmexit_info(exit_reason); 1472 } 1473 return VMX_TEST_VMEXIT; 1474 } 1475 1476 static int ept_exit_handler(union exit_reason exit_reason) 1477 { 1478 return ept_exit_handler_common(exit_reason, false); 1479 } 1480 1481 static int eptad_init(struct vmcs *vmcs) 1482 { 1483 int r = ept_init_common(true); 1484 1485 if (r == VMX_TEST_EXIT) 1486 return r; 1487 1488 if ((rdmsr(MSR_IA32_VMX_EPT_VPID_CAP) & EPT_CAP_AD_FLAG) == 0) { 1489 printf("\tEPT A/D bits are not supported"); 1490 return VMX_TEST_EXIT; 1491 } 1492 1493 return r; 1494 } 1495 1496 static int pml_init(struct vmcs *vmcs) 1497 { 1498 u32 ctrl_cpu; 1499 int r = eptad_init(vmcs); 1500 1501 if (r == VMX_TEST_EXIT) 1502 return r; 1503 1504 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1505 !(ctrl_cpu_rev[1].clr & CPU_PML)) { 1506 printf("\tPML is not supported"); 1507 return VMX_TEST_EXIT; 1508 } 1509 1510 pml_log = alloc_page(); 1511 vmcs_write(PMLADDR, (u64)pml_log); 1512 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1513 1514 ctrl_cpu = vmcs_read(CPU_EXEC_CTRL1) | CPU_PML; 1515 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu); 1516 1517 return VMX_TEST_START; 1518 } 1519 1520 static void pml_main(void) 1521 { 1522 int count = 0; 1523 1524 vmx_set_test_stage(0); 1525 *((u32 *)data_page2) = 0x1; 1526 vmcall(); 1527 report(vmx_get_test_stage() == 1, "PML - Dirty GPA Logging"); 1528 1529 while (vmx_get_test_stage() == 1) { 1530 vmcall(); 1531 *((u32 *)data_page2) = 0x1; 1532 if (count++ > PML_INDEX) 1533 break; 1534 } 1535 report(vmx_get_test_stage() == 2, "PML Full Event"); 1536 } 1537 1538 static void eptad_main(void) 1539 { 1540 ept_common(); 1541 } 1542 1543 static int eptad_exit_handler(union exit_reason exit_reason) 1544 { 1545 return ept_exit_handler_common(exit_reason, true); 1546 } 1547 1548 #define TIMER_VECTOR 222 1549 1550 static volatile bool timer_fired; 1551 1552 static void timer_isr(isr_regs_t *regs) 1553 { 1554 timer_fired = true; 1555 apic_write(APIC_EOI, 0); 1556 } 1557 1558 static int interrupt_init(struct vmcs *vmcs) 1559 { 1560 msr_bmp_init(); 1561 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1562 handle_irq(TIMER_VECTOR, timer_isr); 1563 return VMX_TEST_START; 1564 } 1565 1566 static void interrupt_main(void) 1567 { 1568 long long start, loops; 1569 1570 vmx_set_test_stage(0); 1571 1572 apic_write(APIC_LVTT, TIMER_VECTOR); 1573 irq_enable(); 1574 1575 apic_write(APIC_TMICT, 1); 1576 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1577 asm volatile ("nop"); 1578 report(timer_fired, "direct interrupt while running guest"); 1579 1580 apic_write(APIC_TMICT, 0); 1581 irq_disable(); 1582 vmcall(); 1583 timer_fired = false; 1584 apic_write(APIC_TMICT, 1); 1585 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1586 asm volatile ("nop"); 1587 report(timer_fired, "intercepted interrupt while running guest"); 1588 1589 irq_enable(); 1590 apic_write(APIC_TMICT, 0); 1591 irq_disable(); 1592 vmcall(); 1593 timer_fired = false; 1594 start = rdtsc(); 1595 apic_write(APIC_TMICT, 1000000); 1596 1597 safe_halt(); 1598 1599 report(rdtsc() - start > 1000000 && timer_fired, 1600 "direct interrupt + hlt"); 1601 1602 apic_write(APIC_TMICT, 0); 1603 irq_disable(); 1604 vmcall(); 1605 timer_fired = false; 1606 start = rdtsc(); 1607 apic_write(APIC_TMICT, 1000000); 1608 1609 safe_halt(); 1610 1611 report(rdtsc() - start > 10000 && timer_fired, 1612 "intercepted interrupt + hlt"); 1613 1614 apic_write(APIC_TMICT, 0); 1615 irq_disable(); 1616 vmcall(); 1617 timer_fired = false; 1618 start = rdtsc(); 1619 apic_write(APIC_TMICT, 1000000); 1620 1621 irq_enable(); 1622 asm volatile ("nop"); 1623 vmcall(); 1624 1625 report(rdtsc() - start > 10000 && timer_fired, 1626 "direct interrupt + activity state hlt"); 1627 1628 apic_write(APIC_TMICT, 0); 1629 irq_disable(); 1630 vmcall(); 1631 timer_fired = false; 1632 start = rdtsc(); 1633 apic_write(APIC_TMICT, 1000000); 1634 1635 irq_enable(); 1636 asm volatile ("nop"); 1637 vmcall(); 1638 1639 report(rdtsc() - start > 10000 && timer_fired, 1640 "intercepted interrupt + activity state hlt"); 1641 1642 apic_write(APIC_TMICT, 0); 1643 irq_disable(); 1644 vmx_set_test_stage(7); 1645 vmcall(); 1646 timer_fired = false; 1647 apic_write(APIC_TMICT, 1); 1648 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1649 asm volatile ("nop"); 1650 report(timer_fired, 1651 "running a guest with interrupt acknowledgement set"); 1652 1653 apic_write(APIC_TMICT, 0); 1654 irq_enable(); 1655 timer_fired = false; 1656 vmcall(); 1657 report(timer_fired, "Inject an event to a halted guest"); 1658 } 1659 1660 static int interrupt_exit_handler(union exit_reason exit_reason) 1661 { 1662 u64 guest_rip = vmcs_read(GUEST_RIP); 1663 u32 insn_len = vmcs_read(EXI_INST_LEN); 1664 1665 switch (exit_reason.basic) { 1666 case VMX_VMCALL: 1667 switch (vmx_get_test_stage()) { 1668 case 0: 1669 case 2: 1670 case 5: 1671 vmcs_write(PIN_CONTROLS, 1672 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1673 break; 1674 case 7: 1675 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_INTA); 1676 vmcs_write(PIN_CONTROLS, 1677 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1678 break; 1679 case 1: 1680 case 3: 1681 vmcs_write(PIN_CONTROLS, 1682 vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1683 break; 1684 case 4: 1685 case 6: 1686 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1687 break; 1688 1689 case 8: 1690 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1691 vmcs_write(ENT_INTR_INFO, 1692 TIMER_VECTOR | 1693 (VMX_INTR_TYPE_EXT_INTR << INTR_INFO_INTR_TYPE_SHIFT) | 1694 INTR_INFO_VALID_MASK); 1695 break; 1696 } 1697 vmx_inc_test_stage(); 1698 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1699 return VMX_TEST_RESUME; 1700 case VMX_EXTINT: 1701 if (vmcs_read(EXI_CONTROLS) & EXI_INTA) { 1702 int vector = vmcs_read(EXI_INTR_INFO) & 0xff; 1703 handle_external_interrupt(vector); 1704 } else { 1705 irq_enable(); 1706 asm volatile ("nop"); 1707 irq_disable(); 1708 } 1709 if (vmx_get_test_stage() >= 2) 1710 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 1711 return VMX_TEST_RESUME; 1712 default: 1713 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 1714 print_vmexit_info(exit_reason); 1715 } 1716 1717 return VMX_TEST_VMEXIT; 1718 } 1719 1720 1721 static volatile int nmi_fired; 1722 1723 #define NMI_DELAY 100000000ULL 1724 1725 static void nmi_isr(isr_regs_t *regs) 1726 { 1727 nmi_fired = true; 1728 } 1729 1730 static int nmi_hlt_init(struct vmcs *vmcs) 1731 { 1732 msr_bmp_init(); 1733 handle_irq(NMI_VECTOR, nmi_isr); 1734 vmcs_write(PIN_CONTROLS, 1735 vmcs_read(PIN_CONTROLS) & ~PIN_NMI); 1736 vmcs_write(PIN_CONTROLS, 1737 vmcs_read(PIN_CONTROLS) & ~PIN_VIRT_NMI); 1738 return VMX_TEST_START; 1739 } 1740 1741 static void nmi_message_thread(void *data) 1742 { 1743 while (vmx_get_test_stage() != 1) 1744 pause(); 1745 1746 delay(NMI_DELAY); 1747 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_NMI | APIC_INT_ASSERT, id_map[0]); 1748 1749 while (vmx_get_test_stage() != 2) 1750 pause(); 1751 1752 delay(NMI_DELAY); 1753 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_NMI | APIC_INT_ASSERT, id_map[0]); 1754 } 1755 1756 static void nmi_hlt_main(void) 1757 { 1758 long long start; 1759 1760 if (cpu_count() < 2) { 1761 report_skip(__func__); 1762 vmx_set_test_stage(-1); 1763 return; 1764 } 1765 1766 vmx_set_test_stage(0); 1767 on_cpu_async(1, nmi_message_thread, NULL); 1768 start = rdtsc(); 1769 vmx_set_test_stage(1); 1770 asm volatile ("hlt"); 1771 report((rdtsc() - start > NMI_DELAY) && nmi_fired, 1772 "direct NMI + hlt"); 1773 if (!nmi_fired) 1774 vmx_set_test_stage(-1); 1775 nmi_fired = false; 1776 1777 vmcall(); 1778 1779 start = rdtsc(); 1780 vmx_set_test_stage(2); 1781 asm volatile ("hlt"); 1782 report((rdtsc() - start > NMI_DELAY) && !nmi_fired, 1783 "intercepted NMI + hlt"); 1784 if (nmi_fired) { 1785 report(!nmi_fired, "intercepted NMI was dispatched"); 1786 vmx_set_test_stage(-1); 1787 return; 1788 } 1789 vmx_set_test_stage(3); 1790 } 1791 1792 static int nmi_hlt_exit_handler(union exit_reason exit_reason) 1793 { 1794 u64 guest_rip = vmcs_read(GUEST_RIP); 1795 u32 insn_len = vmcs_read(EXI_INST_LEN); 1796 1797 switch (vmx_get_test_stage()) { 1798 case 1: 1799 if (exit_reason.basic != VMX_VMCALL) { 1800 report_fail("VMEXIT not due to vmcall. Exit reason 0x%x", 1801 exit_reason.full); 1802 print_vmexit_info(exit_reason); 1803 return VMX_TEST_VMEXIT; 1804 } 1805 1806 vmcs_write(PIN_CONTROLS, 1807 vmcs_read(PIN_CONTROLS) | PIN_NMI); 1808 vmcs_write(PIN_CONTROLS, 1809 vmcs_read(PIN_CONTROLS) | PIN_VIRT_NMI); 1810 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1811 break; 1812 1813 case 2: 1814 if (exit_reason.basic != VMX_EXC_NMI) { 1815 report_fail("VMEXIT not due to NMI intercept. Exit reason 0x%x", 1816 exit_reason.full); 1817 print_vmexit_info(exit_reason); 1818 return VMX_TEST_VMEXIT; 1819 } 1820 report_pass("NMI intercept while running guest"); 1821 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 1822 break; 1823 1824 case 3: 1825 break; 1826 1827 default: 1828 return VMX_TEST_VMEXIT; 1829 } 1830 1831 if (vmx_get_test_stage() == 3) 1832 return VMX_TEST_VMEXIT; 1833 1834 return VMX_TEST_RESUME; 1835 } 1836 1837 1838 static int dbgctls_init(struct vmcs *vmcs) 1839 { 1840 u64 dr7 = 0x402; 1841 u64 zero = 0; 1842 1843 msr_bmp_init(); 1844 asm volatile( 1845 "mov %0,%%dr0\n\t" 1846 "mov %0,%%dr1\n\t" 1847 "mov %0,%%dr2\n\t" 1848 "mov %1,%%dr7\n\t" 1849 : : "r" (zero), "r" (dr7)); 1850 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1851 vmcs_write(GUEST_DR7, 0x404); 1852 vmcs_write(GUEST_DEBUGCTL, 0x2); 1853 1854 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 1855 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_SAVE_DBGCTLS); 1856 1857 return VMX_TEST_START; 1858 } 1859 1860 static void dbgctls_main(void) 1861 { 1862 u64 dr7, debugctl; 1863 1864 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1865 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1866 /* Commented out: KVM does not support DEBUGCTL so far */ 1867 (void)debugctl; 1868 report(dr7 == 0x404, "Load debug controls" /* && debugctl == 0x2 */); 1869 1870 dr7 = 0x408; 1871 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1872 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1873 1874 vmx_set_test_stage(0); 1875 vmcall(); 1876 report(vmx_get_test_stage() == 1, "Save debug controls"); 1877 1878 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS || 1879 ctrl_exit_rev.set & EXI_SAVE_DBGCTLS) { 1880 printf("\tDebug controls are always loaded/saved\n"); 1881 return; 1882 } 1883 vmx_set_test_stage(2); 1884 vmcall(); 1885 1886 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1887 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1888 /* Commented out: KVM does not support DEBUGCTL so far */ 1889 (void)debugctl; 1890 report(dr7 == 0x402, 1891 "Guest=host debug controls" /* && debugctl == 0x1 */); 1892 1893 dr7 = 0x408; 1894 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1895 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1896 1897 vmx_set_test_stage(3); 1898 vmcall(); 1899 report(vmx_get_test_stage() == 4, "Don't save debug controls"); 1900 } 1901 1902 static int dbgctls_exit_handler(union exit_reason exit_reason) 1903 { 1904 u32 insn_len = vmcs_read(EXI_INST_LEN); 1905 u64 guest_rip = vmcs_read(GUEST_RIP); 1906 u64 dr7, debugctl; 1907 1908 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1909 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1910 1911 switch (exit_reason.basic) { 1912 case VMX_VMCALL: 1913 switch (vmx_get_test_stage()) { 1914 case 0: 1915 if (dr7 == 0x400 && debugctl == 0 && 1916 vmcs_read(GUEST_DR7) == 0x408 /* && 1917 Commented out: KVM does not support DEBUGCTL so far 1918 vmcs_read(GUEST_DEBUGCTL) == 0x3 */) 1919 vmx_inc_test_stage(); 1920 break; 1921 case 2: 1922 dr7 = 0x402; 1923 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1924 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1925 vmcs_write(GUEST_DR7, 0x404); 1926 vmcs_write(GUEST_DEBUGCTL, 0x2); 1927 1928 vmcs_write(ENT_CONTROLS, 1929 vmcs_read(ENT_CONTROLS) & ~ENT_LOAD_DBGCTLS); 1930 vmcs_write(EXI_CONTROLS, 1931 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_DBGCTLS); 1932 break; 1933 case 3: 1934 if (dr7 == 0x400 && debugctl == 0 && 1935 vmcs_read(GUEST_DR7) == 0x404 /* && 1936 Commented out: KVM does not support DEBUGCTL so far 1937 vmcs_read(GUEST_DEBUGCTL) == 0x2 */) 1938 vmx_inc_test_stage(); 1939 break; 1940 } 1941 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1942 return VMX_TEST_RESUME; 1943 default: 1944 report_fail("Unknown exit reason, %d", exit_reason.full); 1945 print_vmexit_info(exit_reason); 1946 } 1947 return VMX_TEST_VMEXIT; 1948 } 1949 1950 struct vmx_msr_entry { 1951 u32 index; 1952 u32 reserved; 1953 u64 value; 1954 } __attribute__((packed)); 1955 1956 #define MSR_MAGIC 0x31415926 1957 struct vmx_msr_entry *exit_msr_store, *entry_msr_load, *exit_msr_load; 1958 1959 static int msr_switch_init(struct vmcs *vmcs) 1960 { 1961 msr_bmp_init(); 1962 exit_msr_store = alloc_page(); 1963 exit_msr_load = alloc_page(); 1964 entry_msr_load = alloc_page(); 1965 entry_msr_load[0].index = MSR_KERNEL_GS_BASE; 1966 entry_msr_load[0].value = MSR_MAGIC; 1967 1968 vmx_set_test_stage(1); 1969 vmcs_write(ENT_MSR_LD_CNT, 1); 1970 vmcs_write(ENTER_MSR_LD_ADDR, (u64)entry_msr_load); 1971 vmcs_write(EXI_MSR_ST_CNT, 1); 1972 vmcs_write(EXIT_MSR_ST_ADDR, (u64)exit_msr_store); 1973 vmcs_write(EXI_MSR_LD_CNT, 1); 1974 vmcs_write(EXIT_MSR_LD_ADDR, (u64)exit_msr_load); 1975 return VMX_TEST_START; 1976 } 1977 1978 static void msr_switch_main(void) 1979 { 1980 if (vmx_get_test_stage() == 1) { 1981 report(rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC, 1982 "VM entry MSR load"); 1983 vmx_set_test_stage(2); 1984 wrmsr(MSR_KERNEL_GS_BASE, MSR_MAGIC + 1); 1985 exit_msr_store[0].index = MSR_KERNEL_GS_BASE; 1986 exit_msr_load[0].index = MSR_KERNEL_GS_BASE; 1987 exit_msr_load[0].value = MSR_MAGIC + 2; 1988 } 1989 vmcall(); 1990 } 1991 1992 static int msr_switch_exit_handler(union exit_reason exit_reason) 1993 { 1994 if (exit_reason.basic == VMX_VMCALL && vmx_get_test_stage() == 2) { 1995 report(exit_msr_store[0].value == MSR_MAGIC + 1, 1996 "VM exit MSR store"); 1997 report(rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC + 2, 1998 "VM exit MSR load"); 1999 vmx_set_test_stage(3); 2000 entry_msr_load[0].index = MSR_FS_BASE; 2001 return VMX_TEST_RESUME; 2002 } 2003 printf("ERROR %s: unexpected stage=%u or reason=0x%x\n", 2004 __func__, vmx_get_test_stage(), exit_reason.full); 2005 return VMX_TEST_EXIT; 2006 } 2007 2008 static int msr_switch_entry_failure(struct vmentry_result *result) 2009 { 2010 if (result->vm_fail) { 2011 printf("ERROR %s: VM-Fail on %s\n", __func__, result->instr); 2012 return VMX_TEST_EXIT; 2013 } 2014 2015 if (result->exit_reason.failed_vmentry && 2016 result->exit_reason.basic == VMX_FAIL_MSR && 2017 vmx_get_test_stage() == 3) { 2018 report(vmcs_read(EXI_QUALIFICATION) == 1, 2019 "VM entry MSR load: try to load FS_BASE"); 2020 return VMX_TEST_VMEXIT; 2021 } 2022 printf("ERROR %s: unexpected stage=%u or reason=%x\n", 2023 __func__, vmx_get_test_stage(), result->exit_reason.full); 2024 return VMX_TEST_EXIT; 2025 } 2026 2027 static int vmmcall_init(struct vmcs *vmcs) 2028 { 2029 vmcs_write(EXC_BITMAP, 1 << UD_VECTOR); 2030 return VMX_TEST_START; 2031 } 2032 2033 static void vmmcall_main(void) 2034 { 2035 asm volatile( 2036 "mov $0xABCD, %%rax\n\t" 2037 "vmmcall\n\t" 2038 ::: "rax"); 2039 2040 report_fail("VMMCALL"); 2041 } 2042 2043 static int vmmcall_exit_handler(union exit_reason exit_reason) 2044 { 2045 switch (exit_reason.basic) { 2046 case VMX_VMCALL: 2047 printf("here\n"); 2048 report_fail("VMMCALL triggers #UD"); 2049 break; 2050 case VMX_EXC_NMI: 2051 report((vmcs_read(EXI_INTR_INFO) & 0xff) == UD_VECTOR, 2052 "VMMCALL triggers #UD"); 2053 break; 2054 default: 2055 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 2056 print_vmexit_info(exit_reason); 2057 } 2058 2059 return VMX_TEST_VMEXIT; 2060 } 2061 2062 static int disable_rdtscp_init(struct vmcs *vmcs) 2063 { 2064 u32 ctrl_cpu1; 2065 2066 if (ctrl_cpu_rev[0].clr & CPU_SECONDARY) { 2067 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 2068 ctrl_cpu1 &= ~CPU_RDTSCP; 2069 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 2070 } 2071 2072 return VMX_TEST_START; 2073 } 2074 2075 static void disable_rdtscp_ud_handler(struct ex_regs *regs) 2076 { 2077 switch (vmx_get_test_stage()) { 2078 case 0: 2079 report_pass("RDTSCP triggers #UD"); 2080 vmx_inc_test_stage(); 2081 regs->rip += 3; 2082 break; 2083 case 2: 2084 report_pass("RDPID triggers #UD"); 2085 vmx_inc_test_stage(); 2086 regs->rip += 4; 2087 break; 2088 } 2089 return; 2090 2091 } 2092 2093 static void disable_rdtscp_main(void) 2094 { 2095 /* Test that #UD is properly injected in L2. */ 2096 handle_exception(UD_VECTOR, disable_rdtscp_ud_handler); 2097 2098 vmx_set_test_stage(0); 2099 asm volatile("rdtscp" : : : "eax", "ecx", "edx"); 2100 vmcall(); 2101 asm volatile(".byte 0xf3, 0x0f, 0xc7, 0xf8" : : : "eax"); 2102 2103 handle_exception(UD_VECTOR, 0); 2104 vmcall(); 2105 } 2106 2107 static int disable_rdtscp_exit_handler(union exit_reason exit_reason) 2108 { 2109 switch (exit_reason.basic) { 2110 case VMX_VMCALL: 2111 switch (vmx_get_test_stage()) { 2112 case 0: 2113 report_fail("RDTSCP triggers #UD"); 2114 vmx_inc_test_stage(); 2115 /* fallthrough */ 2116 case 1: 2117 vmx_inc_test_stage(); 2118 vmcs_write(GUEST_RIP, vmcs_read(GUEST_RIP) + 3); 2119 return VMX_TEST_RESUME; 2120 case 2: 2121 report_fail("RDPID triggers #UD"); 2122 break; 2123 } 2124 break; 2125 2126 default: 2127 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 2128 print_vmexit_info(exit_reason); 2129 } 2130 return VMX_TEST_VMEXIT; 2131 } 2132 2133 static int int3_init(struct vmcs *vmcs) 2134 { 2135 vmcs_write(EXC_BITMAP, ~0u); 2136 return VMX_TEST_START; 2137 } 2138 2139 static void int3_guest_main(void) 2140 { 2141 asm volatile ("int3"); 2142 } 2143 2144 static int int3_exit_handler(union exit_reason exit_reason) 2145 { 2146 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2147 2148 report(exit_reason.basic == VMX_EXC_NMI && 2149 (intr_info & INTR_INFO_VALID_MASK) && 2150 (intr_info & INTR_INFO_VECTOR_MASK) == BP_VECTOR && 2151 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2152 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION, 2153 "L1 intercepts #BP"); 2154 2155 return VMX_TEST_VMEXIT; 2156 } 2157 2158 static int into_init(struct vmcs *vmcs) 2159 { 2160 vmcs_write(EXC_BITMAP, ~0u); 2161 return VMX_TEST_START; 2162 } 2163 2164 static void into_guest_main(void) 2165 { 2166 struct far_pointer32 fp = { 2167 .offset = (uintptr_t)&&into, 2168 .selector = KERNEL_CS32, 2169 }; 2170 uintptr_t rsp; 2171 2172 asm volatile ("mov %%rsp, %0" : "=r"(rsp)); 2173 2174 if (fp.offset != (uintptr_t)&&into) { 2175 printf("Code address too high.\n"); 2176 return; 2177 } 2178 if ((u32)rsp != rsp) { 2179 printf("Stack address too high.\n"); 2180 return; 2181 } 2182 2183 asm goto ("lcall *%0" : : "m" (fp) : "rax" : into); 2184 return; 2185 into: 2186 asm volatile (".code32;" 2187 "movl $0x7fffffff, %eax;" 2188 "addl %eax, %eax;" 2189 "into;" 2190 "lret;" 2191 ".code64"); 2192 __builtin_unreachable(); 2193 } 2194 2195 static int into_exit_handler(union exit_reason exit_reason) 2196 { 2197 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2198 2199 report(exit_reason.basic == VMX_EXC_NMI && 2200 (intr_info & INTR_INFO_VALID_MASK) && 2201 (intr_info & INTR_INFO_VECTOR_MASK) == OF_VECTOR && 2202 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2203 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION, 2204 "L1 intercepts #OF"); 2205 2206 return VMX_TEST_VMEXIT; 2207 } 2208 2209 static void exit_monitor_from_l2_main(void) 2210 { 2211 printf("Calling exit(0) from l2...\n"); 2212 exit(0); 2213 } 2214 2215 static int exit_monitor_from_l2_handler(union exit_reason exit_reason) 2216 { 2217 report_fail("The guest should have killed the VMM"); 2218 return VMX_TEST_EXIT; 2219 } 2220 2221 static void assert_exit_reason(u64 expected) 2222 { 2223 u64 actual = vmcs_read(EXI_REASON); 2224 2225 TEST_ASSERT_EQ_MSG(expected, actual, "Expected %s, got %s.", 2226 exit_reason_description(expected), 2227 exit_reason_description(actual)); 2228 } 2229 2230 static void skip_exit_insn(void) 2231 { 2232 u64 guest_rip = vmcs_read(GUEST_RIP); 2233 u32 insn_len = vmcs_read(EXI_INST_LEN); 2234 vmcs_write(GUEST_RIP, guest_rip + insn_len); 2235 } 2236 2237 static void skip_exit_vmcall(void) 2238 { 2239 assert_exit_reason(VMX_VMCALL); 2240 skip_exit_insn(); 2241 } 2242 2243 static void v2_null_test_guest(void) 2244 { 2245 } 2246 2247 static void v2_null_test(void) 2248 { 2249 test_set_guest(v2_null_test_guest); 2250 enter_guest(); 2251 report_pass(__func__); 2252 } 2253 2254 static void v2_multiple_entries_test_guest(void) 2255 { 2256 vmx_set_test_stage(1); 2257 vmcall(); 2258 vmx_set_test_stage(2); 2259 } 2260 2261 static void v2_multiple_entries_test(void) 2262 { 2263 test_set_guest(v2_multiple_entries_test_guest); 2264 enter_guest(); 2265 TEST_ASSERT_EQ(vmx_get_test_stage(), 1); 2266 skip_exit_vmcall(); 2267 enter_guest(); 2268 TEST_ASSERT_EQ(vmx_get_test_stage(), 2); 2269 report_pass(__func__); 2270 } 2271 2272 static int fixture_test_data = 1; 2273 2274 static void fixture_test_teardown(void *data) 2275 { 2276 *((int *) data) = 1; 2277 } 2278 2279 static void fixture_test_guest(void) 2280 { 2281 fixture_test_data++; 2282 } 2283 2284 2285 static void fixture_test_setup(void) 2286 { 2287 TEST_ASSERT_EQ_MSG(1, fixture_test_data, 2288 "fixture_test_teardown didn't run?!"); 2289 fixture_test_data = 2; 2290 test_add_teardown(fixture_test_teardown, &fixture_test_data); 2291 test_set_guest(fixture_test_guest); 2292 } 2293 2294 static void fixture_test_case1(void) 2295 { 2296 fixture_test_setup(); 2297 TEST_ASSERT_EQ(2, fixture_test_data); 2298 enter_guest(); 2299 TEST_ASSERT_EQ(3, fixture_test_data); 2300 report_pass(__func__); 2301 } 2302 2303 static void fixture_test_case2(void) 2304 { 2305 fixture_test_setup(); 2306 TEST_ASSERT_EQ(2, fixture_test_data); 2307 enter_guest(); 2308 TEST_ASSERT_EQ(3, fixture_test_data); 2309 report_pass(__func__); 2310 } 2311 2312 enum ept_access_op { 2313 OP_READ, 2314 OP_WRITE, 2315 OP_EXEC, 2316 OP_FLUSH_TLB, 2317 OP_EXIT, 2318 }; 2319 2320 static struct ept_access_test_data { 2321 unsigned long gpa; 2322 unsigned long *gva; 2323 unsigned long hpa; 2324 unsigned long *hva; 2325 enum ept_access_op op; 2326 } ept_access_test_data; 2327 2328 extern unsigned char ret42_start; 2329 extern unsigned char ret42_end; 2330 2331 /* Returns 42. */ 2332 asm( 2333 ".align 64\n" 2334 "ret42_start:\n" 2335 "mov $42, %eax\n" 2336 "ret\n" 2337 "ret42_end:\n" 2338 ); 2339 2340 static void 2341 diagnose_ept_violation_qual(u64 expected, u64 actual) 2342 { 2343 2344 #define DIAGNOSE(flag) \ 2345 do { \ 2346 if ((expected & flag) != (actual & flag)) \ 2347 printf(#flag " %sexpected\n", \ 2348 (expected & flag) ? "" : "un"); \ 2349 } while (0) 2350 2351 DIAGNOSE(EPT_VLT_RD); 2352 DIAGNOSE(EPT_VLT_WR); 2353 DIAGNOSE(EPT_VLT_FETCH); 2354 DIAGNOSE(EPT_VLT_PERM_RD); 2355 DIAGNOSE(EPT_VLT_PERM_WR); 2356 DIAGNOSE(EPT_VLT_PERM_EX); 2357 DIAGNOSE(EPT_VLT_LADDR_VLD); 2358 DIAGNOSE(EPT_VLT_PADDR); 2359 2360 #undef DIAGNOSE 2361 } 2362 2363 static void do_ept_access_op(enum ept_access_op op) 2364 { 2365 ept_access_test_data.op = op; 2366 enter_guest(); 2367 } 2368 2369 /* 2370 * Force the guest to flush its TLB (i.e., flush gva -> gpa mappings). Only 2371 * needed by tests that modify guest PTEs. 2372 */ 2373 static void ept_access_test_guest_flush_tlb(void) 2374 { 2375 do_ept_access_op(OP_FLUSH_TLB); 2376 skip_exit_vmcall(); 2377 } 2378 2379 /* 2380 * Modifies the EPT entry at @level in the mapping of @gpa. First clears the 2381 * bits in @clear then sets the bits in @set. @mkhuge transforms the entry into 2382 * a huge page. 2383 */ 2384 static unsigned long ept_twiddle(unsigned long gpa, bool mkhuge, int level, 2385 unsigned long clear, unsigned long set) 2386 { 2387 struct ept_access_test_data *data = &ept_access_test_data; 2388 unsigned long orig_pte; 2389 unsigned long pte; 2390 2391 /* Screw with the mapping at the requested level. */ 2392 TEST_ASSERT(get_ept_pte(pml4, gpa, level, &orig_pte)); 2393 pte = orig_pte; 2394 if (mkhuge) 2395 pte = (orig_pte & ~EPT_ADDR_MASK) | data->hpa | EPT_LARGE_PAGE; 2396 else 2397 pte = orig_pte; 2398 pte = (pte & ~clear) | set; 2399 set_ept_pte(pml4, gpa, level, pte); 2400 invept(INVEPT_SINGLE, eptp); 2401 2402 return orig_pte; 2403 } 2404 2405 static void ept_untwiddle(unsigned long gpa, int level, unsigned long orig_pte) 2406 { 2407 set_ept_pte(pml4, gpa, level, orig_pte); 2408 invept(INVEPT_SINGLE, eptp); 2409 } 2410 2411 static void do_ept_violation(bool leaf, enum ept_access_op op, 2412 u64 expected_qual, u64 expected_paddr) 2413 { 2414 u64 qual; 2415 2416 /* Try the access and observe the violation. */ 2417 do_ept_access_op(op); 2418 2419 assert_exit_reason(VMX_EPT_VIOLATION); 2420 2421 qual = vmcs_read(EXI_QUALIFICATION); 2422 2423 /* Mask undefined bits (which may later be defined in certain cases). */ 2424 qual &= ~(EPT_VLT_GUEST_USER | EPT_VLT_GUEST_RW | EPT_VLT_GUEST_EX | 2425 EPT_VLT_PERM_USER_EX); 2426 2427 diagnose_ept_violation_qual(expected_qual, qual); 2428 TEST_EXPECT_EQ(expected_qual, qual); 2429 2430 #if 0 2431 /* Disable for now otherwise every test will fail */ 2432 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2433 (unsigned long) ( 2434 op == OP_EXEC ? data->gva + 1 : data->gva)); 2435 #endif 2436 /* 2437 * TODO: tests that probe expected_paddr in pages other than the one at 2438 * the beginning of the 1g region. 2439 */ 2440 TEST_EXPECT_EQ(vmcs_read(INFO_PHYS_ADDR), expected_paddr); 2441 } 2442 2443 static void 2444 ept_violation_at_level_mkhuge(bool mkhuge, int level, unsigned long clear, 2445 unsigned long set, enum ept_access_op op, 2446 u64 expected_qual) 2447 { 2448 struct ept_access_test_data *data = &ept_access_test_data; 2449 unsigned long orig_pte; 2450 2451 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2452 2453 do_ept_violation(level == 1 || mkhuge, op, expected_qual, 2454 op == OP_EXEC ? data->gpa + sizeof(unsigned long) : 2455 data->gpa); 2456 2457 /* Fix the violation and resume the op loop. */ 2458 ept_untwiddle(data->gpa, level, orig_pte); 2459 enter_guest(); 2460 skip_exit_vmcall(); 2461 } 2462 2463 static void 2464 ept_violation_at_level(int level, unsigned long clear, unsigned long set, 2465 enum ept_access_op op, u64 expected_qual) 2466 { 2467 ept_violation_at_level_mkhuge(false, level, clear, set, op, 2468 expected_qual); 2469 if (ept_huge_pages_supported(level)) 2470 ept_violation_at_level_mkhuge(true, level, clear, set, op, 2471 expected_qual); 2472 } 2473 2474 static void ept_violation(unsigned long clear, unsigned long set, 2475 enum ept_access_op op, u64 expected_qual) 2476 { 2477 ept_violation_at_level(1, clear, set, op, expected_qual); 2478 ept_violation_at_level(2, clear, set, op, expected_qual); 2479 ept_violation_at_level(3, clear, set, op, expected_qual); 2480 ept_violation_at_level(4, clear, set, op, expected_qual); 2481 } 2482 2483 static void ept_access_violation(unsigned long access, enum ept_access_op op, 2484 u64 expected_qual) 2485 { 2486 ept_violation(EPT_PRESENT, access, op, 2487 expected_qual | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2488 } 2489 2490 /* 2491 * For translations that don't involve a GVA, that is physical address (paddr) 2492 * accesses, EPT violations don't set the flag EPT_VLT_PADDR. For a typical 2493 * guest memory access, the hardware does GVA -> GPA -> HPA. However, certain 2494 * translations don't involve GVAs, such as when the hardware does the guest 2495 * page table walk. For example, in translating GVA_1 -> GPA_1, the guest MMU 2496 * might try to set an A bit on a guest PTE. If the GPA_2 that the PTE resides 2497 * on isn't present in the EPT, then the EPT violation will be for GPA_2 and 2498 * the EPT_VLT_PADDR bit will be clear in the exit qualification. 2499 * 2500 * Note that paddr violations can also be triggered by loading PAE page tables 2501 * with wonky addresses. We don't test that yet. 2502 * 2503 * This function modifies the EPT entry that maps the GPA that the guest page 2504 * table entry mapping ept_access_test_data.gva resides on. 2505 * 2506 * @ept_access EPT permissions to set. Other permissions are cleared. 2507 * 2508 * @pte_ad Set the A/D bits on the guest PTE accordingly. 2509 * 2510 * @op Guest operation to perform with 2511 * ept_access_test_data.gva. 2512 * 2513 * @expect_violation 2514 * Is a violation expected during the paddr access? 2515 * 2516 * @expected_qual Expected qualification for the EPT violation. 2517 * EPT_VLT_PADDR should be clear. 2518 */ 2519 static void ept_access_paddr(unsigned long ept_access, unsigned long pte_ad, 2520 enum ept_access_op op, bool expect_violation, 2521 u64 expected_qual) 2522 { 2523 struct ept_access_test_data *data = &ept_access_test_data; 2524 unsigned long *ptep; 2525 unsigned long gpa; 2526 unsigned long orig_epte; 2527 unsigned long epte; 2528 int i; 2529 2530 /* Modify the guest PTE mapping data->gva according to @pte_ad. */ 2531 ptep = get_pte_level(current_page_table(), data->gva, /*level=*/1); 2532 TEST_ASSERT(ptep); 2533 TEST_ASSERT_EQ(*ptep & PT_ADDR_MASK, data->gpa); 2534 *ptep = (*ptep & ~PT_AD_MASK) | pte_ad; 2535 ept_access_test_guest_flush_tlb(); 2536 2537 /* 2538 * Now modify the access bits on the EPT entry for the GPA that the 2539 * guest PTE resides on. Note that by modifying a single EPT entry, 2540 * we're potentially affecting 512 guest PTEs. However, we've carefully 2541 * constructed our test such that those other 511 PTEs aren't used by 2542 * the guest: data->gva is at the beginning of a 1G huge page, thus the 2543 * PTE we're modifying is at the beginning of a 4K page and the 2544 * following 511 entires are also under our control (and not touched by 2545 * the guest). 2546 */ 2547 gpa = virt_to_phys(ptep); 2548 TEST_ASSERT_EQ(gpa & ~PAGE_MASK, 0); 2549 /* 2550 * Make sure the guest page table page is mapped with a 4K EPT entry, 2551 * otherwise our level=1 twiddling below will fail. We use the 2552 * identity map (gpa = gpa) since page tables are shared with the host. 2553 */ 2554 install_ept(pml4, gpa, gpa, EPT_PRESENT); 2555 orig_epte = ept_twiddle(gpa, /*mkhuge=*/0, /*level=*/1, 2556 /*clear=*/EPT_PRESENT, /*set=*/ept_access); 2557 2558 if (expect_violation) { 2559 do_ept_violation(/*leaf=*/true, op, 2560 expected_qual | EPT_VLT_LADDR_VLD, gpa); 2561 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2562 do_ept_access_op(op); 2563 } else { 2564 do_ept_access_op(op); 2565 if (ept_ad_enabled()) { 2566 for (i = EPT_PAGE_LEVEL; i > 0; i--) { 2567 TEST_ASSERT(get_ept_pte(pml4, gpa, i, &epte)); 2568 TEST_ASSERT(epte & EPT_ACCESS_FLAG); 2569 if (i == 1) 2570 TEST_ASSERT(epte & EPT_DIRTY_FLAG); 2571 else 2572 TEST_ASSERT_EQ(epte & EPT_DIRTY_FLAG, 0); 2573 } 2574 } 2575 2576 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2577 } 2578 2579 TEST_ASSERT(*ptep & PT_ACCESSED_MASK); 2580 if ((pte_ad & PT_DIRTY_MASK) || op == OP_WRITE) 2581 TEST_ASSERT(*ptep & PT_DIRTY_MASK); 2582 2583 skip_exit_vmcall(); 2584 } 2585 2586 static void ept_access_allowed_paddr(unsigned long ept_access, 2587 unsigned long pte_ad, 2588 enum ept_access_op op) 2589 { 2590 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/false, 2591 /*expected_qual=*/-1); 2592 } 2593 2594 static void ept_access_violation_paddr(unsigned long ept_access, 2595 unsigned long pte_ad, 2596 enum ept_access_op op, 2597 u64 expected_qual) 2598 { 2599 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/true, 2600 expected_qual); 2601 } 2602 2603 2604 static void ept_allowed_at_level_mkhuge(bool mkhuge, int level, 2605 unsigned long clear, 2606 unsigned long set, 2607 enum ept_access_op op) 2608 { 2609 struct ept_access_test_data *data = &ept_access_test_data; 2610 unsigned long orig_pte; 2611 2612 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2613 2614 /* No violation. Should proceed to vmcall. */ 2615 do_ept_access_op(op); 2616 skip_exit_vmcall(); 2617 2618 ept_untwiddle(data->gpa, level, orig_pte); 2619 } 2620 2621 static void ept_allowed_at_level(int level, unsigned long clear, 2622 unsigned long set, enum ept_access_op op) 2623 { 2624 ept_allowed_at_level_mkhuge(false, level, clear, set, op); 2625 if (ept_huge_pages_supported(level)) 2626 ept_allowed_at_level_mkhuge(true, level, clear, set, op); 2627 } 2628 2629 static void ept_allowed(unsigned long clear, unsigned long set, 2630 enum ept_access_op op) 2631 { 2632 ept_allowed_at_level(1, clear, set, op); 2633 ept_allowed_at_level(2, clear, set, op); 2634 ept_allowed_at_level(3, clear, set, op); 2635 ept_allowed_at_level(4, clear, set, op); 2636 } 2637 2638 static void ept_ignored_bit(int bit) 2639 { 2640 /* Set the bit. */ 2641 ept_allowed(0, 1ul << bit, OP_READ); 2642 ept_allowed(0, 1ul << bit, OP_WRITE); 2643 ept_allowed(0, 1ul << bit, OP_EXEC); 2644 2645 /* Clear the bit. */ 2646 ept_allowed(1ul << bit, 0, OP_READ); 2647 ept_allowed(1ul << bit, 0, OP_WRITE); 2648 ept_allowed(1ul << bit, 0, OP_EXEC); 2649 } 2650 2651 static void ept_access_allowed(unsigned long access, enum ept_access_op op) 2652 { 2653 ept_allowed(EPT_PRESENT, access, op); 2654 } 2655 2656 2657 static void ept_misconfig_at_level_mkhuge_op(bool mkhuge, int level, 2658 unsigned long clear, 2659 unsigned long set, 2660 enum ept_access_op op) 2661 { 2662 struct ept_access_test_data *data = &ept_access_test_data; 2663 unsigned long orig_pte; 2664 2665 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2666 2667 do_ept_access_op(op); 2668 assert_exit_reason(VMX_EPT_MISCONFIG); 2669 2670 /* Intel 27.2.1, "For all other VM exits, this field is cleared." */ 2671 #if 0 2672 /* broken: */ 2673 TEST_EXPECT_EQ_MSG(vmcs_read(EXI_QUALIFICATION), 0); 2674 #endif 2675 #if 0 2676 /* 2677 * broken: 2678 * According to description of exit qual for EPT violation, 2679 * EPT_VLT_LADDR_VLD indicates if GUEST_LINEAR_ADDRESS is valid. 2680 * However, I can't find anything that says GUEST_LINEAR_ADDRESS ought 2681 * to be set for msiconfig. 2682 */ 2683 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2684 (unsigned long) ( 2685 op == OP_EXEC ? data->gva + 1 : data->gva)); 2686 #endif 2687 2688 /* Fix the violation and resume the op loop. */ 2689 ept_untwiddle(data->gpa, level, orig_pte); 2690 enter_guest(); 2691 skip_exit_vmcall(); 2692 } 2693 2694 static void ept_misconfig_at_level_mkhuge(bool mkhuge, int level, 2695 unsigned long clear, 2696 unsigned long set) 2697 { 2698 /* The op shouldn't matter (read, write, exec), so try them all! */ 2699 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_READ); 2700 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_WRITE); 2701 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_EXEC); 2702 } 2703 2704 static void ept_misconfig_at_level(int level, unsigned long clear, 2705 unsigned long set) 2706 { 2707 ept_misconfig_at_level_mkhuge(false, level, clear, set); 2708 if (ept_huge_pages_supported(level)) 2709 ept_misconfig_at_level_mkhuge(true, level, clear, set); 2710 } 2711 2712 static void ept_misconfig(unsigned long clear, unsigned long set) 2713 { 2714 ept_misconfig_at_level(1, clear, set); 2715 ept_misconfig_at_level(2, clear, set); 2716 ept_misconfig_at_level(3, clear, set); 2717 ept_misconfig_at_level(4, clear, set); 2718 } 2719 2720 static void ept_access_misconfig(unsigned long access) 2721 { 2722 ept_misconfig(EPT_PRESENT, access); 2723 } 2724 2725 static void ept_reserved_bit_at_level_nohuge(int level, int bit) 2726 { 2727 /* Setting the bit causes a misconfig. */ 2728 ept_misconfig_at_level_mkhuge(false, level, 0, 1ul << bit); 2729 2730 /* Making the entry non-present turns reserved bits into ignored. */ 2731 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2732 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2733 } 2734 2735 static void ept_reserved_bit_at_level_huge(int level, int bit) 2736 { 2737 /* Setting the bit causes a misconfig. */ 2738 ept_misconfig_at_level_mkhuge(true, level, 0, 1ul << bit); 2739 2740 /* Making the entry non-present turns reserved bits into ignored. */ 2741 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2742 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2743 } 2744 2745 static void ept_reserved_bit_at_level(int level, int bit) 2746 { 2747 /* Setting the bit causes a misconfig. */ 2748 ept_misconfig_at_level(level, 0, 1ul << bit); 2749 2750 /* Making the entry non-present turns reserved bits into ignored. */ 2751 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2752 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2753 } 2754 2755 static void ept_reserved_bit(int bit) 2756 { 2757 ept_reserved_bit_at_level(1, bit); 2758 ept_reserved_bit_at_level(2, bit); 2759 ept_reserved_bit_at_level(3, bit); 2760 ept_reserved_bit_at_level(4, bit); 2761 } 2762 2763 #define PAGE_2M_ORDER 9 2764 #define PAGE_1G_ORDER 18 2765 2766 static void *get_1g_page(void) 2767 { 2768 static void *alloc; 2769 2770 if (!alloc) 2771 alloc = alloc_pages(PAGE_1G_ORDER); 2772 return alloc; 2773 } 2774 2775 static void ept_access_test_teardown(void *unused) 2776 { 2777 /* Exit the guest cleanly. */ 2778 do_ept_access_op(OP_EXIT); 2779 } 2780 2781 static void ept_access_test_guest(void) 2782 { 2783 struct ept_access_test_data *data = &ept_access_test_data; 2784 int (*code)(void) = (int (*)(void)) &data->gva[1]; 2785 2786 while (true) { 2787 switch (data->op) { 2788 case OP_READ: 2789 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_1); 2790 break; 2791 case OP_WRITE: 2792 *data->gva = MAGIC_VAL_2; 2793 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_2); 2794 *data->gva = MAGIC_VAL_1; 2795 break; 2796 case OP_EXEC: 2797 TEST_ASSERT_EQ(42, code()); 2798 break; 2799 case OP_FLUSH_TLB: 2800 write_cr3(read_cr3()); 2801 break; 2802 case OP_EXIT: 2803 return; 2804 default: 2805 TEST_ASSERT_MSG(false, "Unknown op %d", data->op); 2806 } 2807 vmcall(); 2808 } 2809 } 2810 2811 static void ept_access_test_setup(void) 2812 { 2813 struct ept_access_test_data *data = &ept_access_test_data; 2814 unsigned long npages = 1ul << PAGE_1G_ORDER; 2815 unsigned long size = npages * PAGE_SIZE; 2816 unsigned long *page_table = current_page_table(); 2817 unsigned long pte; 2818 2819 if (setup_ept(false)) 2820 test_skip("EPT not supported"); 2821 2822 /* We use data->gpa = 1 << 39 so that test data has a separate pml4 entry */ 2823 if (cpuid_maxphyaddr() < 40) 2824 test_skip("Test needs MAXPHYADDR >= 40"); 2825 2826 test_set_guest(ept_access_test_guest); 2827 test_add_teardown(ept_access_test_teardown, NULL); 2828 2829 data->hva = get_1g_page(); 2830 TEST_ASSERT(data->hva); 2831 data->hpa = virt_to_phys(data->hva); 2832 2833 data->gpa = 1ul << 39; 2834 data->gva = (void *) ALIGN((unsigned long) alloc_vpages(npages * 2), 2835 size); 2836 TEST_ASSERT(!any_present_pages(page_table, data->gva, size)); 2837 install_pages(page_table, data->gpa, size, data->gva); 2838 2839 /* 2840 * Make sure nothing's mapped here so the tests that screw with the 2841 * pml4 entry don't inadvertently break something. 2842 */ 2843 TEST_ASSERT(get_ept_pte(pml4, data->gpa, 4, &pte) && pte == 0); 2844 TEST_ASSERT(get_ept_pte(pml4, data->gpa + size - 1, 4, &pte) && pte == 0); 2845 install_ept(pml4, data->hpa, data->gpa, EPT_PRESENT); 2846 2847 data->hva[0] = MAGIC_VAL_1; 2848 memcpy(&data->hva[1], &ret42_start, &ret42_end - &ret42_start); 2849 } 2850 2851 static void ept_access_test_not_present(void) 2852 { 2853 ept_access_test_setup(); 2854 /* --- */ 2855 ept_access_violation(0, OP_READ, EPT_VLT_RD); 2856 ept_access_violation(0, OP_WRITE, EPT_VLT_WR); 2857 ept_access_violation(0, OP_EXEC, EPT_VLT_FETCH); 2858 } 2859 2860 static void ept_access_test_read_only(void) 2861 { 2862 ept_access_test_setup(); 2863 2864 /* r-- */ 2865 ept_access_allowed(EPT_RA, OP_READ); 2866 ept_access_violation(EPT_RA, OP_WRITE, EPT_VLT_WR | EPT_VLT_PERM_RD); 2867 ept_access_violation(EPT_RA, OP_EXEC, EPT_VLT_FETCH | EPT_VLT_PERM_RD); 2868 } 2869 2870 static void ept_access_test_write_only(void) 2871 { 2872 ept_access_test_setup(); 2873 /* -w- */ 2874 ept_access_misconfig(EPT_WA); 2875 } 2876 2877 static void ept_access_test_read_write(void) 2878 { 2879 ept_access_test_setup(); 2880 /* rw- */ 2881 ept_access_allowed(EPT_RA | EPT_WA, OP_READ); 2882 ept_access_allowed(EPT_RA | EPT_WA, OP_WRITE); 2883 ept_access_violation(EPT_RA | EPT_WA, OP_EXEC, 2884 EPT_VLT_FETCH | EPT_VLT_PERM_RD | EPT_VLT_PERM_WR); 2885 } 2886 2887 2888 static void ept_access_test_execute_only(void) 2889 { 2890 ept_access_test_setup(); 2891 /* --x */ 2892 if (ept_execute_only_supported()) { 2893 ept_access_violation(EPT_EA, OP_READ, 2894 EPT_VLT_RD | EPT_VLT_PERM_EX); 2895 ept_access_violation(EPT_EA, OP_WRITE, 2896 EPT_VLT_WR | EPT_VLT_PERM_EX); 2897 ept_access_allowed(EPT_EA, OP_EXEC); 2898 } else { 2899 ept_access_misconfig(EPT_EA); 2900 } 2901 } 2902 2903 static void ept_access_test_read_execute(void) 2904 { 2905 ept_access_test_setup(); 2906 /* r-x */ 2907 ept_access_allowed(EPT_RA | EPT_EA, OP_READ); 2908 ept_access_violation(EPT_RA | EPT_EA, OP_WRITE, 2909 EPT_VLT_WR | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX); 2910 ept_access_allowed(EPT_RA | EPT_EA, OP_EXEC); 2911 } 2912 2913 static void ept_access_test_write_execute(void) 2914 { 2915 ept_access_test_setup(); 2916 /* -wx */ 2917 ept_access_misconfig(EPT_WA | EPT_EA); 2918 } 2919 2920 static void ept_access_test_read_write_execute(void) 2921 { 2922 ept_access_test_setup(); 2923 /* rwx */ 2924 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_READ); 2925 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_WRITE); 2926 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_EXEC); 2927 } 2928 2929 static void ept_access_test_reserved_bits(void) 2930 { 2931 int i; 2932 int maxphyaddr; 2933 2934 ept_access_test_setup(); 2935 2936 /* Reserved bits above maxphyaddr. */ 2937 maxphyaddr = cpuid_maxphyaddr(); 2938 for (i = maxphyaddr; i <= 51; i++) { 2939 report_prefix_pushf("reserved_bit=%d", i); 2940 ept_reserved_bit(i); 2941 report_prefix_pop(); 2942 } 2943 2944 /* Level-specific reserved bits. */ 2945 ept_reserved_bit_at_level_nohuge(2, 3); 2946 ept_reserved_bit_at_level_nohuge(2, 4); 2947 ept_reserved_bit_at_level_nohuge(2, 5); 2948 ept_reserved_bit_at_level_nohuge(2, 6); 2949 /* 2M alignment. */ 2950 for (i = 12; i < 20; i++) { 2951 report_prefix_pushf("reserved_bit=%d", i); 2952 ept_reserved_bit_at_level_huge(2, i); 2953 report_prefix_pop(); 2954 } 2955 ept_reserved_bit_at_level_nohuge(3, 3); 2956 ept_reserved_bit_at_level_nohuge(3, 4); 2957 ept_reserved_bit_at_level_nohuge(3, 5); 2958 ept_reserved_bit_at_level_nohuge(3, 6); 2959 /* 1G alignment. */ 2960 for (i = 12; i < 29; i++) { 2961 report_prefix_pushf("reserved_bit=%d", i); 2962 ept_reserved_bit_at_level_huge(3, i); 2963 report_prefix_pop(); 2964 } 2965 ept_reserved_bit_at_level(4, 3); 2966 ept_reserved_bit_at_level(4, 4); 2967 ept_reserved_bit_at_level(4, 5); 2968 ept_reserved_bit_at_level(4, 6); 2969 ept_reserved_bit_at_level(4, 7); 2970 } 2971 2972 static void ept_access_test_ignored_bits(void) 2973 { 2974 ept_access_test_setup(); 2975 /* 2976 * Bits ignored at every level. Bits 8 and 9 (A and D) are ignored as 2977 * far as translation is concerned even if AD bits are enabled in the 2978 * EPTP. Bit 63 is ignored because "EPT-violation #VE" VM-execution 2979 * control is 0. 2980 */ 2981 ept_ignored_bit(8); 2982 ept_ignored_bit(9); 2983 ept_ignored_bit(10); 2984 ept_ignored_bit(11); 2985 ept_ignored_bit(52); 2986 ept_ignored_bit(53); 2987 ept_ignored_bit(54); 2988 ept_ignored_bit(55); 2989 ept_ignored_bit(56); 2990 ept_ignored_bit(57); 2991 ept_ignored_bit(58); 2992 ept_ignored_bit(59); 2993 ept_ignored_bit(60); 2994 ept_ignored_bit(61); 2995 ept_ignored_bit(62); 2996 ept_ignored_bit(63); 2997 } 2998 2999 static void ept_access_test_paddr_not_present_ad_disabled(void) 3000 { 3001 ept_access_test_setup(); 3002 ept_disable_ad_bits(); 3003 3004 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, EPT_VLT_RD); 3005 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, EPT_VLT_RD); 3006 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, EPT_VLT_RD); 3007 } 3008 3009 static void ept_access_test_paddr_not_present_ad_enabled(void) 3010 { 3011 u64 qual = EPT_VLT_RD | EPT_VLT_WR; 3012 3013 ept_access_test_setup(); 3014 ept_enable_ad_bits_or_skip_test(); 3015 3016 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, qual); 3017 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, qual); 3018 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, qual); 3019 } 3020 3021 static void ept_access_test_paddr_read_only_ad_disabled(void) 3022 { 3023 /* 3024 * When EPT AD bits are disabled, all accesses to guest paging 3025 * structures are reported separately as a read and (after 3026 * translation of the GPA to host physical address) a read+write 3027 * if the A/D bits have to be set. 3028 */ 3029 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 3030 3031 ept_access_test_setup(); 3032 ept_disable_ad_bits(); 3033 3034 /* Can't update A bit, so all accesses fail. */ 3035 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 3036 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 3037 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 3038 /* AD bits disabled, so only writes try to update the D bit. */ 3039 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ); 3040 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 3041 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC); 3042 /* Both A and D already set, so read-only is OK. */ 3043 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_READ); 3044 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_WRITE); 3045 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_EXEC); 3046 } 3047 3048 static void ept_access_test_paddr_read_only_ad_enabled(void) 3049 { 3050 /* 3051 * When EPT AD bits are enabled, all accesses to guest paging 3052 * structures are considered writes as far as EPT translation 3053 * is concerned. 3054 */ 3055 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 3056 3057 ept_access_test_setup(); 3058 ept_enable_ad_bits_or_skip_test(); 3059 3060 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 3061 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 3062 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 3063 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ, qual); 3064 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 3065 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC, qual); 3066 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_READ, qual); 3067 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_WRITE, qual); 3068 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_EXEC, qual); 3069 } 3070 3071 static void ept_access_test_paddr_read_write(void) 3072 { 3073 ept_access_test_setup(); 3074 /* Read-write access to paging structure. */ 3075 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_READ); 3076 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_WRITE); 3077 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_EXEC); 3078 } 3079 3080 static void ept_access_test_paddr_read_write_execute(void) 3081 { 3082 ept_access_test_setup(); 3083 /* RWX access to paging structure. */ 3084 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_READ); 3085 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_WRITE); 3086 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_EXEC); 3087 } 3088 3089 static void ept_access_test_paddr_read_execute_ad_disabled(void) 3090 { 3091 /* 3092 * When EPT AD bits are disabled, all accesses to guest paging 3093 * structures are reported separately as a read and (after 3094 * translation of the GPA to host physical address) a read+write 3095 * if the A/D bits have to be set. 3096 */ 3097 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3098 3099 ept_access_test_setup(); 3100 ept_disable_ad_bits(); 3101 3102 /* Can't update A bit, so all accesses fail. */ 3103 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3104 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3105 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3106 /* AD bits disabled, so only writes try to update the D bit. */ 3107 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ); 3108 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3109 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC); 3110 /* Both A and D already set, so read-only is OK. */ 3111 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ); 3112 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE); 3113 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC); 3114 } 3115 3116 static void ept_access_test_paddr_read_execute_ad_enabled(void) 3117 { 3118 /* 3119 * When EPT AD bits are enabled, all accesses to guest paging 3120 * structures are considered writes as far as EPT translation 3121 * is concerned. 3122 */ 3123 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3124 3125 ept_access_test_setup(); 3126 ept_enable_ad_bits_or_skip_test(); 3127 3128 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3129 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3130 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3131 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ, qual); 3132 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3133 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC, qual); 3134 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ, qual); 3135 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE, qual); 3136 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC, qual); 3137 } 3138 3139 static void ept_access_test_paddr_not_present_page_fault(void) 3140 { 3141 ept_access_test_setup(); 3142 /* 3143 * TODO: test no EPT violation as long as guest PF occurs. e.g., GPA is 3144 * page is read-only in EPT but GVA is also mapped read only in PT. 3145 * Thus guest page fault before host takes EPT violation for trying to 3146 * update A bit. 3147 */ 3148 } 3149 3150 static void ept_access_test_force_2m_page(void) 3151 { 3152 ept_access_test_setup(); 3153 3154 TEST_ASSERT_EQ(ept_2m_supported(), true); 3155 ept_allowed_at_level_mkhuge(true, 2, 0, 0, OP_READ); 3156 ept_violation_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_RA, OP_WRITE, 3157 EPT_VLT_WR | EPT_VLT_PERM_RD | 3158 EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 3159 ept_misconfig_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_WA); 3160 } 3161 3162 static bool invvpid_valid(u64 type, u64 vpid, u64 gla) 3163 { 3164 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3165 3166 TEST_ASSERT(msr & VPID_CAP_INVVPID); 3167 3168 if (type < INVVPID_ADDR || type > INVVPID_CONTEXT_LOCAL) 3169 return false; 3170 3171 if (!(msr & (1ull << (type + VPID_CAP_INVVPID_TYPES_SHIFT)))) 3172 return false; 3173 3174 if (vpid >> 16) 3175 return false; 3176 3177 if (type != INVVPID_ALL && !vpid) 3178 return false; 3179 3180 if (type == INVVPID_ADDR && !is_canonical(gla)) 3181 return false; 3182 3183 return true; 3184 } 3185 3186 static void try_invvpid(u64 type, u64 vpid, u64 gla) 3187 { 3188 int rc; 3189 bool valid = invvpid_valid(type, vpid, gla); 3190 u64 expected = valid ? VMXERR_UNSUPPORTED_VMCS_COMPONENT 3191 : VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID; 3192 /* 3193 * Set VMX_INST_ERROR to VMXERR_UNVALID_VMCS_COMPONENT, so 3194 * that we can tell if it is updated by INVVPID. 3195 */ 3196 vmcs_read(~0); 3197 rc = __invvpid(type, vpid, gla); 3198 report(!rc == valid, "INVVPID type %ld VPID %lx GLA %lx %s", type, 3199 vpid, gla, 3200 valid ? "passes" : "fails"); 3201 report(vmcs_read(VMX_INST_ERROR) == expected, 3202 "After %s INVVPID, VMX_INST_ERR is %ld (actual %ld)", 3203 rc ? "failed" : "successful", 3204 expected, vmcs_read(VMX_INST_ERROR)); 3205 } 3206 3207 static void ds_invvpid(void *data) 3208 { 3209 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3210 u64 type = ffs(msr >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 3211 3212 TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 3213 asm volatile("invvpid %0, %1" 3214 : 3215 : "m"(*(struct invvpid_operand *)data), 3216 "r"(type)); 3217 } 3218 3219 /* 3220 * The SS override is ignored in 64-bit mode, so we use an addressing 3221 * mode with %rsp as the base register to generate an implicit SS 3222 * reference. 3223 */ 3224 static void ss_invvpid(void *data) 3225 { 3226 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3227 u64 type = ffs(msr >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 3228 3229 TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 3230 asm volatile("sub %%rsp,%0; invvpid (%%rsp,%0,1), %1" 3231 : "+r"(data) 3232 : "r"(type)); 3233 } 3234 3235 static void invvpid_test_gp(void) 3236 { 3237 bool fault; 3238 3239 fault = test_for_exception(GP_VECTOR, &ds_invvpid, 3240 (void *)NONCANONICAL); 3241 report(fault, "INVVPID with non-canonical DS operand raises #GP"); 3242 } 3243 3244 static void invvpid_test_ss(void) 3245 { 3246 bool fault; 3247 3248 fault = test_for_exception(SS_VECTOR, &ss_invvpid, 3249 (void *)NONCANONICAL); 3250 report(fault, "INVVPID with non-canonical SS operand raises #SS"); 3251 } 3252 3253 static void invvpid_test_pf(void) 3254 { 3255 void *vpage = alloc_vpage(); 3256 bool fault; 3257 3258 fault = test_for_exception(PF_VECTOR, &ds_invvpid, vpage); 3259 report(fault, "INVVPID with unmapped operand raises #PF"); 3260 } 3261 3262 static void try_compat_invvpid(void *unused) 3263 { 3264 struct far_pointer32 fp = { 3265 .offset = (uintptr_t)&&invvpid, 3266 .selector = KERNEL_CS32, 3267 }; 3268 uintptr_t rsp; 3269 3270 asm volatile ("mov %%rsp, %0" : "=r"(rsp)); 3271 3272 TEST_ASSERT_MSG(fp.offset == (uintptr_t)&&invvpid, 3273 "Code address too high."); 3274 TEST_ASSERT_MSG(rsp == (u32)rsp, "Stack address too high."); 3275 3276 asm goto ("lcall *%0" : : "m" (fp) : "rax" : invvpid); 3277 return; 3278 invvpid: 3279 asm volatile (".code32;" 3280 "invvpid (%eax), %eax;" 3281 "lret;" 3282 ".code64"); 3283 __builtin_unreachable(); 3284 } 3285 3286 static void invvpid_test_compatibility_mode(void) 3287 { 3288 bool fault; 3289 3290 fault = test_for_exception(UD_VECTOR, &try_compat_invvpid, NULL); 3291 report(fault, "Compatibility mode INVVPID raises #UD"); 3292 } 3293 3294 static void invvpid_test_not_in_vmx_operation(void) 3295 { 3296 bool fault; 3297 3298 TEST_ASSERT(!vmx_off()); 3299 fault = test_for_exception(UD_VECTOR, &ds_invvpid, NULL); 3300 report(fault, "INVVPID outside of VMX operation raises #UD"); 3301 TEST_ASSERT(!vmx_on()); 3302 } 3303 3304 /* 3305 * This does not test real-address mode, virtual-8086 mode, protected mode, 3306 * or CPL > 0. 3307 */ 3308 static void invvpid_test(void) 3309 { 3310 u64 msr; 3311 int i; 3312 unsigned types = 0; 3313 unsigned type; 3314 3315 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 3316 !(ctrl_cpu_rev[1].clr & CPU_VPID)) 3317 test_skip("VPID not supported"); 3318 3319 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3320 3321 if (!(msr & VPID_CAP_INVVPID)) 3322 test_skip("INVVPID not supported.\n"); 3323 3324 if (msr & VPID_CAP_INVVPID_ADDR) 3325 types |= 1u << INVVPID_ADDR; 3326 if (msr & VPID_CAP_INVVPID_CXTGLB) 3327 types |= 1u << INVVPID_CONTEXT_GLOBAL; 3328 if (msr & VPID_CAP_INVVPID_ALL) 3329 types |= 1u << INVVPID_ALL; 3330 if (msr & VPID_CAP_INVVPID_CXTLOC) 3331 types |= 1u << INVVPID_CONTEXT_LOCAL; 3332 3333 if (!types) 3334 test_skip("No INVVPID types supported.\n"); 3335 3336 for (i = -127; i < 128; i++) 3337 try_invvpid(i, 0xffff, 0); 3338 3339 /* 3340 * VPID must not be more than 16 bits. 3341 */ 3342 for (i = 0; i < 64; i++) 3343 for (type = 0; type < 4; type++) 3344 if (types & (1u << type)) 3345 try_invvpid(type, 1ul << i, 0); 3346 3347 /* 3348 * VPID must not be zero, except for "all contexts." 3349 */ 3350 for (type = 0; type < 4; type++) 3351 if (types & (1u << type)) 3352 try_invvpid(type, 0, 0); 3353 3354 /* 3355 * The gla operand is only validated for single-address INVVPID. 3356 */ 3357 if (types & (1u << INVVPID_ADDR)) 3358 try_invvpid(INVVPID_ADDR, 0xffff, NONCANONICAL); 3359 3360 invvpid_test_gp(); 3361 invvpid_test_ss(); 3362 invvpid_test_pf(); 3363 invvpid_test_compatibility_mode(); 3364 invvpid_test_not_in_vmx_operation(); 3365 } 3366 3367 /* 3368 * Test for early VMLAUNCH failure. Returns true if VMLAUNCH makes it 3369 * at least as far as the guest-state checks. Returns false if the 3370 * VMLAUNCH fails early and execution falls through to the next 3371 * instruction. 3372 */ 3373 static bool vmlaunch_succeeds(void) 3374 { 3375 u32 exit_reason; 3376 3377 /* 3378 * Indirectly set VMX_INST_ERR to 12 ("VMREAD/VMWRITE from/to 3379 * unsupported VMCS component"). The caller can then check 3380 * to see if a failed VM-entry sets VMX_INST_ERR as expected. 3381 */ 3382 vmcs_write(~0u, 0); 3383 3384 vmcs_write(HOST_RIP, (uintptr_t)&&success); 3385 __asm__ __volatile__ goto ("vmwrite %%rsp, %0; vmlaunch" 3386 : 3387 : "r" ((u64)HOST_RSP) 3388 : "cc", "memory" 3389 : success); 3390 return false; 3391 success: 3392 exit_reason = vmcs_read(EXI_REASON); 3393 TEST_ASSERT(exit_reason == (VMX_FAIL_STATE | VMX_ENTRY_FAILURE) || 3394 exit_reason == (VMX_FAIL_MSR | VMX_ENTRY_FAILURE)); 3395 return true; 3396 } 3397 3398 /* 3399 * Try to launch the current VMCS. 3400 */ 3401 static void test_vmx_vmlaunch(u32 xerror) 3402 { 3403 bool success = vmlaunch_succeeds(); 3404 u32 vmx_inst_err; 3405 3406 report(success == !xerror, "vmlaunch %s", 3407 !xerror ? "succeeds" : "fails"); 3408 if (!success && xerror) { 3409 vmx_inst_err = vmcs_read(VMX_INST_ERROR); 3410 report(vmx_inst_err == xerror, 3411 "VMX inst error is %d (actual %d)", xerror, 3412 vmx_inst_err); 3413 } 3414 } 3415 3416 /* 3417 * Try to launch the current VMCS, and expect one of two possible 3418 * errors (or success) codes. 3419 */ 3420 static void test_vmx_vmlaunch2(u32 xerror1, u32 xerror2) 3421 { 3422 bool success = vmlaunch_succeeds(); 3423 u32 vmx_inst_err; 3424 3425 if (!xerror1 == !xerror2) 3426 report(success == !xerror1, "vmlaunch %s", 3427 !xerror1 ? "succeeds" : "fails"); 3428 3429 if (!success && (xerror1 || xerror2)) { 3430 vmx_inst_err = vmcs_read(VMX_INST_ERROR); 3431 report(vmx_inst_err == xerror1 || vmx_inst_err == xerror2, 3432 "VMX inst error is %d or %d (actual %d)", xerror1, 3433 xerror2, vmx_inst_err); 3434 } 3435 } 3436 3437 static void test_vmx_invalid_controls(void) 3438 { 3439 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_CONTROL_FIELD); 3440 } 3441 3442 static void test_vmx_valid_controls(void) 3443 { 3444 test_vmx_vmlaunch(0); 3445 } 3446 3447 /* 3448 * Test a particular value of a VM-execution control bit, if the value 3449 * is required or if the value is zero. 3450 */ 3451 static void test_rsvd_ctl_bit_value(const char *name, union vmx_ctrl_msr msr, 3452 enum Encoding encoding, unsigned bit, 3453 unsigned val) 3454 { 3455 u32 mask = 1u << bit; 3456 bool expected; 3457 u32 controls; 3458 3459 if (msr.set & mask) 3460 TEST_ASSERT(msr.clr & mask); 3461 3462 /* 3463 * We can't arbitrarily turn on a control bit, because it may 3464 * introduce dependencies on other VMCS fields. So, we only 3465 * test turning on bits that have a required setting. 3466 */ 3467 if (val && (msr.clr & mask) && !(msr.set & mask)) 3468 return; 3469 3470 report_prefix_pushf("%s %s bit %d", 3471 val ? "Set" : "Clear", name, bit); 3472 3473 controls = vmcs_read(encoding); 3474 if (val) { 3475 vmcs_write(encoding, msr.set | mask); 3476 expected = (msr.clr & mask); 3477 } else { 3478 vmcs_write(encoding, msr.set & ~mask); 3479 expected = !(msr.set & mask); 3480 } 3481 if (expected) 3482 test_vmx_valid_controls(); 3483 else 3484 test_vmx_invalid_controls(); 3485 vmcs_write(encoding, controls); 3486 report_prefix_pop(); 3487 } 3488 3489 /* 3490 * Test reserved values of a VM-execution control bit, based on the 3491 * allowed bit settings from the corresponding VMX capability MSR. 3492 */ 3493 static void test_rsvd_ctl_bit(const char *name, union vmx_ctrl_msr msr, 3494 enum Encoding encoding, unsigned bit) 3495 { 3496 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 0); 3497 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 1); 3498 } 3499 3500 /* 3501 * Reserved bits in the pin-based VM-execution controls must be set 3502 * properly. Software may consult the VMX capability MSRs to determine 3503 * the proper settings. 3504 * [Intel SDM] 3505 */ 3506 static void test_pin_based_ctls(void) 3507 { 3508 unsigned bit; 3509 3510 printf("%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PIN" : 3511 "MSR_IA32_VMX_PINBASED_CTLS", ctrl_pin_rev.val); 3512 for (bit = 0; bit < 32; bit++) 3513 test_rsvd_ctl_bit("pin-based controls", 3514 ctrl_pin_rev, PIN_CONTROLS, bit); 3515 } 3516 3517 /* 3518 * Reserved bits in the primary processor-based VM-execution controls 3519 * must be set properly. Software may consult the VMX capability MSRs 3520 * to determine the proper settings. 3521 * [Intel SDM] 3522 */ 3523 static void test_primary_processor_based_ctls(void) 3524 { 3525 unsigned bit; 3526 3527 printf("\n%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PROC" : 3528 "MSR_IA32_VMX_PROCBASED_CTLS", ctrl_cpu_rev[0].val); 3529 for (bit = 0; bit < 32; bit++) 3530 test_rsvd_ctl_bit("primary processor-based controls", 3531 ctrl_cpu_rev[0], CPU_EXEC_CTRL0, bit); 3532 } 3533 3534 /* 3535 * If the "activate secondary controls" primary processor-based 3536 * VM-execution control is 1, reserved bits in the secondary 3537 * processor-based VM-execution controls must be cleared. Software may 3538 * consult the VMX capability MSRs to determine which bits are 3539 * reserved. 3540 * If the "activate secondary controls" primary processor-based 3541 * VM-execution control is 0 (or if the processor does not support the 3542 * 1-setting of that control), no checks are performed on the 3543 * secondary processor-based VM-execution controls. 3544 * [Intel SDM] 3545 */ 3546 static void test_secondary_processor_based_ctls(void) 3547 { 3548 u32 primary; 3549 u32 secondary; 3550 unsigned bit; 3551 3552 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) 3553 return; 3554 3555 primary = vmcs_read(CPU_EXEC_CTRL0); 3556 secondary = vmcs_read(CPU_EXEC_CTRL1); 3557 3558 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3559 printf("\nMSR_IA32_VMX_PROCBASED_CTLS2: %lx\n", ctrl_cpu_rev[1].val); 3560 for (bit = 0; bit < 32; bit++) 3561 test_rsvd_ctl_bit("secondary processor-based controls", 3562 ctrl_cpu_rev[1], CPU_EXEC_CTRL1, bit); 3563 3564 /* 3565 * When the "activate secondary controls" VM-execution control 3566 * is clear, there are no checks on the secondary controls. 3567 */ 3568 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3569 vmcs_write(CPU_EXEC_CTRL1, ~0); 3570 report(vmlaunch_succeeds(), 3571 "Secondary processor-based controls ignored"); 3572 vmcs_write(CPU_EXEC_CTRL1, secondary); 3573 vmcs_write(CPU_EXEC_CTRL0, primary); 3574 } 3575 3576 static void try_cr3_target_count(unsigned i, unsigned max) 3577 { 3578 report_prefix_pushf("CR3 target count 0x%x", i); 3579 vmcs_write(CR3_TARGET_COUNT, i); 3580 if (i <= max) 3581 test_vmx_valid_controls(); 3582 else 3583 test_vmx_invalid_controls(); 3584 report_prefix_pop(); 3585 } 3586 3587 /* 3588 * The CR3-target count must not be greater than 4. Future processors 3589 * may support a different number of CR3-target values. Software 3590 * should read the VMX capability MSR IA32_VMX_MISC to determine the 3591 * number of values supported. 3592 * [Intel SDM] 3593 */ 3594 static void test_cr3_targets(void) 3595 { 3596 unsigned supported_targets = (rdmsr(MSR_IA32_VMX_MISC) >> 16) & 0x1ff; 3597 u32 cr3_targets = vmcs_read(CR3_TARGET_COUNT); 3598 unsigned i; 3599 3600 printf("\nSupported CR3 targets: %d\n", supported_targets); 3601 TEST_ASSERT(supported_targets <= 256); 3602 3603 try_cr3_target_count(-1u, supported_targets); 3604 try_cr3_target_count(0x80000000, supported_targets); 3605 try_cr3_target_count(0x7fffffff, supported_targets); 3606 for (i = 0; i <= supported_targets + 1; i++) 3607 try_cr3_target_count(i, supported_targets); 3608 vmcs_write(CR3_TARGET_COUNT, cr3_targets); 3609 3610 /* VMWRITE to nonexistent target fields should fail. */ 3611 for (i = supported_targets; i < 256; i++) 3612 TEST_ASSERT(vmcs_write(CR3_TARGET_0 + i*2, 0)); 3613 } 3614 3615 /* 3616 * Test a particular address setting in the VMCS 3617 */ 3618 static void test_vmcs_addr(const char *name, 3619 enum Encoding encoding, 3620 u64 align, 3621 bool ignored, 3622 bool skip_beyond_mapped_ram, 3623 u64 addr) 3624 { 3625 report_prefix_pushf("%s = %lx", name, addr); 3626 vmcs_write(encoding, addr); 3627 if (skip_beyond_mapped_ram && 3628 addr > fwcfg_get_u64(FW_CFG_RAM_SIZE) - align && 3629 addr < (1ul << cpuid_maxphyaddr())) 3630 printf("Skipping physical address beyond mapped RAM\n"); 3631 else if (ignored || (IS_ALIGNED(addr, align) && 3632 addr < (1ul << cpuid_maxphyaddr()))) 3633 test_vmx_valid_controls(); 3634 else 3635 test_vmx_invalid_controls(); 3636 report_prefix_pop(); 3637 } 3638 3639 /* 3640 * Test interesting values for a VMCS address 3641 */ 3642 static void test_vmcs_addr_values(const char *name, 3643 enum Encoding encoding, 3644 u64 align, 3645 bool ignored, 3646 bool skip_beyond_mapped_ram, 3647 u32 bit_start, u32 bit_end) 3648 { 3649 unsigned i; 3650 u64 orig_val = vmcs_read(encoding); 3651 3652 for (i = bit_start; i <= bit_end; i++) 3653 test_vmcs_addr(name, encoding, align, ignored, 3654 skip_beyond_mapped_ram, 1ul << i); 3655 3656 test_vmcs_addr(name, encoding, align, ignored, 3657 skip_beyond_mapped_ram, PAGE_SIZE - 1); 3658 test_vmcs_addr(name, encoding, align, ignored, 3659 skip_beyond_mapped_ram, PAGE_SIZE); 3660 test_vmcs_addr(name, encoding, align, ignored, 3661 skip_beyond_mapped_ram, 3662 (1ul << cpuid_maxphyaddr()) - PAGE_SIZE); 3663 test_vmcs_addr(name, encoding, align, ignored, 3664 skip_beyond_mapped_ram, -1ul); 3665 3666 vmcs_write(encoding, orig_val); 3667 } 3668 3669 /* 3670 * Test a physical address reference in the VMCS, when the corresponding 3671 * feature is enabled and when the corresponding feature is disabled. 3672 */ 3673 static void test_vmcs_addr_reference(u32 control_bit, enum Encoding field, 3674 const char *field_name, 3675 const char *control_name, u64 align, 3676 bool skip_beyond_mapped_ram, 3677 bool control_primary) 3678 { 3679 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 3680 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 3681 u64 page_addr; 3682 3683 if (control_primary) { 3684 if (!(ctrl_cpu_rev[0].clr & control_bit)) 3685 return; 3686 } else { 3687 if (!(ctrl_cpu_rev[1].clr & control_bit)) 3688 return; 3689 } 3690 3691 page_addr = vmcs_read(field); 3692 3693 report_prefix_pushf("%s enabled", control_name); 3694 if (control_primary) { 3695 vmcs_write(CPU_EXEC_CTRL0, primary | control_bit); 3696 } else { 3697 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3698 vmcs_write(CPU_EXEC_CTRL1, secondary | control_bit); 3699 } 3700 3701 test_vmcs_addr_values(field_name, field, align, false, 3702 skip_beyond_mapped_ram, 0, 63); 3703 report_prefix_pop(); 3704 3705 report_prefix_pushf("%s disabled", control_name); 3706 if (control_primary) { 3707 vmcs_write(CPU_EXEC_CTRL0, primary & ~control_bit); 3708 } else { 3709 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3710 vmcs_write(CPU_EXEC_CTRL1, secondary & ~control_bit); 3711 } 3712 3713 test_vmcs_addr_values(field_name, field, align, true, false, 0, 63); 3714 report_prefix_pop(); 3715 3716 vmcs_write(field, page_addr); 3717 vmcs_write(CPU_EXEC_CTRL0, primary); 3718 vmcs_write(CPU_EXEC_CTRL1, secondary); 3719 } 3720 3721 /* 3722 * If the "use I/O bitmaps" VM-execution control is 1, bits 11:0 of 3723 * each I/O-bitmap address must be 0. Neither address should set any 3724 * bits beyond the processor's physical-address width. 3725 * [Intel SDM] 3726 */ 3727 static void test_io_bitmaps(void) 3728 { 3729 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_A, 3730 "I/O bitmap A", "Use I/O bitmaps", 3731 PAGE_SIZE, false, true); 3732 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_B, 3733 "I/O bitmap B", "Use I/O bitmaps", 3734 PAGE_SIZE, false, true); 3735 } 3736 3737 /* 3738 * If the "use MSR bitmaps" VM-execution control is 1, bits 11:0 of 3739 * the MSR-bitmap address must be 0. The address should not set any 3740 * bits beyond the processor's physical-address width. 3741 * [Intel SDM] 3742 */ 3743 static void test_msr_bitmap(void) 3744 { 3745 test_vmcs_addr_reference(CPU_MSR_BITMAP, MSR_BITMAP, 3746 "MSR bitmap", "Use MSR bitmaps", 3747 PAGE_SIZE, false, true); 3748 } 3749 3750 /* 3751 * If the "use TPR shadow" VM-execution control is 1, the virtual-APIC 3752 * address must satisfy the following checks: 3753 * - Bits 11:0 of the address must be 0. 3754 * - The address should not set any bits beyond the processor's 3755 * physical-address width. 3756 * [Intel SDM] 3757 */ 3758 static void test_apic_virt_addr(void) 3759 { 3760 /* 3761 * Ensure the processor will never use the virtual-APIC page, since 3762 * we will point it to invalid RAM. Otherwise KVM is puzzled about 3763 * what we're trying to achieve and fails vmentry. 3764 */ 3765 u32 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 3766 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0 | CPU_CR8_LOAD | CPU_CR8_STORE); 3767 test_vmcs_addr_reference(CPU_TPR_SHADOW, APIC_VIRT_ADDR, 3768 "virtual-APIC address", "Use TPR shadow", 3769 PAGE_SIZE, false, true); 3770 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 3771 } 3772 3773 /* 3774 * If the "virtualize APIC-accesses" VM-execution control is 1, the 3775 * APIC-access address must satisfy the following checks: 3776 * - Bits 11:0 of the address must be 0. 3777 * - The address should not set any bits beyond the processor's 3778 * physical-address width. 3779 * [Intel SDM] 3780 */ 3781 static void test_apic_access_addr(void) 3782 { 3783 void *apic_access_page = alloc_page(); 3784 3785 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_page)); 3786 3787 test_vmcs_addr_reference(CPU_VIRT_APIC_ACCESSES, APIC_ACCS_ADDR, 3788 "APIC-access address", 3789 "virtualize APIC-accesses", PAGE_SIZE, 3790 true, false); 3791 } 3792 3793 static bool set_bit_pattern(u8 mask, u32 *secondary) 3794 { 3795 u8 i; 3796 bool flag = false; 3797 u32 test_bits[3] = { 3798 CPU_VIRT_X2APIC, 3799 CPU_APIC_REG_VIRT, 3800 CPU_VINTD 3801 }; 3802 3803 for (i = 0; i < ARRAY_SIZE(test_bits); i++) { 3804 if ((mask & (1u << i)) && 3805 (ctrl_cpu_rev[1].clr & test_bits[i])) { 3806 *secondary |= test_bits[i]; 3807 flag = true; 3808 } 3809 } 3810 3811 return (flag); 3812 } 3813 3814 /* 3815 * If the "use TPR shadow" VM-execution control is 0, the following 3816 * VM-execution controls must also be 0: 3817 * - virtualize x2APIC mode 3818 * - APIC-register virtualization 3819 * - virtual-interrupt delivery 3820 * [Intel SDM] 3821 * 3822 * 2. If the "virtualize x2APIC mode" VM-execution control is 1, the 3823 * "virtualize APIC accesses" VM-execution control must be 0. 3824 * [Intel SDM] 3825 */ 3826 static void test_apic_virtual_ctls(void) 3827 { 3828 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3829 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3830 u32 primary = saved_primary; 3831 u32 secondary = saved_secondary; 3832 bool ctrl = false; 3833 char str[10] = "disabled"; 3834 u8 i = 0, j; 3835 3836 /* 3837 * First test 3838 */ 3839 if (!((ctrl_cpu_rev[0].clr & (CPU_SECONDARY | CPU_TPR_SHADOW)) == 3840 (CPU_SECONDARY | CPU_TPR_SHADOW))) 3841 return; 3842 3843 primary |= CPU_SECONDARY; 3844 primary &= ~CPU_TPR_SHADOW; 3845 vmcs_write(CPU_EXEC_CTRL0, primary); 3846 3847 while (1) { 3848 for (j = 1; j < 8; j++) { 3849 secondary &= ~(CPU_VIRT_X2APIC | CPU_APIC_REG_VIRT | CPU_VINTD); 3850 if (primary & CPU_TPR_SHADOW) { 3851 ctrl = true; 3852 } else { 3853 if (! set_bit_pattern(j, &secondary)) 3854 ctrl = true; 3855 else 3856 ctrl = false; 3857 } 3858 3859 vmcs_write(CPU_EXEC_CTRL1, secondary); 3860 report_prefix_pushf("Use TPR shadow %s, virtualize x2APIC mode %s, APIC-register virtualization %s, virtual-interrupt delivery %s", 3861 str, (secondary & CPU_VIRT_X2APIC) ? "enabled" : "disabled", (secondary & CPU_APIC_REG_VIRT) ? "enabled" : "disabled", (secondary & CPU_VINTD) ? "enabled" : "disabled"); 3862 if (ctrl) 3863 test_vmx_valid_controls(); 3864 else 3865 test_vmx_invalid_controls(); 3866 report_prefix_pop(); 3867 } 3868 3869 if (i == 1) 3870 break; 3871 i++; 3872 3873 primary |= CPU_TPR_SHADOW; 3874 vmcs_write(CPU_EXEC_CTRL0, primary); 3875 strcpy(str, "enabled"); 3876 } 3877 3878 /* 3879 * Second test 3880 */ 3881 u32 apic_virt_ctls = (CPU_VIRT_X2APIC | CPU_VIRT_APIC_ACCESSES); 3882 3883 primary = saved_primary; 3884 secondary = saved_secondary; 3885 if (!((ctrl_cpu_rev[1].clr & apic_virt_ctls) == apic_virt_ctls)) 3886 return; 3887 3888 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3889 secondary &= ~CPU_VIRT_APIC_ACCESSES; 3890 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_X2APIC); 3891 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access disabled"); 3892 test_vmx_valid_controls(); 3893 report_prefix_pop(); 3894 3895 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_APIC_ACCESSES); 3896 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access enabled"); 3897 test_vmx_valid_controls(); 3898 report_prefix_pop(); 3899 3900 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_X2APIC); 3901 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access enabled"); 3902 test_vmx_invalid_controls(); 3903 report_prefix_pop(); 3904 3905 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_APIC_ACCESSES); 3906 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access disabled"); 3907 test_vmx_valid_controls(); 3908 report_prefix_pop(); 3909 3910 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3911 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3912 } 3913 3914 /* 3915 * If the "virtual-interrupt delivery" VM-execution control is 1, the 3916 * "external-interrupt exiting" VM-execution control must be 1. 3917 * [Intel SDM] 3918 */ 3919 static void test_virtual_intr_ctls(void) 3920 { 3921 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3922 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3923 u32 saved_pin = vmcs_read(PIN_CONTROLS); 3924 u32 primary = saved_primary; 3925 u32 secondary = saved_secondary; 3926 u32 pin = saved_pin; 3927 3928 if (!((ctrl_cpu_rev[1].clr & CPU_VINTD) && 3929 (ctrl_pin_rev.clr & PIN_EXTINT))) 3930 return; 3931 3932 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 3933 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VINTD); 3934 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 3935 report_prefix_pushf("Virtualize interrupt-delivery disabled; external-interrupt exiting disabled"); 3936 test_vmx_valid_controls(); 3937 report_prefix_pop(); 3938 3939 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VINTD); 3940 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 3941 test_vmx_invalid_controls(); 3942 report_prefix_pop(); 3943 3944 vmcs_write(PIN_CONTROLS, pin | PIN_EXTINT); 3945 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting enabled"); 3946 test_vmx_valid_controls(); 3947 report_prefix_pop(); 3948 3949 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 3950 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 3951 test_vmx_invalid_controls(); 3952 report_prefix_pop(); 3953 3954 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3955 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3956 vmcs_write(PIN_CONTROLS, saved_pin); 3957 } 3958 3959 static void test_pi_desc_addr(u64 addr, bool ctrl) 3960 { 3961 vmcs_write(POSTED_INTR_DESC_ADDR, addr); 3962 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-descriptor-address 0x%lx", addr); 3963 if (ctrl) 3964 test_vmx_valid_controls(); 3965 else 3966 test_vmx_invalid_controls(); 3967 report_prefix_pop(); 3968 } 3969 3970 /* 3971 * If the "process posted interrupts" VM-execution control is 1, the 3972 * following must be true: 3973 * 3974 * - The "virtual-interrupt delivery" VM-execution control is 1. 3975 * - The "acknowledge interrupt on exit" VM-exit control is 1. 3976 * - The posted-interrupt notification vector has a value in the 3977 * - range 0 - 255 (bits 15:8 are all 0). 3978 * - Bits 5:0 of the posted-interrupt descriptor address are all 0. 3979 * - The posted-interrupt descriptor address does not set any bits 3980 * beyond the processor's physical-address width. 3981 * [Intel SDM] 3982 */ 3983 static void test_posted_intr(void) 3984 { 3985 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3986 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3987 u32 saved_pin = vmcs_read(PIN_CONTROLS); 3988 u32 exit_ctl_saved = vmcs_read(EXI_CONTROLS); 3989 u32 primary = saved_primary; 3990 u32 secondary = saved_secondary; 3991 u32 pin = saved_pin; 3992 u32 exit_ctl = exit_ctl_saved; 3993 u16 vec; 3994 int i; 3995 3996 if (!((ctrl_pin_rev.clr & PIN_POST_INTR) && 3997 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 3998 (ctrl_exit_rev.clr & EXI_INTA))) 3999 return; 4000 4001 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 4002 4003 /* 4004 * Test virtual-interrupt-delivery and acknowledge-interrupt-on-exit 4005 */ 4006 pin |= PIN_POST_INTR; 4007 vmcs_write(PIN_CONTROLS, pin); 4008 secondary &= ~CPU_VINTD; 4009 vmcs_write(CPU_EXEC_CTRL1, secondary); 4010 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled"); 4011 test_vmx_invalid_controls(); 4012 report_prefix_pop(); 4013 4014 secondary |= CPU_VINTD; 4015 vmcs_write(CPU_EXEC_CTRL1, secondary); 4016 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled"); 4017 test_vmx_invalid_controls(); 4018 report_prefix_pop(); 4019 4020 exit_ctl &= ~EXI_INTA; 4021 vmcs_write(EXI_CONTROLS, exit_ctl); 4022 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit disabled"); 4023 test_vmx_invalid_controls(); 4024 report_prefix_pop(); 4025 4026 exit_ctl |= EXI_INTA; 4027 vmcs_write(EXI_CONTROLS, exit_ctl); 4028 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 4029 test_vmx_valid_controls(); 4030 report_prefix_pop(); 4031 4032 secondary &= ~CPU_VINTD; 4033 vmcs_write(CPU_EXEC_CTRL1, secondary); 4034 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled; acknowledge-interrupt-on-exit enabled"); 4035 test_vmx_invalid_controls(); 4036 report_prefix_pop(); 4037 4038 secondary |= CPU_VINTD; 4039 vmcs_write(CPU_EXEC_CTRL1, secondary); 4040 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 4041 test_vmx_valid_controls(); 4042 report_prefix_pop(); 4043 4044 /* 4045 * Test posted-interrupt notification vector 4046 */ 4047 for (i = 0; i < 8; i++) { 4048 vec = (1ul << i); 4049 vmcs_write(PINV, vec); 4050 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 4051 test_vmx_valid_controls(); 4052 report_prefix_pop(); 4053 } 4054 for (i = 8; i < 16; i++) { 4055 vec = (1ul << i); 4056 vmcs_write(PINV, vec); 4057 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 4058 test_vmx_invalid_controls(); 4059 report_prefix_pop(); 4060 } 4061 4062 vec &= ~(0xff << 8); 4063 vmcs_write(PINV, vec); 4064 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 4065 test_vmx_valid_controls(); 4066 report_prefix_pop(); 4067 4068 /* 4069 * Test posted-interrupt descriptor addresss 4070 */ 4071 for (i = 0; i < 6; i++) { 4072 test_pi_desc_addr(1ul << i, false); 4073 } 4074 4075 test_pi_desc_addr(0xf0, false); 4076 test_pi_desc_addr(0xff, false); 4077 test_pi_desc_addr(0x0f, false); 4078 test_pi_desc_addr(0x8000, true); 4079 test_pi_desc_addr(0x00, true); 4080 test_pi_desc_addr(0xc000, true); 4081 4082 test_vmcs_addr_values("process-posted interrupts", 4083 POSTED_INTR_DESC_ADDR, 64, 4084 false, false, 0, 63); 4085 4086 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 4087 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 4088 vmcs_write(PIN_CONTROLS, saved_pin); 4089 } 4090 4091 static void test_apic_ctls(void) 4092 { 4093 test_apic_virt_addr(); 4094 test_apic_access_addr(); 4095 test_apic_virtual_ctls(); 4096 test_virtual_intr_ctls(); 4097 test_posted_intr(); 4098 } 4099 4100 /* 4101 * If the "enable VPID" VM-execution control is 1, the value of the 4102 * of the VPID VM-execution control field must not be 0000H. 4103 * [Intel SDM] 4104 */ 4105 static void test_vpid(void) 4106 { 4107 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 4108 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 4109 u16 vpid = 0x0000; 4110 int i; 4111 4112 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4113 (ctrl_cpu_rev[1].clr & CPU_VPID))) { 4114 printf("Secondary controls and/or VPID not supported\n"); 4115 return; 4116 } 4117 4118 vmcs_write(CPU_EXEC_CTRL0, saved_primary | CPU_SECONDARY); 4119 vmcs_write(CPU_EXEC_CTRL1, saved_secondary & ~CPU_VPID); 4120 vmcs_write(VPID, vpid); 4121 report_prefix_pushf("VPID disabled; VPID value %x", vpid); 4122 test_vmx_valid_controls(); 4123 report_prefix_pop(); 4124 4125 vmcs_write(CPU_EXEC_CTRL1, saved_secondary | CPU_VPID); 4126 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 4127 test_vmx_invalid_controls(); 4128 report_prefix_pop(); 4129 4130 for (i = 0; i < 16; i++) { 4131 vpid = (short)1 << i;; 4132 vmcs_write(VPID, vpid); 4133 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 4134 test_vmx_valid_controls(); 4135 report_prefix_pop(); 4136 } 4137 4138 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 4139 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 4140 } 4141 4142 static void set_vtpr(unsigned vtpr) 4143 { 4144 *(u32 *)phys_to_virt(vmcs_read(APIC_VIRT_ADDR) + APIC_TASKPRI) = vtpr; 4145 } 4146 4147 static void try_tpr_threshold_and_vtpr(unsigned threshold, unsigned vtpr) 4148 { 4149 bool valid = true; 4150 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4151 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4152 4153 if ((primary & CPU_TPR_SHADOW) && 4154 (!(primary & CPU_SECONDARY) || 4155 !(secondary & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 4156 valid = (threshold & 0xf) <= ((vtpr >> 4) & 0xf); 4157 4158 set_vtpr(vtpr); 4159 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0x%x", 4160 threshold, (vtpr >> 4) & 0xf); 4161 if (valid) 4162 test_vmx_valid_controls(); 4163 else 4164 test_vmx_invalid_controls(); 4165 report_prefix_pop(); 4166 } 4167 4168 static void test_invalid_event_injection(void) 4169 { 4170 u32 ent_intr_info_save = vmcs_read(ENT_INTR_INFO); 4171 u32 ent_intr_error_save = vmcs_read(ENT_INTR_ERROR); 4172 u32 ent_inst_len_save = vmcs_read(ENT_INST_LEN); 4173 u32 primary_save = vmcs_read(CPU_EXEC_CTRL0); 4174 u32 secondary_save = vmcs_read(CPU_EXEC_CTRL1); 4175 u64 guest_cr0_save = vmcs_read(GUEST_CR0); 4176 u32 ent_intr_info_base = INTR_INFO_VALID_MASK; 4177 u32 ent_intr_info, ent_intr_err, ent_intr_len; 4178 u32 cnt; 4179 4180 /* Setup */ 4181 report_prefix_push("invalid event injection"); 4182 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4183 vmcs_write(ENT_INST_LEN, 0x00000001); 4184 4185 /* The field's interruption type is not set to a reserved value. */ 4186 ent_intr_info = ent_intr_info_base | INTR_TYPE_RESERVED | DE_VECTOR; 4187 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4188 "RESERVED interruption type invalid [-]", 4189 ent_intr_info); 4190 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4191 test_vmx_invalid_controls(); 4192 report_prefix_pop(); 4193 4194 ent_intr_info = ent_intr_info_base | INTR_TYPE_EXT_INTR | 4195 DE_VECTOR; 4196 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4197 "RESERVED interruption type invalid [+]", 4198 ent_intr_info); 4199 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4200 test_vmx_valid_controls(); 4201 report_prefix_pop(); 4202 4203 /* If the interruption type is other event, the vector is 0. */ 4204 ent_intr_info = ent_intr_info_base | INTR_TYPE_OTHER_EVENT | DB_VECTOR; 4205 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4206 "(OTHER EVENT && vector != 0) invalid [-]", 4207 ent_intr_info); 4208 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4209 test_vmx_invalid_controls(); 4210 report_prefix_pop(); 4211 4212 /* If the interruption type is NMI, the vector is 2 (negative case). */ 4213 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | DE_VECTOR; 4214 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4215 "(NMI && vector != 2) invalid [-]", ent_intr_info); 4216 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4217 test_vmx_invalid_controls(); 4218 report_prefix_pop(); 4219 4220 /* If the interruption type is NMI, the vector is 2 (positive case). */ 4221 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | NMI_VECTOR; 4222 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4223 "(NMI && vector == 2) valid [+]", ent_intr_info); 4224 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4225 test_vmx_valid_controls(); 4226 report_prefix_pop(); 4227 4228 /* 4229 * If the interruption type 4230 * is HW exception, the vector is at most 31. 4231 */ 4232 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 0x20; 4233 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4234 "(HW exception && vector > 31) invalid [-]", 4235 ent_intr_info); 4236 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4237 test_vmx_invalid_controls(); 4238 report_prefix_pop(); 4239 4240 /* 4241 * deliver-error-code is 1 iff either 4242 * (a) the "unrestricted guest" VM-execution control is 0 4243 * (b) CR0.PE is set. 4244 */ 4245 4246 /* Assert that unrestricted guest is disabled or unsupported */ 4247 assert(!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 4248 !(secondary_save & CPU_URG)); 4249 4250 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4251 GP_VECTOR; 4252 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4253 "error code <-> (!URG || prot_mode) [-]", 4254 ent_intr_info); 4255 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4256 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4257 test_vmx_invalid_controls(); 4258 report_prefix_pop(); 4259 4260 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4261 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4262 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4263 "error code <-> (!URG || prot_mode) [+]", 4264 ent_intr_info); 4265 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4266 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4267 test_vmx_valid_controls(); 4268 report_prefix_pop(); 4269 4270 if (enable_unrestricted_guest(false)) 4271 goto skip_unrestricted_guest; 4272 4273 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4274 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4275 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4276 "error code <-> (!URG || prot_mode) [-]", 4277 ent_intr_info); 4278 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4279 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4280 test_vmx_invalid_controls(); 4281 report_prefix_pop(); 4282 4283 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4284 GP_VECTOR; 4285 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4286 "error code <-> (!URG || prot_mode) [-]", 4287 ent_intr_info); 4288 vmcs_write(GUEST_CR0, guest_cr0_save | X86_CR0_PE); 4289 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4290 test_vmx_invalid_controls(); 4291 report_prefix_pop(); 4292 4293 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4294 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4295 4296 skip_unrestricted_guest: 4297 vmcs_write(GUEST_CR0, guest_cr0_save); 4298 4299 /* deliver-error-code is 1 iff the interruption type is HW exception */ 4300 report_prefix_push("error code <-> HW exception"); 4301 for (cnt = 0; cnt < 8; cnt++) { 4302 u32 exception_type_mask = cnt << 8; 4303 u32 deliver_error_code_mask = 4304 exception_type_mask != INTR_TYPE_HARD_EXCEPTION ? 4305 INTR_INFO_DELIVER_CODE_MASK : 0; 4306 4307 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4308 exception_type_mask | GP_VECTOR; 4309 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4310 ent_intr_info); 4311 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4312 test_vmx_invalid_controls(); 4313 report_prefix_pop(); 4314 } 4315 report_prefix_pop(); 4316 4317 /* 4318 * deliver-error-code is 1 iff the the vector 4319 * indicates an exception that would normally deliver an error code 4320 */ 4321 report_prefix_push("error code <-> vector delivers error code"); 4322 for (cnt = 0; cnt < 32; cnt++) { 4323 bool has_error_code = false; 4324 u32 deliver_error_code_mask; 4325 4326 switch (cnt) { 4327 case DF_VECTOR: 4328 case TS_VECTOR: 4329 case NP_VECTOR: 4330 case SS_VECTOR: 4331 case GP_VECTOR: 4332 case PF_VECTOR: 4333 case AC_VECTOR: 4334 has_error_code = true; 4335 case CP_VECTOR: 4336 /* Some CPUs have error code and some do not, skip */ 4337 continue; 4338 } 4339 4340 /* Negative case */ 4341 deliver_error_code_mask = has_error_code ? 4342 0 : 4343 INTR_INFO_DELIVER_CODE_MASK; 4344 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4345 INTR_TYPE_HARD_EXCEPTION | cnt; 4346 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4347 ent_intr_info); 4348 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4349 test_vmx_invalid_controls(); 4350 report_prefix_pop(); 4351 4352 /* Positive case */ 4353 deliver_error_code_mask = has_error_code ? 4354 INTR_INFO_DELIVER_CODE_MASK : 4355 0; 4356 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4357 INTR_TYPE_HARD_EXCEPTION | cnt; 4358 report_prefix_pushf("VM-entry intr info=0x%x [+]", 4359 ent_intr_info); 4360 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4361 test_vmx_valid_controls(); 4362 report_prefix_pop(); 4363 } 4364 report_prefix_pop(); 4365 4366 /* Reserved bits in the field (30:12) are 0. */ 4367 report_prefix_push("reserved bits clear"); 4368 for (cnt = 12; cnt <= 30; cnt++) { 4369 ent_intr_info = ent_intr_info_base | 4370 INTR_INFO_DELIVER_CODE_MASK | 4371 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR | 4372 (1U << cnt); 4373 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4374 ent_intr_info); 4375 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4376 test_vmx_invalid_controls(); 4377 report_prefix_pop(); 4378 } 4379 report_prefix_pop(); 4380 4381 /* 4382 * If deliver-error-code is 1 4383 * bits 31:16 of the VM-entry exception error-code field are 0. 4384 */ 4385 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4386 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4387 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4388 "VM-entry exception error code[31:16] clear", 4389 ent_intr_info); 4390 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4391 for (cnt = 16; cnt <= 31; cnt++) { 4392 ent_intr_err = 1U << cnt; 4393 report_prefix_pushf("VM-entry intr error=0x%x [-]", 4394 ent_intr_err); 4395 vmcs_write(ENT_INTR_ERROR, ent_intr_err); 4396 test_vmx_invalid_controls(); 4397 report_prefix_pop(); 4398 } 4399 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4400 report_prefix_pop(); 4401 4402 /* 4403 * If the interruption type is software interrupt, software exception, 4404 * or privileged software exception, the VM-entry instruction-length 4405 * field is in the range 0 - 15. 4406 */ 4407 4408 for (cnt = 0; cnt < 3; cnt++) { 4409 switch (cnt) { 4410 case 0: 4411 ent_intr_info = ent_intr_info_base | 4412 INTR_TYPE_SOFT_INTR; 4413 break; 4414 case 1: 4415 ent_intr_info = ent_intr_info_base | 4416 INTR_TYPE_SOFT_EXCEPTION; 4417 break; 4418 case 2: 4419 ent_intr_info = ent_intr_info_base | 4420 INTR_TYPE_PRIV_SW_EXCEPTION; 4421 break; 4422 } 4423 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4424 "VM-entry instruction-length check", 4425 ent_intr_info); 4426 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4427 4428 /* Instruction length set to -1 (0xFFFFFFFF) should fail */ 4429 ent_intr_len = -1; 4430 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4431 ent_intr_len); 4432 vmcs_write(ENT_INST_LEN, ent_intr_len); 4433 test_vmx_invalid_controls(); 4434 report_prefix_pop(); 4435 4436 /* Instruction length set to 16 should fail */ 4437 ent_intr_len = 0x00000010; 4438 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4439 ent_intr_len); 4440 vmcs_write(ENT_INST_LEN, 0x00000010); 4441 test_vmx_invalid_controls(); 4442 report_prefix_pop(); 4443 4444 report_prefix_pop(); 4445 } 4446 4447 /* Cleanup */ 4448 vmcs_write(ENT_INTR_INFO, ent_intr_info_save); 4449 vmcs_write(ENT_INTR_ERROR, ent_intr_error_save); 4450 vmcs_write(ENT_INST_LEN, ent_inst_len_save); 4451 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4452 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4453 vmcs_write(GUEST_CR0, guest_cr0_save); 4454 report_prefix_pop(); 4455 } 4456 4457 /* 4458 * Test interesting vTPR values for a given TPR threshold. 4459 */ 4460 static void test_vtpr_values(unsigned threshold) 4461 { 4462 try_tpr_threshold_and_vtpr(threshold, (threshold - 1) << 4); 4463 try_tpr_threshold_and_vtpr(threshold, threshold << 4); 4464 try_tpr_threshold_and_vtpr(threshold, (threshold + 1) << 4); 4465 } 4466 4467 static void try_tpr_threshold(unsigned threshold) 4468 { 4469 bool valid = true; 4470 4471 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4472 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4473 4474 if ((primary & CPU_TPR_SHADOW) && !((primary & CPU_SECONDARY) && 4475 (secondary & CPU_VINTD))) 4476 valid = !(threshold >> 4); 4477 4478 set_vtpr(-1); 4479 vmcs_write(TPR_THRESHOLD, threshold); 4480 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0xf", threshold); 4481 if (valid) 4482 test_vmx_valid_controls(); 4483 else 4484 test_vmx_invalid_controls(); 4485 report_prefix_pop(); 4486 4487 if (valid) 4488 test_vtpr_values(threshold); 4489 } 4490 4491 /* 4492 * Test interesting TPR threshold values. 4493 */ 4494 static void test_tpr_threshold_values(void) 4495 { 4496 unsigned i; 4497 4498 for (i = 0; i < 0x10; i++) 4499 try_tpr_threshold(i); 4500 for (i = 4; i < 32; i++) 4501 try_tpr_threshold(1u << i); 4502 try_tpr_threshold(-1u); 4503 try_tpr_threshold(0x7fffffff); 4504 } 4505 4506 /* 4507 * This test covers the following two VM entry checks: 4508 * 4509 * i) If the "use TPR shadow" VM-execution control is 1 and the 4510 * "virtual-interrupt delivery" VM-execution control is 0, bits 4511 * 31:4 of the TPR threshold VM-execution control field must 4512 be 0. 4513 * [Intel SDM] 4514 * 4515 * ii) If the "use TPR shadow" VM-execution control is 1, the 4516 * "virtual-interrupt delivery" VM-execution control is 0 4517 * and the "virtualize APIC accesses" VM-execution control 4518 * is 0, the value of bits 3:0 of the TPR threshold VM-execution 4519 * control field must not be greater than the value of bits 4520 * 7:4 of VTPR. 4521 * [Intel SDM] 4522 */ 4523 static void test_tpr_threshold(void) 4524 { 4525 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4526 u64 apic_virt_addr = vmcs_read(APIC_VIRT_ADDR); 4527 u64 threshold = vmcs_read(TPR_THRESHOLD); 4528 void *virtual_apic_page; 4529 4530 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) 4531 return; 4532 4533 virtual_apic_page = alloc_page(); 4534 memset(virtual_apic_page, 0xff, PAGE_SIZE); 4535 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 4536 4537 vmcs_write(CPU_EXEC_CTRL0, primary & ~(CPU_TPR_SHADOW | CPU_SECONDARY)); 4538 report_prefix_pushf("Use TPR shadow disabled, secondary controls disabled"); 4539 test_tpr_threshold_values(); 4540 report_prefix_pop(); 4541 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_TPR_SHADOW); 4542 report_prefix_pushf("Use TPR shadow enabled, secondary controls disabled"); 4543 test_tpr_threshold_values(); 4544 report_prefix_pop(); 4545 4546 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4547 (ctrl_cpu_rev[1].clr & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 4548 goto out; 4549 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4550 4551 if (ctrl_cpu_rev[1].clr & CPU_VINTD) { 4552 vmcs_write(CPU_EXEC_CTRL1, CPU_VINTD); 4553 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4554 test_tpr_threshold_values(); 4555 report_prefix_pop(); 4556 4557 vmcs_write(CPU_EXEC_CTRL0, 4558 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4559 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4560 test_tpr_threshold_values(); 4561 report_prefix_pop(); 4562 } 4563 4564 if (ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES) { 4565 vmcs_write(CPU_EXEC_CTRL0, 4566 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4567 vmcs_write(CPU_EXEC_CTRL1, CPU_VIRT_APIC_ACCESSES); 4568 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4569 test_tpr_threshold_values(); 4570 report_prefix_pop(); 4571 4572 vmcs_write(CPU_EXEC_CTRL0, 4573 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4574 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4575 test_tpr_threshold_values(); 4576 report_prefix_pop(); 4577 } 4578 4579 if ((ctrl_cpu_rev[1].clr & 4580 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) == 4581 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) { 4582 vmcs_write(CPU_EXEC_CTRL0, 4583 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4584 vmcs_write(CPU_EXEC_CTRL1, 4585 CPU_VINTD | CPU_VIRT_APIC_ACCESSES); 4586 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4587 test_tpr_threshold_values(); 4588 report_prefix_pop(); 4589 4590 vmcs_write(CPU_EXEC_CTRL0, 4591 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4592 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4593 test_tpr_threshold_values(); 4594 report_prefix_pop(); 4595 } 4596 4597 vmcs_write(CPU_EXEC_CTRL1, secondary); 4598 out: 4599 vmcs_write(TPR_THRESHOLD, threshold); 4600 vmcs_write(APIC_VIRT_ADDR, apic_virt_addr); 4601 vmcs_write(CPU_EXEC_CTRL0, primary); 4602 } 4603 4604 /* 4605 * This test verifies the following two vmentry checks: 4606 * 4607 * If the "NMI exiting" VM-execution control is 0, "Virtual NMIs" 4608 * VM-execution control must be 0. 4609 * [Intel SDM] 4610 * 4611 * If the "virtual NMIs" VM-execution control is 0, the "NMI-window 4612 * exiting" VM-execution control must be 0. 4613 * [Intel SDM] 4614 */ 4615 static void test_nmi_ctrls(void) 4616 { 4617 u32 pin_ctrls, cpu_ctrls0, test_pin_ctrls, test_cpu_ctrls0; 4618 4619 if ((ctrl_pin_rev.clr & (PIN_NMI | PIN_VIRT_NMI)) != 4620 (PIN_NMI | PIN_VIRT_NMI)) { 4621 printf("NMI exiting and Virtual NMIs are not supported !\n"); 4622 return; 4623 } 4624 4625 /* Save the controls so that we can restore them after our tests */ 4626 pin_ctrls = vmcs_read(PIN_CONTROLS); 4627 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 4628 4629 test_pin_ctrls = pin_ctrls & ~(PIN_NMI | PIN_VIRT_NMI); 4630 test_cpu_ctrls0 = cpu_ctrls0 & ~CPU_NMI_WINDOW; 4631 4632 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4633 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs disabled"); 4634 test_vmx_valid_controls(); 4635 report_prefix_pop(); 4636 4637 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_VIRT_NMI); 4638 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs enabled"); 4639 test_vmx_invalid_controls(); 4640 report_prefix_pop(); 4641 4642 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4643 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs enabled"); 4644 test_vmx_valid_controls(); 4645 report_prefix_pop(); 4646 4647 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_NMI); 4648 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs disabled"); 4649 test_vmx_valid_controls(); 4650 report_prefix_pop(); 4651 4652 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 4653 report_info("NMI-window exiting is not supported, skipping..."); 4654 goto done; 4655 } 4656 4657 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4658 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4659 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting enabled"); 4660 test_vmx_invalid_controls(); 4661 report_prefix_pop(); 4662 4663 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4664 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4665 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting disabled"); 4666 test_vmx_valid_controls(); 4667 report_prefix_pop(); 4668 4669 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4670 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4671 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting enabled"); 4672 test_vmx_valid_controls(); 4673 report_prefix_pop(); 4674 4675 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4676 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4677 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting disabled"); 4678 test_vmx_valid_controls(); 4679 report_prefix_pop(); 4680 4681 /* Restore the controls to their original values */ 4682 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 4683 done: 4684 vmcs_write(PIN_CONTROLS, pin_ctrls); 4685 } 4686 4687 static void test_eptp_ad_bit(u64 eptp, bool ctrl) 4688 { 4689 vmcs_write(EPTP, eptp); 4690 report_prefix_pushf("Enable-EPT enabled; EPT accessed and dirty flag %s", 4691 (eptp & EPTP_AD_FLAG) ? "1": "0"); 4692 if (ctrl) 4693 test_vmx_valid_controls(); 4694 else 4695 test_vmx_invalid_controls(); 4696 report_prefix_pop(); 4697 4698 } 4699 4700 /* 4701 * 1. If the "enable EPT" VM-execution control is 1, the "EPTP VM-execution" 4702 * control field must satisfy the following checks: 4703 * 4704 * - The EPT memory type (bits 2:0) must be a value supported by the 4705 * processor as indicated in the IA32_VMX_EPT_VPID_CAP MSR. 4706 * - Bits 5:3 (1 less than the EPT page-walk length) must indicate a 4707 * supported EPT page-walk length. 4708 * - Bit 6 (enable bit for accessed and dirty flags for EPT) must be 4709 * 0 if bit 21 of the IA32_VMX_EPT_VPID_CAP MSR is read as 0, 4710 * indicating that the processor does not support accessed and dirty 4711 * dirty flags for EPT. 4712 * - Reserved bits 11:7 and 63:N (where N is the processor's 4713 * physical-address width) must all be 0. 4714 * 4715 * 2. If the "unrestricted guest" VM-execution control is 1, the 4716 * "enable EPT" VM-execution control must also be 1. 4717 */ 4718 static void test_ept_eptp(void) 4719 { 4720 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4721 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4722 u64 eptp_saved = vmcs_read(EPTP); 4723 u32 primary = primary_saved; 4724 u32 secondary = secondary_saved; 4725 u64 msr, eptp = eptp_saved; 4726 bool un_cache = false; 4727 bool wr_bk = false; 4728 bool ctrl; 4729 u32 i, maxphysaddr; 4730 u64 j, resv_bits_mask = 0; 4731 4732 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4733 (ctrl_cpu_rev[1].clr & CPU_EPT))) { 4734 printf("\"CPU secondary\" and/or \"enable EPT\" execution controls are not supported !\n"); 4735 return; 4736 } 4737 4738 /* 4739 * Memory type (bits 2:0) 4740 */ 4741 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 4742 if (msr & EPT_CAP_UC) 4743 un_cache = true; 4744 if (msr & EPT_CAP_WB) 4745 wr_bk = true; 4746 4747 /* Support for 4-level EPT is mandatory. */ 4748 report(msr & EPT_CAP_PWL4, "4-level EPT support check"); 4749 4750 primary |= CPU_SECONDARY; 4751 vmcs_write(CPU_EXEC_CTRL0, primary); 4752 secondary |= CPU_EPT; 4753 vmcs_write(CPU_EXEC_CTRL1, secondary); 4754 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4755 (3ul << EPTP_PG_WALK_LEN_SHIFT); 4756 vmcs_write(EPTP, eptp); 4757 4758 for (i = 0; i < 8; i++) { 4759 if (i == 0) { 4760 if (un_cache) { 4761 report_info("EPT paging structure memory-type is Un-cacheable\n"); 4762 ctrl = true; 4763 } else { 4764 ctrl = false; 4765 } 4766 } else if (i == 6) { 4767 if (wr_bk) { 4768 report_info("EPT paging structure memory-type is Write-back\n"); 4769 ctrl = true; 4770 } else { 4771 ctrl = false; 4772 } 4773 } else { 4774 ctrl = false; 4775 } 4776 4777 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | i; 4778 vmcs_write(EPTP, eptp); 4779 report_prefix_pushf("Enable-EPT enabled; EPT memory type %lu", 4780 eptp & EPT_MEM_TYPE_MASK); 4781 if (ctrl) 4782 test_vmx_valid_controls(); 4783 else 4784 test_vmx_invalid_controls(); 4785 report_prefix_pop(); 4786 } 4787 4788 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | 6ul; 4789 4790 /* 4791 * Page walk length (bits 5:3). Note, the value in VMCS.EPTP "is 1 4792 * less than the EPT page-walk length". 4793 */ 4794 for (i = 0; i < 8; i++) { 4795 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4796 (i << EPTP_PG_WALK_LEN_SHIFT); 4797 if (i == 3 || (i == 4 && (msr & EPT_CAP_PWL5))) 4798 ctrl = true; 4799 else 4800 ctrl = false; 4801 4802 vmcs_write(EPTP, eptp); 4803 report_prefix_pushf("Enable-EPT enabled; EPT page walk length %lu", 4804 eptp & EPTP_PG_WALK_LEN_MASK); 4805 if (ctrl) 4806 test_vmx_valid_controls(); 4807 else 4808 test_vmx_invalid_controls(); 4809 report_prefix_pop(); 4810 } 4811 4812 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4813 3ul << EPTP_PG_WALK_LEN_SHIFT; 4814 4815 /* 4816 * Accessed and dirty flag (bit 6) 4817 */ 4818 if (msr & EPT_CAP_AD_FLAG) { 4819 report_info("Processor supports accessed and dirty flag"); 4820 eptp &= ~EPTP_AD_FLAG; 4821 test_eptp_ad_bit(eptp, true); 4822 4823 eptp |= EPTP_AD_FLAG; 4824 test_eptp_ad_bit(eptp, true); 4825 } else { 4826 report_info("Processor does not supports accessed and dirty flag"); 4827 eptp &= ~EPTP_AD_FLAG; 4828 test_eptp_ad_bit(eptp, true); 4829 4830 eptp |= EPTP_AD_FLAG; 4831 test_eptp_ad_bit(eptp, false); 4832 } 4833 4834 /* 4835 * Reserved bits [11:7] and [63:N] 4836 */ 4837 for (i = 0; i < 32; i++) { 4838 eptp = (eptp & 4839 ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)) | 4840 (i << EPTP_RESERV_BITS_SHIFT); 4841 vmcs_write(EPTP, eptp); 4842 report_prefix_pushf("Enable-EPT enabled; reserved bits [11:7] %lu", 4843 (eptp >> EPTP_RESERV_BITS_SHIFT) & 4844 EPTP_RESERV_BITS_MASK); 4845 if (i == 0) 4846 test_vmx_valid_controls(); 4847 else 4848 test_vmx_invalid_controls(); 4849 report_prefix_pop(); 4850 } 4851 4852 eptp = (eptp & ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)); 4853 4854 maxphysaddr = cpuid_maxphyaddr(); 4855 for (i = 0; i < (63 - maxphysaddr + 1); i++) { 4856 resv_bits_mask |= 1ul << i; 4857 } 4858 4859 for (j = maxphysaddr - 1; j <= 63; j++) { 4860 eptp = (eptp & ~(resv_bits_mask << maxphysaddr)) | 4861 (j < maxphysaddr ? 0 : 1ul << j); 4862 vmcs_write(EPTP, eptp); 4863 report_prefix_pushf("Enable-EPT enabled; reserved bits [63:N] %lu", 4864 (eptp >> maxphysaddr) & resv_bits_mask); 4865 if (j < maxphysaddr) 4866 test_vmx_valid_controls(); 4867 else 4868 test_vmx_invalid_controls(); 4869 report_prefix_pop(); 4870 } 4871 4872 secondary &= ~(CPU_EPT | CPU_URG); 4873 vmcs_write(CPU_EXEC_CTRL1, secondary); 4874 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest disabled"); 4875 test_vmx_valid_controls(); 4876 report_prefix_pop(); 4877 4878 if (!(ctrl_cpu_rev[1].clr & CPU_URG)) 4879 goto skip_unrestricted_guest; 4880 4881 secondary |= CPU_URG; 4882 vmcs_write(CPU_EXEC_CTRL1, secondary); 4883 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest enabled"); 4884 test_vmx_invalid_controls(); 4885 report_prefix_pop(); 4886 4887 secondary |= CPU_EPT; 4888 setup_dummy_ept(); 4889 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest enabled"); 4890 test_vmx_valid_controls(); 4891 report_prefix_pop(); 4892 4893 skip_unrestricted_guest: 4894 secondary &= ~CPU_URG; 4895 vmcs_write(CPU_EXEC_CTRL1, secondary); 4896 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest disabled"); 4897 test_vmx_valid_controls(); 4898 report_prefix_pop(); 4899 4900 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4901 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4902 vmcs_write(EPTP, eptp_saved); 4903 } 4904 4905 /* 4906 * If the 'enable PML' VM-execution control is 1, the 'enable EPT' 4907 * VM-execution control must also be 1. In addition, the PML address 4908 * must satisfy the following checks: 4909 * 4910 * * Bits 11:0 of the address must be 0. 4911 * * The address should not set any bits beyond the processor's 4912 * physical-address width. 4913 * 4914 * [Intel SDM] 4915 */ 4916 static void test_pml(void) 4917 { 4918 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4919 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4920 u32 primary = primary_saved; 4921 u32 secondary = secondary_saved; 4922 4923 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4924 (ctrl_cpu_rev[1].clr & CPU_EPT) && (ctrl_cpu_rev[1].clr & CPU_PML))) { 4925 printf("\"Secondary execution\" control or \"enable EPT\" control or \"enable PML\" control is not supported !\n"); 4926 return; 4927 } 4928 4929 primary |= CPU_SECONDARY; 4930 vmcs_write(CPU_EXEC_CTRL0, primary); 4931 secondary &= ~(CPU_PML | CPU_EPT); 4932 vmcs_write(CPU_EXEC_CTRL1, secondary); 4933 report_prefix_pushf("enable-PML disabled, enable-EPT disabled"); 4934 test_vmx_valid_controls(); 4935 report_prefix_pop(); 4936 4937 secondary |= CPU_PML; 4938 vmcs_write(CPU_EXEC_CTRL1, secondary); 4939 report_prefix_pushf("enable-PML enabled, enable-EPT disabled"); 4940 test_vmx_invalid_controls(); 4941 report_prefix_pop(); 4942 4943 secondary |= CPU_EPT; 4944 setup_dummy_ept(); 4945 report_prefix_pushf("enable-PML enabled, enable-EPT enabled"); 4946 test_vmx_valid_controls(); 4947 report_prefix_pop(); 4948 4949 secondary &= ~CPU_PML; 4950 vmcs_write(CPU_EXEC_CTRL1, secondary); 4951 report_prefix_pushf("enable-PML disabled, enable EPT enabled"); 4952 test_vmx_valid_controls(); 4953 report_prefix_pop(); 4954 4955 test_vmcs_addr_reference(CPU_PML, PMLADDR, "PML address", "PML", 4956 PAGE_SIZE, false, false); 4957 4958 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4959 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4960 } 4961 4962 /* 4963 * If the "activate VMX-preemption timer" VM-execution control is 0, the 4964 * the "save VMX-preemption timer value" VM-exit control must also be 0. 4965 * 4966 * [Intel SDM] 4967 */ 4968 static void test_vmx_preemption_timer(void) 4969 { 4970 u32 saved_pin = vmcs_read(PIN_CONTROLS); 4971 u32 saved_exit = vmcs_read(EXI_CONTROLS); 4972 u32 pin = saved_pin; 4973 u32 exit = saved_exit; 4974 4975 if (!((ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) || 4976 (ctrl_pin_rev.clr & PIN_PREEMPT))) { 4977 printf("\"Save-VMX-preemption-timer\" control and/or \"Enable-VMX-preemption-timer\" control is not supported\n"); 4978 return; 4979 } 4980 4981 pin |= PIN_PREEMPT; 4982 vmcs_write(PIN_CONTROLS, pin); 4983 exit &= ~EXI_SAVE_PREEMPT; 4984 vmcs_write(EXI_CONTROLS, exit); 4985 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer disabled"); 4986 test_vmx_valid_controls(); 4987 report_prefix_pop(); 4988 4989 exit |= EXI_SAVE_PREEMPT; 4990 vmcs_write(EXI_CONTROLS, exit); 4991 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer enabled"); 4992 test_vmx_valid_controls(); 4993 report_prefix_pop(); 4994 4995 pin &= ~PIN_PREEMPT; 4996 vmcs_write(PIN_CONTROLS, pin); 4997 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer enabled"); 4998 test_vmx_invalid_controls(); 4999 report_prefix_pop(); 5000 5001 exit &= ~EXI_SAVE_PREEMPT; 5002 vmcs_write(EXI_CONTROLS, exit); 5003 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer disabled"); 5004 test_vmx_valid_controls(); 5005 report_prefix_pop(); 5006 5007 vmcs_write(PIN_CONTROLS, saved_pin); 5008 vmcs_write(EXI_CONTROLS, saved_exit); 5009 } 5010 5011 extern unsigned char test_mtf1; 5012 extern unsigned char test_mtf2; 5013 extern unsigned char test_mtf3; 5014 extern unsigned char test_mtf4; 5015 5016 static void test_mtf_guest(void) 5017 { 5018 asm ("vmcall;\n\t" 5019 "out %al, $0x80;\n\t" 5020 "test_mtf1:\n\t" 5021 "vmcall;\n\t" 5022 "out %al, $0x80;\n\t" 5023 "test_mtf2:\n\t" 5024 /* 5025 * Prepare for the 'MOV CR3' test. Attempt to induce a 5026 * general-protection fault by moving a non-canonical address into 5027 * CR3. The 'MOV CR3' instruction does not take an imm64 operand, 5028 * so we must MOV the desired value into a register first. 5029 * 5030 * MOV RAX is done before the VMCALL such that MTF is only enabled 5031 * for the instruction under test. 5032 */ 5033 "mov $0xaaaaaaaaaaaaaaaa, %rax;\n\t" 5034 "vmcall;\n\t" 5035 "mov %rax, %cr3;\n\t" 5036 "test_mtf3:\n\t" 5037 "vmcall;\n\t" 5038 /* 5039 * ICEBP/INT1 instruction. Though the instruction is now 5040 * documented, don't rely on assemblers enumerating the 5041 * instruction. Resort to hand assembly. 5042 */ 5043 ".byte 0xf1;\n\t" 5044 "vmcall;\n\t" 5045 "test_mtf4:\n\t" 5046 "mov $0, %eax;\n\t"); 5047 } 5048 5049 static void test_mtf_gp_handler(struct ex_regs *regs) 5050 { 5051 regs->rip = (unsigned long) &test_mtf3; 5052 } 5053 5054 static void test_mtf_db_handler(struct ex_regs *regs) 5055 { 5056 } 5057 5058 static void enable_mtf(void) 5059 { 5060 u32 ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 5061 5062 vmcs_write(CPU_EXEC_CTRL0, ctrl0 | CPU_MTF); 5063 } 5064 5065 static void disable_mtf(void) 5066 { 5067 u32 ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 5068 5069 vmcs_write(CPU_EXEC_CTRL0, ctrl0 & ~CPU_MTF); 5070 } 5071 5072 static void enable_tf(void) 5073 { 5074 unsigned long rflags = vmcs_read(GUEST_RFLAGS); 5075 5076 vmcs_write(GUEST_RFLAGS, rflags | X86_EFLAGS_TF); 5077 } 5078 5079 static void disable_tf(void) 5080 { 5081 unsigned long rflags = vmcs_read(GUEST_RFLAGS); 5082 5083 vmcs_write(GUEST_RFLAGS, rflags & ~X86_EFLAGS_TF); 5084 } 5085 5086 static void report_mtf(const char *insn_name, unsigned long exp_rip) 5087 { 5088 unsigned long rip = vmcs_read(GUEST_RIP); 5089 5090 assert_exit_reason(VMX_MTF); 5091 report(rip == exp_rip, "MTF VM-exit after %s. RIP: 0x%lx (expected 0x%lx)", 5092 insn_name, rip, exp_rip); 5093 } 5094 5095 static void vmx_mtf_test(void) 5096 { 5097 unsigned long pending_dbg; 5098 handler old_gp, old_db; 5099 5100 if (!(ctrl_cpu_rev[0].clr & CPU_MTF)) { 5101 printf("CPU does not support the 'monitor trap flag' processor-based VM-execution control.\n"); 5102 return; 5103 } 5104 5105 test_set_guest(test_mtf_guest); 5106 5107 /* Expect an MTF VM-exit after OUT instruction */ 5108 enter_guest(); 5109 skip_exit_vmcall(); 5110 5111 enable_mtf(); 5112 enter_guest(); 5113 report_mtf("OUT", (unsigned long) &test_mtf1); 5114 disable_mtf(); 5115 5116 /* 5117 * Concurrent #DB trap and MTF on instruction boundary. Expect MTF 5118 * VM-exit with populated 'pending debug exceptions' VMCS field. 5119 */ 5120 enter_guest(); 5121 skip_exit_vmcall(); 5122 5123 enable_mtf(); 5124 enable_tf(); 5125 5126 enter_guest(); 5127 report_mtf("OUT", (unsigned long) &test_mtf2); 5128 pending_dbg = vmcs_read(GUEST_PENDING_DEBUG); 5129 report(pending_dbg & DR_STEP, 5130 "'pending debug exceptions' field after MTF VM-exit: 0x%lx (expected 0x%lx)", 5131 pending_dbg, (unsigned long) DR_STEP); 5132 5133 disable_mtf(); 5134 disable_tf(); 5135 vmcs_write(GUEST_PENDING_DEBUG, 0); 5136 5137 /* 5138 * #GP exception takes priority over MTF. Expect MTF VM-exit with RIP 5139 * advanced to first instruction of #GP handler. 5140 */ 5141 enter_guest(); 5142 skip_exit_vmcall(); 5143 5144 old_gp = handle_exception(GP_VECTOR, test_mtf_gp_handler); 5145 5146 enable_mtf(); 5147 enter_guest(); 5148 report_mtf("MOV CR3", (unsigned long) get_idt_addr(&boot_idt[GP_VECTOR])); 5149 disable_mtf(); 5150 5151 /* 5152 * Concurrent MTF and privileged software exception (i.e. ICEBP/INT1). 5153 * MTF should follow the delivery of #DB trap, though the SDM doesn't 5154 * provide clear indication of the relative priority. 5155 */ 5156 enter_guest(); 5157 skip_exit_vmcall(); 5158 5159 handle_exception(GP_VECTOR, old_gp); 5160 old_db = handle_exception(DB_VECTOR, test_mtf_db_handler); 5161 5162 enable_mtf(); 5163 enter_guest(); 5164 report_mtf("INT1", (unsigned long) get_idt_addr(&boot_idt[DB_VECTOR])); 5165 disable_mtf(); 5166 5167 enter_guest(); 5168 skip_exit_vmcall(); 5169 handle_exception(DB_VECTOR, old_db); 5170 vmcs_write(ENT_INTR_INFO, INTR_INFO_VALID_MASK | INTR_TYPE_OTHER_EVENT); 5171 enter_guest(); 5172 report_mtf("injected MTF", (unsigned long) &test_mtf4); 5173 enter_guest(); 5174 } 5175 5176 extern char vmx_mtf_pdpte_guest_begin; 5177 extern char vmx_mtf_pdpte_guest_end; 5178 5179 asm("vmx_mtf_pdpte_guest_begin:\n\t" 5180 "mov %cr0, %rax\n\t" /* save CR0 with PG=1 */ 5181 "vmcall\n\t" /* on return from this CR0.PG=0 */ 5182 "mov %rax, %cr0\n\t" /* restore CR0.PG=1 to enter PAE mode */ 5183 "vmcall\n\t" 5184 "retq\n\t" 5185 "vmx_mtf_pdpte_guest_end:"); 5186 5187 static void vmx_mtf_pdpte_test(void) 5188 { 5189 void *test_mtf_pdpte_guest; 5190 pteval_t *pdpt; 5191 u32 guest_ar_cs; 5192 u64 guest_efer; 5193 pteval_t *pte; 5194 u64 guest_cr0; 5195 u64 guest_cr3; 5196 u64 guest_cr4; 5197 u64 ent_ctls; 5198 int i; 5199 5200 if (setup_ept(false)) 5201 return; 5202 5203 if (!(ctrl_cpu_rev[0].clr & CPU_MTF)) { 5204 printf("CPU does not support 'monitor trap flag.'\n"); 5205 return; 5206 } 5207 5208 if (!(ctrl_cpu_rev[1].clr & CPU_URG)) { 5209 printf("CPU does not support 'unrestricted guest.'\n"); 5210 return; 5211 } 5212 5213 vmcs_write(EXC_BITMAP, ~0); 5214 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | CPU_URG); 5215 5216 /* 5217 * Copy the guest code to an identity-mapped page. 5218 */ 5219 test_mtf_pdpte_guest = alloc_page(); 5220 memcpy(test_mtf_pdpte_guest, &vmx_mtf_pdpte_guest_begin, 5221 &vmx_mtf_pdpte_guest_end - &vmx_mtf_pdpte_guest_begin); 5222 5223 test_set_guest(test_mtf_pdpte_guest); 5224 5225 enter_guest(); 5226 skip_exit_vmcall(); 5227 5228 /* 5229 * Put the guest in non-paged 32-bit protected mode, ready to enter 5230 * PAE mode when CR0.PG is set. CR4.PAE will already have been set 5231 * when the guest started out in long mode. 5232 */ 5233 ent_ctls = vmcs_read(ENT_CONTROLS); 5234 vmcs_write(ENT_CONTROLS, ent_ctls & ~ENT_GUEST_64); 5235 5236 guest_efer = vmcs_read(GUEST_EFER); 5237 vmcs_write(GUEST_EFER, guest_efer & ~(EFER_LMA | EFER_LME)); 5238 5239 /* 5240 * Set CS access rights bits for 32-bit protected mode: 5241 * 3:0 B execute/read/accessed 5242 * 4 1 code or data 5243 * 6:5 0 descriptor privilege level 5244 * 7 1 present 5245 * 11:8 0 reserved 5246 * 12 0 available for use by system software 5247 * 13 0 64 bit mode not active 5248 * 14 1 default operation size 32-bit segment 5249 * 15 1 page granularity: segment limit in 4K units 5250 * 16 0 segment usable 5251 * 31:17 0 reserved 5252 */ 5253 guest_ar_cs = vmcs_read(GUEST_AR_CS); 5254 vmcs_write(GUEST_AR_CS, 0xc09b); 5255 5256 guest_cr0 = vmcs_read(GUEST_CR0); 5257 vmcs_write(GUEST_CR0, guest_cr0 & ~X86_CR0_PG); 5258 5259 guest_cr4 = vmcs_read(GUEST_CR4); 5260 vmcs_write(GUEST_CR4, guest_cr4 & ~X86_CR4_PCIDE); 5261 5262 guest_cr3 = vmcs_read(GUEST_CR3); 5263 5264 /* 5265 * Turn the 4-level page table into a PAE page table by following the 0th 5266 * PML4 entry to a PDPT page, and grab the first four PDPTEs from that 5267 * page. 5268 * 5269 * Why does this work? 5270 * 5271 * PAE uses 32-bit addressing which implies: 5272 * Bits 11:0 page offset 5273 * Bits 20:12 entry into 512-entry page table 5274 * Bits 29:21 entry into a 512-entry directory table 5275 * Bits 31:30 entry into the page directory pointer table. 5276 * Bits 63:32 zero 5277 * 5278 * As only 2 bits are needed to select the PDPTEs for the entire 5279 * 32-bit address space, take the first 4 PDPTEs in the level 3 page 5280 * directory pointer table. It doesn't matter which of these PDPTEs 5281 * are present because they must cover the guest code given that it 5282 * has already run successfully. 5283 * 5284 * Get a pointer to PTE for GVA=0 in the page directory pointer table 5285 */ 5286 pte = get_pte_level( 5287 (pgd_t *)phys_to_virt(guest_cr3 & ~X86_CR3_PCID_MASK), 0, 5288 PDPT_LEVEL); 5289 5290 /* 5291 * Need some memory for the 4-entry PAE page directory pointer 5292 * table. Use the end of the identity-mapped page where the guest code 5293 * is stored. There is definitely space as the guest code is only a 5294 * few bytes. 5295 */ 5296 pdpt = test_mtf_pdpte_guest + PAGE_SIZE - 4 * sizeof(pteval_t); 5297 5298 /* 5299 * Copy the first four PDPTEs into the PAE page table with reserved 5300 * bits cleared. Note that permission bits from the PML4E and PDPTE 5301 * are not propagated. 5302 */ 5303 for (i = 0; i < 4; i++) { 5304 TEST_ASSERT_EQ_MSG(0, (pte[i] & PDPTE64_RSVD_MASK), 5305 "PDPTE has invalid reserved bits"); 5306 TEST_ASSERT_EQ_MSG(0, (pte[i] & PDPTE64_PAGE_SIZE_MASK), 5307 "Cannot use 1GB super pages for PAE"); 5308 pdpt[i] = pte[i] & ~(PAE_PDPTE_RSVD_MASK); 5309 } 5310 vmcs_write(GUEST_CR3, virt_to_phys(pdpt)); 5311 5312 enable_mtf(); 5313 enter_guest(); 5314 assert_exit_reason(VMX_MTF); 5315 disable_mtf(); 5316 5317 /* 5318 * The four PDPTEs should have been loaded into the VMCS when 5319 * the guest set CR0.PG to enter PAE mode. 5320 */ 5321 for (i = 0; i < 4; i++) { 5322 u64 pdpte = vmcs_read(GUEST_PDPTE + 2 * i); 5323 5324 report(pdpte == pdpt[i], "PDPTE%d is 0x%lx (expected 0x%lx)", 5325 i, pdpte, pdpt[i]); 5326 } 5327 5328 /* 5329 * Now, try to enter the guest in PAE mode. If the PDPTEs in the 5330 * vmcs are wrong, this will fail. 5331 */ 5332 enter_guest(); 5333 skip_exit_vmcall(); 5334 5335 /* 5336 * Return guest to 64-bit mode and wrap up. 5337 */ 5338 vmcs_write(ENT_CONTROLS, ent_ctls); 5339 vmcs_write(GUEST_EFER, guest_efer); 5340 vmcs_write(GUEST_AR_CS, guest_ar_cs); 5341 vmcs_write(GUEST_CR0, guest_cr0); 5342 vmcs_write(GUEST_CR4, guest_cr4); 5343 vmcs_write(GUEST_CR3, guest_cr3); 5344 5345 enter_guest(); 5346 } 5347 5348 /* 5349 * Tests for VM-execution control fields 5350 */ 5351 static void test_vm_execution_ctls(void) 5352 { 5353 test_pin_based_ctls(); 5354 test_primary_processor_based_ctls(); 5355 test_secondary_processor_based_ctls(); 5356 test_cr3_targets(); 5357 test_io_bitmaps(); 5358 test_msr_bitmap(); 5359 test_apic_ctls(); 5360 test_tpr_threshold(); 5361 test_nmi_ctrls(); 5362 test_pml(); 5363 test_vpid(); 5364 test_ept_eptp(); 5365 test_vmx_preemption_timer(); 5366 } 5367 5368 /* 5369 * The following checks are performed for the VM-entry MSR-load address if 5370 * the VM-entry MSR-load count field is non-zero: 5371 * 5372 * - The lower 4 bits of the VM-entry MSR-load address must be 0. 5373 * The address should not set any bits beyond the processor's 5374 * physical-address width. 5375 * 5376 * - The address of the last byte in the VM-entry MSR-load area 5377 * should not set any bits beyond the processor's physical-address 5378 * width. The address of this last byte is VM-entry MSR-load address 5379 * + (MSR count * 16) - 1. (The arithmetic used for the computation 5380 * uses more bits than the processor's physical-address width.) 5381 * 5382 * 5383 * [Intel SDM] 5384 */ 5385 static void test_entry_msr_load(void) 5386 { 5387 entry_msr_load = alloc_page(); 5388 u64 tmp; 5389 u32 entry_msr_ld_cnt = 1; 5390 int i; 5391 u32 addr_len = 64; 5392 5393 vmcs_write(ENT_MSR_LD_CNT, entry_msr_ld_cnt); 5394 5395 /* Check first 4 bits of VM-entry MSR-load address */ 5396 for (i = 0; i < 4; i++) { 5397 tmp = (u64)entry_msr_load | 1ull << i; 5398 vmcs_write(ENTER_MSR_LD_ADDR, tmp); 5399 report_prefix_pushf("VM-entry MSR-load addr [4:0] %lx", 5400 tmp & 0xf); 5401 test_vmx_invalid_controls(); 5402 report_prefix_pop(); 5403 } 5404 5405 if (basic.val & (1ul << 48)) 5406 addr_len = 32; 5407 5408 test_vmcs_addr_values("VM-entry-MSR-load address", 5409 ENTER_MSR_LD_ADDR, 16, false, false, 5410 4, addr_len - 1); 5411 5412 /* 5413 * Check last byte of VM-entry MSR-load address 5414 */ 5415 entry_msr_load = (struct vmx_msr_entry *)((u64)entry_msr_load & ~0xf); 5416 5417 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 5418 i < 64; i++) { 5419 tmp = ((u64)entry_msr_load + entry_msr_ld_cnt * 16 - 1) | 5420 1ul << i; 5421 vmcs_write(ENTER_MSR_LD_ADDR, 5422 tmp - (entry_msr_ld_cnt * 16 - 1)); 5423 test_vmx_invalid_controls(); 5424 } 5425 5426 vmcs_write(ENT_MSR_LD_CNT, 2); 5427 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 5428 test_vmx_invalid_controls(); 5429 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 5430 test_vmx_valid_controls(); 5431 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 5432 test_vmx_valid_controls(); 5433 } 5434 5435 static struct vmx_state_area_test_data { 5436 u32 msr; 5437 u64 exp; 5438 bool enabled; 5439 } vmx_state_area_test_data; 5440 5441 static void guest_state_test_main(void) 5442 { 5443 u64 obs; 5444 struct vmx_state_area_test_data *data = &vmx_state_area_test_data; 5445 5446 while (1) { 5447 if (vmx_get_test_stage() == 2) 5448 break; 5449 5450 if (data->enabled) { 5451 obs = rdmsr(data->msr); 5452 report(data->exp == obs, 5453 "Guest state is 0x%lx (expected 0x%lx)", 5454 obs, data->exp); 5455 } 5456 5457 vmcall(); 5458 } 5459 5460 asm volatile("fnop"); 5461 } 5462 5463 static void test_guest_state(const char *test, bool xfail, u64 field, 5464 const char * field_name) 5465 { 5466 struct vmentry_result result; 5467 u8 abort_flags; 5468 5469 abort_flags = ABORT_ON_EARLY_VMENTRY_FAIL; 5470 if (!xfail) 5471 abort_flags = ABORT_ON_INVALID_GUEST_STATE; 5472 5473 __enter_guest(abort_flags, &result); 5474 5475 report(result.exit_reason.failed_vmentry == xfail && 5476 ((xfail && result.exit_reason.basic == VMX_FAIL_STATE) || 5477 (!xfail && result.exit_reason.basic == VMX_VMCALL)) && 5478 (!xfail || vmcs_read(EXI_QUALIFICATION) == ENTRY_FAIL_DEFAULT), 5479 "%s, %s = %lx", test, field_name, field); 5480 5481 if (!result.exit_reason.failed_vmentry) 5482 skip_exit_insn(); 5483 } 5484 5485 /* 5486 * Tests for VM-entry control fields 5487 */ 5488 static void test_vm_entry_ctls(void) 5489 { 5490 test_invalid_event_injection(); 5491 test_entry_msr_load(); 5492 } 5493 5494 /* 5495 * The following checks are performed for the VM-exit MSR-store address if 5496 * the VM-exit MSR-store count field is non-zero: 5497 * 5498 * - The lower 4 bits of the VM-exit MSR-store address must be 0. 5499 * The address should not set any bits beyond the processor's 5500 * physical-address width. 5501 * 5502 * - The address of the last byte in the VM-exit MSR-store area 5503 * should not set any bits beyond the processor's physical-address 5504 * width. The address of this last byte is VM-exit MSR-store address 5505 * + (MSR count * 16) - 1. (The arithmetic used for the computation 5506 * uses more bits than the processor's physical-address width.) 5507 * 5508 * If IA32_VMX_BASIC[48] is read as 1, neither address should set any bits 5509 * in the range 63:32. 5510 * 5511 * [Intel SDM] 5512 */ 5513 static void test_exit_msr_store(void) 5514 { 5515 exit_msr_store = alloc_page(); 5516 u64 tmp; 5517 u32 exit_msr_st_cnt = 1; 5518 int i; 5519 u32 addr_len = 64; 5520 5521 vmcs_write(EXI_MSR_ST_CNT, exit_msr_st_cnt); 5522 5523 /* Check first 4 bits of VM-exit MSR-store address */ 5524 for (i = 0; i < 4; i++) { 5525 tmp = (u64)exit_msr_store | 1ull << i; 5526 vmcs_write(EXIT_MSR_ST_ADDR, tmp); 5527 report_prefix_pushf("VM-exit MSR-store addr [4:0] %lx", 5528 tmp & 0xf); 5529 test_vmx_invalid_controls(); 5530 report_prefix_pop(); 5531 } 5532 5533 if (basic.val & (1ul << 48)) 5534 addr_len = 32; 5535 5536 test_vmcs_addr_values("VM-exit-MSR-store address", 5537 EXIT_MSR_ST_ADDR, 16, false, false, 5538 4, addr_len - 1); 5539 5540 /* 5541 * Check last byte of VM-exit MSR-store address 5542 */ 5543 exit_msr_store = (struct vmx_msr_entry *)((u64)exit_msr_store & ~0xf); 5544 5545 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 5546 i < 64; i++) { 5547 tmp = ((u64)exit_msr_store + exit_msr_st_cnt * 16 - 1) | 5548 1ul << i; 5549 vmcs_write(EXIT_MSR_ST_ADDR, 5550 tmp - (exit_msr_st_cnt * 16 - 1)); 5551 test_vmx_invalid_controls(); 5552 } 5553 5554 vmcs_write(EXI_MSR_ST_CNT, 2); 5555 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 5556 test_vmx_invalid_controls(); 5557 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 5558 test_vmx_valid_controls(); 5559 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 5560 test_vmx_valid_controls(); 5561 } 5562 5563 /* 5564 * Tests for VM-exit controls 5565 */ 5566 static void test_vm_exit_ctls(void) 5567 { 5568 test_exit_msr_store(); 5569 } 5570 5571 /* 5572 * Check that the virtual CPU checks all of the VMX controls as 5573 * documented in the Intel SDM. 5574 */ 5575 static void vmx_controls_test(void) 5576 { 5577 /* 5578 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 5579 * fail due to invalid guest state, should we make it that 5580 * far. 5581 */ 5582 vmcs_write(GUEST_RFLAGS, 0); 5583 5584 test_vm_execution_ctls(); 5585 test_vm_exit_ctls(); 5586 test_vm_entry_ctls(); 5587 } 5588 5589 struct apic_reg_virt_config { 5590 bool apic_register_virtualization; 5591 bool use_tpr_shadow; 5592 bool virtualize_apic_accesses; 5593 bool virtualize_x2apic_mode; 5594 bool activate_secondary_controls; 5595 }; 5596 5597 struct apic_reg_test { 5598 const char *name; 5599 struct apic_reg_virt_config apic_reg_virt_config; 5600 }; 5601 5602 struct apic_reg_virt_expectation { 5603 enum Reason rd_exit_reason; 5604 enum Reason wr_exit_reason; 5605 u32 val; 5606 u32 (*virt_fn)(u32); 5607 5608 /* 5609 * If false, accessing the APIC access address from L2 is treated as a 5610 * normal memory operation, rather than triggering virtualization. 5611 */ 5612 bool virtualize_apic_accesses; 5613 }; 5614 5615 static u32 apic_virt_identity(u32 val) 5616 { 5617 return val; 5618 } 5619 5620 static u32 apic_virt_nibble1(u32 val) 5621 { 5622 return val & 0xf0; 5623 } 5624 5625 static u32 apic_virt_byte3(u32 val) 5626 { 5627 return val & (0xff << 24); 5628 } 5629 5630 static bool apic_reg_virt_exit_expectation( 5631 u32 reg, struct apic_reg_virt_config *config, 5632 struct apic_reg_virt_expectation *expectation) 5633 { 5634 /* Good configs, where some L2 APIC accesses are virtualized. */ 5635 bool virtualize_apic_accesses_only = 5636 config->virtualize_apic_accesses && 5637 !config->use_tpr_shadow && 5638 !config->apic_register_virtualization && 5639 !config->virtualize_x2apic_mode && 5640 config->activate_secondary_controls; 5641 bool virtualize_apic_accesses_and_use_tpr_shadow = 5642 config->virtualize_apic_accesses && 5643 config->use_tpr_shadow && 5644 !config->apic_register_virtualization && 5645 !config->virtualize_x2apic_mode && 5646 config->activate_secondary_controls; 5647 bool apic_register_virtualization = 5648 config->virtualize_apic_accesses && 5649 config->use_tpr_shadow && 5650 config->apic_register_virtualization && 5651 !config->virtualize_x2apic_mode && 5652 config->activate_secondary_controls; 5653 5654 expectation->val = MAGIC_VAL_1; 5655 expectation->virt_fn = apic_virt_identity; 5656 expectation->virtualize_apic_accesses = 5657 config->virtualize_apic_accesses && 5658 config->activate_secondary_controls; 5659 if (virtualize_apic_accesses_only) { 5660 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5661 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5662 } else if (virtualize_apic_accesses_and_use_tpr_shadow) { 5663 switch (reg) { 5664 case APIC_TASKPRI: 5665 expectation->rd_exit_reason = VMX_VMCALL; 5666 expectation->wr_exit_reason = VMX_VMCALL; 5667 expectation->virt_fn = apic_virt_nibble1; 5668 break; 5669 default: 5670 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5671 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5672 } 5673 } else if (apic_register_virtualization) { 5674 expectation->rd_exit_reason = VMX_VMCALL; 5675 5676 switch (reg) { 5677 case APIC_ID: 5678 case APIC_EOI: 5679 case APIC_LDR: 5680 case APIC_DFR: 5681 case APIC_SPIV: 5682 case APIC_ESR: 5683 case APIC_ICR: 5684 case APIC_LVTT: 5685 case APIC_LVTTHMR: 5686 case APIC_LVTPC: 5687 case APIC_LVT0: 5688 case APIC_LVT1: 5689 case APIC_LVTERR: 5690 case APIC_TMICT: 5691 case APIC_TDCR: 5692 expectation->wr_exit_reason = VMX_APIC_WRITE; 5693 break; 5694 case APIC_LVR: 5695 case APIC_ISR ... APIC_ISR + 0x70: 5696 case APIC_TMR ... APIC_TMR + 0x70: 5697 case APIC_IRR ... APIC_IRR + 0x70: 5698 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5699 break; 5700 case APIC_TASKPRI: 5701 expectation->wr_exit_reason = VMX_VMCALL; 5702 expectation->virt_fn = apic_virt_nibble1; 5703 break; 5704 case APIC_ICR2: 5705 expectation->wr_exit_reason = VMX_VMCALL; 5706 expectation->virt_fn = apic_virt_byte3; 5707 break; 5708 default: 5709 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5710 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5711 } 5712 } else if (!expectation->virtualize_apic_accesses) { 5713 /* 5714 * No APIC registers are directly virtualized. This includes 5715 * VTPR, which can be virtualized through MOV to/from CR8 via 5716 * the use TPR shadow control, but not through directly 5717 * accessing VTPR. 5718 */ 5719 expectation->rd_exit_reason = VMX_VMCALL; 5720 expectation->wr_exit_reason = VMX_VMCALL; 5721 } else { 5722 printf("Cannot parse APIC register virtualization config:\n" 5723 "\tvirtualize_apic_accesses: %d\n" 5724 "\tuse_tpr_shadow: %d\n" 5725 "\tapic_register_virtualization: %d\n" 5726 "\tvirtualize_x2apic_mode: %d\n" 5727 "\tactivate_secondary_controls: %d\n", 5728 config->virtualize_apic_accesses, 5729 config->use_tpr_shadow, 5730 config->apic_register_virtualization, 5731 config->virtualize_x2apic_mode, 5732 config->activate_secondary_controls); 5733 5734 return false; 5735 } 5736 5737 return true; 5738 } 5739 5740 struct apic_reg_test apic_reg_tests[] = { 5741 /* Good configs, where some L2 APIC accesses are virtualized. */ 5742 { 5743 .name = "Virtualize APIC accesses", 5744 .apic_reg_virt_config = { 5745 .virtualize_apic_accesses = true, 5746 .use_tpr_shadow = false, 5747 .apic_register_virtualization = false, 5748 .virtualize_x2apic_mode = false, 5749 .activate_secondary_controls = true, 5750 }, 5751 }, 5752 { 5753 .name = "Virtualize APIC accesses + Use TPR shadow", 5754 .apic_reg_virt_config = { 5755 .virtualize_apic_accesses = true, 5756 .use_tpr_shadow = true, 5757 .apic_register_virtualization = false, 5758 .virtualize_x2apic_mode = false, 5759 .activate_secondary_controls = true, 5760 }, 5761 }, 5762 { 5763 .name = "APIC-register virtualization", 5764 .apic_reg_virt_config = { 5765 .virtualize_apic_accesses = true, 5766 .use_tpr_shadow = true, 5767 .apic_register_virtualization = true, 5768 .virtualize_x2apic_mode = false, 5769 .activate_secondary_controls = true, 5770 }, 5771 }, 5772 5773 /* 5774 * Test that the secondary processor-based VM-execution controls are 5775 * correctly ignored when "activate secondary controls" is disabled. 5776 */ 5777 { 5778 .name = "Activate secondary controls off", 5779 .apic_reg_virt_config = { 5780 .virtualize_apic_accesses = true, 5781 .use_tpr_shadow = false, 5782 .apic_register_virtualization = true, 5783 .virtualize_x2apic_mode = true, 5784 .activate_secondary_controls = false, 5785 }, 5786 }, 5787 { 5788 .name = "Activate secondary controls off + Use TPR shadow", 5789 .apic_reg_virt_config = { 5790 .virtualize_apic_accesses = true, 5791 .use_tpr_shadow = true, 5792 .apic_register_virtualization = true, 5793 .virtualize_x2apic_mode = true, 5794 .activate_secondary_controls = false, 5795 }, 5796 }, 5797 5798 /* 5799 * Test that the APIC access address is treated like an arbitrary memory 5800 * address when "virtualize APIC accesses" is disabled. 5801 */ 5802 { 5803 .name = "Virtualize APIC accesses off + Use TPR shadow", 5804 .apic_reg_virt_config = { 5805 .virtualize_apic_accesses = false, 5806 .use_tpr_shadow = true, 5807 .apic_register_virtualization = true, 5808 .virtualize_x2apic_mode = true, 5809 .activate_secondary_controls = true, 5810 }, 5811 }, 5812 5813 /* 5814 * Test that VM entry fails due to invalid controls when 5815 * "APIC-register virtualization" is enabled while "use TPR shadow" is 5816 * disabled. 5817 */ 5818 { 5819 .name = "APIC-register virtualization + Use TPR shadow off", 5820 .apic_reg_virt_config = { 5821 .virtualize_apic_accesses = true, 5822 .use_tpr_shadow = false, 5823 .apic_register_virtualization = true, 5824 .virtualize_x2apic_mode = false, 5825 .activate_secondary_controls = true, 5826 }, 5827 }, 5828 5829 /* 5830 * Test that VM entry fails due to invalid controls when 5831 * "Virtualize x2APIC mode" is enabled while "use TPR shadow" is 5832 * disabled. 5833 */ 5834 { 5835 .name = "Virtualize x2APIC mode + Use TPR shadow off", 5836 .apic_reg_virt_config = { 5837 .virtualize_apic_accesses = false, 5838 .use_tpr_shadow = false, 5839 .apic_register_virtualization = false, 5840 .virtualize_x2apic_mode = true, 5841 .activate_secondary_controls = true, 5842 }, 5843 }, 5844 { 5845 .name = "Virtualize x2APIC mode + Use TPR shadow off v2", 5846 .apic_reg_virt_config = { 5847 .virtualize_apic_accesses = false, 5848 .use_tpr_shadow = false, 5849 .apic_register_virtualization = true, 5850 .virtualize_x2apic_mode = true, 5851 .activate_secondary_controls = true, 5852 }, 5853 }, 5854 5855 /* 5856 * Test that VM entry fails due to invalid controls when 5857 * "virtualize x2APIC mode" is enabled while "virtualize APIC accesses" 5858 * is enabled. 5859 */ 5860 { 5861 .name = "Virtualize x2APIC mode + Virtualize APIC accesses", 5862 .apic_reg_virt_config = { 5863 .virtualize_apic_accesses = true, 5864 .use_tpr_shadow = true, 5865 .apic_register_virtualization = false, 5866 .virtualize_x2apic_mode = true, 5867 .activate_secondary_controls = true, 5868 }, 5869 }, 5870 { 5871 .name = "Virtualize x2APIC mode + Virtualize APIC accesses v2", 5872 .apic_reg_virt_config = { 5873 .virtualize_apic_accesses = true, 5874 .use_tpr_shadow = true, 5875 .apic_register_virtualization = true, 5876 .virtualize_x2apic_mode = true, 5877 .activate_secondary_controls = true, 5878 }, 5879 }, 5880 }; 5881 5882 enum Apic_op { 5883 APIC_OP_XAPIC_RD, 5884 APIC_OP_XAPIC_WR, 5885 TERMINATE, 5886 }; 5887 5888 static u32 vmx_xapic_read(u32 *apic_access_address, u32 reg) 5889 { 5890 return *(volatile u32 *)((uintptr_t)apic_access_address + reg); 5891 } 5892 5893 static void vmx_xapic_write(u32 *apic_access_address, u32 reg, u32 val) 5894 { 5895 *(volatile u32 *)((uintptr_t)apic_access_address + reg) = val; 5896 } 5897 5898 struct apic_reg_virt_guest_args { 5899 enum Apic_op op; 5900 u32 *apic_access_address; 5901 u32 reg; 5902 u32 val; 5903 bool check_rd; 5904 u32 (*virt_fn)(u32); 5905 } apic_reg_virt_guest_args; 5906 5907 static void apic_reg_virt_guest(void) 5908 { 5909 volatile struct apic_reg_virt_guest_args *args = 5910 &apic_reg_virt_guest_args; 5911 5912 for (;;) { 5913 enum Apic_op op = args->op; 5914 u32 *apic_access_address = args->apic_access_address; 5915 u32 reg = args->reg; 5916 u32 val = args->val; 5917 bool check_rd = args->check_rd; 5918 u32 (*virt_fn)(u32) = args->virt_fn; 5919 5920 if (op == TERMINATE) 5921 break; 5922 5923 if (op == APIC_OP_XAPIC_RD) { 5924 u32 ret = vmx_xapic_read(apic_access_address, reg); 5925 5926 if (check_rd) { 5927 u32 want = virt_fn(val); 5928 u32 got = virt_fn(ret); 5929 5930 report(got == want, 5931 "read 0x%x, expected 0x%x.", got, want); 5932 } 5933 } else if (op == APIC_OP_XAPIC_WR) { 5934 vmx_xapic_write(apic_access_address, reg, val); 5935 } 5936 5937 /* 5938 * The L1 should always execute a vmcall after it's done testing 5939 * an individual APIC operation. This helps to validate that the 5940 * L1 and L2 are in sync with each other, as expected. 5941 */ 5942 vmcall(); 5943 } 5944 } 5945 5946 static void test_xapic_rd( 5947 u32 reg, struct apic_reg_virt_expectation *expectation, 5948 u32 *apic_access_address, u32 *virtual_apic_page) 5949 { 5950 u32 val = expectation->val; 5951 u32 exit_reason_want = expectation->rd_exit_reason; 5952 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 5953 5954 report_prefix_pushf("xapic - reading 0x%03x", reg); 5955 5956 /* Configure guest to do an xapic read */ 5957 args->op = APIC_OP_XAPIC_RD; 5958 args->apic_access_address = apic_access_address; 5959 args->reg = reg; 5960 args->val = val; 5961 args->check_rd = exit_reason_want == VMX_VMCALL; 5962 args->virt_fn = expectation->virt_fn; 5963 5964 /* Setup virtual APIC page */ 5965 if (!expectation->virtualize_apic_accesses) { 5966 apic_access_address[apic_reg_index(reg)] = val; 5967 virtual_apic_page[apic_reg_index(reg)] = 0; 5968 } else if (exit_reason_want == VMX_VMCALL) { 5969 apic_access_address[apic_reg_index(reg)] = 0; 5970 virtual_apic_page[apic_reg_index(reg)] = val; 5971 } 5972 5973 /* Enter guest */ 5974 enter_guest(); 5975 5976 /* 5977 * Validate the behavior and 5978 * pass a magic value back to the guest. 5979 */ 5980 if (exit_reason_want == VMX_APIC_ACCESS) { 5981 u32 apic_page_offset = vmcs_read(EXI_QUALIFICATION) & 0xfff; 5982 5983 assert_exit_reason(exit_reason_want); 5984 report(apic_page_offset == reg, 5985 "got APIC access exit @ page offset 0x%03x, want 0x%03x", 5986 apic_page_offset, reg); 5987 skip_exit_insn(); 5988 5989 /* Reenter guest so it can consume/check rcx and exit again. */ 5990 enter_guest(); 5991 } else if (exit_reason_want != VMX_VMCALL) { 5992 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 5993 } 5994 5995 skip_exit_vmcall(); 5996 report_prefix_pop(); 5997 } 5998 5999 static void test_xapic_wr( 6000 u32 reg, struct apic_reg_virt_expectation *expectation, 6001 u32 *apic_access_address, u32 *virtual_apic_page) 6002 { 6003 u32 val = expectation->val; 6004 u32 exit_reason_want = expectation->wr_exit_reason; 6005 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 6006 bool virtualized = 6007 expectation->virtualize_apic_accesses && 6008 (exit_reason_want == VMX_APIC_WRITE || 6009 exit_reason_want == VMX_VMCALL); 6010 bool checked = false; 6011 6012 report_prefix_pushf("xapic - writing 0x%x to 0x%03x", val, reg); 6013 6014 /* Configure guest to do an xapic read */ 6015 args->op = APIC_OP_XAPIC_WR; 6016 args->apic_access_address = apic_access_address; 6017 args->reg = reg; 6018 args->val = val; 6019 6020 /* Setup virtual APIC page */ 6021 if (virtualized || !expectation->virtualize_apic_accesses) { 6022 apic_access_address[apic_reg_index(reg)] = 0; 6023 virtual_apic_page[apic_reg_index(reg)] = 0; 6024 } 6025 6026 /* Enter guest */ 6027 enter_guest(); 6028 6029 /* 6030 * Validate the behavior and 6031 * pass a magic value back to the guest. 6032 */ 6033 if (exit_reason_want == VMX_APIC_ACCESS) { 6034 u32 apic_page_offset = vmcs_read(EXI_QUALIFICATION) & 0xfff; 6035 6036 assert_exit_reason(exit_reason_want); 6037 report(apic_page_offset == reg, 6038 "got APIC access exit @ page offset 0x%03x, want 0x%03x", 6039 apic_page_offset, reg); 6040 skip_exit_insn(); 6041 6042 /* Reenter guest so it can consume/check rcx and exit again. */ 6043 enter_guest(); 6044 } else if (exit_reason_want == VMX_APIC_WRITE) { 6045 assert_exit_reason(exit_reason_want); 6046 report(virtual_apic_page[apic_reg_index(reg)] == val, 6047 "got APIC write exit @ page offset 0x%03x; val is 0x%x, want 0x%x", 6048 apic_reg_index(reg), 6049 virtual_apic_page[apic_reg_index(reg)], val); 6050 checked = true; 6051 6052 /* Reenter guest so it can consume/check rcx and exit again. */ 6053 enter_guest(); 6054 } else if (exit_reason_want != VMX_VMCALL) { 6055 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 6056 } 6057 6058 assert_exit_reason(VMX_VMCALL); 6059 if (virtualized && !checked) { 6060 u32 want = expectation->virt_fn(val); 6061 u32 got = virtual_apic_page[apic_reg_index(reg)]; 6062 got = expectation->virt_fn(got); 6063 6064 report(got == want, "exitless write; val is 0x%x, want 0x%x", 6065 got, want); 6066 } else if (!expectation->virtualize_apic_accesses && !checked) { 6067 u32 got = apic_access_address[apic_reg_index(reg)]; 6068 6069 report(got == val, 6070 "non-virtualized write; val is 0x%x, want 0x%x", got, 6071 val); 6072 } else if (!expectation->virtualize_apic_accesses && checked) { 6073 report_fail("Non-virtualized write was prematurely checked!"); 6074 } 6075 6076 skip_exit_vmcall(); 6077 report_prefix_pop(); 6078 } 6079 6080 enum Config_type { 6081 CONFIG_TYPE_GOOD, 6082 CONFIG_TYPE_UNSUPPORTED, 6083 CONFIG_TYPE_VMENTRY_FAILS_EARLY, 6084 }; 6085 6086 static enum Config_type configure_apic_reg_virt_test( 6087 struct apic_reg_virt_config *apic_reg_virt_config) 6088 { 6089 u32 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6090 u32 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6091 /* Configs where L2 entry fails early, due to invalid controls. */ 6092 bool use_tpr_shadow_incorrectly_off = 6093 !apic_reg_virt_config->use_tpr_shadow && 6094 (apic_reg_virt_config->apic_register_virtualization || 6095 apic_reg_virt_config->virtualize_x2apic_mode) && 6096 apic_reg_virt_config->activate_secondary_controls; 6097 bool virtualize_apic_accesses_incorrectly_on = 6098 apic_reg_virt_config->virtualize_apic_accesses && 6099 apic_reg_virt_config->virtualize_x2apic_mode && 6100 apic_reg_virt_config->activate_secondary_controls; 6101 bool vmentry_fails_early = 6102 use_tpr_shadow_incorrectly_off || 6103 virtualize_apic_accesses_incorrectly_on; 6104 6105 if (apic_reg_virt_config->activate_secondary_controls) { 6106 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 6107 printf("VM-execution control \"activate secondary controls\" NOT supported.\n"); 6108 return CONFIG_TYPE_UNSUPPORTED; 6109 } 6110 cpu_exec_ctrl0 |= CPU_SECONDARY; 6111 } else { 6112 cpu_exec_ctrl0 &= ~CPU_SECONDARY; 6113 } 6114 6115 if (apic_reg_virt_config->virtualize_apic_accesses) { 6116 if (!(ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES)) { 6117 printf("VM-execution control \"virtualize APIC accesses\" NOT supported.\n"); 6118 return CONFIG_TYPE_UNSUPPORTED; 6119 } 6120 cpu_exec_ctrl1 |= CPU_VIRT_APIC_ACCESSES; 6121 } else { 6122 cpu_exec_ctrl1 &= ~CPU_VIRT_APIC_ACCESSES; 6123 } 6124 6125 if (apic_reg_virt_config->use_tpr_shadow) { 6126 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) { 6127 printf("VM-execution control \"use TPR shadow\" NOT supported.\n"); 6128 return CONFIG_TYPE_UNSUPPORTED; 6129 } 6130 cpu_exec_ctrl0 |= CPU_TPR_SHADOW; 6131 } else { 6132 cpu_exec_ctrl0 &= ~CPU_TPR_SHADOW; 6133 } 6134 6135 if (apic_reg_virt_config->apic_register_virtualization) { 6136 if (!(ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT)) { 6137 printf("VM-execution control \"APIC-register virtualization\" NOT supported.\n"); 6138 return CONFIG_TYPE_UNSUPPORTED; 6139 } 6140 cpu_exec_ctrl1 |= CPU_APIC_REG_VIRT; 6141 } else { 6142 cpu_exec_ctrl1 &= ~CPU_APIC_REG_VIRT; 6143 } 6144 6145 if (apic_reg_virt_config->virtualize_x2apic_mode) { 6146 if (!(ctrl_cpu_rev[1].clr & CPU_VIRT_X2APIC)) { 6147 printf("VM-execution control \"virtualize x2APIC mode\" NOT supported.\n"); 6148 return CONFIG_TYPE_UNSUPPORTED; 6149 } 6150 cpu_exec_ctrl1 |= CPU_VIRT_X2APIC; 6151 } else { 6152 cpu_exec_ctrl1 &= ~CPU_VIRT_X2APIC; 6153 } 6154 6155 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6156 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6157 6158 if (vmentry_fails_early) 6159 return CONFIG_TYPE_VMENTRY_FAILS_EARLY; 6160 6161 return CONFIG_TYPE_GOOD; 6162 } 6163 6164 static bool cpu_has_apicv(void) 6165 { 6166 return ((ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT) && 6167 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 6168 (ctrl_pin_rev.clr & PIN_POST_INTR)); 6169 } 6170 6171 /* Validates APIC register access across valid virtualization configurations. */ 6172 static void apic_reg_virt_test(void) 6173 { 6174 u32 *apic_access_address; 6175 u32 *virtual_apic_page; 6176 u64 control; 6177 u64 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6178 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6179 int i; 6180 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 6181 6182 if (!cpu_has_apicv()) { 6183 report_skip(__func__); 6184 return; 6185 } 6186 6187 control = cpu_exec_ctrl1; 6188 control &= ~CPU_VINTD; 6189 vmcs_write(CPU_EXEC_CTRL1, control); 6190 6191 test_set_guest(apic_reg_virt_guest); 6192 6193 /* 6194 * From the SDM: The 1-setting of the "virtualize APIC accesses" 6195 * VM-execution is guaranteed to apply only if translations to the 6196 * APIC-access address use a 4-KByte page. 6197 */ 6198 apic_access_address = alloc_page(); 6199 force_4k_page(apic_access_address); 6200 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_address)); 6201 6202 virtual_apic_page = alloc_page(); 6203 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 6204 6205 for (i = 0; i < ARRAY_SIZE(apic_reg_tests); i++) { 6206 struct apic_reg_test *apic_reg_test = &apic_reg_tests[i]; 6207 struct apic_reg_virt_config *apic_reg_virt_config = 6208 &apic_reg_test->apic_reg_virt_config; 6209 enum Config_type config_type; 6210 u32 reg; 6211 6212 printf("--- %s test ---\n", apic_reg_test->name); 6213 config_type = 6214 configure_apic_reg_virt_test(apic_reg_virt_config); 6215 if (config_type == CONFIG_TYPE_UNSUPPORTED) { 6216 printf("Skip because of missing features.\n"); 6217 continue; 6218 } 6219 6220 if (config_type == CONFIG_TYPE_VMENTRY_FAILS_EARLY) { 6221 enter_guest_with_bad_controls(); 6222 continue; 6223 } 6224 6225 for (reg = 0; reg < PAGE_SIZE / sizeof(u32); reg += 0x10) { 6226 struct apic_reg_virt_expectation expectation = {}; 6227 bool ok; 6228 6229 ok = apic_reg_virt_exit_expectation( 6230 reg, apic_reg_virt_config, &expectation); 6231 if (!ok) { 6232 report_fail("Malformed test."); 6233 break; 6234 } 6235 6236 test_xapic_rd(reg, &expectation, apic_access_address, 6237 virtual_apic_page); 6238 test_xapic_wr(reg, &expectation, apic_access_address, 6239 virtual_apic_page); 6240 } 6241 } 6242 6243 /* Terminate the guest */ 6244 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6245 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6246 args->op = TERMINATE; 6247 enter_guest(); 6248 assert_exit_reason(VMX_VMCALL); 6249 } 6250 6251 struct virt_x2apic_mode_config { 6252 struct apic_reg_virt_config apic_reg_virt_config; 6253 bool virtual_interrupt_delivery; 6254 bool use_msr_bitmaps; 6255 bool disable_x2apic_msr_intercepts; 6256 bool disable_x2apic; 6257 }; 6258 6259 struct virt_x2apic_mode_test_case { 6260 const char *name; 6261 struct virt_x2apic_mode_config virt_x2apic_mode_config; 6262 }; 6263 6264 enum Virt_x2apic_mode_behavior_type { 6265 X2APIC_ACCESS_VIRTUALIZED, 6266 X2APIC_ACCESS_PASSED_THROUGH, 6267 X2APIC_ACCESS_TRIGGERS_GP, 6268 }; 6269 6270 struct virt_x2apic_mode_expectation { 6271 enum Reason rd_exit_reason; 6272 enum Reason wr_exit_reason; 6273 6274 /* 6275 * RDMSR and WRMSR handle 64-bit values. However, except for ICR, all of 6276 * the x2APIC registers are 32 bits. Notice: 6277 * 1. vmx_x2apic_read() clears the upper 32 bits for 32-bit registers. 6278 * 2. vmx_x2apic_write() expects the val arg to be well-formed. 6279 */ 6280 u64 rd_val; 6281 u64 wr_val; 6282 6283 /* 6284 * Compares input to virtualized output; 6285 * 1st arg is pointer to return expected virtualization output. 6286 */ 6287 u64 (*virt_fn)(u64); 6288 6289 enum Virt_x2apic_mode_behavior_type rd_behavior; 6290 enum Virt_x2apic_mode_behavior_type wr_behavior; 6291 bool wr_only; 6292 }; 6293 6294 static u64 virt_x2apic_mode_identity(u64 val) 6295 { 6296 return val; 6297 } 6298 6299 static u64 virt_x2apic_mode_nibble1(u64 val) 6300 { 6301 return val & 0xf0; 6302 } 6303 6304 static void virt_x2apic_mode_rd_expectation( 6305 u32 reg, bool virt_x2apic_mode_on, bool disable_x2apic, 6306 bool apic_register_virtualization, bool virtual_interrupt_delivery, 6307 struct virt_x2apic_mode_expectation *expectation) 6308 { 6309 bool readable = 6310 !x2apic_reg_reserved(reg) && 6311 reg != APIC_EOI; 6312 6313 expectation->rd_exit_reason = VMX_VMCALL; 6314 expectation->virt_fn = virt_x2apic_mode_identity; 6315 if (virt_x2apic_mode_on && apic_register_virtualization) { 6316 expectation->rd_val = MAGIC_VAL_1; 6317 if (reg == APIC_PROCPRI && virtual_interrupt_delivery) 6318 expectation->virt_fn = virt_x2apic_mode_nibble1; 6319 else if (reg == APIC_TASKPRI) 6320 expectation->virt_fn = virt_x2apic_mode_nibble1; 6321 expectation->rd_behavior = X2APIC_ACCESS_VIRTUALIZED; 6322 } else if (virt_x2apic_mode_on && !apic_register_virtualization && 6323 reg == APIC_TASKPRI) { 6324 expectation->rd_val = MAGIC_VAL_1; 6325 expectation->virt_fn = virt_x2apic_mode_nibble1; 6326 expectation->rd_behavior = X2APIC_ACCESS_VIRTUALIZED; 6327 } else if (!disable_x2apic && readable) { 6328 expectation->rd_val = apic_read(reg); 6329 expectation->rd_behavior = X2APIC_ACCESS_PASSED_THROUGH; 6330 } else { 6331 expectation->rd_behavior = X2APIC_ACCESS_TRIGGERS_GP; 6332 } 6333 } 6334 6335 /* 6336 * get_x2apic_wr_val() creates an innocuous write value for an x2APIC register. 6337 * 6338 * For writable registers, get_x2apic_wr_val() deposits the write value into the 6339 * val pointer arg and returns true. For non-writable registers, val is not 6340 * modified and get_x2apic_wr_val() returns false. 6341 */ 6342 static bool get_x2apic_wr_val(u32 reg, u64 *val) 6343 { 6344 switch (reg) { 6345 case APIC_TASKPRI: 6346 /* Bits 31:8 are reserved. */ 6347 *val &= 0xff; 6348 break; 6349 case APIC_EOI: 6350 case APIC_ESR: 6351 case APIC_TMICT: 6352 /* 6353 * EOI, ESR: WRMSR of a non-zero value causes #GP(0). 6354 * TMICT: A write of 0 to the initial-count register effectively 6355 * stops the local APIC timer, in both one-shot and 6356 * periodic mode. 6357 */ 6358 *val = 0; 6359 break; 6360 case APIC_SPIV: 6361 case APIC_LVTT: 6362 case APIC_LVTTHMR: 6363 case APIC_LVTPC: 6364 case APIC_LVT0: 6365 case APIC_LVT1: 6366 case APIC_LVTERR: 6367 case APIC_TDCR: 6368 /* 6369 * To avoid writing a 1 to a reserved bit or causing some other 6370 * unintended side effect, read the current value and use it as 6371 * the write value. 6372 */ 6373 *val = apic_read(reg); 6374 break; 6375 case APIC_CMCI: 6376 if (!apic_lvt_entry_supported(6)) 6377 return false; 6378 *val = apic_read(reg); 6379 break; 6380 case APIC_ICR: 6381 *val = 0x40000 | 0xf1; 6382 break; 6383 case APIC_SELF_IPI: 6384 /* 6385 * With special processing (i.e., virtualize x2APIC mode + 6386 * virtual interrupt delivery), writing zero causes an 6387 * APIC-write VM exit. We plan to add a test for enabling 6388 * "virtual-interrupt delivery" in VMCS12, and that's where we 6389 * will test a self IPI with special processing. 6390 */ 6391 *val = 0x0; 6392 break; 6393 default: 6394 return false; 6395 } 6396 6397 return true; 6398 } 6399 6400 static bool special_processing_applies(u32 reg, u64 *val, 6401 bool virt_int_delivery) 6402 { 6403 bool special_processing = 6404 (reg == APIC_TASKPRI) || 6405 (virt_int_delivery && 6406 (reg == APIC_EOI || reg == APIC_SELF_IPI)); 6407 6408 if (special_processing) { 6409 TEST_ASSERT(get_x2apic_wr_val(reg, val)); 6410 return true; 6411 } 6412 6413 return false; 6414 } 6415 6416 static void virt_x2apic_mode_wr_expectation( 6417 u32 reg, bool virt_x2apic_mode_on, bool disable_x2apic, 6418 bool virt_int_delivery, 6419 struct virt_x2apic_mode_expectation *expectation) 6420 { 6421 expectation->wr_exit_reason = VMX_VMCALL; 6422 expectation->wr_val = MAGIC_VAL_1; 6423 expectation->wr_only = false; 6424 6425 if (virt_x2apic_mode_on && 6426 special_processing_applies(reg, &expectation->wr_val, 6427 virt_int_delivery)) { 6428 expectation->wr_behavior = X2APIC_ACCESS_VIRTUALIZED; 6429 if (reg == APIC_SELF_IPI) 6430 expectation->wr_exit_reason = VMX_APIC_WRITE; 6431 } else if (!disable_x2apic && 6432 get_x2apic_wr_val(reg, &expectation->wr_val)) { 6433 expectation->wr_behavior = X2APIC_ACCESS_PASSED_THROUGH; 6434 if (reg == APIC_EOI || reg == APIC_SELF_IPI) 6435 expectation->wr_only = true; 6436 if (reg == APIC_ICR) 6437 expectation->wr_exit_reason = VMX_EXTINT; 6438 } else { 6439 expectation->wr_behavior = X2APIC_ACCESS_TRIGGERS_GP; 6440 /* 6441 * Writing 1 to a reserved bit triggers a #GP. 6442 * Thus, set the write value to 0, which seems 6443 * the most likely to detect a missed #GP. 6444 */ 6445 expectation->wr_val = 0; 6446 } 6447 } 6448 6449 static void virt_x2apic_mode_exit_expectation( 6450 u32 reg, struct virt_x2apic_mode_config *config, 6451 struct virt_x2apic_mode_expectation *expectation) 6452 { 6453 struct apic_reg_virt_config *base_config = 6454 &config->apic_reg_virt_config; 6455 bool virt_x2apic_mode_on = 6456 base_config->virtualize_x2apic_mode && 6457 config->use_msr_bitmaps && 6458 config->disable_x2apic_msr_intercepts && 6459 base_config->activate_secondary_controls; 6460 6461 virt_x2apic_mode_wr_expectation( 6462 reg, virt_x2apic_mode_on, config->disable_x2apic, 6463 config->virtual_interrupt_delivery, expectation); 6464 virt_x2apic_mode_rd_expectation( 6465 reg, virt_x2apic_mode_on, config->disable_x2apic, 6466 base_config->apic_register_virtualization, 6467 config->virtual_interrupt_delivery, expectation); 6468 } 6469 6470 struct virt_x2apic_mode_test_case virt_x2apic_mode_tests[] = { 6471 /* 6472 * Baseline "virtualize x2APIC mode" configuration: 6473 * - virtualize x2APIC mode 6474 * - virtual-interrupt delivery 6475 * - APIC-register virtualization 6476 * - x2APIC MSR intercepts disabled 6477 * 6478 * Reads come from virtual APIC page, special processing applies to 6479 * VTPR, EOI, and SELF IPI, and all other writes pass through to L1 6480 * APIC. 6481 */ 6482 { 6483 .name = "Baseline", 6484 .virt_x2apic_mode_config = { 6485 .virtual_interrupt_delivery = true, 6486 .use_msr_bitmaps = true, 6487 .disable_x2apic_msr_intercepts = true, 6488 .disable_x2apic = false, 6489 .apic_reg_virt_config = { 6490 .apic_register_virtualization = true, 6491 .use_tpr_shadow = true, 6492 .virtualize_apic_accesses = false, 6493 .virtualize_x2apic_mode = true, 6494 .activate_secondary_controls = true, 6495 }, 6496 }, 6497 }, 6498 { 6499 .name = "Baseline w/ x2apic disabled", 6500 .virt_x2apic_mode_config = { 6501 .virtual_interrupt_delivery = true, 6502 .use_msr_bitmaps = true, 6503 .disable_x2apic_msr_intercepts = true, 6504 .disable_x2apic = true, 6505 .apic_reg_virt_config = { 6506 .apic_register_virtualization = true, 6507 .use_tpr_shadow = true, 6508 .virtualize_apic_accesses = false, 6509 .virtualize_x2apic_mode = true, 6510 .activate_secondary_controls = true, 6511 }, 6512 }, 6513 }, 6514 6515 /* 6516 * Baseline, minus virtual-interrupt delivery. Reads come from virtual 6517 * APIC page, special processing applies to VTPR, and all other writes 6518 * pass through to L1 APIC. 6519 */ 6520 { 6521 .name = "Baseline - virtual interrupt delivery", 6522 .virt_x2apic_mode_config = { 6523 .virtual_interrupt_delivery = false, 6524 .use_msr_bitmaps = true, 6525 .disable_x2apic_msr_intercepts = true, 6526 .disable_x2apic = false, 6527 .apic_reg_virt_config = { 6528 .apic_register_virtualization = true, 6529 .use_tpr_shadow = true, 6530 .virtualize_apic_accesses = false, 6531 .virtualize_x2apic_mode = true, 6532 .activate_secondary_controls = true, 6533 }, 6534 }, 6535 }, 6536 6537 /* 6538 * Baseline, minus APIC-register virtualization. x2APIC reads pass 6539 * through to L1's APIC, unless reading VTPR 6540 */ 6541 { 6542 .name = "Virtualize x2APIC mode, no APIC reg virt", 6543 .virt_x2apic_mode_config = { 6544 .virtual_interrupt_delivery = true, 6545 .use_msr_bitmaps = true, 6546 .disable_x2apic_msr_intercepts = true, 6547 .disable_x2apic = false, 6548 .apic_reg_virt_config = { 6549 .apic_register_virtualization = false, 6550 .use_tpr_shadow = true, 6551 .virtualize_apic_accesses = false, 6552 .virtualize_x2apic_mode = true, 6553 .activate_secondary_controls = true, 6554 }, 6555 }, 6556 }, 6557 { 6558 .name = "Virtualize x2APIC mode, no APIC reg virt, x2APIC off", 6559 .virt_x2apic_mode_config = { 6560 .virtual_interrupt_delivery = true, 6561 .use_msr_bitmaps = true, 6562 .disable_x2apic_msr_intercepts = true, 6563 .disable_x2apic = true, 6564 .apic_reg_virt_config = { 6565 .apic_register_virtualization = false, 6566 .use_tpr_shadow = true, 6567 .virtualize_apic_accesses = false, 6568 .virtualize_x2apic_mode = true, 6569 .activate_secondary_controls = true, 6570 }, 6571 }, 6572 }, 6573 6574 /* 6575 * Enable "virtualize x2APIC mode" and "APIC-register virtualization", 6576 * and disable intercepts for the x2APIC MSRs, but fail to enable 6577 * "activate secondary controls" (i.e. L2 gets access to L1's x2APIC 6578 * MSRs). 6579 */ 6580 { 6581 .name = "Fail to enable activate secondary controls", 6582 .virt_x2apic_mode_config = { 6583 .virtual_interrupt_delivery = true, 6584 .use_msr_bitmaps = true, 6585 .disable_x2apic_msr_intercepts = true, 6586 .disable_x2apic = false, 6587 .apic_reg_virt_config = { 6588 .apic_register_virtualization = true, 6589 .use_tpr_shadow = true, 6590 .virtualize_apic_accesses = false, 6591 .virtualize_x2apic_mode = true, 6592 .activate_secondary_controls = false, 6593 }, 6594 }, 6595 }, 6596 6597 /* 6598 * Enable "APIC-register virtualization" and enable "activate secondary 6599 * controls" and disable intercepts for the x2APIC MSRs, but do not 6600 * enable the "virtualize x2APIC mode" VM-execution control (i.e. L2 6601 * gets access to L1's x2APIC MSRs). 6602 */ 6603 { 6604 .name = "Fail to enable virtualize x2APIC mode", 6605 .virt_x2apic_mode_config = { 6606 .virtual_interrupt_delivery = true, 6607 .use_msr_bitmaps = true, 6608 .disable_x2apic_msr_intercepts = true, 6609 .disable_x2apic = false, 6610 .apic_reg_virt_config = { 6611 .apic_register_virtualization = true, 6612 .use_tpr_shadow = true, 6613 .virtualize_apic_accesses = false, 6614 .virtualize_x2apic_mode = false, 6615 .activate_secondary_controls = true, 6616 }, 6617 }, 6618 }, 6619 6620 /* 6621 * Disable "Virtualize x2APIC mode", disable x2APIC MSR intercepts, and 6622 * enable "APIC-register virtualization" --> L2 gets L1's x2APIC MSRs. 6623 */ 6624 { 6625 .name = "Baseline", 6626 .virt_x2apic_mode_config = { 6627 .virtual_interrupt_delivery = true, 6628 .use_msr_bitmaps = true, 6629 .disable_x2apic_msr_intercepts = true, 6630 .disable_x2apic = false, 6631 .apic_reg_virt_config = { 6632 .apic_register_virtualization = true, 6633 .use_tpr_shadow = true, 6634 .virtualize_apic_accesses = false, 6635 .virtualize_x2apic_mode = false, 6636 .activate_secondary_controls = true, 6637 }, 6638 }, 6639 }, 6640 }; 6641 6642 enum X2apic_op { 6643 X2APIC_OP_RD, 6644 X2APIC_OP_WR, 6645 X2APIC_TERMINATE, 6646 }; 6647 6648 static u64 vmx_x2apic_read(u32 reg) 6649 { 6650 u32 msr_addr = x2apic_msr(reg); 6651 u64 val; 6652 6653 val = rdmsr(msr_addr); 6654 6655 return val; 6656 } 6657 6658 static void vmx_x2apic_write(u32 reg, u64 val) 6659 { 6660 u32 msr_addr = x2apic_msr(reg); 6661 6662 wrmsr(msr_addr, val); 6663 } 6664 6665 struct virt_x2apic_mode_guest_args { 6666 enum X2apic_op op; 6667 u32 reg; 6668 u64 val; 6669 bool should_gp; 6670 u64 (*virt_fn)(u64); 6671 } virt_x2apic_mode_guest_args; 6672 6673 static volatile bool handle_x2apic_gp_ran; 6674 static volatile u32 handle_x2apic_gp_insn_len; 6675 static void handle_x2apic_gp(struct ex_regs *regs) 6676 { 6677 handle_x2apic_gp_ran = true; 6678 regs->rip += handle_x2apic_gp_insn_len; 6679 } 6680 6681 static handler setup_x2apic_gp_handler(void) 6682 { 6683 handler old_handler; 6684 6685 old_handler = handle_exception(GP_VECTOR, handle_x2apic_gp); 6686 /* RDMSR and WRMSR are both 2 bytes, assuming no prefixes. */ 6687 handle_x2apic_gp_insn_len = 2; 6688 6689 return old_handler; 6690 } 6691 6692 static void teardown_x2apic_gp_handler(handler old_handler) 6693 { 6694 handle_exception(GP_VECTOR, old_handler); 6695 6696 /* 6697 * Defensively reset instruction length, so that if the handler is 6698 * incorrectly used, it will loop infinitely, rather than run off into 6699 * la la land. 6700 */ 6701 handle_x2apic_gp_insn_len = 0; 6702 handle_x2apic_gp_ran = false; 6703 } 6704 6705 static void virt_x2apic_mode_guest(void) 6706 { 6707 volatile struct virt_x2apic_mode_guest_args *args = 6708 &virt_x2apic_mode_guest_args; 6709 6710 for (;;) { 6711 enum X2apic_op op = args->op; 6712 u32 reg = args->reg; 6713 u64 val = args->val; 6714 bool should_gp = args->should_gp; 6715 u64 (*virt_fn)(u64) = args->virt_fn; 6716 handler old_handler; 6717 6718 if (op == X2APIC_TERMINATE) 6719 break; 6720 6721 if (should_gp) { 6722 TEST_ASSERT(!handle_x2apic_gp_ran); 6723 old_handler = setup_x2apic_gp_handler(); 6724 } 6725 6726 if (op == X2APIC_OP_RD) { 6727 u64 ret = vmx_x2apic_read(reg); 6728 6729 if (!should_gp) { 6730 u64 want = virt_fn(val); 6731 u64 got = virt_fn(ret); 6732 6733 report(got == want, 6734 "APIC read; got 0x%lx, want 0x%lx.", 6735 got, want); 6736 } 6737 } else if (op == X2APIC_OP_WR) { 6738 vmx_x2apic_write(reg, val); 6739 } 6740 6741 if (should_gp) { 6742 report(handle_x2apic_gp_ran, 6743 "x2APIC op triggered GP."); 6744 teardown_x2apic_gp_handler(old_handler); 6745 } 6746 6747 /* 6748 * The L1 should always execute a vmcall after it's done testing 6749 * an individual APIC operation. This helps to validate that the 6750 * L1 and L2 are in sync with each other, as expected. 6751 */ 6752 vmcall(); 6753 } 6754 } 6755 6756 static void test_x2apic_rd( 6757 u32 reg, struct virt_x2apic_mode_expectation *expectation, 6758 u32 *virtual_apic_page) 6759 { 6760 u64 val = expectation->rd_val; 6761 u32 exit_reason_want = expectation->rd_exit_reason; 6762 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6763 6764 report_prefix_pushf("x2apic - reading 0x%03x", reg); 6765 6766 /* Configure guest to do an x2apic read */ 6767 args->op = X2APIC_OP_RD; 6768 args->reg = reg; 6769 args->val = val; 6770 args->should_gp = expectation->rd_behavior == X2APIC_ACCESS_TRIGGERS_GP; 6771 args->virt_fn = expectation->virt_fn; 6772 6773 /* Setup virtual APIC page */ 6774 if (expectation->rd_behavior == X2APIC_ACCESS_VIRTUALIZED) 6775 virtual_apic_page[apic_reg_index(reg)] = (u32)val; 6776 6777 /* Enter guest */ 6778 enter_guest(); 6779 6780 if (exit_reason_want != VMX_VMCALL) { 6781 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 6782 } 6783 6784 skip_exit_vmcall(); 6785 report_prefix_pop(); 6786 } 6787 6788 static volatile bool handle_x2apic_ipi_ran; 6789 static void handle_x2apic_ipi(isr_regs_t *regs) 6790 { 6791 handle_x2apic_ipi_ran = true; 6792 eoi(); 6793 } 6794 6795 static void test_x2apic_wr( 6796 u32 reg, struct virt_x2apic_mode_expectation *expectation, 6797 u32 *virtual_apic_page) 6798 { 6799 u64 val = expectation->wr_val; 6800 u32 exit_reason_want = expectation->wr_exit_reason; 6801 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6802 int ipi_vector = 0xf1; 6803 u32 restore_val = 0; 6804 6805 report_prefix_pushf("x2apic - writing 0x%lx to 0x%03x", val, reg); 6806 6807 /* Configure guest to do an x2apic read */ 6808 args->op = X2APIC_OP_WR; 6809 args->reg = reg; 6810 args->val = val; 6811 args->should_gp = expectation->wr_behavior == X2APIC_ACCESS_TRIGGERS_GP; 6812 6813 /* Setup virtual APIC page */ 6814 if (expectation->wr_behavior == X2APIC_ACCESS_VIRTUALIZED) 6815 virtual_apic_page[apic_reg_index(reg)] = 0; 6816 if (expectation->wr_behavior == X2APIC_ACCESS_PASSED_THROUGH && !expectation->wr_only) 6817 restore_val = apic_read(reg); 6818 6819 /* Setup IPI handler */ 6820 handle_x2apic_ipi_ran = false; 6821 handle_irq(ipi_vector, handle_x2apic_ipi); 6822 6823 /* Enter guest */ 6824 enter_guest(); 6825 6826 /* 6827 * Validate the behavior and 6828 * pass a magic value back to the guest. 6829 */ 6830 if (exit_reason_want == VMX_EXTINT) { 6831 assert_exit_reason(exit_reason_want); 6832 6833 /* Clear the external interrupt. */ 6834 irq_enable(); 6835 asm volatile ("nop"); 6836 irq_disable(); 6837 report(handle_x2apic_ipi_ran, 6838 "Got pending interrupt after IRQ enabled."); 6839 6840 enter_guest(); 6841 } else if (exit_reason_want == VMX_APIC_WRITE) { 6842 assert_exit_reason(exit_reason_want); 6843 report(virtual_apic_page[apic_reg_index(reg)] == val, 6844 "got APIC write exit @ page offset 0x%03x; val is 0x%x, want 0x%lx", 6845 apic_reg_index(reg), 6846 virtual_apic_page[apic_reg_index(reg)], val); 6847 6848 /* Reenter guest so it can consume/check rcx and exit again. */ 6849 enter_guest(); 6850 } else if (exit_reason_want != VMX_VMCALL) { 6851 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 6852 } 6853 6854 assert_exit_reason(VMX_VMCALL); 6855 if (expectation->wr_behavior == X2APIC_ACCESS_VIRTUALIZED) { 6856 u64 want = val; 6857 u32 got = virtual_apic_page[apic_reg_index(reg)]; 6858 6859 report(got == want, "x2APIC write; got 0x%x, want 0x%lx", got, 6860 want); 6861 } else if (expectation->wr_behavior == X2APIC_ACCESS_PASSED_THROUGH) { 6862 if (!expectation->wr_only) { 6863 u32 got = apic_read(reg); 6864 bool ok; 6865 6866 /* 6867 * When L1's TPR is passed through to L2, the lower 6868 * nibble can be lost. For example, if L2 executes 6869 * WRMSR(0x808, 0x78), then, L1 might read 0x70. 6870 * 6871 * Here's how the lower nibble can get lost: 6872 * 1. L2 executes WRMSR(0x808, 0x78). 6873 * 2. L2 exits to L0 with a WRMSR exit. 6874 * 3. L0 emulates WRMSR, by writing L1's TPR. 6875 * 4. L0 re-enters L2. 6876 * 5. L2 exits to L0 (reason doesn't matter). 6877 * 6. L0 reflects L2's exit to L1. 6878 * 7. Before entering L1, L0 exits to user-space 6879 * (e.g., to satisfy TPR access reporting). 6880 * 8. User-space executes KVM_SET_REGS ioctl, which 6881 * clears the lower nibble of L1's TPR. 6882 */ 6883 if (reg == APIC_TASKPRI) { 6884 got = apic_virt_nibble1(got); 6885 val = apic_virt_nibble1(val); 6886 } 6887 6888 ok = got == val; 6889 report(ok, 6890 "non-virtualized write; val is 0x%x, want 0x%lx", 6891 got, val); 6892 apic_write(reg, restore_val); 6893 } else { 6894 report_pass("non-virtualized and write-only OK"); 6895 } 6896 } 6897 skip_exit_insn(); 6898 6899 report_prefix_pop(); 6900 } 6901 6902 static enum Config_type configure_virt_x2apic_mode_test( 6903 struct virt_x2apic_mode_config *virt_x2apic_mode_config, 6904 u8 *msr_bitmap_page) 6905 { 6906 int msr; 6907 u32 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6908 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6909 6910 /* x2apic-specific VMCS config */ 6911 if (virt_x2apic_mode_config->use_msr_bitmaps) { 6912 /* virt_x2apic_mode_test() checks for MSR bitmaps support */ 6913 cpu_exec_ctrl0 |= CPU_MSR_BITMAP; 6914 } else { 6915 cpu_exec_ctrl0 &= ~CPU_MSR_BITMAP; 6916 } 6917 6918 if (virt_x2apic_mode_config->virtual_interrupt_delivery) { 6919 if (!(ctrl_cpu_rev[1].clr & CPU_VINTD)) { 6920 report_skip("VM-execution control \"virtual-interrupt delivery\" NOT supported.\n"); 6921 return CONFIG_TYPE_UNSUPPORTED; 6922 } 6923 cpu_exec_ctrl1 |= CPU_VINTD; 6924 } else { 6925 cpu_exec_ctrl1 &= ~CPU_VINTD; 6926 } 6927 6928 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6929 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6930 6931 /* x2APIC MSR intercepts are usually off for "Virtualize x2APIC mode" */ 6932 for (msr = 0x800; msr <= 0x8ff; msr++) { 6933 if (virt_x2apic_mode_config->disable_x2apic_msr_intercepts) { 6934 clear_bit(msr, msr_bitmap_page + 0x000); 6935 clear_bit(msr, msr_bitmap_page + 0x800); 6936 } else { 6937 set_bit(msr, msr_bitmap_page + 0x000); 6938 set_bit(msr, msr_bitmap_page + 0x800); 6939 } 6940 } 6941 6942 /* x2APIC mode can impact virtualization */ 6943 reset_apic(); 6944 if (!virt_x2apic_mode_config->disable_x2apic) 6945 enable_x2apic(); 6946 6947 return configure_apic_reg_virt_test( 6948 &virt_x2apic_mode_config->apic_reg_virt_config); 6949 } 6950 6951 static void virt_x2apic_mode_test(void) 6952 { 6953 u32 *virtual_apic_page; 6954 u8 *msr_bitmap_page; 6955 u64 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6956 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6957 int i; 6958 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6959 6960 if (!cpu_has_apicv()) { 6961 report_skip(__func__); 6962 return; 6963 } 6964 6965 /* 6966 * This is to exercise an issue in KVM's logic to merge L0's and L1's 6967 * MSR bitmaps. Previously, an L1 could get at L0's x2APIC MSRs by 6968 * writing the IA32_SPEC_CTRL MSR or the IA32_PRED_CMD MSRs. KVM would 6969 * then proceed to manipulate the MSR bitmaps, as if VMCS12 had the 6970 * "Virtualize x2APIC mod" control set, even when it didn't. 6971 */ 6972 if (has_spec_ctrl()) 6973 wrmsr(MSR_IA32_SPEC_CTRL, 1); 6974 6975 /* 6976 * Check that VMCS12 supports: 6977 * - "Virtual-APIC address", indicated by "use TPR shadow" 6978 * - "MSR-bitmap address", indicated by "use MSR bitmaps" 6979 */ 6980 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) { 6981 report_skip("VM-execution control \"use TPR shadow\" NOT supported.\n"); 6982 return; 6983 } else if (!(ctrl_cpu_rev[0].clr & CPU_MSR_BITMAP)) { 6984 report_skip("VM-execution control \"use MSR bitmaps\" NOT supported.\n"); 6985 return; 6986 } 6987 6988 test_set_guest(virt_x2apic_mode_guest); 6989 6990 virtual_apic_page = alloc_page(); 6991 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 6992 6993 msr_bitmap_page = alloc_page(); 6994 memset(msr_bitmap_page, 0xff, PAGE_SIZE); 6995 vmcs_write(MSR_BITMAP, virt_to_phys(msr_bitmap_page)); 6996 6997 for (i = 0; i < ARRAY_SIZE(virt_x2apic_mode_tests); i++) { 6998 struct virt_x2apic_mode_test_case *virt_x2apic_mode_test_case = 6999 &virt_x2apic_mode_tests[i]; 7000 struct virt_x2apic_mode_config *virt_x2apic_mode_config = 7001 &virt_x2apic_mode_test_case->virt_x2apic_mode_config; 7002 enum Config_type config_type; 7003 u32 reg; 7004 7005 printf("--- %s test ---\n", virt_x2apic_mode_test_case->name); 7006 config_type = 7007 configure_virt_x2apic_mode_test(virt_x2apic_mode_config, 7008 msr_bitmap_page); 7009 if (config_type == CONFIG_TYPE_UNSUPPORTED) { 7010 report_skip("Skip because of missing features.\n"); 7011 continue; 7012 } else if (config_type == CONFIG_TYPE_VMENTRY_FAILS_EARLY) { 7013 enter_guest_with_bad_controls(); 7014 continue; 7015 } 7016 7017 for (reg = 0; reg < PAGE_SIZE / sizeof(u32); reg += 0x10) { 7018 struct virt_x2apic_mode_expectation expectation; 7019 7020 virt_x2apic_mode_exit_expectation( 7021 reg, virt_x2apic_mode_config, &expectation); 7022 7023 test_x2apic_rd(reg, &expectation, virtual_apic_page); 7024 test_x2apic_wr(reg, &expectation, virtual_apic_page); 7025 } 7026 } 7027 7028 7029 /* Terminate the guest */ 7030 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 7031 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 7032 args->op = X2APIC_TERMINATE; 7033 enter_guest(); 7034 assert_exit_reason(VMX_VMCALL); 7035 } 7036 7037 static void test_ctl_reg(const char *cr_name, u64 cr, u64 fixed0, u64 fixed1) 7038 { 7039 u64 val; 7040 u64 cr_saved = vmcs_read(cr); 7041 int i; 7042 7043 val = fixed0 & fixed1; 7044 if (cr == HOST_CR4) 7045 vmcs_write(cr, val | X86_CR4_PAE); 7046 else 7047 vmcs_write(cr, val); 7048 report_prefix_pushf("%s %lx", cr_name, val); 7049 if (val == fixed0) 7050 test_vmx_vmlaunch(0); 7051 else 7052 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7053 report_prefix_pop(); 7054 7055 for (i = 0; i < 64; i++) { 7056 7057 /* Set a bit when the corresponding bit in fixed1 is 0 */ 7058 if ((fixed1 & (1ull << i)) == 0) { 7059 if (cr == HOST_CR4 && ((1ull << i) & X86_CR4_SMEP || 7060 (1ull << i) & X86_CR4_SMAP)) 7061 continue; 7062 7063 vmcs_write(cr, cr_saved | (1ull << i)); 7064 report_prefix_pushf("%s %llx", cr_name, 7065 cr_saved | (1ull << i)); 7066 test_vmx_vmlaunch( 7067 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7068 report_prefix_pop(); 7069 } 7070 7071 /* Unset a bit when the corresponding bit in fixed0 is 1 */ 7072 if (fixed0 & (1ull << i)) { 7073 vmcs_write(cr, cr_saved & ~(1ull << i)); 7074 report_prefix_pushf("%s %llx", cr_name, 7075 cr_saved & ~(1ull << i)); 7076 test_vmx_vmlaunch( 7077 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7078 report_prefix_pop(); 7079 } 7080 } 7081 7082 vmcs_write(cr, cr_saved); 7083 } 7084 7085 /* 7086 * 1. The CR0 field must not set any bit to a value not supported in VMX 7087 * operation. 7088 * 2. The CR4 field must not set any bit to a value not supported in VMX 7089 * operation. 7090 * 3. On processors that support Intel 64 architecture, the CR3 field must 7091 * be such that bits 63:52 and bits in the range 51:32 beyond the 7092 * processor's physical-address width must be 0. 7093 * 7094 * [Intel SDM] 7095 */ 7096 static void test_host_ctl_regs(void) 7097 { 7098 u64 fixed0, fixed1, cr3, cr3_saved; 7099 int i; 7100 7101 /* Test CR0 */ 7102 fixed0 = rdmsr(MSR_IA32_VMX_CR0_FIXED0); 7103 fixed1 = rdmsr(MSR_IA32_VMX_CR0_FIXED1); 7104 test_ctl_reg("HOST_CR0", HOST_CR0, fixed0, fixed1); 7105 7106 /* Test CR4 */ 7107 fixed0 = rdmsr(MSR_IA32_VMX_CR4_FIXED0); 7108 fixed1 = rdmsr(MSR_IA32_VMX_CR4_FIXED1) & 7109 ~(X86_CR4_SMEP | X86_CR4_SMAP); 7110 test_ctl_reg("HOST_CR4", HOST_CR4, fixed0, fixed1); 7111 7112 /* Test CR3 */ 7113 cr3_saved = vmcs_read(HOST_CR3); 7114 for (i = cpuid_maxphyaddr(); i < 64; i++) { 7115 cr3 = cr3_saved | (1ul << i); 7116 vmcs_write(HOST_CR3, cr3); 7117 report_prefix_pushf("HOST_CR3 %lx", cr3); 7118 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7119 report_prefix_pop(); 7120 } 7121 7122 vmcs_write(HOST_CR3, cr3_saved); 7123 } 7124 7125 static void test_efer_vmlaunch(u32 fld, bool ok) 7126 { 7127 if (fld == HOST_EFER) { 7128 if (ok) 7129 test_vmx_vmlaunch(0); 7130 else 7131 test_vmx_vmlaunch2(VMXERR_ENTRY_INVALID_CONTROL_FIELD, 7132 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7133 } else { 7134 test_guest_state("EFER test", !ok, GUEST_EFER, "GUEST_EFER"); 7135 } 7136 } 7137 7138 static void test_efer_one(u32 fld, const char * fld_name, u64 efer, 7139 u32 ctrl_fld, u64 ctrl, 7140 int i, const char *efer_bit_name) 7141 { 7142 bool ok; 7143 7144 ok = true; 7145 if (ctrl_fld == EXI_CONTROLS && (ctrl & EXI_LOAD_EFER)) { 7146 if (!!(efer & EFER_LMA) != !!(ctrl & EXI_HOST_64)) 7147 ok = false; 7148 if (!!(efer & EFER_LME) != !!(ctrl & EXI_HOST_64)) 7149 ok = false; 7150 } 7151 if (ctrl_fld == ENT_CONTROLS && (ctrl & ENT_LOAD_EFER)) { 7152 /* Check LMA too since CR0.PG is set. */ 7153 if (!!(efer & EFER_LMA) != !!(ctrl & ENT_GUEST_64)) 7154 ok = false; 7155 if (!!(efer & EFER_LME) != !!(ctrl & ENT_GUEST_64)) 7156 ok = false; 7157 } 7158 7159 /* 7160 * Skip the test if it would enter the guest in 32-bit mode. 7161 * Perhaps write the test in assembly and make sure it 7162 * can be run in either mode? 7163 */ 7164 if (fld == GUEST_EFER && ok && !(ctrl & ENT_GUEST_64)) 7165 return; 7166 7167 vmcs_write(ctrl_fld, ctrl); 7168 vmcs_write(fld, efer); 7169 report_prefix_pushf("%s %s bit turned %s, controls %s", 7170 fld_name, efer_bit_name, 7171 (i & 1) ? "on" : "off", 7172 (i & 2) ? "on" : "off"); 7173 7174 test_efer_vmlaunch(fld, ok); 7175 report_prefix_pop(); 7176 } 7177 7178 static void test_efer_bit(u32 fld, const char * fld_name, 7179 u32 ctrl_fld, u64 ctrl_bit, u64 efer_bit, 7180 const char *efer_bit_name) 7181 { 7182 u64 efer_saved = vmcs_read(fld); 7183 u32 ctrl_saved = vmcs_read(ctrl_fld); 7184 int i; 7185 7186 for (i = 0; i < 4; i++) { 7187 u64 efer = efer_saved & ~efer_bit; 7188 u64 ctrl = ctrl_saved & ~ctrl_bit; 7189 7190 if (i & 1) 7191 efer |= efer_bit; 7192 if (i & 2) 7193 ctrl |= ctrl_bit; 7194 7195 test_efer_one(fld, fld_name, efer, ctrl_fld, ctrl, 7196 i, efer_bit_name); 7197 } 7198 7199 vmcs_write(ctrl_fld, ctrl_saved); 7200 vmcs_write(fld, efer_saved); 7201 } 7202 7203 static void test_efer(u32 fld, const char * fld_name, u32 ctrl_fld, 7204 u64 ctrl_bit1, u64 ctrl_bit2) 7205 { 7206 u64 efer_saved = vmcs_read(fld); 7207 u32 ctrl_saved = vmcs_read(ctrl_fld); 7208 u64 efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 7209 u64 i; 7210 u64 efer; 7211 7212 if (cpu_has_efer_nx()) 7213 efer_reserved_bits &= ~EFER_NX; 7214 7215 if (!ctrl_bit1) { 7216 printf("\"Load-IA32-EFER\" exit control not supported\n"); 7217 goto test_entry_exit_mode; 7218 } 7219 7220 report_prefix_pushf("%s %lx", fld_name, efer_saved); 7221 test_efer_vmlaunch(fld, true); 7222 report_prefix_pop(); 7223 7224 /* 7225 * Check reserved bits 7226 */ 7227 vmcs_write(ctrl_fld, ctrl_saved & ~ctrl_bit1); 7228 for (i = 0; i < 64; i++) { 7229 if ((1ull << i) & efer_reserved_bits) { 7230 efer = efer_saved | (1ull << i); 7231 vmcs_write(fld, efer); 7232 report_prefix_pushf("%s %lx", fld_name, efer); 7233 test_efer_vmlaunch(fld, true); 7234 report_prefix_pop(); 7235 } 7236 } 7237 7238 vmcs_write(ctrl_fld, ctrl_saved | ctrl_bit1); 7239 for (i = 0; i < 64; i++) { 7240 if ((1ull << i) & efer_reserved_bits) { 7241 efer = efer_saved | (1ull << i); 7242 vmcs_write(fld, efer); 7243 report_prefix_pushf("%s %lx", fld_name, efer); 7244 test_efer_vmlaunch(fld, false); 7245 report_prefix_pop(); 7246 } 7247 } 7248 7249 vmcs_write(ctrl_fld, ctrl_saved); 7250 vmcs_write(fld, efer_saved); 7251 7252 /* 7253 * Check LMA and LME bits 7254 */ 7255 test_efer_bit(fld, fld_name, 7256 ctrl_fld, ctrl_bit1, 7257 EFER_LMA, 7258 "EFER_LMA"); 7259 test_efer_bit(fld, fld_name, 7260 ctrl_fld, ctrl_bit1, 7261 EFER_LME, 7262 "EFER_LME"); 7263 7264 test_entry_exit_mode: 7265 test_efer_bit(fld, fld_name, 7266 ctrl_fld, ctrl_bit2, 7267 EFER_LMA, 7268 "EFER_LMA"); 7269 test_efer_bit(fld, fld_name, 7270 ctrl_fld, ctrl_bit2, 7271 EFER_LME, 7272 "EFER_LME"); 7273 } 7274 7275 /* 7276 * If the 'load IA32_EFER' VM-exit control is 1, bits reserved in the 7277 * IA32_EFER MSR must be 0 in the field for that register. In addition, 7278 * the values of the LMA and LME bits in the field must each be that of 7279 * the 'host address-space size' VM-exit control. 7280 * 7281 * [Intel SDM] 7282 */ 7283 static void test_host_efer(void) 7284 { 7285 test_efer(HOST_EFER, "HOST_EFER", EXI_CONTROLS, 7286 ctrl_exit_rev.clr & EXI_LOAD_EFER, 7287 EXI_HOST_64); 7288 } 7289 7290 /* 7291 * If the 'load IA32_EFER' VM-enter control is 1, bits reserved in the 7292 * IA32_EFER MSR must be 0 in the field for that register. In addition, 7293 * the values of the LMA and LME bits in the field must each be that of 7294 * the 'IA32e-mode guest' VM-exit control. 7295 */ 7296 static void test_guest_efer(void) 7297 { 7298 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) { 7299 printf("\"Load-IA32-EFER\" entry control not supported\n"); 7300 return; 7301 } 7302 7303 vmcs_write(GUEST_EFER, rdmsr(MSR_EFER)); 7304 test_efer(GUEST_EFER, "GUEST_EFER", ENT_CONTROLS, 7305 ctrl_enter_rev.clr & ENT_LOAD_EFER, 7306 ENT_GUEST_64); 7307 } 7308 7309 /* 7310 * PAT values higher than 8 are uninteresting since they're likely lumped 7311 * in with "8". We only test values above 8 one bit at a time, 7312 * in order to reduce the number of VM-Entries and keep the runtime reasonable. 7313 */ 7314 #define PAT_VAL_LIMIT 8 7315 7316 static void test_pat(u32 field, const char * field_name, u32 ctrl_field, 7317 u64 ctrl_bit) 7318 { 7319 u32 ctrl_saved = vmcs_read(ctrl_field); 7320 u64 pat_saved = vmcs_read(field); 7321 u64 i, val; 7322 u32 j; 7323 int error; 7324 7325 vmcs_clear_bits(ctrl_field, ctrl_bit); 7326 7327 for (i = 0; i < 256; i = (i < PAT_VAL_LIMIT) ? i + 1 : i * 2) { 7328 /* Test PAT0..PAT7 fields */ 7329 for (j = 0; j < (i ? 8 : 1); j++) { 7330 val = i << j * 8; 7331 vmcs_write(field, val); 7332 if (field == HOST_PAT) { 7333 report_prefix_pushf("%s %lx", field_name, val); 7334 test_vmx_vmlaunch(0); 7335 report_prefix_pop(); 7336 7337 } else { // GUEST_PAT 7338 test_guest_state("ENT_LOAD_PAT enabled", false, 7339 val, "GUEST_PAT"); 7340 } 7341 } 7342 } 7343 7344 vmcs_set_bits(ctrl_field, ctrl_bit); 7345 for (i = 0; i < 256; i = (i < PAT_VAL_LIMIT) ? i + 1 : i * 2) { 7346 /* Test PAT0..PAT7 fields */ 7347 for (j = 0; j < (i ? 8 : 1); j++) { 7348 val = i << j * 8; 7349 vmcs_write(field, val); 7350 7351 if (field == HOST_PAT) { 7352 report_prefix_pushf("%s %lx", field_name, val); 7353 if (i == 0x2 || i == 0x3 || i >= 0x8) 7354 error = 7355 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD; 7356 else 7357 error = 0; 7358 7359 test_vmx_vmlaunch(error); 7360 report_prefix_pop(); 7361 7362 } else { // GUEST_PAT 7363 error = (i == 0x2 || i == 0x3 || i >= 0x8); 7364 test_guest_state("ENT_LOAD_PAT enabled", !!error, 7365 val, "GUEST_PAT"); 7366 } 7367 7368 } 7369 } 7370 7371 vmcs_write(ctrl_field, ctrl_saved); 7372 vmcs_write(field, pat_saved); 7373 } 7374 7375 /* 7376 * If the "load IA32_PAT" VM-exit control is 1, the value of the field 7377 * for the IA32_PAT MSR must be one that could be written by WRMSR 7378 * without fault at CPL 0. Specifically, each of the 8 bytes in the 7379 * field must have one of the values 0 (UC), 1 (WC), 4 (WT), 5 (WP), 7380 * 6 (WB), or 7 (UC-). 7381 * 7382 * [Intel SDM] 7383 */ 7384 static void test_load_host_pat(void) 7385 { 7386 /* 7387 * "load IA32_PAT" VM-exit control 7388 */ 7389 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) { 7390 printf("\"Load-IA32-PAT\" exit control not supported\n"); 7391 return; 7392 } 7393 7394 test_pat(HOST_PAT, "HOST_PAT", EXI_CONTROLS, EXI_LOAD_PAT); 7395 } 7396 7397 union cpuidA_eax { 7398 struct { 7399 unsigned int version_id:8; 7400 unsigned int num_counters_gp:8; 7401 unsigned int bit_width:8; 7402 unsigned int mask_length:8; 7403 } split; 7404 unsigned int full; 7405 }; 7406 7407 union cpuidA_edx { 7408 struct { 7409 unsigned int num_counters_fixed:5; 7410 unsigned int bit_width_fixed:8; 7411 unsigned int reserved:9; 7412 } split; 7413 unsigned int full; 7414 }; 7415 7416 static bool valid_pgc(u64 val) 7417 { 7418 struct cpuid id; 7419 union cpuidA_eax eax; 7420 union cpuidA_edx edx; 7421 u64 mask; 7422 7423 id = cpuid(0xA); 7424 eax.full = id.a; 7425 edx.full = id.d; 7426 mask = ~(((1ull << eax.split.num_counters_gp) - 1) | 7427 (((1ull << edx.split.num_counters_fixed) - 1) << 32)); 7428 7429 return !(val & mask); 7430 } 7431 7432 static void test_pgc_vmlaunch(u32 xerror, u32 xreason, bool xfail, bool host) 7433 { 7434 u32 inst_err; 7435 u64 obs; 7436 bool success; 7437 struct vmx_state_area_test_data *data = &vmx_state_area_test_data; 7438 7439 if (host) { 7440 success = vmlaunch_succeeds(); 7441 obs = rdmsr(data->msr); 7442 if (!success) { 7443 inst_err = vmcs_read(VMX_INST_ERROR); 7444 report(xerror == inst_err, "vmlaunch failed, " 7445 "VMX Inst Error is %d (expected %d)", 7446 inst_err, xerror); 7447 } else { 7448 report(!data->enabled || data->exp == obs, 7449 "Host state is 0x%lx (expected 0x%lx)", 7450 obs, data->exp); 7451 report(success != xfail, "vmlaunch succeeded"); 7452 } 7453 } else { 7454 test_guest_state("load GUEST_PERF_GLOBAL_CTRL", xfail, 7455 GUEST_PERF_GLOBAL_CTRL, 7456 "GUEST_PERF_GLOBAL_CTRL"); 7457 } 7458 } 7459 7460 /* 7461 * test_load_perf_global_ctrl is a generic function for testing the 7462 * "load IA32_PERF_GLOBAL_CTRL" VM-{Entry,Exit} controls. This test function 7463 * tests the provided ctrl_val when disabled and enabled. 7464 * 7465 * @nr: VMCS field number corresponding to the host/guest state field 7466 * @name: Name of the above VMCS field for printing in test report 7467 * @ctrl_nr: VMCS field number corresponding to the VM-{Entry,Exit} control 7468 * @ctrl_val: Bit to set on the ctrl_field 7469 */ 7470 static void test_perf_global_ctrl(u32 nr, const char *name, u32 ctrl_nr, 7471 const char *ctrl_name, u64 ctrl_val) 7472 { 7473 u64 ctrl_saved = vmcs_read(ctrl_nr); 7474 u64 pgc_saved = vmcs_read(nr); 7475 u64 i, val; 7476 bool host = nr == HOST_PERF_GLOBAL_CTRL; 7477 struct vmx_state_area_test_data *data = &vmx_state_area_test_data; 7478 7479 data->msr = MSR_CORE_PERF_GLOBAL_CTRL; 7480 msr_bmp_init(); 7481 vmcs_write(ctrl_nr, ctrl_saved & ~ctrl_val); 7482 data->enabled = false; 7483 report_prefix_pushf("\"load IA32_PERF_GLOBAL_CTRL\"=0 on %s", 7484 ctrl_name); 7485 7486 for (i = 0; i < 64; i++) { 7487 val = 1ull << i; 7488 vmcs_write(nr, val); 7489 report_prefix_pushf("%s = 0x%lx", name, val); 7490 test_pgc_vmlaunch(0, VMX_VMCALL, false, host); 7491 report_prefix_pop(); 7492 } 7493 report_prefix_pop(); 7494 7495 vmcs_write(ctrl_nr, ctrl_saved | ctrl_val); 7496 data->enabled = true; 7497 report_prefix_pushf("\"load IA32_PERF_GLOBAL_CTRL\"=1 on %s", 7498 ctrl_name); 7499 for (i = 0; i < 64; i++) { 7500 val = 1ull << i; 7501 data->exp = val; 7502 vmcs_write(nr, val); 7503 report_prefix_pushf("%s = 0x%lx", name, val); 7504 if (valid_pgc(val)) { 7505 test_pgc_vmlaunch(0, VMX_VMCALL, false, host); 7506 } else { 7507 if (host) 7508 test_pgc_vmlaunch( 7509 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, 7510 0, 7511 true, 7512 host); 7513 else 7514 test_pgc_vmlaunch( 7515 0, 7516 VMX_ENTRY_FAILURE | VMX_FAIL_STATE, 7517 true, 7518 host); 7519 } 7520 report_prefix_pop(); 7521 } 7522 7523 data->enabled = false; 7524 report_prefix_pop(); 7525 vmcs_write(ctrl_nr, ctrl_saved); 7526 vmcs_write(nr, pgc_saved); 7527 } 7528 7529 static void test_load_host_perf_global_ctrl(void) 7530 { 7531 if (!(ctrl_exit_rev.clr & EXI_LOAD_PERF)) { 7532 printf("\"load IA32_PERF_GLOBAL_CTRL\" exit control not supported\n"); 7533 return; 7534 } 7535 7536 test_perf_global_ctrl(HOST_PERF_GLOBAL_CTRL, "HOST_PERF_GLOBAL_CTRL", 7537 EXI_CONTROLS, "EXI_CONTROLS", EXI_LOAD_PERF); 7538 } 7539 7540 7541 static void test_load_guest_perf_global_ctrl(void) 7542 { 7543 if (!(ctrl_enter_rev.clr & ENT_LOAD_PERF)) { 7544 printf("\"load IA32_PERF_GLOBAL_CTRL\" entry control not supported\n"); 7545 return; 7546 } 7547 7548 test_perf_global_ctrl(GUEST_PERF_GLOBAL_CTRL, "GUEST_PERF_GLOBAL_CTRL", 7549 ENT_CONTROLS, "ENT_CONTROLS", ENT_LOAD_PERF); 7550 } 7551 7552 7553 /* 7554 * test_vmcs_field - test a value for the given VMCS field 7555 * @field: VMCS field 7556 * @field_name: string name of VMCS field 7557 * @bit_start: starting bit 7558 * @bit_end: ending bit 7559 * @val: value that the bit range must or must not contain 7560 * @valid_val: whether value given in 'val' must be valid or not 7561 * @error: expected VMCS error when vmentry fails for an invalid value 7562 */ 7563 static void test_vmcs_field(u64 field, const char *field_name, u32 bit_start, 7564 u32 bit_end, u64 val, bool valid_val, u32 error) 7565 { 7566 u64 field_saved = vmcs_read(field); 7567 u32 i; 7568 u64 tmp; 7569 u32 bit_on; 7570 u64 mask = ~0ull; 7571 7572 mask = (mask >> bit_end) << bit_end; 7573 mask = mask | ((1 << bit_start) - 1); 7574 tmp = (field_saved & mask) | (val << bit_start); 7575 7576 vmcs_write(field, tmp); 7577 report_prefix_pushf("%s %lx", field_name, tmp); 7578 if (valid_val) 7579 test_vmx_vmlaunch(0); 7580 else 7581 test_vmx_vmlaunch(error); 7582 report_prefix_pop(); 7583 7584 for (i = bit_start; i <= bit_end; i = i + 2) { 7585 bit_on = ((1ull < i) & (val << bit_start)) ? 0 : 1; 7586 if (bit_on) 7587 tmp = field_saved | (1ull << i); 7588 else 7589 tmp = field_saved & ~(1ull << i); 7590 vmcs_write(field, tmp); 7591 report_prefix_pushf("%s %lx", field_name, tmp); 7592 if (valid_val) 7593 test_vmx_vmlaunch(error); 7594 else 7595 test_vmx_vmlaunch(0); 7596 report_prefix_pop(); 7597 } 7598 7599 vmcs_write(field, field_saved); 7600 } 7601 7602 static void test_canonical(u64 field, const char * field_name, bool host) 7603 { 7604 u64 addr_saved = vmcs_read(field); 7605 7606 /* 7607 * Use the existing value if possible. Writing a random canonical 7608 * value is not an option as doing so would corrupt the field being 7609 * tested and likely hose the test. 7610 */ 7611 if (is_canonical(addr_saved)) { 7612 if (host) { 7613 report_prefix_pushf("%s %lx", field_name, addr_saved); 7614 test_vmx_vmlaunch(0); 7615 report_prefix_pop(); 7616 } else { 7617 test_guest_state("Test canonical address", false, 7618 addr_saved, field_name); 7619 } 7620 } 7621 7622 vmcs_write(field, NONCANONICAL); 7623 7624 if (host) { 7625 report_prefix_pushf("%s %llx", field_name, NONCANONICAL); 7626 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7627 report_prefix_pop(); 7628 } else { 7629 test_guest_state("Test non-canonical address", true, 7630 NONCANONICAL, field_name); 7631 } 7632 7633 vmcs_write(field, addr_saved); 7634 } 7635 7636 #define TEST_RPL_TI_FLAGS(reg, name) \ 7637 test_vmcs_field(reg, name, 0, 2, 0x0, true, \ 7638 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7639 7640 #define TEST_CS_TR_FLAGS(reg, name) \ 7641 test_vmcs_field(reg, name, 3, 15, 0x0000, false, \ 7642 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7643 7644 /* 7645 * 1. In the selector field for each of CS, SS, DS, ES, FS, GS and TR, the 7646 * RPL (bits 1:0) and the TI flag (bit 2) must be 0. 7647 * 2. The selector fields for CS and TR cannot be 0000H. 7648 * 3. The selector field for SS cannot be 0000H if the "host address-space 7649 * size" VM-exit control is 0. 7650 * 4. On processors that support Intel 64 architecture, the base-address 7651 * fields for FS, GS and TR must contain canonical addresses. 7652 */ 7653 static void test_host_segment_regs(void) 7654 { 7655 u16 selector_saved; 7656 7657 /* 7658 * Test RPL and TI flags 7659 */ 7660 TEST_RPL_TI_FLAGS(HOST_SEL_CS, "HOST_SEL_CS"); 7661 TEST_RPL_TI_FLAGS(HOST_SEL_SS, "HOST_SEL_SS"); 7662 TEST_RPL_TI_FLAGS(HOST_SEL_DS, "HOST_SEL_DS"); 7663 TEST_RPL_TI_FLAGS(HOST_SEL_ES, "HOST_SEL_ES"); 7664 TEST_RPL_TI_FLAGS(HOST_SEL_FS, "HOST_SEL_FS"); 7665 TEST_RPL_TI_FLAGS(HOST_SEL_GS, "HOST_SEL_GS"); 7666 TEST_RPL_TI_FLAGS(HOST_SEL_TR, "HOST_SEL_TR"); 7667 7668 /* 7669 * Test that CS and TR fields can not be 0x0000 7670 */ 7671 TEST_CS_TR_FLAGS(HOST_SEL_CS, "HOST_SEL_CS"); 7672 TEST_CS_TR_FLAGS(HOST_SEL_TR, "HOST_SEL_TR"); 7673 7674 /* 7675 * SS field can not be 0x0000 if "host address-space size" VM-exit 7676 * control is 0 7677 */ 7678 selector_saved = vmcs_read(HOST_SEL_SS); 7679 vmcs_write(HOST_SEL_SS, 0); 7680 report_prefix_pushf("HOST_SEL_SS 0"); 7681 if (vmcs_read(EXI_CONTROLS) & EXI_HOST_64) { 7682 test_vmx_vmlaunch(0); 7683 } else { 7684 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7685 } 7686 report_prefix_pop(); 7687 7688 vmcs_write(HOST_SEL_SS, selector_saved); 7689 7690 /* 7691 * Base address for FS, GS and TR must be canonical 7692 */ 7693 test_canonical(HOST_BASE_FS, "HOST_BASE_FS", true); 7694 test_canonical(HOST_BASE_GS, "HOST_BASE_GS", true); 7695 test_canonical(HOST_BASE_TR, "HOST_BASE_TR", true); 7696 } 7697 7698 /* 7699 * On processors that support Intel 64 architecture, the base-address 7700 * fields for GDTR and IDTR must contain canonical addresses. 7701 */ 7702 static void test_host_desc_tables(void) 7703 { 7704 test_canonical(HOST_BASE_GDTR, "HOST_BASE_GDTR", true); 7705 test_canonical(HOST_BASE_IDTR, "HOST_BASE_IDTR", true); 7706 } 7707 7708 /* 7709 * If the "host address-space size" VM-exit control is 0, the following must 7710 * hold: 7711 * - The "IA-32e mode guest" VM-entry control is 0. 7712 * - Bit 17 of the CR4 field (corresponding to CR4.PCIDE) is 0. 7713 * - Bits 63:32 in the RIP field are 0. 7714 * 7715 * If the "host address-space size" VM-exit control is 1, the following must 7716 * hold: 7717 * - Bit 5 of the CR4 field (corresponding to CR4.PAE) is 1. 7718 * - The RIP field contains a canonical address. 7719 * 7720 */ 7721 static void test_host_addr_size(void) 7722 { 7723 u64 cr4_saved = vmcs_read(HOST_CR4); 7724 u64 rip_saved = vmcs_read(HOST_RIP); 7725 u64 entry_ctrl_saved = vmcs_read(ENT_CONTROLS); 7726 int i; 7727 u64 tmp; 7728 7729 if (vmcs_read(EXI_CONTROLS) & EXI_HOST_64) { 7730 vmcs_write(ENT_CONTROLS, entry_ctrl_saved | ENT_GUEST_64); 7731 report_prefix_pushf("\"IA-32e mode guest\" enabled"); 7732 test_vmx_vmlaunch(0); 7733 report_prefix_pop(); 7734 7735 vmcs_write(HOST_CR4, cr4_saved | X86_CR4_PCIDE); 7736 report_prefix_pushf("\"CR4.PCIDE\" set"); 7737 test_vmx_vmlaunch(0); 7738 report_prefix_pop(); 7739 7740 for (i = 32; i <= 63; i = i + 4) { 7741 tmp = rip_saved | 1ull << i; 7742 vmcs_write(HOST_RIP, tmp); 7743 report_prefix_pushf("HOST_RIP %lx", tmp); 7744 test_vmx_vmlaunch(0); 7745 report_prefix_pop(); 7746 } 7747 7748 if (cr4_saved & X86_CR4_PAE) { 7749 vmcs_write(HOST_CR4, cr4_saved & ~X86_CR4_PAE); 7750 report_prefix_pushf("\"CR4.PAE\" unset"); 7751 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7752 } else { 7753 report_prefix_pushf("\"CR4.PAE\" set"); 7754 test_vmx_vmlaunch(0); 7755 } 7756 report_prefix_pop(); 7757 7758 vmcs_write(HOST_RIP, NONCANONICAL); 7759 report_prefix_pushf("HOST_RIP %llx", NONCANONICAL); 7760 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7761 report_prefix_pop(); 7762 7763 vmcs_write(ENT_CONTROLS, entry_ctrl_saved | ENT_GUEST_64); 7764 vmcs_write(HOST_RIP, rip_saved); 7765 vmcs_write(HOST_CR4, cr4_saved); 7766 7767 /* Restore host's active RIP and CR4 values. */ 7768 report_prefix_pushf("restore host state"); 7769 test_vmx_vmlaunch(0); 7770 report_prefix_pop(); 7771 } 7772 } 7773 7774 /* 7775 * Check that the virtual CPU checks the VMX Host State Area as 7776 * documented in the Intel SDM. 7777 */ 7778 static void vmx_host_state_area_test(void) 7779 { 7780 /* 7781 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 7782 * fail due to invalid guest state, should we make it that 7783 * far. 7784 */ 7785 vmcs_write(GUEST_RFLAGS, 0); 7786 7787 test_host_ctl_regs(); 7788 7789 test_canonical(HOST_SYSENTER_ESP, "HOST_SYSENTER_ESP", true); 7790 test_canonical(HOST_SYSENTER_EIP, "HOST_SYSENTER_EIP", true); 7791 7792 test_host_efer(); 7793 test_load_host_pat(); 7794 test_host_segment_regs(); 7795 test_host_desc_tables(); 7796 test_host_addr_size(); 7797 test_load_host_perf_global_ctrl(); 7798 } 7799 7800 /* 7801 * If the "load debug controls" VM-entry control is 1, bits 63:32 in 7802 * the DR7 field must be 0. 7803 * 7804 * [Intel SDM] 7805 */ 7806 static void test_guest_dr7(void) 7807 { 7808 u32 ent_saved = vmcs_read(ENT_CONTROLS); 7809 u64 dr7_saved = vmcs_read(GUEST_DR7); 7810 u64 val; 7811 int i; 7812 7813 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS) { 7814 vmcs_clear_bits(ENT_CONTROLS, ENT_LOAD_DBGCTLS); 7815 for (i = 0; i < 64; i++) { 7816 val = 1ull << i; 7817 vmcs_write(GUEST_DR7, val); 7818 test_guest_state("ENT_LOAD_DBGCTLS disabled", false, 7819 val, "GUEST_DR7"); 7820 } 7821 } 7822 if (ctrl_enter_rev.clr & ENT_LOAD_DBGCTLS) { 7823 vmcs_set_bits(ENT_CONTROLS, ENT_LOAD_DBGCTLS); 7824 for (i = 0; i < 64; i++) { 7825 val = 1ull << i; 7826 vmcs_write(GUEST_DR7, val); 7827 test_guest_state("ENT_LOAD_DBGCTLS enabled", i >= 32, 7828 val, "GUEST_DR7"); 7829 } 7830 } 7831 vmcs_write(GUEST_DR7, dr7_saved); 7832 vmcs_write(ENT_CONTROLS, ent_saved); 7833 } 7834 7835 /* 7836 * If the "load IA32_PAT" VM-entry control is 1, the value of the field 7837 * for the IA32_PAT MSR must be one that could be written by WRMSR 7838 * without fault at CPL 0. Specifically, each of the 8 bytes in the 7839 * field must have one of the values 0 (UC), 1 (WC), 4 (WT), 5 (WP), 7840 * 6 (WB), or 7 (UC-). 7841 * 7842 * [Intel SDM] 7843 */ 7844 static void test_load_guest_pat(void) 7845 { 7846 /* 7847 * "load IA32_PAT" VM-entry control 7848 */ 7849 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 7850 printf("\"Load-IA32-PAT\" entry control not supported\n"); 7851 return; 7852 } 7853 7854 test_pat(GUEST_PAT, "GUEST_PAT", ENT_CONTROLS, ENT_LOAD_PAT); 7855 } 7856 7857 #define MSR_IA32_BNDCFGS_RSVD_MASK 0x00000ffc 7858 7859 /* 7860 * If the "load IA32_BNDCFGS" VM-entry control is 1, the following 7861 * checks are performed on the field for the IA32_BNDCFGS MSR: 7862 * 7863 * - Bits reserved in the IA32_BNDCFGS MSR must be 0. 7864 * - The linear address in bits 63:12 must be canonical. 7865 * 7866 * [Intel SDM] 7867 */ 7868 static void test_load_guest_bndcfgs(void) 7869 { 7870 u64 bndcfgs_saved = vmcs_read(GUEST_BNDCFGS); 7871 u64 bndcfgs; 7872 7873 if (!(ctrl_enter_rev.clr & ENT_LOAD_BNDCFGS)) { 7874 printf("\"Load-IA32-BNDCFGS\" entry control not supported\n"); 7875 return; 7876 } 7877 7878 vmcs_clear_bits(ENT_CONTROLS, ENT_LOAD_BNDCFGS); 7879 7880 vmcs_write(GUEST_BNDCFGS, NONCANONICAL); 7881 test_guest_state("ENT_LOAD_BNDCFGS disabled", false, 7882 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7883 bndcfgs = bndcfgs_saved | MSR_IA32_BNDCFGS_RSVD_MASK; 7884 vmcs_write(GUEST_BNDCFGS, bndcfgs); 7885 test_guest_state("ENT_LOAD_BNDCFGS disabled", false, 7886 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7887 7888 vmcs_set_bits(ENT_CONTROLS, ENT_LOAD_BNDCFGS); 7889 7890 vmcs_write(GUEST_BNDCFGS, NONCANONICAL); 7891 test_guest_state("ENT_LOAD_BNDCFGS enabled", true, 7892 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7893 bndcfgs = bndcfgs_saved | MSR_IA32_BNDCFGS_RSVD_MASK; 7894 vmcs_write(GUEST_BNDCFGS, bndcfgs); 7895 test_guest_state("ENT_LOAD_BNDCFGS enabled", true, 7896 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7897 7898 vmcs_write(GUEST_BNDCFGS, bndcfgs_saved); 7899 } 7900 7901 #define GUEST_SEG_UNUSABLE_MASK (1u << 16) 7902 #define GUEST_SEG_SEL_TI_MASK (1u << 2) 7903 7904 7905 #define TEST_SEGMENT_SEL(test, xfail, sel, val) \ 7906 do { \ 7907 vmcs_write(sel, val); \ 7908 test_guest_state(test " segment", xfail, val, xstr(sel)); \ 7909 } while (0) 7910 7911 #define TEST_INVALID_SEG_SEL(sel, val) \ 7912 TEST_SEGMENT_SEL("Invalid: " xstr(val), true, sel, val); 7913 7914 #define TEST_VALID_SEG_SEL(sel, val) \ 7915 TEST_SEGMENT_SEL("Valid: " xstr(val), false, sel, val); 7916 7917 /* 7918 * The following checks are done on the Selector field of the Guest Segment 7919 * Registers: 7920 * - TR. The TI flag (bit 2) must be 0. 7921 * - LDTR. If LDTR is usable, the TI flag (bit 2) must be 0. 7922 * - SS. If the guest will not be virtual-8086 and the "unrestricted 7923 * guest" VM-execution control is 0, the RPL (bits 1:0) must equal 7924 * the RPL of the selector field for CS. 7925 * 7926 * [Intel SDM] 7927 */ 7928 static void test_guest_segment_sel_fields(void) 7929 { 7930 u16 sel_saved; 7931 u32 ar_saved; 7932 u32 cpu_ctrl0_saved; 7933 u32 cpu_ctrl1_saved; 7934 u16 cs_rpl_bits; 7935 7936 /* 7937 * Test for GUEST_SEL_TR 7938 */ 7939 sel_saved = vmcs_read(GUEST_SEL_TR); 7940 TEST_INVALID_SEG_SEL(GUEST_SEL_TR, sel_saved | GUEST_SEG_SEL_TI_MASK); 7941 vmcs_write(GUEST_SEL_TR, sel_saved); 7942 7943 /* 7944 * Test for GUEST_SEL_LDTR 7945 */ 7946 sel_saved = vmcs_read(GUEST_SEL_LDTR); 7947 ar_saved = vmcs_read(GUEST_AR_LDTR); 7948 /* LDTR is set unusable */ 7949 vmcs_write(GUEST_AR_LDTR, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7950 TEST_VALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved | GUEST_SEG_SEL_TI_MASK); 7951 TEST_VALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved & ~GUEST_SEG_SEL_TI_MASK); 7952 /* LDTR is set usable */ 7953 vmcs_write(GUEST_AR_LDTR, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7954 TEST_INVALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved | GUEST_SEG_SEL_TI_MASK); 7955 7956 TEST_VALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved & ~GUEST_SEG_SEL_TI_MASK); 7957 7958 vmcs_write(GUEST_AR_LDTR, ar_saved); 7959 vmcs_write(GUEST_SEL_LDTR, sel_saved); 7960 7961 /* 7962 * Test for GUEST_SEL_SS 7963 */ 7964 cpu_ctrl0_saved = vmcs_read(CPU_EXEC_CTRL0); 7965 cpu_ctrl1_saved = vmcs_read(CPU_EXEC_CTRL1); 7966 ar_saved = vmcs_read(GUEST_AR_SS); 7967 /* Turn off "unrestricted guest" vm-execution control */ 7968 vmcs_write(CPU_EXEC_CTRL1, cpu_ctrl1_saved & ~CPU_URG); 7969 cs_rpl_bits = vmcs_read(GUEST_SEL_CS) & 0x3; 7970 sel_saved = vmcs_read(GUEST_SEL_SS); 7971 TEST_INVALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 7972 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 7973 /* Make SS usable if it's unusable or vice-versa */ 7974 if (ar_saved & GUEST_SEG_UNUSABLE_MASK) 7975 vmcs_write(GUEST_AR_SS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7976 else 7977 vmcs_write(GUEST_AR_SS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7978 TEST_INVALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 7979 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 7980 7981 /* Need a valid EPTP as the passing case fully enters the guest. */ 7982 if (enable_unrestricted_guest(true)) 7983 goto skip_ss_tests; 7984 7985 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 7986 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 7987 7988 /* Make SS usable if it's unusable or vice-versa */ 7989 if (vmcs_read(GUEST_AR_SS) & GUEST_SEG_UNUSABLE_MASK) 7990 vmcs_write(GUEST_AR_SS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7991 else 7992 vmcs_write(GUEST_AR_SS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7993 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 7994 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 7995 skip_ss_tests: 7996 7997 vmcs_write(GUEST_AR_SS, ar_saved); 7998 vmcs_write(GUEST_SEL_SS, sel_saved); 7999 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrl0_saved); 8000 vmcs_write(CPU_EXEC_CTRL1, cpu_ctrl1_saved); 8001 } 8002 8003 #define TEST_SEGMENT_BASE_ADDR_UPPER_BITS(xfail, seg_base) \ 8004 do { \ 8005 addr_saved = vmcs_read(seg_base); \ 8006 for (i = 32; i < 63; i = i + 4) { \ 8007 addr = addr_saved | 1ull << i; \ 8008 vmcs_write(seg_base, addr); \ 8009 test_guest_state("seg.BASE[63:32] != 0, usable = " xstr(xfail), \ 8010 xfail, addr, xstr(seg_base)); \ 8011 } \ 8012 vmcs_write(seg_base, addr_saved); \ 8013 } while (0) 8014 8015 #define TEST_SEGMENT_BASE_ADDR_CANONICAL(xfail, seg_base) \ 8016 do { \ 8017 addr_saved = vmcs_read(seg_base); \ 8018 vmcs_write(seg_base, NONCANONICAL); \ 8019 test_guest_state("seg.BASE non-canonical, usable = " xstr(xfail), \ 8020 xfail, NONCANONICAL, xstr(seg_base)); \ 8021 vmcs_write(seg_base, addr_saved); \ 8022 } while (0) 8023 8024 /* 8025 * The following checks are done on the Base Address field of the Guest 8026 * Segment Registers on processors that support Intel 64 architecture: 8027 * - TR, FS, GS : The address must be canonical. 8028 * - LDTR : If LDTR is usable, the address must be canonical. 8029 * - CS : Bits 63:32 of the address must be zero. 8030 * - SS, DS, ES : If the register is usable, bits 63:32 of the address 8031 * must be zero. 8032 * 8033 * [Intel SDM] 8034 */ 8035 static void test_guest_segment_base_addr_fields(void) 8036 { 8037 u64 addr_saved; 8038 u64 addr; 8039 u32 ar_saved; 8040 int i; 8041 8042 /* 8043 * The address of TR, FS, GS and LDTR must be canonical. 8044 */ 8045 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_TR); 8046 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_FS); 8047 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_GS); 8048 ar_saved = vmcs_read(GUEST_AR_LDTR); 8049 /* Make LDTR unusable */ 8050 vmcs_write(GUEST_AR_LDTR, ar_saved | GUEST_SEG_UNUSABLE_MASK); 8051 TEST_SEGMENT_BASE_ADDR_CANONICAL(false, GUEST_BASE_LDTR); 8052 /* Make LDTR usable */ 8053 vmcs_write(GUEST_AR_LDTR, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 8054 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_LDTR); 8055 8056 vmcs_write(GUEST_AR_LDTR, ar_saved); 8057 8058 /* 8059 * Bits 63:32 in CS, SS, DS and ES base address must be zero 8060 */ 8061 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_CS); 8062 ar_saved = vmcs_read(GUEST_AR_SS); 8063 /* Make SS unusable */ 8064 vmcs_write(GUEST_AR_SS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 8065 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(false, GUEST_BASE_SS); 8066 /* Make SS usable */ 8067 vmcs_write(GUEST_AR_SS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 8068 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_SS); 8069 vmcs_write(GUEST_AR_SS, ar_saved); 8070 8071 ar_saved = vmcs_read(GUEST_AR_DS); 8072 /* Make DS unusable */ 8073 vmcs_write(GUEST_AR_DS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 8074 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(false, GUEST_BASE_DS); 8075 /* Make DS usable */ 8076 vmcs_write(GUEST_AR_DS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 8077 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_DS); 8078 vmcs_write(GUEST_AR_DS, ar_saved); 8079 8080 ar_saved = vmcs_read(GUEST_AR_ES); 8081 /* Make ES unusable */ 8082 vmcs_write(GUEST_AR_ES, ar_saved | GUEST_SEG_UNUSABLE_MASK); 8083 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(false, GUEST_BASE_ES); 8084 /* Make ES usable */ 8085 vmcs_write(GUEST_AR_ES, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 8086 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_ES); 8087 vmcs_write(GUEST_AR_ES, ar_saved); 8088 } 8089 8090 /* 8091 * Check that the virtual CPU checks the VMX Guest State Area as 8092 * documented in the Intel SDM. 8093 */ 8094 static void vmx_guest_state_area_test(void) 8095 { 8096 vmx_set_test_stage(1); 8097 test_set_guest(guest_state_test_main); 8098 8099 /* 8100 * The IA32_SYSENTER_ESP field and the IA32_SYSENTER_EIP field 8101 * must each contain a canonical address. 8102 */ 8103 test_canonical(GUEST_SYSENTER_ESP, "GUEST_SYSENTER_ESP", false); 8104 test_canonical(GUEST_SYSENTER_EIP, "GUEST_SYSENTER_EIP", false); 8105 8106 test_guest_dr7(); 8107 test_load_guest_pat(); 8108 test_guest_efer(); 8109 test_load_guest_perf_global_ctrl(); 8110 test_load_guest_bndcfgs(); 8111 8112 test_guest_segment_sel_fields(); 8113 test_guest_segment_base_addr_fields(); 8114 8115 test_canonical(GUEST_BASE_GDTR, "GUEST_BASE_GDTR", false); 8116 test_canonical(GUEST_BASE_IDTR, "GUEST_BASE_IDTR", false); 8117 8118 u32 guest_desc_limit_saved = vmcs_read(GUEST_LIMIT_GDTR); 8119 int i; 8120 for (i = 16; i <= 31; i++) { 8121 u32 tmp = guest_desc_limit_saved | (1ull << i); 8122 vmcs_write(GUEST_LIMIT_GDTR, tmp); 8123 test_guest_state("GDT.limit > 0xffff", true, tmp, "GUEST_LIMIT_GDTR"); 8124 } 8125 vmcs_write(GUEST_LIMIT_GDTR, guest_desc_limit_saved); 8126 8127 guest_desc_limit_saved = vmcs_read(GUEST_LIMIT_IDTR); 8128 for (i = 16; i <= 31; i++) { 8129 u32 tmp = guest_desc_limit_saved | (1ull << i); 8130 vmcs_write(GUEST_LIMIT_IDTR, tmp); 8131 test_guest_state("IDT.limit > 0xffff", true, tmp, "GUEST_LIMIT_IDTR"); 8132 } 8133 vmcs_write(GUEST_LIMIT_IDTR, guest_desc_limit_saved); 8134 8135 /* 8136 * Let the guest finish execution 8137 */ 8138 vmx_set_test_stage(2); 8139 enter_guest(); 8140 } 8141 8142 extern void unrestricted_guest_main(void); 8143 asm (".code32\n" 8144 "unrestricted_guest_main:\n" 8145 "vmcall\n" 8146 "nop\n" 8147 "mov $1, %edi\n" 8148 "call hypercall\n" 8149 ".code64\n"); 8150 8151 static void setup_unrestricted_guest(void) 8152 { 8153 vmcs_write(GUEST_CR0, vmcs_read(GUEST_CR0) & ~(X86_CR0_PG)); 8154 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) & ~ENT_GUEST_64); 8155 vmcs_write(GUEST_EFER, vmcs_read(GUEST_EFER) & ~EFER_LMA); 8156 vmcs_write(GUEST_RIP, virt_to_phys(unrestricted_guest_main)); 8157 } 8158 8159 static void unsetup_unrestricted_guest(void) 8160 { 8161 vmcs_write(GUEST_CR0, vmcs_read(GUEST_CR0) | X86_CR0_PG); 8162 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) | ENT_GUEST_64); 8163 vmcs_write(GUEST_EFER, vmcs_read(GUEST_EFER) | EFER_LMA); 8164 vmcs_write(GUEST_RIP, (u64) phys_to_virt(vmcs_read(GUEST_RIP))); 8165 vmcs_write(GUEST_RSP, (u64) phys_to_virt(vmcs_read(GUEST_RSP))); 8166 } 8167 8168 /* 8169 * If "unrestricted guest" secondary VM-execution control is set, guests 8170 * can run in unpaged protected mode. 8171 */ 8172 static void vmentry_unrestricted_guest_test(void) 8173 { 8174 if (enable_unrestricted_guest(true)) { 8175 report_skip("Unrestricted guest not supported"); 8176 return; 8177 } 8178 8179 test_set_guest(unrestricted_guest_main); 8180 setup_unrestricted_guest(); 8181 test_guest_state("Unrestricted guest test", false, CPU_URG, "CPU_URG"); 8182 8183 /* 8184 * Let the guest finish execution as a regular guest 8185 */ 8186 unsetup_unrestricted_guest(); 8187 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) & ~CPU_URG); 8188 enter_guest(); 8189 } 8190 8191 static bool valid_vmcs_for_vmentry(void) 8192 { 8193 struct vmcs *current_vmcs = NULL; 8194 8195 if (vmcs_save(¤t_vmcs)) 8196 return false; 8197 8198 return current_vmcs && !current_vmcs->hdr.shadow_vmcs; 8199 } 8200 8201 static void try_vmentry_in_movss_shadow(void) 8202 { 8203 u32 vm_inst_err; 8204 u32 flags; 8205 bool early_failure = false; 8206 u32 expected_flags = X86_EFLAGS_FIXED; 8207 bool valid_vmcs = valid_vmcs_for_vmentry(); 8208 8209 expected_flags |= valid_vmcs ? X86_EFLAGS_ZF : X86_EFLAGS_CF; 8210 8211 /* 8212 * Indirectly set VM_INST_ERR to 12 ("VMREAD/VMWRITE from/to 8213 * unsupported VMCS component"). 8214 */ 8215 vmcs_write(~0u, 0); 8216 8217 __asm__ __volatile__ ("mov %[host_rsp], %%edx;" 8218 "vmwrite %%rsp, %%rdx;" 8219 "mov 0f, %%rax;" 8220 "mov %[host_rip], %%edx;" 8221 "vmwrite %%rax, %%rdx;" 8222 "mov $-1, %%ah;" 8223 "sahf;" 8224 "mov %%ss, %%ax;" 8225 "mov %%ax, %%ss;" 8226 "vmlaunch;" 8227 "mov $1, %[early_failure];" 8228 "0: lahf;" 8229 "movzbl %%ah, %[flags]" 8230 : [early_failure] "+r" (early_failure), 8231 [flags] "=&a" (flags) 8232 : [host_rsp] "i" (HOST_RSP), 8233 [host_rip] "i" (HOST_RIP) 8234 : "rdx", "cc", "memory"); 8235 vm_inst_err = vmcs_read(VMX_INST_ERROR); 8236 8237 report(early_failure, "Early VM-entry failure"); 8238 report(flags == expected_flags, "RFLAGS[8:0] is %x (actual %x)", 8239 expected_flags, flags); 8240 if (valid_vmcs) 8241 report(vm_inst_err == VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, 8242 "VM-instruction error is %d (actual %d)", 8243 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, vm_inst_err); 8244 } 8245 8246 static void vmentry_movss_shadow_test(void) 8247 { 8248 struct vmcs *orig_vmcs; 8249 8250 TEST_ASSERT(!vmcs_save(&orig_vmcs)); 8251 8252 /* 8253 * Set the launched flag on the current VMCS to verify the correct 8254 * error priority, below. 8255 */ 8256 test_set_guest(v2_null_test_guest); 8257 enter_guest(); 8258 8259 /* 8260 * With bit 1 of the guest's RFLAGS clear, VM-entry should 8261 * fail due to invalid guest state (if we make it that far). 8262 */ 8263 vmcs_write(GUEST_RFLAGS, 0); 8264 8265 /* 8266 * "VM entry with events blocked by MOV SS" takes precedence over 8267 * "VMLAUNCH with non-clear VMCS." 8268 */ 8269 report_prefix_push("valid current-VMCS"); 8270 try_vmentry_in_movss_shadow(); 8271 report_prefix_pop(); 8272 8273 /* 8274 * VMfailInvalid takes precedence over "VM entry with events 8275 * blocked by MOV SS." 8276 */ 8277 TEST_ASSERT(!vmcs_clear(orig_vmcs)); 8278 report_prefix_push("no current-VMCS"); 8279 try_vmentry_in_movss_shadow(); 8280 report_prefix_pop(); 8281 8282 TEST_ASSERT(!make_vmcs_current(orig_vmcs)); 8283 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 8284 } 8285 8286 static void vmx_ldtr_test_guest(void) 8287 { 8288 u16 ldtr = sldt(); 8289 8290 report(ldtr == NP_SEL, "Expected %x for L2 LDTR selector (got %x)", 8291 NP_SEL, ldtr); 8292 } 8293 8294 /* 8295 * Ensure that the L1 LDTR is set to 0 on VM-exit. 8296 */ 8297 static void vmx_ldtr_test(void) 8298 { 8299 const u8 ldt_ar = 0x82; /* Present LDT */ 8300 u16 sel = FIRST_SPARE_SEL; 8301 8302 /* Set up a non-zero L1 LDTR prior to VM-entry. */ 8303 set_gdt_entry(sel, 0, 0, ldt_ar, 0); 8304 lldt(sel); 8305 8306 test_set_guest(vmx_ldtr_test_guest); 8307 /* 8308 * Set up a different LDTR for L2. The actual GDT contents are 8309 * irrelevant, since we stuff the hidden descriptor state 8310 * straight into the VMCS rather than reading it from the GDT. 8311 */ 8312 vmcs_write(GUEST_SEL_LDTR, NP_SEL); 8313 vmcs_write(GUEST_AR_LDTR, ldt_ar); 8314 enter_guest(); 8315 8316 /* 8317 * VM-exit should clear LDTR (and make it unusable, but we 8318 * won't verify that here). 8319 */ 8320 sel = sldt(); 8321 report(!sel, "Expected 0 for L1 LDTR selector (got %x)", sel); 8322 } 8323 8324 static void vmx_single_vmcall_guest(void) 8325 { 8326 vmcall(); 8327 } 8328 8329 static void vmx_cr_load_test(void) 8330 { 8331 unsigned long cr3, cr4, orig_cr3, orig_cr4; 8332 u32 ctrls[2] = {0}; 8333 pgd_t *pml5; 8334 8335 orig_cr4 = read_cr4(); 8336 orig_cr3 = read_cr3(); 8337 8338 if (!this_cpu_has(X86_FEATURE_PCID)) { 8339 report_skip("PCID not detected"); 8340 return; 8341 } 8342 if (!this_cpu_has(X86_FEATURE_MCE)) { 8343 report_skip("MCE not detected"); 8344 return; 8345 } 8346 8347 TEST_ASSERT(!(orig_cr3 & X86_CR3_PCID_MASK)); 8348 8349 /* Enable PCID for L1. */ 8350 cr4 = orig_cr4 | X86_CR4_PCIDE; 8351 cr3 = orig_cr3 | 0x1; 8352 TEST_ASSERT(!write_cr4_checking(cr4)); 8353 write_cr3(cr3); 8354 8355 test_set_guest(vmx_single_vmcall_guest); 8356 vmcs_write(HOST_CR4, cr4); 8357 vmcs_write(HOST_CR3, cr3); 8358 enter_guest(); 8359 8360 /* 8361 * No exception is expected. 8362 * 8363 * NB. KVM loads the last guest write to CR4 into CR4 read 8364 * shadow. In order to trigger an exit to KVM, we can toggle a 8365 * bit that is owned by KVM. We use CR4.MCE, which shall 8366 * have no side effect because normally no guest MCE (e.g., as the 8367 * result of bad memory) would happen during this test. 8368 */ 8369 TEST_ASSERT(!write_cr4_checking(cr4 ^ X86_CR4_MCE)); 8370 8371 /* Cleanup L1 state. */ 8372 write_cr3(orig_cr3); 8373 TEST_ASSERT(!write_cr4_checking(orig_cr4)); 8374 8375 if (!this_cpu_has(X86_FEATURE_LA57)) 8376 goto done; 8377 8378 /* 8379 * Allocate a full page for PML5 to guarantee alignment, though only 8380 * the first entry needs to be filled (the test's virtual addresses 8381 * most definitely do not have any of bits 56:48 set). 8382 */ 8383 pml5 = alloc_page(); 8384 *pml5 = orig_cr3 | PT_PRESENT_MASK | PT_WRITABLE_MASK; 8385 8386 /* 8387 * Transition to/from 5-level paging in the host via VM-Exit. CR4.LA57 8388 * can't be toggled while long is active via MOV CR4, but there are no 8389 * such restrictions on VM-Exit. 8390 */ 8391 lol_5level: 8392 vmcs_write(HOST_CR4, orig_cr4 | X86_CR4_LA57); 8393 vmcs_write(HOST_CR3, virt_to_phys(pml5)); 8394 enter_guest(); 8395 8396 /* 8397 * VMREAD with a memory operand to verify KVM detects the LA57 change, 8398 * e.g. uses the correct guest root level in gva_to_gpa(). 8399 */ 8400 TEST_ASSERT(vmcs_readm(HOST_CR3) == virt_to_phys(pml5)); 8401 TEST_ASSERT(vmcs_readm(HOST_CR4) == (orig_cr4 | X86_CR4_LA57)); 8402 8403 vmcs_write(HOST_CR4, orig_cr4); 8404 vmcs_write(HOST_CR3, orig_cr3); 8405 enter_guest(); 8406 8407 TEST_ASSERT(vmcs_readm(HOST_CR3) == orig_cr3); 8408 TEST_ASSERT(vmcs_readm(HOST_CR4) == orig_cr4); 8409 8410 /* 8411 * And now do the same LA57 shenanigans with EPT enabled. KVM uses 8412 * two separate MMUs when L1 uses TDP, whereas the above shadow paging 8413 * version shares an MMU between L1 and L2. 8414 * 8415 * If the saved execution controls are non-zero then the EPT version 8416 * has already run. In that case, restore the old controls. If EPT 8417 * setup fails, e.g. EPT isn't supported, fall through and finish up. 8418 */ 8419 if (ctrls[0]) { 8420 vmcs_write(CPU_EXEC_CTRL0, ctrls[0]); 8421 vmcs_write(CPU_EXEC_CTRL1, ctrls[1]); 8422 } else if (!setup_ept(false)) { 8423 ctrls[0] = vmcs_read(CPU_EXEC_CTRL0); 8424 ctrls[1] = vmcs_read(CPU_EXEC_CTRL1); 8425 goto lol_5level; 8426 } 8427 8428 free_page(pml5); 8429 8430 done: 8431 skip_exit_vmcall(); 8432 enter_guest(); 8433 } 8434 8435 static void vmx_cr4_osxsave_test_guest(void) 8436 { 8437 write_cr4(read_cr4() & ~X86_CR4_OSXSAVE); 8438 } 8439 8440 /* 8441 * Ensure that kvm recalculates the L1 guest's CPUID.01H:ECX.OSXSAVE 8442 * after VM-exit from an L2 guest that sets CR4.OSXSAVE to a different 8443 * value than in L1. 8444 */ 8445 static void vmx_cr4_osxsave_test(void) 8446 { 8447 if (!this_cpu_has(X86_FEATURE_XSAVE)) { 8448 report_skip("XSAVE not detected"); 8449 return; 8450 } 8451 8452 if (!(read_cr4() & X86_CR4_OSXSAVE)) { 8453 unsigned long cr4 = read_cr4() | X86_CR4_OSXSAVE; 8454 8455 write_cr4(cr4); 8456 vmcs_write(GUEST_CR4, cr4); 8457 vmcs_write(HOST_CR4, cr4); 8458 } 8459 8460 TEST_ASSERT(cpuid_osxsave()); 8461 8462 test_set_guest(vmx_cr4_osxsave_test_guest); 8463 enter_guest(); 8464 8465 TEST_ASSERT(cpuid_osxsave()); 8466 } 8467 8468 static void vmx_nm_test_guest(void) 8469 { 8470 write_cr0(read_cr0() | X86_CR0_TS); 8471 asm volatile("fnop"); 8472 } 8473 8474 static void check_nm_exit(const char *test) 8475 { 8476 u32 reason = vmcs_read(EXI_REASON); 8477 u32 intr_info = vmcs_read(EXI_INTR_INFO); 8478 const u32 expected = INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 8479 NM_VECTOR; 8480 8481 report(reason == VMX_EXC_NMI && intr_info == expected, "%s", test); 8482 } 8483 8484 /* 8485 * This test checks that: 8486 * 8487 * (a) If L2 launches with CR0.TS clear, but later sets CR0.TS, then 8488 * a subsequent #NM VM-exit is reflected to L1. 8489 * 8490 * (b) If L2 launches with CR0.TS clear and CR0.EM set, then a 8491 * subsequent #NM VM-exit is reflected to L1. 8492 */ 8493 static void vmx_nm_test(void) 8494 { 8495 unsigned long cr0 = read_cr0(); 8496 8497 test_set_guest(vmx_nm_test_guest); 8498 8499 /* 8500 * L1 wants to intercept #NM exceptions encountered in L2. 8501 */ 8502 vmcs_write(EXC_BITMAP, 1 << NM_VECTOR); 8503 8504 /* 8505 * Launch L2 with CR0.TS clear, but don't claim host ownership of 8506 * any CR0 bits. L2 will set CR0.TS and then try to execute fnop, 8507 * which will raise #NM. L0 should reflect the #NM VM-exit to L1. 8508 */ 8509 vmcs_write(CR0_MASK, 0); 8510 vmcs_write(GUEST_CR0, cr0 & ~X86_CR0_TS); 8511 enter_guest(); 8512 check_nm_exit("fnop with CR0.TS set in L2 triggers #NM VM-exit to L1"); 8513 8514 /* 8515 * Re-enter L2 at the fnop instruction, with CR0.TS clear but 8516 * CR0.EM set. The fnop will still raise #NM, and L0 should 8517 * reflect the #NM VM-exit to L1. 8518 */ 8519 vmcs_write(GUEST_CR0, (cr0 & ~X86_CR0_TS) | X86_CR0_EM); 8520 enter_guest(); 8521 check_nm_exit("fnop with CR0.EM set in L2 triggers #NM VM-exit to L1"); 8522 8523 /* 8524 * Re-enter L2 at the fnop instruction, with both CR0.TS and 8525 * CR0.EM clear. There will be no #NM, and the L2 guest should 8526 * exit normally. 8527 */ 8528 vmcs_write(GUEST_CR0, cr0 & ~(X86_CR0_TS | X86_CR0_EM)); 8529 enter_guest(); 8530 } 8531 8532 bool vmx_pending_event_ipi_fired; 8533 static void vmx_pending_event_ipi_isr(isr_regs_t *regs) 8534 { 8535 vmx_pending_event_ipi_fired = true; 8536 eoi(); 8537 } 8538 8539 bool vmx_pending_event_guest_run; 8540 static void vmx_pending_event_guest(void) 8541 { 8542 vmcall(); 8543 vmx_pending_event_guest_run = true; 8544 } 8545 8546 static void vmx_pending_event_test_core(bool guest_hlt) 8547 { 8548 int ipi_vector = 0xf1; 8549 8550 vmx_pending_event_ipi_fired = false; 8551 handle_irq(ipi_vector, vmx_pending_event_ipi_isr); 8552 8553 vmx_pending_event_guest_run = false; 8554 test_set_guest(vmx_pending_event_guest); 8555 8556 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 8557 8558 enter_guest(); 8559 skip_exit_vmcall(); 8560 8561 if (guest_hlt) 8562 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8563 8564 irq_disable(); 8565 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | 8566 APIC_DM_FIXED | ipi_vector, 8567 0); 8568 8569 enter_guest(); 8570 8571 assert_exit_reason(VMX_EXTINT); 8572 report(!vmx_pending_event_guest_run, 8573 "Guest did not run before host received IPI"); 8574 8575 irq_enable(); 8576 asm volatile ("nop"); 8577 irq_disable(); 8578 report(vmx_pending_event_ipi_fired, 8579 "Got pending interrupt after IRQ enabled"); 8580 8581 if (guest_hlt) 8582 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 8583 8584 enter_guest(); 8585 report(vmx_pending_event_guest_run, 8586 "Guest finished running when no interrupt"); 8587 } 8588 8589 static void vmx_pending_event_test(void) 8590 { 8591 vmx_pending_event_test_core(false); 8592 } 8593 8594 static void vmx_pending_event_hlt_test(void) 8595 { 8596 vmx_pending_event_test_core(true); 8597 } 8598 8599 static int vmx_window_test_db_count; 8600 8601 static void vmx_window_test_db_handler(struct ex_regs *regs) 8602 { 8603 vmx_window_test_db_count++; 8604 } 8605 8606 static void vmx_nmi_window_test_guest(void) 8607 { 8608 handle_exception(DB_VECTOR, vmx_window_test_db_handler); 8609 8610 asm volatile("vmcall\n\t" 8611 "nop\n\t"); 8612 8613 handle_exception(DB_VECTOR, NULL); 8614 } 8615 8616 static void verify_nmi_window_exit(u64 rip) 8617 { 8618 u32 exit_reason = vmcs_read(EXI_REASON); 8619 8620 report(exit_reason == VMX_NMI_WINDOW, 8621 "Exit reason (%d) is 'NMI window'", exit_reason); 8622 report(vmcs_read(GUEST_RIP) == rip, "RIP (%#lx) is %#lx", 8623 vmcs_read(GUEST_RIP), rip); 8624 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 8625 } 8626 8627 static void vmx_nmi_window_test(void) 8628 { 8629 u64 nop_addr; 8630 void *db_fault_addr = get_idt_addr(&boot_idt[DB_VECTOR]); 8631 8632 if (!(ctrl_pin_rev.clr & PIN_VIRT_NMI)) { 8633 report_skip("CPU does not support the \"Virtual NMIs\" VM-execution control."); 8634 return; 8635 } 8636 8637 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 8638 report_skip("CPU does not support the \"NMI-window exiting\" VM-execution control."); 8639 return; 8640 } 8641 8642 vmx_window_test_db_count = 0; 8643 8644 report_prefix_push("NMI-window"); 8645 test_set_guest(vmx_nmi_window_test_guest); 8646 vmcs_set_bits(PIN_CONTROLS, PIN_VIRT_NMI); 8647 enter_guest(); 8648 skip_exit_vmcall(); 8649 nop_addr = vmcs_read(GUEST_RIP); 8650 8651 /* 8652 * Ask for "NMI-window exiting," and expect an immediate VM-exit. 8653 * RIP will not advance. 8654 */ 8655 report_prefix_push("active, no blocking"); 8656 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 8657 enter_guest(); 8658 verify_nmi_window_exit(nop_addr); 8659 report_prefix_pop(); 8660 8661 /* 8662 * Ask for "NMI-window exiting" in a MOV-SS shadow, and expect 8663 * a VM-exit on the next instruction after the nop. (The nop 8664 * is one byte.) 8665 */ 8666 report_prefix_push("active, blocking by MOV-SS"); 8667 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 8668 enter_guest(); 8669 verify_nmi_window_exit(nop_addr + 1); 8670 report_prefix_pop(); 8671 8672 /* 8673 * Ask for "NMI-window exiting" (with event injection), and 8674 * expect a VM-exit after the event is injected. (RIP should 8675 * be at the address specified in the IDT entry for #DB.) 8676 */ 8677 report_prefix_push("active, no blocking, injecting #DB"); 8678 vmcs_write(ENT_INTR_INFO, 8679 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 8680 enter_guest(); 8681 verify_nmi_window_exit((u64)db_fault_addr); 8682 report_prefix_pop(); 8683 8684 /* 8685 * Ask for "NMI-window exiting" with NMI blocking, and expect 8686 * a VM-exit after the next IRET (i.e. after the #DB handler 8687 * returns). So, RIP should be back at one byte past the nop. 8688 */ 8689 report_prefix_push("active, blocking by NMI"); 8690 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_NMI); 8691 enter_guest(); 8692 verify_nmi_window_exit(nop_addr + 1); 8693 report(vmx_window_test_db_count == 1, 8694 "#DB handler executed once (actual %d times)", 8695 vmx_window_test_db_count); 8696 report_prefix_pop(); 8697 8698 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 8699 report_skip("CPU does not support activity state HLT."); 8700 } else { 8701 /* 8702 * Ask for "NMI-window exiting" when entering activity 8703 * state HLT, and expect an immediate VM-exit. RIP is 8704 * still one byte past the nop. 8705 */ 8706 report_prefix_push("halted, no blocking"); 8707 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8708 enter_guest(); 8709 verify_nmi_window_exit(nop_addr + 1); 8710 report_prefix_pop(); 8711 8712 /* 8713 * Ask for "NMI-window exiting" when entering activity 8714 * state HLT (with event injection), and expect a 8715 * VM-exit after the event is injected. (RIP should be 8716 * at the address specified in the IDT entry for #DB.) 8717 */ 8718 report_prefix_push("halted, no blocking, injecting #DB"); 8719 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8720 vmcs_write(ENT_INTR_INFO, 8721 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 8722 DB_VECTOR); 8723 enter_guest(); 8724 verify_nmi_window_exit((u64)db_fault_addr); 8725 report_prefix_pop(); 8726 } 8727 8728 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 8729 enter_guest(); 8730 report_prefix_pop(); 8731 } 8732 8733 static void vmx_intr_window_test_guest(void) 8734 { 8735 handle_exception(DB_VECTOR, vmx_window_test_db_handler); 8736 8737 /* 8738 * The two consecutive STIs are to ensure that only the first 8739 * one has a shadow. Note that NOP and STI are one byte 8740 * instructions. 8741 */ 8742 asm volatile("vmcall\n\t" 8743 "nop\n\t" 8744 "sti\n\t" 8745 "sti\n\t"); 8746 8747 handle_exception(DB_VECTOR, NULL); 8748 } 8749 8750 static void verify_intr_window_exit(u64 rip) 8751 { 8752 u32 exit_reason = vmcs_read(EXI_REASON); 8753 8754 report(exit_reason == VMX_INTR_WINDOW, 8755 "Exit reason (%d) is 'interrupt window'", exit_reason); 8756 report(vmcs_read(GUEST_RIP) == rip, "RIP (%#lx) is %#lx", 8757 vmcs_read(GUEST_RIP), rip); 8758 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 8759 } 8760 8761 static void vmx_intr_window_test(void) 8762 { 8763 u64 vmcall_addr; 8764 u64 nop_addr; 8765 unsigned int orig_db_gate_type; 8766 void *db_fault_addr = get_idt_addr(&boot_idt[DB_VECTOR]); 8767 8768 if (!(ctrl_cpu_rev[0].clr & CPU_INTR_WINDOW)) { 8769 report_skip("CPU does not support the \"interrupt-window exiting\" VM-execution control."); 8770 return; 8771 } 8772 8773 /* 8774 * Change the IDT entry for #DB from interrupt gate to trap gate, 8775 * so that it won't clear RFLAGS.IF. We don't want interrupts to 8776 * be disabled after vectoring a #DB. 8777 */ 8778 orig_db_gate_type = boot_idt[DB_VECTOR].type; 8779 boot_idt[DB_VECTOR].type = 15; 8780 8781 report_prefix_push("interrupt-window"); 8782 test_set_guest(vmx_intr_window_test_guest); 8783 enter_guest(); 8784 assert_exit_reason(VMX_VMCALL); 8785 vmcall_addr = vmcs_read(GUEST_RIP); 8786 8787 /* 8788 * Ask for "interrupt-window exiting" with RFLAGS.IF set and 8789 * no blocking; expect an immediate VM-exit. Note that we have 8790 * not advanced past the vmcall instruction yet, so RIP should 8791 * point to the vmcall instruction. 8792 */ 8793 report_prefix_push("active, no blocking, RFLAGS.IF=1"); 8794 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8795 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_IF); 8796 enter_guest(); 8797 verify_intr_window_exit(vmcall_addr); 8798 report_prefix_pop(); 8799 8800 /* 8801 * Ask for "interrupt-window exiting" (with event injection) 8802 * with RFLAGS.IF set and no blocking; expect a VM-exit after 8803 * the event is injected. That is, RIP should should be at the 8804 * address specified in the IDT entry for #DB. 8805 */ 8806 report_prefix_push("active, no blocking, RFLAGS.IF=1, injecting #DB"); 8807 vmcs_write(ENT_INTR_INFO, 8808 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 8809 vmcall_addr = vmcs_read(GUEST_RIP); 8810 enter_guest(); 8811 verify_intr_window_exit((u64)db_fault_addr); 8812 report_prefix_pop(); 8813 8814 /* 8815 * Let the L2 guest run through the IRET, back to the VMCALL. 8816 * We have to clear the "interrupt-window exiting" 8817 * VM-execution control, or it would just keep causing 8818 * VM-exits. Then, advance past the VMCALL and set the 8819 * "interrupt-window exiting" VM-execution control again. 8820 */ 8821 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8822 enter_guest(); 8823 skip_exit_vmcall(); 8824 nop_addr = vmcs_read(GUEST_RIP); 8825 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8826 8827 /* 8828 * Ask for "interrupt-window exiting" in a MOV-SS shadow with 8829 * RFLAGS.IF set, and expect a VM-exit on the next 8830 * instruction. (NOP is one byte.) 8831 */ 8832 report_prefix_push("active, blocking by MOV-SS, RFLAGS.IF=1"); 8833 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 8834 enter_guest(); 8835 verify_intr_window_exit(nop_addr + 1); 8836 report_prefix_pop(); 8837 8838 /* 8839 * Back up to the NOP and ask for "interrupt-window exiting" 8840 * in an STI shadow with RFLAGS.IF set, and expect a VM-exit 8841 * on the next instruction. (NOP is one byte.) 8842 */ 8843 report_prefix_push("active, blocking by STI, RFLAGS.IF=1"); 8844 vmcs_write(GUEST_RIP, nop_addr); 8845 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_STI); 8846 enter_guest(); 8847 verify_intr_window_exit(nop_addr + 1); 8848 report_prefix_pop(); 8849 8850 /* 8851 * Ask for "interrupt-window exiting" with RFLAGS.IF clear, 8852 * and expect a VM-exit on the instruction following the STI 8853 * shadow. Only the first STI (which is one byte past the NOP) 8854 * should have a shadow. The second STI (which is two bytes 8855 * past the NOP) has no shadow. Therefore, the interrupt 8856 * window opens at three bytes past the NOP. 8857 */ 8858 report_prefix_push("active, RFLAGS.IF = 0"); 8859 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 8860 enter_guest(); 8861 verify_intr_window_exit(nop_addr + 3); 8862 report_prefix_pop(); 8863 8864 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 8865 report_skip("CPU does not support activity state HLT."); 8866 } else { 8867 /* 8868 * Ask for "interrupt-window exiting" when entering 8869 * activity state HLT, and expect an immediate 8870 * VM-exit. RIP is still three bytes past the nop. 8871 */ 8872 report_prefix_push("halted, no blocking"); 8873 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8874 enter_guest(); 8875 verify_intr_window_exit(nop_addr + 3); 8876 report_prefix_pop(); 8877 8878 /* 8879 * Ask for "interrupt-window exiting" when entering 8880 * activity state HLT (with event injection), and 8881 * expect a VM-exit after the event is injected. That 8882 * is, RIP should should be at the address specified 8883 * in the IDT entry for #DB. 8884 */ 8885 report_prefix_push("halted, no blocking, injecting #DB"); 8886 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8887 vmcs_write(ENT_INTR_INFO, 8888 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 8889 DB_VECTOR); 8890 enter_guest(); 8891 verify_intr_window_exit((u64)db_fault_addr); 8892 report_prefix_pop(); 8893 } 8894 8895 boot_idt[DB_VECTOR].type = orig_db_gate_type; 8896 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8897 enter_guest(); 8898 report_prefix_pop(); 8899 } 8900 8901 #define GUEST_TSC_OFFSET (1u << 30) 8902 8903 static u64 guest_tsc; 8904 8905 static void vmx_store_tsc_test_guest(void) 8906 { 8907 guest_tsc = rdtsc(); 8908 } 8909 8910 /* 8911 * This test ensures that when IA32_TSC is in the VM-exit MSR-store 8912 * list, the value saved is not subject to the TSC offset that is 8913 * applied to RDTSC/RDTSCP/RDMSR(IA32_TSC) in guest execution. 8914 */ 8915 static void vmx_store_tsc_test(void) 8916 { 8917 struct vmx_msr_entry msr_entry = { .index = MSR_IA32_TSC }; 8918 u64 low, high; 8919 8920 if (!(ctrl_cpu_rev[0].clr & CPU_USE_TSC_OFFSET)) { 8921 report_skip("'Use TSC offsetting' not supported"); 8922 return; 8923 } 8924 8925 test_set_guest(vmx_store_tsc_test_guest); 8926 8927 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_USE_TSC_OFFSET); 8928 vmcs_write(EXI_MSR_ST_CNT, 1); 8929 vmcs_write(EXIT_MSR_ST_ADDR, virt_to_phys(&msr_entry)); 8930 vmcs_write(TSC_OFFSET, GUEST_TSC_OFFSET); 8931 8932 low = rdtsc(); 8933 enter_guest(); 8934 high = rdtsc(); 8935 8936 report(low + GUEST_TSC_OFFSET <= guest_tsc && 8937 guest_tsc <= high + GUEST_TSC_OFFSET, 8938 "RDTSC value in the guest (%lu) is in range [%lu, %lu]", 8939 guest_tsc, low + GUEST_TSC_OFFSET, high + GUEST_TSC_OFFSET); 8940 report(low <= msr_entry.value && msr_entry.value <= high, 8941 "IA32_TSC value saved in the VM-exit MSR-store list (%lu) is in range [%lu, %lu]", 8942 msr_entry.value, low, high); 8943 } 8944 8945 static void vmx_preemption_timer_zero_test_db_handler(struct ex_regs *regs) 8946 { 8947 } 8948 8949 static void vmx_preemption_timer_zero_test_guest(void) 8950 { 8951 while (vmx_get_test_stage() < 3) 8952 vmcall(); 8953 } 8954 8955 static void vmx_preemption_timer_zero_activate_preemption_timer(void) 8956 { 8957 vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT); 8958 vmcs_write(PREEMPT_TIMER_VALUE, 0); 8959 } 8960 8961 static void vmx_preemption_timer_zero_advance_past_vmcall(void) 8962 { 8963 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 8964 enter_guest(); 8965 skip_exit_vmcall(); 8966 } 8967 8968 static void vmx_preemption_timer_zero_inject_db(bool intercept_db) 8969 { 8970 vmx_preemption_timer_zero_activate_preemption_timer(); 8971 vmcs_write(ENT_INTR_INFO, INTR_INFO_VALID_MASK | 8972 INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 8973 vmcs_write(EXC_BITMAP, intercept_db ? 1 << DB_VECTOR : 0); 8974 enter_guest(); 8975 } 8976 8977 static void vmx_preemption_timer_zero_set_pending_dbg(u32 exception_bitmap) 8978 { 8979 vmx_preemption_timer_zero_activate_preemption_timer(); 8980 vmcs_write(GUEST_PENDING_DEBUG, BIT(12) | DR_TRAP1); 8981 vmcs_write(EXC_BITMAP, exception_bitmap); 8982 enter_guest(); 8983 } 8984 8985 static void vmx_preemption_timer_zero_expect_preempt_at_rip(u64 expected_rip) 8986 { 8987 u32 reason = (u32)vmcs_read(EXI_REASON); 8988 u64 guest_rip = vmcs_read(GUEST_RIP); 8989 8990 report(reason == VMX_PREEMPT && guest_rip == expected_rip, 8991 "Exit reason is 0x%x (expected 0x%x) and guest RIP is %lx (0x%lx expected).", 8992 reason, VMX_PREEMPT, guest_rip, expected_rip); 8993 } 8994 8995 /* 8996 * This test ensures that when the VMX preemption timer is zero at 8997 * VM-entry, a VM-exit occurs after any event injection and after any 8998 * pending debug exceptions are raised, but before execution of any 8999 * guest instructions. 9000 */ 9001 static void vmx_preemption_timer_zero_test(void) 9002 { 9003 u64 db_fault_address = (u64)get_idt_addr(&boot_idt[DB_VECTOR]); 9004 handler old_db; 9005 u32 reason; 9006 9007 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 9008 report_skip("'Activate VMX-preemption timer' not supported"); 9009 return; 9010 } 9011 9012 /* 9013 * Install a custom #DB handler that doesn't abort. 9014 */ 9015 old_db = handle_exception(DB_VECTOR, 9016 vmx_preemption_timer_zero_test_db_handler); 9017 9018 test_set_guest(vmx_preemption_timer_zero_test_guest); 9019 9020 /* 9021 * VMX-preemption timer should fire after event injection. 9022 */ 9023 vmx_set_test_stage(0); 9024 vmx_preemption_timer_zero_inject_db(0); 9025 vmx_preemption_timer_zero_expect_preempt_at_rip(db_fault_address); 9026 vmx_preemption_timer_zero_advance_past_vmcall(); 9027 9028 /* 9029 * VMX-preemption timer should fire after event injection. 9030 * Exception bitmap is irrelevant, since you can't intercept 9031 * an event that you injected. 9032 */ 9033 vmx_set_test_stage(1); 9034 vmx_preemption_timer_zero_inject_db(true); 9035 vmx_preemption_timer_zero_expect_preempt_at_rip(db_fault_address); 9036 vmx_preemption_timer_zero_advance_past_vmcall(); 9037 9038 /* 9039 * VMX-preemption timer should fire after pending debug exceptions 9040 * have delivered a #DB trap. 9041 */ 9042 vmx_set_test_stage(2); 9043 vmx_preemption_timer_zero_set_pending_dbg(0); 9044 vmx_preemption_timer_zero_expect_preempt_at_rip(db_fault_address); 9045 vmx_preemption_timer_zero_advance_past_vmcall(); 9046 9047 /* 9048 * VMX-preemption timer would fire after pending debug exceptions 9049 * have delivered a #DB trap, but in this case, the #DB trap is 9050 * intercepted. 9051 */ 9052 vmx_set_test_stage(3); 9053 vmx_preemption_timer_zero_set_pending_dbg(1 << DB_VECTOR); 9054 reason = (u32)vmcs_read(EXI_REASON); 9055 report(reason == VMX_EXC_NMI, "Exit reason is 0x%x (expected 0x%x)", 9056 reason, VMX_EXC_NMI); 9057 9058 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 9059 enter_guest(); 9060 9061 handle_exception(DB_VECTOR, old_db); 9062 } 9063 9064 static u64 vmx_preemption_timer_tf_test_prev_rip; 9065 9066 static void vmx_preemption_timer_tf_test_db_handler(struct ex_regs *regs) 9067 { 9068 extern char vmx_preemption_timer_tf_test_endloop; 9069 9070 if (vmx_get_test_stage() == 2) { 9071 /* 9072 * Stage 2 means that we're done, one way or another. 9073 * Arrange for the iret to drop us out of the wbinvd 9074 * loop and stop single-stepping. 9075 */ 9076 regs->rip = (u64)&vmx_preemption_timer_tf_test_endloop; 9077 regs->rflags &= ~X86_EFLAGS_TF; 9078 } else if (regs->rip == vmx_preemption_timer_tf_test_prev_rip) { 9079 /* 9080 * The RIP should alternate between the wbinvd and the 9081 * jmp instruction in the code below. If we ever see 9082 * the same instruction twice in a row, that means a 9083 * single-step trap has been dropped. Let the 9084 * hypervisor know about the failure by executing a 9085 * VMCALL. 9086 */ 9087 vmcall(); 9088 } 9089 vmx_preemption_timer_tf_test_prev_rip = regs->rip; 9090 } 9091 9092 static void vmx_preemption_timer_tf_test_guest(void) 9093 { 9094 /* 9095 * The hypervisor doesn't intercept WBINVD, so the loop below 9096 * shouldn't be a problem--it's just two instructions 9097 * executing in VMX non-root mode. However, when the 9098 * hypervisor is running in a virtual environment, the parent 9099 * hypervisor might intercept WBINVD and emulate it. If the 9100 * parent hypervisor is broken, the single-step trap after the 9101 * WBINVD might be lost. 9102 */ 9103 asm volatile("vmcall\n\t" 9104 "0: wbinvd\n\t" 9105 "1: jmp 0b\n\t" 9106 "vmx_preemption_timer_tf_test_endloop:"); 9107 } 9108 9109 /* 9110 * Ensure that the delivery of a "VMX-preemption timer expired" 9111 * VM-exit doesn't disrupt single-stepping in the guest. Note that 9112 * passing this test doesn't ensure correctness, because the test will 9113 * only fail if the VMX-preemtion timer fires at the right time (or 9114 * the wrong time, as it were). 9115 */ 9116 static void vmx_preemption_timer_tf_test(void) 9117 { 9118 handler old_db; 9119 u32 reason; 9120 int i; 9121 9122 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 9123 report_skip("'Activate VMX-preemption timer' not supported"); 9124 return; 9125 } 9126 9127 old_db = handle_exception(DB_VECTOR, 9128 vmx_preemption_timer_tf_test_db_handler); 9129 9130 test_set_guest(vmx_preemption_timer_tf_test_guest); 9131 9132 enter_guest(); 9133 skip_exit_vmcall(); 9134 9135 vmx_set_test_stage(1); 9136 vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT); 9137 vmcs_write(PREEMPT_TIMER_VALUE, 50000); 9138 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_TF); 9139 9140 /* 9141 * The only exit we should see is "VMX-preemption timer 9142 * expired." If we get a VMCALL exit, that means the #DB 9143 * handler has detected a missing single-step trap. It doesn't 9144 * matter where the guest RIP is when the VMX-preemption timer 9145 * expires (whether it's in the WBINVD loop or in the #DB 9146 * handler)--a single-step trap should never be discarded. 9147 */ 9148 for (i = 0; i < 10000; i++) { 9149 enter_guest(); 9150 reason = (u32)vmcs_read(EXI_REASON); 9151 if (reason == VMX_PREEMPT) 9152 continue; 9153 TEST_ASSERT(reason == VMX_VMCALL); 9154 skip_exit_insn(); 9155 break; 9156 } 9157 9158 report(reason == VMX_PREEMPT, "No single-step traps skipped"); 9159 9160 vmx_set_test_stage(2); 9161 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 9162 enter_guest(); 9163 9164 handle_exception(DB_VECTOR, old_db); 9165 } 9166 9167 #define VMX_PREEMPTION_TIMER_EXPIRY_CYCLES 1000000 9168 9169 static u64 vmx_preemption_timer_expiry_start; 9170 static u64 vmx_preemption_timer_expiry_finish; 9171 9172 static void vmx_preemption_timer_expiry_test_guest(void) 9173 { 9174 vmcall(); 9175 vmx_preemption_timer_expiry_start = fenced_rdtsc(); 9176 9177 while (vmx_get_test_stage() == 0) 9178 vmx_preemption_timer_expiry_finish = fenced_rdtsc(); 9179 } 9180 9181 /* 9182 * Test that the VMX-preemption timer is not excessively delayed. 9183 * 9184 * Per the SDM, volume 3, VM-entry starts the VMX-preemption timer 9185 * with the unsigned value in the VMX-preemption timer-value field, 9186 * and the VMX-preemption timer counts down by 1 every time bit X in 9187 * the TSC changes due to a TSC increment (where X is 9188 * IA32_VMX_MISC[4:0]). If the timer counts down to zero in any state 9189 * other than the wait-for-SIPI state, the logical processor 9190 * transitions to the C0 C-state and causes a VM-exit. 9191 * 9192 * The guest code above reads the starting TSC after VM-entry. At this 9193 * point, the VMX-preemption timer has already been activated. Next, 9194 * the guest code reads the current TSC in a loop, storing the value 9195 * read to memory. 9196 * 9197 * If the RDTSC in the loop reads a value past the VMX-preemption 9198 * timer deadline, then the VMX-preemption timer VM-exit must be 9199 * delivered before the next instruction retires. Even if a higher 9200 * priority SMI is delivered first, the VMX-preemption timer VM-exit 9201 * must be delivered before the next instruction retires. Hence, a TSC 9202 * value past the VMX-preemption timer deadline might be read, but it 9203 * cannot be stored. If a TSC value past the deadline *is* stored, 9204 * then the architectural specification has been violated. 9205 */ 9206 static void vmx_preemption_timer_expiry_test(void) 9207 { 9208 u32 preemption_timer_value; 9209 union vmx_misc misc; 9210 u64 tsc_deadline; 9211 u32 reason; 9212 9213 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 9214 report_skip("'Activate VMX-preemption timer' not supported"); 9215 return; 9216 } 9217 9218 test_set_guest(vmx_preemption_timer_expiry_test_guest); 9219 9220 enter_guest(); 9221 skip_exit_vmcall(); 9222 9223 misc.val = rdmsr(MSR_IA32_VMX_MISC); 9224 preemption_timer_value = 9225 VMX_PREEMPTION_TIMER_EXPIRY_CYCLES >> misc.pt_bit; 9226 9227 vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT); 9228 vmcs_write(PREEMPT_TIMER_VALUE, preemption_timer_value); 9229 vmx_set_test_stage(0); 9230 9231 enter_guest(); 9232 reason = (u32)vmcs_read(EXI_REASON); 9233 TEST_ASSERT(reason == VMX_PREEMPT); 9234 9235 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 9236 vmx_set_test_stage(1); 9237 enter_guest(); 9238 9239 tsc_deadline = ((vmx_preemption_timer_expiry_start >> misc.pt_bit) << 9240 misc.pt_bit) + (preemption_timer_value << misc.pt_bit); 9241 9242 report(vmx_preemption_timer_expiry_finish < tsc_deadline, 9243 "Last stored guest TSC (%lu) < TSC deadline (%lu)", 9244 vmx_preemption_timer_expiry_finish, tsc_deadline); 9245 } 9246 9247 static void vmx_db_test_guest(void) 9248 { 9249 /* 9250 * For a hardware generated single-step #DB. 9251 */ 9252 asm volatile("vmcall;" 9253 "nop;" 9254 ".Lpost_nop:"); 9255 /* 9256 * ...in a MOVSS shadow, with pending debug exceptions. 9257 */ 9258 asm volatile("vmcall;" 9259 "nop;" 9260 ".Lpost_movss_nop:"); 9261 /* 9262 * For an L0 synthesized single-step #DB. (L0 intercepts WBINVD and 9263 * emulates it in software.) 9264 */ 9265 asm volatile("vmcall;" 9266 "wbinvd;" 9267 ".Lpost_wbinvd:"); 9268 /* 9269 * ...in a MOVSS shadow, with pending debug exceptions. 9270 */ 9271 asm volatile("vmcall;" 9272 "wbinvd;" 9273 ".Lpost_movss_wbinvd:"); 9274 /* 9275 * For a hardware generated single-step #DB in a transactional region. 9276 */ 9277 asm volatile("vmcall;" 9278 ".Lxbegin: xbegin .Lskip_rtm;" 9279 "xend;" 9280 ".Lskip_rtm:"); 9281 } 9282 9283 /* 9284 * Clear the pending debug exceptions and RFLAGS.TF and re-enter 9285 * L2. No #DB is delivered and L2 continues to the next point of 9286 * interest. 9287 */ 9288 static void dismiss_db(void) 9289 { 9290 vmcs_write(GUEST_PENDING_DEBUG, 0); 9291 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 9292 enter_guest(); 9293 } 9294 9295 /* 9296 * Check a variety of VMCS fields relevant to an intercepted #DB exception. 9297 * Then throw away the #DB exception and resume L2. 9298 */ 9299 static void check_db_exit(bool xfail_qual, bool xfail_dr6, bool xfail_pdbg, 9300 void *expected_rip, u64 expected_exit_qual, 9301 u64 expected_dr6) 9302 { 9303 u32 reason = vmcs_read(EXI_REASON); 9304 u32 intr_info = vmcs_read(EXI_INTR_INFO); 9305 u64 exit_qual = vmcs_read(EXI_QUALIFICATION); 9306 u64 guest_rip = vmcs_read(GUEST_RIP); 9307 u64 guest_pending_dbg = vmcs_read(GUEST_PENDING_DEBUG); 9308 u64 dr6 = read_dr6(); 9309 const u32 expected_intr_info = INTR_INFO_VALID_MASK | 9310 INTR_TYPE_HARD_EXCEPTION | DB_VECTOR; 9311 9312 report(reason == VMX_EXC_NMI && intr_info == expected_intr_info, 9313 "Expected #DB VM-exit"); 9314 report((u64)expected_rip == guest_rip, "Expected RIP %p (actual %lx)", 9315 expected_rip, guest_rip); 9316 report_xfail(xfail_pdbg, 0 == guest_pending_dbg, 9317 "Expected pending debug exceptions 0 (actual %lx)", 9318 guest_pending_dbg); 9319 report_xfail(xfail_qual, expected_exit_qual == exit_qual, 9320 "Expected exit qualification %lx (actual %lx)", 9321 expected_exit_qual, exit_qual); 9322 report_xfail(xfail_dr6, expected_dr6 == dr6, 9323 "Expected DR6 %lx (actual %lx)", expected_dr6, dr6); 9324 dismiss_db(); 9325 } 9326 9327 /* 9328 * Assuming the guest has just exited on a VMCALL instruction, skip 9329 * over the vmcall, and set the guest's RFLAGS.TF in the VMCS. If 9330 * pending debug exceptions are non-zero, set the VMCS up as if the 9331 * previous instruction was a MOVSS that generated the indicated 9332 * pending debug exceptions. Then enter L2. 9333 */ 9334 static void single_step_guest(const char *test_name, u64 starting_dr6, 9335 u64 pending_debug_exceptions) 9336 { 9337 printf("\n%s\n", test_name); 9338 skip_exit_vmcall(); 9339 write_dr6(starting_dr6); 9340 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_TF); 9341 if (pending_debug_exceptions) { 9342 vmcs_write(GUEST_PENDING_DEBUG, pending_debug_exceptions); 9343 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 9344 } 9345 enter_guest(); 9346 } 9347 9348 /* 9349 * When L1 intercepts #DB, verify that a single-step trap clears 9350 * pending debug exceptions, populates the exit qualification field 9351 * properly, and that DR6 is not prematurely clobbered. In a 9352 * (simulated) MOVSS shadow, make sure that the pending debug 9353 * exception bits are properly accumulated into the exit qualification 9354 * field. 9355 */ 9356 static void vmx_db_test(void) 9357 { 9358 /* 9359 * We are going to set a few arbitrary bits in DR6 to verify that 9360 * (a) DR6 is not modified by an intercepted #DB, and 9361 * (b) stale bits in DR6 (DR6.BD, in particular) don't leak into 9362 * the exit qualification field for a subsequent #DB exception. 9363 */ 9364 const u64 starting_dr6 = DR6_RESERVED | BIT(13) | DR_TRAP3 | DR_TRAP1; 9365 extern char post_nop asm(".Lpost_nop"); 9366 extern char post_movss_nop asm(".Lpost_movss_nop"); 9367 extern char post_wbinvd asm(".Lpost_wbinvd"); 9368 extern char post_movss_wbinvd asm(".Lpost_movss_wbinvd"); 9369 extern char xbegin asm(".Lxbegin"); 9370 extern char skip_rtm asm(".Lskip_rtm"); 9371 9372 /* 9373 * L1 wants to intercept #DB exceptions encountered in L2. 9374 */ 9375 vmcs_write(EXC_BITMAP, BIT(DB_VECTOR)); 9376 9377 /* 9378 * Start L2 and run it up to the first point of interest. 9379 */ 9380 test_set_guest(vmx_db_test_guest); 9381 enter_guest(); 9382 9383 /* 9384 * Hardware-delivered #DB trap for single-step sets the 9385 * standard that L0 has to follow for emulated instructions. 9386 */ 9387 single_step_guest("Hardware delivered single-step", starting_dr6, 0); 9388 check_db_exit(false, false, false, &post_nop, DR_STEP, starting_dr6); 9389 9390 /* 9391 * Hardware-delivered #DB trap for single-step in MOVSS shadow 9392 * also sets the standard that L0 has to follow for emulated 9393 * instructions. Here, we establish the VMCS pending debug 9394 * exceptions to indicate that the simulated MOVSS triggered a 9395 * data breakpoint as well as the single-step trap. 9396 */ 9397 single_step_guest("Hardware delivered single-step in MOVSS shadow", 9398 starting_dr6, BIT(12) | DR_STEP | DR_TRAP0 ); 9399 check_db_exit(false, false, false, &post_movss_nop, DR_STEP | DR_TRAP0, 9400 starting_dr6); 9401 9402 /* 9403 * L0 synthesized #DB trap for single-step is buggy, because 9404 * kvm (a) clobbers DR6 too early, and (b) tries its best to 9405 * reconstitute the exit qualification from the prematurely 9406 * modified DR6, but fails miserably. 9407 */ 9408 single_step_guest("Software synthesized single-step", starting_dr6, 0); 9409 check_db_exit(false, false, false, &post_wbinvd, DR_STEP, starting_dr6); 9410 9411 /* 9412 * L0 synthesized #DB trap for single-step in MOVSS shadow is 9413 * even worse, because L0 also leaves the pending debug 9414 * exceptions in the VMCS instead of accumulating them into 9415 * the exit qualification field for the #DB exception. 9416 */ 9417 single_step_guest("Software synthesized single-step in MOVSS shadow", 9418 starting_dr6, BIT(12) | DR_STEP | DR_TRAP0); 9419 check_db_exit(true, false, true, &post_movss_wbinvd, DR_STEP | DR_TRAP0, 9420 starting_dr6); 9421 9422 /* 9423 * Optional RTM test for hardware that supports RTM, to 9424 * demonstrate that the current volume 3 of the SDM 9425 * (325384-067US), table 27-1 is incorrect. Bit 16 of the exit 9426 * qualification for debug exceptions is not reserved. It is 9427 * set to 1 if a debug exception (#DB) or a breakpoint 9428 * exception (#BP) occurs inside an RTM region while advanced 9429 * debugging of RTM transactional regions is enabled. 9430 */ 9431 if (this_cpu_has(X86_FEATURE_RTM)) { 9432 vmcs_write(ENT_CONTROLS, 9433 vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 9434 /* 9435 * Set DR7.RTM[bit 11] and IA32_DEBUGCTL.RTM[bit 15] 9436 * in the guest to enable advanced debugging of RTM 9437 * transactional regions. 9438 */ 9439 vmcs_write(GUEST_DR7, BIT(11)); 9440 vmcs_write(GUEST_DEBUGCTL, BIT(15)); 9441 single_step_guest("Hardware delivered single-step in " 9442 "transactional region", starting_dr6, 0); 9443 check_db_exit(false, false, false, &xbegin, BIT(16), 9444 starting_dr6); 9445 } else { 9446 vmcs_write(GUEST_RIP, (u64)&skip_rtm); 9447 enter_guest(); 9448 } 9449 } 9450 9451 static void enable_vid(void) 9452 { 9453 void *virtual_apic_page; 9454 9455 assert(cpu_has_apicv()); 9456 9457 disable_intercept_for_x2apic_msrs(); 9458 9459 virtual_apic_page = alloc_page(); 9460 vmcs_write(APIC_VIRT_ADDR, (u64)virtual_apic_page); 9461 9462 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 9463 9464 vmcs_write(EOI_EXIT_BITMAP0, 0x0); 9465 vmcs_write(EOI_EXIT_BITMAP1, 0x0); 9466 vmcs_write(EOI_EXIT_BITMAP2, 0x0); 9467 vmcs_write(EOI_EXIT_BITMAP3, 0x0); 9468 9469 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY | CPU_TPR_SHADOW); 9470 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_VINTD | CPU_VIRT_X2APIC); 9471 } 9472 9473 static void trigger_ioapic_scan_thread(void *data) 9474 { 9475 /* Wait until other CPU entered L2 */ 9476 while (vmx_get_test_stage() != 1) 9477 ; 9478 9479 /* Trigger ioapic scan */ 9480 ioapic_set_redir(0xf, 0x79, TRIGGER_LEVEL); 9481 vmx_set_test_stage(2); 9482 } 9483 9484 static void irq_79_handler_guest(isr_regs_t *regs) 9485 { 9486 eoi(); 9487 9488 /* L1 expects vmexit on VMX_VMCALL and not VMX_EOI_INDUCED */ 9489 vmcall(); 9490 } 9491 9492 /* 9493 * Constant for num of busy-loop iterations after which 9494 * a timer interrupt should have happened in host 9495 */ 9496 #define TIMER_INTERRUPT_DELAY 100000000 9497 9498 static void vmx_eoi_bitmap_ioapic_scan_test_guest(void) 9499 { 9500 handle_irq(0x79, irq_79_handler_guest); 9501 irq_enable(); 9502 9503 /* Signal to L1 CPU to trigger ioapic scan */ 9504 vmx_set_test_stage(1); 9505 /* Wait until L1 CPU to trigger ioapic scan */ 9506 while (vmx_get_test_stage() != 2) 9507 ; 9508 9509 /* 9510 * Wait for L0 timer interrupt to be raised while we run in L2 9511 * such that L0 will process the IOAPIC scan request before 9512 * resuming L2 9513 */ 9514 delay(TIMER_INTERRUPT_DELAY); 9515 9516 asm volatile ("int $0x79"); 9517 } 9518 9519 static void vmx_eoi_bitmap_ioapic_scan_test(void) 9520 { 9521 if (!cpu_has_apicv() || (cpu_count() < 2)) { 9522 report_skip(__func__); 9523 return; 9524 } 9525 9526 enable_vid(); 9527 9528 on_cpu_async(1, trigger_ioapic_scan_thread, NULL); 9529 test_set_guest(vmx_eoi_bitmap_ioapic_scan_test_guest); 9530 9531 /* 9532 * Launch L2. 9533 * We expect the exit reason to be VMX_VMCALL (and not EOI INDUCED). 9534 * In case the reason isn't VMX_VMCALL, the asserion inside 9535 * skip_exit_vmcall() will fail. 9536 */ 9537 enter_guest(); 9538 skip_exit_vmcall(); 9539 9540 /* Let L2 finish */ 9541 enter_guest(); 9542 report_pass(__func__); 9543 } 9544 9545 #define HLT_WITH_RVI_VECTOR (0xf1) 9546 9547 bool vmx_hlt_with_rvi_guest_isr_fired; 9548 static void vmx_hlt_with_rvi_guest_isr(isr_regs_t *regs) 9549 { 9550 vmx_hlt_with_rvi_guest_isr_fired = true; 9551 eoi(); 9552 } 9553 9554 static void vmx_hlt_with_rvi_guest(void) 9555 { 9556 handle_irq(HLT_WITH_RVI_VECTOR, vmx_hlt_with_rvi_guest_isr); 9557 9558 irq_enable(); 9559 asm volatile ("nop"); 9560 9561 vmcall(); 9562 } 9563 9564 static void vmx_hlt_with_rvi_test(void) 9565 { 9566 if (!cpu_has_apicv()) { 9567 report_skip(__func__); 9568 return; 9569 } 9570 9571 enable_vid(); 9572 9573 vmx_hlt_with_rvi_guest_isr_fired = false; 9574 test_set_guest(vmx_hlt_with_rvi_guest); 9575 9576 enter_guest(); 9577 skip_exit_vmcall(); 9578 9579 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 9580 vmcs_write(GUEST_INT_STATUS, HLT_WITH_RVI_VECTOR); 9581 enter_guest(); 9582 9583 report(vmx_hlt_with_rvi_guest_isr_fired, "Interrupt raised in guest"); 9584 } 9585 9586 static void set_irq_line_thread(void *data) 9587 { 9588 /* Wait until other CPU entered L2 */ 9589 while (vmx_get_test_stage() != 1) 9590 ; 9591 9592 /* Set irq-line 0xf to raise vector 0x78 for vCPU 0 */ 9593 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 9594 vmx_set_test_stage(2); 9595 } 9596 9597 static bool irq_78_handler_vmcall_before_eoi; 9598 static void irq_78_handler_guest(isr_regs_t *regs) 9599 { 9600 set_irq_line(0xf, 0); 9601 if (irq_78_handler_vmcall_before_eoi) 9602 vmcall(); 9603 eoi(); 9604 vmcall(); 9605 } 9606 9607 static void vmx_apic_passthrough_guest(void) 9608 { 9609 handle_irq(0x78, irq_78_handler_guest); 9610 irq_enable(); 9611 9612 /* If requested, wait for other CPU to trigger ioapic scan */ 9613 if (vmx_get_test_stage() < 1) { 9614 vmx_set_test_stage(1); 9615 while (vmx_get_test_stage() != 2) 9616 ; 9617 } 9618 9619 set_irq_line(0xf, 1); 9620 } 9621 9622 static void vmx_apic_passthrough(bool set_irq_line_from_thread) 9623 { 9624 if (set_irq_line_from_thread && (cpu_count() < 2)) { 9625 report_skip(__func__); 9626 return; 9627 } 9628 9629 /* Test device is required for generating IRQs */ 9630 if (!test_device_enabled()) { 9631 report_skip(__func__); 9632 return; 9633 } 9634 u64 cpu_ctrl_0 = CPU_SECONDARY; 9635 u64 cpu_ctrl_1 = 0; 9636 9637 disable_intercept_for_x2apic_msrs(); 9638 9639 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 9640 9641 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 9642 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 9643 9644 if (set_irq_line_from_thread) { 9645 irq_78_handler_vmcall_before_eoi = false; 9646 on_cpu_async(1, set_irq_line_thread, NULL); 9647 } else { 9648 irq_78_handler_vmcall_before_eoi = true; 9649 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 9650 vmx_set_test_stage(2); 9651 } 9652 test_set_guest(vmx_apic_passthrough_guest); 9653 9654 if (irq_78_handler_vmcall_before_eoi) { 9655 /* Before EOI remote_irr should still be set */ 9656 enter_guest(); 9657 skip_exit_vmcall(); 9658 TEST_ASSERT_EQ_MSG(1, (int)ioapic_read_redir(0xf).remote_irr, 9659 "IOAPIC pass-through: remote_irr=1 before EOI"); 9660 } 9661 9662 /* After EOI remote_irr should be cleared */ 9663 enter_guest(); 9664 skip_exit_vmcall(); 9665 TEST_ASSERT_EQ_MSG(0, (int)ioapic_read_redir(0xf).remote_irr, 9666 "IOAPIC pass-through: remote_irr=0 after EOI"); 9667 9668 /* Let L2 finish */ 9669 enter_guest(); 9670 report_pass(__func__); 9671 } 9672 9673 static void vmx_apic_passthrough_test(void) 9674 { 9675 vmx_apic_passthrough(false); 9676 } 9677 9678 static void vmx_apic_passthrough_thread_test(void) 9679 { 9680 vmx_apic_passthrough(true); 9681 } 9682 9683 static void vmx_apic_passthrough_tpr_threshold_guest(void) 9684 { 9685 cli(); 9686 apic_set_tpr(0); 9687 } 9688 9689 static bool vmx_apic_passthrough_tpr_threshold_ipi_isr_fired; 9690 static void vmx_apic_passthrough_tpr_threshold_ipi_isr(isr_regs_t *regs) 9691 { 9692 vmx_apic_passthrough_tpr_threshold_ipi_isr_fired = true; 9693 eoi(); 9694 } 9695 9696 static void vmx_apic_passthrough_tpr_threshold_test(void) 9697 { 9698 int ipi_vector = 0xe1; 9699 9700 disable_intercept_for_x2apic_msrs(); 9701 vmcs_clear_bits(PIN_CONTROLS, PIN_EXTINT); 9702 9703 /* Raise L0 TPR-threshold by queueing vector in LAPIC IRR */ 9704 cli(); 9705 apic_set_tpr((ipi_vector >> 4) + 1); 9706 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | 9707 APIC_DM_FIXED | ipi_vector, 9708 0); 9709 9710 test_set_guest(vmx_apic_passthrough_tpr_threshold_guest); 9711 enter_guest(); 9712 9713 report(apic_get_tpr() == 0, "TPR was zero by guest"); 9714 9715 /* Clean pending self-IPI */ 9716 vmx_apic_passthrough_tpr_threshold_ipi_isr_fired = false; 9717 handle_irq(ipi_vector, vmx_apic_passthrough_tpr_threshold_ipi_isr); 9718 sti(); 9719 asm volatile ("nop"); 9720 report(vmx_apic_passthrough_tpr_threshold_ipi_isr_fired, "self-IPI fired"); 9721 9722 report_pass(__func__); 9723 } 9724 9725 static u64 init_signal_test_exit_reason; 9726 static bool init_signal_test_thread_continued; 9727 9728 static void init_signal_test_thread(void *data) 9729 { 9730 struct vmcs *test_vmcs = data; 9731 9732 /* Enter VMX operation (i.e. exec VMXON) */ 9733 u64 *ap_vmxon_region = alloc_page(); 9734 enable_vmx(); 9735 init_vmx(ap_vmxon_region); 9736 _vmx_on(ap_vmxon_region); 9737 9738 /* Signal CPU have entered VMX operation */ 9739 vmx_set_test_stage(1); 9740 9741 /* Wait for BSP CPU to send INIT signal */ 9742 while (vmx_get_test_stage() != 2) 9743 ; 9744 9745 /* 9746 * Signal that we continue as usual as INIT signal 9747 * should be blocked while CPU is in VMX operation 9748 */ 9749 vmx_set_test_stage(3); 9750 9751 /* Wait for signal to enter VMX non-root mode */ 9752 while (vmx_get_test_stage() != 4) 9753 ; 9754 9755 /* Enter VMX non-root mode */ 9756 test_set_guest(v2_null_test_guest); 9757 make_vmcs_current(test_vmcs); 9758 enter_guest(); 9759 /* Save exit reason for BSP CPU to compare to expected result */ 9760 init_signal_test_exit_reason = vmcs_read(EXI_REASON); 9761 /* VMCLEAR test-vmcs so it could be loaded by BSP CPU */ 9762 vmcs_clear(test_vmcs); 9763 launched = false; 9764 /* Signal that CPU exited to VMX root mode */ 9765 vmx_set_test_stage(5); 9766 9767 /* Wait for BSP CPU to signal to exit VMX operation */ 9768 while (vmx_get_test_stage() != 6) 9769 ; 9770 9771 /* Exit VMX operation (i.e. exec VMXOFF) */ 9772 vmx_off(); 9773 9774 /* 9775 * Signal to BSP CPU that we continue as usual as INIT signal 9776 * should have been consumed by VMX_INIT exit from guest 9777 */ 9778 vmx_set_test_stage(7); 9779 9780 /* Wait for BSP CPU to signal to enter VMX operation */ 9781 while (vmx_get_test_stage() != 8) 9782 ; 9783 /* Enter VMX operation (i.e. exec VMXON) */ 9784 _vmx_on(ap_vmxon_region); 9785 /* Signal to BSP we are in VMX operation */ 9786 vmx_set_test_stage(9); 9787 9788 /* Wait for BSP CPU to send INIT signal */ 9789 while (vmx_get_test_stage() != 10) 9790 ; 9791 9792 /* Exit VMX operation (i.e. exec VMXOFF) */ 9793 vmx_off(); 9794 9795 /* 9796 * Exiting VMX operation should result in latched 9797 * INIT signal being processed. Therefore, we should 9798 * never reach the below code. Thus, signal to BSP 9799 * CPU if we have reached here so it is able to 9800 * report an issue if it happens. 9801 */ 9802 init_signal_test_thread_continued = true; 9803 } 9804 9805 #define INIT_SIGNAL_TEST_DELAY 100000000ULL 9806 9807 static void vmx_init_signal_test(void) 9808 { 9809 struct vmcs *test_vmcs; 9810 9811 if (cpu_count() < 2) { 9812 report_skip(__func__); 9813 return; 9814 } 9815 9816 /* VMCLEAR test-vmcs so it could be loaded by other CPU */ 9817 vmcs_save(&test_vmcs); 9818 vmcs_clear(test_vmcs); 9819 9820 vmx_set_test_stage(0); 9821 on_cpu_async(1, init_signal_test_thread, test_vmcs); 9822 9823 /* Wait for other CPU to enter VMX operation */ 9824 while (vmx_get_test_stage() != 1) 9825 ; 9826 9827 /* Send INIT signal to other CPU */ 9828 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_INIT | APIC_INT_ASSERT, 9829 id_map[1]); 9830 /* Signal other CPU we have sent INIT signal */ 9831 vmx_set_test_stage(2); 9832 9833 /* 9834 * Wait reasonable amount of time for INIT signal to 9835 * be received on other CPU and verify that other CPU 9836 * have proceed as usual to next test stage as INIT 9837 * signal should be blocked while other CPU in 9838 * VMX operation 9839 */ 9840 delay(INIT_SIGNAL_TEST_DELAY); 9841 report(vmx_get_test_stage() == 3, 9842 "INIT signal blocked when CPU in VMX operation"); 9843 /* No point to continue if we failed at this point */ 9844 if (vmx_get_test_stage() != 3) 9845 return; 9846 9847 /* Signal other CPU to enter VMX non-root mode */ 9848 init_signal_test_exit_reason = -1ull; 9849 vmx_set_test_stage(4); 9850 /* 9851 * Wait reasonable amont of time for other CPU 9852 * to exit to VMX root mode 9853 */ 9854 delay(INIT_SIGNAL_TEST_DELAY); 9855 if (vmx_get_test_stage() != 5) { 9856 report_fail("Pending INIT signal didn't result in VMX exit"); 9857 return; 9858 } 9859 report(init_signal_test_exit_reason == VMX_INIT, 9860 "INIT signal during VMX non-root mode result in exit-reason %s (%lu)", 9861 exit_reason_description(init_signal_test_exit_reason), 9862 init_signal_test_exit_reason); 9863 9864 /* Run guest to completion */ 9865 make_vmcs_current(test_vmcs); 9866 enter_guest(); 9867 9868 /* Signal other CPU to exit VMX operation */ 9869 init_signal_test_thread_continued = false; 9870 vmx_set_test_stage(6); 9871 9872 /* Wait reasonable amount of time for other CPU to exit VMX operation */ 9873 delay(INIT_SIGNAL_TEST_DELAY); 9874 report(vmx_get_test_stage() == 7, 9875 "INIT signal consumed on VMX_INIT exit"); 9876 /* No point to continue if we failed at this point */ 9877 if (vmx_get_test_stage() != 7) 9878 return; 9879 9880 /* Signal other CPU to enter VMX operation */ 9881 vmx_set_test_stage(8); 9882 /* Wait for other CPU to enter VMX operation */ 9883 while (vmx_get_test_stage() != 9) 9884 ; 9885 9886 /* Send INIT signal to other CPU */ 9887 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_INIT | APIC_INT_ASSERT, 9888 id_map[1]); 9889 /* Signal other CPU we have sent INIT signal */ 9890 vmx_set_test_stage(10); 9891 9892 /* 9893 * Wait reasonable amount of time for other CPU 9894 * to exit VMX operation and process INIT signal 9895 */ 9896 delay(INIT_SIGNAL_TEST_DELAY); 9897 report(!init_signal_test_thread_continued, 9898 "INIT signal processed after exit VMX operation"); 9899 9900 /* 9901 * TODO: Send SIPI to other CPU to sipi_entry (See x86/cstart64.S) 9902 * to re-init it to kvm-unit-tests standard environment. 9903 * Somehow (?) verify that SIPI was indeed received. 9904 */ 9905 } 9906 9907 #define SIPI_SIGNAL_TEST_DELAY 100000000ULL 9908 9909 static void vmx_sipi_test_guest(void) 9910 { 9911 if (apic_id() == 0) { 9912 /* wait AP enter guest with activity=WAIT_SIPI */ 9913 while (vmx_get_test_stage() != 1) 9914 ; 9915 delay(SIPI_SIGNAL_TEST_DELAY); 9916 9917 /* First SIPI signal */ 9918 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_STARTUP | APIC_INT_ASSERT, id_map[1]); 9919 report_pass("BSP(L2): Send first SIPI to cpu[%d]", id_map[1]); 9920 9921 /* wait AP enter guest */ 9922 while (vmx_get_test_stage() != 2) 9923 ; 9924 delay(SIPI_SIGNAL_TEST_DELAY); 9925 9926 /* Second SIPI signal should be ignored since AP is not in WAIT_SIPI state */ 9927 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_STARTUP | APIC_INT_ASSERT, id_map[1]); 9928 report_pass("BSP(L2): Send second SIPI to cpu[%d]", id_map[1]); 9929 9930 /* Delay a while to check whether second SIPI would cause VMExit */ 9931 delay(SIPI_SIGNAL_TEST_DELAY); 9932 9933 /* Test is done, notify AP to exit test */ 9934 vmx_set_test_stage(3); 9935 9936 /* wait AP exit non-root mode */ 9937 while (vmx_get_test_stage() != 5) 9938 ; 9939 } else { 9940 /* wait BSP notify test is done */ 9941 while (vmx_get_test_stage() != 3) 9942 ; 9943 9944 /* AP exit guest */ 9945 vmx_set_test_stage(4); 9946 } 9947 } 9948 9949 static void sipi_test_ap_thread(void *data) 9950 { 9951 struct vmcs *ap_vmcs; 9952 u64 *ap_vmxon_region; 9953 void *ap_stack, *ap_syscall_stack; 9954 u64 cpu_ctrl_0 = CPU_SECONDARY; 9955 u64 cpu_ctrl_1 = 0; 9956 9957 /* Enter VMX operation (i.e. exec VMXON) */ 9958 ap_vmxon_region = alloc_page(); 9959 enable_vmx(); 9960 init_vmx(ap_vmxon_region); 9961 _vmx_on(ap_vmxon_region); 9962 init_vmcs(&ap_vmcs); 9963 make_vmcs_current(ap_vmcs); 9964 9965 /* Set stack for AP */ 9966 ap_stack = alloc_page(); 9967 ap_syscall_stack = alloc_page(); 9968 vmcs_write(GUEST_RSP, (u64)(ap_stack + PAGE_SIZE - 1)); 9969 vmcs_write(GUEST_SYSENTER_ESP, (u64)(ap_syscall_stack + PAGE_SIZE - 1)); 9970 9971 /* passthrough lapic to L2 */ 9972 disable_intercept_for_x2apic_msrs(); 9973 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 9974 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 9975 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 9976 9977 /* Set guest activity state to wait-for-SIPI state */ 9978 vmcs_write(GUEST_ACTV_STATE, ACTV_WAIT_SIPI); 9979 9980 vmx_set_test_stage(1); 9981 9982 /* AP enter guest */ 9983 enter_guest(); 9984 9985 if (vmcs_read(EXI_REASON) == VMX_SIPI) { 9986 report_pass("AP: Handle SIPI VMExit"); 9987 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 9988 vmx_set_test_stage(2); 9989 } else { 9990 report_fail("AP: Unexpected VMExit, reason=%ld", vmcs_read(EXI_REASON)); 9991 vmx_off(); 9992 return; 9993 } 9994 9995 /* AP enter guest */ 9996 enter_guest(); 9997 9998 report(vmcs_read(EXI_REASON) != VMX_SIPI, 9999 "AP: should no SIPI VMExit since activity is not in WAIT_SIPI state"); 10000 10001 /* notify BSP that AP is already exit from non-root mode */ 10002 vmx_set_test_stage(5); 10003 10004 /* Leave VMX operation */ 10005 vmx_off(); 10006 } 10007 10008 static void vmx_sipi_signal_test(void) 10009 { 10010 if (!(rdmsr(MSR_IA32_VMX_MISC) & MSR_IA32_VMX_MISC_ACTIVITY_WAIT_SIPI)) { 10011 printf("\tACTIVITY_WAIT_SIPI state is not supported.\n"); 10012 return; 10013 } 10014 10015 if (cpu_count() < 2) { 10016 report_skip(__func__); 10017 return; 10018 } 10019 10020 u64 cpu_ctrl_0 = CPU_SECONDARY; 10021 u64 cpu_ctrl_1 = 0; 10022 10023 /* passthrough lapic to L2 */ 10024 disable_intercept_for_x2apic_msrs(); 10025 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 10026 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 10027 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 10028 10029 test_set_guest(vmx_sipi_test_guest); 10030 10031 /* update CR3 on AP */ 10032 on_cpu(1, update_cr3, (void *)read_cr3()); 10033 10034 /* start AP */ 10035 on_cpu_async(1, sipi_test_ap_thread, NULL); 10036 10037 vmx_set_test_stage(0); 10038 10039 /* BSP enter guest */ 10040 enter_guest(); 10041 } 10042 10043 10044 enum vmcs_access { 10045 ACCESS_VMREAD, 10046 ACCESS_VMWRITE, 10047 ACCESS_NONE, 10048 }; 10049 10050 struct vmcs_shadow_test_common { 10051 enum vmcs_access op; 10052 enum Reason reason; 10053 u64 field; 10054 u64 value; 10055 u64 flags; 10056 u64 time; 10057 } l1_l2_common; 10058 10059 static inline u64 vmread_flags(u64 field, u64 *val) 10060 { 10061 u64 flags; 10062 10063 asm volatile ("vmread %2, %1; pushf; pop %0" 10064 : "=r" (flags), "=rm" (*val) : "r" (field) : "cc"); 10065 return flags & X86_EFLAGS_ALU; 10066 } 10067 10068 static inline u64 vmwrite_flags(u64 field, u64 val) 10069 { 10070 u64 flags; 10071 10072 asm volatile ("vmwrite %1, %2; pushf; pop %0" 10073 : "=r"(flags) : "rm" (val), "r" (field) : "cc"); 10074 return flags & X86_EFLAGS_ALU; 10075 } 10076 10077 static void vmx_vmcs_shadow_test_guest(void) 10078 { 10079 struct vmcs_shadow_test_common *c = &l1_l2_common; 10080 u64 start; 10081 10082 while (c->op != ACCESS_NONE) { 10083 start = rdtsc(); 10084 switch (c->op) { 10085 default: 10086 c->flags = -1ull; 10087 break; 10088 case ACCESS_VMREAD: 10089 c->flags = vmread_flags(c->field, &c->value); 10090 break; 10091 case ACCESS_VMWRITE: 10092 c->flags = vmwrite_flags(c->field, 0); 10093 break; 10094 } 10095 c->time = rdtsc() - start; 10096 vmcall(); 10097 } 10098 } 10099 10100 static u64 vmread_from_shadow(u64 field) 10101 { 10102 struct vmcs *primary; 10103 struct vmcs *shadow; 10104 u64 value; 10105 10106 TEST_ASSERT(!vmcs_save(&primary)); 10107 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 10108 TEST_ASSERT(!make_vmcs_current(shadow)); 10109 value = vmcs_read(field); 10110 TEST_ASSERT(!make_vmcs_current(primary)); 10111 return value; 10112 } 10113 10114 static u64 vmwrite_to_shadow(u64 field, u64 value) 10115 { 10116 struct vmcs *primary; 10117 struct vmcs *shadow; 10118 10119 TEST_ASSERT(!vmcs_save(&primary)); 10120 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 10121 TEST_ASSERT(!make_vmcs_current(shadow)); 10122 vmcs_write(field, value); 10123 value = vmcs_read(field); 10124 TEST_ASSERT(!make_vmcs_current(primary)); 10125 return value; 10126 } 10127 10128 static void vmcs_shadow_test_access(u8 *bitmap[2], enum vmcs_access access) 10129 { 10130 struct vmcs_shadow_test_common *c = &l1_l2_common; 10131 10132 c->op = access; 10133 vmcs_write(VMX_INST_ERROR, 0); 10134 enter_guest(); 10135 c->reason = vmcs_read(EXI_REASON) & 0xffff; 10136 if (c->reason != VMX_VMCALL) { 10137 skip_exit_insn(); 10138 enter_guest(); 10139 } 10140 skip_exit_vmcall(); 10141 } 10142 10143 static void vmcs_shadow_test_field(u8 *bitmap[2], u64 field) 10144 { 10145 struct vmcs_shadow_test_common *c = &l1_l2_common; 10146 struct vmcs *shadow; 10147 u64 value; 10148 uintptr_t flags[2]; 10149 bool good_shadow; 10150 u32 vmx_inst_error; 10151 10152 report_prefix_pushf("field %lx", field); 10153 c->field = field; 10154 10155 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 10156 if (shadow != (struct vmcs *)-1ull) { 10157 flags[ACCESS_VMREAD] = vmread_flags(field, &value); 10158 flags[ACCESS_VMWRITE] = vmwrite_flags(field, value); 10159 good_shadow = !flags[ACCESS_VMREAD] && !flags[ACCESS_VMWRITE]; 10160 } else { 10161 /* 10162 * When VMCS link pointer is -1ull, VMWRITE/VMREAD on 10163 * shadowed-fields should fail with setting RFLAGS.CF. 10164 */ 10165 flags[ACCESS_VMREAD] = X86_EFLAGS_CF; 10166 flags[ACCESS_VMWRITE] = X86_EFLAGS_CF; 10167 good_shadow = false; 10168 } 10169 10170 /* Intercept both VMREAD and VMWRITE. */ 10171 report_prefix_push("no VMREAD/VMWRITE permission"); 10172 /* VMWRITE/VMREAD done on reserved-bit should always intercept */ 10173 if (!(field >> VMCS_FIELD_RESERVED_SHIFT)) { 10174 set_bit(field, bitmap[ACCESS_VMREAD]); 10175 set_bit(field, bitmap[ACCESS_VMWRITE]); 10176 } 10177 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10178 report(c->reason == VMX_VMWRITE, "not shadowed for VMWRITE"); 10179 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10180 report(c->reason == VMX_VMREAD, "not shadowed for VMREAD"); 10181 report_prefix_pop(); 10182 10183 if (field >> VMCS_FIELD_RESERVED_SHIFT) 10184 goto out; 10185 10186 /* Permit shadowed VMREAD. */ 10187 report_prefix_push("VMREAD permission only"); 10188 clear_bit(field, bitmap[ACCESS_VMREAD]); 10189 set_bit(field, bitmap[ACCESS_VMWRITE]); 10190 if (good_shadow) 10191 value = vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 10192 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10193 report(c->reason == VMX_VMWRITE, "not shadowed for VMWRITE"); 10194 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10195 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10196 report(c->reason == VMX_VMCALL, "shadowed for VMREAD (in %ld cycles)", 10197 c->time); 10198 report(c->flags == flags[ACCESS_VMREAD], 10199 "ALU flags after VMREAD (%lx) are as expected (%lx)", 10200 c->flags, flags[ACCESS_VMREAD]); 10201 if (good_shadow) 10202 report(c->value == value, 10203 "value read from shadow (%lx) is as expected (%lx)", 10204 c->value, value); 10205 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 10206 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10207 "VMX_INST_ERROR (%d) is as expected (%d)", 10208 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10209 report_prefix_pop(); 10210 10211 /* Permit shadowed VMWRITE. */ 10212 report_prefix_push("VMWRITE permission only"); 10213 set_bit(field, bitmap[ACCESS_VMREAD]); 10214 clear_bit(field, bitmap[ACCESS_VMWRITE]); 10215 if (good_shadow) 10216 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 10217 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10218 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10219 report(c->reason == VMX_VMCALL, 10220 "shadowed for VMWRITE (in %ld cycles)", 10221 c->time); 10222 report(c->flags == flags[ACCESS_VMREAD], 10223 "ALU flags after VMWRITE (%lx) are as expected (%lx)", 10224 c->flags, flags[ACCESS_VMREAD]); 10225 if (good_shadow) { 10226 value = vmread_from_shadow(field); 10227 report(value == 0, 10228 "shadow VMCS value (%lx) is as expected (%lx)", value, 10229 0ul); 10230 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 10231 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10232 "VMX_INST_ERROR (%d) is as expected (%d)", 10233 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10234 } 10235 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10236 report(c->reason == VMX_VMREAD, "not shadowed for VMREAD"); 10237 report_prefix_pop(); 10238 10239 /* Permit shadowed VMREAD and VMWRITE. */ 10240 report_prefix_push("VMREAD and VMWRITE permission"); 10241 clear_bit(field, bitmap[ACCESS_VMREAD]); 10242 clear_bit(field, bitmap[ACCESS_VMWRITE]); 10243 if (good_shadow) 10244 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 10245 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10246 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10247 report(c->reason == VMX_VMCALL, 10248 "shadowed for VMWRITE (in %ld cycles)", 10249 c->time); 10250 report(c->flags == flags[ACCESS_VMREAD], 10251 "ALU flags after VMWRITE (%lx) are as expected (%lx)", 10252 c->flags, flags[ACCESS_VMREAD]); 10253 if (good_shadow) { 10254 value = vmread_from_shadow(field); 10255 report(value == 0, 10256 "shadow VMCS value (%lx) is as expected (%lx)", value, 10257 0ul); 10258 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 10259 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10260 "VMX_INST_ERROR (%d) is as expected (%d)", 10261 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10262 } 10263 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10264 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10265 report(c->reason == VMX_VMCALL, "shadowed for VMREAD (in %ld cycles)", 10266 c->time); 10267 report(c->flags == flags[ACCESS_VMREAD], 10268 "ALU flags after VMREAD (%lx) are as expected (%lx)", 10269 c->flags, flags[ACCESS_VMREAD]); 10270 if (good_shadow) 10271 report(c->value == 0, 10272 "value read from shadow (%lx) is as expected (%lx)", 10273 c->value, 0ul); 10274 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 10275 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10276 "VMX_INST_ERROR (%d) is as expected (%d)", 10277 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10278 report_prefix_pop(); 10279 10280 out: 10281 report_prefix_pop(); 10282 } 10283 10284 static void vmx_vmcs_shadow_test_body(u8 *bitmap[2]) 10285 { 10286 unsigned base; 10287 unsigned index; 10288 unsigned bit; 10289 unsigned highest_index = rdmsr(MSR_IA32_VMX_VMCS_ENUM); 10290 10291 /* Run test on all possible valid VMCS fields */ 10292 for (base = 0; 10293 base < (1 << VMCS_FIELD_RESERVED_SHIFT); 10294 base += (1 << VMCS_FIELD_TYPE_SHIFT)) 10295 for (index = 0; index <= highest_index; index++) 10296 vmcs_shadow_test_field(bitmap, base + index); 10297 10298 /* 10299 * Run tests on some invalid VMCS fields 10300 * (Have reserved bit set). 10301 */ 10302 for (bit = VMCS_FIELD_RESERVED_SHIFT; bit < VMCS_FIELD_BIT_SIZE; bit++) 10303 vmcs_shadow_test_field(bitmap, (1ull << bit)); 10304 } 10305 10306 static void vmx_vmcs_shadow_test(void) 10307 { 10308 u8 *bitmap[2]; 10309 struct vmcs *shadow; 10310 10311 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 10312 printf("\t'Activate secondary controls' not supported.\n"); 10313 return; 10314 } 10315 10316 if (!(ctrl_cpu_rev[1].clr & CPU_SHADOW_VMCS)) { 10317 printf("\t'VMCS shadowing' not supported.\n"); 10318 return; 10319 } 10320 10321 if (!(rdmsr(MSR_IA32_VMX_MISC) & 10322 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS)) { 10323 printf("\tVMWRITE can't modify VM-exit information fields.\n"); 10324 return; 10325 } 10326 10327 test_set_guest(vmx_vmcs_shadow_test_guest); 10328 10329 bitmap[ACCESS_VMREAD] = alloc_page(); 10330 bitmap[ACCESS_VMWRITE] = alloc_page(); 10331 10332 vmcs_write(VMREAD_BITMAP, virt_to_phys(bitmap[ACCESS_VMREAD])); 10333 vmcs_write(VMWRITE_BITMAP, virt_to_phys(bitmap[ACCESS_VMWRITE])); 10334 10335 shadow = alloc_page(); 10336 shadow->hdr.revision_id = basic.revision; 10337 shadow->hdr.shadow_vmcs = 1; 10338 TEST_ASSERT(!vmcs_clear(shadow)); 10339 10340 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_RDTSC); 10341 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY); 10342 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_SHADOW_VMCS); 10343 10344 vmcs_write(VMCS_LINK_PTR, virt_to_phys(shadow)); 10345 report_prefix_push("valid link pointer"); 10346 vmx_vmcs_shadow_test_body(bitmap); 10347 report_prefix_pop(); 10348 10349 vmcs_write(VMCS_LINK_PTR, -1ull); 10350 report_prefix_push("invalid link pointer"); 10351 vmx_vmcs_shadow_test_body(bitmap); 10352 report_prefix_pop(); 10353 10354 l1_l2_common.op = ACCESS_NONE; 10355 enter_guest(); 10356 } 10357 10358 /* 10359 * This test monitors the difference between a guest RDTSC instruction 10360 * and the IA32_TIME_STAMP_COUNTER MSR value stored in the VMCS12 10361 * VM-exit MSR-store list when taking a VM-exit on the instruction 10362 * following RDTSC. 10363 */ 10364 #define RDTSC_DIFF_ITERS 100000 10365 #define RDTSC_DIFF_FAILS 100 10366 #define HOST_CAPTURED_GUEST_TSC_DIFF_THRESHOLD 750 10367 10368 /* 10369 * Set 'use TSC offsetting' and set the guest offset to the 10370 * inverse of the host's current TSC value, so that the guest starts running 10371 * with an effective TSC value of 0. 10372 */ 10373 static void reset_guest_tsc_to_zero(void) 10374 { 10375 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_USE_TSC_OFFSET); 10376 vmcs_write(TSC_OFFSET, -rdtsc()); 10377 } 10378 10379 static void rdtsc_vmexit_diff_test_guest(void) 10380 { 10381 int i; 10382 10383 for (i = 0; i < RDTSC_DIFF_ITERS; i++) 10384 /* Ensure rdtsc is the last instruction before the vmcall. */ 10385 asm volatile("rdtsc; vmcall" : : : "eax", "edx"); 10386 } 10387 10388 /* 10389 * This function only considers the "use TSC offsetting" VM-execution 10390 * control. It does not handle "use TSC scaling" (because the latter 10391 * isn't available to the host today.) 10392 */ 10393 static unsigned long long host_time_to_guest_time(unsigned long long t) 10394 { 10395 TEST_ASSERT(!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 10396 !(vmcs_read(CPU_EXEC_CTRL1) & CPU_USE_TSC_SCALING)); 10397 10398 if (vmcs_read(CPU_EXEC_CTRL0) & CPU_USE_TSC_OFFSET) 10399 t += vmcs_read(TSC_OFFSET); 10400 10401 return t; 10402 } 10403 10404 static unsigned long long rdtsc_vmexit_diff_test_iteration(void) 10405 { 10406 unsigned long long guest_tsc, host_to_guest_tsc; 10407 10408 enter_guest(); 10409 skip_exit_vmcall(); 10410 guest_tsc = (u32) regs.rax + (regs.rdx << 32); 10411 host_to_guest_tsc = host_time_to_guest_time(exit_msr_store[0].value); 10412 10413 return host_to_guest_tsc - guest_tsc; 10414 } 10415 10416 static void rdtsc_vmexit_diff_test(void) 10417 { 10418 unsigned long long delta; 10419 int fail = 0; 10420 int i; 10421 10422 if (!(ctrl_cpu_rev[0].clr & CPU_USE_TSC_OFFSET)) 10423 test_skip("CPU doesn't support the 'use TSC offsetting' processor-based VM-execution control.\n"); 10424 10425 test_set_guest(rdtsc_vmexit_diff_test_guest); 10426 10427 reset_guest_tsc_to_zero(); 10428 10429 /* 10430 * Set up the VMCS12 VM-exit MSR-store list to store just one 10431 * MSR: IA32_TIME_STAMP_COUNTER. Note that the value stored is 10432 * in the host time domain (i.e., it is not adjusted according 10433 * to the TSC multiplier and TSC offset fields in the VMCS12, 10434 * as a guest RDTSC would be.) 10435 */ 10436 exit_msr_store = alloc_page(); 10437 exit_msr_store[0].index = MSR_IA32_TSC; 10438 vmcs_write(EXI_MSR_ST_CNT, 1); 10439 vmcs_write(EXIT_MSR_ST_ADDR, virt_to_phys(exit_msr_store)); 10440 10441 for (i = 0; i < RDTSC_DIFF_ITERS && fail < RDTSC_DIFF_FAILS; i++) { 10442 delta = rdtsc_vmexit_diff_test_iteration(); 10443 if (delta >= HOST_CAPTURED_GUEST_TSC_DIFF_THRESHOLD) 10444 fail++; 10445 } 10446 10447 enter_guest(); 10448 10449 report(fail < RDTSC_DIFF_FAILS, 10450 "RDTSC to VM-exit delta too high in %d of %d iterations, last = %llu", 10451 fail, i, delta); 10452 } 10453 10454 static int invalid_msr_init(struct vmcs *vmcs) 10455 { 10456 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 10457 printf("\tPreemption timer is not supported\n"); 10458 return VMX_TEST_EXIT; 10459 } 10460 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 10461 preempt_val = 10000000; 10462 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 10463 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 10464 10465 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 10466 printf("\tSave preemption value is not supported\n"); 10467 10468 vmcs_write(ENT_MSR_LD_CNT, 1); 10469 vmcs_write(ENTER_MSR_LD_ADDR, (u64)0x13370000); 10470 10471 return VMX_TEST_START; 10472 } 10473 10474 10475 static void invalid_msr_main(void) 10476 { 10477 report_fail("Invalid MSR load"); 10478 } 10479 10480 static int invalid_msr_exit_handler(union exit_reason exit_reason) 10481 { 10482 report_fail("Invalid MSR load"); 10483 print_vmexit_info(exit_reason); 10484 return VMX_TEST_EXIT; 10485 } 10486 10487 static int invalid_msr_entry_failure(struct vmentry_result *result) 10488 { 10489 report(result->exit_reason.failed_vmentry && 10490 result->exit_reason.basic == VMX_FAIL_MSR, "Invalid MSR load"); 10491 return VMX_TEST_VMEXIT; 10492 } 10493 10494 /* 10495 * The max number of MSRs in an atomic switch MSR list is: 10496 * (111B + 1) * 512 = 4096 10497 * 10498 * Each list entry consumes: 10499 * 4-byte MSR index + 4 bytes reserved + 8-byte data = 16 bytes 10500 * 10501 * Allocate 128 kB to cover max_msr_list_size (i.e., 64 kB) and then some. 10502 */ 10503 static const u32 msr_list_page_order = 5; 10504 10505 static void atomic_switch_msr_limit_test_guest(void) 10506 { 10507 vmcall(); 10508 } 10509 10510 static void populate_msr_list(struct vmx_msr_entry *msr_list, 10511 size_t byte_capacity, int count) 10512 { 10513 int i; 10514 10515 for (i = 0; i < count; i++) { 10516 msr_list[i].index = MSR_IA32_TSC; 10517 msr_list[i].reserved = 0; 10518 msr_list[i].value = 0x1234567890abcdef; 10519 } 10520 10521 memset(msr_list + count, 0xff, 10522 byte_capacity - count * sizeof(*msr_list)); 10523 } 10524 10525 static int max_msr_list_size(void) 10526 { 10527 u32 vmx_misc = rdmsr(MSR_IA32_VMX_MISC); 10528 u32 factor = ((vmx_misc & GENMASK(27, 25)) >> 25) + 1; 10529 10530 return factor * 512; 10531 } 10532 10533 static void atomic_switch_msrs_test(int count) 10534 { 10535 struct vmx_msr_entry *vm_enter_load; 10536 struct vmx_msr_entry *vm_exit_load; 10537 struct vmx_msr_entry *vm_exit_store; 10538 int max_allowed = max_msr_list_size(); 10539 int byte_capacity = 1ul << (msr_list_page_order + PAGE_SHIFT); 10540 /* Exceeding the max MSR list size at exit trigers KVM to abort. */ 10541 int exit_count = count > max_allowed ? max_allowed : count; 10542 int cleanup_count = count > max_allowed ? 2 : 1; 10543 int i; 10544 10545 /* 10546 * Check for the IA32_TSC MSR, 10547 * available with the "TSC flag" and used to populate the MSR lists. 10548 */ 10549 if (!(cpuid(1).d & (1 << 4))) { 10550 report_skip(__func__); 10551 return; 10552 } 10553 10554 /* Set L2 guest. */ 10555 test_set_guest(atomic_switch_msr_limit_test_guest); 10556 10557 /* Setup atomic MSR switch lists. */ 10558 vm_enter_load = alloc_pages(msr_list_page_order); 10559 vm_exit_load = alloc_pages(msr_list_page_order); 10560 vm_exit_store = alloc_pages(msr_list_page_order); 10561 10562 vmcs_write(ENTER_MSR_LD_ADDR, (u64)vm_enter_load); 10563 vmcs_write(EXIT_MSR_LD_ADDR, (u64)vm_exit_load); 10564 vmcs_write(EXIT_MSR_ST_ADDR, (u64)vm_exit_store); 10565 10566 /* 10567 * VM-Enter should succeed up to the max number of MSRs per list, and 10568 * should not consume junk beyond the last entry. 10569 */ 10570 populate_msr_list(vm_enter_load, byte_capacity, count); 10571 populate_msr_list(vm_exit_load, byte_capacity, exit_count); 10572 populate_msr_list(vm_exit_store, byte_capacity, exit_count); 10573 10574 vmcs_write(ENT_MSR_LD_CNT, count); 10575 vmcs_write(EXI_MSR_LD_CNT, exit_count); 10576 vmcs_write(EXI_MSR_ST_CNT, exit_count); 10577 10578 if (count <= max_allowed) { 10579 enter_guest(); 10580 assert_exit_reason(VMX_VMCALL); 10581 skip_exit_vmcall(); 10582 } else { 10583 u32 exit_qual; 10584 10585 test_guest_state("Invalid MSR Load Count", true, count, 10586 "ENT_MSR_LD_CNT"); 10587 10588 exit_qual = vmcs_read(EXI_QUALIFICATION); 10589 report(exit_qual == max_allowed + 1, "exit_qual, %u, is %u.", 10590 exit_qual, max_allowed + 1); 10591 } 10592 10593 /* Cleanup. */ 10594 vmcs_write(ENT_MSR_LD_CNT, 0); 10595 vmcs_write(EXI_MSR_LD_CNT, 0); 10596 vmcs_write(EXI_MSR_ST_CNT, 0); 10597 for (i = 0; i < cleanup_count; i++) { 10598 enter_guest(); 10599 skip_exit_vmcall(); 10600 } 10601 free_pages_by_order(vm_enter_load, msr_list_page_order); 10602 free_pages_by_order(vm_exit_load, msr_list_page_order); 10603 free_pages_by_order(vm_exit_store, msr_list_page_order); 10604 } 10605 10606 static void atomic_switch_max_msrs_test(void) 10607 { 10608 atomic_switch_msrs_test(max_msr_list_size()); 10609 } 10610 10611 static void atomic_switch_overflow_msrs_test(void) 10612 { 10613 if (test_device_enabled()) 10614 atomic_switch_msrs_test(max_msr_list_size() + 1); 10615 else 10616 test_skip("Test is only supported on KVM"); 10617 } 10618 10619 static void vmx_pf_exception_test_guest(void) 10620 { 10621 ac_test_run(PT_LEVEL_PML4); 10622 } 10623 10624 static void vmx_pf_exception_test(void) 10625 { 10626 u64 efer; 10627 struct cpuid cpuid; 10628 10629 test_set_guest(vmx_pf_exception_test_guest); 10630 10631 enter_guest(); 10632 10633 while (vmcs_read(EXI_REASON) != VMX_VMCALL) { 10634 switch (vmcs_read(EXI_REASON)) { 10635 case VMX_RDMSR: 10636 assert(regs.rcx == MSR_EFER); 10637 efer = vmcs_read(GUEST_EFER); 10638 regs.rdx = efer >> 32; 10639 regs.rax = efer & 0xffffffff; 10640 break; 10641 case VMX_WRMSR: 10642 assert(regs.rcx == MSR_EFER); 10643 efer = regs.rdx << 32 | (regs.rax & 0xffffffff); 10644 vmcs_write(GUEST_EFER, efer); 10645 break; 10646 case VMX_CPUID: 10647 cpuid = (struct cpuid) {0, 0, 0, 0}; 10648 cpuid = raw_cpuid(regs.rax, regs.rcx); 10649 regs.rax = cpuid.a; 10650 regs.rbx = cpuid.b; 10651 regs.rcx = cpuid.c; 10652 regs.rdx = cpuid.d; 10653 break; 10654 default: 10655 assert_msg(false, 10656 "Unexpected exit to L1, exit_reason: %s (0x%lx)", 10657 exit_reason_description(vmcs_read(EXI_REASON)), 10658 vmcs_read(EXI_REASON)); 10659 } 10660 skip_exit_insn(); 10661 enter_guest(); 10662 } 10663 10664 assert_exit_reason(VMX_VMCALL); 10665 } 10666 #define TEST(name) { #name, .v2 = name } 10667 10668 /* name/init/guest_main/exit_handler/syscall_handler/guest_regs */ 10669 struct vmx_test vmx_tests[] = { 10670 { "null", NULL, basic_guest_main, basic_exit_handler, NULL, {0} }, 10671 { "vmenter", NULL, vmenter_main, vmenter_exit_handler, NULL, {0} }, 10672 { "preemption timer", preemption_timer_init, preemption_timer_main, 10673 preemption_timer_exit_handler, NULL, {0} }, 10674 { "control field PAT", test_ctrl_pat_init, test_ctrl_pat_main, 10675 test_ctrl_pat_exit_handler, NULL, {0} }, 10676 { "control field EFER", test_ctrl_efer_init, test_ctrl_efer_main, 10677 test_ctrl_efer_exit_handler, NULL, {0} }, 10678 { "CR shadowing", NULL, cr_shadowing_main, 10679 cr_shadowing_exit_handler, NULL, {0} }, 10680 { "I/O bitmap", iobmp_init, iobmp_main, iobmp_exit_handler, 10681 NULL, {0} }, 10682 { "instruction intercept", insn_intercept_init, insn_intercept_main, 10683 insn_intercept_exit_handler, NULL, {0} }, 10684 { "EPT A/D disabled", ept_init, ept_main, ept_exit_handler, NULL, {0} }, 10685 { "EPT A/D enabled", eptad_init, eptad_main, eptad_exit_handler, NULL, {0} }, 10686 { "PML", pml_init, pml_main, pml_exit_handler, NULL, {0} }, 10687 { "interrupt", interrupt_init, interrupt_main, 10688 interrupt_exit_handler, NULL, {0} }, 10689 { "nmi_hlt", nmi_hlt_init, nmi_hlt_main, 10690 nmi_hlt_exit_handler, NULL, {0} }, 10691 { "debug controls", dbgctls_init, dbgctls_main, dbgctls_exit_handler, 10692 NULL, {0} }, 10693 { "MSR switch", msr_switch_init, msr_switch_main, 10694 msr_switch_exit_handler, NULL, {0}, msr_switch_entry_failure }, 10695 { "vmmcall", vmmcall_init, vmmcall_main, vmmcall_exit_handler, NULL, {0} }, 10696 { "disable RDTSCP", disable_rdtscp_init, disable_rdtscp_main, 10697 disable_rdtscp_exit_handler, NULL, {0} }, 10698 { "int3", int3_init, int3_guest_main, int3_exit_handler, NULL, {0} }, 10699 { "into", into_init, into_guest_main, into_exit_handler, NULL, {0} }, 10700 { "exit_monitor_from_l2_test", NULL, exit_monitor_from_l2_main, 10701 exit_monitor_from_l2_handler, NULL, {0} }, 10702 { "invalid_msr", invalid_msr_init, invalid_msr_main, 10703 invalid_msr_exit_handler, NULL, {0}, invalid_msr_entry_failure}, 10704 /* Basic V2 tests. */ 10705 TEST(v2_null_test), 10706 TEST(v2_multiple_entries_test), 10707 TEST(fixture_test_case1), 10708 TEST(fixture_test_case2), 10709 /* Opcode tests. */ 10710 TEST(invvpid_test), 10711 /* VM-entry tests */ 10712 TEST(vmx_controls_test), 10713 TEST(vmx_host_state_area_test), 10714 TEST(vmx_guest_state_area_test), 10715 TEST(vmentry_movss_shadow_test), 10716 TEST(vmentry_unrestricted_guest_test), 10717 /* APICv tests */ 10718 TEST(vmx_eoi_bitmap_ioapic_scan_test), 10719 TEST(vmx_hlt_with_rvi_test), 10720 TEST(apic_reg_virt_test), 10721 TEST(virt_x2apic_mode_test), 10722 /* APIC pass-through tests */ 10723 TEST(vmx_apic_passthrough_test), 10724 TEST(vmx_apic_passthrough_thread_test), 10725 TEST(vmx_apic_passthrough_tpr_threshold_test), 10726 TEST(vmx_init_signal_test), 10727 TEST(vmx_sipi_signal_test), 10728 /* VMCS Shadowing tests */ 10729 TEST(vmx_vmcs_shadow_test), 10730 /* Regression tests */ 10731 TEST(vmx_ldtr_test), 10732 TEST(vmx_cr_load_test), 10733 TEST(vmx_cr4_osxsave_test), 10734 TEST(vmx_nm_test), 10735 TEST(vmx_db_test), 10736 TEST(vmx_nmi_window_test), 10737 TEST(vmx_intr_window_test), 10738 TEST(vmx_pending_event_test), 10739 TEST(vmx_pending_event_hlt_test), 10740 TEST(vmx_store_tsc_test), 10741 TEST(vmx_preemption_timer_zero_test), 10742 TEST(vmx_preemption_timer_tf_test), 10743 TEST(vmx_preemption_timer_expiry_test), 10744 /* EPT access tests. */ 10745 TEST(ept_access_test_not_present), 10746 TEST(ept_access_test_read_only), 10747 TEST(ept_access_test_write_only), 10748 TEST(ept_access_test_read_write), 10749 TEST(ept_access_test_execute_only), 10750 TEST(ept_access_test_read_execute), 10751 TEST(ept_access_test_write_execute), 10752 TEST(ept_access_test_read_write_execute), 10753 TEST(ept_access_test_reserved_bits), 10754 TEST(ept_access_test_ignored_bits), 10755 TEST(ept_access_test_paddr_not_present_ad_disabled), 10756 TEST(ept_access_test_paddr_not_present_ad_enabled), 10757 TEST(ept_access_test_paddr_read_only_ad_disabled), 10758 TEST(ept_access_test_paddr_read_only_ad_enabled), 10759 TEST(ept_access_test_paddr_read_write), 10760 TEST(ept_access_test_paddr_read_write_execute), 10761 TEST(ept_access_test_paddr_read_execute_ad_disabled), 10762 TEST(ept_access_test_paddr_read_execute_ad_enabled), 10763 TEST(ept_access_test_paddr_not_present_page_fault), 10764 TEST(ept_access_test_force_2m_page), 10765 /* Atomic MSR switch tests. */ 10766 TEST(atomic_switch_max_msrs_test), 10767 TEST(atomic_switch_overflow_msrs_test), 10768 TEST(rdtsc_vmexit_diff_test), 10769 TEST(vmx_mtf_test), 10770 TEST(vmx_mtf_pdpte_test), 10771 TEST(vmx_pf_exception_test), 10772 { NULL, NULL, NULL, NULL, NULL, {0} }, 10773 }; 10774