1 /* 2 * All test cases of nested virtualization should be in this file 3 * 4 * Author : Arthur Chunqi Li <yzt356@gmail.com> 5 */ 6 7 #include <asm/debugreg.h> 8 9 #include "vmx.h" 10 #include "msr.h" 11 #include "processor.h" 12 #include "vm.h" 13 #include "pci.h" 14 #include "fwcfg.h" 15 #include "isr.h" 16 #include "desc.h" 17 #include "apic.h" 18 #include "types.h" 19 #include "vmalloc.h" 20 #include "alloc_page.h" 21 #include "smp.h" 22 #include "delay.h" 23 #include "access.h" 24 25 #define VPID_CAP_INVVPID_TYPES_SHIFT 40 26 27 u64 ia32_pat; 28 u64 ia32_efer; 29 void *io_bitmap_a, *io_bitmap_b; 30 u16 ioport; 31 32 unsigned long *pml4; 33 u64 eptp; 34 void *data_page1, *data_page2; 35 36 phys_addr_t pci_physaddr; 37 38 void *pml_log; 39 #define PML_INDEX 512 40 41 static inline unsigned ffs(unsigned x) 42 { 43 int pos = -1; 44 45 __asm__ __volatile__("bsf %1, %%eax; cmovnz %%eax, %0" 46 : "+r"(pos) : "rm"(x) : "eax"); 47 return pos + 1; 48 } 49 50 static inline void vmcall(void) 51 { 52 asm volatile("vmcall"); 53 } 54 55 static void basic_guest_main(void) 56 { 57 report_pass("Basic VMX test"); 58 } 59 60 static int basic_exit_handler(union exit_reason exit_reason) 61 { 62 report_fail("Basic VMX test"); 63 print_vmexit_info(exit_reason); 64 return VMX_TEST_EXIT; 65 } 66 67 static void vmenter_main(void) 68 { 69 u64 rax; 70 u64 rsp, resume_rsp; 71 72 report_pass("test vmlaunch"); 73 74 asm volatile( 75 "mov %%rsp, %0\n\t" 76 "mov %3, %%rax\n\t" 77 "vmcall\n\t" 78 "mov %%rax, %1\n\t" 79 "mov %%rsp, %2\n\t" 80 : "=r"(rsp), "=r"(rax), "=r"(resume_rsp) 81 : "g"(0xABCD)); 82 report((rax == 0xFFFF) && (rsp == resume_rsp), "test vmresume"); 83 } 84 85 static int vmenter_exit_handler(union exit_reason exit_reason) 86 { 87 u64 guest_rip = vmcs_read(GUEST_RIP); 88 89 switch (exit_reason.basic) { 90 case VMX_VMCALL: 91 if (regs.rax != 0xABCD) { 92 report_fail("test vmresume"); 93 return VMX_TEST_VMEXIT; 94 } 95 regs.rax = 0xFFFF; 96 vmcs_write(GUEST_RIP, guest_rip + 3); 97 return VMX_TEST_RESUME; 98 default: 99 report_fail("test vmresume"); 100 print_vmexit_info(exit_reason); 101 } 102 return VMX_TEST_VMEXIT; 103 } 104 105 u32 preempt_scale; 106 volatile unsigned long long tsc_val; 107 volatile u32 preempt_val; 108 u64 saved_rip; 109 110 static int preemption_timer_init(struct vmcs *vmcs) 111 { 112 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 113 printf("\tPreemption timer is not supported\n"); 114 return VMX_TEST_EXIT; 115 } 116 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 117 preempt_val = 10000000; 118 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 119 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 120 121 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 122 printf("\tSave preemption value is not supported\n"); 123 124 return VMX_TEST_START; 125 } 126 127 static void preemption_timer_main(void) 128 { 129 tsc_val = rdtsc(); 130 if (ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) { 131 vmx_set_test_stage(0); 132 vmcall(); 133 if (vmx_get_test_stage() == 1) 134 vmcall(); 135 } 136 vmx_set_test_stage(1); 137 while (vmx_get_test_stage() == 1) { 138 if (((rdtsc() - tsc_val) >> preempt_scale) 139 > 10 * preempt_val) { 140 vmx_set_test_stage(2); 141 vmcall(); 142 } 143 } 144 tsc_val = rdtsc(); 145 asm volatile ("hlt"); 146 vmcall(); 147 vmx_set_test_stage(5); 148 vmcall(); 149 } 150 151 static int preemption_timer_exit_handler(union exit_reason exit_reason) 152 { 153 bool guest_halted; 154 u64 guest_rip; 155 u32 insn_len; 156 u32 ctrl_exit; 157 158 guest_rip = vmcs_read(GUEST_RIP); 159 insn_len = vmcs_read(EXI_INST_LEN); 160 switch (exit_reason.basic) { 161 case VMX_PREEMPT: 162 switch (vmx_get_test_stage()) { 163 case 1: 164 case 2: 165 report(((rdtsc() - tsc_val) >> preempt_scale) >= preempt_val, 166 "busy-wait for preemption timer"); 167 vmx_set_test_stage(3); 168 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 169 return VMX_TEST_RESUME; 170 case 3: 171 guest_halted = 172 (vmcs_read(GUEST_ACTV_STATE) == ACTV_HLT); 173 report(((rdtsc() - tsc_val) >> preempt_scale) >= preempt_val 174 && guest_halted, 175 "preemption timer during hlt"); 176 vmx_set_test_stage(4); 177 vmcs_write(PIN_CONTROLS, 178 vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 179 vmcs_write(EXI_CONTROLS, 180 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_PREEMPT); 181 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 182 return VMX_TEST_RESUME; 183 case 4: 184 report(saved_rip == guest_rip, 185 "preemption timer with 0 value"); 186 break; 187 default: 188 report_fail("Invalid stage."); 189 print_vmexit_info(exit_reason); 190 break; 191 } 192 break; 193 case VMX_VMCALL: 194 vmcs_write(GUEST_RIP, guest_rip + insn_len); 195 switch (vmx_get_test_stage()) { 196 case 0: 197 report(vmcs_read(PREEMPT_TIMER_VALUE) == preempt_val, 198 "Keep preemption value"); 199 vmx_set_test_stage(1); 200 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 201 ctrl_exit = (vmcs_read(EXI_CONTROLS) | 202 EXI_SAVE_PREEMPT) & ctrl_exit_rev.clr; 203 vmcs_write(EXI_CONTROLS, ctrl_exit); 204 return VMX_TEST_RESUME; 205 case 1: 206 report(vmcs_read(PREEMPT_TIMER_VALUE) < preempt_val, 207 "Save preemption value"); 208 return VMX_TEST_RESUME; 209 case 2: 210 report_fail("busy-wait for preemption timer"); 211 vmx_set_test_stage(3); 212 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 213 return VMX_TEST_RESUME; 214 case 3: 215 report_fail("preemption timer during hlt"); 216 vmx_set_test_stage(4); 217 /* fall through */ 218 case 4: 219 vmcs_write(PIN_CONTROLS, 220 vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 221 vmcs_write(PREEMPT_TIMER_VALUE, 0); 222 saved_rip = guest_rip + insn_len; 223 return VMX_TEST_RESUME; 224 case 5: 225 report_fail("preemption timer with 0 value (vmcall stage 5)"); 226 break; 227 default: 228 // Should not reach here 229 report_fail("unexpected stage, %d", 230 vmx_get_test_stage()); 231 print_vmexit_info(exit_reason); 232 return VMX_TEST_VMEXIT; 233 } 234 break; 235 default: 236 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 237 print_vmexit_info(exit_reason); 238 } 239 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 240 return VMX_TEST_VMEXIT; 241 } 242 243 static void msr_bmp_init(void) 244 { 245 void *msr_bitmap; 246 u32 ctrl_cpu0; 247 248 msr_bitmap = alloc_page(); 249 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 250 ctrl_cpu0 |= CPU_MSR_BITMAP; 251 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 252 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 253 } 254 255 static void *get_msr_bitmap(void) 256 { 257 void *msr_bitmap; 258 259 if (vmcs_read(CPU_EXEC_CTRL0) & CPU_MSR_BITMAP) { 260 msr_bitmap = (void *)vmcs_read(MSR_BITMAP); 261 } else { 262 msr_bitmap = alloc_page(); 263 memset(msr_bitmap, 0xff, PAGE_SIZE); 264 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 265 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_MSR_BITMAP); 266 } 267 268 return msr_bitmap; 269 } 270 271 static void disable_intercept_for_x2apic_msrs(void) 272 { 273 unsigned long *msr_bitmap = (unsigned long *)get_msr_bitmap(); 274 u32 msr; 275 276 for (msr = APIC_BASE_MSR; 277 msr < (APIC_BASE_MSR+0xff); 278 msr += BITS_PER_LONG) { 279 unsigned int word = msr / BITS_PER_LONG; 280 281 msr_bitmap[word] = 0; 282 msr_bitmap[word + (0x800 / sizeof(long))] = 0; 283 } 284 } 285 286 static int test_ctrl_pat_init(struct vmcs *vmcs) 287 { 288 u64 ctrl_ent; 289 u64 ctrl_exi; 290 291 msr_bmp_init(); 292 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT) && 293 !(ctrl_exit_rev.clr & EXI_LOAD_PAT) && 294 !(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 295 printf("\tSave/load PAT is not supported\n"); 296 return 1; 297 } 298 299 ctrl_ent = vmcs_read(ENT_CONTROLS); 300 ctrl_exi = vmcs_read(EXI_CONTROLS); 301 ctrl_ent |= ctrl_enter_rev.clr & ENT_LOAD_PAT; 302 ctrl_exi |= ctrl_exit_rev.clr & (EXI_SAVE_PAT | EXI_LOAD_PAT); 303 vmcs_write(ENT_CONTROLS, ctrl_ent); 304 vmcs_write(EXI_CONTROLS, ctrl_exi); 305 ia32_pat = rdmsr(MSR_IA32_CR_PAT); 306 vmcs_write(GUEST_PAT, 0x0); 307 vmcs_write(HOST_PAT, ia32_pat); 308 return VMX_TEST_START; 309 } 310 311 static void test_ctrl_pat_main(void) 312 { 313 u64 guest_ia32_pat; 314 315 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 316 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) 317 printf("\tENT_LOAD_PAT is not supported.\n"); 318 else { 319 if (guest_ia32_pat != 0) { 320 report_fail("Entry load PAT"); 321 return; 322 } 323 } 324 wrmsr(MSR_IA32_CR_PAT, 0x6); 325 vmcall(); 326 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 327 if (ctrl_enter_rev.clr & ENT_LOAD_PAT) 328 report(guest_ia32_pat == ia32_pat, "Entry load PAT"); 329 } 330 331 static int test_ctrl_pat_exit_handler(union exit_reason exit_reason) 332 { 333 u64 guest_rip; 334 u64 guest_pat; 335 336 guest_rip = vmcs_read(GUEST_RIP); 337 switch (exit_reason.basic) { 338 case VMX_VMCALL: 339 guest_pat = vmcs_read(GUEST_PAT); 340 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT)) { 341 printf("\tEXI_SAVE_PAT is not supported\n"); 342 vmcs_write(GUEST_PAT, 0x6); 343 } else { 344 report(guest_pat == 0x6, "Exit save PAT"); 345 } 346 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) 347 printf("\tEXI_LOAD_PAT is not supported\n"); 348 else 349 report(rdmsr(MSR_IA32_CR_PAT) == ia32_pat, 350 "Exit load PAT"); 351 vmcs_write(GUEST_PAT, ia32_pat); 352 vmcs_write(GUEST_RIP, guest_rip + 3); 353 return VMX_TEST_RESUME; 354 default: 355 printf("ERROR : Unknown exit reason, 0x%x.\n", exit_reason.full); 356 break; 357 } 358 return VMX_TEST_VMEXIT; 359 } 360 361 static int test_ctrl_efer_init(struct vmcs *vmcs) 362 { 363 u64 ctrl_ent; 364 u64 ctrl_exi; 365 366 msr_bmp_init(); 367 ctrl_ent = vmcs_read(ENT_CONTROLS) | ENT_LOAD_EFER; 368 ctrl_exi = vmcs_read(EXI_CONTROLS) | EXI_SAVE_EFER | EXI_LOAD_EFER; 369 vmcs_write(ENT_CONTROLS, ctrl_ent & ctrl_enter_rev.clr); 370 vmcs_write(EXI_CONTROLS, ctrl_exi & ctrl_exit_rev.clr); 371 ia32_efer = rdmsr(MSR_EFER); 372 vmcs_write(GUEST_EFER, ia32_efer ^ EFER_NX); 373 vmcs_write(HOST_EFER, ia32_efer ^ EFER_NX); 374 return VMX_TEST_START; 375 } 376 377 static void test_ctrl_efer_main(void) 378 { 379 u64 guest_ia32_efer; 380 381 guest_ia32_efer = rdmsr(MSR_EFER); 382 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) 383 printf("\tENT_LOAD_EFER is not supported.\n"); 384 else { 385 if (guest_ia32_efer != (ia32_efer ^ EFER_NX)) { 386 report_fail("Entry load EFER"); 387 return; 388 } 389 } 390 wrmsr(MSR_EFER, ia32_efer); 391 vmcall(); 392 guest_ia32_efer = rdmsr(MSR_EFER); 393 if (ctrl_enter_rev.clr & ENT_LOAD_EFER) 394 report(guest_ia32_efer == ia32_efer, "Entry load EFER"); 395 } 396 397 static int test_ctrl_efer_exit_handler(union exit_reason exit_reason) 398 { 399 u64 guest_rip; 400 u64 guest_efer; 401 402 guest_rip = vmcs_read(GUEST_RIP); 403 switch (exit_reason.basic) { 404 case VMX_VMCALL: 405 guest_efer = vmcs_read(GUEST_EFER); 406 if (!(ctrl_exit_rev.clr & EXI_SAVE_EFER)) { 407 printf("\tEXI_SAVE_EFER is not supported\n"); 408 vmcs_write(GUEST_EFER, ia32_efer); 409 } else { 410 report(guest_efer == ia32_efer, "Exit save EFER"); 411 } 412 if (!(ctrl_exit_rev.clr & EXI_LOAD_EFER)) { 413 printf("\tEXI_LOAD_EFER is not supported\n"); 414 wrmsr(MSR_EFER, ia32_efer ^ EFER_NX); 415 } else { 416 report(rdmsr(MSR_EFER) == (ia32_efer ^ EFER_NX), 417 "Exit load EFER"); 418 } 419 vmcs_write(GUEST_PAT, ia32_efer); 420 vmcs_write(GUEST_RIP, guest_rip + 3); 421 return VMX_TEST_RESUME; 422 default: 423 printf("ERROR : Unknown exit reason, 0x%x.\n", exit_reason.full); 424 break; 425 } 426 return VMX_TEST_VMEXIT; 427 } 428 429 u32 guest_cr0, guest_cr4; 430 431 static void cr_shadowing_main(void) 432 { 433 u32 cr0, cr4, tmp; 434 435 // Test read through 436 vmx_set_test_stage(0); 437 guest_cr0 = read_cr0(); 438 if (vmx_get_test_stage() == 1) 439 report_fail("Read through CR0"); 440 else 441 vmcall(); 442 vmx_set_test_stage(1); 443 guest_cr4 = read_cr4(); 444 if (vmx_get_test_stage() == 2) 445 report_fail("Read through CR4"); 446 else 447 vmcall(); 448 // Test write through 449 guest_cr0 = guest_cr0 ^ (X86_CR0_TS | X86_CR0_MP); 450 guest_cr4 = guest_cr4 ^ (X86_CR4_TSD | X86_CR4_DE); 451 vmx_set_test_stage(2); 452 write_cr0(guest_cr0); 453 if (vmx_get_test_stage() == 3) 454 report_fail("Write throuth CR0"); 455 else 456 vmcall(); 457 vmx_set_test_stage(3); 458 write_cr4(guest_cr4); 459 if (vmx_get_test_stage() == 4) 460 report_fail("Write through CR4"); 461 else 462 vmcall(); 463 // Test read shadow 464 vmx_set_test_stage(4); 465 vmcall(); 466 cr0 = read_cr0(); 467 if (vmx_get_test_stage() != 5) 468 report(cr0 == guest_cr0, "Read shadowing CR0"); 469 vmx_set_test_stage(5); 470 cr4 = read_cr4(); 471 if (vmx_get_test_stage() != 6) 472 report(cr4 == guest_cr4, "Read shadowing CR4"); 473 // Test write shadow (same value with shadow) 474 vmx_set_test_stage(6); 475 write_cr0(guest_cr0); 476 if (vmx_get_test_stage() == 7) 477 report_fail("Write shadowing CR0 (same value with shadow)"); 478 else 479 vmcall(); 480 vmx_set_test_stage(7); 481 write_cr4(guest_cr4); 482 if (vmx_get_test_stage() == 8) 483 report_fail("Write shadowing CR4 (same value with shadow)"); 484 else 485 vmcall(); 486 // Test write shadow (different value) 487 vmx_set_test_stage(8); 488 tmp = guest_cr0 ^ X86_CR0_TS; 489 asm volatile("mov %0, %%rsi\n\t" 490 "mov %%rsi, %%cr0\n\t" 491 ::"m"(tmp) 492 :"rsi", "memory", "cc"); 493 report(vmx_get_test_stage() == 9, 494 "Write shadowing different X86_CR0_TS"); 495 vmx_set_test_stage(9); 496 tmp = guest_cr0 ^ X86_CR0_MP; 497 asm volatile("mov %0, %%rsi\n\t" 498 "mov %%rsi, %%cr0\n\t" 499 ::"m"(tmp) 500 :"rsi", "memory", "cc"); 501 report(vmx_get_test_stage() == 10, 502 "Write shadowing different X86_CR0_MP"); 503 vmx_set_test_stage(10); 504 tmp = guest_cr4 ^ X86_CR4_TSD; 505 asm volatile("mov %0, %%rsi\n\t" 506 "mov %%rsi, %%cr4\n\t" 507 ::"m"(tmp) 508 :"rsi", "memory", "cc"); 509 report(vmx_get_test_stage() == 11, 510 "Write shadowing different X86_CR4_TSD"); 511 vmx_set_test_stage(11); 512 tmp = guest_cr4 ^ X86_CR4_DE; 513 asm volatile("mov %0, %%rsi\n\t" 514 "mov %%rsi, %%cr4\n\t" 515 ::"m"(tmp) 516 :"rsi", "memory", "cc"); 517 report(vmx_get_test_stage() == 12, 518 "Write shadowing different X86_CR4_DE"); 519 } 520 521 static int cr_shadowing_exit_handler(union exit_reason exit_reason) 522 { 523 u64 guest_rip; 524 u32 insn_len; 525 u32 exit_qual; 526 527 guest_rip = vmcs_read(GUEST_RIP); 528 insn_len = vmcs_read(EXI_INST_LEN); 529 exit_qual = vmcs_read(EXI_QUALIFICATION); 530 switch (exit_reason.basic) { 531 case VMX_VMCALL: 532 switch (vmx_get_test_stage()) { 533 case 0: 534 report(guest_cr0 == vmcs_read(GUEST_CR0), 535 "Read through CR0"); 536 break; 537 case 1: 538 report(guest_cr4 == vmcs_read(GUEST_CR4), 539 "Read through CR4"); 540 break; 541 case 2: 542 report(guest_cr0 == vmcs_read(GUEST_CR0), 543 "Write through CR0"); 544 break; 545 case 3: 546 report(guest_cr4 == vmcs_read(GUEST_CR4), 547 "Write through CR4"); 548 break; 549 case 4: 550 guest_cr0 = vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP); 551 guest_cr4 = vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE); 552 vmcs_write(CR0_MASK, X86_CR0_TS | X86_CR0_MP); 553 vmcs_write(CR0_READ_SHADOW, guest_cr0 & (X86_CR0_TS | X86_CR0_MP)); 554 vmcs_write(CR4_MASK, X86_CR4_TSD | X86_CR4_DE); 555 vmcs_write(CR4_READ_SHADOW, guest_cr4 & (X86_CR4_TSD | X86_CR4_DE)); 556 break; 557 case 6: 558 report(guest_cr0 == (vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP)), 559 "Write shadowing CR0 (same value)"); 560 break; 561 case 7: 562 report(guest_cr4 == (vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE)), 563 "Write shadowing CR4 (same value)"); 564 break; 565 default: 566 // Should not reach here 567 report_fail("unexpected stage, %d", 568 vmx_get_test_stage()); 569 print_vmexit_info(exit_reason); 570 return VMX_TEST_VMEXIT; 571 } 572 vmcs_write(GUEST_RIP, guest_rip + insn_len); 573 return VMX_TEST_RESUME; 574 case VMX_CR: 575 switch (vmx_get_test_stage()) { 576 case 4: 577 report_fail("Read shadowing CR0"); 578 vmx_inc_test_stage(); 579 break; 580 case 5: 581 report_fail("Read shadowing CR4"); 582 vmx_inc_test_stage(); 583 break; 584 case 6: 585 report_fail("Write shadowing CR0 (same value)"); 586 vmx_inc_test_stage(); 587 break; 588 case 7: 589 report_fail("Write shadowing CR4 (same value)"); 590 vmx_inc_test_stage(); 591 break; 592 case 8: 593 case 9: 594 // 0x600 encodes "mov %esi, %cr0" 595 if (exit_qual == 0x600) 596 vmx_inc_test_stage(); 597 break; 598 case 10: 599 case 11: 600 // 0x604 encodes "mov %esi, %cr4" 601 if (exit_qual == 0x604) 602 vmx_inc_test_stage(); 603 break; 604 default: 605 // Should not reach here 606 report_fail("unexpected stage, %d", 607 vmx_get_test_stage()); 608 print_vmexit_info(exit_reason); 609 return VMX_TEST_VMEXIT; 610 } 611 vmcs_write(GUEST_RIP, guest_rip + insn_len); 612 return VMX_TEST_RESUME; 613 default: 614 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 615 print_vmexit_info(exit_reason); 616 } 617 return VMX_TEST_VMEXIT; 618 } 619 620 static int iobmp_init(struct vmcs *vmcs) 621 { 622 u32 ctrl_cpu0; 623 624 io_bitmap_a = alloc_page(); 625 io_bitmap_b = alloc_page(); 626 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 627 ctrl_cpu0 |= CPU_IO_BITMAP; 628 ctrl_cpu0 &= (~CPU_IO); 629 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 630 vmcs_write(IO_BITMAP_A, (u64)io_bitmap_a); 631 vmcs_write(IO_BITMAP_B, (u64)io_bitmap_b); 632 return VMX_TEST_START; 633 } 634 635 static void iobmp_main(void) 636 { 637 // stage 0, test IO pass 638 vmx_set_test_stage(0); 639 inb(0x5000); 640 outb(0x0, 0x5000); 641 report(vmx_get_test_stage() == 0, "I/O bitmap - I/O pass"); 642 // test IO width, in/out 643 ((u8 *)io_bitmap_a)[0] = 0xFF; 644 vmx_set_test_stage(2); 645 inb(0x0); 646 report(vmx_get_test_stage() == 3, "I/O bitmap - trap in"); 647 vmx_set_test_stage(3); 648 outw(0x0, 0x0); 649 report(vmx_get_test_stage() == 4, "I/O bitmap - trap out"); 650 vmx_set_test_stage(4); 651 inl(0x0); 652 report(vmx_get_test_stage() == 5, "I/O bitmap - I/O width, long"); 653 // test low/high IO port 654 vmx_set_test_stage(5); 655 ((u8 *)io_bitmap_a)[0x5000 / 8] = (1 << (0x5000 % 8)); 656 inb(0x5000); 657 report(vmx_get_test_stage() == 6, "I/O bitmap - I/O port, low part"); 658 vmx_set_test_stage(6); 659 ((u8 *)io_bitmap_b)[0x1000 / 8] = (1 << (0x1000 % 8)); 660 inb(0x9000); 661 report(vmx_get_test_stage() == 7, "I/O bitmap - I/O port, high part"); 662 // test partial pass 663 vmx_set_test_stage(7); 664 inl(0x4FFF); 665 report(vmx_get_test_stage() == 8, "I/O bitmap - partial pass"); 666 // test overrun 667 vmx_set_test_stage(8); 668 memset(io_bitmap_a, 0x0, PAGE_SIZE); 669 memset(io_bitmap_b, 0x0, PAGE_SIZE); 670 inl(0xFFFF); 671 report(vmx_get_test_stage() == 9, "I/O bitmap - overrun"); 672 vmx_set_test_stage(9); 673 vmcall(); 674 outb(0x0, 0x0); 675 report(vmx_get_test_stage() == 9, 676 "I/O bitmap - ignore unconditional exiting"); 677 vmx_set_test_stage(10); 678 vmcall(); 679 outb(0x0, 0x0); 680 report(vmx_get_test_stage() == 11, 681 "I/O bitmap - unconditional exiting"); 682 } 683 684 static int iobmp_exit_handler(union exit_reason exit_reason) 685 { 686 u64 guest_rip; 687 ulong exit_qual; 688 u32 insn_len, ctrl_cpu0; 689 690 guest_rip = vmcs_read(GUEST_RIP); 691 exit_qual = vmcs_read(EXI_QUALIFICATION); 692 insn_len = vmcs_read(EXI_INST_LEN); 693 switch (exit_reason.basic) { 694 case VMX_IO: 695 switch (vmx_get_test_stage()) { 696 case 0: 697 case 1: 698 vmx_inc_test_stage(); 699 break; 700 case 2: 701 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_BYTE, 702 "I/O bitmap - I/O width, byte"); 703 report(exit_qual & VMX_IO_IN, 704 "I/O bitmap - I/O direction, in"); 705 vmx_inc_test_stage(); 706 break; 707 case 3: 708 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_WORD, 709 "I/O bitmap - I/O width, word"); 710 report(!(exit_qual & VMX_IO_IN), 711 "I/O bitmap - I/O direction, out"); 712 vmx_inc_test_stage(); 713 break; 714 case 4: 715 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_LONG, 716 "I/O bitmap - I/O width, long"); 717 vmx_inc_test_stage(); 718 break; 719 case 5: 720 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x5000) 721 vmx_inc_test_stage(); 722 break; 723 case 6: 724 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x9000) 725 vmx_inc_test_stage(); 726 break; 727 case 7: 728 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x4FFF) 729 vmx_inc_test_stage(); 730 break; 731 case 8: 732 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0xFFFF) 733 vmx_inc_test_stage(); 734 break; 735 case 9: 736 case 10: 737 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 738 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0 & ~CPU_IO); 739 vmx_inc_test_stage(); 740 break; 741 default: 742 // Should not reach here 743 report_fail("unexpected stage, %d", 744 vmx_get_test_stage()); 745 print_vmexit_info(exit_reason); 746 return VMX_TEST_VMEXIT; 747 } 748 vmcs_write(GUEST_RIP, guest_rip + insn_len); 749 return VMX_TEST_RESUME; 750 case VMX_VMCALL: 751 switch (vmx_get_test_stage()) { 752 case 9: 753 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 754 ctrl_cpu0 |= CPU_IO | CPU_IO_BITMAP; 755 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 756 break; 757 case 10: 758 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 759 ctrl_cpu0 = (ctrl_cpu0 & ~CPU_IO_BITMAP) | CPU_IO; 760 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 761 break; 762 default: 763 // Should not reach here 764 report_fail("unexpected stage, %d", 765 vmx_get_test_stage()); 766 print_vmexit_info(exit_reason); 767 return VMX_TEST_VMEXIT; 768 } 769 vmcs_write(GUEST_RIP, guest_rip + insn_len); 770 return VMX_TEST_RESUME; 771 default: 772 printf("guest_rip = %#lx\n", guest_rip); 773 printf("\tERROR : Unknown exit reason, 0x%x\n", exit_reason.full); 774 break; 775 } 776 return VMX_TEST_VMEXIT; 777 } 778 779 #define INSN_CPU0 0 780 #define INSN_CPU1 1 781 #define INSN_ALWAYS_TRAP 2 782 783 #define FIELD_EXIT_QUAL (1 << 0) 784 #define FIELD_INSN_INFO (1 << 1) 785 786 asm( 787 "insn_hlt: hlt;ret\n\t" 788 "insn_invlpg: invlpg 0x12345678;ret\n\t" 789 "insn_mwait: xor %eax, %eax; xor %ecx, %ecx; mwait;ret\n\t" 790 "insn_rdpmc: xor %ecx, %ecx; rdpmc;ret\n\t" 791 "insn_rdtsc: rdtsc;ret\n\t" 792 "insn_cr3_load: mov cr3,%rax; mov %rax,%cr3;ret\n\t" 793 "insn_cr3_store: mov %cr3,%rax;ret\n\t" 794 "insn_cr8_load: xor %eax, %eax; mov %rax,%cr8;ret\n\t" 795 "insn_cr8_store: mov %cr8,%rax;ret\n\t" 796 "insn_monitor: xor %eax, %eax; xor %ecx, %ecx; xor %edx, %edx; monitor;ret\n\t" 797 "insn_pause: pause;ret\n\t" 798 "insn_wbinvd: wbinvd;ret\n\t" 799 "insn_cpuid: mov $10, %eax; cpuid;ret\n\t" 800 "insn_invd: invd;ret\n\t" 801 "insn_sgdt: sgdt gdt_descr;ret\n\t" 802 "insn_lgdt: lgdt gdt_descr;ret\n\t" 803 "insn_sidt: sidt idt_descr;ret\n\t" 804 "insn_lidt: lidt idt_descr;ret\n\t" 805 "insn_sldt: sldt %ax;ret\n\t" 806 "insn_lldt: xor %eax, %eax; lldt %ax;ret\n\t" 807 "insn_str: str %ax;ret\n\t" 808 "insn_rdrand: rdrand %rax;ret\n\t" 809 "insn_rdseed: rdseed %rax;ret\n\t" 810 ); 811 extern void insn_hlt(void); 812 extern void insn_invlpg(void); 813 extern void insn_mwait(void); 814 extern void insn_rdpmc(void); 815 extern void insn_rdtsc(void); 816 extern void insn_cr3_load(void); 817 extern void insn_cr3_store(void); 818 extern void insn_cr8_load(void); 819 extern void insn_cr8_store(void); 820 extern void insn_monitor(void); 821 extern void insn_pause(void); 822 extern void insn_wbinvd(void); 823 extern void insn_sgdt(void); 824 extern void insn_lgdt(void); 825 extern void insn_sidt(void); 826 extern void insn_lidt(void); 827 extern void insn_sldt(void); 828 extern void insn_lldt(void); 829 extern void insn_str(void); 830 extern void insn_cpuid(void); 831 extern void insn_invd(void); 832 extern void insn_rdrand(void); 833 extern void insn_rdseed(void); 834 835 u32 cur_insn; 836 u64 cr3; 837 838 #define X86_FEATURE_MONITOR (1 << 3) 839 840 typedef bool (*supported_fn)(void); 841 842 static bool monitor_supported(void) 843 { 844 return this_cpu_has(X86_FEATURE_MWAIT); 845 } 846 847 struct insn_table { 848 const char *name; 849 u32 flag; 850 void (*insn_func)(void); 851 u32 type; 852 u32 reason; 853 ulong exit_qual; 854 u32 insn_info; 855 // Use FIELD_EXIT_QUAL and FIELD_INSN_INFO to define 856 // which field need to be tested, reason is always tested 857 u32 test_field; 858 const supported_fn supported_fn; 859 u8 disabled; 860 }; 861 862 /* 863 * Add more test cases of instruction intercept here. Elements in this 864 * table is: 865 * name/control flag/insn function/type/exit reason/exit qulification/ 866 * instruction info/field to test 867 * The last field defines which fields (exit_qual and insn_info) need to be 868 * tested in exit handler. If set to 0, only "reason" is checked. 869 */ 870 static struct insn_table insn_table[] = { 871 // Flags for Primary Processor-Based VM-Execution Controls 872 {"HLT", CPU_HLT, insn_hlt, INSN_CPU0, 12, 0, 0, 0}, 873 {"INVLPG", CPU_INVLPG, insn_invlpg, INSN_CPU0, 14, 874 0x12345678, 0, FIELD_EXIT_QUAL}, 875 {"MWAIT", CPU_MWAIT, insn_mwait, INSN_CPU0, 36, 0, 0, 0, &monitor_supported}, 876 {"RDPMC", CPU_RDPMC, insn_rdpmc, INSN_CPU0, 15, 0, 0, 0}, 877 {"RDTSC", CPU_RDTSC, insn_rdtsc, INSN_CPU0, 16, 0, 0, 0}, 878 {"CR3 load", CPU_CR3_LOAD, insn_cr3_load, INSN_CPU0, 28, 0x3, 0, 879 FIELD_EXIT_QUAL}, 880 {"CR3 store", CPU_CR3_STORE, insn_cr3_store, INSN_CPU0, 28, 0x13, 0, 881 FIELD_EXIT_QUAL}, 882 {"CR8 load", CPU_CR8_LOAD, insn_cr8_load, INSN_CPU0, 28, 0x8, 0, 883 FIELD_EXIT_QUAL}, 884 {"CR8 store", CPU_CR8_STORE, insn_cr8_store, INSN_CPU0, 28, 0x18, 0, 885 FIELD_EXIT_QUAL}, 886 {"MONITOR", CPU_MONITOR, insn_monitor, INSN_CPU0, 39, 0, 0, 0, &monitor_supported}, 887 {"PAUSE", CPU_PAUSE, insn_pause, INSN_CPU0, 40, 0, 0, 0}, 888 // Flags for Secondary Processor-Based VM-Execution Controls 889 {"WBINVD", CPU_WBINVD, insn_wbinvd, INSN_CPU1, 54, 0, 0, 0}, 890 {"DESC_TABLE (SGDT)", CPU_DESC_TABLE, insn_sgdt, INSN_CPU1, 46, 0, 0, 0}, 891 {"DESC_TABLE (LGDT)", CPU_DESC_TABLE, insn_lgdt, INSN_CPU1, 46, 0, 0, 0}, 892 {"DESC_TABLE (SIDT)", CPU_DESC_TABLE, insn_sidt, INSN_CPU1, 46, 0, 0, 0}, 893 {"DESC_TABLE (LIDT)", CPU_DESC_TABLE, insn_lidt, INSN_CPU1, 46, 0, 0, 0}, 894 {"DESC_TABLE (SLDT)", CPU_DESC_TABLE, insn_sldt, INSN_CPU1, 47, 0, 0, 0}, 895 {"DESC_TABLE (LLDT)", CPU_DESC_TABLE, insn_lldt, INSN_CPU1, 47, 0, 0, 0}, 896 {"DESC_TABLE (STR)", CPU_DESC_TABLE, insn_str, INSN_CPU1, 47, 0, 0, 0}, 897 /* LTR causes a #GP if done with a busy selector, so it is not tested. */ 898 {"RDRAND", CPU_RDRAND, insn_rdrand, INSN_CPU1, VMX_RDRAND, 0, 0, 0}, 899 {"RDSEED", CPU_RDSEED, insn_rdseed, INSN_CPU1, VMX_RDSEED, 0, 0, 0}, 900 // Instructions always trap 901 {"CPUID", 0, insn_cpuid, INSN_ALWAYS_TRAP, 10, 0, 0, 0}, 902 {"INVD", 0, insn_invd, INSN_ALWAYS_TRAP, 13, 0, 0, 0}, 903 // Instructions never trap 904 {NULL}, 905 }; 906 907 static int insn_intercept_init(struct vmcs *vmcs) 908 { 909 u32 ctrl_cpu, cur_insn; 910 911 ctrl_cpu = ctrl_cpu_rev[0].set | CPU_SECONDARY; 912 ctrl_cpu &= ctrl_cpu_rev[0].clr; 913 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu); 914 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu_rev[1].set); 915 cr3 = read_cr3(); 916 917 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 918 if (insn_table[cur_insn].supported_fn == NULL) 919 continue; 920 insn_table[cur_insn].disabled = !insn_table[cur_insn].supported_fn(); 921 } 922 return VMX_TEST_START; 923 } 924 925 static void insn_intercept_main(void) 926 { 927 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 928 vmx_set_test_stage(cur_insn * 2); 929 if ((insn_table[cur_insn].type == INSN_CPU0 && 930 !(ctrl_cpu_rev[0].clr & insn_table[cur_insn].flag)) || 931 (insn_table[cur_insn].type == INSN_CPU1 && 932 !(ctrl_cpu_rev[1].clr & insn_table[cur_insn].flag))) { 933 printf("\tCPU_CTRL%d.CPU_%s is not supported.\n", 934 insn_table[cur_insn].type - INSN_CPU0, 935 insn_table[cur_insn].name); 936 continue; 937 } 938 939 if (insn_table[cur_insn].disabled) { 940 printf("\tFeature required for %s is not supported.\n", 941 insn_table[cur_insn].name); 942 continue; 943 } 944 945 if ((insn_table[cur_insn].type == INSN_CPU0 && 946 !(ctrl_cpu_rev[0].set & insn_table[cur_insn].flag)) || 947 (insn_table[cur_insn].type == INSN_CPU1 && 948 !(ctrl_cpu_rev[1].set & insn_table[cur_insn].flag))) { 949 /* skip hlt, it stalls the guest and is tested below */ 950 if (insn_table[cur_insn].insn_func != insn_hlt) 951 insn_table[cur_insn].insn_func(); 952 report(vmx_get_test_stage() == cur_insn * 2, 953 "execute %s", 954 insn_table[cur_insn].name); 955 } else if (insn_table[cur_insn].type != INSN_ALWAYS_TRAP) 956 printf("\tCPU_CTRL%d.CPU_%s always traps.\n", 957 insn_table[cur_insn].type - INSN_CPU0, 958 insn_table[cur_insn].name); 959 960 vmcall(); 961 962 insn_table[cur_insn].insn_func(); 963 report(vmx_get_test_stage() == cur_insn * 2 + 1, 964 "intercept %s", 965 insn_table[cur_insn].name); 966 967 vmx_set_test_stage(cur_insn * 2 + 1); 968 vmcall(); 969 } 970 } 971 972 static int insn_intercept_exit_handler(union exit_reason exit_reason) 973 { 974 u64 guest_rip; 975 ulong exit_qual; 976 u32 insn_len; 977 u32 insn_info; 978 bool pass; 979 980 guest_rip = vmcs_read(GUEST_RIP); 981 exit_qual = vmcs_read(EXI_QUALIFICATION); 982 insn_len = vmcs_read(EXI_INST_LEN); 983 insn_info = vmcs_read(EXI_INST_INFO); 984 985 if (exit_reason.basic == VMX_VMCALL) { 986 u32 val = 0; 987 988 if (insn_table[cur_insn].type == INSN_CPU0) 989 val = vmcs_read(CPU_EXEC_CTRL0); 990 else if (insn_table[cur_insn].type == INSN_CPU1) 991 val = vmcs_read(CPU_EXEC_CTRL1); 992 993 if (vmx_get_test_stage() & 1) 994 val &= ~insn_table[cur_insn].flag; 995 else 996 val |= insn_table[cur_insn].flag; 997 998 if (insn_table[cur_insn].type == INSN_CPU0) 999 vmcs_write(CPU_EXEC_CTRL0, val | ctrl_cpu_rev[0].set); 1000 else if (insn_table[cur_insn].type == INSN_CPU1) 1001 vmcs_write(CPU_EXEC_CTRL1, val | ctrl_cpu_rev[1].set); 1002 } else { 1003 pass = (cur_insn * 2 == vmx_get_test_stage()) && 1004 insn_table[cur_insn].reason == exit_reason.full; 1005 if (insn_table[cur_insn].test_field & FIELD_EXIT_QUAL && 1006 insn_table[cur_insn].exit_qual != exit_qual) 1007 pass = false; 1008 if (insn_table[cur_insn].test_field & FIELD_INSN_INFO && 1009 insn_table[cur_insn].insn_info != insn_info) 1010 pass = false; 1011 if (pass) 1012 vmx_inc_test_stage(); 1013 } 1014 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1015 return VMX_TEST_RESUME; 1016 } 1017 1018 /** 1019 * __setup_ept - Setup the VMCS fields to enable Extended Page Tables (EPT) 1020 * @hpa: Host physical address of the top-level, a.k.a. root, EPT table 1021 * @enable_ad: Whether or not to enable Access/Dirty bits for EPT entries 1022 * 1023 * Returns 0 on success, 1 on failure. 1024 * 1025 * Note that @hpa doesn't need to point at actual memory if VM-Launch is 1026 * expected to fail, e.g. setup_dummy_ept() arbitrarily passes '0' to satisfy 1027 * the various EPTP consistency checks, but doesn't ensure backing for HPA '0'. 1028 */ 1029 static int __setup_ept(u64 hpa, bool enable_ad) 1030 { 1031 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1032 !(ctrl_cpu_rev[1].clr & CPU_EPT)) { 1033 printf("\tEPT is not supported\n"); 1034 return 1; 1035 } 1036 if (!(ept_vpid.val & EPT_CAP_WB)) { 1037 printf("\tWB memtype for EPT walks not supported\n"); 1038 return 1; 1039 } 1040 if (!(ept_vpid.val & EPT_CAP_PWL4)) { 1041 printf("\tPWL4 is not supported\n"); 1042 return 1; 1043 } 1044 1045 eptp = EPT_MEM_TYPE_WB; 1046 eptp |= (3 << EPTP_PG_WALK_LEN_SHIFT); 1047 eptp |= hpa; 1048 if (enable_ad) 1049 eptp |= EPTP_AD_FLAG; 1050 1051 vmcs_write(EPTP, eptp); 1052 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0)| CPU_SECONDARY); 1053 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1)| CPU_EPT); 1054 1055 return 0; 1056 } 1057 1058 /** 1059 * setup_ept - Enable Extended Page Tables (EPT) and setup an identity map 1060 * @enable_ad: Whether or not to enable Access/Dirty bits for EPT entries 1061 * 1062 * Returns 0 on success, 1 on failure. 1063 * 1064 * This is the "real" function for setting up EPT tables, i.e. use this for 1065 * tests that need to run code in the guest with EPT enabled. 1066 */ 1067 static int setup_ept(bool enable_ad) 1068 { 1069 unsigned long end_of_memory; 1070 1071 pml4 = alloc_page(); 1072 1073 if (__setup_ept(virt_to_phys(pml4), enable_ad)) 1074 return 1; 1075 1076 end_of_memory = fwcfg_get_u64(FW_CFG_RAM_SIZE); 1077 if (end_of_memory < (1ul << 32)) 1078 end_of_memory = (1ul << 32); 1079 /* Cannot use large EPT pages if we need to track EPT 1080 * accessed/dirty bits at 4K granularity. 1081 */ 1082 setup_ept_range(pml4, 0, end_of_memory, 0, 1083 !enable_ad && ept_2m_supported(), 1084 EPT_WA | EPT_RA | EPT_EA); 1085 return 0; 1086 } 1087 1088 /** 1089 * setup_dummy_ept - Enable Extended Page Tables (EPT) with a dummy root HPA 1090 * 1091 * Setup EPT using a semi-arbitrary dummy root HPA. This function is intended 1092 * for use by tests that need EPT enabled to verify dependent VMCS controls 1093 * but never expect to fully enter the guest, i.e. don't need setup the actual 1094 * EPT tables. 1095 */ 1096 static void setup_dummy_ept(void) 1097 { 1098 if (__setup_ept(0, false)) 1099 report_abort("EPT setup unexpectedly failed"); 1100 } 1101 1102 static int enable_unrestricted_guest(bool need_valid_ept) 1103 { 1104 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1105 !(ctrl_cpu_rev[1].clr & CPU_URG) || 1106 !(ctrl_cpu_rev[1].clr & CPU_EPT)) 1107 return 1; 1108 1109 if (need_valid_ept) 1110 setup_ept(false); 1111 else 1112 setup_dummy_ept(); 1113 1114 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 1115 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | CPU_URG); 1116 1117 return 0; 1118 } 1119 1120 static void ept_enable_ad_bits(void) 1121 { 1122 eptp |= EPTP_AD_FLAG; 1123 vmcs_write(EPTP, eptp); 1124 } 1125 1126 static void ept_disable_ad_bits(void) 1127 { 1128 eptp &= ~EPTP_AD_FLAG; 1129 vmcs_write(EPTP, eptp); 1130 } 1131 1132 static int ept_ad_enabled(void) 1133 { 1134 return eptp & EPTP_AD_FLAG; 1135 } 1136 1137 static void ept_enable_ad_bits_or_skip_test(void) 1138 { 1139 if (!ept_ad_bits_supported()) 1140 test_skip("EPT AD bits not supported."); 1141 ept_enable_ad_bits(); 1142 } 1143 1144 static int apic_version; 1145 1146 static int ept_init_common(bool have_ad) 1147 { 1148 int ret; 1149 struct pci_dev pcidev; 1150 1151 /* INVEPT is required by the EPT violation handler. */ 1152 if (!is_invept_type_supported(INVEPT_SINGLE)) 1153 return VMX_TEST_EXIT; 1154 1155 if (setup_ept(have_ad)) 1156 return VMX_TEST_EXIT; 1157 1158 data_page1 = alloc_page(); 1159 data_page2 = alloc_page(); 1160 *((u32 *)data_page1) = MAGIC_VAL_1; 1161 *((u32 *)data_page2) = MAGIC_VAL_2; 1162 install_ept(pml4, (unsigned long)data_page1, (unsigned long)data_page2, 1163 EPT_RA | EPT_WA | EPT_EA); 1164 1165 apic_version = apic_read(APIC_LVR); 1166 1167 ret = pci_find_dev(PCI_VENDOR_ID_REDHAT, PCI_DEVICE_ID_REDHAT_TEST); 1168 if (ret != PCIDEVADDR_INVALID) { 1169 pci_dev_init(&pcidev, ret); 1170 pci_physaddr = pcidev.resource[PCI_TESTDEV_BAR_MEM]; 1171 } 1172 1173 return VMX_TEST_START; 1174 } 1175 1176 static int ept_init(struct vmcs *vmcs) 1177 { 1178 return ept_init_common(false); 1179 } 1180 1181 static void ept_common(void) 1182 { 1183 vmx_set_test_stage(0); 1184 if (*((u32 *)data_page2) != MAGIC_VAL_1 || 1185 *((u32 *)data_page1) != MAGIC_VAL_1) 1186 report_fail("EPT basic framework - read"); 1187 else { 1188 *((u32 *)data_page2) = MAGIC_VAL_3; 1189 vmcall(); 1190 if (vmx_get_test_stage() == 1) { 1191 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1192 *((u32 *)data_page2) == MAGIC_VAL_2) 1193 report_pass("EPT basic framework"); 1194 else 1195 report_pass("EPT basic framework - remap"); 1196 } 1197 } 1198 // Test EPT Misconfigurations 1199 vmx_set_test_stage(1); 1200 vmcall(); 1201 *((u32 *)data_page1) = MAGIC_VAL_1; 1202 if (vmx_get_test_stage() != 2) { 1203 report_fail("EPT misconfigurations"); 1204 goto t1; 1205 } 1206 vmx_set_test_stage(2); 1207 vmcall(); 1208 *((u32 *)data_page1) = MAGIC_VAL_1; 1209 report(vmx_get_test_stage() == 3, "EPT misconfigurations"); 1210 t1: 1211 // Test EPT violation 1212 vmx_set_test_stage(3); 1213 vmcall(); 1214 *((u32 *)data_page1) = MAGIC_VAL_1; 1215 report(vmx_get_test_stage() == 4, "EPT violation - page permission"); 1216 // Violation caused by EPT paging structure 1217 vmx_set_test_stage(4); 1218 vmcall(); 1219 *((u32 *)data_page1) = MAGIC_VAL_2; 1220 report(vmx_get_test_stage() == 5, "EPT violation - paging structure"); 1221 1222 // MMIO Read/Write 1223 vmx_set_test_stage(5); 1224 vmcall(); 1225 1226 *(u32 volatile *)pci_physaddr; 1227 report(vmx_get_test_stage() == 6, "MMIO EPT violation - read"); 1228 1229 *(u32 volatile *)pci_physaddr = MAGIC_VAL_1; 1230 report(vmx_get_test_stage() == 7, "MMIO EPT violation - write"); 1231 } 1232 1233 static void ept_main(void) 1234 { 1235 ept_common(); 1236 1237 // Test EPT access to L1 MMIO 1238 vmx_set_test_stage(7); 1239 report(*((u32 *)0xfee00030UL) == apic_version, "EPT - MMIO access"); 1240 1241 // Test invalid operand for INVEPT 1242 vmcall(); 1243 report(vmx_get_test_stage() == 8, "EPT - unsupported INVEPT"); 1244 } 1245 1246 static bool invept_test(int type, u64 eptp) 1247 { 1248 bool ret, supported; 1249 1250 supported = ept_vpid.val & (EPT_CAP_INVEPT_SINGLE >> INVEPT_SINGLE << type); 1251 ret = __invept(type, eptp); 1252 1253 if (ret == !supported) 1254 return false; 1255 1256 if (!supported) 1257 printf("WARNING: unsupported invept passed!\n"); 1258 else 1259 printf("WARNING: invept failed!\n"); 1260 1261 return true; 1262 } 1263 1264 static int pml_exit_handler(union exit_reason exit_reason) 1265 { 1266 u16 index, count; 1267 u64 *pmlbuf = pml_log; 1268 u64 guest_rip = vmcs_read(GUEST_RIP);; 1269 u64 guest_cr3 = vmcs_read(GUEST_CR3); 1270 u32 insn_len = vmcs_read(EXI_INST_LEN); 1271 1272 switch (exit_reason.basic) { 1273 case VMX_VMCALL: 1274 switch (vmx_get_test_stage()) { 1275 case 0: 1276 index = vmcs_read(GUEST_PML_INDEX); 1277 for (count = index + 1; count < PML_INDEX; count++) { 1278 if (pmlbuf[count] == (u64)data_page2) { 1279 vmx_inc_test_stage(); 1280 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1281 break; 1282 } 1283 } 1284 break; 1285 case 1: 1286 index = vmcs_read(GUEST_PML_INDEX); 1287 /* Keep clearing the dirty bit till a overflow */ 1288 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1289 break; 1290 default: 1291 report_fail("unexpected stage, %d.", 1292 vmx_get_test_stage()); 1293 print_vmexit_info(exit_reason); 1294 return VMX_TEST_VMEXIT; 1295 } 1296 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1297 return VMX_TEST_RESUME; 1298 case VMX_PML_FULL: 1299 vmx_inc_test_stage(); 1300 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1301 return VMX_TEST_RESUME; 1302 default: 1303 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 1304 print_vmexit_info(exit_reason); 1305 } 1306 return VMX_TEST_VMEXIT; 1307 } 1308 1309 static int ept_exit_handler_common(union exit_reason exit_reason, bool have_ad) 1310 { 1311 u64 guest_rip; 1312 u64 guest_cr3; 1313 u32 insn_len; 1314 u32 exit_qual; 1315 static unsigned long data_page1_pte, data_page1_pte_pte, memaddr_pte, 1316 guest_pte_addr; 1317 1318 guest_rip = vmcs_read(GUEST_RIP); 1319 guest_cr3 = vmcs_read(GUEST_CR3); 1320 insn_len = vmcs_read(EXI_INST_LEN); 1321 exit_qual = vmcs_read(EXI_QUALIFICATION); 1322 pteval_t *ptep; 1323 switch (exit_reason.basic) { 1324 case VMX_VMCALL: 1325 switch (vmx_get_test_stage()) { 1326 case 0: 1327 check_ept_ad(pml4, guest_cr3, 1328 (unsigned long)data_page1, 1329 have_ad ? EPT_ACCESS_FLAG : 0, 1330 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1331 check_ept_ad(pml4, guest_cr3, 1332 (unsigned long)data_page2, 1333 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0, 1334 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1335 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1336 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1337 if (have_ad) 1338 ept_sync(INVEPT_SINGLE, eptp);; 1339 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1340 *((u32 *)data_page2) == MAGIC_VAL_2) { 1341 vmx_inc_test_stage(); 1342 install_ept(pml4, (unsigned long)data_page2, 1343 (unsigned long)data_page2, 1344 EPT_RA | EPT_WA | EPT_EA); 1345 } else 1346 report_fail("EPT basic framework - write"); 1347 break; 1348 case 1: 1349 install_ept(pml4, (unsigned long)data_page1, 1350 (unsigned long)data_page1, EPT_WA); 1351 ept_sync(INVEPT_SINGLE, eptp); 1352 break; 1353 case 2: 1354 install_ept(pml4, (unsigned long)data_page1, 1355 (unsigned long)data_page1, 1356 EPT_RA | EPT_WA | EPT_EA | 1357 (2 << EPT_MEM_TYPE_SHIFT)); 1358 ept_sync(INVEPT_SINGLE, eptp); 1359 break; 1360 case 3: 1361 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1362 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)data_page1, 1363 1, &data_page1_pte)); 1364 set_ept_pte(pml4, (unsigned long)data_page1, 1365 1, data_page1_pte & ~EPT_PRESENT); 1366 ept_sync(INVEPT_SINGLE, eptp); 1367 break; 1368 case 4: 1369 ptep = get_pte_level((pgd_t *)guest_cr3, data_page1, /*level=*/2); 1370 guest_pte_addr = virt_to_phys(ptep) & PAGE_MASK; 1371 1372 TEST_ASSERT(get_ept_pte(pml4, guest_pte_addr, 2, &data_page1_pte_pte)); 1373 set_ept_pte(pml4, guest_pte_addr, 2, 1374 data_page1_pte_pte & ~EPT_PRESENT); 1375 ept_sync(INVEPT_SINGLE, eptp); 1376 break; 1377 case 5: 1378 install_ept(pml4, (unsigned long)pci_physaddr, 1379 (unsigned long)pci_physaddr, 0); 1380 ept_sync(INVEPT_SINGLE, eptp); 1381 break; 1382 case 7: 1383 if (!invept_test(0, eptp)) 1384 vmx_inc_test_stage(); 1385 break; 1386 // Should not reach here 1387 default: 1388 report_fail("ERROR - unexpected stage, %d.", 1389 vmx_get_test_stage()); 1390 print_vmexit_info(exit_reason); 1391 return VMX_TEST_VMEXIT; 1392 } 1393 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1394 return VMX_TEST_RESUME; 1395 case VMX_EPT_MISCONFIG: 1396 switch (vmx_get_test_stage()) { 1397 case 1: 1398 case 2: 1399 vmx_inc_test_stage(); 1400 install_ept(pml4, (unsigned long)data_page1, 1401 (unsigned long)data_page1, 1402 EPT_RA | EPT_WA | EPT_EA); 1403 ept_sync(INVEPT_SINGLE, eptp); 1404 break; 1405 // Should not reach here 1406 default: 1407 report_fail("ERROR - unexpected stage, %d.", 1408 vmx_get_test_stage()); 1409 print_vmexit_info(exit_reason); 1410 return VMX_TEST_VMEXIT; 1411 } 1412 return VMX_TEST_RESUME; 1413 case VMX_EPT_VIOLATION: 1414 /* 1415 * Exit-qualifications are masked not to account for advanced 1416 * VM-exit information. Once KVM supports this feature, this 1417 * masking should be removed. 1418 */ 1419 exit_qual &= ~EPT_VLT_GUEST_MASK; 1420 1421 switch(vmx_get_test_stage()) { 1422 case 3: 1423 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1424 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1425 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1426 if (exit_qual == (EPT_VLT_WR | EPT_VLT_LADDR_VLD | 1427 EPT_VLT_PADDR)) 1428 vmx_inc_test_stage(); 1429 set_ept_pte(pml4, (unsigned long)data_page1, 1430 1, data_page1_pte | (EPT_PRESENT)); 1431 ept_sync(INVEPT_SINGLE, eptp); 1432 break; 1433 case 4: 1434 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1435 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1436 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1437 if (exit_qual == (EPT_VLT_RD | 1438 (have_ad ? EPT_VLT_WR : 0) | 1439 EPT_VLT_LADDR_VLD)) 1440 vmx_inc_test_stage(); 1441 set_ept_pte(pml4, guest_pte_addr, 2, 1442 data_page1_pte_pte | (EPT_PRESENT)); 1443 ept_sync(INVEPT_SINGLE, eptp); 1444 break; 1445 case 5: 1446 if (exit_qual & EPT_VLT_RD) 1447 vmx_inc_test_stage(); 1448 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1449 1, &memaddr_pte)); 1450 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA); 1451 ept_sync(INVEPT_SINGLE, eptp); 1452 break; 1453 case 6: 1454 if (exit_qual & EPT_VLT_WR) 1455 vmx_inc_test_stage(); 1456 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1457 1, &memaddr_pte)); 1458 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA | EPT_WA); 1459 ept_sync(INVEPT_SINGLE, eptp); 1460 break; 1461 default: 1462 // Should not reach here 1463 report_fail("ERROR : unexpected stage, %d", 1464 vmx_get_test_stage()); 1465 print_vmexit_info(exit_reason); 1466 return VMX_TEST_VMEXIT; 1467 } 1468 return VMX_TEST_RESUME; 1469 default: 1470 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 1471 print_vmexit_info(exit_reason); 1472 } 1473 return VMX_TEST_VMEXIT; 1474 } 1475 1476 static int ept_exit_handler(union exit_reason exit_reason) 1477 { 1478 return ept_exit_handler_common(exit_reason, false); 1479 } 1480 1481 static int eptad_init(struct vmcs *vmcs) 1482 { 1483 int r = ept_init_common(true); 1484 1485 if (r == VMX_TEST_EXIT) 1486 return r; 1487 1488 if ((rdmsr(MSR_IA32_VMX_EPT_VPID_CAP) & EPT_CAP_AD_FLAG) == 0) { 1489 printf("\tEPT A/D bits are not supported"); 1490 return VMX_TEST_EXIT; 1491 } 1492 1493 return r; 1494 } 1495 1496 static int pml_init(struct vmcs *vmcs) 1497 { 1498 u32 ctrl_cpu; 1499 int r = eptad_init(vmcs); 1500 1501 if (r == VMX_TEST_EXIT) 1502 return r; 1503 1504 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1505 !(ctrl_cpu_rev[1].clr & CPU_PML)) { 1506 printf("\tPML is not supported"); 1507 return VMX_TEST_EXIT; 1508 } 1509 1510 pml_log = alloc_page(); 1511 vmcs_write(PMLADDR, (u64)pml_log); 1512 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1513 1514 ctrl_cpu = vmcs_read(CPU_EXEC_CTRL1) | CPU_PML; 1515 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu); 1516 1517 return VMX_TEST_START; 1518 } 1519 1520 static void pml_main(void) 1521 { 1522 int count = 0; 1523 1524 vmx_set_test_stage(0); 1525 *((u32 *)data_page2) = 0x1; 1526 vmcall(); 1527 report(vmx_get_test_stage() == 1, "PML - Dirty GPA Logging"); 1528 1529 while (vmx_get_test_stage() == 1) { 1530 vmcall(); 1531 *((u32 *)data_page2) = 0x1; 1532 if (count++ > PML_INDEX) 1533 break; 1534 } 1535 report(vmx_get_test_stage() == 2, "PML Full Event"); 1536 } 1537 1538 static void eptad_main(void) 1539 { 1540 ept_common(); 1541 } 1542 1543 static int eptad_exit_handler(union exit_reason exit_reason) 1544 { 1545 return ept_exit_handler_common(exit_reason, true); 1546 } 1547 1548 static bool invvpid_test(int type, u16 vpid) 1549 { 1550 bool ret, supported; 1551 1552 supported = ept_vpid.val & 1553 (VPID_CAP_INVVPID_ADDR >> INVVPID_ADDR << type); 1554 ret = __invvpid(type, vpid, 0); 1555 1556 if (ret == !supported) 1557 return false; 1558 1559 if (!supported) 1560 printf("WARNING: unsupported invvpid passed!\n"); 1561 else 1562 printf("WARNING: invvpid failed!\n"); 1563 1564 return true; 1565 } 1566 1567 static int vpid_init(struct vmcs *vmcs) 1568 { 1569 u32 ctrl_cpu1; 1570 1571 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1572 !(ctrl_cpu_rev[1].clr & CPU_VPID)) { 1573 printf("\tVPID is not supported"); 1574 return VMX_TEST_EXIT; 1575 } 1576 1577 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 1578 ctrl_cpu1 |= CPU_VPID; 1579 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 1580 return VMX_TEST_START; 1581 } 1582 1583 static void vpid_main(void) 1584 { 1585 vmx_set_test_stage(0); 1586 vmcall(); 1587 report(vmx_get_test_stage() == 1, "INVVPID SINGLE ADDRESS"); 1588 vmx_set_test_stage(2); 1589 vmcall(); 1590 report(vmx_get_test_stage() == 3, "INVVPID SINGLE"); 1591 vmx_set_test_stage(4); 1592 vmcall(); 1593 report(vmx_get_test_stage() == 5, "INVVPID ALL"); 1594 } 1595 1596 static int vpid_exit_handler(union exit_reason exit_reason) 1597 { 1598 u64 guest_rip; 1599 u32 insn_len; 1600 1601 guest_rip = vmcs_read(GUEST_RIP); 1602 insn_len = vmcs_read(EXI_INST_LEN); 1603 1604 switch (exit_reason.basic) { 1605 case VMX_VMCALL: 1606 switch(vmx_get_test_stage()) { 1607 case 0: 1608 if (!invvpid_test(INVVPID_ADDR, 1)) 1609 vmx_inc_test_stage(); 1610 break; 1611 case 2: 1612 if (!invvpid_test(INVVPID_CONTEXT_GLOBAL, 1)) 1613 vmx_inc_test_stage(); 1614 break; 1615 case 4: 1616 if (!invvpid_test(INVVPID_ALL, 1)) 1617 vmx_inc_test_stage(); 1618 break; 1619 default: 1620 report_fail("ERROR: unexpected stage, %d", 1621 vmx_get_test_stage()); 1622 print_vmexit_info(exit_reason); 1623 return VMX_TEST_VMEXIT; 1624 } 1625 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1626 return VMX_TEST_RESUME; 1627 default: 1628 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 1629 print_vmexit_info(exit_reason); 1630 } 1631 return VMX_TEST_VMEXIT; 1632 } 1633 1634 #define TIMER_VECTOR 222 1635 1636 static volatile bool timer_fired; 1637 1638 static void timer_isr(isr_regs_t *regs) 1639 { 1640 timer_fired = true; 1641 apic_write(APIC_EOI, 0); 1642 } 1643 1644 static int interrupt_init(struct vmcs *vmcs) 1645 { 1646 msr_bmp_init(); 1647 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1648 handle_irq(TIMER_VECTOR, timer_isr); 1649 return VMX_TEST_START; 1650 } 1651 1652 static void interrupt_main(void) 1653 { 1654 long long start, loops; 1655 1656 vmx_set_test_stage(0); 1657 1658 apic_write(APIC_LVTT, TIMER_VECTOR); 1659 irq_enable(); 1660 1661 apic_write(APIC_TMICT, 1); 1662 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1663 asm volatile ("nop"); 1664 report(timer_fired, "direct interrupt while running guest"); 1665 1666 apic_write(APIC_TMICT, 0); 1667 irq_disable(); 1668 vmcall(); 1669 timer_fired = false; 1670 apic_write(APIC_TMICT, 1); 1671 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1672 asm volatile ("nop"); 1673 report(timer_fired, "intercepted interrupt while running guest"); 1674 1675 irq_enable(); 1676 apic_write(APIC_TMICT, 0); 1677 irq_disable(); 1678 vmcall(); 1679 timer_fired = false; 1680 start = rdtsc(); 1681 apic_write(APIC_TMICT, 1000000); 1682 1683 safe_halt(); 1684 1685 report(rdtsc() - start > 1000000 && timer_fired, 1686 "direct interrupt + hlt"); 1687 1688 apic_write(APIC_TMICT, 0); 1689 irq_disable(); 1690 vmcall(); 1691 timer_fired = false; 1692 start = rdtsc(); 1693 apic_write(APIC_TMICT, 1000000); 1694 1695 safe_halt(); 1696 1697 report(rdtsc() - start > 10000 && timer_fired, 1698 "intercepted interrupt + hlt"); 1699 1700 apic_write(APIC_TMICT, 0); 1701 irq_disable(); 1702 vmcall(); 1703 timer_fired = false; 1704 start = rdtsc(); 1705 apic_write(APIC_TMICT, 1000000); 1706 1707 irq_enable(); 1708 asm volatile ("nop"); 1709 vmcall(); 1710 1711 report(rdtsc() - start > 10000 && timer_fired, 1712 "direct interrupt + activity state hlt"); 1713 1714 apic_write(APIC_TMICT, 0); 1715 irq_disable(); 1716 vmcall(); 1717 timer_fired = false; 1718 start = rdtsc(); 1719 apic_write(APIC_TMICT, 1000000); 1720 1721 irq_enable(); 1722 asm volatile ("nop"); 1723 vmcall(); 1724 1725 report(rdtsc() - start > 10000 && timer_fired, 1726 "intercepted interrupt + activity state hlt"); 1727 1728 apic_write(APIC_TMICT, 0); 1729 irq_disable(); 1730 vmx_set_test_stage(7); 1731 vmcall(); 1732 timer_fired = false; 1733 apic_write(APIC_TMICT, 1); 1734 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1735 asm volatile ("nop"); 1736 report(timer_fired, 1737 "running a guest with interrupt acknowledgement set"); 1738 1739 apic_write(APIC_TMICT, 0); 1740 irq_enable(); 1741 timer_fired = false; 1742 vmcall(); 1743 report(timer_fired, "Inject an event to a halted guest"); 1744 } 1745 1746 static int interrupt_exit_handler(union exit_reason exit_reason) 1747 { 1748 u64 guest_rip = vmcs_read(GUEST_RIP); 1749 u32 insn_len = vmcs_read(EXI_INST_LEN); 1750 1751 switch (exit_reason.basic) { 1752 case VMX_VMCALL: 1753 switch (vmx_get_test_stage()) { 1754 case 0: 1755 case 2: 1756 case 5: 1757 vmcs_write(PIN_CONTROLS, 1758 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1759 break; 1760 case 7: 1761 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_INTA); 1762 vmcs_write(PIN_CONTROLS, 1763 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1764 break; 1765 case 1: 1766 case 3: 1767 vmcs_write(PIN_CONTROLS, 1768 vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1769 break; 1770 case 4: 1771 case 6: 1772 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1773 break; 1774 1775 case 8: 1776 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1777 vmcs_write(ENT_INTR_INFO, 1778 TIMER_VECTOR | 1779 (VMX_INTR_TYPE_EXT_INTR << INTR_INFO_INTR_TYPE_SHIFT) | 1780 INTR_INFO_VALID_MASK); 1781 break; 1782 } 1783 vmx_inc_test_stage(); 1784 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1785 return VMX_TEST_RESUME; 1786 case VMX_EXTINT: 1787 if (vmcs_read(EXI_CONTROLS) & EXI_INTA) { 1788 int vector = vmcs_read(EXI_INTR_INFO) & 0xff; 1789 handle_external_interrupt(vector); 1790 } else { 1791 irq_enable(); 1792 asm volatile ("nop"); 1793 irq_disable(); 1794 } 1795 if (vmx_get_test_stage() >= 2) 1796 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 1797 return VMX_TEST_RESUME; 1798 default: 1799 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 1800 print_vmexit_info(exit_reason); 1801 } 1802 1803 return VMX_TEST_VMEXIT; 1804 } 1805 1806 1807 static volatile int nmi_fired; 1808 1809 #define NMI_DELAY 100000000ULL 1810 1811 static void nmi_isr(isr_regs_t *regs) 1812 { 1813 nmi_fired = true; 1814 } 1815 1816 static int nmi_hlt_init(struct vmcs *vmcs) 1817 { 1818 msr_bmp_init(); 1819 handle_irq(NMI_VECTOR, nmi_isr); 1820 vmcs_write(PIN_CONTROLS, 1821 vmcs_read(PIN_CONTROLS) & ~PIN_NMI); 1822 vmcs_write(PIN_CONTROLS, 1823 vmcs_read(PIN_CONTROLS) & ~PIN_VIRT_NMI); 1824 return VMX_TEST_START; 1825 } 1826 1827 static void nmi_message_thread(void *data) 1828 { 1829 while (vmx_get_test_stage() != 1) 1830 pause(); 1831 1832 delay(NMI_DELAY); 1833 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_NMI | APIC_INT_ASSERT, id_map[0]); 1834 1835 while (vmx_get_test_stage() != 2) 1836 pause(); 1837 1838 delay(NMI_DELAY); 1839 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_NMI | APIC_INT_ASSERT, id_map[0]); 1840 } 1841 1842 static void nmi_hlt_main(void) 1843 { 1844 long long start; 1845 1846 if (cpu_count() < 2) { 1847 report_skip(__func__); 1848 vmx_set_test_stage(-1); 1849 return; 1850 } 1851 1852 vmx_set_test_stage(0); 1853 on_cpu_async(1, nmi_message_thread, NULL); 1854 start = rdtsc(); 1855 vmx_set_test_stage(1); 1856 asm volatile ("hlt"); 1857 report((rdtsc() - start > NMI_DELAY) && nmi_fired, 1858 "direct NMI + hlt"); 1859 if (!nmi_fired) 1860 vmx_set_test_stage(-1); 1861 nmi_fired = false; 1862 1863 vmcall(); 1864 1865 start = rdtsc(); 1866 vmx_set_test_stage(2); 1867 asm volatile ("hlt"); 1868 report((rdtsc() - start > NMI_DELAY) && !nmi_fired, 1869 "intercepted NMI + hlt"); 1870 if (nmi_fired) { 1871 report(!nmi_fired, "intercepted NMI was dispatched"); 1872 vmx_set_test_stage(-1); 1873 return; 1874 } 1875 vmx_set_test_stage(3); 1876 } 1877 1878 static int nmi_hlt_exit_handler(union exit_reason exit_reason) 1879 { 1880 u64 guest_rip = vmcs_read(GUEST_RIP); 1881 u32 insn_len = vmcs_read(EXI_INST_LEN); 1882 1883 switch (vmx_get_test_stage()) { 1884 case 1: 1885 if (exit_reason.basic != VMX_VMCALL) { 1886 report_fail("VMEXIT not due to vmcall. Exit reason 0x%x", 1887 exit_reason.full); 1888 print_vmexit_info(exit_reason); 1889 return VMX_TEST_VMEXIT; 1890 } 1891 1892 vmcs_write(PIN_CONTROLS, 1893 vmcs_read(PIN_CONTROLS) | PIN_NMI); 1894 vmcs_write(PIN_CONTROLS, 1895 vmcs_read(PIN_CONTROLS) | PIN_VIRT_NMI); 1896 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1897 break; 1898 1899 case 2: 1900 if (exit_reason.basic != VMX_EXC_NMI) { 1901 report_fail("VMEXIT not due to NMI intercept. Exit reason 0x%x", 1902 exit_reason.full); 1903 print_vmexit_info(exit_reason); 1904 return VMX_TEST_VMEXIT; 1905 } 1906 report_pass("NMI intercept while running guest"); 1907 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 1908 break; 1909 1910 case 3: 1911 break; 1912 1913 default: 1914 return VMX_TEST_VMEXIT; 1915 } 1916 1917 if (vmx_get_test_stage() == 3) 1918 return VMX_TEST_VMEXIT; 1919 1920 return VMX_TEST_RESUME; 1921 } 1922 1923 1924 static int dbgctls_init(struct vmcs *vmcs) 1925 { 1926 u64 dr7 = 0x402; 1927 u64 zero = 0; 1928 1929 msr_bmp_init(); 1930 asm volatile( 1931 "mov %0,%%dr0\n\t" 1932 "mov %0,%%dr1\n\t" 1933 "mov %0,%%dr2\n\t" 1934 "mov %1,%%dr7\n\t" 1935 : : "r" (zero), "r" (dr7)); 1936 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1937 vmcs_write(GUEST_DR7, 0x404); 1938 vmcs_write(GUEST_DEBUGCTL, 0x2); 1939 1940 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 1941 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_SAVE_DBGCTLS); 1942 1943 return VMX_TEST_START; 1944 } 1945 1946 static void dbgctls_main(void) 1947 { 1948 u64 dr7, debugctl; 1949 1950 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1951 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1952 /* Commented out: KVM does not support DEBUGCTL so far */ 1953 (void)debugctl; 1954 report(dr7 == 0x404, "Load debug controls" /* && debugctl == 0x2 */); 1955 1956 dr7 = 0x408; 1957 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1958 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1959 1960 vmx_set_test_stage(0); 1961 vmcall(); 1962 report(vmx_get_test_stage() == 1, "Save debug controls"); 1963 1964 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS || 1965 ctrl_exit_rev.set & EXI_SAVE_DBGCTLS) { 1966 printf("\tDebug controls are always loaded/saved\n"); 1967 return; 1968 } 1969 vmx_set_test_stage(2); 1970 vmcall(); 1971 1972 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1973 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1974 /* Commented out: KVM does not support DEBUGCTL so far */ 1975 (void)debugctl; 1976 report(dr7 == 0x402, 1977 "Guest=host debug controls" /* && debugctl == 0x1 */); 1978 1979 dr7 = 0x408; 1980 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1981 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1982 1983 vmx_set_test_stage(3); 1984 vmcall(); 1985 report(vmx_get_test_stage() == 4, "Don't save debug controls"); 1986 } 1987 1988 static int dbgctls_exit_handler(union exit_reason exit_reason) 1989 { 1990 u32 insn_len = vmcs_read(EXI_INST_LEN); 1991 u64 guest_rip = vmcs_read(GUEST_RIP); 1992 u64 dr7, debugctl; 1993 1994 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1995 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1996 1997 switch (exit_reason.basic) { 1998 case VMX_VMCALL: 1999 switch (vmx_get_test_stage()) { 2000 case 0: 2001 if (dr7 == 0x400 && debugctl == 0 && 2002 vmcs_read(GUEST_DR7) == 0x408 /* && 2003 Commented out: KVM does not support DEBUGCTL so far 2004 vmcs_read(GUEST_DEBUGCTL) == 0x3 */) 2005 vmx_inc_test_stage(); 2006 break; 2007 case 2: 2008 dr7 = 0x402; 2009 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 2010 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 2011 vmcs_write(GUEST_DR7, 0x404); 2012 vmcs_write(GUEST_DEBUGCTL, 0x2); 2013 2014 vmcs_write(ENT_CONTROLS, 2015 vmcs_read(ENT_CONTROLS) & ~ENT_LOAD_DBGCTLS); 2016 vmcs_write(EXI_CONTROLS, 2017 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_DBGCTLS); 2018 break; 2019 case 3: 2020 if (dr7 == 0x400 && debugctl == 0 && 2021 vmcs_read(GUEST_DR7) == 0x404 /* && 2022 Commented out: KVM does not support DEBUGCTL so far 2023 vmcs_read(GUEST_DEBUGCTL) == 0x2 */) 2024 vmx_inc_test_stage(); 2025 break; 2026 } 2027 vmcs_write(GUEST_RIP, guest_rip + insn_len); 2028 return VMX_TEST_RESUME; 2029 default: 2030 report_fail("Unknown exit reason, %d", exit_reason.full); 2031 print_vmexit_info(exit_reason); 2032 } 2033 return VMX_TEST_VMEXIT; 2034 } 2035 2036 struct vmx_msr_entry { 2037 u32 index; 2038 u32 reserved; 2039 u64 value; 2040 } __attribute__((packed)); 2041 2042 #define MSR_MAGIC 0x31415926 2043 struct vmx_msr_entry *exit_msr_store, *entry_msr_load, *exit_msr_load; 2044 2045 static int msr_switch_init(struct vmcs *vmcs) 2046 { 2047 msr_bmp_init(); 2048 exit_msr_store = alloc_page(); 2049 exit_msr_load = alloc_page(); 2050 entry_msr_load = alloc_page(); 2051 entry_msr_load[0].index = MSR_KERNEL_GS_BASE; 2052 entry_msr_load[0].value = MSR_MAGIC; 2053 2054 vmx_set_test_stage(1); 2055 vmcs_write(ENT_MSR_LD_CNT, 1); 2056 vmcs_write(ENTER_MSR_LD_ADDR, (u64)entry_msr_load); 2057 vmcs_write(EXI_MSR_ST_CNT, 1); 2058 vmcs_write(EXIT_MSR_ST_ADDR, (u64)exit_msr_store); 2059 vmcs_write(EXI_MSR_LD_CNT, 1); 2060 vmcs_write(EXIT_MSR_LD_ADDR, (u64)exit_msr_load); 2061 return VMX_TEST_START; 2062 } 2063 2064 static void msr_switch_main(void) 2065 { 2066 if (vmx_get_test_stage() == 1) { 2067 report(rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC, 2068 "VM entry MSR load"); 2069 vmx_set_test_stage(2); 2070 wrmsr(MSR_KERNEL_GS_BASE, MSR_MAGIC + 1); 2071 exit_msr_store[0].index = MSR_KERNEL_GS_BASE; 2072 exit_msr_load[0].index = MSR_KERNEL_GS_BASE; 2073 exit_msr_load[0].value = MSR_MAGIC + 2; 2074 } 2075 vmcall(); 2076 } 2077 2078 static int msr_switch_exit_handler(union exit_reason exit_reason) 2079 { 2080 if (exit_reason.basic == VMX_VMCALL && vmx_get_test_stage() == 2) { 2081 report(exit_msr_store[0].value == MSR_MAGIC + 1, 2082 "VM exit MSR store"); 2083 report(rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC + 2, 2084 "VM exit MSR load"); 2085 vmx_set_test_stage(3); 2086 entry_msr_load[0].index = MSR_FS_BASE; 2087 return VMX_TEST_RESUME; 2088 } 2089 printf("ERROR %s: unexpected stage=%u or reason=0x%x\n", 2090 __func__, vmx_get_test_stage(), exit_reason.full); 2091 return VMX_TEST_EXIT; 2092 } 2093 2094 static int msr_switch_entry_failure(struct vmentry_result *result) 2095 { 2096 if (result->vm_fail) { 2097 printf("ERROR %s: VM-Fail on %s\n", __func__, result->instr); 2098 return VMX_TEST_EXIT; 2099 } 2100 2101 if (result->exit_reason.failed_vmentry && 2102 result->exit_reason.basic == VMX_FAIL_MSR && 2103 vmx_get_test_stage() == 3) { 2104 report(vmcs_read(EXI_QUALIFICATION) == 1, 2105 "VM entry MSR load: try to load FS_BASE"); 2106 return VMX_TEST_VMEXIT; 2107 } 2108 printf("ERROR %s: unexpected stage=%u or reason=%x\n", 2109 __func__, vmx_get_test_stage(), result->exit_reason.full); 2110 return VMX_TEST_EXIT; 2111 } 2112 2113 static int vmmcall_init(struct vmcs *vmcs) 2114 { 2115 vmcs_write(EXC_BITMAP, 1 << UD_VECTOR); 2116 return VMX_TEST_START; 2117 } 2118 2119 static void vmmcall_main(void) 2120 { 2121 asm volatile( 2122 "mov $0xABCD, %%rax\n\t" 2123 "vmmcall\n\t" 2124 ::: "rax"); 2125 2126 report_fail("VMMCALL"); 2127 } 2128 2129 static int vmmcall_exit_handler(union exit_reason exit_reason) 2130 { 2131 switch (exit_reason.basic) { 2132 case VMX_VMCALL: 2133 printf("here\n"); 2134 report_fail("VMMCALL triggers #UD"); 2135 break; 2136 case VMX_EXC_NMI: 2137 report((vmcs_read(EXI_INTR_INFO) & 0xff) == UD_VECTOR, 2138 "VMMCALL triggers #UD"); 2139 break; 2140 default: 2141 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 2142 print_vmexit_info(exit_reason); 2143 } 2144 2145 return VMX_TEST_VMEXIT; 2146 } 2147 2148 static int disable_rdtscp_init(struct vmcs *vmcs) 2149 { 2150 u32 ctrl_cpu1; 2151 2152 if (ctrl_cpu_rev[0].clr & CPU_SECONDARY) { 2153 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 2154 ctrl_cpu1 &= ~CPU_RDTSCP; 2155 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 2156 } 2157 2158 return VMX_TEST_START; 2159 } 2160 2161 static void disable_rdtscp_ud_handler(struct ex_regs *regs) 2162 { 2163 switch (vmx_get_test_stage()) { 2164 case 0: 2165 report_pass("RDTSCP triggers #UD"); 2166 vmx_inc_test_stage(); 2167 regs->rip += 3; 2168 break; 2169 case 2: 2170 report_pass("RDPID triggers #UD"); 2171 vmx_inc_test_stage(); 2172 regs->rip += 4; 2173 break; 2174 } 2175 return; 2176 2177 } 2178 2179 static void disable_rdtscp_main(void) 2180 { 2181 /* Test that #UD is properly injected in L2. */ 2182 handle_exception(UD_VECTOR, disable_rdtscp_ud_handler); 2183 2184 vmx_set_test_stage(0); 2185 asm volatile("rdtscp" : : : "eax", "ecx", "edx"); 2186 vmcall(); 2187 asm volatile(".byte 0xf3, 0x0f, 0xc7, 0xf8" : : : "eax"); 2188 2189 handle_exception(UD_VECTOR, 0); 2190 vmcall(); 2191 } 2192 2193 static int disable_rdtscp_exit_handler(union exit_reason exit_reason) 2194 { 2195 switch (exit_reason.basic) { 2196 case VMX_VMCALL: 2197 switch (vmx_get_test_stage()) { 2198 case 0: 2199 report_fail("RDTSCP triggers #UD"); 2200 vmx_inc_test_stage(); 2201 /* fallthrough */ 2202 case 1: 2203 vmx_inc_test_stage(); 2204 vmcs_write(GUEST_RIP, vmcs_read(GUEST_RIP) + 3); 2205 return VMX_TEST_RESUME; 2206 case 2: 2207 report_fail("RDPID triggers #UD"); 2208 break; 2209 } 2210 break; 2211 2212 default: 2213 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 2214 print_vmexit_info(exit_reason); 2215 } 2216 return VMX_TEST_VMEXIT; 2217 } 2218 2219 static int int3_init(struct vmcs *vmcs) 2220 { 2221 vmcs_write(EXC_BITMAP, ~0u); 2222 return VMX_TEST_START; 2223 } 2224 2225 static void int3_guest_main(void) 2226 { 2227 asm volatile ("int3"); 2228 } 2229 2230 static int int3_exit_handler(union exit_reason exit_reason) 2231 { 2232 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2233 2234 report(exit_reason.basic == VMX_EXC_NMI && 2235 (intr_info & INTR_INFO_VALID_MASK) && 2236 (intr_info & INTR_INFO_VECTOR_MASK) == BP_VECTOR && 2237 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2238 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION, 2239 "L1 intercepts #BP"); 2240 2241 return VMX_TEST_VMEXIT; 2242 } 2243 2244 static int into_init(struct vmcs *vmcs) 2245 { 2246 vmcs_write(EXC_BITMAP, ~0u); 2247 return VMX_TEST_START; 2248 } 2249 2250 static void into_guest_main(void) 2251 { 2252 struct far_pointer32 fp = { 2253 .offset = (uintptr_t)&&into, 2254 .selector = KERNEL_CS32, 2255 }; 2256 uintptr_t rsp; 2257 2258 asm volatile ("mov %%rsp, %0" : "=r"(rsp)); 2259 2260 if (fp.offset != (uintptr_t)&&into) { 2261 printf("Code address too high.\n"); 2262 return; 2263 } 2264 if ((u32)rsp != rsp) { 2265 printf("Stack address too high.\n"); 2266 return; 2267 } 2268 2269 asm goto ("lcall *%0" : : "m" (fp) : "rax" : into); 2270 return; 2271 into: 2272 asm volatile (".code32;" 2273 "movl $0x7fffffff, %eax;" 2274 "addl %eax, %eax;" 2275 "into;" 2276 "lret;" 2277 ".code64"); 2278 __builtin_unreachable(); 2279 } 2280 2281 static int into_exit_handler(union exit_reason exit_reason) 2282 { 2283 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2284 2285 report(exit_reason.basic == VMX_EXC_NMI && 2286 (intr_info & INTR_INFO_VALID_MASK) && 2287 (intr_info & INTR_INFO_VECTOR_MASK) == OF_VECTOR && 2288 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2289 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION, 2290 "L1 intercepts #OF"); 2291 2292 return VMX_TEST_VMEXIT; 2293 } 2294 2295 static void exit_monitor_from_l2_main(void) 2296 { 2297 printf("Calling exit(0) from l2...\n"); 2298 exit(0); 2299 } 2300 2301 static int exit_monitor_from_l2_handler(union exit_reason exit_reason) 2302 { 2303 report_fail("The guest should have killed the VMM"); 2304 return VMX_TEST_EXIT; 2305 } 2306 2307 static void assert_exit_reason(u64 expected) 2308 { 2309 u64 actual = vmcs_read(EXI_REASON); 2310 2311 TEST_ASSERT_EQ_MSG(expected, actual, "Expected %s, got %s.", 2312 exit_reason_description(expected), 2313 exit_reason_description(actual)); 2314 } 2315 2316 static void skip_exit_insn(void) 2317 { 2318 u64 guest_rip = vmcs_read(GUEST_RIP); 2319 u32 insn_len = vmcs_read(EXI_INST_LEN); 2320 vmcs_write(GUEST_RIP, guest_rip + insn_len); 2321 } 2322 2323 static void skip_exit_vmcall(void) 2324 { 2325 assert_exit_reason(VMX_VMCALL); 2326 skip_exit_insn(); 2327 } 2328 2329 static void v2_null_test_guest(void) 2330 { 2331 } 2332 2333 static void v2_null_test(void) 2334 { 2335 test_set_guest(v2_null_test_guest); 2336 enter_guest(); 2337 report_pass(__func__); 2338 } 2339 2340 static void v2_multiple_entries_test_guest(void) 2341 { 2342 vmx_set_test_stage(1); 2343 vmcall(); 2344 vmx_set_test_stage(2); 2345 } 2346 2347 static void v2_multiple_entries_test(void) 2348 { 2349 test_set_guest(v2_multiple_entries_test_guest); 2350 enter_guest(); 2351 TEST_ASSERT_EQ(vmx_get_test_stage(), 1); 2352 skip_exit_vmcall(); 2353 enter_guest(); 2354 TEST_ASSERT_EQ(vmx_get_test_stage(), 2); 2355 report_pass(__func__); 2356 } 2357 2358 static int fixture_test_data = 1; 2359 2360 static void fixture_test_teardown(void *data) 2361 { 2362 *((int *) data) = 1; 2363 } 2364 2365 static void fixture_test_guest(void) 2366 { 2367 fixture_test_data++; 2368 } 2369 2370 2371 static void fixture_test_setup(void) 2372 { 2373 TEST_ASSERT_EQ_MSG(1, fixture_test_data, 2374 "fixture_test_teardown didn't run?!"); 2375 fixture_test_data = 2; 2376 test_add_teardown(fixture_test_teardown, &fixture_test_data); 2377 test_set_guest(fixture_test_guest); 2378 } 2379 2380 static void fixture_test_case1(void) 2381 { 2382 fixture_test_setup(); 2383 TEST_ASSERT_EQ(2, fixture_test_data); 2384 enter_guest(); 2385 TEST_ASSERT_EQ(3, fixture_test_data); 2386 report_pass(__func__); 2387 } 2388 2389 static void fixture_test_case2(void) 2390 { 2391 fixture_test_setup(); 2392 TEST_ASSERT_EQ(2, fixture_test_data); 2393 enter_guest(); 2394 TEST_ASSERT_EQ(3, fixture_test_data); 2395 report_pass(__func__); 2396 } 2397 2398 enum ept_access_op { 2399 OP_READ, 2400 OP_WRITE, 2401 OP_EXEC, 2402 OP_FLUSH_TLB, 2403 OP_EXIT, 2404 }; 2405 2406 static struct ept_access_test_data { 2407 unsigned long gpa; 2408 unsigned long *gva; 2409 unsigned long hpa; 2410 unsigned long *hva; 2411 enum ept_access_op op; 2412 } ept_access_test_data; 2413 2414 extern unsigned char ret42_start; 2415 extern unsigned char ret42_end; 2416 2417 /* Returns 42. */ 2418 asm( 2419 ".align 64\n" 2420 "ret42_start:\n" 2421 "mov $42, %eax\n" 2422 "ret\n" 2423 "ret42_end:\n" 2424 ); 2425 2426 static void 2427 diagnose_ept_violation_qual(u64 expected, u64 actual) 2428 { 2429 2430 #define DIAGNOSE(flag) \ 2431 do { \ 2432 if ((expected & flag) != (actual & flag)) \ 2433 printf(#flag " %sexpected\n", \ 2434 (expected & flag) ? "" : "un"); \ 2435 } while (0) 2436 2437 DIAGNOSE(EPT_VLT_RD); 2438 DIAGNOSE(EPT_VLT_WR); 2439 DIAGNOSE(EPT_VLT_FETCH); 2440 DIAGNOSE(EPT_VLT_PERM_RD); 2441 DIAGNOSE(EPT_VLT_PERM_WR); 2442 DIAGNOSE(EPT_VLT_PERM_EX); 2443 DIAGNOSE(EPT_VLT_LADDR_VLD); 2444 DIAGNOSE(EPT_VLT_PADDR); 2445 2446 #undef DIAGNOSE 2447 } 2448 2449 static void do_ept_access_op(enum ept_access_op op) 2450 { 2451 ept_access_test_data.op = op; 2452 enter_guest(); 2453 } 2454 2455 /* 2456 * Force the guest to flush its TLB (i.e., flush gva -> gpa mappings). Only 2457 * needed by tests that modify guest PTEs. 2458 */ 2459 static void ept_access_test_guest_flush_tlb(void) 2460 { 2461 do_ept_access_op(OP_FLUSH_TLB); 2462 skip_exit_vmcall(); 2463 } 2464 2465 /* 2466 * Modifies the EPT entry at @level in the mapping of @gpa. First clears the 2467 * bits in @clear then sets the bits in @set. @mkhuge transforms the entry into 2468 * a huge page. 2469 */ 2470 static unsigned long ept_twiddle(unsigned long gpa, bool mkhuge, int level, 2471 unsigned long clear, unsigned long set) 2472 { 2473 struct ept_access_test_data *data = &ept_access_test_data; 2474 unsigned long orig_pte; 2475 unsigned long pte; 2476 2477 /* Screw with the mapping at the requested level. */ 2478 TEST_ASSERT(get_ept_pte(pml4, gpa, level, &orig_pte)); 2479 pte = orig_pte; 2480 if (mkhuge) 2481 pte = (orig_pte & ~EPT_ADDR_MASK) | data->hpa | EPT_LARGE_PAGE; 2482 else 2483 pte = orig_pte; 2484 pte = (pte & ~clear) | set; 2485 set_ept_pte(pml4, gpa, level, pte); 2486 ept_sync(INVEPT_SINGLE, eptp); 2487 2488 return orig_pte; 2489 } 2490 2491 static void ept_untwiddle(unsigned long gpa, int level, unsigned long orig_pte) 2492 { 2493 set_ept_pte(pml4, gpa, level, orig_pte); 2494 ept_sync(INVEPT_SINGLE, eptp); 2495 } 2496 2497 static void do_ept_violation(bool leaf, enum ept_access_op op, 2498 u64 expected_qual, u64 expected_paddr) 2499 { 2500 u64 qual; 2501 2502 /* Try the access and observe the violation. */ 2503 do_ept_access_op(op); 2504 2505 assert_exit_reason(VMX_EPT_VIOLATION); 2506 2507 qual = vmcs_read(EXI_QUALIFICATION); 2508 2509 /* Mask undefined bits (which may later be defined in certain cases). */ 2510 qual &= ~(EPT_VLT_GUEST_USER | EPT_VLT_GUEST_RW | EPT_VLT_GUEST_EX | 2511 EPT_VLT_PERM_USER_EX); 2512 2513 diagnose_ept_violation_qual(expected_qual, qual); 2514 TEST_EXPECT_EQ(expected_qual, qual); 2515 2516 #if 0 2517 /* Disable for now otherwise every test will fail */ 2518 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2519 (unsigned long) ( 2520 op == OP_EXEC ? data->gva + 1 : data->gva)); 2521 #endif 2522 /* 2523 * TODO: tests that probe expected_paddr in pages other than the one at 2524 * the beginning of the 1g region. 2525 */ 2526 TEST_EXPECT_EQ(vmcs_read(INFO_PHYS_ADDR), expected_paddr); 2527 } 2528 2529 static void 2530 ept_violation_at_level_mkhuge(bool mkhuge, int level, unsigned long clear, 2531 unsigned long set, enum ept_access_op op, 2532 u64 expected_qual) 2533 { 2534 struct ept_access_test_data *data = &ept_access_test_data; 2535 unsigned long orig_pte; 2536 2537 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2538 2539 do_ept_violation(level == 1 || mkhuge, op, expected_qual, 2540 op == OP_EXEC ? data->gpa + sizeof(unsigned long) : 2541 data->gpa); 2542 2543 /* Fix the violation and resume the op loop. */ 2544 ept_untwiddle(data->gpa, level, orig_pte); 2545 enter_guest(); 2546 skip_exit_vmcall(); 2547 } 2548 2549 static void 2550 ept_violation_at_level(int level, unsigned long clear, unsigned long set, 2551 enum ept_access_op op, u64 expected_qual) 2552 { 2553 ept_violation_at_level_mkhuge(false, level, clear, set, op, 2554 expected_qual); 2555 if (ept_huge_pages_supported(level)) 2556 ept_violation_at_level_mkhuge(true, level, clear, set, op, 2557 expected_qual); 2558 } 2559 2560 static void ept_violation(unsigned long clear, unsigned long set, 2561 enum ept_access_op op, u64 expected_qual) 2562 { 2563 ept_violation_at_level(1, clear, set, op, expected_qual); 2564 ept_violation_at_level(2, clear, set, op, expected_qual); 2565 ept_violation_at_level(3, clear, set, op, expected_qual); 2566 ept_violation_at_level(4, clear, set, op, expected_qual); 2567 } 2568 2569 static void ept_access_violation(unsigned long access, enum ept_access_op op, 2570 u64 expected_qual) 2571 { 2572 ept_violation(EPT_PRESENT, access, op, 2573 expected_qual | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2574 } 2575 2576 /* 2577 * For translations that don't involve a GVA, that is physical address (paddr) 2578 * accesses, EPT violations don't set the flag EPT_VLT_PADDR. For a typical 2579 * guest memory access, the hardware does GVA -> GPA -> HPA. However, certain 2580 * translations don't involve GVAs, such as when the hardware does the guest 2581 * page table walk. For example, in translating GVA_1 -> GPA_1, the guest MMU 2582 * might try to set an A bit on a guest PTE. If the GPA_2 that the PTE resides 2583 * on isn't present in the EPT, then the EPT violation will be for GPA_2 and 2584 * the EPT_VLT_PADDR bit will be clear in the exit qualification. 2585 * 2586 * Note that paddr violations can also be triggered by loading PAE page tables 2587 * with wonky addresses. We don't test that yet. 2588 * 2589 * This function modifies the EPT entry that maps the GPA that the guest page 2590 * table entry mapping ept_access_test_data.gva resides on. 2591 * 2592 * @ept_access EPT permissions to set. Other permissions are cleared. 2593 * 2594 * @pte_ad Set the A/D bits on the guest PTE accordingly. 2595 * 2596 * @op Guest operation to perform with 2597 * ept_access_test_data.gva. 2598 * 2599 * @expect_violation 2600 * Is a violation expected during the paddr access? 2601 * 2602 * @expected_qual Expected qualification for the EPT violation. 2603 * EPT_VLT_PADDR should be clear. 2604 */ 2605 static void ept_access_paddr(unsigned long ept_access, unsigned long pte_ad, 2606 enum ept_access_op op, bool expect_violation, 2607 u64 expected_qual) 2608 { 2609 struct ept_access_test_data *data = &ept_access_test_data; 2610 unsigned long *ptep; 2611 unsigned long gpa; 2612 unsigned long orig_epte; 2613 unsigned long epte; 2614 int i; 2615 2616 /* Modify the guest PTE mapping data->gva according to @pte_ad. */ 2617 ptep = get_pte_level(current_page_table(), data->gva, /*level=*/1); 2618 TEST_ASSERT(ptep); 2619 TEST_ASSERT_EQ(*ptep & PT_ADDR_MASK, data->gpa); 2620 *ptep = (*ptep & ~PT_AD_MASK) | pte_ad; 2621 ept_access_test_guest_flush_tlb(); 2622 2623 /* 2624 * Now modify the access bits on the EPT entry for the GPA that the 2625 * guest PTE resides on. Note that by modifying a single EPT entry, 2626 * we're potentially affecting 512 guest PTEs. However, we've carefully 2627 * constructed our test such that those other 511 PTEs aren't used by 2628 * the guest: data->gva is at the beginning of a 1G huge page, thus the 2629 * PTE we're modifying is at the beginning of a 4K page and the 2630 * following 511 entires are also under our control (and not touched by 2631 * the guest). 2632 */ 2633 gpa = virt_to_phys(ptep); 2634 TEST_ASSERT_EQ(gpa & ~PAGE_MASK, 0); 2635 /* 2636 * Make sure the guest page table page is mapped with a 4K EPT entry, 2637 * otherwise our level=1 twiddling below will fail. We use the 2638 * identity map (gpa = gpa) since page tables are shared with the host. 2639 */ 2640 install_ept(pml4, gpa, gpa, EPT_PRESENT); 2641 orig_epte = ept_twiddle(gpa, /*mkhuge=*/0, /*level=*/1, 2642 /*clear=*/EPT_PRESENT, /*set=*/ept_access); 2643 2644 if (expect_violation) { 2645 do_ept_violation(/*leaf=*/true, op, 2646 expected_qual | EPT_VLT_LADDR_VLD, gpa); 2647 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2648 do_ept_access_op(op); 2649 } else { 2650 do_ept_access_op(op); 2651 if (ept_ad_enabled()) { 2652 for (i = EPT_PAGE_LEVEL; i > 0; i--) { 2653 TEST_ASSERT(get_ept_pte(pml4, gpa, i, &epte)); 2654 TEST_ASSERT(epte & EPT_ACCESS_FLAG); 2655 if (i == 1) 2656 TEST_ASSERT(epte & EPT_DIRTY_FLAG); 2657 else 2658 TEST_ASSERT_EQ(epte & EPT_DIRTY_FLAG, 0); 2659 } 2660 } 2661 2662 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2663 } 2664 2665 TEST_ASSERT(*ptep & PT_ACCESSED_MASK); 2666 if ((pte_ad & PT_DIRTY_MASK) || op == OP_WRITE) 2667 TEST_ASSERT(*ptep & PT_DIRTY_MASK); 2668 2669 skip_exit_vmcall(); 2670 } 2671 2672 static void ept_access_allowed_paddr(unsigned long ept_access, 2673 unsigned long pte_ad, 2674 enum ept_access_op op) 2675 { 2676 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/false, 2677 /*expected_qual=*/-1); 2678 } 2679 2680 static void ept_access_violation_paddr(unsigned long ept_access, 2681 unsigned long pte_ad, 2682 enum ept_access_op op, 2683 u64 expected_qual) 2684 { 2685 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/true, 2686 expected_qual); 2687 } 2688 2689 2690 static void ept_allowed_at_level_mkhuge(bool mkhuge, int level, 2691 unsigned long clear, 2692 unsigned long set, 2693 enum ept_access_op op) 2694 { 2695 struct ept_access_test_data *data = &ept_access_test_data; 2696 unsigned long orig_pte; 2697 2698 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2699 2700 /* No violation. Should proceed to vmcall. */ 2701 do_ept_access_op(op); 2702 skip_exit_vmcall(); 2703 2704 ept_untwiddle(data->gpa, level, orig_pte); 2705 } 2706 2707 static void ept_allowed_at_level(int level, unsigned long clear, 2708 unsigned long set, enum ept_access_op op) 2709 { 2710 ept_allowed_at_level_mkhuge(false, level, clear, set, op); 2711 if (ept_huge_pages_supported(level)) 2712 ept_allowed_at_level_mkhuge(true, level, clear, set, op); 2713 } 2714 2715 static void ept_allowed(unsigned long clear, unsigned long set, 2716 enum ept_access_op op) 2717 { 2718 ept_allowed_at_level(1, clear, set, op); 2719 ept_allowed_at_level(2, clear, set, op); 2720 ept_allowed_at_level(3, clear, set, op); 2721 ept_allowed_at_level(4, clear, set, op); 2722 } 2723 2724 static void ept_ignored_bit(int bit) 2725 { 2726 /* Set the bit. */ 2727 ept_allowed(0, 1ul << bit, OP_READ); 2728 ept_allowed(0, 1ul << bit, OP_WRITE); 2729 ept_allowed(0, 1ul << bit, OP_EXEC); 2730 2731 /* Clear the bit. */ 2732 ept_allowed(1ul << bit, 0, OP_READ); 2733 ept_allowed(1ul << bit, 0, OP_WRITE); 2734 ept_allowed(1ul << bit, 0, OP_EXEC); 2735 } 2736 2737 static void ept_access_allowed(unsigned long access, enum ept_access_op op) 2738 { 2739 ept_allowed(EPT_PRESENT, access, op); 2740 } 2741 2742 2743 static void ept_misconfig_at_level_mkhuge_op(bool mkhuge, int level, 2744 unsigned long clear, 2745 unsigned long set, 2746 enum ept_access_op op) 2747 { 2748 struct ept_access_test_data *data = &ept_access_test_data; 2749 unsigned long orig_pte; 2750 2751 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2752 2753 do_ept_access_op(op); 2754 assert_exit_reason(VMX_EPT_MISCONFIG); 2755 2756 /* Intel 27.2.1, "For all other VM exits, this field is cleared." */ 2757 #if 0 2758 /* broken: */ 2759 TEST_EXPECT_EQ_MSG(vmcs_read(EXI_QUALIFICATION), 0); 2760 #endif 2761 #if 0 2762 /* 2763 * broken: 2764 * According to description of exit qual for EPT violation, 2765 * EPT_VLT_LADDR_VLD indicates if GUEST_LINEAR_ADDRESS is valid. 2766 * However, I can't find anything that says GUEST_LINEAR_ADDRESS ought 2767 * to be set for msiconfig. 2768 */ 2769 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2770 (unsigned long) ( 2771 op == OP_EXEC ? data->gva + 1 : data->gva)); 2772 #endif 2773 2774 /* Fix the violation and resume the op loop. */ 2775 ept_untwiddle(data->gpa, level, orig_pte); 2776 enter_guest(); 2777 skip_exit_vmcall(); 2778 } 2779 2780 static void ept_misconfig_at_level_mkhuge(bool mkhuge, int level, 2781 unsigned long clear, 2782 unsigned long set) 2783 { 2784 /* The op shouldn't matter (read, write, exec), so try them all! */ 2785 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_READ); 2786 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_WRITE); 2787 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_EXEC); 2788 } 2789 2790 static void ept_misconfig_at_level(int level, unsigned long clear, 2791 unsigned long set) 2792 { 2793 ept_misconfig_at_level_mkhuge(false, level, clear, set); 2794 if (ept_huge_pages_supported(level)) 2795 ept_misconfig_at_level_mkhuge(true, level, clear, set); 2796 } 2797 2798 static void ept_misconfig(unsigned long clear, unsigned long set) 2799 { 2800 ept_misconfig_at_level(1, clear, set); 2801 ept_misconfig_at_level(2, clear, set); 2802 ept_misconfig_at_level(3, clear, set); 2803 ept_misconfig_at_level(4, clear, set); 2804 } 2805 2806 static void ept_access_misconfig(unsigned long access) 2807 { 2808 ept_misconfig(EPT_PRESENT, access); 2809 } 2810 2811 static void ept_reserved_bit_at_level_nohuge(int level, int bit) 2812 { 2813 /* Setting the bit causes a misconfig. */ 2814 ept_misconfig_at_level_mkhuge(false, level, 0, 1ul << bit); 2815 2816 /* Making the entry non-present turns reserved bits into ignored. */ 2817 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2818 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2819 } 2820 2821 static void ept_reserved_bit_at_level_huge(int level, int bit) 2822 { 2823 /* Setting the bit causes a misconfig. */ 2824 ept_misconfig_at_level_mkhuge(true, level, 0, 1ul << bit); 2825 2826 /* Making the entry non-present turns reserved bits into ignored. */ 2827 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2828 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2829 } 2830 2831 static void ept_reserved_bit_at_level(int level, int bit) 2832 { 2833 /* Setting the bit causes a misconfig. */ 2834 ept_misconfig_at_level(level, 0, 1ul << bit); 2835 2836 /* Making the entry non-present turns reserved bits into ignored. */ 2837 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2838 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2839 } 2840 2841 static void ept_reserved_bit(int bit) 2842 { 2843 ept_reserved_bit_at_level(1, bit); 2844 ept_reserved_bit_at_level(2, bit); 2845 ept_reserved_bit_at_level(3, bit); 2846 ept_reserved_bit_at_level(4, bit); 2847 } 2848 2849 #define PAGE_2M_ORDER 9 2850 #define PAGE_1G_ORDER 18 2851 2852 static void *get_1g_page(void) 2853 { 2854 static void *alloc; 2855 2856 if (!alloc) 2857 alloc = alloc_pages(PAGE_1G_ORDER); 2858 return alloc; 2859 } 2860 2861 static void ept_access_test_teardown(void *unused) 2862 { 2863 /* Exit the guest cleanly. */ 2864 do_ept_access_op(OP_EXIT); 2865 } 2866 2867 static void ept_access_test_guest(void) 2868 { 2869 struct ept_access_test_data *data = &ept_access_test_data; 2870 int (*code)(void) = (int (*)(void)) &data->gva[1]; 2871 2872 while (true) { 2873 switch (data->op) { 2874 case OP_READ: 2875 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_1); 2876 break; 2877 case OP_WRITE: 2878 *data->gva = MAGIC_VAL_2; 2879 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_2); 2880 *data->gva = MAGIC_VAL_1; 2881 break; 2882 case OP_EXEC: 2883 TEST_ASSERT_EQ(42, code()); 2884 break; 2885 case OP_FLUSH_TLB: 2886 write_cr3(read_cr3()); 2887 break; 2888 case OP_EXIT: 2889 return; 2890 default: 2891 TEST_ASSERT_MSG(false, "Unknown op %d", data->op); 2892 } 2893 vmcall(); 2894 } 2895 } 2896 2897 static void ept_access_test_setup(void) 2898 { 2899 struct ept_access_test_data *data = &ept_access_test_data; 2900 unsigned long npages = 1ul << PAGE_1G_ORDER; 2901 unsigned long size = npages * PAGE_SIZE; 2902 unsigned long *page_table = current_page_table(); 2903 unsigned long pte; 2904 2905 if (setup_ept(false)) 2906 test_skip("EPT not supported"); 2907 2908 /* We use data->gpa = 1 << 39 so that test data has a separate pml4 entry */ 2909 if (cpuid_maxphyaddr() < 40) 2910 test_skip("Test needs MAXPHYADDR >= 40"); 2911 2912 test_set_guest(ept_access_test_guest); 2913 test_add_teardown(ept_access_test_teardown, NULL); 2914 2915 data->hva = get_1g_page(); 2916 TEST_ASSERT(data->hva); 2917 data->hpa = virt_to_phys(data->hva); 2918 2919 data->gpa = 1ul << 39; 2920 data->gva = (void *) ALIGN((unsigned long) alloc_vpages(npages * 2), 2921 size); 2922 TEST_ASSERT(!any_present_pages(page_table, data->gva, size)); 2923 install_pages(page_table, data->gpa, size, data->gva); 2924 2925 /* 2926 * Make sure nothing's mapped here so the tests that screw with the 2927 * pml4 entry don't inadvertently break something. 2928 */ 2929 TEST_ASSERT(get_ept_pte(pml4, data->gpa, 4, &pte) && pte == 0); 2930 TEST_ASSERT(get_ept_pte(pml4, data->gpa + size - 1, 4, &pte) && pte == 0); 2931 install_ept(pml4, data->hpa, data->gpa, EPT_PRESENT); 2932 2933 data->hva[0] = MAGIC_VAL_1; 2934 memcpy(&data->hva[1], &ret42_start, &ret42_end - &ret42_start); 2935 } 2936 2937 static void ept_access_test_not_present(void) 2938 { 2939 ept_access_test_setup(); 2940 /* --- */ 2941 ept_access_violation(0, OP_READ, EPT_VLT_RD); 2942 ept_access_violation(0, OP_WRITE, EPT_VLT_WR); 2943 ept_access_violation(0, OP_EXEC, EPT_VLT_FETCH); 2944 } 2945 2946 static void ept_access_test_read_only(void) 2947 { 2948 ept_access_test_setup(); 2949 2950 /* r-- */ 2951 ept_access_allowed(EPT_RA, OP_READ); 2952 ept_access_violation(EPT_RA, OP_WRITE, EPT_VLT_WR | EPT_VLT_PERM_RD); 2953 ept_access_violation(EPT_RA, OP_EXEC, EPT_VLT_FETCH | EPT_VLT_PERM_RD); 2954 } 2955 2956 static void ept_access_test_write_only(void) 2957 { 2958 ept_access_test_setup(); 2959 /* -w- */ 2960 ept_access_misconfig(EPT_WA); 2961 } 2962 2963 static void ept_access_test_read_write(void) 2964 { 2965 ept_access_test_setup(); 2966 /* rw- */ 2967 ept_access_allowed(EPT_RA | EPT_WA, OP_READ); 2968 ept_access_allowed(EPT_RA | EPT_WA, OP_WRITE); 2969 ept_access_violation(EPT_RA | EPT_WA, OP_EXEC, 2970 EPT_VLT_FETCH | EPT_VLT_PERM_RD | EPT_VLT_PERM_WR); 2971 } 2972 2973 2974 static void ept_access_test_execute_only(void) 2975 { 2976 ept_access_test_setup(); 2977 /* --x */ 2978 if (ept_execute_only_supported()) { 2979 ept_access_violation(EPT_EA, OP_READ, 2980 EPT_VLT_RD | EPT_VLT_PERM_EX); 2981 ept_access_violation(EPT_EA, OP_WRITE, 2982 EPT_VLT_WR | EPT_VLT_PERM_EX); 2983 ept_access_allowed(EPT_EA, OP_EXEC); 2984 } else { 2985 ept_access_misconfig(EPT_EA); 2986 } 2987 } 2988 2989 static void ept_access_test_read_execute(void) 2990 { 2991 ept_access_test_setup(); 2992 /* r-x */ 2993 ept_access_allowed(EPT_RA | EPT_EA, OP_READ); 2994 ept_access_violation(EPT_RA | EPT_EA, OP_WRITE, 2995 EPT_VLT_WR | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX); 2996 ept_access_allowed(EPT_RA | EPT_EA, OP_EXEC); 2997 } 2998 2999 static void ept_access_test_write_execute(void) 3000 { 3001 ept_access_test_setup(); 3002 /* -wx */ 3003 ept_access_misconfig(EPT_WA | EPT_EA); 3004 } 3005 3006 static void ept_access_test_read_write_execute(void) 3007 { 3008 ept_access_test_setup(); 3009 /* rwx */ 3010 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_READ); 3011 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_WRITE); 3012 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_EXEC); 3013 } 3014 3015 static void ept_access_test_reserved_bits(void) 3016 { 3017 int i; 3018 int maxphyaddr; 3019 3020 ept_access_test_setup(); 3021 3022 /* Reserved bits above maxphyaddr. */ 3023 maxphyaddr = cpuid_maxphyaddr(); 3024 for (i = maxphyaddr; i <= 51; i++) { 3025 report_prefix_pushf("reserved_bit=%d", i); 3026 ept_reserved_bit(i); 3027 report_prefix_pop(); 3028 } 3029 3030 /* Level-specific reserved bits. */ 3031 ept_reserved_bit_at_level_nohuge(2, 3); 3032 ept_reserved_bit_at_level_nohuge(2, 4); 3033 ept_reserved_bit_at_level_nohuge(2, 5); 3034 ept_reserved_bit_at_level_nohuge(2, 6); 3035 /* 2M alignment. */ 3036 for (i = 12; i < 20; i++) { 3037 report_prefix_pushf("reserved_bit=%d", i); 3038 ept_reserved_bit_at_level_huge(2, i); 3039 report_prefix_pop(); 3040 } 3041 ept_reserved_bit_at_level_nohuge(3, 3); 3042 ept_reserved_bit_at_level_nohuge(3, 4); 3043 ept_reserved_bit_at_level_nohuge(3, 5); 3044 ept_reserved_bit_at_level_nohuge(3, 6); 3045 /* 1G alignment. */ 3046 for (i = 12; i < 29; i++) { 3047 report_prefix_pushf("reserved_bit=%d", i); 3048 ept_reserved_bit_at_level_huge(3, i); 3049 report_prefix_pop(); 3050 } 3051 ept_reserved_bit_at_level(4, 3); 3052 ept_reserved_bit_at_level(4, 4); 3053 ept_reserved_bit_at_level(4, 5); 3054 ept_reserved_bit_at_level(4, 6); 3055 ept_reserved_bit_at_level(4, 7); 3056 } 3057 3058 static void ept_access_test_ignored_bits(void) 3059 { 3060 ept_access_test_setup(); 3061 /* 3062 * Bits ignored at every level. Bits 8 and 9 (A and D) are ignored as 3063 * far as translation is concerned even if AD bits are enabled in the 3064 * EPTP. Bit 63 is ignored because "EPT-violation #VE" VM-execution 3065 * control is 0. 3066 */ 3067 ept_ignored_bit(8); 3068 ept_ignored_bit(9); 3069 ept_ignored_bit(10); 3070 ept_ignored_bit(11); 3071 ept_ignored_bit(52); 3072 ept_ignored_bit(53); 3073 ept_ignored_bit(54); 3074 ept_ignored_bit(55); 3075 ept_ignored_bit(56); 3076 ept_ignored_bit(57); 3077 ept_ignored_bit(58); 3078 ept_ignored_bit(59); 3079 ept_ignored_bit(60); 3080 ept_ignored_bit(61); 3081 ept_ignored_bit(62); 3082 ept_ignored_bit(63); 3083 } 3084 3085 static void ept_access_test_paddr_not_present_ad_disabled(void) 3086 { 3087 ept_access_test_setup(); 3088 ept_disable_ad_bits(); 3089 3090 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, EPT_VLT_RD); 3091 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, EPT_VLT_RD); 3092 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, EPT_VLT_RD); 3093 } 3094 3095 static void ept_access_test_paddr_not_present_ad_enabled(void) 3096 { 3097 u64 qual = EPT_VLT_RD | EPT_VLT_WR; 3098 3099 ept_access_test_setup(); 3100 ept_enable_ad_bits_or_skip_test(); 3101 3102 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, qual); 3103 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, qual); 3104 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, qual); 3105 } 3106 3107 static void ept_access_test_paddr_read_only_ad_disabled(void) 3108 { 3109 /* 3110 * When EPT AD bits are disabled, all accesses to guest paging 3111 * structures are reported separately as a read and (after 3112 * translation of the GPA to host physical address) a read+write 3113 * if the A/D bits have to be set. 3114 */ 3115 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 3116 3117 ept_access_test_setup(); 3118 ept_disable_ad_bits(); 3119 3120 /* Can't update A bit, so all accesses fail. */ 3121 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 3122 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 3123 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 3124 /* AD bits disabled, so only writes try to update the D bit. */ 3125 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ); 3126 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 3127 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC); 3128 /* Both A and D already set, so read-only is OK. */ 3129 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_READ); 3130 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_WRITE); 3131 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_EXEC); 3132 } 3133 3134 static void ept_access_test_paddr_read_only_ad_enabled(void) 3135 { 3136 /* 3137 * When EPT AD bits are enabled, all accesses to guest paging 3138 * structures are considered writes as far as EPT translation 3139 * is concerned. 3140 */ 3141 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 3142 3143 ept_access_test_setup(); 3144 ept_enable_ad_bits_or_skip_test(); 3145 3146 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 3147 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 3148 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 3149 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ, qual); 3150 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 3151 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC, qual); 3152 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_READ, qual); 3153 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_WRITE, qual); 3154 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_EXEC, qual); 3155 } 3156 3157 static void ept_access_test_paddr_read_write(void) 3158 { 3159 ept_access_test_setup(); 3160 /* Read-write access to paging structure. */ 3161 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_READ); 3162 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_WRITE); 3163 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_EXEC); 3164 } 3165 3166 static void ept_access_test_paddr_read_write_execute(void) 3167 { 3168 ept_access_test_setup(); 3169 /* RWX access to paging structure. */ 3170 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_READ); 3171 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_WRITE); 3172 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_EXEC); 3173 } 3174 3175 static void ept_access_test_paddr_read_execute_ad_disabled(void) 3176 { 3177 /* 3178 * When EPT AD bits are disabled, all accesses to guest paging 3179 * structures are reported separately as a read and (after 3180 * translation of the GPA to host physical address) a read+write 3181 * if the A/D bits have to be set. 3182 */ 3183 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3184 3185 ept_access_test_setup(); 3186 ept_disable_ad_bits(); 3187 3188 /* Can't update A bit, so all accesses fail. */ 3189 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3190 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3191 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3192 /* AD bits disabled, so only writes try to update the D bit. */ 3193 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ); 3194 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3195 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC); 3196 /* Both A and D already set, so read-only is OK. */ 3197 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ); 3198 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE); 3199 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC); 3200 } 3201 3202 static void ept_access_test_paddr_read_execute_ad_enabled(void) 3203 { 3204 /* 3205 * When EPT AD bits are enabled, all accesses to guest paging 3206 * structures are considered writes as far as EPT translation 3207 * is concerned. 3208 */ 3209 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3210 3211 ept_access_test_setup(); 3212 ept_enable_ad_bits_or_skip_test(); 3213 3214 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3215 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3216 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3217 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ, qual); 3218 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3219 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC, qual); 3220 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ, qual); 3221 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE, qual); 3222 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC, qual); 3223 } 3224 3225 static void ept_access_test_paddr_not_present_page_fault(void) 3226 { 3227 ept_access_test_setup(); 3228 /* 3229 * TODO: test no EPT violation as long as guest PF occurs. e.g., GPA is 3230 * page is read-only in EPT but GVA is also mapped read only in PT. 3231 * Thus guest page fault before host takes EPT violation for trying to 3232 * update A bit. 3233 */ 3234 } 3235 3236 static void ept_access_test_force_2m_page(void) 3237 { 3238 ept_access_test_setup(); 3239 3240 TEST_ASSERT_EQ(ept_2m_supported(), true); 3241 ept_allowed_at_level_mkhuge(true, 2, 0, 0, OP_READ); 3242 ept_violation_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_RA, OP_WRITE, 3243 EPT_VLT_WR | EPT_VLT_PERM_RD | 3244 EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 3245 ept_misconfig_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_WA); 3246 } 3247 3248 static bool invvpid_valid(u64 type, u64 vpid, u64 gla) 3249 { 3250 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3251 3252 TEST_ASSERT(msr & VPID_CAP_INVVPID); 3253 3254 if (type < INVVPID_ADDR || type > INVVPID_CONTEXT_LOCAL) 3255 return false; 3256 3257 if (!(msr & (1ull << (type + VPID_CAP_INVVPID_TYPES_SHIFT)))) 3258 return false; 3259 3260 if (vpid >> 16) 3261 return false; 3262 3263 if (type != INVVPID_ALL && !vpid) 3264 return false; 3265 3266 if (type == INVVPID_ADDR && !is_canonical(gla)) 3267 return false; 3268 3269 return true; 3270 } 3271 3272 static void try_invvpid(u64 type, u64 vpid, u64 gla) 3273 { 3274 int rc; 3275 bool valid = invvpid_valid(type, vpid, gla); 3276 u64 expected = valid ? VMXERR_UNSUPPORTED_VMCS_COMPONENT 3277 : VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID; 3278 /* 3279 * Set VMX_INST_ERROR to VMXERR_UNVALID_VMCS_COMPONENT, so 3280 * that we can tell if it is updated by INVVPID. 3281 */ 3282 vmcs_read(~0); 3283 rc = __invvpid(type, vpid, gla); 3284 report(!rc == valid, "INVVPID type %ld VPID %lx GLA %lx %s", type, 3285 vpid, gla, 3286 valid ? "passes" : "fails"); 3287 report(vmcs_read(VMX_INST_ERROR) == expected, 3288 "After %s INVVPID, VMX_INST_ERR is %ld (actual %ld)", 3289 rc ? "failed" : "successful", 3290 expected, vmcs_read(VMX_INST_ERROR)); 3291 } 3292 3293 static void ds_invvpid(void *data) 3294 { 3295 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3296 u64 type = ffs(msr >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 3297 3298 TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 3299 asm volatile("invvpid %0, %1" 3300 : 3301 : "m"(*(struct invvpid_operand *)data), 3302 "r"(type)); 3303 } 3304 3305 /* 3306 * The SS override is ignored in 64-bit mode, so we use an addressing 3307 * mode with %rsp as the base register to generate an implicit SS 3308 * reference. 3309 */ 3310 static void ss_invvpid(void *data) 3311 { 3312 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3313 u64 type = ffs(msr >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 3314 3315 TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 3316 asm volatile("sub %%rsp,%0; invvpid (%%rsp,%0,1), %1" 3317 : "+r"(data) 3318 : "r"(type)); 3319 } 3320 3321 static void invvpid_test_gp(void) 3322 { 3323 bool fault; 3324 3325 fault = test_for_exception(GP_VECTOR, &ds_invvpid, 3326 (void *)NONCANONICAL); 3327 report(fault, "INVVPID with non-canonical DS operand raises #GP"); 3328 } 3329 3330 static void invvpid_test_ss(void) 3331 { 3332 bool fault; 3333 3334 fault = test_for_exception(SS_VECTOR, &ss_invvpid, 3335 (void *)NONCANONICAL); 3336 report(fault, "INVVPID with non-canonical SS operand raises #SS"); 3337 } 3338 3339 static void invvpid_test_pf(void) 3340 { 3341 void *vpage = alloc_vpage(); 3342 bool fault; 3343 3344 fault = test_for_exception(PF_VECTOR, &ds_invvpid, vpage); 3345 report(fault, "INVVPID with unmapped operand raises #PF"); 3346 } 3347 3348 static void try_compat_invvpid(void *unused) 3349 { 3350 struct far_pointer32 fp = { 3351 .offset = (uintptr_t)&&invvpid, 3352 .selector = KERNEL_CS32, 3353 }; 3354 uintptr_t rsp; 3355 3356 asm volatile ("mov %%rsp, %0" : "=r"(rsp)); 3357 3358 TEST_ASSERT_MSG(fp.offset == (uintptr_t)&&invvpid, 3359 "Code address too high."); 3360 TEST_ASSERT_MSG(rsp == (u32)rsp, "Stack address too high."); 3361 3362 asm goto ("lcall *%0" : : "m" (fp) : "rax" : invvpid); 3363 return; 3364 invvpid: 3365 asm volatile (".code32;" 3366 "invvpid (%eax), %eax;" 3367 "lret;" 3368 ".code64"); 3369 __builtin_unreachable(); 3370 } 3371 3372 static void invvpid_test_compatibility_mode(void) 3373 { 3374 bool fault; 3375 3376 fault = test_for_exception(UD_VECTOR, &try_compat_invvpid, NULL); 3377 report(fault, "Compatibility mode INVVPID raises #UD"); 3378 } 3379 3380 static void invvpid_test_not_in_vmx_operation(void) 3381 { 3382 bool fault; 3383 3384 TEST_ASSERT(!vmx_off()); 3385 fault = test_for_exception(UD_VECTOR, &ds_invvpid, NULL); 3386 report(fault, "INVVPID outside of VMX operation raises #UD"); 3387 TEST_ASSERT(!vmx_on()); 3388 } 3389 3390 /* 3391 * This does not test real-address mode, virtual-8086 mode, protected mode, 3392 * or CPL > 0. 3393 */ 3394 static void invvpid_test_v2(void) 3395 { 3396 u64 msr; 3397 int i; 3398 unsigned types = 0; 3399 unsigned type; 3400 3401 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 3402 !(ctrl_cpu_rev[1].clr & CPU_VPID)) 3403 test_skip("VPID not supported"); 3404 3405 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3406 3407 if (!(msr & VPID_CAP_INVVPID)) 3408 test_skip("INVVPID not supported.\n"); 3409 3410 if (msr & VPID_CAP_INVVPID_ADDR) 3411 types |= 1u << INVVPID_ADDR; 3412 if (msr & VPID_CAP_INVVPID_CXTGLB) 3413 types |= 1u << INVVPID_CONTEXT_GLOBAL; 3414 if (msr & VPID_CAP_INVVPID_ALL) 3415 types |= 1u << INVVPID_ALL; 3416 if (msr & VPID_CAP_INVVPID_CXTLOC) 3417 types |= 1u << INVVPID_CONTEXT_LOCAL; 3418 3419 if (!types) 3420 test_skip("No INVVPID types supported.\n"); 3421 3422 for (i = -127; i < 128; i++) 3423 try_invvpid(i, 0xffff, 0); 3424 3425 /* 3426 * VPID must not be more than 16 bits. 3427 */ 3428 for (i = 0; i < 64; i++) 3429 for (type = 0; type < 4; type++) 3430 if (types & (1u << type)) 3431 try_invvpid(type, 1ul << i, 0); 3432 3433 /* 3434 * VPID must not be zero, except for "all contexts." 3435 */ 3436 for (type = 0; type < 4; type++) 3437 if (types & (1u << type)) 3438 try_invvpid(type, 0, 0); 3439 3440 /* 3441 * The gla operand is only validated for single-address INVVPID. 3442 */ 3443 if (types & (1u << INVVPID_ADDR)) 3444 try_invvpid(INVVPID_ADDR, 0xffff, NONCANONICAL); 3445 3446 invvpid_test_gp(); 3447 invvpid_test_ss(); 3448 invvpid_test_pf(); 3449 invvpid_test_compatibility_mode(); 3450 invvpid_test_not_in_vmx_operation(); 3451 } 3452 3453 /* 3454 * Test for early VMLAUNCH failure. Returns true if VMLAUNCH makes it 3455 * at least as far as the guest-state checks. Returns false if the 3456 * VMLAUNCH fails early and execution falls through to the next 3457 * instruction. 3458 */ 3459 static bool vmlaunch_succeeds(void) 3460 { 3461 u32 exit_reason; 3462 3463 /* 3464 * Indirectly set VMX_INST_ERR to 12 ("VMREAD/VMWRITE from/to 3465 * unsupported VMCS component"). The caller can then check 3466 * to see if a failed VM-entry sets VMX_INST_ERR as expected. 3467 */ 3468 vmcs_write(~0u, 0); 3469 3470 vmcs_write(HOST_RIP, (uintptr_t)&&success); 3471 __asm__ __volatile__ goto ("vmwrite %%rsp, %0; vmlaunch" 3472 : 3473 : "r" ((u64)HOST_RSP) 3474 : "cc", "memory" 3475 : success); 3476 return false; 3477 success: 3478 exit_reason = vmcs_read(EXI_REASON); 3479 TEST_ASSERT(exit_reason == (VMX_FAIL_STATE | VMX_ENTRY_FAILURE) || 3480 exit_reason == (VMX_FAIL_MSR | VMX_ENTRY_FAILURE)); 3481 return true; 3482 } 3483 3484 /* 3485 * Try to launch the current VMCS. 3486 */ 3487 static void test_vmx_vmlaunch(u32 xerror) 3488 { 3489 bool success = vmlaunch_succeeds(); 3490 u32 vmx_inst_err; 3491 3492 report(success == !xerror, "vmlaunch %s", 3493 !xerror ? "succeeds" : "fails"); 3494 if (!success && xerror) { 3495 vmx_inst_err = vmcs_read(VMX_INST_ERROR); 3496 report(vmx_inst_err == xerror, 3497 "VMX inst error is %d (actual %d)", xerror, 3498 vmx_inst_err); 3499 } 3500 } 3501 3502 /* 3503 * Try to launch the current VMCS, and expect one of two possible 3504 * errors (or success) codes. 3505 */ 3506 static void test_vmx_vmlaunch2(u32 xerror1, u32 xerror2) 3507 { 3508 bool success = vmlaunch_succeeds(); 3509 u32 vmx_inst_err; 3510 3511 if (!xerror1 == !xerror2) 3512 report(success == !xerror1, "vmlaunch %s", 3513 !xerror1 ? "succeeds" : "fails"); 3514 3515 if (!success && (xerror1 || xerror2)) { 3516 vmx_inst_err = vmcs_read(VMX_INST_ERROR); 3517 report(vmx_inst_err == xerror1 || vmx_inst_err == xerror2, 3518 "VMX inst error is %d or %d (actual %d)", xerror1, 3519 xerror2, vmx_inst_err); 3520 } 3521 } 3522 3523 static void test_vmx_invalid_controls(void) 3524 { 3525 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_CONTROL_FIELD); 3526 } 3527 3528 static void test_vmx_valid_controls(void) 3529 { 3530 test_vmx_vmlaunch(0); 3531 } 3532 3533 /* 3534 * Test a particular value of a VM-execution control bit, if the value 3535 * is required or if the value is zero. 3536 */ 3537 static void test_rsvd_ctl_bit_value(const char *name, union vmx_ctrl_msr msr, 3538 enum Encoding encoding, unsigned bit, 3539 unsigned val) 3540 { 3541 u32 mask = 1u << bit; 3542 bool expected; 3543 u32 controls; 3544 3545 if (msr.set & mask) 3546 TEST_ASSERT(msr.clr & mask); 3547 3548 /* 3549 * We can't arbitrarily turn on a control bit, because it may 3550 * introduce dependencies on other VMCS fields. So, we only 3551 * test turning on bits that have a required setting. 3552 */ 3553 if (val && (msr.clr & mask) && !(msr.set & mask)) 3554 return; 3555 3556 report_prefix_pushf("%s %s bit %d", 3557 val ? "Set" : "Clear", name, bit); 3558 3559 controls = vmcs_read(encoding); 3560 if (val) { 3561 vmcs_write(encoding, msr.set | mask); 3562 expected = (msr.clr & mask); 3563 } else { 3564 vmcs_write(encoding, msr.set & ~mask); 3565 expected = !(msr.set & mask); 3566 } 3567 if (expected) 3568 test_vmx_valid_controls(); 3569 else 3570 test_vmx_invalid_controls(); 3571 vmcs_write(encoding, controls); 3572 report_prefix_pop(); 3573 } 3574 3575 /* 3576 * Test reserved values of a VM-execution control bit, based on the 3577 * allowed bit settings from the corresponding VMX capability MSR. 3578 */ 3579 static void test_rsvd_ctl_bit(const char *name, union vmx_ctrl_msr msr, 3580 enum Encoding encoding, unsigned bit) 3581 { 3582 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 0); 3583 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 1); 3584 } 3585 3586 /* 3587 * Reserved bits in the pin-based VM-execution controls must be set 3588 * properly. Software may consult the VMX capability MSRs to determine 3589 * the proper settings. 3590 * [Intel SDM] 3591 */ 3592 static void test_pin_based_ctls(void) 3593 { 3594 unsigned bit; 3595 3596 printf("%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PIN" : 3597 "MSR_IA32_VMX_PINBASED_CTLS", ctrl_pin_rev.val); 3598 for (bit = 0; bit < 32; bit++) 3599 test_rsvd_ctl_bit("pin-based controls", 3600 ctrl_pin_rev, PIN_CONTROLS, bit); 3601 } 3602 3603 /* 3604 * Reserved bits in the primary processor-based VM-execution controls 3605 * must be set properly. Software may consult the VMX capability MSRs 3606 * to determine the proper settings. 3607 * [Intel SDM] 3608 */ 3609 static void test_primary_processor_based_ctls(void) 3610 { 3611 unsigned bit; 3612 3613 printf("\n%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PROC" : 3614 "MSR_IA32_VMX_PROCBASED_CTLS", ctrl_cpu_rev[0].val); 3615 for (bit = 0; bit < 32; bit++) 3616 test_rsvd_ctl_bit("primary processor-based controls", 3617 ctrl_cpu_rev[0], CPU_EXEC_CTRL0, bit); 3618 } 3619 3620 /* 3621 * If the "activate secondary controls" primary processor-based 3622 * VM-execution control is 1, reserved bits in the secondary 3623 * processor-based VM-execution controls must be cleared. Software may 3624 * consult the VMX capability MSRs to determine which bits are 3625 * reserved. 3626 * If the "activate secondary controls" primary processor-based 3627 * VM-execution control is 0 (or if the processor does not support the 3628 * 1-setting of that control), no checks are performed on the 3629 * secondary processor-based VM-execution controls. 3630 * [Intel SDM] 3631 */ 3632 static void test_secondary_processor_based_ctls(void) 3633 { 3634 u32 primary; 3635 u32 secondary; 3636 unsigned bit; 3637 3638 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) 3639 return; 3640 3641 primary = vmcs_read(CPU_EXEC_CTRL0); 3642 secondary = vmcs_read(CPU_EXEC_CTRL1); 3643 3644 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3645 printf("\nMSR_IA32_VMX_PROCBASED_CTLS2: %lx\n", ctrl_cpu_rev[1].val); 3646 for (bit = 0; bit < 32; bit++) 3647 test_rsvd_ctl_bit("secondary processor-based controls", 3648 ctrl_cpu_rev[1], CPU_EXEC_CTRL1, bit); 3649 3650 /* 3651 * When the "activate secondary controls" VM-execution control 3652 * is clear, there are no checks on the secondary controls. 3653 */ 3654 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3655 vmcs_write(CPU_EXEC_CTRL1, ~0); 3656 report(vmlaunch_succeeds(), 3657 "Secondary processor-based controls ignored"); 3658 vmcs_write(CPU_EXEC_CTRL1, secondary); 3659 vmcs_write(CPU_EXEC_CTRL0, primary); 3660 } 3661 3662 static void try_cr3_target_count(unsigned i, unsigned max) 3663 { 3664 report_prefix_pushf("CR3 target count 0x%x", i); 3665 vmcs_write(CR3_TARGET_COUNT, i); 3666 if (i <= max) 3667 test_vmx_valid_controls(); 3668 else 3669 test_vmx_invalid_controls(); 3670 report_prefix_pop(); 3671 } 3672 3673 /* 3674 * The CR3-target count must not be greater than 4. Future processors 3675 * may support a different number of CR3-target values. Software 3676 * should read the VMX capability MSR IA32_VMX_MISC to determine the 3677 * number of values supported. 3678 * [Intel SDM] 3679 */ 3680 static void test_cr3_targets(void) 3681 { 3682 unsigned supported_targets = (rdmsr(MSR_IA32_VMX_MISC) >> 16) & 0x1ff; 3683 u32 cr3_targets = vmcs_read(CR3_TARGET_COUNT); 3684 unsigned i; 3685 3686 printf("\nSupported CR3 targets: %d\n", supported_targets); 3687 TEST_ASSERT(supported_targets <= 256); 3688 3689 try_cr3_target_count(-1u, supported_targets); 3690 try_cr3_target_count(0x80000000, supported_targets); 3691 try_cr3_target_count(0x7fffffff, supported_targets); 3692 for (i = 0; i <= supported_targets + 1; i++) 3693 try_cr3_target_count(i, supported_targets); 3694 vmcs_write(CR3_TARGET_COUNT, cr3_targets); 3695 3696 /* VMWRITE to nonexistent target fields should fail. */ 3697 for (i = supported_targets; i < 256; i++) 3698 TEST_ASSERT(vmcs_write(CR3_TARGET_0 + i*2, 0)); 3699 } 3700 3701 /* 3702 * Test a particular address setting in the VMCS 3703 */ 3704 static void test_vmcs_addr(const char *name, 3705 enum Encoding encoding, 3706 u64 align, 3707 bool ignored, 3708 bool skip_beyond_mapped_ram, 3709 u64 addr) 3710 { 3711 report_prefix_pushf("%s = %lx", name, addr); 3712 vmcs_write(encoding, addr); 3713 if (skip_beyond_mapped_ram && 3714 addr > fwcfg_get_u64(FW_CFG_RAM_SIZE) - align && 3715 addr < (1ul << cpuid_maxphyaddr())) 3716 printf("Skipping physical address beyond mapped RAM\n"); 3717 else if (ignored || (IS_ALIGNED(addr, align) && 3718 addr < (1ul << cpuid_maxphyaddr()))) 3719 test_vmx_valid_controls(); 3720 else 3721 test_vmx_invalid_controls(); 3722 report_prefix_pop(); 3723 } 3724 3725 /* 3726 * Test interesting values for a VMCS address 3727 */ 3728 static void test_vmcs_addr_values(const char *name, 3729 enum Encoding encoding, 3730 u64 align, 3731 bool ignored, 3732 bool skip_beyond_mapped_ram, 3733 u32 bit_start, u32 bit_end) 3734 { 3735 unsigned i; 3736 u64 orig_val = vmcs_read(encoding); 3737 3738 for (i = bit_start; i <= bit_end; i++) 3739 test_vmcs_addr(name, encoding, align, ignored, 3740 skip_beyond_mapped_ram, 1ul << i); 3741 3742 test_vmcs_addr(name, encoding, align, ignored, 3743 skip_beyond_mapped_ram, PAGE_SIZE - 1); 3744 test_vmcs_addr(name, encoding, align, ignored, 3745 skip_beyond_mapped_ram, PAGE_SIZE); 3746 test_vmcs_addr(name, encoding, align, ignored, 3747 skip_beyond_mapped_ram, 3748 (1ul << cpuid_maxphyaddr()) - PAGE_SIZE); 3749 test_vmcs_addr(name, encoding, align, ignored, 3750 skip_beyond_mapped_ram, -1ul); 3751 3752 vmcs_write(encoding, orig_val); 3753 } 3754 3755 /* 3756 * Test a physical address reference in the VMCS, when the corresponding 3757 * feature is enabled and when the corresponding feature is disabled. 3758 */ 3759 static void test_vmcs_addr_reference(u32 control_bit, enum Encoding field, 3760 const char *field_name, 3761 const char *control_name, u64 align, 3762 bool skip_beyond_mapped_ram, 3763 bool control_primary) 3764 { 3765 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 3766 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 3767 u64 page_addr; 3768 3769 if (control_primary) { 3770 if (!(ctrl_cpu_rev[0].clr & control_bit)) 3771 return; 3772 } else { 3773 if (!(ctrl_cpu_rev[1].clr & control_bit)) 3774 return; 3775 } 3776 3777 page_addr = vmcs_read(field); 3778 3779 report_prefix_pushf("%s enabled", control_name); 3780 if (control_primary) { 3781 vmcs_write(CPU_EXEC_CTRL0, primary | control_bit); 3782 } else { 3783 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3784 vmcs_write(CPU_EXEC_CTRL1, secondary | control_bit); 3785 } 3786 3787 test_vmcs_addr_values(field_name, field, align, false, 3788 skip_beyond_mapped_ram, 0, 63); 3789 report_prefix_pop(); 3790 3791 report_prefix_pushf("%s disabled", control_name); 3792 if (control_primary) { 3793 vmcs_write(CPU_EXEC_CTRL0, primary & ~control_bit); 3794 } else { 3795 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3796 vmcs_write(CPU_EXEC_CTRL1, secondary & ~control_bit); 3797 } 3798 3799 test_vmcs_addr_values(field_name, field, align, true, false, 0, 63); 3800 report_prefix_pop(); 3801 3802 vmcs_write(field, page_addr); 3803 vmcs_write(CPU_EXEC_CTRL0, primary); 3804 vmcs_write(CPU_EXEC_CTRL1, secondary); 3805 } 3806 3807 /* 3808 * If the "use I/O bitmaps" VM-execution control is 1, bits 11:0 of 3809 * each I/O-bitmap address must be 0. Neither address should set any 3810 * bits beyond the processor's physical-address width. 3811 * [Intel SDM] 3812 */ 3813 static void test_io_bitmaps(void) 3814 { 3815 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_A, 3816 "I/O bitmap A", "Use I/O bitmaps", 3817 PAGE_SIZE, false, true); 3818 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_B, 3819 "I/O bitmap B", "Use I/O bitmaps", 3820 PAGE_SIZE, false, true); 3821 } 3822 3823 /* 3824 * If the "use MSR bitmaps" VM-execution control is 1, bits 11:0 of 3825 * the MSR-bitmap address must be 0. The address should not set any 3826 * bits beyond the processor's physical-address width. 3827 * [Intel SDM] 3828 */ 3829 static void test_msr_bitmap(void) 3830 { 3831 test_vmcs_addr_reference(CPU_MSR_BITMAP, MSR_BITMAP, 3832 "MSR bitmap", "Use MSR bitmaps", 3833 PAGE_SIZE, false, true); 3834 } 3835 3836 /* 3837 * If the "use TPR shadow" VM-execution control is 1, the virtual-APIC 3838 * address must satisfy the following checks: 3839 * - Bits 11:0 of the address must be 0. 3840 * - The address should not set any bits beyond the processor's 3841 * physical-address width. 3842 * [Intel SDM] 3843 */ 3844 static void test_apic_virt_addr(void) 3845 { 3846 /* 3847 * Ensure the processor will never use the virtual-APIC page, since 3848 * we will point it to invalid RAM. Otherwise KVM is puzzled about 3849 * what we're trying to achieve and fails vmentry. 3850 */ 3851 u32 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 3852 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0 | CPU_CR8_LOAD | CPU_CR8_STORE); 3853 test_vmcs_addr_reference(CPU_TPR_SHADOW, APIC_VIRT_ADDR, 3854 "virtual-APIC address", "Use TPR shadow", 3855 PAGE_SIZE, false, true); 3856 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 3857 } 3858 3859 /* 3860 * If the "virtualize APIC-accesses" VM-execution control is 1, the 3861 * APIC-access address must satisfy the following checks: 3862 * - Bits 11:0 of the address must be 0. 3863 * - The address should not set any bits beyond the processor's 3864 * physical-address width. 3865 * [Intel SDM] 3866 */ 3867 static void test_apic_access_addr(void) 3868 { 3869 void *apic_access_page = alloc_page(); 3870 3871 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_page)); 3872 3873 test_vmcs_addr_reference(CPU_VIRT_APIC_ACCESSES, APIC_ACCS_ADDR, 3874 "APIC-access address", 3875 "virtualize APIC-accesses", PAGE_SIZE, 3876 true, false); 3877 } 3878 3879 static bool set_bit_pattern(u8 mask, u32 *secondary) 3880 { 3881 u8 i; 3882 bool flag = false; 3883 u32 test_bits[3] = { 3884 CPU_VIRT_X2APIC, 3885 CPU_APIC_REG_VIRT, 3886 CPU_VINTD 3887 }; 3888 3889 for (i = 0; i < ARRAY_SIZE(test_bits); i++) { 3890 if ((mask & (1u << i)) && 3891 (ctrl_cpu_rev[1].clr & test_bits[i])) { 3892 *secondary |= test_bits[i]; 3893 flag = true; 3894 } 3895 } 3896 3897 return (flag); 3898 } 3899 3900 /* 3901 * If the "use TPR shadow" VM-execution control is 0, the following 3902 * VM-execution controls must also be 0: 3903 * - virtualize x2APIC mode 3904 * - APIC-register virtualization 3905 * - virtual-interrupt delivery 3906 * [Intel SDM] 3907 * 3908 * 2. If the "virtualize x2APIC mode" VM-execution control is 1, the 3909 * "virtualize APIC accesses" VM-execution control must be 0. 3910 * [Intel SDM] 3911 */ 3912 static void test_apic_virtual_ctls(void) 3913 { 3914 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3915 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3916 u32 primary = saved_primary; 3917 u32 secondary = saved_secondary; 3918 bool ctrl = false; 3919 char str[10] = "disabled"; 3920 u8 i = 0, j; 3921 3922 /* 3923 * First test 3924 */ 3925 if (!((ctrl_cpu_rev[0].clr & (CPU_SECONDARY | CPU_TPR_SHADOW)) == 3926 (CPU_SECONDARY | CPU_TPR_SHADOW))) 3927 return; 3928 3929 primary |= CPU_SECONDARY; 3930 primary &= ~CPU_TPR_SHADOW; 3931 vmcs_write(CPU_EXEC_CTRL0, primary); 3932 3933 while (1) { 3934 for (j = 1; j < 8; j++) { 3935 secondary &= ~(CPU_VIRT_X2APIC | CPU_APIC_REG_VIRT | CPU_VINTD); 3936 if (primary & CPU_TPR_SHADOW) { 3937 ctrl = true; 3938 } else { 3939 if (! set_bit_pattern(j, &secondary)) 3940 ctrl = true; 3941 else 3942 ctrl = false; 3943 } 3944 3945 vmcs_write(CPU_EXEC_CTRL1, secondary); 3946 report_prefix_pushf("Use TPR shadow %s, virtualize x2APIC mode %s, APIC-register virtualization %s, virtual-interrupt delivery %s", 3947 str, (secondary & CPU_VIRT_X2APIC) ? "enabled" : "disabled", (secondary & CPU_APIC_REG_VIRT) ? "enabled" : "disabled", (secondary & CPU_VINTD) ? "enabled" : "disabled"); 3948 if (ctrl) 3949 test_vmx_valid_controls(); 3950 else 3951 test_vmx_invalid_controls(); 3952 report_prefix_pop(); 3953 } 3954 3955 if (i == 1) 3956 break; 3957 i++; 3958 3959 primary |= CPU_TPR_SHADOW; 3960 vmcs_write(CPU_EXEC_CTRL0, primary); 3961 strcpy(str, "enabled"); 3962 } 3963 3964 /* 3965 * Second test 3966 */ 3967 u32 apic_virt_ctls = (CPU_VIRT_X2APIC | CPU_VIRT_APIC_ACCESSES); 3968 3969 primary = saved_primary; 3970 secondary = saved_secondary; 3971 if (!((ctrl_cpu_rev[1].clr & apic_virt_ctls) == apic_virt_ctls)) 3972 return; 3973 3974 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3975 secondary &= ~CPU_VIRT_APIC_ACCESSES; 3976 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_X2APIC); 3977 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access disabled"); 3978 test_vmx_valid_controls(); 3979 report_prefix_pop(); 3980 3981 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_APIC_ACCESSES); 3982 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access enabled"); 3983 test_vmx_valid_controls(); 3984 report_prefix_pop(); 3985 3986 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_X2APIC); 3987 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access enabled"); 3988 test_vmx_invalid_controls(); 3989 report_prefix_pop(); 3990 3991 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_APIC_ACCESSES); 3992 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access disabled"); 3993 test_vmx_valid_controls(); 3994 report_prefix_pop(); 3995 3996 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3997 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3998 } 3999 4000 /* 4001 * If the "virtual-interrupt delivery" VM-execution control is 1, the 4002 * "external-interrupt exiting" VM-execution control must be 1. 4003 * [Intel SDM] 4004 */ 4005 static void test_virtual_intr_ctls(void) 4006 { 4007 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 4008 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 4009 u32 saved_pin = vmcs_read(PIN_CONTROLS); 4010 u32 primary = saved_primary; 4011 u32 secondary = saved_secondary; 4012 u32 pin = saved_pin; 4013 4014 if (!((ctrl_cpu_rev[1].clr & CPU_VINTD) && 4015 (ctrl_pin_rev.clr & PIN_EXTINT))) 4016 return; 4017 4018 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 4019 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VINTD); 4020 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 4021 report_prefix_pushf("Virtualize interrupt-delivery disabled; external-interrupt exiting disabled"); 4022 test_vmx_valid_controls(); 4023 report_prefix_pop(); 4024 4025 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VINTD); 4026 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 4027 test_vmx_invalid_controls(); 4028 report_prefix_pop(); 4029 4030 vmcs_write(PIN_CONTROLS, pin | PIN_EXTINT); 4031 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting enabled"); 4032 test_vmx_valid_controls(); 4033 report_prefix_pop(); 4034 4035 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 4036 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 4037 test_vmx_invalid_controls(); 4038 report_prefix_pop(); 4039 4040 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 4041 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 4042 vmcs_write(PIN_CONTROLS, saved_pin); 4043 } 4044 4045 static void test_pi_desc_addr(u64 addr, bool ctrl) 4046 { 4047 vmcs_write(POSTED_INTR_DESC_ADDR, addr); 4048 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-descriptor-address 0x%lx", addr); 4049 if (ctrl) 4050 test_vmx_valid_controls(); 4051 else 4052 test_vmx_invalid_controls(); 4053 report_prefix_pop(); 4054 } 4055 4056 /* 4057 * If the "process posted interrupts" VM-execution control is 1, the 4058 * following must be true: 4059 * 4060 * - The "virtual-interrupt delivery" VM-execution control is 1. 4061 * - The "acknowledge interrupt on exit" VM-exit control is 1. 4062 * - The posted-interrupt notification vector has a value in the 4063 * - range 0 - 255 (bits 15:8 are all 0). 4064 * - Bits 5:0 of the posted-interrupt descriptor address are all 0. 4065 * - The posted-interrupt descriptor address does not set any bits 4066 * beyond the processor's physical-address width. 4067 * [Intel SDM] 4068 */ 4069 static void test_posted_intr(void) 4070 { 4071 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 4072 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 4073 u32 saved_pin = vmcs_read(PIN_CONTROLS); 4074 u32 exit_ctl_saved = vmcs_read(EXI_CONTROLS); 4075 u32 primary = saved_primary; 4076 u32 secondary = saved_secondary; 4077 u32 pin = saved_pin; 4078 u32 exit_ctl = exit_ctl_saved; 4079 u16 vec; 4080 int i; 4081 4082 if (!((ctrl_pin_rev.clr & PIN_POST_INTR) && 4083 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 4084 (ctrl_exit_rev.clr & EXI_INTA))) 4085 return; 4086 4087 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 4088 4089 /* 4090 * Test virtual-interrupt-delivery and acknowledge-interrupt-on-exit 4091 */ 4092 pin |= PIN_POST_INTR; 4093 vmcs_write(PIN_CONTROLS, pin); 4094 secondary &= ~CPU_VINTD; 4095 vmcs_write(CPU_EXEC_CTRL1, secondary); 4096 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled"); 4097 test_vmx_invalid_controls(); 4098 report_prefix_pop(); 4099 4100 secondary |= CPU_VINTD; 4101 vmcs_write(CPU_EXEC_CTRL1, secondary); 4102 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled"); 4103 test_vmx_invalid_controls(); 4104 report_prefix_pop(); 4105 4106 exit_ctl &= ~EXI_INTA; 4107 vmcs_write(EXI_CONTROLS, exit_ctl); 4108 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit disabled"); 4109 test_vmx_invalid_controls(); 4110 report_prefix_pop(); 4111 4112 exit_ctl |= EXI_INTA; 4113 vmcs_write(EXI_CONTROLS, exit_ctl); 4114 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 4115 test_vmx_valid_controls(); 4116 report_prefix_pop(); 4117 4118 secondary &= ~CPU_VINTD; 4119 vmcs_write(CPU_EXEC_CTRL1, secondary); 4120 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled; acknowledge-interrupt-on-exit enabled"); 4121 test_vmx_invalid_controls(); 4122 report_prefix_pop(); 4123 4124 secondary |= CPU_VINTD; 4125 vmcs_write(CPU_EXEC_CTRL1, secondary); 4126 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 4127 test_vmx_valid_controls(); 4128 report_prefix_pop(); 4129 4130 /* 4131 * Test posted-interrupt notification vector 4132 */ 4133 for (i = 0; i < 8; i++) { 4134 vec = (1ul << i); 4135 vmcs_write(PINV, vec); 4136 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 4137 test_vmx_valid_controls(); 4138 report_prefix_pop(); 4139 } 4140 for (i = 8; i < 16; i++) { 4141 vec = (1ul << i); 4142 vmcs_write(PINV, vec); 4143 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 4144 test_vmx_invalid_controls(); 4145 report_prefix_pop(); 4146 } 4147 4148 vec &= ~(0xff << 8); 4149 vmcs_write(PINV, vec); 4150 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 4151 test_vmx_valid_controls(); 4152 report_prefix_pop(); 4153 4154 /* 4155 * Test posted-interrupt descriptor addresss 4156 */ 4157 for (i = 0; i < 6; i++) { 4158 test_pi_desc_addr(1ul << i, false); 4159 } 4160 4161 test_pi_desc_addr(0xf0, false); 4162 test_pi_desc_addr(0xff, false); 4163 test_pi_desc_addr(0x0f, false); 4164 test_pi_desc_addr(0x8000, true); 4165 test_pi_desc_addr(0x00, true); 4166 test_pi_desc_addr(0xc000, true); 4167 4168 test_vmcs_addr_values("process-posted interrupts", 4169 POSTED_INTR_DESC_ADDR, 64, 4170 false, false, 0, 63); 4171 4172 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 4173 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 4174 vmcs_write(PIN_CONTROLS, saved_pin); 4175 } 4176 4177 static void test_apic_ctls(void) 4178 { 4179 test_apic_virt_addr(); 4180 test_apic_access_addr(); 4181 test_apic_virtual_ctls(); 4182 test_virtual_intr_ctls(); 4183 test_posted_intr(); 4184 } 4185 4186 /* 4187 * If the "enable VPID" VM-execution control is 1, the value of the 4188 * of the VPID VM-execution control field must not be 0000H. 4189 * [Intel SDM] 4190 */ 4191 static void test_vpid(void) 4192 { 4193 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 4194 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 4195 u16 vpid = 0x0000; 4196 int i; 4197 4198 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4199 (ctrl_cpu_rev[1].clr & CPU_VPID))) { 4200 printf("Secondary controls and/or VPID not supported\n"); 4201 return; 4202 } 4203 4204 vmcs_write(CPU_EXEC_CTRL0, saved_primary | CPU_SECONDARY); 4205 vmcs_write(CPU_EXEC_CTRL1, saved_secondary & ~CPU_VPID); 4206 vmcs_write(VPID, vpid); 4207 report_prefix_pushf("VPID disabled; VPID value %x", vpid); 4208 test_vmx_valid_controls(); 4209 report_prefix_pop(); 4210 4211 vmcs_write(CPU_EXEC_CTRL1, saved_secondary | CPU_VPID); 4212 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 4213 test_vmx_invalid_controls(); 4214 report_prefix_pop(); 4215 4216 for (i = 0; i < 16; i++) { 4217 vpid = (short)1 << i;; 4218 vmcs_write(VPID, vpid); 4219 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 4220 test_vmx_valid_controls(); 4221 report_prefix_pop(); 4222 } 4223 4224 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 4225 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 4226 } 4227 4228 static void set_vtpr(unsigned vtpr) 4229 { 4230 *(u32 *)phys_to_virt(vmcs_read(APIC_VIRT_ADDR) + APIC_TASKPRI) = vtpr; 4231 } 4232 4233 static void try_tpr_threshold_and_vtpr(unsigned threshold, unsigned vtpr) 4234 { 4235 bool valid = true; 4236 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4237 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4238 4239 if ((primary & CPU_TPR_SHADOW) && 4240 (!(primary & CPU_SECONDARY) || 4241 !(secondary & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 4242 valid = (threshold & 0xf) <= ((vtpr >> 4) & 0xf); 4243 4244 set_vtpr(vtpr); 4245 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0x%x", 4246 threshold, (vtpr >> 4) & 0xf); 4247 if (valid) 4248 test_vmx_valid_controls(); 4249 else 4250 test_vmx_invalid_controls(); 4251 report_prefix_pop(); 4252 } 4253 4254 static void test_invalid_event_injection(void) 4255 { 4256 u32 ent_intr_info_save = vmcs_read(ENT_INTR_INFO); 4257 u32 ent_intr_error_save = vmcs_read(ENT_INTR_ERROR); 4258 u32 ent_inst_len_save = vmcs_read(ENT_INST_LEN); 4259 u32 primary_save = vmcs_read(CPU_EXEC_CTRL0); 4260 u32 secondary_save = vmcs_read(CPU_EXEC_CTRL1); 4261 u64 guest_cr0_save = vmcs_read(GUEST_CR0); 4262 u32 ent_intr_info_base = INTR_INFO_VALID_MASK; 4263 u32 ent_intr_info, ent_intr_err, ent_intr_len; 4264 u32 cnt; 4265 4266 /* Setup */ 4267 report_prefix_push("invalid event injection"); 4268 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4269 vmcs_write(ENT_INST_LEN, 0x00000001); 4270 4271 /* The field's interruption type is not set to a reserved value. */ 4272 ent_intr_info = ent_intr_info_base | INTR_TYPE_RESERVED | DE_VECTOR; 4273 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4274 "RESERVED interruption type invalid [-]", 4275 ent_intr_info); 4276 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4277 test_vmx_invalid_controls(); 4278 report_prefix_pop(); 4279 4280 ent_intr_info = ent_intr_info_base | INTR_TYPE_EXT_INTR | 4281 DE_VECTOR; 4282 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4283 "RESERVED interruption type invalid [+]", 4284 ent_intr_info); 4285 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4286 test_vmx_valid_controls(); 4287 report_prefix_pop(); 4288 4289 /* If the interruption type is other event, the vector is 0. */ 4290 ent_intr_info = ent_intr_info_base | INTR_TYPE_OTHER_EVENT | DB_VECTOR; 4291 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4292 "(OTHER EVENT && vector != 0) invalid [-]", 4293 ent_intr_info); 4294 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4295 test_vmx_invalid_controls(); 4296 report_prefix_pop(); 4297 4298 /* If the interruption type is NMI, the vector is 2 (negative case). */ 4299 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | DE_VECTOR; 4300 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4301 "(NMI && vector != 2) invalid [-]", ent_intr_info); 4302 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4303 test_vmx_invalid_controls(); 4304 report_prefix_pop(); 4305 4306 /* If the interruption type is NMI, the vector is 2 (positive case). */ 4307 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | NMI_VECTOR; 4308 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4309 "(NMI && vector == 2) valid [+]", ent_intr_info); 4310 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4311 test_vmx_valid_controls(); 4312 report_prefix_pop(); 4313 4314 /* 4315 * If the interruption type 4316 * is HW exception, the vector is at most 31. 4317 */ 4318 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 0x20; 4319 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4320 "(HW exception && vector > 31) invalid [-]", 4321 ent_intr_info); 4322 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4323 test_vmx_invalid_controls(); 4324 report_prefix_pop(); 4325 4326 /* 4327 * deliver-error-code is 1 iff either 4328 * (a) the "unrestricted guest" VM-execution control is 0 4329 * (b) CR0.PE is set. 4330 */ 4331 4332 /* Assert that unrestricted guest is disabled or unsupported */ 4333 assert(!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 4334 !(secondary_save & CPU_URG)); 4335 4336 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4337 GP_VECTOR; 4338 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4339 "error code <-> (!URG || prot_mode) [-]", 4340 ent_intr_info); 4341 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4342 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4343 test_vmx_invalid_controls(); 4344 report_prefix_pop(); 4345 4346 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4347 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4348 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4349 "error code <-> (!URG || prot_mode) [+]", 4350 ent_intr_info); 4351 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4352 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4353 test_vmx_valid_controls(); 4354 report_prefix_pop(); 4355 4356 if (enable_unrestricted_guest(false)) 4357 goto skip_unrestricted_guest; 4358 4359 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4360 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4361 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4362 "error code <-> (!URG || prot_mode) [-]", 4363 ent_intr_info); 4364 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4365 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4366 test_vmx_invalid_controls(); 4367 report_prefix_pop(); 4368 4369 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4370 GP_VECTOR; 4371 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4372 "error code <-> (!URG || prot_mode) [-]", 4373 ent_intr_info); 4374 vmcs_write(GUEST_CR0, guest_cr0_save | X86_CR0_PE); 4375 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4376 test_vmx_invalid_controls(); 4377 report_prefix_pop(); 4378 4379 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4380 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4381 4382 skip_unrestricted_guest: 4383 vmcs_write(GUEST_CR0, guest_cr0_save); 4384 4385 /* deliver-error-code is 1 iff the interruption type is HW exception */ 4386 report_prefix_push("error code <-> HW exception"); 4387 for (cnt = 0; cnt < 8; cnt++) { 4388 u32 exception_type_mask = cnt << 8; 4389 u32 deliver_error_code_mask = 4390 exception_type_mask != INTR_TYPE_HARD_EXCEPTION ? 4391 INTR_INFO_DELIVER_CODE_MASK : 0; 4392 4393 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4394 exception_type_mask | GP_VECTOR; 4395 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4396 ent_intr_info); 4397 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4398 test_vmx_invalid_controls(); 4399 report_prefix_pop(); 4400 } 4401 report_prefix_pop(); 4402 4403 /* 4404 * deliver-error-code is 1 iff the the vector 4405 * indicates an exception that would normally deliver an error code 4406 */ 4407 report_prefix_push("error code <-> vector delivers error code"); 4408 for (cnt = 0; cnt < 32; cnt++) { 4409 bool has_error_code = false; 4410 u32 deliver_error_code_mask; 4411 4412 switch (cnt) { 4413 case DF_VECTOR: 4414 case TS_VECTOR: 4415 case NP_VECTOR: 4416 case SS_VECTOR: 4417 case GP_VECTOR: 4418 case PF_VECTOR: 4419 case AC_VECTOR: 4420 has_error_code = true; 4421 case CP_VECTOR: 4422 /* Some CPUs have error code and some do not, skip */ 4423 continue; 4424 } 4425 4426 /* Negative case */ 4427 deliver_error_code_mask = has_error_code ? 4428 0 : 4429 INTR_INFO_DELIVER_CODE_MASK; 4430 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4431 INTR_TYPE_HARD_EXCEPTION | cnt; 4432 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4433 ent_intr_info); 4434 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4435 test_vmx_invalid_controls(); 4436 report_prefix_pop(); 4437 4438 /* Positive case */ 4439 deliver_error_code_mask = has_error_code ? 4440 INTR_INFO_DELIVER_CODE_MASK : 4441 0; 4442 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4443 INTR_TYPE_HARD_EXCEPTION | cnt; 4444 report_prefix_pushf("VM-entry intr info=0x%x [+]", 4445 ent_intr_info); 4446 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4447 test_vmx_valid_controls(); 4448 report_prefix_pop(); 4449 } 4450 report_prefix_pop(); 4451 4452 /* Reserved bits in the field (30:12) are 0. */ 4453 report_prefix_push("reserved bits clear"); 4454 for (cnt = 12; cnt <= 30; cnt++) { 4455 ent_intr_info = ent_intr_info_base | 4456 INTR_INFO_DELIVER_CODE_MASK | 4457 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR | 4458 (1U << cnt); 4459 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4460 ent_intr_info); 4461 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4462 test_vmx_invalid_controls(); 4463 report_prefix_pop(); 4464 } 4465 report_prefix_pop(); 4466 4467 /* 4468 * If deliver-error-code is 1 4469 * bits 31:16 of the VM-entry exception error-code field are 0. 4470 */ 4471 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4472 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4473 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4474 "VM-entry exception error code[31:16] clear", 4475 ent_intr_info); 4476 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4477 for (cnt = 16; cnt <= 31; cnt++) { 4478 ent_intr_err = 1U << cnt; 4479 report_prefix_pushf("VM-entry intr error=0x%x [-]", 4480 ent_intr_err); 4481 vmcs_write(ENT_INTR_ERROR, ent_intr_err); 4482 test_vmx_invalid_controls(); 4483 report_prefix_pop(); 4484 } 4485 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4486 report_prefix_pop(); 4487 4488 /* 4489 * If the interruption type is software interrupt, software exception, 4490 * or privileged software exception, the VM-entry instruction-length 4491 * field is in the range 0 - 15. 4492 */ 4493 4494 for (cnt = 0; cnt < 3; cnt++) { 4495 switch (cnt) { 4496 case 0: 4497 ent_intr_info = ent_intr_info_base | 4498 INTR_TYPE_SOFT_INTR; 4499 break; 4500 case 1: 4501 ent_intr_info = ent_intr_info_base | 4502 INTR_TYPE_SOFT_EXCEPTION; 4503 break; 4504 case 2: 4505 ent_intr_info = ent_intr_info_base | 4506 INTR_TYPE_PRIV_SW_EXCEPTION; 4507 break; 4508 } 4509 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4510 "VM-entry instruction-length check", 4511 ent_intr_info); 4512 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4513 4514 /* Instruction length set to -1 (0xFFFFFFFF) should fail */ 4515 ent_intr_len = -1; 4516 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4517 ent_intr_len); 4518 vmcs_write(ENT_INST_LEN, ent_intr_len); 4519 test_vmx_invalid_controls(); 4520 report_prefix_pop(); 4521 4522 /* Instruction length set to 16 should fail */ 4523 ent_intr_len = 0x00000010; 4524 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4525 ent_intr_len); 4526 vmcs_write(ENT_INST_LEN, 0x00000010); 4527 test_vmx_invalid_controls(); 4528 report_prefix_pop(); 4529 4530 report_prefix_pop(); 4531 } 4532 4533 /* Cleanup */ 4534 vmcs_write(ENT_INTR_INFO, ent_intr_info_save); 4535 vmcs_write(ENT_INTR_ERROR, ent_intr_error_save); 4536 vmcs_write(ENT_INST_LEN, ent_inst_len_save); 4537 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4538 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4539 vmcs_write(GUEST_CR0, guest_cr0_save); 4540 report_prefix_pop(); 4541 } 4542 4543 /* 4544 * Test interesting vTPR values for a given TPR threshold. 4545 */ 4546 static void test_vtpr_values(unsigned threshold) 4547 { 4548 try_tpr_threshold_and_vtpr(threshold, (threshold - 1) << 4); 4549 try_tpr_threshold_and_vtpr(threshold, threshold << 4); 4550 try_tpr_threshold_and_vtpr(threshold, (threshold + 1) << 4); 4551 } 4552 4553 static void try_tpr_threshold(unsigned threshold) 4554 { 4555 bool valid = true; 4556 4557 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4558 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4559 4560 if ((primary & CPU_TPR_SHADOW) && !((primary & CPU_SECONDARY) && 4561 (secondary & CPU_VINTD))) 4562 valid = !(threshold >> 4); 4563 4564 set_vtpr(-1); 4565 vmcs_write(TPR_THRESHOLD, threshold); 4566 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0xf", threshold); 4567 if (valid) 4568 test_vmx_valid_controls(); 4569 else 4570 test_vmx_invalid_controls(); 4571 report_prefix_pop(); 4572 4573 if (valid) 4574 test_vtpr_values(threshold); 4575 } 4576 4577 /* 4578 * Test interesting TPR threshold values. 4579 */ 4580 static void test_tpr_threshold_values(void) 4581 { 4582 unsigned i; 4583 4584 for (i = 0; i < 0x10; i++) 4585 try_tpr_threshold(i); 4586 for (i = 4; i < 32; i++) 4587 try_tpr_threshold(1u << i); 4588 try_tpr_threshold(-1u); 4589 try_tpr_threshold(0x7fffffff); 4590 } 4591 4592 /* 4593 * This test covers the following two VM entry checks: 4594 * 4595 * i) If the "use TPR shadow" VM-execution control is 1 and the 4596 * "virtual-interrupt delivery" VM-execution control is 0, bits 4597 * 31:4 of the TPR threshold VM-execution control field must 4598 be 0. 4599 * [Intel SDM] 4600 * 4601 * ii) If the "use TPR shadow" VM-execution control is 1, the 4602 * "virtual-interrupt delivery" VM-execution control is 0 4603 * and the "virtualize APIC accesses" VM-execution control 4604 * is 0, the value of bits 3:0 of the TPR threshold VM-execution 4605 * control field must not be greater than the value of bits 4606 * 7:4 of VTPR. 4607 * [Intel SDM] 4608 */ 4609 static void test_tpr_threshold(void) 4610 { 4611 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4612 u64 apic_virt_addr = vmcs_read(APIC_VIRT_ADDR); 4613 u64 threshold = vmcs_read(TPR_THRESHOLD); 4614 void *virtual_apic_page; 4615 4616 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) 4617 return; 4618 4619 virtual_apic_page = alloc_page(); 4620 memset(virtual_apic_page, 0xff, PAGE_SIZE); 4621 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 4622 4623 vmcs_write(CPU_EXEC_CTRL0, primary & ~(CPU_TPR_SHADOW | CPU_SECONDARY)); 4624 report_prefix_pushf("Use TPR shadow disabled, secondary controls disabled"); 4625 test_tpr_threshold_values(); 4626 report_prefix_pop(); 4627 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_TPR_SHADOW); 4628 report_prefix_pushf("Use TPR shadow enabled, secondary controls disabled"); 4629 test_tpr_threshold_values(); 4630 report_prefix_pop(); 4631 4632 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4633 (ctrl_cpu_rev[1].clr & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 4634 goto out; 4635 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4636 4637 if (ctrl_cpu_rev[1].clr & CPU_VINTD) { 4638 vmcs_write(CPU_EXEC_CTRL1, CPU_VINTD); 4639 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4640 test_tpr_threshold_values(); 4641 report_prefix_pop(); 4642 4643 vmcs_write(CPU_EXEC_CTRL0, 4644 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4645 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4646 test_tpr_threshold_values(); 4647 report_prefix_pop(); 4648 } 4649 4650 if (ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES) { 4651 vmcs_write(CPU_EXEC_CTRL0, 4652 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4653 vmcs_write(CPU_EXEC_CTRL1, CPU_VIRT_APIC_ACCESSES); 4654 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4655 test_tpr_threshold_values(); 4656 report_prefix_pop(); 4657 4658 vmcs_write(CPU_EXEC_CTRL0, 4659 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4660 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4661 test_tpr_threshold_values(); 4662 report_prefix_pop(); 4663 } 4664 4665 if ((ctrl_cpu_rev[1].clr & 4666 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) == 4667 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) { 4668 vmcs_write(CPU_EXEC_CTRL0, 4669 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4670 vmcs_write(CPU_EXEC_CTRL1, 4671 CPU_VINTD | CPU_VIRT_APIC_ACCESSES); 4672 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4673 test_tpr_threshold_values(); 4674 report_prefix_pop(); 4675 4676 vmcs_write(CPU_EXEC_CTRL0, 4677 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4678 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4679 test_tpr_threshold_values(); 4680 report_prefix_pop(); 4681 } 4682 4683 vmcs_write(CPU_EXEC_CTRL1, secondary); 4684 out: 4685 vmcs_write(TPR_THRESHOLD, threshold); 4686 vmcs_write(APIC_VIRT_ADDR, apic_virt_addr); 4687 vmcs_write(CPU_EXEC_CTRL0, primary); 4688 } 4689 4690 /* 4691 * This test verifies the following two vmentry checks: 4692 * 4693 * If the "NMI exiting" VM-execution control is 0, "Virtual NMIs" 4694 * VM-execution control must be 0. 4695 * [Intel SDM] 4696 * 4697 * If the "virtual NMIs" VM-execution control is 0, the "NMI-window 4698 * exiting" VM-execution control must be 0. 4699 * [Intel SDM] 4700 */ 4701 static void test_nmi_ctrls(void) 4702 { 4703 u32 pin_ctrls, cpu_ctrls0, test_pin_ctrls, test_cpu_ctrls0; 4704 4705 if ((ctrl_pin_rev.clr & (PIN_NMI | PIN_VIRT_NMI)) != 4706 (PIN_NMI | PIN_VIRT_NMI)) { 4707 printf("NMI exiting and Virtual NMIs are not supported !\n"); 4708 return; 4709 } 4710 4711 /* Save the controls so that we can restore them after our tests */ 4712 pin_ctrls = vmcs_read(PIN_CONTROLS); 4713 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 4714 4715 test_pin_ctrls = pin_ctrls & ~(PIN_NMI | PIN_VIRT_NMI); 4716 test_cpu_ctrls0 = cpu_ctrls0 & ~CPU_NMI_WINDOW; 4717 4718 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4719 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs disabled"); 4720 test_vmx_valid_controls(); 4721 report_prefix_pop(); 4722 4723 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_VIRT_NMI); 4724 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs enabled"); 4725 test_vmx_invalid_controls(); 4726 report_prefix_pop(); 4727 4728 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4729 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs enabled"); 4730 test_vmx_valid_controls(); 4731 report_prefix_pop(); 4732 4733 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_NMI); 4734 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs disabled"); 4735 test_vmx_valid_controls(); 4736 report_prefix_pop(); 4737 4738 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 4739 report_info("NMI-window exiting is not supported, skipping..."); 4740 goto done; 4741 } 4742 4743 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4744 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4745 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting enabled"); 4746 test_vmx_invalid_controls(); 4747 report_prefix_pop(); 4748 4749 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4750 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4751 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting disabled"); 4752 test_vmx_valid_controls(); 4753 report_prefix_pop(); 4754 4755 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4756 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4757 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting enabled"); 4758 test_vmx_valid_controls(); 4759 report_prefix_pop(); 4760 4761 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4762 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4763 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting disabled"); 4764 test_vmx_valid_controls(); 4765 report_prefix_pop(); 4766 4767 /* Restore the controls to their original values */ 4768 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 4769 done: 4770 vmcs_write(PIN_CONTROLS, pin_ctrls); 4771 } 4772 4773 static void test_eptp_ad_bit(u64 eptp, bool ctrl) 4774 { 4775 vmcs_write(EPTP, eptp); 4776 report_prefix_pushf("Enable-EPT enabled; EPT accessed and dirty flag %s", 4777 (eptp & EPTP_AD_FLAG) ? "1": "0"); 4778 if (ctrl) 4779 test_vmx_valid_controls(); 4780 else 4781 test_vmx_invalid_controls(); 4782 report_prefix_pop(); 4783 4784 } 4785 4786 /* 4787 * 1. If the "enable EPT" VM-execution control is 1, the "EPTP VM-execution" 4788 * control field must satisfy the following checks: 4789 * 4790 * - The EPT memory type (bits 2:0) must be a value supported by the 4791 * processor as indicated in the IA32_VMX_EPT_VPID_CAP MSR. 4792 * - Bits 5:3 (1 less than the EPT page-walk length) must indicate a 4793 * supported EPT page-walk length. 4794 * - Bit 6 (enable bit for accessed and dirty flags for EPT) must be 4795 * 0 if bit 21 of the IA32_VMX_EPT_VPID_CAP MSR is read as 0, 4796 * indicating that the processor does not support accessed and dirty 4797 * dirty flags for EPT. 4798 * - Reserved bits 11:7 and 63:N (where N is the processor's 4799 * physical-address width) must all be 0. 4800 * 4801 * 2. If the "unrestricted guest" VM-execution control is 1, the 4802 * "enable EPT" VM-execution control must also be 1. 4803 */ 4804 static void test_ept_eptp(void) 4805 { 4806 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4807 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4808 u64 eptp_saved = vmcs_read(EPTP); 4809 u32 primary = primary_saved; 4810 u32 secondary = secondary_saved; 4811 u64 msr, eptp = eptp_saved; 4812 bool un_cache = false; 4813 bool wr_bk = false; 4814 bool ctrl; 4815 u32 i, maxphysaddr; 4816 u64 j, resv_bits_mask = 0; 4817 4818 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4819 (ctrl_cpu_rev[1].clr & CPU_EPT))) { 4820 printf("\"CPU secondary\" and/or \"enable EPT\" execution controls are not supported !\n"); 4821 return; 4822 } 4823 4824 /* 4825 * Memory type (bits 2:0) 4826 */ 4827 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 4828 if (msr & EPT_CAP_UC) 4829 un_cache = true; 4830 if (msr & EPT_CAP_WB) 4831 wr_bk = true; 4832 4833 /* Support for 4-level EPT is mandatory. */ 4834 report(msr & EPT_CAP_PWL4, "4-level EPT support check"); 4835 4836 primary |= CPU_SECONDARY; 4837 vmcs_write(CPU_EXEC_CTRL0, primary); 4838 secondary |= CPU_EPT; 4839 vmcs_write(CPU_EXEC_CTRL1, secondary); 4840 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4841 (3ul << EPTP_PG_WALK_LEN_SHIFT); 4842 vmcs_write(EPTP, eptp); 4843 4844 for (i = 0; i < 8; i++) { 4845 if (i == 0) { 4846 if (un_cache) { 4847 report_info("EPT paging structure memory-type is Un-cacheable\n"); 4848 ctrl = true; 4849 } else { 4850 ctrl = false; 4851 } 4852 } else if (i == 6) { 4853 if (wr_bk) { 4854 report_info("EPT paging structure memory-type is Write-back\n"); 4855 ctrl = true; 4856 } else { 4857 ctrl = false; 4858 } 4859 } else { 4860 ctrl = false; 4861 } 4862 4863 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | i; 4864 vmcs_write(EPTP, eptp); 4865 report_prefix_pushf("Enable-EPT enabled; EPT memory type %lu", 4866 eptp & EPT_MEM_TYPE_MASK); 4867 if (ctrl) 4868 test_vmx_valid_controls(); 4869 else 4870 test_vmx_invalid_controls(); 4871 report_prefix_pop(); 4872 } 4873 4874 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | 6ul; 4875 4876 /* 4877 * Page walk length (bits 5:3). Note, the value in VMCS.EPTP "is 1 4878 * less than the EPT page-walk length". 4879 */ 4880 for (i = 0; i < 8; i++) { 4881 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4882 (i << EPTP_PG_WALK_LEN_SHIFT); 4883 if (i == 3 || (i == 4 && (msr & EPT_CAP_PWL5))) 4884 ctrl = true; 4885 else 4886 ctrl = false; 4887 4888 vmcs_write(EPTP, eptp); 4889 report_prefix_pushf("Enable-EPT enabled; EPT page walk length %lu", 4890 eptp & EPTP_PG_WALK_LEN_MASK); 4891 if (ctrl) 4892 test_vmx_valid_controls(); 4893 else 4894 test_vmx_invalid_controls(); 4895 report_prefix_pop(); 4896 } 4897 4898 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4899 3ul << EPTP_PG_WALK_LEN_SHIFT; 4900 4901 /* 4902 * Accessed and dirty flag (bit 6) 4903 */ 4904 if (msr & EPT_CAP_AD_FLAG) { 4905 report_info("Processor supports accessed and dirty flag"); 4906 eptp &= ~EPTP_AD_FLAG; 4907 test_eptp_ad_bit(eptp, true); 4908 4909 eptp |= EPTP_AD_FLAG; 4910 test_eptp_ad_bit(eptp, true); 4911 } else { 4912 report_info("Processor does not supports accessed and dirty flag"); 4913 eptp &= ~EPTP_AD_FLAG; 4914 test_eptp_ad_bit(eptp, true); 4915 4916 eptp |= EPTP_AD_FLAG; 4917 test_eptp_ad_bit(eptp, false); 4918 } 4919 4920 /* 4921 * Reserved bits [11:7] and [63:N] 4922 */ 4923 for (i = 0; i < 32; i++) { 4924 eptp = (eptp & 4925 ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)) | 4926 (i << EPTP_RESERV_BITS_SHIFT); 4927 vmcs_write(EPTP, eptp); 4928 report_prefix_pushf("Enable-EPT enabled; reserved bits [11:7] %lu", 4929 (eptp >> EPTP_RESERV_BITS_SHIFT) & 4930 EPTP_RESERV_BITS_MASK); 4931 if (i == 0) 4932 test_vmx_valid_controls(); 4933 else 4934 test_vmx_invalid_controls(); 4935 report_prefix_pop(); 4936 } 4937 4938 eptp = (eptp & ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)); 4939 4940 maxphysaddr = cpuid_maxphyaddr(); 4941 for (i = 0; i < (63 - maxphysaddr + 1); i++) { 4942 resv_bits_mask |= 1ul << i; 4943 } 4944 4945 for (j = maxphysaddr - 1; j <= 63; j++) { 4946 eptp = (eptp & ~(resv_bits_mask << maxphysaddr)) | 4947 (j < maxphysaddr ? 0 : 1ul << j); 4948 vmcs_write(EPTP, eptp); 4949 report_prefix_pushf("Enable-EPT enabled; reserved bits [63:N] %lu", 4950 (eptp >> maxphysaddr) & resv_bits_mask); 4951 if (j < maxphysaddr) 4952 test_vmx_valid_controls(); 4953 else 4954 test_vmx_invalid_controls(); 4955 report_prefix_pop(); 4956 } 4957 4958 secondary &= ~(CPU_EPT | CPU_URG); 4959 vmcs_write(CPU_EXEC_CTRL1, secondary); 4960 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest disabled"); 4961 test_vmx_valid_controls(); 4962 report_prefix_pop(); 4963 4964 if (!(ctrl_cpu_rev[1].clr & CPU_URG)) 4965 goto skip_unrestricted_guest; 4966 4967 secondary |= CPU_URG; 4968 vmcs_write(CPU_EXEC_CTRL1, secondary); 4969 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest enabled"); 4970 test_vmx_invalid_controls(); 4971 report_prefix_pop(); 4972 4973 secondary |= CPU_EPT; 4974 setup_dummy_ept(); 4975 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest enabled"); 4976 test_vmx_valid_controls(); 4977 report_prefix_pop(); 4978 4979 skip_unrestricted_guest: 4980 secondary &= ~CPU_URG; 4981 vmcs_write(CPU_EXEC_CTRL1, secondary); 4982 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest disabled"); 4983 test_vmx_valid_controls(); 4984 report_prefix_pop(); 4985 4986 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4987 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4988 vmcs_write(EPTP, eptp_saved); 4989 } 4990 4991 /* 4992 * If the 'enable PML' VM-execution control is 1, the 'enable EPT' 4993 * VM-execution control must also be 1. In addition, the PML address 4994 * must satisfy the following checks: 4995 * 4996 * * Bits 11:0 of the address must be 0. 4997 * * The address should not set any bits beyond the processor's 4998 * physical-address width. 4999 * 5000 * [Intel SDM] 5001 */ 5002 static void test_pml(void) 5003 { 5004 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 5005 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 5006 u32 primary = primary_saved; 5007 u32 secondary = secondary_saved; 5008 5009 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 5010 (ctrl_cpu_rev[1].clr & CPU_EPT) && (ctrl_cpu_rev[1].clr & CPU_PML))) { 5011 printf("\"Secondary execution\" control or \"enable EPT\" control or \"enable PML\" control is not supported !\n"); 5012 return; 5013 } 5014 5015 primary |= CPU_SECONDARY; 5016 vmcs_write(CPU_EXEC_CTRL0, primary); 5017 secondary &= ~(CPU_PML | CPU_EPT); 5018 vmcs_write(CPU_EXEC_CTRL1, secondary); 5019 report_prefix_pushf("enable-PML disabled, enable-EPT disabled"); 5020 test_vmx_valid_controls(); 5021 report_prefix_pop(); 5022 5023 secondary |= CPU_PML; 5024 vmcs_write(CPU_EXEC_CTRL1, secondary); 5025 report_prefix_pushf("enable-PML enabled, enable-EPT disabled"); 5026 test_vmx_invalid_controls(); 5027 report_prefix_pop(); 5028 5029 secondary |= CPU_EPT; 5030 setup_dummy_ept(); 5031 report_prefix_pushf("enable-PML enabled, enable-EPT enabled"); 5032 test_vmx_valid_controls(); 5033 report_prefix_pop(); 5034 5035 secondary &= ~CPU_PML; 5036 vmcs_write(CPU_EXEC_CTRL1, secondary); 5037 report_prefix_pushf("enable-PML disabled, enable EPT enabled"); 5038 test_vmx_valid_controls(); 5039 report_prefix_pop(); 5040 5041 test_vmcs_addr_reference(CPU_PML, PMLADDR, "PML address", "PML", 5042 PAGE_SIZE, false, false); 5043 5044 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 5045 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 5046 } 5047 5048 /* 5049 * If the "activate VMX-preemption timer" VM-execution control is 0, the 5050 * the "save VMX-preemption timer value" VM-exit control must also be 0. 5051 * 5052 * [Intel SDM] 5053 */ 5054 static void test_vmx_preemption_timer(void) 5055 { 5056 u32 saved_pin = vmcs_read(PIN_CONTROLS); 5057 u32 saved_exit = vmcs_read(EXI_CONTROLS); 5058 u32 pin = saved_pin; 5059 u32 exit = saved_exit; 5060 5061 if (!((ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) || 5062 (ctrl_pin_rev.clr & PIN_PREEMPT))) { 5063 printf("\"Save-VMX-preemption-timer\" control and/or \"Enable-VMX-preemption-timer\" control is not supported\n"); 5064 return; 5065 } 5066 5067 pin |= PIN_PREEMPT; 5068 vmcs_write(PIN_CONTROLS, pin); 5069 exit &= ~EXI_SAVE_PREEMPT; 5070 vmcs_write(EXI_CONTROLS, exit); 5071 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer disabled"); 5072 test_vmx_valid_controls(); 5073 report_prefix_pop(); 5074 5075 exit |= EXI_SAVE_PREEMPT; 5076 vmcs_write(EXI_CONTROLS, exit); 5077 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer enabled"); 5078 test_vmx_valid_controls(); 5079 report_prefix_pop(); 5080 5081 pin &= ~PIN_PREEMPT; 5082 vmcs_write(PIN_CONTROLS, pin); 5083 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer enabled"); 5084 test_vmx_invalid_controls(); 5085 report_prefix_pop(); 5086 5087 exit &= ~EXI_SAVE_PREEMPT; 5088 vmcs_write(EXI_CONTROLS, exit); 5089 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer disabled"); 5090 test_vmx_valid_controls(); 5091 report_prefix_pop(); 5092 5093 vmcs_write(PIN_CONTROLS, saved_pin); 5094 vmcs_write(EXI_CONTROLS, saved_exit); 5095 } 5096 5097 extern unsigned char test_mtf1; 5098 extern unsigned char test_mtf2; 5099 extern unsigned char test_mtf3; 5100 extern unsigned char test_mtf4; 5101 5102 static void test_mtf_guest(void) 5103 { 5104 asm ("vmcall;\n\t" 5105 "out %al, $0x80;\n\t" 5106 "test_mtf1:\n\t" 5107 "vmcall;\n\t" 5108 "out %al, $0x80;\n\t" 5109 "test_mtf2:\n\t" 5110 /* 5111 * Prepare for the 'MOV CR3' test. Attempt to induce a 5112 * general-protection fault by moving a non-canonical address into 5113 * CR3. The 'MOV CR3' instruction does not take an imm64 operand, 5114 * so we must MOV the desired value into a register first. 5115 * 5116 * MOV RAX is done before the VMCALL such that MTF is only enabled 5117 * for the instruction under test. 5118 */ 5119 "mov $0xaaaaaaaaaaaaaaaa, %rax;\n\t" 5120 "vmcall;\n\t" 5121 "mov %rax, %cr3;\n\t" 5122 "test_mtf3:\n\t" 5123 "vmcall;\n\t" 5124 /* 5125 * ICEBP/INT1 instruction. Though the instruction is now 5126 * documented, don't rely on assemblers enumerating the 5127 * instruction. Resort to hand assembly. 5128 */ 5129 ".byte 0xf1;\n\t" 5130 "vmcall;\n\t" 5131 "test_mtf4:\n\t" 5132 "mov $0, %eax;\n\t"); 5133 } 5134 5135 static void test_mtf_gp_handler(struct ex_regs *regs) 5136 { 5137 regs->rip = (unsigned long) &test_mtf3; 5138 } 5139 5140 static void test_mtf_db_handler(struct ex_regs *regs) 5141 { 5142 } 5143 5144 static void enable_mtf(void) 5145 { 5146 u32 ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 5147 5148 vmcs_write(CPU_EXEC_CTRL0, ctrl0 | CPU_MTF); 5149 } 5150 5151 static void disable_mtf(void) 5152 { 5153 u32 ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 5154 5155 vmcs_write(CPU_EXEC_CTRL0, ctrl0 & ~CPU_MTF); 5156 } 5157 5158 static void enable_tf(void) 5159 { 5160 unsigned long rflags = vmcs_read(GUEST_RFLAGS); 5161 5162 vmcs_write(GUEST_RFLAGS, rflags | X86_EFLAGS_TF); 5163 } 5164 5165 static void disable_tf(void) 5166 { 5167 unsigned long rflags = vmcs_read(GUEST_RFLAGS); 5168 5169 vmcs_write(GUEST_RFLAGS, rflags & ~X86_EFLAGS_TF); 5170 } 5171 5172 static void report_mtf(const char *insn_name, unsigned long exp_rip) 5173 { 5174 unsigned long rip = vmcs_read(GUEST_RIP); 5175 5176 assert_exit_reason(VMX_MTF); 5177 report(rip == exp_rip, "MTF VM-exit after %s. RIP: 0x%lx (expected 0x%lx)", 5178 insn_name, rip, exp_rip); 5179 } 5180 5181 static void vmx_mtf_test(void) 5182 { 5183 unsigned long pending_dbg; 5184 handler old_gp, old_db; 5185 5186 if (!(ctrl_cpu_rev[0].clr & CPU_MTF)) { 5187 printf("CPU does not support the 'monitor trap flag' processor-based VM-execution control.\n"); 5188 return; 5189 } 5190 5191 test_set_guest(test_mtf_guest); 5192 5193 /* Expect an MTF VM-exit after OUT instruction */ 5194 enter_guest(); 5195 skip_exit_vmcall(); 5196 5197 enable_mtf(); 5198 enter_guest(); 5199 report_mtf("OUT", (unsigned long) &test_mtf1); 5200 disable_mtf(); 5201 5202 /* 5203 * Concurrent #DB trap and MTF on instruction boundary. Expect MTF 5204 * VM-exit with populated 'pending debug exceptions' VMCS field. 5205 */ 5206 enter_guest(); 5207 skip_exit_vmcall(); 5208 5209 enable_mtf(); 5210 enable_tf(); 5211 5212 enter_guest(); 5213 report_mtf("OUT", (unsigned long) &test_mtf2); 5214 pending_dbg = vmcs_read(GUEST_PENDING_DEBUG); 5215 report(pending_dbg & DR_STEP, 5216 "'pending debug exceptions' field after MTF VM-exit: 0x%lx (expected 0x%lx)", 5217 pending_dbg, (unsigned long) DR_STEP); 5218 5219 disable_mtf(); 5220 disable_tf(); 5221 vmcs_write(GUEST_PENDING_DEBUG, 0); 5222 5223 /* 5224 * #GP exception takes priority over MTF. Expect MTF VM-exit with RIP 5225 * advanced to first instruction of #GP handler. 5226 */ 5227 enter_guest(); 5228 skip_exit_vmcall(); 5229 5230 old_gp = handle_exception(GP_VECTOR, test_mtf_gp_handler); 5231 5232 enable_mtf(); 5233 enter_guest(); 5234 report_mtf("MOV CR3", (unsigned long) get_idt_addr(&boot_idt[GP_VECTOR])); 5235 disable_mtf(); 5236 5237 /* 5238 * Concurrent MTF and privileged software exception (i.e. ICEBP/INT1). 5239 * MTF should follow the delivery of #DB trap, though the SDM doesn't 5240 * provide clear indication of the relative priority. 5241 */ 5242 enter_guest(); 5243 skip_exit_vmcall(); 5244 5245 handle_exception(GP_VECTOR, old_gp); 5246 old_db = handle_exception(DB_VECTOR, test_mtf_db_handler); 5247 5248 enable_mtf(); 5249 enter_guest(); 5250 report_mtf("INT1", (unsigned long) get_idt_addr(&boot_idt[DB_VECTOR])); 5251 disable_mtf(); 5252 5253 enter_guest(); 5254 skip_exit_vmcall(); 5255 handle_exception(DB_VECTOR, old_db); 5256 vmcs_write(ENT_INTR_INFO, INTR_INFO_VALID_MASK | INTR_TYPE_OTHER_EVENT); 5257 enter_guest(); 5258 report_mtf("injected MTF", (unsigned long) &test_mtf4); 5259 enter_guest(); 5260 } 5261 5262 extern char vmx_mtf_pdpte_guest_begin; 5263 extern char vmx_mtf_pdpte_guest_end; 5264 5265 asm("vmx_mtf_pdpte_guest_begin:\n\t" 5266 "mov %cr0, %rax\n\t" /* save CR0 with PG=1 */ 5267 "vmcall\n\t" /* on return from this CR0.PG=0 */ 5268 "mov %rax, %cr0\n\t" /* restore CR0.PG=1 to enter PAE mode */ 5269 "vmcall\n\t" 5270 "retq\n\t" 5271 "vmx_mtf_pdpte_guest_end:"); 5272 5273 static void vmx_mtf_pdpte_test(void) 5274 { 5275 void *test_mtf_pdpte_guest; 5276 pteval_t *pdpt; 5277 u32 guest_ar_cs; 5278 u64 guest_efer; 5279 pteval_t *pte; 5280 u64 guest_cr0; 5281 u64 guest_cr3; 5282 u64 guest_cr4; 5283 u64 ent_ctls; 5284 int i; 5285 5286 if (setup_ept(false)) 5287 return; 5288 5289 if (!(ctrl_cpu_rev[0].clr & CPU_MTF)) { 5290 printf("CPU does not support 'monitor trap flag.'\n"); 5291 return; 5292 } 5293 5294 if (!(ctrl_cpu_rev[1].clr & CPU_URG)) { 5295 printf("CPU does not support 'unrestricted guest.'\n"); 5296 return; 5297 } 5298 5299 vmcs_write(EXC_BITMAP, ~0); 5300 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | CPU_URG); 5301 5302 /* 5303 * Copy the guest code to an identity-mapped page. 5304 */ 5305 test_mtf_pdpte_guest = alloc_page(); 5306 memcpy(test_mtf_pdpte_guest, &vmx_mtf_pdpte_guest_begin, 5307 &vmx_mtf_pdpte_guest_end - &vmx_mtf_pdpte_guest_begin); 5308 5309 test_set_guest(test_mtf_pdpte_guest); 5310 5311 enter_guest(); 5312 skip_exit_vmcall(); 5313 5314 /* 5315 * Put the guest in non-paged 32-bit protected mode, ready to enter 5316 * PAE mode when CR0.PG is set. CR4.PAE will already have been set 5317 * when the guest started out in long mode. 5318 */ 5319 ent_ctls = vmcs_read(ENT_CONTROLS); 5320 vmcs_write(ENT_CONTROLS, ent_ctls & ~ENT_GUEST_64); 5321 5322 guest_efer = vmcs_read(GUEST_EFER); 5323 vmcs_write(GUEST_EFER, guest_efer & ~(EFER_LMA | EFER_LME)); 5324 5325 /* 5326 * Set CS access rights bits for 32-bit protected mode: 5327 * 3:0 B execute/read/accessed 5328 * 4 1 code or data 5329 * 6:5 0 descriptor privilege level 5330 * 7 1 present 5331 * 11:8 0 reserved 5332 * 12 0 available for use by system software 5333 * 13 0 64 bit mode not active 5334 * 14 1 default operation size 32-bit segment 5335 * 15 1 page granularity: segment limit in 4K units 5336 * 16 0 segment usable 5337 * 31:17 0 reserved 5338 */ 5339 guest_ar_cs = vmcs_read(GUEST_AR_CS); 5340 vmcs_write(GUEST_AR_CS, 0xc09b); 5341 5342 guest_cr0 = vmcs_read(GUEST_CR0); 5343 vmcs_write(GUEST_CR0, guest_cr0 & ~X86_CR0_PG); 5344 5345 guest_cr4 = vmcs_read(GUEST_CR4); 5346 vmcs_write(GUEST_CR4, guest_cr4 & ~X86_CR4_PCIDE); 5347 5348 guest_cr3 = vmcs_read(GUEST_CR3); 5349 5350 /* 5351 * Turn the 4-level page table into a PAE page table by following the 0th 5352 * PML4 entry to a PDPT page, and grab the first four PDPTEs from that 5353 * page. 5354 * 5355 * Why does this work? 5356 * 5357 * PAE uses 32-bit addressing which implies: 5358 * Bits 11:0 page offset 5359 * Bits 20:12 entry into 512-entry page table 5360 * Bits 29:21 entry into a 512-entry directory table 5361 * Bits 31:30 entry into the page directory pointer table. 5362 * Bits 63:32 zero 5363 * 5364 * As only 2 bits are needed to select the PDPTEs for the entire 5365 * 32-bit address space, take the first 4 PDPTEs in the level 3 page 5366 * directory pointer table. It doesn't matter which of these PDPTEs 5367 * are present because they must cover the guest code given that it 5368 * has already run successfully. 5369 * 5370 * Get a pointer to PTE for GVA=0 in the page directory pointer table 5371 */ 5372 pte = get_pte_level( 5373 (pgd_t *)phys_to_virt(guest_cr3 & ~X86_CR3_PCID_MASK), 0, 5374 PDPT_LEVEL); 5375 5376 /* 5377 * Need some memory for the 4-entry PAE page directory pointer 5378 * table. Use the end of the identity-mapped page where the guest code 5379 * is stored. There is definitely space as the guest code is only a 5380 * few bytes. 5381 */ 5382 pdpt = test_mtf_pdpte_guest + PAGE_SIZE - 4 * sizeof(pteval_t); 5383 5384 /* 5385 * Copy the first four PDPTEs into the PAE page table with reserved 5386 * bits cleared. Note that permission bits from the PML4E and PDPTE 5387 * are not propagated. 5388 */ 5389 for (i = 0; i < 4; i++) { 5390 TEST_ASSERT_EQ_MSG(0, (pte[i] & PDPTE64_RSVD_MASK), 5391 "PDPTE has invalid reserved bits"); 5392 TEST_ASSERT_EQ_MSG(0, (pte[i] & PDPTE64_PAGE_SIZE_MASK), 5393 "Cannot use 1GB super pages for PAE"); 5394 pdpt[i] = pte[i] & ~(PAE_PDPTE_RSVD_MASK); 5395 } 5396 vmcs_write(GUEST_CR3, virt_to_phys(pdpt)); 5397 5398 enable_mtf(); 5399 enter_guest(); 5400 assert_exit_reason(VMX_MTF); 5401 disable_mtf(); 5402 5403 /* 5404 * The four PDPTEs should have been loaded into the VMCS when 5405 * the guest set CR0.PG to enter PAE mode. 5406 */ 5407 for (i = 0; i < 4; i++) { 5408 u64 pdpte = vmcs_read(GUEST_PDPTE + 2 * i); 5409 5410 report(pdpte == pdpt[i], "PDPTE%d is 0x%lx (expected 0x%lx)", 5411 i, pdpte, pdpt[i]); 5412 } 5413 5414 /* 5415 * Now, try to enter the guest in PAE mode. If the PDPTEs in the 5416 * vmcs are wrong, this will fail. 5417 */ 5418 enter_guest(); 5419 skip_exit_vmcall(); 5420 5421 /* 5422 * Return guest to 64-bit mode and wrap up. 5423 */ 5424 vmcs_write(ENT_CONTROLS, ent_ctls); 5425 vmcs_write(GUEST_EFER, guest_efer); 5426 vmcs_write(GUEST_AR_CS, guest_ar_cs); 5427 vmcs_write(GUEST_CR0, guest_cr0); 5428 vmcs_write(GUEST_CR4, guest_cr4); 5429 vmcs_write(GUEST_CR3, guest_cr3); 5430 5431 enter_guest(); 5432 } 5433 5434 /* 5435 * Tests for VM-execution control fields 5436 */ 5437 static void test_vm_execution_ctls(void) 5438 { 5439 test_pin_based_ctls(); 5440 test_primary_processor_based_ctls(); 5441 test_secondary_processor_based_ctls(); 5442 test_cr3_targets(); 5443 test_io_bitmaps(); 5444 test_msr_bitmap(); 5445 test_apic_ctls(); 5446 test_tpr_threshold(); 5447 test_nmi_ctrls(); 5448 test_pml(); 5449 test_vpid(); 5450 test_ept_eptp(); 5451 test_vmx_preemption_timer(); 5452 } 5453 5454 /* 5455 * The following checks are performed for the VM-entry MSR-load address if 5456 * the VM-entry MSR-load count field is non-zero: 5457 * 5458 * - The lower 4 bits of the VM-entry MSR-load address must be 0. 5459 * The address should not set any bits beyond the processor's 5460 * physical-address width. 5461 * 5462 * - The address of the last byte in the VM-entry MSR-load area 5463 * should not set any bits beyond the processor's physical-address 5464 * width. The address of this last byte is VM-entry MSR-load address 5465 * + (MSR count * 16) - 1. (The arithmetic used for the computation 5466 * uses more bits than the processor's physical-address width.) 5467 * 5468 * 5469 * [Intel SDM] 5470 */ 5471 static void test_entry_msr_load(void) 5472 { 5473 entry_msr_load = alloc_page(); 5474 u64 tmp; 5475 u32 entry_msr_ld_cnt = 1; 5476 int i; 5477 u32 addr_len = 64; 5478 5479 vmcs_write(ENT_MSR_LD_CNT, entry_msr_ld_cnt); 5480 5481 /* Check first 4 bits of VM-entry MSR-load address */ 5482 for (i = 0; i < 4; i++) { 5483 tmp = (u64)entry_msr_load | 1ull << i; 5484 vmcs_write(ENTER_MSR_LD_ADDR, tmp); 5485 report_prefix_pushf("VM-entry MSR-load addr [4:0] %lx", 5486 tmp & 0xf); 5487 test_vmx_invalid_controls(); 5488 report_prefix_pop(); 5489 } 5490 5491 if (basic.val & (1ul << 48)) 5492 addr_len = 32; 5493 5494 test_vmcs_addr_values("VM-entry-MSR-load address", 5495 ENTER_MSR_LD_ADDR, 16, false, false, 5496 4, addr_len - 1); 5497 5498 /* 5499 * Check last byte of VM-entry MSR-load address 5500 */ 5501 entry_msr_load = (struct vmx_msr_entry *)((u64)entry_msr_load & ~0xf); 5502 5503 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 5504 i < 64; i++) { 5505 tmp = ((u64)entry_msr_load + entry_msr_ld_cnt * 16 - 1) | 5506 1ul << i; 5507 vmcs_write(ENTER_MSR_LD_ADDR, 5508 tmp - (entry_msr_ld_cnt * 16 - 1)); 5509 test_vmx_invalid_controls(); 5510 } 5511 5512 vmcs_write(ENT_MSR_LD_CNT, 2); 5513 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 5514 test_vmx_invalid_controls(); 5515 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 5516 test_vmx_valid_controls(); 5517 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 5518 test_vmx_valid_controls(); 5519 } 5520 5521 static struct vmx_state_area_test_data { 5522 u32 msr; 5523 u64 exp; 5524 bool enabled; 5525 } vmx_state_area_test_data; 5526 5527 static void guest_state_test_main(void) 5528 { 5529 u64 obs; 5530 struct vmx_state_area_test_data *data = &vmx_state_area_test_data; 5531 5532 while (1) { 5533 if (vmx_get_test_stage() == 2) 5534 break; 5535 5536 if (data->enabled) { 5537 obs = rdmsr(data->msr); 5538 report(data->exp == obs, 5539 "Guest state is 0x%lx (expected 0x%lx)", 5540 obs, data->exp); 5541 } 5542 5543 vmcall(); 5544 } 5545 5546 asm volatile("fnop"); 5547 } 5548 5549 static void test_guest_state(const char *test, bool xfail, u64 field, 5550 const char * field_name) 5551 { 5552 struct vmentry_result result; 5553 u8 abort_flags; 5554 5555 abort_flags = ABORT_ON_EARLY_VMENTRY_FAIL; 5556 if (!xfail) 5557 abort_flags = ABORT_ON_INVALID_GUEST_STATE; 5558 5559 __enter_guest(abort_flags, &result); 5560 5561 report(result.exit_reason.failed_vmentry == xfail && 5562 ((xfail && result.exit_reason.basic == VMX_FAIL_STATE) || 5563 (!xfail && result.exit_reason.basic == VMX_VMCALL)) && 5564 (!xfail || vmcs_read(EXI_QUALIFICATION) == ENTRY_FAIL_DEFAULT), 5565 "%s, %s = %lx", test, field_name, field); 5566 5567 if (!result.exit_reason.failed_vmentry) 5568 skip_exit_insn(); 5569 } 5570 5571 /* 5572 * Tests for VM-entry control fields 5573 */ 5574 static void test_vm_entry_ctls(void) 5575 { 5576 test_invalid_event_injection(); 5577 test_entry_msr_load(); 5578 } 5579 5580 /* 5581 * The following checks are performed for the VM-exit MSR-store address if 5582 * the VM-exit MSR-store count field is non-zero: 5583 * 5584 * - The lower 4 bits of the VM-exit MSR-store address must be 0. 5585 * The address should not set any bits beyond the processor's 5586 * physical-address width. 5587 * 5588 * - The address of the last byte in the VM-exit MSR-store area 5589 * should not set any bits beyond the processor's physical-address 5590 * width. The address of this last byte is VM-exit MSR-store address 5591 * + (MSR count * 16) - 1. (The arithmetic used for the computation 5592 * uses more bits than the processor's physical-address width.) 5593 * 5594 * If IA32_VMX_BASIC[48] is read as 1, neither address should set any bits 5595 * in the range 63:32. 5596 * 5597 * [Intel SDM] 5598 */ 5599 static void test_exit_msr_store(void) 5600 { 5601 exit_msr_store = alloc_page(); 5602 u64 tmp; 5603 u32 exit_msr_st_cnt = 1; 5604 int i; 5605 u32 addr_len = 64; 5606 5607 vmcs_write(EXI_MSR_ST_CNT, exit_msr_st_cnt); 5608 5609 /* Check first 4 bits of VM-exit MSR-store address */ 5610 for (i = 0; i < 4; i++) { 5611 tmp = (u64)exit_msr_store | 1ull << i; 5612 vmcs_write(EXIT_MSR_ST_ADDR, tmp); 5613 report_prefix_pushf("VM-exit MSR-store addr [4:0] %lx", 5614 tmp & 0xf); 5615 test_vmx_invalid_controls(); 5616 report_prefix_pop(); 5617 } 5618 5619 if (basic.val & (1ul << 48)) 5620 addr_len = 32; 5621 5622 test_vmcs_addr_values("VM-exit-MSR-store address", 5623 EXIT_MSR_ST_ADDR, 16, false, false, 5624 4, addr_len - 1); 5625 5626 /* 5627 * Check last byte of VM-exit MSR-store address 5628 */ 5629 exit_msr_store = (struct vmx_msr_entry *)((u64)exit_msr_store & ~0xf); 5630 5631 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 5632 i < 64; i++) { 5633 tmp = ((u64)exit_msr_store + exit_msr_st_cnt * 16 - 1) | 5634 1ul << i; 5635 vmcs_write(EXIT_MSR_ST_ADDR, 5636 tmp - (exit_msr_st_cnt * 16 - 1)); 5637 test_vmx_invalid_controls(); 5638 } 5639 5640 vmcs_write(EXI_MSR_ST_CNT, 2); 5641 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 5642 test_vmx_invalid_controls(); 5643 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 5644 test_vmx_valid_controls(); 5645 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 5646 test_vmx_valid_controls(); 5647 } 5648 5649 /* 5650 * Tests for VM-exit controls 5651 */ 5652 static void test_vm_exit_ctls(void) 5653 { 5654 test_exit_msr_store(); 5655 } 5656 5657 /* 5658 * Check that the virtual CPU checks all of the VMX controls as 5659 * documented in the Intel SDM. 5660 */ 5661 static void vmx_controls_test(void) 5662 { 5663 /* 5664 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 5665 * fail due to invalid guest state, should we make it that 5666 * far. 5667 */ 5668 vmcs_write(GUEST_RFLAGS, 0); 5669 5670 test_vm_execution_ctls(); 5671 test_vm_exit_ctls(); 5672 test_vm_entry_ctls(); 5673 } 5674 5675 struct apic_reg_virt_config { 5676 bool apic_register_virtualization; 5677 bool use_tpr_shadow; 5678 bool virtualize_apic_accesses; 5679 bool virtualize_x2apic_mode; 5680 bool activate_secondary_controls; 5681 }; 5682 5683 struct apic_reg_test { 5684 const char *name; 5685 struct apic_reg_virt_config apic_reg_virt_config; 5686 }; 5687 5688 struct apic_reg_virt_expectation { 5689 enum Reason rd_exit_reason; 5690 enum Reason wr_exit_reason; 5691 u32 val; 5692 u32 (*virt_fn)(u32); 5693 5694 /* 5695 * If false, accessing the APIC access address from L2 is treated as a 5696 * normal memory operation, rather than triggering virtualization. 5697 */ 5698 bool virtualize_apic_accesses; 5699 }; 5700 5701 static u32 apic_virt_identity(u32 val) 5702 { 5703 return val; 5704 } 5705 5706 static u32 apic_virt_nibble1(u32 val) 5707 { 5708 return val & 0xf0; 5709 } 5710 5711 static u32 apic_virt_byte3(u32 val) 5712 { 5713 return val & (0xff << 24); 5714 } 5715 5716 static bool apic_reg_virt_exit_expectation( 5717 u32 reg, struct apic_reg_virt_config *config, 5718 struct apic_reg_virt_expectation *expectation) 5719 { 5720 /* Good configs, where some L2 APIC accesses are virtualized. */ 5721 bool virtualize_apic_accesses_only = 5722 config->virtualize_apic_accesses && 5723 !config->use_tpr_shadow && 5724 !config->apic_register_virtualization && 5725 !config->virtualize_x2apic_mode && 5726 config->activate_secondary_controls; 5727 bool virtualize_apic_accesses_and_use_tpr_shadow = 5728 config->virtualize_apic_accesses && 5729 config->use_tpr_shadow && 5730 !config->apic_register_virtualization && 5731 !config->virtualize_x2apic_mode && 5732 config->activate_secondary_controls; 5733 bool apic_register_virtualization = 5734 config->virtualize_apic_accesses && 5735 config->use_tpr_shadow && 5736 config->apic_register_virtualization && 5737 !config->virtualize_x2apic_mode && 5738 config->activate_secondary_controls; 5739 5740 expectation->val = MAGIC_VAL_1; 5741 expectation->virt_fn = apic_virt_identity; 5742 expectation->virtualize_apic_accesses = 5743 config->virtualize_apic_accesses && 5744 config->activate_secondary_controls; 5745 if (virtualize_apic_accesses_only) { 5746 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5747 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5748 } else if (virtualize_apic_accesses_and_use_tpr_shadow) { 5749 switch (reg) { 5750 case APIC_TASKPRI: 5751 expectation->rd_exit_reason = VMX_VMCALL; 5752 expectation->wr_exit_reason = VMX_VMCALL; 5753 expectation->virt_fn = apic_virt_nibble1; 5754 break; 5755 default: 5756 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5757 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5758 } 5759 } else if (apic_register_virtualization) { 5760 expectation->rd_exit_reason = VMX_VMCALL; 5761 5762 switch (reg) { 5763 case APIC_ID: 5764 case APIC_EOI: 5765 case APIC_LDR: 5766 case APIC_DFR: 5767 case APIC_SPIV: 5768 case APIC_ESR: 5769 case APIC_ICR: 5770 case APIC_LVTT: 5771 case APIC_LVTTHMR: 5772 case APIC_LVTPC: 5773 case APIC_LVT0: 5774 case APIC_LVT1: 5775 case APIC_LVTERR: 5776 case APIC_TMICT: 5777 case APIC_TDCR: 5778 expectation->wr_exit_reason = VMX_APIC_WRITE; 5779 break; 5780 case APIC_LVR: 5781 case APIC_ISR ... APIC_ISR + 0x70: 5782 case APIC_TMR ... APIC_TMR + 0x70: 5783 case APIC_IRR ... APIC_IRR + 0x70: 5784 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5785 break; 5786 case APIC_TASKPRI: 5787 expectation->wr_exit_reason = VMX_VMCALL; 5788 expectation->virt_fn = apic_virt_nibble1; 5789 break; 5790 case APIC_ICR2: 5791 expectation->wr_exit_reason = VMX_VMCALL; 5792 expectation->virt_fn = apic_virt_byte3; 5793 break; 5794 default: 5795 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5796 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5797 } 5798 } else if (!expectation->virtualize_apic_accesses) { 5799 /* 5800 * No APIC registers are directly virtualized. This includes 5801 * VTPR, which can be virtualized through MOV to/from CR8 via 5802 * the use TPR shadow control, but not through directly 5803 * accessing VTPR. 5804 */ 5805 expectation->rd_exit_reason = VMX_VMCALL; 5806 expectation->wr_exit_reason = VMX_VMCALL; 5807 } else { 5808 printf("Cannot parse APIC register virtualization config:\n" 5809 "\tvirtualize_apic_accesses: %d\n" 5810 "\tuse_tpr_shadow: %d\n" 5811 "\tapic_register_virtualization: %d\n" 5812 "\tvirtualize_x2apic_mode: %d\n" 5813 "\tactivate_secondary_controls: %d\n", 5814 config->virtualize_apic_accesses, 5815 config->use_tpr_shadow, 5816 config->apic_register_virtualization, 5817 config->virtualize_x2apic_mode, 5818 config->activate_secondary_controls); 5819 5820 return false; 5821 } 5822 5823 return true; 5824 } 5825 5826 struct apic_reg_test apic_reg_tests[] = { 5827 /* Good configs, where some L2 APIC accesses are virtualized. */ 5828 { 5829 .name = "Virtualize APIC accesses", 5830 .apic_reg_virt_config = { 5831 .virtualize_apic_accesses = true, 5832 .use_tpr_shadow = false, 5833 .apic_register_virtualization = false, 5834 .virtualize_x2apic_mode = false, 5835 .activate_secondary_controls = true, 5836 }, 5837 }, 5838 { 5839 .name = "Virtualize APIC accesses + Use TPR shadow", 5840 .apic_reg_virt_config = { 5841 .virtualize_apic_accesses = true, 5842 .use_tpr_shadow = true, 5843 .apic_register_virtualization = false, 5844 .virtualize_x2apic_mode = false, 5845 .activate_secondary_controls = true, 5846 }, 5847 }, 5848 { 5849 .name = "APIC-register virtualization", 5850 .apic_reg_virt_config = { 5851 .virtualize_apic_accesses = true, 5852 .use_tpr_shadow = true, 5853 .apic_register_virtualization = true, 5854 .virtualize_x2apic_mode = false, 5855 .activate_secondary_controls = true, 5856 }, 5857 }, 5858 5859 /* 5860 * Test that the secondary processor-based VM-execution controls are 5861 * correctly ignored when "activate secondary controls" is disabled. 5862 */ 5863 { 5864 .name = "Activate secondary controls off", 5865 .apic_reg_virt_config = { 5866 .virtualize_apic_accesses = true, 5867 .use_tpr_shadow = false, 5868 .apic_register_virtualization = true, 5869 .virtualize_x2apic_mode = true, 5870 .activate_secondary_controls = false, 5871 }, 5872 }, 5873 { 5874 .name = "Activate secondary controls off + Use TPR shadow", 5875 .apic_reg_virt_config = { 5876 .virtualize_apic_accesses = true, 5877 .use_tpr_shadow = true, 5878 .apic_register_virtualization = true, 5879 .virtualize_x2apic_mode = true, 5880 .activate_secondary_controls = false, 5881 }, 5882 }, 5883 5884 /* 5885 * Test that the APIC access address is treated like an arbitrary memory 5886 * address when "virtualize APIC accesses" is disabled. 5887 */ 5888 { 5889 .name = "Virtualize APIC accesses off + Use TPR shadow", 5890 .apic_reg_virt_config = { 5891 .virtualize_apic_accesses = false, 5892 .use_tpr_shadow = true, 5893 .apic_register_virtualization = true, 5894 .virtualize_x2apic_mode = true, 5895 .activate_secondary_controls = true, 5896 }, 5897 }, 5898 5899 /* 5900 * Test that VM entry fails due to invalid controls when 5901 * "APIC-register virtualization" is enabled while "use TPR shadow" is 5902 * disabled. 5903 */ 5904 { 5905 .name = "APIC-register virtualization + Use TPR shadow off", 5906 .apic_reg_virt_config = { 5907 .virtualize_apic_accesses = true, 5908 .use_tpr_shadow = false, 5909 .apic_register_virtualization = true, 5910 .virtualize_x2apic_mode = false, 5911 .activate_secondary_controls = true, 5912 }, 5913 }, 5914 5915 /* 5916 * Test that VM entry fails due to invalid controls when 5917 * "Virtualize x2APIC mode" is enabled while "use TPR shadow" is 5918 * disabled. 5919 */ 5920 { 5921 .name = "Virtualize x2APIC mode + Use TPR shadow off", 5922 .apic_reg_virt_config = { 5923 .virtualize_apic_accesses = false, 5924 .use_tpr_shadow = false, 5925 .apic_register_virtualization = false, 5926 .virtualize_x2apic_mode = true, 5927 .activate_secondary_controls = true, 5928 }, 5929 }, 5930 { 5931 .name = "Virtualize x2APIC mode + Use TPR shadow off v2", 5932 .apic_reg_virt_config = { 5933 .virtualize_apic_accesses = false, 5934 .use_tpr_shadow = false, 5935 .apic_register_virtualization = true, 5936 .virtualize_x2apic_mode = true, 5937 .activate_secondary_controls = true, 5938 }, 5939 }, 5940 5941 /* 5942 * Test that VM entry fails due to invalid controls when 5943 * "virtualize x2APIC mode" is enabled while "virtualize APIC accesses" 5944 * is enabled. 5945 */ 5946 { 5947 .name = "Virtualize x2APIC mode + Virtualize APIC accesses", 5948 .apic_reg_virt_config = { 5949 .virtualize_apic_accesses = true, 5950 .use_tpr_shadow = true, 5951 .apic_register_virtualization = false, 5952 .virtualize_x2apic_mode = true, 5953 .activate_secondary_controls = true, 5954 }, 5955 }, 5956 { 5957 .name = "Virtualize x2APIC mode + Virtualize APIC accesses v2", 5958 .apic_reg_virt_config = { 5959 .virtualize_apic_accesses = true, 5960 .use_tpr_shadow = true, 5961 .apic_register_virtualization = true, 5962 .virtualize_x2apic_mode = true, 5963 .activate_secondary_controls = true, 5964 }, 5965 }, 5966 }; 5967 5968 enum Apic_op { 5969 APIC_OP_XAPIC_RD, 5970 APIC_OP_XAPIC_WR, 5971 TERMINATE, 5972 }; 5973 5974 static u32 vmx_xapic_read(u32 *apic_access_address, u32 reg) 5975 { 5976 return *(volatile u32 *)((uintptr_t)apic_access_address + reg); 5977 } 5978 5979 static void vmx_xapic_write(u32 *apic_access_address, u32 reg, u32 val) 5980 { 5981 *(volatile u32 *)((uintptr_t)apic_access_address + reg) = val; 5982 } 5983 5984 struct apic_reg_virt_guest_args { 5985 enum Apic_op op; 5986 u32 *apic_access_address; 5987 u32 reg; 5988 u32 val; 5989 bool check_rd; 5990 u32 (*virt_fn)(u32); 5991 } apic_reg_virt_guest_args; 5992 5993 static void apic_reg_virt_guest(void) 5994 { 5995 volatile struct apic_reg_virt_guest_args *args = 5996 &apic_reg_virt_guest_args; 5997 5998 for (;;) { 5999 enum Apic_op op = args->op; 6000 u32 *apic_access_address = args->apic_access_address; 6001 u32 reg = args->reg; 6002 u32 val = args->val; 6003 bool check_rd = args->check_rd; 6004 u32 (*virt_fn)(u32) = args->virt_fn; 6005 6006 if (op == TERMINATE) 6007 break; 6008 6009 if (op == APIC_OP_XAPIC_RD) { 6010 u32 ret = vmx_xapic_read(apic_access_address, reg); 6011 6012 if (check_rd) { 6013 u32 want = virt_fn(val); 6014 u32 got = virt_fn(ret); 6015 6016 report(got == want, 6017 "read 0x%x, expected 0x%x.", got, want); 6018 } 6019 } else if (op == APIC_OP_XAPIC_WR) { 6020 vmx_xapic_write(apic_access_address, reg, val); 6021 } 6022 6023 /* 6024 * The L1 should always execute a vmcall after it's done testing 6025 * an individual APIC operation. This helps to validate that the 6026 * L1 and L2 are in sync with each other, as expected. 6027 */ 6028 vmcall(); 6029 } 6030 } 6031 6032 static void test_xapic_rd( 6033 u32 reg, struct apic_reg_virt_expectation *expectation, 6034 u32 *apic_access_address, u32 *virtual_apic_page) 6035 { 6036 u32 val = expectation->val; 6037 u32 exit_reason_want = expectation->rd_exit_reason; 6038 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 6039 6040 report_prefix_pushf("xapic - reading 0x%03x", reg); 6041 6042 /* Configure guest to do an xapic read */ 6043 args->op = APIC_OP_XAPIC_RD; 6044 args->apic_access_address = apic_access_address; 6045 args->reg = reg; 6046 args->val = val; 6047 args->check_rd = exit_reason_want == VMX_VMCALL; 6048 args->virt_fn = expectation->virt_fn; 6049 6050 /* Setup virtual APIC page */ 6051 if (!expectation->virtualize_apic_accesses) { 6052 apic_access_address[apic_reg_index(reg)] = val; 6053 virtual_apic_page[apic_reg_index(reg)] = 0; 6054 } else if (exit_reason_want == VMX_VMCALL) { 6055 apic_access_address[apic_reg_index(reg)] = 0; 6056 virtual_apic_page[apic_reg_index(reg)] = val; 6057 } 6058 6059 /* Enter guest */ 6060 enter_guest(); 6061 6062 /* 6063 * Validate the behavior and 6064 * pass a magic value back to the guest. 6065 */ 6066 if (exit_reason_want == VMX_APIC_ACCESS) { 6067 u32 apic_page_offset = vmcs_read(EXI_QUALIFICATION) & 0xfff; 6068 6069 assert_exit_reason(exit_reason_want); 6070 report(apic_page_offset == reg, 6071 "got APIC access exit @ page offset 0x%03x, want 0x%03x", 6072 apic_page_offset, reg); 6073 skip_exit_insn(); 6074 6075 /* Reenter guest so it can consume/check rcx and exit again. */ 6076 enter_guest(); 6077 } else if (exit_reason_want != VMX_VMCALL) { 6078 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 6079 } 6080 6081 skip_exit_vmcall(); 6082 report_prefix_pop(); 6083 } 6084 6085 static void test_xapic_wr( 6086 u32 reg, struct apic_reg_virt_expectation *expectation, 6087 u32 *apic_access_address, u32 *virtual_apic_page) 6088 { 6089 u32 val = expectation->val; 6090 u32 exit_reason_want = expectation->wr_exit_reason; 6091 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 6092 bool virtualized = 6093 expectation->virtualize_apic_accesses && 6094 (exit_reason_want == VMX_APIC_WRITE || 6095 exit_reason_want == VMX_VMCALL); 6096 bool checked = false; 6097 6098 report_prefix_pushf("xapic - writing 0x%x to 0x%03x", val, reg); 6099 6100 /* Configure guest to do an xapic read */ 6101 args->op = APIC_OP_XAPIC_WR; 6102 args->apic_access_address = apic_access_address; 6103 args->reg = reg; 6104 args->val = val; 6105 6106 /* Setup virtual APIC page */ 6107 if (virtualized || !expectation->virtualize_apic_accesses) { 6108 apic_access_address[apic_reg_index(reg)] = 0; 6109 virtual_apic_page[apic_reg_index(reg)] = 0; 6110 } 6111 6112 /* Enter guest */ 6113 enter_guest(); 6114 6115 /* 6116 * Validate the behavior and 6117 * pass a magic value back to the guest. 6118 */ 6119 if (exit_reason_want == VMX_APIC_ACCESS) { 6120 u32 apic_page_offset = vmcs_read(EXI_QUALIFICATION) & 0xfff; 6121 6122 assert_exit_reason(exit_reason_want); 6123 report(apic_page_offset == reg, 6124 "got APIC access exit @ page offset 0x%03x, want 0x%03x", 6125 apic_page_offset, reg); 6126 skip_exit_insn(); 6127 6128 /* Reenter guest so it can consume/check rcx and exit again. */ 6129 enter_guest(); 6130 } else if (exit_reason_want == VMX_APIC_WRITE) { 6131 assert_exit_reason(exit_reason_want); 6132 report(virtual_apic_page[apic_reg_index(reg)] == val, 6133 "got APIC write exit @ page offset 0x%03x; val is 0x%x, want 0x%x", 6134 apic_reg_index(reg), 6135 virtual_apic_page[apic_reg_index(reg)], val); 6136 checked = true; 6137 6138 /* Reenter guest so it can consume/check rcx and exit again. */ 6139 enter_guest(); 6140 } else if (exit_reason_want != VMX_VMCALL) { 6141 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 6142 } 6143 6144 assert_exit_reason(VMX_VMCALL); 6145 if (virtualized && !checked) { 6146 u32 want = expectation->virt_fn(val); 6147 u32 got = virtual_apic_page[apic_reg_index(reg)]; 6148 got = expectation->virt_fn(got); 6149 6150 report(got == want, "exitless write; val is 0x%x, want 0x%x", 6151 got, want); 6152 } else if (!expectation->virtualize_apic_accesses && !checked) { 6153 u32 got = apic_access_address[apic_reg_index(reg)]; 6154 6155 report(got == val, 6156 "non-virtualized write; val is 0x%x, want 0x%x", got, 6157 val); 6158 } else if (!expectation->virtualize_apic_accesses && checked) { 6159 report_fail("Non-virtualized write was prematurely checked!"); 6160 } 6161 6162 skip_exit_vmcall(); 6163 report_prefix_pop(); 6164 } 6165 6166 enum Config_type { 6167 CONFIG_TYPE_GOOD, 6168 CONFIG_TYPE_UNSUPPORTED, 6169 CONFIG_TYPE_VMENTRY_FAILS_EARLY, 6170 }; 6171 6172 static enum Config_type configure_apic_reg_virt_test( 6173 struct apic_reg_virt_config *apic_reg_virt_config) 6174 { 6175 u32 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6176 u32 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6177 /* Configs where L2 entry fails early, due to invalid controls. */ 6178 bool use_tpr_shadow_incorrectly_off = 6179 !apic_reg_virt_config->use_tpr_shadow && 6180 (apic_reg_virt_config->apic_register_virtualization || 6181 apic_reg_virt_config->virtualize_x2apic_mode) && 6182 apic_reg_virt_config->activate_secondary_controls; 6183 bool virtualize_apic_accesses_incorrectly_on = 6184 apic_reg_virt_config->virtualize_apic_accesses && 6185 apic_reg_virt_config->virtualize_x2apic_mode && 6186 apic_reg_virt_config->activate_secondary_controls; 6187 bool vmentry_fails_early = 6188 use_tpr_shadow_incorrectly_off || 6189 virtualize_apic_accesses_incorrectly_on; 6190 6191 if (apic_reg_virt_config->activate_secondary_controls) { 6192 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 6193 printf("VM-execution control \"activate secondary controls\" NOT supported.\n"); 6194 return CONFIG_TYPE_UNSUPPORTED; 6195 } 6196 cpu_exec_ctrl0 |= CPU_SECONDARY; 6197 } else { 6198 cpu_exec_ctrl0 &= ~CPU_SECONDARY; 6199 } 6200 6201 if (apic_reg_virt_config->virtualize_apic_accesses) { 6202 if (!(ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES)) { 6203 printf("VM-execution control \"virtualize APIC accesses\" NOT supported.\n"); 6204 return CONFIG_TYPE_UNSUPPORTED; 6205 } 6206 cpu_exec_ctrl1 |= CPU_VIRT_APIC_ACCESSES; 6207 } else { 6208 cpu_exec_ctrl1 &= ~CPU_VIRT_APIC_ACCESSES; 6209 } 6210 6211 if (apic_reg_virt_config->use_tpr_shadow) { 6212 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) { 6213 printf("VM-execution control \"use TPR shadow\" NOT supported.\n"); 6214 return CONFIG_TYPE_UNSUPPORTED; 6215 } 6216 cpu_exec_ctrl0 |= CPU_TPR_SHADOW; 6217 } else { 6218 cpu_exec_ctrl0 &= ~CPU_TPR_SHADOW; 6219 } 6220 6221 if (apic_reg_virt_config->apic_register_virtualization) { 6222 if (!(ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT)) { 6223 printf("VM-execution control \"APIC-register virtualization\" NOT supported.\n"); 6224 return CONFIG_TYPE_UNSUPPORTED; 6225 } 6226 cpu_exec_ctrl1 |= CPU_APIC_REG_VIRT; 6227 } else { 6228 cpu_exec_ctrl1 &= ~CPU_APIC_REG_VIRT; 6229 } 6230 6231 if (apic_reg_virt_config->virtualize_x2apic_mode) { 6232 if (!(ctrl_cpu_rev[1].clr & CPU_VIRT_X2APIC)) { 6233 printf("VM-execution control \"virtualize x2APIC mode\" NOT supported.\n"); 6234 return CONFIG_TYPE_UNSUPPORTED; 6235 } 6236 cpu_exec_ctrl1 |= CPU_VIRT_X2APIC; 6237 } else { 6238 cpu_exec_ctrl1 &= ~CPU_VIRT_X2APIC; 6239 } 6240 6241 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6242 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6243 6244 if (vmentry_fails_early) 6245 return CONFIG_TYPE_VMENTRY_FAILS_EARLY; 6246 6247 return CONFIG_TYPE_GOOD; 6248 } 6249 6250 static bool cpu_has_apicv(void) 6251 { 6252 return ((ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT) && 6253 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 6254 (ctrl_pin_rev.clr & PIN_POST_INTR)); 6255 } 6256 6257 /* Validates APIC register access across valid virtualization configurations. */ 6258 static void apic_reg_virt_test(void) 6259 { 6260 u32 *apic_access_address; 6261 u32 *virtual_apic_page; 6262 u64 control; 6263 u64 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6264 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6265 int i; 6266 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 6267 6268 if (!cpu_has_apicv()) { 6269 report_skip(__func__); 6270 return; 6271 } 6272 6273 control = cpu_exec_ctrl1; 6274 control &= ~CPU_VINTD; 6275 vmcs_write(CPU_EXEC_CTRL1, control); 6276 6277 test_set_guest(apic_reg_virt_guest); 6278 6279 /* 6280 * From the SDM: The 1-setting of the "virtualize APIC accesses" 6281 * VM-execution is guaranteed to apply only if translations to the 6282 * APIC-access address use a 4-KByte page. 6283 */ 6284 apic_access_address = alloc_page(); 6285 force_4k_page(apic_access_address); 6286 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_address)); 6287 6288 virtual_apic_page = alloc_page(); 6289 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 6290 6291 for (i = 0; i < ARRAY_SIZE(apic_reg_tests); i++) { 6292 struct apic_reg_test *apic_reg_test = &apic_reg_tests[i]; 6293 struct apic_reg_virt_config *apic_reg_virt_config = 6294 &apic_reg_test->apic_reg_virt_config; 6295 enum Config_type config_type; 6296 u32 reg; 6297 6298 printf("--- %s test ---\n", apic_reg_test->name); 6299 config_type = 6300 configure_apic_reg_virt_test(apic_reg_virt_config); 6301 if (config_type == CONFIG_TYPE_UNSUPPORTED) { 6302 printf("Skip because of missing features.\n"); 6303 continue; 6304 } 6305 6306 if (config_type == CONFIG_TYPE_VMENTRY_FAILS_EARLY) { 6307 enter_guest_with_bad_controls(); 6308 continue; 6309 } 6310 6311 for (reg = 0; reg < PAGE_SIZE / sizeof(u32); reg += 0x10) { 6312 struct apic_reg_virt_expectation expectation = {}; 6313 bool ok; 6314 6315 ok = apic_reg_virt_exit_expectation( 6316 reg, apic_reg_virt_config, &expectation); 6317 if (!ok) { 6318 report_fail("Malformed test."); 6319 break; 6320 } 6321 6322 test_xapic_rd(reg, &expectation, apic_access_address, 6323 virtual_apic_page); 6324 test_xapic_wr(reg, &expectation, apic_access_address, 6325 virtual_apic_page); 6326 } 6327 } 6328 6329 /* Terminate the guest */ 6330 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6331 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6332 args->op = TERMINATE; 6333 enter_guest(); 6334 assert_exit_reason(VMX_VMCALL); 6335 } 6336 6337 struct virt_x2apic_mode_config { 6338 struct apic_reg_virt_config apic_reg_virt_config; 6339 bool virtual_interrupt_delivery; 6340 bool use_msr_bitmaps; 6341 bool disable_x2apic_msr_intercepts; 6342 bool disable_x2apic; 6343 }; 6344 6345 struct virt_x2apic_mode_test_case { 6346 const char *name; 6347 struct virt_x2apic_mode_config virt_x2apic_mode_config; 6348 }; 6349 6350 enum Virt_x2apic_mode_behavior_type { 6351 X2APIC_ACCESS_VIRTUALIZED, 6352 X2APIC_ACCESS_PASSED_THROUGH, 6353 X2APIC_ACCESS_TRIGGERS_GP, 6354 }; 6355 6356 struct virt_x2apic_mode_expectation { 6357 enum Reason rd_exit_reason; 6358 enum Reason wr_exit_reason; 6359 6360 /* 6361 * RDMSR and WRMSR handle 64-bit values. However, except for ICR, all of 6362 * the x2APIC registers are 32 bits. Notice: 6363 * 1. vmx_x2apic_read() clears the upper 32 bits for 32-bit registers. 6364 * 2. vmx_x2apic_write() expects the val arg to be well-formed. 6365 */ 6366 u64 rd_val; 6367 u64 wr_val; 6368 6369 /* 6370 * Compares input to virtualized output; 6371 * 1st arg is pointer to return expected virtualization output. 6372 */ 6373 u64 (*virt_fn)(u64); 6374 6375 enum Virt_x2apic_mode_behavior_type rd_behavior; 6376 enum Virt_x2apic_mode_behavior_type wr_behavior; 6377 bool wr_only; 6378 }; 6379 6380 static u64 virt_x2apic_mode_identity(u64 val) 6381 { 6382 return val; 6383 } 6384 6385 static u64 virt_x2apic_mode_nibble1(u64 val) 6386 { 6387 return val & 0xf0; 6388 } 6389 6390 static void virt_x2apic_mode_rd_expectation( 6391 u32 reg, bool virt_x2apic_mode_on, bool disable_x2apic, 6392 bool apic_register_virtualization, bool virtual_interrupt_delivery, 6393 struct virt_x2apic_mode_expectation *expectation) 6394 { 6395 bool readable = 6396 !x2apic_reg_reserved(reg) && 6397 reg != APIC_EOI; 6398 6399 expectation->rd_exit_reason = VMX_VMCALL; 6400 expectation->virt_fn = virt_x2apic_mode_identity; 6401 if (virt_x2apic_mode_on && apic_register_virtualization) { 6402 expectation->rd_val = MAGIC_VAL_1; 6403 if (reg == APIC_PROCPRI && virtual_interrupt_delivery) 6404 expectation->virt_fn = virt_x2apic_mode_nibble1; 6405 else if (reg == APIC_TASKPRI) 6406 expectation->virt_fn = virt_x2apic_mode_nibble1; 6407 expectation->rd_behavior = X2APIC_ACCESS_VIRTUALIZED; 6408 } else if (virt_x2apic_mode_on && !apic_register_virtualization && 6409 reg == APIC_TASKPRI) { 6410 expectation->rd_val = MAGIC_VAL_1; 6411 expectation->virt_fn = virt_x2apic_mode_nibble1; 6412 expectation->rd_behavior = X2APIC_ACCESS_VIRTUALIZED; 6413 } else if (!disable_x2apic && readable) { 6414 expectation->rd_val = apic_read(reg); 6415 expectation->rd_behavior = X2APIC_ACCESS_PASSED_THROUGH; 6416 } else { 6417 expectation->rd_behavior = X2APIC_ACCESS_TRIGGERS_GP; 6418 } 6419 } 6420 6421 /* 6422 * get_x2apic_wr_val() creates an innocuous write value for an x2APIC register. 6423 * 6424 * For writable registers, get_x2apic_wr_val() deposits the write value into the 6425 * val pointer arg and returns true. For non-writable registers, val is not 6426 * modified and get_x2apic_wr_val() returns false. 6427 */ 6428 static bool get_x2apic_wr_val(u32 reg, u64 *val) 6429 { 6430 switch (reg) { 6431 case APIC_TASKPRI: 6432 /* Bits 31:8 are reserved. */ 6433 *val &= 0xff; 6434 break; 6435 case APIC_EOI: 6436 case APIC_ESR: 6437 case APIC_TMICT: 6438 /* 6439 * EOI, ESR: WRMSR of a non-zero value causes #GP(0). 6440 * TMICT: A write of 0 to the initial-count register effectively 6441 * stops the local APIC timer, in both one-shot and 6442 * periodic mode. 6443 */ 6444 *val = 0; 6445 break; 6446 case APIC_SPIV: 6447 case APIC_LVTT: 6448 case APIC_LVTTHMR: 6449 case APIC_LVTPC: 6450 case APIC_LVT0: 6451 case APIC_LVT1: 6452 case APIC_LVTERR: 6453 case APIC_TDCR: 6454 /* 6455 * To avoid writing a 1 to a reserved bit or causing some other 6456 * unintended side effect, read the current value and use it as 6457 * the write value. 6458 */ 6459 *val = apic_read(reg); 6460 break; 6461 case APIC_CMCI: 6462 if (!apic_lvt_entry_supported(6)) 6463 return false; 6464 *val = apic_read(reg); 6465 break; 6466 case APIC_ICR: 6467 *val = 0x40000 | 0xf1; 6468 break; 6469 case APIC_SELF_IPI: 6470 /* 6471 * With special processing (i.e., virtualize x2APIC mode + 6472 * virtual interrupt delivery), writing zero causes an 6473 * APIC-write VM exit. We plan to add a test for enabling 6474 * "virtual-interrupt delivery" in VMCS12, and that's where we 6475 * will test a self IPI with special processing. 6476 */ 6477 *val = 0x0; 6478 break; 6479 default: 6480 return false; 6481 } 6482 6483 return true; 6484 } 6485 6486 static bool special_processing_applies(u32 reg, u64 *val, 6487 bool virt_int_delivery) 6488 { 6489 bool special_processing = 6490 (reg == APIC_TASKPRI) || 6491 (virt_int_delivery && 6492 (reg == APIC_EOI || reg == APIC_SELF_IPI)); 6493 6494 if (special_processing) { 6495 TEST_ASSERT(get_x2apic_wr_val(reg, val)); 6496 return true; 6497 } 6498 6499 return false; 6500 } 6501 6502 static void virt_x2apic_mode_wr_expectation( 6503 u32 reg, bool virt_x2apic_mode_on, bool disable_x2apic, 6504 bool virt_int_delivery, 6505 struct virt_x2apic_mode_expectation *expectation) 6506 { 6507 expectation->wr_exit_reason = VMX_VMCALL; 6508 expectation->wr_val = MAGIC_VAL_1; 6509 expectation->wr_only = false; 6510 6511 if (virt_x2apic_mode_on && 6512 special_processing_applies(reg, &expectation->wr_val, 6513 virt_int_delivery)) { 6514 expectation->wr_behavior = X2APIC_ACCESS_VIRTUALIZED; 6515 if (reg == APIC_SELF_IPI) 6516 expectation->wr_exit_reason = VMX_APIC_WRITE; 6517 } else if (!disable_x2apic && 6518 get_x2apic_wr_val(reg, &expectation->wr_val)) { 6519 expectation->wr_behavior = X2APIC_ACCESS_PASSED_THROUGH; 6520 if (reg == APIC_EOI || reg == APIC_SELF_IPI) 6521 expectation->wr_only = true; 6522 if (reg == APIC_ICR) 6523 expectation->wr_exit_reason = VMX_EXTINT; 6524 } else { 6525 expectation->wr_behavior = X2APIC_ACCESS_TRIGGERS_GP; 6526 /* 6527 * Writing 1 to a reserved bit triggers a #GP. 6528 * Thus, set the write value to 0, which seems 6529 * the most likely to detect a missed #GP. 6530 */ 6531 expectation->wr_val = 0; 6532 } 6533 } 6534 6535 static void virt_x2apic_mode_exit_expectation( 6536 u32 reg, struct virt_x2apic_mode_config *config, 6537 struct virt_x2apic_mode_expectation *expectation) 6538 { 6539 struct apic_reg_virt_config *base_config = 6540 &config->apic_reg_virt_config; 6541 bool virt_x2apic_mode_on = 6542 base_config->virtualize_x2apic_mode && 6543 config->use_msr_bitmaps && 6544 config->disable_x2apic_msr_intercepts && 6545 base_config->activate_secondary_controls; 6546 6547 virt_x2apic_mode_wr_expectation( 6548 reg, virt_x2apic_mode_on, config->disable_x2apic, 6549 config->virtual_interrupt_delivery, expectation); 6550 virt_x2apic_mode_rd_expectation( 6551 reg, virt_x2apic_mode_on, config->disable_x2apic, 6552 base_config->apic_register_virtualization, 6553 config->virtual_interrupt_delivery, expectation); 6554 } 6555 6556 struct virt_x2apic_mode_test_case virt_x2apic_mode_tests[] = { 6557 /* 6558 * Baseline "virtualize x2APIC mode" configuration: 6559 * - virtualize x2APIC mode 6560 * - virtual-interrupt delivery 6561 * - APIC-register virtualization 6562 * - x2APIC MSR intercepts disabled 6563 * 6564 * Reads come from virtual APIC page, special processing applies to 6565 * VTPR, EOI, and SELF IPI, and all other writes pass through to L1 6566 * APIC. 6567 */ 6568 { 6569 .name = "Baseline", 6570 .virt_x2apic_mode_config = { 6571 .virtual_interrupt_delivery = true, 6572 .use_msr_bitmaps = true, 6573 .disable_x2apic_msr_intercepts = true, 6574 .disable_x2apic = false, 6575 .apic_reg_virt_config = { 6576 .apic_register_virtualization = true, 6577 .use_tpr_shadow = true, 6578 .virtualize_apic_accesses = false, 6579 .virtualize_x2apic_mode = true, 6580 .activate_secondary_controls = true, 6581 }, 6582 }, 6583 }, 6584 { 6585 .name = "Baseline w/ x2apic disabled", 6586 .virt_x2apic_mode_config = { 6587 .virtual_interrupt_delivery = true, 6588 .use_msr_bitmaps = true, 6589 .disable_x2apic_msr_intercepts = true, 6590 .disable_x2apic = true, 6591 .apic_reg_virt_config = { 6592 .apic_register_virtualization = true, 6593 .use_tpr_shadow = true, 6594 .virtualize_apic_accesses = false, 6595 .virtualize_x2apic_mode = true, 6596 .activate_secondary_controls = true, 6597 }, 6598 }, 6599 }, 6600 6601 /* 6602 * Baseline, minus virtual-interrupt delivery. Reads come from virtual 6603 * APIC page, special processing applies to VTPR, and all other writes 6604 * pass through to L1 APIC. 6605 */ 6606 { 6607 .name = "Baseline - virtual interrupt delivery", 6608 .virt_x2apic_mode_config = { 6609 .virtual_interrupt_delivery = false, 6610 .use_msr_bitmaps = true, 6611 .disable_x2apic_msr_intercepts = true, 6612 .disable_x2apic = false, 6613 .apic_reg_virt_config = { 6614 .apic_register_virtualization = true, 6615 .use_tpr_shadow = true, 6616 .virtualize_apic_accesses = false, 6617 .virtualize_x2apic_mode = true, 6618 .activate_secondary_controls = true, 6619 }, 6620 }, 6621 }, 6622 6623 /* 6624 * Baseline, minus APIC-register virtualization. x2APIC reads pass 6625 * through to L1's APIC, unless reading VTPR 6626 */ 6627 { 6628 .name = "Virtualize x2APIC mode, no APIC reg virt", 6629 .virt_x2apic_mode_config = { 6630 .virtual_interrupt_delivery = true, 6631 .use_msr_bitmaps = true, 6632 .disable_x2apic_msr_intercepts = true, 6633 .disable_x2apic = false, 6634 .apic_reg_virt_config = { 6635 .apic_register_virtualization = false, 6636 .use_tpr_shadow = true, 6637 .virtualize_apic_accesses = false, 6638 .virtualize_x2apic_mode = true, 6639 .activate_secondary_controls = true, 6640 }, 6641 }, 6642 }, 6643 { 6644 .name = "Virtualize x2APIC mode, no APIC reg virt, x2APIC off", 6645 .virt_x2apic_mode_config = { 6646 .virtual_interrupt_delivery = true, 6647 .use_msr_bitmaps = true, 6648 .disable_x2apic_msr_intercepts = true, 6649 .disable_x2apic = true, 6650 .apic_reg_virt_config = { 6651 .apic_register_virtualization = false, 6652 .use_tpr_shadow = true, 6653 .virtualize_apic_accesses = false, 6654 .virtualize_x2apic_mode = true, 6655 .activate_secondary_controls = true, 6656 }, 6657 }, 6658 }, 6659 6660 /* 6661 * Enable "virtualize x2APIC mode" and "APIC-register virtualization", 6662 * and disable intercepts for the x2APIC MSRs, but fail to enable 6663 * "activate secondary controls" (i.e. L2 gets access to L1's x2APIC 6664 * MSRs). 6665 */ 6666 { 6667 .name = "Fail to enable activate secondary controls", 6668 .virt_x2apic_mode_config = { 6669 .virtual_interrupt_delivery = true, 6670 .use_msr_bitmaps = true, 6671 .disable_x2apic_msr_intercepts = true, 6672 .disable_x2apic = false, 6673 .apic_reg_virt_config = { 6674 .apic_register_virtualization = true, 6675 .use_tpr_shadow = true, 6676 .virtualize_apic_accesses = false, 6677 .virtualize_x2apic_mode = true, 6678 .activate_secondary_controls = false, 6679 }, 6680 }, 6681 }, 6682 6683 /* 6684 * Enable "APIC-register virtualization" and enable "activate secondary 6685 * controls" and disable intercepts for the x2APIC MSRs, but do not 6686 * enable the "virtualize x2APIC mode" VM-execution control (i.e. L2 6687 * gets access to L1's x2APIC MSRs). 6688 */ 6689 { 6690 .name = "Fail to enable virtualize x2APIC mode", 6691 .virt_x2apic_mode_config = { 6692 .virtual_interrupt_delivery = true, 6693 .use_msr_bitmaps = true, 6694 .disable_x2apic_msr_intercepts = true, 6695 .disable_x2apic = false, 6696 .apic_reg_virt_config = { 6697 .apic_register_virtualization = true, 6698 .use_tpr_shadow = true, 6699 .virtualize_apic_accesses = false, 6700 .virtualize_x2apic_mode = false, 6701 .activate_secondary_controls = true, 6702 }, 6703 }, 6704 }, 6705 6706 /* 6707 * Disable "Virtualize x2APIC mode", disable x2APIC MSR intercepts, and 6708 * enable "APIC-register virtualization" --> L2 gets L1's x2APIC MSRs. 6709 */ 6710 { 6711 .name = "Baseline", 6712 .virt_x2apic_mode_config = { 6713 .virtual_interrupt_delivery = true, 6714 .use_msr_bitmaps = true, 6715 .disable_x2apic_msr_intercepts = true, 6716 .disable_x2apic = false, 6717 .apic_reg_virt_config = { 6718 .apic_register_virtualization = true, 6719 .use_tpr_shadow = true, 6720 .virtualize_apic_accesses = false, 6721 .virtualize_x2apic_mode = false, 6722 .activate_secondary_controls = true, 6723 }, 6724 }, 6725 }, 6726 }; 6727 6728 enum X2apic_op { 6729 X2APIC_OP_RD, 6730 X2APIC_OP_WR, 6731 X2APIC_TERMINATE, 6732 }; 6733 6734 static u64 vmx_x2apic_read(u32 reg) 6735 { 6736 u32 msr_addr = x2apic_msr(reg); 6737 u64 val; 6738 6739 val = rdmsr(msr_addr); 6740 6741 return val; 6742 } 6743 6744 static void vmx_x2apic_write(u32 reg, u64 val) 6745 { 6746 u32 msr_addr = x2apic_msr(reg); 6747 6748 wrmsr(msr_addr, val); 6749 } 6750 6751 struct virt_x2apic_mode_guest_args { 6752 enum X2apic_op op; 6753 u32 reg; 6754 u64 val; 6755 bool should_gp; 6756 u64 (*virt_fn)(u64); 6757 } virt_x2apic_mode_guest_args; 6758 6759 static volatile bool handle_x2apic_gp_ran; 6760 static volatile u32 handle_x2apic_gp_insn_len; 6761 static void handle_x2apic_gp(struct ex_regs *regs) 6762 { 6763 handle_x2apic_gp_ran = true; 6764 regs->rip += handle_x2apic_gp_insn_len; 6765 } 6766 6767 static handler setup_x2apic_gp_handler(void) 6768 { 6769 handler old_handler; 6770 6771 old_handler = handle_exception(GP_VECTOR, handle_x2apic_gp); 6772 /* RDMSR and WRMSR are both 2 bytes, assuming no prefixes. */ 6773 handle_x2apic_gp_insn_len = 2; 6774 6775 return old_handler; 6776 } 6777 6778 static void teardown_x2apic_gp_handler(handler old_handler) 6779 { 6780 handle_exception(GP_VECTOR, old_handler); 6781 6782 /* 6783 * Defensively reset instruction length, so that if the handler is 6784 * incorrectly used, it will loop infinitely, rather than run off into 6785 * la la land. 6786 */ 6787 handle_x2apic_gp_insn_len = 0; 6788 handle_x2apic_gp_ran = false; 6789 } 6790 6791 static void virt_x2apic_mode_guest(void) 6792 { 6793 volatile struct virt_x2apic_mode_guest_args *args = 6794 &virt_x2apic_mode_guest_args; 6795 6796 for (;;) { 6797 enum X2apic_op op = args->op; 6798 u32 reg = args->reg; 6799 u64 val = args->val; 6800 bool should_gp = args->should_gp; 6801 u64 (*virt_fn)(u64) = args->virt_fn; 6802 handler old_handler; 6803 6804 if (op == X2APIC_TERMINATE) 6805 break; 6806 6807 if (should_gp) { 6808 TEST_ASSERT(!handle_x2apic_gp_ran); 6809 old_handler = setup_x2apic_gp_handler(); 6810 } 6811 6812 if (op == X2APIC_OP_RD) { 6813 u64 ret = vmx_x2apic_read(reg); 6814 6815 if (!should_gp) { 6816 u64 want = virt_fn(val); 6817 u64 got = virt_fn(ret); 6818 6819 report(got == want, 6820 "APIC read; got 0x%lx, want 0x%lx.", 6821 got, want); 6822 } 6823 } else if (op == X2APIC_OP_WR) { 6824 vmx_x2apic_write(reg, val); 6825 } 6826 6827 if (should_gp) { 6828 report(handle_x2apic_gp_ran, 6829 "x2APIC op triggered GP."); 6830 teardown_x2apic_gp_handler(old_handler); 6831 } 6832 6833 /* 6834 * The L1 should always execute a vmcall after it's done testing 6835 * an individual APIC operation. This helps to validate that the 6836 * L1 and L2 are in sync with each other, as expected. 6837 */ 6838 vmcall(); 6839 } 6840 } 6841 6842 static void test_x2apic_rd( 6843 u32 reg, struct virt_x2apic_mode_expectation *expectation, 6844 u32 *virtual_apic_page) 6845 { 6846 u64 val = expectation->rd_val; 6847 u32 exit_reason_want = expectation->rd_exit_reason; 6848 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6849 6850 report_prefix_pushf("x2apic - reading 0x%03x", reg); 6851 6852 /* Configure guest to do an x2apic read */ 6853 args->op = X2APIC_OP_RD; 6854 args->reg = reg; 6855 args->val = val; 6856 args->should_gp = expectation->rd_behavior == X2APIC_ACCESS_TRIGGERS_GP; 6857 args->virt_fn = expectation->virt_fn; 6858 6859 /* Setup virtual APIC page */ 6860 if (expectation->rd_behavior == X2APIC_ACCESS_VIRTUALIZED) 6861 virtual_apic_page[apic_reg_index(reg)] = (u32)val; 6862 6863 /* Enter guest */ 6864 enter_guest(); 6865 6866 if (exit_reason_want != VMX_VMCALL) { 6867 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 6868 } 6869 6870 skip_exit_vmcall(); 6871 report_prefix_pop(); 6872 } 6873 6874 static volatile bool handle_x2apic_ipi_ran; 6875 static void handle_x2apic_ipi(isr_regs_t *regs) 6876 { 6877 handle_x2apic_ipi_ran = true; 6878 eoi(); 6879 } 6880 6881 static void test_x2apic_wr( 6882 u32 reg, struct virt_x2apic_mode_expectation *expectation, 6883 u32 *virtual_apic_page) 6884 { 6885 u64 val = expectation->wr_val; 6886 u32 exit_reason_want = expectation->wr_exit_reason; 6887 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6888 int ipi_vector = 0xf1; 6889 u32 restore_val = 0; 6890 6891 report_prefix_pushf("x2apic - writing 0x%lx to 0x%03x", val, reg); 6892 6893 /* Configure guest to do an x2apic read */ 6894 args->op = X2APIC_OP_WR; 6895 args->reg = reg; 6896 args->val = val; 6897 args->should_gp = expectation->wr_behavior == X2APIC_ACCESS_TRIGGERS_GP; 6898 6899 /* Setup virtual APIC page */ 6900 if (expectation->wr_behavior == X2APIC_ACCESS_VIRTUALIZED) 6901 virtual_apic_page[apic_reg_index(reg)] = 0; 6902 if (expectation->wr_behavior == X2APIC_ACCESS_PASSED_THROUGH && !expectation->wr_only) 6903 restore_val = apic_read(reg); 6904 6905 /* Setup IPI handler */ 6906 handle_x2apic_ipi_ran = false; 6907 handle_irq(ipi_vector, handle_x2apic_ipi); 6908 6909 /* Enter guest */ 6910 enter_guest(); 6911 6912 /* 6913 * Validate the behavior and 6914 * pass a magic value back to the guest. 6915 */ 6916 if (exit_reason_want == VMX_EXTINT) { 6917 assert_exit_reason(exit_reason_want); 6918 6919 /* Clear the external interrupt. */ 6920 irq_enable(); 6921 asm volatile ("nop"); 6922 irq_disable(); 6923 report(handle_x2apic_ipi_ran, 6924 "Got pending interrupt after IRQ enabled."); 6925 6926 enter_guest(); 6927 } else if (exit_reason_want == VMX_APIC_WRITE) { 6928 assert_exit_reason(exit_reason_want); 6929 report(virtual_apic_page[apic_reg_index(reg)] == val, 6930 "got APIC write exit @ page offset 0x%03x; val is 0x%x, want 0x%lx", 6931 apic_reg_index(reg), 6932 virtual_apic_page[apic_reg_index(reg)], val); 6933 6934 /* Reenter guest so it can consume/check rcx and exit again. */ 6935 enter_guest(); 6936 } else if (exit_reason_want != VMX_VMCALL) { 6937 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 6938 } 6939 6940 assert_exit_reason(VMX_VMCALL); 6941 if (expectation->wr_behavior == X2APIC_ACCESS_VIRTUALIZED) { 6942 u64 want = val; 6943 u32 got = virtual_apic_page[apic_reg_index(reg)]; 6944 6945 report(got == want, "x2APIC write; got 0x%x, want 0x%lx", got, 6946 want); 6947 } else if (expectation->wr_behavior == X2APIC_ACCESS_PASSED_THROUGH) { 6948 if (!expectation->wr_only) { 6949 u32 got = apic_read(reg); 6950 bool ok; 6951 6952 /* 6953 * When L1's TPR is passed through to L2, the lower 6954 * nibble can be lost. For example, if L2 executes 6955 * WRMSR(0x808, 0x78), then, L1 might read 0x70. 6956 * 6957 * Here's how the lower nibble can get lost: 6958 * 1. L2 executes WRMSR(0x808, 0x78). 6959 * 2. L2 exits to L0 with a WRMSR exit. 6960 * 3. L0 emulates WRMSR, by writing L1's TPR. 6961 * 4. L0 re-enters L2. 6962 * 5. L2 exits to L0 (reason doesn't matter). 6963 * 6. L0 reflects L2's exit to L1. 6964 * 7. Before entering L1, L0 exits to user-space 6965 * (e.g., to satisfy TPR access reporting). 6966 * 8. User-space executes KVM_SET_REGS ioctl, which 6967 * clears the lower nibble of L1's TPR. 6968 */ 6969 if (reg == APIC_TASKPRI) { 6970 got = apic_virt_nibble1(got); 6971 val = apic_virt_nibble1(val); 6972 } 6973 6974 ok = got == val; 6975 report(ok, 6976 "non-virtualized write; val is 0x%x, want 0x%lx", 6977 got, val); 6978 apic_write(reg, restore_val); 6979 } else { 6980 report_pass("non-virtualized and write-only OK"); 6981 } 6982 } 6983 skip_exit_insn(); 6984 6985 report_prefix_pop(); 6986 } 6987 6988 static enum Config_type configure_virt_x2apic_mode_test( 6989 struct virt_x2apic_mode_config *virt_x2apic_mode_config, 6990 u8 *msr_bitmap_page) 6991 { 6992 int msr; 6993 u32 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6994 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6995 6996 /* x2apic-specific VMCS config */ 6997 if (virt_x2apic_mode_config->use_msr_bitmaps) { 6998 /* virt_x2apic_mode_test() checks for MSR bitmaps support */ 6999 cpu_exec_ctrl0 |= CPU_MSR_BITMAP; 7000 } else { 7001 cpu_exec_ctrl0 &= ~CPU_MSR_BITMAP; 7002 } 7003 7004 if (virt_x2apic_mode_config->virtual_interrupt_delivery) { 7005 if (!(ctrl_cpu_rev[1].clr & CPU_VINTD)) { 7006 report_skip("VM-execution control \"virtual-interrupt delivery\" NOT supported.\n"); 7007 return CONFIG_TYPE_UNSUPPORTED; 7008 } 7009 cpu_exec_ctrl1 |= CPU_VINTD; 7010 } else { 7011 cpu_exec_ctrl1 &= ~CPU_VINTD; 7012 } 7013 7014 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 7015 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 7016 7017 /* x2APIC MSR intercepts are usually off for "Virtualize x2APIC mode" */ 7018 for (msr = 0x800; msr <= 0x8ff; msr++) { 7019 if (virt_x2apic_mode_config->disable_x2apic_msr_intercepts) { 7020 clear_bit(msr, msr_bitmap_page + 0x000); 7021 clear_bit(msr, msr_bitmap_page + 0x800); 7022 } else { 7023 set_bit(msr, msr_bitmap_page + 0x000); 7024 set_bit(msr, msr_bitmap_page + 0x800); 7025 } 7026 } 7027 7028 /* x2APIC mode can impact virtualization */ 7029 reset_apic(); 7030 if (!virt_x2apic_mode_config->disable_x2apic) 7031 enable_x2apic(); 7032 7033 return configure_apic_reg_virt_test( 7034 &virt_x2apic_mode_config->apic_reg_virt_config); 7035 } 7036 7037 static void virt_x2apic_mode_test(void) 7038 { 7039 u32 *virtual_apic_page; 7040 u8 *msr_bitmap_page; 7041 u64 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 7042 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 7043 int i; 7044 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 7045 7046 if (!cpu_has_apicv()) { 7047 report_skip(__func__); 7048 return; 7049 } 7050 7051 /* 7052 * This is to exercise an issue in KVM's logic to merge L0's and L1's 7053 * MSR bitmaps. Previously, an L1 could get at L0's x2APIC MSRs by 7054 * writing the IA32_SPEC_CTRL MSR or the IA32_PRED_CMD MSRs. KVM would 7055 * then proceed to manipulate the MSR bitmaps, as if VMCS12 had the 7056 * "Virtualize x2APIC mod" control set, even when it didn't. 7057 */ 7058 if (has_spec_ctrl()) 7059 wrmsr(MSR_IA32_SPEC_CTRL, 1); 7060 7061 /* 7062 * Check that VMCS12 supports: 7063 * - "Virtual-APIC address", indicated by "use TPR shadow" 7064 * - "MSR-bitmap address", indicated by "use MSR bitmaps" 7065 */ 7066 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) { 7067 report_skip("VM-execution control \"use TPR shadow\" NOT supported.\n"); 7068 return; 7069 } else if (!(ctrl_cpu_rev[0].clr & CPU_MSR_BITMAP)) { 7070 report_skip("VM-execution control \"use MSR bitmaps\" NOT supported.\n"); 7071 return; 7072 } 7073 7074 test_set_guest(virt_x2apic_mode_guest); 7075 7076 virtual_apic_page = alloc_page(); 7077 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 7078 7079 msr_bitmap_page = alloc_page(); 7080 memset(msr_bitmap_page, 0xff, PAGE_SIZE); 7081 vmcs_write(MSR_BITMAP, virt_to_phys(msr_bitmap_page)); 7082 7083 for (i = 0; i < ARRAY_SIZE(virt_x2apic_mode_tests); i++) { 7084 struct virt_x2apic_mode_test_case *virt_x2apic_mode_test_case = 7085 &virt_x2apic_mode_tests[i]; 7086 struct virt_x2apic_mode_config *virt_x2apic_mode_config = 7087 &virt_x2apic_mode_test_case->virt_x2apic_mode_config; 7088 enum Config_type config_type; 7089 u32 reg; 7090 7091 printf("--- %s test ---\n", virt_x2apic_mode_test_case->name); 7092 config_type = 7093 configure_virt_x2apic_mode_test(virt_x2apic_mode_config, 7094 msr_bitmap_page); 7095 if (config_type == CONFIG_TYPE_UNSUPPORTED) { 7096 report_skip("Skip because of missing features.\n"); 7097 continue; 7098 } else if (config_type == CONFIG_TYPE_VMENTRY_FAILS_EARLY) { 7099 enter_guest_with_bad_controls(); 7100 continue; 7101 } 7102 7103 for (reg = 0; reg < PAGE_SIZE / sizeof(u32); reg += 0x10) { 7104 struct virt_x2apic_mode_expectation expectation; 7105 7106 virt_x2apic_mode_exit_expectation( 7107 reg, virt_x2apic_mode_config, &expectation); 7108 7109 test_x2apic_rd(reg, &expectation, virtual_apic_page); 7110 test_x2apic_wr(reg, &expectation, virtual_apic_page); 7111 } 7112 } 7113 7114 7115 /* Terminate the guest */ 7116 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 7117 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 7118 args->op = X2APIC_TERMINATE; 7119 enter_guest(); 7120 assert_exit_reason(VMX_VMCALL); 7121 } 7122 7123 static void test_ctl_reg(const char *cr_name, u64 cr, u64 fixed0, u64 fixed1) 7124 { 7125 u64 val; 7126 u64 cr_saved = vmcs_read(cr); 7127 int i; 7128 7129 val = fixed0 & fixed1; 7130 if (cr == HOST_CR4) 7131 vmcs_write(cr, val | X86_CR4_PAE); 7132 else 7133 vmcs_write(cr, val); 7134 report_prefix_pushf("%s %lx", cr_name, val); 7135 if (val == fixed0) 7136 test_vmx_vmlaunch(0); 7137 else 7138 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7139 report_prefix_pop(); 7140 7141 for (i = 0; i < 64; i++) { 7142 7143 /* Set a bit when the corresponding bit in fixed1 is 0 */ 7144 if ((fixed1 & (1ull << i)) == 0) { 7145 if (cr == HOST_CR4 && ((1ull << i) & X86_CR4_SMEP || 7146 (1ull << i) & X86_CR4_SMAP)) 7147 continue; 7148 7149 vmcs_write(cr, cr_saved | (1ull << i)); 7150 report_prefix_pushf("%s %llx", cr_name, 7151 cr_saved | (1ull << i)); 7152 test_vmx_vmlaunch( 7153 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7154 report_prefix_pop(); 7155 } 7156 7157 /* Unset a bit when the corresponding bit in fixed0 is 1 */ 7158 if (fixed0 & (1ull << i)) { 7159 vmcs_write(cr, cr_saved & ~(1ull << i)); 7160 report_prefix_pushf("%s %llx", cr_name, 7161 cr_saved & ~(1ull << i)); 7162 test_vmx_vmlaunch( 7163 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7164 report_prefix_pop(); 7165 } 7166 } 7167 7168 vmcs_write(cr, cr_saved); 7169 } 7170 7171 /* 7172 * 1. The CR0 field must not set any bit to a value not supported in VMX 7173 * operation. 7174 * 2. The CR4 field must not set any bit to a value not supported in VMX 7175 * operation. 7176 * 3. On processors that support Intel 64 architecture, the CR3 field must 7177 * be such that bits 63:52 and bits in the range 51:32 beyond the 7178 * processor's physical-address width must be 0. 7179 * 7180 * [Intel SDM] 7181 */ 7182 static void test_host_ctl_regs(void) 7183 { 7184 u64 fixed0, fixed1, cr3, cr3_saved; 7185 int i; 7186 7187 /* Test CR0 */ 7188 fixed0 = rdmsr(MSR_IA32_VMX_CR0_FIXED0); 7189 fixed1 = rdmsr(MSR_IA32_VMX_CR0_FIXED1); 7190 test_ctl_reg("HOST_CR0", HOST_CR0, fixed0, fixed1); 7191 7192 /* Test CR4 */ 7193 fixed0 = rdmsr(MSR_IA32_VMX_CR4_FIXED0); 7194 fixed1 = rdmsr(MSR_IA32_VMX_CR4_FIXED1) & 7195 ~(X86_CR4_SMEP | X86_CR4_SMAP); 7196 test_ctl_reg("HOST_CR4", HOST_CR4, fixed0, fixed1); 7197 7198 /* Test CR3 */ 7199 cr3_saved = vmcs_read(HOST_CR3); 7200 for (i = cpuid_maxphyaddr(); i < 64; i++) { 7201 cr3 = cr3_saved | (1ul << i); 7202 vmcs_write(HOST_CR3, cr3); 7203 report_prefix_pushf("HOST_CR3 %lx", cr3); 7204 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7205 report_prefix_pop(); 7206 } 7207 7208 vmcs_write(HOST_CR3, cr3_saved); 7209 } 7210 7211 static void test_efer_vmlaunch(u32 fld, bool ok) 7212 { 7213 if (fld == HOST_EFER) { 7214 if (ok) 7215 test_vmx_vmlaunch(0); 7216 else 7217 test_vmx_vmlaunch2(VMXERR_ENTRY_INVALID_CONTROL_FIELD, 7218 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7219 } else { 7220 test_guest_state("EFER test", !ok, GUEST_EFER, "GUEST_EFER"); 7221 } 7222 } 7223 7224 static void test_efer_one(u32 fld, const char * fld_name, u64 efer, 7225 u32 ctrl_fld, u64 ctrl, 7226 int i, const char *efer_bit_name) 7227 { 7228 bool ok; 7229 7230 ok = true; 7231 if (ctrl_fld == EXI_CONTROLS && (ctrl & EXI_LOAD_EFER)) { 7232 if (!!(efer & EFER_LMA) != !!(ctrl & EXI_HOST_64)) 7233 ok = false; 7234 if (!!(efer & EFER_LME) != !!(ctrl & EXI_HOST_64)) 7235 ok = false; 7236 } 7237 if (ctrl_fld == ENT_CONTROLS && (ctrl & ENT_LOAD_EFER)) { 7238 /* Check LMA too since CR0.PG is set. */ 7239 if (!!(efer & EFER_LMA) != !!(ctrl & ENT_GUEST_64)) 7240 ok = false; 7241 if (!!(efer & EFER_LME) != !!(ctrl & ENT_GUEST_64)) 7242 ok = false; 7243 } 7244 7245 /* 7246 * Skip the test if it would enter the guest in 32-bit mode. 7247 * Perhaps write the test in assembly and make sure it 7248 * can be run in either mode? 7249 */ 7250 if (fld == GUEST_EFER && ok && !(ctrl & ENT_GUEST_64)) 7251 return; 7252 7253 vmcs_write(ctrl_fld, ctrl); 7254 vmcs_write(fld, efer); 7255 report_prefix_pushf("%s %s bit turned %s, controls %s", 7256 fld_name, efer_bit_name, 7257 (i & 1) ? "on" : "off", 7258 (i & 2) ? "on" : "off"); 7259 7260 test_efer_vmlaunch(fld, ok); 7261 report_prefix_pop(); 7262 } 7263 7264 static void test_efer_bit(u32 fld, const char * fld_name, 7265 u32 ctrl_fld, u64 ctrl_bit, u64 efer_bit, 7266 const char *efer_bit_name) 7267 { 7268 u64 efer_saved = vmcs_read(fld); 7269 u32 ctrl_saved = vmcs_read(ctrl_fld); 7270 int i; 7271 7272 for (i = 0; i < 4; i++) { 7273 u64 efer = efer_saved & ~efer_bit; 7274 u64 ctrl = ctrl_saved & ~ctrl_bit; 7275 7276 if (i & 1) 7277 efer |= efer_bit; 7278 if (i & 2) 7279 ctrl |= ctrl_bit; 7280 7281 test_efer_one(fld, fld_name, efer, ctrl_fld, ctrl, 7282 i, efer_bit_name); 7283 } 7284 7285 vmcs_write(ctrl_fld, ctrl_saved); 7286 vmcs_write(fld, efer_saved); 7287 } 7288 7289 static void test_efer(u32 fld, const char * fld_name, u32 ctrl_fld, 7290 u64 ctrl_bit1, u64 ctrl_bit2) 7291 { 7292 u64 efer_saved = vmcs_read(fld); 7293 u32 ctrl_saved = vmcs_read(ctrl_fld); 7294 u64 efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 7295 u64 i; 7296 u64 efer; 7297 7298 if (cpu_has_efer_nx()) 7299 efer_reserved_bits &= ~EFER_NX; 7300 7301 if (!ctrl_bit1) { 7302 printf("\"Load-IA32-EFER\" exit control not supported\n"); 7303 goto test_entry_exit_mode; 7304 } 7305 7306 report_prefix_pushf("%s %lx", fld_name, efer_saved); 7307 test_efer_vmlaunch(fld, true); 7308 report_prefix_pop(); 7309 7310 /* 7311 * Check reserved bits 7312 */ 7313 vmcs_write(ctrl_fld, ctrl_saved & ~ctrl_bit1); 7314 for (i = 0; i < 64; i++) { 7315 if ((1ull << i) & efer_reserved_bits) { 7316 efer = efer_saved | (1ull << i); 7317 vmcs_write(fld, efer); 7318 report_prefix_pushf("%s %lx", fld_name, efer); 7319 test_efer_vmlaunch(fld, true); 7320 report_prefix_pop(); 7321 } 7322 } 7323 7324 vmcs_write(ctrl_fld, ctrl_saved | ctrl_bit1); 7325 for (i = 0; i < 64; i++) { 7326 if ((1ull << i) & efer_reserved_bits) { 7327 efer = efer_saved | (1ull << i); 7328 vmcs_write(fld, efer); 7329 report_prefix_pushf("%s %lx", fld_name, efer); 7330 test_efer_vmlaunch(fld, false); 7331 report_prefix_pop(); 7332 } 7333 } 7334 7335 vmcs_write(ctrl_fld, ctrl_saved); 7336 vmcs_write(fld, efer_saved); 7337 7338 /* 7339 * Check LMA and LME bits 7340 */ 7341 test_efer_bit(fld, fld_name, 7342 ctrl_fld, ctrl_bit1, 7343 EFER_LMA, 7344 "EFER_LMA"); 7345 test_efer_bit(fld, fld_name, 7346 ctrl_fld, ctrl_bit1, 7347 EFER_LME, 7348 "EFER_LME"); 7349 7350 test_entry_exit_mode: 7351 test_efer_bit(fld, fld_name, 7352 ctrl_fld, ctrl_bit2, 7353 EFER_LMA, 7354 "EFER_LMA"); 7355 test_efer_bit(fld, fld_name, 7356 ctrl_fld, ctrl_bit2, 7357 EFER_LME, 7358 "EFER_LME"); 7359 } 7360 7361 /* 7362 * If the 'load IA32_EFER' VM-exit control is 1, bits reserved in the 7363 * IA32_EFER MSR must be 0 in the field for that register. In addition, 7364 * the values of the LMA and LME bits in the field must each be that of 7365 * the 'host address-space size' VM-exit control. 7366 * 7367 * [Intel SDM] 7368 */ 7369 static void test_host_efer(void) 7370 { 7371 test_efer(HOST_EFER, "HOST_EFER", EXI_CONTROLS, 7372 ctrl_exit_rev.clr & EXI_LOAD_EFER, 7373 EXI_HOST_64); 7374 } 7375 7376 /* 7377 * If the 'load IA32_EFER' VM-enter control is 1, bits reserved in the 7378 * IA32_EFER MSR must be 0 in the field for that register. In addition, 7379 * the values of the LMA and LME bits in the field must each be that of 7380 * the 'IA32e-mode guest' VM-exit control. 7381 */ 7382 static void test_guest_efer(void) 7383 { 7384 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) { 7385 printf("\"Load-IA32-EFER\" entry control not supported\n"); 7386 return; 7387 } 7388 7389 vmcs_write(GUEST_EFER, rdmsr(MSR_EFER)); 7390 test_efer(GUEST_EFER, "GUEST_EFER", ENT_CONTROLS, 7391 ctrl_enter_rev.clr & ENT_LOAD_EFER, 7392 ENT_GUEST_64); 7393 } 7394 7395 /* 7396 * PAT values higher than 8 are uninteresting since they're likely lumped 7397 * in with "8". We only test values above 8 one bit at a time, 7398 * in order to reduce the number of VM-Entries and keep the runtime reasonable. 7399 */ 7400 #define PAT_VAL_LIMIT 8 7401 7402 static void test_pat(u32 field, const char * field_name, u32 ctrl_field, 7403 u64 ctrl_bit) 7404 { 7405 u32 ctrl_saved = vmcs_read(ctrl_field); 7406 u64 pat_saved = vmcs_read(field); 7407 u64 i, val; 7408 u32 j; 7409 int error; 7410 7411 vmcs_clear_bits(ctrl_field, ctrl_bit); 7412 7413 for (i = 0; i < 256; i = (i < PAT_VAL_LIMIT) ? i + 1 : i * 2) { 7414 /* Test PAT0..PAT7 fields */ 7415 for (j = 0; j < (i ? 8 : 1); j++) { 7416 val = i << j * 8; 7417 vmcs_write(field, val); 7418 if (field == HOST_PAT) { 7419 report_prefix_pushf("%s %lx", field_name, val); 7420 test_vmx_vmlaunch(0); 7421 report_prefix_pop(); 7422 7423 } else { // GUEST_PAT 7424 test_guest_state("ENT_LOAD_PAT enabled", false, 7425 val, "GUEST_PAT"); 7426 } 7427 } 7428 } 7429 7430 vmcs_set_bits(ctrl_field, ctrl_bit); 7431 for (i = 0; i < 256; i = (i < PAT_VAL_LIMIT) ? i + 1 : i * 2) { 7432 /* Test PAT0..PAT7 fields */ 7433 for (j = 0; j < (i ? 8 : 1); j++) { 7434 val = i << j * 8; 7435 vmcs_write(field, val); 7436 7437 if (field == HOST_PAT) { 7438 report_prefix_pushf("%s %lx", field_name, val); 7439 if (i == 0x2 || i == 0x3 || i >= 0x8) 7440 error = 7441 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD; 7442 else 7443 error = 0; 7444 7445 test_vmx_vmlaunch(error); 7446 report_prefix_pop(); 7447 7448 } else { // GUEST_PAT 7449 error = (i == 0x2 || i == 0x3 || i >= 0x8); 7450 test_guest_state("ENT_LOAD_PAT enabled", !!error, 7451 val, "GUEST_PAT"); 7452 } 7453 7454 } 7455 } 7456 7457 vmcs_write(ctrl_field, ctrl_saved); 7458 vmcs_write(field, pat_saved); 7459 } 7460 7461 /* 7462 * If the "load IA32_PAT" VM-exit control is 1, the value of the field 7463 * for the IA32_PAT MSR must be one that could be written by WRMSR 7464 * without fault at CPL 0. Specifically, each of the 8 bytes in the 7465 * field must have one of the values 0 (UC), 1 (WC), 4 (WT), 5 (WP), 7466 * 6 (WB), or 7 (UC-). 7467 * 7468 * [Intel SDM] 7469 */ 7470 static void test_load_host_pat(void) 7471 { 7472 /* 7473 * "load IA32_PAT" VM-exit control 7474 */ 7475 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) { 7476 printf("\"Load-IA32-PAT\" exit control not supported\n"); 7477 return; 7478 } 7479 7480 test_pat(HOST_PAT, "HOST_PAT", EXI_CONTROLS, EXI_LOAD_PAT); 7481 } 7482 7483 union cpuidA_eax { 7484 struct { 7485 unsigned int version_id:8; 7486 unsigned int num_counters_gp:8; 7487 unsigned int bit_width:8; 7488 unsigned int mask_length:8; 7489 } split; 7490 unsigned int full; 7491 }; 7492 7493 union cpuidA_edx { 7494 struct { 7495 unsigned int num_counters_fixed:5; 7496 unsigned int bit_width_fixed:8; 7497 unsigned int reserved:9; 7498 } split; 7499 unsigned int full; 7500 }; 7501 7502 static bool valid_pgc(u64 val) 7503 { 7504 struct cpuid id; 7505 union cpuidA_eax eax; 7506 union cpuidA_edx edx; 7507 u64 mask; 7508 7509 id = cpuid(0xA); 7510 eax.full = id.a; 7511 edx.full = id.d; 7512 mask = ~(((1ull << eax.split.num_counters_gp) - 1) | 7513 (((1ull << edx.split.num_counters_fixed) - 1) << 32)); 7514 7515 return !(val & mask); 7516 } 7517 7518 static void test_pgc_vmlaunch(u32 xerror, u32 xreason, bool xfail, bool host) 7519 { 7520 u32 inst_err; 7521 u64 obs; 7522 bool success; 7523 struct vmx_state_area_test_data *data = &vmx_state_area_test_data; 7524 7525 if (host) { 7526 success = vmlaunch_succeeds(); 7527 obs = rdmsr(data->msr); 7528 if (!success) { 7529 inst_err = vmcs_read(VMX_INST_ERROR); 7530 report(xerror == inst_err, "vmlaunch failed, " 7531 "VMX Inst Error is %d (expected %d)", 7532 inst_err, xerror); 7533 } else { 7534 report(!data->enabled || data->exp == obs, 7535 "Host state is 0x%lx (expected 0x%lx)", 7536 obs, data->exp); 7537 report(success != xfail, "vmlaunch succeeded"); 7538 } 7539 } else { 7540 test_guest_state("load GUEST_PERF_GLOBAL_CTRL", xfail, 7541 GUEST_PERF_GLOBAL_CTRL, 7542 "GUEST_PERF_GLOBAL_CTRL"); 7543 } 7544 } 7545 7546 /* 7547 * test_load_perf_global_ctrl is a generic function for testing the 7548 * "load IA32_PERF_GLOBAL_CTRL" VM-{Entry,Exit} controls. This test function 7549 * tests the provided ctrl_val when disabled and enabled. 7550 * 7551 * @nr: VMCS field number corresponding to the host/guest state field 7552 * @name: Name of the above VMCS field for printing in test report 7553 * @ctrl_nr: VMCS field number corresponding to the VM-{Entry,Exit} control 7554 * @ctrl_val: Bit to set on the ctrl_field 7555 */ 7556 static void test_perf_global_ctrl(u32 nr, const char *name, u32 ctrl_nr, 7557 const char *ctrl_name, u64 ctrl_val) 7558 { 7559 u64 ctrl_saved = vmcs_read(ctrl_nr); 7560 u64 pgc_saved = vmcs_read(nr); 7561 u64 i, val; 7562 bool host = nr == HOST_PERF_GLOBAL_CTRL; 7563 struct vmx_state_area_test_data *data = &vmx_state_area_test_data; 7564 7565 data->msr = MSR_CORE_PERF_GLOBAL_CTRL; 7566 msr_bmp_init(); 7567 vmcs_write(ctrl_nr, ctrl_saved & ~ctrl_val); 7568 data->enabled = false; 7569 report_prefix_pushf("\"load IA32_PERF_GLOBAL_CTRL\"=0 on %s", 7570 ctrl_name); 7571 7572 for (i = 0; i < 64; i++) { 7573 val = 1ull << i; 7574 vmcs_write(nr, val); 7575 report_prefix_pushf("%s = 0x%lx", name, val); 7576 test_pgc_vmlaunch(0, VMX_VMCALL, false, host); 7577 report_prefix_pop(); 7578 } 7579 report_prefix_pop(); 7580 7581 vmcs_write(ctrl_nr, ctrl_saved | ctrl_val); 7582 data->enabled = true; 7583 report_prefix_pushf("\"load IA32_PERF_GLOBAL_CTRL\"=1 on %s", 7584 ctrl_name); 7585 for (i = 0; i < 64; i++) { 7586 val = 1ull << i; 7587 data->exp = val; 7588 vmcs_write(nr, val); 7589 report_prefix_pushf("%s = 0x%lx", name, val); 7590 if (valid_pgc(val)) { 7591 test_pgc_vmlaunch(0, VMX_VMCALL, false, host); 7592 } else { 7593 if (host) 7594 test_pgc_vmlaunch( 7595 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, 7596 0, 7597 true, 7598 host); 7599 else 7600 test_pgc_vmlaunch( 7601 0, 7602 VMX_ENTRY_FAILURE | VMX_FAIL_STATE, 7603 true, 7604 host); 7605 } 7606 report_prefix_pop(); 7607 } 7608 7609 data->enabled = false; 7610 report_prefix_pop(); 7611 vmcs_write(ctrl_nr, ctrl_saved); 7612 vmcs_write(nr, pgc_saved); 7613 } 7614 7615 static void test_load_host_perf_global_ctrl(void) 7616 { 7617 if (!(ctrl_exit_rev.clr & EXI_LOAD_PERF)) { 7618 printf("\"load IA32_PERF_GLOBAL_CTRL\" exit control not supported\n"); 7619 return; 7620 } 7621 7622 test_perf_global_ctrl(HOST_PERF_GLOBAL_CTRL, "HOST_PERF_GLOBAL_CTRL", 7623 EXI_CONTROLS, "EXI_CONTROLS", EXI_LOAD_PERF); 7624 } 7625 7626 7627 static void test_load_guest_perf_global_ctrl(void) 7628 { 7629 if (!(ctrl_enter_rev.clr & ENT_LOAD_PERF)) { 7630 printf("\"load IA32_PERF_GLOBAL_CTRL\" entry control not supported\n"); 7631 return; 7632 } 7633 7634 test_perf_global_ctrl(GUEST_PERF_GLOBAL_CTRL, "GUEST_PERF_GLOBAL_CTRL", 7635 ENT_CONTROLS, "ENT_CONTROLS", ENT_LOAD_PERF); 7636 } 7637 7638 7639 /* 7640 * test_vmcs_field - test a value for the given VMCS field 7641 * @field: VMCS field 7642 * @field_name: string name of VMCS field 7643 * @bit_start: starting bit 7644 * @bit_end: ending bit 7645 * @val: value that the bit range must or must not contain 7646 * @valid_val: whether value given in 'val' must be valid or not 7647 * @error: expected VMCS error when vmentry fails for an invalid value 7648 */ 7649 static void test_vmcs_field(u64 field, const char *field_name, u32 bit_start, 7650 u32 bit_end, u64 val, bool valid_val, u32 error) 7651 { 7652 u64 field_saved = vmcs_read(field); 7653 u32 i; 7654 u64 tmp; 7655 u32 bit_on; 7656 u64 mask = ~0ull; 7657 7658 mask = (mask >> bit_end) << bit_end; 7659 mask = mask | ((1 << bit_start) - 1); 7660 tmp = (field_saved & mask) | (val << bit_start); 7661 7662 vmcs_write(field, tmp); 7663 report_prefix_pushf("%s %lx", field_name, tmp); 7664 if (valid_val) 7665 test_vmx_vmlaunch(0); 7666 else 7667 test_vmx_vmlaunch(error); 7668 report_prefix_pop(); 7669 7670 for (i = bit_start; i <= bit_end; i = i + 2) { 7671 bit_on = ((1ull < i) & (val << bit_start)) ? 0 : 1; 7672 if (bit_on) 7673 tmp = field_saved | (1ull << i); 7674 else 7675 tmp = field_saved & ~(1ull << i); 7676 vmcs_write(field, tmp); 7677 report_prefix_pushf("%s %lx", field_name, tmp); 7678 if (valid_val) 7679 test_vmx_vmlaunch(error); 7680 else 7681 test_vmx_vmlaunch(0); 7682 report_prefix_pop(); 7683 } 7684 7685 vmcs_write(field, field_saved); 7686 } 7687 7688 static void test_canonical(u64 field, const char * field_name, bool host) 7689 { 7690 u64 addr_saved = vmcs_read(field); 7691 7692 /* 7693 * Use the existing value if possible. Writing a random canonical 7694 * value is not an option as doing so would corrupt the field being 7695 * tested and likely hose the test. 7696 */ 7697 if (is_canonical(addr_saved)) { 7698 if (host) { 7699 report_prefix_pushf("%s %lx", field_name, addr_saved); 7700 test_vmx_vmlaunch(0); 7701 report_prefix_pop(); 7702 } else { 7703 test_guest_state("Test canonical address", false, 7704 addr_saved, field_name); 7705 } 7706 } 7707 7708 vmcs_write(field, NONCANONICAL); 7709 7710 if (host) { 7711 report_prefix_pushf("%s %llx", field_name, NONCANONICAL); 7712 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7713 report_prefix_pop(); 7714 } else { 7715 test_guest_state("Test non-canonical address", true, 7716 NONCANONICAL, field_name); 7717 } 7718 7719 vmcs_write(field, addr_saved); 7720 } 7721 7722 #define TEST_RPL_TI_FLAGS(reg, name) \ 7723 test_vmcs_field(reg, name, 0, 2, 0x0, true, \ 7724 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7725 7726 #define TEST_CS_TR_FLAGS(reg, name) \ 7727 test_vmcs_field(reg, name, 3, 15, 0x0000, false, \ 7728 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7729 7730 /* 7731 * 1. In the selector field for each of CS, SS, DS, ES, FS, GS and TR, the 7732 * RPL (bits 1:0) and the TI flag (bit 2) must be 0. 7733 * 2. The selector fields for CS and TR cannot be 0000H. 7734 * 3. The selector field for SS cannot be 0000H if the "host address-space 7735 * size" VM-exit control is 0. 7736 * 4. On processors that support Intel 64 architecture, the base-address 7737 * fields for FS, GS and TR must contain canonical addresses. 7738 */ 7739 static void test_host_segment_regs(void) 7740 { 7741 u16 selector_saved; 7742 7743 /* 7744 * Test RPL and TI flags 7745 */ 7746 TEST_RPL_TI_FLAGS(HOST_SEL_CS, "HOST_SEL_CS"); 7747 TEST_RPL_TI_FLAGS(HOST_SEL_SS, "HOST_SEL_SS"); 7748 TEST_RPL_TI_FLAGS(HOST_SEL_DS, "HOST_SEL_DS"); 7749 TEST_RPL_TI_FLAGS(HOST_SEL_ES, "HOST_SEL_ES"); 7750 TEST_RPL_TI_FLAGS(HOST_SEL_FS, "HOST_SEL_FS"); 7751 TEST_RPL_TI_FLAGS(HOST_SEL_GS, "HOST_SEL_GS"); 7752 TEST_RPL_TI_FLAGS(HOST_SEL_TR, "HOST_SEL_TR"); 7753 7754 /* 7755 * Test that CS and TR fields can not be 0x0000 7756 */ 7757 TEST_CS_TR_FLAGS(HOST_SEL_CS, "HOST_SEL_CS"); 7758 TEST_CS_TR_FLAGS(HOST_SEL_TR, "HOST_SEL_TR"); 7759 7760 /* 7761 * SS field can not be 0x0000 if "host address-space size" VM-exit 7762 * control is 0 7763 */ 7764 selector_saved = vmcs_read(HOST_SEL_SS); 7765 vmcs_write(HOST_SEL_SS, 0); 7766 report_prefix_pushf("HOST_SEL_SS 0"); 7767 if (vmcs_read(EXI_CONTROLS) & EXI_HOST_64) { 7768 test_vmx_vmlaunch(0); 7769 } else { 7770 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7771 } 7772 report_prefix_pop(); 7773 7774 vmcs_write(HOST_SEL_SS, selector_saved); 7775 7776 /* 7777 * Base address for FS, GS and TR must be canonical 7778 */ 7779 test_canonical(HOST_BASE_FS, "HOST_BASE_FS", true); 7780 test_canonical(HOST_BASE_GS, "HOST_BASE_GS", true); 7781 test_canonical(HOST_BASE_TR, "HOST_BASE_TR", true); 7782 } 7783 7784 /* 7785 * On processors that support Intel 64 architecture, the base-address 7786 * fields for GDTR and IDTR must contain canonical addresses. 7787 */ 7788 static void test_host_desc_tables(void) 7789 { 7790 test_canonical(HOST_BASE_GDTR, "HOST_BASE_GDTR", true); 7791 test_canonical(HOST_BASE_IDTR, "HOST_BASE_IDTR", true); 7792 } 7793 7794 /* 7795 * If the "host address-space size" VM-exit control is 0, the following must 7796 * hold: 7797 * - The "IA-32e mode guest" VM-entry control is 0. 7798 * - Bit 17 of the CR4 field (corresponding to CR4.PCIDE) is 0. 7799 * - Bits 63:32 in the RIP field are 0. 7800 * 7801 * If the "host address-space size" VM-exit control is 1, the following must 7802 * hold: 7803 * - Bit 5 of the CR4 field (corresponding to CR4.PAE) is 1. 7804 * - The RIP field contains a canonical address. 7805 * 7806 */ 7807 static void test_host_addr_size(void) 7808 { 7809 u64 cr4_saved = vmcs_read(HOST_CR4); 7810 u64 rip_saved = vmcs_read(HOST_RIP); 7811 u64 entry_ctrl_saved = vmcs_read(ENT_CONTROLS); 7812 int i; 7813 u64 tmp; 7814 7815 if (vmcs_read(EXI_CONTROLS) & EXI_HOST_64) { 7816 vmcs_write(ENT_CONTROLS, entry_ctrl_saved | ENT_GUEST_64); 7817 report_prefix_pushf("\"IA-32e mode guest\" enabled"); 7818 test_vmx_vmlaunch(0); 7819 report_prefix_pop(); 7820 7821 vmcs_write(HOST_CR4, cr4_saved | X86_CR4_PCIDE); 7822 report_prefix_pushf("\"CR4.PCIDE\" set"); 7823 test_vmx_vmlaunch(0); 7824 report_prefix_pop(); 7825 7826 for (i = 32; i <= 63; i = i + 4) { 7827 tmp = rip_saved | 1ull << i; 7828 vmcs_write(HOST_RIP, tmp); 7829 report_prefix_pushf("HOST_RIP %lx", tmp); 7830 test_vmx_vmlaunch(0); 7831 report_prefix_pop(); 7832 } 7833 7834 if (cr4_saved & X86_CR4_PAE) { 7835 vmcs_write(HOST_CR4, cr4_saved & ~X86_CR4_PAE); 7836 report_prefix_pushf("\"CR4.PAE\" unset"); 7837 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7838 } else { 7839 report_prefix_pushf("\"CR4.PAE\" set"); 7840 test_vmx_vmlaunch(0); 7841 } 7842 report_prefix_pop(); 7843 7844 vmcs_write(HOST_RIP, NONCANONICAL); 7845 report_prefix_pushf("HOST_RIP %llx", NONCANONICAL); 7846 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7847 report_prefix_pop(); 7848 7849 vmcs_write(ENT_CONTROLS, entry_ctrl_saved | ENT_GUEST_64); 7850 vmcs_write(HOST_RIP, rip_saved); 7851 vmcs_write(HOST_CR4, cr4_saved); 7852 7853 /* Restore host's active RIP and CR4 values. */ 7854 report_prefix_pushf("restore host state"); 7855 test_vmx_vmlaunch(0); 7856 report_prefix_pop(); 7857 } 7858 } 7859 7860 /* 7861 * Check that the virtual CPU checks the VMX Host State Area as 7862 * documented in the Intel SDM. 7863 */ 7864 static void vmx_host_state_area_test(void) 7865 { 7866 /* 7867 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 7868 * fail due to invalid guest state, should we make it that 7869 * far. 7870 */ 7871 vmcs_write(GUEST_RFLAGS, 0); 7872 7873 test_host_ctl_regs(); 7874 7875 test_canonical(HOST_SYSENTER_ESP, "HOST_SYSENTER_ESP", true); 7876 test_canonical(HOST_SYSENTER_EIP, "HOST_SYSENTER_EIP", true); 7877 7878 test_host_efer(); 7879 test_load_host_pat(); 7880 test_host_segment_regs(); 7881 test_host_desc_tables(); 7882 test_host_addr_size(); 7883 test_load_host_perf_global_ctrl(); 7884 } 7885 7886 /* 7887 * If the "load debug controls" VM-entry control is 1, bits 63:32 in 7888 * the DR7 field must be 0. 7889 * 7890 * [Intel SDM] 7891 */ 7892 static void test_guest_dr7(void) 7893 { 7894 u32 ent_saved = vmcs_read(ENT_CONTROLS); 7895 u64 dr7_saved = vmcs_read(GUEST_DR7); 7896 u64 val; 7897 int i; 7898 7899 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS) { 7900 vmcs_clear_bits(ENT_CONTROLS, ENT_LOAD_DBGCTLS); 7901 for (i = 0; i < 64; i++) { 7902 val = 1ull << i; 7903 vmcs_write(GUEST_DR7, val); 7904 test_guest_state("ENT_LOAD_DBGCTLS disabled", false, 7905 val, "GUEST_DR7"); 7906 } 7907 } 7908 if (ctrl_enter_rev.clr & ENT_LOAD_DBGCTLS) { 7909 vmcs_set_bits(ENT_CONTROLS, ENT_LOAD_DBGCTLS); 7910 for (i = 0; i < 64; i++) { 7911 val = 1ull << i; 7912 vmcs_write(GUEST_DR7, val); 7913 test_guest_state("ENT_LOAD_DBGCTLS enabled", i >= 32, 7914 val, "GUEST_DR7"); 7915 } 7916 } 7917 vmcs_write(GUEST_DR7, dr7_saved); 7918 vmcs_write(ENT_CONTROLS, ent_saved); 7919 } 7920 7921 /* 7922 * If the "load IA32_PAT" VM-entry control is 1, the value of the field 7923 * for the IA32_PAT MSR must be one that could be written by WRMSR 7924 * without fault at CPL 0. Specifically, each of the 8 bytes in the 7925 * field must have one of the values 0 (UC), 1 (WC), 4 (WT), 5 (WP), 7926 * 6 (WB), or 7 (UC-). 7927 * 7928 * [Intel SDM] 7929 */ 7930 static void test_load_guest_pat(void) 7931 { 7932 /* 7933 * "load IA32_PAT" VM-entry control 7934 */ 7935 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 7936 printf("\"Load-IA32-PAT\" entry control not supported\n"); 7937 return; 7938 } 7939 7940 test_pat(GUEST_PAT, "GUEST_PAT", ENT_CONTROLS, ENT_LOAD_PAT); 7941 } 7942 7943 #define MSR_IA32_BNDCFGS_RSVD_MASK 0x00000ffc 7944 7945 /* 7946 * If the "load IA32_BNDCFGS" VM-entry control is 1, the following 7947 * checks are performed on the field for the IA32_BNDCFGS MSR: 7948 * 7949 * - Bits reserved in the IA32_BNDCFGS MSR must be 0. 7950 * - The linear address in bits 63:12 must be canonical. 7951 * 7952 * [Intel SDM] 7953 */ 7954 static void test_load_guest_bndcfgs(void) 7955 { 7956 u64 bndcfgs_saved = vmcs_read(GUEST_BNDCFGS); 7957 u64 bndcfgs; 7958 7959 if (!(ctrl_enter_rev.clr & ENT_LOAD_BNDCFGS)) { 7960 printf("\"Load-IA32-BNDCFGS\" entry control not supported\n"); 7961 return; 7962 } 7963 7964 vmcs_clear_bits(ENT_CONTROLS, ENT_LOAD_BNDCFGS); 7965 7966 vmcs_write(GUEST_BNDCFGS, NONCANONICAL); 7967 test_guest_state("ENT_LOAD_BNDCFGS disabled", false, 7968 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7969 bndcfgs = bndcfgs_saved | MSR_IA32_BNDCFGS_RSVD_MASK; 7970 vmcs_write(GUEST_BNDCFGS, bndcfgs); 7971 test_guest_state("ENT_LOAD_BNDCFGS disabled", false, 7972 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7973 7974 vmcs_set_bits(ENT_CONTROLS, ENT_LOAD_BNDCFGS); 7975 7976 vmcs_write(GUEST_BNDCFGS, NONCANONICAL); 7977 test_guest_state("ENT_LOAD_BNDCFGS enabled", true, 7978 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7979 bndcfgs = bndcfgs_saved | MSR_IA32_BNDCFGS_RSVD_MASK; 7980 vmcs_write(GUEST_BNDCFGS, bndcfgs); 7981 test_guest_state("ENT_LOAD_BNDCFGS enabled", true, 7982 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7983 7984 vmcs_write(GUEST_BNDCFGS, bndcfgs_saved); 7985 } 7986 7987 #define GUEST_SEG_UNUSABLE_MASK (1u << 16) 7988 #define GUEST_SEG_SEL_TI_MASK (1u << 2) 7989 7990 7991 #define TEST_SEGMENT_SEL(test, xfail, sel, val) \ 7992 do { \ 7993 vmcs_write(sel, val); \ 7994 test_guest_state(test " segment", xfail, val, xstr(sel)); \ 7995 } while (0) 7996 7997 #define TEST_INVALID_SEG_SEL(sel, val) \ 7998 TEST_SEGMENT_SEL("Invalid: " xstr(val), true, sel, val); 7999 8000 #define TEST_VALID_SEG_SEL(sel, val) \ 8001 TEST_SEGMENT_SEL("Valid: " xstr(val), false, sel, val); 8002 8003 /* 8004 * The following checks are done on the Selector field of the Guest Segment 8005 * Registers: 8006 * - TR. The TI flag (bit 2) must be 0. 8007 * - LDTR. If LDTR is usable, the TI flag (bit 2) must be 0. 8008 * - SS. If the guest will not be virtual-8086 and the "unrestricted 8009 * guest" VM-execution control is 0, the RPL (bits 1:0) must equal 8010 * the RPL of the selector field for CS. 8011 * 8012 * [Intel SDM] 8013 */ 8014 static void test_guest_segment_sel_fields(void) 8015 { 8016 u16 sel_saved; 8017 u32 ar_saved; 8018 u32 cpu_ctrl0_saved; 8019 u32 cpu_ctrl1_saved; 8020 u16 cs_rpl_bits; 8021 8022 /* 8023 * Test for GUEST_SEL_TR 8024 */ 8025 sel_saved = vmcs_read(GUEST_SEL_TR); 8026 TEST_INVALID_SEG_SEL(GUEST_SEL_TR, sel_saved | GUEST_SEG_SEL_TI_MASK); 8027 vmcs_write(GUEST_SEL_TR, sel_saved); 8028 8029 /* 8030 * Test for GUEST_SEL_LDTR 8031 */ 8032 sel_saved = vmcs_read(GUEST_SEL_LDTR); 8033 ar_saved = vmcs_read(GUEST_AR_LDTR); 8034 /* LDTR is set unusable */ 8035 vmcs_write(GUEST_AR_LDTR, ar_saved | GUEST_SEG_UNUSABLE_MASK); 8036 TEST_VALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved | GUEST_SEG_SEL_TI_MASK); 8037 TEST_VALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved & ~GUEST_SEG_SEL_TI_MASK); 8038 /* LDTR is set usable */ 8039 vmcs_write(GUEST_AR_LDTR, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 8040 TEST_INVALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved | GUEST_SEG_SEL_TI_MASK); 8041 8042 TEST_VALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved & ~GUEST_SEG_SEL_TI_MASK); 8043 8044 vmcs_write(GUEST_AR_LDTR, ar_saved); 8045 vmcs_write(GUEST_SEL_LDTR, sel_saved); 8046 8047 /* 8048 * Test for GUEST_SEL_SS 8049 */ 8050 cpu_ctrl0_saved = vmcs_read(CPU_EXEC_CTRL0); 8051 cpu_ctrl1_saved = vmcs_read(CPU_EXEC_CTRL1); 8052 ar_saved = vmcs_read(GUEST_AR_SS); 8053 /* Turn off "unrestricted guest" vm-execution control */ 8054 vmcs_write(CPU_EXEC_CTRL1, cpu_ctrl1_saved & ~CPU_URG); 8055 cs_rpl_bits = vmcs_read(GUEST_SEL_CS) & 0x3; 8056 sel_saved = vmcs_read(GUEST_SEL_SS); 8057 TEST_INVALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 8058 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 8059 /* Make SS usable if it's unusable or vice-versa */ 8060 if (ar_saved & GUEST_SEG_UNUSABLE_MASK) 8061 vmcs_write(GUEST_AR_SS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 8062 else 8063 vmcs_write(GUEST_AR_SS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 8064 TEST_INVALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 8065 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 8066 8067 /* Need a valid EPTP as the passing case fully enters the guest. */ 8068 if (enable_unrestricted_guest(true)) 8069 goto skip_ss_tests; 8070 8071 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 8072 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 8073 8074 /* Make SS usable if it's unusable or vice-versa */ 8075 if (vmcs_read(GUEST_AR_SS) & GUEST_SEG_UNUSABLE_MASK) 8076 vmcs_write(GUEST_AR_SS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 8077 else 8078 vmcs_write(GUEST_AR_SS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 8079 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 8080 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 8081 skip_ss_tests: 8082 8083 vmcs_write(GUEST_AR_SS, ar_saved); 8084 vmcs_write(GUEST_SEL_SS, sel_saved); 8085 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrl0_saved); 8086 vmcs_write(CPU_EXEC_CTRL1, cpu_ctrl1_saved); 8087 } 8088 8089 #define TEST_SEGMENT_BASE_ADDR_UPPER_BITS(xfail, seg_base) \ 8090 do { \ 8091 addr_saved = vmcs_read(seg_base); \ 8092 for (i = 32; i < 63; i = i + 4) { \ 8093 addr = addr_saved | 1ull << i; \ 8094 vmcs_write(seg_base, addr); \ 8095 test_guest_state("seg.BASE[63:32] != 0, usable = " xstr(xfail), \ 8096 xfail, addr, xstr(seg_base)); \ 8097 } \ 8098 vmcs_write(seg_base, addr_saved); \ 8099 } while (0) 8100 8101 #define TEST_SEGMENT_BASE_ADDR_CANONICAL(xfail, seg_base) \ 8102 do { \ 8103 addr_saved = vmcs_read(seg_base); \ 8104 vmcs_write(seg_base, NONCANONICAL); \ 8105 test_guest_state("seg.BASE non-canonical, usable = " xstr(xfail), \ 8106 xfail, NONCANONICAL, xstr(seg_base)); \ 8107 vmcs_write(seg_base, addr_saved); \ 8108 } while (0) 8109 8110 /* 8111 * The following checks are done on the Base Address field of the Guest 8112 * Segment Registers on processors that support Intel 64 architecture: 8113 * - TR, FS, GS : The address must be canonical. 8114 * - LDTR : If LDTR is usable, the address must be canonical. 8115 * - CS : Bits 63:32 of the address must be zero. 8116 * - SS, DS, ES : If the register is usable, bits 63:32 of the address 8117 * must be zero. 8118 * 8119 * [Intel SDM] 8120 */ 8121 static void test_guest_segment_base_addr_fields(void) 8122 { 8123 u64 addr_saved; 8124 u64 addr; 8125 u32 ar_saved; 8126 int i; 8127 8128 /* 8129 * The address of TR, FS, GS and LDTR must be canonical. 8130 */ 8131 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_TR); 8132 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_FS); 8133 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_GS); 8134 ar_saved = vmcs_read(GUEST_AR_LDTR); 8135 /* Make LDTR unusable */ 8136 vmcs_write(GUEST_AR_LDTR, ar_saved | GUEST_SEG_UNUSABLE_MASK); 8137 TEST_SEGMENT_BASE_ADDR_CANONICAL(false, GUEST_BASE_LDTR); 8138 /* Make LDTR usable */ 8139 vmcs_write(GUEST_AR_LDTR, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 8140 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_LDTR); 8141 8142 vmcs_write(GUEST_AR_LDTR, ar_saved); 8143 8144 /* 8145 * Bits 63:32 in CS, SS, DS and ES base address must be zero 8146 */ 8147 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_CS); 8148 ar_saved = vmcs_read(GUEST_AR_SS); 8149 /* Make SS unusable */ 8150 vmcs_write(GUEST_AR_SS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 8151 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(false, GUEST_BASE_SS); 8152 /* Make SS usable */ 8153 vmcs_write(GUEST_AR_SS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 8154 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_SS); 8155 vmcs_write(GUEST_AR_SS, ar_saved); 8156 8157 ar_saved = vmcs_read(GUEST_AR_DS); 8158 /* Make DS unusable */ 8159 vmcs_write(GUEST_AR_DS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 8160 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(false, GUEST_BASE_DS); 8161 /* Make DS usable */ 8162 vmcs_write(GUEST_AR_DS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 8163 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_DS); 8164 vmcs_write(GUEST_AR_DS, ar_saved); 8165 8166 ar_saved = vmcs_read(GUEST_AR_ES); 8167 /* Make ES unusable */ 8168 vmcs_write(GUEST_AR_ES, ar_saved | GUEST_SEG_UNUSABLE_MASK); 8169 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(false, GUEST_BASE_ES); 8170 /* Make ES usable */ 8171 vmcs_write(GUEST_AR_ES, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 8172 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_ES); 8173 vmcs_write(GUEST_AR_ES, ar_saved); 8174 } 8175 8176 /* 8177 * Check that the virtual CPU checks the VMX Guest State Area as 8178 * documented in the Intel SDM. 8179 */ 8180 static void vmx_guest_state_area_test(void) 8181 { 8182 vmx_set_test_stage(1); 8183 test_set_guest(guest_state_test_main); 8184 8185 /* 8186 * The IA32_SYSENTER_ESP field and the IA32_SYSENTER_EIP field 8187 * must each contain a canonical address. 8188 */ 8189 test_canonical(GUEST_SYSENTER_ESP, "GUEST_SYSENTER_ESP", false); 8190 test_canonical(GUEST_SYSENTER_EIP, "GUEST_SYSENTER_EIP", false); 8191 8192 test_guest_dr7(); 8193 test_load_guest_pat(); 8194 test_guest_efer(); 8195 test_load_guest_perf_global_ctrl(); 8196 test_load_guest_bndcfgs(); 8197 8198 test_guest_segment_sel_fields(); 8199 test_guest_segment_base_addr_fields(); 8200 8201 test_canonical(GUEST_BASE_GDTR, "GUEST_BASE_GDTR", false); 8202 test_canonical(GUEST_BASE_IDTR, "GUEST_BASE_IDTR", false); 8203 8204 u32 guest_desc_limit_saved = vmcs_read(GUEST_LIMIT_GDTR); 8205 int i; 8206 for (i = 16; i <= 31; i++) { 8207 u32 tmp = guest_desc_limit_saved | (1ull << i); 8208 vmcs_write(GUEST_LIMIT_GDTR, tmp); 8209 test_guest_state("GDT.limit > 0xffff", true, tmp, "GUEST_LIMIT_GDTR"); 8210 } 8211 vmcs_write(GUEST_LIMIT_GDTR, guest_desc_limit_saved); 8212 8213 guest_desc_limit_saved = vmcs_read(GUEST_LIMIT_IDTR); 8214 for (i = 16; i <= 31; i++) { 8215 u32 tmp = guest_desc_limit_saved | (1ull << i); 8216 vmcs_write(GUEST_LIMIT_IDTR, tmp); 8217 test_guest_state("IDT.limit > 0xffff", true, tmp, "GUEST_LIMIT_IDTR"); 8218 } 8219 vmcs_write(GUEST_LIMIT_IDTR, guest_desc_limit_saved); 8220 8221 /* 8222 * Let the guest finish execution 8223 */ 8224 vmx_set_test_stage(2); 8225 enter_guest(); 8226 } 8227 8228 extern void unrestricted_guest_main(void); 8229 asm (".code32\n" 8230 "unrestricted_guest_main:\n" 8231 "vmcall\n" 8232 "nop\n" 8233 "mov $1, %edi\n" 8234 "call hypercall\n" 8235 ".code64\n"); 8236 8237 static void setup_unrestricted_guest(void) 8238 { 8239 vmcs_write(GUEST_CR0, vmcs_read(GUEST_CR0) & ~(X86_CR0_PG)); 8240 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) & ~ENT_GUEST_64); 8241 vmcs_write(GUEST_EFER, vmcs_read(GUEST_EFER) & ~EFER_LMA); 8242 vmcs_write(GUEST_RIP, virt_to_phys(unrestricted_guest_main)); 8243 } 8244 8245 static void unsetup_unrestricted_guest(void) 8246 { 8247 vmcs_write(GUEST_CR0, vmcs_read(GUEST_CR0) | X86_CR0_PG); 8248 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) | ENT_GUEST_64); 8249 vmcs_write(GUEST_EFER, vmcs_read(GUEST_EFER) | EFER_LMA); 8250 vmcs_write(GUEST_RIP, (u64) phys_to_virt(vmcs_read(GUEST_RIP))); 8251 vmcs_write(GUEST_RSP, (u64) phys_to_virt(vmcs_read(GUEST_RSP))); 8252 } 8253 8254 /* 8255 * If "unrestricted guest" secondary VM-execution control is set, guests 8256 * can run in unpaged protected mode. 8257 */ 8258 static void vmentry_unrestricted_guest_test(void) 8259 { 8260 if (enable_unrestricted_guest(true)) { 8261 report_skip("Unrestricted guest not supported"); 8262 return; 8263 } 8264 8265 test_set_guest(unrestricted_guest_main); 8266 setup_unrestricted_guest(); 8267 test_guest_state("Unrestricted guest test", false, CPU_URG, "CPU_URG"); 8268 8269 /* 8270 * Let the guest finish execution as a regular guest 8271 */ 8272 unsetup_unrestricted_guest(); 8273 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) & ~CPU_URG); 8274 enter_guest(); 8275 } 8276 8277 static bool valid_vmcs_for_vmentry(void) 8278 { 8279 struct vmcs *current_vmcs = NULL; 8280 8281 if (vmcs_save(¤t_vmcs)) 8282 return false; 8283 8284 return current_vmcs && !current_vmcs->hdr.shadow_vmcs; 8285 } 8286 8287 static void try_vmentry_in_movss_shadow(void) 8288 { 8289 u32 vm_inst_err; 8290 u32 flags; 8291 bool early_failure = false; 8292 u32 expected_flags = X86_EFLAGS_FIXED; 8293 bool valid_vmcs = valid_vmcs_for_vmentry(); 8294 8295 expected_flags |= valid_vmcs ? X86_EFLAGS_ZF : X86_EFLAGS_CF; 8296 8297 /* 8298 * Indirectly set VM_INST_ERR to 12 ("VMREAD/VMWRITE from/to 8299 * unsupported VMCS component"). 8300 */ 8301 vmcs_write(~0u, 0); 8302 8303 __asm__ __volatile__ ("mov %[host_rsp], %%edx;" 8304 "vmwrite %%rsp, %%rdx;" 8305 "mov 0f, %%rax;" 8306 "mov %[host_rip], %%edx;" 8307 "vmwrite %%rax, %%rdx;" 8308 "mov $-1, %%ah;" 8309 "sahf;" 8310 "mov %%ss, %%ax;" 8311 "mov %%ax, %%ss;" 8312 "vmlaunch;" 8313 "mov $1, %[early_failure];" 8314 "0: lahf;" 8315 "movzbl %%ah, %[flags]" 8316 : [early_failure] "+r" (early_failure), 8317 [flags] "=&a" (flags) 8318 : [host_rsp] "i" (HOST_RSP), 8319 [host_rip] "i" (HOST_RIP) 8320 : "rdx", "cc", "memory"); 8321 vm_inst_err = vmcs_read(VMX_INST_ERROR); 8322 8323 report(early_failure, "Early VM-entry failure"); 8324 report(flags == expected_flags, "RFLAGS[8:0] is %x (actual %x)", 8325 expected_flags, flags); 8326 if (valid_vmcs) 8327 report(vm_inst_err == VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, 8328 "VM-instruction error is %d (actual %d)", 8329 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, vm_inst_err); 8330 } 8331 8332 static void vmentry_movss_shadow_test(void) 8333 { 8334 struct vmcs *orig_vmcs; 8335 8336 TEST_ASSERT(!vmcs_save(&orig_vmcs)); 8337 8338 /* 8339 * Set the launched flag on the current VMCS to verify the correct 8340 * error priority, below. 8341 */ 8342 test_set_guest(v2_null_test_guest); 8343 enter_guest(); 8344 8345 /* 8346 * With bit 1 of the guest's RFLAGS clear, VM-entry should 8347 * fail due to invalid guest state (if we make it that far). 8348 */ 8349 vmcs_write(GUEST_RFLAGS, 0); 8350 8351 /* 8352 * "VM entry with events blocked by MOV SS" takes precedence over 8353 * "VMLAUNCH with non-clear VMCS." 8354 */ 8355 report_prefix_push("valid current-VMCS"); 8356 try_vmentry_in_movss_shadow(); 8357 report_prefix_pop(); 8358 8359 /* 8360 * VMfailInvalid takes precedence over "VM entry with events 8361 * blocked by MOV SS." 8362 */ 8363 TEST_ASSERT(!vmcs_clear(orig_vmcs)); 8364 report_prefix_push("no current-VMCS"); 8365 try_vmentry_in_movss_shadow(); 8366 report_prefix_pop(); 8367 8368 TEST_ASSERT(!make_vmcs_current(orig_vmcs)); 8369 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 8370 } 8371 8372 static void vmx_ldtr_test_guest(void) 8373 { 8374 u16 ldtr = sldt(); 8375 8376 report(ldtr == NP_SEL, "Expected %x for L2 LDTR selector (got %x)", 8377 NP_SEL, ldtr); 8378 } 8379 8380 /* 8381 * Ensure that the L1 LDTR is set to 0 on VM-exit. 8382 */ 8383 static void vmx_ldtr_test(void) 8384 { 8385 const u8 ldt_ar = 0x82; /* Present LDT */ 8386 u16 sel = FIRST_SPARE_SEL; 8387 8388 /* Set up a non-zero L1 LDTR prior to VM-entry. */ 8389 set_gdt_entry(sel, 0, 0, ldt_ar, 0); 8390 lldt(sel); 8391 8392 test_set_guest(vmx_ldtr_test_guest); 8393 /* 8394 * Set up a different LDTR for L2. The actual GDT contents are 8395 * irrelevant, since we stuff the hidden descriptor state 8396 * straight into the VMCS rather than reading it from the GDT. 8397 */ 8398 vmcs_write(GUEST_SEL_LDTR, NP_SEL); 8399 vmcs_write(GUEST_AR_LDTR, ldt_ar); 8400 enter_guest(); 8401 8402 /* 8403 * VM-exit should clear LDTR (and make it unusable, but we 8404 * won't verify that here). 8405 */ 8406 sel = sldt(); 8407 report(!sel, "Expected 0 for L1 LDTR selector (got %x)", sel); 8408 } 8409 8410 static void vmx_single_vmcall_guest(void) 8411 { 8412 vmcall(); 8413 } 8414 8415 static void vmx_cr_load_test(void) 8416 { 8417 unsigned long cr3, cr4, orig_cr3, orig_cr4; 8418 u32 ctrls[2] = {0}; 8419 pgd_t *pml5; 8420 8421 orig_cr4 = read_cr4(); 8422 orig_cr3 = read_cr3(); 8423 8424 if (!this_cpu_has(X86_FEATURE_PCID)) { 8425 report_skip("PCID not detected"); 8426 return; 8427 } 8428 if (!this_cpu_has(X86_FEATURE_MCE)) { 8429 report_skip("MCE not detected"); 8430 return; 8431 } 8432 8433 TEST_ASSERT(!(orig_cr3 & X86_CR3_PCID_MASK)); 8434 8435 /* Enable PCID for L1. */ 8436 cr4 = orig_cr4 | X86_CR4_PCIDE; 8437 cr3 = orig_cr3 | 0x1; 8438 TEST_ASSERT(!write_cr4_checking(cr4)); 8439 write_cr3(cr3); 8440 8441 test_set_guest(vmx_single_vmcall_guest); 8442 vmcs_write(HOST_CR4, cr4); 8443 vmcs_write(HOST_CR3, cr3); 8444 enter_guest(); 8445 8446 /* 8447 * No exception is expected. 8448 * 8449 * NB. KVM loads the last guest write to CR4 into CR4 read 8450 * shadow. In order to trigger an exit to KVM, we can toggle a 8451 * bit that is owned by KVM. We use CR4.MCE, which shall 8452 * have no side effect because normally no guest MCE (e.g., as the 8453 * result of bad memory) would happen during this test. 8454 */ 8455 TEST_ASSERT(!write_cr4_checking(cr4 ^ X86_CR4_MCE)); 8456 8457 /* Cleanup L1 state. */ 8458 write_cr3(orig_cr3); 8459 TEST_ASSERT(!write_cr4_checking(orig_cr4)); 8460 8461 if (!this_cpu_has(X86_FEATURE_LA57)) 8462 goto done; 8463 8464 /* 8465 * Allocate a full page for PML5 to guarantee alignment, though only 8466 * the first entry needs to be filled (the test's virtual addresses 8467 * most definitely do not have any of bits 56:48 set). 8468 */ 8469 pml5 = alloc_page(); 8470 *pml5 = orig_cr3 | PT_PRESENT_MASK | PT_WRITABLE_MASK; 8471 8472 /* 8473 * Transition to/from 5-level paging in the host via VM-Exit. CR4.LA57 8474 * can't be toggled while long is active via MOV CR4, but there are no 8475 * such restrictions on VM-Exit. 8476 */ 8477 lol_5level: 8478 vmcs_write(HOST_CR4, orig_cr4 | X86_CR4_LA57); 8479 vmcs_write(HOST_CR3, virt_to_phys(pml5)); 8480 enter_guest(); 8481 8482 /* 8483 * VMREAD with a memory operand to verify KVM detects the LA57 change, 8484 * e.g. uses the correct guest root level in gva_to_gpa(). 8485 */ 8486 TEST_ASSERT(vmcs_readm(HOST_CR3) == virt_to_phys(pml5)); 8487 TEST_ASSERT(vmcs_readm(HOST_CR4) == (orig_cr4 | X86_CR4_LA57)); 8488 8489 vmcs_write(HOST_CR4, orig_cr4); 8490 vmcs_write(HOST_CR3, orig_cr3); 8491 enter_guest(); 8492 8493 TEST_ASSERT(vmcs_readm(HOST_CR3) == orig_cr3); 8494 TEST_ASSERT(vmcs_readm(HOST_CR4) == orig_cr4); 8495 8496 /* 8497 * And now do the same LA57 shenanigans with EPT enabled. KVM uses 8498 * two separate MMUs when L1 uses TDP, whereas the above shadow paging 8499 * version shares an MMU between L1 and L2. 8500 * 8501 * If the saved execution controls are non-zero then the EPT version 8502 * has already run. In that case, restore the old controls. If EPT 8503 * setup fails, e.g. EPT isn't supported, fall through and finish up. 8504 */ 8505 if (ctrls[0]) { 8506 vmcs_write(CPU_EXEC_CTRL0, ctrls[0]); 8507 vmcs_write(CPU_EXEC_CTRL1, ctrls[1]); 8508 } else if (!setup_ept(false)) { 8509 ctrls[0] = vmcs_read(CPU_EXEC_CTRL0); 8510 ctrls[1] = vmcs_read(CPU_EXEC_CTRL1); 8511 goto lol_5level; 8512 } 8513 8514 free_page(pml5); 8515 8516 done: 8517 skip_exit_vmcall(); 8518 enter_guest(); 8519 } 8520 8521 static void vmx_cr4_osxsave_test_guest(void) 8522 { 8523 write_cr4(read_cr4() & ~X86_CR4_OSXSAVE); 8524 } 8525 8526 /* 8527 * Ensure that kvm recalculates the L1 guest's CPUID.01H:ECX.OSXSAVE 8528 * after VM-exit from an L2 guest that sets CR4.OSXSAVE to a different 8529 * value than in L1. 8530 */ 8531 static void vmx_cr4_osxsave_test(void) 8532 { 8533 if (!this_cpu_has(X86_FEATURE_XSAVE)) { 8534 report_skip("XSAVE not detected"); 8535 return; 8536 } 8537 8538 if (!(read_cr4() & X86_CR4_OSXSAVE)) { 8539 unsigned long cr4 = read_cr4() | X86_CR4_OSXSAVE; 8540 8541 write_cr4(cr4); 8542 vmcs_write(GUEST_CR4, cr4); 8543 vmcs_write(HOST_CR4, cr4); 8544 } 8545 8546 TEST_ASSERT(cpuid_osxsave()); 8547 8548 test_set_guest(vmx_cr4_osxsave_test_guest); 8549 enter_guest(); 8550 8551 TEST_ASSERT(cpuid_osxsave()); 8552 } 8553 8554 static void vmx_nm_test_guest(void) 8555 { 8556 write_cr0(read_cr0() | X86_CR0_TS); 8557 asm volatile("fnop"); 8558 } 8559 8560 static void check_nm_exit(const char *test) 8561 { 8562 u32 reason = vmcs_read(EXI_REASON); 8563 u32 intr_info = vmcs_read(EXI_INTR_INFO); 8564 const u32 expected = INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 8565 NM_VECTOR; 8566 8567 report(reason == VMX_EXC_NMI && intr_info == expected, "%s", test); 8568 } 8569 8570 /* 8571 * This test checks that: 8572 * 8573 * (a) If L2 launches with CR0.TS clear, but later sets CR0.TS, then 8574 * a subsequent #NM VM-exit is reflected to L1. 8575 * 8576 * (b) If L2 launches with CR0.TS clear and CR0.EM set, then a 8577 * subsequent #NM VM-exit is reflected to L1. 8578 */ 8579 static void vmx_nm_test(void) 8580 { 8581 unsigned long cr0 = read_cr0(); 8582 8583 test_set_guest(vmx_nm_test_guest); 8584 8585 /* 8586 * L1 wants to intercept #NM exceptions encountered in L2. 8587 */ 8588 vmcs_write(EXC_BITMAP, 1 << NM_VECTOR); 8589 8590 /* 8591 * Launch L2 with CR0.TS clear, but don't claim host ownership of 8592 * any CR0 bits. L2 will set CR0.TS and then try to execute fnop, 8593 * which will raise #NM. L0 should reflect the #NM VM-exit to L1. 8594 */ 8595 vmcs_write(CR0_MASK, 0); 8596 vmcs_write(GUEST_CR0, cr0 & ~X86_CR0_TS); 8597 enter_guest(); 8598 check_nm_exit("fnop with CR0.TS set in L2 triggers #NM VM-exit to L1"); 8599 8600 /* 8601 * Re-enter L2 at the fnop instruction, with CR0.TS clear but 8602 * CR0.EM set. The fnop will still raise #NM, and L0 should 8603 * reflect the #NM VM-exit to L1. 8604 */ 8605 vmcs_write(GUEST_CR0, (cr0 & ~X86_CR0_TS) | X86_CR0_EM); 8606 enter_guest(); 8607 check_nm_exit("fnop with CR0.EM set in L2 triggers #NM VM-exit to L1"); 8608 8609 /* 8610 * Re-enter L2 at the fnop instruction, with both CR0.TS and 8611 * CR0.EM clear. There will be no #NM, and the L2 guest should 8612 * exit normally. 8613 */ 8614 vmcs_write(GUEST_CR0, cr0 & ~(X86_CR0_TS | X86_CR0_EM)); 8615 enter_guest(); 8616 } 8617 8618 bool vmx_pending_event_ipi_fired; 8619 static void vmx_pending_event_ipi_isr(isr_regs_t *regs) 8620 { 8621 vmx_pending_event_ipi_fired = true; 8622 eoi(); 8623 } 8624 8625 bool vmx_pending_event_guest_run; 8626 static void vmx_pending_event_guest(void) 8627 { 8628 vmcall(); 8629 vmx_pending_event_guest_run = true; 8630 } 8631 8632 static void vmx_pending_event_test_core(bool guest_hlt) 8633 { 8634 int ipi_vector = 0xf1; 8635 8636 vmx_pending_event_ipi_fired = false; 8637 handle_irq(ipi_vector, vmx_pending_event_ipi_isr); 8638 8639 vmx_pending_event_guest_run = false; 8640 test_set_guest(vmx_pending_event_guest); 8641 8642 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 8643 8644 enter_guest(); 8645 skip_exit_vmcall(); 8646 8647 if (guest_hlt) 8648 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8649 8650 irq_disable(); 8651 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | 8652 APIC_DM_FIXED | ipi_vector, 8653 0); 8654 8655 enter_guest(); 8656 8657 assert_exit_reason(VMX_EXTINT); 8658 report(!vmx_pending_event_guest_run, 8659 "Guest did not run before host received IPI"); 8660 8661 irq_enable(); 8662 asm volatile ("nop"); 8663 irq_disable(); 8664 report(vmx_pending_event_ipi_fired, 8665 "Got pending interrupt after IRQ enabled"); 8666 8667 if (guest_hlt) 8668 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 8669 8670 enter_guest(); 8671 report(vmx_pending_event_guest_run, 8672 "Guest finished running when no interrupt"); 8673 } 8674 8675 static void vmx_pending_event_test(void) 8676 { 8677 vmx_pending_event_test_core(false); 8678 } 8679 8680 static void vmx_pending_event_hlt_test(void) 8681 { 8682 vmx_pending_event_test_core(true); 8683 } 8684 8685 static int vmx_window_test_db_count; 8686 8687 static void vmx_window_test_db_handler(struct ex_regs *regs) 8688 { 8689 vmx_window_test_db_count++; 8690 } 8691 8692 static void vmx_nmi_window_test_guest(void) 8693 { 8694 handle_exception(DB_VECTOR, vmx_window_test_db_handler); 8695 8696 asm volatile("vmcall\n\t" 8697 "nop\n\t"); 8698 8699 handle_exception(DB_VECTOR, NULL); 8700 } 8701 8702 static void verify_nmi_window_exit(u64 rip) 8703 { 8704 u32 exit_reason = vmcs_read(EXI_REASON); 8705 8706 report(exit_reason == VMX_NMI_WINDOW, 8707 "Exit reason (%d) is 'NMI window'", exit_reason); 8708 report(vmcs_read(GUEST_RIP) == rip, "RIP (%#lx) is %#lx", 8709 vmcs_read(GUEST_RIP), rip); 8710 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 8711 } 8712 8713 static void vmx_nmi_window_test(void) 8714 { 8715 u64 nop_addr; 8716 void *db_fault_addr = get_idt_addr(&boot_idt[DB_VECTOR]); 8717 8718 if (!(ctrl_pin_rev.clr & PIN_VIRT_NMI)) { 8719 report_skip("CPU does not support the \"Virtual NMIs\" VM-execution control."); 8720 return; 8721 } 8722 8723 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 8724 report_skip("CPU does not support the \"NMI-window exiting\" VM-execution control."); 8725 return; 8726 } 8727 8728 vmx_window_test_db_count = 0; 8729 8730 report_prefix_push("NMI-window"); 8731 test_set_guest(vmx_nmi_window_test_guest); 8732 vmcs_set_bits(PIN_CONTROLS, PIN_VIRT_NMI); 8733 enter_guest(); 8734 skip_exit_vmcall(); 8735 nop_addr = vmcs_read(GUEST_RIP); 8736 8737 /* 8738 * Ask for "NMI-window exiting," and expect an immediate VM-exit. 8739 * RIP will not advance. 8740 */ 8741 report_prefix_push("active, no blocking"); 8742 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 8743 enter_guest(); 8744 verify_nmi_window_exit(nop_addr); 8745 report_prefix_pop(); 8746 8747 /* 8748 * Ask for "NMI-window exiting" in a MOV-SS shadow, and expect 8749 * a VM-exit on the next instruction after the nop. (The nop 8750 * is one byte.) 8751 */ 8752 report_prefix_push("active, blocking by MOV-SS"); 8753 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 8754 enter_guest(); 8755 verify_nmi_window_exit(nop_addr + 1); 8756 report_prefix_pop(); 8757 8758 /* 8759 * Ask for "NMI-window exiting" (with event injection), and 8760 * expect a VM-exit after the event is injected. (RIP should 8761 * be at the address specified in the IDT entry for #DB.) 8762 */ 8763 report_prefix_push("active, no blocking, injecting #DB"); 8764 vmcs_write(ENT_INTR_INFO, 8765 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 8766 enter_guest(); 8767 verify_nmi_window_exit((u64)db_fault_addr); 8768 report_prefix_pop(); 8769 8770 /* 8771 * Ask for "NMI-window exiting" with NMI blocking, and expect 8772 * a VM-exit after the next IRET (i.e. after the #DB handler 8773 * returns). So, RIP should be back at one byte past the nop. 8774 */ 8775 report_prefix_push("active, blocking by NMI"); 8776 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_NMI); 8777 enter_guest(); 8778 verify_nmi_window_exit(nop_addr + 1); 8779 report(vmx_window_test_db_count == 1, 8780 "#DB handler executed once (actual %d times)", 8781 vmx_window_test_db_count); 8782 report_prefix_pop(); 8783 8784 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 8785 report_skip("CPU does not support activity state HLT."); 8786 } else { 8787 /* 8788 * Ask for "NMI-window exiting" when entering activity 8789 * state HLT, and expect an immediate VM-exit. RIP is 8790 * still one byte past the nop. 8791 */ 8792 report_prefix_push("halted, no blocking"); 8793 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8794 enter_guest(); 8795 verify_nmi_window_exit(nop_addr + 1); 8796 report_prefix_pop(); 8797 8798 /* 8799 * Ask for "NMI-window exiting" when entering activity 8800 * state HLT (with event injection), and expect a 8801 * VM-exit after the event is injected. (RIP should be 8802 * at the address specified in the IDT entry for #DB.) 8803 */ 8804 report_prefix_push("halted, no blocking, injecting #DB"); 8805 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8806 vmcs_write(ENT_INTR_INFO, 8807 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 8808 DB_VECTOR); 8809 enter_guest(); 8810 verify_nmi_window_exit((u64)db_fault_addr); 8811 report_prefix_pop(); 8812 } 8813 8814 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 8815 enter_guest(); 8816 report_prefix_pop(); 8817 } 8818 8819 static void vmx_intr_window_test_guest(void) 8820 { 8821 handle_exception(DB_VECTOR, vmx_window_test_db_handler); 8822 8823 /* 8824 * The two consecutive STIs are to ensure that only the first 8825 * one has a shadow. Note that NOP and STI are one byte 8826 * instructions. 8827 */ 8828 asm volatile("vmcall\n\t" 8829 "nop\n\t" 8830 "sti\n\t" 8831 "sti\n\t"); 8832 8833 handle_exception(DB_VECTOR, NULL); 8834 } 8835 8836 static void verify_intr_window_exit(u64 rip) 8837 { 8838 u32 exit_reason = vmcs_read(EXI_REASON); 8839 8840 report(exit_reason == VMX_INTR_WINDOW, 8841 "Exit reason (%d) is 'interrupt window'", exit_reason); 8842 report(vmcs_read(GUEST_RIP) == rip, "RIP (%#lx) is %#lx", 8843 vmcs_read(GUEST_RIP), rip); 8844 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 8845 } 8846 8847 static void vmx_intr_window_test(void) 8848 { 8849 u64 vmcall_addr; 8850 u64 nop_addr; 8851 unsigned int orig_db_gate_type; 8852 void *db_fault_addr = get_idt_addr(&boot_idt[DB_VECTOR]); 8853 8854 if (!(ctrl_cpu_rev[0].clr & CPU_INTR_WINDOW)) { 8855 report_skip("CPU does not support the \"interrupt-window exiting\" VM-execution control."); 8856 return; 8857 } 8858 8859 /* 8860 * Change the IDT entry for #DB from interrupt gate to trap gate, 8861 * so that it won't clear RFLAGS.IF. We don't want interrupts to 8862 * be disabled after vectoring a #DB. 8863 */ 8864 orig_db_gate_type = boot_idt[DB_VECTOR].type; 8865 boot_idt[DB_VECTOR].type = 15; 8866 8867 report_prefix_push("interrupt-window"); 8868 test_set_guest(vmx_intr_window_test_guest); 8869 enter_guest(); 8870 assert_exit_reason(VMX_VMCALL); 8871 vmcall_addr = vmcs_read(GUEST_RIP); 8872 8873 /* 8874 * Ask for "interrupt-window exiting" with RFLAGS.IF set and 8875 * no blocking; expect an immediate VM-exit. Note that we have 8876 * not advanced past the vmcall instruction yet, so RIP should 8877 * point to the vmcall instruction. 8878 */ 8879 report_prefix_push("active, no blocking, RFLAGS.IF=1"); 8880 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8881 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_IF); 8882 enter_guest(); 8883 verify_intr_window_exit(vmcall_addr); 8884 report_prefix_pop(); 8885 8886 /* 8887 * Ask for "interrupt-window exiting" (with event injection) 8888 * with RFLAGS.IF set and no blocking; expect a VM-exit after 8889 * the event is injected. That is, RIP should should be at the 8890 * address specified in the IDT entry for #DB. 8891 */ 8892 report_prefix_push("active, no blocking, RFLAGS.IF=1, injecting #DB"); 8893 vmcs_write(ENT_INTR_INFO, 8894 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 8895 vmcall_addr = vmcs_read(GUEST_RIP); 8896 enter_guest(); 8897 verify_intr_window_exit((u64)db_fault_addr); 8898 report_prefix_pop(); 8899 8900 /* 8901 * Let the L2 guest run through the IRET, back to the VMCALL. 8902 * We have to clear the "interrupt-window exiting" 8903 * VM-execution control, or it would just keep causing 8904 * VM-exits. Then, advance past the VMCALL and set the 8905 * "interrupt-window exiting" VM-execution control again. 8906 */ 8907 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8908 enter_guest(); 8909 skip_exit_vmcall(); 8910 nop_addr = vmcs_read(GUEST_RIP); 8911 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8912 8913 /* 8914 * Ask for "interrupt-window exiting" in a MOV-SS shadow with 8915 * RFLAGS.IF set, and expect a VM-exit on the next 8916 * instruction. (NOP is one byte.) 8917 */ 8918 report_prefix_push("active, blocking by MOV-SS, RFLAGS.IF=1"); 8919 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 8920 enter_guest(); 8921 verify_intr_window_exit(nop_addr + 1); 8922 report_prefix_pop(); 8923 8924 /* 8925 * Back up to the NOP and ask for "interrupt-window exiting" 8926 * in an STI shadow with RFLAGS.IF set, and expect a VM-exit 8927 * on the next instruction. (NOP is one byte.) 8928 */ 8929 report_prefix_push("active, blocking by STI, RFLAGS.IF=1"); 8930 vmcs_write(GUEST_RIP, nop_addr); 8931 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_STI); 8932 enter_guest(); 8933 verify_intr_window_exit(nop_addr + 1); 8934 report_prefix_pop(); 8935 8936 /* 8937 * Ask for "interrupt-window exiting" with RFLAGS.IF clear, 8938 * and expect a VM-exit on the instruction following the STI 8939 * shadow. Only the first STI (which is one byte past the NOP) 8940 * should have a shadow. The second STI (which is two bytes 8941 * past the NOP) has no shadow. Therefore, the interrupt 8942 * window opens at three bytes past the NOP. 8943 */ 8944 report_prefix_push("active, RFLAGS.IF = 0"); 8945 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 8946 enter_guest(); 8947 verify_intr_window_exit(nop_addr + 3); 8948 report_prefix_pop(); 8949 8950 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 8951 report_skip("CPU does not support activity state HLT."); 8952 } else { 8953 /* 8954 * Ask for "interrupt-window exiting" when entering 8955 * activity state HLT, and expect an immediate 8956 * VM-exit. RIP is still three bytes past the nop. 8957 */ 8958 report_prefix_push("halted, no blocking"); 8959 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8960 enter_guest(); 8961 verify_intr_window_exit(nop_addr + 3); 8962 report_prefix_pop(); 8963 8964 /* 8965 * Ask for "interrupt-window exiting" when entering 8966 * activity state HLT (with event injection), and 8967 * expect a VM-exit after the event is injected. That 8968 * is, RIP should should be at the address specified 8969 * in the IDT entry for #DB. 8970 */ 8971 report_prefix_push("halted, no blocking, injecting #DB"); 8972 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8973 vmcs_write(ENT_INTR_INFO, 8974 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 8975 DB_VECTOR); 8976 enter_guest(); 8977 verify_intr_window_exit((u64)db_fault_addr); 8978 report_prefix_pop(); 8979 } 8980 8981 boot_idt[DB_VECTOR].type = orig_db_gate_type; 8982 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8983 enter_guest(); 8984 report_prefix_pop(); 8985 } 8986 8987 #define GUEST_TSC_OFFSET (1u << 30) 8988 8989 static u64 guest_tsc; 8990 8991 static void vmx_store_tsc_test_guest(void) 8992 { 8993 guest_tsc = rdtsc(); 8994 } 8995 8996 /* 8997 * This test ensures that when IA32_TSC is in the VM-exit MSR-store 8998 * list, the value saved is not subject to the TSC offset that is 8999 * applied to RDTSC/RDTSCP/RDMSR(IA32_TSC) in guest execution. 9000 */ 9001 static void vmx_store_tsc_test(void) 9002 { 9003 struct vmx_msr_entry msr_entry = { .index = MSR_IA32_TSC }; 9004 u64 low, high; 9005 9006 if (!(ctrl_cpu_rev[0].clr & CPU_USE_TSC_OFFSET)) { 9007 report_skip("'Use TSC offsetting' not supported"); 9008 return; 9009 } 9010 9011 test_set_guest(vmx_store_tsc_test_guest); 9012 9013 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_USE_TSC_OFFSET); 9014 vmcs_write(EXI_MSR_ST_CNT, 1); 9015 vmcs_write(EXIT_MSR_ST_ADDR, virt_to_phys(&msr_entry)); 9016 vmcs_write(TSC_OFFSET, GUEST_TSC_OFFSET); 9017 9018 low = rdtsc(); 9019 enter_guest(); 9020 high = rdtsc(); 9021 9022 report(low + GUEST_TSC_OFFSET <= guest_tsc && 9023 guest_tsc <= high + GUEST_TSC_OFFSET, 9024 "RDTSC value in the guest (%lu) is in range [%lu, %lu]", 9025 guest_tsc, low + GUEST_TSC_OFFSET, high + GUEST_TSC_OFFSET); 9026 report(low <= msr_entry.value && msr_entry.value <= high, 9027 "IA32_TSC value saved in the VM-exit MSR-store list (%lu) is in range [%lu, %lu]", 9028 msr_entry.value, low, high); 9029 } 9030 9031 static void vmx_preemption_timer_zero_test_db_handler(struct ex_regs *regs) 9032 { 9033 } 9034 9035 static void vmx_preemption_timer_zero_test_guest(void) 9036 { 9037 while (vmx_get_test_stage() < 3) 9038 vmcall(); 9039 } 9040 9041 static void vmx_preemption_timer_zero_activate_preemption_timer(void) 9042 { 9043 vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT); 9044 vmcs_write(PREEMPT_TIMER_VALUE, 0); 9045 } 9046 9047 static void vmx_preemption_timer_zero_advance_past_vmcall(void) 9048 { 9049 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 9050 enter_guest(); 9051 skip_exit_vmcall(); 9052 } 9053 9054 static void vmx_preemption_timer_zero_inject_db(bool intercept_db) 9055 { 9056 vmx_preemption_timer_zero_activate_preemption_timer(); 9057 vmcs_write(ENT_INTR_INFO, INTR_INFO_VALID_MASK | 9058 INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 9059 vmcs_write(EXC_BITMAP, intercept_db ? 1 << DB_VECTOR : 0); 9060 enter_guest(); 9061 } 9062 9063 static void vmx_preemption_timer_zero_set_pending_dbg(u32 exception_bitmap) 9064 { 9065 vmx_preemption_timer_zero_activate_preemption_timer(); 9066 vmcs_write(GUEST_PENDING_DEBUG, BIT(12) | DR_TRAP1); 9067 vmcs_write(EXC_BITMAP, exception_bitmap); 9068 enter_guest(); 9069 } 9070 9071 static void vmx_preemption_timer_zero_expect_preempt_at_rip(u64 expected_rip) 9072 { 9073 u32 reason = (u32)vmcs_read(EXI_REASON); 9074 u64 guest_rip = vmcs_read(GUEST_RIP); 9075 9076 report(reason == VMX_PREEMPT && guest_rip == expected_rip, 9077 "Exit reason is 0x%x (expected 0x%x) and guest RIP is %lx (0x%lx expected).", 9078 reason, VMX_PREEMPT, guest_rip, expected_rip); 9079 } 9080 9081 /* 9082 * This test ensures that when the VMX preemption timer is zero at 9083 * VM-entry, a VM-exit occurs after any event injection and after any 9084 * pending debug exceptions are raised, but before execution of any 9085 * guest instructions. 9086 */ 9087 static void vmx_preemption_timer_zero_test(void) 9088 { 9089 u64 db_fault_address = (u64)get_idt_addr(&boot_idt[DB_VECTOR]); 9090 handler old_db; 9091 u32 reason; 9092 9093 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 9094 report_skip("'Activate VMX-preemption timer' not supported"); 9095 return; 9096 } 9097 9098 /* 9099 * Install a custom #DB handler that doesn't abort. 9100 */ 9101 old_db = handle_exception(DB_VECTOR, 9102 vmx_preemption_timer_zero_test_db_handler); 9103 9104 test_set_guest(vmx_preemption_timer_zero_test_guest); 9105 9106 /* 9107 * VMX-preemption timer should fire after event injection. 9108 */ 9109 vmx_set_test_stage(0); 9110 vmx_preemption_timer_zero_inject_db(0); 9111 vmx_preemption_timer_zero_expect_preempt_at_rip(db_fault_address); 9112 vmx_preemption_timer_zero_advance_past_vmcall(); 9113 9114 /* 9115 * VMX-preemption timer should fire after event injection. 9116 * Exception bitmap is irrelevant, since you can't intercept 9117 * an event that you injected. 9118 */ 9119 vmx_set_test_stage(1); 9120 vmx_preemption_timer_zero_inject_db(true); 9121 vmx_preemption_timer_zero_expect_preempt_at_rip(db_fault_address); 9122 vmx_preemption_timer_zero_advance_past_vmcall(); 9123 9124 /* 9125 * VMX-preemption timer should fire after pending debug exceptions 9126 * have delivered a #DB trap. 9127 */ 9128 vmx_set_test_stage(2); 9129 vmx_preemption_timer_zero_set_pending_dbg(0); 9130 vmx_preemption_timer_zero_expect_preempt_at_rip(db_fault_address); 9131 vmx_preemption_timer_zero_advance_past_vmcall(); 9132 9133 /* 9134 * VMX-preemption timer would fire after pending debug exceptions 9135 * have delivered a #DB trap, but in this case, the #DB trap is 9136 * intercepted. 9137 */ 9138 vmx_set_test_stage(3); 9139 vmx_preemption_timer_zero_set_pending_dbg(1 << DB_VECTOR); 9140 reason = (u32)vmcs_read(EXI_REASON); 9141 report(reason == VMX_EXC_NMI, "Exit reason is 0x%x (expected 0x%x)", 9142 reason, VMX_EXC_NMI); 9143 9144 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 9145 enter_guest(); 9146 9147 handle_exception(DB_VECTOR, old_db); 9148 } 9149 9150 static u64 vmx_preemption_timer_tf_test_prev_rip; 9151 9152 static void vmx_preemption_timer_tf_test_db_handler(struct ex_regs *regs) 9153 { 9154 extern char vmx_preemption_timer_tf_test_endloop; 9155 9156 if (vmx_get_test_stage() == 2) { 9157 /* 9158 * Stage 2 means that we're done, one way or another. 9159 * Arrange for the iret to drop us out of the wbinvd 9160 * loop and stop single-stepping. 9161 */ 9162 regs->rip = (u64)&vmx_preemption_timer_tf_test_endloop; 9163 regs->rflags &= ~X86_EFLAGS_TF; 9164 } else if (regs->rip == vmx_preemption_timer_tf_test_prev_rip) { 9165 /* 9166 * The RIP should alternate between the wbinvd and the 9167 * jmp instruction in the code below. If we ever see 9168 * the same instruction twice in a row, that means a 9169 * single-step trap has been dropped. Let the 9170 * hypervisor know about the failure by executing a 9171 * VMCALL. 9172 */ 9173 vmcall(); 9174 } 9175 vmx_preemption_timer_tf_test_prev_rip = regs->rip; 9176 } 9177 9178 static void vmx_preemption_timer_tf_test_guest(void) 9179 { 9180 /* 9181 * The hypervisor doesn't intercept WBINVD, so the loop below 9182 * shouldn't be a problem--it's just two instructions 9183 * executing in VMX non-root mode. However, when the 9184 * hypervisor is running in a virtual environment, the parent 9185 * hypervisor might intercept WBINVD and emulate it. If the 9186 * parent hypervisor is broken, the single-step trap after the 9187 * WBINVD might be lost. 9188 */ 9189 asm volatile("vmcall\n\t" 9190 "0: wbinvd\n\t" 9191 "1: jmp 0b\n\t" 9192 "vmx_preemption_timer_tf_test_endloop:"); 9193 } 9194 9195 /* 9196 * Ensure that the delivery of a "VMX-preemption timer expired" 9197 * VM-exit doesn't disrupt single-stepping in the guest. Note that 9198 * passing this test doesn't ensure correctness, because the test will 9199 * only fail if the VMX-preemtion timer fires at the right time (or 9200 * the wrong time, as it were). 9201 */ 9202 static void vmx_preemption_timer_tf_test(void) 9203 { 9204 handler old_db; 9205 u32 reason; 9206 int i; 9207 9208 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 9209 report_skip("'Activate VMX-preemption timer' not supported"); 9210 return; 9211 } 9212 9213 old_db = handle_exception(DB_VECTOR, 9214 vmx_preemption_timer_tf_test_db_handler); 9215 9216 test_set_guest(vmx_preemption_timer_tf_test_guest); 9217 9218 enter_guest(); 9219 skip_exit_vmcall(); 9220 9221 vmx_set_test_stage(1); 9222 vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT); 9223 vmcs_write(PREEMPT_TIMER_VALUE, 50000); 9224 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_TF); 9225 9226 /* 9227 * The only exit we should see is "VMX-preemption timer 9228 * expired." If we get a VMCALL exit, that means the #DB 9229 * handler has detected a missing single-step trap. It doesn't 9230 * matter where the guest RIP is when the VMX-preemption timer 9231 * expires (whether it's in the WBINVD loop or in the #DB 9232 * handler)--a single-step trap should never be discarded. 9233 */ 9234 for (i = 0; i < 10000; i++) { 9235 enter_guest(); 9236 reason = (u32)vmcs_read(EXI_REASON); 9237 if (reason == VMX_PREEMPT) 9238 continue; 9239 TEST_ASSERT(reason == VMX_VMCALL); 9240 skip_exit_insn(); 9241 break; 9242 } 9243 9244 report(reason == VMX_PREEMPT, "No single-step traps skipped"); 9245 9246 vmx_set_test_stage(2); 9247 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 9248 enter_guest(); 9249 9250 handle_exception(DB_VECTOR, old_db); 9251 } 9252 9253 #define VMX_PREEMPTION_TIMER_EXPIRY_CYCLES 1000000 9254 9255 static u64 vmx_preemption_timer_expiry_start; 9256 static u64 vmx_preemption_timer_expiry_finish; 9257 9258 static void vmx_preemption_timer_expiry_test_guest(void) 9259 { 9260 vmcall(); 9261 vmx_preemption_timer_expiry_start = fenced_rdtsc(); 9262 9263 while (vmx_get_test_stage() == 0) 9264 vmx_preemption_timer_expiry_finish = fenced_rdtsc(); 9265 } 9266 9267 /* 9268 * Test that the VMX-preemption timer is not excessively delayed. 9269 * 9270 * Per the SDM, volume 3, VM-entry starts the VMX-preemption timer 9271 * with the unsigned value in the VMX-preemption timer-value field, 9272 * and the VMX-preemption timer counts down by 1 every time bit X in 9273 * the TSC changes due to a TSC increment (where X is 9274 * IA32_VMX_MISC[4:0]). If the timer counts down to zero in any state 9275 * other than the wait-for-SIPI state, the logical processor 9276 * transitions to the C0 C-state and causes a VM-exit. 9277 * 9278 * The guest code above reads the starting TSC after VM-entry. At this 9279 * point, the VMX-preemption timer has already been activated. Next, 9280 * the guest code reads the current TSC in a loop, storing the value 9281 * read to memory. 9282 * 9283 * If the RDTSC in the loop reads a value past the VMX-preemption 9284 * timer deadline, then the VMX-preemption timer VM-exit must be 9285 * delivered before the next instruction retires. Even if a higher 9286 * priority SMI is delivered first, the VMX-preemption timer VM-exit 9287 * must be delivered before the next instruction retires. Hence, a TSC 9288 * value past the VMX-preemption timer deadline might be read, but it 9289 * cannot be stored. If a TSC value past the deadline *is* stored, 9290 * then the architectural specification has been violated. 9291 */ 9292 static void vmx_preemption_timer_expiry_test(void) 9293 { 9294 u32 preemption_timer_value; 9295 union vmx_misc misc; 9296 u64 tsc_deadline; 9297 u32 reason; 9298 9299 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 9300 report_skip("'Activate VMX-preemption timer' not supported"); 9301 return; 9302 } 9303 9304 test_set_guest(vmx_preemption_timer_expiry_test_guest); 9305 9306 enter_guest(); 9307 skip_exit_vmcall(); 9308 9309 misc.val = rdmsr(MSR_IA32_VMX_MISC); 9310 preemption_timer_value = 9311 VMX_PREEMPTION_TIMER_EXPIRY_CYCLES >> misc.pt_bit; 9312 9313 vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT); 9314 vmcs_write(PREEMPT_TIMER_VALUE, preemption_timer_value); 9315 vmx_set_test_stage(0); 9316 9317 enter_guest(); 9318 reason = (u32)vmcs_read(EXI_REASON); 9319 TEST_ASSERT(reason == VMX_PREEMPT); 9320 9321 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 9322 vmx_set_test_stage(1); 9323 enter_guest(); 9324 9325 tsc_deadline = ((vmx_preemption_timer_expiry_start >> misc.pt_bit) << 9326 misc.pt_bit) + (preemption_timer_value << misc.pt_bit); 9327 9328 report(vmx_preemption_timer_expiry_finish < tsc_deadline, 9329 "Last stored guest TSC (%lu) < TSC deadline (%lu)", 9330 vmx_preemption_timer_expiry_finish, tsc_deadline); 9331 } 9332 9333 static void vmx_db_test_guest(void) 9334 { 9335 /* 9336 * For a hardware generated single-step #DB. 9337 */ 9338 asm volatile("vmcall;" 9339 "nop;" 9340 ".Lpost_nop:"); 9341 /* 9342 * ...in a MOVSS shadow, with pending debug exceptions. 9343 */ 9344 asm volatile("vmcall;" 9345 "nop;" 9346 ".Lpost_movss_nop:"); 9347 /* 9348 * For an L0 synthesized single-step #DB. (L0 intercepts WBINVD and 9349 * emulates it in software.) 9350 */ 9351 asm volatile("vmcall;" 9352 "wbinvd;" 9353 ".Lpost_wbinvd:"); 9354 /* 9355 * ...in a MOVSS shadow, with pending debug exceptions. 9356 */ 9357 asm volatile("vmcall;" 9358 "wbinvd;" 9359 ".Lpost_movss_wbinvd:"); 9360 /* 9361 * For a hardware generated single-step #DB in a transactional region. 9362 */ 9363 asm volatile("vmcall;" 9364 ".Lxbegin: xbegin .Lskip_rtm;" 9365 "xend;" 9366 ".Lskip_rtm:"); 9367 } 9368 9369 /* 9370 * Clear the pending debug exceptions and RFLAGS.TF and re-enter 9371 * L2. No #DB is delivered and L2 continues to the next point of 9372 * interest. 9373 */ 9374 static void dismiss_db(void) 9375 { 9376 vmcs_write(GUEST_PENDING_DEBUG, 0); 9377 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 9378 enter_guest(); 9379 } 9380 9381 /* 9382 * Check a variety of VMCS fields relevant to an intercepted #DB exception. 9383 * Then throw away the #DB exception and resume L2. 9384 */ 9385 static void check_db_exit(bool xfail_qual, bool xfail_dr6, bool xfail_pdbg, 9386 void *expected_rip, u64 expected_exit_qual, 9387 u64 expected_dr6) 9388 { 9389 u32 reason = vmcs_read(EXI_REASON); 9390 u32 intr_info = vmcs_read(EXI_INTR_INFO); 9391 u64 exit_qual = vmcs_read(EXI_QUALIFICATION); 9392 u64 guest_rip = vmcs_read(GUEST_RIP); 9393 u64 guest_pending_dbg = vmcs_read(GUEST_PENDING_DEBUG); 9394 u64 dr6 = read_dr6(); 9395 const u32 expected_intr_info = INTR_INFO_VALID_MASK | 9396 INTR_TYPE_HARD_EXCEPTION | DB_VECTOR; 9397 9398 report(reason == VMX_EXC_NMI && intr_info == expected_intr_info, 9399 "Expected #DB VM-exit"); 9400 report((u64)expected_rip == guest_rip, "Expected RIP %p (actual %lx)", 9401 expected_rip, guest_rip); 9402 report_xfail(xfail_pdbg, 0 == guest_pending_dbg, 9403 "Expected pending debug exceptions 0 (actual %lx)", 9404 guest_pending_dbg); 9405 report_xfail(xfail_qual, expected_exit_qual == exit_qual, 9406 "Expected exit qualification %lx (actual %lx)", 9407 expected_exit_qual, exit_qual); 9408 report_xfail(xfail_dr6, expected_dr6 == dr6, 9409 "Expected DR6 %lx (actual %lx)", expected_dr6, dr6); 9410 dismiss_db(); 9411 } 9412 9413 /* 9414 * Assuming the guest has just exited on a VMCALL instruction, skip 9415 * over the vmcall, and set the guest's RFLAGS.TF in the VMCS. If 9416 * pending debug exceptions are non-zero, set the VMCS up as if the 9417 * previous instruction was a MOVSS that generated the indicated 9418 * pending debug exceptions. Then enter L2. 9419 */ 9420 static void single_step_guest(const char *test_name, u64 starting_dr6, 9421 u64 pending_debug_exceptions) 9422 { 9423 printf("\n%s\n", test_name); 9424 skip_exit_vmcall(); 9425 write_dr6(starting_dr6); 9426 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_TF); 9427 if (pending_debug_exceptions) { 9428 vmcs_write(GUEST_PENDING_DEBUG, pending_debug_exceptions); 9429 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 9430 } 9431 enter_guest(); 9432 } 9433 9434 /* 9435 * When L1 intercepts #DB, verify that a single-step trap clears 9436 * pending debug exceptions, populates the exit qualification field 9437 * properly, and that DR6 is not prematurely clobbered. In a 9438 * (simulated) MOVSS shadow, make sure that the pending debug 9439 * exception bits are properly accumulated into the exit qualification 9440 * field. 9441 */ 9442 static void vmx_db_test(void) 9443 { 9444 /* 9445 * We are going to set a few arbitrary bits in DR6 to verify that 9446 * (a) DR6 is not modified by an intercepted #DB, and 9447 * (b) stale bits in DR6 (DR6.BD, in particular) don't leak into 9448 * the exit qualification field for a subsequent #DB exception. 9449 */ 9450 const u64 starting_dr6 = DR6_RESERVED | BIT(13) | DR_TRAP3 | DR_TRAP1; 9451 extern char post_nop asm(".Lpost_nop"); 9452 extern char post_movss_nop asm(".Lpost_movss_nop"); 9453 extern char post_wbinvd asm(".Lpost_wbinvd"); 9454 extern char post_movss_wbinvd asm(".Lpost_movss_wbinvd"); 9455 extern char xbegin asm(".Lxbegin"); 9456 extern char skip_rtm asm(".Lskip_rtm"); 9457 9458 /* 9459 * L1 wants to intercept #DB exceptions encountered in L2. 9460 */ 9461 vmcs_write(EXC_BITMAP, BIT(DB_VECTOR)); 9462 9463 /* 9464 * Start L2 and run it up to the first point of interest. 9465 */ 9466 test_set_guest(vmx_db_test_guest); 9467 enter_guest(); 9468 9469 /* 9470 * Hardware-delivered #DB trap for single-step sets the 9471 * standard that L0 has to follow for emulated instructions. 9472 */ 9473 single_step_guest("Hardware delivered single-step", starting_dr6, 0); 9474 check_db_exit(false, false, false, &post_nop, DR_STEP, starting_dr6); 9475 9476 /* 9477 * Hardware-delivered #DB trap for single-step in MOVSS shadow 9478 * also sets the standard that L0 has to follow for emulated 9479 * instructions. Here, we establish the VMCS pending debug 9480 * exceptions to indicate that the simulated MOVSS triggered a 9481 * data breakpoint as well as the single-step trap. 9482 */ 9483 single_step_guest("Hardware delivered single-step in MOVSS shadow", 9484 starting_dr6, BIT(12) | DR_STEP | DR_TRAP0 ); 9485 check_db_exit(false, false, false, &post_movss_nop, DR_STEP | DR_TRAP0, 9486 starting_dr6); 9487 9488 /* 9489 * L0 synthesized #DB trap for single-step is buggy, because 9490 * kvm (a) clobbers DR6 too early, and (b) tries its best to 9491 * reconstitute the exit qualification from the prematurely 9492 * modified DR6, but fails miserably. 9493 */ 9494 single_step_guest("Software synthesized single-step", starting_dr6, 0); 9495 check_db_exit(false, false, false, &post_wbinvd, DR_STEP, starting_dr6); 9496 9497 /* 9498 * L0 synthesized #DB trap for single-step in MOVSS shadow is 9499 * even worse, because L0 also leaves the pending debug 9500 * exceptions in the VMCS instead of accumulating them into 9501 * the exit qualification field for the #DB exception. 9502 */ 9503 single_step_guest("Software synthesized single-step in MOVSS shadow", 9504 starting_dr6, BIT(12) | DR_STEP | DR_TRAP0); 9505 check_db_exit(true, false, true, &post_movss_wbinvd, DR_STEP | DR_TRAP0, 9506 starting_dr6); 9507 9508 /* 9509 * Optional RTM test for hardware that supports RTM, to 9510 * demonstrate that the current volume 3 of the SDM 9511 * (325384-067US), table 27-1 is incorrect. Bit 16 of the exit 9512 * qualification for debug exceptions is not reserved. It is 9513 * set to 1 if a debug exception (#DB) or a breakpoint 9514 * exception (#BP) occurs inside an RTM region while advanced 9515 * debugging of RTM transactional regions is enabled. 9516 */ 9517 if (this_cpu_has(X86_FEATURE_RTM)) { 9518 vmcs_write(ENT_CONTROLS, 9519 vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 9520 /* 9521 * Set DR7.RTM[bit 11] and IA32_DEBUGCTL.RTM[bit 15] 9522 * in the guest to enable advanced debugging of RTM 9523 * transactional regions. 9524 */ 9525 vmcs_write(GUEST_DR7, BIT(11)); 9526 vmcs_write(GUEST_DEBUGCTL, BIT(15)); 9527 single_step_guest("Hardware delivered single-step in " 9528 "transactional region", starting_dr6, 0); 9529 check_db_exit(false, false, false, &xbegin, BIT(16), 9530 starting_dr6); 9531 } else { 9532 vmcs_write(GUEST_RIP, (u64)&skip_rtm); 9533 enter_guest(); 9534 } 9535 } 9536 9537 static void enable_vid(void) 9538 { 9539 void *virtual_apic_page; 9540 9541 assert(cpu_has_apicv()); 9542 9543 disable_intercept_for_x2apic_msrs(); 9544 9545 virtual_apic_page = alloc_page(); 9546 vmcs_write(APIC_VIRT_ADDR, (u64)virtual_apic_page); 9547 9548 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 9549 9550 vmcs_write(EOI_EXIT_BITMAP0, 0x0); 9551 vmcs_write(EOI_EXIT_BITMAP1, 0x0); 9552 vmcs_write(EOI_EXIT_BITMAP2, 0x0); 9553 vmcs_write(EOI_EXIT_BITMAP3, 0x0); 9554 9555 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY | CPU_TPR_SHADOW); 9556 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_VINTD | CPU_VIRT_X2APIC); 9557 } 9558 9559 static void trigger_ioapic_scan_thread(void *data) 9560 { 9561 /* Wait until other CPU entered L2 */ 9562 while (vmx_get_test_stage() != 1) 9563 ; 9564 9565 /* Trigger ioapic scan */ 9566 ioapic_set_redir(0xf, 0x79, TRIGGER_LEVEL); 9567 vmx_set_test_stage(2); 9568 } 9569 9570 static void irq_79_handler_guest(isr_regs_t *regs) 9571 { 9572 eoi(); 9573 9574 /* L1 expects vmexit on VMX_VMCALL and not VMX_EOI_INDUCED */ 9575 vmcall(); 9576 } 9577 9578 /* 9579 * Constant for num of busy-loop iterations after which 9580 * a timer interrupt should have happened in host 9581 */ 9582 #define TIMER_INTERRUPT_DELAY 100000000 9583 9584 static void vmx_eoi_bitmap_ioapic_scan_test_guest(void) 9585 { 9586 handle_irq(0x79, irq_79_handler_guest); 9587 irq_enable(); 9588 9589 /* Signal to L1 CPU to trigger ioapic scan */ 9590 vmx_set_test_stage(1); 9591 /* Wait until L1 CPU to trigger ioapic scan */ 9592 while (vmx_get_test_stage() != 2) 9593 ; 9594 9595 /* 9596 * Wait for L0 timer interrupt to be raised while we run in L2 9597 * such that L0 will process the IOAPIC scan request before 9598 * resuming L2 9599 */ 9600 delay(TIMER_INTERRUPT_DELAY); 9601 9602 asm volatile ("int $0x79"); 9603 } 9604 9605 static void vmx_eoi_bitmap_ioapic_scan_test(void) 9606 { 9607 if (!cpu_has_apicv() || (cpu_count() < 2)) { 9608 report_skip(__func__); 9609 return; 9610 } 9611 9612 enable_vid(); 9613 9614 on_cpu_async(1, trigger_ioapic_scan_thread, NULL); 9615 test_set_guest(vmx_eoi_bitmap_ioapic_scan_test_guest); 9616 9617 /* 9618 * Launch L2. 9619 * We expect the exit reason to be VMX_VMCALL (and not EOI INDUCED). 9620 * In case the reason isn't VMX_VMCALL, the asserion inside 9621 * skip_exit_vmcall() will fail. 9622 */ 9623 enter_guest(); 9624 skip_exit_vmcall(); 9625 9626 /* Let L2 finish */ 9627 enter_guest(); 9628 report_pass(__func__); 9629 } 9630 9631 #define HLT_WITH_RVI_VECTOR (0xf1) 9632 9633 bool vmx_hlt_with_rvi_guest_isr_fired; 9634 static void vmx_hlt_with_rvi_guest_isr(isr_regs_t *regs) 9635 { 9636 vmx_hlt_with_rvi_guest_isr_fired = true; 9637 eoi(); 9638 } 9639 9640 static void vmx_hlt_with_rvi_guest(void) 9641 { 9642 handle_irq(HLT_WITH_RVI_VECTOR, vmx_hlt_with_rvi_guest_isr); 9643 9644 irq_enable(); 9645 asm volatile ("nop"); 9646 9647 vmcall(); 9648 } 9649 9650 static void vmx_hlt_with_rvi_test(void) 9651 { 9652 if (!cpu_has_apicv()) { 9653 report_skip(__func__); 9654 return; 9655 } 9656 9657 enable_vid(); 9658 9659 vmx_hlt_with_rvi_guest_isr_fired = false; 9660 test_set_guest(vmx_hlt_with_rvi_guest); 9661 9662 enter_guest(); 9663 skip_exit_vmcall(); 9664 9665 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 9666 vmcs_write(GUEST_INT_STATUS, HLT_WITH_RVI_VECTOR); 9667 enter_guest(); 9668 9669 report(vmx_hlt_with_rvi_guest_isr_fired, "Interrupt raised in guest"); 9670 } 9671 9672 static void set_irq_line_thread(void *data) 9673 { 9674 /* Wait until other CPU entered L2 */ 9675 while (vmx_get_test_stage() != 1) 9676 ; 9677 9678 /* Set irq-line 0xf to raise vector 0x78 for vCPU 0 */ 9679 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 9680 vmx_set_test_stage(2); 9681 } 9682 9683 static bool irq_78_handler_vmcall_before_eoi; 9684 static void irq_78_handler_guest(isr_regs_t *regs) 9685 { 9686 set_irq_line(0xf, 0); 9687 if (irq_78_handler_vmcall_before_eoi) 9688 vmcall(); 9689 eoi(); 9690 vmcall(); 9691 } 9692 9693 static void vmx_apic_passthrough_guest(void) 9694 { 9695 handle_irq(0x78, irq_78_handler_guest); 9696 irq_enable(); 9697 9698 /* If requested, wait for other CPU to trigger ioapic scan */ 9699 if (vmx_get_test_stage() < 1) { 9700 vmx_set_test_stage(1); 9701 while (vmx_get_test_stage() != 2) 9702 ; 9703 } 9704 9705 set_irq_line(0xf, 1); 9706 } 9707 9708 static void vmx_apic_passthrough(bool set_irq_line_from_thread) 9709 { 9710 if (set_irq_line_from_thread && (cpu_count() < 2)) { 9711 report_skip(__func__); 9712 return; 9713 } 9714 9715 /* Test device is required for generating IRQs */ 9716 if (!test_device_enabled()) { 9717 report_skip(__func__); 9718 return; 9719 } 9720 u64 cpu_ctrl_0 = CPU_SECONDARY; 9721 u64 cpu_ctrl_1 = 0; 9722 9723 disable_intercept_for_x2apic_msrs(); 9724 9725 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 9726 9727 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 9728 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 9729 9730 if (set_irq_line_from_thread) { 9731 irq_78_handler_vmcall_before_eoi = false; 9732 on_cpu_async(1, set_irq_line_thread, NULL); 9733 } else { 9734 irq_78_handler_vmcall_before_eoi = true; 9735 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 9736 vmx_set_test_stage(2); 9737 } 9738 test_set_guest(vmx_apic_passthrough_guest); 9739 9740 if (irq_78_handler_vmcall_before_eoi) { 9741 /* Before EOI remote_irr should still be set */ 9742 enter_guest(); 9743 skip_exit_vmcall(); 9744 TEST_ASSERT_EQ_MSG(1, (int)ioapic_read_redir(0xf).remote_irr, 9745 "IOAPIC pass-through: remote_irr=1 before EOI"); 9746 } 9747 9748 /* After EOI remote_irr should be cleared */ 9749 enter_guest(); 9750 skip_exit_vmcall(); 9751 TEST_ASSERT_EQ_MSG(0, (int)ioapic_read_redir(0xf).remote_irr, 9752 "IOAPIC pass-through: remote_irr=0 after EOI"); 9753 9754 /* Let L2 finish */ 9755 enter_guest(); 9756 report_pass(__func__); 9757 } 9758 9759 static void vmx_apic_passthrough_test(void) 9760 { 9761 vmx_apic_passthrough(false); 9762 } 9763 9764 static void vmx_apic_passthrough_thread_test(void) 9765 { 9766 vmx_apic_passthrough(true); 9767 } 9768 9769 static void vmx_apic_passthrough_tpr_threshold_guest(void) 9770 { 9771 cli(); 9772 apic_set_tpr(0); 9773 } 9774 9775 static bool vmx_apic_passthrough_tpr_threshold_ipi_isr_fired; 9776 static void vmx_apic_passthrough_tpr_threshold_ipi_isr(isr_regs_t *regs) 9777 { 9778 vmx_apic_passthrough_tpr_threshold_ipi_isr_fired = true; 9779 eoi(); 9780 } 9781 9782 static void vmx_apic_passthrough_tpr_threshold_test(void) 9783 { 9784 int ipi_vector = 0xe1; 9785 9786 disable_intercept_for_x2apic_msrs(); 9787 vmcs_clear_bits(PIN_CONTROLS, PIN_EXTINT); 9788 9789 /* Raise L0 TPR-threshold by queueing vector in LAPIC IRR */ 9790 cli(); 9791 apic_set_tpr((ipi_vector >> 4) + 1); 9792 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | 9793 APIC_DM_FIXED | ipi_vector, 9794 0); 9795 9796 test_set_guest(vmx_apic_passthrough_tpr_threshold_guest); 9797 enter_guest(); 9798 9799 report(apic_get_tpr() == 0, "TPR was zero by guest"); 9800 9801 /* Clean pending self-IPI */ 9802 vmx_apic_passthrough_tpr_threshold_ipi_isr_fired = false; 9803 handle_irq(ipi_vector, vmx_apic_passthrough_tpr_threshold_ipi_isr); 9804 sti(); 9805 asm volatile ("nop"); 9806 report(vmx_apic_passthrough_tpr_threshold_ipi_isr_fired, "self-IPI fired"); 9807 9808 report_pass(__func__); 9809 } 9810 9811 static u64 init_signal_test_exit_reason; 9812 static bool init_signal_test_thread_continued; 9813 9814 static void init_signal_test_thread(void *data) 9815 { 9816 struct vmcs *test_vmcs = data; 9817 9818 /* Enter VMX operation (i.e. exec VMXON) */ 9819 u64 *ap_vmxon_region = alloc_page(); 9820 enable_vmx(); 9821 init_vmx(ap_vmxon_region); 9822 _vmx_on(ap_vmxon_region); 9823 9824 /* Signal CPU have entered VMX operation */ 9825 vmx_set_test_stage(1); 9826 9827 /* Wait for BSP CPU to send INIT signal */ 9828 while (vmx_get_test_stage() != 2) 9829 ; 9830 9831 /* 9832 * Signal that we continue as usual as INIT signal 9833 * should be blocked while CPU is in VMX operation 9834 */ 9835 vmx_set_test_stage(3); 9836 9837 /* Wait for signal to enter VMX non-root mode */ 9838 while (vmx_get_test_stage() != 4) 9839 ; 9840 9841 /* Enter VMX non-root mode */ 9842 test_set_guest(v2_null_test_guest); 9843 make_vmcs_current(test_vmcs); 9844 enter_guest(); 9845 /* Save exit reason for BSP CPU to compare to expected result */ 9846 init_signal_test_exit_reason = vmcs_read(EXI_REASON); 9847 /* VMCLEAR test-vmcs so it could be loaded by BSP CPU */ 9848 vmcs_clear(test_vmcs); 9849 launched = false; 9850 /* Signal that CPU exited to VMX root mode */ 9851 vmx_set_test_stage(5); 9852 9853 /* Wait for BSP CPU to signal to exit VMX operation */ 9854 while (vmx_get_test_stage() != 6) 9855 ; 9856 9857 /* Exit VMX operation (i.e. exec VMXOFF) */ 9858 vmx_off(); 9859 9860 /* 9861 * Signal to BSP CPU that we continue as usual as INIT signal 9862 * should have been consumed by VMX_INIT exit from guest 9863 */ 9864 vmx_set_test_stage(7); 9865 9866 /* Wait for BSP CPU to signal to enter VMX operation */ 9867 while (vmx_get_test_stage() != 8) 9868 ; 9869 /* Enter VMX operation (i.e. exec VMXON) */ 9870 _vmx_on(ap_vmxon_region); 9871 /* Signal to BSP we are in VMX operation */ 9872 vmx_set_test_stage(9); 9873 9874 /* Wait for BSP CPU to send INIT signal */ 9875 while (vmx_get_test_stage() != 10) 9876 ; 9877 9878 /* Exit VMX operation (i.e. exec VMXOFF) */ 9879 vmx_off(); 9880 9881 /* 9882 * Exiting VMX operation should result in latched 9883 * INIT signal being processed. Therefore, we should 9884 * never reach the below code. Thus, signal to BSP 9885 * CPU if we have reached here so it is able to 9886 * report an issue if it happens. 9887 */ 9888 init_signal_test_thread_continued = true; 9889 } 9890 9891 #define INIT_SIGNAL_TEST_DELAY 100000000ULL 9892 9893 static void vmx_init_signal_test(void) 9894 { 9895 struct vmcs *test_vmcs; 9896 9897 if (cpu_count() < 2) { 9898 report_skip(__func__); 9899 return; 9900 } 9901 9902 /* VMCLEAR test-vmcs so it could be loaded by other CPU */ 9903 vmcs_save(&test_vmcs); 9904 vmcs_clear(test_vmcs); 9905 9906 vmx_set_test_stage(0); 9907 on_cpu_async(1, init_signal_test_thread, test_vmcs); 9908 9909 /* Wait for other CPU to enter VMX operation */ 9910 while (vmx_get_test_stage() != 1) 9911 ; 9912 9913 /* Send INIT signal to other CPU */ 9914 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_INIT | APIC_INT_ASSERT, 9915 id_map[1]); 9916 /* Signal other CPU we have sent INIT signal */ 9917 vmx_set_test_stage(2); 9918 9919 /* 9920 * Wait reasonable amount of time for INIT signal to 9921 * be received on other CPU and verify that other CPU 9922 * have proceed as usual to next test stage as INIT 9923 * signal should be blocked while other CPU in 9924 * VMX operation 9925 */ 9926 delay(INIT_SIGNAL_TEST_DELAY); 9927 report(vmx_get_test_stage() == 3, 9928 "INIT signal blocked when CPU in VMX operation"); 9929 /* No point to continue if we failed at this point */ 9930 if (vmx_get_test_stage() != 3) 9931 return; 9932 9933 /* Signal other CPU to enter VMX non-root mode */ 9934 init_signal_test_exit_reason = -1ull; 9935 vmx_set_test_stage(4); 9936 /* 9937 * Wait reasonable amont of time for other CPU 9938 * to exit to VMX root mode 9939 */ 9940 delay(INIT_SIGNAL_TEST_DELAY); 9941 if (vmx_get_test_stage() != 5) { 9942 report_fail("Pending INIT signal didn't result in VMX exit"); 9943 return; 9944 } 9945 report(init_signal_test_exit_reason == VMX_INIT, 9946 "INIT signal during VMX non-root mode result in exit-reason %s (%lu)", 9947 exit_reason_description(init_signal_test_exit_reason), 9948 init_signal_test_exit_reason); 9949 9950 /* Run guest to completion */ 9951 make_vmcs_current(test_vmcs); 9952 enter_guest(); 9953 9954 /* Signal other CPU to exit VMX operation */ 9955 init_signal_test_thread_continued = false; 9956 vmx_set_test_stage(6); 9957 9958 /* Wait reasonable amount of time for other CPU to exit VMX operation */ 9959 delay(INIT_SIGNAL_TEST_DELAY); 9960 report(vmx_get_test_stage() == 7, 9961 "INIT signal consumed on VMX_INIT exit"); 9962 /* No point to continue if we failed at this point */ 9963 if (vmx_get_test_stage() != 7) 9964 return; 9965 9966 /* Signal other CPU to enter VMX operation */ 9967 vmx_set_test_stage(8); 9968 /* Wait for other CPU to enter VMX operation */ 9969 while (vmx_get_test_stage() != 9) 9970 ; 9971 9972 /* Send INIT signal to other CPU */ 9973 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_INIT | APIC_INT_ASSERT, 9974 id_map[1]); 9975 /* Signal other CPU we have sent INIT signal */ 9976 vmx_set_test_stage(10); 9977 9978 /* 9979 * Wait reasonable amount of time for other CPU 9980 * to exit VMX operation and process INIT signal 9981 */ 9982 delay(INIT_SIGNAL_TEST_DELAY); 9983 report(!init_signal_test_thread_continued, 9984 "INIT signal processed after exit VMX operation"); 9985 9986 /* 9987 * TODO: Send SIPI to other CPU to sipi_entry (See x86/cstart64.S) 9988 * to re-init it to kvm-unit-tests standard environment. 9989 * Somehow (?) verify that SIPI was indeed received. 9990 */ 9991 } 9992 9993 #define SIPI_SIGNAL_TEST_DELAY 100000000ULL 9994 9995 static void vmx_sipi_test_guest(void) 9996 { 9997 if (apic_id() == 0) { 9998 /* wait AP enter guest with activity=WAIT_SIPI */ 9999 while (vmx_get_test_stage() != 1) 10000 ; 10001 delay(SIPI_SIGNAL_TEST_DELAY); 10002 10003 /* First SIPI signal */ 10004 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_STARTUP | APIC_INT_ASSERT, id_map[1]); 10005 report_pass("BSP(L2): Send first SIPI to cpu[%d]", id_map[1]); 10006 10007 /* wait AP enter guest */ 10008 while (vmx_get_test_stage() != 2) 10009 ; 10010 delay(SIPI_SIGNAL_TEST_DELAY); 10011 10012 /* Second SIPI signal should be ignored since AP is not in WAIT_SIPI state */ 10013 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_STARTUP | APIC_INT_ASSERT, id_map[1]); 10014 report_pass("BSP(L2): Send second SIPI to cpu[%d]", id_map[1]); 10015 10016 /* Delay a while to check whether second SIPI would cause VMExit */ 10017 delay(SIPI_SIGNAL_TEST_DELAY); 10018 10019 /* Test is done, notify AP to exit test */ 10020 vmx_set_test_stage(3); 10021 10022 /* wait AP exit non-root mode */ 10023 while (vmx_get_test_stage() != 5) 10024 ; 10025 } else { 10026 /* wait BSP notify test is done */ 10027 while (vmx_get_test_stage() != 3) 10028 ; 10029 10030 /* AP exit guest */ 10031 vmx_set_test_stage(4); 10032 } 10033 } 10034 10035 static void sipi_test_ap_thread(void *data) 10036 { 10037 struct vmcs *ap_vmcs; 10038 u64 *ap_vmxon_region; 10039 void *ap_stack, *ap_syscall_stack; 10040 u64 cpu_ctrl_0 = CPU_SECONDARY; 10041 u64 cpu_ctrl_1 = 0; 10042 10043 /* Enter VMX operation (i.e. exec VMXON) */ 10044 ap_vmxon_region = alloc_page(); 10045 enable_vmx(); 10046 init_vmx(ap_vmxon_region); 10047 _vmx_on(ap_vmxon_region); 10048 init_vmcs(&ap_vmcs); 10049 make_vmcs_current(ap_vmcs); 10050 10051 /* Set stack for AP */ 10052 ap_stack = alloc_page(); 10053 ap_syscall_stack = alloc_page(); 10054 vmcs_write(GUEST_RSP, (u64)(ap_stack + PAGE_SIZE - 1)); 10055 vmcs_write(GUEST_SYSENTER_ESP, (u64)(ap_syscall_stack + PAGE_SIZE - 1)); 10056 10057 /* passthrough lapic to L2 */ 10058 disable_intercept_for_x2apic_msrs(); 10059 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 10060 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 10061 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 10062 10063 /* Set guest activity state to wait-for-SIPI state */ 10064 vmcs_write(GUEST_ACTV_STATE, ACTV_WAIT_SIPI); 10065 10066 vmx_set_test_stage(1); 10067 10068 /* AP enter guest */ 10069 enter_guest(); 10070 10071 if (vmcs_read(EXI_REASON) == VMX_SIPI) { 10072 report_pass("AP: Handle SIPI VMExit"); 10073 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 10074 vmx_set_test_stage(2); 10075 } else { 10076 report_fail("AP: Unexpected VMExit, reason=%ld", vmcs_read(EXI_REASON)); 10077 vmx_off(); 10078 return; 10079 } 10080 10081 /* AP enter guest */ 10082 enter_guest(); 10083 10084 report(vmcs_read(EXI_REASON) != VMX_SIPI, 10085 "AP: should no SIPI VMExit since activity is not in WAIT_SIPI state"); 10086 10087 /* notify BSP that AP is already exit from non-root mode */ 10088 vmx_set_test_stage(5); 10089 10090 /* Leave VMX operation */ 10091 vmx_off(); 10092 } 10093 10094 static void vmx_sipi_signal_test(void) 10095 { 10096 if (!(rdmsr(MSR_IA32_VMX_MISC) & MSR_IA32_VMX_MISC_ACTIVITY_WAIT_SIPI)) { 10097 printf("\tACTIVITY_WAIT_SIPI state is not supported.\n"); 10098 return; 10099 } 10100 10101 if (cpu_count() < 2) { 10102 report_skip(__func__); 10103 return; 10104 } 10105 10106 u64 cpu_ctrl_0 = CPU_SECONDARY; 10107 u64 cpu_ctrl_1 = 0; 10108 10109 /* passthrough lapic to L2 */ 10110 disable_intercept_for_x2apic_msrs(); 10111 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 10112 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 10113 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 10114 10115 test_set_guest(vmx_sipi_test_guest); 10116 10117 /* update CR3 on AP */ 10118 on_cpu(1, update_cr3, (void *)read_cr3()); 10119 10120 /* start AP */ 10121 on_cpu_async(1, sipi_test_ap_thread, NULL); 10122 10123 vmx_set_test_stage(0); 10124 10125 /* BSP enter guest */ 10126 enter_guest(); 10127 } 10128 10129 10130 enum vmcs_access { 10131 ACCESS_VMREAD, 10132 ACCESS_VMWRITE, 10133 ACCESS_NONE, 10134 }; 10135 10136 struct vmcs_shadow_test_common { 10137 enum vmcs_access op; 10138 enum Reason reason; 10139 u64 field; 10140 u64 value; 10141 u64 flags; 10142 u64 time; 10143 } l1_l2_common; 10144 10145 static inline u64 vmread_flags(u64 field, u64 *val) 10146 { 10147 u64 flags; 10148 10149 asm volatile ("vmread %2, %1; pushf; pop %0" 10150 : "=r" (flags), "=rm" (*val) : "r" (field) : "cc"); 10151 return flags & X86_EFLAGS_ALU; 10152 } 10153 10154 static inline u64 vmwrite_flags(u64 field, u64 val) 10155 { 10156 u64 flags; 10157 10158 asm volatile ("vmwrite %1, %2; pushf; pop %0" 10159 : "=r"(flags) : "rm" (val), "r" (field) : "cc"); 10160 return flags & X86_EFLAGS_ALU; 10161 } 10162 10163 static void vmx_vmcs_shadow_test_guest(void) 10164 { 10165 struct vmcs_shadow_test_common *c = &l1_l2_common; 10166 u64 start; 10167 10168 while (c->op != ACCESS_NONE) { 10169 start = rdtsc(); 10170 switch (c->op) { 10171 default: 10172 c->flags = -1ull; 10173 break; 10174 case ACCESS_VMREAD: 10175 c->flags = vmread_flags(c->field, &c->value); 10176 break; 10177 case ACCESS_VMWRITE: 10178 c->flags = vmwrite_flags(c->field, 0); 10179 break; 10180 } 10181 c->time = rdtsc() - start; 10182 vmcall(); 10183 } 10184 } 10185 10186 static u64 vmread_from_shadow(u64 field) 10187 { 10188 struct vmcs *primary; 10189 struct vmcs *shadow; 10190 u64 value; 10191 10192 TEST_ASSERT(!vmcs_save(&primary)); 10193 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 10194 TEST_ASSERT(!make_vmcs_current(shadow)); 10195 value = vmcs_read(field); 10196 TEST_ASSERT(!make_vmcs_current(primary)); 10197 return value; 10198 } 10199 10200 static u64 vmwrite_to_shadow(u64 field, u64 value) 10201 { 10202 struct vmcs *primary; 10203 struct vmcs *shadow; 10204 10205 TEST_ASSERT(!vmcs_save(&primary)); 10206 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 10207 TEST_ASSERT(!make_vmcs_current(shadow)); 10208 vmcs_write(field, value); 10209 value = vmcs_read(field); 10210 TEST_ASSERT(!make_vmcs_current(primary)); 10211 return value; 10212 } 10213 10214 static void vmcs_shadow_test_access(u8 *bitmap[2], enum vmcs_access access) 10215 { 10216 struct vmcs_shadow_test_common *c = &l1_l2_common; 10217 10218 c->op = access; 10219 vmcs_write(VMX_INST_ERROR, 0); 10220 enter_guest(); 10221 c->reason = vmcs_read(EXI_REASON) & 0xffff; 10222 if (c->reason != VMX_VMCALL) { 10223 skip_exit_insn(); 10224 enter_guest(); 10225 } 10226 skip_exit_vmcall(); 10227 } 10228 10229 static void vmcs_shadow_test_field(u8 *bitmap[2], u64 field) 10230 { 10231 struct vmcs_shadow_test_common *c = &l1_l2_common; 10232 struct vmcs *shadow; 10233 u64 value; 10234 uintptr_t flags[2]; 10235 bool good_shadow; 10236 u32 vmx_inst_error; 10237 10238 report_prefix_pushf("field %lx", field); 10239 c->field = field; 10240 10241 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 10242 if (shadow != (struct vmcs *)-1ull) { 10243 flags[ACCESS_VMREAD] = vmread_flags(field, &value); 10244 flags[ACCESS_VMWRITE] = vmwrite_flags(field, value); 10245 good_shadow = !flags[ACCESS_VMREAD] && !flags[ACCESS_VMWRITE]; 10246 } else { 10247 /* 10248 * When VMCS link pointer is -1ull, VMWRITE/VMREAD on 10249 * shadowed-fields should fail with setting RFLAGS.CF. 10250 */ 10251 flags[ACCESS_VMREAD] = X86_EFLAGS_CF; 10252 flags[ACCESS_VMWRITE] = X86_EFLAGS_CF; 10253 good_shadow = false; 10254 } 10255 10256 /* Intercept both VMREAD and VMWRITE. */ 10257 report_prefix_push("no VMREAD/VMWRITE permission"); 10258 /* VMWRITE/VMREAD done on reserved-bit should always intercept */ 10259 if (!(field >> VMCS_FIELD_RESERVED_SHIFT)) { 10260 set_bit(field, bitmap[ACCESS_VMREAD]); 10261 set_bit(field, bitmap[ACCESS_VMWRITE]); 10262 } 10263 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10264 report(c->reason == VMX_VMWRITE, "not shadowed for VMWRITE"); 10265 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10266 report(c->reason == VMX_VMREAD, "not shadowed for VMREAD"); 10267 report_prefix_pop(); 10268 10269 if (field >> VMCS_FIELD_RESERVED_SHIFT) 10270 goto out; 10271 10272 /* Permit shadowed VMREAD. */ 10273 report_prefix_push("VMREAD permission only"); 10274 clear_bit(field, bitmap[ACCESS_VMREAD]); 10275 set_bit(field, bitmap[ACCESS_VMWRITE]); 10276 if (good_shadow) 10277 value = vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 10278 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10279 report(c->reason == VMX_VMWRITE, "not shadowed for VMWRITE"); 10280 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10281 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10282 report(c->reason == VMX_VMCALL, "shadowed for VMREAD (in %ld cycles)", 10283 c->time); 10284 report(c->flags == flags[ACCESS_VMREAD], 10285 "ALU flags after VMREAD (%lx) are as expected (%lx)", 10286 c->flags, flags[ACCESS_VMREAD]); 10287 if (good_shadow) 10288 report(c->value == value, 10289 "value read from shadow (%lx) is as expected (%lx)", 10290 c->value, value); 10291 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 10292 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10293 "VMX_INST_ERROR (%d) is as expected (%d)", 10294 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10295 report_prefix_pop(); 10296 10297 /* Permit shadowed VMWRITE. */ 10298 report_prefix_push("VMWRITE permission only"); 10299 set_bit(field, bitmap[ACCESS_VMREAD]); 10300 clear_bit(field, bitmap[ACCESS_VMWRITE]); 10301 if (good_shadow) 10302 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 10303 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10304 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10305 report(c->reason == VMX_VMCALL, 10306 "shadowed for VMWRITE (in %ld cycles)", 10307 c->time); 10308 report(c->flags == flags[ACCESS_VMREAD], 10309 "ALU flags after VMWRITE (%lx) are as expected (%lx)", 10310 c->flags, flags[ACCESS_VMREAD]); 10311 if (good_shadow) { 10312 value = vmread_from_shadow(field); 10313 report(value == 0, 10314 "shadow VMCS value (%lx) is as expected (%lx)", value, 10315 0ul); 10316 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 10317 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10318 "VMX_INST_ERROR (%d) is as expected (%d)", 10319 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10320 } 10321 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10322 report(c->reason == VMX_VMREAD, "not shadowed for VMREAD"); 10323 report_prefix_pop(); 10324 10325 /* Permit shadowed VMREAD and VMWRITE. */ 10326 report_prefix_push("VMREAD and VMWRITE permission"); 10327 clear_bit(field, bitmap[ACCESS_VMREAD]); 10328 clear_bit(field, bitmap[ACCESS_VMWRITE]); 10329 if (good_shadow) 10330 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 10331 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10332 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10333 report(c->reason == VMX_VMCALL, 10334 "shadowed for VMWRITE (in %ld cycles)", 10335 c->time); 10336 report(c->flags == flags[ACCESS_VMREAD], 10337 "ALU flags after VMWRITE (%lx) are as expected (%lx)", 10338 c->flags, flags[ACCESS_VMREAD]); 10339 if (good_shadow) { 10340 value = vmread_from_shadow(field); 10341 report(value == 0, 10342 "shadow VMCS value (%lx) is as expected (%lx)", value, 10343 0ul); 10344 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 10345 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10346 "VMX_INST_ERROR (%d) is as expected (%d)", 10347 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10348 } 10349 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10350 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10351 report(c->reason == VMX_VMCALL, "shadowed for VMREAD (in %ld cycles)", 10352 c->time); 10353 report(c->flags == flags[ACCESS_VMREAD], 10354 "ALU flags after VMREAD (%lx) are as expected (%lx)", 10355 c->flags, flags[ACCESS_VMREAD]); 10356 if (good_shadow) 10357 report(c->value == 0, 10358 "value read from shadow (%lx) is as expected (%lx)", 10359 c->value, 0ul); 10360 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 10361 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10362 "VMX_INST_ERROR (%d) is as expected (%d)", 10363 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10364 report_prefix_pop(); 10365 10366 out: 10367 report_prefix_pop(); 10368 } 10369 10370 static void vmx_vmcs_shadow_test_body(u8 *bitmap[2]) 10371 { 10372 unsigned base; 10373 unsigned index; 10374 unsigned bit; 10375 unsigned highest_index = rdmsr(MSR_IA32_VMX_VMCS_ENUM); 10376 10377 /* Run test on all possible valid VMCS fields */ 10378 for (base = 0; 10379 base < (1 << VMCS_FIELD_RESERVED_SHIFT); 10380 base += (1 << VMCS_FIELD_TYPE_SHIFT)) 10381 for (index = 0; index <= highest_index; index++) 10382 vmcs_shadow_test_field(bitmap, base + index); 10383 10384 /* 10385 * Run tests on some invalid VMCS fields 10386 * (Have reserved bit set). 10387 */ 10388 for (bit = VMCS_FIELD_RESERVED_SHIFT; bit < VMCS_FIELD_BIT_SIZE; bit++) 10389 vmcs_shadow_test_field(bitmap, (1ull << bit)); 10390 } 10391 10392 static void vmx_vmcs_shadow_test(void) 10393 { 10394 u8 *bitmap[2]; 10395 struct vmcs *shadow; 10396 10397 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 10398 printf("\t'Activate secondary controls' not supported.\n"); 10399 return; 10400 } 10401 10402 if (!(ctrl_cpu_rev[1].clr & CPU_SHADOW_VMCS)) { 10403 printf("\t'VMCS shadowing' not supported.\n"); 10404 return; 10405 } 10406 10407 if (!(rdmsr(MSR_IA32_VMX_MISC) & 10408 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS)) { 10409 printf("\tVMWRITE can't modify VM-exit information fields.\n"); 10410 return; 10411 } 10412 10413 test_set_guest(vmx_vmcs_shadow_test_guest); 10414 10415 bitmap[ACCESS_VMREAD] = alloc_page(); 10416 bitmap[ACCESS_VMWRITE] = alloc_page(); 10417 10418 vmcs_write(VMREAD_BITMAP, virt_to_phys(bitmap[ACCESS_VMREAD])); 10419 vmcs_write(VMWRITE_BITMAP, virt_to_phys(bitmap[ACCESS_VMWRITE])); 10420 10421 shadow = alloc_page(); 10422 shadow->hdr.revision_id = basic.revision; 10423 shadow->hdr.shadow_vmcs = 1; 10424 TEST_ASSERT(!vmcs_clear(shadow)); 10425 10426 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_RDTSC); 10427 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY); 10428 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_SHADOW_VMCS); 10429 10430 vmcs_write(VMCS_LINK_PTR, virt_to_phys(shadow)); 10431 report_prefix_push("valid link pointer"); 10432 vmx_vmcs_shadow_test_body(bitmap); 10433 report_prefix_pop(); 10434 10435 vmcs_write(VMCS_LINK_PTR, -1ull); 10436 report_prefix_push("invalid link pointer"); 10437 vmx_vmcs_shadow_test_body(bitmap); 10438 report_prefix_pop(); 10439 10440 l1_l2_common.op = ACCESS_NONE; 10441 enter_guest(); 10442 } 10443 10444 /* 10445 * This test monitors the difference between a guest RDTSC instruction 10446 * and the IA32_TIME_STAMP_COUNTER MSR value stored in the VMCS12 10447 * VM-exit MSR-store list when taking a VM-exit on the instruction 10448 * following RDTSC. 10449 */ 10450 #define RDTSC_DIFF_ITERS 100000 10451 #define RDTSC_DIFF_FAILS 100 10452 #define HOST_CAPTURED_GUEST_TSC_DIFF_THRESHOLD 750 10453 10454 /* 10455 * Set 'use TSC offsetting' and set the guest offset to the 10456 * inverse of the host's current TSC value, so that the guest starts running 10457 * with an effective TSC value of 0. 10458 */ 10459 static void reset_guest_tsc_to_zero(void) 10460 { 10461 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_USE_TSC_OFFSET); 10462 vmcs_write(TSC_OFFSET, -rdtsc()); 10463 } 10464 10465 static void rdtsc_vmexit_diff_test_guest(void) 10466 { 10467 int i; 10468 10469 for (i = 0; i < RDTSC_DIFF_ITERS; i++) 10470 /* Ensure rdtsc is the last instruction before the vmcall. */ 10471 asm volatile("rdtsc; vmcall" : : : "eax", "edx"); 10472 } 10473 10474 /* 10475 * This function only considers the "use TSC offsetting" VM-execution 10476 * control. It does not handle "use TSC scaling" (because the latter 10477 * isn't available to the host today.) 10478 */ 10479 static unsigned long long host_time_to_guest_time(unsigned long long t) 10480 { 10481 TEST_ASSERT(!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 10482 !(vmcs_read(CPU_EXEC_CTRL1) & CPU_USE_TSC_SCALING)); 10483 10484 if (vmcs_read(CPU_EXEC_CTRL0) & CPU_USE_TSC_OFFSET) 10485 t += vmcs_read(TSC_OFFSET); 10486 10487 return t; 10488 } 10489 10490 static unsigned long long rdtsc_vmexit_diff_test_iteration(void) 10491 { 10492 unsigned long long guest_tsc, host_to_guest_tsc; 10493 10494 enter_guest(); 10495 skip_exit_vmcall(); 10496 guest_tsc = (u32) regs.rax + (regs.rdx << 32); 10497 host_to_guest_tsc = host_time_to_guest_time(exit_msr_store[0].value); 10498 10499 return host_to_guest_tsc - guest_tsc; 10500 } 10501 10502 static void rdtsc_vmexit_diff_test(void) 10503 { 10504 unsigned long long delta; 10505 int fail = 0; 10506 int i; 10507 10508 if (!(ctrl_cpu_rev[0].clr & CPU_USE_TSC_OFFSET)) 10509 test_skip("CPU doesn't support the 'use TSC offsetting' processor-based VM-execution control.\n"); 10510 10511 test_set_guest(rdtsc_vmexit_diff_test_guest); 10512 10513 reset_guest_tsc_to_zero(); 10514 10515 /* 10516 * Set up the VMCS12 VM-exit MSR-store list to store just one 10517 * MSR: IA32_TIME_STAMP_COUNTER. Note that the value stored is 10518 * in the host time domain (i.e., it is not adjusted according 10519 * to the TSC multiplier and TSC offset fields in the VMCS12, 10520 * as a guest RDTSC would be.) 10521 */ 10522 exit_msr_store = alloc_page(); 10523 exit_msr_store[0].index = MSR_IA32_TSC; 10524 vmcs_write(EXI_MSR_ST_CNT, 1); 10525 vmcs_write(EXIT_MSR_ST_ADDR, virt_to_phys(exit_msr_store)); 10526 10527 for (i = 0; i < RDTSC_DIFF_ITERS && fail < RDTSC_DIFF_FAILS; i++) { 10528 delta = rdtsc_vmexit_diff_test_iteration(); 10529 if (delta >= HOST_CAPTURED_GUEST_TSC_DIFF_THRESHOLD) 10530 fail++; 10531 } 10532 10533 enter_guest(); 10534 10535 report(fail < RDTSC_DIFF_FAILS, 10536 "RDTSC to VM-exit delta too high in %d of %d iterations, last = %llu", 10537 fail, i, delta); 10538 } 10539 10540 static int invalid_msr_init(struct vmcs *vmcs) 10541 { 10542 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 10543 printf("\tPreemption timer is not supported\n"); 10544 return VMX_TEST_EXIT; 10545 } 10546 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 10547 preempt_val = 10000000; 10548 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 10549 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 10550 10551 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 10552 printf("\tSave preemption value is not supported\n"); 10553 10554 vmcs_write(ENT_MSR_LD_CNT, 1); 10555 vmcs_write(ENTER_MSR_LD_ADDR, (u64)0x13370000); 10556 10557 return VMX_TEST_START; 10558 } 10559 10560 10561 static void invalid_msr_main(void) 10562 { 10563 report_fail("Invalid MSR load"); 10564 } 10565 10566 static int invalid_msr_exit_handler(union exit_reason exit_reason) 10567 { 10568 report_fail("Invalid MSR load"); 10569 print_vmexit_info(exit_reason); 10570 return VMX_TEST_EXIT; 10571 } 10572 10573 static int invalid_msr_entry_failure(struct vmentry_result *result) 10574 { 10575 report(result->exit_reason.failed_vmentry && 10576 result->exit_reason.basic == VMX_FAIL_MSR, "Invalid MSR load"); 10577 return VMX_TEST_VMEXIT; 10578 } 10579 10580 /* 10581 * The max number of MSRs in an atomic switch MSR list is: 10582 * (111B + 1) * 512 = 4096 10583 * 10584 * Each list entry consumes: 10585 * 4-byte MSR index + 4 bytes reserved + 8-byte data = 16 bytes 10586 * 10587 * Allocate 128 kB to cover max_msr_list_size (i.e., 64 kB) and then some. 10588 */ 10589 static const u32 msr_list_page_order = 5; 10590 10591 static void atomic_switch_msr_limit_test_guest(void) 10592 { 10593 vmcall(); 10594 } 10595 10596 static void populate_msr_list(struct vmx_msr_entry *msr_list, 10597 size_t byte_capacity, int count) 10598 { 10599 int i; 10600 10601 for (i = 0; i < count; i++) { 10602 msr_list[i].index = MSR_IA32_TSC; 10603 msr_list[i].reserved = 0; 10604 msr_list[i].value = 0x1234567890abcdef; 10605 } 10606 10607 memset(msr_list + count, 0xff, 10608 byte_capacity - count * sizeof(*msr_list)); 10609 } 10610 10611 static int max_msr_list_size(void) 10612 { 10613 u32 vmx_misc = rdmsr(MSR_IA32_VMX_MISC); 10614 u32 factor = ((vmx_misc & GENMASK(27, 25)) >> 25) + 1; 10615 10616 return factor * 512; 10617 } 10618 10619 static void atomic_switch_msrs_test(int count) 10620 { 10621 struct vmx_msr_entry *vm_enter_load; 10622 struct vmx_msr_entry *vm_exit_load; 10623 struct vmx_msr_entry *vm_exit_store; 10624 int max_allowed = max_msr_list_size(); 10625 int byte_capacity = 1ul << (msr_list_page_order + PAGE_SHIFT); 10626 /* Exceeding the max MSR list size at exit trigers KVM to abort. */ 10627 int exit_count = count > max_allowed ? max_allowed : count; 10628 int cleanup_count = count > max_allowed ? 2 : 1; 10629 int i; 10630 10631 /* 10632 * Check for the IA32_TSC MSR, 10633 * available with the "TSC flag" and used to populate the MSR lists. 10634 */ 10635 if (!(cpuid(1).d & (1 << 4))) { 10636 report_skip(__func__); 10637 return; 10638 } 10639 10640 /* Set L2 guest. */ 10641 test_set_guest(atomic_switch_msr_limit_test_guest); 10642 10643 /* Setup atomic MSR switch lists. */ 10644 vm_enter_load = alloc_pages(msr_list_page_order); 10645 vm_exit_load = alloc_pages(msr_list_page_order); 10646 vm_exit_store = alloc_pages(msr_list_page_order); 10647 10648 vmcs_write(ENTER_MSR_LD_ADDR, (u64)vm_enter_load); 10649 vmcs_write(EXIT_MSR_LD_ADDR, (u64)vm_exit_load); 10650 vmcs_write(EXIT_MSR_ST_ADDR, (u64)vm_exit_store); 10651 10652 /* 10653 * VM-Enter should succeed up to the max number of MSRs per list, and 10654 * should not consume junk beyond the last entry. 10655 */ 10656 populate_msr_list(vm_enter_load, byte_capacity, count); 10657 populate_msr_list(vm_exit_load, byte_capacity, exit_count); 10658 populate_msr_list(vm_exit_store, byte_capacity, exit_count); 10659 10660 vmcs_write(ENT_MSR_LD_CNT, count); 10661 vmcs_write(EXI_MSR_LD_CNT, exit_count); 10662 vmcs_write(EXI_MSR_ST_CNT, exit_count); 10663 10664 if (count <= max_allowed) { 10665 enter_guest(); 10666 assert_exit_reason(VMX_VMCALL); 10667 skip_exit_vmcall(); 10668 } else { 10669 u32 exit_qual; 10670 10671 test_guest_state("Invalid MSR Load Count", true, count, 10672 "ENT_MSR_LD_CNT"); 10673 10674 exit_qual = vmcs_read(EXI_QUALIFICATION); 10675 report(exit_qual == max_allowed + 1, "exit_qual, %u, is %u.", 10676 exit_qual, max_allowed + 1); 10677 } 10678 10679 /* Cleanup. */ 10680 vmcs_write(ENT_MSR_LD_CNT, 0); 10681 vmcs_write(EXI_MSR_LD_CNT, 0); 10682 vmcs_write(EXI_MSR_ST_CNT, 0); 10683 for (i = 0; i < cleanup_count; i++) { 10684 enter_guest(); 10685 skip_exit_vmcall(); 10686 } 10687 free_pages_by_order(vm_enter_load, msr_list_page_order); 10688 free_pages_by_order(vm_exit_load, msr_list_page_order); 10689 free_pages_by_order(vm_exit_store, msr_list_page_order); 10690 } 10691 10692 static void atomic_switch_max_msrs_test(void) 10693 { 10694 atomic_switch_msrs_test(max_msr_list_size()); 10695 } 10696 10697 static void atomic_switch_overflow_msrs_test(void) 10698 { 10699 if (test_device_enabled()) 10700 atomic_switch_msrs_test(max_msr_list_size() + 1); 10701 else 10702 test_skip("Test is only supported on KVM"); 10703 } 10704 10705 static void vmx_pf_exception_test_guest(void) 10706 { 10707 ac_test_run(PT_LEVEL_PML4); 10708 } 10709 10710 static void vmx_pf_exception_test(void) 10711 { 10712 u64 efer; 10713 struct cpuid cpuid; 10714 10715 test_set_guest(vmx_pf_exception_test_guest); 10716 10717 enter_guest(); 10718 10719 while (vmcs_read(EXI_REASON) != VMX_VMCALL) { 10720 switch (vmcs_read(EXI_REASON)) { 10721 case VMX_RDMSR: 10722 assert(regs.rcx == MSR_EFER); 10723 efer = vmcs_read(GUEST_EFER); 10724 regs.rdx = efer >> 32; 10725 regs.rax = efer & 0xffffffff; 10726 break; 10727 case VMX_WRMSR: 10728 assert(regs.rcx == MSR_EFER); 10729 efer = regs.rdx << 32 | (regs.rax & 0xffffffff); 10730 vmcs_write(GUEST_EFER, efer); 10731 break; 10732 case VMX_CPUID: 10733 cpuid = (struct cpuid) {0, 0, 0, 0}; 10734 cpuid = raw_cpuid(regs.rax, regs.rcx); 10735 regs.rax = cpuid.a; 10736 regs.rbx = cpuid.b; 10737 regs.rcx = cpuid.c; 10738 regs.rdx = cpuid.d; 10739 break; 10740 default: 10741 assert_msg(false, 10742 "Unexpected exit to L1, exit_reason: %s (0x%lx)", 10743 exit_reason_description(vmcs_read(EXI_REASON)), 10744 vmcs_read(EXI_REASON)); 10745 } 10746 skip_exit_insn(); 10747 enter_guest(); 10748 } 10749 10750 assert_exit_reason(VMX_VMCALL); 10751 } 10752 #define TEST(name) { #name, .v2 = name } 10753 10754 /* name/init/guest_main/exit_handler/syscall_handler/guest_regs */ 10755 struct vmx_test vmx_tests[] = { 10756 { "null", NULL, basic_guest_main, basic_exit_handler, NULL, {0} }, 10757 { "vmenter", NULL, vmenter_main, vmenter_exit_handler, NULL, {0} }, 10758 { "preemption timer", preemption_timer_init, preemption_timer_main, 10759 preemption_timer_exit_handler, NULL, {0} }, 10760 { "control field PAT", test_ctrl_pat_init, test_ctrl_pat_main, 10761 test_ctrl_pat_exit_handler, NULL, {0} }, 10762 { "control field EFER", test_ctrl_efer_init, test_ctrl_efer_main, 10763 test_ctrl_efer_exit_handler, NULL, {0} }, 10764 { "CR shadowing", NULL, cr_shadowing_main, 10765 cr_shadowing_exit_handler, NULL, {0} }, 10766 { "I/O bitmap", iobmp_init, iobmp_main, iobmp_exit_handler, 10767 NULL, {0} }, 10768 { "instruction intercept", insn_intercept_init, insn_intercept_main, 10769 insn_intercept_exit_handler, NULL, {0} }, 10770 { "EPT A/D disabled", ept_init, ept_main, ept_exit_handler, NULL, {0} }, 10771 { "EPT A/D enabled", eptad_init, eptad_main, eptad_exit_handler, NULL, {0} }, 10772 { "PML", pml_init, pml_main, pml_exit_handler, NULL, {0} }, 10773 { "VPID", vpid_init, vpid_main, vpid_exit_handler, NULL, {0} }, 10774 { "interrupt", interrupt_init, interrupt_main, 10775 interrupt_exit_handler, NULL, {0} }, 10776 { "nmi_hlt", nmi_hlt_init, nmi_hlt_main, 10777 nmi_hlt_exit_handler, NULL, {0} }, 10778 { "debug controls", dbgctls_init, dbgctls_main, dbgctls_exit_handler, 10779 NULL, {0} }, 10780 { "MSR switch", msr_switch_init, msr_switch_main, 10781 msr_switch_exit_handler, NULL, {0}, msr_switch_entry_failure }, 10782 { "vmmcall", vmmcall_init, vmmcall_main, vmmcall_exit_handler, NULL, {0} }, 10783 { "disable RDTSCP", disable_rdtscp_init, disable_rdtscp_main, 10784 disable_rdtscp_exit_handler, NULL, {0} }, 10785 { "int3", int3_init, int3_guest_main, int3_exit_handler, NULL, {0} }, 10786 { "into", into_init, into_guest_main, into_exit_handler, NULL, {0} }, 10787 { "exit_monitor_from_l2_test", NULL, exit_monitor_from_l2_main, 10788 exit_monitor_from_l2_handler, NULL, {0} }, 10789 { "invalid_msr", invalid_msr_init, invalid_msr_main, 10790 invalid_msr_exit_handler, NULL, {0}, invalid_msr_entry_failure}, 10791 /* Basic V2 tests. */ 10792 TEST(v2_null_test), 10793 TEST(v2_multiple_entries_test), 10794 TEST(fixture_test_case1), 10795 TEST(fixture_test_case2), 10796 /* Opcode tests. */ 10797 TEST(invvpid_test_v2), 10798 /* VM-entry tests */ 10799 TEST(vmx_controls_test), 10800 TEST(vmx_host_state_area_test), 10801 TEST(vmx_guest_state_area_test), 10802 TEST(vmentry_movss_shadow_test), 10803 TEST(vmentry_unrestricted_guest_test), 10804 /* APICv tests */ 10805 TEST(vmx_eoi_bitmap_ioapic_scan_test), 10806 TEST(vmx_hlt_with_rvi_test), 10807 TEST(apic_reg_virt_test), 10808 TEST(virt_x2apic_mode_test), 10809 /* APIC pass-through tests */ 10810 TEST(vmx_apic_passthrough_test), 10811 TEST(vmx_apic_passthrough_thread_test), 10812 TEST(vmx_apic_passthrough_tpr_threshold_test), 10813 TEST(vmx_init_signal_test), 10814 TEST(vmx_sipi_signal_test), 10815 /* VMCS Shadowing tests */ 10816 TEST(vmx_vmcs_shadow_test), 10817 /* Regression tests */ 10818 TEST(vmx_ldtr_test), 10819 TEST(vmx_cr_load_test), 10820 TEST(vmx_cr4_osxsave_test), 10821 TEST(vmx_nm_test), 10822 TEST(vmx_db_test), 10823 TEST(vmx_nmi_window_test), 10824 TEST(vmx_intr_window_test), 10825 TEST(vmx_pending_event_test), 10826 TEST(vmx_pending_event_hlt_test), 10827 TEST(vmx_store_tsc_test), 10828 TEST(vmx_preemption_timer_zero_test), 10829 TEST(vmx_preemption_timer_tf_test), 10830 TEST(vmx_preemption_timer_expiry_test), 10831 /* EPT access tests. */ 10832 TEST(ept_access_test_not_present), 10833 TEST(ept_access_test_read_only), 10834 TEST(ept_access_test_write_only), 10835 TEST(ept_access_test_read_write), 10836 TEST(ept_access_test_execute_only), 10837 TEST(ept_access_test_read_execute), 10838 TEST(ept_access_test_write_execute), 10839 TEST(ept_access_test_read_write_execute), 10840 TEST(ept_access_test_reserved_bits), 10841 TEST(ept_access_test_ignored_bits), 10842 TEST(ept_access_test_paddr_not_present_ad_disabled), 10843 TEST(ept_access_test_paddr_not_present_ad_enabled), 10844 TEST(ept_access_test_paddr_read_only_ad_disabled), 10845 TEST(ept_access_test_paddr_read_only_ad_enabled), 10846 TEST(ept_access_test_paddr_read_write), 10847 TEST(ept_access_test_paddr_read_write_execute), 10848 TEST(ept_access_test_paddr_read_execute_ad_disabled), 10849 TEST(ept_access_test_paddr_read_execute_ad_enabled), 10850 TEST(ept_access_test_paddr_not_present_page_fault), 10851 TEST(ept_access_test_force_2m_page), 10852 /* Atomic MSR switch tests. */ 10853 TEST(atomic_switch_max_msrs_test), 10854 TEST(atomic_switch_overflow_msrs_test), 10855 TEST(rdtsc_vmexit_diff_test), 10856 TEST(vmx_mtf_test), 10857 TEST(vmx_mtf_pdpte_test), 10858 TEST(vmx_pf_exception_test), 10859 { NULL, NULL, NULL, NULL, NULL, {0} }, 10860 }; 10861