1 /* 2 * All test cases of nested virtualization should be in this file 3 * 4 * Author : Arthur Chunqi Li <yzt356@gmail.com> 5 */ 6 7 #include <asm/debugreg.h> 8 9 #include "vmx.h" 10 #include "msr.h" 11 #include "processor.h" 12 #include "vm.h" 13 #include "pci.h" 14 #include "fwcfg.h" 15 #include "isr.h" 16 #include "desc.h" 17 #include "apic.h" 18 #include "types.h" 19 #include "vmalloc.h" 20 #include "alloc_page.h" 21 #include "smp.h" 22 #include "delay.h" 23 24 #define NONCANONICAL 0xaaaaaaaaaaaaaaaaull 25 26 #define VPID_CAP_INVVPID_TYPES_SHIFT 40 27 28 u64 ia32_pat; 29 u64 ia32_efer; 30 void *io_bitmap_a, *io_bitmap_b; 31 u16 ioport; 32 33 unsigned long *pml4; 34 u64 eptp; 35 void *data_page1, *data_page2; 36 37 phys_addr_t pci_physaddr; 38 39 void *pml_log; 40 #define PML_INDEX 512 41 42 static inline unsigned ffs(unsigned x) 43 { 44 int pos = -1; 45 46 __asm__ __volatile__("bsf %1, %%eax; cmovnz %%eax, %0" 47 : "+r"(pos) : "rm"(x) : "eax"); 48 return pos + 1; 49 } 50 51 static inline void vmcall(void) 52 { 53 asm volatile("vmcall"); 54 } 55 56 static void basic_guest_main(void) 57 { 58 report("Basic VMX test", 1); 59 } 60 61 static int basic_exit_handler(void) 62 { 63 report("Basic VMX test", 0); 64 print_vmexit_info(); 65 return VMX_TEST_EXIT; 66 } 67 68 static void vmenter_main(void) 69 { 70 u64 rax; 71 u64 rsp, resume_rsp; 72 73 report("test vmlaunch", 1); 74 75 asm volatile( 76 "mov %%rsp, %0\n\t" 77 "mov %3, %%rax\n\t" 78 "vmcall\n\t" 79 "mov %%rax, %1\n\t" 80 "mov %%rsp, %2\n\t" 81 : "=r"(rsp), "=r"(rax), "=r"(resume_rsp) 82 : "g"(0xABCD)); 83 report("test vmresume", (rax == 0xFFFF) && (rsp == resume_rsp)); 84 } 85 86 static int vmenter_exit_handler(void) 87 { 88 u64 guest_rip; 89 ulong reason; 90 91 guest_rip = vmcs_read(GUEST_RIP); 92 reason = vmcs_read(EXI_REASON) & 0xff; 93 switch (reason) { 94 case VMX_VMCALL: 95 if (regs.rax != 0xABCD) { 96 report("test vmresume", 0); 97 return VMX_TEST_VMEXIT; 98 } 99 regs.rax = 0xFFFF; 100 vmcs_write(GUEST_RIP, guest_rip + 3); 101 return VMX_TEST_RESUME; 102 default: 103 report("test vmresume", 0); 104 print_vmexit_info(); 105 } 106 return VMX_TEST_VMEXIT; 107 } 108 109 u32 preempt_scale; 110 volatile unsigned long long tsc_val; 111 volatile u32 preempt_val; 112 u64 saved_rip; 113 114 static int preemption_timer_init(struct vmcs *vmcs) 115 { 116 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 117 printf("\tPreemption timer is not supported\n"); 118 return VMX_TEST_EXIT; 119 } 120 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 121 preempt_val = 10000000; 122 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 123 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 124 125 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 126 printf("\tSave preemption value is not supported\n"); 127 128 return VMX_TEST_START; 129 } 130 131 static void preemption_timer_main(void) 132 { 133 tsc_val = rdtsc(); 134 if (ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) { 135 vmx_set_test_stage(0); 136 vmcall(); 137 if (vmx_get_test_stage() == 1) 138 vmcall(); 139 } 140 vmx_set_test_stage(1); 141 while (vmx_get_test_stage() == 1) { 142 if (((rdtsc() - tsc_val) >> preempt_scale) 143 > 10 * preempt_val) { 144 vmx_set_test_stage(2); 145 vmcall(); 146 } 147 } 148 tsc_val = rdtsc(); 149 asm volatile ("hlt"); 150 vmcall(); 151 vmx_set_test_stage(5); 152 vmcall(); 153 } 154 155 static int preemption_timer_exit_handler(void) 156 { 157 bool guest_halted; 158 u64 guest_rip; 159 ulong reason; 160 u32 insn_len; 161 u32 ctrl_exit; 162 163 guest_rip = vmcs_read(GUEST_RIP); 164 reason = vmcs_read(EXI_REASON) & 0xff; 165 insn_len = vmcs_read(EXI_INST_LEN); 166 switch (reason) { 167 case VMX_PREEMPT: 168 switch (vmx_get_test_stage()) { 169 case 1: 170 case 2: 171 report("busy-wait for preemption timer", 172 ((rdtsc() - tsc_val) >> preempt_scale) >= 173 preempt_val); 174 vmx_set_test_stage(3); 175 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 176 return VMX_TEST_RESUME; 177 case 3: 178 guest_halted = 179 (vmcs_read(GUEST_ACTV_STATE) == ACTV_HLT); 180 report("preemption timer during hlt", 181 ((rdtsc() - tsc_val) >> preempt_scale) >= 182 preempt_val && guest_halted); 183 vmx_set_test_stage(4); 184 vmcs_write(PIN_CONTROLS, 185 vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 186 vmcs_write(EXI_CONTROLS, 187 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_PREEMPT); 188 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 189 return VMX_TEST_RESUME; 190 case 4: 191 report("preemption timer with 0 value", 192 saved_rip == guest_rip); 193 break; 194 default: 195 report("Invalid stage.", false); 196 print_vmexit_info(); 197 break; 198 } 199 break; 200 case VMX_VMCALL: 201 vmcs_write(GUEST_RIP, guest_rip + insn_len); 202 switch (vmx_get_test_stage()) { 203 case 0: 204 report("Keep preemption value", 205 vmcs_read(PREEMPT_TIMER_VALUE) == preempt_val); 206 vmx_set_test_stage(1); 207 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 208 ctrl_exit = (vmcs_read(EXI_CONTROLS) | 209 EXI_SAVE_PREEMPT) & ctrl_exit_rev.clr; 210 vmcs_write(EXI_CONTROLS, ctrl_exit); 211 return VMX_TEST_RESUME; 212 case 1: 213 report("Save preemption value", 214 vmcs_read(PREEMPT_TIMER_VALUE) < preempt_val); 215 return VMX_TEST_RESUME; 216 case 2: 217 report("busy-wait for preemption timer", 0); 218 vmx_set_test_stage(3); 219 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 220 return VMX_TEST_RESUME; 221 case 3: 222 report("preemption timer during hlt", 0); 223 vmx_set_test_stage(4); 224 /* fall through */ 225 case 4: 226 vmcs_write(PIN_CONTROLS, 227 vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 228 vmcs_write(PREEMPT_TIMER_VALUE, 0); 229 saved_rip = guest_rip + insn_len; 230 return VMX_TEST_RESUME; 231 case 5: 232 report("preemption timer with 0 value (vmcall stage 5)", 0); 233 break; 234 default: 235 // Should not reach here 236 report("unexpected stage, %d", false, 237 vmx_get_test_stage()); 238 print_vmexit_info(); 239 return VMX_TEST_VMEXIT; 240 } 241 break; 242 default: 243 report("Unknown exit reason, %ld", false, reason); 244 print_vmexit_info(); 245 } 246 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 247 return VMX_TEST_VMEXIT; 248 } 249 250 static void msr_bmp_init(void) 251 { 252 void *msr_bitmap; 253 u32 ctrl_cpu0; 254 255 msr_bitmap = alloc_page(); 256 memset(msr_bitmap, 0x0, PAGE_SIZE); 257 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 258 ctrl_cpu0 |= CPU_MSR_BITMAP; 259 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 260 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 261 } 262 263 static void *get_msr_bitmap(void) 264 { 265 void *msr_bitmap; 266 267 if (vmcs_read(CPU_EXEC_CTRL0) & CPU_MSR_BITMAP) { 268 msr_bitmap = (void *)vmcs_read(MSR_BITMAP); 269 } else { 270 msr_bitmap = alloc_page(); 271 memset(msr_bitmap, 0xff, PAGE_SIZE); 272 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 273 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_MSR_BITMAP); 274 } 275 276 return msr_bitmap; 277 } 278 279 static void disable_intercept_for_x2apic_msrs(void) 280 { 281 unsigned long *msr_bitmap = (unsigned long *)get_msr_bitmap(); 282 u32 msr; 283 284 for (msr = APIC_BASE_MSR; 285 msr < (APIC_BASE_MSR+0xff); 286 msr += BITS_PER_LONG) { 287 unsigned int word = msr / BITS_PER_LONG; 288 289 msr_bitmap[word] = 0; 290 msr_bitmap[word + (0x800 / sizeof(long))] = 0; 291 } 292 } 293 294 static int test_ctrl_pat_init(struct vmcs *vmcs) 295 { 296 u64 ctrl_ent; 297 u64 ctrl_exi; 298 299 msr_bmp_init(); 300 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT) && 301 !(ctrl_exit_rev.clr & EXI_LOAD_PAT) && 302 !(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 303 printf("\tSave/load PAT is not supported\n"); 304 return 1; 305 } 306 307 ctrl_ent = vmcs_read(ENT_CONTROLS); 308 ctrl_exi = vmcs_read(EXI_CONTROLS); 309 ctrl_ent |= ctrl_enter_rev.clr & ENT_LOAD_PAT; 310 ctrl_exi |= ctrl_exit_rev.clr & (EXI_SAVE_PAT | EXI_LOAD_PAT); 311 vmcs_write(ENT_CONTROLS, ctrl_ent); 312 vmcs_write(EXI_CONTROLS, ctrl_exi); 313 ia32_pat = rdmsr(MSR_IA32_CR_PAT); 314 vmcs_write(GUEST_PAT, 0x0); 315 vmcs_write(HOST_PAT, ia32_pat); 316 return VMX_TEST_START; 317 } 318 319 static void test_ctrl_pat_main(void) 320 { 321 u64 guest_ia32_pat; 322 323 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 324 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) 325 printf("\tENT_LOAD_PAT is not supported.\n"); 326 else { 327 if (guest_ia32_pat != 0) { 328 report("Entry load PAT", 0); 329 return; 330 } 331 } 332 wrmsr(MSR_IA32_CR_PAT, 0x6); 333 vmcall(); 334 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 335 if (ctrl_enter_rev.clr & ENT_LOAD_PAT) 336 report("Entry load PAT", guest_ia32_pat == ia32_pat); 337 } 338 339 static int test_ctrl_pat_exit_handler(void) 340 { 341 u64 guest_rip; 342 ulong reason; 343 u64 guest_pat; 344 345 guest_rip = vmcs_read(GUEST_RIP); 346 reason = vmcs_read(EXI_REASON) & 0xff; 347 switch (reason) { 348 case VMX_VMCALL: 349 guest_pat = vmcs_read(GUEST_PAT); 350 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT)) { 351 printf("\tEXI_SAVE_PAT is not supported\n"); 352 vmcs_write(GUEST_PAT, 0x6); 353 } else { 354 report("Exit save PAT", guest_pat == 0x6); 355 } 356 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) 357 printf("\tEXI_LOAD_PAT is not supported\n"); 358 else 359 report("Exit load PAT", rdmsr(MSR_IA32_CR_PAT) == ia32_pat); 360 vmcs_write(GUEST_PAT, ia32_pat); 361 vmcs_write(GUEST_RIP, guest_rip + 3); 362 return VMX_TEST_RESUME; 363 default: 364 printf("ERROR : Undefined exit reason, reason = %ld.\n", reason); 365 break; 366 } 367 return VMX_TEST_VMEXIT; 368 } 369 370 static int test_ctrl_efer_init(struct vmcs *vmcs) 371 { 372 u64 ctrl_ent; 373 u64 ctrl_exi; 374 375 msr_bmp_init(); 376 ctrl_ent = vmcs_read(ENT_CONTROLS) | ENT_LOAD_EFER; 377 ctrl_exi = vmcs_read(EXI_CONTROLS) | EXI_SAVE_EFER | EXI_LOAD_EFER; 378 vmcs_write(ENT_CONTROLS, ctrl_ent & ctrl_enter_rev.clr); 379 vmcs_write(EXI_CONTROLS, ctrl_exi & ctrl_exit_rev.clr); 380 ia32_efer = rdmsr(MSR_EFER); 381 vmcs_write(GUEST_EFER, ia32_efer ^ EFER_NX); 382 vmcs_write(HOST_EFER, ia32_efer ^ EFER_NX); 383 return VMX_TEST_START; 384 } 385 386 static void test_ctrl_efer_main(void) 387 { 388 u64 guest_ia32_efer; 389 390 guest_ia32_efer = rdmsr(MSR_EFER); 391 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) 392 printf("\tENT_LOAD_EFER is not supported.\n"); 393 else { 394 if (guest_ia32_efer != (ia32_efer ^ EFER_NX)) { 395 report("Entry load EFER", 0); 396 return; 397 } 398 } 399 wrmsr(MSR_EFER, ia32_efer); 400 vmcall(); 401 guest_ia32_efer = rdmsr(MSR_EFER); 402 if (ctrl_enter_rev.clr & ENT_LOAD_EFER) 403 report("Entry load EFER", guest_ia32_efer == ia32_efer); 404 } 405 406 static int test_ctrl_efer_exit_handler(void) 407 { 408 u64 guest_rip; 409 ulong reason; 410 u64 guest_efer; 411 412 guest_rip = vmcs_read(GUEST_RIP); 413 reason = vmcs_read(EXI_REASON) & 0xff; 414 switch (reason) { 415 case VMX_VMCALL: 416 guest_efer = vmcs_read(GUEST_EFER); 417 if (!(ctrl_exit_rev.clr & EXI_SAVE_EFER)) { 418 printf("\tEXI_SAVE_EFER is not supported\n"); 419 vmcs_write(GUEST_EFER, ia32_efer); 420 } else { 421 report("Exit save EFER", guest_efer == ia32_efer); 422 } 423 if (!(ctrl_exit_rev.clr & EXI_LOAD_EFER)) { 424 printf("\tEXI_LOAD_EFER is not supported\n"); 425 wrmsr(MSR_EFER, ia32_efer ^ EFER_NX); 426 } else { 427 report("Exit load EFER", rdmsr(MSR_EFER) == (ia32_efer ^ EFER_NX)); 428 } 429 vmcs_write(GUEST_PAT, ia32_efer); 430 vmcs_write(GUEST_RIP, guest_rip + 3); 431 return VMX_TEST_RESUME; 432 default: 433 printf("ERROR : Undefined exit reason, reason = %ld.\n", reason); 434 break; 435 } 436 return VMX_TEST_VMEXIT; 437 } 438 439 u32 guest_cr0, guest_cr4; 440 441 static void cr_shadowing_main(void) 442 { 443 u32 cr0, cr4, tmp; 444 445 // Test read through 446 vmx_set_test_stage(0); 447 guest_cr0 = read_cr0(); 448 if (vmx_get_test_stage() == 1) 449 report("Read through CR0", 0); 450 else 451 vmcall(); 452 vmx_set_test_stage(1); 453 guest_cr4 = read_cr4(); 454 if (vmx_get_test_stage() == 2) 455 report("Read through CR4", 0); 456 else 457 vmcall(); 458 // Test write through 459 guest_cr0 = guest_cr0 ^ (X86_CR0_TS | X86_CR0_MP); 460 guest_cr4 = guest_cr4 ^ (X86_CR4_TSD | X86_CR4_DE); 461 vmx_set_test_stage(2); 462 write_cr0(guest_cr0); 463 if (vmx_get_test_stage() == 3) 464 report("Write throuth CR0", 0); 465 else 466 vmcall(); 467 vmx_set_test_stage(3); 468 write_cr4(guest_cr4); 469 if (vmx_get_test_stage() == 4) 470 report("Write through CR4", 0); 471 else 472 vmcall(); 473 // Test read shadow 474 vmx_set_test_stage(4); 475 vmcall(); 476 cr0 = read_cr0(); 477 if (vmx_get_test_stage() != 5) 478 report("Read shadowing CR0", cr0 == guest_cr0); 479 vmx_set_test_stage(5); 480 cr4 = read_cr4(); 481 if (vmx_get_test_stage() != 6) 482 report("Read shadowing CR4", cr4 == guest_cr4); 483 // Test write shadow (same value with shadow) 484 vmx_set_test_stage(6); 485 write_cr0(guest_cr0); 486 if (vmx_get_test_stage() == 7) 487 report("Write shadowing CR0 (same value with shadow)", 0); 488 else 489 vmcall(); 490 vmx_set_test_stage(7); 491 write_cr4(guest_cr4); 492 if (vmx_get_test_stage() == 8) 493 report("Write shadowing CR4 (same value with shadow)", 0); 494 else 495 vmcall(); 496 // Test write shadow (different value) 497 vmx_set_test_stage(8); 498 tmp = guest_cr0 ^ X86_CR0_TS; 499 asm volatile("mov %0, %%rsi\n\t" 500 "mov %%rsi, %%cr0\n\t" 501 ::"m"(tmp) 502 :"rsi", "memory", "cc"); 503 report("Write shadowing different X86_CR0_TS", vmx_get_test_stage() == 9); 504 vmx_set_test_stage(9); 505 tmp = guest_cr0 ^ X86_CR0_MP; 506 asm volatile("mov %0, %%rsi\n\t" 507 "mov %%rsi, %%cr0\n\t" 508 ::"m"(tmp) 509 :"rsi", "memory", "cc"); 510 report("Write shadowing different X86_CR0_MP", vmx_get_test_stage() == 10); 511 vmx_set_test_stage(10); 512 tmp = guest_cr4 ^ X86_CR4_TSD; 513 asm volatile("mov %0, %%rsi\n\t" 514 "mov %%rsi, %%cr4\n\t" 515 ::"m"(tmp) 516 :"rsi", "memory", "cc"); 517 report("Write shadowing different X86_CR4_TSD", vmx_get_test_stage() == 11); 518 vmx_set_test_stage(11); 519 tmp = guest_cr4 ^ X86_CR4_DE; 520 asm volatile("mov %0, %%rsi\n\t" 521 "mov %%rsi, %%cr4\n\t" 522 ::"m"(tmp) 523 :"rsi", "memory", "cc"); 524 report("Write shadowing different X86_CR4_DE", vmx_get_test_stage() == 12); 525 } 526 527 static int cr_shadowing_exit_handler(void) 528 { 529 u64 guest_rip; 530 ulong reason; 531 u32 insn_len; 532 u32 exit_qual; 533 534 guest_rip = vmcs_read(GUEST_RIP); 535 reason = vmcs_read(EXI_REASON) & 0xff; 536 insn_len = vmcs_read(EXI_INST_LEN); 537 exit_qual = vmcs_read(EXI_QUALIFICATION); 538 switch (reason) { 539 case VMX_VMCALL: 540 switch (vmx_get_test_stage()) { 541 case 0: 542 report("Read through CR0", guest_cr0 == vmcs_read(GUEST_CR0)); 543 break; 544 case 1: 545 report("Read through CR4", guest_cr4 == vmcs_read(GUEST_CR4)); 546 break; 547 case 2: 548 report("Write through CR0", guest_cr0 == vmcs_read(GUEST_CR0)); 549 break; 550 case 3: 551 report("Write through CR4", guest_cr4 == vmcs_read(GUEST_CR4)); 552 break; 553 case 4: 554 guest_cr0 = vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP); 555 guest_cr4 = vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE); 556 vmcs_write(CR0_MASK, X86_CR0_TS | X86_CR0_MP); 557 vmcs_write(CR0_READ_SHADOW, guest_cr0 & (X86_CR0_TS | X86_CR0_MP)); 558 vmcs_write(CR4_MASK, X86_CR4_TSD | X86_CR4_DE); 559 vmcs_write(CR4_READ_SHADOW, guest_cr4 & (X86_CR4_TSD | X86_CR4_DE)); 560 break; 561 case 6: 562 report("Write shadowing CR0 (same value)", 563 guest_cr0 == (vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP))); 564 break; 565 case 7: 566 report("Write shadowing CR4 (same value)", 567 guest_cr4 == (vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE))); 568 break; 569 default: 570 // Should not reach here 571 report("unexpected stage, %d", false, 572 vmx_get_test_stage()); 573 print_vmexit_info(); 574 return VMX_TEST_VMEXIT; 575 } 576 vmcs_write(GUEST_RIP, guest_rip + insn_len); 577 return VMX_TEST_RESUME; 578 case VMX_CR: 579 switch (vmx_get_test_stage()) { 580 case 4: 581 report("Read shadowing CR0", 0); 582 vmx_inc_test_stage(); 583 break; 584 case 5: 585 report("Read shadowing CR4", 0); 586 vmx_inc_test_stage(); 587 break; 588 case 6: 589 report("Write shadowing CR0 (same value)", 0); 590 vmx_inc_test_stage(); 591 break; 592 case 7: 593 report("Write shadowing CR4 (same value)", 0); 594 vmx_inc_test_stage(); 595 break; 596 case 8: 597 case 9: 598 // 0x600 encodes "mov %esi, %cr0" 599 if (exit_qual == 0x600) 600 vmx_inc_test_stage(); 601 break; 602 case 10: 603 case 11: 604 // 0x604 encodes "mov %esi, %cr4" 605 if (exit_qual == 0x604) 606 vmx_inc_test_stage(); 607 break; 608 default: 609 // Should not reach here 610 report("unexpected stage, %d", false, 611 vmx_get_test_stage()); 612 print_vmexit_info(); 613 return VMX_TEST_VMEXIT; 614 } 615 vmcs_write(GUEST_RIP, guest_rip + insn_len); 616 return VMX_TEST_RESUME; 617 default: 618 report("Unknown exit reason, %ld", false, reason); 619 print_vmexit_info(); 620 } 621 return VMX_TEST_VMEXIT; 622 } 623 624 static int iobmp_init(struct vmcs *vmcs) 625 { 626 u32 ctrl_cpu0; 627 628 io_bitmap_a = alloc_page(); 629 io_bitmap_b = alloc_page(); 630 memset(io_bitmap_a, 0x0, PAGE_SIZE); 631 memset(io_bitmap_b, 0x0, PAGE_SIZE); 632 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 633 ctrl_cpu0 |= CPU_IO_BITMAP; 634 ctrl_cpu0 &= (~CPU_IO); 635 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 636 vmcs_write(IO_BITMAP_A, (u64)io_bitmap_a); 637 vmcs_write(IO_BITMAP_B, (u64)io_bitmap_b); 638 return VMX_TEST_START; 639 } 640 641 static void iobmp_main(void) 642 { 643 // stage 0, test IO pass 644 vmx_set_test_stage(0); 645 inb(0x5000); 646 outb(0x0, 0x5000); 647 report("I/O bitmap - I/O pass", vmx_get_test_stage() == 0); 648 // test IO width, in/out 649 ((u8 *)io_bitmap_a)[0] = 0xFF; 650 vmx_set_test_stage(2); 651 inb(0x0); 652 report("I/O bitmap - trap in", vmx_get_test_stage() == 3); 653 vmx_set_test_stage(3); 654 outw(0x0, 0x0); 655 report("I/O bitmap - trap out", vmx_get_test_stage() == 4); 656 vmx_set_test_stage(4); 657 inl(0x0); 658 report("I/O bitmap - I/O width, long", vmx_get_test_stage() == 5); 659 // test low/high IO port 660 vmx_set_test_stage(5); 661 ((u8 *)io_bitmap_a)[0x5000 / 8] = (1 << (0x5000 % 8)); 662 inb(0x5000); 663 report("I/O bitmap - I/O port, low part", vmx_get_test_stage() == 6); 664 vmx_set_test_stage(6); 665 ((u8 *)io_bitmap_b)[0x1000 / 8] = (1 << (0x1000 % 8)); 666 inb(0x9000); 667 report("I/O bitmap - I/O port, high part", vmx_get_test_stage() == 7); 668 // test partial pass 669 vmx_set_test_stage(7); 670 inl(0x4FFF); 671 report("I/O bitmap - partial pass", vmx_get_test_stage() == 8); 672 // test overrun 673 vmx_set_test_stage(8); 674 memset(io_bitmap_a, 0x0, PAGE_SIZE); 675 memset(io_bitmap_b, 0x0, PAGE_SIZE); 676 inl(0xFFFF); 677 report("I/O bitmap - overrun", vmx_get_test_stage() == 9); 678 vmx_set_test_stage(9); 679 vmcall(); 680 outb(0x0, 0x0); 681 report("I/O bitmap - ignore unconditional exiting", 682 vmx_get_test_stage() == 9); 683 vmx_set_test_stage(10); 684 vmcall(); 685 outb(0x0, 0x0); 686 report("I/O bitmap - unconditional exiting", 687 vmx_get_test_stage() == 11); 688 } 689 690 static int iobmp_exit_handler(void) 691 { 692 u64 guest_rip; 693 ulong reason, exit_qual; 694 u32 insn_len, ctrl_cpu0; 695 696 guest_rip = vmcs_read(GUEST_RIP); 697 reason = vmcs_read(EXI_REASON) & 0xff; 698 exit_qual = vmcs_read(EXI_QUALIFICATION); 699 insn_len = vmcs_read(EXI_INST_LEN); 700 switch (reason) { 701 case VMX_IO: 702 switch (vmx_get_test_stage()) { 703 case 0: 704 case 1: 705 vmx_inc_test_stage(); 706 break; 707 case 2: 708 report("I/O bitmap - I/O width, byte", 709 (exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_BYTE); 710 report("I/O bitmap - I/O direction, in", exit_qual & VMX_IO_IN); 711 vmx_inc_test_stage(); 712 break; 713 case 3: 714 report("I/O bitmap - I/O width, word", 715 (exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_WORD); 716 report("I/O bitmap - I/O direction, out", 717 !(exit_qual & VMX_IO_IN)); 718 vmx_inc_test_stage(); 719 break; 720 case 4: 721 report("I/O bitmap - I/O width, long", 722 (exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_LONG); 723 vmx_inc_test_stage(); 724 break; 725 case 5: 726 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x5000) 727 vmx_inc_test_stage(); 728 break; 729 case 6: 730 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x9000) 731 vmx_inc_test_stage(); 732 break; 733 case 7: 734 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x4FFF) 735 vmx_inc_test_stage(); 736 break; 737 case 8: 738 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0xFFFF) 739 vmx_inc_test_stage(); 740 break; 741 case 9: 742 case 10: 743 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 744 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0 & ~CPU_IO); 745 vmx_inc_test_stage(); 746 break; 747 default: 748 // Should not reach here 749 report("unexpected stage, %d", false, 750 vmx_get_test_stage()); 751 print_vmexit_info(); 752 return VMX_TEST_VMEXIT; 753 } 754 vmcs_write(GUEST_RIP, guest_rip + insn_len); 755 return VMX_TEST_RESUME; 756 case VMX_VMCALL: 757 switch (vmx_get_test_stage()) { 758 case 9: 759 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 760 ctrl_cpu0 |= CPU_IO | CPU_IO_BITMAP; 761 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 762 break; 763 case 10: 764 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 765 ctrl_cpu0 = (ctrl_cpu0 & ~CPU_IO_BITMAP) | CPU_IO; 766 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 767 break; 768 default: 769 // Should not reach here 770 report("unexpected stage, %d", false, 771 vmx_get_test_stage()); 772 print_vmexit_info(); 773 return VMX_TEST_VMEXIT; 774 } 775 vmcs_write(GUEST_RIP, guest_rip + insn_len); 776 return VMX_TEST_RESUME; 777 default: 778 printf("guest_rip = %#lx\n", guest_rip); 779 printf("\tERROR : Undefined exit reason, reason = %ld.\n", reason); 780 break; 781 } 782 return VMX_TEST_VMEXIT; 783 } 784 785 #define INSN_CPU0 0 786 #define INSN_CPU1 1 787 #define INSN_ALWAYS_TRAP 2 788 789 #define FIELD_EXIT_QUAL (1 << 0) 790 #define FIELD_INSN_INFO (1 << 1) 791 792 asm( 793 "insn_hlt: hlt;ret\n\t" 794 "insn_invlpg: invlpg 0x12345678;ret\n\t" 795 "insn_mwait: xor %eax, %eax; xor %ecx, %ecx; mwait;ret\n\t" 796 "insn_rdpmc: xor %ecx, %ecx; rdpmc;ret\n\t" 797 "insn_rdtsc: rdtsc;ret\n\t" 798 "insn_cr3_load: mov cr3,%rax; mov %rax,%cr3;ret\n\t" 799 "insn_cr3_store: mov %cr3,%rax;ret\n\t" 800 #ifdef __x86_64__ 801 "insn_cr8_load: xor %eax, %eax; mov %rax,%cr8;ret\n\t" 802 "insn_cr8_store: mov %cr8,%rax;ret\n\t" 803 #endif 804 "insn_monitor: xor %eax, %eax; xor %ecx, %ecx; xor %edx, %edx; monitor;ret\n\t" 805 "insn_pause: pause;ret\n\t" 806 "insn_wbinvd: wbinvd;ret\n\t" 807 "insn_cpuid: mov $10, %eax; cpuid;ret\n\t" 808 "insn_invd: invd;ret\n\t" 809 "insn_sgdt: sgdt gdt64_desc;ret\n\t" 810 "insn_lgdt: lgdt gdt64_desc;ret\n\t" 811 "insn_sidt: sidt idt_descr;ret\n\t" 812 "insn_lidt: lidt idt_descr;ret\n\t" 813 "insn_sldt: sldt %ax;ret\n\t" 814 "insn_lldt: xor %eax, %eax; lldt %ax;ret\n\t" 815 "insn_str: str %ax;ret\n\t" 816 "insn_rdrand: rdrand %rax;ret\n\t" 817 "insn_rdseed: rdseed %rax;ret\n\t" 818 ); 819 extern void insn_hlt(void); 820 extern void insn_invlpg(void); 821 extern void insn_mwait(void); 822 extern void insn_rdpmc(void); 823 extern void insn_rdtsc(void); 824 extern void insn_cr3_load(void); 825 extern void insn_cr3_store(void); 826 #ifdef __x86_64__ 827 extern void insn_cr8_load(void); 828 extern void insn_cr8_store(void); 829 #endif 830 extern void insn_monitor(void); 831 extern void insn_pause(void); 832 extern void insn_wbinvd(void); 833 extern void insn_sgdt(void); 834 extern void insn_lgdt(void); 835 extern void insn_sidt(void); 836 extern void insn_lidt(void); 837 extern void insn_sldt(void); 838 extern void insn_lldt(void); 839 extern void insn_str(void); 840 extern void insn_cpuid(void); 841 extern void insn_invd(void); 842 extern void insn_rdrand(void); 843 extern void insn_rdseed(void); 844 845 u32 cur_insn; 846 u64 cr3; 847 848 struct insn_table { 849 const char *name; 850 u32 flag; 851 void (*insn_func)(void); 852 u32 type; 853 u32 reason; 854 ulong exit_qual; 855 u32 insn_info; 856 // Use FIELD_EXIT_QUAL and FIELD_INSN_INFO to define 857 // which field need to be tested, reason is always tested 858 u32 test_field; 859 }; 860 861 /* 862 * Add more test cases of instruction intercept here. Elements in this 863 * table is: 864 * name/control flag/insn function/type/exit reason/exit qulification/ 865 * instruction info/field to test 866 * The last field defines which fields (exit_qual and insn_info) need to be 867 * tested in exit handler. If set to 0, only "reason" is checked. 868 */ 869 static struct insn_table insn_table[] = { 870 // Flags for Primary Processor-Based VM-Execution Controls 871 {"HLT", CPU_HLT, insn_hlt, INSN_CPU0, 12, 0, 0, 0}, 872 {"INVLPG", CPU_INVLPG, insn_invlpg, INSN_CPU0, 14, 873 0x12345678, 0, FIELD_EXIT_QUAL}, 874 {"MWAIT", CPU_MWAIT, insn_mwait, INSN_CPU0, 36, 0, 0, 0}, 875 {"RDPMC", CPU_RDPMC, insn_rdpmc, INSN_CPU0, 15, 0, 0, 0}, 876 {"RDTSC", CPU_RDTSC, insn_rdtsc, INSN_CPU0, 16, 0, 0, 0}, 877 {"CR3 load", CPU_CR3_LOAD, insn_cr3_load, INSN_CPU0, 28, 0x3, 0, 878 FIELD_EXIT_QUAL}, 879 {"CR3 store", CPU_CR3_STORE, insn_cr3_store, INSN_CPU0, 28, 0x13, 0, 880 FIELD_EXIT_QUAL}, 881 #ifdef __x86_64__ 882 {"CR8 load", CPU_CR8_LOAD, insn_cr8_load, INSN_CPU0, 28, 0x8, 0, 883 FIELD_EXIT_QUAL}, 884 {"CR8 store", CPU_CR8_STORE, insn_cr8_store, INSN_CPU0, 28, 0x18, 0, 885 FIELD_EXIT_QUAL}, 886 #endif 887 {"MONITOR", CPU_MONITOR, insn_monitor, INSN_CPU0, 39, 0, 0, 0}, 888 {"PAUSE", CPU_PAUSE, insn_pause, INSN_CPU0, 40, 0, 0, 0}, 889 // Flags for Secondary Processor-Based VM-Execution Controls 890 {"WBINVD", CPU_WBINVD, insn_wbinvd, INSN_CPU1, 54, 0, 0, 0}, 891 {"DESC_TABLE (SGDT)", CPU_DESC_TABLE, insn_sgdt, INSN_CPU1, 46, 0, 0, 0}, 892 {"DESC_TABLE (LGDT)", CPU_DESC_TABLE, insn_lgdt, INSN_CPU1, 46, 0, 0, 0}, 893 {"DESC_TABLE (SIDT)", CPU_DESC_TABLE, insn_sidt, INSN_CPU1, 46, 0, 0, 0}, 894 {"DESC_TABLE (LIDT)", CPU_DESC_TABLE, insn_lidt, INSN_CPU1, 46, 0, 0, 0}, 895 {"DESC_TABLE (SLDT)", CPU_DESC_TABLE, insn_sldt, INSN_CPU1, 47, 0, 0, 0}, 896 {"DESC_TABLE (LLDT)", CPU_DESC_TABLE, insn_lldt, INSN_CPU1, 47, 0, 0, 0}, 897 {"DESC_TABLE (STR)", CPU_DESC_TABLE, insn_str, INSN_CPU1, 47, 0, 0, 0}, 898 /* LTR causes a #GP if done with a busy selector, so it is not tested. */ 899 {"RDRAND", CPU_RDRAND, insn_rdrand, INSN_CPU1, VMX_RDRAND, 0, 0, 0}, 900 {"RDSEED", CPU_RDSEED, insn_rdseed, INSN_CPU1, VMX_RDSEED, 0, 0, 0}, 901 // Instructions always trap 902 {"CPUID", 0, insn_cpuid, INSN_ALWAYS_TRAP, 10, 0, 0, 0}, 903 {"INVD", 0, insn_invd, INSN_ALWAYS_TRAP, 13, 0, 0, 0}, 904 // Instructions never trap 905 {NULL}, 906 }; 907 908 static int insn_intercept_init(struct vmcs *vmcs) 909 { 910 u32 ctrl_cpu; 911 912 ctrl_cpu = ctrl_cpu_rev[0].set | CPU_SECONDARY; 913 ctrl_cpu &= ctrl_cpu_rev[0].clr; 914 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu); 915 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu_rev[1].set); 916 cr3 = read_cr3(); 917 return VMX_TEST_START; 918 } 919 920 static void insn_intercept_main(void) 921 { 922 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 923 vmx_set_test_stage(cur_insn * 2); 924 if ((insn_table[cur_insn].type == INSN_CPU0 && 925 !(ctrl_cpu_rev[0].clr & insn_table[cur_insn].flag)) || 926 (insn_table[cur_insn].type == INSN_CPU1 && 927 !(ctrl_cpu_rev[1].clr & insn_table[cur_insn].flag))) { 928 printf("\tCPU_CTRL%d.CPU_%s is not supported.\n", 929 insn_table[cur_insn].type - INSN_CPU0, 930 insn_table[cur_insn].name); 931 continue; 932 } 933 934 if ((insn_table[cur_insn].type == INSN_CPU0 && 935 !(ctrl_cpu_rev[0].set & insn_table[cur_insn].flag)) || 936 (insn_table[cur_insn].type == INSN_CPU1 && 937 !(ctrl_cpu_rev[1].set & insn_table[cur_insn].flag))) { 938 /* skip hlt, it stalls the guest and is tested below */ 939 if (insn_table[cur_insn].insn_func != insn_hlt) 940 insn_table[cur_insn].insn_func(); 941 report("execute %s", vmx_get_test_stage() == cur_insn * 2, 942 insn_table[cur_insn].name); 943 } else if (insn_table[cur_insn].type != INSN_ALWAYS_TRAP) 944 printf("\tCPU_CTRL%d.CPU_%s always traps.\n", 945 insn_table[cur_insn].type - INSN_CPU0, 946 insn_table[cur_insn].name); 947 948 vmcall(); 949 950 insn_table[cur_insn].insn_func(); 951 report("intercept %s", vmx_get_test_stage() == cur_insn * 2 + 1, 952 insn_table[cur_insn].name); 953 954 vmx_set_test_stage(cur_insn * 2 + 1); 955 vmcall(); 956 } 957 } 958 959 static int insn_intercept_exit_handler(void) 960 { 961 u64 guest_rip; 962 u32 reason; 963 ulong exit_qual; 964 u32 insn_len; 965 u32 insn_info; 966 bool pass; 967 968 guest_rip = vmcs_read(GUEST_RIP); 969 reason = vmcs_read(EXI_REASON) & 0xff; 970 exit_qual = vmcs_read(EXI_QUALIFICATION); 971 insn_len = vmcs_read(EXI_INST_LEN); 972 insn_info = vmcs_read(EXI_INST_INFO); 973 974 if (reason == VMX_VMCALL) { 975 u32 val = 0; 976 977 if (insn_table[cur_insn].type == INSN_CPU0) 978 val = vmcs_read(CPU_EXEC_CTRL0); 979 else if (insn_table[cur_insn].type == INSN_CPU1) 980 val = vmcs_read(CPU_EXEC_CTRL1); 981 982 if (vmx_get_test_stage() & 1) 983 val &= ~insn_table[cur_insn].flag; 984 else 985 val |= insn_table[cur_insn].flag; 986 987 if (insn_table[cur_insn].type == INSN_CPU0) 988 vmcs_write(CPU_EXEC_CTRL0, val | ctrl_cpu_rev[0].set); 989 else if (insn_table[cur_insn].type == INSN_CPU1) 990 vmcs_write(CPU_EXEC_CTRL1, val | ctrl_cpu_rev[1].set); 991 } else { 992 pass = (cur_insn * 2 == vmx_get_test_stage()) && 993 insn_table[cur_insn].reason == reason; 994 if (insn_table[cur_insn].test_field & FIELD_EXIT_QUAL && 995 insn_table[cur_insn].exit_qual != exit_qual) 996 pass = false; 997 if (insn_table[cur_insn].test_field & FIELD_INSN_INFO && 998 insn_table[cur_insn].insn_info != insn_info) 999 pass = false; 1000 if (pass) 1001 vmx_inc_test_stage(); 1002 } 1003 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1004 return VMX_TEST_RESUME; 1005 } 1006 1007 1008 /* Enables EPT and sets up the identity map. */ 1009 static int setup_ept(bool enable_ad) 1010 { 1011 unsigned long end_of_memory; 1012 1013 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1014 !(ctrl_cpu_rev[1].clr & CPU_EPT)) { 1015 printf("\tEPT is not supported"); 1016 return 1; 1017 } 1018 1019 1020 if (!(ept_vpid.val & EPT_CAP_UC) && 1021 !(ept_vpid.val & EPT_CAP_WB)) { 1022 printf("\tEPT paging-structure memory type " 1023 "UC&WB are not supported\n"); 1024 return 1; 1025 } 1026 if (ept_vpid.val & EPT_CAP_UC) 1027 eptp = EPT_MEM_TYPE_UC; 1028 else 1029 eptp = EPT_MEM_TYPE_WB; 1030 if (!(ept_vpid.val & EPT_CAP_PWL4)) { 1031 printf("\tPWL4 is not supported\n"); 1032 return 1; 1033 } 1034 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0)| CPU_SECONDARY); 1035 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1)| CPU_EPT); 1036 eptp |= (3 << EPTP_PG_WALK_LEN_SHIFT); 1037 pml4 = alloc_page(); 1038 memset(pml4, 0, PAGE_SIZE); 1039 eptp |= virt_to_phys(pml4); 1040 if (enable_ad) 1041 eptp |= EPTP_AD_FLAG; 1042 vmcs_write(EPTP, eptp); 1043 end_of_memory = fwcfg_get_u64(FW_CFG_RAM_SIZE); 1044 if (end_of_memory < (1ul << 32)) 1045 end_of_memory = (1ul << 32); 1046 /* Cannot use large EPT pages if we need to track EPT 1047 * accessed/dirty bits at 4K granularity. 1048 */ 1049 setup_ept_range(pml4, 0, end_of_memory, 0, 1050 !enable_ad && ept_2m_supported(), 1051 EPT_WA | EPT_RA | EPT_EA); 1052 return 0; 1053 } 1054 1055 static void ept_enable_ad_bits(void) 1056 { 1057 eptp |= EPTP_AD_FLAG; 1058 vmcs_write(EPTP, eptp); 1059 } 1060 1061 static void ept_disable_ad_bits(void) 1062 { 1063 eptp &= ~EPTP_AD_FLAG; 1064 vmcs_write(EPTP, eptp); 1065 } 1066 1067 static void ept_enable_ad_bits_or_skip_test(void) 1068 { 1069 if (!ept_ad_bits_supported()) 1070 test_skip("EPT AD bits not supported."); 1071 ept_enable_ad_bits(); 1072 } 1073 1074 static int apic_version; 1075 1076 static int ept_init_common(bool have_ad) 1077 { 1078 int ret; 1079 struct pci_dev pcidev; 1080 1081 if (setup_ept(have_ad)) 1082 return VMX_TEST_EXIT; 1083 data_page1 = alloc_page(); 1084 data_page2 = alloc_page(); 1085 memset(data_page1, 0x0, PAGE_SIZE); 1086 memset(data_page2, 0x0, PAGE_SIZE); 1087 *((u32 *)data_page1) = MAGIC_VAL_1; 1088 *((u32 *)data_page2) = MAGIC_VAL_2; 1089 install_ept(pml4, (unsigned long)data_page1, (unsigned long)data_page2, 1090 EPT_RA | EPT_WA | EPT_EA); 1091 1092 apic_version = apic_read(APIC_LVR); 1093 1094 ret = pci_find_dev(PCI_VENDOR_ID_REDHAT, PCI_DEVICE_ID_REDHAT_TEST); 1095 if (ret != PCIDEVADDR_INVALID) { 1096 pci_dev_init(&pcidev, ret); 1097 pci_physaddr = pcidev.resource[PCI_TESTDEV_BAR_MEM]; 1098 } 1099 1100 return VMX_TEST_START; 1101 } 1102 1103 static int ept_init(struct vmcs *vmcs) 1104 { 1105 return ept_init_common(false); 1106 } 1107 1108 static void ept_common(void) 1109 { 1110 vmx_set_test_stage(0); 1111 if (*((u32 *)data_page2) != MAGIC_VAL_1 || 1112 *((u32 *)data_page1) != MAGIC_VAL_1) 1113 report("EPT basic framework - read", 0); 1114 else { 1115 *((u32 *)data_page2) = MAGIC_VAL_3; 1116 vmcall(); 1117 if (vmx_get_test_stage() == 1) { 1118 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1119 *((u32 *)data_page2) == MAGIC_VAL_2) 1120 report("EPT basic framework", 1); 1121 else 1122 report("EPT basic framework - remap", 1); 1123 } 1124 } 1125 // Test EPT Misconfigurations 1126 vmx_set_test_stage(1); 1127 vmcall(); 1128 *((u32 *)data_page1) = MAGIC_VAL_1; 1129 if (vmx_get_test_stage() != 2) { 1130 report("EPT misconfigurations", 0); 1131 goto t1; 1132 } 1133 vmx_set_test_stage(2); 1134 vmcall(); 1135 *((u32 *)data_page1) = MAGIC_VAL_1; 1136 report("EPT misconfigurations", vmx_get_test_stage() == 3); 1137 t1: 1138 // Test EPT violation 1139 vmx_set_test_stage(3); 1140 vmcall(); 1141 *((u32 *)data_page1) = MAGIC_VAL_1; 1142 report("EPT violation - page permission", vmx_get_test_stage() == 4); 1143 // Violation caused by EPT paging structure 1144 vmx_set_test_stage(4); 1145 vmcall(); 1146 *((u32 *)data_page1) = MAGIC_VAL_2; 1147 report("EPT violation - paging structure", vmx_get_test_stage() == 5); 1148 1149 // MMIO Read/Write 1150 vmx_set_test_stage(5); 1151 vmcall(); 1152 1153 *(u32 volatile *)pci_physaddr; 1154 report("MMIO EPT violation - read", vmx_get_test_stage() == 6); 1155 1156 *(u32 volatile *)pci_physaddr = MAGIC_VAL_1; 1157 report("MMIO EPT violation - write", vmx_get_test_stage() == 7); 1158 } 1159 1160 static void ept_main(void) 1161 { 1162 ept_common(); 1163 1164 // Test EPT access to L1 MMIO 1165 vmx_set_test_stage(7); 1166 report("EPT - MMIO access", *((u32 *)0xfee00030UL) == apic_version); 1167 1168 // Test invalid operand for INVEPT 1169 vmcall(); 1170 report("EPT - unsupported INVEPT", vmx_get_test_stage() == 8); 1171 } 1172 1173 static bool invept_test(int type, u64 eptp) 1174 { 1175 bool ret, supported; 1176 1177 supported = ept_vpid.val & (EPT_CAP_INVEPT_SINGLE >> INVEPT_SINGLE << type); 1178 ret = invept(type, eptp); 1179 1180 if (ret == !supported) 1181 return false; 1182 1183 if (!supported) 1184 printf("WARNING: unsupported invept passed!\n"); 1185 else 1186 printf("WARNING: invept failed!\n"); 1187 1188 return true; 1189 } 1190 1191 static int pml_exit_handler(void) 1192 { 1193 u16 index, count; 1194 ulong reason = vmcs_read(EXI_REASON) & 0xff; 1195 u64 *pmlbuf = pml_log; 1196 u64 guest_rip = vmcs_read(GUEST_RIP);; 1197 u64 guest_cr3 = vmcs_read(GUEST_CR3); 1198 u32 insn_len = vmcs_read(EXI_INST_LEN); 1199 1200 switch (reason) { 1201 case VMX_VMCALL: 1202 switch (vmx_get_test_stage()) { 1203 case 0: 1204 index = vmcs_read(GUEST_PML_INDEX); 1205 for (count = index + 1; count < PML_INDEX; count++) { 1206 if (pmlbuf[count] == (u64)data_page2) { 1207 vmx_inc_test_stage(); 1208 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1209 break; 1210 } 1211 } 1212 break; 1213 case 1: 1214 index = vmcs_read(GUEST_PML_INDEX); 1215 /* Keep clearing the dirty bit till a overflow */ 1216 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1217 break; 1218 default: 1219 report("unexpected stage, %d.", false, 1220 vmx_get_test_stage()); 1221 print_vmexit_info(); 1222 return VMX_TEST_VMEXIT; 1223 } 1224 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1225 return VMX_TEST_RESUME; 1226 case VMX_PML_FULL: 1227 vmx_inc_test_stage(); 1228 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1229 return VMX_TEST_RESUME; 1230 default: 1231 report("Unknown exit reason, %ld", false, reason); 1232 print_vmexit_info(); 1233 } 1234 return VMX_TEST_VMEXIT; 1235 } 1236 1237 static int ept_exit_handler_common(bool have_ad) 1238 { 1239 u64 guest_rip; 1240 u64 guest_cr3; 1241 ulong reason; 1242 u32 insn_len; 1243 u32 exit_qual; 1244 static unsigned long data_page1_pte, data_page1_pte_pte, memaddr_pte; 1245 1246 guest_rip = vmcs_read(GUEST_RIP); 1247 guest_cr3 = vmcs_read(GUEST_CR3); 1248 reason = vmcs_read(EXI_REASON) & 0xff; 1249 insn_len = vmcs_read(EXI_INST_LEN); 1250 exit_qual = vmcs_read(EXI_QUALIFICATION); 1251 switch (reason) { 1252 case VMX_VMCALL: 1253 switch (vmx_get_test_stage()) { 1254 case 0: 1255 check_ept_ad(pml4, guest_cr3, 1256 (unsigned long)data_page1, 1257 have_ad ? EPT_ACCESS_FLAG : 0, 1258 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1259 check_ept_ad(pml4, guest_cr3, 1260 (unsigned long)data_page2, 1261 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0, 1262 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1263 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1264 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1265 if (have_ad) 1266 ept_sync(INVEPT_SINGLE, eptp);; 1267 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1268 *((u32 *)data_page2) == MAGIC_VAL_2) { 1269 vmx_inc_test_stage(); 1270 install_ept(pml4, (unsigned long)data_page2, 1271 (unsigned long)data_page2, 1272 EPT_RA | EPT_WA | EPT_EA); 1273 } else 1274 report("EPT basic framework - write", 0); 1275 break; 1276 case 1: 1277 install_ept(pml4, (unsigned long)data_page1, 1278 (unsigned long)data_page1, EPT_WA); 1279 ept_sync(INVEPT_SINGLE, eptp); 1280 break; 1281 case 2: 1282 install_ept(pml4, (unsigned long)data_page1, 1283 (unsigned long)data_page1, 1284 EPT_RA | EPT_WA | EPT_EA | 1285 (2 << EPT_MEM_TYPE_SHIFT)); 1286 ept_sync(INVEPT_SINGLE, eptp); 1287 break; 1288 case 3: 1289 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1290 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)data_page1, 1291 1, &data_page1_pte)); 1292 set_ept_pte(pml4, (unsigned long)data_page1, 1293 1, data_page1_pte & ~EPT_PRESENT); 1294 ept_sync(INVEPT_SINGLE, eptp); 1295 break; 1296 case 4: 1297 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)data_page1, 1298 2, &data_page1_pte)); 1299 data_page1_pte &= PAGE_MASK; 1300 TEST_ASSERT(get_ept_pte(pml4, data_page1_pte, 1301 2, &data_page1_pte_pte)); 1302 set_ept_pte(pml4, data_page1_pte, 2, 1303 data_page1_pte_pte & ~EPT_PRESENT); 1304 ept_sync(INVEPT_SINGLE, eptp); 1305 break; 1306 case 5: 1307 install_ept(pml4, (unsigned long)pci_physaddr, 1308 (unsigned long)pci_physaddr, 0); 1309 ept_sync(INVEPT_SINGLE, eptp); 1310 break; 1311 case 7: 1312 if (!invept_test(0, eptp)) 1313 vmx_inc_test_stage(); 1314 break; 1315 // Should not reach here 1316 default: 1317 report("ERROR - unexpected stage, %d.", false, 1318 vmx_get_test_stage()); 1319 print_vmexit_info(); 1320 return VMX_TEST_VMEXIT; 1321 } 1322 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1323 return VMX_TEST_RESUME; 1324 case VMX_EPT_MISCONFIG: 1325 switch (vmx_get_test_stage()) { 1326 case 1: 1327 case 2: 1328 vmx_inc_test_stage(); 1329 install_ept(pml4, (unsigned long)data_page1, 1330 (unsigned long)data_page1, 1331 EPT_RA | EPT_WA | EPT_EA); 1332 ept_sync(INVEPT_SINGLE, eptp); 1333 break; 1334 // Should not reach here 1335 default: 1336 report("ERROR - unexpected stage, %d.", false, 1337 vmx_get_test_stage()); 1338 print_vmexit_info(); 1339 return VMX_TEST_VMEXIT; 1340 } 1341 return VMX_TEST_RESUME; 1342 case VMX_EPT_VIOLATION: 1343 switch(vmx_get_test_stage()) { 1344 case 3: 1345 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1346 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1347 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1348 if (exit_qual == (EPT_VLT_WR | EPT_VLT_LADDR_VLD | 1349 EPT_VLT_PADDR)) 1350 vmx_inc_test_stage(); 1351 set_ept_pte(pml4, (unsigned long)data_page1, 1352 1, data_page1_pte | (EPT_PRESENT)); 1353 ept_sync(INVEPT_SINGLE, eptp); 1354 break; 1355 case 4: 1356 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1357 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1358 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1359 if (exit_qual == (EPT_VLT_RD | 1360 (have_ad ? EPT_VLT_WR : 0) | 1361 EPT_VLT_LADDR_VLD)) 1362 vmx_inc_test_stage(); 1363 set_ept_pte(pml4, data_page1_pte, 2, 1364 data_page1_pte_pte | (EPT_PRESENT)); 1365 ept_sync(INVEPT_SINGLE, eptp); 1366 break; 1367 case 5: 1368 if (exit_qual & EPT_VLT_RD) 1369 vmx_inc_test_stage(); 1370 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1371 1, &memaddr_pte)); 1372 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA); 1373 ept_sync(INVEPT_SINGLE, eptp); 1374 break; 1375 case 6: 1376 if (exit_qual & EPT_VLT_WR) 1377 vmx_inc_test_stage(); 1378 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1379 1, &memaddr_pte)); 1380 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA | EPT_WA); 1381 ept_sync(INVEPT_SINGLE, eptp); 1382 break; 1383 default: 1384 // Should not reach here 1385 report("ERROR : unexpected stage, %d", false, 1386 vmx_get_test_stage()); 1387 print_vmexit_info(); 1388 return VMX_TEST_VMEXIT; 1389 } 1390 return VMX_TEST_RESUME; 1391 default: 1392 report("Unknown exit reason, %ld", false, reason); 1393 print_vmexit_info(); 1394 } 1395 return VMX_TEST_VMEXIT; 1396 } 1397 1398 static int ept_exit_handler(void) 1399 { 1400 return ept_exit_handler_common(false); 1401 } 1402 1403 static int eptad_init(struct vmcs *vmcs) 1404 { 1405 int r = ept_init_common(true); 1406 1407 if (r == VMX_TEST_EXIT) 1408 return r; 1409 1410 if ((rdmsr(MSR_IA32_VMX_EPT_VPID_CAP) & EPT_CAP_AD_FLAG) == 0) { 1411 printf("\tEPT A/D bits are not supported"); 1412 return VMX_TEST_EXIT; 1413 } 1414 1415 return r; 1416 } 1417 1418 static int pml_init(struct vmcs *vmcs) 1419 { 1420 u32 ctrl_cpu; 1421 int r = eptad_init(vmcs); 1422 1423 if (r == VMX_TEST_EXIT) 1424 return r; 1425 1426 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1427 !(ctrl_cpu_rev[1].clr & CPU_PML)) { 1428 printf("\tPML is not supported"); 1429 return VMX_TEST_EXIT; 1430 } 1431 1432 pml_log = alloc_page(); 1433 memset(pml_log, 0x0, PAGE_SIZE); 1434 vmcs_write(PMLADDR, (u64)pml_log); 1435 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1436 1437 ctrl_cpu = vmcs_read(CPU_EXEC_CTRL1) | CPU_PML; 1438 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu); 1439 1440 return VMX_TEST_START; 1441 } 1442 1443 static void pml_main(void) 1444 { 1445 int count = 0; 1446 1447 vmx_set_test_stage(0); 1448 *((u32 *)data_page2) = 0x1; 1449 vmcall(); 1450 report("PML - Dirty GPA Logging", vmx_get_test_stage() == 1); 1451 1452 while (vmx_get_test_stage() == 1) { 1453 vmcall(); 1454 *((u32 *)data_page2) = 0x1; 1455 if (count++ > PML_INDEX) 1456 break; 1457 } 1458 report("PML Full Event", vmx_get_test_stage() == 2); 1459 } 1460 1461 static void eptad_main(void) 1462 { 1463 ept_common(); 1464 } 1465 1466 static int eptad_exit_handler(void) 1467 { 1468 return ept_exit_handler_common(true); 1469 } 1470 1471 static bool invvpid_test(int type, u16 vpid) 1472 { 1473 bool ret, supported; 1474 1475 supported = ept_vpid.val & 1476 (VPID_CAP_INVVPID_ADDR >> INVVPID_ADDR << type); 1477 ret = invvpid(type, vpid, 0); 1478 1479 if (ret == !supported) 1480 return false; 1481 1482 if (!supported) 1483 printf("WARNING: unsupported invvpid passed!\n"); 1484 else 1485 printf("WARNING: invvpid failed!\n"); 1486 1487 return true; 1488 } 1489 1490 static int vpid_init(struct vmcs *vmcs) 1491 { 1492 u32 ctrl_cpu1; 1493 1494 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1495 !(ctrl_cpu_rev[1].clr & CPU_VPID)) { 1496 printf("\tVPID is not supported"); 1497 return VMX_TEST_EXIT; 1498 } 1499 1500 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 1501 ctrl_cpu1 |= CPU_VPID; 1502 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 1503 return VMX_TEST_START; 1504 } 1505 1506 static void vpid_main(void) 1507 { 1508 vmx_set_test_stage(0); 1509 vmcall(); 1510 report("INVVPID SINGLE ADDRESS", vmx_get_test_stage() == 1); 1511 vmx_set_test_stage(2); 1512 vmcall(); 1513 report("INVVPID SINGLE", vmx_get_test_stage() == 3); 1514 vmx_set_test_stage(4); 1515 vmcall(); 1516 report("INVVPID ALL", vmx_get_test_stage() == 5); 1517 } 1518 1519 static int vpid_exit_handler(void) 1520 { 1521 u64 guest_rip; 1522 ulong reason; 1523 u32 insn_len; 1524 1525 guest_rip = vmcs_read(GUEST_RIP); 1526 reason = vmcs_read(EXI_REASON) & 0xff; 1527 insn_len = vmcs_read(EXI_INST_LEN); 1528 1529 switch (reason) { 1530 case VMX_VMCALL: 1531 switch(vmx_get_test_stage()) { 1532 case 0: 1533 if (!invvpid_test(INVVPID_ADDR, 1)) 1534 vmx_inc_test_stage(); 1535 break; 1536 case 2: 1537 if (!invvpid_test(INVVPID_CONTEXT_GLOBAL, 1)) 1538 vmx_inc_test_stage(); 1539 break; 1540 case 4: 1541 if (!invvpid_test(INVVPID_ALL, 1)) 1542 vmx_inc_test_stage(); 1543 break; 1544 default: 1545 report("ERROR: unexpected stage, %d", false, 1546 vmx_get_test_stage()); 1547 print_vmexit_info(); 1548 return VMX_TEST_VMEXIT; 1549 } 1550 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1551 return VMX_TEST_RESUME; 1552 default: 1553 report("Unknown exit reason, %ld", false, reason); 1554 print_vmexit_info(); 1555 } 1556 return VMX_TEST_VMEXIT; 1557 } 1558 1559 #define TIMER_VECTOR 222 1560 1561 static volatile bool timer_fired; 1562 1563 static void timer_isr(isr_regs_t *regs) 1564 { 1565 timer_fired = true; 1566 apic_write(APIC_EOI, 0); 1567 } 1568 1569 static int interrupt_init(struct vmcs *vmcs) 1570 { 1571 msr_bmp_init(); 1572 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1573 handle_irq(TIMER_VECTOR, timer_isr); 1574 return VMX_TEST_START; 1575 } 1576 1577 static void interrupt_main(void) 1578 { 1579 long long start, loops; 1580 1581 vmx_set_test_stage(0); 1582 1583 apic_write(APIC_LVTT, TIMER_VECTOR); 1584 irq_enable(); 1585 1586 apic_write(APIC_TMICT, 1); 1587 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1588 asm volatile ("nop"); 1589 report("direct interrupt while running guest", timer_fired); 1590 1591 apic_write(APIC_TMICT, 0); 1592 irq_disable(); 1593 vmcall(); 1594 timer_fired = false; 1595 apic_write(APIC_TMICT, 1); 1596 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1597 asm volatile ("nop"); 1598 report("intercepted interrupt while running guest", timer_fired); 1599 1600 irq_enable(); 1601 apic_write(APIC_TMICT, 0); 1602 irq_disable(); 1603 vmcall(); 1604 timer_fired = false; 1605 start = rdtsc(); 1606 apic_write(APIC_TMICT, 1000000); 1607 1608 asm volatile ("sti; hlt"); 1609 1610 report("direct interrupt + hlt", 1611 rdtsc() - start > 1000000 && timer_fired); 1612 1613 apic_write(APIC_TMICT, 0); 1614 irq_disable(); 1615 vmcall(); 1616 timer_fired = false; 1617 start = rdtsc(); 1618 apic_write(APIC_TMICT, 1000000); 1619 1620 asm volatile ("sti; hlt"); 1621 1622 report("intercepted interrupt + hlt", 1623 rdtsc() - start > 10000 && timer_fired); 1624 1625 apic_write(APIC_TMICT, 0); 1626 irq_disable(); 1627 vmcall(); 1628 timer_fired = false; 1629 start = rdtsc(); 1630 apic_write(APIC_TMICT, 1000000); 1631 1632 irq_enable(); 1633 asm volatile ("nop"); 1634 vmcall(); 1635 1636 report("direct interrupt + activity state hlt", 1637 rdtsc() - start > 10000 && timer_fired); 1638 1639 apic_write(APIC_TMICT, 0); 1640 irq_disable(); 1641 vmcall(); 1642 timer_fired = false; 1643 start = rdtsc(); 1644 apic_write(APIC_TMICT, 1000000); 1645 1646 irq_enable(); 1647 asm volatile ("nop"); 1648 vmcall(); 1649 1650 report("intercepted interrupt + activity state hlt", 1651 rdtsc() - start > 10000 && timer_fired); 1652 1653 apic_write(APIC_TMICT, 0); 1654 irq_disable(); 1655 vmx_set_test_stage(7); 1656 vmcall(); 1657 timer_fired = false; 1658 apic_write(APIC_TMICT, 1); 1659 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1660 asm volatile ("nop"); 1661 report("running a guest with interrupt acknowledgement set", timer_fired); 1662 1663 apic_write(APIC_TMICT, 0); 1664 irq_enable(); 1665 timer_fired = false; 1666 vmcall(); 1667 report("Inject an event to a halted guest", timer_fired); 1668 } 1669 1670 static int interrupt_exit_handler(void) 1671 { 1672 u64 guest_rip = vmcs_read(GUEST_RIP); 1673 ulong reason = vmcs_read(EXI_REASON) & 0xff; 1674 u32 insn_len = vmcs_read(EXI_INST_LEN); 1675 1676 switch (reason) { 1677 case VMX_VMCALL: 1678 switch (vmx_get_test_stage()) { 1679 case 0: 1680 case 2: 1681 case 5: 1682 vmcs_write(PIN_CONTROLS, 1683 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1684 break; 1685 case 7: 1686 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_INTA); 1687 vmcs_write(PIN_CONTROLS, 1688 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1689 break; 1690 case 1: 1691 case 3: 1692 vmcs_write(PIN_CONTROLS, 1693 vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1694 break; 1695 case 4: 1696 case 6: 1697 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1698 break; 1699 1700 case 8: 1701 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1702 vmcs_write(ENT_INTR_INFO, 1703 TIMER_VECTOR | 1704 (VMX_INTR_TYPE_EXT_INTR << INTR_INFO_INTR_TYPE_SHIFT) | 1705 INTR_INFO_VALID_MASK); 1706 break; 1707 } 1708 vmx_inc_test_stage(); 1709 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1710 return VMX_TEST_RESUME; 1711 case VMX_EXTINT: 1712 if (vmcs_read(EXI_CONTROLS) & EXI_INTA) { 1713 int vector = vmcs_read(EXI_INTR_INFO) & 0xff; 1714 handle_external_interrupt(vector); 1715 } else { 1716 irq_enable(); 1717 asm volatile ("nop"); 1718 irq_disable(); 1719 } 1720 if (vmx_get_test_stage() >= 2) 1721 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 1722 return VMX_TEST_RESUME; 1723 default: 1724 report("Unknown exit reason, %ld", false, reason); 1725 print_vmexit_info(); 1726 } 1727 1728 return VMX_TEST_VMEXIT; 1729 } 1730 1731 static int dbgctls_init(struct vmcs *vmcs) 1732 { 1733 u64 dr7 = 0x402; 1734 u64 zero = 0; 1735 1736 msr_bmp_init(); 1737 asm volatile( 1738 "mov %0,%%dr0\n\t" 1739 "mov %0,%%dr1\n\t" 1740 "mov %0,%%dr2\n\t" 1741 "mov %1,%%dr7\n\t" 1742 : : "r" (zero), "r" (dr7)); 1743 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1744 vmcs_write(GUEST_DR7, 0x404); 1745 vmcs_write(GUEST_DEBUGCTL, 0x2); 1746 1747 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 1748 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_SAVE_DBGCTLS); 1749 1750 return VMX_TEST_START; 1751 } 1752 1753 static void dbgctls_main(void) 1754 { 1755 u64 dr7, debugctl; 1756 1757 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1758 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1759 /* Commented out: KVM does not support DEBUGCTL so far */ 1760 (void)debugctl; 1761 report("Load debug controls", dr7 == 0x404 /* && debugctl == 0x2 */); 1762 1763 dr7 = 0x408; 1764 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1765 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1766 1767 vmx_set_test_stage(0); 1768 vmcall(); 1769 report("Save debug controls", vmx_get_test_stage() == 1); 1770 1771 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS || 1772 ctrl_exit_rev.set & EXI_SAVE_DBGCTLS) { 1773 printf("\tDebug controls are always loaded/saved\n"); 1774 return; 1775 } 1776 vmx_set_test_stage(2); 1777 vmcall(); 1778 1779 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1780 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1781 /* Commented out: KVM does not support DEBUGCTL so far */ 1782 (void)debugctl; 1783 report("Guest=host debug controls", dr7 == 0x402 /* && debugctl == 0x1 */); 1784 1785 dr7 = 0x408; 1786 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1787 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1788 1789 vmx_set_test_stage(3); 1790 vmcall(); 1791 report("Don't save debug controls", vmx_get_test_stage() == 4); 1792 } 1793 1794 static int dbgctls_exit_handler(void) 1795 { 1796 unsigned int reason = vmcs_read(EXI_REASON) & 0xff; 1797 u32 insn_len = vmcs_read(EXI_INST_LEN); 1798 u64 guest_rip = vmcs_read(GUEST_RIP); 1799 u64 dr7, debugctl; 1800 1801 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1802 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1803 1804 switch (reason) { 1805 case VMX_VMCALL: 1806 switch (vmx_get_test_stage()) { 1807 case 0: 1808 if (dr7 == 0x400 && debugctl == 0 && 1809 vmcs_read(GUEST_DR7) == 0x408 /* && 1810 Commented out: KVM does not support DEBUGCTL so far 1811 vmcs_read(GUEST_DEBUGCTL) == 0x3 */) 1812 vmx_inc_test_stage(); 1813 break; 1814 case 2: 1815 dr7 = 0x402; 1816 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1817 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1818 vmcs_write(GUEST_DR7, 0x404); 1819 vmcs_write(GUEST_DEBUGCTL, 0x2); 1820 1821 vmcs_write(ENT_CONTROLS, 1822 vmcs_read(ENT_CONTROLS) & ~ENT_LOAD_DBGCTLS); 1823 vmcs_write(EXI_CONTROLS, 1824 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_DBGCTLS); 1825 break; 1826 case 3: 1827 if (dr7 == 0x400 && debugctl == 0 && 1828 vmcs_read(GUEST_DR7) == 0x404 /* && 1829 Commented out: KVM does not support DEBUGCTL so far 1830 vmcs_read(GUEST_DEBUGCTL) == 0x2 */) 1831 vmx_inc_test_stage(); 1832 break; 1833 } 1834 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1835 return VMX_TEST_RESUME; 1836 default: 1837 report("Unknown exit reason, %d", false, reason); 1838 print_vmexit_info(); 1839 } 1840 return VMX_TEST_VMEXIT; 1841 } 1842 1843 struct vmx_msr_entry { 1844 u32 index; 1845 u32 reserved; 1846 u64 value; 1847 } __attribute__((packed)); 1848 1849 #define MSR_MAGIC 0x31415926 1850 struct vmx_msr_entry *exit_msr_store, *entry_msr_load, *exit_msr_load; 1851 1852 static int msr_switch_init(struct vmcs *vmcs) 1853 { 1854 msr_bmp_init(); 1855 exit_msr_store = alloc_page(); 1856 exit_msr_load = alloc_page(); 1857 entry_msr_load = alloc_page(); 1858 memset(exit_msr_store, 0, PAGE_SIZE); 1859 memset(exit_msr_load, 0, PAGE_SIZE); 1860 memset(entry_msr_load, 0, PAGE_SIZE); 1861 entry_msr_load[0].index = MSR_KERNEL_GS_BASE; 1862 entry_msr_load[0].value = MSR_MAGIC; 1863 1864 vmx_set_test_stage(1); 1865 vmcs_write(ENT_MSR_LD_CNT, 1); 1866 vmcs_write(ENTER_MSR_LD_ADDR, (u64)entry_msr_load); 1867 vmcs_write(EXI_MSR_ST_CNT, 1); 1868 vmcs_write(EXIT_MSR_ST_ADDR, (u64)exit_msr_store); 1869 vmcs_write(EXI_MSR_LD_CNT, 1); 1870 vmcs_write(EXIT_MSR_LD_ADDR, (u64)exit_msr_load); 1871 return VMX_TEST_START; 1872 } 1873 1874 static void msr_switch_main(void) 1875 { 1876 if (vmx_get_test_stage() == 1) { 1877 report("VM entry MSR load", 1878 rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC); 1879 vmx_set_test_stage(2); 1880 wrmsr(MSR_KERNEL_GS_BASE, MSR_MAGIC + 1); 1881 exit_msr_store[0].index = MSR_KERNEL_GS_BASE; 1882 exit_msr_load[0].index = MSR_KERNEL_GS_BASE; 1883 exit_msr_load[0].value = MSR_MAGIC + 2; 1884 } 1885 vmcall(); 1886 } 1887 1888 static int msr_switch_exit_handler(void) 1889 { 1890 ulong reason; 1891 1892 reason = vmcs_read(EXI_REASON); 1893 if (reason == VMX_VMCALL && vmx_get_test_stage() == 2) { 1894 report("VM exit MSR store", 1895 exit_msr_store[0].value == MSR_MAGIC + 1); 1896 report("VM exit MSR load", 1897 rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC + 2); 1898 vmx_set_test_stage(3); 1899 entry_msr_load[0].index = MSR_FS_BASE; 1900 return VMX_TEST_RESUME; 1901 } 1902 printf("ERROR %s: unexpected stage=%u or reason=%lu\n", 1903 __func__, vmx_get_test_stage(), reason); 1904 return VMX_TEST_EXIT; 1905 } 1906 1907 static int msr_switch_entry_failure(struct vmentry_failure *failure) 1908 { 1909 ulong reason; 1910 1911 if (failure->early) { 1912 printf("ERROR %s: early exit\n", __func__); 1913 return VMX_TEST_EXIT; 1914 } 1915 1916 reason = vmcs_read(EXI_REASON); 1917 if (reason == (VMX_ENTRY_FAILURE | VMX_FAIL_MSR) && 1918 vmx_get_test_stage() == 3) { 1919 report("VM entry MSR load: try to load FS_BASE", 1920 vmcs_read(EXI_QUALIFICATION) == 1); 1921 return VMX_TEST_VMEXIT; 1922 } 1923 printf("ERROR %s: unexpected stage=%u or reason=%lu\n", 1924 __func__, vmx_get_test_stage(), reason); 1925 return VMX_TEST_EXIT; 1926 } 1927 1928 static int vmmcall_init(struct vmcs *vmcs) 1929 { 1930 vmcs_write(EXC_BITMAP, 1 << UD_VECTOR); 1931 return VMX_TEST_START; 1932 } 1933 1934 static void vmmcall_main(void) 1935 { 1936 asm volatile( 1937 "mov $0xABCD, %%rax\n\t" 1938 "vmmcall\n\t" 1939 ::: "rax"); 1940 1941 report("VMMCALL", 0); 1942 } 1943 1944 static int vmmcall_exit_handler(void) 1945 { 1946 ulong reason; 1947 1948 reason = vmcs_read(EXI_REASON); 1949 switch (reason) { 1950 case VMX_VMCALL: 1951 printf("here\n"); 1952 report("VMMCALL triggers #UD", 0); 1953 break; 1954 case VMX_EXC_NMI: 1955 report("VMMCALL triggers #UD", 1956 (vmcs_read(EXI_INTR_INFO) & 0xff) == UD_VECTOR); 1957 break; 1958 default: 1959 report("Unknown exit reason, %ld", false, reason); 1960 print_vmexit_info(); 1961 } 1962 1963 return VMX_TEST_VMEXIT; 1964 } 1965 1966 static int disable_rdtscp_init(struct vmcs *vmcs) 1967 { 1968 u32 ctrl_cpu1; 1969 1970 if (ctrl_cpu_rev[0].clr & CPU_SECONDARY) { 1971 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 1972 ctrl_cpu1 &= ~CPU_RDTSCP; 1973 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 1974 } 1975 1976 return VMX_TEST_START; 1977 } 1978 1979 static void disable_rdtscp_ud_handler(struct ex_regs *regs) 1980 { 1981 switch (vmx_get_test_stage()) { 1982 case 0: 1983 report("RDTSCP triggers #UD", true); 1984 vmx_inc_test_stage(); 1985 regs->rip += 3; 1986 break; 1987 case 2: 1988 report("RDPID triggers #UD", true); 1989 vmx_inc_test_stage(); 1990 regs->rip += 4; 1991 break; 1992 } 1993 return; 1994 1995 } 1996 1997 static void disable_rdtscp_main(void) 1998 { 1999 /* Test that #UD is properly injected in L2. */ 2000 handle_exception(UD_VECTOR, disable_rdtscp_ud_handler); 2001 2002 vmx_set_test_stage(0); 2003 asm volatile("rdtscp" : : : "eax", "ecx", "edx"); 2004 vmcall(); 2005 asm volatile(".byte 0xf3, 0x0f, 0xc7, 0xf8" : : : "eax"); 2006 2007 handle_exception(UD_VECTOR, 0); 2008 vmcall(); 2009 } 2010 2011 static int disable_rdtscp_exit_handler(void) 2012 { 2013 unsigned int reason = vmcs_read(EXI_REASON) & 0xff; 2014 2015 switch (reason) { 2016 case VMX_VMCALL: 2017 switch (vmx_get_test_stage()) { 2018 case 0: 2019 report("RDTSCP triggers #UD", false); 2020 vmx_inc_test_stage(); 2021 /* fallthrough */ 2022 case 1: 2023 vmx_inc_test_stage(); 2024 vmcs_write(GUEST_RIP, vmcs_read(GUEST_RIP) + 3); 2025 return VMX_TEST_RESUME; 2026 case 2: 2027 report("RDPID triggers #UD", false); 2028 break; 2029 } 2030 break; 2031 2032 default: 2033 report("Unknown exit reason, %d", false, reason); 2034 print_vmexit_info(); 2035 } 2036 return VMX_TEST_VMEXIT; 2037 } 2038 2039 static int int3_init(struct vmcs *vmcs) 2040 { 2041 vmcs_write(EXC_BITMAP, ~0u); 2042 return VMX_TEST_START; 2043 } 2044 2045 static void int3_guest_main(void) 2046 { 2047 asm volatile ("int3"); 2048 } 2049 2050 static int int3_exit_handler(void) 2051 { 2052 u32 reason = vmcs_read(EXI_REASON); 2053 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2054 2055 report("L1 intercepts #BP", reason == VMX_EXC_NMI && 2056 (intr_info & INTR_INFO_VALID_MASK) && 2057 (intr_info & INTR_INFO_VECTOR_MASK) == BP_VECTOR && 2058 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2059 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION); 2060 2061 return VMX_TEST_VMEXIT; 2062 } 2063 2064 static int into_init(struct vmcs *vmcs) 2065 { 2066 vmcs_write(EXC_BITMAP, ~0u); 2067 return VMX_TEST_START; 2068 } 2069 2070 static void into_guest_main(void) 2071 { 2072 struct far_pointer32 fp = { 2073 .offset = (uintptr_t)&&into, 2074 .selector = KERNEL_CS32, 2075 }; 2076 register uintptr_t rsp asm("rsp"); 2077 2078 if (fp.offset != (uintptr_t)&&into) { 2079 printf("Code address too high.\n"); 2080 return; 2081 } 2082 if ((u32)rsp != rsp) { 2083 printf("Stack address too high.\n"); 2084 return; 2085 } 2086 2087 asm goto ("lcall *%0" : : "m" (fp) : "rax" : into); 2088 return; 2089 into: 2090 asm volatile (".code32;" 2091 "movl $0x7fffffff, %eax;" 2092 "addl %eax, %eax;" 2093 "into;" 2094 "lret;" 2095 ".code64"); 2096 __builtin_unreachable(); 2097 } 2098 2099 static int into_exit_handler(void) 2100 { 2101 u32 reason = vmcs_read(EXI_REASON); 2102 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2103 2104 report("L1 intercepts #OF", reason == VMX_EXC_NMI && 2105 (intr_info & INTR_INFO_VALID_MASK) && 2106 (intr_info & INTR_INFO_VECTOR_MASK) == OF_VECTOR && 2107 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2108 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION); 2109 2110 return VMX_TEST_VMEXIT; 2111 } 2112 2113 static void exit_monitor_from_l2_main(void) 2114 { 2115 printf("Calling exit(0) from l2...\n"); 2116 exit(0); 2117 } 2118 2119 static int exit_monitor_from_l2_handler(void) 2120 { 2121 report("The guest should have killed the VMM", false); 2122 return VMX_TEST_EXIT; 2123 } 2124 2125 static void assert_exit_reason(u64 expected) 2126 { 2127 u64 actual = vmcs_read(EXI_REASON); 2128 2129 TEST_ASSERT_EQ_MSG(expected, actual, "Expected %s, got %s.", 2130 exit_reason_description(expected), 2131 exit_reason_description(actual)); 2132 } 2133 2134 static void skip_exit_insn(void) 2135 { 2136 u64 guest_rip = vmcs_read(GUEST_RIP); 2137 u32 insn_len = vmcs_read(EXI_INST_LEN); 2138 vmcs_write(GUEST_RIP, guest_rip + insn_len); 2139 } 2140 2141 static void skip_exit_vmcall(void) 2142 { 2143 assert_exit_reason(VMX_VMCALL); 2144 skip_exit_insn(); 2145 } 2146 2147 static void v2_null_test_guest(void) 2148 { 2149 } 2150 2151 static void v2_null_test(void) 2152 { 2153 test_set_guest(v2_null_test_guest); 2154 enter_guest(); 2155 report(__func__, 1); 2156 } 2157 2158 static void v2_multiple_entries_test_guest(void) 2159 { 2160 vmx_set_test_stage(1); 2161 vmcall(); 2162 vmx_set_test_stage(2); 2163 } 2164 2165 static void v2_multiple_entries_test(void) 2166 { 2167 test_set_guest(v2_multiple_entries_test_guest); 2168 enter_guest(); 2169 TEST_ASSERT_EQ(vmx_get_test_stage(), 1); 2170 skip_exit_vmcall(); 2171 enter_guest(); 2172 TEST_ASSERT_EQ(vmx_get_test_stage(), 2); 2173 report(__func__, 1); 2174 } 2175 2176 static int fixture_test_data = 1; 2177 2178 static void fixture_test_teardown(void *data) 2179 { 2180 *((int *) data) = 1; 2181 } 2182 2183 static void fixture_test_guest(void) 2184 { 2185 fixture_test_data++; 2186 } 2187 2188 2189 static void fixture_test_setup(void) 2190 { 2191 TEST_ASSERT_EQ_MSG(1, fixture_test_data, 2192 "fixture_test_teardown didn't run?!"); 2193 fixture_test_data = 2; 2194 test_add_teardown(fixture_test_teardown, &fixture_test_data); 2195 test_set_guest(fixture_test_guest); 2196 } 2197 2198 static void fixture_test_case1(void) 2199 { 2200 fixture_test_setup(); 2201 TEST_ASSERT_EQ(2, fixture_test_data); 2202 enter_guest(); 2203 TEST_ASSERT_EQ(3, fixture_test_data); 2204 report(__func__, 1); 2205 } 2206 2207 static void fixture_test_case2(void) 2208 { 2209 fixture_test_setup(); 2210 TEST_ASSERT_EQ(2, fixture_test_data); 2211 enter_guest(); 2212 TEST_ASSERT_EQ(3, fixture_test_data); 2213 report(__func__, 1); 2214 } 2215 2216 enum ept_access_op { 2217 OP_READ, 2218 OP_WRITE, 2219 OP_EXEC, 2220 OP_FLUSH_TLB, 2221 OP_EXIT, 2222 }; 2223 2224 static struct ept_access_test_data { 2225 unsigned long gpa; 2226 unsigned long *gva; 2227 unsigned long hpa; 2228 unsigned long *hva; 2229 enum ept_access_op op; 2230 } ept_access_test_data; 2231 2232 extern unsigned char ret42_start; 2233 extern unsigned char ret42_end; 2234 2235 /* Returns 42. */ 2236 asm( 2237 ".align 64\n" 2238 "ret42_start:\n" 2239 "mov $42, %eax\n" 2240 "ret\n" 2241 "ret42_end:\n" 2242 ); 2243 2244 static void 2245 diagnose_ept_violation_qual(u64 expected, u64 actual) 2246 { 2247 2248 #define DIAGNOSE(flag) \ 2249 do { \ 2250 if ((expected & flag) != (actual & flag)) \ 2251 printf(#flag " %sexpected\n", \ 2252 (expected & flag) ? "" : "un"); \ 2253 } while (0) 2254 2255 DIAGNOSE(EPT_VLT_RD); 2256 DIAGNOSE(EPT_VLT_WR); 2257 DIAGNOSE(EPT_VLT_FETCH); 2258 DIAGNOSE(EPT_VLT_PERM_RD); 2259 DIAGNOSE(EPT_VLT_PERM_WR); 2260 DIAGNOSE(EPT_VLT_PERM_EX); 2261 DIAGNOSE(EPT_VLT_LADDR_VLD); 2262 DIAGNOSE(EPT_VLT_PADDR); 2263 2264 #undef DIAGNOSE 2265 } 2266 2267 static void do_ept_access_op(enum ept_access_op op) 2268 { 2269 ept_access_test_data.op = op; 2270 enter_guest(); 2271 } 2272 2273 /* 2274 * Force the guest to flush its TLB (i.e., flush gva -> gpa mappings). Only 2275 * needed by tests that modify guest PTEs. 2276 */ 2277 static void ept_access_test_guest_flush_tlb(void) 2278 { 2279 do_ept_access_op(OP_FLUSH_TLB); 2280 skip_exit_vmcall(); 2281 } 2282 2283 /* 2284 * Modifies the EPT entry at @level in the mapping of @gpa. First clears the 2285 * bits in @clear then sets the bits in @set. @mkhuge transforms the entry into 2286 * a huge page. 2287 */ 2288 static unsigned long ept_twiddle(unsigned long gpa, bool mkhuge, int level, 2289 unsigned long clear, unsigned long set) 2290 { 2291 struct ept_access_test_data *data = &ept_access_test_data; 2292 unsigned long orig_pte; 2293 unsigned long pte; 2294 2295 /* Screw with the mapping at the requested level. */ 2296 TEST_ASSERT(get_ept_pte(pml4, gpa, level, &orig_pte)); 2297 pte = orig_pte; 2298 if (mkhuge) 2299 pte = (orig_pte & ~EPT_ADDR_MASK) | data->hpa | EPT_LARGE_PAGE; 2300 else 2301 pte = orig_pte; 2302 pte = (pte & ~clear) | set; 2303 set_ept_pte(pml4, gpa, level, pte); 2304 ept_sync(INVEPT_SINGLE, eptp); 2305 2306 return orig_pte; 2307 } 2308 2309 static void ept_untwiddle(unsigned long gpa, int level, unsigned long orig_pte) 2310 { 2311 set_ept_pte(pml4, gpa, level, orig_pte); 2312 } 2313 2314 static void do_ept_violation(bool leaf, enum ept_access_op op, 2315 u64 expected_qual, u64 expected_paddr) 2316 { 2317 u64 qual; 2318 2319 /* Try the access and observe the violation. */ 2320 do_ept_access_op(op); 2321 2322 assert_exit_reason(VMX_EPT_VIOLATION); 2323 2324 qual = vmcs_read(EXI_QUALIFICATION); 2325 2326 diagnose_ept_violation_qual(expected_qual, qual); 2327 TEST_EXPECT_EQ(expected_qual, qual); 2328 2329 #if 0 2330 /* Disable for now otherwise every test will fail */ 2331 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2332 (unsigned long) ( 2333 op == OP_EXEC ? data->gva + 1 : data->gva)); 2334 #endif 2335 /* 2336 * TODO: tests that probe expected_paddr in pages other than the one at 2337 * the beginning of the 1g region. 2338 */ 2339 TEST_EXPECT_EQ(vmcs_read(INFO_PHYS_ADDR), expected_paddr); 2340 } 2341 2342 static void 2343 ept_violation_at_level_mkhuge(bool mkhuge, int level, unsigned long clear, 2344 unsigned long set, enum ept_access_op op, 2345 u64 expected_qual) 2346 { 2347 struct ept_access_test_data *data = &ept_access_test_data; 2348 unsigned long orig_pte; 2349 2350 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2351 2352 do_ept_violation(level == 1 || mkhuge, op, expected_qual, 2353 op == OP_EXEC ? data->gpa + sizeof(unsigned long) : 2354 data->gpa); 2355 2356 /* Fix the violation and resume the op loop. */ 2357 ept_untwiddle(data->gpa, level, orig_pte); 2358 enter_guest(); 2359 skip_exit_vmcall(); 2360 } 2361 2362 static void 2363 ept_violation_at_level(int level, unsigned long clear, unsigned long set, 2364 enum ept_access_op op, u64 expected_qual) 2365 { 2366 ept_violation_at_level_mkhuge(false, level, clear, set, op, 2367 expected_qual); 2368 if (ept_huge_pages_supported(level)) 2369 ept_violation_at_level_mkhuge(true, level, clear, set, op, 2370 expected_qual); 2371 } 2372 2373 static void ept_violation(unsigned long clear, unsigned long set, 2374 enum ept_access_op op, u64 expected_qual) 2375 { 2376 ept_violation_at_level(1, clear, set, op, expected_qual); 2377 ept_violation_at_level(2, clear, set, op, expected_qual); 2378 ept_violation_at_level(3, clear, set, op, expected_qual); 2379 ept_violation_at_level(4, clear, set, op, expected_qual); 2380 } 2381 2382 static void ept_access_violation(unsigned long access, enum ept_access_op op, 2383 u64 expected_qual) 2384 { 2385 ept_violation(EPT_PRESENT, access, op, 2386 expected_qual | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2387 } 2388 2389 /* 2390 * For translations that don't involve a GVA, that is physical address (paddr) 2391 * accesses, EPT violations don't set the flag EPT_VLT_PADDR. For a typical 2392 * guest memory access, the hardware does GVA -> GPA -> HPA. However, certain 2393 * translations don't involve GVAs, such as when the hardware does the guest 2394 * page table walk. For example, in translating GVA_1 -> GPA_1, the guest MMU 2395 * might try to set an A bit on a guest PTE. If the GPA_2 that the PTE resides 2396 * on isn't present in the EPT, then the EPT violation will be for GPA_2 and 2397 * the EPT_VLT_PADDR bit will be clear in the exit qualification. 2398 * 2399 * Note that paddr violations can also be triggered by loading PAE page tables 2400 * with wonky addresses. We don't test that yet. 2401 * 2402 * This function modifies the EPT entry that maps the GPA that the guest page 2403 * table entry mapping ept_access_data.gva resides on. 2404 * 2405 * @ept_access EPT permissions to set. Other permissions are cleared. 2406 * 2407 * @pte_ad Set the A/D bits on the guest PTE accordingly. 2408 * 2409 * @op Guest operation to perform with ept_access_data.gva. 2410 * 2411 * @expect_violation 2412 * Is a violation expected during the paddr access? 2413 * 2414 * @expected_qual Expected qualification for the EPT violation. 2415 * EPT_VLT_PADDR should be clear. 2416 */ 2417 static void ept_access_paddr(unsigned long ept_access, unsigned long pte_ad, 2418 enum ept_access_op op, bool expect_violation, 2419 u64 expected_qual) 2420 { 2421 struct ept_access_test_data *data = &ept_access_test_data; 2422 unsigned long *ptep; 2423 unsigned long gpa; 2424 unsigned long orig_epte; 2425 2426 /* Modify the guest PTE mapping data->gva according to @pte_ad. */ 2427 ptep = get_pte_level(current_page_table(), data->gva, /*level=*/1); 2428 TEST_ASSERT(ptep); 2429 TEST_ASSERT_EQ(*ptep & PT_ADDR_MASK, data->gpa); 2430 *ptep = (*ptep & ~PT_AD_MASK) | pte_ad; 2431 ept_access_test_guest_flush_tlb(); 2432 2433 /* 2434 * Now modify the access bits on the EPT entry for the GPA that the 2435 * guest PTE resides on. Note that by modifying a single EPT entry, 2436 * we're potentially affecting 512 guest PTEs. However, we've carefully 2437 * constructed our test such that those other 511 PTEs aren't used by 2438 * the guest: data->gva is at the beginning of a 1G huge page, thus the 2439 * PTE we're modifying is at the beginning of a 4K page and the 2440 * following 511 entires are also under our control (and not touched by 2441 * the guest). 2442 */ 2443 gpa = virt_to_phys(ptep); 2444 TEST_ASSERT_EQ(gpa & ~PAGE_MASK, 0); 2445 /* 2446 * Make sure the guest page table page is mapped with a 4K EPT entry, 2447 * otherwise our level=1 twiddling below will fail. We use the 2448 * identity map (gpa = gpa) since page tables are shared with the host. 2449 */ 2450 install_ept(pml4, gpa, gpa, EPT_PRESENT); 2451 orig_epte = ept_twiddle(gpa, /*mkhuge=*/0, /*level=*/1, 2452 /*clear=*/EPT_PRESENT, /*set=*/ept_access); 2453 2454 if (expect_violation) { 2455 do_ept_violation(/*leaf=*/true, op, 2456 expected_qual | EPT_VLT_LADDR_VLD, gpa); 2457 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2458 do_ept_access_op(op); 2459 } else { 2460 do_ept_access_op(op); 2461 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2462 } 2463 2464 TEST_ASSERT(*ptep & PT_ACCESSED_MASK); 2465 if ((pte_ad & PT_DIRTY_MASK) || op == OP_WRITE) 2466 TEST_ASSERT(*ptep & PT_DIRTY_MASK); 2467 2468 skip_exit_vmcall(); 2469 } 2470 2471 static void ept_access_allowed_paddr(unsigned long ept_access, 2472 unsigned long pte_ad, 2473 enum ept_access_op op) 2474 { 2475 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/false, 2476 /*expected_qual=*/-1); 2477 } 2478 2479 static void ept_access_violation_paddr(unsigned long ept_access, 2480 unsigned long pte_ad, 2481 enum ept_access_op op, 2482 u64 expected_qual) 2483 { 2484 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/true, 2485 expected_qual); 2486 } 2487 2488 2489 static void ept_allowed_at_level_mkhuge(bool mkhuge, int level, 2490 unsigned long clear, 2491 unsigned long set, 2492 enum ept_access_op op) 2493 { 2494 struct ept_access_test_data *data = &ept_access_test_data; 2495 unsigned long orig_pte; 2496 2497 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2498 2499 /* No violation. Should proceed to vmcall. */ 2500 do_ept_access_op(op); 2501 skip_exit_vmcall(); 2502 2503 ept_untwiddle(data->gpa, level, orig_pte); 2504 } 2505 2506 static void ept_allowed_at_level(int level, unsigned long clear, 2507 unsigned long set, enum ept_access_op op) 2508 { 2509 ept_allowed_at_level_mkhuge(false, level, clear, set, op); 2510 if (ept_huge_pages_supported(level)) 2511 ept_allowed_at_level_mkhuge(true, level, clear, set, op); 2512 } 2513 2514 static void ept_allowed(unsigned long clear, unsigned long set, 2515 enum ept_access_op op) 2516 { 2517 ept_allowed_at_level(1, clear, set, op); 2518 ept_allowed_at_level(2, clear, set, op); 2519 ept_allowed_at_level(3, clear, set, op); 2520 ept_allowed_at_level(4, clear, set, op); 2521 } 2522 2523 static void ept_ignored_bit(int bit) 2524 { 2525 /* Set the bit. */ 2526 ept_allowed(0, 1ul << bit, OP_READ); 2527 ept_allowed(0, 1ul << bit, OP_WRITE); 2528 ept_allowed(0, 1ul << bit, OP_EXEC); 2529 2530 /* Clear the bit. */ 2531 ept_allowed(1ul << bit, 0, OP_READ); 2532 ept_allowed(1ul << bit, 0, OP_WRITE); 2533 ept_allowed(1ul << bit, 0, OP_EXEC); 2534 } 2535 2536 static void ept_access_allowed(unsigned long access, enum ept_access_op op) 2537 { 2538 ept_allowed(EPT_PRESENT, access, op); 2539 } 2540 2541 2542 static void ept_misconfig_at_level_mkhuge_op(bool mkhuge, int level, 2543 unsigned long clear, 2544 unsigned long set, 2545 enum ept_access_op op) 2546 { 2547 struct ept_access_test_data *data = &ept_access_test_data; 2548 unsigned long orig_pte; 2549 2550 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2551 2552 do_ept_access_op(op); 2553 assert_exit_reason(VMX_EPT_MISCONFIG); 2554 2555 /* Intel 27.2.1, "For all other VM exits, this field is cleared." */ 2556 #if 0 2557 /* broken: */ 2558 TEST_EXPECT_EQ_MSG(vmcs_read(EXI_QUALIFICATION), 0); 2559 #endif 2560 #if 0 2561 /* 2562 * broken: 2563 * According to description of exit qual for EPT violation, 2564 * EPT_VLT_LADDR_VLD indicates if GUEST_LINEAR_ADDRESS is valid. 2565 * However, I can't find anything that says GUEST_LINEAR_ADDRESS ought 2566 * to be set for msiconfig. 2567 */ 2568 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2569 (unsigned long) ( 2570 op == OP_EXEC ? data->gva + 1 : data->gva)); 2571 #endif 2572 2573 /* Fix the violation and resume the op loop. */ 2574 ept_untwiddle(data->gpa, level, orig_pte); 2575 enter_guest(); 2576 skip_exit_vmcall(); 2577 } 2578 2579 static void ept_misconfig_at_level_mkhuge(bool mkhuge, int level, 2580 unsigned long clear, 2581 unsigned long set) 2582 { 2583 /* The op shouldn't matter (read, write, exec), so try them all! */ 2584 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_READ); 2585 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_WRITE); 2586 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_EXEC); 2587 } 2588 2589 static void ept_misconfig_at_level(int level, unsigned long clear, 2590 unsigned long set) 2591 { 2592 ept_misconfig_at_level_mkhuge(false, level, clear, set); 2593 if (ept_huge_pages_supported(level)) 2594 ept_misconfig_at_level_mkhuge(true, level, clear, set); 2595 } 2596 2597 static void ept_misconfig(unsigned long clear, unsigned long set) 2598 { 2599 ept_misconfig_at_level(1, clear, set); 2600 ept_misconfig_at_level(2, clear, set); 2601 ept_misconfig_at_level(3, clear, set); 2602 ept_misconfig_at_level(4, clear, set); 2603 } 2604 2605 static void ept_access_misconfig(unsigned long access) 2606 { 2607 ept_misconfig(EPT_PRESENT, access); 2608 } 2609 2610 static void ept_reserved_bit_at_level_nohuge(int level, int bit) 2611 { 2612 /* Setting the bit causes a misconfig. */ 2613 ept_misconfig_at_level_mkhuge(false, level, 0, 1ul << bit); 2614 2615 /* Making the entry non-present turns reserved bits into ignored. */ 2616 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2617 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2618 } 2619 2620 static void ept_reserved_bit_at_level_huge(int level, int bit) 2621 { 2622 /* Setting the bit causes a misconfig. */ 2623 ept_misconfig_at_level_mkhuge(true, level, 0, 1ul << bit); 2624 2625 /* Making the entry non-present turns reserved bits into ignored. */ 2626 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2627 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2628 } 2629 2630 static void ept_reserved_bit_at_level(int level, int bit) 2631 { 2632 /* Setting the bit causes a misconfig. */ 2633 ept_misconfig_at_level(level, 0, 1ul << bit); 2634 2635 /* Making the entry non-present turns reserved bits into ignored. */ 2636 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2637 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2638 } 2639 2640 static void ept_reserved_bit(int bit) 2641 { 2642 ept_reserved_bit_at_level(1, bit); 2643 ept_reserved_bit_at_level(2, bit); 2644 ept_reserved_bit_at_level(3, bit); 2645 ept_reserved_bit_at_level(4, bit); 2646 } 2647 2648 #define PAGE_2M_ORDER 9 2649 #define PAGE_1G_ORDER 18 2650 2651 static void *get_1g_page(void) 2652 { 2653 static void *alloc; 2654 2655 if (!alloc) 2656 alloc = alloc_pages(PAGE_1G_ORDER); 2657 return alloc; 2658 } 2659 2660 static void ept_access_test_teardown(void *unused) 2661 { 2662 /* Exit the guest cleanly. */ 2663 do_ept_access_op(OP_EXIT); 2664 } 2665 2666 static void ept_access_test_guest(void) 2667 { 2668 struct ept_access_test_data *data = &ept_access_test_data; 2669 int (*code)(void) = (int (*)(void)) &data->gva[1]; 2670 2671 while (true) { 2672 switch (data->op) { 2673 case OP_READ: 2674 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_1); 2675 break; 2676 case OP_WRITE: 2677 *data->gva = MAGIC_VAL_2; 2678 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_2); 2679 *data->gva = MAGIC_VAL_1; 2680 break; 2681 case OP_EXEC: 2682 TEST_ASSERT_EQ(42, code()); 2683 break; 2684 case OP_FLUSH_TLB: 2685 write_cr3(read_cr3()); 2686 break; 2687 case OP_EXIT: 2688 return; 2689 default: 2690 TEST_ASSERT_MSG(false, "Unknown op %d", data->op); 2691 } 2692 vmcall(); 2693 } 2694 } 2695 2696 static void ept_access_test_setup(void) 2697 { 2698 struct ept_access_test_data *data = &ept_access_test_data; 2699 unsigned long npages = 1ul << PAGE_1G_ORDER; 2700 unsigned long size = npages * PAGE_SIZE; 2701 unsigned long *page_table = current_page_table(); 2702 unsigned long pte; 2703 2704 if (setup_ept(false)) 2705 test_skip("EPT not supported"); 2706 2707 /* We use data->gpa = 1 << 39 so that test data has a separate pml4 entry */ 2708 if (cpuid_maxphyaddr() < 40) 2709 test_skip("Test needs MAXPHYADDR >= 40"); 2710 2711 test_set_guest(ept_access_test_guest); 2712 test_add_teardown(ept_access_test_teardown, NULL); 2713 2714 data->hva = get_1g_page(); 2715 TEST_ASSERT(data->hva); 2716 data->hpa = virt_to_phys(data->hva); 2717 2718 data->gpa = 1ul << 39; 2719 data->gva = (void *) ALIGN((unsigned long) alloc_vpages(npages * 2), 2720 size); 2721 TEST_ASSERT(!any_present_pages(page_table, data->gva, size)); 2722 install_pages(page_table, data->gpa, size, data->gva); 2723 2724 /* 2725 * Make sure nothing's mapped here so the tests that screw with the 2726 * pml4 entry don't inadvertently break something. 2727 */ 2728 TEST_ASSERT(get_ept_pte(pml4, data->gpa, 4, &pte) && pte == 0); 2729 TEST_ASSERT(get_ept_pte(pml4, data->gpa + size - 1, 4, &pte) && pte == 0); 2730 install_ept(pml4, data->hpa, data->gpa, EPT_PRESENT); 2731 2732 data->hva[0] = MAGIC_VAL_1; 2733 memcpy(&data->hva[1], &ret42_start, &ret42_end - &ret42_start); 2734 } 2735 2736 static void ept_access_test_not_present(void) 2737 { 2738 ept_access_test_setup(); 2739 /* --- */ 2740 ept_access_violation(0, OP_READ, EPT_VLT_RD); 2741 ept_access_violation(0, OP_WRITE, EPT_VLT_WR); 2742 ept_access_violation(0, OP_EXEC, EPT_VLT_FETCH); 2743 } 2744 2745 static void ept_access_test_read_only(void) 2746 { 2747 ept_access_test_setup(); 2748 2749 /* r-- */ 2750 ept_access_allowed(EPT_RA, OP_READ); 2751 ept_access_violation(EPT_RA, OP_WRITE, EPT_VLT_WR | EPT_VLT_PERM_RD); 2752 ept_access_violation(EPT_RA, OP_EXEC, EPT_VLT_FETCH | EPT_VLT_PERM_RD); 2753 } 2754 2755 static void ept_access_test_write_only(void) 2756 { 2757 ept_access_test_setup(); 2758 /* -w- */ 2759 ept_access_misconfig(EPT_WA); 2760 } 2761 2762 static void ept_access_test_read_write(void) 2763 { 2764 ept_access_test_setup(); 2765 /* rw- */ 2766 ept_access_allowed(EPT_RA | EPT_WA, OP_READ); 2767 ept_access_allowed(EPT_RA | EPT_WA, OP_WRITE); 2768 ept_access_violation(EPT_RA | EPT_WA, OP_EXEC, 2769 EPT_VLT_FETCH | EPT_VLT_PERM_RD | EPT_VLT_PERM_WR); 2770 } 2771 2772 2773 static void ept_access_test_execute_only(void) 2774 { 2775 ept_access_test_setup(); 2776 /* --x */ 2777 if (ept_execute_only_supported()) { 2778 ept_access_violation(EPT_EA, OP_READ, 2779 EPT_VLT_RD | EPT_VLT_PERM_EX); 2780 ept_access_violation(EPT_EA, OP_WRITE, 2781 EPT_VLT_WR | EPT_VLT_PERM_EX); 2782 ept_access_allowed(EPT_EA, OP_EXEC); 2783 } else { 2784 ept_access_misconfig(EPT_EA); 2785 } 2786 } 2787 2788 static void ept_access_test_read_execute(void) 2789 { 2790 ept_access_test_setup(); 2791 /* r-x */ 2792 ept_access_allowed(EPT_RA | EPT_EA, OP_READ); 2793 ept_access_violation(EPT_RA | EPT_EA, OP_WRITE, 2794 EPT_VLT_WR | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX); 2795 ept_access_allowed(EPT_RA | EPT_EA, OP_EXEC); 2796 } 2797 2798 static void ept_access_test_write_execute(void) 2799 { 2800 ept_access_test_setup(); 2801 /* -wx */ 2802 ept_access_misconfig(EPT_WA | EPT_EA); 2803 } 2804 2805 static void ept_access_test_read_write_execute(void) 2806 { 2807 ept_access_test_setup(); 2808 /* rwx */ 2809 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_READ); 2810 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_WRITE); 2811 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_EXEC); 2812 } 2813 2814 static void ept_access_test_reserved_bits(void) 2815 { 2816 int i; 2817 int maxphyaddr; 2818 2819 ept_access_test_setup(); 2820 2821 /* Reserved bits above maxphyaddr. */ 2822 maxphyaddr = cpuid_maxphyaddr(); 2823 for (i = maxphyaddr; i <= 51; i++) { 2824 report_prefix_pushf("reserved_bit=%d", i); 2825 ept_reserved_bit(i); 2826 report_prefix_pop(); 2827 } 2828 2829 /* Level-specific reserved bits. */ 2830 ept_reserved_bit_at_level_nohuge(2, 3); 2831 ept_reserved_bit_at_level_nohuge(2, 4); 2832 ept_reserved_bit_at_level_nohuge(2, 5); 2833 ept_reserved_bit_at_level_nohuge(2, 6); 2834 /* 2M alignment. */ 2835 for (i = 12; i < 20; i++) { 2836 report_prefix_pushf("reserved_bit=%d", i); 2837 ept_reserved_bit_at_level_huge(2, i); 2838 report_prefix_pop(); 2839 } 2840 ept_reserved_bit_at_level_nohuge(3, 3); 2841 ept_reserved_bit_at_level_nohuge(3, 4); 2842 ept_reserved_bit_at_level_nohuge(3, 5); 2843 ept_reserved_bit_at_level_nohuge(3, 6); 2844 /* 1G alignment. */ 2845 for (i = 12; i < 29; i++) { 2846 report_prefix_pushf("reserved_bit=%d", i); 2847 ept_reserved_bit_at_level_huge(3, i); 2848 report_prefix_pop(); 2849 } 2850 ept_reserved_bit_at_level(4, 3); 2851 ept_reserved_bit_at_level(4, 4); 2852 ept_reserved_bit_at_level(4, 5); 2853 ept_reserved_bit_at_level(4, 6); 2854 ept_reserved_bit_at_level(4, 7); 2855 } 2856 2857 static void ept_access_test_ignored_bits(void) 2858 { 2859 ept_access_test_setup(); 2860 /* 2861 * Bits ignored at every level. Bits 8 and 9 (A and D) are ignored as 2862 * far as translation is concerned even if AD bits are enabled in the 2863 * EPTP. Bit 63 is ignored because "EPT-violation #VE" VM-execution 2864 * control is 0. 2865 */ 2866 ept_ignored_bit(8); 2867 ept_ignored_bit(9); 2868 ept_ignored_bit(10); 2869 ept_ignored_bit(11); 2870 ept_ignored_bit(52); 2871 ept_ignored_bit(53); 2872 ept_ignored_bit(54); 2873 ept_ignored_bit(55); 2874 ept_ignored_bit(56); 2875 ept_ignored_bit(57); 2876 ept_ignored_bit(58); 2877 ept_ignored_bit(59); 2878 ept_ignored_bit(60); 2879 ept_ignored_bit(61); 2880 ept_ignored_bit(62); 2881 ept_ignored_bit(63); 2882 } 2883 2884 static void ept_access_test_paddr_not_present_ad_disabled(void) 2885 { 2886 ept_access_test_setup(); 2887 ept_disable_ad_bits(); 2888 2889 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, EPT_VLT_RD); 2890 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, EPT_VLT_RD); 2891 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, EPT_VLT_RD); 2892 } 2893 2894 static void ept_access_test_paddr_not_present_ad_enabled(void) 2895 { 2896 u64 qual = EPT_VLT_RD | EPT_VLT_WR; 2897 2898 ept_access_test_setup(); 2899 ept_enable_ad_bits_or_skip_test(); 2900 2901 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, qual); 2902 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, qual); 2903 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, qual); 2904 } 2905 2906 static void ept_access_test_paddr_read_only_ad_disabled(void) 2907 { 2908 /* 2909 * When EPT AD bits are disabled, all accesses to guest paging 2910 * structures are reported separately as a read and (after 2911 * translation of the GPA to host physical address) a read+write 2912 * if the A/D bits have to be set. 2913 */ 2914 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 2915 2916 ept_access_test_setup(); 2917 ept_disable_ad_bits(); 2918 2919 /* Can't update A bit, so all accesses fail. */ 2920 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 2921 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 2922 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 2923 /* AD bits disabled, so only writes try to update the D bit. */ 2924 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ); 2925 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 2926 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC); 2927 /* Both A and D already set, so read-only is OK. */ 2928 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_READ); 2929 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_WRITE); 2930 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_EXEC); 2931 } 2932 2933 static void ept_access_test_paddr_read_only_ad_enabled(void) 2934 { 2935 /* 2936 * When EPT AD bits are enabled, all accesses to guest paging 2937 * structures are considered writes as far as EPT translation 2938 * is concerned. 2939 */ 2940 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 2941 2942 ept_access_test_setup(); 2943 ept_enable_ad_bits_or_skip_test(); 2944 2945 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 2946 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 2947 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 2948 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ, qual); 2949 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 2950 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC, qual); 2951 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_READ, qual); 2952 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_WRITE, qual); 2953 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_EXEC, qual); 2954 } 2955 2956 static void ept_access_test_paddr_read_write(void) 2957 { 2958 ept_access_test_setup(); 2959 /* Read-write access to paging structure. */ 2960 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_READ); 2961 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_WRITE); 2962 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_EXEC); 2963 } 2964 2965 static void ept_access_test_paddr_read_write_execute(void) 2966 { 2967 ept_access_test_setup(); 2968 /* RWX access to paging structure. */ 2969 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_READ); 2970 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_WRITE); 2971 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_EXEC); 2972 } 2973 2974 static void ept_access_test_paddr_read_execute_ad_disabled(void) 2975 { 2976 /* 2977 * When EPT AD bits are disabled, all accesses to guest paging 2978 * structures are reported separately as a read and (after 2979 * translation of the GPA to host physical address) a read+write 2980 * if the A/D bits have to be set. 2981 */ 2982 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 2983 2984 ept_access_test_setup(); 2985 ept_disable_ad_bits(); 2986 2987 /* Can't update A bit, so all accesses fail. */ 2988 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 2989 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 2990 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 2991 /* AD bits disabled, so only writes try to update the D bit. */ 2992 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ); 2993 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 2994 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC); 2995 /* Both A and D already set, so read-only is OK. */ 2996 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ); 2997 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE); 2998 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC); 2999 } 3000 3001 static void ept_access_test_paddr_read_execute_ad_enabled(void) 3002 { 3003 /* 3004 * When EPT AD bits are enabled, all accesses to guest paging 3005 * structures are considered writes as far as EPT translation 3006 * is concerned. 3007 */ 3008 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3009 3010 ept_access_test_setup(); 3011 ept_enable_ad_bits_or_skip_test(); 3012 3013 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3014 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3015 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3016 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ, qual); 3017 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3018 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC, qual); 3019 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ, qual); 3020 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE, qual); 3021 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC, qual); 3022 } 3023 3024 static void ept_access_test_paddr_not_present_page_fault(void) 3025 { 3026 ept_access_test_setup(); 3027 /* 3028 * TODO: test no EPT violation as long as guest PF occurs. e.g., GPA is 3029 * page is read-only in EPT but GVA is also mapped read only in PT. 3030 * Thus guest page fault before host takes EPT violation for trying to 3031 * update A bit. 3032 */ 3033 } 3034 3035 static void ept_access_test_force_2m_page(void) 3036 { 3037 ept_access_test_setup(); 3038 3039 TEST_ASSERT_EQ(ept_2m_supported(), true); 3040 ept_allowed_at_level_mkhuge(true, 2, 0, 0, OP_READ); 3041 ept_violation_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_RA, OP_WRITE, 3042 EPT_VLT_WR | EPT_VLT_PERM_RD | 3043 EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 3044 ept_misconfig_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_WA); 3045 } 3046 3047 static bool invvpid_valid(u64 type, u64 vpid, u64 gla) 3048 { 3049 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3050 3051 TEST_ASSERT(msr & VPID_CAP_INVVPID); 3052 3053 if (type < INVVPID_ADDR || type > INVVPID_CONTEXT_LOCAL) 3054 return false; 3055 3056 if (!(msr & (1ull << (type + VPID_CAP_INVVPID_TYPES_SHIFT)))) 3057 return false; 3058 3059 if (vpid >> 16) 3060 return false; 3061 3062 if (type != INVVPID_ALL && !vpid) 3063 return false; 3064 3065 if (type == INVVPID_ADDR && !is_canonical(gla)) 3066 return false; 3067 3068 return true; 3069 } 3070 3071 static void try_invvpid(u64 type, u64 vpid, u64 gla) 3072 { 3073 int rc; 3074 bool valid = invvpid_valid(type, vpid, gla); 3075 u64 expected = valid ? VMXERR_UNSUPPORTED_VMCS_COMPONENT 3076 : VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID; 3077 /* 3078 * Set VMX_INST_ERROR to VMXERR_UNVALID_VMCS_COMPONENT, so 3079 * that we can tell if it is updated by INVVPID. 3080 */ 3081 vmcs_read(~0); 3082 rc = invvpid(type, vpid, gla); 3083 report("INVVPID type %ld VPID %lx GLA %lx %s", 3084 !rc == valid, type, vpid, gla, 3085 valid ? "passes" : "fails"); 3086 report("After %s INVVPID, VMX_INST_ERR is %ld (actual %ld)", 3087 vmcs_read(VMX_INST_ERROR) == expected, 3088 rc ? "failed" : "successful", 3089 expected, vmcs_read(VMX_INST_ERROR)); 3090 } 3091 3092 static void ds_invvpid(void *data) 3093 { 3094 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3095 u64 type = ffs(msr >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 3096 3097 TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 3098 asm volatile("invvpid %0, %1" 3099 : 3100 : "m"(*(struct invvpid_operand *)data), 3101 "r"(type)); 3102 } 3103 3104 /* 3105 * The SS override is ignored in 64-bit mode, so we use an addressing 3106 * mode with %rsp as the base register to generate an implicit SS 3107 * reference. 3108 */ 3109 static void ss_invvpid(void *data) 3110 { 3111 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3112 u64 type = ffs(msr >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 3113 3114 TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 3115 asm volatile("sub %%rsp,%0; invvpid (%%rsp,%0,1), %1" 3116 : "+r"(data) 3117 : "r"(type)); 3118 } 3119 3120 static void invvpid_test_gp(void) 3121 { 3122 bool fault; 3123 3124 fault = test_for_exception(GP_VECTOR, &ds_invvpid, 3125 (void *)NONCANONICAL); 3126 report("INVVPID with non-canonical DS operand raises #GP", fault); 3127 } 3128 3129 static void invvpid_test_ss(void) 3130 { 3131 bool fault; 3132 3133 fault = test_for_exception(SS_VECTOR, &ss_invvpid, 3134 (void *)NONCANONICAL); 3135 report("INVVPID with non-canonical SS operand raises #SS", fault); 3136 } 3137 3138 static void invvpid_test_pf(void) 3139 { 3140 void *vpage = alloc_vpage(); 3141 bool fault; 3142 3143 fault = test_for_exception(PF_VECTOR, &ds_invvpid, vpage); 3144 report("INVVPID with unmapped operand raises #PF", fault); 3145 } 3146 3147 static void try_compat_invvpid(void *unused) 3148 { 3149 struct far_pointer32 fp = { 3150 .offset = (uintptr_t)&&invvpid, 3151 .selector = KERNEL_CS32, 3152 }; 3153 register uintptr_t rsp asm("rsp"); 3154 3155 TEST_ASSERT_MSG(fp.offset == (uintptr_t)&&invvpid, 3156 "Code address too high."); 3157 TEST_ASSERT_MSG(rsp == (u32)rsp, "Stack address too high."); 3158 3159 asm goto ("lcall *%0" : : "m" (fp) : "rax" : invvpid); 3160 return; 3161 invvpid: 3162 asm volatile (".code32;" 3163 "invvpid (%eax), %eax;" 3164 "lret;" 3165 ".code64"); 3166 __builtin_unreachable(); 3167 } 3168 3169 static void invvpid_test_compatibility_mode(void) 3170 { 3171 bool fault; 3172 3173 fault = test_for_exception(UD_VECTOR, &try_compat_invvpid, NULL); 3174 report("Compatibility mode INVVPID raises #UD", fault); 3175 } 3176 3177 static void invvpid_test_not_in_vmx_operation(void) 3178 { 3179 bool fault; 3180 3181 TEST_ASSERT(!vmx_off()); 3182 fault = test_for_exception(UD_VECTOR, &ds_invvpid, NULL); 3183 report("INVVPID outside of VMX operation raises #UD", fault); 3184 TEST_ASSERT(!vmx_on()); 3185 } 3186 3187 /* 3188 * This does not test real-address mode, virtual-8086 mode, protected mode, 3189 * or CPL > 0. 3190 */ 3191 static void invvpid_test_v2(void) 3192 { 3193 u64 msr; 3194 int i; 3195 unsigned types = 0; 3196 unsigned type; 3197 3198 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 3199 !(ctrl_cpu_rev[1].clr & CPU_VPID)) 3200 test_skip("VPID not supported"); 3201 3202 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3203 3204 if (!(msr & VPID_CAP_INVVPID)) 3205 test_skip("INVVPID not supported.\n"); 3206 3207 if (msr & VPID_CAP_INVVPID_ADDR) 3208 types |= 1u << INVVPID_ADDR; 3209 if (msr & VPID_CAP_INVVPID_CXTGLB) 3210 types |= 1u << INVVPID_CONTEXT_GLOBAL; 3211 if (msr & VPID_CAP_INVVPID_ALL) 3212 types |= 1u << INVVPID_ALL; 3213 if (msr & VPID_CAP_INVVPID_CXTLOC) 3214 types |= 1u << INVVPID_CONTEXT_LOCAL; 3215 3216 if (!types) 3217 test_skip("No INVVPID types supported.\n"); 3218 3219 for (i = -127; i < 128; i++) 3220 try_invvpid(i, 0xffff, 0); 3221 3222 /* 3223 * VPID must not be more than 16 bits. 3224 */ 3225 for (i = 0; i < 64; i++) 3226 for (type = 0; type < 4; type++) 3227 if (types & (1u << type)) 3228 try_invvpid(type, 1ul << i, 0); 3229 3230 /* 3231 * VPID must not be zero, except for "all contexts." 3232 */ 3233 for (type = 0; type < 4; type++) 3234 if (types & (1u << type)) 3235 try_invvpid(type, 0, 0); 3236 3237 /* 3238 * The gla operand is only validated for single-address INVVPID. 3239 */ 3240 if (types & (1u << INVVPID_ADDR)) 3241 try_invvpid(INVVPID_ADDR, 0xffff, NONCANONICAL); 3242 3243 invvpid_test_gp(); 3244 invvpid_test_ss(); 3245 invvpid_test_pf(); 3246 invvpid_test_compatibility_mode(); 3247 invvpid_test_not_in_vmx_operation(); 3248 } 3249 3250 /* 3251 * Test for early VMLAUNCH failure. Returns true if VMLAUNCH makes it 3252 * at least as far as the guest-state checks. Returns false if the 3253 * VMLAUNCH fails early and execution falls through to the next 3254 * instruction. 3255 */ 3256 static bool vmlaunch_succeeds(void) 3257 { 3258 u32 exit_reason; 3259 3260 /* 3261 * Indirectly set VMX_INST_ERR to 12 ("VMREAD/VMWRITE from/to 3262 * unsupported VMCS component"). The caller can then check 3263 * to see if a failed VM-entry sets VMX_INST_ERR as expected. 3264 */ 3265 vmcs_write(~0u, 0); 3266 3267 vmcs_write(HOST_RIP, (uintptr_t)&&success); 3268 __asm__ __volatile__ goto ("vmwrite %%rsp, %0; vmlaunch" 3269 : 3270 : "r" ((u64)HOST_RSP) 3271 : "cc", "memory" 3272 : success); 3273 return false; 3274 success: 3275 exit_reason = vmcs_read(EXI_REASON); 3276 TEST_ASSERT(exit_reason == (VMX_FAIL_STATE | VMX_ENTRY_FAILURE) || 3277 exit_reason == (VMX_FAIL_MSR | VMX_ENTRY_FAILURE)); 3278 return true; 3279 } 3280 3281 /* 3282 * Try to launch the current VMCS. 3283 */ 3284 static void test_vmx_controls(bool controls_valid, bool xfail) 3285 { 3286 bool success = vmlaunch_succeeds(); 3287 u32 vmx_inst_err; 3288 3289 report_xfail("vmlaunch %s", xfail, success == controls_valid, 3290 controls_valid ? "succeeds" : "fails"); 3291 if (!success) { 3292 vmx_inst_err = vmcs_read(VMX_INST_ERROR); 3293 report("VMX inst error is %d (actual %d)", 3294 vmx_inst_err == VMXERR_ENTRY_INVALID_CONTROL_FIELD, 3295 VMXERR_ENTRY_INVALID_CONTROL_FIELD, vmx_inst_err); 3296 } 3297 } 3298 3299 /* 3300 * Test a particular value of a VM-execution control bit, if the value 3301 * is required or if the value is zero. 3302 */ 3303 static void test_rsvd_ctl_bit_value(const char *name, union vmx_ctrl_msr msr, 3304 enum Encoding encoding, unsigned bit, 3305 unsigned val) 3306 { 3307 u32 mask = 1u << bit; 3308 bool expected; 3309 u32 controls; 3310 3311 if (msr.set & mask) 3312 TEST_ASSERT(msr.clr & mask); 3313 3314 /* 3315 * We can't arbitrarily turn on a control bit, because it may 3316 * introduce dependencies on other VMCS fields. So, we only 3317 * test turning on bits that have a required setting. 3318 */ 3319 if (val && (msr.clr & mask) && !(msr.set & mask)) 3320 return; 3321 3322 report_prefix_pushf("%s %s bit %d", 3323 val ? "Set" : "Clear", name, bit); 3324 3325 controls = vmcs_read(encoding); 3326 if (val) { 3327 vmcs_write(encoding, msr.set | mask); 3328 expected = (msr.clr & mask); 3329 } else { 3330 vmcs_write(encoding, msr.set & ~mask); 3331 expected = !(msr.set & mask); 3332 } 3333 test_vmx_controls(expected, false); 3334 vmcs_write(encoding, controls); 3335 report_prefix_pop(); 3336 } 3337 3338 /* 3339 * Test reserved values of a VM-execution control bit, based on the 3340 * allowed bit settings from the corresponding VMX capability MSR. 3341 */ 3342 static void test_rsvd_ctl_bit(const char *name, union vmx_ctrl_msr msr, 3343 enum Encoding encoding, unsigned bit) 3344 { 3345 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 0); 3346 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 1); 3347 } 3348 3349 /* 3350 * Reserved bits in the pin-based VM-execution controls must be set 3351 * properly. Software may consult the VMX capability MSRs to determine 3352 * the proper settings. 3353 * [Intel SDM] 3354 */ 3355 static void test_pin_based_ctls(void) 3356 { 3357 unsigned bit; 3358 3359 printf("%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PIN" : 3360 "MSR_IA32_VMX_PINBASED_CTLS", ctrl_pin_rev.val); 3361 for (bit = 0; bit < 32; bit++) 3362 test_rsvd_ctl_bit("pin-based controls", 3363 ctrl_pin_rev, PIN_CONTROLS, bit); 3364 } 3365 3366 /* 3367 * Reserved bits in the primary processor-based VM-execution controls 3368 * must be set properly. Software may consult the VMX capability MSRs 3369 * to determine the proper settings. 3370 * [Intel SDM] 3371 */ 3372 static void test_primary_processor_based_ctls(void) 3373 { 3374 unsigned bit; 3375 3376 printf("\n%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PROC" : 3377 "MSR_IA32_VMX_PROCBASED_CTLS", ctrl_cpu_rev[0].val); 3378 for (bit = 0; bit < 32; bit++) 3379 test_rsvd_ctl_bit("primary processor-based controls", 3380 ctrl_cpu_rev[0], CPU_EXEC_CTRL0, bit); 3381 } 3382 3383 /* 3384 * If the "activate secondary controls" primary processor-based 3385 * VM-execution control is 1, reserved bits in the secondary 3386 * processor-based VM-execution controls must be cleared. Software may 3387 * consult the VMX capability MSRs to determine which bits are 3388 * reserved. 3389 * If the "activate secondary controls" primary processor-based 3390 * VM-execution control is 0 (or if the processor does not support the 3391 * 1-setting of that control), no checks are performed on the 3392 * secondary processor-based VM-execution controls. 3393 * [Intel SDM] 3394 */ 3395 static void test_secondary_processor_based_ctls(void) 3396 { 3397 u32 primary; 3398 u32 secondary; 3399 unsigned bit; 3400 3401 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) 3402 return; 3403 3404 primary = vmcs_read(CPU_EXEC_CTRL0); 3405 secondary = vmcs_read(CPU_EXEC_CTRL1); 3406 3407 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3408 printf("\nMSR_IA32_VMX_PROCBASED_CTLS2: %lx\n", ctrl_cpu_rev[1].val); 3409 for (bit = 0; bit < 32; bit++) 3410 test_rsvd_ctl_bit("secondary processor-based controls", 3411 ctrl_cpu_rev[1], CPU_EXEC_CTRL1, bit); 3412 3413 /* 3414 * When the "activate secondary controls" VM-execution control 3415 * is clear, there are no checks on the secondary controls. 3416 */ 3417 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3418 vmcs_write(CPU_EXEC_CTRL1, ~0); 3419 report("Secondary processor-based controls ignored", 3420 vmlaunch_succeeds()); 3421 vmcs_write(CPU_EXEC_CTRL1, secondary); 3422 vmcs_write(CPU_EXEC_CTRL0, primary); 3423 } 3424 3425 static void try_cr3_target_count(unsigned i, unsigned max) 3426 { 3427 report_prefix_pushf("CR3 target count 0x%x", i); 3428 vmcs_write(CR3_TARGET_COUNT, i); 3429 test_vmx_controls(i <= max, false); 3430 report_prefix_pop(); 3431 } 3432 3433 /* 3434 * The CR3-target count must not be greater than 4. Future processors 3435 * may support a different number of CR3-target values. Software 3436 * should read the VMX capability MSR IA32_VMX_MISC to determine the 3437 * number of values supported. 3438 * [Intel SDM] 3439 */ 3440 static void test_cr3_targets(void) 3441 { 3442 unsigned supported_targets = (rdmsr(MSR_IA32_VMX_MISC) >> 16) & 0x1ff; 3443 u32 cr3_targets = vmcs_read(CR3_TARGET_COUNT); 3444 unsigned i; 3445 3446 printf("\nSupported CR3 targets: %d\n", supported_targets); 3447 TEST_ASSERT(supported_targets <= 256); 3448 3449 try_cr3_target_count(-1u, supported_targets); 3450 try_cr3_target_count(0x80000000, supported_targets); 3451 try_cr3_target_count(0x7fffffff, supported_targets); 3452 for (i = 0; i <= supported_targets + 1; i++) 3453 try_cr3_target_count(i, supported_targets); 3454 vmcs_write(CR3_TARGET_COUNT, cr3_targets); 3455 } 3456 3457 /* 3458 * Test a particular address setting in the VMCS 3459 */ 3460 static void test_vmcs_addr(const char *name, 3461 enum Encoding encoding, 3462 u64 align, 3463 bool ignored, 3464 bool xfail_beyond_mapped_ram, 3465 u64 addr) 3466 { 3467 bool xfail = 3468 (xfail_beyond_mapped_ram && 3469 addr > fwcfg_get_u64(FW_CFG_RAM_SIZE) - align && 3470 addr < (1ul << cpuid_maxphyaddr())); 3471 3472 report_prefix_pushf("%s = %lx", name, addr); 3473 vmcs_write(encoding, addr); 3474 test_vmx_controls(ignored || (IS_ALIGNED(addr, align) && 3475 addr < (1ul << cpuid_maxphyaddr())), 3476 xfail); 3477 report_prefix_pop(); 3478 xfail = false; 3479 } 3480 3481 /* 3482 * Test interesting values for a VMCS address 3483 */ 3484 static void test_vmcs_addr_values(const char *name, 3485 enum Encoding encoding, 3486 u64 align, 3487 bool ignored, 3488 bool xfail_beyond_mapped_ram, 3489 u32 bit_start, u32 bit_end) 3490 { 3491 unsigned i; 3492 u64 orig_val = vmcs_read(encoding); 3493 3494 for (i = bit_start; i <= bit_end; i++) 3495 test_vmcs_addr(name, encoding, align, ignored, 3496 xfail_beyond_mapped_ram, 1ul << i); 3497 3498 test_vmcs_addr(name, encoding, align, ignored, 3499 xfail_beyond_mapped_ram, PAGE_SIZE - 1); 3500 test_vmcs_addr(name, encoding, align, ignored, 3501 xfail_beyond_mapped_ram, PAGE_SIZE); 3502 test_vmcs_addr(name, encoding, align, ignored, 3503 xfail_beyond_mapped_ram, 3504 (1ul << cpuid_maxphyaddr()) - PAGE_SIZE); 3505 test_vmcs_addr(name, encoding, align, ignored, 3506 xfail_beyond_mapped_ram, -1ul); 3507 3508 vmcs_write(encoding, orig_val); 3509 } 3510 3511 /* 3512 * Test a physical address reference in the VMCS, when the corresponding 3513 * feature is enabled and when the corresponding feature is disabled. 3514 */ 3515 static void test_vmcs_addr_reference(u32 control_bit, enum Encoding field, 3516 const char *field_name, 3517 const char *control_name, u64 align, 3518 bool xfail_beyond_mapped_ram, 3519 bool control_primary) 3520 { 3521 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 3522 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 3523 u64 page_addr; 3524 3525 if (control_primary) { 3526 if (!(ctrl_cpu_rev[0].clr & control_bit)) 3527 return; 3528 } else { 3529 if (!(ctrl_cpu_rev[1].clr & control_bit)) 3530 return; 3531 } 3532 3533 page_addr = vmcs_read(field); 3534 3535 report_prefix_pushf("%s enabled", control_name); 3536 if (control_primary) { 3537 vmcs_write(CPU_EXEC_CTRL0, primary | control_bit); 3538 } else { 3539 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3540 vmcs_write(CPU_EXEC_CTRL1, secondary | control_bit); 3541 } 3542 3543 test_vmcs_addr_values(field_name, field, align, false, 3544 xfail_beyond_mapped_ram, 0, 63); 3545 report_prefix_pop(); 3546 3547 report_prefix_pushf("%s disabled", control_name); 3548 if (control_primary) { 3549 vmcs_write(CPU_EXEC_CTRL0, primary & ~control_bit); 3550 } else { 3551 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3552 vmcs_write(CPU_EXEC_CTRL1, secondary & ~control_bit); 3553 } 3554 3555 test_vmcs_addr_values(field_name, field, align, true, false, 0, 63); 3556 report_prefix_pop(); 3557 3558 vmcs_write(field, page_addr); 3559 vmcs_write(CPU_EXEC_CTRL0, primary); 3560 } 3561 3562 /* 3563 * If the "use I/O bitmaps" VM-execution control is 1, bits 11:0 of 3564 * each I/O-bitmap address must be 0. Neither address should set any 3565 * bits beyond the processor's physical-address width. 3566 * [Intel SDM] 3567 */ 3568 static void test_io_bitmaps(void) 3569 { 3570 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_A, 3571 "I/O bitmap A", "Use I/O bitmaps", 3572 PAGE_SIZE, false, true); 3573 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_B, 3574 "I/O bitmap B", "Use I/O bitmaps", 3575 PAGE_SIZE, false, true); 3576 } 3577 3578 /* 3579 * If the "use MSR bitmaps" VM-execution control is 1, bits 11:0 of 3580 * the MSR-bitmap address must be 0. The address should not set any 3581 * bits beyond the processor's physical-address width. 3582 * [Intel SDM] 3583 */ 3584 static void test_msr_bitmap(void) 3585 { 3586 test_vmcs_addr_reference(CPU_MSR_BITMAP, MSR_BITMAP, 3587 "MSR bitmap", "Use MSR bitmaps", 3588 PAGE_SIZE, false, true); 3589 } 3590 3591 /* 3592 * If the "use TPR shadow" VM-execution control is 1, the virtual-APIC 3593 * address must satisfy the following checks: 3594 * - Bits 11:0 of the address must be 0. 3595 * - The address should not set any bits beyond the processor's 3596 * physical-address width. 3597 * [Intel SDM] 3598 */ 3599 static void test_apic_virt_addr(void) 3600 { 3601 test_vmcs_addr_reference(CPU_TPR_SHADOW, APIC_VIRT_ADDR, 3602 "virtual-APIC address", "Use TPR shadow", 3603 PAGE_SIZE, true, true); 3604 } 3605 3606 /* 3607 * If the "virtualize APIC-accesses" VM-execution control is 1, the 3608 * APIC-access address must satisfy the following checks: 3609 * - Bits 11:0 of the address must be 0. 3610 * - The address should not set any bits beyond the processor's 3611 * physical-address width. 3612 * [Intel SDM] 3613 */ 3614 static void test_apic_access_addr(void) 3615 { 3616 void *apic_access_page = alloc_page(); 3617 3618 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_page)); 3619 3620 test_vmcs_addr_reference(CPU_VIRT_APIC_ACCESSES, APIC_ACCS_ADDR, 3621 "APIC-access address", 3622 "virtualize APIC-accesses", PAGE_SIZE, 3623 false, false); 3624 } 3625 3626 static bool set_bit_pattern(u8 mask, u32 *secondary) 3627 { 3628 u8 i; 3629 bool flag = false; 3630 u32 test_bits[3] = { 3631 CPU_VIRT_X2APIC, 3632 CPU_APIC_REG_VIRT, 3633 CPU_VINTD 3634 }; 3635 3636 for (i = 0; i < ARRAY_SIZE(test_bits); i++) { 3637 if ((mask & (1u << i)) && 3638 (ctrl_cpu_rev[1].clr & test_bits[i])) { 3639 *secondary |= test_bits[i]; 3640 flag = true; 3641 } 3642 } 3643 3644 return (flag); 3645 } 3646 3647 /* 3648 * If the "use TPR shadow" VM-execution control is 0, the following 3649 * VM-execution controls must also be 0: 3650 * - virtualize x2APIC mode 3651 * - APIC-register virtualization 3652 * - virtual-interrupt delivery 3653 * [Intel SDM] 3654 * 3655 * 2. If the "virtualize x2APIC mode" VM-execution control is 1, the 3656 * "virtualize APIC accesses" VM-execution control must be 0. 3657 * [Intel SDM] 3658 */ 3659 static void test_apic_virtual_ctls(void) 3660 { 3661 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3662 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3663 u32 primary = saved_primary; 3664 u32 secondary = saved_secondary; 3665 bool ctrl = false; 3666 char str[10] = "disabled"; 3667 u8 i = 0, j; 3668 3669 /* 3670 * First test 3671 */ 3672 if (!((ctrl_cpu_rev[0].clr & (CPU_SECONDARY | CPU_TPR_SHADOW)) == 3673 (CPU_SECONDARY | CPU_TPR_SHADOW))) 3674 return; 3675 3676 primary |= CPU_SECONDARY; 3677 primary &= ~CPU_TPR_SHADOW; 3678 vmcs_write(CPU_EXEC_CTRL0, primary); 3679 3680 while (1) { 3681 for (j = 1; j < 8; j++) { 3682 secondary &= ~(CPU_VIRT_X2APIC | CPU_APIC_REG_VIRT | CPU_VINTD); 3683 if (primary & CPU_TPR_SHADOW) { 3684 ctrl = true; 3685 } else { 3686 if (! set_bit_pattern(j, &secondary)) 3687 ctrl = true; 3688 else 3689 ctrl = false; 3690 } 3691 3692 vmcs_write(CPU_EXEC_CTRL1, secondary); 3693 report_prefix_pushf("Use TPR shadow %s, virtualize x2APIC mode %s, APIC-register virtualization %s, virtual-interrupt delivery %s", 3694 str, (secondary & CPU_VIRT_X2APIC) ? "enabled" : "disabled", (secondary & CPU_APIC_REG_VIRT) ? "enabled" : "disabled", (secondary & CPU_VINTD) ? "enabled" : "disabled"); 3695 test_vmx_controls(ctrl, false); 3696 report_prefix_pop(); 3697 } 3698 3699 if (i == 1) 3700 break; 3701 i++; 3702 3703 primary |= CPU_TPR_SHADOW; 3704 vmcs_write(CPU_EXEC_CTRL0, primary); 3705 strcpy(str, "enabled"); 3706 } 3707 3708 /* 3709 * Second test 3710 */ 3711 u32 apic_virt_ctls = (CPU_VIRT_X2APIC | CPU_VIRT_APIC_ACCESSES); 3712 3713 primary = saved_primary; 3714 secondary = saved_secondary; 3715 if (!((ctrl_cpu_rev[1].clr & apic_virt_ctls) == apic_virt_ctls)) 3716 return; 3717 3718 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3719 secondary &= ~CPU_VIRT_APIC_ACCESSES; 3720 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_X2APIC); 3721 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access disabled"); 3722 test_vmx_controls(true, false); 3723 report_prefix_pop(); 3724 3725 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_APIC_ACCESSES); 3726 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access enabled"); 3727 test_vmx_controls(true, false); 3728 report_prefix_pop(); 3729 3730 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_X2APIC); 3731 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access enabled"); 3732 test_vmx_controls(false, false); 3733 report_prefix_pop(); 3734 3735 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_APIC_ACCESSES); 3736 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access disabled"); 3737 test_vmx_controls(true, false); 3738 report_prefix_pop(); 3739 3740 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3741 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3742 } 3743 3744 /* 3745 * If the "virtual-interrupt delivery" VM-execution control is 1, the 3746 * "external-interrupt exiting" VM-execution control must be 1. 3747 * [Intel SDM] 3748 */ 3749 static void test_virtual_intr_ctls(void) 3750 { 3751 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3752 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3753 u32 saved_pin = vmcs_read(PIN_CONTROLS); 3754 u32 primary = saved_primary; 3755 u32 secondary = saved_secondary; 3756 u32 pin = saved_pin; 3757 3758 if (!((ctrl_cpu_rev[1].clr & CPU_VINTD) && 3759 (ctrl_pin_rev.clr & PIN_EXTINT))) 3760 return; 3761 3762 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 3763 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VINTD); 3764 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 3765 report_prefix_pushf("Virtualize interrupt-delivery disabled; external-interrupt exiting disabled"); 3766 test_vmx_controls(true, false); 3767 report_prefix_pop(); 3768 3769 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VINTD); 3770 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 3771 test_vmx_controls(false, false); 3772 report_prefix_pop(); 3773 3774 vmcs_write(PIN_CONTROLS, pin | PIN_EXTINT); 3775 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting enabled"); 3776 test_vmx_controls(true, false); 3777 report_prefix_pop(); 3778 3779 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 3780 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 3781 test_vmx_controls(false, false); 3782 report_prefix_pop(); 3783 3784 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3785 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3786 vmcs_write(PIN_CONTROLS, saved_pin); 3787 } 3788 3789 static void test_pi_desc_addr(u64 addr, bool ctrl) 3790 { 3791 vmcs_write(POSTED_INTR_DESC_ADDR, addr); 3792 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-descriptor-address 0x%lx", addr); 3793 test_vmx_controls(ctrl, false); 3794 report_prefix_pop(); 3795 } 3796 3797 /* 3798 * If the “process posted interrupts†VM-execution control is 1, the 3799 * following must be true: 3800 * 3801 * - The “virtual-interrupt delivery†VM-execution control is 1. 3802 * - The “acknowledge interrupt on exit†VM-exit control is 1. 3803 * - The posted-interrupt notification vector has a value in the 3804 * - range 0–255 (bits 15:8 are all 0). 3805 * - Bits 5:0 of the posted-interrupt descriptor address are all 0. 3806 * - The posted-interrupt descriptor address does not set any bits 3807 * beyond the processor's physical-address width. 3808 * [Intel SDM] 3809 */ 3810 static void test_posted_intr(void) 3811 { 3812 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3813 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3814 u32 saved_pin = vmcs_read(PIN_CONTROLS); 3815 u32 exit_ctl_saved = vmcs_read(EXI_CONTROLS); 3816 u32 primary = saved_primary; 3817 u32 secondary = saved_secondary; 3818 u32 pin = saved_pin; 3819 u32 exit_ctl = exit_ctl_saved; 3820 u16 vec; 3821 int i; 3822 3823 if (!((ctrl_pin_rev.clr & PIN_POST_INTR) && 3824 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 3825 (ctrl_exit_rev.clr & EXI_INTA))) 3826 return; 3827 3828 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 3829 3830 /* 3831 * Test virtual-interrupt-delivery and acknowledge-interrupt-on-exit 3832 */ 3833 pin |= PIN_POST_INTR; 3834 vmcs_write(PIN_CONTROLS, pin); 3835 secondary &= ~CPU_VINTD; 3836 vmcs_write(CPU_EXEC_CTRL1, secondary); 3837 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled"); 3838 test_vmx_controls(false, false); 3839 report_prefix_pop(); 3840 3841 secondary |= CPU_VINTD; 3842 vmcs_write(CPU_EXEC_CTRL1, secondary); 3843 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled"); 3844 test_vmx_controls(false, false); 3845 report_prefix_pop(); 3846 3847 exit_ctl &= ~EXI_INTA; 3848 vmcs_write(EXI_CONTROLS, exit_ctl); 3849 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit disabled"); 3850 test_vmx_controls(false, false); 3851 report_prefix_pop(); 3852 3853 exit_ctl |= EXI_INTA; 3854 vmcs_write(EXI_CONTROLS, exit_ctl); 3855 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 3856 test_vmx_controls(true, false); 3857 report_prefix_pop(); 3858 3859 secondary &= ~CPU_VINTD; 3860 vmcs_write(CPU_EXEC_CTRL1, secondary); 3861 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled; acknowledge-interrupt-on-exit enabled"); 3862 test_vmx_controls(false, false); 3863 report_prefix_pop(); 3864 3865 secondary |= CPU_VINTD; 3866 vmcs_write(CPU_EXEC_CTRL1, secondary); 3867 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 3868 test_vmx_controls(true, false); 3869 report_prefix_pop(); 3870 3871 /* 3872 * Test posted-interrupt notification vector 3873 */ 3874 for (i = 0; i < 8; i++) { 3875 vec = (1ul << i); 3876 vmcs_write(PINV, vec); 3877 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 3878 test_vmx_controls(true, false); 3879 report_prefix_pop(); 3880 } 3881 for (i = 8; i < 16; i++) { 3882 vec = (1ul << i); 3883 vmcs_write(PINV, vec); 3884 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 3885 test_vmx_controls(false, false); 3886 report_prefix_pop(); 3887 } 3888 3889 vec &= ~(0xff << 8); 3890 vmcs_write(PINV, vec); 3891 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 3892 test_vmx_controls(true, false); 3893 report_prefix_pop(); 3894 3895 /* 3896 * Test posted-interrupt descriptor addresss 3897 */ 3898 for (i = 0; i < 6; i++) { 3899 test_pi_desc_addr(1ul << i, false); 3900 } 3901 3902 test_pi_desc_addr(0xf0, false); 3903 test_pi_desc_addr(0xff, false); 3904 test_pi_desc_addr(0x0f, false); 3905 test_pi_desc_addr(0x8000, true); 3906 test_pi_desc_addr(0x00, true); 3907 test_pi_desc_addr(0xc000, true); 3908 3909 test_vmcs_addr_values("process-posted interrupts", 3910 POSTED_INTR_DESC_ADDR, 64, 3911 false, false, 0, 63); 3912 3913 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3914 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3915 vmcs_write(PIN_CONTROLS, saved_pin); 3916 } 3917 3918 static void test_apic_ctls(void) 3919 { 3920 test_apic_virt_addr(); 3921 test_apic_access_addr(); 3922 test_apic_virtual_ctls(); 3923 test_virtual_intr_ctls(); 3924 test_posted_intr(); 3925 } 3926 3927 /* 3928 * If the “enable VPID†VM-execution control is 1, the value of the 3929 * of the VPID VM-execution control field must not be 0000H. 3930 * [Intel SDM] 3931 */ 3932 static void test_vpid(void) 3933 { 3934 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3935 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3936 u16 vpid = 0x0000; 3937 int i; 3938 3939 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 3940 (ctrl_cpu_rev[1].clr & CPU_VPID))) { 3941 test_skip("Secondary controls and/or VPID not supported"); 3942 return; 3943 } 3944 3945 vmcs_write(CPU_EXEC_CTRL0, saved_primary | CPU_SECONDARY); 3946 vmcs_write(CPU_EXEC_CTRL1, saved_secondary & ~CPU_VPID); 3947 vmcs_write(VPID, vpid); 3948 report_prefix_pushf("VPID disabled; VPID value %x", vpid); 3949 test_vmx_controls(true, false); 3950 report_prefix_pop(); 3951 3952 vmcs_write(CPU_EXEC_CTRL1, saved_secondary | CPU_VPID); 3953 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 3954 test_vmx_controls(false, false); 3955 report_prefix_pop(); 3956 3957 for (i = 0; i < 16; i++) { 3958 vpid = (short)1 << i;; 3959 vmcs_write(VPID, vpid); 3960 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 3961 test_vmx_controls(true, false); 3962 report_prefix_pop(); 3963 } 3964 3965 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3966 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3967 } 3968 3969 static void set_vtpr(unsigned vtpr) 3970 { 3971 *(u32 *)phys_to_virt(vmcs_read(APIC_VIRT_ADDR) + APIC_TASKPRI) = vtpr; 3972 } 3973 3974 static void try_tpr_threshold_and_vtpr(unsigned threshold, unsigned vtpr) 3975 { 3976 bool valid = true; 3977 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 3978 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 3979 3980 if ((primary & CPU_TPR_SHADOW) && 3981 (!(primary & CPU_SECONDARY) || 3982 !(secondary & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 3983 valid = (threshold & 0xf) <= ((vtpr >> 4) & 0xf); 3984 3985 set_vtpr(vtpr); 3986 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0x%x", 3987 threshold, (vtpr >> 4) & 0xf); 3988 test_vmx_controls(valid, false); 3989 report_prefix_pop(); 3990 } 3991 3992 static void test_invalid_event_injection(void) 3993 { 3994 u32 ent_intr_info_save = vmcs_read(ENT_INTR_INFO); 3995 u32 ent_intr_error_save = vmcs_read(ENT_INTR_ERROR); 3996 u32 ent_inst_len_save = vmcs_read(ENT_INST_LEN); 3997 u32 primary_save = vmcs_read(CPU_EXEC_CTRL0); 3998 u32 secondary_save = vmcs_read(CPU_EXEC_CTRL1); 3999 u64 guest_cr0_save = vmcs_read(GUEST_CR0); 4000 u32 ent_intr_info_base = INTR_INFO_VALID_MASK; 4001 u32 ent_intr_info, ent_intr_err, ent_intr_len; 4002 u32 cnt; 4003 4004 /* Setup */ 4005 report_prefix_push("invalid event injection"); 4006 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4007 vmcs_write(ENT_INST_LEN, 0x00000001); 4008 4009 /* The field’s interruption type is not set to a reserved value. */ 4010 ent_intr_info = ent_intr_info_base | INTR_TYPE_RESERVED | DE_VECTOR; 4011 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4012 "RESERVED interruption type invalid [-]", 4013 ent_intr_info); 4014 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4015 test_vmx_controls(false, false); 4016 report_prefix_pop(); 4017 4018 ent_intr_info = ent_intr_info_base | INTR_TYPE_EXT_INTR | 4019 DE_VECTOR; 4020 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4021 "RESERVED interruption type invalid [+]", 4022 ent_intr_info); 4023 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4024 test_vmx_controls(true, false); 4025 report_prefix_pop(); 4026 4027 /* If the interruption type is other event, the vector is 0. */ 4028 ent_intr_info = ent_intr_info_base | INTR_TYPE_OTHER_EVENT | DB_VECTOR; 4029 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4030 "(OTHER EVENT && vector != 0) invalid [-]", 4031 ent_intr_info); 4032 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4033 test_vmx_controls(false, false); 4034 report_prefix_pop(); 4035 4036 /* If the interruption type is NMI, the vector is 2 (negative case). */ 4037 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | DE_VECTOR; 4038 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4039 "(NMI && vector != 2) invalid [-]", ent_intr_info); 4040 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4041 test_vmx_controls(false, false); 4042 report_prefix_pop(); 4043 4044 /* If the interruption type is NMI, the vector is 2 (positive case). */ 4045 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | NMI_VECTOR; 4046 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4047 "(NMI && vector == 2) valid [+]", ent_intr_info); 4048 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4049 test_vmx_controls(true, false); 4050 report_prefix_pop(); 4051 4052 /* 4053 * If the interruption type 4054 * is HW exception, the vector is at most 31. 4055 */ 4056 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 0x20; 4057 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4058 "(HW exception && vector > 31) invalid [-]", 4059 ent_intr_info); 4060 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4061 test_vmx_controls(false, false); 4062 report_prefix_pop(); 4063 4064 /* 4065 * deliver-error-code is 1 iff either 4066 * (a) the "unrestricted guest" VM-execution control is 0 4067 * (b) CR0.PE is set. 4068 */ 4069 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4070 GP_VECTOR; 4071 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4072 "error code <-> (!URG || prot_mode) [-]", 4073 ent_intr_info); 4074 disable_unrestricted_guest(); 4075 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4076 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4077 test_vmx_controls(false, false); 4078 report_prefix_pop(); 4079 4080 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4081 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4082 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4083 "error code <-> (!URG || prot_mode) [+]", 4084 ent_intr_info); 4085 disable_unrestricted_guest(); 4086 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4087 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4088 test_vmx_controls(true, false); 4089 report_prefix_pop(); 4090 4091 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4092 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4093 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4094 "error code <-> (!URG || prot_mode) [-]", 4095 ent_intr_info); 4096 enable_unrestricted_guest(); 4097 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4098 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4099 test_vmx_controls(false, false); 4100 report_prefix_pop(); 4101 4102 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4103 GP_VECTOR; 4104 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4105 "error code <-> (!URG || prot_mode) [-]", 4106 ent_intr_info); 4107 vmcs_write(GUEST_CR0, guest_cr0_save | X86_CR0_PE); 4108 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4109 test_vmx_controls(false, false); 4110 report_prefix_pop(); 4111 4112 /* deliver-error-code is 1 iff the interruption type is HW exception */ 4113 report_prefix_push("error code <-> HW exception"); 4114 for (cnt = 0; cnt < 8; cnt++) { 4115 u32 exception_type_mask = cnt << 8; 4116 u32 deliver_error_code_mask = 4117 exception_type_mask != INTR_TYPE_HARD_EXCEPTION ? 4118 INTR_INFO_DELIVER_CODE_MASK : 0; 4119 4120 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4121 exception_type_mask | GP_VECTOR; 4122 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4123 ent_intr_info); 4124 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4125 test_vmx_controls(false, false); 4126 report_prefix_pop(); 4127 } 4128 report_prefix_pop(); 4129 4130 /* 4131 * deliver-error-code is 1 iff the the vector 4132 * indicates an exception that would normally deliver an error code 4133 */ 4134 report_prefix_push("error code <-> vector delivers error code"); 4135 for (cnt = 0; cnt < 32; cnt++) { 4136 bool has_error_code = false; 4137 u32 deliver_error_code_mask; 4138 4139 switch (cnt) { 4140 case DF_VECTOR: 4141 case TS_VECTOR: 4142 case NP_VECTOR: 4143 case SS_VECTOR: 4144 case GP_VECTOR: 4145 case PF_VECTOR: 4146 case AC_VECTOR: 4147 has_error_code = true; 4148 } 4149 4150 /* Negative case */ 4151 deliver_error_code_mask = has_error_code ? 4152 0 : 4153 INTR_INFO_DELIVER_CODE_MASK; 4154 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4155 INTR_TYPE_HARD_EXCEPTION | cnt; 4156 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4157 ent_intr_info); 4158 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4159 test_vmx_controls(false, false); 4160 report_prefix_pop(); 4161 4162 /* Positive case */ 4163 deliver_error_code_mask = has_error_code ? 4164 INTR_INFO_DELIVER_CODE_MASK : 4165 0; 4166 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4167 INTR_TYPE_HARD_EXCEPTION | cnt; 4168 report_prefix_pushf("VM-entry intr info=0x%x [+]", 4169 ent_intr_info); 4170 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4171 test_vmx_controls(true, false); 4172 report_prefix_pop(); 4173 } 4174 report_prefix_pop(); 4175 4176 /* Reserved bits in the field (30:12) are 0. */ 4177 report_prefix_push("reserved bits clear"); 4178 for (cnt = 12; cnt <= 30; cnt++) { 4179 ent_intr_info = ent_intr_info_base | 4180 INTR_INFO_DELIVER_CODE_MASK | 4181 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR | 4182 (1U << cnt); 4183 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4184 ent_intr_info); 4185 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4186 test_vmx_controls(false, false); 4187 report_prefix_pop(); 4188 } 4189 report_prefix_pop(); 4190 4191 /* 4192 * If deliver-error-code is 1 4193 * bits 31:15 of the VM-entry exception error-code field are 0. 4194 */ 4195 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4196 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4197 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4198 "VM-entry exception error code[31:15] clear", 4199 ent_intr_info); 4200 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4201 for (cnt = 15; cnt <= 31; cnt++) { 4202 ent_intr_err = 1U << cnt; 4203 report_prefix_pushf("VM-entry intr error=0x%x [-]", 4204 ent_intr_err); 4205 vmcs_write(ENT_INTR_ERROR, ent_intr_err); 4206 test_vmx_controls(false, false); 4207 report_prefix_pop(); 4208 } 4209 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4210 report_prefix_pop(); 4211 4212 /* 4213 * If the interruption type is software interrupt, software exception, 4214 * or privileged software exception, the VM-entry instruction-length 4215 * field is in the range 0–15. 4216 */ 4217 4218 for (cnt = 0; cnt < 3; cnt++) { 4219 switch (cnt) { 4220 case 0: 4221 ent_intr_info = ent_intr_info_base | 4222 INTR_TYPE_SOFT_INTR; 4223 break; 4224 case 1: 4225 ent_intr_info = ent_intr_info_base | 4226 INTR_TYPE_SOFT_EXCEPTION; 4227 break; 4228 case 2: 4229 ent_intr_info = ent_intr_info_base | 4230 INTR_TYPE_PRIV_SW_EXCEPTION; 4231 break; 4232 } 4233 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4234 "VM-entry instruction-length check", 4235 ent_intr_info); 4236 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4237 4238 /* Instruction length set to -1 (0xFFFFFFFF) should fail */ 4239 ent_intr_len = -1; 4240 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4241 ent_intr_len); 4242 vmcs_write(ENT_INST_LEN, ent_intr_len); 4243 test_vmx_controls(false, false); 4244 report_prefix_pop(); 4245 4246 /* Instruction length set to 16 should fail */ 4247 ent_intr_len = 0x00000010; 4248 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4249 ent_intr_len); 4250 vmcs_write(ENT_INST_LEN, 0x00000010); 4251 test_vmx_controls(false, false); 4252 report_prefix_pop(); 4253 4254 report_prefix_pop(); 4255 } 4256 4257 /* Cleanup */ 4258 vmcs_write(ENT_INTR_INFO, ent_intr_info_save); 4259 vmcs_write(ENT_INTR_ERROR, ent_intr_error_save); 4260 vmcs_write(ENT_INST_LEN, ent_inst_len_save); 4261 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4262 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4263 vmcs_write(GUEST_CR0, guest_cr0_save); 4264 report_prefix_pop(); 4265 } 4266 4267 /* 4268 * Test interesting vTPR values for a given TPR threshold. 4269 */ 4270 static void test_vtpr_values(unsigned threshold) 4271 { 4272 try_tpr_threshold_and_vtpr(threshold, (threshold - 1) << 4); 4273 try_tpr_threshold_and_vtpr(threshold, threshold << 4); 4274 try_tpr_threshold_and_vtpr(threshold, (threshold + 1) << 4); 4275 } 4276 4277 static void try_tpr_threshold(unsigned threshold) 4278 { 4279 bool valid = true; 4280 4281 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4282 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4283 4284 if ((primary & CPU_TPR_SHADOW) && !((primary & CPU_SECONDARY) && 4285 (secondary & CPU_VINTD))) 4286 valid = !(threshold >> 4); 4287 4288 set_vtpr(-1); 4289 vmcs_write(TPR_THRESHOLD, threshold); 4290 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0xf", threshold); 4291 test_vmx_controls(valid, false); 4292 report_prefix_pop(); 4293 4294 if (valid) 4295 test_vtpr_values(threshold); 4296 } 4297 4298 /* 4299 * Test interesting TPR threshold values. 4300 */ 4301 static void test_tpr_threshold_values(void) 4302 { 4303 unsigned i; 4304 4305 for (i = 0; i < 0x10; i++) 4306 try_tpr_threshold(i); 4307 for (i = 4; i < 32; i++) 4308 try_tpr_threshold(1u << i); 4309 try_tpr_threshold(-1u); 4310 try_tpr_threshold(0x7fffffff); 4311 } 4312 4313 /* 4314 * This test covers the following two VM entry checks: 4315 * 4316 * i) If the "use TPR shadow" VM-execution control is 1 and the 4317 * "virtual-interrupt delivery" VM-execution control is 0, bits 4318 * 31:4 of the TPR threshold VM-execution control field must 4319 be 0. 4320 * [Intel SDM] 4321 * 4322 * ii) If the "use TPR shadow" VM-execution control is 1, the 4323 * "virtual-interrupt delivery" VM-execution control is 0 4324 * and the "virtualize APIC accesses" VM-execution control 4325 * is 0, the value of bits 3:0 of the TPR threshold VM-execution 4326 * control field must not be greater than the value of bits 4327 * 7:4 of VTPR. 4328 * [Intel SDM] 4329 */ 4330 static void test_tpr_threshold(void) 4331 { 4332 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4333 void *virtual_apic_page; 4334 4335 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) 4336 return; 4337 4338 virtual_apic_page = alloc_page(); 4339 memset(virtual_apic_page, 0xff, PAGE_SIZE); 4340 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 4341 4342 vmcs_write(CPU_EXEC_CTRL0, primary & ~(CPU_TPR_SHADOW | CPU_SECONDARY)); 4343 report_prefix_pushf("Use TPR shadow disabled, secondary controls disabled"); 4344 test_tpr_threshold_values(); 4345 report_prefix_pop(); 4346 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_TPR_SHADOW); 4347 report_prefix_pushf("Use TPR shadow enabled, secondary controls disabled"); 4348 test_tpr_threshold_values(); 4349 report_prefix_pop(); 4350 4351 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4352 (ctrl_cpu_rev[1].clr & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) { 4353 vmcs_write(CPU_EXEC_CTRL0, primary); 4354 return; 4355 } 4356 4357 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4358 4359 if (ctrl_cpu_rev[1].clr & CPU_VINTD) { 4360 vmcs_write(CPU_EXEC_CTRL1, CPU_VINTD); 4361 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4362 test_tpr_threshold_values(); 4363 report_prefix_pop(); 4364 4365 vmcs_write(CPU_EXEC_CTRL0, 4366 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4367 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4368 test_tpr_threshold_values(); 4369 report_prefix_pop(); 4370 } 4371 4372 if (ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES) { 4373 vmcs_write(CPU_EXEC_CTRL0, 4374 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4375 vmcs_write(CPU_EXEC_CTRL1, CPU_VIRT_APIC_ACCESSES); 4376 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4377 test_tpr_threshold_values(); 4378 report_prefix_pop(); 4379 4380 vmcs_write(CPU_EXEC_CTRL0, 4381 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4382 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4383 test_tpr_threshold_values(); 4384 report_prefix_pop(); 4385 } 4386 4387 if ((ctrl_cpu_rev[1].clr & 4388 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) == 4389 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) { 4390 vmcs_write(CPU_EXEC_CTRL0, 4391 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4392 vmcs_write(CPU_EXEC_CTRL1, 4393 CPU_VINTD | CPU_VIRT_APIC_ACCESSES); 4394 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4395 test_tpr_threshold_values(); 4396 report_prefix_pop(); 4397 4398 vmcs_write(CPU_EXEC_CTRL0, 4399 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4400 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4401 test_tpr_threshold_values(); 4402 report_prefix_pop(); 4403 } 4404 4405 vmcs_write(CPU_EXEC_CTRL1, secondary); 4406 vmcs_write(CPU_EXEC_CTRL0, primary); 4407 } 4408 4409 /* 4410 * This test verifies the following two vmentry checks: 4411 * 4412 * If the "NMI exiting" VM-execution control is 0, "Virtual NMIs" 4413 * VM-execution control must be 0. 4414 * [Intel SDM] 4415 * 4416 * If the “virtual NMIs” VM-execution control is 0, the “NMI-window 4417 * exiting” VM-execution control must be 0. 4418 * [Intel SDM] 4419 */ 4420 static void test_nmi_ctrls(void) 4421 { 4422 u32 pin_ctrls, cpu_ctrls0, test_pin_ctrls, test_cpu_ctrls0; 4423 4424 if ((ctrl_pin_rev.clr & (PIN_NMI | PIN_VIRT_NMI)) != 4425 (PIN_NMI | PIN_VIRT_NMI)) { 4426 test_skip("NMI exiting and Virtual NMIs are not supported !"); 4427 return; 4428 } 4429 4430 /* Save the controls so that we can restore them after our tests */ 4431 pin_ctrls = vmcs_read(PIN_CONTROLS); 4432 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 4433 4434 test_pin_ctrls = pin_ctrls & ~(PIN_NMI | PIN_VIRT_NMI); 4435 test_cpu_ctrls0 = cpu_ctrls0 & ~CPU_NMI_WINDOW; 4436 4437 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4438 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs disabled"); 4439 test_vmx_controls(true, false); 4440 report_prefix_pop(); 4441 4442 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_VIRT_NMI); 4443 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs enabled"); 4444 test_vmx_controls(false, false); 4445 report_prefix_pop(); 4446 4447 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4448 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs enabled"); 4449 test_vmx_controls(true, false); 4450 report_prefix_pop(); 4451 4452 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_NMI); 4453 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs disabled"); 4454 test_vmx_controls(true, false); 4455 report_prefix_pop(); 4456 4457 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 4458 report_info("NMI-window exiting is not supported, skipping..."); 4459 goto done; 4460 } 4461 4462 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4463 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4464 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting enabled"); 4465 test_vmx_controls(false, false); 4466 report_prefix_pop(); 4467 4468 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4469 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4470 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting disabled"); 4471 test_vmx_controls(true, false); 4472 report_prefix_pop(); 4473 4474 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4475 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4476 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting enabled"); 4477 test_vmx_controls(true, false); 4478 report_prefix_pop(); 4479 4480 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4481 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4482 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting disabled"); 4483 test_vmx_controls(true, false); 4484 report_prefix_pop(); 4485 4486 /* Restore the controls to their original values */ 4487 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 4488 done: 4489 vmcs_write(PIN_CONTROLS, pin_ctrls); 4490 } 4491 4492 static void test_eptp_ad_bit(u64 eptp, bool ctrl) 4493 { 4494 vmcs_write(EPTP, eptp); 4495 report_prefix_pushf("Enable-EPT enabled; EPT accessed and dirty flag %s", 4496 (eptp & EPTP_AD_FLAG) ? "1": "0"); 4497 test_vmx_controls(ctrl, false); 4498 report_prefix_pop(); 4499 4500 } 4501 4502 /* 4503 * 1. If the "enable EPT" VM-execution control is 1, the "EPTP VM-execution" 4504 * control field must satisfy the following checks: 4505 * 4506 * - The EPT memory type (bits 2:0) must be a value supported by the 4507 * processor as indicated in the IA32_VMX_EPT_VPID_CAP MSR. 4508 * - Bits 5:3 (1 less than the EPT page-walk length) must be 3, 4509 * indicating an EPT page-walk length of 4. 4510 * - Bit 6 (enable bit for accessed and dirty flags for EPT) must be 4511 * 0 if bit 21 of the IA32_VMX_EPT_VPID_CAP MSR is read as 0, 4512 * indicating that the processor does not support accessed and dirty 4513 * dirty flags for EPT. 4514 * - Reserved bits 11:7 and 63:N (where N is the processor's 4515 * physical-address width) must all be 0. 4516 * 4517 * 2. If the "unrestricted guest" VM-execution control is 1, the 4518 * "enable EPT" VM-execution control must also be 1. 4519 */ 4520 static void test_ept_eptp(void) 4521 { 4522 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4523 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4524 u64 eptp_saved = vmcs_read(EPTP); 4525 u32 primary = primary_saved; 4526 u32 secondary = secondary_saved; 4527 u64 msr, eptp = eptp_saved; 4528 bool un_cache = false; 4529 bool wr_bk = false; 4530 bool ctrl; 4531 u32 i, maxphysaddr; 4532 u64 j, resv_bits_mask = 0; 4533 4534 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4535 (ctrl_cpu_rev[1].clr & CPU_EPT))) { 4536 test_skip("\"CPU secondary\" and/or \"enable EPT\" execution controls are not supported !"); 4537 return; 4538 } 4539 4540 /* 4541 * Memory type (bits 2:0) 4542 */ 4543 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 4544 if (msr & EPT_CAP_UC) 4545 un_cache = true; 4546 if (msr & EPT_CAP_WB) 4547 wr_bk = true; 4548 4549 primary |= CPU_SECONDARY; 4550 vmcs_write(CPU_EXEC_CTRL0, primary); 4551 secondary |= CPU_EPT; 4552 vmcs_write(CPU_EXEC_CTRL1, secondary); 4553 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4554 (3ul << EPTP_PG_WALK_LEN_SHIFT); 4555 vmcs_write(EPTP, eptp); 4556 4557 for (i = 0; i < 8; i++) { 4558 if (i == 0) { 4559 if (un_cache) { 4560 report_info("EPT paging structure memory-type is Un-cacheable\n"); 4561 ctrl = true; 4562 } else { 4563 ctrl = false; 4564 } 4565 } else if (i == 6) { 4566 if (wr_bk) { 4567 report_info("EPT paging structure memory-type is Write-back\n"); 4568 ctrl = true; 4569 } else { 4570 ctrl = false; 4571 } 4572 } else { 4573 ctrl = false; 4574 } 4575 4576 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | i; 4577 vmcs_write(EPTP, eptp); 4578 report_prefix_pushf("Enable-EPT enabled; EPT memory type %lu", 4579 eptp & EPT_MEM_TYPE_MASK); 4580 test_vmx_controls(ctrl, false); 4581 report_prefix_pop(); 4582 } 4583 4584 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | 6ul; 4585 4586 /* 4587 * Page walk length (bits 5:3) 4588 */ 4589 for (i = 0; i < 8; i++) { 4590 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4591 (i << EPTP_PG_WALK_LEN_SHIFT); 4592 if (i == 3) 4593 ctrl = true; 4594 else 4595 ctrl = false; 4596 4597 vmcs_write(EPTP, eptp); 4598 report_prefix_pushf("Enable-EPT enabled; EPT page walk length %lu", 4599 eptp & EPTP_PG_WALK_LEN_MASK); 4600 test_vmx_controls(ctrl, false); 4601 report_prefix_pop(); 4602 } 4603 4604 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4605 3ul << EPTP_PG_WALK_LEN_SHIFT; 4606 4607 /* 4608 * Accessed and dirty flag (bit 6) 4609 */ 4610 if (msr & EPT_CAP_AD_FLAG) { 4611 report_info("Processor supports accessed and dirty flag"); 4612 eptp &= ~EPTP_AD_FLAG; 4613 test_eptp_ad_bit(eptp, true); 4614 4615 eptp |= EPTP_AD_FLAG; 4616 test_eptp_ad_bit(eptp, true); 4617 } else { 4618 report_info("Processor does not supports accessed and dirty flag"); 4619 eptp &= ~EPTP_AD_FLAG; 4620 test_eptp_ad_bit(eptp, true); 4621 4622 eptp |= EPTP_AD_FLAG; 4623 test_eptp_ad_bit(eptp, false); 4624 } 4625 4626 /* 4627 * Reserved bits [11:7] and [63:N] 4628 */ 4629 for (i = 0; i < 32; i++) { 4630 if (i == 0) 4631 ctrl = true; 4632 else 4633 ctrl = false; 4634 4635 eptp = (eptp & 4636 ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)) | 4637 (i << EPTP_RESERV_BITS_SHIFT); 4638 vmcs_write(EPTP, eptp); 4639 report_prefix_pushf("Enable-EPT enabled; reserved bits [11:7] %lu", 4640 (eptp >> EPTP_RESERV_BITS_SHIFT) & 4641 EPTP_RESERV_BITS_MASK); 4642 test_vmx_controls(ctrl, false); 4643 report_prefix_pop(); 4644 } 4645 4646 eptp = (eptp & ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)); 4647 4648 maxphysaddr = cpuid_maxphyaddr(); 4649 for (i = 0; i < (63 - maxphysaddr + 1); i++) { 4650 resv_bits_mask |= 1ul << i; 4651 } 4652 4653 for (j = 0; j < (63 - maxphysaddr + 1); j++) { 4654 if (j == 0) 4655 ctrl = true; 4656 else 4657 ctrl = false; 4658 4659 eptp = (eptp & ~(resv_bits_mask << maxphysaddr)) | 4660 (j << maxphysaddr); 4661 vmcs_write(EPTP, eptp); 4662 report_prefix_pushf("Enable-EPT enabled; reserved bits [63:N] %lu", 4663 (eptp >> maxphysaddr) & resv_bits_mask); 4664 test_vmx_controls(ctrl, false); 4665 report_prefix_pop(); 4666 } 4667 4668 secondary &= ~(CPU_EPT | CPU_URG); 4669 vmcs_write(CPU_EXEC_CTRL1, secondary); 4670 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest disabled"); 4671 test_vmx_controls(true, false); 4672 report_prefix_pop(); 4673 4674 secondary |= CPU_URG; 4675 vmcs_write(CPU_EXEC_CTRL1, secondary); 4676 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest enabled"); 4677 test_vmx_controls(false, false); 4678 report_prefix_pop(); 4679 4680 secondary |= CPU_EPT; 4681 setup_ept(false); 4682 vmcs_write(CPU_EXEC_CTRL1, secondary); 4683 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest enabled"); 4684 test_vmx_controls(true, false); 4685 report_prefix_pop(); 4686 4687 secondary &= ~CPU_URG; 4688 vmcs_write(CPU_EXEC_CTRL1, secondary); 4689 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest disabled"); 4690 test_vmx_controls(true, false); 4691 report_prefix_pop(); 4692 4693 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4694 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4695 vmcs_write(EPTP, eptp_saved); 4696 } 4697 4698 /* 4699 * If the 'enable PML' VM-execution control is 1, the 'enable EPT' 4700 * VM-execution control must also be 1. In addition, the PML address 4701 * must satisfy the following checks: 4702 * 4703 * * Bits 11:0 of the address must be 0. 4704 * * The address should not set any bits beyond the processor's 4705 * physical-address width. 4706 * 4707 * [Intel SDM] 4708 */ 4709 static void test_pml(void) 4710 { 4711 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4712 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4713 u32 primary = primary_saved; 4714 u32 secondary = secondary_saved; 4715 4716 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4717 (ctrl_cpu_rev[1].clr & CPU_EPT) && (ctrl_cpu_rev[1].clr & CPU_PML))) { 4718 test_skip("\"Secondary execution\" control or \"enable EPT\" control or \"enable PML\" control is not supported !"); 4719 return; 4720 } 4721 4722 primary |= CPU_SECONDARY; 4723 vmcs_write(CPU_EXEC_CTRL0, primary); 4724 secondary &= ~(CPU_PML | CPU_EPT); 4725 vmcs_write(CPU_EXEC_CTRL1, secondary); 4726 report_prefix_pushf("enable-PML disabled, enable-EPT disabled"); 4727 test_vmx_controls(true, false); 4728 report_prefix_pop(); 4729 4730 secondary |= CPU_PML; 4731 vmcs_write(CPU_EXEC_CTRL1, secondary); 4732 report_prefix_pushf("enable-PML enabled, enable-EPT disabled"); 4733 test_vmx_controls(false, false); 4734 report_prefix_pop(); 4735 4736 secondary |= CPU_EPT; 4737 setup_ept(false); 4738 vmcs_write(CPU_EXEC_CTRL1, secondary); 4739 report_prefix_pushf("enable-PML enabled, enable-EPT enabled"); 4740 test_vmx_controls(true, false); 4741 report_prefix_pop(); 4742 4743 secondary &= ~CPU_PML; 4744 vmcs_write(CPU_EXEC_CTRL1, secondary); 4745 report_prefix_pushf("enable-PML disabled, enable EPT enabled"); 4746 test_vmx_controls(true, false); 4747 report_prefix_pop(); 4748 4749 test_vmcs_addr_reference(CPU_PML, PMLADDR, "PML address", "PML", 4750 PAGE_SIZE, false, false); 4751 4752 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4753 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4754 } 4755 4756 /* 4757 * If the "activate VMX-preemption timer" VM-execution control is 0, the 4758 * the "save VMX-preemption timer value" VM-exit control must also be 0. 4759 * 4760 * [Intel SDM] 4761 */ 4762 static void test_vmx_preemption_timer(void) 4763 { 4764 u32 saved_pin = vmcs_read(PIN_CONTROLS); 4765 u32 saved_exit = vmcs_read(EXI_CONTROLS); 4766 u32 pin = saved_pin; 4767 u32 exit = saved_exit; 4768 4769 if (!((ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) || 4770 (ctrl_pin_rev.clr & PIN_PREEMPT))) { 4771 printf("\"Save-VMX-preemption-timer\" control and/or \"Enable-VMX-preemption-timer\" control is not supported\n"); 4772 return; 4773 } 4774 4775 pin |= PIN_PREEMPT; 4776 vmcs_write(PIN_CONTROLS, pin); 4777 exit &= ~EXI_SAVE_PREEMPT; 4778 vmcs_write(EXI_CONTROLS, exit); 4779 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer disabled"); 4780 test_vmx_controls(true, false); 4781 report_prefix_pop(); 4782 4783 exit |= EXI_SAVE_PREEMPT; 4784 vmcs_write(EXI_CONTROLS, exit); 4785 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer enabled"); 4786 test_vmx_controls(true, false); 4787 report_prefix_pop(); 4788 4789 pin &= ~PIN_PREEMPT; 4790 vmcs_write(PIN_CONTROLS, pin); 4791 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer enabled"); 4792 test_vmx_controls(false, false); 4793 report_prefix_pop(); 4794 4795 exit &= ~EXI_SAVE_PREEMPT; 4796 vmcs_write(EXI_CONTROLS, exit); 4797 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer disabled"); 4798 test_vmx_controls(true, false); 4799 report_prefix_pop(); 4800 4801 vmcs_write(PIN_CONTROLS, saved_pin); 4802 vmcs_write(EXI_CONTROLS, saved_exit); 4803 } 4804 4805 /* 4806 * Tests for VM-execution control fields 4807 */ 4808 static void test_vm_execution_ctls(void) 4809 { 4810 test_pin_based_ctls(); 4811 test_primary_processor_based_ctls(); 4812 test_secondary_processor_based_ctls(); 4813 test_cr3_targets(); 4814 test_io_bitmaps(); 4815 test_msr_bitmap(); 4816 test_apic_ctls(); 4817 test_tpr_threshold(); 4818 test_nmi_ctrls(); 4819 test_pml(); 4820 test_vpid(); 4821 test_ept_eptp(); 4822 test_vmx_preemption_timer(); 4823 } 4824 4825 /* 4826 * The following checks are performed for the VM-entry MSR-load address if 4827 * the VM-entry MSR-load count field is non-zero: 4828 * 4829 * - The lower 4 bits of the VM-entry MSR-load address must be 0. 4830 * The address should not set any bits beyond the processor’s 4831 * physical-address width. 4832 * 4833 * - The address of the last byte in the VM-entry MSR-load area 4834 * should not set any bits beyond the processor’s physical-address 4835 * width. The address of this last byte is VM-entry MSR-load address 4836 * + (MSR count * 16) - 1. (The arithmetic used for the computation 4837 * uses more bits than the processor’s physical-address width.) 4838 * 4839 * 4840 * [Intel SDM] 4841 */ 4842 static void test_entry_msr_load(void) 4843 { 4844 entry_msr_load = alloc_page(); 4845 u64 tmp; 4846 u32 entry_msr_ld_cnt = 1; 4847 int i; 4848 u32 addr_len = 64; 4849 4850 vmcs_write(ENT_MSR_LD_CNT, entry_msr_ld_cnt); 4851 4852 /* Check first 4 bits of VM-entry MSR-load address */ 4853 for (i = 0; i < 4; i++) { 4854 tmp = (u64)entry_msr_load | 1ull << i; 4855 vmcs_write(ENTER_MSR_LD_ADDR, tmp); 4856 report_prefix_pushf("VM-entry MSR-load addr [4:0] %lx", 4857 tmp & 0xf); 4858 test_vmx_controls(false, false); 4859 report_prefix_pop(); 4860 } 4861 4862 if (basic.val & (1ul << 48)) 4863 addr_len = 32; 4864 4865 test_vmcs_addr_values("VM-entry-MSR-load address", 4866 ENTER_MSR_LD_ADDR, 16, false, false, 4867 4, addr_len - 1); 4868 4869 /* 4870 * Check last byte of VM-entry MSR-load address 4871 */ 4872 entry_msr_load = (struct vmx_msr_entry *)((u64)entry_msr_load & ~0xf); 4873 4874 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 4875 i < 64; i++) { 4876 tmp = ((u64)entry_msr_load + entry_msr_ld_cnt * 16 - 1) | 4877 1ul << i; 4878 vmcs_write(ENTER_MSR_LD_ADDR, 4879 tmp - (entry_msr_ld_cnt * 16 - 1)); 4880 test_vmx_controls(false, false); 4881 } 4882 4883 vmcs_write(ENT_MSR_LD_CNT, 2); 4884 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 4885 test_vmx_controls(false, false); 4886 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 4887 test_vmx_controls(true, false); 4888 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 4889 test_vmx_controls(true, false); 4890 } 4891 4892 /* 4893 * Tests for VM-entry control fields 4894 */ 4895 static void test_vm_entry_ctls(void) 4896 { 4897 test_invalid_event_injection(); 4898 test_entry_msr_load(); 4899 } 4900 4901 /* 4902 * The following checks are performed for the VM-exit MSR-store address if 4903 * the VM-exit MSR-store count field is non-zero: 4904 * 4905 * - The lower 4 bits of the VM-exit MSR-store address must be 0. 4906 * The address should not set any bits beyond the processor’s 4907 * physical-address width. 4908 * 4909 * - The address of the last byte in the VM-exit MSR-store area 4910 * should not set any bits beyond the processor’s physical-address 4911 * width. The address of this last byte is VM-exit MSR-store address 4912 * + (MSR count * 16) - 1. (The arithmetic used for the computation 4913 * uses more bits than the processor’s physical-address width.) 4914 * 4915 * If IA32_VMX_BASIC[48] is read as 1, neither address should set any bits 4916 * in the range 63:32. 4917 * 4918 * [Intel SDM] 4919 */ 4920 static void test_exit_msr_store(void) 4921 { 4922 exit_msr_store = alloc_page(); 4923 u64 tmp; 4924 u32 exit_msr_st_cnt = 1; 4925 int i; 4926 u32 addr_len = 64; 4927 4928 vmcs_write(EXI_MSR_ST_CNT, exit_msr_st_cnt); 4929 4930 /* Check first 4 bits of VM-exit MSR-store address */ 4931 for (i = 0; i < 4; i++) { 4932 tmp = (u64)exit_msr_store | 1ull << i; 4933 vmcs_write(EXIT_MSR_ST_ADDR, tmp); 4934 report_prefix_pushf("VM-exit MSR-store addr [4:0] %lx", 4935 tmp & 0xf); 4936 test_vmx_controls(false, false); 4937 report_prefix_pop(); 4938 } 4939 4940 if (basic.val & (1ul << 48)) 4941 addr_len = 32; 4942 4943 test_vmcs_addr_values("VM-exit-MSR-store address", 4944 EXIT_MSR_ST_ADDR, 16, false, false, 4945 4, addr_len - 1); 4946 4947 /* 4948 * Check last byte of VM-exit MSR-store address 4949 */ 4950 exit_msr_store = (struct vmx_msr_entry *)((u64)exit_msr_store & ~0xf); 4951 4952 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 4953 i < 64; i++) { 4954 tmp = ((u64)exit_msr_store + exit_msr_st_cnt * 16 - 1) | 4955 1ul << i; 4956 vmcs_write(EXIT_MSR_ST_ADDR, 4957 tmp - (exit_msr_st_cnt * 16 - 1)); 4958 test_vmx_controls(false, false); 4959 } 4960 4961 vmcs_write(EXI_MSR_ST_CNT, 2); 4962 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 4963 test_vmx_controls(false, false); 4964 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 4965 test_vmx_controls(true, false); 4966 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 4967 test_vmx_controls(true, false); 4968 } 4969 4970 /* 4971 * Tests for VM-exit controls 4972 */ 4973 static void test_vm_exit_ctls(void) 4974 { 4975 test_exit_msr_store(); 4976 } 4977 4978 /* 4979 * Check that the virtual CPU checks all of the VMX controls as 4980 * documented in the Intel SDM. 4981 */ 4982 static void vmx_controls_test(void) 4983 { 4984 /* 4985 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 4986 * fail due to invalid guest state, should we make it that 4987 * far. 4988 */ 4989 vmcs_write(GUEST_RFLAGS, 0); 4990 4991 test_vm_execution_ctls(); 4992 test_vm_entry_ctls(); 4993 test_vm_exit_ctls(); 4994 } 4995 4996 static bool valid_vmcs_for_vmentry(void) 4997 { 4998 struct vmcs *current_vmcs = NULL; 4999 5000 if (vmcs_save(¤t_vmcs)) 5001 return false; 5002 5003 return current_vmcs && !current_vmcs->hdr.shadow_vmcs; 5004 } 5005 5006 static void try_vmentry_in_movss_shadow(void) 5007 { 5008 u32 vm_inst_err; 5009 u32 flags; 5010 bool early_failure = false; 5011 u32 expected_flags = X86_EFLAGS_FIXED; 5012 bool valid_vmcs = valid_vmcs_for_vmentry(); 5013 5014 expected_flags |= valid_vmcs ? X86_EFLAGS_ZF : X86_EFLAGS_CF; 5015 5016 /* 5017 * Indirectly set VM_INST_ERR to 12 ("VMREAD/VMWRITE from/to 5018 * unsupported VMCS component"). 5019 */ 5020 vmcs_write(~0u, 0); 5021 5022 __asm__ __volatile__ ("mov %[host_rsp], %%edx;" 5023 "vmwrite %%rsp, %%rdx;" 5024 "mov 0f, %%rax;" 5025 "mov %[host_rip], %%edx;" 5026 "vmwrite %%rax, %%rdx;" 5027 "mov $-1, %%ah;" 5028 "sahf;" 5029 "mov %%ss, %%ax;" 5030 "mov %%ax, %%ss;" 5031 "vmlaunch;" 5032 "mov $1, %[early_failure];" 5033 "0: lahf;" 5034 "movzbl %%ah, %[flags]" 5035 : [early_failure] "+r" (early_failure), 5036 [flags] "=&a" (flags) 5037 : [host_rsp] "i" (HOST_RSP), 5038 [host_rip] "i" (HOST_RIP) 5039 : "rdx", "cc", "memory"); 5040 vm_inst_err = vmcs_read(VMX_INST_ERROR); 5041 5042 report("Early VM-entry failure", early_failure); 5043 report("RFLAGS[8:0] is %x (actual %x)", flags == expected_flags, 5044 expected_flags, flags); 5045 if (valid_vmcs) 5046 report("VM-instruction error is %d (actual %d)", 5047 vm_inst_err == VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, 5048 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, vm_inst_err); 5049 } 5050 5051 static void vmentry_movss_shadow_test(void) 5052 { 5053 struct vmcs *orig_vmcs; 5054 5055 TEST_ASSERT(!vmcs_save(&orig_vmcs)); 5056 5057 /* 5058 * Set the launched flag on the current VMCS to verify the correct 5059 * error priority, below. 5060 */ 5061 test_set_guest(v2_null_test_guest); 5062 enter_guest(); 5063 5064 /* 5065 * With bit 1 of the guest's RFLAGS clear, VM-entry should 5066 * fail due to invalid guest state (if we make it that far). 5067 */ 5068 vmcs_write(GUEST_RFLAGS, 0); 5069 5070 /* 5071 * "VM entry with events blocked by MOV SS" takes precedence over 5072 * "VMLAUNCH with non-clear VMCS." 5073 */ 5074 report_prefix_push("valid current-VMCS"); 5075 try_vmentry_in_movss_shadow(); 5076 report_prefix_pop(); 5077 5078 /* 5079 * VMfailInvalid takes precedence over "VM entry with events 5080 * blocked by MOV SS." 5081 */ 5082 TEST_ASSERT(!vmcs_clear(orig_vmcs)); 5083 report_prefix_push("no current-VMCS"); 5084 try_vmentry_in_movss_shadow(); 5085 report_prefix_pop(); 5086 5087 TEST_ASSERT(!make_vmcs_current(orig_vmcs)); 5088 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 5089 } 5090 5091 #define X86_FEATURE_PCID (1 << 17) 5092 #define X86_FEATURE_MCE (1 << 7) 5093 5094 static int write_cr4_checking(unsigned long val) 5095 { 5096 asm volatile(ASM_TRY("1f") 5097 "mov %0, %%cr4\n\t" 5098 "1:": : "r" (val)); 5099 return exception_vector(); 5100 } 5101 5102 static void vmx_cr_load_test(void) 5103 { 5104 struct cpuid _cpuid = cpuid(1); 5105 unsigned long cr4 = read_cr4(), cr3 = read_cr3(); 5106 5107 if (!(_cpuid.c & X86_FEATURE_PCID)) { 5108 report_skip("PCID not detected"); 5109 return; 5110 } 5111 if (!(_cpuid.d & X86_FEATURE_MCE)) { 5112 report_skip("MCE not detected"); 5113 return; 5114 } 5115 5116 TEST_ASSERT(!(cr4 & (X86_CR4_PCIDE | X86_CR4_MCE))); 5117 TEST_ASSERT(!(cr3 & X86_CR3_PCID_MASK)); 5118 5119 /* Enable PCID for L1. */ 5120 cr4 |= X86_CR4_PCIDE; 5121 cr3 |= 0x1; 5122 TEST_ASSERT(!write_cr4_checking(cr4)); 5123 write_cr3(cr3); 5124 5125 test_set_guest(v2_null_test_guest); 5126 vmcs_write(HOST_CR4, cr4); 5127 vmcs_write(HOST_CR3, cr3); 5128 enter_guest(); 5129 5130 /* 5131 * No exception is expected. 5132 * 5133 * NB. KVM loads the last guest write to CR4 into CR4 read 5134 * shadow. In order to trigger an exit to KVM, we can set a 5135 * bit that was zero in the above CR4 write and is owned by 5136 * KVM. We choose to set CR4.MCE, which shall have no side 5137 * effect because normally no guest MCE (e.g., as the result 5138 * of bad memory) would happen during this test. 5139 */ 5140 TEST_ASSERT(!write_cr4_checking(cr4 | X86_CR4_MCE)); 5141 5142 /* Cleanup L1 state: disable PCID. */ 5143 write_cr3(cr3 & ~X86_CR3_PCID_MASK); 5144 TEST_ASSERT(!write_cr4_checking(cr4 & ~X86_CR4_PCIDE)); 5145 } 5146 5147 static void vmx_nm_test_guest(void) 5148 { 5149 write_cr0(read_cr0() | X86_CR0_TS); 5150 asm volatile("fnop"); 5151 } 5152 5153 static void check_nm_exit(const char *test) 5154 { 5155 u32 reason = vmcs_read(EXI_REASON); 5156 u32 intr_info = vmcs_read(EXI_INTR_INFO); 5157 const u32 expected = INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 5158 NM_VECTOR; 5159 5160 report("%s", reason == VMX_EXC_NMI && intr_info == expected, test); 5161 } 5162 5163 /* 5164 * This test checks that: 5165 * 5166 * (a) If L2 launches with CR0.TS clear, but later sets CR0.TS, then 5167 * a subsequent #NM VM-exit is reflected to L1. 5168 * 5169 * (b) If L2 launches with CR0.TS clear and CR0.EM set, then a 5170 * subsequent #NM VM-exit is reflected to L1. 5171 */ 5172 static void vmx_nm_test(void) 5173 { 5174 unsigned long cr0 = read_cr0(); 5175 5176 test_set_guest(vmx_nm_test_guest); 5177 5178 /* 5179 * L1 wants to intercept #NM exceptions encountered in L2. 5180 */ 5181 vmcs_write(EXC_BITMAP, 1 << NM_VECTOR); 5182 5183 /* 5184 * Launch L2 with CR0.TS clear, but don't claim host ownership of 5185 * any CR0 bits. L2 will set CR0.TS and then try to execute fnop, 5186 * which will raise #NM. L0 should reflect the #NM VM-exit to L1. 5187 */ 5188 vmcs_write(CR0_MASK, 0); 5189 vmcs_write(GUEST_CR0, cr0 & ~X86_CR0_TS); 5190 enter_guest(); 5191 check_nm_exit("fnop with CR0.TS set in L2 triggers #NM VM-exit to L1"); 5192 5193 /* 5194 * Re-enter L2 at the fnop instruction, with CR0.TS clear but 5195 * CR0.EM set. The fnop will still raise #NM, and L0 should 5196 * reflect the #NM VM-exit to L1. 5197 */ 5198 vmcs_write(GUEST_CR0, (cr0 & ~X86_CR0_TS) | X86_CR0_EM); 5199 enter_guest(); 5200 check_nm_exit("fnop with CR0.EM set in L2 triggers #NM VM-exit to L1"); 5201 5202 /* 5203 * Re-enter L2 at the fnop instruction, with both CR0.TS and 5204 * CR0.EM clear. There will be no #NM, and the L2 guest should 5205 * exit normally. 5206 */ 5207 vmcs_write(GUEST_CR0, cr0 & ~(X86_CR0_TS | X86_CR0_EM)); 5208 enter_guest(); 5209 } 5210 5211 bool vmx_pending_event_ipi_fired; 5212 static void vmx_pending_event_ipi_isr(isr_regs_t *regs) 5213 { 5214 vmx_pending_event_ipi_fired = true; 5215 eoi(); 5216 } 5217 5218 bool vmx_pending_event_guest_run; 5219 static void vmx_pending_event_guest(void) 5220 { 5221 vmcall(); 5222 vmx_pending_event_guest_run = true; 5223 } 5224 5225 static void vmx_pending_event_test_core(bool guest_hlt) 5226 { 5227 int ipi_vector = 0xf1; 5228 5229 vmx_pending_event_ipi_fired = false; 5230 handle_irq(ipi_vector, vmx_pending_event_ipi_isr); 5231 5232 vmx_pending_event_guest_run = false; 5233 test_set_guest(vmx_pending_event_guest); 5234 5235 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 5236 5237 enter_guest(); 5238 skip_exit_vmcall(); 5239 5240 if (guest_hlt) 5241 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 5242 5243 irq_disable(); 5244 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | 5245 APIC_DM_FIXED | ipi_vector, 5246 0); 5247 5248 enter_guest(); 5249 5250 assert_exit_reason(VMX_EXTINT); 5251 report("Guest did not run before host received IPI", 5252 !vmx_pending_event_guest_run); 5253 5254 irq_enable(); 5255 asm volatile ("nop"); 5256 irq_disable(); 5257 report("Got pending interrupt after IRQ enabled", 5258 vmx_pending_event_ipi_fired); 5259 5260 if (guest_hlt) 5261 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 5262 5263 enter_guest(); 5264 report("Guest finished running when no interrupt", 5265 vmx_pending_event_guest_run); 5266 } 5267 5268 static void vmx_pending_event_test(void) 5269 { 5270 vmx_pending_event_test_core(false); 5271 } 5272 5273 static void vmx_pending_event_hlt_test(void) 5274 { 5275 vmx_pending_event_test_core(true); 5276 } 5277 5278 static int vmx_window_test_ud_count; 5279 5280 static void vmx_window_test_ud_handler(struct ex_regs *regs) 5281 { 5282 vmx_window_test_ud_count++; 5283 } 5284 5285 static void vmx_nmi_window_test_guest(void) 5286 { 5287 handle_exception(UD_VECTOR, vmx_window_test_ud_handler); 5288 5289 asm volatile("vmcall\n\t" 5290 "nop\n\t"); 5291 5292 handle_exception(UD_VECTOR, NULL); 5293 } 5294 5295 static void verify_nmi_window_exit(u64 rip) 5296 { 5297 u32 exit_reason = vmcs_read(EXI_REASON); 5298 5299 report("Exit reason (%d) is 'NMI window'", 5300 exit_reason == VMX_NMI_WINDOW, exit_reason); 5301 report("RIP (%#lx) is %#lx", vmcs_read(GUEST_RIP) == rip, 5302 vmcs_read(GUEST_RIP), rip); 5303 report("Activity state (%ld) is 'ACTIVE'", 5304 vmcs_read(GUEST_ACTV_STATE) == ACTV_ACTIVE, 5305 vmcs_read(GUEST_ACTV_STATE)); 5306 } 5307 5308 static void vmx_nmi_window_test(void) 5309 { 5310 u64 nop_addr; 5311 void *ud_fault_addr = get_idt_addr(&boot_idt[UD_VECTOR]); 5312 5313 if (!(ctrl_pin_rev.clr & PIN_VIRT_NMI)) { 5314 report_skip("CPU does not support the \"Virtual NMIs\" VM-execution control."); 5315 return; 5316 } 5317 5318 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 5319 report_skip("CPU does not support the \"NMI-window exiting\" VM-execution control."); 5320 return; 5321 } 5322 5323 vmx_window_test_ud_count = 0; 5324 5325 report_prefix_push("NMI-window"); 5326 test_set_guest(vmx_nmi_window_test_guest); 5327 vmcs_set_bits(PIN_CONTROLS, PIN_VIRT_NMI); 5328 enter_guest(); 5329 skip_exit_vmcall(); 5330 nop_addr = vmcs_read(GUEST_RIP); 5331 5332 /* 5333 * Ask for "NMI-window exiting," and expect an immediate VM-exit. 5334 * RIP will not advance. 5335 */ 5336 report_prefix_push("active, no blocking"); 5337 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 5338 enter_guest(); 5339 verify_nmi_window_exit(nop_addr); 5340 report_prefix_pop(); 5341 5342 /* 5343 * Ask for "NMI-window exiting" in a MOV-SS shadow, and expect 5344 * a VM-exit on the next instruction after the nop. (The nop 5345 * is one byte.) 5346 */ 5347 report_prefix_push("active, blocking by MOV-SS"); 5348 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 5349 enter_guest(); 5350 verify_nmi_window_exit(nop_addr + 1); 5351 report_prefix_pop(); 5352 5353 /* 5354 * Ask for "NMI-window exiting" (with event injection), and 5355 * expect a VM-exit after the event is injected. (RIP should 5356 * be at the address specified in the IDT entry for #UD.) 5357 */ 5358 report_prefix_push("active, no blocking, injecting #UD"); 5359 vmcs_write(ENT_INTR_INFO, 5360 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | UD_VECTOR); 5361 enter_guest(); 5362 verify_nmi_window_exit((u64)ud_fault_addr); 5363 report_prefix_pop(); 5364 5365 /* 5366 * Ask for "NMI-window exiting" with NMI blocking, and expect 5367 * a VM-exit after the next IRET (i.e. after the #UD handler 5368 * returns). So, RIP should be back at one byte past the nop. 5369 */ 5370 report_prefix_push("active, blocking by NMI"); 5371 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_NMI); 5372 enter_guest(); 5373 verify_nmi_window_exit(nop_addr + 1); 5374 report("#UD handler executed once (actual %d times)", 5375 vmx_window_test_ud_count == 1, 5376 vmx_window_test_ud_count); 5377 report_prefix_pop(); 5378 5379 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 5380 report_skip("CPU does not support activity state HLT."); 5381 } else { 5382 /* 5383 * Ask for "NMI-window exiting" when entering activity 5384 * state HLT, and expect an immediate VM-exit. RIP is 5385 * still one byte past the nop. 5386 */ 5387 report_prefix_push("halted, no blocking"); 5388 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 5389 enter_guest(); 5390 verify_nmi_window_exit(nop_addr + 1); 5391 report_prefix_pop(); 5392 5393 /* 5394 * Ask for "NMI-window exiting" when entering activity 5395 * state HLT (with event injection), and expect a 5396 * VM-exit after the event is injected. (RIP should be 5397 * at the address specified in the IDT entry for #UD.) 5398 */ 5399 report_prefix_push("halted, no blocking, injecting #UD"); 5400 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 5401 vmcs_write(ENT_INTR_INFO, 5402 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 5403 UD_VECTOR); 5404 enter_guest(); 5405 verify_nmi_window_exit((u64)ud_fault_addr); 5406 report_prefix_pop(); 5407 } 5408 5409 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 5410 enter_guest(); 5411 report_prefix_pop(); 5412 } 5413 5414 static void vmx_intr_window_test_guest(void) 5415 { 5416 handle_exception(UD_VECTOR, vmx_window_test_ud_handler); 5417 5418 /* 5419 * The two consecutive STIs are to ensure that only the first 5420 * one has a shadow. Note that NOP and STI are one byte 5421 * instructions. 5422 */ 5423 asm volatile("vmcall\n\t" 5424 "nop\n\t" 5425 "sti\n\t" 5426 "sti\n\t"); 5427 5428 handle_exception(UD_VECTOR, NULL); 5429 } 5430 5431 static void verify_intr_window_exit(u64 rip) 5432 { 5433 u32 exit_reason = vmcs_read(EXI_REASON); 5434 5435 report("Exit reason (%d) is 'interrupt window'", 5436 exit_reason == VMX_INTR_WINDOW, exit_reason); 5437 report("RIP (%#lx) is %#lx", vmcs_read(GUEST_RIP) == rip, 5438 vmcs_read(GUEST_RIP), rip); 5439 report("Activity state (%ld) is 'ACTIVE'", 5440 vmcs_read(GUEST_ACTV_STATE) == ACTV_ACTIVE, 5441 vmcs_read(GUEST_ACTV_STATE)); 5442 } 5443 5444 static void vmx_intr_window_test(void) 5445 { 5446 u64 vmcall_addr; 5447 u64 nop_addr; 5448 unsigned int orig_ud_gate_type; 5449 void *ud_fault_addr = get_idt_addr(&boot_idt[UD_VECTOR]); 5450 5451 if (!(ctrl_cpu_rev[0].clr & CPU_INTR_WINDOW)) { 5452 report_skip("CPU does not support the \"interrupt-window exiting\" VM-execution control."); 5453 return; 5454 } 5455 5456 /* 5457 * Change the IDT entry for #UD from interrupt gate to trap gate, 5458 * so that it won't clear RFLAGS.IF. We don't want interrupts to 5459 * be disabled after vectoring a #UD. 5460 */ 5461 orig_ud_gate_type = boot_idt[UD_VECTOR].type; 5462 boot_idt[UD_VECTOR].type = 15; 5463 5464 report_prefix_push("interrupt-window"); 5465 test_set_guest(vmx_intr_window_test_guest); 5466 enter_guest(); 5467 assert_exit_reason(VMX_VMCALL); 5468 vmcall_addr = vmcs_read(GUEST_RIP); 5469 5470 /* 5471 * Ask for "interrupt-window exiting" with RFLAGS.IF set and 5472 * no blocking; expect an immediate VM-exit. Note that we have 5473 * not advanced past the vmcall instruction yet, so RIP should 5474 * point to the vmcall instruction. 5475 */ 5476 report_prefix_push("active, no blocking, RFLAGS.IF=1"); 5477 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 5478 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_IF); 5479 enter_guest(); 5480 verify_intr_window_exit(vmcall_addr); 5481 report_prefix_pop(); 5482 5483 /* 5484 * Ask for "interrupt-window exiting" (with event injection) 5485 * with RFLAGS.IF set and no blocking; expect a VM-exit after 5486 * the event is injected. That is, RIP should should be at the 5487 * address specified in the IDT entry for #UD. 5488 */ 5489 report_prefix_push("active, no blocking, RFLAGS.IF=1, injecting #UD"); 5490 vmcs_write(ENT_INTR_INFO, 5491 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | UD_VECTOR); 5492 vmcall_addr = vmcs_read(GUEST_RIP); 5493 enter_guest(); 5494 verify_intr_window_exit((u64)ud_fault_addr); 5495 report_prefix_pop(); 5496 5497 /* 5498 * Let the L2 guest run through the IRET, back to the VMCALL. 5499 * We have to clear the "interrupt-window exiting" 5500 * VM-execution control, or it would just keep causing 5501 * VM-exits. Then, advance past the VMCALL and set the 5502 * "interrupt-window exiting" VM-execution control again. 5503 */ 5504 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 5505 enter_guest(); 5506 skip_exit_vmcall(); 5507 nop_addr = vmcs_read(GUEST_RIP); 5508 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 5509 5510 /* 5511 * Ask for "interrupt-window exiting" in a MOV-SS shadow with 5512 * RFLAGS.IF set, and expect a VM-exit on the next 5513 * instruction. (NOP is one byte.) 5514 */ 5515 report_prefix_push("active, blocking by MOV-SS, RFLAGS.IF=1"); 5516 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 5517 enter_guest(); 5518 verify_intr_window_exit(nop_addr + 1); 5519 report_prefix_pop(); 5520 5521 /* 5522 * Back up to the NOP and ask for "interrupt-window exiting" 5523 * in an STI shadow with RFLAGS.IF set, and expect a VM-exit 5524 * on the next instruction. (NOP is one byte.) 5525 */ 5526 report_prefix_push("active, blocking by STI, RFLAGS.IF=1"); 5527 vmcs_write(GUEST_RIP, nop_addr); 5528 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_STI); 5529 enter_guest(); 5530 verify_intr_window_exit(nop_addr + 1); 5531 report_prefix_pop(); 5532 5533 /* 5534 * Ask for "interrupt-window exiting" with RFLAGS.IF clear, 5535 * and expect a VM-exit on the instruction following the STI 5536 * shadow. Only the first STI (which is one byte past the NOP) 5537 * should have a shadow. The second STI (which is two bytes 5538 * past the NOP) has no shadow. Therefore, the interrupt 5539 * window opens at three bytes past the NOP. 5540 */ 5541 report_prefix_push("active, RFLAGS.IF = 0"); 5542 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 5543 enter_guest(); 5544 verify_intr_window_exit(nop_addr + 3); 5545 report_prefix_pop(); 5546 5547 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 5548 report_skip("CPU does not support activity state HLT."); 5549 } else { 5550 /* 5551 * Ask for "interrupt-window exiting" when entering 5552 * activity state HLT, and expect an immediate 5553 * VM-exit. RIP is still three bytes past the nop. 5554 */ 5555 report_prefix_push("halted, no blocking"); 5556 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 5557 enter_guest(); 5558 verify_intr_window_exit(nop_addr + 3); 5559 report_prefix_pop(); 5560 5561 /* 5562 * Ask for "interrupt-window exiting" when entering 5563 * activity state HLT (with event injection), and 5564 * expect a VM-exit after the event is injected. That 5565 * is, RIP should should be at the address specified 5566 * in the IDT entry for #UD. 5567 */ 5568 report_prefix_push("halted, no blocking, injecting #UD"); 5569 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 5570 vmcs_write(ENT_INTR_INFO, 5571 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 5572 UD_VECTOR); 5573 enter_guest(); 5574 verify_intr_window_exit((u64)ud_fault_addr); 5575 report_prefix_pop(); 5576 } 5577 5578 boot_idt[UD_VECTOR].type = orig_ud_gate_type; 5579 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 5580 enter_guest(); 5581 report_prefix_pop(); 5582 } 5583 5584 #define GUEST_TSC_OFFSET (1u << 30) 5585 5586 static u64 guest_tsc; 5587 5588 static void vmx_store_tsc_test_guest(void) 5589 { 5590 guest_tsc = rdtsc(); 5591 } 5592 5593 /* 5594 * This test ensures that when IA32_TSC is in the VM-exit MSR-store 5595 * list, the value saved is not subject to the TSC offset that is 5596 * applied to RDTSC/RDTSCP/RDMSR(IA32_TSC) in guest execution. 5597 */ 5598 static void vmx_store_tsc_test(void) 5599 { 5600 struct vmx_msr_entry msr_entry = { .index = MSR_IA32_TSC }; 5601 u64 low, high; 5602 5603 if (!(ctrl_cpu_rev[0].clr & CPU_USE_TSC_OFFSET)) { 5604 report_skip("'Use TSC offsetting' not supported"); 5605 return; 5606 } 5607 5608 test_set_guest(vmx_store_tsc_test_guest); 5609 5610 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_USE_TSC_OFFSET); 5611 vmcs_write(EXI_MSR_ST_CNT, 1); 5612 vmcs_write(EXIT_MSR_ST_ADDR, virt_to_phys(&msr_entry)); 5613 vmcs_write(TSC_OFFSET, GUEST_TSC_OFFSET); 5614 5615 low = rdtsc(); 5616 enter_guest(); 5617 high = rdtsc(); 5618 5619 report("RDTSC value in the guest (%lu) is in range [%lu, %lu]", 5620 low + GUEST_TSC_OFFSET <= guest_tsc && 5621 guest_tsc <= high + GUEST_TSC_OFFSET, 5622 guest_tsc, low + GUEST_TSC_OFFSET, high + GUEST_TSC_OFFSET); 5623 report("IA32_TSC value saved in the VM-exit MSR-store list (%lu) is in range [%lu, %lu]", 5624 low <= msr_entry.value && msr_entry.value <= high, 5625 msr_entry.value, low, high); 5626 } 5627 5628 static void vmx_db_test_guest(void) 5629 { 5630 /* 5631 * For a hardware generated single-step #DB. 5632 */ 5633 asm volatile("vmcall;" 5634 "nop;" 5635 ".Lpost_nop:"); 5636 /* 5637 * ...in a MOVSS shadow, with pending debug exceptions. 5638 */ 5639 asm volatile("vmcall;" 5640 "nop;" 5641 ".Lpost_movss_nop:"); 5642 /* 5643 * For an L0 synthesized single-step #DB. (L0 intercepts WBINVD and 5644 * emulates it in software.) 5645 */ 5646 asm volatile("vmcall;" 5647 "wbinvd;" 5648 ".Lpost_wbinvd:"); 5649 /* 5650 * ...in a MOVSS shadow, with pending debug exceptions. 5651 */ 5652 asm volatile("vmcall;" 5653 "wbinvd;" 5654 ".Lpost_movss_wbinvd:"); 5655 /* 5656 * For a hardware generated single-step #DB in a transactional region. 5657 */ 5658 asm volatile("vmcall;" 5659 ".Lxbegin: xbegin .Lskip_rtm;" 5660 "xend;" 5661 ".Lskip_rtm:"); 5662 } 5663 5664 /* 5665 * Clear the pending debug exceptions and RFLAGS.TF and re-enter 5666 * L2. No #DB is delivered and L2 continues to the next point of 5667 * interest. 5668 */ 5669 static void dismiss_db(void) 5670 { 5671 vmcs_write(GUEST_PENDING_DEBUG, 0); 5672 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 5673 enter_guest(); 5674 } 5675 5676 /* 5677 * Check a variety of VMCS fields relevant to an intercepted #DB exception. 5678 * Then throw away the #DB exception and resume L2. 5679 */ 5680 static void check_db_exit(bool xfail_qual, bool xfail_dr6, bool xfail_pdbg, 5681 void *expected_rip, u64 expected_exit_qual, 5682 u64 expected_dr6) 5683 { 5684 u32 reason = vmcs_read(EXI_REASON); 5685 u32 intr_info = vmcs_read(EXI_INTR_INFO); 5686 u64 exit_qual = vmcs_read(EXI_QUALIFICATION); 5687 u64 guest_rip = vmcs_read(GUEST_RIP); 5688 u64 guest_pending_dbg = vmcs_read(GUEST_PENDING_DEBUG); 5689 u64 dr6 = read_dr6(); 5690 const u32 expected_intr_info = INTR_INFO_VALID_MASK | 5691 INTR_TYPE_HARD_EXCEPTION | DB_VECTOR; 5692 5693 report("Expected #DB VM-exit", 5694 reason == VMX_EXC_NMI && intr_info == expected_intr_info); 5695 report("Expected RIP %p (actual %lx)", (u64)expected_rip == guest_rip, 5696 expected_rip, guest_rip); 5697 report_xfail("Expected pending debug exceptions 0 (actual %lx)", 5698 xfail_pdbg, 0 == guest_pending_dbg, guest_pending_dbg); 5699 report_xfail("Expected exit qualification %lx (actual %lx)", xfail_qual, 5700 expected_exit_qual == exit_qual, 5701 expected_exit_qual, exit_qual); 5702 report_xfail("Expected DR6 %lx (actual %lx)", xfail_dr6, 5703 expected_dr6 == dr6, expected_dr6, dr6); 5704 dismiss_db(); 5705 } 5706 5707 /* 5708 * Assuming the guest has just exited on a VMCALL instruction, skip 5709 * over the vmcall, and set the guest's RFLAGS.TF in the VMCS. If 5710 * pending debug exceptions are non-zero, set the VMCS up as if the 5711 * previous instruction was a MOVSS that generated the indicated 5712 * pending debug exceptions. Then enter L2. 5713 */ 5714 static void single_step_guest(const char *test_name, u64 starting_dr6, 5715 u64 pending_debug_exceptions) 5716 { 5717 printf("\n%s\n", test_name); 5718 skip_exit_vmcall(); 5719 write_dr6(starting_dr6); 5720 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_TF); 5721 if (pending_debug_exceptions) { 5722 vmcs_write(GUEST_PENDING_DEBUG, pending_debug_exceptions); 5723 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 5724 } 5725 enter_guest(); 5726 } 5727 5728 /* 5729 * When L1 intercepts #DB, verify that a single-step trap clears 5730 * pending debug exceptions, populates the exit qualification field 5731 * properly, and that DR6 is not prematurely clobbered. In a 5732 * (simulated) MOVSS shadow, make sure that the pending debug 5733 * exception bits are properly accumulated into the exit qualification 5734 * field. 5735 */ 5736 static void vmx_db_test(void) 5737 { 5738 /* 5739 * We are going to set a few arbitrary bits in DR6 to verify that 5740 * (a) DR6 is not modified by an intercepted #DB, and 5741 * (b) stale bits in DR6 (DR6.BD, in particular) don't leak into 5742 * the exit qualification field for a subsequent #DB exception. 5743 */ 5744 const u64 starting_dr6 = DR6_RESERVED | BIT(13) | DR_TRAP3 | DR_TRAP1; 5745 extern char post_nop asm(".Lpost_nop"); 5746 extern char post_movss_nop asm(".Lpost_movss_nop"); 5747 extern char post_wbinvd asm(".Lpost_wbinvd"); 5748 extern char post_movss_wbinvd asm(".Lpost_movss_wbinvd"); 5749 extern char xbegin asm(".Lxbegin"); 5750 extern char skip_rtm asm(".Lskip_rtm"); 5751 5752 /* 5753 * L1 wants to intercept #DB exceptions encountered in L2. 5754 */ 5755 vmcs_write(EXC_BITMAP, BIT(DB_VECTOR)); 5756 5757 /* 5758 * Start L2 and run it up to the first point of interest. 5759 */ 5760 test_set_guest(vmx_db_test_guest); 5761 enter_guest(); 5762 5763 /* 5764 * Hardware-delivered #DB trap for single-step sets the 5765 * standard that L0 has to follow for emulated instructions. 5766 */ 5767 single_step_guest("Hardware delivered single-step", starting_dr6, 0); 5768 check_db_exit(false, false, false, &post_nop, DR_STEP, starting_dr6); 5769 5770 /* 5771 * Hardware-delivered #DB trap for single-step in MOVSS shadow 5772 * also sets the standard that L0 has to follow for emulated 5773 * instructions. Here, we establish the VMCS pending debug 5774 * exceptions to indicate that the simulated MOVSS triggered a 5775 * data breakpoint as well as the single-step trap. 5776 */ 5777 single_step_guest("Hardware delivered single-step in MOVSS shadow", 5778 starting_dr6, BIT(12) | DR_STEP | DR_TRAP0 ); 5779 check_db_exit(false, false, false, &post_movss_nop, DR_STEP | DR_TRAP0, 5780 starting_dr6); 5781 5782 /* 5783 * L0 synthesized #DB trap for single-step is buggy, because 5784 * kvm (a) clobbers DR6 too early, and (b) tries its best to 5785 * reconstitute the exit qualification from the prematurely 5786 * modified DR6, but fails miserably. 5787 */ 5788 single_step_guest("Software synthesized single-step", starting_dr6, 0); 5789 check_db_exit(true, true, false, &post_wbinvd, DR_STEP, starting_dr6); 5790 5791 /* 5792 * L0 synthesized #DB trap for single-step in MOVSS shadow is 5793 * even worse, because L0 also leaves the pending debug 5794 * exceptions in the VMCS instead of accumulating them into 5795 * the exit qualification field for the #DB exception. 5796 */ 5797 single_step_guest("Software synthesized single-step in MOVSS shadow", 5798 starting_dr6, BIT(12) | DR_STEP | DR_TRAP0); 5799 check_db_exit(true, true, true, &post_movss_wbinvd, DR_STEP | DR_TRAP0, 5800 starting_dr6); 5801 5802 /* 5803 * Optional RTM test for hardware that supports RTM, to 5804 * demonstrate that the current volume 3 of the SDM 5805 * (325384-067US), table 27-1 is incorrect. Bit 16 of the exit 5806 * qualification for debug exceptions is not reserved. It is 5807 * set to 1 if a debug exception (#DB) or a breakpoint 5808 * exception (#BP) occurs inside an RTM region while advanced 5809 * debugging of RTM transactional regions is enabled. 5810 */ 5811 if (cpuid(7).b & BIT(11)) { 5812 vmcs_write(ENT_CONTROLS, 5813 vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 5814 /* 5815 * Set DR7.RTM[bit 11] and IA32_DEBUGCTL.RTM[bit 15] 5816 * in the guest to enable advanced debugging of RTM 5817 * transactional regions. 5818 */ 5819 vmcs_write(GUEST_DR7, BIT(11)); 5820 vmcs_write(GUEST_DEBUGCTL, BIT(15)); 5821 single_step_guest("Hardware delivered single-step in " 5822 "transactional region", starting_dr6, 0); 5823 check_db_exit(false, false, false, &xbegin, BIT(16), 5824 starting_dr6); 5825 } else { 5826 vmcs_write(GUEST_RIP, (u64)&skip_rtm); 5827 enter_guest(); 5828 } 5829 } 5830 5831 static bool cpu_has_apicv(void) 5832 { 5833 return ((ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT) && 5834 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 5835 (ctrl_pin_rev.clr & PIN_POST_INTR)); 5836 } 5837 5838 static void enable_vid(void) 5839 { 5840 void *virtual_apic_page; 5841 5842 assert(cpu_has_apicv()); 5843 5844 disable_intercept_for_x2apic_msrs(); 5845 5846 virtual_apic_page = alloc_page(); 5847 vmcs_write(APIC_VIRT_ADDR, (u64)virtual_apic_page); 5848 5849 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 5850 5851 vmcs_write(EOI_EXIT_BITMAP0, 0x0); 5852 vmcs_write(EOI_EXIT_BITMAP1, 0x0); 5853 vmcs_write(EOI_EXIT_BITMAP2, 0x0); 5854 vmcs_write(EOI_EXIT_BITMAP3, 0x0); 5855 5856 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY | CPU_TPR_SHADOW); 5857 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_VINTD | CPU_VIRT_X2APIC); 5858 } 5859 5860 static void trigger_ioapic_scan_thread(void *data) 5861 { 5862 /* Wait until other CPU entered L2 */ 5863 while (vmx_get_test_stage() != 1) 5864 ; 5865 5866 /* Trigger ioapic scan */ 5867 ioapic_set_redir(0xf, 0x79, TRIGGER_LEVEL); 5868 vmx_set_test_stage(2); 5869 } 5870 5871 static void irq_79_handler_guest(isr_regs_t *regs) 5872 { 5873 eoi(); 5874 5875 /* L1 expects vmexit on VMX_VMCALL and not VMX_EOI_INDUCED */ 5876 vmcall(); 5877 } 5878 5879 /* 5880 * Constant for num of busy-loop iterations after which 5881 * a timer interrupt should have happened in host 5882 */ 5883 #define TIMER_INTERRUPT_DELAY 100000000 5884 5885 static void vmx_eoi_bitmap_ioapic_scan_test_guest(void) 5886 { 5887 handle_irq(0x79, irq_79_handler_guest); 5888 irq_enable(); 5889 5890 /* Signal to L1 CPU to trigger ioapic scan */ 5891 vmx_set_test_stage(1); 5892 /* Wait until L1 CPU to trigger ioapic scan */ 5893 while (vmx_get_test_stage() != 2) 5894 ; 5895 5896 /* 5897 * Wait for L0 timer interrupt to be raised while we run in L2 5898 * such that L0 will process the IOAPIC scan request before 5899 * resuming L2 5900 */ 5901 delay(TIMER_INTERRUPT_DELAY); 5902 5903 asm volatile ("int $0x79"); 5904 } 5905 5906 static void vmx_eoi_bitmap_ioapic_scan_test(void) 5907 { 5908 if (!cpu_has_apicv() || (cpu_count() < 2)) { 5909 report_skip(__func__); 5910 return; 5911 } 5912 5913 enable_vid(); 5914 5915 on_cpu_async(1, trigger_ioapic_scan_thread, NULL); 5916 test_set_guest(vmx_eoi_bitmap_ioapic_scan_test_guest); 5917 5918 /* 5919 * Launch L2. 5920 * We expect the exit reason to be VMX_VMCALL (and not EOI INDUCED). 5921 * In case the reason isn't VMX_VMCALL, the asserion inside 5922 * skip_exit_vmcall() will fail. 5923 */ 5924 enter_guest(); 5925 skip_exit_vmcall(); 5926 5927 /* Let L2 finish */ 5928 enter_guest(); 5929 report(__func__, 1); 5930 } 5931 5932 #define HLT_WITH_RVI_VECTOR (0xf1) 5933 5934 bool vmx_hlt_with_rvi_guest_isr_fired; 5935 static void vmx_hlt_with_rvi_guest_isr(isr_regs_t *regs) 5936 { 5937 vmx_hlt_with_rvi_guest_isr_fired = true; 5938 eoi(); 5939 } 5940 5941 static void vmx_hlt_with_rvi_guest(void) 5942 { 5943 handle_irq(HLT_WITH_RVI_VECTOR, vmx_hlt_with_rvi_guest_isr); 5944 5945 irq_enable(); 5946 asm volatile ("nop"); 5947 5948 vmcall(); 5949 } 5950 5951 static void vmx_hlt_with_rvi_test(void) 5952 { 5953 if (!cpu_has_apicv()) { 5954 report_skip(__func__); 5955 return; 5956 } 5957 5958 enable_vid(); 5959 5960 vmx_hlt_with_rvi_guest_isr_fired = false; 5961 test_set_guest(vmx_hlt_with_rvi_guest); 5962 5963 enter_guest(); 5964 skip_exit_vmcall(); 5965 5966 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 5967 vmcs_write(GUEST_INT_STATUS, HLT_WITH_RVI_VECTOR); 5968 enter_guest(); 5969 5970 report("Interrupt raised in guest", vmx_hlt_with_rvi_guest_isr_fired); 5971 } 5972 5973 static void set_irq_line_thread(void *data) 5974 { 5975 /* Wait until other CPU entered L2 */ 5976 while (vmx_get_test_stage() != 1) 5977 ; 5978 5979 /* Set irq-line 0xf to raise vector 0x78 for vCPU 0 */ 5980 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 5981 vmx_set_test_stage(2); 5982 } 5983 5984 static bool irq_78_handler_vmcall_before_eoi; 5985 static void irq_78_handler_guest(isr_regs_t *regs) 5986 { 5987 set_irq_line(0xf, 0); 5988 if (irq_78_handler_vmcall_before_eoi) 5989 vmcall(); 5990 eoi(); 5991 vmcall(); 5992 } 5993 5994 static void vmx_apic_passthrough_guest(void) 5995 { 5996 handle_irq(0x78, irq_78_handler_guest); 5997 irq_enable(); 5998 5999 /* If requested, wait for other CPU to trigger ioapic scan */ 6000 if (vmx_get_test_stage() < 1) { 6001 vmx_set_test_stage(1); 6002 while (vmx_get_test_stage() != 2) 6003 ; 6004 } 6005 6006 set_irq_line(0xf, 1); 6007 } 6008 6009 static void vmx_apic_passthrough(bool set_irq_line_from_thread) 6010 { 6011 if (set_irq_line_from_thread && (cpu_count() < 2)) { 6012 report_skip(__func__); 6013 return; 6014 } 6015 6016 u64 cpu_ctrl_0 = CPU_SECONDARY; 6017 u64 cpu_ctrl_1 = 0; 6018 6019 disable_intercept_for_x2apic_msrs(); 6020 6021 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 6022 6023 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 6024 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 6025 6026 if (set_irq_line_from_thread) { 6027 irq_78_handler_vmcall_before_eoi = false; 6028 on_cpu_async(1, set_irq_line_thread, NULL); 6029 } else { 6030 irq_78_handler_vmcall_before_eoi = true; 6031 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 6032 vmx_set_test_stage(2); 6033 } 6034 test_set_guest(vmx_apic_passthrough_guest); 6035 6036 if (irq_78_handler_vmcall_before_eoi) { 6037 /* Before EOI remote_irr should still be set */ 6038 enter_guest(); 6039 skip_exit_vmcall(); 6040 TEST_ASSERT_EQ_MSG(1, (int)ioapic_read_redir(0xf).remote_irr, 6041 "IOAPIC pass-through: remote_irr=1 before EOI"); 6042 } 6043 6044 /* After EOI remote_irr should be cleared */ 6045 enter_guest(); 6046 skip_exit_vmcall(); 6047 TEST_ASSERT_EQ_MSG(0, (int)ioapic_read_redir(0xf).remote_irr, 6048 "IOAPIC pass-through: remote_irr=0 after EOI"); 6049 6050 /* Let L2 finish */ 6051 enter_guest(); 6052 report(__func__, 1); 6053 } 6054 6055 static void vmx_apic_passthrough_test(void) 6056 { 6057 vmx_apic_passthrough(false); 6058 } 6059 6060 static void vmx_apic_passthrough_thread_test(void) 6061 { 6062 vmx_apic_passthrough(true); 6063 } 6064 6065 enum vmcs_access { 6066 ACCESS_VMREAD, 6067 ACCESS_VMWRITE, 6068 ACCESS_NONE, 6069 }; 6070 6071 struct vmcs_shadow_test_common { 6072 enum vmcs_access op; 6073 enum Reason reason; 6074 u64 field; 6075 u64 value; 6076 u64 flags; 6077 u64 time; 6078 } l1_l2_common; 6079 6080 static inline u64 vmread_flags(u64 field, u64 *val) 6081 { 6082 u64 flags; 6083 6084 asm volatile ("vmread %2, %1; pushf; pop %0" 6085 : "=r" (flags), "=rm" (*val) : "r" (field) : "cc"); 6086 return flags & X86_EFLAGS_ALU; 6087 } 6088 6089 static inline u64 vmwrite_flags(u64 field, u64 val) 6090 { 6091 u64 flags; 6092 6093 asm volatile ("vmwrite %1, %2; pushf; pop %0" 6094 : "=r"(flags) : "rm" (val), "r" (field) : "cc"); 6095 return flags & X86_EFLAGS_ALU; 6096 } 6097 6098 static void vmx_vmcs_shadow_test_guest(void) 6099 { 6100 struct vmcs_shadow_test_common *c = &l1_l2_common; 6101 u64 start; 6102 6103 while (c->op != ACCESS_NONE) { 6104 start = rdtsc(); 6105 switch (c->op) { 6106 default: 6107 c->flags = -1ull; 6108 break; 6109 case ACCESS_VMREAD: 6110 c->flags = vmread_flags(c->field, &c->value); 6111 break; 6112 case ACCESS_VMWRITE: 6113 c->flags = vmwrite_flags(c->field, 0); 6114 break; 6115 } 6116 c->time = rdtsc() - start; 6117 vmcall(); 6118 } 6119 } 6120 6121 static u64 vmread_from_shadow(u64 field) 6122 { 6123 struct vmcs *primary; 6124 struct vmcs *shadow; 6125 u64 value; 6126 6127 TEST_ASSERT(!vmcs_save(&primary)); 6128 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 6129 TEST_ASSERT(!make_vmcs_current(shadow)); 6130 value = vmcs_read(field); 6131 TEST_ASSERT(!make_vmcs_current(primary)); 6132 return value; 6133 } 6134 6135 static u64 vmwrite_to_shadow(u64 field, u64 value) 6136 { 6137 struct vmcs *primary; 6138 struct vmcs *shadow; 6139 6140 TEST_ASSERT(!vmcs_save(&primary)); 6141 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 6142 TEST_ASSERT(!make_vmcs_current(shadow)); 6143 vmcs_write(field, value); 6144 value = vmcs_read(field); 6145 TEST_ASSERT(!make_vmcs_current(primary)); 6146 return value; 6147 } 6148 6149 static void vmcs_shadow_test_access(u8 *bitmap[2], enum vmcs_access access) 6150 { 6151 struct vmcs_shadow_test_common *c = &l1_l2_common; 6152 6153 c->op = access; 6154 vmcs_write(VMX_INST_ERROR, 0); 6155 enter_guest(); 6156 c->reason = vmcs_read(EXI_REASON) & 0xffff; 6157 if (c->reason != VMX_VMCALL) { 6158 skip_exit_insn(); 6159 enter_guest(); 6160 } 6161 skip_exit_vmcall(); 6162 } 6163 6164 static void vmcs_shadow_test_field(u8 *bitmap[2], u64 field) 6165 { 6166 struct vmcs_shadow_test_common *c = &l1_l2_common; 6167 struct vmcs *shadow; 6168 u64 value; 6169 uintptr_t flags[2]; 6170 bool good_shadow; 6171 u32 vmx_inst_error; 6172 6173 report_prefix_pushf("field %lx", field); 6174 c->field = field; 6175 6176 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 6177 if (shadow != (struct vmcs *)-1ull) { 6178 flags[ACCESS_VMREAD] = vmread_flags(field, &value); 6179 flags[ACCESS_VMWRITE] = vmwrite_flags(field, value); 6180 good_shadow = !flags[ACCESS_VMREAD] && !flags[ACCESS_VMWRITE]; 6181 } else { 6182 /* 6183 * When VMCS link pointer is -1ull, VMWRITE/VMREAD on 6184 * shadowed-fields should fail with setting RFLAGS.CF. 6185 */ 6186 flags[ACCESS_VMREAD] = X86_EFLAGS_CF; 6187 flags[ACCESS_VMWRITE] = X86_EFLAGS_CF; 6188 good_shadow = false; 6189 } 6190 6191 /* Intercept both VMREAD and VMWRITE. */ 6192 report_prefix_push("no VMREAD/VMWRITE permission"); 6193 /* VMWRITE/VMREAD done on reserved-bit should always intercept */ 6194 if (!(field >> VMCS_FIELD_RESERVED_SHIFT)) { 6195 set_bit(field, bitmap[ACCESS_VMREAD]); 6196 set_bit(field, bitmap[ACCESS_VMWRITE]); 6197 } 6198 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 6199 report("not shadowed for VMWRITE", c->reason == VMX_VMWRITE); 6200 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 6201 report("not shadowed for VMREAD", c->reason == VMX_VMREAD); 6202 report_prefix_pop(); 6203 6204 if (field >> VMCS_FIELD_RESERVED_SHIFT) 6205 goto out; 6206 6207 /* Permit shadowed VMREAD. */ 6208 report_prefix_push("VMREAD permission only"); 6209 clear_bit(field, bitmap[ACCESS_VMREAD]); 6210 set_bit(field, bitmap[ACCESS_VMWRITE]); 6211 if (good_shadow) 6212 value = vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 6213 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 6214 report("not shadowed for VMWRITE", c->reason == VMX_VMWRITE); 6215 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 6216 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 6217 report("shadowed for VMREAD (in %ld cycles)", c->reason == VMX_VMCALL, 6218 c->time); 6219 report("ALU flags after VMREAD (%lx) are as expected (%lx)", 6220 c->flags == flags[ACCESS_VMREAD], 6221 c->flags, flags[ACCESS_VMREAD]); 6222 if (good_shadow) 6223 report("value read from shadow (%lx) is as expected (%lx)", 6224 c->value == value, c->value, value); 6225 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 6226 report("VMX_INST_ERROR (%d) is as expected (%d)", 6227 vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 6228 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 6229 report_prefix_pop(); 6230 6231 /* Permit shadowed VMWRITE. */ 6232 report_prefix_push("VMWRITE permission only"); 6233 set_bit(field, bitmap[ACCESS_VMREAD]); 6234 clear_bit(field, bitmap[ACCESS_VMWRITE]); 6235 if (good_shadow) 6236 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 6237 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 6238 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 6239 report("shadowed for VMWRITE (in %ld cycles)", c->reason == VMX_VMCALL, 6240 c->time); 6241 report("ALU flags after VMWRITE (%lx) are as expected (%lx)", 6242 c->flags == flags[ACCESS_VMREAD], 6243 c->flags, flags[ACCESS_VMREAD]); 6244 if (good_shadow) { 6245 value = vmread_from_shadow(field); 6246 report("shadow VMCS value (%lx) is as expected (%lx)", 6247 value == 0, value, 0ul); 6248 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 6249 report("VMX_INST_ERROR (%d) is as expected (%d)", 6250 vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 6251 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 6252 } 6253 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 6254 report("not shadowed for VMREAD", c->reason == VMX_VMREAD); 6255 report_prefix_pop(); 6256 6257 /* Permit shadowed VMREAD and VMWRITE. */ 6258 report_prefix_push("VMREAD and VMWRITE permission"); 6259 clear_bit(field, bitmap[ACCESS_VMREAD]); 6260 clear_bit(field, bitmap[ACCESS_VMWRITE]); 6261 if (good_shadow) 6262 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 6263 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 6264 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 6265 report("shadowed for VMWRITE (in %ld cycles)", c->reason == VMX_VMCALL, 6266 c->time); 6267 report("ALU flags after VMWRITE (%lx) are as expected (%lx)", 6268 c->flags == flags[ACCESS_VMREAD], 6269 c->flags, flags[ACCESS_VMREAD]); 6270 if (good_shadow) { 6271 value = vmread_from_shadow(field); 6272 report("shadow VMCS value (%lx) is as expected (%lx)", 6273 value == 0, value, 0ul); 6274 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 6275 report("VMX_INST_ERROR (%d) is as expected (%d)", 6276 vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 6277 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 6278 } 6279 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 6280 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 6281 report("shadowed for VMREAD (in %ld cycles)", c->reason == VMX_VMCALL, 6282 c->time); 6283 report("ALU flags after VMREAD (%lx) are as expected (%lx)", 6284 c->flags == flags[ACCESS_VMREAD], 6285 c->flags, flags[ACCESS_VMREAD]); 6286 if (good_shadow) 6287 report("value read from shadow (%lx) is as expected (%lx)", 6288 c->value == 0, c->value, 0ul); 6289 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 6290 report("VMX_INST_ERROR (%d) is as expected (%d)", 6291 vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 6292 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 6293 report_prefix_pop(); 6294 6295 out: 6296 report_prefix_pop(); 6297 } 6298 6299 static void vmx_vmcs_shadow_test_body(u8 *bitmap[2]) 6300 { 6301 unsigned base; 6302 unsigned index; 6303 unsigned bit; 6304 unsigned highest_index = rdmsr(MSR_IA32_VMX_VMCS_ENUM); 6305 6306 /* Run test on all possible valid VMCS fields */ 6307 for (base = 0; 6308 base < (1 << VMCS_FIELD_RESERVED_SHIFT); 6309 base += (1 << VMCS_FIELD_TYPE_SHIFT)) 6310 for (index = 0; index <= highest_index; index++) 6311 vmcs_shadow_test_field(bitmap, base + index); 6312 6313 /* 6314 * Run tests on some invalid VMCS fields 6315 * (Have reserved bit set). 6316 */ 6317 for (bit = VMCS_FIELD_RESERVED_SHIFT; bit < VMCS_FIELD_BIT_SIZE; bit++) 6318 vmcs_shadow_test_field(bitmap, (1ull << bit)); 6319 } 6320 6321 static void vmx_vmcs_shadow_test(void) 6322 { 6323 u8 *bitmap[2]; 6324 struct vmcs *shadow; 6325 6326 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 6327 printf("\t'Activate secondary controls' not supported.\n"); 6328 return; 6329 } 6330 6331 if (!(ctrl_cpu_rev[1].clr & CPU_SHADOW_VMCS)) { 6332 printf("\t'VMCS shadowing' not supported.\n"); 6333 return; 6334 } 6335 6336 if (!(rdmsr(MSR_IA32_VMX_MISC) & 6337 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS)) { 6338 printf("\tVMWRITE can't modify VM-exit information fields.\n"); 6339 return; 6340 } 6341 6342 test_set_guest(vmx_vmcs_shadow_test_guest); 6343 6344 bitmap[ACCESS_VMREAD] = alloc_page(); 6345 bitmap[ACCESS_VMWRITE] = alloc_page(); 6346 6347 vmcs_write(VMREAD_BITMAP, virt_to_phys(bitmap[ACCESS_VMREAD])); 6348 vmcs_write(VMWRITE_BITMAP, virt_to_phys(bitmap[ACCESS_VMWRITE])); 6349 6350 shadow = alloc_page(); 6351 shadow->hdr.revision_id = basic.revision; 6352 shadow->hdr.shadow_vmcs = 1; 6353 TEST_ASSERT(!vmcs_clear(shadow)); 6354 6355 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_RDTSC); 6356 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY); 6357 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_SHADOW_VMCS); 6358 6359 vmcs_write(VMCS_LINK_PTR, virt_to_phys(shadow)); 6360 report_prefix_push("valid link pointer"); 6361 vmx_vmcs_shadow_test_body(bitmap); 6362 report_prefix_pop(); 6363 6364 vmcs_write(VMCS_LINK_PTR, -1ull); 6365 report_prefix_push("invalid link pointer"); 6366 vmx_vmcs_shadow_test_body(bitmap); 6367 report_prefix_pop(); 6368 6369 l1_l2_common.op = ACCESS_NONE; 6370 enter_guest(); 6371 } 6372 6373 6374 6375 static int invalid_msr_init(struct vmcs *vmcs) 6376 { 6377 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 6378 printf("\tPreemption timer is not supported\n"); 6379 return VMX_TEST_EXIT; 6380 } 6381 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 6382 preempt_val = 10000000; 6383 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 6384 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 6385 6386 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 6387 printf("\tSave preemption value is not supported\n"); 6388 6389 vmcs_write(ENT_MSR_LD_CNT, 1); 6390 vmcs_write(ENTER_MSR_LD_ADDR, (u64)0x13370000); 6391 6392 return VMX_TEST_START; 6393 } 6394 6395 6396 static void invalid_msr_main(void) 6397 { 6398 report("Invalid MSR load", 0); 6399 } 6400 6401 static int invalid_msr_exit_handler(void) 6402 { 6403 report("Invalid MSR load", 0); 6404 print_vmexit_info(); 6405 return VMX_TEST_EXIT; 6406 } 6407 6408 static int invalid_msr_entry_failure(struct vmentry_failure *failure) 6409 { 6410 ulong reason; 6411 6412 reason = vmcs_read(EXI_REASON); 6413 report("Invalid MSR load", reason == (0x80000000u | VMX_FAIL_MSR)); 6414 return VMX_TEST_VMEXIT; 6415 } 6416 6417 6418 #define TEST(name) { #name, .v2 = name } 6419 6420 /* name/init/guest_main/exit_handler/syscall_handler/guest_regs */ 6421 struct vmx_test vmx_tests[] = { 6422 { "null", NULL, basic_guest_main, basic_exit_handler, NULL, {0} }, 6423 { "vmenter", NULL, vmenter_main, vmenter_exit_handler, NULL, {0} }, 6424 { "preemption timer", preemption_timer_init, preemption_timer_main, 6425 preemption_timer_exit_handler, NULL, {0} }, 6426 { "control field PAT", test_ctrl_pat_init, test_ctrl_pat_main, 6427 test_ctrl_pat_exit_handler, NULL, {0} }, 6428 { "control field EFER", test_ctrl_efer_init, test_ctrl_efer_main, 6429 test_ctrl_efer_exit_handler, NULL, {0} }, 6430 { "CR shadowing", NULL, cr_shadowing_main, 6431 cr_shadowing_exit_handler, NULL, {0} }, 6432 { "I/O bitmap", iobmp_init, iobmp_main, iobmp_exit_handler, 6433 NULL, {0} }, 6434 { "instruction intercept", insn_intercept_init, insn_intercept_main, 6435 insn_intercept_exit_handler, NULL, {0} }, 6436 { "EPT A/D disabled", ept_init, ept_main, ept_exit_handler, NULL, {0} }, 6437 { "EPT A/D enabled", eptad_init, eptad_main, eptad_exit_handler, NULL, {0} }, 6438 { "PML", pml_init, pml_main, pml_exit_handler, NULL, {0} }, 6439 { "VPID", vpid_init, vpid_main, vpid_exit_handler, NULL, {0} }, 6440 { "interrupt", interrupt_init, interrupt_main, 6441 interrupt_exit_handler, NULL, {0} }, 6442 { "debug controls", dbgctls_init, dbgctls_main, dbgctls_exit_handler, 6443 NULL, {0} }, 6444 { "MSR switch", msr_switch_init, msr_switch_main, 6445 msr_switch_exit_handler, NULL, {0}, msr_switch_entry_failure }, 6446 { "vmmcall", vmmcall_init, vmmcall_main, vmmcall_exit_handler, NULL, {0} }, 6447 { "disable RDTSCP", disable_rdtscp_init, disable_rdtscp_main, 6448 disable_rdtscp_exit_handler, NULL, {0} }, 6449 { "int3", int3_init, int3_guest_main, int3_exit_handler, NULL, {0} }, 6450 { "into", into_init, into_guest_main, into_exit_handler, NULL, {0} }, 6451 { "exit_monitor_from_l2_test", NULL, exit_monitor_from_l2_main, 6452 exit_monitor_from_l2_handler, NULL, {0} }, 6453 { "invalid_msr", invalid_msr_init, invalid_msr_main, 6454 invalid_msr_exit_handler, NULL, {0}, invalid_msr_entry_failure}, 6455 /* Basic V2 tests. */ 6456 TEST(v2_null_test), 6457 TEST(v2_multiple_entries_test), 6458 TEST(fixture_test_case1), 6459 TEST(fixture_test_case2), 6460 /* Opcode tests. */ 6461 TEST(invvpid_test_v2), 6462 /* VM-entry tests */ 6463 TEST(vmx_controls_test), 6464 TEST(vmentry_movss_shadow_test), 6465 /* APICv tests */ 6466 TEST(vmx_eoi_bitmap_ioapic_scan_test), 6467 TEST(vmx_hlt_with_rvi_test), 6468 /* APIC pass-through tests */ 6469 TEST(vmx_apic_passthrough_test), 6470 TEST(vmx_apic_passthrough_thread_test), 6471 /* VMCS Shadowing tests */ 6472 TEST(vmx_vmcs_shadow_test), 6473 /* Regression tests */ 6474 TEST(vmx_cr_load_test), 6475 TEST(vmx_nm_test), 6476 TEST(vmx_db_test), 6477 TEST(vmx_nmi_window_test), 6478 TEST(vmx_intr_window_test), 6479 TEST(vmx_pending_event_test), 6480 TEST(vmx_pending_event_hlt_test), 6481 TEST(vmx_store_tsc_test), 6482 /* EPT access tests. */ 6483 TEST(ept_access_test_not_present), 6484 TEST(ept_access_test_read_only), 6485 TEST(ept_access_test_write_only), 6486 TEST(ept_access_test_read_write), 6487 TEST(ept_access_test_execute_only), 6488 TEST(ept_access_test_read_execute), 6489 TEST(ept_access_test_write_execute), 6490 TEST(ept_access_test_read_write_execute), 6491 TEST(ept_access_test_reserved_bits), 6492 TEST(ept_access_test_ignored_bits), 6493 TEST(ept_access_test_paddr_not_present_ad_disabled), 6494 TEST(ept_access_test_paddr_not_present_ad_enabled), 6495 TEST(ept_access_test_paddr_read_only_ad_disabled), 6496 TEST(ept_access_test_paddr_read_only_ad_enabled), 6497 TEST(ept_access_test_paddr_read_write), 6498 TEST(ept_access_test_paddr_read_write_execute), 6499 TEST(ept_access_test_paddr_read_execute_ad_disabled), 6500 TEST(ept_access_test_paddr_read_execute_ad_enabled), 6501 TEST(ept_access_test_paddr_not_present_page_fault), 6502 TEST(ept_access_test_force_2m_page), 6503 { NULL, NULL, NULL, NULL, NULL, {0} }, 6504 }; 6505