1 /* 2 * All test cases of nested virtualization should be in this file 3 * 4 * Author : Arthur Chunqi Li <yzt356@gmail.com> 5 */ 6 7 #include <asm/debugreg.h> 8 9 #include "vmx.h" 10 #include "msr.h" 11 #include "processor.h" 12 #include "vm.h" 13 #include "pci.h" 14 #include "fwcfg.h" 15 #include "isr.h" 16 #include "desc.h" 17 #include "apic.h" 18 #include "types.h" 19 #include "vmalloc.h" 20 #include "alloc_page.h" 21 #include "smp.h" 22 #include "delay.h" 23 24 #define VPID_CAP_INVVPID_TYPES_SHIFT 40 25 26 u64 ia32_pat; 27 u64 ia32_efer; 28 void *io_bitmap_a, *io_bitmap_b; 29 u16 ioport; 30 31 unsigned long *pml4; 32 u64 eptp; 33 void *data_page1, *data_page2; 34 35 phys_addr_t pci_physaddr; 36 37 void *pml_log; 38 #define PML_INDEX 512 39 40 static inline unsigned ffs(unsigned x) 41 { 42 int pos = -1; 43 44 __asm__ __volatile__("bsf %1, %%eax; cmovnz %%eax, %0" 45 : "+r"(pos) : "rm"(x) : "eax"); 46 return pos + 1; 47 } 48 49 static inline void vmcall(void) 50 { 51 asm volatile("vmcall"); 52 } 53 54 static void basic_guest_main(void) 55 { 56 report(1, "Basic VMX test"); 57 } 58 59 static int basic_exit_handler(union exit_reason exit_reason) 60 { 61 report_fail("Basic VMX test"); 62 print_vmexit_info(exit_reason); 63 return VMX_TEST_EXIT; 64 } 65 66 static void vmenter_main(void) 67 { 68 u64 rax; 69 u64 rsp, resume_rsp; 70 71 report(1, "test vmlaunch"); 72 73 asm volatile( 74 "mov %%rsp, %0\n\t" 75 "mov %3, %%rax\n\t" 76 "vmcall\n\t" 77 "mov %%rax, %1\n\t" 78 "mov %%rsp, %2\n\t" 79 : "=r"(rsp), "=r"(rax), "=r"(resume_rsp) 80 : "g"(0xABCD)); 81 report((rax == 0xFFFF) && (rsp == resume_rsp), "test vmresume"); 82 } 83 84 static int vmenter_exit_handler(union exit_reason exit_reason) 85 { 86 u64 guest_rip = vmcs_read(GUEST_RIP); 87 88 switch (exit_reason.basic) { 89 case VMX_VMCALL: 90 if (regs.rax != 0xABCD) { 91 report_fail("test vmresume"); 92 return VMX_TEST_VMEXIT; 93 } 94 regs.rax = 0xFFFF; 95 vmcs_write(GUEST_RIP, guest_rip + 3); 96 return VMX_TEST_RESUME; 97 default: 98 report_fail("test vmresume"); 99 print_vmexit_info(exit_reason); 100 } 101 return VMX_TEST_VMEXIT; 102 } 103 104 u32 preempt_scale; 105 volatile unsigned long long tsc_val; 106 volatile u32 preempt_val; 107 u64 saved_rip; 108 109 static int preemption_timer_init(struct vmcs *vmcs) 110 { 111 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 112 printf("\tPreemption timer is not supported\n"); 113 return VMX_TEST_EXIT; 114 } 115 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 116 preempt_val = 10000000; 117 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 118 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 119 120 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 121 printf("\tSave preemption value is not supported\n"); 122 123 return VMX_TEST_START; 124 } 125 126 static void preemption_timer_main(void) 127 { 128 tsc_val = rdtsc(); 129 if (ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) { 130 vmx_set_test_stage(0); 131 vmcall(); 132 if (vmx_get_test_stage() == 1) 133 vmcall(); 134 } 135 vmx_set_test_stage(1); 136 while (vmx_get_test_stage() == 1) { 137 if (((rdtsc() - tsc_val) >> preempt_scale) 138 > 10 * preempt_val) { 139 vmx_set_test_stage(2); 140 vmcall(); 141 } 142 } 143 tsc_val = rdtsc(); 144 asm volatile ("hlt"); 145 vmcall(); 146 vmx_set_test_stage(5); 147 vmcall(); 148 } 149 150 static int preemption_timer_exit_handler(union exit_reason exit_reason) 151 { 152 bool guest_halted; 153 u64 guest_rip; 154 u32 insn_len; 155 u32 ctrl_exit; 156 157 guest_rip = vmcs_read(GUEST_RIP); 158 insn_len = vmcs_read(EXI_INST_LEN); 159 switch (exit_reason.basic) { 160 case VMX_PREEMPT: 161 switch (vmx_get_test_stage()) { 162 case 1: 163 case 2: 164 report(((rdtsc() - tsc_val) >> preempt_scale) >= preempt_val, 165 "busy-wait for preemption timer"); 166 vmx_set_test_stage(3); 167 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 168 return VMX_TEST_RESUME; 169 case 3: 170 guest_halted = 171 (vmcs_read(GUEST_ACTV_STATE) == ACTV_HLT); 172 report(((rdtsc() - tsc_val) >> preempt_scale) >= preempt_val 173 && guest_halted, 174 "preemption timer during hlt"); 175 vmx_set_test_stage(4); 176 vmcs_write(PIN_CONTROLS, 177 vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 178 vmcs_write(EXI_CONTROLS, 179 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_PREEMPT); 180 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 181 return VMX_TEST_RESUME; 182 case 4: 183 report(saved_rip == guest_rip, 184 "preemption timer with 0 value"); 185 break; 186 default: 187 report_fail("Invalid stage."); 188 print_vmexit_info(exit_reason); 189 break; 190 } 191 break; 192 case VMX_VMCALL: 193 vmcs_write(GUEST_RIP, guest_rip + insn_len); 194 switch (vmx_get_test_stage()) { 195 case 0: 196 report(vmcs_read(PREEMPT_TIMER_VALUE) == preempt_val, 197 "Keep preemption value"); 198 vmx_set_test_stage(1); 199 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 200 ctrl_exit = (vmcs_read(EXI_CONTROLS) | 201 EXI_SAVE_PREEMPT) & ctrl_exit_rev.clr; 202 vmcs_write(EXI_CONTROLS, ctrl_exit); 203 return VMX_TEST_RESUME; 204 case 1: 205 report(vmcs_read(PREEMPT_TIMER_VALUE) < preempt_val, 206 "Save preemption value"); 207 return VMX_TEST_RESUME; 208 case 2: 209 report_fail("busy-wait for preemption timer"); 210 vmx_set_test_stage(3); 211 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 212 return VMX_TEST_RESUME; 213 case 3: 214 report_fail("preemption timer during hlt"); 215 vmx_set_test_stage(4); 216 /* fall through */ 217 case 4: 218 vmcs_write(PIN_CONTROLS, 219 vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 220 vmcs_write(PREEMPT_TIMER_VALUE, 0); 221 saved_rip = guest_rip + insn_len; 222 return VMX_TEST_RESUME; 223 case 5: 224 report_fail("preemption timer with 0 value (vmcall stage 5)"); 225 break; 226 default: 227 // Should not reach here 228 report_fail("unexpected stage, %d", 229 vmx_get_test_stage()); 230 print_vmexit_info(exit_reason); 231 return VMX_TEST_VMEXIT; 232 } 233 break; 234 default: 235 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 236 print_vmexit_info(exit_reason); 237 } 238 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 239 return VMX_TEST_VMEXIT; 240 } 241 242 static void msr_bmp_init(void) 243 { 244 void *msr_bitmap; 245 u32 ctrl_cpu0; 246 247 msr_bitmap = alloc_page(); 248 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 249 ctrl_cpu0 |= CPU_MSR_BITMAP; 250 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 251 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 252 } 253 254 static void *get_msr_bitmap(void) 255 { 256 void *msr_bitmap; 257 258 if (vmcs_read(CPU_EXEC_CTRL0) & CPU_MSR_BITMAP) { 259 msr_bitmap = (void *)vmcs_read(MSR_BITMAP); 260 } else { 261 msr_bitmap = alloc_page(); 262 memset(msr_bitmap, 0xff, PAGE_SIZE); 263 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 264 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_MSR_BITMAP); 265 } 266 267 return msr_bitmap; 268 } 269 270 static void disable_intercept_for_x2apic_msrs(void) 271 { 272 unsigned long *msr_bitmap = (unsigned long *)get_msr_bitmap(); 273 u32 msr; 274 275 for (msr = APIC_BASE_MSR; 276 msr < (APIC_BASE_MSR+0xff); 277 msr += BITS_PER_LONG) { 278 unsigned int word = msr / BITS_PER_LONG; 279 280 msr_bitmap[word] = 0; 281 msr_bitmap[word + (0x800 / sizeof(long))] = 0; 282 } 283 } 284 285 static int test_ctrl_pat_init(struct vmcs *vmcs) 286 { 287 u64 ctrl_ent; 288 u64 ctrl_exi; 289 290 msr_bmp_init(); 291 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT) && 292 !(ctrl_exit_rev.clr & EXI_LOAD_PAT) && 293 !(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 294 printf("\tSave/load PAT is not supported\n"); 295 return 1; 296 } 297 298 ctrl_ent = vmcs_read(ENT_CONTROLS); 299 ctrl_exi = vmcs_read(EXI_CONTROLS); 300 ctrl_ent |= ctrl_enter_rev.clr & ENT_LOAD_PAT; 301 ctrl_exi |= ctrl_exit_rev.clr & (EXI_SAVE_PAT | EXI_LOAD_PAT); 302 vmcs_write(ENT_CONTROLS, ctrl_ent); 303 vmcs_write(EXI_CONTROLS, ctrl_exi); 304 ia32_pat = rdmsr(MSR_IA32_CR_PAT); 305 vmcs_write(GUEST_PAT, 0x0); 306 vmcs_write(HOST_PAT, ia32_pat); 307 return VMX_TEST_START; 308 } 309 310 static void test_ctrl_pat_main(void) 311 { 312 u64 guest_ia32_pat; 313 314 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 315 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) 316 printf("\tENT_LOAD_PAT is not supported.\n"); 317 else { 318 if (guest_ia32_pat != 0) { 319 report_fail("Entry load PAT"); 320 return; 321 } 322 } 323 wrmsr(MSR_IA32_CR_PAT, 0x6); 324 vmcall(); 325 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 326 if (ctrl_enter_rev.clr & ENT_LOAD_PAT) 327 report(guest_ia32_pat == ia32_pat, "Entry load PAT"); 328 } 329 330 static int test_ctrl_pat_exit_handler(union exit_reason exit_reason) 331 { 332 u64 guest_rip; 333 u64 guest_pat; 334 335 guest_rip = vmcs_read(GUEST_RIP); 336 switch (exit_reason.basic) { 337 case VMX_VMCALL: 338 guest_pat = vmcs_read(GUEST_PAT); 339 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT)) { 340 printf("\tEXI_SAVE_PAT is not supported\n"); 341 vmcs_write(GUEST_PAT, 0x6); 342 } else { 343 report(guest_pat == 0x6, "Exit save PAT"); 344 } 345 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) 346 printf("\tEXI_LOAD_PAT is not supported\n"); 347 else 348 report(rdmsr(MSR_IA32_CR_PAT) == ia32_pat, 349 "Exit load PAT"); 350 vmcs_write(GUEST_PAT, ia32_pat); 351 vmcs_write(GUEST_RIP, guest_rip + 3); 352 return VMX_TEST_RESUME; 353 default: 354 printf("ERROR : Unknown exit reason, 0x%x.\n", exit_reason.full); 355 break; 356 } 357 return VMX_TEST_VMEXIT; 358 } 359 360 static int test_ctrl_efer_init(struct vmcs *vmcs) 361 { 362 u64 ctrl_ent; 363 u64 ctrl_exi; 364 365 msr_bmp_init(); 366 ctrl_ent = vmcs_read(ENT_CONTROLS) | ENT_LOAD_EFER; 367 ctrl_exi = vmcs_read(EXI_CONTROLS) | EXI_SAVE_EFER | EXI_LOAD_EFER; 368 vmcs_write(ENT_CONTROLS, ctrl_ent & ctrl_enter_rev.clr); 369 vmcs_write(EXI_CONTROLS, ctrl_exi & ctrl_exit_rev.clr); 370 ia32_efer = rdmsr(MSR_EFER); 371 vmcs_write(GUEST_EFER, ia32_efer ^ EFER_NX); 372 vmcs_write(HOST_EFER, ia32_efer ^ EFER_NX); 373 return VMX_TEST_START; 374 } 375 376 static void test_ctrl_efer_main(void) 377 { 378 u64 guest_ia32_efer; 379 380 guest_ia32_efer = rdmsr(MSR_EFER); 381 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) 382 printf("\tENT_LOAD_EFER is not supported.\n"); 383 else { 384 if (guest_ia32_efer != (ia32_efer ^ EFER_NX)) { 385 report_fail("Entry load EFER"); 386 return; 387 } 388 } 389 wrmsr(MSR_EFER, ia32_efer); 390 vmcall(); 391 guest_ia32_efer = rdmsr(MSR_EFER); 392 if (ctrl_enter_rev.clr & ENT_LOAD_EFER) 393 report(guest_ia32_efer == ia32_efer, "Entry load EFER"); 394 } 395 396 static int test_ctrl_efer_exit_handler(union exit_reason exit_reason) 397 { 398 u64 guest_rip; 399 u64 guest_efer; 400 401 guest_rip = vmcs_read(GUEST_RIP); 402 switch (exit_reason.basic) { 403 case VMX_VMCALL: 404 guest_efer = vmcs_read(GUEST_EFER); 405 if (!(ctrl_exit_rev.clr & EXI_SAVE_EFER)) { 406 printf("\tEXI_SAVE_EFER is not supported\n"); 407 vmcs_write(GUEST_EFER, ia32_efer); 408 } else { 409 report(guest_efer == ia32_efer, "Exit save EFER"); 410 } 411 if (!(ctrl_exit_rev.clr & EXI_LOAD_EFER)) { 412 printf("\tEXI_LOAD_EFER is not supported\n"); 413 wrmsr(MSR_EFER, ia32_efer ^ EFER_NX); 414 } else { 415 report(rdmsr(MSR_EFER) == (ia32_efer ^ EFER_NX), 416 "Exit load EFER"); 417 } 418 vmcs_write(GUEST_PAT, ia32_efer); 419 vmcs_write(GUEST_RIP, guest_rip + 3); 420 return VMX_TEST_RESUME; 421 default: 422 printf("ERROR : Unknown exit reason, 0x%x.\n", exit_reason.full); 423 break; 424 } 425 return VMX_TEST_VMEXIT; 426 } 427 428 u32 guest_cr0, guest_cr4; 429 430 static void cr_shadowing_main(void) 431 { 432 u32 cr0, cr4, tmp; 433 434 // Test read through 435 vmx_set_test_stage(0); 436 guest_cr0 = read_cr0(); 437 if (vmx_get_test_stage() == 1) 438 report_fail("Read through CR0"); 439 else 440 vmcall(); 441 vmx_set_test_stage(1); 442 guest_cr4 = read_cr4(); 443 if (vmx_get_test_stage() == 2) 444 report_fail("Read through CR4"); 445 else 446 vmcall(); 447 // Test write through 448 guest_cr0 = guest_cr0 ^ (X86_CR0_TS | X86_CR0_MP); 449 guest_cr4 = guest_cr4 ^ (X86_CR4_TSD | X86_CR4_DE); 450 vmx_set_test_stage(2); 451 write_cr0(guest_cr0); 452 if (vmx_get_test_stage() == 3) 453 report_fail("Write throuth CR0"); 454 else 455 vmcall(); 456 vmx_set_test_stage(3); 457 write_cr4(guest_cr4); 458 if (vmx_get_test_stage() == 4) 459 report_fail("Write through CR4"); 460 else 461 vmcall(); 462 // Test read shadow 463 vmx_set_test_stage(4); 464 vmcall(); 465 cr0 = read_cr0(); 466 if (vmx_get_test_stage() != 5) 467 report(cr0 == guest_cr0, "Read shadowing CR0"); 468 vmx_set_test_stage(5); 469 cr4 = read_cr4(); 470 if (vmx_get_test_stage() != 6) 471 report(cr4 == guest_cr4, "Read shadowing CR4"); 472 // Test write shadow (same value with shadow) 473 vmx_set_test_stage(6); 474 write_cr0(guest_cr0); 475 if (vmx_get_test_stage() == 7) 476 report_fail("Write shadowing CR0 (same value with shadow)"); 477 else 478 vmcall(); 479 vmx_set_test_stage(7); 480 write_cr4(guest_cr4); 481 if (vmx_get_test_stage() == 8) 482 report_fail("Write shadowing CR4 (same value with shadow)"); 483 else 484 vmcall(); 485 // Test write shadow (different value) 486 vmx_set_test_stage(8); 487 tmp = guest_cr0 ^ X86_CR0_TS; 488 asm volatile("mov %0, %%rsi\n\t" 489 "mov %%rsi, %%cr0\n\t" 490 ::"m"(tmp) 491 :"rsi", "memory", "cc"); 492 report(vmx_get_test_stage() == 9, 493 "Write shadowing different X86_CR0_TS"); 494 vmx_set_test_stage(9); 495 tmp = guest_cr0 ^ X86_CR0_MP; 496 asm volatile("mov %0, %%rsi\n\t" 497 "mov %%rsi, %%cr0\n\t" 498 ::"m"(tmp) 499 :"rsi", "memory", "cc"); 500 report(vmx_get_test_stage() == 10, 501 "Write shadowing different X86_CR0_MP"); 502 vmx_set_test_stage(10); 503 tmp = guest_cr4 ^ X86_CR4_TSD; 504 asm volatile("mov %0, %%rsi\n\t" 505 "mov %%rsi, %%cr4\n\t" 506 ::"m"(tmp) 507 :"rsi", "memory", "cc"); 508 report(vmx_get_test_stage() == 11, 509 "Write shadowing different X86_CR4_TSD"); 510 vmx_set_test_stage(11); 511 tmp = guest_cr4 ^ X86_CR4_DE; 512 asm volatile("mov %0, %%rsi\n\t" 513 "mov %%rsi, %%cr4\n\t" 514 ::"m"(tmp) 515 :"rsi", "memory", "cc"); 516 report(vmx_get_test_stage() == 12, 517 "Write shadowing different X86_CR4_DE"); 518 } 519 520 static int cr_shadowing_exit_handler(union exit_reason exit_reason) 521 { 522 u64 guest_rip; 523 u32 insn_len; 524 u32 exit_qual; 525 526 guest_rip = vmcs_read(GUEST_RIP); 527 insn_len = vmcs_read(EXI_INST_LEN); 528 exit_qual = vmcs_read(EXI_QUALIFICATION); 529 switch (exit_reason.basic) { 530 case VMX_VMCALL: 531 switch (vmx_get_test_stage()) { 532 case 0: 533 report(guest_cr0 == vmcs_read(GUEST_CR0), 534 "Read through CR0"); 535 break; 536 case 1: 537 report(guest_cr4 == vmcs_read(GUEST_CR4), 538 "Read through CR4"); 539 break; 540 case 2: 541 report(guest_cr0 == vmcs_read(GUEST_CR0), 542 "Write through CR0"); 543 break; 544 case 3: 545 report(guest_cr4 == vmcs_read(GUEST_CR4), 546 "Write through CR4"); 547 break; 548 case 4: 549 guest_cr0 = vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP); 550 guest_cr4 = vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE); 551 vmcs_write(CR0_MASK, X86_CR0_TS | X86_CR0_MP); 552 vmcs_write(CR0_READ_SHADOW, guest_cr0 & (X86_CR0_TS | X86_CR0_MP)); 553 vmcs_write(CR4_MASK, X86_CR4_TSD | X86_CR4_DE); 554 vmcs_write(CR4_READ_SHADOW, guest_cr4 & (X86_CR4_TSD | X86_CR4_DE)); 555 break; 556 case 6: 557 report(guest_cr0 == (vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP)), 558 "Write shadowing CR0 (same value)"); 559 break; 560 case 7: 561 report(guest_cr4 == (vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE)), 562 "Write shadowing CR4 (same value)"); 563 break; 564 default: 565 // Should not reach here 566 report_fail("unexpected stage, %d", 567 vmx_get_test_stage()); 568 print_vmexit_info(exit_reason); 569 return VMX_TEST_VMEXIT; 570 } 571 vmcs_write(GUEST_RIP, guest_rip + insn_len); 572 return VMX_TEST_RESUME; 573 case VMX_CR: 574 switch (vmx_get_test_stage()) { 575 case 4: 576 report_fail("Read shadowing CR0"); 577 vmx_inc_test_stage(); 578 break; 579 case 5: 580 report_fail("Read shadowing CR4"); 581 vmx_inc_test_stage(); 582 break; 583 case 6: 584 report_fail("Write shadowing CR0 (same value)"); 585 vmx_inc_test_stage(); 586 break; 587 case 7: 588 report_fail("Write shadowing CR4 (same value)"); 589 vmx_inc_test_stage(); 590 break; 591 case 8: 592 case 9: 593 // 0x600 encodes "mov %esi, %cr0" 594 if (exit_qual == 0x600) 595 vmx_inc_test_stage(); 596 break; 597 case 10: 598 case 11: 599 // 0x604 encodes "mov %esi, %cr4" 600 if (exit_qual == 0x604) 601 vmx_inc_test_stage(); 602 break; 603 default: 604 // Should not reach here 605 report_fail("unexpected stage, %d", 606 vmx_get_test_stage()); 607 print_vmexit_info(exit_reason); 608 return VMX_TEST_VMEXIT; 609 } 610 vmcs_write(GUEST_RIP, guest_rip + insn_len); 611 return VMX_TEST_RESUME; 612 default: 613 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 614 print_vmexit_info(exit_reason); 615 } 616 return VMX_TEST_VMEXIT; 617 } 618 619 static int iobmp_init(struct vmcs *vmcs) 620 { 621 u32 ctrl_cpu0; 622 623 io_bitmap_a = alloc_page(); 624 io_bitmap_b = alloc_page(); 625 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 626 ctrl_cpu0 |= CPU_IO_BITMAP; 627 ctrl_cpu0 &= (~CPU_IO); 628 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 629 vmcs_write(IO_BITMAP_A, (u64)io_bitmap_a); 630 vmcs_write(IO_BITMAP_B, (u64)io_bitmap_b); 631 return VMX_TEST_START; 632 } 633 634 static void iobmp_main(void) 635 { 636 // stage 0, test IO pass 637 vmx_set_test_stage(0); 638 inb(0x5000); 639 outb(0x0, 0x5000); 640 report(vmx_get_test_stage() == 0, "I/O bitmap - I/O pass"); 641 // test IO width, in/out 642 ((u8 *)io_bitmap_a)[0] = 0xFF; 643 vmx_set_test_stage(2); 644 inb(0x0); 645 report(vmx_get_test_stage() == 3, "I/O bitmap - trap in"); 646 vmx_set_test_stage(3); 647 outw(0x0, 0x0); 648 report(vmx_get_test_stage() == 4, "I/O bitmap - trap out"); 649 vmx_set_test_stage(4); 650 inl(0x0); 651 report(vmx_get_test_stage() == 5, "I/O bitmap - I/O width, long"); 652 // test low/high IO port 653 vmx_set_test_stage(5); 654 ((u8 *)io_bitmap_a)[0x5000 / 8] = (1 << (0x5000 % 8)); 655 inb(0x5000); 656 report(vmx_get_test_stage() == 6, "I/O bitmap - I/O port, low part"); 657 vmx_set_test_stage(6); 658 ((u8 *)io_bitmap_b)[0x1000 / 8] = (1 << (0x1000 % 8)); 659 inb(0x9000); 660 report(vmx_get_test_stage() == 7, "I/O bitmap - I/O port, high part"); 661 // test partial pass 662 vmx_set_test_stage(7); 663 inl(0x4FFF); 664 report(vmx_get_test_stage() == 8, "I/O bitmap - partial pass"); 665 // test overrun 666 vmx_set_test_stage(8); 667 memset(io_bitmap_a, 0x0, PAGE_SIZE); 668 memset(io_bitmap_b, 0x0, PAGE_SIZE); 669 inl(0xFFFF); 670 report(vmx_get_test_stage() == 9, "I/O bitmap - overrun"); 671 vmx_set_test_stage(9); 672 vmcall(); 673 outb(0x0, 0x0); 674 report(vmx_get_test_stage() == 9, 675 "I/O bitmap - ignore unconditional exiting"); 676 vmx_set_test_stage(10); 677 vmcall(); 678 outb(0x0, 0x0); 679 report(vmx_get_test_stage() == 11, 680 "I/O bitmap - unconditional exiting"); 681 } 682 683 static int iobmp_exit_handler(union exit_reason exit_reason) 684 { 685 u64 guest_rip; 686 ulong exit_qual; 687 u32 insn_len, ctrl_cpu0; 688 689 guest_rip = vmcs_read(GUEST_RIP); 690 exit_qual = vmcs_read(EXI_QUALIFICATION); 691 insn_len = vmcs_read(EXI_INST_LEN); 692 switch (exit_reason.basic) { 693 case VMX_IO: 694 switch (vmx_get_test_stage()) { 695 case 0: 696 case 1: 697 vmx_inc_test_stage(); 698 break; 699 case 2: 700 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_BYTE, 701 "I/O bitmap - I/O width, byte"); 702 report(exit_qual & VMX_IO_IN, 703 "I/O bitmap - I/O direction, in"); 704 vmx_inc_test_stage(); 705 break; 706 case 3: 707 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_WORD, 708 "I/O bitmap - I/O width, word"); 709 report(!(exit_qual & VMX_IO_IN), 710 "I/O bitmap - I/O direction, out"); 711 vmx_inc_test_stage(); 712 break; 713 case 4: 714 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_LONG, 715 "I/O bitmap - I/O width, long"); 716 vmx_inc_test_stage(); 717 break; 718 case 5: 719 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x5000) 720 vmx_inc_test_stage(); 721 break; 722 case 6: 723 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x9000) 724 vmx_inc_test_stage(); 725 break; 726 case 7: 727 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x4FFF) 728 vmx_inc_test_stage(); 729 break; 730 case 8: 731 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0xFFFF) 732 vmx_inc_test_stage(); 733 break; 734 case 9: 735 case 10: 736 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 737 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0 & ~CPU_IO); 738 vmx_inc_test_stage(); 739 break; 740 default: 741 // Should not reach here 742 report_fail("unexpected stage, %d", 743 vmx_get_test_stage()); 744 print_vmexit_info(exit_reason); 745 return VMX_TEST_VMEXIT; 746 } 747 vmcs_write(GUEST_RIP, guest_rip + insn_len); 748 return VMX_TEST_RESUME; 749 case VMX_VMCALL: 750 switch (vmx_get_test_stage()) { 751 case 9: 752 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 753 ctrl_cpu0 |= CPU_IO | CPU_IO_BITMAP; 754 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 755 break; 756 case 10: 757 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 758 ctrl_cpu0 = (ctrl_cpu0 & ~CPU_IO_BITMAP) | CPU_IO; 759 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 760 break; 761 default: 762 // Should not reach here 763 report_fail("unexpected stage, %d", 764 vmx_get_test_stage()); 765 print_vmexit_info(exit_reason); 766 return VMX_TEST_VMEXIT; 767 } 768 vmcs_write(GUEST_RIP, guest_rip + insn_len); 769 return VMX_TEST_RESUME; 770 default: 771 printf("guest_rip = %#lx\n", guest_rip); 772 printf("\tERROR : Unknown exit reason, 0x%x\n", exit_reason.full); 773 break; 774 } 775 return VMX_TEST_VMEXIT; 776 } 777 778 #define INSN_CPU0 0 779 #define INSN_CPU1 1 780 #define INSN_ALWAYS_TRAP 2 781 782 #define FIELD_EXIT_QUAL (1 << 0) 783 #define FIELD_INSN_INFO (1 << 1) 784 785 asm( 786 "insn_hlt: hlt;ret\n\t" 787 "insn_invlpg: invlpg 0x12345678;ret\n\t" 788 "insn_mwait: xor %eax, %eax; xor %ecx, %ecx; mwait;ret\n\t" 789 "insn_rdpmc: xor %ecx, %ecx; rdpmc;ret\n\t" 790 "insn_rdtsc: rdtsc;ret\n\t" 791 "insn_cr3_load: mov cr3,%rax; mov %rax,%cr3;ret\n\t" 792 "insn_cr3_store: mov %cr3,%rax;ret\n\t" 793 "insn_cr8_load: xor %eax, %eax; mov %rax,%cr8;ret\n\t" 794 "insn_cr8_store: mov %cr8,%rax;ret\n\t" 795 "insn_monitor: xor %eax, %eax; xor %ecx, %ecx; xor %edx, %edx; monitor;ret\n\t" 796 "insn_pause: pause;ret\n\t" 797 "insn_wbinvd: wbinvd;ret\n\t" 798 "insn_cpuid: mov $10, %eax; cpuid;ret\n\t" 799 "insn_invd: invd;ret\n\t" 800 "insn_sgdt: sgdt gdt64_desc;ret\n\t" 801 "insn_lgdt: lgdt gdt64_desc;ret\n\t" 802 "insn_sidt: sidt idt_descr;ret\n\t" 803 "insn_lidt: lidt idt_descr;ret\n\t" 804 "insn_sldt: sldt %ax;ret\n\t" 805 "insn_lldt: xor %eax, %eax; lldt %ax;ret\n\t" 806 "insn_str: str %ax;ret\n\t" 807 "insn_rdrand: rdrand %rax;ret\n\t" 808 "insn_rdseed: rdseed %rax;ret\n\t" 809 ); 810 extern void insn_hlt(void); 811 extern void insn_invlpg(void); 812 extern void insn_mwait(void); 813 extern void insn_rdpmc(void); 814 extern void insn_rdtsc(void); 815 extern void insn_cr3_load(void); 816 extern void insn_cr3_store(void); 817 extern void insn_cr8_load(void); 818 extern void insn_cr8_store(void); 819 extern void insn_monitor(void); 820 extern void insn_pause(void); 821 extern void insn_wbinvd(void); 822 extern void insn_sgdt(void); 823 extern void insn_lgdt(void); 824 extern void insn_sidt(void); 825 extern void insn_lidt(void); 826 extern void insn_sldt(void); 827 extern void insn_lldt(void); 828 extern void insn_str(void); 829 extern void insn_cpuid(void); 830 extern void insn_invd(void); 831 extern void insn_rdrand(void); 832 extern void insn_rdseed(void); 833 834 u32 cur_insn; 835 u64 cr3; 836 837 #define X86_FEATURE_MONITOR (1 << 3) 838 839 typedef bool (*supported_fn)(void); 840 841 static bool monitor_supported(void) 842 { 843 return this_cpu_has(X86_FEATURE_MWAIT); 844 } 845 846 struct insn_table { 847 const char *name; 848 u32 flag; 849 void (*insn_func)(void); 850 u32 type; 851 u32 reason; 852 ulong exit_qual; 853 u32 insn_info; 854 // Use FIELD_EXIT_QUAL and FIELD_INSN_INFO to define 855 // which field need to be tested, reason is always tested 856 u32 test_field; 857 const supported_fn supported_fn; 858 u8 disabled; 859 }; 860 861 /* 862 * Add more test cases of instruction intercept here. Elements in this 863 * table is: 864 * name/control flag/insn function/type/exit reason/exit qulification/ 865 * instruction info/field to test 866 * The last field defines which fields (exit_qual and insn_info) need to be 867 * tested in exit handler. If set to 0, only "reason" is checked. 868 */ 869 static struct insn_table insn_table[] = { 870 // Flags for Primary Processor-Based VM-Execution Controls 871 {"HLT", CPU_HLT, insn_hlt, INSN_CPU0, 12, 0, 0, 0}, 872 {"INVLPG", CPU_INVLPG, insn_invlpg, INSN_CPU0, 14, 873 0x12345678, 0, FIELD_EXIT_QUAL}, 874 {"MWAIT", CPU_MWAIT, insn_mwait, INSN_CPU0, 36, 0, 0, 0, &monitor_supported}, 875 {"RDPMC", CPU_RDPMC, insn_rdpmc, INSN_CPU0, 15, 0, 0, 0}, 876 {"RDTSC", CPU_RDTSC, insn_rdtsc, INSN_CPU0, 16, 0, 0, 0}, 877 {"CR3 load", CPU_CR3_LOAD, insn_cr3_load, INSN_CPU0, 28, 0x3, 0, 878 FIELD_EXIT_QUAL}, 879 {"CR3 store", CPU_CR3_STORE, insn_cr3_store, INSN_CPU0, 28, 0x13, 0, 880 FIELD_EXIT_QUAL}, 881 {"CR8 load", CPU_CR8_LOAD, insn_cr8_load, INSN_CPU0, 28, 0x8, 0, 882 FIELD_EXIT_QUAL}, 883 {"CR8 store", CPU_CR8_STORE, insn_cr8_store, INSN_CPU0, 28, 0x18, 0, 884 FIELD_EXIT_QUAL}, 885 {"MONITOR", CPU_MONITOR, insn_monitor, INSN_CPU0, 39, 0, 0, 0, &monitor_supported}, 886 {"PAUSE", CPU_PAUSE, insn_pause, INSN_CPU0, 40, 0, 0, 0}, 887 // Flags for Secondary Processor-Based VM-Execution Controls 888 {"WBINVD", CPU_WBINVD, insn_wbinvd, INSN_CPU1, 54, 0, 0, 0}, 889 {"DESC_TABLE (SGDT)", CPU_DESC_TABLE, insn_sgdt, INSN_CPU1, 46, 0, 0, 0}, 890 {"DESC_TABLE (LGDT)", CPU_DESC_TABLE, insn_lgdt, INSN_CPU1, 46, 0, 0, 0}, 891 {"DESC_TABLE (SIDT)", CPU_DESC_TABLE, insn_sidt, INSN_CPU1, 46, 0, 0, 0}, 892 {"DESC_TABLE (LIDT)", CPU_DESC_TABLE, insn_lidt, INSN_CPU1, 46, 0, 0, 0}, 893 {"DESC_TABLE (SLDT)", CPU_DESC_TABLE, insn_sldt, INSN_CPU1, 47, 0, 0, 0}, 894 {"DESC_TABLE (LLDT)", CPU_DESC_TABLE, insn_lldt, INSN_CPU1, 47, 0, 0, 0}, 895 {"DESC_TABLE (STR)", CPU_DESC_TABLE, insn_str, INSN_CPU1, 47, 0, 0, 0}, 896 /* LTR causes a #GP if done with a busy selector, so it is not tested. */ 897 {"RDRAND", CPU_RDRAND, insn_rdrand, INSN_CPU1, VMX_RDRAND, 0, 0, 0}, 898 {"RDSEED", CPU_RDSEED, insn_rdseed, INSN_CPU1, VMX_RDSEED, 0, 0, 0}, 899 // Instructions always trap 900 {"CPUID", 0, insn_cpuid, INSN_ALWAYS_TRAP, 10, 0, 0, 0}, 901 {"INVD", 0, insn_invd, INSN_ALWAYS_TRAP, 13, 0, 0, 0}, 902 // Instructions never trap 903 {NULL}, 904 }; 905 906 static int insn_intercept_init(struct vmcs *vmcs) 907 { 908 u32 ctrl_cpu, cur_insn; 909 910 ctrl_cpu = ctrl_cpu_rev[0].set | CPU_SECONDARY; 911 ctrl_cpu &= ctrl_cpu_rev[0].clr; 912 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu); 913 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu_rev[1].set); 914 cr3 = read_cr3(); 915 916 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 917 if (insn_table[cur_insn].supported_fn == NULL) 918 continue; 919 insn_table[cur_insn].disabled = !insn_table[cur_insn].supported_fn(); 920 } 921 return VMX_TEST_START; 922 } 923 924 static void insn_intercept_main(void) 925 { 926 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 927 vmx_set_test_stage(cur_insn * 2); 928 if ((insn_table[cur_insn].type == INSN_CPU0 && 929 !(ctrl_cpu_rev[0].clr & insn_table[cur_insn].flag)) || 930 (insn_table[cur_insn].type == INSN_CPU1 && 931 !(ctrl_cpu_rev[1].clr & insn_table[cur_insn].flag))) { 932 printf("\tCPU_CTRL%d.CPU_%s is not supported.\n", 933 insn_table[cur_insn].type - INSN_CPU0, 934 insn_table[cur_insn].name); 935 continue; 936 } 937 938 if (insn_table[cur_insn].disabled) { 939 printf("\tFeature required for %s is not supported.\n", 940 insn_table[cur_insn].name); 941 continue; 942 } 943 944 if ((insn_table[cur_insn].type == INSN_CPU0 && 945 !(ctrl_cpu_rev[0].set & insn_table[cur_insn].flag)) || 946 (insn_table[cur_insn].type == INSN_CPU1 && 947 !(ctrl_cpu_rev[1].set & insn_table[cur_insn].flag))) { 948 /* skip hlt, it stalls the guest and is tested below */ 949 if (insn_table[cur_insn].insn_func != insn_hlt) 950 insn_table[cur_insn].insn_func(); 951 report(vmx_get_test_stage() == cur_insn * 2, 952 "execute %s", 953 insn_table[cur_insn].name); 954 } else if (insn_table[cur_insn].type != INSN_ALWAYS_TRAP) 955 printf("\tCPU_CTRL%d.CPU_%s always traps.\n", 956 insn_table[cur_insn].type - INSN_CPU0, 957 insn_table[cur_insn].name); 958 959 vmcall(); 960 961 insn_table[cur_insn].insn_func(); 962 report(vmx_get_test_stage() == cur_insn * 2 + 1, 963 "intercept %s", 964 insn_table[cur_insn].name); 965 966 vmx_set_test_stage(cur_insn * 2 + 1); 967 vmcall(); 968 } 969 } 970 971 static int insn_intercept_exit_handler(union exit_reason exit_reason) 972 { 973 u64 guest_rip; 974 ulong exit_qual; 975 u32 insn_len; 976 u32 insn_info; 977 bool pass; 978 979 guest_rip = vmcs_read(GUEST_RIP); 980 exit_qual = vmcs_read(EXI_QUALIFICATION); 981 insn_len = vmcs_read(EXI_INST_LEN); 982 insn_info = vmcs_read(EXI_INST_INFO); 983 984 if (exit_reason.basic == VMX_VMCALL) { 985 u32 val = 0; 986 987 if (insn_table[cur_insn].type == INSN_CPU0) 988 val = vmcs_read(CPU_EXEC_CTRL0); 989 else if (insn_table[cur_insn].type == INSN_CPU1) 990 val = vmcs_read(CPU_EXEC_CTRL1); 991 992 if (vmx_get_test_stage() & 1) 993 val &= ~insn_table[cur_insn].flag; 994 else 995 val |= insn_table[cur_insn].flag; 996 997 if (insn_table[cur_insn].type == INSN_CPU0) 998 vmcs_write(CPU_EXEC_CTRL0, val | ctrl_cpu_rev[0].set); 999 else if (insn_table[cur_insn].type == INSN_CPU1) 1000 vmcs_write(CPU_EXEC_CTRL1, val | ctrl_cpu_rev[1].set); 1001 } else { 1002 pass = (cur_insn * 2 == vmx_get_test_stage()) && 1003 insn_table[cur_insn].reason == exit_reason.full; 1004 if (insn_table[cur_insn].test_field & FIELD_EXIT_QUAL && 1005 insn_table[cur_insn].exit_qual != exit_qual) 1006 pass = false; 1007 if (insn_table[cur_insn].test_field & FIELD_INSN_INFO && 1008 insn_table[cur_insn].insn_info != insn_info) 1009 pass = false; 1010 if (pass) 1011 vmx_inc_test_stage(); 1012 } 1013 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1014 return VMX_TEST_RESUME; 1015 } 1016 1017 /** 1018 * __setup_ept - Setup the VMCS fields to enable Extended Page Tables (EPT) 1019 * @hpa: Host physical address of the top-level, a.k.a. root, EPT table 1020 * @enable_ad: Whether or not to enable Access/Dirty bits for EPT entries 1021 * 1022 * Returns 0 on success, 1 on failure. 1023 * 1024 * Note that @hpa doesn't need to point at actual memory if VM-Launch is 1025 * expected to fail, e.g. setup_dummy_ept() arbitrarily passes '0' to satisfy 1026 * the various EPTP consistency checks, but doesn't ensure backing for HPA '0'. 1027 */ 1028 static int __setup_ept(u64 hpa, bool enable_ad) 1029 { 1030 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1031 !(ctrl_cpu_rev[1].clr & CPU_EPT)) { 1032 printf("\tEPT is not supported\n"); 1033 return 1; 1034 } 1035 if (!(ept_vpid.val & EPT_CAP_WB)) { 1036 printf("\tWB memtype for EPT walks not supported\n"); 1037 return 1; 1038 } 1039 if (!(ept_vpid.val & EPT_CAP_PWL4)) { 1040 printf("\tPWL4 is not supported\n"); 1041 return 1; 1042 } 1043 1044 eptp = EPT_MEM_TYPE_WB; 1045 eptp |= (3 << EPTP_PG_WALK_LEN_SHIFT); 1046 eptp |= hpa; 1047 if (enable_ad) 1048 eptp |= EPTP_AD_FLAG; 1049 1050 vmcs_write(EPTP, eptp); 1051 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0)| CPU_SECONDARY); 1052 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1)| CPU_EPT); 1053 1054 return 0; 1055 } 1056 1057 /** 1058 * setup_ept - Enable Extended Page Tables (EPT) and setup an identity map 1059 * @enable_ad: Whether or not to enable Access/Dirty bits for EPT entries 1060 * 1061 * Returns 0 on success, 1 on failure. 1062 * 1063 * This is the "real" function for setting up EPT tables, i.e. use this for 1064 * tests that need to run code in the guest with EPT enabled. 1065 */ 1066 static int setup_ept(bool enable_ad) 1067 { 1068 unsigned long end_of_memory; 1069 1070 pml4 = alloc_page(); 1071 1072 if (__setup_ept(virt_to_phys(pml4), enable_ad)) 1073 return 1; 1074 1075 end_of_memory = fwcfg_get_u64(FW_CFG_RAM_SIZE); 1076 if (end_of_memory < (1ul << 32)) 1077 end_of_memory = (1ul << 32); 1078 /* Cannot use large EPT pages if we need to track EPT 1079 * accessed/dirty bits at 4K granularity. 1080 */ 1081 setup_ept_range(pml4, 0, end_of_memory, 0, 1082 !enable_ad && ept_2m_supported(), 1083 EPT_WA | EPT_RA | EPT_EA); 1084 return 0; 1085 } 1086 1087 /** 1088 * setup_dummy_ept - Enable Extended Page Tables (EPT) with a dummy root HPA 1089 * 1090 * Setup EPT using a semi-arbitrary dummy root HPA. This function is intended 1091 * for use by tests that need EPT enabled to verify dependent VMCS controls 1092 * but never expect to fully enter the guest, i.e. don't need setup the actual 1093 * EPT tables. 1094 */ 1095 static void setup_dummy_ept(void) 1096 { 1097 if (__setup_ept(0, false)) 1098 report_abort("EPT setup unexpectedly failed"); 1099 } 1100 1101 static int enable_unrestricted_guest(bool need_valid_ept) 1102 { 1103 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1104 !(ctrl_cpu_rev[1].clr & CPU_URG) || 1105 !(ctrl_cpu_rev[1].clr & CPU_EPT)) 1106 return 1; 1107 1108 if (need_valid_ept) 1109 setup_ept(false); 1110 else 1111 setup_dummy_ept(); 1112 1113 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 1114 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | CPU_URG); 1115 1116 return 0; 1117 } 1118 1119 static void ept_enable_ad_bits(void) 1120 { 1121 eptp |= EPTP_AD_FLAG; 1122 vmcs_write(EPTP, eptp); 1123 } 1124 1125 static void ept_disable_ad_bits(void) 1126 { 1127 eptp &= ~EPTP_AD_FLAG; 1128 vmcs_write(EPTP, eptp); 1129 } 1130 1131 static int ept_ad_enabled(void) 1132 { 1133 return eptp & EPTP_AD_FLAG; 1134 } 1135 1136 static void ept_enable_ad_bits_or_skip_test(void) 1137 { 1138 if (!ept_ad_bits_supported()) 1139 test_skip("EPT AD bits not supported."); 1140 ept_enable_ad_bits(); 1141 } 1142 1143 static int apic_version; 1144 1145 static int ept_init_common(bool have_ad) 1146 { 1147 int ret; 1148 struct pci_dev pcidev; 1149 1150 if (setup_ept(have_ad)) 1151 return VMX_TEST_EXIT; 1152 data_page1 = alloc_page(); 1153 data_page2 = alloc_page(); 1154 *((u32 *)data_page1) = MAGIC_VAL_1; 1155 *((u32 *)data_page2) = MAGIC_VAL_2; 1156 install_ept(pml4, (unsigned long)data_page1, (unsigned long)data_page2, 1157 EPT_RA | EPT_WA | EPT_EA); 1158 1159 apic_version = apic_read(APIC_LVR); 1160 1161 ret = pci_find_dev(PCI_VENDOR_ID_REDHAT, PCI_DEVICE_ID_REDHAT_TEST); 1162 if (ret != PCIDEVADDR_INVALID) { 1163 pci_dev_init(&pcidev, ret); 1164 pci_physaddr = pcidev.resource[PCI_TESTDEV_BAR_MEM]; 1165 } 1166 1167 return VMX_TEST_START; 1168 } 1169 1170 static int ept_init(struct vmcs *vmcs) 1171 { 1172 return ept_init_common(false); 1173 } 1174 1175 static void ept_common(void) 1176 { 1177 vmx_set_test_stage(0); 1178 if (*((u32 *)data_page2) != MAGIC_VAL_1 || 1179 *((u32 *)data_page1) != MAGIC_VAL_1) 1180 report_fail("EPT basic framework - read"); 1181 else { 1182 *((u32 *)data_page2) = MAGIC_VAL_3; 1183 vmcall(); 1184 if (vmx_get_test_stage() == 1) { 1185 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1186 *((u32 *)data_page2) == MAGIC_VAL_2) 1187 report(1, "EPT basic framework"); 1188 else 1189 report(1, "EPT basic framework - remap"); 1190 } 1191 } 1192 // Test EPT Misconfigurations 1193 vmx_set_test_stage(1); 1194 vmcall(); 1195 *((u32 *)data_page1) = MAGIC_VAL_1; 1196 if (vmx_get_test_stage() != 2) { 1197 report_fail("EPT misconfigurations"); 1198 goto t1; 1199 } 1200 vmx_set_test_stage(2); 1201 vmcall(); 1202 *((u32 *)data_page1) = MAGIC_VAL_1; 1203 report(vmx_get_test_stage() == 3, "EPT misconfigurations"); 1204 t1: 1205 // Test EPT violation 1206 vmx_set_test_stage(3); 1207 vmcall(); 1208 *((u32 *)data_page1) = MAGIC_VAL_1; 1209 report(vmx_get_test_stage() == 4, "EPT violation - page permission"); 1210 // Violation caused by EPT paging structure 1211 vmx_set_test_stage(4); 1212 vmcall(); 1213 *((u32 *)data_page1) = MAGIC_VAL_2; 1214 report(vmx_get_test_stage() == 5, "EPT violation - paging structure"); 1215 1216 // MMIO Read/Write 1217 vmx_set_test_stage(5); 1218 vmcall(); 1219 1220 *(u32 volatile *)pci_physaddr; 1221 report(vmx_get_test_stage() == 6, "MMIO EPT violation - read"); 1222 1223 *(u32 volatile *)pci_physaddr = MAGIC_VAL_1; 1224 report(vmx_get_test_stage() == 7, "MMIO EPT violation - write"); 1225 } 1226 1227 static void ept_main(void) 1228 { 1229 ept_common(); 1230 1231 // Test EPT access to L1 MMIO 1232 vmx_set_test_stage(7); 1233 report(*((u32 *)0xfee00030UL) == apic_version, "EPT - MMIO access"); 1234 1235 // Test invalid operand for INVEPT 1236 vmcall(); 1237 report(vmx_get_test_stage() == 8, "EPT - unsupported INVEPT"); 1238 } 1239 1240 static bool invept_test(int type, u64 eptp) 1241 { 1242 bool ret, supported; 1243 1244 supported = ept_vpid.val & (EPT_CAP_INVEPT_SINGLE >> INVEPT_SINGLE << type); 1245 ret = invept(type, eptp); 1246 1247 if (ret == !supported) 1248 return false; 1249 1250 if (!supported) 1251 printf("WARNING: unsupported invept passed!\n"); 1252 else 1253 printf("WARNING: invept failed!\n"); 1254 1255 return true; 1256 } 1257 1258 static int pml_exit_handler(union exit_reason exit_reason) 1259 { 1260 u16 index, count; 1261 u64 *pmlbuf = pml_log; 1262 u64 guest_rip = vmcs_read(GUEST_RIP);; 1263 u64 guest_cr3 = vmcs_read(GUEST_CR3); 1264 u32 insn_len = vmcs_read(EXI_INST_LEN); 1265 1266 switch (exit_reason.basic) { 1267 case VMX_VMCALL: 1268 switch (vmx_get_test_stage()) { 1269 case 0: 1270 index = vmcs_read(GUEST_PML_INDEX); 1271 for (count = index + 1; count < PML_INDEX; count++) { 1272 if (pmlbuf[count] == (u64)data_page2) { 1273 vmx_inc_test_stage(); 1274 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1275 break; 1276 } 1277 } 1278 break; 1279 case 1: 1280 index = vmcs_read(GUEST_PML_INDEX); 1281 /* Keep clearing the dirty bit till a overflow */ 1282 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1283 break; 1284 default: 1285 report_fail("unexpected stage, %d.", 1286 vmx_get_test_stage()); 1287 print_vmexit_info(exit_reason); 1288 return VMX_TEST_VMEXIT; 1289 } 1290 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1291 return VMX_TEST_RESUME; 1292 case VMX_PML_FULL: 1293 vmx_inc_test_stage(); 1294 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1295 return VMX_TEST_RESUME; 1296 default: 1297 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 1298 print_vmexit_info(exit_reason); 1299 } 1300 return VMX_TEST_VMEXIT; 1301 } 1302 1303 static int ept_exit_handler_common(union exit_reason exit_reason, bool have_ad) 1304 { 1305 u64 guest_rip; 1306 u64 guest_cr3; 1307 u32 insn_len; 1308 u32 exit_qual; 1309 static unsigned long data_page1_pte, data_page1_pte_pte, memaddr_pte, 1310 guest_pte_addr; 1311 1312 guest_rip = vmcs_read(GUEST_RIP); 1313 guest_cr3 = vmcs_read(GUEST_CR3); 1314 insn_len = vmcs_read(EXI_INST_LEN); 1315 exit_qual = vmcs_read(EXI_QUALIFICATION); 1316 pteval_t *ptep; 1317 switch (exit_reason.basic) { 1318 case VMX_VMCALL: 1319 switch (vmx_get_test_stage()) { 1320 case 0: 1321 check_ept_ad(pml4, guest_cr3, 1322 (unsigned long)data_page1, 1323 have_ad ? EPT_ACCESS_FLAG : 0, 1324 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1325 check_ept_ad(pml4, guest_cr3, 1326 (unsigned long)data_page2, 1327 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0, 1328 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1329 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1330 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1331 if (have_ad) 1332 ept_sync(INVEPT_SINGLE, eptp);; 1333 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1334 *((u32 *)data_page2) == MAGIC_VAL_2) { 1335 vmx_inc_test_stage(); 1336 install_ept(pml4, (unsigned long)data_page2, 1337 (unsigned long)data_page2, 1338 EPT_RA | EPT_WA | EPT_EA); 1339 } else 1340 report_fail("EPT basic framework - write"); 1341 break; 1342 case 1: 1343 install_ept(pml4, (unsigned long)data_page1, 1344 (unsigned long)data_page1, EPT_WA); 1345 ept_sync(INVEPT_SINGLE, eptp); 1346 break; 1347 case 2: 1348 install_ept(pml4, (unsigned long)data_page1, 1349 (unsigned long)data_page1, 1350 EPT_RA | EPT_WA | EPT_EA | 1351 (2 << EPT_MEM_TYPE_SHIFT)); 1352 ept_sync(INVEPT_SINGLE, eptp); 1353 break; 1354 case 3: 1355 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1356 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)data_page1, 1357 1, &data_page1_pte)); 1358 set_ept_pte(pml4, (unsigned long)data_page1, 1359 1, data_page1_pte & ~EPT_PRESENT); 1360 ept_sync(INVEPT_SINGLE, eptp); 1361 break; 1362 case 4: 1363 ptep = get_pte_level((pgd_t *)guest_cr3, data_page1, /*level=*/2); 1364 guest_pte_addr = virt_to_phys(ptep) & PAGE_MASK; 1365 1366 TEST_ASSERT(get_ept_pte(pml4, guest_pte_addr, 2, &data_page1_pte_pte)); 1367 set_ept_pte(pml4, guest_pte_addr, 2, 1368 data_page1_pte_pte & ~EPT_PRESENT); 1369 ept_sync(INVEPT_SINGLE, eptp); 1370 break; 1371 case 5: 1372 install_ept(pml4, (unsigned long)pci_physaddr, 1373 (unsigned long)pci_physaddr, 0); 1374 ept_sync(INVEPT_SINGLE, eptp); 1375 break; 1376 case 7: 1377 if (!invept_test(0, eptp)) 1378 vmx_inc_test_stage(); 1379 break; 1380 // Should not reach here 1381 default: 1382 report_fail("ERROR - unexpected stage, %d.", 1383 vmx_get_test_stage()); 1384 print_vmexit_info(exit_reason); 1385 return VMX_TEST_VMEXIT; 1386 } 1387 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1388 return VMX_TEST_RESUME; 1389 case VMX_EPT_MISCONFIG: 1390 switch (vmx_get_test_stage()) { 1391 case 1: 1392 case 2: 1393 vmx_inc_test_stage(); 1394 install_ept(pml4, (unsigned long)data_page1, 1395 (unsigned long)data_page1, 1396 EPT_RA | EPT_WA | EPT_EA); 1397 ept_sync(INVEPT_SINGLE, eptp); 1398 break; 1399 // Should not reach here 1400 default: 1401 report_fail("ERROR - unexpected stage, %d.", 1402 vmx_get_test_stage()); 1403 print_vmexit_info(exit_reason); 1404 return VMX_TEST_VMEXIT; 1405 } 1406 return VMX_TEST_RESUME; 1407 case VMX_EPT_VIOLATION: 1408 /* 1409 * Exit-qualifications are masked not to account for advanced 1410 * VM-exit information. Once KVM supports this feature, this 1411 * masking should be removed. 1412 */ 1413 exit_qual &= ~EPT_VLT_GUEST_MASK; 1414 1415 switch(vmx_get_test_stage()) { 1416 case 3: 1417 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1418 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1419 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1420 if (exit_qual == (EPT_VLT_WR | EPT_VLT_LADDR_VLD | 1421 EPT_VLT_PADDR)) 1422 vmx_inc_test_stage(); 1423 set_ept_pte(pml4, (unsigned long)data_page1, 1424 1, data_page1_pte | (EPT_PRESENT)); 1425 ept_sync(INVEPT_SINGLE, eptp); 1426 break; 1427 case 4: 1428 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1429 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1430 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1431 if (exit_qual == (EPT_VLT_RD | 1432 (have_ad ? EPT_VLT_WR : 0) | 1433 EPT_VLT_LADDR_VLD)) 1434 vmx_inc_test_stage(); 1435 set_ept_pte(pml4, guest_pte_addr, 2, 1436 data_page1_pte_pte | (EPT_PRESENT)); 1437 ept_sync(INVEPT_SINGLE, eptp); 1438 break; 1439 case 5: 1440 if (exit_qual & EPT_VLT_RD) 1441 vmx_inc_test_stage(); 1442 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1443 1, &memaddr_pte)); 1444 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA); 1445 ept_sync(INVEPT_SINGLE, eptp); 1446 break; 1447 case 6: 1448 if (exit_qual & EPT_VLT_WR) 1449 vmx_inc_test_stage(); 1450 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1451 1, &memaddr_pte)); 1452 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA | EPT_WA); 1453 ept_sync(INVEPT_SINGLE, eptp); 1454 break; 1455 default: 1456 // Should not reach here 1457 report_fail("ERROR : unexpected stage, %d", 1458 vmx_get_test_stage()); 1459 print_vmexit_info(exit_reason); 1460 return VMX_TEST_VMEXIT; 1461 } 1462 return VMX_TEST_RESUME; 1463 default: 1464 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 1465 print_vmexit_info(exit_reason); 1466 } 1467 return VMX_TEST_VMEXIT; 1468 } 1469 1470 static int ept_exit_handler(union exit_reason exit_reason) 1471 { 1472 return ept_exit_handler_common(exit_reason, false); 1473 } 1474 1475 static int eptad_init(struct vmcs *vmcs) 1476 { 1477 int r = ept_init_common(true); 1478 1479 if (r == VMX_TEST_EXIT) 1480 return r; 1481 1482 if ((rdmsr(MSR_IA32_VMX_EPT_VPID_CAP) & EPT_CAP_AD_FLAG) == 0) { 1483 printf("\tEPT A/D bits are not supported"); 1484 return VMX_TEST_EXIT; 1485 } 1486 1487 return r; 1488 } 1489 1490 static int pml_init(struct vmcs *vmcs) 1491 { 1492 u32 ctrl_cpu; 1493 int r = eptad_init(vmcs); 1494 1495 if (r == VMX_TEST_EXIT) 1496 return r; 1497 1498 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1499 !(ctrl_cpu_rev[1].clr & CPU_PML)) { 1500 printf("\tPML is not supported"); 1501 return VMX_TEST_EXIT; 1502 } 1503 1504 pml_log = alloc_page(); 1505 vmcs_write(PMLADDR, (u64)pml_log); 1506 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1507 1508 ctrl_cpu = vmcs_read(CPU_EXEC_CTRL1) | CPU_PML; 1509 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu); 1510 1511 return VMX_TEST_START; 1512 } 1513 1514 static void pml_main(void) 1515 { 1516 int count = 0; 1517 1518 vmx_set_test_stage(0); 1519 *((u32 *)data_page2) = 0x1; 1520 vmcall(); 1521 report(vmx_get_test_stage() == 1, "PML - Dirty GPA Logging"); 1522 1523 while (vmx_get_test_stage() == 1) { 1524 vmcall(); 1525 *((u32 *)data_page2) = 0x1; 1526 if (count++ > PML_INDEX) 1527 break; 1528 } 1529 report(vmx_get_test_stage() == 2, "PML Full Event"); 1530 } 1531 1532 static void eptad_main(void) 1533 { 1534 ept_common(); 1535 } 1536 1537 static int eptad_exit_handler(union exit_reason exit_reason) 1538 { 1539 return ept_exit_handler_common(exit_reason, true); 1540 } 1541 1542 static bool invvpid_test(int type, u16 vpid) 1543 { 1544 bool ret, supported; 1545 1546 supported = ept_vpid.val & 1547 (VPID_CAP_INVVPID_ADDR >> INVVPID_ADDR << type); 1548 ret = invvpid(type, vpid, 0); 1549 1550 if (ret == !supported) 1551 return false; 1552 1553 if (!supported) 1554 printf("WARNING: unsupported invvpid passed!\n"); 1555 else 1556 printf("WARNING: invvpid failed!\n"); 1557 1558 return true; 1559 } 1560 1561 static int vpid_init(struct vmcs *vmcs) 1562 { 1563 u32 ctrl_cpu1; 1564 1565 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1566 !(ctrl_cpu_rev[1].clr & CPU_VPID)) { 1567 printf("\tVPID is not supported"); 1568 return VMX_TEST_EXIT; 1569 } 1570 1571 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 1572 ctrl_cpu1 |= CPU_VPID; 1573 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 1574 return VMX_TEST_START; 1575 } 1576 1577 static void vpid_main(void) 1578 { 1579 vmx_set_test_stage(0); 1580 vmcall(); 1581 report(vmx_get_test_stage() == 1, "INVVPID SINGLE ADDRESS"); 1582 vmx_set_test_stage(2); 1583 vmcall(); 1584 report(vmx_get_test_stage() == 3, "INVVPID SINGLE"); 1585 vmx_set_test_stage(4); 1586 vmcall(); 1587 report(vmx_get_test_stage() == 5, "INVVPID ALL"); 1588 } 1589 1590 static int vpid_exit_handler(union exit_reason exit_reason) 1591 { 1592 u64 guest_rip; 1593 u32 insn_len; 1594 1595 guest_rip = vmcs_read(GUEST_RIP); 1596 insn_len = vmcs_read(EXI_INST_LEN); 1597 1598 switch (exit_reason.basic) { 1599 case VMX_VMCALL: 1600 switch(vmx_get_test_stage()) { 1601 case 0: 1602 if (!invvpid_test(INVVPID_ADDR, 1)) 1603 vmx_inc_test_stage(); 1604 break; 1605 case 2: 1606 if (!invvpid_test(INVVPID_CONTEXT_GLOBAL, 1)) 1607 vmx_inc_test_stage(); 1608 break; 1609 case 4: 1610 if (!invvpid_test(INVVPID_ALL, 1)) 1611 vmx_inc_test_stage(); 1612 break; 1613 default: 1614 report_fail("ERROR: unexpected stage, %d", 1615 vmx_get_test_stage()); 1616 print_vmexit_info(exit_reason); 1617 return VMX_TEST_VMEXIT; 1618 } 1619 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1620 return VMX_TEST_RESUME; 1621 default: 1622 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 1623 print_vmexit_info(exit_reason); 1624 } 1625 return VMX_TEST_VMEXIT; 1626 } 1627 1628 #define TIMER_VECTOR 222 1629 1630 static volatile bool timer_fired; 1631 1632 static void timer_isr(isr_regs_t *regs) 1633 { 1634 timer_fired = true; 1635 apic_write(APIC_EOI, 0); 1636 } 1637 1638 static int interrupt_init(struct vmcs *vmcs) 1639 { 1640 msr_bmp_init(); 1641 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1642 handle_irq(TIMER_VECTOR, timer_isr); 1643 return VMX_TEST_START; 1644 } 1645 1646 static void interrupt_main(void) 1647 { 1648 long long start, loops; 1649 1650 vmx_set_test_stage(0); 1651 1652 apic_write(APIC_LVTT, TIMER_VECTOR); 1653 irq_enable(); 1654 1655 apic_write(APIC_TMICT, 1); 1656 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1657 asm volatile ("nop"); 1658 report(timer_fired, "direct interrupt while running guest"); 1659 1660 apic_write(APIC_TMICT, 0); 1661 irq_disable(); 1662 vmcall(); 1663 timer_fired = false; 1664 apic_write(APIC_TMICT, 1); 1665 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1666 asm volatile ("nop"); 1667 report(timer_fired, "intercepted interrupt while running guest"); 1668 1669 irq_enable(); 1670 apic_write(APIC_TMICT, 0); 1671 irq_disable(); 1672 vmcall(); 1673 timer_fired = false; 1674 start = rdtsc(); 1675 apic_write(APIC_TMICT, 1000000); 1676 1677 asm volatile ("sti; hlt"); 1678 1679 report(rdtsc() - start > 1000000 && timer_fired, 1680 "direct interrupt + hlt"); 1681 1682 apic_write(APIC_TMICT, 0); 1683 irq_disable(); 1684 vmcall(); 1685 timer_fired = false; 1686 start = rdtsc(); 1687 apic_write(APIC_TMICT, 1000000); 1688 1689 asm volatile ("sti; hlt"); 1690 1691 report(rdtsc() - start > 10000 && timer_fired, 1692 "intercepted interrupt + hlt"); 1693 1694 apic_write(APIC_TMICT, 0); 1695 irq_disable(); 1696 vmcall(); 1697 timer_fired = false; 1698 start = rdtsc(); 1699 apic_write(APIC_TMICT, 1000000); 1700 1701 irq_enable(); 1702 asm volatile ("nop"); 1703 vmcall(); 1704 1705 report(rdtsc() - start > 10000 && timer_fired, 1706 "direct interrupt + activity state hlt"); 1707 1708 apic_write(APIC_TMICT, 0); 1709 irq_disable(); 1710 vmcall(); 1711 timer_fired = false; 1712 start = rdtsc(); 1713 apic_write(APIC_TMICT, 1000000); 1714 1715 irq_enable(); 1716 asm volatile ("nop"); 1717 vmcall(); 1718 1719 report(rdtsc() - start > 10000 && timer_fired, 1720 "intercepted interrupt + activity state hlt"); 1721 1722 apic_write(APIC_TMICT, 0); 1723 irq_disable(); 1724 vmx_set_test_stage(7); 1725 vmcall(); 1726 timer_fired = false; 1727 apic_write(APIC_TMICT, 1); 1728 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1729 asm volatile ("nop"); 1730 report(timer_fired, 1731 "running a guest with interrupt acknowledgement set"); 1732 1733 apic_write(APIC_TMICT, 0); 1734 irq_enable(); 1735 timer_fired = false; 1736 vmcall(); 1737 report(timer_fired, "Inject an event to a halted guest"); 1738 } 1739 1740 static int interrupt_exit_handler(union exit_reason exit_reason) 1741 { 1742 u64 guest_rip = vmcs_read(GUEST_RIP); 1743 u32 insn_len = vmcs_read(EXI_INST_LEN); 1744 1745 switch (exit_reason.basic) { 1746 case VMX_VMCALL: 1747 switch (vmx_get_test_stage()) { 1748 case 0: 1749 case 2: 1750 case 5: 1751 vmcs_write(PIN_CONTROLS, 1752 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1753 break; 1754 case 7: 1755 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_INTA); 1756 vmcs_write(PIN_CONTROLS, 1757 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1758 break; 1759 case 1: 1760 case 3: 1761 vmcs_write(PIN_CONTROLS, 1762 vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1763 break; 1764 case 4: 1765 case 6: 1766 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1767 break; 1768 1769 case 8: 1770 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1771 vmcs_write(ENT_INTR_INFO, 1772 TIMER_VECTOR | 1773 (VMX_INTR_TYPE_EXT_INTR << INTR_INFO_INTR_TYPE_SHIFT) | 1774 INTR_INFO_VALID_MASK); 1775 break; 1776 } 1777 vmx_inc_test_stage(); 1778 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1779 return VMX_TEST_RESUME; 1780 case VMX_EXTINT: 1781 if (vmcs_read(EXI_CONTROLS) & EXI_INTA) { 1782 int vector = vmcs_read(EXI_INTR_INFO) & 0xff; 1783 handle_external_interrupt(vector); 1784 } else { 1785 irq_enable(); 1786 asm volatile ("nop"); 1787 irq_disable(); 1788 } 1789 if (vmx_get_test_stage() >= 2) 1790 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 1791 return VMX_TEST_RESUME; 1792 default: 1793 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 1794 print_vmexit_info(exit_reason); 1795 } 1796 1797 return VMX_TEST_VMEXIT; 1798 } 1799 1800 1801 static volatile int nmi_fired; 1802 1803 #define NMI_DELAY 100000000ULL 1804 1805 static void nmi_isr(isr_regs_t *regs) 1806 { 1807 nmi_fired = true; 1808 } 1809 1810 static int nmi_hlt_init(struct vmcs *vmcs) 1811 { 1812 msr_bmp_init(); 1813 handle_irq(NMI_VECTOR, nmi_isr); 1814 vmcs_write(PIN_CONTROLS, 1815 vmcs_read(PIN_CONTROLS) & ~PIN_NMI); 1816 vmcs_write(PIN_CONTROLS, 1817 vmcs_read(PIN_CONTROLS) & ~PIN_VIRT_NMI); 1818 return VMX_TEST_START; 1819 } 1820 1821 static void nmi_message_thread(void *data) 1822 { 1823 while (vmx_get_test_stage() != 1) 1824 pause(); 1825 1826 delay(NMI_DELAY); 1827 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_NMI | APIC_INT_ASSERT, id_map[0]); 1828 1829 while (vmx_get_test_stage() != 2) 1830 pause(); 1831 1832 delay(NMI_DELAY); 1833 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_NMI | APIC_INT_ASSERT, id_map[0]); 1834 } 1835 1836 static void nmi_hlt_main(void) 1837 { 1838 long long start; 1839 1840 if (cpu_count() < 2) { 1841 report_skip(__func__); 1842 vmx_set_test_stage(-1); 1843 return; 1844 } 1845 1846 vmx_set_test_stage(0); 1847 on_cpu_async(1, nmi_message_thread, NULL); 1848 start = rdtsc(); 1849 vmx_set_test_stage(1); 1850 asm volatile ("hlt"); 1851 report((rdtsc() - start > NMI_DELAY) && nmi_fired, 1852 "direct NMI + hlt"); 1853 if (!nmi_fired) 1854 vmx_set_test_stage(-1); 1855 nmi_fired = false; 1856 1857 vmcall(); 1858 1859 start = rdtsc(); 1860 vmx_set_test_stage(2); 1861 asm volatile ("hlt"); 1862 report((rdtsc() - start > NMI_DELAY) && !nmi_fired, 1863 "intercepted NMI + hlt"); 1864 if (nmi_fired) { 1865 report(!nmi_fired, "intercepted NMI was dispatched"); 1866 vmx_set_test_stage(-1); 1867 return; 1868 } 1869 vmx_set_test_stage(3); 1870 } 1871 1872 static int nmi_hlt_exit_handler(union exit_reason exit_reason) 1873 { 1874 u64 guest_rip = vmcs_read(GUEST_RIP); 1875 u32 insn_len = vmcs_read(EXI_INST_LEN); 1876 1877 switch (vmx_get_test_stage()) { 1878 case 1: 1879 if (exit_reason.basic != VMX_VMCALL) { 1880 report_fail("VMEXIT not due to vmcall. Exit reason 0x%x", 1881 exit_reason.full); 1882 print_vmexit_info(exit_reason); 1883 return VMX_TEST_VMEXIT; 1884 } 1885 1886 vmcs_write(PIN_CONTROLS, 1887 vmcs_read(PIN_CONTROLS) | PIN_NMI); 1888 vmcs_write(PIN_CONTROLS, 1889 vmcs_read(PIN_CONTROLS) | PIN_VIRT_NMI); 1890 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1891 break; 1892 1893 case 2: 1894 if (exit_reason.basic != VMX_EXC_NMI) { 1895 report_fail("VMEXIT not due to NMI intercept. Exit reason 0x%x", 1896 exit_reason.full); 1897 print_vmexit_info(exit_reason); 1898 return VMX_TEST_VMEXIT; 1899 } 1900 report(true, "NMI intercept while running guest"); 1901 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 1902 break; 1903 1904 case 3: 1905 break; 1906 1907 default: 1908 return VMX_TEST_VMEXIT; 1909 } 1910 1911 if (vmx_get_test_stage() == 3) 1912 return VMX_TEST_VMEXIT; 1913 1914 return VMX_TEST_RESUME; 1915 } 1916 1917 1918 static int dbgctls_init(struct vmcs *vmcs) 1919 { 1920 u64 dr7 = 0x402; 1921 u64 zero = 0; 1922 1923 msr_bmp_init(); 1924 asm volatile( 1925 "mov %0,%%dr0\n\t" 1926 "mov %0,%%dr1\n\t" 1927 "mov %0,%%dr2\n\t" 1928 "mov %1,%%dr7\n\t" 1929 : : "r" (zero), "r" (dr7)); 1930 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1931 vmcs_write(GUEST_DR7, 0x404); 1932 vmcs_write(GUEST_DEBUGCTL, 0x2); 1933 1934 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 1935 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_SAVE_DBGCTLS); 1936 1937 return VMX_TEST_START; 1938 } 1939 1940 static void dbgctls_main(void) 1941 { 1942 u64 dr7, debugctl; 1943 1944 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1945 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1946 /* Commented out: KVM does not support DEBUGCTL so far */ 1947 (void)debugctl; 1948 report(dr7 == 0x404, "Load debug controls" /* && debugctl == 0x2 */); 1949 1950 dr7 = 0x408; 1951 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1952 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1953 1954 vmx_set_test_stage(0); 1955 vmcall(); 1956 report(vmx_get_test_stage() == 1, "Save debug controls"); 1957 1958 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS || 1959 ctrl_exit_rev.set & EXI_SAVE_DBGCTLS) { 1960 printf("\tDebug controls are always loaded/saved\n"); 1961 return; 1962 } 1963 vmx_set_test_stage(2); 1964 vmcall(); 1965 1966 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1967 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1968 /* Commented out: KVM does not support DEBUGCTL so far */ 1969 (void)debugctl; 1970 report(dr7 == 0x402, 1971 "Guest=host debug controls" /* && debugctl == 0x1 */); 1972 1973 dr7 = 0x408; 1974 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1975 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1976 1977 vmx_set_test_stage(3); 1978 vmcall(); 1979 report(vmx_get_test_stage() == 4, "Don't save debug controls"); 1980 } 1981 1982 static int dbgctls_exit_handler(union exit_reason exit_reason) 1983 { 1984 u32 insn_len = vmcs_read(EXI_INST_LEN); 1985 u64 guest_rip = vmcs_read(GUEST_RIP); 1986 u64 dr7, debugctl; 1987 1988 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1989 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1990 1991 switch (exit_reason.basic) { 1992 case VMX_VMCALL: 1993 switch (vmx_get_test_stage()) { 1994 case 0: 1995 if (dr7 == 0x400 && debugctl == 0 && 1996 vmcs_read(GUEST_DR7) == 0x408 /* && 1997 Commented out: KVM does not support DEBUGCTL so far 1998 vmcs_read(GUEST_DEBUGCTL) == 0x3 */) 1999 vmx_inc_test_stage(); 2000 break; 2001 case 2: 2002 dr7 = 0x402; 2003 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 2004 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 2005 vmcs_write(GUEST_DR7, 0x404); 2006 vmcs_write(GUEST_DEBUGCTL, 0x2); 2007 2008 vmcs_write(ENT_CONTROLS, 2009 vmcs_read(ENT_CONTROLS) & ~ENT_LOAD_DBGCTLS); 2010 vmcs_write(EXI_CONTROLS, 2011 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_DBGCTLS); 2012 break; 2013 case 3: 2014 if (dr7 == 0x400 && debugctl == 0 && 2015 vmcs_read(GUEST_DR7) == 0x404 /* && 2016 Commented out: KVM does not support DEBUGCTL so far 2017 vmcs_read(GUEST_DEBUGCTL) == 0x2 */) 2018 vmx_inc_test_stage(); 2019 break; 2020 } 2021 vmcs_write(GUEST_RIP, guest_rip + insn_len); 2022 return VMX_TEST_RESUME; 2023 default: 2024 report_fail("Unknown exit reason, %d", exit_reason.full); 2025 print_vmexit_info(exit_reason); 2026 } 2027 return VMX_TEST_VMEXIT; 2028 } 2029 2030 struct vmx_msr_entry { 2031 u32 index; 2032 u32 reserved; 2033 u64 value; 2034 } __attribute__((packed)); 2035 2036 #define MSR_MAGIC 0x31415926 2037 struct vmx_msr_entry *exit_msr_store, *entry_msr_load, *exit_msr_load; 2038 2039 static int msr_switch_init(struct vmcs *vmcs) 2040 { 2041 msr_bmp_init(); 2042 exit_msr_store = alloc_page(); 2043 exit_msr_load = alloc_page(); 2044 entry_msr_load = alloc_page(); 2045 entry_msr_load[0].index = MSR_KERNEL_GS_BASE; 2046 entry_msr_load[0].value = MSR_MAGIC; 2047 2048 vmx_set_test_stage(1); 2049 vmcs_write(ENT_MSR_LD_CNT, 1); 2050 vmcs_write(ENTER_MSR_LD_ADDR, (u64)entry_msr_load); 2051 vmcs_write(EXI_MSR_ST_CNT, 1); 2052 vmcs_write(EXIT_MSR_ST_ADDR, (u64)exit_msr_store); 2053 vmcs_write(EXI_MSR_LD_CNT, 1); 2054 vmcs_write(EXIT_MSR_LD_ADDR, (u64)exit_msr_load); 2055 return VMX_TEST_START; 2056 } 2057 2058 static void msr_switch_main(void) 2059 { 2060 if (vmx_get_test_stage() == 1) { 2061 report(rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC, 2062 "VM entry MSR load"); 2063 vmx_set_test_stage(2); 2064 wrmsr(MSR_KERNEL_GS_BASE, MSR_MAGIC + 1); 2065 exit_msr_store[0].index = MSR_KERNEL_GS_BASE; 2066 exit_msr_load[0].index = MSR_KERNEL_GS_BASE; 2067 exit_msr_load[0].value = MSR_MAGIC + 2; 2068 } 2069 vmcall(); 2070 } 2071 2072 static int msr_switch_exit_handler(union exit_reason exit_reason) 2073 { 2074 if (exit_reason.basic == VMX_VMCALL && vmx_get_test_stage() == 2) { 2075 report(exit_msr_store[0].value == MSR_MAGIC + 1, 2076 "VM exit MSR store"); 2077 report(rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC + 2, 2078 "VM exit MSR load"); 2079 vmx_set_test_stage(3); 2080 entry_msr_load[0].index = MSR_FS_BASE; 2081 return VMX_TEST_RESUME; 2082 } 2083 printf("ERROR %s: unexpected stage=%u or reason=0x%x\n", 2084 __func__, vmx_get_test_stage(), exit_reason.full); 2085 return VMX_TEST_EXIT; 2086 } 2087 2088 static int msr_switch_entry_failure(struct vmentry_result *result) 2089 { 2090 if (result->vm_fail) { 2091 printf("ERROR %s: VM-Fail on %s\n", __func__, result->instr); 2092 return VMX_TEST_EXIT; 2093 } 2094 2095 if (result->exit_reason.failed_vmentry && 2096 result->exit_reason.basic == VMX_FAIL_MSR && 2097 vmx_get_test_stage() == 3) { 2098 report(vmcs_read(EXI_QUALIFICATION) == 1, 2099 "VM entry MSR load: try to load FS_BASE"); 2100 return VMX_TEST_VMEXIT; 2101 } 2102 printf("ERROR %s: unexpected stage=%u or reason=%x\n", 2103 __func__, vmx_get_test_stage(), result->exit_reason.full); 2104 return VMX_TEST_EXIT; 2105 } 2106 2107 static int vmmcall_init(struct vmcs *vmcs) 2108 { 2109 vmcs_write(EXC_BITMAP, 1 << UD_VECTOR); 2110 return VMX_TEST_START; 2111 } 2112 2113 static void vmmcall_main(void) 2114 { 2115 asm volatile( 2116 "mov $0xABCD, %%rax\n\t" 2117 "vmmcall\n\t" 2118 ::: "rax"); 2119 2120 report_fail("VMMCALL"); 2121 } 2122 2123 static int vmmcall_exit_handler(union exit_reason exit_reason) 2124 { 2125 switch (exit_reason.basic) { 2126 case VMX_VMCALL: 2127 printf("here\n"); 2128 report_fail("VMMCALL triggers #UD"); 2129 break; 2130 case VMX_EXC_NMI: 2131 report((vmcs_read(EXI_INTR_INFO) & 0xff) == UD_VECTOR, 2132 "VMMCALL triggers #UD"); 2133 break; 2134 default: 2135 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 2136 print_vmexit_info(exit_reason); 2137 } 2138 2139 return VMX_TEST_VMEXIT; 2140 } 2141 2142 static int disable_rdtscp_init(struct vmcs *vmcs) 2143 { 2144 u32 ctrl_cpu1; 2145 2146 if (ctrl_cpu_rev[0].clr & CPU_SECONDARY) { 2147 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 2148 ctrl_cpu1 &= ~CPU_RDTSCP; 2149 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 2150 } 2151 2152 return VMX_TEST_START; 2153 } 2154 2155 static void disable_rdtscp_ud_handler(struct ex_regs *regs) 2156 { 2157 switch (vmx_get_test_stage()) { 2158 case 0: 2159 report(true, "RDTSCP triggers #UD"); 2160 vmx_inc_test_stage(); 2161 regs->rip += 3; 2162 break; 2163 case 2: 2164 report(true, "RDPID triggers #UD"); 2165 vmx_inc_test_stage(); 2166 regs->rip += 4; 2167 break; 2168 } 2169 return; 2170 2171 } 2172 2173 static void disable_rdtscp_main(void) 2174 { 2175 /* Test that #UD is properly injected in L2. */ 2176 handle_exception(UD_VECTOR, disable_rdtscp_ud_handler); 2177 2178 vmx_set_test_stage(0); 2179 asm volatile("rdtscp" : : : "eax", "ecx", "edx"); 2180 vmcall(); 2181 asm volatile(".byte 0xf3, 0x0f, 0xc7, 0xf8" : : : "eax"); 2182 2183 handle_exception(UD_VECTOR, 0); 2184 vmcall(); 2185 } 2186 2187 static int disable_rdtscp_exit_handler(union exit_reason exit_reason) 2188 { 2189 switch (exit_reason.basic) { 2190 case VMX_VMCALL: 2191 switch (vmx_get_test_stage()) { 2192 case 0: 2193 report_fail("RDTSCP triggers #UD"); 2194 vmx_inc_test_stage(); 2195 /* fallthrough */ 2196 case 1: 2197 vmx_inc_test_stage(); 2198 vmcs_write(GUEST_RIP, vmcs_read(GUEST_RIP) + 3); 2199 return VMX_TEST_RESUME; 2200 case 2: 2201 report_fail("RDPID triggers #UD"); 2202 break; 2203 } 2204 break; 2205 2206 default: 2207 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 2208 print_vmexit_info(exit_reason); 2209 } 2210 return VMX_TEST_VMEXIT; 2211 } 2212 2213 static int int3_init(struct vmcs *vmcs) 2214 { 2215 vmcs_write(EXC_BITMAP, ~0u); 2216 return VMX_TEST_START; 2217 } 2218 2219 static void int3_guest_main(void) 2220 { 2221 asm volatile ("int3"); 2222 } 2223 2224 static int int3_exit_handler(union exit_reason exit_reason) 2225 { 2226 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2227 2228 report(exit_reason.basic == VMX_EXC_NMI && 2229 (intr_info & INTR_INFO_VALID_MASK) && 2230 (intr_info & INTR_INFO_VECTOR_MASK) == BP_VECTOR && 2231 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2232 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION, 2233 "L1 intercepts #BP"); 2234 2235 return VMX_TEST_VMEXIT; 2236 } 2237 2238 static int into_init(struct vmcs *vmcs) 2239 { 2240 vmcs_write(EXC_BITMAP, ~0u); 2241 return VMX_TEST_START; 2242 } 2243 2244 static void into_guest_main(void) 2245 { 2246 struct far_pointer32 fp = { 2247 .offset = (uintptr_t)&&into, 2248 .selector = KERNEL_CS32, 2249 }; 2250 uintptr_t rsp; 2251 2252 asm volatile ("mov %%rsp, %0" : "=r"(rsp)); 2253 2254 if (fp.offset != (uintptr_t)&&into) { 2255 printf("Code address too high.\n"); 2256 return; 2257 } 2258 if ((u32)rsp != rsp) { 2259 printf("Stack address too high.\n"); 2260 return; 2261 } 2262 2263 asm goto ("lcall *%0" : : "m" (fp) : "rax" : into); 2264 return; 2265 into: 2266 asm volatile (".code32;" 2267 "movl $0x7fffffff, %eax;" 2268 "addl %eax, %eax;" 2269 "into;" 2270 "lret;" 2271 ".code64"); 2272 __builtin_unreachable(); 2273 } 2274 2275 static int into_exit_handler(union exit_reason exit_reason) 2276 { 2277 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2278 2279 report(exit_reason.basic == VMX_EXC_NMI && 2280 (intr_info & INTR_INFO_VALID_MASK) && 2281 (intr_info & INTR_INFO_VECTOR_MASK) == OF_VECTOR && 2282 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2283 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION, 2284 "L1 intercepts #OF"); 2285 2286 return VMX_TEST_VMEXIT; 2287 } 2288 2289 static void exit_monitor_from_l2_main(void) 2290 { 2291 printf("Calling exit(0) from l2...\n"); 2292 exit(0); 2293 } 2294 2295 static int exit_monitor_from_l2_handler(union exit_reason exit_reason) 2296 { 2297 report_fail("The guest should have killed the VMM"); 2298 return VMX_TEST_EXIT; 2299 } 2300 2301 static void assert_exit_reason(u64 expected) 2302 { 2303 u64 actual = vmcs_read(EXI_REASON); 2304 2305 TEST_ASSERT_EQ_MSG(expected, actual, "Expected %s, got %s.", 2306 exit_reason_description(expected), 2307 exit_reason_description(actual)); 2308 } 2309 2310 static void skip_exit_insn(void) 2311 { 2312 u64 guest_rip = vmcs_read(GUEST_RIP); 2313 u32 insn_len = vmcs_read(EXI_INST_LEN); 2314 vmcs_write(GUEST_RIP, guest_rip + insn_len); 2315 } 2316 2317 static void skip_exit_vmcall(void) 2318 { 2319 assert_exit_reason(VMX_VMCALL); 2320 skip_exit_insn(); 2321 } 2322 2323 static void v2_null_test_guest(void) 2324 { 2325 } 2326 2327 static void v2_null_test(void) 2328 { 2329 test_set_guest(v2_null_test_guest); 2330 enter_guest(); 2331 report(1, __func__); 2332 } 2333 2334 static void v2_multiple_entries_test_guest(void) 2335 { 2336 vmx_set_test_stage(1); 2337 vmcall(); 2338 vmx_set_test_stage(2); 2339 } 2340 2341 static void v2_multiple_entries_test(void) 2342 { 2343 test_set_guest(v2_multiple_entries_test_guest); 2344 enter_guest(); 2345 TEST_ASSERT_EQ(vmx_get_test_stage(), 1); 2346 skip_exit_vmcall(); 2347 enter_guest(); 2348 TEST_ASSERT_EQ(vmx_get_test_stage(), 2); 2349 report(1, __func__); 2350 } 2351 2352 static int fixture_test_data = 1; 2353 2354 static void fixture_test_teardown(void *data) 2355 { 2356 *((int *) data) = 1; 2357 } 2358 2359 static void fixture_test_guest(void) 2360 { 2361 fixture_test_data++; 2362 } 2363 2364 2365 static void fixture_test_setup(void) 2366 { 2367 TEST_ASSERT_EQ_MSG(1, fixture_test_data, 2368 "fixture_test_teardown didn't run?!"); 2369 fixture_test_data = 2; 2370 test_add_teardown(fixture_test_teardown, &fixture_test_data); 2371 test_set_guest(fixture_test_guest); 2372 } 2373 2374 static void fixture_test_case1(void) 2375 { 2376 fixture_test_setup(); 2377 TEST_ASSERT_EQ(2, fixture_test_data); 2378 enter_guest(); 2379 TEST_ASSERT_EQ(3, fixture_test_data); 2380 report(1, __func__); 2381 } 2382 2383 static void fixture_test_case2(void) 2384 { 2385 fixture_test_setup(); 2386 TEST_ASSERT_EQ(2, fixture_test_data); 2387 enter_guest(); 2388 TEST_ASSERT_EQ(3, fixture_test_data); 2389 report(1, __func__); 2390 } 2391 2392 enum ept_access_op { 2393 OP_READ, 2394 OP_WRITE, 2395 OP_EXEC, 2396 OP_FLUSH_TLB, 2397 OP_EXIT, 2398 }; 2399 2400 static struct ept_access_test_data { 2401 unsigned long gpa; 2402 unsigned long *gva; 2403 unsigned long hpa; 2404 unsigned long *hva; 2405 enum ept_access_op op; 2406 } ept_access_test_data; 2407 2408 extern unsigned char ret42_start; 2409 extern unsigned char ret42_end; 2410 2411 /* Returns 42. */ 2412 asm( 2413 ".align 64\n" 2414 "ret42_start:\n" 2415 "mov $42, %eax\n" 2416 "ret\n" 2417 "ret42_end:\n" 2418 ); 2419 2420 static void 2421 diagnose_ept_violation_qual(u64 expected, u64 actual) 2422 { 2423 2424 #define DIAGNOSE(flag) \ 2425 do { \ 2426 if ((expected & flag) != (actual & flag)) \ 2427 printf(#flag " %sexpected\n", \ 2428 (expected & flag) ? "" : "un"); \ 2429 } while (0) 2430 2431 DIAGNOSE(EPT_VLT_RD); 2432 DIAGNOSE(EPT_VLT_WR); 2433 DIAGNOSE(EPT_VLT_FETCH); 2434 DIAGNOSE(EPT_VLT_PERM_RD); 2435 DIAGNOSE(EPT_VLT_PERM_WR); 2436 DIAGNOSE(EPT_VLT_PERM_EX); 2437 DIAGNOSE(EPT_VLT_LADDR_VLD); 2438 DIAGNOSE(EPT_VLT_PADDR); 2439 2440 #undef DIAGNOSE 2441 } 2442 2443 static void do_ept_access_op(enum ept_access_op op) 2444 { 2445 ept_access_test_data.op = op; 2446 enter_guest(); 2447 } 2448 2449 /* 2450 * Force the guest to flush its TLB (i.e., flush gva -> gpa mappings). Only 2451 * needed by tests that modify guest PTEs. 2452 */ 2453 static void ept_access_test_guest_flush_tlb(void) 2454 { 2455 do_ept_access_op(OP_FLUSH_TLB); 2456 skip_exit_vmcall(); 2457 } 2458 2459 /* 2460 * Modifies the EPT entry at @level in the mapping of @gpa. First clears the 2461 * bits in @clear then sets the bits in @set. @mkhuge transforms the entry into 2462 * a huge page. 2463 */ 2464 static unsigned long ept_twiddle(unsigned long gpa, bool mkhuge, int level, 2465 unsigned long clear, unsigned long set) 2466 { 2467 struct ept_access_test_data *data = &ept_access_test_data; 2468 unsigned long orig_pte; 2469 unsigned long pte; 2470 2471 /* Screw with the mapping at the requested level. */ 2472 TEST_ASSERT(get_ept_pte(pml4, gpa, level, &orig_pte)); 2473 pte = orig_pte; 2474 if (mkhuge) 2475 pte = (orig_pte & ~EPT_ADDR_MASK) | data->hpa | EPT_LARGE_PAGE; 2476 else 2477 pte = orig_pte; 2478 pte = (pte & ~clear) | set; 2479 set_ept_pte(pml4, gpa, level, pte); 2480 ept_sync(INVEPT_SINGLE, eptp); 2481 2482 return orig_pte; 2483 } 2484 2485 static void ept_untwiddle(unsigned long gpa, int level, unsigned long orig_pte) 2486 { 2487 set_ept_pte(pml4, gpa, level, orig_pte); 2488 ept_sync(INVEPT_SINGLE, eptp); 2489 } 2490 2491 static void do_ept_violation(bool leaf, enum ept_access_op op, 2492 u64 expected_qual, u64 expected_paddr) 2493 { 2494 u64 qual; 2495 2496 /* Try the access and observe the violation. */ 2497 do_ept_access_op(op); 2498 2499 assert_exit_reason(VMX_EPT_VIOLATION); 2500 2501 qual = vmcs_read(EXI_QUALIFICATION); 2502 2503 /* Mask undefined bits (which may later be defined in certain cases). */ 2504 qual &= ~(EPT_VLT_GUEST_USER | EPT_VLT_GUEST_RW | EPT_VLT_GUEST_EX | 2505 EPT_VLT_PERM_USER_EX); 2506 2507 diagnose_ept_violation_qual(expected_qual, qual); 2508 TEST_EXPECT_EQ(expected_qual, qual); 2509 2510 #if 0 2511 /* Disable for now otherwise every test will fail */ 2512 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2513 (unsigned long) ( 2514 op == OP_EXEC ? data->gva + 1 : data->gva)); 2515 #endif 2516 /* 2517 * TODO: tests that probe expected_paddr in pages other than the one at 2518 * the beginning of the 1g region. 2519 */ 2520 TEST_EXPECT_EQ(vmcs_read(INFO_PHYS_ADDR), expected_paddr); 2521 } 2522 2523 static void 2524 ept_violation_at_level_mkhuge(bool mkhuge, int level, unsigned long clear, 2525 unsigned long set, enum ept_access_op op, 2526 u64 expected_qual) 2527 { 2528 struct ept_access_test_data *data = &ept_access_test_data; 2529 unsigned long orig_pte; 2530 2531 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2532 2533 do_ept_violation(level == 1 || mkhuge, op, expected_qual, 2534 op == OP_EXEC ? data->gpa + sizeof(unsigned long) : 2535 data->gpa); 2536 2537 /* Fix the violation and resume the op loop. */ 2538 ept_untwiddle(data->gpa, level, orig_pte); 2539 enter_guest(); 2540 skip_exit_vmcall(); 2541 } 2542 2543 static void 2544 ept_violation_at_level(int level, unsigned long clear, unsigned long set, 2545 enum ept_access_op op, u64 expected_qual) 2546 { 2547 ept_violation_at_level_mkhuge(false, level, clear, set, op, 2548 expected_qual); 2549 if (ept_huge_pages_supported(level)) 2550 ept_violation_at_level_mkhuge(true, level, clear, set, op, 2551 expected_qual); 2552 } 2553 2554 static void ept_violation(unsigned long clear, unsigned long set, 2555 enum ept_access_op op, u64 expected_qual) 2556 { 2557 ept_violation_at_level(1, clear, set, op, expected_qual); 2558 ept_violation_at_level(2, clear, set, op, expected_qual); 2559 ept_violation_at_level(3, clear, set, op, expected_qual); 2560 ept_violation_at_level(4, clear, set, op, expected_qual); 2561 } 2562 2563 static void ept_access_violation(unsigned long access, enum ept_access_op op, 2564 u64 expected_qual) 2565 { 2566 ept_violation(EPT_PRESENT, access, op, 2567 expected_qual | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2568 } 2569 2570 /* 2571 * For translations that don't involve a GVA, that is physical address (paddr) 2572 * accesses, EPT violations don't set the flag EPT_VLT_PADDR. For a typical 2573 * guest memory access, the hardware does GVA -> GPA -> HPA. However, certain 2574 * translations don't involve GVAs, such as when the hardware does the guest 2575 * page table walk. For example, in translating GVA_1 -> GPA_1, the guest MMU 2576 * might try to set an A bit on a guest PTE. If the GPA_2 that the PTE resides 2577 * on isn't present in the EPT, then the EPT violation will be for GPA_2 and 2578 * the EPT_VLT_PADDR bit will be clear in the exit qualification. 2579 * 2580 * Note that paddr violations can also be triggered by loading PAE page tables 2581 * with wonky addresses. We don't test that yet. 2582 * 2583 * This function modifies the EPT entry that maps the GPA that the guest page 2584 * table entry mapping ept_access_test_data.gva resides on. 2585 * 2586 * @ept_access EPT permissions to set. Other permissions are cleared. 2587 * 2588 * @pte_ad Set the A/D bits on the guest PTE accordingly. 2589 * 2590 * @op Guest operation to perform with 2591 * ept_access_test_data.gva. 2592 * 2593 * @expect_violation 2594 * Is a violation expected during the paddr access? 2595 * 2596 * @expected_qual Expected qualification for the EPT violation. 2597 * EPT_VLT_PADDR should be clear. 2598 */ 2599 static void ept_access_paddr(unsigned long ept_access, unsigned long pte_ad, 2600 enum ept_access_op op, bool expect_violation, 2601 u64 expected_qual) 2602 { 2603 struct ept_access_test_data *data = &ept_access_test_data; 2604 unsigned long *ptep; 2605 unsigned long gpa; 2606 unsigned long orig_epte; 2607 unsigned long epte; 2608 int i; 2609 2610 /* Modify the guest PTE mapping data->gva according to @pte_ad. */ 2611 ptep = get_pte_level(current_page_table(), data->gva, /*level=*/1); 2612 TEST_ASSERT(ptep); 2613 TEST_ASSERT_EQ(*ptep & PT_ADDR_MASK, data->gpa); 2614 *ptep = (*ptep & ~PT_AD_MASK) | pte_ad; 2615 ept_access_test_guest_flush_tlb(); 2616 2617 /* 2618 * Now modify the access bits on the EPT entry for the GPA that the 2619 * guest PTE resides on. Note that by modifying a single EPT entry, 2620 * we're potentially affecting 512 guest PTEs. However, we've carefully 2621 * constructed our test such that those other 511 PTEs aren't used by 2622 * the guest: data->gva is at the beginning of a 1G huge page, thus the 2623 * PTE we're modifying is at the beginning of a 4K page and the 2624 * following 511 entires are also under our control (and not touched by 2625 * the guest). 2626 */ 2627 gpa = virt_to_phys(ptep); 2628 TEST_ASSERT_EQ(gpa & ~PAGE_MASK, 0); 2629 /* 2630 * Make sure the guest page table page is mapped with a 4K EPT entry, 2631 * otherwise our level=1 twiddling below will fail. We use the 2632 * identity map (gpa = gpa) since page tables are shared with the host. 2633 */ 2634 install_ept(pml4, gpa, gpa, EPT_PRESENT); 2635 orig_epte = ept_twiddle(gpa, /*mkhuge=*/0, /*level=*/1, 2636 /*clear=*/EPT_PRESENT, /*set=*/ept_access); 2637 2638 if (expect_violation) { 2639 do_ept_violation(/*leaf=*/true, op, 2640 expected_qual | EPT_VLT_LADDR_VLD, gpa); 2641 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2642 do_ept_access_op(op); 2643 } else { 2644 do_ept_access_op(op); 2645 if (ept_ad_enabled()) { 2646 for (i = EPT_PAGE_LEVEL; i > 0; i--) { 2647 TEST_ASSERT(get_ept_pte(pml4, gpa, i, &epte)); 2648 TEST_ASSERT(epte & EPT_ACCESS_FLAG); 2649 if (i == 1) 2650 TEST_ASSERT(epte & EPT_DIRTY_FLAG); 2651 else 2652 TEST_ASSERT_EQ(epte & EPT_DIRTY_FLAG, 0); 2653 } 2654 } 2655 2656 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2657 } 2658 2659 TEST_ASSERT(*ptep & PT_ACCESSED_MASK); 2660 if ((pte_ad & PT_DIRTY_MASK) || op == OP_WRITE) 2661 TEST_ASSERT(*ptep & PT_DIRTY_MASK); 2662 2663 skip_exit_vmcall(); 2664 } 2665 2666 static void ept_access_allowed_paddr(unsigned long ept_access, 2667 unsigned long pte_ad, 2668 enum ept_access_op op) 2669 { 2670 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/false, 2671 /*expected_qual=*/-1); 2672 } 2673 2674 static void ept_access_violation_paddr(unsigned long ept_access, 2675 unsigned long pte_ad, 2676 enum ept_access_op op, 2677 u64 expected_qual) 2678 { 2679 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/true, 2680 expected_qual); 2681 } 2682 2683 2684 static void ept_allowed_at_level_mkhuge(bool mkhuge, int level, 2685 unsigned long clear, 2686 unsigned long set, 2687 enum ept_access_op op) 2688 { 2689 struct ept_access_test_data *data = &ept_access_test_data; 2690 unsigned long orig_pte; 2691 2692 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2693 2694 /* No violation. Should proceed to vmcall. */ 2695 do_ept_access_op(op); 2696 skip_exit_vmcall(); 2697 2698 ept_untwiddle(data->gpa, level, orig_pte); 2699 } 2700 2701 static void ept_allowed_at_level(int level, unsigned long clear, 2702 unsigned long set, enum ept_access_op op) 2703 { 2704 ept_allowed_at_level_mkhuge(false, level, clear, set, op); 2705 if (ept_huge_pages_supported(level)) 2706 ept_allowed_at_level_mkhuge(true, level, clear, set, op); 2707 } 2708 2709 static void ept_allowed(unsigned long clear, unsigned long set, 2710 enum ept_access_op op) 2711 { 2712 ept_allowed_at_level(1, clear, set, op); 2713 ept_allowed_at_level(2, clear, set, op); 2714 ept_allowed_at_level(3, clear, set, op); 2715 ept_allowed_at_level(4, clear, set, op); 2716 } 2717 2718 static void ept_ignored_bit(int bit) 2719 { 2720 /* Set the bit. */ 2721 ept_allowed(0, 1ul << bit, OP_READ); 2722 ept_allowed(0, 1ul << bit, OP_WRITE); 2723 ept_allowed(0, 1ul << bit, OP_EXEC); 2724 2725 /* Clear the bit. */ 2726 ept_allowed(1ul << bit, 0, OP_READ); 2727 ept_allowed(1ul << bit, 0, OP_WRITE); 2728 ept_allowed(1ul << bit, 0, OP_EXEC); 2729 } 2730 2731 static void ept_access_allowed(unsigned long access, enum ept_access_op op) 2732 { 2733 ept_allowed(EPT_PRESENT, access, op); 2734 } 2735 2736 2737 static void ept_misconfig_at_level_mkhuge_op(bool mkhuge, int level, 2738 unsigned long clear, 2739 unsigned long set, 2740 enum ept_access_op op) 2741 { 2742 struct ept_access_test_data *data = &ept_access_test_data; 2743 unsigned long orig_pte; 2744 2745 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2746 2747 do_ept_access_op(op); 2748 assert_exit_reason(VMX_EPT_MISCONFIG); 2749 2750 /* Intel 27.2.1, "For all other VM exits, this field is cleared." */ 2751 #if 0 2752 /* broken: */ 2753 TEST_EXPECT_EQ_MSG(vmcs_read(EXI_QUALIFICATION), 0); 2754 #endif 2755 #if 0 2756 /* 2757 * broken: 2758 * According to description of exit qual for EPT violation, 2759 * EPT_VLT_LADDR_VLD indicates if GUEST_LINEAR_ADDRESS is valid. 2760 * However, I can't find anything that says GUEST_LINEAR_ADDRESS ought 2761 * to be set for msiconfig. 2762 */ 2763 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2764 (unsigned long) ( 2765 op == OP_EXEC ? data->gva + 1 : data->gva)); 2766 #endif 2767 2768 /* Fix the violation and resume the op loop. */ 2769 ept_untwiddle(data->gpa, level, orig_pte); 2770 enter_guest(); 2771 skip_exit_vmcall(); 2772 } 2773 2774 static void ept_misconfig_at_level_mkhuge(bool mkhuge, int level, 2775 unsigned long clear, 2776 unsigned long set) 2777 { 2778 /* The op shouldn't matter (read, write, exec), so try them all! */ 2779 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_READ); 2780 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_WRITE); 2781 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_EXEC); 2782 } 2783 2784 static void ept_misconfig_at_level(int level, unsigned long clear, 2785 unsigned long set) 2786 { 2787 ept_misconfig_at_level_mkhuge(false, level, clear, set); 2788 if (ept_huge_pages_supported(level)) 2789 ept_misconfig_at_level_mkhuge(true, level, clear, set); 2790 } 2791 2792 static void ept_misconfig(unsigned long clear, unsigned long set) 2793 { 2794 ept_misconfig_at_level(1, clear, set); 2795 ept_misconfig_at_level(2, clear, set); 2796 ept_misconfig_at_level(3, clear, set); 2797 ept_misconfig_at_level(4, clear, set); 2798 } 2799 2800 static void ept_access_misconfig(unsigned long access) 2801 { 2802 ept_misconfig(EPT_PRESENT, access); 2803 } 2804 2805 static void ept_reserved_bit_at_level_nohuge(int level, int bit) 2806 { 2807 /* Setting the bit causes a misconfig. */ 2808 ept_misconfig_at_level_mkhuge(false, level, 0, 1ul << bit); 2809 2810 /* Making the entry non-present turns reserved bits into ignored. */ 2811 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2812 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2813 } 2814 2815 static void ept_reserved_bit_at_level_huge(int level, int bit) 2816 { 2817 /* Setting the bit causes a misconfig. */ 2818 ept_misconfig_at_level_mkhuge(true, level, 0, 1ul << bit); 2819 2820 /* Making the entry non-present turns reserved bits into ignored. */ 2821 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2822 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2823 } 2824 2825 static void ept_reserved_bit_at_level(int level, int bit) 2826 { 2827 /* Setting the bit causes a misconfig. */ 2828 ept_misconfig_at_level(level, 0, 1ul << bit); 2829 2830 /* Making the entry non-present turns reserved bits into ignored. */ 2831 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2832 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2833 } 2834 2835 static void ept_reserved_bit(int bit) 2836 { 2837 ept_reserved_bit_at_level(1, bit); 2838 ept_reserved_bit_at_level(2, bit); 2839 ept_reserved_bit_at_level(3, bit); 2840 ept_reserved_bit_at_level(4, bit); 2841 } 2842 2843 #define PAGE_2M_ORDER 9 2844 #define PAGE_1G_ORDER 18 2845 2846 static void *get_1g_page(void) 2847 { 2848 static void *alloc; 2849 2850 if (!alloc) 2851 alloc = alloc_pages(PAGE_1G_ORDER); 2852 return alloc; 2853 } 2854 2855 static void ept_access_test_teardown(void *unused) 2856 { 2857 /* Exit the guest cleanly. */ 2858 do_ept_access_op(OP_EXIT); 2859 } 2860 2861 static void ept_access_test_guest(void) 2862 { 2863 struct ept_access_test_data *data = &ept_access_test_data; 2864 int (*code)(void) = (int (*)(void)) &data->gva[1]; 2865 2866 while (true) { 2867 switch (data->op) { 2868 case OP_READ: 2869 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_1); 2870 break; 2871 case OP_WRITE: 2872 *data->gva = MAGIC_VAL_2; 2873 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_2); 2874 *data->gva = MAGIC_VAL_1; 2875 break; 2876 case OP_EXEC: 2877 TEST_ASSERT_EQ(42, code()); 2878 break; 2879 case OP_FLUSH_TLB: 2880 write_cr3(read_cr3()); 2881 break; 2882 case OP_EXIT: 2883 return; 2884 default: 2885 TEST_ASSERT_MSG(false, "Unknown op %d", data->op); 2886 } 2887 vmcall(); 2888 } 2889 } 2890 2891 static void ept_access_test_setup(void) 2892 { 2893 struct ept_access_test_data *data = &ept_access_test_data; 2894 unsigned long npages = 1ul << PAGE_1G_ORDER; 2895 unsigned long size = npages * PAGE_SIZE; 2896 unsigned long *page_table = current_page_table(); 2897 unsigned long pte; 2898 2899 if (setup_ept(false)) 2900 test_skip("EPT not supported"); 2901 2902 /* We use data->gpa = 1 << 39 so that test data has a separate pml4 entry */ 2903 if (cpuid_maxphyaddr() < 40) 2904 test_skip("Test needs MAXPHYADDR >= 40"); 2905 2906 test_set_guest(ept_access_test_guest); 2907 test_add_teardown(ept_access_test_teardown, NULL); 2908 2909 data->hva = get_1g_page(); 2910 TEST_ASSERT(data->hva); 2911 data->hpa = virt_to_phys(data->hva); 2912 2913 data->gpa = 1ul << 39; 2914 data->gva = (void *) ALIGN((unsigned long) alloc_vpages(npages * 2), 2915 size); 2916 TEST_ASSERT(!any_present_pages(page_table, data->gva, size)); 2917 install_pages(page_table, data->gpa, size, data->gva); 2918 2919 /* 2920 * Make sure nothing's mapped here so the tests that screw with the 2921 * pml4 entry don't inadvertently break something. 2922 */ 2923 TEST_ASSERT(get_ept_pte(pml4, data->gpa, 4, &pte) && pte == 0); 2924 TEST_ASSERT(get_ept_pte(pml4, data->gpa + size - 1, 4, &pte) && pte == 0); 2925 install_ept(pml4, data->hpa, data->gpa, EPT_PRESENT); 2926 2927 data->hva[0] = MAGIC_VAL_1; 2928 memcpy(&data->hva[1], &ret42_start, &ret42_end - &ret42_start); 2929 } 2930 2931 static void ept_access_test_not_present(void) 2932 { 2933 ept_access_test_setup(); 2934 /* --- */ 2935 ept_access_violation(0, OP_READ, EPT_VLT_RD); 2936 ept_access_violation(0, OP_WRITE, EPT_VLT_WR); 2937 ept_access_violation(0, OP_EXEC, EPT_VLT_FETCH); 2938 } 2939 2940 static void ept_access_test_read_only(void) 2941 { 2942 ept_access_test_setup(); 2943 2944 /* r-- */ 2945 ept_access_allowed(EPT_RA, OP_READ); 2946 ept_access_violation(EPT_RA, OP_WRITE, EPT_VLT_WR | EPT_VLT_PERM_RD); 2947 ept_access_violation(EPT_RA, OP_EXEC, EPT_VLT_FETCH | EPT_VLT_PERM_RD); 2948 } 2949 2950 static void ept_access_test_write_only(void) 2951 { 2952 ept_access_test_setup(); 2953 /* -w- */ 2954 ept_access_misconfig(EPT_WA); 2955 } 2956 2957 static void ept_access_test_read_write(void) 2958 { 2959 ept_access_test_setup(); 2960 /* rw- */ 2961 ept_access_allowed(EPT_RA | EPT_WA, OP_READ); 2962 ept_access_allowed(EPT_RA | EPT_WA, OP_WRITE); 2963 ept_access_violation(EPT_RA | EPT_WA, OP_EXEC, 2964 EPT_VLT_FETCH | EPT_VLT_PERM_RD | EPT_VLT_PERM_WR); 2965 } 2966 2967 2968 static void ept_access_test_execute_only(void) 2969 { 2970 ept_access_test_setup(); 2971 /* --x */ 2972 if (ept_execute_only_supported()) { 2973 ept_access_violation(EPT_EA, OP_READ, 2974 EPT_VLT_RD | EPT_VLT_PERM_EX); 2975 ept_access_violation(EPT_EA, OP_WRITE, 2976 EPT_VLT_WR | EPT_VLT_PERM_EX); 2977 ept_access_allowed(EPT_EA, OP_EXEC); 2978 } else { 2979 ept_access_misconfig(EPT_EA); 2980 } 2981 } 2982 2983 static void ept_access_test_read_execute(void) 2984 { 2985 ept_access_test_setup(); 2986 /* r-x */ 2987 ept_access_allowed(EPT_RA | EPT_EA, OP_READ); 2988 ept_access_violation(EPT_RA | EPT_EA, OP_WRITE, 2989 EPT_VLT_WR | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX); 2990 ept_access_allowed(EPT_RA | EPT_EA, OP_EXEC); 2991 } 2992 2993 static void ept_access_test_write_execute(void) 2994 { 2995 ept_access_test_setup(); 2996 /* -wx */ 2997 ept_access_misconfig(EPT_WA | EPT_EA); 2998 } 2999 3000 static void ept_access_test_read_write_execute(void) 3001 { 3002 ept_access_test_setup(); 3003 /* rwx */ 3004 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_READ); 3005 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_WRITE); 3006 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_EXEC); 3007 } 3008 3009 static void ept_access_test_reserved_bits(void) 3010 { 3011 int i; 3012 int maxphyaddr; 3013 3014 ept_access_test_setup(); 3015 3016 /* Reserved bits above maxphyaddr. */ 3017 maxphyaddr = cpuid_maxphyaddr(); 3018 for (i = maxphyaddr; i <= 51; i++) { 3019 report_prefix_pushf("reserved_bit=%d", i); 3020 ept_reserved_bit(i); 3021 report_prefix_pop(); 3022 } 3023 3024 /* Level-specific reserved bits. */ 3025 ept_reserved_bit_at_level_nohuge(2, 3); 3026 ept_reserved_bit_at_level_nohuge(2, 4); 3027 ept_reserved_bit_at_level_nohuge(2, 5); 3028 ept_reserved_bit_at_level_nohuge(2, 6); 3029 /* 2M alignment. */ 3030 for (i = 12; i < 20; i++) { 3031 report_prefix_pushf("reserved_bit=%d", i); 3032 ept_reserved_bit_at_level_huge(2, i); 3033 report_prefix_pop(); 3034 } 3035 ept_reserved_bit_at_level_nohuge(3, 3); 3036 ept_reserved_bit_at_level_nohuge(3, 4); 3037 ept_reserved_bit_at_level_nohuge(3, 5); 3038 ept_reserved_bit_at_level_nohuge(3, 6); 3039 /* 1G alignment. */ 3040 for (i = 12; i < 29; i++) { 3041 report_prefix_pushf("reserved_bit=%d", i); 3042 ept_reserved_bit_at_level_huge(3, i); 3043 report_prefix_pop(); 3044 } 3045 ept_reserved_bit_at_level(4, 3); 3046 ept_reserved_bit_at_level(4, 4); 3047 ept_reserved_bit_at_level(4, 5); 3048 ept_reserved_bit_at_level(4, 6); 3049 ept_reserved_bit_at_level(4, 7); 3050 } 3051 3052 static void ept_access_test_ignored_bits(void) 3053 { 3054 ept_access_test_setup(); 3055 /* 3056 * Bits ignored at every level. Bits 8 and 9 (A and D) are ignored as 3057 * far as translation is concerned even if AD bits are enabled in the 3058 * EPTP. Bit 63 is ignored because "EPT-violation #VE" VM-execution 3059 * control is 0. 3060 */ 3061 ept_ignored_bit(8); 3062 ept_ignored_bit(9); 3063 ept_ignored_bit(10); 3064 ept_ignored_bit(11); 3065 ept_ignored_bit(52); 3066 ept_ignored_bit(53); 3067 ept_ignored_bit(54); 3068 ept_ignored_bit(55); 3069 ept_ignored_bit(56); 3070 ept_ignored_bit(57); 3071 ept_ignored_bit(58); 3072 ept_ignored_bit(59); 3073 ept_ignored_bit(60); 3074 ept_ignored_bit(61); 3075 ept_ignored_bit(62); 3076 ept_ignored_bit(63); 3077 } 3078 3079 static void ept_access_test_paddr_not_present_ad_disabled(void) 3080 { 3081 ept_access_test_setup(); 3082 ept_disable_ad_bits(); 3083 3084 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, EPT_VLT_RD); 3085 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, EPT_VLT_RD); 3086 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, EPT_VLT_RD); 3087 } 3088 3089 static void ept_access_test_paddr_not_present_ad_enabled(void) 3090 { 3091 u64 qual = EPT_VLT_RD | EPT_VLT_WR; 3092 3093 ept_access_test_setup(); 3094 ept_enable_ad_bits_or_skip_test(); 3095 3096 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, qual); 3097 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, qual); 3098 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, qual); 3099 } 3100 3101 static void ept_access_test_paddr_read_only_ad_disabled(void) 3102 { 3103 /* 3104 * When EPT AD bits are disabled, all accesses to guest paging 3105 * structures are reported separately as a read and (after 3106 * translation of the GPA to host physical address) a read+write 3107 * if the A/D bits have to be set. 3108 */ 3109 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 3110 3111 ept_access_test_setup(); 3112 ept_disable_ad_bits(); 3113 3114 /* Can't update A bit, so all accesses fail. */ 3115 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 3116 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 3117 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 3118 /* AD bits disabled, so only writes try to update the D bit. */ 3119 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ); 3120 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 3121 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC); 3122 /* Both A and D already set, so read-only is OK. */ 3123 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_READ); 3124 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_WRITE); 3125 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_EXEC); 3126 } 3127 3128 static void ept_access_test_paddr_read_only_ad_enabled(void) 3129 { 3130 /* 3131 * When EPT AD bits are enabled, all accesses to guest paging 3132 * structures are considered writes as far as EPT translation 3133 * is concerned. 3134 */ 3135 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 3136 3137 ept_access_test_setup(); 3138 ept_enable_ad_bits_or_skip_test(); 3139 3140 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 3141 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 3142 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 3143 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ, qual); 3144 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 3145 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC, qual); 3146 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_READ, qual); 3147 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_WRITE, qual); 3148 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_EXEC, qual); 3149 } 3150 3151 static void ept_access_test_paddr_read_write(void) 3152 { 3153 ept_access_test_setup(); 3154 /* Read-write access to paging structure. */ 3155 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_READ); 3156 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_WRITE); 3157 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_EXEC); 3158 } 3159 3160 static void ept_access_test_paddr_read_write_execute(void) 3161 { 3162 ept_access_test_setup(); 3163 /* RWX access to paging structure. */ 3164 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_READ); 3165 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_WRITE); 3166 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_EXEC); 3167 } 3168 3169 static void ept_access_test_paddr_read_execute_ad_disabled(void) 3170 { 3171 /* 3172 * When EPT AD bits are disabled, all accesses to guest paging 3173 * structures are reported separately as a read and (after 3174 * translation of the GPA to host physical address) a read+write 3175 * if the A/D bits have to be set. 3176 */ 3177 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3178 3179 ept_access_test_setup(); 3180 ept_disable_ad_bits(); 3181 3182 /* Can't update A bit, so all accesses fail. */ 3183 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3184 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3185 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3186 /* AD bits disabled, so only writes try to update the D bit. */ 3187 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ); 3188 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3189 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC); 3190 /* Both A and D already set, so read-only is OK. */ 3191 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ); 3192 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE); 3193 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC); 3194 } 3195 3196 static void ept_access_test_paddr_read_execute_ad_enabled(void) 3197 { 3198 /* 3199 * When EPT AD bits are enabled, all accesses to guest paging 3200 * structures are considered writes as far as EPT translation 3201 * is concerned. 3202 */ 3203 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3204 3205 ept_access_test_setup(); 3206 ept_enable_ad_bits_or_skip_test(); 3207 3208 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3209 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3210 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3211 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ, qual); 3212 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3213 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC, qual); 3214 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ, qual); 3215 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE, qual); 3216 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC, qual); 3217 } 3218 3219 static void ept_access_test_paddr_not_present_page_fault(void) 3220 { 3221 ept_access_test_setup(); 3222 /* 3223 * TODO: test no EPT violation as long as guest PF occurs. e.g., GPA is 3224 * page is read-only in EPT but GVA is also mapped read only in PT. 3225 * Thus guest page fault before host takes EPT violation for trying to 3226 * update A bit. 3227 */ 3228 } 3229 3230 static void ept_access_test_force_2m_page(void) 3231 { 3232 ept_access_test_setup(); 3233 3234 TEST_ASSERT_EQ(ept_2m_supported(), true); 3235 ept_allowed_at_level_mkhuge(true, 2, 0, 0, OP_READ); 3236 ept_violation_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_RA, OP_WRITE, 3237 EPT_VLT_WR | EPT_VLT_PERM_RD | 3238 EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 3239 ept_misconfig_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_WA); 3240 } 3241 3242 static bool invvpid_valid(u64 type, u64 vpid, u64 gla) 3243 { 3244 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3245 3246 TEST_ASSERT(msr & VPID_CAP_INVVPID); 3247 3248 if (type < INVVPID_ADDR || type > INVVPID_CONTEXT_LOCAL) 3249 return false; 3250 3251 if (!(msr & (1ull << (type + VPID_CAP_INVVPID_TYPES_SHIFT)))) 3252 return false; 3253 3254 if (vpid >> 16) 3255 return false; 3256 3257 if (type != INVVPID_ALL && !vpid) 3258 return false; 3259 3260 if (type == INVVPID_ADDR && !is_canonical(gla)) 3261 return false; 3262 3263 return true; 3264 } 3265 3266 static void try_invvpid(u64 type, u64 vpid, u64 gla) 3267 { 3268 int rc; 3269 bool valid = invvpid_valid(type, vpid, gla); 3270 u64 expected = valid ? VMXERR_UNSUPPORTED_VMCS_COMPONENT 3271 : VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID; 3272 /* 3273 * Set VMX_INST_ERROR to VMXERR_UNVALID_VMCS_COMPONENT, so 3274 * that we can tell if it is updated by INVVPID. 3275 */ 3276 vmcs_read(~0); 3277 rc = invvpid(type, vpid, gla); 3278 report(!rc == valid, "INVVPID type %ld VPID %lx GLA %lx %s", type, 3279 vpid, gla, 3280 valid ? "passes" : "fails"); 3281 report(vmcs_read(VMX_INST_ERROR) == expected, 3282 "After %s INVVPID, VMX_INST_ERR is %ld (actual %ld)", 3283 rc ? "failed" : "successful", 3284 expected, vmcs_read(VMX_INST_ERROR)); 3285 } 3286 3287 static void ds_invvpid(void *data) 3288 { 3289 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3290 u64 type = ffs(msr >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 3291 3292 TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 3293 asm volatile("invvpid %0, %1" 3294 : 3295 : "m"(*(struct invvpid_operand *)data), 3296 "r"(type)); 3297 } 3298 3299 /* 3300 * The SS override is ignored in 64-bit mode, so we use an addressing 3301 * mode with %rsp as the base register to generate an implicit SS 3302 * reference. 3303 */ 3304 static void ss_invvpid(void *data) 3305 { 3306 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3307 u64 type = ffs(msr >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 3308 3309 TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 3310 asm volatile("sub %%rsp,%0; invvpid (%%rsp,%0,1), %1" 3311 : "+r"(data) 3312 : "r"(type)); 3313 } 3314 3315 static void invvpid_test_gp(void) 3316 { 3317 bool fault; 3318 3319 fault = test_for_exception(GP_VECTOR, &ds_invvpid, 3320 (void *)NONCANONICAL); 3321 report(fault, "INVVPID with non-canonical DS operand raises #GP"); 3322 } 3323 3324 static void invvpid_test_ss(void) 3325 { 3326 bool fault; 3327 3328 fault = test_for_exception(SS_VECTOR, &ss_invvpid, 3329 (void *)NONCANONICAL); 3330 report(fault, "INVVPID with non-canonical SS operand raises #SS"); 3331 } 3332 3333 static void invvpid_test_pf(void) 3334 { 3335 void *vpage = alloc_vpage(); 3336 bool fault; 3337 3338 fault = test_for_exception(PF_VECTOR, &ds_invvpid, vpage); 3339 report(fault, "INVVPID with unmapped operand raises #PF"); 3340 } 3341 3342 static void try_compat_invvpid(void *unused) 3343 { 3344 struct far_pointer32 fp = { 3345 .offset = (uintptr_t)&&invvpid, 3346 .selector = KERNEL_CS32, 3347 }; 3348 uintptr_t rsp; 3349 3350 asm volatile ("mov %%rsp, %0" : "=r"(rsp)); 3351 3352 TEST_ASSERT_MSG(fp.offset == (uintptr_t)&&invvpid, 3353 "Code address too high."); 3354 TEST_ASSERT_MSG(rsp == (u32)rsp, "Stack address too high."); 3355 3356 asm goto ("lcall *%0" : : "m" (fp) : "rax" : invvpid); 3357 return; 3358 invvpid: 3359 asm volatile (".code32;" 3360 "invvpid (%eax), %eax;" 3361 "lret;" 3362 ".code64"); 3363 __builtin_unreachable(); 3364 } 3365 3366 static void invvpid_test_compatibility_mode(void) 3367 { 3368 bool fault; 3369 3370 fault = test_for_exception(UD_VECTOR, &try_compat_invvpid, NULL); 3371 report(fault, "Compatibility mode INVVPID raises #UD"); 3372 } 3373 3374 static void invvpid_test_not_in_vmx_operation(void) 3375 { 3376 bool fault; 3377 3378 TEST_ASSERT(!vmx_off()); 3379 fault = test_for_exception(UD_VECTOR, &ds_invvpid, NULL); 3380 report(fault, "INVVPID outside of VMX operation raises #UD"); 3381 TEST_ASSERT(!vmx_on()); 3382 } 3383 3384 /* 3385 * This does not test real-address mode, virtual-8086 mode, protected mode, 3386 * or CPL > 0. 3387 */ 3388 static void invvpid_test_v2(void) 3389 { 3390 u64 msr; 3391 int i; 3392 unsigned types = 0; 3393 unsigned type; 3394 3395 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 3396 !(ctrl_cpu_rev[1].clr & CPU_VPID)) 3397 test_skip("VPID not supported"); 3398 3399 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3400 3401 if (!(msr & VPID_CAP_INVVPID)) 3402 test_skip("INVVPID not supported.\n"); 3403 3404 if (msr & VPID_CAP_INVVPID_ADDR) 3405 types |= 1u << INVVPID_ADDR; 3406 if (msr & VPID_CAP_INVVPID_CXTGLB) 3407 types |= 1u << INVVPID_CONTEXT_GLOBAL; 3408 if (msr & VPID_CAP_INVVPID_ALL) 3409 types |= 1u << INVVPID_ALL; 3410 if (msr & VPID_CAP_INVVPID_CXTLOC) 3411 types |= 1u << INVVPID_CONTEXT_LOCAL; 3412 3413 if (!types) 3414 test_skip("No INVVPID types supported.\n"); 3415 3416 for (i = -127; i < 128; i++) 3417 try_invvpid(i, 0xffff, 0); 3418 3419 /* 3420 * VPID must not be more than 16 bits. 3421 */ 3422 for (i = 0; i < 64; i++) 3423 for (type = 0; type < 4; type++) 3424 if (types & (1u << type)) 3425 try_invvpid(type, 1ul << i, 0); 3426 3427 /* 3428 * VPID must not be zero, except for "all contexts." 3429 */ 3430 for (type = 0; type < 4; type++) 3431 if (types & (1u << type)) 3432 try_invvpid(type, 0, 0); 3433 3434 /* 3435 * The gla operand is only validated for single-address INVVPID. 3436 */ 3437 if (types & (1u << INVVPID_ADDR)) 3438 try_invvpid(INVVPID_ADDR, 0xffff, NONCANONICAL); 3439 3440 invvpid_test_gp(); 3441 invvpid_test_ss(); 3442 invvpid_test_pf(); 3443 invvpid_test_compatibility_mode(); 3444 invvpid_test_not_in_vmx_operation(); 3445 } 3446 3447 /* 3448 * Test for early VMLAUNCH failure. Returns true if VMLAUNCH makes it 3449 * at least as far as the guest-state checks. Returns false if the 3450 * VMLAUNCH fails early and execution falls through to the next 3451 * instruction. 3452 */ 3453 static bool vmlaunch_succeeds(void) 3454 { 3455 u32 exit_reason; 3456 3457 /* 3458 * Indirectly set VMX_INST_ERR to 12 ("VMREAD/VMWRITE from/to 3459 * unsupported VMCS component"). The caller can then check 3460 * to see if a failed VM-entry sets VMX_INST_ERR as expected. 3461 */ 3462 vmcs_write(~0u, 0); 3463 3464 vmcs_write(HOST_RIP, (uintptr_t)&&success); 3465 __asm__ __volatile__ goto ("vmwrite %%rsp, %0; vmlaunch" 3466 : 3467 : "r" ((u64)HOST_RSP) 3468 : "cc", "memory" 3469 : success); 3470 return false; 3471 success: 3472 exit_reason = vmcs_read(EXI_REASON); 3473 TEST_ASSERT(exit_reason == (VMX_FAIL_STATE | VMX_ENTRY_FAILURE) || 3474 exit_reason == (VMX_FAIL_MSR | VMX_ENTRY_FAILURE)); 3475 return true; 3476 } 3477 3478 /* 3479 * Try to launch the current VMCS. 3480 */ 3481 static void test_vmx_vmlaunch(u32 xerror) 3482 { 3483 bool success = vmlaunch_succeeds(); 3484 u32 vmx_inst_err; 3485 3486 report(success == !xerror, "vmlaunch %s", 3487 !xerror ? "succeeds" : "fails"); 3488 if (!success && xerror) { 3489 vmx_inst_err = vmcs_read(VMX_INST_ERROR); 3490 report(vmx_inst_err == xerror, 3491 "VMX inst error is %d (actual %d)", xerror, 3492 vmx_inst_err); 3493 } 3494 } 3495 3496 /* 3497 * Try to launch the current VMCS, and expect one of two possible 3498 * errors (or success) codes. 3499 */ 3500 static void test_vmx_vmlaunch2(u32 xerror1, u32 xerror2) 3501 { 3502 bool success = vmlaunch_succeeds(); 3503 u32 vmx_inst_err; 3504 3505 if (!xerror1 == !xerror2) 3506 report(success == !xerror1, "vmlaunch %s", 3507 !xerror1 ? "succeeds" : "fails"); 3508 3509 if (!success && (xerror1 || xerror2)) { 3510 vmx_inst_err = vmcs_read(VMX_INST_ERROR); 3511 report(vmx_inst_err == xerror1 || vmx_inst_err == xerror2, 3512 "VMX inst error is %d or %d (actual %d)", xerror1, 3513 xerror2, vmx_inst_err); 3514 } 3515 } 3516 3517 static void test_vmx_invalid_controls(void) 3518 { 3519 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_CONTROL_FIELD); 3520 } 3521 3522 static void test_vmx_valid_controls(void) 3523 { 3524 test_vmx_vmlaunch(0); 3525 } 3526 3527 /* 3528 * Test a particular value of a VM-execution control bit, if the value 3529 * is required or if the value is zero. 3530 */ 3531 static void test_rsvd_ctl_bit_value(const char *name, union vmx_ctrl_msr msr, 3532 enum Encoding encoding, unsigned bit, 3533 unsigned val) 3534 { 3535 u32 mask = 1u << bit; 3536 bool expected; 3537 u32 controls; 3538 3539 if (msr.set & mask) 3540 TEST_ASSERT(msr.clr & mask); 3541 3542 /* 3543 * We can't arbitrarily turn on a control bit, because it may 3544 * introduce dependencies on other VMCS fields. So, we only 3545 * test turning on bits that have a required setting. 3546 */ 3547 if (val && (msr.clr & mask) && !(msr.set & mask)) 3548 return; 3549 3550 report_prefix_pushf("%s %s bit %d", 3551 val ? "Set" : "Clear", name, bit); 3552 3553 controls = vmcs_read(encoding); 3554 if (val) { 3555 vmcs_write(encoding, msr.set | mask); 3556 expected = (msr.clr & mask); 3557 } else { 3558 vmcs_write(encoding, msr.set & ~mask); 3559 expected = !(msr.set & mask); 3560 } 3561 if (expected) 3562 test_vmx_valid_controls(); 3563 else 3564 test_vmx_invalid_controls(); 3565 vmcs_write(encoding, controls); 3566 report_prefix_pop(); 3567 } 3568 3569 /* 3570 * Test reserved values of a VM-execution control bit, based on the 3571 * allowed bit settings from the corresponding VMX capability MSR. 3572 */ 3573 static void test_rsvd_ctl_bit(const char *name, union vmx_ctrl_msr msr, 3574 enum Encoding encoding, unsigned bit) 3575 { 3576 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 0); 3577 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 1); 3578 } 3579 3580 /* 3581 * Reserved bits in the pin-based VM-execution controls must be set 3582 * properly. Software may consult the VMX capability MSRs to determine 3583 * the proper settings. 3584 * [Intel SDM] 3585 */ 3586 static void test_pin_based_ctls(void) 3587 { 3588 unsigned bit; 3589 3590 printf("%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PIN" : 3591 "MSR_IA32_VMX_PINBASED_CTLS", ctrl_pin_rev.val); 3592 for (bit = 0; bit < 32; bit++) 3593 test_rsvd_ctl_bit("pin-based controls", 3594 ctrl_pin_rev, PIN_CONTROLS, bit); 3595 } 3596 3597 /* 3598 * Reserved bits in the primary processor-based VM-execution controls 3599 * must be set properly. Software may consult the VMX capability MSRs 3600 * to determine the proper settings. 3601 * [Intel SDM] 3602 */ 3603 static void test_primary_processor_based_ctls(void) 3604 { 3605 unsigned bit; 3606 3607 printf("\n%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PROC" : 3608 "MSR_IA32_VMX_PROCBASED_CTLS", ctrl_cpu_rev[0].val); 3609 for (bit = 0; bit < 32; bit++) 3610 test_rsvd_ctl_bit("primary processor-based controls", 3611 ctrl_cpu_rev[0], CPU_EXEC_CTRL0, bit); 3612 } 3613 3614 /* 3615 * If the "activate secondary controls" primary processor-based 3616 * VM-execution control is 1, reserved bits in the secondary 3617 * processor-based VM-execution controls must be cleared. Software may 3618 * consult the VMX capability MSRs to determine which bits are 3619 * reserved. 3620 * If the "activate secondary controls" primary processor-based 3621 * VM-execution control is 0 (or if the processor does not support the 3622 * 1-setting of that control), no checks are performed on the 3623 * secondary processor-based VM-execution controls. 3624 * [Intel SDM] 3625 */ 3626 static void test_secondary_processor_based_ctls(void) 3627 { 3628 u32 primary; 3629 u32 secondary; 3630 unsigned bit; 3631 3632 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) 3633 return; 3634 3635 primary = vmcs_read(CPU_EXEC_CTRL0); 3636 secondary = vmcs_read(CPU_EXEC_CTRL1); 3637 3638 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3639 printf("\nMSR_IA32_VMX_PROCBASED_CTLS2: %lx\n", ctrl_cpu_rev[1].val); 3640 for (bit = 0; bit < 32; bit++) 3641 test_rsvd_ctl_bit("secondary processor-based controls", 3642 ctrl_cpu_rev[1], CPU_EXEC_CTRL1, bit); 3643 3644 /* 3645 * When the "activate secondary controls" VM-execution control 3646 * is clear, there are no checks on the secondary controls. 3647 */ 3648 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3649 vmcs_write(CPU_EXEC_CTRL1, ~0); 3650 report(vmlaunch_succeeds(), 3651 "Secondary processor-based controls ignored"); 3652 vmcs_write(CPU_EXEC_CTRL1, secondary); 3653 vmcs_write(CPU_EXEC_CTRL0, primary); 3654 } 3655 3656 static void try_cr3_target_count(unsigned i, unsigned max) 3657 { 3658 report_prefix_pushf("CR3 target count 0x%x", i); 3659 vmcs_write(CR3_TARGET_COUNT, i); 3660 if (i <= max) 3661 test_vmx_valid_controls(); 3662 else 3663 test_vmx_invalid_controls(); 3664 report_prefix_pop(); 3665 } 3666 3667 /* 3668 * The CR3-target count must not be greater than 4. Future processors 3669 * may support a different number of CR3-target values. Software 3670 * should read the VMX capability MSR IA32_VMX_MISC to determine the 3671 * number of values supported. 3672 * [Intel SDM] 3673 */ 3674 static void test_cr3_targets(void) 3675 { 3676 unsigned supported_targets = (rdmsr(MSR_IA32_VMX_MISC) >> 16) & 0x1ff; 3677 u32 cr3_targets = vmcs_read(CR3_TARGET_COUNT); 3678 unsigned i; 3679 3680 printf("\nSupported CR3 targets: %d\n", supported_targets); 3681 TEST_ASSERT(supported_targets <= 256); 3682 3683 try_cr3_target_count(-1u, supported_targets); 3684 try_cr3_target_count(0x80000000, supported_targets); 3685 try_cr3_target_count(0x7fffffff, supported_targets); 3686 for (i = 0; i <= supported_targets + 1; i++) 3687 try_cr3_target_count(i, supported_targets); 3688 vmcs_write(CR3_TARGET_COUNT, cr3_targets); 3689 3690 /* VMWRITE to nonexistent target fields should fail. */ 3691 for (i = supported_targets; i < 256; i++) 3692 TEST_ASSERT(vmcs_write(CR3_TARGET_0 + i*2, 0)); 3693 } 3694 3695 /* 3696 * Test a particular address setting in the VMCS 3697 */ 3698 static void test_vmcs_addr(const char *name, 3699 enum Encoding encoding, 3700 u64 align, 3701 bool ignored, 3702 bool skip_beyond_mapped_ram, 3703 u64 addr) 3704 { 3705 report_prefix_pushf("%s = %lx", name, addr); 3706 vmcs_write(encoding, addr); 3707 if (skip_beyond_mapped_ram && 3708 addr > fwcfg_get_u64(FW_CFG_RAM_SIZE) - align && 3709 addr < (1ul << cpuid_maxphyaddr())) 3710 printf("Skipping physical address beyond mapped RAM\n"); 3711 else if (ignored || (IS_ALIGNED(addr, align) && 3712 addr < (1ul << cpuid_maxphyaddr()))) 3713 test_vmx_valid_controls(); 3714 else 3715 test_vmx_invalid_controls(); 3716 report_prefix_pop(); 3717 } 3718 3719 /* 3720 * Test interesting values for a VMCS address 3721 */ 3722 static void test_vmcs_addr_values(const char *name, 3723 enum Encoding encoding, 3724 u64 align, 3725 bool ignored, 3726 bool skip_beyond_mapped_ram, 3727 u32 bit_start, u32 bit_end) 3728 { 3729 unsigned i; 3730 u64 orig_val = vmcs_read(encoding); 3731 3732 for (i = bit_start; i <= bit_end; i++) 3733 test_vmcs_addr(name, encoding, align, ignored, 3734 skip_beyond_mapped_ram, 1ul << i); 3735 3736 test_vmcs_addr(name, encoding, align, ignored, 3737 skip_beyond_mapped_ram, PAGE_SIZE - 1); 3738 test_vmcs_addr(name, encoding, align, ignored, 3739 skip_beyond_mapped_ram, PAGE_SIZE); 3740 test_vmcs_addr(name, encoding, align, ignored, 3741 skip_beyond_mapped_ram, 3742 (1ul << cpuid_maxphyaddr()) - PAGE_SIZE); 3743 test_vmcs_addr(name, encoding, align, ignored, 3744 skip_beyond_mapped_ram, -1ul); 3745 3746 vmcs_write(encoding, orig_val); 3747 } 3748 3749 /* 3750 * Test a physical address reference in the VMCS, when the corresponding 3751 * feature is enabled and when the corresponding feature is disabled. 3752 */ 3753 static void test_vmcs_addr_reference(u32 control_bit, enum Encoding field, 3754 const char *field_name, 3755 const char *control_name, u64 align, 3756 bool skip_beyond_mapped_ram, 3757 bool control_primary) 3758 { 3759 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 3760 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 3761 u64 page_addr; 3762 3763 if (control_primary) { 3764 if (!(ctrl_cpu_rev[0].clr & control_bit)) 3765 return; 3766 } else { 3767 if (!(ctrl_cpu_rev[1].clr & control_bit)) 3768 return; 3769 } 3770 3771 page_addr = vmcs_read(field); 3772 3773 report_prefix_pushf("%s enabled", control_name); 3774 if (control_primary) { 3775 vmcs_write(CPU_EXEC_CTRL0, primary | control_bit); 3776 } else { 3777 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3778 vmcs_write(CPU_EXEC_CTRL1, secondary | control_bit); 3779 } 3780 3781 test_vmcs_addr_values(field_name, field, align, false, 3782 skip_beyond_mapped_ram, 0, 63); 3783 report_prefix_pop(); 3784 3785 report_prefix_pushf("%s disabled", control_name); 3786 if (control_primary) { 3787 vmcs_write(CPU_EXEC_CTRL0, primary & ~control_bit); 3788 } else { 3789 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3790 vmcs_write(CPU_EXEC_CTRL1, secondary & ~control_bit); 3791 } 3792 3793 test_vmcs_addr_values(field_name, field, align, true, false, 0, 63); 3794 report_prefix_pop(); 3795 3796 vmcs_write(field, page_addr); 3797 vmcs_write(CPU_EXEC_CTRL0, primary); 3798 vmcs_write(CPU_EXEC_CTRL1, secondary); 3799 } 3800 3801 /* 3802 * If the "use I/O bitmaps" VM-execution control is 1, bits 11:0 of 3803 * each I/O-bitmap address must be 0. Neither address should set any 3804 * bits beyond the processor's physical-address width. 3805 * [Intel SDM] 3806 */ 3807 static void test_io_bitmaps(void) 3808 { 3809 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_A, 3810 "I/O bitmap A", "Use I/O bitmaps", 3811 PAGE_SIZE, false, true); 3812 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_B, 3813 "I/O bitmap B", "Use I/O bitmaps", 3814 PAGE_SIZE, false, true); 3815 } 3816 3817 /* 3818 * If the "use MSR bitmaps" VM-execution control is 1, bits 11:0 of 3819 * the MSR-bitmap address must be 0. The address should not set any 3820 * bits beyond the processor's physical-address width. 3821 * [Intel SDM] 3822 */ 3823 static void test_msr_bitmap(void) 3824 { 3825 test_vmcs_addr_reference(CPU_MSR_BITMAP, MSR_BITMAP, 3826 "MSR bitmap", "Use MSR bitmaps", 3827 PAGE_SIZE, false, true); 3828 } 3829 3830 /* 3831 * If the "use TPR shadow" VM-execution control is 1, the virtual-APIC 3832 * address must satisfy the following checks: 3833 * - Bits 11:0 of the address must be 0. 3834 * - The address should not set any bits beyond the processor's 3835 * physical-address width. 3836 * [Intel SDM] 3837 */ 3838 static void test_apic_virt_addr(void) 3839 { 3840 /* 3841 * Ensure the processor will never use the virtual-APIC page, since 3842 * we will point it to invalid RAM. Otherwise KVM is puzzled about 3843 * what we're trying to achieve and fails vmentry. 3844 */ 3845 u32 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 3846 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0 | CPU_CR8_LOAD | CPU_CR8_STORE); 3847 test_vmcs_addr_reference(CPU_TPR_SHADOW, APIC_VIRT_ADDR, 3848 "virtual-APIC address", "Use TPR shadow", 3849 PAGE_SIZE, false, true); 3850 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 3851 } 3852 3853 /* 3854 * If the "virtualize APIC-accesses" VM-execution control is 1, the 3855 * APIC-access address must satisfy the following checks: 3856 * - Bits 11:0 of the address must be 0. 3857 * - The address should not set any bits beyond the processor's 3858 * physical-address width. 3859 * [Intel SDM] 3860 */ 3861 static void test_apic_access_addr(void) 3862 { 3863 void *apic_access_page = alloc_page(); 3864 3865 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_page)); 3866 3867 test_vmcs_addr_reference(CPU_VIRT_APIC_ACCESSES, APIC_ACCS_ADDR, 3868 "APIC-access address", 3869 "virtualize APIC-accesses", PAGE_SIZE, 3870 true, false); 3871 } 3872 3873 static bool set_bit_pattern(u8 mask, u32 *secondary) 3874 { 3875 u8 i; 3876 bool flag = false; 3877 u32 test_bits[3] = { 3878 CPU_VIRT_X2APIC, 3879 CPU_APIC_REG_VIRT, 3880 CPU_VINTD 3881 }; 3882 3883 for (i = 0; i < ARRAY_SIZE(test_bits); i++) { 3884 if ((mask & (1u << i)) && 3885 (ctrl_cpu_rev[1].clr & test_bits[i])) { 3886 *secondary |= test_bits[i]; 3887 flag = true; 3888 } 3889 } 3890 3891 return (flag); 3892 } 3893 3894 /* 3895 * If the "use TPR shadow" VM-execution control is 0, the following 3896 * VM-execution controls must also be 0: 3897 * - virtualize x2APIC mode 3898 * - APIC-register virtualization 3899 * - virtual-interrupt delivery 3900 * [Intel SDM] 3901 * 3902 * 2. If the "virtualize x2APIC mode" VM-execution control is 1, the 3903 * "virtualize APIC accesses" VM-execution control must be 0. 3904 * [Intel SDM] 3905 */ 3906 static void test_apic_virtual_ctls(void) 3907 { 3908 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3909 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3910 u32 primary = saved_primary; 3911 u32 secondary = saved_secondary; 3912 bool ctrl = false; 3913 char str[10] = "disabled"; 3914 u8 i = 0, j; 3915 3916 /* 3917 * First test 3918 */ 3919 if (!((ctrl_cpu_rev[0].clr & (CPU_SECONDARY | CPU_TPR_SHADOW)) == 3920 (CPU_SECONDARY | CPU_TPR_SHADOW))) 3921 return; 3922 3923 primary |= CPU_SECONDARY; 3924 primary &= ~CPU_TPR_SHADOW; 3925 vmcs_write(CPU_EXEC_CTRL0, primary); 3926 3927 while (1) { 3928 for (j = 1; j < 8; j++) { 3929 secondary &= ~(CPU_VIRT_X2APIC | CPU_APIC_REG_VIRT | CPU_VINTD); 3930 if (primary & CPU_TPR_SHADOW) { 3931 ctrl = true; 3932 } else { 3933 if (! set_bit_pattern(j, &secondary)) 3934 ctrl = true; 3935 else 3936 ctrl = false; 3937 } 3938 3939 vmcs_write(CPU_EXEC_CTRL1, secondary); 3940 report_prefix_pushf("Use TPR shadow %s, virtualize x2APIC mode %s, APIC-register virtualization %s, virtual-interrupt delivery %s", 3941 str, (secondary & CPU_VIRT_X2APIC) ? "enabled" : "disabled", (secondary & CPU_APIC_REG_VIRT) ? "enabled" : "disabled", (secondary & CPU_VINTD) ? "enabled" : "disabled"); 3942 if (ctrl) 3943 test_vmx_valid_controls(); 3944 else 3945 test_vmx_invalid_controls(); 3946 report_prefix_pop(); 3947 } 3948 3949 if (i == 1) 3950 break; 3951 i++; 3952 3953 primary |= CPU_TPR_SHADOW; 3954 vmcs_write(CPU_EXEC_CTRL0, primary); 3955 strcpy(str, "enabled"); 3956 } 3957 3958 /* 3959 * Second test 3960 */ 3961 u32 apic_virt_ctls = (CPU_VIRT_X2APIC | CPU_VIRT_APIC_ACCESSES); 3962 3963 primary = saved_primary; 3964 secondary = saved_secondary; 3965 if (!((ctrl_cpu_rev[1].clr & apic_virt_ctls) == apic_virt_ctls)) 3966 return; 3967 3968 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3969 secondary &= ~CPU_VIRT_APIC_ACCESSES; 3970 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_X2APIC); 3971 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access disabled"); 3972 test_vmx_valid_controls(); 3973 report_prefix_pop(); 3974 3975 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_APIC_ACCESSES); 3976 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access enabled"); 3977 test_vmx_valid_controls(); 3978 report_prefix_pop(); 3979 3980 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_X2APIC); 3981 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access enabled"); 3982 test_vmx_invalid_controls(); 3983 report_prefix_pop(); 3984 3985 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_APIC_ACCESSES); 3986 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access disabled"); 3987 test_vmx_valid_controls(); 3988 report_prefix_pop(); 3989 3990 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3991 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3992 } 3993 3994 /* 3995 * If the "virtual-interrupt delivery" VM-execution control is 1, the 3996 * "external-interrupt exiting" VM-execution control must be 1. 3997 * [Intel SDM] 3998 */ 3999 static void test_virtual_intr_ctls(void) 4000 { 4001 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 4002 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 4003 u32 saved_pin = vmcs_read(PIN_CONTROLS); 4004 u32 primary = saved_primary; 4005 u32 secondary = saved_secondary; 4006 u32 pin = saved_pin; 4007 4008 if (!((ctrl_cpu_rev[1].clr & CPU_VINTD) && 4009 (ctrl_pin_rev.clr & PIN_EXTINT))) 4010 return; 4011 4012 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 4013 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VINTD); 4014 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 4015 report_prefix_pushf("Virtualize interrupt-delivery disabled; external-interrupt exiting disabled"); 4016 test_vmx_valid_controls(); 4017 report_prefix_pop(); 4018 4019 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VINTD); 4020 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 4021 test_vmx_invalid_controls(); 4022 report_prefix_pop(); 4023 4024 vmcs_write(PIN_CONTROLS, pin | PIN_EXTINT); 4025 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting enabled"); 4026 test_vmx_valid_controls(); 4027 report_prefix_pop(); 4028 4029 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 4030 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 4031 test_vmx_invalid_controls(); 4032 report_prefix_pop(); 4033 4034 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 4035 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 4036 vmcs_write(PIN_CONTROLS, saved_pin); 4037 } 4038 4039 static void test_pi_desc_addr(u64 addr, bool ctrl) 4040 { 4041 vmcs_write(POSTED_INTR_DESC_ADDR, addr); 4042 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-descriptor-address 0x%lx", addr); 4043 if (ctrl) 4044 test_vmx_valid_controls(); 4045 else 4046 test_vmx_invalid_controls(); 4047 report_prefix_pop(); 4048 } 4049 4050 /* 4051 * If the "process posted interrupts" VM-execution control is 1, the 4052 * following must be true: 4053 * 4054 * - The "virtual-interrupt delivery" VM-execution control is 1. 4055 * - The "acknowledge interrupt on exit" VM-exit control is 1. 4056 * - The posted-interrupt notification vector has a value in the 4057 * - range 0 - 255 (bits 15:8 are all 0). 4058 * - Bits 5:0 of the posted-interrupt descriptor address are all 0. 4059 * - The posted-interrupt descriptor address does not set any bits 4060 * beyond the processor's physical-address width. 4061 * [Intel SDM] 4062 */ 4063 static void test_posted_intr(void) 4064 { 4065 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 4066 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 4067 u32 saved_pin = vmcs_read(PIN_CONTROLS); 4068 u32 exit_ctl_saved = vmcs_read(EXI_CONTROLS); 4069 u32 primary = saved_primary; 4070 u32 secondary = saved_secondary; 4071 u32 pin = saved_pin; 4072 u32 exit_ctl = exit_ctl_saved; 4073 u16 vec; 4074 int i; 4075 4076 if (!((ctrl_pin_rev.clr & PIN_POST_INTR) && 4077 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 4078 (ctrl_exit_rev.clr & EXI_INTA))) 4079 return; 4080 4081 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 4082 4083 /* 4084 * Test virtual-interrupt-delivery and acknowledge-interrupt-on-exit 4085 */ 4086 pin |= PIN_POST_INTR; 4087 vmcs_write(PIN_CONTROLS, pin); 4088 secondary &= ~CPU_VINTD; 4089 vmcs_write(CPU_EXEC_CTRL1, secondary); 4090 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled"); 4091 test_vmx_invalid_controls(); 4092 report_prefix_pop(); 4093 4094 secondary |= CPU_VINTD; 4095 vmcs_write(CPU_EXEC_CTRL1, secondary); 4096 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled"); 4097 test_vmx_invalid_controls(); 4098 report_prefix_pop(); 4099 4100 exit_ctl &= ~EXI_INTA; 4101 vmcs_write(EXI_CONTROLS, exit_ctl); 4102 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit disabled"); 4103 test_vmx_invalid_controls(); 4104 report_prefix_pop(); 4105 4106 exit_ctl |= EXI_INTA; 4107 vmcs_write(EXI_CONTROLS, exit_ctl); 4108 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 4109 test_vmx_valid_controls(); 4110 report_prefix_pop(); 4111 4112 secondary &= ~CPU_VINTD; 4113 vmcs_write(CPU_EXEC_CTRL1, secondary); 4114 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled; acknowledge-interrupt-on-exit enabled"); 4115 test_vmx_invalid_controls(); 4116 report_prefix_pop(); 4117 4118 secondary |= CPU_VINTD; 4119 vmcs_write(CPU_EXEC_CTRL1, secondary); 4120 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 4121 test_vmx_valid_controls(); 4122 report_prefix_pop(); 4123 4124 /* 4125 * Test posted-interrupt notification vector 4126 */ 4127 for (i = 0; i < 8; i++) { 4128 vec = (1ul << i); 4129 vmcs_write(PINV, vec); 4130 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 4131 test_vmx_valid_controls(); 4132 report_prefix_pop(); 4133 } 4134 for (i = 8; i < 16; i++) { 4135 vec = (1ul << i); 4136 vmcs_write(PINV, vec); 4137 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 4138 test_vmx_invalid_controls(); 4139 report_prefix_pop(); 4140 } 4141 4142 vec &= ~(0xff << 8); 4143 vmcs_write(PINV, vec); 4144 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 4145 test_vmx_valid_controls(); 4146 report_prefix_pop(); 4147 4148 /* 4149 * Test posted-interrupt descriptor addresss 4150 */ 4151 for (i = 0; i < 6; i++) { 4152 test_pi_desc_addr(1ul << i, false); 4153 } 4154 4155 test_pi_desc_addr(0xf0, false); 4156 test_pi_desc_addr(0xff, false); 4157 test_pi_desc_addr(0x0f, false); 4158 test_pi_desc_addr(0x8000, true); 4159 test_pi_desc_addr(0x00, true); 4160 test_pi_desc_addr(0xc000, true); 4161 4162 test_vmcs_addr_values("process-posted interrupts", 4163 POSTED_INTR_DESC_ADDR, 64, 4164 false, false, 0, 63); 4165 4166 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 4167 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 4168 vmcs_write(PIN_CONTROLS, saved_pin); 4169 } 4170 4171 static void test_apic_ctls(void) 4172 { 4173 test_apic_virt_addr(); 4174 test_apic_access_addr(); 4175 test_apic_virtual_ctls(); 4176 test_virtual_intr_ctls(); 4177 test_posted_intr(); 4178 } 4179 4180 /* 4181 * If the "enable VPID" VM-execution control is 1, the value of the 4182 * of the VPID VM-execution control field must not be 0000H. 4183 * [Intel SDM] 4184 */ 4185 static void test_vpid(void) 4186 { 4187 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 4188 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 4189 u16 vpid = 0x0000; 4190 int i; 4191 4192 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4193 (ctrl_cpu_rev[1].clr & CPU_VPID))) { 4194 printf("Secondary controls and/or VPID not supported\n"); 4195 return; 4196 } 4197 4198 vmcs_write(CPU_EXEC_CTRL0, saved_primary | CPU_SECONDARY); 4199 vmcs_write(CPU_EXEC_CTRL1, saved_secondary & ~CPU_VPID); 4200 vmcs_write(VPID, vpid); 4201 report_prefix_pushf("VPID disabled; VPID value %x", vpid); 4202 test_vmx_valid_controls(); 4203 report_prefix_pop(); 4204 4205 vmcs_write(CPU_EXEC_CTRL1, saved_secondary | CPU_VPID); 4206 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 4207 test_vmx_invalid_controls(); 4208 report_prefix_pop(); 4209 4210 for (i = 0; i < 16; i++) { 4211 vpid = (short)1 << i;; 4212 vmcs_write(VPID, vpid); 4213 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 4214 test_vmx_valid_controls(); 4215 report_prefix_pop(); 4216 } 4217 4218 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 4219 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 4220 } 4221 4222 static void set_vtpr(unsigned vtpr) 4223 { 4224 *(u32 *)phys_to_virt(vmcs_read(APIC_VIRT_ADDR) + APIC_TASKPRI) = vtpr; 4225 } 4226 4227 static void try_tpr_threshold_and_vtpr(unsigned threshold, unsigned vtpr) 4228 { 4229 bool valid = true; 4230 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4231 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4232 4233 if ((primary & CPU_TPR_SHADOW) && 4234 (!(primary & CPU_SECONDARY) || 4235 !(secondary & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 4236 valid = (threshold & 0xf) <= ((vtpr >> 4) & 0xf); 4237 4238 set_vtpr(vtpr); 4239 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0x%x", 4240 threshold, (vtpr >> 4) & 0xf); 4241 if (valid) 4242 test_vmx_valid_controls(); 4243 else 4244 test_vmx_invalid_controls(); 4245 report_prefix_pop(); 4246 } 4247 4248 static void test_invalid_event_injection(void) 4249 { 4250 u32 ent_intr_info_save = vmcs_read(ENT_INTR_INFO); 4251 u32 ent_intr_error_save = vmcs_read(ENT_INTR_ERROR); 4252 u32 ent_inst_len_save = vmcs_read(ENT_INST_LEN); 4253 u32 primary_save = vmcs_read(CPU_EXEC_CTRL0); 4254 u32 secondary_save = vmcs_read(CPU_EXEC_CTRL1); 4255 u64 guest_cr0_save = vmcs_read(GUEST_CR0); 4256 u32 ent_intr_info_base = INTR_INFO_VALID_MASK; 4257 u32 ent_intr_info, ent_intr_err, ent_intr_len; 4258 u32 cnt; 4259 4260 /* Setup */ 4261 report_prefix_push("invalid event injection"); 4262 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4263 vmcs_write(ENT_INST_LEN, 0x00000001); 4264 4265 /* The field's interruption type is not set to a reserved value. */ 4266 ent_intr_info = ent_intr_info_base | INTR_TYPE_RESERVED | DE_VECTOR; 4267 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4268 "RESERVED interruption type invalid [-]", 4269 ent_intr_info); 4270 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4271 test_vmx_invalid_controls(); 4272 report_prefix_pop(); 4273 4274 ent_intr_info = ent_intr_info_base | INTR_TYPE_EXT_INTR | 4275 DE_VECTOR; 4276 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4277 "RESERVED interruption type invalid [+]", 4278 ent_intr_info); 4279 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4280 test_vmx_valid_controls(); 4281 report_prefix_pop(); 4282 4283 /* If the interruption type is other event, the vector is 0. */ 4284 ent_intr_info = ent_intr_info_base | INTR_TYPE_OTHER_EVENT | DB_VECTOR; 4285 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4286 "(OTHER EVENT && vector != 0) invalid [-]", 4287 ent_intr_info); 4288 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4289 test_vmx_invalid_controls(); 4290 report_prefix_pop(); 4291 4292 /* If the interruption type is NMI, the vector is 2 (negative case). */ 4293 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | DE_VECTOR; 4294 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4295 "(NMI && vector != 2) invalid [-]", ent_intr_info); 4296 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4297 test_vmx_invalid_controls(); 4298 report_prefix_pop(); 4299 4300 /* If the interruption type is NMI, the vector is 2 (positive case). */ 4301 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | NMI_VECTOR; 4302 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4303 "(NMI && vector == 2) valid [+]", ent_intr_info); 4304 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4305 test_vmx_valid_controls(); 4306 report_prefix_pop(); 4307 4308 /* 4309 * If the interruption type 4310 * is HW exception, the vector is at most 31. 4311 */ 4312 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 0x20; 4313 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4314 "(HW exception && vector > 31) invalid [-]", 4315 ent_intr_info); 4316 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4317 test_vmx_invalid_controls(); 4318 report_prefix_pop(); 4319 4320 /* 4321 * deliver-error-code is 1 iff either 4322 * (a) the "unrestricted guest" VM-execution control is 0 4323 * (b) CR0.PE is set. 4324 */ 4325 4326 /* Assert that unrestricted guest is disabled or unsupported */ 4327 assert(!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 4328 !(secondary_save & CPU_URG)); 4329 4330 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4331 GP_VECTOR; 4332 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4333 "error code <-> (!URG || prot_mode) [-]", 4334 ent_intr_info); 4335 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4336 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4337 test_vmx_invalid_controls(); 4338 report_prefix_pop(); 4339 4340 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4341 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4342 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4343 "error code <-> (!URG || prot_mode) [+]", 4344 ent_intr_info); 4345 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4346 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4347 test_vmx_valid_controls(); 4348 report_prefix_pop(); 4349 4350 if (enable_unrestricted_guest(false)) 4351 goto skip_unrestricted_guest; 4352 4353 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4354 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4355 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4356 "error code <-> (!URG || prot_mode) [-]", 4357 ent_intr_info); 4358 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4359 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4360 test_vmx_invalid_controls(); 4361 report_prefix_pop(); 4362 4363 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4364 GP_VECTOR; 4365 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4366 "error code <-> (!URG || prot_mode) [-]", 4367 ent_intr_info); 4368 vmcs_write(GUEST_CR0, guest_cr0_save | X86_CR0_PE); 4369 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4370 test_vmx_invalid_controls(); 4371 report_prefix_pop(); 4372 4373 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4374 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4375 4376 skip_unrestricted_guest: 4377 vmcs_write(GUEST_CR0, guest_cr0_save); 4378 4379 /* deliver-error-code is 1 iff the interruption type is HW exception */ 4380 report_prefix_push("error code <-> HW exception"); 4381 for (cnt = 0; cnt < 8; cnt++) { 4382 u32 exception_type_mask = cnt << 8; 4383 u32 deliver_error_code_mask = 4384 exception_type_mask != INTR_TYPE_HARD_EXCEPTION ? 4385 INTR_INFO_DELIVER_CODE_MASK : 0; 4386 4387 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4388 exception_type_mask | GP_VECTOR; 4389 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4390 ent_intr_info); 4391 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4392 test_vmx_invalid_controls(); 4393 report_prefix_pop(); 4394 } 4395 report_prefix_pop(); 4396 4397 /* 4398 * deliver-error-code is 1 iff the the vector 4399 * indicates an exception that would normally deliver an error code 4400 */ 4401 report_prefix_push("error code <-> vector delivers error code"); 4402 for (cnt = 0; cnt < 32; cnt++) { 4403 bool has_error_code = false; 4404 u32 deliver_error_code_mask; 4405 4406 switch (cnt) { 4407 case DF_VECTOR: 4408 case TS_VECTOR: 4409 case NP_VECTOR: 4410 case SS_VECTOR: 4411 case GP_VECTOR: 4412 case PF_VECTOR: 4413 case AC_VECTOR: 4414 has_error_code = true; 4415 case CP_VECTOR: 4416 /* Some CPUs have error code and some do not, skip */ 4417 continue; 4418 } 4419 4420 /* Negative case */ 4421 deliver_error_code_mask = has_error_code ? 4422 0 : 4423 INTR_INFO_DELIVER_CODE_MASK; 4424 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4425 INTR_TYPE_HARD_EXCEPTION | cnt; 4426 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4427 ent_intr_info); 4428 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4429 test_vmx_invalid_controls(); 4430 report_prefix_pop(); 4431 4432 /* Positive case */ 4433 deliver_error_code_mask = has_error_code ? 4434 INTR_INFO_DELIVER_CODE_MASK : 4435 0; 4436 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4437 INTR_TYPE_HARD_EXCEPTION | cnt; 4438 report_prefix_pushf("VM-entry intr info=0x%x [+]", 4439 ent_intr_info); 4440 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4441 test_vmx_valid_controls(); 4442 report_prefix_pop(); 4443 } 4444 report_prefix_pop(); 4445 4446 /* Reserved bits in the field (30:12) are 0. */ 4447 report_prefix_push("reserved bits clear"); 4448 for (cnt = 12; cnt <= 30; cnt++) { 4449 ent_intr_info = ent_intr_info_base | 4450 INTR_INFO_DELIVER_CODE_MASK | 4451 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR | 4452 (1U << cnt); 4453 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4454 ent_intr_info); 4455 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4456 test_vmx_invalid_controls(); 4457 report_prefix_pop(); 4458 } 4459 report_prefix_pop(); 4460 4461 /* 4462 * If deliver-error-code is 1 4463 * bits 31:16 of the VM-entry exception error-code field are 0. 4464 */ 4465 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4466 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4467 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4468 "VM-entry exception error code[31:16] clear", 4469 ent_intr_info); 4470 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4471 for (cnt = 16; cnt <= 31; cnt++) { 4472 ent_intr_err = 1U << cnt; 4473 report_prefix_pushf("VM-entry intr error=0x%x [-]", 4474 ent_intr_err); 4475 vmcs_write(ENT_INTR_ERROR, ent_intr_err); 4476 test_vmx_invalid_controls(); 4477 report_prefix_pop(); 4478 } 4479 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4480 report_prefix_pop(); 4481 4482 /* 4483 * If the interruption type is software interrupt, software exception, 4484 * or privileged software exception, the VM-entry instruction-length 4485 * field is in the range 0 - 15. 4486 */ 4487 4488 for (cnt = 0; cnt < 3; cnt++) { 4489 switch (cnt) { 4490 case 0: 4491 ent_intr_info = ent_intr_info_base | 4492 INTR_TYPE_SOFT_INTR; 4493 break; 4494 case 1: 4495 ent_intr_info = ent_intr_info_base | 4496 INTR_TYPE_SOFT_EXCEPTION; 4497 break; 4498 case 2: 4499 ent_intr_info = ent_intr_info_base | 4500 INTR_TYPE_PRIV_SW_EXCEPTION; 4501 break; 4502 } 4503 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4504 "VM-entry instruction-length check", 4505 ent_intr_info); 4506 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4507 4508 /* Instruction length set to -1 (0xFFFFFFFF) should fail */ 4509 ent_intr_len = -1; 4510 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4511 ent_intr_len); 4512 vmcs_write(ENT_INST_LEN, ent_intr_len); 4513 test_vmx_invalid_controls(); 4514 report_prefix_pop(); 4515 4516 /* Instruction length set to 16 should fail */ 4517 ent_intr_len = 0x00000010; 4518 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4519 ent_intr_len); 4520 vmcs_write(ENT_INST_LEN, 0x00000010); 4521 test_vmx_invalid_controls(); 4522 report_prefix_pop(); 4523 4524 report_prefix_pop(); 4525 } 4526 4527 /* Cleanup */ 4528 vmcs_write(ENT_INTR_INFO, ent_intr_info_save); 4529 vmcs_write(ENT_INTR_ERROR, ent_intr_error_save); 4530 vmcs_write(ENT_INST_LEN, ent_inst_len_save); 4531 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4532 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4533 vmcs_write(GUEST_CR0, guest_cr0_save); 4534 report_prefix_pop(); 4535 } 4536 4537 /* 4538 * Test interesting vTPR values for a given TPR threshold. 4539 */ 4540 static void test_vtpr_values(unsigned threshold) 4541 { 4542 try_tpr_threshold_and_vtpr(threshold, (threshold - 1) << 4); 4543 try_tpr_threshold_and_vtpr(threshold, threshold << 4); 4544 try_tpr_threshold_and_vtpr(threshold, (threshold + 1) << 4); 4545 } 4546 4547 static void try_tpr_threshold(unsigned threshold) 4548 { 4549 bool valid = true; 4550 4551 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4552 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4553 4554 if ((primary & CPU_TPR_SHADOW) && !((primary & CPU_SECONDARY) && 4555 (secondary & CPU_VINTD))) 4556 valid = !(threshold >> 4); 4557 4558 set_vtpr(-1); 4559 vmcs_write(TPR_THRESHOLD, threshold); 4560 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0xf", threshold); 4561 if (valid) 4562 test_vmx_valid_controls(); 4563 else 4564 test_vmx_invalid_controls(); 4565 report_prefix_pop(); 4566 4567 if (valid) 4568 test_vtpr_values(threshold); 4569 } 4570 4571 /* 4572 * Test interesting TPR threshold values. 4573 */ 4574 static void test_tpr_threshold_values(void) 4575 { 4576 unsigned i; 4577 4578 for (i = 0; i < 0x10; i++) 4579 try_tpr_threshold(i); 4580 for (i = 4; i < 32; i++) 4581 try_tpr_threshold(1u << i); 4582 try_tpr_threshold(-1u); 4583 try_tpr_threshold(0x7fffffff); 4584 } 4585 4586 /* 4587 * This test covers the following two VM entry checks: 4588 * 4589 * i) If the "use TPR shadow" VM-execution control is 1 and the 4590 * "virtual-interrupt delivery" VM-execution control is 0, bits 4591 * 31:4 of the TPR threshold VM-execution control field must 4592 be 0. 4593 * [Intel SDM] 4594 * 4595 * ii) If the "use TPR shadow" VM-execution control is 1, the 4596 * "virtual-interrupt delivery" VM-execution control is 0 4597 * and the "virtualize APIC accesses" VM-execution control 4598 * is 0, the value of bits 3:0 of the TPR threshold VM-execution 4599 * control field must not be greater than the value of bits 4600 * 7:4 of VTPR. 4601 * [Intel SDM] 4602 */ 4603 static void test_tpr_threshold(void) 4604 { 4605 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4606 u64 apic_virt_addr = vmcs_read(APIC_VIRT_ADDR); 4607 u64 threshold = vmcs_read(TPR_THRESHOLD); 4608 void *virtual_apic_page; 4609 4610 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) 4611 return; 4612 4613 virtual_apic_page = alloc_page(); 4614 memset(virtual_apic_page, 0xff, PAGE_SIZE); 4615 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 4616 4617 vmcs_write(CPU_EXEC_CTRL0, primary & ~(CPU_TPR_SHADOW | CPU_SECONDARY)); 4618 report_prefix_pushf("Use TPR shadow disabled, secondary controls disabled"); 4619 test_tpr_threshold_values(); 4620 report_prefix_pop(); 4621 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_TPR_SHADOW); 4622 report_prefix_pushf("Use TPR shadow enabled, secondary controls disabled"); 4623 test_tpr_threshold_values(); 4624 report_prefix_pop(); 4625 4626 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4627 (ctrl_cpu_rev[1].clr & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 4628 goto out; 4629 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4630 4631 if (ctrl_cpu_rev[1].clr & CPU_VINTD) { 4632 vmcs_write(CPU_EXEC_CTRL1, CPU_VINTD); 4633 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4634 test_tpr_threshold_values(); 4635 report_prefix_pop(); 4636 4637 vmcs_write(CPU_EXEC_CTRL0, 4638 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4639 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4640 test_tpr_threshold_values(); 4641 report_prefix_pop(); 4642 } 4643 4644 if (ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES) { 4645 vmcs_write(CPU_EXEC_CTRL0, 4646 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4647 vmcs_write(CPU_EXEC_CTRL1, CPU_VIRT_APIC_ACCESSES); 4648 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4649 test_tpr_threshold_values(); 4650 report_prefix_pop(); 4651 4652 vmcs_write(CPU_EXEC_CTRL0, 4653 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4654 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4655 test_tpr_threshold_values(); 4656 report_prefix_pop(); 4657 } 4658 4659 if ((ctrl_cpu_rev[1].clr & 4660 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) == 4661 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) { 4662 vmcs_write(CPU_EXEC_CTRL0, 4663 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4664 vmcs_write(CPU_EXEC_CTRL1, 4665 CPU_VINTD | CPU_VIRT_APIC_ACCESSES); 4666 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4667 test_tpr_threshold_values(); 4668 report_prefix_pop(); 4669 4670 vmcs_write(CPU_EXEC_CTRL0, 4671 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4672 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4673 test_tpr_threshold_values(); 4674 report_prefix_pop(); 4675 } 4676 4677 vmcs_write(CPU_EXEC_CTRL1, secondary); 4678 out: 4679 vmcs_write(TPR_THRESHOLD, threshold); 4680 vmcs_write(APIC_VIRT_ADDR, apic_virt_addr); 4681 vmcs_write(CPU_EXEC_CTRL0, primary); 4682 } 4683 4684 /* 4685 * This test verifies the following two vmentry checks: 4686 * 4687 * If the "NMI exiting" VM-execution control is 0, "Virtual NMIs" 4688 * VM-execution control must be 0. 4689 * [Intel SDM] 4690 * 4691 * If the "virtual NMIs" VM-execution control is 0, the "NMI-window 4692 * exiting" VM-execution control must be 0. 4693 * [Intel SDM] 4694 */ 4695 static void test_nmi_ctrls(void) 4696 { 4697 u32 pin_ctrls, cpu_ctrls0, test_pin_ctrls, test_cpu_ctrls0; 4698 4699 if ((ctrl_pin_rev.clr & (PIN_NMI | PIN_VIRT_NMI)) != 4700 (PIN_NMI | PIN_VIRT_NMI)) { 4701 printf("NMI exiting and Virtual NMIs are not supported !\n"); 4702 return; 4703 } 4704 4705 /* Save the controls so that we can restore them after our tests */ 4706 pin_ctrls = vmcs_read(PIN_CONTROLS); 4707 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 4708 4709 test_pin_ctrls = pin_ctrls & ~(PIN_NMI | PIN_VIRT_NMI); 4710 test_cpu_ctrls0 = cpu_ctrls0 & ~CPU_NMI_WINDOW; 4711 4712 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4713 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs disabled"); 4714 test_vmx_valid_controls(); 4715 report_prefix_pop(); 4716 4717 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_VIRT_NMI); 4718 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs enabled"); 4719 test_vmx_invalid_controls(); 4720 report_prefix_pop(); 4721 4722 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4723 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs enabled"); 4724 test_vmx_valid_controls(); 4725 report_prefix_pop(); 4726 4727 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_NMI); 4728 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs disabled"); 4729 test_vmx_valid_controls(); 4730 report_prefix_pop(); 4731 4732 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 4733 report_info("NMI-window exiting is not supported, skipping..."); 4734 goto done; 4735 } 4736 4737 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4738 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4739 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting enabled"); 4740 test_vmx_invalid_controls(); 4741 report_prefix_pop(); 4742 4743 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4744 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4745 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting disabled"); 4746 test_vmx_valid_controls(); 4747 report_prefix_pop(); 4748 4749 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4750 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4751 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting enabled"); 4752 test_vmx_valid_controls(); 4753 report_prefix_pop(); 4754 4755 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4756 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4757 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting disabled"); 4758 test_vmx_valid_controls(); 4759 report_prefix_pop(); 4760 4761 /* Restore the controls to their original values */ 4762 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 4763 done: 4764 vmcs_write(PIN_CONTROLS, pin_ctrls); 4765 } 4766 4767 static void test_eptp_ad_bit(u64 eptp, bool ctrl) 4768 { 4769 vmcs_write(EPTP, eptp); 4770 report_prefix_pushf("Enable-EPT enabled; EPT accessed and dirty flag %s", 4771 (eptp & EPTP_AD_FLAG) ? "1": "0"); 4772 if (ctrl) 4773 test_vmx_valid_controls(); 4774 else 4775 test_vmx_invalid_controls(); 4776 report_prefix_pop(); 4777 4778 } 4779 4780 /* 4781 * 1. If the "enable EPT" VM-execution control is 1, the "EPTP VM-execution" 4782 * control field must satisfy the following checks: 4783 * 4784 * - The EPT memory type (bits 2:0) must be a value supported by the 4785 * processor as indicated in the IA32_VMX_EPT_VPID_CAP MSR. 4786 * - Bits 5:3 (1 less than the EPT page-walk length) must indicate a 4787 * supported EPT page-walk length. 4788 * - Bit 6 (enable bit for accessed and dirty flags for EPT) must be 4789 * 0 if bit 21 of the IA32_VMX_EPT_VPID_CAP MSR is read as 0, 4790 * indicating that the processor does not support accessed and dirty 4791 * dirty flags for EPT. 4792 * - Reserved bits 11:7 and 63:N (where N is the processor's 4793 * physical-address width) must all be 0. 4794 * 4795 * 2. If the "unrestricted guest" VM-execution control is 1, the 4796 * "enable EPT" VM-execution control must also be 1. 4797 */ 4798 static void test_ept_eptp(void) 4799 { 4800 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4801 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4802 u64 eptp_saved = vmcs_read(EPTP); 4803 u32 primary = primary_saved; 4804 u32 secondary = secondary_saved; 4805 u64 msr, eptp = eptp_saved; 4806 bool un_cache = false; 4807 bool wr_bk = false; 4808 bool ctrl; 4809 u32 i, maxphysaddr; 4810 u64 j, resv_bits_mask = 0; 4811 4812 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4813 (ctrl_cpu_rev[1].clr & CPU_EPT))) { 4814 printf("\"CPU secondary\" and/or \"enable EPT\" execution controls are not supported !\n"); 4815 return; 4816 } 4817 4818 /* 4819 * Memory type (bits 2:0) 4820 */ 4821 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 4822 if (msr & EPT_CAP_UC) 4823 un_cache = true; 4824 if (msr & EPT_CAP_WB) 4825 wr_bk = true; 4826 4827 /* Support for 4-level EPT is mandatory. */ 4828 report(msr & EPT_CAP_PWL4, "4-level EPT support check"); 4829 4830 primary |= CPU_SECONDARY; 4831 vmcs_write(CPU_EXEC_CTRL0, primary); 4832 secondary |= CPU_EPT; 4833 vmcs_write(CPU_EXEC_CTRL1, secondary); 4834 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4835 (3ul << EPTP_PG_WALK_LEN_SHIFT); 4836 vmcs_write(EPTP, eptp); 4837 4838 for (i = 0; i < 8; i++) { 4839 if (i == 0) { 4840 if (un_cache) { 4841 report_info("EPT paging structure memory-type is Un-cacheable\n"); 4842 ctrl = true; 4843 } else { 4844 ctrl = false; 4845 } 4846 } else if (i == 6) { 4847 if (wr_bk) { 4848 report_info("EPT paging structure memory-type is Write-back\n"); 4849 ctrl = true; 4850 } else { 4851 ctrl = false; 4852 } 4853 } else { 4854 ctrl = false; 4855 } 4856 4857 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | i; 4858 vmcs_write(EPTP, eptp); 4859 report_prefix_pushf("Enable-EPT enabled; EPT memory type %lu", 4860 eptp & EPT_MEM_TYPE_MASK); 4861 if (ctrl) 4862 test_vmx_valid_controls(); 4863 else 4864 test_vmx_invalid_controls(); 4865 report_prefix_pop(); 4866 } 4867 4868 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | 6ul; 4869 4870 /* 4871 * Page walk length (bits 5:3). Note, the value in VMCS.EPTP "is 1 4872 * less than the EPT page-walk length". 4873 */ 4874 for (i = 0; i < 8; i++) { 4875 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4876 (i << EPTP_PG_WALK_LEN_SHIFT); 4877 if (i == 3 || (i == 4 && (msr & EPT_CAP_PWL5))) 4878 ctrl = true; 4879 else 4880 ctrl = false; 4881 4882 vmcs_write(EPTP, eptp); 4883 report_prefix_pushf("Enable-EPT enabled; EPT page walk length %lu", 4884 eptp & EPTP_PG_WALK_LEN_MASK); 4885 if (ctrl) 4886 test_vmx_valid_controls(); 4887 else 4888 test_vmx_invalid_controls(); 4889 report_prefix_pop(); 4890 } 4891 4892 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4893 3ul << EPTP_PG_WALK_LEN_SHIFT; 4894 4895 /* 4896 * Accessed and dirty flag (bit 6) 4897 */ 4898 if (msr & EPT_CAP_AD_FLAG) { 4899 report_info("Processor supports accessed and dirty flag"); 4900 eptp &= ~EPTP_AD_FLAG; 4901 test_eptp_ad_bit(eptp, true); 4902 4903 eptp |= EPTP_AD_FLAG; 4904 test_eptp_ad_bit(eptp, true); 4905 } else { 4906 report_info("Processor does not supports accessed and dirty flag"); 4907 eptp &= ~EPTP_AD_FLAG; 4908 test_eptp_ad_bit(eptp, true); 4909 4910 eptp |= EPTP_AD_FLAG; 4911 test_eptp_ad_bit(eptp, false); 4912 } 4913 4914 /* 4915 * Reserved bits [11:7] and [63:N] 4916 */ 4917 for (i = 0; i < 32; i++) { 4918 eptp = (eptp & 4919 ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)) | 4920 (i << EPTP_RESERV_BITS_SHIFT); 4921 vmcs_write(EPTP, eptp); 4922 report_prefix_pushf("Enable-EPT enabled; reserved bits [11:7] %lu", 4923 (eptp >> EPTP_RESERV_BITS_SHIFT) & 4924 EPTP_RESERV_BITS_MASK); 4925 if (i == 0) 4926 test_vmx_valid_controls(); 4927 else 4928 test_vmx_invalid_controls(); 4929 report_prefix_pop(); 4930 } 4931 4932 eptp = (eptp & ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)); 4933 4934 maxphysaddr = cpuid_maxphyaddr(); 4935 for (i = 0; i < (63 - maxphysaddr + 1); i++) { 4936 resv_bits_mask |= 1ul << i; 4937 } 4938 4939 for (j = maxphysaddr - 1; j <= 63; j++) { 4940 eptp = (eptp & ~(resv_bits_mask << maxphysaddr)) | 4941 (j < maxphysaddr ? 0 : 1ul << j); 4942 vmcs_write(EPTP, eptp); 4943 report_prefix_pushf("Enable-EPT enabled; reserved bits [63:N] %lu", 4944 (eptp >> maxphysaddr) & resv_bits_mask); 4945 if (j < maxphysaddr) 4946 test_vmx_valid_controls(); 4947 else 4948 test_vmx_invalid_controls(); 4949 report_prefix_pop(); 4950 } 4951 4952 secondary &= ~(CPU_EPT | CPU_URG); 4953 vmcs_write(CPU_EXEC_CTRL1, secondary); 4954 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest disabled"); 4955 test_vmx_valid_controls(); 4956 report_prefix_pop(); 4957 4958 if (!(ctrl_cpu_rev[1].clr & CPU_URG)) 4959 goto skip_unrestricted_guest; 4960 4961 secondary |= CPU_URG; 4962 vmcs_write(CPU_EXEC_CTRL1, secondary); 4963 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest enabled"); 4964 test_vmx_invalid_controls(); 4965 report_prefix_pop(); 4966 4967 secondary |= CPU_EPT; 4968 setup_dummy_ept(); 4969 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest enabled"); 4970 test_vmx_valid_controls(); 4971 report_prefix_pop(); 4972 4973 skip_unrestricted_guest: 4974 secondary &= ~CPU_URG; 4975 vmcs_write(CPU_EXEC_CTRL1, secondary); 4976 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest disabled"); 4977 test_vmx_valid_controls(); 4978 report_prefix_pop(); 4979 4980 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4981 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4982 vmcs_write(EPTP, eptp_saved); 4983 } 4984 4985 /* 4986 * If the 'enable PML' VM-execution control is 1, the 'enable EPT' 4987 * VM-execution control must also be 1. In addition, the PML address 4988 * must satisfy the following checks: 4989 * 4990 * * Bits 11:0 of the address must be 0. 4991 * * The address should not set any bits beyond the processor's 4992 * physical-address width. 4993 * 4994 * [Intel SDM] 4995 */ 4996 static void test_pml(void) 4997 { 4998 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4999 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 5000 u32 primary = primary_saved; 5001 u32 secondary = secondary_saved; 5002 5003 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 5004 (ctrl_cpu_rev[1].clr & CPU_EPT) && (ctrl_cpu_rev[1].clr & CPU_PML))) { 5005 printf("\"Secondary execution\" control or \"enable EPT\" control or \"enable PML\" control is not supported !\n"); 5006 return; 5007 } 5008 5009 primary |= CPU_SECONDARY; 5010 vmcs_write(CPU_EXEC_CTRL0, primary); 5011 secondary &= ~(CPU_PML | CPU_EPT); 5012 vmcs_write(CPU_EXEC_CTRL1, secondary); 5013 report_prefix_pushf("enable-PML disabled, enable-EPT disabled"); 5014 test_vmx_valid_controls(); 5015 report_prefix_pop(); 5016 5017 secondary |= CPU_PML; 5018 vmcs_write(CPU_EXEC_CTRL1, secondary); 5019 report_prefix_pushf("enable-PML enabled, enable-EPT disabled"); 5020 test_vmx_invalid_controls(); 5021 report_prefix_pop(); 5022 5023 secondary |= CPU_EPT; 5024 setup_dummy_ept(); 5025 report_prefix_pushf("enable-PML enabled, enable-EPT enabled"); 5026 test_vmx_valid_controls(); 5027 report_prefix_pop(); 5028 5029 secondary &= ~CPU_PML; 5030 vmcs_write(CPU_EXEC_CTRL1, secondary); 5031 report_prefix_pushf("enable-PML disabled, enable EPT enabled"); 5032 test_vmx_valid_controls(); 5033 report_prefix_pop(); 5034 5035 test_vmcs_addr_reference(CPU_PML, PMLADDR, "PML address", "PML", 5036 PAGE_SIZE, false, false); 5037 5038 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 5039 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 5040 } 5041 5042 /* 5043 * If the "activate VMX-preemption timer" VM-execution control is 0, the 5044 * the "save VMX-preemption timer value" VM-exit control must also be 0. 5045 * 5046 * [Intel SDM] 5047 */ 5048 static void test_vmx_preemption_timer(void) 5049 { 5050 u32 saved_pin = vmcs_read(PIN_CONTROLS); 5051 u32 saved_exit = vmcs_read(EXI_CONTROLS); 5052 u32 pin = saved_pin; 5053 u32 exit = saved_exit; 5054 5055 if (!((ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) || 5056 (ctrl_pin_rev.clr & PIN_PREEMPT))) { 5057 printf("\"Save-VMX-preemption-timer\" control and/or \"Enable-VMX-preemption-timer\" control is not supported\n"); 5058 return; 5059 } 5060 5061 pin |= PIN_PREEMPT; 5062 vmcs_write(PIN_CONTROLS, pin); 5063 exit &= ~EXI_SAVE_PREEMPT; 5064 vmcs_write(EXI_CONTROLS, exit); 5065 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer disabled"); 5066 test_vmx_valid_controls(); 5067 report_prefix_pop(); 5068 5069 exit |= EXI_SAVE_PREEMPT; 5070 vmcs_write(EXI_CONTROLS, exit); 5071 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer enabled"); 5072 test_vmx_valid_controls(); 5073 report_prefix_pop(); 5074 5075 pin &= ~PIN_PREEMPT; 5076 vmcs_write(PIN_CONTROLS, pin); 5077 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer enabled"); 5078 test_vmx_invalid_controls(); 5079 report_prefix_pop(); 5080 5081 exit &= ~EXI_SAVE_PREEMPT; 5082 vmcs_write(EXI_CONTROLS, exit); 5083 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer disabled"); 5084 test_vmx_valid_controls(); 5085 report_prefix_pop(); 5086 5087 vmcs_write(PIN_CONTROLS, saved_pin); 5088 vmcs_write(EXI_CONTROLS, saved_exit); 5089 } 5090 5091 extern unsigned char test_mtf1; 5092 extern unsigned char test_mtf2; 5093 extern unsigned char test_mtf3; 5094 extern unsigned char test_mtf4; 5095 5096 static void test_mtf_guest(void) 5097 { 5098 asm ("vmcall;\n\t" 5099 "out %al, $0x80;\n\t" 5100 "test_mtf1:\n\t" 5101 "vmcall;\n\t" 5102 "out %al, $0x80;\n\t" 5103 "test_mtf2:\n\t" 5104 /* 5105 * Prepare for the 'MOV CR3' test. Attempt to induce a 5106 * general-protection fault by moving a non-canonical address into 5107 * CR3. The 'MOV CR3' instruction does not take an imm64 operand, 5108 * so we must MOV the desired value into a register first. 5109 * 5110 * MOV RAX is done before the VMCALL such that MTF is only enabled 5111 * for the instruction under test. 5112 */ 5113 "mov $0xaaaaaaaaaaaaaaaa, %rax;\n\t" 5114 "vmcall;\n\t" 5115 "mov %rax, %cr3;\n\t" 5116 "test_mtf3:\n\t" 5117 "vmcall;\n\t" 5118 /* 5119 * ICEBP/INT1 instruction. Though the instruction is now 5120 * documented, don't rely on assemblers enumerating the 5121 * instruction. Resort to hand assembly. 5122 */ 5123 ".byte 0xf1;\n\t" 5124 "vmcall;\n\t" 5125 "test_mtf4:\n\t" 5126 "mov $0, %eax;\n\t"); 5127 } 5128 5129 static void test_mtf_gp_handler(struct ex_regs *regs) 5130 { 5131 regs->rip = (unsigned long) &test_mtf3; 5132 } 5133 5134 static void test_mtf_db_handler(struct ex_regs *regs) 5135 { 5136 } 5137 5138 static void enable_mtf(void) 5139 { 5140 u32 ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 5141 5142 vmcs_write(CPU_EXEC_CTRL0, ctrl0 | CPU_MTF); 5143 } 5144 5145 static void disable_mtf(void) 5146 { 5147 u32 ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 5148 5149 vmcs_write(CPU_EXEC_CTRL0, ctrl0 & ~CPU_MTF); 5150 } 5151 5152 static void enable_tf(void) 5153 { 5154 unsigned long rflags = vmcs_read(GUEST_RFLAGS); 5155 5156 vmcs_write(GUEST_RFLAGS, rflags | X86_EFLAGS_TF); 5157 } 5158 5159 static void disable_tf(void) 5160 { 5161 unsigned long rflags = vmcs_read(GUEST_RFLAGS); 5162 5163 vmcs_write(GUEST_RFLAGS, rflags & ~X86_EFLAGS_TF); 5164 } 5165 5166 static void report_mtf(const char *insn_name, unsigned long exp_rip) 5167 { 5168 unsigned long rip = vmcs_read(GUEST_RIP); 5169 5170 assert_exit_reason(VMX_MTF); 5171 report(rip == exp_rip, "MTF VM-exit after %s. RIP: 0x%lx (expected 0x%lx)", 5172 insn_name, rip, exp_rip); 5173 } 5174 5175 static void vmx_mtf_test(void) 5176 { 5177 unsigned long pending_dbg; 5178 handler old_gp, old_db; 5179 5180 if (!(ctrl_cpu_rev[0].clr & CPU_MTF)) { 5181 printf("CPU does not support the 'monitor trap flag' processor-based VM-execution control.\n"); 5182 return; 5183 } 5184 5185 test_set_guest(test_mtf_guest); 5186 5187 /* Expect an MTF VM-exit after OUT instruction */ 5188 enter_guest(); 5189 skip_exit_vmcall(); 5190 5191 enable_mtf(); 5192 enter_guest(); 5193 report_mtf("OUT", (unsigned long) &test_mtf1); 5194 disable_mtf(); 5195 5196 /* 5197 * Concurrent #DB trap and MTF on instruction boundary. Expect MTF 5198 * VM-exit with populated 'pending debug exceptions' VMCS field. 5199 */ 5200 enter_guest(); 5201 skip_exit_vmcall(); 5202 5203 enable_mtf(); 5204 enable_tf(); 5205 5206 enter_guest(); 5207 report_mtf("OUT", (unsigned long) &test_mtf2); 5208 pending_dbg = vmcs_read(GUEST_PENDING_DEBUG); 5209 report(pending_dbg & DR_STEP, 5210 "'pending debug exceptions' field after MTF VM-exit: 0x%lx (expected 0x%lx)", 5211 pending_dbg, (unsigned long) DR_STEP); 5212 5213 disable_mtf(); 5214 disable_tf(); 5215 vmcs_write(GUEST_PENDING_DEBUG, 0); 5216 5217 /* 5218 * #GP exception takes priority over MTF. Expect MTF VM-exit with RIP 5219 * advanced to first instruction of #GP handler. 5220 */ 5221 enter_guest(); 5222 skip_exit_vmcall(); 5223 5224 old_gp = handle_exception(GP_VECTOR, test_mtf_gp_handler); 5225 5226 enable_mtf(); 5227 enter_guest(); 5228 report_mtf("MOV CR3", (unsigned long) get_idt_addr(&boot_idt[GP_VECTOR])); 5229 disable_mtf(); 5230 5231 /* 5232 * Concurrent MTF and privileged software exception (i.e. ICEBP/INT1). 5233 * MTF should follow the delivery of #DB trap, though the SDM doesn't 5234 * provide clear indication of the relative priority. 5235 */ 5236 enter_guest(); 5237 skip_exit_vmcall(); 5238 5239 handle_exception(GP_VECTOR, old_gp); 5240 old_db = handle_exception(DB_VECTOR, test_mtf_db_handler); 5241 5242 enable_mtf(); 5243 enter_guest(); 5244 report_mtf("INT1", (unsigned long) get_idt_addr(&boot_idt[DB_VECTOR])); 5245 disable_mtf(); 5246 5247 enter_guest(); 5248 skip_exit_vmcall(); 5249 handle_exception(DB_VECTOR, old_db); 5250 vmcs_write(ENT_INTR_INFO, INTR_INFO_VALID_MASK | INTR_TYPE_OTHER_EVENT); 5251 enter_guest(); 5252 report_mtf("injected MTF", (unsigned long) &test_mtf4); 5253 enter_guest(); 5254 } 5255 5256 extern char vmx_mtf_pdpte_guest_begin; 5257 extern char vmx_mtf_pdpte_guest_end; 5258 5259 asm("vmx_mtf_pdpte_guest_begin:\n\t" 5260 "mov %cr0, %rax\n\t" /* save CR0 with PG=1 */ 5261 "vmcall\n\t" /* on return from this CR0.PG=0 */ 5262 "mov %rax, %cr0\n\t" /* restore CR0.PG=1 to enter PAE mode */ 5263 "vmcall\n\t" 5264 "retq\n\t" 5265 "vmx_mtf_pdpte_guest_end:"); 5266 5267 static void vmx_mtf_pdpte_test(void) 5268 { 5269 void *test_mtf_pdpte_guest; 5270 pteval_t *pdpt; 5271 u32 guest_ar_cs; 5272 u64 guest_efer; 5273 pteval_t *pte; 5274 u64 guest_cr0; 5275 u64 guest_cr3; 5276 u64 guest_cr4; 5277 u64 ent_ctls; 5278 int i; 5279 5280 if (setup_ept(false)) 5281 return; 5282 5283 if (!(ctrl_cpu_rev[0].clr & CPU_MTF)) { 5284 printf("CPU does not support 'monitor trap flag.'\n"); 5285 return; 5286 } 5287 5288 if (!(ctrl_cpu_rev[1].clr & CPU_URG)) { 5289 printf("CPU does not support 'unrestricted guest.'\n"); 5290 return; 5291 } 5292 5293 vmcs_write(EXC_BITMAP, ~0); 5294 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | CPU_URG); 5295 5296 /* 5297 * Copy the guest code to an identity-mapped page. 5298 */ 5299 test_mtf_pdpte_guest = alloc_page(); 5300 memcpy(test_mtf_pdpte_guest, &vmx_mtf_pdpte_guest_begin, 5301 &vmx_mtf_pdpte_guest_end - &vmx_mtf_pdpte_guest_begin); 5302 5303 test_set_guest(test_mtf_pdpte_guest); 5304 5305 enter_guest(); 5306 skip_exit_vmcall(); 5307 5308 /* 5309 * Put the guest in non-paged 32-bit protected mode, ready to enter 5310 * PAE mode when CR0.PG is set. CR4.PAE will already have been set 5311 * when the guest started out in long mode. 5312 */ 5313 ent_ctls = vmcs_read(ENT_CONTROLS); 5314 vmcs_write(ENT_CONTROLS, ent_ctls & ~ENT_GUEST_64); 5315 5316 guest_efer = vmcs_read(GUEST_EFER); 5317 vmcs_write(GUEST_EFER, guest_efer & ~(EFER_LMA | EFER_LME)); 5318 5319 /* 5320 * Set CS access rights bits for 32-bit protected mode: 5321 * 3:0 B execute/read/accessed 5322 * 4 1 code or data 5323 * 6:5 0 descriptor privilege level 5324 * 7 1 present 5325 * 11:8 0 reserved 5326 * 12 0 available for use by system software 5327 * 13 0 64 bit mode not active 5328 * 14 1 default operation size 32-bit segment 5329 * 15 1 page granularity: segment limit in 4K units 5330 * 16 0 segment usable 5331 * 31:17 0 reserved 5332 */ 5333 guest_ar_cs = vmcs_read(GUEST_AR_CS); 5334 vmcs_write(GUEST_AR_CS, 0xc09b); 5335 5336 guest_cr0 = vmcs_read(GUEST_CR0); 5337 vmcs_write(GUEST_CR0, guest_cr0 & ~X86_CR0_PG); 5338 5339 guest_cr4 = vmcs_read(GUEST_CR4); 5340 vmcs_write(GUEST_CR4, guest_cr4 & ~X86_CR4_PCIDE); 5341 5342 guest_cr3 = vmcs_read(GUEST_CR3); 5343 5344 /* 5345 * Turn the 4-level page table into a PAE page table by following the 0th 5346 * PML4 entry to a PDPT page, and grab the first four PDPTEs from that 5347 * page. 5348 * 5349 * Why does this work? 5350 * 5351 * PAE uses 32-bit addressing which implies: 5352 * Bits 11:0 page offset 5353 * Bits 20:12 entry into 512-entry page table 5354 * Bits 29:21 entry into a 512-entry directory table 5355 * Bits 31:30 entry into the page directory pointer table. 5356 * Bits 63:32 zero 5357 * 5358 * As only 2 bits are needed to select the PDPTEs for the entire 5359 * 32-bit address space, take the first 4 PDPTEs in the level 3 page 5360 * directory pointer table. It doesn't matter which of these PDPTEs 5361 * are present because they must cover the guest code given that it 5362 * has already run successfully. 5363 * 5364 * Get a pointer to PTE for GVA=0 in the page directory pointer table 5365 */ 5366 pte = get_pte_level( 5367 (pgd_t *)phys_to_virt(guest_cr3 & ~X86_CR3_PCID_MASK), 0, 5368 PDPT_LEVEL); 5369 5370 /* 5371 * Need some memory for the 4-entry PAE page directory pointer 5372 * table. Use the end of the identity-mapped page where the guest code 5373 * is stored. There is definitely space as the guest code is only a 5374 * few bytes. 5375 */ 5376 pdpt = test_mtf_pdpte_guest + PAGE_SIZE - 4 * sizeof(pteval_t); 5377 5378 /* 5379 * Copy the first four PDPTEs into the PAE page table with reserved 5380 * bits cleared. Note that permission bits from the PML4E and PDPTE 5381 * are not propagated. 5382 */ 5383 for (i = 0; i < 4; i++) { 5384 TEST_ASSERT_EQ_MSG(0, (pte[i] & PDPTE64_RSVD_MASK), 5385 "PDPTE has invalid reserved bits"); 5386 TEST_ASSERT_EQ_MSG(0, (pte[i] & PDPTE64_PAGE_SIZE_MASK), 5387 "Cannot use 1GB super pages for PAE"); 5388 pdpt[i] = pte[i] & ~(PAE_PDPTE_RSVD_MASK); 5389 } 5390 vmcs_write(GUEST_CR3, virt_to_phys(pdpt)); 5391 5392 enable_mtf(); 5393 enter_guest(); 5394 assert_exit_reason(VMX_MTF); 5395 disable_mtf(); 5396 5397 /* 5398 * The four PDPTEs should have been loaded into the VMCS when 5399 * the guest set CR0.PG to enter PAE mode. 5400 */ 5401 for (i = 0; i < 4; i++) { 5402 u64 pdpte = vmcs_read(GUEST_PDPTE + 2 * i); 5403 5404 report(pdpte == pdpt[i], "PDPTE%d is 0x%lx (expected 0x%lx)", 5405 i, pdpte, pdpt[i]); 5406 } 5407 5408 /* 5409 * Now, try to enter the guest in PAE mode. If the PDPTEs in the 5410 * vmcs are wrong, this will fail. 5411 */ 5412 enter_guest(); 5413 skip_exit_vmcall(); 5414 5415 /* 5416 * Return guest to 64-bit mode and wrap up. 5417 */ 5418 vmcs_write(ENT_CONTROLS, ent_ctls); 5419 vmcs_write(GUEST_EFER, guest_efer); 5420 vmcs_write(GUEST_AR_CS, guest_ar_cs); 5421 vmcs_write(GUEST_CR0, guest_cr0); 5422 vmcs_write(GUEST_CR4, guest_cr4); 5423 vmcs_write(GUEST_CR3, guest_cr3); 5424 5425 enter_guest(); 5426 } 5427 5428 /* 5429 * Tests for VM-execution control fields 5430 */ 5431 static void test_vm_execution_ctls(void) 5432 { 5433 test_pin_based_ctls(); 5434 test_primary_processor_based_ctls(); 5435 test_secondary_processor_based_ctls(); 5436 test_cr3_targets(); 5437 test_io_bitmaps(); 5438 test_msr_bitmap(); 5439 test_apic_ctls(); 5440 test_tpr_threshold(); 5441 test_nmi_ctrls(); 5442 test_pml(); 5443 test_vpid(); 5444 test_ept_eptp(); 5445 test_vmx_preemption_timer(); 5446 } 5447 5448 /* 5449 * The following checks are performed for the VM-entry MSR-load address if 5450 * the VM-entry MSR-load count field is non-zero: 5451 * 5452 * - The lower 4 bits of the VM-entry MSR-load address must be 0. 5453 * The address should not set any bits beyond the processor's 5454 * physical-address width. 5455 * 5456 * - The address of the last byte in the VM-entry MSR-load area 5457 * should not set any bits beyond the processor's physical-address 5458 * width. The address of this last byte is VM-entry MSR-load address 5459 * + (MSR count * 16) - 1. (The arithmetic used for the computation 5460 * uses more bits than the processor's physical-address width.) 5461 * 5462 * 5463 * [Intel SDM] 5464 */ 5465 static void test_entry_msr_load(void) 5466 { 5467 entry_msr_load = alloc_page(); 5468 u64 tmp; 5469 u32 entry_msr_ld_cnt = 1; 5470 int i; 5471 u32 addr_len = 64; 5472 5473 vmcs_write(ENT_MSR_LD_CNT, entry_msr_ld_cnt); 5474 5475 /* Check first 4 bits of VM-entry MSR-load address */ 5476 for (i = 0; i < 4; i++) { 5477 tmp = (u64)entry_msr_load | 1ull << i; 5478 vmcs_write(ENTER_MSR_LD_ADDR, tmp); 5479 report_prefix_pushf("VM-entry MSR-load addr [4:0] %lx", 5480 tmp & 0xf); 5481 test_vmx_invalid_controls(); 5482 report_prefix_pop(); 5483 } 5484 5485 if (basic.val & (1ul << 48)) 5486 addr_len = 32; 5487 5488 test_vmcs_addr_values("VM-entry-MSR-load address", 5489 ENTER_MSR_LD_ADDR, 16, false, false, 5490 4, addr_len - 1); 5491 5492 /* 5493 * Check last byte of VM-entry MSR-load address 5494 */ 5495 entry_msr_load = (struct vmx_msr_entry *)((u64)entry_msr_load & ~0xf); 5496 5497 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 5498 i < 64; i++) { 5499 tmp = ((u64)entry_msr_load + entry_msr_ld_cnt * 16 - 1) | 5500 1ul << i; 5501 vmcs_write(ENTER_MSR_LD_ADDR, 5502 tmp - (entry_msr_ld_cnt * 16 - 1)); 5503 test_vmx_invalid_controls(); 5504 } 5505 5506 vmcs_write(ENT_MSR_LD_CNT, 2); 5507 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 5508 test_vmx_invalid_controls(); 5509 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 5510 test_vmx_valid_controls(); 5511 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 5512 test_vmx_valid_controls(); 5513 } 5514 5515 static struct vmx_state_area_test_data { 5516 u32 msr; 5517 u64 exp; 5518 bool enabled; 5519 } vmx_state_area_test_data; 5520 5521 static void guest_state_test_main(void) 5522 { 5523 u64 obs; 5524 struct vmx_state_area_test_data *data = &vmx_state_area_test_data; 5525 5526 while (1) { 5527 if (vmx_get_test_stage() == 2) 5528 break; 5529 5530 if (data->enabled) { 5531 obs = rdmsr(data->msr); 5532 report(data->exp == obs, 5533 "Guest state is 0x%lx (expected 0x%lx)", 5534 obs, data->exp); 5535 } 5536 5537 vmcall(); 5538 } 5539 5540 asm volatile("fnop"); 5541 } 5542 5543 static void test_guest_state(const char *test, bool xfail, u64 field, 5544 const char * field_name) 5545 { 5546 struct vmentry_result result; 5547 u8 abort_flags; 5548 5549 abort_flags = ABORT_ON_EARLY_VMENTRY_FAIL; 5550 if (!xfail) 5551 abort_flags = ABORT_ON_INVALID_GUEST_STATE; 5552 5553 __enter_guest(abort_flags, &result); 5554 5555 report(result.exit_reason.failed_vmentry == xfail && 5556 ((xfail && result.exit_reason.basic == VMX_FAIL_STATE) || 5557 (!xfail && result.exit_reason.basic == VMX_VMCALL)) && 5558 (!xfail || vmcs_read(EXI_QUALIFICATION) == ENTRY_FAIL_DEFAULT), 5559 "%s, %s = %lx", test, field_name, field); 5560 5561 if (!result.exit_reason.failed_vmentry) 5562 skip_exit_insn(); 5563 } 5564 5565 /* 5566 * Tests for VM-entry control fields 5567 */ 5568 static void test_vm_entry_ctls(void) 5569 { 5570 test_invalid_event_injection(); 5571 test_entry_msr_load(); 5572 } 5573 5574 /* 5575 * The following checks are performed for the VM-exit MSR-store address if 5576 * the VM-exit MSR-store count field is non-zero: 5577 * 5578 * - The lower 4 bits of the VM-exit MSR-store address must be 0. 5579 * The address should not set any bits beyond the processor's 5580 * physical-address width. 5581 * 5582 * - The address of the last byte in the VM-exit MSR-store area 5583 * should not set any bits beyond the processor's physical-address 5584 * width. The address of this last byte is VM-exit MSR-store address 5585 * + (MSR count * 16) - 1. (The arithmetic used for the computation 5586 * uses more bits than the processor's physical-address width.) 5587 * 5588 * If IA32_VMX_BASIC[48] is read as 1, neither address should set any bits 5589 * in the range 63:32. 5590 * 5591 * [Intel SDM] 5592 */ 5593 static void test_exit_msr_store(void) 5594 { 5595 exit_msr_store = alloc_page(); 5596 u64 tmp; 5597 u32 exit_msr_st_cnt = 1; 5598 int i; 5599 u32 addr_len = 64; 5600 5601 vmcs_write(EXI_MSR_ST_CNT, exit_msr_st_cnt); 5602 5603 /* Check first 4 bits of VM-exit MSR-store address */ 5604 for (i = 0; i < 4; i++) { 5605 tmp = (u64)exit_msr_store | 1ull << i; 5606 vmcs_write(EXIT_MSR_ST_ADDR, tmp); 5607 report_prefix_pushf("VM-exit MSR-store addr [4:0] %lx", 5608 tmp & 0xf); 5609 test_vmx_invalid_controls(); 5610 report_prefix_pop(); 5611 } 5612 5613 if (basic.val & (1ul << 48)) 5614 addr_len = 32; 5615 5616 test_vmcs_addr_values("VM-exit-MSR-store address", 5617 EXIT_MSR_ST_ADDR, 16, false, false, 5618 4, addr_len - 1); 5619 5620 /* 5621 * Check last byte of VM-exit MSR-store address 5622 */ 5623 exit_msr_store = (struct vmx_msr_entry *)((u64)exit_msr_store & ~0xf); 5624 5625 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 5626 i < 64; i++) { 5627 tmp = ((u64)exit_msr_store + exit_msr_st_cnt * 16 - 1) | 5628 1ul << i; 5629 vmcs_write(EXIT_MSR_ST_ADDR, 5630 tmp - (exit_msr_st_cnt * 16 - 1)); 5631 test_vmx_invalid_controls(); 5632 } 5633 5634 vmcs_write(EXI_MSR_ST_CNT, 2); 5635 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 5636 test_vmx_invalid_controls(); 5637 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 5638 test_vmx_valid_controls(); 5639 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 5640 test_vmx_valid_controls(); 5641 } 5642 5643 /* 5644 * Tests for VM-exit controls 5645 */ 5646 static void test_vm_exit_ctls(void) 5647 { 5648 test_exit_msr_store(); 5649 } 5650 5651 /* 5652 * Check that the virtual CPU checks all of the VMX controls as 5653 * documented in the Intel SDM. 5654 */ 5655 static void vmx_controls_test(void) 5656 { 5657 /* 5658 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 5659 * fail due to invalid guest state, should we make it that 5660 * far. 5661 */ 5662 vmcs_write(GUEST_RFLAGS, 0); 5663 5664 test_vm_execution_ctls(); 5665 test_vm_exit_ctls(); 5666 test_vm_entry_ctls(); 5667 } 5668 5669 struct apic_reg_virt_config { 5670 bool apic_register_virtualization; 5671 bool use_tpr_shadow; 5672 bool virtualize_apic_accesses; 5673 bool virtualize_x2apic_mode; 5674 bool activate_secondary_controls; 5675 }; 5676 5677 struct apic_reg_test { 5678 const char *name; 5679 struct apic_reg_virt_config apic_reg_virt_config; 5680 }; 5681 5682 struct apic_reg_virt_expectation { 5683 enum Reason rd_exit_reason; 5684 enum Reason wr_exit_reason; 5685 u32 val; 5686 u32 (*virt_fn)(u32); 5687 5688 /* 5689 * If false, accessing the APIC access address from L2 is treated as a 5690 * normal memory operation, rather than triggering virtualization. 5691 */ 5692 bool virtualize_apic_accesses; 5693 }; 5694 5695 static u32 apic_virt_identity(u32 val) 5696 { 5697 return val; 5698 } 5699 5700 static u32 apic_virt_nibble1(u32 val) 5701 { 5702 return val & 0xf0; 5703 } 5704 5705 static u32 apic_virt_byte3(u32 val) 5706 { 5707 return val & (0xff << 24); 5708 } 5709 5710 static bool apic_reg_virt_exit_expectation( 5711 u32 reg, struct apic_reg_virt_config *config, 5712 struct apic_reg_virt_expectation *expectation) 5713 { 5714 /* Good configs, where some L2 APIC accesses are virtualized. */ 5715 bool virtualize_apic_accesses_only = 5716 config->virtualize_apic_accesses && 5717 !config->use_tpr_shadow && 5718 !config->apic_register_virtualization && 5719 !config->virtualize_x2apic_mode && 5720 config->activate_secondary_controls; 5721 bool virtualize_apic_accesses_and_use_tpr_shadow = 5722 config->virtualize_apic_accesses && 5723 config->use_tpr_shadow && 5724 !config->apic_register_virtualization && 5725 !config->virtualize_x2apic_mode && 5726 config->activate_secondary_controls; 5727 bool apic_register_virtualization = 5728 config->virtualize_apic_accesses && 5729 config->use_tpr_shadow && 5730 config->apic_register_virtualization && 5731 !config->virtualize_x2apic_mode && 5732 config->activate_secondary_controls; 5733 5734 expectation->val = MAGIC_VAL_1; 5735 expectation->virt_fn = apic_virt_identity; 5736 expectation->virtualize_apic_accesses = 5737 config->virtualize_apic_accesses && 5738 config->activate_secondary_controls; 5739 if (virtualize_apic_accesses_only) { 5740 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5741 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5742 } else if (virtualize_apic_accesses_and_use_tpr_shadow) { 5743 switch (reg) { 5744 case APIC_TASKPRI: 5745 expectation->rd_exit_reason = VMX_VMCALL; 5746 expectation->wr_exit_reason = VMX_VMCALL; 5747 expectation->virt_fn = apic_virt_nibble1; 5748 break; 5749 default: 5750 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5751 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5752 } 5753 } else if (apic_register_virtualization) { 5754 expectation->rd_exit_reason = VMX_VMCALL; 5755 5756 switch (reg) { 5757 case APIC_ID: 5758 case APIC_EOI: 5759 case APIC_LDR: 5760 case APIC_DFR: 5761 case APIC_SPIV: 5762 case APIC_ESR: 5763 case APIC_ICR: 5764 case APIC_LVTT: 5765 case APIC_LVTTHMR: 5766 case APIC_LVTPC: 5767 case APIC_LVT0: 5768 case APIC_LVT1: 5769 case APIC_LVTERR: 5770 case APIC_TMICT: 5771 case APIC_TDCR: 5772 expectation->wr_exit_reason = VMX_APIC_WRITE; 5773 break; 5774 case APIC_LVR: 5775 case APIC_ISR ... APIC_ISR + 0x70: 5776 case APIC_TMR ... APIC_TMR + 0x70: 5777 case APIC_IRR ... APIC_IRR + 0x70: 5778 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5779 break; 5780 case APIC_TASKPRI: 5781 expectation->wr_exit_reason = VMX_VMCALL; 5782 expectation->virt_fn = apic_virt_nibble1; 5783 break; 5784 case APIC_ICR2: 5785 expectation->wr_exit_reason = VMX_VMCALL; 5786 expectation->virt_fn = apic_virt_byte3; 5787 break; 5788 default: 5789 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5790 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5791 } 5792 } else if (!expectation->virtualize_apic_accesses) { 5793 /* 5794 * No APIC registers are directly virtualized. This includes 5795 * VTPR, which can be virtualized through MOV to/from CR8 via 5796 * the use TPR shadow control, but not through directly 5797 * accessing VTPR. 5798 */ 5799 expectation->rd_exit_reason = VMX_VMCALL; 5800 expectation->wr_exit_reason = VMX_VMCALL; 5801 } else { 5802 printf("Cannot parse APIC register virtualization config:\n" 5803 "\tvirtualize_apic_accesses: %d\n" 5804 "\tuse_tpr_shadow: %d\n" 5805 "\tapic_register_virtualization: %d\n" 5806 "\tvirtualize_x2apic_mode: %d\n" 5807 "\tactivate_secondary_controls: %d\n", 5808 config->virtualize_apic_accesses, 5809 config->use_tpr_shadow, 5810 config->apic_register_virtualization, 5811 config->virtualize_x2apic_mode, 5812 config->activate_secondary_controls); 5813 5814 return false; 5815 } 5816 5817 return true; 5818 } 5819 5820 struct apic_reg_test apic_reg_tests[] = { 5821 /* Good configs, where some L2 APIC accesses are virtualized. */ 5822 { 5823 .name = "Virtualize APIC accesses", 5824 .apic_reg_virt_config = { 5825 .virtualize_apic_accesses = true, 5826 .use_tpr_shadow = false, 5827 .apic_register_virtualization = false, 5828 .virtualize_x2apic_mode = false, 5829 .activate_secondary_controls = true, 5830 }, 5831 }, 5832 { 5833 .name = "Virtualize APIC accesses + Use TPR shadow", 5834 .apic_reg_virt_config = { 5835 .virtualize_apic_accesses = true, 5836 .use_tpr_shadow = true, 5837 .apic_register_virtualization = false, 5838 .virtualize_x2apic_mode = false, 5839 .activate_secondary_controls = true, 5840 }, 5841 }, 5842 { 5843 .name = "APIC-register virtualization", 5844 .apic_reg_virt_config = { 5845 .virtualize_apic_accesses = true, 5846 .use_tpr_shadow = true, 5847 .apic_register_virtualization = true, 5848 .virtualize_x2apic_mode = false, 5849 .activate_secondary_controls = true, 5850 }, 5851 }, 5852 5853 /* 5854 * Test that the secondary processor-based VM-execution controls are 5855 * correctly ignored when "activate secondary controls" is disabled. 5856 */ 5857 { 5858 .name = "Activate secondary controls off", 5859 .apic_reg_virt_config = { 5860 .virtualize_apic_accesses = true, 5861 .use_tpr_shadow = false, 5862 .apic_register_virtualization = true, 5863 .virtualize_x2apic_mode = true, 5864 .activate_secondary_controls = false, 5865 }, 5866 }, 5867 { 5868 .name = "Activate secondary controls off + Use TPR shadow", 5869 .apic_reg_virt_config = { 5870 .virtualize_apic_accesses = true, 5871 .use_tpr_shadow = true, 5872 .apic_register_virtualization = true, 5873 .virtualize_x2apic_mode = true, 5874 .activate_secondary_controls = false, 5875 }, 5876 }, 5877 5878 /* 5879 * Test that the APIC access address is treated like an arbitrary memory 5880 * address when "virtualize APIC accesses" is disabled. 5881 */ 5882 { 5883 .name = "Virtualize APIC accesses off + Use TPR shadow", 5884 .apic_reg_virt_config = { 5885 .virtualize_apic_accesses = false, 5886 .use_tpr_shadow = true, 5887 .apic_register_virtualization = true, 5888 .virtualize_x2apic_mode = true, 5889 .activate_secondary_controls = true, 5890 }, 5891 }, 5892 5893 /* 5894 * Test that VM entry fails due to invalid controls when 5895 * "APIC-register virtualization" is enabled while "use TPR shadow" is 5896 * disabled. 5897 */ 5898 { 5899 .name = "APIC-register virtualization + Use TPR shadow off", 5900 .apic_reg_virt_config = { 5901 .virtualize_apic_accesses = true, 5902 .use_tpr_shadow = false, 5903 .apic_register_virtualization = true, 5904 .virtualize_x2apic_mode = false, 5905 .activate_secondary_controls = true, 5906 }, 5907 }, 5908 5909 /* 5910 * Test that VM entry fails due to invalid controls when 5911 * "Virtualize x2APIC mode" is enabled while "use TPR shadow" is 5912 * disabled. 5913 */ 5914 { 5915 .name = "Virtualize x2APIC mode + Use TPR shadow off", 5916 .apic_reg_virt_config = { 5917 .virtualize_apic_accesses = false, 5918 .use_tpr_shadow = false, 5919 .apic_register_virtualization = false, 5920 .virtualize_x2apic_mode = true, 5921 .activate_secondary_controls = true, 5922 }, 5923 }, 5924 { 5925 .name = "Virtualize x2APIC mode + Use TPR shadow off v2", 5926 .apic_reg_virt_config = { 5927 .virtualize_apic_accesses = false, 5928 .use_tpr_shadow = false, 5929 .apic_register_virtualization = true, 5930 .virtualize_x2apic_mode = true, 5931 .activate_secondary_controls = true, 5932 }, 5933 }, 5934 5935 /* 5936 * Test that VM entry fails due to invalid controls when 5937 * "virtualize x2APIC mode" is enabled while "virtualize APIC accesses" 5938 * is enabled. 5939 */ 5940 { 5941 .name = "Virtualize x2APIC mode + Virtualize APIC accesses", 5942 .apic_reg_virt_config = { 5943 .virtualize_apic_accesses = true, 5944 .use_tpr_shadow = true, 5945 .apic_register_virtualization = false, 5946 .virtualize_x2apic_mode = true, 5947 .activate_secondary_controls = true, 5948 }, 5949 }, 5950 { 5951 .name = "Virtualize x2APIC mode + Virtualize APIC accesses v2", 5952 .apic_reg_virt_config = { 5953 .virtualize_apic_accesses = true, 5954 .use_tpr_shadow = true, 5955 .apic_register_virtualization = true, 5956 .virtualize_x2apic_mode = true, 5957 .activate_secondary_controls = true, 5958 }, 5959 }, 5960 }; 5961 5962 enum Apic_op { 5963 APIC_OP_XAPIC_RD, 5964 APIC_OP_XAPIC_WR, 5965 TERMINATE, 5966 }; 5967 5968 static u32 vmx_xapic_read(u32 *apic_access_address, u32 reg) 5969 { 5970 return *(volatile u32 *)((uintptr_t)apic_access_address + reg); 5971 } 5972 5973 static void vmx_xapic_write(u32 *apic_access_address, u32 reg, u32 val) 5974 { 5975 *(volatile u32 *)((uintptr_t)apic_access_address + reg) = val; 5976 } 5977 5978 struct apic_reg_virt_guest_args { 5979 enum Apic_op op; 5980 u32 *apic_access_address; 5981 u32 reg; 5982 u32 val; 5983 bool check_rd; 5984 u32 (*virt_fn)(u32); 5985 } apic_reg_virt_guest_args; 5986 5987 static void apic_reg_virt_guest(void) 5988 { 5989 volatile struct apic_reg_virt_guest_args *args = 5990 &apic_reg_virt_guest_args; 5991 5992 for (;;) { 5993 enum Apic_op op = args->op; 5994 u32 *apic_access_address = args->apic_access_address; 5995 u32 reg = args->reg; 5996 u32 val = args->val; 5997 bool check_rd = args->check_rd; 5998 u32 (*virt_fn)(u32) = args->virt_fn; 5999 6000 if (op == TERMINATE) 6001 break; 6002 6003 if (op == APIC_OP_XAPIC_RD) { 6004 u32 ret = vmx_xapic_read(apic_access_address, reg); 6005 6006 if (check_rd) { 6007 u32 want = virt_fn(val); 6008 u32 got = virt_fn(ret); 6009 6010 report(got == want, 6011 "read 0x%x, expected 0x%x.", got, want); 6012 } 6013 } else if (op == APIC_OP_XAPIC_WR) { 6014 vmx_xapic_write(apic_access_address, reg, val); 6015 } 6016 6017 /* 6018 * The L1 should always execute a vmcall after it's done testing 6019 * an individual APIC operation. This helps to validate that the 6020 * L1 and L2 are in sync with each other, as expected. 6021 */ 6022 vmcall(); 6023 } 6024 } 6025 6026 static void test_xapic_rd( 6027 u32 reg, struct apic_reg_virt_expectation *expectation, 6028 u32 *apic_access_address, u32 *virtual_apic_page) 6029 { 6030 u32 val = expectation->val; 6031 u32 exit_reason_want = expectation->rd_exit_reason; 6032 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 6033 6034 report_prefix_pushf("xapic - reading 0x%03x", reg); 6035 6036 /* Configure guest to do an xapic read */ 6037 args->op = APIC_OP_XAPIC_RD; 6038 args->apic_access_address = apic_access_address; 6039 args->reg = reg; 6040 args->val = val; 6041 args->check_rd = exit_reason_want == VMX_VMCALL; 6042 args->virt_fn = expectation->virt_fn; 6043 6044 /* Setup virtual APIC page */ 6045 if (!expectation->virtualize_apic_accesses) { 6046 apic_access_address[apic_reg_index(reg)] = val; 6047 virtual_apic_page[apic_reg_index(reg)] = 0; 6048 } else if (exit_reason_want == VMX_VMCALL) { 6049 apic_access_address[apic_reg_index(reg)] = 0; 6050 virtual_apic_page[apic_reg_index(reg)] = val; 6051 } 6052 6053 /* Enter guest */ 6054 enter_guest(); 6055 6056 /* 6057 * Validate the behavior and 6058 * pass a magic value back to the guest. 6059 */ 6060 if (exit_reason_want == VMX_APIC_ACCESS) { 6061 u32 apic_page_offset = vmcs_read(EXI_QUALIFICATION) & 0xfff; 6062 6063 assert_exit_reason(exit_reason_want); 6064 report(apic_page_offset == reg, 6065 "got APIC access exit @ page offset 0x%03x, want 0x%03x", 6066 apic_page_offset, reg); 6067 skip_exit_insn(); 6068 6069 /* Reenter guest so it can consume/check rcx and exit again. */ 6070 enter_guest(); 6071 } else if (exit_reason_want != VMX_VMCALL) { 6072 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 6073 } 6074 6075 skip_exit_vmcall(); 6076 report_prefix_pop(); 6077 } 6078 6079 static void test_xapic_wr( 6080 u32 reg, struct apic_reg_virt_expectation *expectation, 6081 u32 *apic_access_address, u32 *virtual_apic_page) 6082 { 6083 u32 val = expectation->val; 6084 u32 exit_reason_want = expectation->wr_exit_reason; 6085 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 6086 bool virtualized = 6087 expectation->virtualize_apic_accesses && 6088 (exit_reason_want == VMX_APIC_WRITE || 6089 exit_reason_want == VMX_VMCALL); 6090 bool checked = false; 6091 6092 report_prefix_pushf("xapic - writing 0x%x to 0x%03x", val, reg); 6093 6094 /* Configure guest to do an xapic read */ 6095 args->op = APIC_OP_XAPIC_WR; 6096 args->apic_access_address = apic_access_address; 6097 args->reg = reg; 6098 args->val = val; 6099 6100 /* Setup virtual APIC page */ 6101 if (virtualized || !expectation->virtualize_apic_accesses) { 6102 apic_access_address[apic_reg_index(reg)] = 0; 6103 virtual_apic_page[apic_reg_index(reg)] = 0; 6104 } 6105 6106 /* Enter guest */ 6107 enter_guest(); 6108 6109 /* 6110 * Validate the behavior and 6111 * pass a magic value back to the guest. 6112 */ 6113 if (exit_reason_want == VMX_APIC_ACCESS) { 6114 u32 apic_page_offset = vmcs_read(EXI_QUALIFICATION) & 0xfff; 6115 6116 assert_exit_reason(exit_reason_want); 6117 report(apic_page_offset == reg, 6118 "got APIC access exit @ page offset 0x%03x, want 0x%03x", 6119 apic_page_offset, reg); 6120 skip_exit_insn(); 6121 6122 /* Reenter guest so it can consume/check rcx and exit again. */ 6123 enter_guest(); 6124 } else if (exit_reason_want == VMX_APIC_WRITE) { 6125 assert_exit_reason(exit_reason_want); 6126 report(virtual_apic_page[apic_reg_index(reg)] == val, 6127 "got APIC write exit @ page offset 0x%03x; val is 0x%x, want 0x%x", 6128 apic_reg_index(reg), 6129 virtual_apic_page[apic_reg_index(reg)], val); 6130 checked = true; 6131 6132 /* Reenter guest so it can consume/check rcx and exit again. */ 6133 enter_guest(); 6134 } else if (exit_reason_want != VMX_VMCALL) { 6135 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 6136 } 6137 6138 assert_exit_reason(VMX_VMCALL); 6139 if (virtualized && !checked) { 6140 u32 want = expectation->virt_fn(val); 6141 u32 got = virtual_apic_page[apic_reg_index(reg)]; 6142 got = expectation->virt_fn(got); 6143 6144 report(got == want, "exitless write; val is 0x%x, want 0x%x", 6145 got, want); 6146 } else if (!expectation->virtualize_apic_accesses && !checked) { 6147 u32 got = apic_access_address[apic_reg_index(reg)]; 6148 6149 report(got == val, 6150 "non-virtualized write; val is 0x%x, want 0x%x", got, 6151 val); 6152 } else if (!expectation->virtualize_apic_accesses && checked) { 6153 report_fail("Non-virtualized write was prematurely checked!"); 6154 } 6155 6156 skip_exit_vmcall(); 6157 report_prefix_pop(); 6158 } 6159 6160 enum Config_type { 6161 CONFIG_TYPE_GOOD, 6162 CONFIG_TYPE_UNSUPPORTED, 6163 CONFIG_TYPE_VMENTRY_FAILS_EARLY, 6164 }; 6165 6166 static enum Config_type configure_apic_reg_virt_test( 6167 struct apic_reg_virt_config *apic_reg_virt_config) 6168 { 6169 u32 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6170 u32 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6171 /* Configs where L2 entry fails early, due to invalid controls. */ 6172 bool use_tpr_shadow_incorrectly_off = 6173 !apic_reg_virt_config->use_tpr_shadow && 6174 (apic_reg_virt_config->apic_register_virtualization || 6175 apic_reg_virt_config->virtualize_x2apic_mode) && 6176 apic_reg_virt_config->activate_secondary_controls; 6177 bool virtualize_apic_accesses_incorrectly_on = 6178 apic_reg_virt_config->virtualize_apic_accesses && 6179 apic_reg_virt_config->virtualize_x2apic_mode && 6180 apic_reg_virt_config->activate_secondary_controls; 6181 bool vmentry_fails_early = 6182 use_tpr_shadow_incorrectly_off || 6183 virtualize_apic_accesses_incorrectly_on; 6184 6185 if (apic_reg_virt_config->activate_secondary_controls) { 6186 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 6187 printf("VM-execution control \"activate secondary controls\" NOT supported.\n"); 6188 return CONFIG_TYPE_UNSUPPORTED; 6189 } 6190 cpu_exec_ctrl0 |= CPU_SECONDARY; 6191 } else { 6192 cpu_exec_ctrl0 &= ~CPU_SECONDARY; 6193 } 6194 6195 if (apic_reg_virt_config->virtualize_apic_accesses) { 6196 if (!(ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES)) { 6197 printf("VM-execution control \"virtualize APIC accesses\" NOT supported.\n"); 6198 return CONFIG_TYPE_UNSUPPORTED; 6199 } 6200 cpu_exec_ctrl1 |= CPU_VIRT_APIC_ACCESSES; 6201 } else { 6202 cpu_exec_ctrl1 &= ~CPU_VIRT_APIC_ACCESSES; 6203 } 6204 6205 if (apic_reg_virt_config->use_tpr_shadow) { 6206 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) { 6207 printf("VM-execution control \"use TPR shadow\" NOT supported.\n"); 6208 return CONFIG_TYPE_UNSUPPORTED; 6209 } 6210 cpu_exec_ctrl0 |= CPU_TPR_SHADOW; 6211 } else { 6212 cpu_exec_ctrl0 &= ~CPU_TPR_SHADOW; 6213 } 6214 6215 if (apic_reg_virt_config->apic_register_virtualization) { 6216 if (!(ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT)) { 6217 printf("VM-execution control \"APIC-register virtualization\" NOT supported.\n"); 6218 return CONFIG_TYPE_UNSUPPORTED; 6219 } 6220 cpu_exec_ctrl1 |= CPU_APIC_REG_VIRT; 6221 } else { 6222 cpu_exec_ctrl1 &= ~CPU_APIC_REG_VIRT; 6223 } 6224 6225 if (apic_reg_virt_config->virtualize_x2apic_mode) { 6226 if (!(ctrl_cpu_rev[1].clr & CPU_VIRT_X2APIC)) { 6227 printf("VM-execution control \"virtualize x2APIC mode\" NOT supported.\n"); 6228 return CONFIG_TYPE_UNSUPPORTED; 6229 } 6230 cpu_exec_ctrl1 |= CPU_VIRT_X2APIC; 6231 } else { 6232 cpu_exec_ctrl1 &= ~CPU_VIRT_X2APIC; 6233 } 6234 6235 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6236 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6237 6238 if (vmentry_fails_early) 6239 return CONFIG_TYPE_VMENTRY_FAILS_EARLY; 6240 6241 return CONFIG_TYPE_GOOD; 6242 } 6243 6244 static bool cpu_has_apicv(void) 6245 { 6246 return ((ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT) && 6247 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 6248 (ctrl_pin_rev.clr & PIN_POST_INTR)); 6249 } 6250 6251 /* Validates APIC register access across valid virtualization configurations. */ 6252 static void apic_reg_virt_test(void) 6253 { 6254 u32 *apic_access_address; 6255 u32 *virtual_apic_page; 6256 u64 control; 6257 u64 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6258 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6259 int i; 6260 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 6261 6262 if (!cpu_has_apicv()) { 6263 report_skip(__func__); 6264 return; 6265 } 6266 6267 control = cpu_exec_ctrl1; 6268 control &= ~CPU_VINTD; 6269 vmcs_write(CPU_EXEC_CTRL1, control); 6270 6271 test_set_guest(apic_reg_virt_guest); 6272 6273 /* 6274 * From the SDM: The 1-setting of the "virtualize APIC accesses" 6275 * VM-execution is guaranteed to apply only if translations to the 6276 * APIC-access address use a 4-KByte page. 6277 */ 6278 apic_access_address = alloc_page(); 6279 force_4k_page(apic_access_address); 6280 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_address)); 6281 6282 virtual_apic_page = alloc_page(); 6283 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 6284 6285 for (i = 0; i < ARRAY_SIZE(apic_reg_tests); i++) { 6286 struct apic_reg_test *apic_reg_test = &apic_reg_tests[i]; 6287 struct apic_reg_virt_config *apic_reg_virt_config = 6288 &apic_reg_test->apic_reg_virt_config; 6289 enum Config_type config_type; 6290 u32 reg; 6291 6292 printf("--- %s test ---\n", apic_reg_test->name); 6293 config_type = 6294 configure_apic_reg_virt_test(apic_reg_virt_config); 6295 if (config_type == CONFIG_TYPE_UNSUPPORTED) { 6296 printf("Skip because of missing features.\n"); 6297 continue; 6298 } 6299 6300 if (config_type == CONFIG_TYPE_VMENTRY_FAILS_EARLY) { 6301 enter_guest_with_bad_controls(); 6302 continue; 6303 } 6304 6305 for (reg = 0; reg < PAGE_SIZE / sizeof(u32); reg += 0x10) { 6306 struct apic_reg_virt_expectation expectation = {}; 6307 bool ok; 6308 6309 ok = apic_reg_virt_exit_expectation( 6310 reg, apic_reg_virt_config, &expectation); 6311 if (!ok) { 6312 report_fail("Malformed test."); 6313 break; 6314 } 6315 6316 test_xapic_rd(reg, &expectation, apic_access_address, 6317 virtual_apic_page); 6318 test_xapic_wr(reg, &expectation, apic_access_address, 6319 virtual_apic_page); 6320 } 6321 } 6322 6323 /* Terminate the guest */ 6324 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6325 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6326 args->op = TERMINATE; 6327 enter_guest(); 6328 assert_exit_reason(VMX_VMCALL); 6329 } 6330 6331 struct virt_x2apic_mode_config { 6332 struct apic_reg_virt_config apic_reg_virt_config; 6333 bool virtual_interrupt_delivery; 6334 bool use_msr_bitmaps; 6335 bool disable_x2apic_msr_intercepts; 6336 bool disable_x2apic; 6337 }; 6338 6339 struct virt_x2apic_mode_test_case { 6340 const char *name; 6341 struct virt_x2apic_mode_config virt_x2apic_mode_config; 6342 }; 6343 6344 enum Virt_x2apic_mode_behavior_type { 6345 X2APIC_ACCESS_VIRTUALIZED, 6346 X2APIC_ACCESS_PASSED_THROUGH, 6347 X2APIC_ACCESS_TRIGGERS_GP, 6348 }; 6349 6350 struct virt_x2apic_mode_expectation { 6351 enum Reason rd_exit_reason; 6352 enum Reason wr_exit_reason; 6353 6354 /* 6355 * RDMSR and WRMSR handle 64-bit values. However, except for ICR, all of 6356 * the x2APIC registers are 32 bits. Notice: 6357 * 1. vmx_x2apic_read() clears the upper 32 bits for 32-bit registers. 6358 * 2. vmx_x2apic_write() expects the val arg to be well-formed. 6359 */ 6360 u64 rd_val; 6361 u64 wr_val; 6362 6363 /* 6364 * Compares input to virtualized output; 6365 * 1st arg is pointer to return expected virtualization output. 6366 */ 6367 u64 (*virt_fn)(u64); 6368 6369 enum Virt_x2apic_mode_behavior_type rd_behavior; 6370 enum Virt_x2apic_mode_behavior_type wr_behavior; 6371 bool wr_only; 6372 }; 6373 6374 static u64 virt_x2apic_mode_identity(u64 val) 6375 { 6376 return val; 6377 } 6378 6379 static u64 virt_x2apic_mode_nibble1(u64 val) 6380 { 6381 return val & 0xf0; 6382 } 6383 6384 static void virt_x2apic_mode_rd_expectation( 6385 u32 reg, bool virt_x2apic_mode_on, bool disable_x2apic, 6386 bool apic_register_virtualization, bool virtual_interrupt_delivery, 6387 struct virt_x2apic_mode_expectation *expectation) 6388 { 6389 bool readable = 6390 !x2apic_reg_reserved(reg) && 6391 reg != APIC_EOI; 6392 6393 expectation->rd_exit_reason = VMX_VMCALL; 6394 expectation->virt_fn = virt_x2apic_mode_identity; 6395 if (virt_x2apic_mode_on && apic_register_virtualization) { 6396 expectation->rd_val = MAGIC_VAL_1; 6397 if (reg == APIC_PROCPRI && virtual_interrupt_delivery) 6398 expectation->virt_fn = virt_x2apic_mode_nibble1; 6399 else if (reg == APIC_TASKPRI) 6400 expectation->virt_fn = virt_x2apic_mode_nibble1; 6401 expectation->rd_behavior = X2APIC_ACCESS_VIRTUALIZED; 6402 } else if (virt_x2apic_mode_on && !apic_register_virtualization && 6403 reg == APIC_TASKPRI) { 6404 expectation->rd_val = MAGIC_VAL_1; 6405 expectation->virt_fn = virt_x2apic_mode_nibble1; 6406 expectation->rd_behavior = X2APIC_ACCESS_VIRTUALIZED; 6407 } else if (!disable_x2apic && readable) { 6408 expectation->rd_val = apic_read(reg); 6409 expectation->rd_behavior = X2APIC_ACCESS_PASSED_THROUGH; 6410 } else { 6411 expectation->rd_behavior = X2APIC_ACCESS_TRIGGERS_GP; 6412 } 6413 } 6414 6415 /* 6416 * get_x2apic_wr_val() creates an innocuous write value for an x2APIC register. 6417 * 6418 * For writable registers, get_x2apic_wr_val() deposits the write value into the 6419 * val pointer arg and returns true. For non-writable registers, val is not 6420 * modified and get_x2apic_wr_val() returns false. 6421 */ 6422 static bool get_x2apic_wr_val(u32 reg, u64 *val) 6423 { 6424 switch (reg) { 6425 case APIC_TASKPRI: 6426 /* Bits 31:8 are reserved. */ 6427 *val &= 0xff; 6428 break; 6429 case APIC_EOI: 6430 case APIC_ESR: 6431 case APIC_TMICT: 6432 /* 6433 * EOI, ESR: WRMSR of a non-zero value causes #GP(0). 6434 * TMICT: A write of 0 to the initial-count register effectively 6435 * stops the local APIC timer, in both one-shot and 6436 * periodic mode. 6437 */ 6438 *val = 0; 6439 break; 6440 case APIC_SPIV: 6441 case APIC_LVTT: 6442 case APIC_LVTTHMR: 6443 case APIC_LVTPC: 6444 case APIC_LVT0: 6445 case APIC_LVT1: 6446 case APIC_LVTERR: 6447 case APIC_TDCR: 6448 /* 6449 * To avoid writing a 1 to a reserved bit or causing some other 6450 * unintended side effect, read the current value and use it as 6451 * the write value. 6452 */ 6453 *val = apic_read(reg); 6454 break; 6455 case APIC_CMCI: 6456 if (!apic_lvt_entry_supported(6)) 6457 return false; 6458 *val = apic_read(reg); 6459 break; 6460 case APIC_ICR: 6461 *val = 0x40000 | 0xf1; 6462 break; 6463 case APIC_SELF_IPI: 6464 /* 6465 * With special processing (i.e., virtualize x2APIC mode + 6466 * virtual interrupt delivery), writing zero causes an 6467 * APIC-write VM exit. We plan to add a test for enabling 6468 * "virtual-interrupt delivery" in VMCS12, and that's where we 6469 * will test a self IPI with special processing. 6470 */ 6471 *val = 0x0; 6472 break; 6473 default: 6474 return false; 6475 } 6476 6477 return true; 6478 } 6479 6480 static bool special_processing_applies(u32 reg, u64 *val, 6481 bool virt_int_delivery) 6482 { 6483 bool special_processing = 6484 (reg == APIC_TASKPRI) || 6485 (virt_int_delivery && 6486 (reg == APIC_EOI || reg == APIC_SELF_IPI)); 6487 6488 if (special_processing) { 6489 TEST_ASSERT(get_x2apic_wr_val(reg, val)); 6490 return true; 6491 } 6492 6493 return false; 6494 } 6495 6496 static void virt_x2apic_mode_wr_expectation( 6497 u32 reg, bool virt_x2apic_mode_on, bool disable_x2apic, 6498 bool virt_int_delivery, 6499 struct virt_x2apic_mode_expectation *expectation) 6500 { 6501 expectation->wr_exit_reason = VMX_VMCALL; 6502 expectation->wr_val = MAGIC_VAL_1; 6503 expectation->wr_only = false; 6504 6505 if (virt_x2apic_mode_on && 6506 special_processing_applies(reg, &expectation->wr_val, 6507 virt_int_delivery)) { 6508 expectation->wr_behavior = X2APIC_ACCESS_VIRTUALIZED; 6509 if (reg == APIC_SELF_IPI) 6510 expectation->wr_exit_reason = VMX_APIC_WRITE; 6511 } else if (!disable_x2apic && 6512 get_x2apic_wr_val(reg, &expectation->wr_val)) { 6513 expectation->wr_behavior = X2APIC_ACCESS_PASSED_THROUGH; 6514 if (reg == APIC_EOI || reg == APIC_SELF_IPI) 6515 expectation->wr_only = true; 6516 if (reg == APIC_ICR) 6517 expectation->wr_exit_reason = VMX_EXTINT; 6518 } else { 6519 expectation->wr_behavior = X2APIC_ACCESS_TRIGGERS_GP; 6520 /* 6521 * Writing 1 to a reserved bit triggers a #GP. 6522 * Thus, set the write value to 0, which seems 6523 * the most likely to detect a missed #GP. 6524 */ 6525 expectation->wr_val = 0; 6526 } 6527 } 6528 6529 static void virt_x2apic_mode_exit_expectation( 6530 u32 reg, struct virt_x2apic_mode_config *config, 6531 struct virt_x2apic_mode_expectation *expectation) 6532 { 6533 struct apic_reg_virt_config *base_config = 6534 &config->apic_reg_virt_config; 6535 bool virt_x2apic_mode_on = 6536 base_config->virtualize_x2apic_mode && 6537 config->use_msr_bitmaps && 6538 config->disable_x2apic_msr_intercepts && 6539 base_config->activate_secondary_controls; 6540 6541 virt_x2apic_mode_wr_expectation( 6542 reg, virt_x2apic_mode_on, config->disable_x2apic, 6543 config->virtual_interrupt_delivery, expectation); 6544 virt_x2apic_mode_rd_expectation( 6545 reg, virt_x2apic_mode_on, config->disable_x2apic, 6546 base_config->apic_register_virtualization, 6547 config->virtual_interrupt_delivery, expectation); 6548 } 6549 6550 struct virt_x2apic_mode_test_case virt_x2apic_mode_tests[] = { 6551 /* 6552 * Baseline "virtualize x2APIC mode" configuration: 6553 * - virtualize x2APIC mode 6554 * - virtual-interrupt delivery 6555 * - APIC-register virtualization 6556 * - x2APIC MSR intercepts disabled 6557 * 6558 * Reads come from virtual APIC page, special processing applies to 6559 * VTPR, EOI, and SELF IPI, and all other writes pass through to L1 6560 * APIC. 6561 */ 6562 { 6563 .name = "Baseline", 6564 .virt_x2apic_mode_config = { 6565 .virtual_interrupt_delivery = true, 6566 .use_msr_bitmaps = true, 6567 .disable_x2apic_msr_intercepts = true, 6568 .disable_x2apic = false, 6569 .apic_reg_virt_config = { 6570 .apic_register_virtualization = true, 6571 .use_tpr_shadow = true, 6572 .virtualize_apic_accesses = false, 6573 .virtualize_x2apic_mode = true, 6574 .activate_secondary_controls = true, 6575 }, 6576 }, 6577 }, 6578 { 6579 .name = "Baseline w/ x2apic disabled", 6580 .virt_x2apic_mode_config = { 6581 .virtual_interrupt_delivery = true, 6582 .use_msr_bitmaps = true, 6583 .disable_x2apic_msr_intercepts = true, 6584 .disable_x2apic = true, 6585 .apic_reg_virt_config = { 6586 .apic_register_virtualization = true, 6587 .use_tpr_shadow = true, 6588 .virtualize_apic_accesses = false, 6589 .virtualize_x2apic_mode = true, 6590 .activate_secondary_controls = true, 6591 }, 6592 }, 6593 }, 6594 6595 /* 6596 * Baseline, minus virtual-interrupt delivery. Reads come from virtual 6597 * APIC page, special processing applies to VTPR, and all other writes 6598 * pass through to L1 APIC. 6599 */ 6600 { 6601 .name = "Baseline - virtual interrupt delivery", 6602 .virt_x2apic_mode_config = { 6603 .virtual_interrupt_delivery = false, 6604 .use_msr_bitmaps = true, 6605 .disable_x2apic_msr_intercepts = true, 6606 .disable_x2apic = false, 6607 .apic_reg_virt_config = { 6608 .apic_register_virtualization = true, 6609 .use_tpr_shadow = true, 6610 .virtualize_apic_accesses = false, 6611 .virtualize_x2apic_mode = true, 6612 .activate_secondary_controls = true, 6613 }, 6614 }, 6615 }, 6616 6617 /* 6618 * Baseline, minus APIC-register virtualization. x2APIC reads pass 6619 * through to L1's APIC, unless reading VTPR 6620 */ 6621 { 6622 .name = "Virtualize x2APIC mode, no APIC reg virt", 6623 .virt_x2apic_mode_config = { 6624 .virtual_interrupt_delivery = true, 6625 .use_msr_bitmaps = true, 6626 .disable_x2apic_msr_intercepts = true, 6627 .disable_x2apic = false, 6628 .apic_reg_virt_config = { 6629 .apic_register_virtualization = false, 6630 .use_tpr_shadow = true, 6631 .virtualize_apic_accesses = false, 6632 .virtualize_x2apic_mode = true, 6633 .activate_secondary_controls = true, 6634 }, 6635 }, 6636 }, 6637 { 6638 .name = "Virtualize x2APIC mode, no APIC reg virt, x2APIC off", 6639 .virt_x2apic_mode_config = { 6640 .virtual_interrupt_delivery = true, 6641 .use_msr_bitmaps = true, 6642 .disable_x2apic_msr_intercepts = true, 6643 .disable_x2apic = true, 6644 .apic_reg_virt_config = { 6645 .apic_register_virtualization = false, 6646 .use_tpr_shadow = true, 6647 .virtualize_apic_accesses = false, 6648 .virtualize_x2apic_mode = true, 6649 .activate_secondary_controls = true, 6650 }, 6651 }, 6652 }, 6653 6654 /* 6655 * Enable "virtualize x2APIC mode" and "APIC-register virtualization", 6656 * and disable intercepts for the x2APIC MSRs, but fail to enable 6657 * "activate secondary controls" (i.e. L2 gets access to L1's x2APIC 6658 * MSRs). 6659 */ 6660 { 6661 .name = "Fail to enable activate secondary controls", 6662 .virt_x2apic_mode_config = { 6663 .virtual_interrupt_delivery = true, 6664 .use_msr_bitmaps = true, 6665 .disable_x2apic_msr_intercepts = true, 6666 .disable_x2apic = false, 6667 .apic_reg_virt_config = { 6668 .apic_register_virtualization = true, 6669 .use_tpr_shadow = true, 6670 .virtualize_apic_accesses = false, 6671 .virtualize_x2apic_mode = true, 6672 .activate_secondary_controls = false, 6673 }, 6674 }, 6675 }, 6676 6677 /* 6678 * Enable "APIC-register virtualization" and enable "activate secondary 6679 * controls" and disable intercepts for the x2APIC MSRs, but do not 6680 * enable the "virtualize x2APIC mode" VM-execution control (i.e. L2 6681 * gets access to L1's x2APIC MSRs). 6682 */ 6683 { 6684 .name = "Fail to enable virtualize x2APIC mode", 6685 .virt_x2apic_mode_config = { 6686 .virtual_interrupt_delivery = true, 6687 .use_msr_bitmaps = true, 6688 .disable_x2apic_msr_intercepts = true, 6689 .disable_x2apic = false, 6690 .apic_reg_virt_config = { 6691 .apic_register_virtualization = true, 6692 .use_tpr_shadow = true, 6693 .virtualize_apic_accesses = false, 6694 .virtualize_x2apic_mode = false, 6695 .activate_secondary_controls = true, 6696 }, 6697 }, 6698 }, 6699 6700 /* 6701 * Disable "Virtualize x2APIC mode", disable x2APIC MSR intercepts, and 6702 * enable "APIC-register virtualization" --> L2 gets L1's x2APIC MSRs. 6703 */ 6704 { 6705 .name = "Baseline", 6706 .virt_x2apic_mode_config = { 6707 .virtual_interrupt_delivery = true, 6708 .use_msr_bitmaps = true, 6709 .disable_x2apic_msr_intercepts = true, 6710 .disable_x2apic = false, 6711 .apic_reg_virt_config = { 6712 .apic_register_virtualization = true, 6713 .use_tpr_shadow = true, 6714 .virtualize_apic_accesses = false, 6715 .virtualize_x2apic_mode = false, 6716 .activate_secondary_controls = true, 6717 }, 6718 }, 6719 }, 6720 }; 6721 6722 enum X2apic_op { 6723 X2APIC_OP_RD, 6724 X2APIC_OP_WR, 6725 X2APIC_TERMINATE, 6726 }; 6727 6728 static u64 vmx_x2apic_read(u32 reg) 6729 { 6730 u32 msr_addr = x2apic_msr(reg); 6731 u64 val; 6732 6733 val = rdmsr(msr_addr); 6734 6735 return val; 6736 } 6737 6738 static void vmx_x2apic_write(u32 reg, u64 val) 6739 { 6740 u32 msr_addr = x2apic_msr(reg); 6741 6742 wrmsr(msr_addr, val); 6743 } 6744 6745 struct virt_x2apic_mode_guest_args { 6746 enum X2apic_op op; 6747 u32 reg; 6748 u64 val; 6749 bool should_gp; 6750 u64 (*virt_fn)(u64); 6751 } virt_x2apic_mode_guest_args; 6752 6753 static volatile bool handle_x2apic_gp_ran; 6754 static volatile u32 handle_x2apic_gp_insn_len; 6755 static void handle_x2apic_gp(struct ex_regs *regs) 6756 { 6757 handle_x2apic_gp_ran = true; 6758 regs->rip += handle_x2apic_gp_insn_len; 6759 } 6760 6761 static handler setup_x2apic_gp_handler(void) 6762 { 6763 handler old_handler; 6764 6765 old_handler = handle_exception(GP_VECTOR, handle_x2apic_gp); 6766 /* RDMSR and WRMSR are both 2 bytes, assuming no prefixes. */ 6767 handle_x2apic_gp_insn_len = 2; 6768 6769 return old_handler; 6770 } 6771 6772 static void teardown_x2apic_gp_handler(handler old_handler) 6773 { 6774 handle_exception(GP_VECTOR, old_handler); 6775 6776 /* 6777 * Defensively reset instruction length, so that if the handler is 6778 * incorrectly used, it will loop infinitely, rather than run off into 6779 * la la land. 6780 */ 6781 handle_x2apic_gp_insn_len = 0; 6782 handle_x2apic_gp_ran = false; 6783 } 6784 6785 static void virt_x2apic_mode_guest(void) 6786 { 6787 volatile struct virt_x2apic_mode_guest_args *args = 6788 &virt_x2apic_mode_guest_args; 6789 6790 for (;;) { 6791 enum X2apic_op op = args->op; 6792 u32 reg = args->reg; 6793 u64 val = args->val; 6794 bool should_gp = args->should_gp; 6795 u64 (*virt_fn)(u64) = args->virt_fn; 6796 handler old_handler; 6797 6798 if (op == X2APIC_TERMINATE) 6799 break; 6800 6801 if (should_gp) { 6802 TEST_ASSERT(!handle_x2apic_gp_ran); 6803 old_handler = setup_x2apic_gp_handler(); 6804 } 6805 6806 if (op == X2APIC_OP_RD) { 6807 u64 ret = vmx_x2apic_read(reg); 6808 6809 if (!should_gp) { 6810 u64 want = virt_fn(val); 6811 u64 got = virt_fn(ret); 6812 6813 report(got == want, 6814 "APIC read; got 0x%lx, want 0x%lx.", 6815 got, want); 6816 } 6817 } else if (op == X2APIC_OP_WR) { 6818 vmx_x2apic_write(reg, val); 6819 } 6820 6821 if (should_gp) { 6822 report(handle_x2apic_gp_ran, 6823 "x2APIC op triggered GP."); 6824 teardown_x2apic_gp_handler(old_handler); 6825 } 6826 6827 /* 6828 * The L1 should always execute a vmcall after it's done testing 6829 * an individual APIC operation. This helps to validate that the 6830 * L1 and L2 are in sync with each other, as expected. 6831 */ 6832 vmcall(); 6833 } 6834 } 6835 6836 static void test_x2apic_rd( 6837 u32 reg, struct virt_x2apic_mode_expectation *expectation, 6838 u32 *virtual_apic_page) 6839 { 6840 u64 val = expectation->rd_val; 6841 u32 exit_reason_want = expectation->rd_exit_reason; 6842 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6843 6844 report_prefix_pushf("x2apic - reading 0x%03x", reg); 6845 6846 /* Configure guest to do an x2apic read */ 6847 args->op = X2APIC_OP_RD; 6848 args->reg = reg; 6849 args->val = val; 6850 args->should_gp = expectation->rd_behavior == X2APIC_ACCESS_TRIGGERS_GP; 6851 args->virt_fn = expectation->virt_fn; 6852 6853 /* Setup virtual APIC page */ 6854 if (expectation->rd_behavior == X2APIC_ACCESS_VIRTUALIZED) 6855 virtual_apic_page[apic_reg_index(reg)] = (u32)val; 6856 6857 /* Enter guest */ 6858 enter_guest(); 6859 6860 if (exit_reason_want != VMX_VMCALL) { 6861 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 6862 } 6863 6864 skip_exit_vmcall(); 6865 report_prefix_pop(); 6866 } 6867 6868 static volatile bool handle_x2apic_ipi_ran; 6869 static void handle_x2apic_ipi(isr_regs_t *regs) 6870 { 6871 handle_x2apic_ipi_ran = true; 6872 eoi(); 6873 } 6874 6875 static void test_x2apic_wr( 6876 u32 reg, struct virt_x2apic_mode_expectation *expectation, 6877 u32 *virtual_apic_page) 6878 { 6879 u64 val = expectation->wr_val; 6880 u32 exit_reason_want = expectation->wr_exit_reason; 6881 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6882 int ipi_vector = 0xf1; 6883 u32 restore_val = 0; 6884 6885 report_prefix_pushf("x2apic - writing 0x%lx to 0x%03x", val, reg); 6886 6887 /* Configure guest to do an x2apic read */ 6888 args->op = X2APIC_OP_WR; 6889 args->reg = reg; 6890 args->val = val; 6891 args->should_gp = expectation->wr_behavior == X2APIC_ACCESS_TRIGGERS_GP; 6892 6893 /* Setup virtual APIC page */ 6894 if (expectation->wr_behavior == X2APIC_ACCESS_VIRTUALIZED) 6895 virtual_apic_page[apic_reg_index(reg)] = 0; 6896 if (expectation->wr_behavior == X2APIC_ACCESS_PASSED_THROUGH && !expectation->wr_only) 6897 restore_val = apic_read(reg); 6898 6899 /* Setup IPI handler */ 6900 handle_x2apic_ipi_ran = false; 6901 handle_irq(ipi_vector, handle_x2apic_ipi); 6902 6903 /* Enter guest */ 6904 enter_guest(); 6905 6906 /* 6907 * Validate the behavior and 6908 * pass a magic value back to the guest. 6909 */ 6910 if (exit_reason_want == VMX_EXTINT) { 6911 assert_exit_reason(exit_reason_want); 6912 6913 /* Clear the external interrupt. */ 6914 irq_enable(); 6915 asm volatile ("nop"); 6916 irq_disable(); 6917 report(handle_x2apic_ipi_ran, 6918 "Got pending interrupt after IRQ enabled."); 6919 6920 enter_guest(); 6921 } else if (exit_reason_want == VMX_APIC_WRITE) { 6922 assert_exit_reason(exit_reason_want); 6923 report(virtual_apic_page[apic_reg_index(reg)] == val, 6924 "got APIC write exit @ page offset 0x%03x; val is 0x%x, want 0x%lx", 6925 apic_reg_index(reg), 6926 virtual_apic_page[apic_reg_index(reg)], val); 6927 6928 /* Reenter guest so it can consume/check rcx and exit again. */ 6929 enter_guest(); 6930 } else if (exit_reason_want != VMX_VMCALL) { 6931 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 6932 } 6933 6934 assert_exit_reason(VMX_VMCALL); 6935 if (expectation->wr_behavior == X2APIC_ACCESS_VIRTUALIZED) { 6936 u64 want = val; 6937 u32 got = virtual_apic_page[apic_reg_index(reg)]; 6938 6939 report(got == want, "x2APIC write; got 0x%x, want 0x%lx", got, 6940 want); 6941 } else if (expectation->wr_behavior == X2APIC_ACCESS_PASSED_THROUGH) { 6942 if (!expectation->wr_only) { 6943 u32 got = apic_read(reg); 6944 bool ok; 6945 6946 /* 6947 * When L1's TPR is passed through to L2, the lower 6948 * nibble can be lost. For example, if L2 executes 6949 * WRMSR(0x808, 0x78), then, L1 might read 0x70. 6950 * 6951 * Here's how the lower nibble can get lost: 6952 * 1. L2 executes WRMSR(0x808, 0x78). 6953 * 2. L2 exits to L0 with a WRMSR exit. 6954 * 3. L0 emulates WRMSR, by writing L1's TPR. 6955 * 4. L0 re-enters L2. 6956 * 5. L2 exits to L0 (reason doesn't matter). 6957 * 6. L0 reflects L2's exit to L1. 6958 * 7. Before entering L1, L0 exits to user-space 6959 * (e.g., to satisfy TPR access reporting). 6960 * 8. User-space executes KVM_SET_REGS ioctl, which 6961 * clears the lower nibble of L1's TPR. 6962 */ 6963 if (reg == APIC_TASKPRI) { 6964 got = apic_virt_nibble1(got); 6965 val = apic_virt_nibble1(val); 6966 } 6967 6968 ok = got == val; 6969 report(ok, 6970 "non-virtualized write; val is 0x%x, want 0x%lx", 6971 got, val); 6972 apic_write(reg, restore_val); 6973 } else { 6974 report(true, "non-virtualized and write-only OK"); 6975 } 6976 } 6977 skip_exit_insn(); 6978 6979 report_prefix_pop(); 6980 } 6981 6982 static enum Config_type configure_virt_x2apic_mode_test( 6983 struct virt_x2apic_mode_config *virt_x2apic_mode_config, 6984 u8 *msr_bitmap_page) 6985 { 6986 int msr; 6987 u32 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6988 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6989 6990 /* x2apic-specific VMCS config */ 6991 if (virt_x2apic_mode_config->use_msr_bitmaps) { 6992 /* virt_x2apic_mode_test() checks for MSR bitmaps support */ 6993 cpu_exec_ctrl0 |= CPU_MSR_BITMAP; 6994 } else { 6995 cpu_exec_ctrl0 &= ~CPU_MSR_BITMAP; 6996 } 6997 6998 if (virt_x2apic_mode_config->virtual_interrupt_delivery) { 6999 if (!(ctrl_cpu_rev[1].clr & CPU_VINTD)) { 7000 report_skip("VM-execution control \"virtual-interrupt delivery\" NOT supported.\n"); 7001 return CONFIG_TYPE_UNSUPPORTED; 7002 } 7003 cpu_exec_ctrl1 |= CPU_VINTD; 7004 } else { 7005 cpu_exec_ctrl1 &= ~CPU_VINTD; 7006 } 7007 7008 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 7009 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 7010 7011 /* x2APIC MSR intercepts are usually off for "Virtualize x2APIC mode" */ 7012 for (msr = 0x800; msr <= 0x8ff; msr++) { 7013 if (virt_x2apic_mode_config->disable_x2apic_msr_intercepts) { 7014 clear_bit(msr, msr_bitmap_page + 0x000); 7015 clear_bit(msr, msr_bitmap_page + 0x800); 7016 } else { 7017 set_bit(msr, msr_bitmap_page + 0x000); 7018 set_bit(msr, msr_bitmap_page + 0x800); 7019 } 7020 } 7021 7022 /* x2APIC mode can impact virtualization */ 7023 reset_apic(); 7024 if (!virt_x2apic_mode_config->disable_x2apic) 7025 enable_x2apic(); 7026 7027 return configure_apic_reg_virt_test( 7028 &virt_x2apic_mode_config->apic_reg_virt_config); 7029 } 7030 7031 static void virt_x2apic_mode_test(void) 7032 { 7033 u32 *virtual_apic_page; 7034 u8 *msr_bitmap_page; 7035 u64 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 7036 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 7037 int i; 7038 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 7039 7040 if (!cpu_has_apicv()) { 7041 report_skip(__func__); 7042 return; 7043 } 7044 7045 /* 7046 * This is to exercise an issue in KVM's logic to merge L0's and L1's 7047 * MSR bitmaps. Previously, an L1 could get at L0's x2APIC MSRs by 7048 * writing the IA32_SPEC_CTRL MSR or the IA32_PRED_CMD MSRs. KVM would 7049 * then proceed to manipulate the MSR bitmaps, as if VMCS12 had the 7050 * "Virtualize x2APIC mod" control set, even when it didn't. 7051 */ 7052 if (has_spec_ctrl()) 7053 wrmsr(MSR_IA32_SPEC_CTRL, 1); 7054 7055 /* 7056 * Check that VMCS12 supports: 7057 * - "Virtual-APIC address", indicated by "use TPR shadow" 7058 * - "MSR-bitmap address", indicated by "use MSR bitmaps" 7059 */ 7060 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) { 7061 report_skip("VM-execution control \"use TPR shadow\" NOT supported.\n"); 7062 return; 7063 } else if (!(ctrl_cpu_rev[0].clr & CPU_MSR_BITMAP)) { 7064 report_skip("VM-execution control \"use MSR bitmaps\" NOT supported.\n"); 7065 return; 7066 } 7067 7068 test_set_guest(virt_x2apic_mode_guest); 7069 7070 virtual_apic_page = alloc_page(); 7071 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 7072 7073 msr_bitmap_page = alloc_page(); 7074 memset(msr_bitmap_page, 0xff, PAGE_SIZE); 7075 vmcs_write(MSR_BITMAP, virt_to_phys(msr_bitmap_page)); 7076 7077 for (i = 0; i < ARRAY_SIZE(virt_x2apic_mode_tests); i++) { 7078 struct virt_x2apic_mode_test_case *virt_x2apic_mode_test_case = 7079 &virt_x2apic_mode_tests[i]; 7080 struct virt_x2apic_mode_config *virt_x2apic_mode_config = 7081 &virt_x2apic_mode_test_case->virt_x2apic_mode_config; 7082 enum Config_type config_type; 7083 u32 reg; 7084 7085 printf("--- %s test ---\n", virt_x2apic_mode_test_case->name); 7086 config_type = 7087 configure_virt_x2apic_mode_test(virt_x2apic_mode_config, 7088 msr_bitmap_page); 7089 if (config_type == CONFIG_TYPE_UNSUPPORTED) { 7090 report_skip("Skip because of missing features.\n"); 7091 continue; 7092 } else if (config_type == CONFIG_TYPE_VMENTRY_FAILS_EARLY) { 7093 enter_guest_with_bad_controls(); 7094 continue; 7095 } 7096 7097 for (reg = 0; reg < PAGE_SIZE / sizeof(u32); reg += 0x10) { 7098 struct virt_x2apic_mode_expectation expectation; 7099 7100 virt_x2apic_mode_exit_expectation( 7101 reg, virt_x2apic_mode_config, &expectation); 7102 7103 test_x2apic_rd(reg, &expectation, virtual_apic_page); 7104 test_x2apic_wr(reg, &expectation, virtual_apic_page); 7105 } 7106 } 7107 7108 7109 /* Terminate the guest */ 7110 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 7111 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 7112 args->op = X2APIC_TERMINATE; 7113 enter_guest(); 7114 assert_exit_reason(VMX_VMCALL); 7115 } 7116 7117 static void test_ctl_reg(const char *cr_name, u64 cr, u64 fixed0, u64 fixed1) 7118 { 7119 u64 val; 7120 u64 cr_saved = vmcs_read(cr); 7121 int i; 7122 7123 val = fixed0 & fixed1; 7124 if (cr == HOST_CR4) 7125 vmcs_write(cr, val | X86_CR4_PAE); 7126 else 7127 vmcs_write(cr, val); 7128 report_prefix_pushf("%s %lx", cr_name, val); 7129 if (val == fixed0) 7130 test_vmx_vmlaunch(0); 7131 else 7132 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7133 report_prefix_pop(); 7134 7135 for (i = 0; i < 64; i++) { 7136 7137 /* Set a bit when the corresponding bit in fixed1 is 0 */ 7138 if ((fixed1 & (1ull << i)) == 0) { 7139 if (cr == HOST_CR4 && ((1ull << i) & X86_CR4_SMEP || 7140 (1ull << i) & X86_CR4_SMAP)) 7141 continue; 7142 7143 vmcs_write(cr, cr_saved | (1ull << i)); 7144 report_prefix_pushf("%s %llx", cr_name, 7145 cr_saved | (1ull << i)); 7146 test_vmx_vmlaunch( 7147 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7148 report_prefix_pop(); 7149 } 7150 7151 /* Unset a bit when the corresponding bit in fixed0 is 1 */ 7152 if (fixed0 & (1ull << i)) { 7153 vmcs_write(cr, cr_saved & ~(1ull << i)); 7154 report_prefix_pushf("%s %llx", cr_name, 7155 cr_saved & ~(1ull << i)); 7156 test_vmx_vmlaunch( 7157 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7158 report_prefix_pop(); 7159 } 7160 } 7161 7162 vmcs_write(cr, cr_saved); 7163 } 7164 7165 /* 7166 * 1. The CR0 field must not set any bit to a value not supported in VMX 7167 * operation. 7168 * 2. The CR4 field must not set any bit to a value not supported in VMX 7169 * operation. 7170 * 3. On processors that support Intel 64 architecture, the CR3 field must 7171 * be such that bits 63:52 and bits in the range 51:32 beyond the 7172 * processor's physical-address width must be 0. 7173 * 7174 * [Intel SDM] 7175 */ 7176 static void test_host_ctl_regs(void) 7177 { 7178 u64 fixed0, fixed1, cr3, cr3_saved; 7179 int i; 7180 7181 /* Test CR0 */ 7182 fixed0 = rdmsr(MSR_IA32_VMX_CR0_FIXED0); 7183 fixed1 = rdmsr(MSR_IA32_VMX_CR0_FIXED1); 7184 test_ctl_reg("HOST_CR0", HOST_CR0, fixed0, fixed1); 7185 7186 /* Test CR4 */ 7187 fixed0 = rdmsr(MSR_IA32_VMX_CR4_FIXED0); 7188 fixed1 = rdmsr(MSR_IA32_VMX_CR4_FIXED1) & 7189 ~(X86_CR4_SMEP | X86_CR4_SMAP); 7190 test_ctl_reg("HOST_CR4", HOST_CR4, fixed0, fixed1); 7191 7192 /* Test CR3 */ 7193 cr3_saved = vmcs_read(HOST_CR3); 7194 for (i = cpuid_maxphyaddr(); i < 64; i++) { 7195 cr3 = cr3_saved | (1ul << i); 7196 vmcs_write(HOST_CR3, cr3); 7197 report_prefix_pushf("HOST_CR3 %lx", cr3); 7198 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7199 report_prefix_pop(); 7200 } 7201 7202 vmcs_write(HOST_CR3, cr3_saved); 7203 } 7204 7205 static void test_efer_vmlaunch(u32 fld, bool ok) 7206 { 7207 if (fld == HOST_EFER) { 7208 if (ok) 7209 test_vmx_vmlaunch(0); 7210 else 7211 test_vmx_vmlaunch2(VMXERR_ENTRY_INVALID_CONTROL_FIELD, 7212 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7213 } else { 7214 test_guest_state("EFER test", !ok, GUEST_EFER, "GUEST_EFER"); 7215 } 7216 } 7217 7218 static void test_efer_one(u32 fld, const char * fld_name, u64 efer, 7219 u32 ctrl_fld, u64 ctrl, 7220 int i, const char *efer_bit_name) 7221 { 7222 bool ok; 7223 7224 ok = true; 7225 if (ctrl_fld == EXI_CONTROLS && (ctrl & EXI_LOAD_EFER)) { 7226 if (!!(efer & EFER_LMA) != !!(ctrl & EXI_HOST_64)) 7227 ok = false; 7228 if (!!(efer & EFER_LME) != !!(ctrl & EXI_HOST_64)) 7229 ok = false; 7230 } 7231 if (ctrl_fld == ENT_CONTROLS && (ctrl & ENT_LOAD_EFER)) { 7232 /* Check LMA too since CR0.PG is set. */ 7233 if (!!(efer & EFER_LMA) != !!(ctrl & ENT_GUEST_64)) 7234 ok = false; 7235 if (!!(efer & EFER_LME) != !!(ctrl & ENT_GUEST_64)) 7236 ok = false; 7237 } 7238 7239 /* 7240 * Skip the test if it would enter the guest in 32-bit mode. 7241 * Perhaps write the test in assembly and make sure it 7242 * can be run in either mode? 7243 */ 7244 if (fld == GUEST_EFER && ok && !(ctrl & ENT_GUEST_64)) 7245 return; 7246 7247 vmcs_write(ctrl_fld, ctrl); 7248 vmcs_write(fld, efer); 7249 report_prefix_pushf("%s %s bit turned %s, controls %s", 7250 fld_name, efer_bit_name, 7251 (i & 1) ? "on" : "off", 7252 (i & 2) ? "on" : "off"); 7253 7254 test_efer_vmlaunch(fld, ok); 7255 report_prefix_pop(); 7256 } 7257 7258 static void test_efer_bit(u32 fld, const char * fld_name, 7259 u32 ctrl_fld, u64 ctrl_bit, u64 efer_bit, 7260 const char *efer_bit_name) 7261 { 7262 u64 efer_saved = vmcs_read(fld); 7263 u32 ctrl_saved = vmcs_read(ctrl_fld); 7264 int i; 7265 7266 for (i = 0; i < 4; i++) { 7267 u64 efer = efer_saved & ~efer_bit; 7268 u64 ctrl = ctrl_saved & ~ctrl_bit; 7269 7270 if (i & 1) 7271 efer |= efer_bit; 7272 if (i & 2) 7273 ctrl |= ctrl_bit; 7274 7275 test_efer_one(fld, fld_name, efer, ctrl_fld, ctrl, 7276 i, efer_bit_name); 7277 } 7278 7279 vmcs_write(ctrl_fld, ctrl_saved); 7280 vmcs_write(fld, efer_saved); 7281 } 7282 7283 static void test_efer(u32 fld, const char * fld_name, u32 ctrl_fld, 7284 u64 ctrl_bit1, u64 ctrl_bit2) 7285 { 7286 u64 efer_saved = vmcs_read(fld); 7287 u32 ctrl_saved = vmcs_read(ctrl_fld); 7288 u64 efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 7289 u64 i; 7290 u64 efer; 7291 7292 if (cpu_has_efer_nx()) 7293 efer_reserved_bits &= ~EFER_NX; 7294 7295 if (!ctrl_bit1) { 7296 printf("\"Load-IA32-EFER\" exit control not supported\n"); 7297 goto test_entry_exit_mode; 7298 } 7299 7300 report_prefix_pushf("%s %lx", fld_name, efer_saved); 7301 test_efer_vmlaunch(fld, true); 7302 report_prefix_pop(); 7303 7304 /* 7305 * Check reserved bits 7306 */ 7307 vmcs_write(ctrl_fld, ctrl_saved & ~ctrl_bit1); 7308 for (i = 0; i < 64; i++) { 7309 if ((1ull << i) & efer_reserved_bits) { 7310 efer = efer_saved | (1ull << i); 7311 vmcs_write(fld, efer); 7312 report_prefix_pushf("%s %lx", fld_name, efer); 7313 test_efer_vmlaunch(fld, true); 7314 report_prefix_pop(); 7315 } 7316 } 7317 7318 vmcs_write(ctrl_fld, ctrl_saved | ctrl_bit1); 7319 for (i = 0; i < 64; i++) { 7320 if ((1ull << i) & efer_reserved_bits) { 7321 efer = efer_saved | (1ull << i); 7322 vmcs_write(fld, efer); 7323 report_prefix_pushf("%s %lx", fld_name, efer); 7324 test_efer_vmlaunch(fld, false); 7325 report_prefix_pop(); 7326 } 7327 } 7328 7329 vmcs_write(ctrl_fld, ctrl_saved); 7330 vmcs_write(fld, efer_saved); 7331 7332 /* 7333 * Check LMA and LME bits 7334 */ 7335 test_efer_bit(fld, fld_name, 7336 ctrl_fld, ctrl_bit1, 7337 EFER_LMA, 7338 "EFER_LMA"); 7339 test_efer_bit(fld, fld_name, 7340 ctrl_fld, ctrl_bit1, 7341 EFER_LME, 7342 "EFER_LME"); 7343 7344 test_entry_exit_mode: 7345 test_efer_bit(fld, fld_name, 7346 ctrl_fld, ctrl_bit2, 7347 EFER_LMA, 7348 "EFER_LMA"); 7349 test_efer_bit(fld, fld_name, 7350 ctrl_fld, ctrl_bit2, 7351 EFER_LME, 7352 "EFER_LME"); 7353 } 7354 7355 /* 7356 * If the 'load IA32_EFER' VM-exit control is 1, bits reserved in the 7357 * IA32_EFER MSR must be 0 in the field for that register. In addition, 7358 * the values of the LMA and LME bits in the field must each be that of 7359 * the 'host address-space size' VM-exit control. 7360 * 7361 * [Intel SDM] 7362 */ 7363 static void test_host_efer(void) 7364 { 7365 test_efer(HOST_EFER, "HOST_EFER", EXI_CONTROLS, 7366 ctrl_exit_rev.clr & EXI_LOAD_EFER, 7367 EXI_HOST_64); 7368 } 7369 7370 /* 7371 * If the 'load IA32_EFER' VM-enter control is 1, bits reserved in the 7372 * IA32_EFER MSR must be 0 in the field for that register. In addition, 7373 * the values of the LMA and LME bits in the field must each be that of 7374 * the 'IA32e-mode guest' VM-exit control. 7375 */ 7376 static void test_guest_efer(void) 7377 { 7378 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) { 7379 printf("\"Load-IA32-EFER\" entry control not supported\n"); 7380 return; 7381 } 7382 7383 vmcs_write(GUEST_EFER, rdmsr(MSR_EFER)); 7384 test_efer(GUEST_EFER, "GUEST_EFER", ENT_CONTROLS, 7385 ctrl_enter_rev.clr & ENT_LOAD_EFER, 7386 ENT_GUEST_64); 7387 } 7388 7389 /* 7390 * PAT values higher than 8 are uninteresting since they're likely lumped 7391 * in with "8". We only test values above 8 one bit at a time, 7392 * in order to reduce the number of VM-Entries and keep the runtime reasonable. 7393 */ 7394 #define PAT_VAL_LIMIT 8 7395 7396 static void test_pat(u32 field, const char * field_name, u32 ctrl_field, 7397 u64 ctrl_bit) 7398 { 7399 u32 ctrl_saved = vmcs_read(ctrl_field); 7400 u64 pat_saved = vmcs_read(field); 7401 u64 i, val; 7402 u32 j; 7403 int error; 7404 7405 vmcs_clear_bits(ctrl_field, ctrl_bit); 7406 7407 for (i = 0; i < 256; i = (i < PAT_VAL_LIMIT) ? i + 1 : i * 2) { 7408 /* Test PAT0..PAT7 fields */ 7409 for (j = 0; j < (i ? 8 : 1); j++) { 7410 val = i << j * 8; 7411 vmcs_write(field, val); 7412 if (field == HOST_PAT) { 7413 report_prefix_pushf("%s %lx", field_name, val); 7414 test_vmx_vmlaunch(0); 7415 report_prefix_pop(); 7416 7417 } else { // GUEST_PAT 7418 test_guest_state("ENT_LOAD_PAT enabled", false, 7419 val, "GUEST_PAT"); 7420 } 7421 } 7422 } 7423 7424 vmcs_set_bits(ctrl_field, ctrl_bit); 7425 for (i = 0; i < 256; i = (i < PAT_VAL_LIMIT) ? i + 1 : i * 2) { 7426 /* Test PAT0..PAT7 fields */ 7427 for (j = 0; j < (i ? 8 : 1); j++) { 7428 val = i << j * 8; 7429 vmcs_write(field, val); 7430 7431 if (field == HOST_PAT) { 7432 report_prefix_pushf("%s %lx", field_name, val); 7433 if (i == 0x2 || i == 0x3 || i >= 0x8) 7434 error = 7435 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD; 7436 else 7437 error = 0; 7438 7439 test_vmx_vmlaunch(error); 7440 report_prefix_pop(); 7441 7442 } else { // GUEST_PAT 7443 error = (i == 0x2 || i == 0x3 || i >= 0x8); 7444 test_guest_state("ENT_LOAD_PAT enabled", !!error, 7445 val, "GUEST_PAT"); 7446 } 7447 7448 } 7449 } 7450 7451 vmcs_write(ctrl_field, ctrl_saved); 7452 vmcs_write(field, pat_saved); 7453 } 7454 7455 /* 7456 * If the "load IA32_PAT" VM-exit control is 1, the value of the field 7457 * for the IA32_PAT MSR must be one that could be written by WRMSR 7458 * without fault at CPL 0. Specifically, each of the 8 bytes in the 7459 * field must have one of the values 0 (UC), 1 (WC), 4 (WT), 5 (WP), 7460 * 6 (WB), or 7 (UC-). 7461 * 7462 * [Intel SDM] 7463 */ 7464 static void test_load_host_pat(void) 7465 { 7466 /* 7467 * "load IA32_PAT" VM-exit control 7468 */ 7469 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) { 7470 printf("\"Load-IA32-PAT\" exit control not supported\n"); 7471 return; 7472 } 7473 7474 test_pat(HOST_PAT, "HOST_PAT", EXI_CONTROLS, EXI_LOAD_PAT); 7475 } 7476 7477 union cpuidA_eax { 7478 struct { 7479 unsigned int version_id:8; 7480 unsigned int num_counters_gp:8; 7481 unsigned int bit_width:8; 7482 unsigned int mask_length:8; 7483 } split; 7484 unsigned int full; 7485 }; 7486 7487 union cpuidA_edx { 7488 struct { 7489 unsigned int num_counters_fixed:5; 7490 unsigned int bit_width_fixed:8; 7491 unsigned int reserved:9; 7492 } split; 7493 unsigned int full; 7494 }; 7495 7496 static bool valid_pgc(u64 val) 7497 { 7498 struct cpuid id; 7499 union cpuidA_eax eax; 7500 union cpuidA_edx edx; 7501 u64 mask; 7502 7503 id = cpuid(0xA); 7504 eax.full = id.a; 7505 edx.full = id.d; 7506 mask = ~(((1ull << eax.split.num_counters_gp) - 1) | 7507 (((1ull << edx.split.num_counters_fixed) - 1) << 32)); 7508 7509 return !(val & mask); 7510 } 7511 7512 static void test_pgc_vmlaunch(u32 xerror, u32 xreason, bool xfail, bool host) 7513 { 7514 u32 inst_err; 7515 u64 obs; 7516 bool success; 7517 struct vmx_state_area_test_data *data = &vmx_state_area_test_data; 7518 7519 if (host) { 7520 success = vmlaunch_succeeds(); 7521 obs = rdmsr(data->msr); 7522 if (!success) { 7523 inst_err = vmcs_read(VMX_INST_ERROR); 7524 report(xerror == inst_err, "vmlaunch failed, " 7525 "VMX Inst Error is %d (expected %d)", 7526 inst_err, xerror); 7527 } else { 7528 report(!data->enabled || data->exp == obs, 7529 "Host state is 0x%lx (expected 0x%lx)", 7530 obs, data->exp); 7531 report(success != xfail, "vmlaunch succeeded"); 7532 } 7533 } else { 7534 test_guest_state("load GUEST_PERF_GLOBAL_CTRL", xfail, 7535 GUEST_PERF_GLOBAL_CTRL, 7536 "GUEST_PERF_GLOBAL_CTRL"); 7537 } 7538 } 7539 7540 /* 7541 * test_load_perf_global_ctrl is a generic function for testing the 7542 * "load IA32_PERF_GLOBAL_CTRL" VM-{Entry,Exit} controls. This test function 7543 * tests the provided ctrl_val when disabled and enabled. 7544 * 7545 * @nr: VMCS field number corresponding to the host/guest state field 7546 * @name: Name of the above VMCS field for printing in test report 7547 * @ctrl_nr: VMCS field number corresponding to the VM-{Entry,Exit} control 7548 * @ctrl_val: Bit to set on the ctrl_field 7549 */ 7550 static void test_perf_global_ctrl(u32 nr, const char *name, u32 ctrl_nr, 7551 const char *ctrl_name, u64 ctrl_val) 7552 { 7553 u64 ctrl_saved = vmcs_read(ctrl_nr); 7554 u64 pgc_saved = vmcs_read(nr); 7555 u64 i, val; 7556 bool host = nr == HOST_PERF_GLOBAL_CTRL; 7557 struct vmx_state_area_test_data *data = &vmx_state_area_test_data; 7558 7559 data->msr = MSR_CORE_PERF_GLOBAL_CTRL; 7560 msr_bmp_init(); 7561 vmcs_write(ctrl_nr, ctrl_saved & ~ctrl_val); 7562 data->enabled = false; 7563 report_prefix_pushf("\"load IA32_PERF_GLOBAL_CTRL\"=0 on %s", 7564 ctrl_name); 7565 7566 for (i = 0; i < 64; i++) { 7567 val = 1ull << i; 7568 vmcs_write(nr, val); 7569 report_prefix_pushf("%s = 0x%lx", name, val); 7570 test_pgc_vmlaunch(0, VMX_VMCALL, false, host); 7571 report_prefix_pop(); 7572 } 7573 report_prefix_pop(); 7574 7575 vmcs_write(ctrl_nr, ctrl_saved | ctrl_val); 7576 data->enabled = true; 7577 report_prefix_pushf("\"load IA32_PERF_GLOBAL_CTRL\"=1 on %s", 7578 ctrl_name); 7579 for (i = 0; i < 64; i++) { 7580 val = 1ull << i; 7581 data->exp = val; 7582 vmcs_write(nr, val); 7583 report_prefix_pushf("%s = 0x%lx", name, val); 7584 if (valid_pgc(val)) { 7585 test_pgc_vmlaunch(0, VMX_VMCALL, false, host); 7586 } else { 7587 if (host) 7588 test_pgc_vmlaunch( 7589 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, 7590 0, 7591 true, 7592 host); 7593 else 7594 test_pgc_vmlaunch( 7595 0, 7596 VMX_ENTRY_FAILURE | VMX_FAIL_STATE, 7597 true, 7598 host); 7599 } 7600 report_prefix_pop(); 7601 } 7602 7603 data->enabled = false; 7604 report_prefix_pop(); 7605 vmcs_write(ctrl_nr, ctrl_saved); 7606 vmcs_write(nr, pgc_saved); 7607 } 7608 7609 static void test_load_host_perf_global_ctrl(void) 7610 { 7611 if (!(ctrl_exit_rev.clr & EXI_LOAD_PERF)) { 7612 printf("\"load IA32_PERF_GLOBAL_CTRL\" exit control not supported\n"); 7613 return; 7614 } 7615 7616 test_perf_global_ctrl(HOST_PERF_GLOBAL_CTRL, "HOST_PERF_GLOBAL_CTRL", 7617 EXI_CONTROLS, "EXI_CONTROLS", EXI_LOAD_PERF); 7618 } 7619 7620 7621 static void test_load_guest_perf_global_ctrl(void) 7622 { 7623 if (!(ctrl_enter_rev.clr & ENT_LOAD_PERF)) { 7624 printf("\"load IA32_PERF_GLOBAL_CTRL\" entry control not supported\n"); 7625 return; 7626 } 7627 7628 test_perf_global_ctrl(GUEST_PERF_GLOBAL_CTRL, "GUEST_PERF_GLOBAL_CTRL", 7629 ENT_CONTROLS, "ENT_CONTROLS", ENT_LOAD_PERF); 7630 } 7631 7632 7633 /* 7634 * test_vmcs_field - test a value for the given VMCS field 7635 * @field: VMCS field 7636 * @field_name: string name of VMCS field 7637 * @bit_start: starting bit 7638 * @bit_end: ending bit 7639 * @val: value that the bit range must or must not contain 7640 * @valid_val: whether value given in 'val' must be valid or not 7641 * @error: expected VMCS error when vmentry fails for an invalid value 7642 */ 7643 static void test_vmcs_field(u64 field, const char *field_name, u32 bit_start, 7644 u32 bit_end, u64 val, bool valid_val, u32 error) 7645 { 7646 u64 field_saved = vmcs_read(field); 7647 u32 i; 7648 u64 tmp; 7649 u32 bit_on; 7650 u64 mask = ~0ull; 7651 7652 mask = (mask >> bit_end) << bit_end; 7653 mask = mask | ((1 << bit_start) - 1); 7654 tmp = (field_saved & mask) | (val << bit_start); 7655 7656 vmcs_write(field, tmp); 7657 report_prefix_pushf("%s %lx", field_name, tmp); 7658 if (valid_val) 7659 test_vmx_vmlaunch(0); 7660 else 7661 test_vmx_vmlaunch(error); 7662 report_prefix_pop(); 7663 7664 for (i = bit_start; i <= bit_end; i = i + 2) { 7665 bit_on = ((1ull < i) & (val << bit_start)) ? 0 : 1; 7666 if (bit_on) 7667 tmp = field_saved | (1ull << i); 7668 else 7669 tmp = field_saved & ~(1ull << i); 7670 vmcs_write(field, tmp); 7671 report_prefix_pushf("%s %lx", field_name, tmp); 7672 if (valid_val) 7673 test_vmx_vmlaunch(error); 7674 else 7675 test_vmx_vmlaunch(0); 7676 report_prefix_pop(); 7677 } 7678 7679 vmcs_write(field, field_saved); 7680 } 7681 7682 static void test_canonical(u64 field, const char * field_name, bool host) 7683 { 7684 u64 addr_saved = vmcs_read(field); 7685 7686 /* 7687 * Use the existing value if possible. Writing a random canonical 7688 * value is not an option as doing so would corrupt the field being 7689 * tested and likely hose the test. 7690 */ 7691 if (is_canonical(addr_saved)) { 7692 if (host) { 7693 report_prefix_pushf("%s %lx", field_name, addr_saved); 7694 test_vmx_vmlaunch(0); 7695 report_prefix_pop(); 7696 } else { 7697 test_guest_state("Test canonical address", false, 7698 addr_saved, field_name); 7699 } 7700 } 7701 7702 vmcs_write(field, NONCANONICAL); 7703 7704 if (host) { 7705 report_prefix_pushf("%s %llx", field_name, NONCANONICAL); 7706 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7707 report_prefix_pop(); 7708 } else { 7709 test_guest_state("Test non-canonical address", true, 7710 NONCANONICAL, field_name); 7711 } 7712 7713 vmcs_write(field, addr_saved); 7714 } 7715 7716 #define TEST_RPL_TI_FLAGS(reg, name) \ 7717 test_vmcs_field(reg, name, 0, 2, 0x0, true, \ 7718 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7719 7720 #define TEST_CS_TR_FLAGS(reg, name) \ 7721 test_vmcs_field(reg, name, 3, 15, 0x0000, false, \ 7722 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7723 7724 /* 7725 * 1. In the selector field for each of CS, SS, DS, ES, FS, GS and TR, the 7726 * RPL (bits 1:0) and the TI flag (bit 2) must be 0. 7727 * 2. The selector fields for CS and TR cannot be 0000H. 7728 * 3. The selector field for SS cannot be 0000H if the "host address-space 7729 * size" VM-exit control is 0. 7730 * 4. On processors that support Intel 64 architecture, the base-address 7731 * fields for FS, GS and TR must contain canonical addresses. 7732 */ 7733 static void test_host_segment_regs(void) 7734 { 7735 u16 selector_saved; 7736 7737 /* 7738 * Test RPL and TI flags 7739 */ 7740 TEST_RPL_TI_FLAGS(HOST_SEL_CS, "HOST_SEL_CS"); 7741 TEST_RPL_TI_FLAGS(HOST_SEL_SS, "HOST_SEL_SS"); 7742 TEST_RPL_TI_FLAGS(HOST_SEL_DS, "HOST_SEL_DS"); 7743 TEST_RPL_TI_FLAGS(HOST_SEL_ES, "HOST_SEL_ES"); 7744 TEST_RPL_TI_FLAGS(HOST_SEL_FS, "HOST_SEL_FS"); 7745 TEST_RPL_TI_FLAGS(HOST_SEL_GS, "HOST_SEL_GS"); 7746 TEST_RPL_TI_FLAGS(HOST_SEL_TR, "HOST_SEL_TR"); 7747 7748 /* 7749 * Test that CS and TR fields can not be 0x0000 7750 */ 7751 TEST_CS_TR_FLAGS(HOST_SEL_CS, "HOST_SEL_CS"); 7752 TEST_CS_TR_FLAGS(HOST_SEL_TR, "HOST_SEL_TR"); 7753 7754 /* 7755 * SS field can not be 0x0000 if "host address-space size" VM-exit 7756 * control is 0 7757 */ 7758 selector_saved = vmcs_read(HOST_SEL_SS); 7759 vmcs_write(HOST_SEL_SS, 0); 7760 report_prefix_pushf("HOST_SEL_SS 0"); 7761 if (vmcs_read(EXI_CONTROLS) & EXI_HOST_64) { 7762 test_vmx_vmlaunch(0); 7763 } else { 7764 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7765 } 7766 report_prefix_pop(); 7767 7768 vmcs_write(HOST_SEL_SS, selector_saved); 7769 7770 /* 7771 * Base address for FS, GS and TR must be canonical 7772 */ 7773 test_canonical(HOST_BASE_FS, "HOST_BASE_FS", true); 7774 test_canonical(HOST_BASE_GS, "HOST_BASE_GS", true); 7775 test_canonical(HOST_BASE_TR, "HOST_BASE_TR", true); 7776 } 7777 7778 /* 7779 * On processors that support Intel 64 architecture, the base-address 7780 * fields for GDTR and IDTR must contain canonical addresses. 7781 */ 7782 static void test_host_desc_tables(void) 7783 { 7784 test_canonical(HOST_BASE_GDTR, "HOST_BASE_GDTR", true); 7785 test_canonical(HOST_BASE_IDTR, "HOST_BASE_IDTR", true); 7786 } 7787 7788 /* 7789 * If the "host address-space size" VM-exit control is 0, the following must 7790 * hold: 7791 * - The "IA-32e mode guest" VM-entry control is 0. 7792 * - Bit 17 of the CR4 field (corresponding to CR4.PCIDE) is 0. 7793 * - Bits 63:32 in the RIP field are 0. 7794 * 7795 * If the "host address-space size" VM-exit control is 1, the following must 7796 * hold: 7797 * - Bit 5 of the CR4 field (corresponding to CR4.PAE) is 1. 7798 * - The RIP field contains a canonical address. 7799 * 7800 */ 7801 static void test_host_addr_size(void) 7802 { 7803 u64 cr4_saved = vmcs_read(HOST_CR4); 7804 u64 rip_saved = vmcs_read(HOST_RIP); 7805 u64 entry_ctrl_saved = vmcs_read(ENT_CONTROLS); 7806 int i; 7807 u64 tmp; 7808 7809 if (vmcs_read(EXI_CONTROLS) & EXI_HOST_64) { 7810 vmcs_write(ENT_CONTROLS, entry_ctrl_saved | ENT_GUEST_64); 7811 report_prefix_pushf("\"IA-32e mode guest\" enabled"); 7812 test_vmx_vmlaunch(0); 7813 report_prefix_pop(); 7814 7815 vmcs_write(HOST_CR4, cr4_saved | X86_CR4_PCIDE); 7816 report_prefix_pushf("\"CR4.PCIDE\" set"); 7817 test_vmx_vmlaunch(0); 7818 report_prefix_pop(); 7819 7820 for (i = 32; i <= 63; i = i + 4) { 7821 tmp = rip_saved | 1ull << i; 7822 vmcs_write(HOST_RIP, tmp); 7823 report_prefix_pushf("HOST_RIP %lx", tmp); 7824 test_vmx_vmlaunch(0); 7825 report_prefix_pop(); 7826 } 7827 7828 if (cr4_saved & X86_CR4_PAE) { 7829 vmcs_write(HOST_CR4, cr4_saved & ~X86_CR4_PAE); 7830 report_prefix_pushf("\"CR4.PAE\" unset"); 7831 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7832 } else { 7833 report_prefix_pushf("\"CR4.PAE\" set"); 7834 test_vmx_vmlaunch(0); 7835 } 7836 report_prefix_pop(); 7837 7838 vmcs_write(HOST_RIP, NONCANONICAL); 7839 report_prefix_pushf("HOST_RIP %llx", NONCANONICAL); 7840 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7841 report_prefix_pop(); 7842 7843 vmcs_write(ENT_CONTROLS, entry_ctrl_saved | ENT_GUEST_64); 7844 vmcs_write(HOST_RIP, rip_saved); 7845 vmcs_write(HOST_CR4, cr4_saved); 7846 7847 /* Restore host's active RIP and CR4 values. */ 7848 report_prefix_pushf("restore host state"); 7849 test_vmx_vmlaunch(0); 7850 report_prefix_pop(); 7851 } 7852 } 7853 7854 /* 7855 * Check that the virtual CPU checks the VMX Host State Area as 7856 * documented in the Intel SDM. 7857 */ 7858 static void vmx_host_state_area_test(void) 7859 { 7860 /* 7861 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 7862 * fail due to invalid guest state, should we make it that 7863 * far. 7864 */ 7865 vmcs_write(GUEST_RFLAGS, 0); 7866 7867 test_host_ctl_regs(); 7868 7869 test_canonical(HOST_SYSENTER_ESP, "HOST_SYSENTER_ESP", true); 7870 test_canonical(HOST_SYSENTER_EIP, "HOST_SYSENTER_EIP", true); 7871 7872 test_host_efer(); 7873 test_load_host_pat(); 7874 test_host_segment_regs(); 7875 test_host_desc_tables(); 7876 test_host_addr_size(); 7877 test_load_host_perf_global_ctrl(); 7878 } 7879 7880 /* 7881 * If the "load debug controls" VM-entry control is 1, bits 63:32 in 7882 * the DR7 field must be 0. 7883 * 7884 * [Intel SDM] 7885 */ 7886 static void test_guest_dr7(void) 7887 { 7888 u32 ent_saved = vmcs_read(ENT_CONTROLS); 7889 u64 dr7_saved = vmcs_read(GUEST_DR7); 7890 u64 val; 7891 int i; 7892 7893 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS) { 7894 vmcs_clear_bits(ENT_CONTROLS, ENT_LOAD_DBGCTLS); 7895 for (i = 0; i < 64; i++) { 7896 val = 1ull << i; 7897 vmcs_write(GUEST_DR7, val); 7898 test_guest_state("ENT_LOAD_DBGCTLS disabled", false, 7899 val, "GUEST_DR7"); 7900 } 7901 } 7902 if (ctrl_enter_rev.clr & ENT_LOAD_DBGCTLS) { 7903 vmcs_set_bits(ENT_CONTROLS, ENT_LOAD_DBGCTLS); 7904 for (i = 0; i < 64; i++) { 7905 val = 1ull << i; 7906 vmcs_write(GUEST_DR7, val); 7907 test_guest_state("ENT_LOAD_DBGCTLS enabled", i >= 32, 7908 val, "GUEST_DR7"); 7909 } 7910 } 7911 vmcs_write(GUEST_DR7, dr7_saved); 7912 vmcs_write(ENT_CONTROLS, ent_saved); 7913 } 7914 7915 /* 7916 * If the "load IA32_PAT" VM-entry control is 1, the value of the field 7917 * for the IA32_PAT MSR must be one that could be written by WRMSR 7918 * without fault at CPL 0. Specifically, each of the 8 bytes in the 7919 * field must have one of the values 0 (UC), 1 (WC), 4 (WT), 5 (WP), 7920 * 6 (WB), or 7 (UC-). 7921 * 7922 * [Intel SDM] 7923 */ 7924 static void test_load_guest_pat(void) 7925 { 7926 /* 7927 * "load IA32_PAT" VM-entry control 7928 */ 7929 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 7930 printf("\"Load-IA32-PAT\" entry control not supported\n"); 7931 return; 7932 } 7933 7934 test_pat(GUEST_PAT, "GUEST_PAT", ENT_CONTROLS, ENT_LOAD_PAT); 7935 } 7936 7937 #define MSR_IA32_BNDCFGS_RSVD_MASK 0x00000ffc 7938 7939 /* 7940 * If the "load IA32_BNDCFGS" VM-entry control is 1, the following 7941 * checks are performed on the field for the IA32_BNDCFGS MSR: 7942 * 7943 * - Bits reserved in the IA32_BNDCFGS MSR must be 0. 7944 * - The linear address in bits 63:12 must be canonical. 7945 * 7946 * [Intel SDM] 7947 */ 7948 static void test_load_guest_bndcfgs(void) 7949 { 7950 u64 bndcfgs_saved = vmcs_read(GUEST_BNDCFGS); 7951 u64 bndcfgs; 7952 7953 if (!(ctrl_enter_rev.clr & ENT_LOAD_BNDCFGS)) { 7954 printf("\"Load-IA32-BNDCFGS\" entry control not supported\n"); 7955 return; 7956 } 7957 7958 vmcs_clear_bits(ENT_CONTROLS, ENT_LOAD_BNDCFGS); 7959 7960 vmcs_write(GUEST_BNDCFGS, NONCANONICAL); 7961 test_guest_state("ENT_LOAD_BNDCFGS disabled", false, 7962 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7963 bndcfgs = bndcfgs_saved | MSR_IA32_BNDCFGS_RSVD_MASK; 7964 vmcs_write(GUEST_BNDCFGS, bndcfgs); 7965 test_guest_state("ENT_LOAD_BNDCFGS disabled", false, 7966 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7967 7968 vmcs_set_bits(ENT_CONTROLS, ENT_LOAD_BNDCFGS); 7969 7970 vmcs_write(GUEST_BNDCFGS, NONCANONICAL); 7971 test_guest_state("ENT_LOAD_BNDCFGS enabled", true, 7972 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7973 bndcfgs = bndcfgs_saved | MSR_IA32_BNDCFGS_RSVD_MASK; 7974 vmcs_write(GUEST_BNDCFGS, bndcfgs); 7975 test_guest_state("ENT_LOAD_BNDCFGS enabled", true, 7976 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7977 7978 vmcs_write(GUEST_BNDCFGS, bndcfgs_saved); 7979 } 7980 7981 #define GUEST_SEG_UNUSABLE_MASK (1u << 16) 7982 #define GUEST_SEG_SEL_TI_MASK (1u << 2) 7983 7984 7985 #define TEST_SEGMENT_SEL(test, xfail, sel, val) \ 7986 do { \ 7987 vmcs_write(sel, val); \ 7988 test_guest_state(test " segment", xfail, val, xstr(sel)); \ 7989 } while (0) 7990 7991 #define TEST_INVALID_SEG_SEL(sel, val) \ 7992 TEST_SEGMENT_SEL("Invalid: " xstr(val), true, sel, val); 7993 7994 #define TEST_VALID_SEG_SEL(sel, val) \ 7995 TEST_SEGMENT_SEL("Valid: " xstr(val), false, sel, val); 7996 7997 /* 7998 * The following checks are done on the Selector field of the Guest Segment 7999 * Registers: 8000 * - TR. The TI flag (bit 2) must be 0. 8001 * - LDTR. If LDTR is usable, the TI flag (bit 2) must be 0. 8002 * - SS. If the guest will not be virtual-8086 and the "unrestricted 8003 * guest" VM-execution control is 0, the RPL (bits 1:0) must equal 8004 * the RPL of the selector field for CS. 8005 * 8006 * [Intel SDM] 8007 */ 8008 static void test_guest_segment_sel_fields(void) 8009 { 8010 u16 sel_saved; 8011 u32 ar_saved; 8012 u32 cpu_ctrl0_saved; 8013 u32 cpu_ctrl1_saved; 8014 u16 cs_rpl_bits; 8015 8016 /* 8017 * Test for GUEST_SEL_TR 8018 */ 8019 sel_saved = vmcs_read(GUEST_SEL_TR); 8020 TEST_INVALID_SEG_SEL(GUEST_SEL_TR, sel_saved | GUEST_SEG_SEL_TI_MASK); 8021 vmcs_write(GUEST_SEL_TR, sel_saved); 8022 8023 /* 8024 * Test for GUEST_SEL_LDTR 8025 */ 8026 sel_saved = vmcs_read(GUEST_SEL_LDTR); 8027 ar_saved = vmcs_read(GUEST_AR_LDTR); 8028 /* LDTR is set unusable */ 8029 vmcs_write(GUEST_AR_LDTR, ar_saved | GUEST_SEG_UNUSABLE_MASK); 8030 TEST_VALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved | GUEST_SEG_SEL_TI_MASK); 8031 TEST_VALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved & ~GUEST_SEG_SEL_TI_MASK); 8032 /* LDTR is set usable */ 8033 vmcs_write(GUEST_AR_LDTR, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 8034 TEST_INVALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved | GUEST_SEG_SEL_TI_MASK); 8035 8036 TEST_VALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved & ~GUEST_SEG_SEL_TI_MASK); 8037 8038 vmcs_write(GUEST_AR_LDTR, ar_saved); 8039 vmcs_write(GUEST_SEL_LDTR, sel_saved); 8040 8041 /* 8042 * Test for GUEST_SEL_SS 8043 */ 8044 cpu_ctrl0_saved = vmcs_read(CPU_EXEC_CTRL0); 8045 cpu_ctrl1_saved = vmcs_read(CPU_EXEC_CTRL1); 8046 ar_saved = vmcs_read(GUEST_AR_SS); 8047 /* Turn off "unrestricted guest" vm-execution control */ 8048 vmcs_write(CPU_EXEC_CTRL1, cpu_ctrl1_saved & ~CPU_URG); 8049 cs_rpl_bits = vmcs_read(GUEST_SEL_CS) & 0x3; 8050 sel_saved = vmcs_read(GUEST_SEL_SS); 8051 TEST_INVALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 8052 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 8053 /* Make SS usable if it's unusable or vice-versa */ 8054 if (ar_saved & GUEST_SEG_UNUSABLE_MASK) 8055 vmcs_write(GUEST_AR_SS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 8056 else 8057 vmcs_write(GUEST_AR_SS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 8058 TEST_INVALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 8059 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 8060 8061 /* Need a valid EPTP as the passing case fully enters the guest. */ 8062 if (enable_unrestricted_guest(true)) 8063 goto skip_ss_tests; 8064 8065 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 8066 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 8067 8068 /* Make SS usable if it's unusable or vice-versa */ 8069 if (vmcs_read(GUEST_AR_SS) & GUEST_SEG_UNUSABLE_MASK) 8070 vmcs_write(GUEST_AR_SS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 8071 else 8072 vmcs_write(GUEST_AR_SS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 8073 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 8074 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 8075 skip_ss_tests: 8076 8077 vmcs_write(GUEST_AR_SS, ar_saved); 8078 vmcs_write(GUEST_SEL_SS, sel_saved); 8079 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrl0_saved); 8080 vmcs_write(CPU_EXEC_CTRL1, cpu_ctrl1_saved); 8081 } 8082 8083 #define TEST_SEGMENT_BASE_ADDR_UPPER_BITS(xfail, seg_base) \ 8084 do { \ 8085 addr_saved = vmcs_read(seg_base); \ 8086 for (i = 32; i < 63; i = i + 4) { \ 8087 addr = addr_saved | 1ull << i; \ 8088 vmcs_write(seg_base, addr); \ 8089 test_guest_state("seg.BASE[63:32] != 0, usable = " xstr(xfail), \ 8090 xfail, addr, xstr(seg_base)); \ 8091 } \ 8092 vmcs_write(seg_base, addr_saved); \ 8093 } while (0) 8094 8095 #define TEST_SEGMENT_BASE_ADDR_CANONICAL(xfail, seg_base) \ 8096 do { \ 8097 addr_saved = vmcs_read(seg_base); \ 8098 vmcs_write(seg_base, NONCANONICAL); \ 8099 test_guest_state("seg.BASE non-canonical, usable = " xstr(xfail), \ 8100 xfail, NONCANONICAL, xstr(seg_base)); \ 8101 vmcs_write(seg_base, addr_saved); \ 8102 } while (0) 8103 8104 /* 8105 * The following checks are done on the Base Address field of the Guest 8106 * Segment Registers on processors that support Intel 64 architecture: 8107 * - TR, FS, GS : The address must be canonical. 8108 * - LDTR : If LDTR is usable, the address must be canonical. 8109 * - CS : Bits 63:32 of the address must be zero. 8110 * - SS, DS, ES : If the register is usable, bits 63:32 of the address 8111 * must be zero. 8112 * 8113 * [Intel SDM] 8114 */ 8115 static void test_guest_segment_base_addr_fields(void) 8116 { 8117 u64 addr_saved; 8118 u64 addr; 8119 u32 ar_saved; 8120 int i; 8121 8122 /* 8123 * The address of TR, FS, GS and LDTR must be canonical. 8124 */ 8125 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_TR); 8126 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_FS); 8127 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_GS); 8128 ar_saved = vmcs_read(GUEST_AR_LDTR); 8129 /* Make LDTR unusable */ 8130 vmcs_write(GUEST_AR_LDTR, ar_saved | GUEST_SEG_UNUSABLE_MASK); 8131 TEST_SEGMENT_BASE_ADDR_CANONICAL(false, GUEST_BASE_LDTR); 8132 /* Make LDTR usable */ 8133 vmcs_write(GUEST_AR_LDTR, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 8134 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_LDTR); 8135 8136 vmcs_write(GUEST_AR_LDTR, ar_saved); 8137 8138 /* 8139 * Bits 63:32 in CS, SS, DS and ES base address must be zero 8140 */ 8141 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_CS); 8142 ar_saved = vmcs_read(GUEST_AR_SS); 8143 /* Make SS unusable */ 8144 vmcs_write(GUEST_AR_SS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 8145 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(false, GUEST_BASE_SS); 8146 /* Make SS usable */ 8147 vmcs_write(GUEST_AR_SS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 8148 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_SS); 8149 vmcs_write(GUEST_AR_SS, ar_saved); 8150 8151 ar_saved = vmcs_read(GUEST_AR_DS); 8152 /* Make DS unusable */ 8153 vmcs_write(GUEST_AR_DS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 8154 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(false, GUEST_BASE_DS); 8155 /* Make DS usable */ 8156 vmcs_write(GUEST_AR_DS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 8157 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_DS); 8158 vmcs_write(GUEST_AR_DS, ar_saved); 8159 8160 ar_saved = vmcs_read(GUEST_AR_ES); 8161 /* Make ES unusable */ 8162 vmcs_write(GUEST_AR_ES, ar_saved | GUEST_SEG_UNUSABLE_MASK); 8163 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(false, GUEST_BASE_ES); 8164 /* Make ES usable */ 8165 vmcs_write(GUEST_AR_ES, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 8166 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_ES); 8167 vmcs_write(GUEST_AR_ES, ar_saved); 8168 } 8169 8170 /* 8171 * Check that the virtual CPU checks the VMX Guest State Area as 8172 * documented in the Intel SDM. 8173 */ 8174 static void vmx_guest_state_area_test(void) 8175 { 8176 vmx_set_test_stage(1); 8177 test_set_guest(guest_state_test_main); 8178 8179 /* 8180 * The IA32_SYSENTER_ESP field and the IA32_SYSENTER_EIP field 8181 * must each contain a canonical address. 8182 */ 8183 test_canonical(GUEST_SYSENTER_ESP, "GUEST_SYSENTER_ESP", false); 8184 test_canonical(GUEST_SYSENTER_EIP, "GUEST_SYSENTER_EIP", false); 8185 8186 test_guest_dr7(); 8187 test_load_guest_pat(); 8188 test_guest_efer(); 8189 test_load_guest_perf_global_ctrl(); 8190 test_load_guest_bndcfgs(); 8191 8192 test_guest_segment_sel_fields(); 8193 test_guest_segment_base_addr_fields(); 8194 8195 test_canonical(GUEST_BASE_GDTR, "GUEST_BASE_GDTR", false); 8196 test_canonical(GUEST_BASE_IDTR, "GUEST_BASE_IDTR", false); 8197 8198 u32 guest_desc_limit_saved = vmcs_read(GUEST_LIMIT_GDTR); 8199 int i; 8200 for (i = 16; i <= 31; i++) { 8201 u32 tmp = guest_desc_limit_saved | (1ull << i); 8202 vmcs_write(GUEST_LIMIT_GDTR, tmp); 8203 test_guest_state("GDT.limit > 0xffff", true, tmp, "GUEST_LIMIT_GDTR"); 8204 } 8205 vmcs_write(GUEST_LIMIT_GDTR, guest_desc_limit_saved); 8206 8207 guest_desc_limit_saved = vmcs_read(GUEST_LIMIT_IDTR); 8208 for (i = 16; i <= 31; i++) { 8209 u32 tmp = guest_desc_limit_saved | (1ull << i); 8210 vmcs_write(GUEST_LIMIT_IDTR, tmp); 8211 test_guest_state("IDT.limit > 0xffff", true, tmp, "GUEST_LIMIT_IDTR"); 8212 } 8213 vmcs_write(GUEST_LIMIT_IDTR, guest_desc_limit_saved); 8214 8215 /* 8216 * Let the guest finish execution 8217 */ 8218 vmx_set_test_stage(2); 8219 enter_guest(); 8220 } 8221 8222 extern void unrestricted_guest_main(void); 8223 asm (".code32\n" 8224 "unrestricted_guest_main:\n" 8225 "vmcall\n" 8226 "nop\n" 8227 "mov $1, %edi\n" 8228 "call hypercall\n" 8229 ".code64\n"); 8230 8231 static void setup_unrestricted_guest(void) 8232 { 8233 vmcs_write(GUEST_CR0, vmcs_read(GUEST_CR0) & ~(X86_CR0_PG)); 8234 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) & ~ENT_GUEST_64); 8235 vmcs_write(GUEST_EFER, vmcs_read(GUEST_EFER) & ~EFER_LMA); 8236 vmcs_write(GUEST_RIP, virt_to_phys(unrestricted_guest_main)); 8237 } 8238 8239 static void unsetup_unrestricted_guest(void) 8240 { 8241 vmcs_write(GUEST_CR0, vmcs_read(GUEST_CR0) | X86_CR0_PG); 8242 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) | ENT_GUEST_64); 8243 vmcs_write(GUEST_EFER, vmcs_read(GUEST_EFER) | EFER_LMA); 8244 vmcs_write(GUEST_RIP, (u64) phys_to_virt(vmcs_read(GUEST_RIP))); 8245 vmcs_write(GUEST_RSP, (u64) phys_to_virt(vmcs_read(GUEST_RSP))); 8246 } 8247 8248 /* 8249 * If "unrestricted guest" secondary VM-execution control is set, guests 8250 * can run in unpaged protected mode. 8251 */ 8252 static void vmentry_unrestricted_guest_test(void) 8253 { 8254 if (enable_unrestricted_guest(true)) { 8255 report_skip("Unrestricted guest not supported"); 8256 return; 8257 } 8258 8259 test_set_guest(unrestricted_guest_main); 8260 setup_unrestricted_guest(); 8261 test_guest_state("Unrestricted guest test", false, CPU_URG, "CPU_URG"); 8262 8263 /* 8264 * Let the guest finish execution as a regular guest 8265 */ 8266 unsetup_unrestricted_guest(); 8267 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) & ~CPU_URG); 8268 enter_guest(); 8269 } 8270 8271 static bool valid_vmcs_for_vmentry(void) 8272 { 8273 struct vmcs *current_vmcs = NULL; 8274 8275 if (vmcs_save(¤t_vmcs)) 8276 return false; 8277 8278 return current_vmcs && !current_vmcs->hdr.shadow_vmcs; 8279 } 8280 8281 static void try_vmentry_in_movss_shadow(void) 8282 { 8283 u32 vm_inst_err; 8284 u32 flags; 8285 bool early_failure = false; 8286 u32 expected_flags = X86_EFLAGS_FIXED; 8287 bool valid_vmcs = valid_vmcs_for_vmentry(); 8288 8289 expected_flags |= valid_vmcs ? X86_EFLAGS_ZF : X86_EFLAGS_CF; 8290 8291 /* 8292 * Indirectly set VM_INST_ERR to 12 ("VMREAD/VMWRITE from/to 8293 * unsupported VMCS component"). 8294 */ 8295 vmcs_write(~0u, 0); 8296 8297 __asm__ __volatile__ ("mov %[host_rsp], %%edx;" 8298 "vmwrite %%rsp, %%rdx;" 8299 "mov 0f, %%rax;" 8300 "mov %[host_rip], %%edx;" 8301 "vmwrite %%rax, %%rdx;" 8302 "mov $-1, %%ah;" 8303 "sahf;" 8304 "mov %%ss, %%ax;" 8305 "mov %%ax, %%ss;" 8306 "vmlaunch;" 8307 "mov $1, %[early_failure];" 8308 "0: lahf;" 8309 "movzbl %%ah, %[flags]" 8310 : [early_failure] "+r" (early_failure), 8311 [flags] "=&a" (flags) 8312 : [host_rsp] "i" (HOST_RSP), 8313 [host_rip] "i" (HOST_RIP) 8314 : "rdx", "cc", "memory"); 8315 vm_inst_err = vmcs_read(VMX_INST_ERROR); 8316 8317 report(early_failure, "Early VM-entry failure"); 8318 report(flags == expected_flags, "RFLAGS[8:0] is %x (actual %x)", 8319 expected_flags, flags); 8320 if (valid_vmcs) 8321 report(vm_inst_err == VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, 8322 "VM-instruction error is %d (actual %d)", 8323 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, vm_inst_err); 8324 } 8325 8326 static void vmentry_movss_shadow_test(void) 8327 { 8328 struct vmcs *orig_vmcs; 8329 8330 TEST_ASSERT(!vmcs_save(&orig_vmcs)); 8331 8332 /* 8333 * Set the launched flag on the current VMCS to verify the correct 8334 * error priority, below. 8335 */ 8336 test_set_guest(v2_null_test_guest); 8337 enter_guest(); 8338 8339 /* 8340 * With bit 1 of the guest's RFLAGS clear, VM-entry should 8341 * fail due to invalid guest state (if we make it that far). 8342 */ 8343 vmcs_write(GUEST_RFLAGS, 0); 8344 8345 /* 8346 * "VM entry with events blocked by MOV SS" takes precedence over 8347 * "VMLAUNCH with non-clear VMCS." 8348 */ 8349 report_prefix_push("valid current-VMCS"); 8350 try_vmentry_in_movss_shadow(); 8351 report_prefix_pop(); 8352 8353 /* 8354 * VMfailInvalid takes precedence over "VM entry with events 8355 * blocked by MOV SS." 8356 */ 8357 TEST_ASSERT(!vmcs_clear(orig_vmcs)); 8358 report_prefix_push("no current-VMCS"); 8359 try_vmentry_in_movss_shadow(); 8360 report_prefix_pop(); 8361 8362 TEST_ASSERT(!make_vmcs_current(orig_vmcs)); 8363 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 8364 } 8365 8366 static void vmx_single_vmcall_guest(void) 8367 { 8368 vmcall(); 8369 } 8370 8371 static void vmx_cr_load_test(void) 8372 { 8373 unsigned long cr3, cr4, orig_cr3, orig_cr4; 8374 u32 ctrls[2] = {0}; 8375 pgd_t *pml5; 8376 8377 orig_cr4 = read_cr4(); 8378 orig_cr3 = read_cr3(); 8379 8380 if (!this_cpu_has(X86_FEATURE_PCID)) { 8381 report_skip("PCID not detected"); 8382 return; 8383 } 8384 if (!this_cpu_has(X86_FEATURE_MCE)) { 8385 report_skip("MCE not detected"); 8386 return; 8387 } 8388 8389 TEST_ASSERT(!(orig_cr3 & X86_CR3_PCID_MASK)); 8390 8391 /* Enable PCID for L1. */ 8392 cr4 = orig_cr4 | X86_CR4_PCIDE; 8393 cr3 = orig_cr3 | 0x1; 8394 TEST_ASSERT(!write_cr4_checking(cr4)); 8395 write_cr3(cr3); 8396 8397 test_set_guest(vmx_single_vmcall_guest); 8398 vmcs_write(HOST_CR4, cr4); 8399 vmcs_write(HOST_CR3, cr3); 8400 enter_guest(); 8401 8402 /* 8403 * No exception is expected. 8404 * 8405 * NB. KVM loads the last guest write to CR4 into CR4 read 8406 * shadow. In order to trigger an exit to KVM, we can toggle a 8407 * bit that is owned by KVM. We use CR4.MCE, which shall 8408 * have no side effect because normally no guest MCE (e.g., as the 8409 * result of bad memory) would happen during this test. 8410 */ 8411 TEST_ASSERT(!write_cr4_checking(cr4 ^ X86_CR4_MCE)); 8412 8413 /* Cleanup L1 state. */ 8414 write_cr3(orig_cr3); 8415 TEST_ASSERT(!write_cr4_checking(orig_cr4)); 8416 8417 if (!this_cpu_has(X86_FEATURE_LA57)) 8418 goto done; 8419 8420 /* 8421 * Allocate a full page for PML5 to guarantee alignment, though only 8422 * the first entry needs to be filled (the test's virtual addresses 8423 * most definitely do not have any of bits 56:48 set). 8424 */ 8425 pml5 = alloc_page(); 8426 *pml5 = orig_cr3 | PT_PRESENT_MASK | PT_WRITABLE_MASK; 8427 8428 /* 8429 * Transition to/from 5-level paging in the host via VM-Exit. CR4.LA57 8430 * can't be toggled while long is active via MOV CR4, but there are no 8431 * such restrictions on VM-Exit. 8432 */ 8433 lol_5level: 8434 vmcs_write(HOST_CR4, orig_cr4 | X86_CR4_LA57); 8435 vmcs_write(HOST_CR3, virt_to_phys(pml5)); 8436 enter_guest(); 8437 8438 /* 8439 * VMREAD with a memory operand to verify KVM detects the LA57 change, 8440 * e.g. uses the correct guest root level in gva_to_gpa(). 8441 */ 8442 TEST_ASSERT(vmcs_readm(HOST_CR3) == virt_to_phys(pml5)); 8443 TEST_ASSERT(vmcs_readm(HOST_CR4) == (orig_cr4 | X86_CR4_LA57)); 8444 8445 vmcs_write(HOST_CR4, orig_cr4); 8446 vmcs_write(HOST_CR3, orig_cr3); 8447 enter_guest(); 8448 8449 TEST_ASSERT(vmcs_readm(HOST_CR3) == orig_cr3); 8450 TEST_ASSERT(vmcs_readm(HOST_CR4) == orig_cr4); 8451 8452 /* 8453 * And now do the same LA57 shenanigans with EPT enabled. KVM uses 8454 * two separate MMUs when L1 uses TDP, whereas the above shadow paging 8455 * version shares an MMU between L1 and L2. 8456 * 8457 * If the saved execution controls are non-zero then the EPT version 8458 * has already run. In that case, restore the old controls. If EPT 8459 * setup fails, e.g. EPT isn't supported, fall through and finish up. 8460 */ 8461 if (ctrls[0]) { 8462 vmcs_write(CPU_EXEC_CTRL0, ctrls[0]); 8463 vmcs_write(CPU_EXEC_CTRL1, ctrls[1]); 8464 } else if (!setup_ept(false)) { 8465 ctrls[0] = vmcs_read(CPU_EXEC_CTRL0); 8466 ctrls[1] = vmcs_read(CPU_EXEC_CTRL1); 8467 goto lol_5level; 8468 } 8469 8470 free_page(pml5); 8471 8472 done: 8473 skip_exit_vmcall(); 8474 enter_guest(); 8475 } 8476 8477 static void vmx_cr4_osxsave_test_guest(void) 8478 { 8479 write_cr4(read_cr4() & ~X86_CR4_OSXSAVE); 8480 } 8481 8482 /* 8483 * Ensure that kvm recalculates the L1 guest's CPUID.01H:ECX.OSXSAVE 8484 * after VM-exit from an L2 guest that sets CR4.OSXSAVE to a different 8485 * value than in L1. 8486 */ 8487 static void vmx_cr4_osxsave_test(void) 8488 { 8489 if (!this_cpu_has(X86_FEATURE_XSAVE)) { 8490 report_skip("XSAVE not detected"); 8491 return; 8492 } 8493 8494 if (!(read_cr4() & X86_CR4_OSXSAVE)) { 8495 unsigned long cr4 = read_cr4() | X86_CR4_OSXSAVE; 8496 8497 write_cr4(cr4); 8498 vmcs_write(GUEST_CR4, cr4); 8499 vmcs_write(HOST_CR4, cr4); 8500 } 8501 8502 TEST_ASSERT(cpuid_osxsave()); 8503 8504 test_set_guest(vmx_cr4_osxsave_test_guest); 8505 enter_guest(); 8506 8507 TEST_ASSERT(cpuid_osxsave()); 8508 } 8509 8510 static void vmx_nm_test_guest(void) 8511 { 8512 write_cr0(read_cr0() | X86_CR0_TS); 8513 asm volatile("fnop"); 8514 } 8515 8516 static void check_nm_exit(const char *test) 8517 { 8518 u32 reason = vmcs_read(EXI_REASON); 8519 u32 intr_info = vmcs_read(EXI_INTR_INFO); 8520 const u32 expected = INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 8521 NM_VECTOR; 8522 8523 report(reason == VMX_EXC_NMI && intr_info == expected, "%s", test); 8524 } 8525 8526 /* 8527 * This test checks that: 8528 * 8529 * (a) If L2 launches with CR0.TS clear, but later sets CR0.TS, then 8530 * a subsequent #NM VM-exit is reflected to L1. 8531 * 8532 * (b) If L2 launches with CR0.TS clear and CR0.EM set, then a 8533 * subsequent #NM VM-exit is reflected to L1. 8534 */ 8535 static void vmx_nm_test(void) 8536 { 8537 unsigned long cr0 = read_cr0(); 8538 8539 test_set_guest(vmx_nm_test_guest); 8540 8541 /* 8542 * L1 wants to intercept #NM exceptions encountered in L2. 8543 */ 8544 vmcs_write(EXC_BITMAP, 1 << NM_VECTOR); 8545 8546 /* 8547 * Launch L2 with CR0.TS clear, but don't claim host ownership of 8548 * any CR0 bits. L2 will set CR0.TS and then try to execute fnop, 8549 * which will raise #NM. L0 should reflect the #NM VM-exit to L1. 8550 */ 8551 vmcs_write(CR0_MASK, 0); 8552 vmcs_write(GUEST_CR0, cr0 & ~X86_CR0_TS); 8553 enter_guest(); 8554 check_nm_exit("fnop with CR0.TS set in L2 triggers #NM VM-exit to L1"); 8555 8556 /* 8557 * Re-enter L2 at the fnop instruction, with CR0.TS clear but 8558 * CR0.EM set. The fnop will still raise #NM, and L0 should 8559 * reflect the #NM VM-exit to L1. 8560 */ 8561 vmcs_write(GUEST_CR0, (cr0 & ~X86_CR0_TS) | X86_CR0_EM); 8562 enter_guest(); 8563 check_nm_exit("fnop with CR0.EM set in L2 triggers #NM VM-exit to L1"); 8564 8565 /* 8566 * Re-enter L2 at the fnop instruction, with both CR0.TS and 8567 * CR0.EM clear. There will be no #NM, and the L2 guest should 8568 * exit normally. 8569 */ 8570 vmcs_write(GUEST_CR0, cr0 & ~(X86_CR0_TS | X86_CR0_EM)); 8571 enter_guest(); 8572 } 8573 8574 bool vmx_pending_event_ipi_fired; 8575 static void vmx_pending_event_ipi_isr(isr_regs_t *regs) 8576 { 8577 vmx_pending_event_ipi_fired = true; 8578 eoi(); 8579 } 8580 8581 bool vmx_pending_event_guest_run; 8582 static void vmx_pending_event_guest(void) 8583 { 8584 vmcall(); 8585 vmx_pending_event_guest_run = true; 8586 } 8587 8588 static void vmx_pending_event_test_core(bool guest_hlt) 8589 { 8590 int ipi_vector = 0xf1; 8591 8592 vmx_pending_event_ipi_fired = false; 8593 handle_irq(ipi_vector, vmx_pending_event_ipi_isr); 8594 8595 vmx_pending_event_guest_run = false; 8596 test_set_guest(vmx_pending_event_guest); 8597 8598 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 8599 8600 enter_guest(); 8601 skip_exit_vmcall(); 8602 8603 if (guest_hlt) 8604 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8605 8606 irq_disable(); 8607 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | 8608 APIC_DM_FIXED | ipi_vector, 8609 0); 8610 8611 enter_guest(); 8612 8613 assert_exit_reason(VMX_EXTINT); 8614 report(!vmx_pending_event_guest_run, 8615 "Guest did not run before host received IPI"); 8616 8617 irq_enable(); 8618 asm volatile ("nop"); 8619 irq_disable(); 8620 report(vmx_pending_event_ipi_fired, 8621 "Got pending interrupt after IRQ enabled"); 8622 8623 if (guest_hlt) 8624 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 8625 8626 enter_guest(); 8627 report(vmx_pending_event_guest_run, 8628 "Guest finished running when no interrupt"); 8629 } 8630 8631 static void vmx_pending_event_test(void) 8632 { 8633 vmx_pending_event_test_core(false); 8634 } 8635 8636 static void vmx_pending_event_hlt_test(void) 8637 { 8638 vmx_pending_event_test_core(true); 8639 } 8640 8641 static int vmx_window_test_db_count; 8642 8643 static void vmx_window_test_db_handler(struct ex_regs *regs) 8644 { 8645 vmx_window_test_db_count++; 8646 } 8647 8648 static void vmx_nmi_window_test_guest(void) 8649 { 8650 handle_exception(DB_VECTOR, vmx_window_test_db_handler); 8651 8652 asm volatile("vmcall\n\t" 8653 "nop\n\t"); 8654 8655 handle_exception(DB_VECTOR, NULL); 8656 } 8657 8658 static void verify_nmi_window_exit(u64 rip) 8659 { 8660 u32 exit_reason = vmcs_read(EXI_REASON); 8661 8662 report(exit_reason == VMX_NMI_WINDOW, 8663 "Exit reason (%d) is 'NMI window'", exit_reason); 8664 report(vmcs_read(GUEST_RIP) == rip, "RIP (%#lx) is %#lx", 8665 vmcs_read(GUEST_RIP), rip); 8666 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 8667 } 8668 8669 static void vmx_nmi_window_test(void) 8670 { 8671 u64 nop_addr; 8672 void *db_fault_addr = get_idt_addr(&boot_idt[DB_VECTOR]); 8673 8674 if (!(ctrl_pin_rev.clr & PIN_VIRT_NMI)) { 8675 report_skip("CPU does not support the \"Virtual NMIs\" VM-execution control."); 8676 return; 8677 } 8678 8679 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 8680 report_skip("CPU does not support the \"NMI-window exiting\" VM-execution control."); 8681 return; 8682 } 8683 8684 vmx_window_test_db_count = 0; 8685 8686 report_prefix_push("NMI-window"); 8687 test_set_guest(vmx_nmi_window_test_guest); 8688 vmcs_set_bits(PIN_CONTROLS, PIN_VIRT_NMI); 8689 enter_guest(); 8690 skip_exit_vmcall(); 8691 nop_addr = vmcs_read(GUEST_RIP); 8692 8693 /* 8694 * Ask for "NMI-window exiting," and expect an immediate VM-exit. 8695 * RIP will not advance. 8696 */ 8697 report_prefix_push("active, no blocking"); 8698 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 8699 enter_guest(); 8700 verify_nmi_window_exit(nop_addr); 8701 report_prefix_pop(); 8702 8703 /* 8704 * Ask for "NMI-window exiting" in a MOV-SS shadow, and expect 8705 * a VM-exit on the next instruction after the nop. (The nop 8706 * is one byte.) 8707 */ 8708 report_prefix_push("active, blocking by MOV-SS"); 8709 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 8710 enter_guest(); 8711 verify_nmi_window_exit(nop_addr + 1); 8712 report_prefix_pop(); 8713 8714 /* 8715 * Ask for "NMI-window exiting" (with event injection), and 8716 * expect a VM-exit after the event is injected. (RIP should 8717 * be at the address specified in the IDT entry for #DB.) 8718 */ 8719 report_prefix_push("active, no blocking, injecting #DB"); 8720 vmcs_write(ENT_INTR_INFO, 8721 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 8722 enter_guest(); 8723 verify_nmi_window_exit((u64)db_fault_addr); 8724 report_prefix_pop(); 8725 8726 /* 8727 * Ask for "NMI-window exiting" with NMI blocking, and expect 8728 * a VM-exit after the next IRET (i.e. after the #DB handler 8729 * returns). So, RIP should be back at one byte past the nop. 8730 */ 8731 report_prefix_push("active, blocking by NMI"); 8732 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_NMI); 8733 enter_guest(); 8734 verify_nmi_window_exit(nop_addr + 1); 8735 report(vmx_window_test_db_count == 1, 8736 "#DB handler executed once (actual %d times)", 8737 vmx_window_test_db_count); 8738 report_prefix_pop(); 8739 8740 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 8741 report_skip("CPU does not support activity state HLT."); 8742 } else { 8743 /* 8744 * Ask for "NMI-window exiting" when entering activity 8745 * state HLT, and expect an immediate VM-exit. RIP is 8746 * still one byte past the nop. 8747 */ 8748 report_prefix_push("halted, no blocking"); 8749 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8750 enter_guest(); 8751 verify_nmi_window_exit(nop_addr + 1); 8752 report_prefix_pop(); 8753 8754 /* 8755 * Ask for "NMI-window exiting" when entering activity 8756 * state HLT (with event injection), and expect a 8757 * VM-exit after the event is injected. (RIP should be 8758 * at the address specified in the IDT entry for #DB.) 8759 */ 8760 report_prefix_push("halted, no blocking, injecting #DB"); 8761 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8762 vmcs_write(ENT_INTR_INFO, 8763 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 8764 DB_VECTOR); 8765 enter_guest(); 8766 verify_nmi_window_exit((u64)db_fault_addr); 8767 report_prefix_pop(); 8768 } 8769 8770 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 8771 enter_guest(); 8772 report_prefix_pop(); 8773 } 8774 8775 static void vmx_intr_window_test_guest(void) 8776 { 8777 handle_exception(DB_VECTOR, vmx_window_test_db_handler); 8778 8779 /* 8780 * The two consecutive STIs are to ensure that only the first 8781 * one has a shadow. Note that NOP and STI are one byte 8782 * instructions. 8783 */ 8784 asm volatile("vmcall\n\t" 8785 "nop\n\t" 8786 "sti\n\t" 8787 "sti\n\t"); 8788 8789 handle_exception(DB_VECTOR, NULL); 8790 } 8791 8792 static void verify_intr_window_exit(u64 rip) 8793 { 8794 u32 exit_reason = vmcs_read(EXI_REASON); 8795 8796 report(exit_reason == VMX_INTR_WINDOW, 8797 "Exit reason (%d) is 'interrupt window'", exit_reason); 8798 report(vmcs_read(GUEST_RIP) == rip, "RIP (%#lx) is %#lx", 8799 vmcs_read(GUEST_RIP), rip); 8800 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 8801 } 8802 8803 static void vmx_intr_window_test(void) 8804 { 8805 u64 vmcall_addr; 8806 u64 nop_addr; 8807 unsigned int orig_db_gate_type; 8808 void *db_fault_addr = get_idt_addr(&boot_idt[DB_VECTOR]); 8809 8810 if (!(ctrl_cpu_rev[0].clr & CPU_INTR_WINDOW)) { 8811 report_skip("CPU does not support the \"interrupt-window exiting\" VM-execution control."); 8812 return; 8813 } 8814 8815 /* 8816 * Change the IDT entry for #DB from interrupt gate to trap gate, 8817 * so that it won't clear RFLAGS.IF. We don't want interrupts to 8818 * be disabled after vectoring a #DB. 8819 */ 8820 orig_db_gate_type = boot_idt[DB_VECTOR].type; 8821 boot_idt[DB_VECTOR].type = 15; 8822 8823 report_prefix_push("interrupt-window"); 8824 test_set_guest(vmx_intr_window_test_guest); 8825 enter_guest(); 8826 assert_exit_reason(VMX_VMCALL); 8827 vmcall_addr = vmcs_read(GUEST_RIP); 8828 8829 /* 8830 * Ask for "interrupt-window exiting" with RFLAGS.IF set and 8831 * no blocking; expect an immediate VM-exit. Note that we have 8832 * not advanced past the vmcall instruction yet, so RIP should 8833 * point to the vmcall instruction. 8834 */ 8835 report_prefix_push("active, no blocking, RFLAGS.IF=1"); 8836 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8837 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_IF); 8838 enter_guest(); 8839 verify_intr_window_exit(vmcall_addr); 8840 report_prefix_pop(); 8841 8842 /* 8843 * Ask for "interrupt-window exiting" (with event injection) 8844 * with RFLAGS.IF set and no blocking; expect a VM-exit after 8845 * the event is injected. That is, RIP should should be at the 8846 * address specified in the IDT entry for #DB. 8847 */ 8848 report_prefix_push("active, no blocking, RFLAGS.IF=1, injecting #DB"); 8849 vmcs_write(ENT_INTR_INFO, 8850 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 8851 vmcall_addr = vmcs_read(GUEST_RIP); 8852 enter_guest(); 8853 verify_intr_window_exit((u64)db_fault_addr); 8854 report_prefix_pop(); 8855 8856 /* 8857 * Let the L2 guest run through the IRET, back to the VMCALL. 8858 * We have to clear the "interrupt-window exiting" 8859 * VM-execution control, or it would just keep causing 8860 * VM-exits. Then, advance past the VMCALL and set the 8861 * "interrupt-window exiting" VM-execution control again. 8862 */ 8863 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8864 enter_guest(); 8865 skip_exit_vmcall(); 8866 nop_addr = vmcs_read(GUEST_RIP); 8867 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8868 8869 /* 8870 * Ask for "interrupt-window exiting" in a MOV-SS shadow with 8871 * RFLAGS.IF set, and expect a VM-exit on the next 8872 * instruction. (NOP is one byte.) 8873 */ 8874 report_prefix_push("active, blocking by MOV-SS, RFLAGS.IF=1"); 8875 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 8876 enter_guest(); 8877 verify_intr_window_exit(nop_addr + 1); 8878 report_prefix_pop(); 8879 8880 /* 8881 * Back up to the NOP and ask for "interrupt-window exiting" 8882 * in an STI shadow with RFLAGS.IF set, and expect a VM-exit 8883 * on the next instruction. (NOP is one byte.) 8884 */ 8885 report_prefix_push("active, blocking by STI, RFLAGS.IF=1"); 8886 vmcs_write(GUEST_RIP, nop_addr); 8887 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_STI); 8888 enter_guest(); 8889 verify_intr_window_exit(nop_addr + 1); 8890 report_prefix_pop(); 8891 8892 /* 8893 * Ask for "interrupt-window exiting" with RFLAGS.IF clear, 8894 * and expect a VM-exit on the instruction following the STI 8895 * shadow. Only the first STI (which is one byte past the NOP) 8896 * should have a shadow. The second STI (which is two bytes 8897 * past the NOP) has no shadow. Therefore, the interrupt 8898 * window opens at three bytes past the NOP. 8899 */ 8900 report_prefix_push("active, RFLAGS.IF = 0"); 8901 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 8902 enter_guest(); 8903 verify_intr_window_exit(nop_addr + 3); 8904 report_prefix_pop(); 8905 8906 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 8907 report_skip("CPU does not support activity state HLT."); 8908 } else { 8909 /* 8910 * Ask for "interrupt-window exiting" when entering 8911 * activity state HLT, and expect an immediate 8912 * VM-exit. RIP is still three bytes past the nop. 8913 */ 8914 report_prefix_push("halted, no blocking"); 8915 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8916 enter_guest(); 8917 verify_intr_window_exit(nop_addr + 3); 8918 report_prefix_pop(); 8919 8920 /* 8921 * Ask for "interrupt-window exiting" when entering 8922 * activity state HLT (with event injection), and 8923 * expect a VM-exit after the event is injected. That 8924 * is, RIP should should be at the address specified 8925 * in the IDT entry for #DB. 8926 */ 8927 report_prefix_push("halted, no blocking, injecting #DB"); 8928 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8929 vmcs_write(ENT_INTR_INFO, 8930 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 8931 DB_VECTOR); 8932 enter_guest(); 8933 verify_intr_window_exit((u64)db_fault_addr); 8934 report_prefix_pop(); 8935 } 8936 8937 boot_idt[DB_VECTOR].type = orig_db_gate_type; 8938 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8939 enter_guest(); 8940 report_prefix_pop(); 8941 } 8942 8943 #define GUEST_TSC_OFFSET (1u << 30) 8944 8945 static u64 guest_tsc; 8946 8947 static void vmx_store_tsc_test_guest(void) 8948 { 8949 guest_tsc = rdtsc(); 8950 } 8951 8952 /* 8953 * This test ensures that when IA32_TSC is in the VM-exit MSR-store 8954 * list, the value saved is not subject to the TSC offset that is 8955 * applied to RDTSC/RDTSCP/RDMSR(IA32_TSC) in guest execution. 8956 */ 8957 static void vmx_store_tsc_test(void) 8958 { 8959 struct vmx_msr_entry msr_entry = { .index = MSR_IA32_TSC }; 8960 u64 low, high; 8961 8962 if (!(ctrl_cpu_rev[0].clr & CPU_USE_TSC_OFFSET)) { 8963 report_skip("'Use TSC offsetting' not supported"); 8964 return; 8965 } 8966 8967 test_set_guest(vmx_store_tsc_test_guest); 8968 8969 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_USE_TSC_OFFSET); 8970 vmcs_write(EXI_MSR_ST_CNT, 1); 8971 vmcs_write(EXIT_MSR_ST_ADDR, virt_to_phys(&msr_entry)); 8972 vmcs_write(TSC_OFFSET, GUEST_TSC_OFFSET); 8973 8974 low = rdtsc(); 8975 enter_guest(); 8976 high = rdtsc(); 8977 8978 report(low + GUEST_TSC_OFFSET <= guest_tsc && 8979 guest_tsc <= high + GUEST_TSC_OFFSET, 8980 "RDTSC value in the guest (%lu) is in range [%lu, %lu]", 8981 guest_tsc, low + GUEST_TSC_OFFSET, high + GUEST_TSC_OFFSET); 8982 report(low <= msr_entry.value && msr_entry.value <= high, 8983 "IA32_TSC value saved in the VM-exit MSR-store list (%lu) is in range [%lu, %lu]", 8984 msr_entry.value, low, high); 8985 } 8986 8987 static void vmx_preemption_timer_zero_test_db_handler(struct ex_regs *regs) 8988 { 8989 } 8990 8991 static void vmx_preemption_timer_zero_test_guest(void) 8992 { 8993 while (vmx_get_test_stage() < 3) 8994 vmcall(); 8995 } 8996 8997 static void vmx_preemption_timer_zero_activate_preemption_timer(void) 8998 { 8999 vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT); 9000 vmcs_write(PREEMPT_TIMER_VALUE, 0); 9001 } 9002 9003 static void vmx_preemption_timer_zero_advance_past_vmcall(void) 9004 { 9005 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 9006 enter_guest(); 9007 skip_exit_vmcall(); 9008 } 9009 9010 static void vmx_preemption_timer_zero_inject_db(bool intercept_db) 9011 { 9012 vmx_preemption_timer_zero_activate_preemption_timer(); 9013 vmcs_write(ENT_INTR_INFO, INTR_INFO_VALID_MASK | 9014 INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 9015 vmcs_write(EXC_BITMAP, intercept_db ? 1 << DB_VECTOR : 0); 9016 enter_guest(); 9017 } 9018 9019 static void vmx_preemption_timer_zero_set_pending_dbg(u32 exception_bitmap) 9020 { 9021 vmx_preemption_timer_zero_activate_preemption_timer(); 9022 vmcs_write(GUEST_PENDING_DEBUG, BIT(12) | DR_TRAP1); 9023 vmcs_write(EXC_BITMAP, exception_bitmap); 9024 enter_guest(); 9025 } 9026 9027 static void vmx_preemption_timer_zero_expect_preempt_at_rip(u64 expected_rip) 9028 { 9029 u32 reason = (u32)vmcs_read(EXI_REASON); 9030 u64 guest_rip = vmcs_read(GUEST_RIP); 9031 9032 report(reason == VMX_PREEMPT && guest_rip == expected_rip, 9033 "Exit reason is 0x%x (expected 0x%x) and guest RIP is %lx (0x%lx expected).", 9034 reason, VMX_PREEMPT, guest_rip, expected_rip); 9035 } 9036 9037 /* 9038 * This test ensures that when the VMX preemption timer is zero at 9039 * VM-entry, a VM-exit occurs after any event injection and after any 9040 * pending debug exceptions are raised, but before execution of any 9041 * guest instructions. 9042 */ 9043 static void vmx_preemption_timer_zero_test(void) 9044 { 9045 u64 db_fault_address = (u64)get_idt_addr(&boot_idt[DB_VECTOR]); 9046 handler old_db; 9047 u32 reason; 9048 9049 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 9050 report_skip("'Activate VMX-preemption timer' not supported"); 9051 return; 9052 } 9053 9054 /* 9055 * Install a custom #DB handler that doesn't abort. 9056 */ 9057 old_db = handle_exception(DB_VECTOR, 9058 vmx_preemption_timer_zero_test_db_handler); 9059 9060 test_set_guest(vmx_preemption_timer_zero_test_guest); 9061 9062 /* 9063 * VMX-preemption timer should fire after event injection. 9064 */ 9065 vmx_set_test_stage(0); 9066 vmx_preemption_timer_zero_inject_db(0); 9067 vmx_preemption_timer_zero_expect_preempt_at_rip(db_fault_address); 9068 vmx_preemption_timer_zero_advance_past_vmcall(); 9069 9070 /* 9071 * VMX-preemption timer should fire after event injection. 9072 * Exception bitmap is irrelevant, since you can't intercept 9073 * an event that you injected. 9074 */ 9075 vmx_set_test_stage(1); 9076 vmx_preemption_timer_zero_inject_db(true); 9077 vmx_preemption_timer_zero_expect_preempt_at_rip(db_fault_address); 9078 vmx_preemption_timer_zero_advance_past_vmcall(); 9079 9080 /* 9081 * VMX-preemption timer should fire after pending debug exceptions 9082 * have delivered a #DB trap. 9083 */ 9084 vmx_set_test_stage(2); 9085 vmx_preemption_timer_zero_set_pending_dbg(0); 9086 vmx_preemption_timer_zero_expect_preempt_at_rip(db_fault_address); 9087 vmx_preemption_timer_zero_advance_past_vmcall(); 9088 9089 /* 9090 * VMX-preemption timer would fire after pending debug exceptions 9091 * have delivered a #DB trap, but in this case, the #DB trap is 9092 * intercepted. 9093 */ 9094 vmx_set_test_stage(3); 9095 vmx_preemption_timer_zero_set_pending_dbg(1 << DB_VECTOR); 9096 reason = (u32)vmcs_read(EXI_REASON); 9097 report(reason == VMX_EXC_NMI, "Exit reason is 0x%x (expected 0x%x)", 9098 reason, VMX_EXC_NMI); 9099 9100 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 9101 enter_guest(); 9102 9103 handle_exception(DB_VECTOR, old_db); 9104 } 9105 9106 static u64 vmx_preemption_timer_tf_test_prev_rip; 9107 9108 static void vmx_preemption_timer_tf_test_db_handler(struct ex_regs *regs) 9109 { 9110 extern char vmx_preemption_timer_tf_test_endloop; 9111 9112 if (vmx_get_test_stage() == 2) { 9113 /* 9114 * Stage 2 means that we're done, one way or another. 9115 * Arrange for the iret to drop us out of the wbinvd 9116 * loop and stop single-stepping. 9117 */ 9118 regs->rip = (u64)&vmx_preemption_timer_tf_test_endloop; 9119 regs->rflags &= ~X86_EFLAGS_TF; 9120 } else if (regs->rip == vmx_preemption_timer_tf_test_prev_rip) { 9121 /* 9122 * The RIP should alternate between the wbinvd and the 9123 * jmp instruction in the code below. If we ever see 9124 * the same instruction twice in a row, that means a 9125 * single-step trap has been dropped. Let the 9126 * hypervisor know about the failure by executing a 9127 * VMCALL. 9128 */ 9129 vmcall(); 9130 } 9131 vmx_preemption_timer_tf_test_prev_rip = regs->rip; 9132 } 9133 9134 static void vmx_preemption_timer_tf_test_guest(void) 9135 { 9136 /* 9137 * The hypervisor doesn't intercept WBINVD, so the loop below 9138 * shouldn't be a problem--it's just two instructions 9139 * executing in VMX non-root mode. However, when the 9140 * hypervisor is running in a virtual environment, the parent 9141 * hypervisor might intercept WBINVD and emulate it. If the 9142 * parent hypervisor is broken, the single-step trap after the 9143 * WBINVD might be lost. 9144 */ 9145 asm volatile("vmcall\n\t" 9146 "0: wbinvd\n\t" 9147 "1: jmp 0b\n\t" 9148 "vmx_preemption_timer_tf_test_endloop:"); 9149 } 9150 9151 /* 9152 * Ensure that the delivery of a "VMX-preemption timer expired" 9153 * VM-exit doesn't disrupt single-stepping in the guest. Note that 9154 * passing this test doesn't ensure correctness, because the test will 9155 * only fail if the VMX-preemtion timer fires at the right time (or 9156 * the wrong time, as it were). 9157 */ 9158 static void vmx_preemption_timer_tf_test(void) 9159 { 9160 handler old_db; 9161 u32 reason; 9162 int i; 9163 9164 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 9165 report_skip("'Activate VMX-preemption timer' not supported"); 9166 return; 9167 } 9168 9169 old_db = handle_exception(DB_VECTOR, 9170 vmx_preemption_timer_tf_test_db_handler); 9171 9172 test_set_guest(vmx_preemption_timer_tf_test_guest); 9173 9174 enter_guest(); 9175 skip_exit_vmcall(); 9176 9177 vmx_set_test_stage(1); 9178 vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT); 9179 vmcs_write(PREEMPT_TIMER_VALUE, 50000); 9180 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_TF); 9181 9182 /* 9183 * The only exit we should see is "VMX-preemption timer 9184 * expired." If we get a VMCALL exit, that means the #DB 9185 * handler has detected a missing single-step trap. It doesn't 9186 * matter where the guest RIP is when the VMX-preemption timer 9187 * expires (whether it's in the WBINVD loop or in the #DB 9188 * handler)--a single-step trap should never be discarded. 9189 */ 9190 for (i = 0; i < 10000; i++) { 9191 enter_guest(); 9192 reason = (u32)vmcs_read(EXI_REASON); 9193 if (reason == VMX_PREEMPT) 9194 continue; 9195 TEST_ASSERT(reason == VMX_VMCALL); 9196 skip_exit_insn(); 9197 break; 9198 } 9199 9200 report(reason == VMX_PREEMPT, "No single-step traps skipped"); 9201 9202 vmx_set_test_stage(2); 9203 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 9204 enter_guest(); 9205 9206 handle_exception(DB_VECTOR, old_db); 9207 } 9208 9209 #define VMX_PREEMPTION_TIMER_EXPIRY_CYCLES 1000000 9210 9211 static u64 vmx_preemption_timer_expiry_start; 9212 static u64 vmx_preemption_timer_expiry_finish; 9213 9214 static void vmx_preemption_timer_expiry_test_guest(void) 9215 { 9216 vmcall(); 9217 vmx_preemption_timer_expiry_start = fenced_rdtsc(); 9218 9219 while (vmx_get_test_stage() == 0) 9220 vmx_preemption_timer_expiry_finish = fenced_rdtsc(); 9221 } 9222 9223 /* 9224 * Test that the VMX-preemption timer is not excessively delayed. 9225 * 9226 * Per the SDM, volume 3, VM-entry starts the VMX-preemption timer 9227 * with the unsigned value in the VMX-preemption timer-value field, 9228 * and the VMX-preemption timer counts down by 1 every time bit X in 9229 * the TSC changes due to a TSC increment (where X is 9230 * IA32_VMX_MISC[4:0]). If the timer counts down to zero in any state 9231 * other than the wait-for-SIPI state, the logical processor 9232 * transitions to the C0 C-state and causes a VM-exit. 9233 * 9234 * The guest code above reads the starting TSC after VM-entry. At this 9235 * point, the VMX-preemption timer has already been activated. Next, 9236 * the guest code reads the current TSC in a loop, storing the value 9237 * read to memory. 9238 * 9239 * If the RDTSC in the loop reads a value past the VMX-preemption 9240 * timer deadline, then the VMX-preemption timer VM-exit must be 9241 * delivered before the next instruction retires. Even if a higher 9242 * priority SMI is delivered first, the VMX-preemption timer VM-exit 9243 * must be delivered before the next instruction retires. Hence, a TSC 9244 * value past the VMX-preemption timer deadline might be read, but it 9245 * cannot be stored. If a TSC value past the deadline *is* stored, 9246 * then the architectural specification has been violated. 9247 */ 9248 static void vmx_preemption_timer_expiry_test(void) 9249 { 9250 u32 preemption_timer_value; 9251 union vmx_misc misc; 9252 u64 tsc_deadline; 9253 u32 reason; 9254 9255 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 9256 report_skip("'Activate VMX-preemption timer' not supported"); 9257 return; 9258 } 9259 9260 test_set_guest(vmx_preemption_timer_expiry_test_guest); 9261 9262 enter_guest(); 9263 skip_exit_vmcall(); 9264 9265 misc.val = rdmsr(MSR_IA32_VMX_MISC); 9266 preemption_timer_value = 9267 VMX_PREEMPTION_TIMER_EXPIRY_CYCLES >> misc.pt_bit; 9268 9269 vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT); 9270 vmcs_write(PREEMPT_TIMER_VALUE, preemption_timer_value); 9271 vmx_set_test_stage(0); 9272 9273 enter_guest(); 9274 reason = (u32)vmcs_read(EXI_REASON); 9275 TEST_ASSERT(reason == VMX_PREEMPT); 9276 9277 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 9278 vmx_set_test_stage(1); 9279 enter_guest(); 9280 9281 tsc_deadline = ((vmx_preemption_timer_expiry_start >> misc.pt_bit) << 9282 misc.pt_bit) + (preemption_timer_value << misc.pt_bit); 9283 9284 report(vmx_preemption_timer_expiry_finish < tsc_deadline, 9285 "Last stored guest TSC (%lu) < TSC deadline (%lu)", 9286 vmx_preemption_timer_expiry_finish, tsc_deadline); 9287 } 9288 9289 static void vmx_db_test_guest(void) 9290 { 9291 /* 9292 * For a hardware generated single-step #DB. 9293 */ 9294 asm volatile("vmcall;" 9295 "nop;" 9296 ".Lpost_nop:"); 9297 /* 9298 * ...in a MOVSS shadow, with pending debug exceptions. 9299 */ 9300 asm volatile("vmcall;" 9301 "nop;" 9302 ".Lpost_movss_nop:"); 9303 /* 9304 * For an L0 synthesized single-step #DB. (L0 intercepts WBINVD and 9305 * emulates it in software.) 9306 */ 9307 asm volatile("vmcall;" 9308 "wbinvd;" 9309 ".Lpost_wbinvd:"); 9310 /* 9311 * ...in a MOVSS shadow, with pending debug exceptions. 9312 */ 9313 asm volatile("vmcall;" 9314 "wbinvd;" 9315 ".Lpost_movss_wbinvd:"); 9316 /* 9317 * For a hardware generated single-step #DB in a transactional region. 9318 */ 9319 asm volatile("vmcall;" 9320 ".Lxbegin: xbegin .Lskip_rtm;" 9321 "xend;" 9322 ".Lskip_rtm:"); 9323 } 9324 9325 /* 9326 * Clear the pending debug exceptions and RFLAGS.TF and re-enter 9327 * L2. No #DB is delivered and L2 continues to the next point of 9328 * interest. 9329 */ 9330 static void dismiss_db(void) 9331 { 9332 vmcs_write(GUEST_PENDING_DEBUG, 0); 9333 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 9334 enter_guest(); 9335 } 9336 9337 /* 9338 * Check a variety of VMCS fields relevant to an intercepted #DB exception. 9339 * Then throw away the #DB exception and resume L2. 9340 */ 9341 static void check_db_exit(bool xfail_qual, bool xfail_dr6, bool xfail_pdbg, 9342 void *expected_rip, u64 expected_exit_qual, 9343 u64 expected_dr6) 9344 { 9345 u32 reason = vmcs_read(EXI_REASON); 9346 u32 intr_info = vmcs_read(EXI_INTR_INFO); 9347 u64 exit_qual = vmcs_read(EXI_QUALIFICATION); 9348 u64 guest_rip = vmcs_read(GUEST_RIP); 9349 u64 guest_pending_dbg = vmcs_read(GUEST_PENDING_DEBUG); 9350 u64 dr6 = read_dr6(); 9351 const u32 expected_intr_info = INTR_INFO_VALID_MASK | 9352 INTR_TYPE_HARD_EXCEPTION | DB_VECTOR; 9353 9354 report(reason == VMX_EXC_NMI && intr_info == expected_intr_info, 9355 "Expected #DB VM-exit"); 9356 report((u64)expected_rip == guest_rip, "Expected RIP %p (actual %lx)", 9357 expected_rip, guest_rip); 9358 report_xfail(xfail_pdbg, 0 == guest_pending_dbg, 9359 "Expected pending debug exceptions 0 (actual %lx)", 9360 guest_pending_dbg); 9361 report_xfail(xfail_qual, expected_exit_qual == exit_qual, 9362 "Expected exit qualification %lx (actual %lx)", 9363 expected_exit_qual, exit_qual); 9364 report_xfail(xfail_dr6, expected_dr6 == dr6, 9365 "Expected DR6 %lx (actual %lx)", expected_dr6, dr6); 9366 dismiss_db(); 9367 } 9368 9369 /* 9370 * Assuming the guest has just exited on a VMCALL instruction, skip 9371 * over the vmcall, and set the guest's RFLAGS.TF in the VMCS. If 9372 * pending debug exceptions are non-zero, set the VMCS up as if the 9373 * previous instruction was a MOVSS that generated the indicated 9374 * pending debug exceptions. Then enter L2. 9375 */ 9376 static void single_step_guest(const char *test_name, u64 starting_dr6, 9377 u64 pending_debug_exceptions) 9378 { 9379 printf("\n%s\n", test_name); 9380 skip_exit_vmcall(); 9381 write_dr6(starting_dr6); 9382 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_TF); 9383 if (pending_debug_exceptions) { 9384 vmcs_write(GUEST_PENDING_DEBUG, pending_debug_exceptions); 9385 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 9386 } 9387 enter_guest(); 9388 } 9389 9390 /* 9391 * When L1 intercepts #DB, verify that a single-step trap clears 9392 * pending debug exceptions, populates the exit qualification field 9393 * properly, and that DR6 is not prematurely clobbered. In a 9394 * (simulated) MOVSS shadow, make sure that the pending debug 9395 * exception bits are properly accumulated into the exit qualification 9396 * field. 9397 */ 9398 static void vmx_db_test(void) 9399 { 9400 /* 9401 * We are going to set a few arbitrary bits in DR6 to verify that 9402 * (a) DR6 is not modified by an intercepted #DB, and 9403 * (b) stale bits in DR6 (DR6.BD, in particular) don't leak into 9404 * the exit qualification field for a subsequent #DB exception. 9405 */ 9406 const u64 starting_dr6 = DR6_RESERVED | BIT(13) | DR_TRAP3 | DR_TRAP1; 9407 extern char post_nop asm(".Lpost_nop"); 9408 extern char post_movss_nop asm(".Lpost_movss_nop"); 9409 extern char post_wbinvd asm(".Lpost_wbinvd"); 9410 extern char post_movss_wbinvd asm(".Lpost_movss_wbinvd"); 9411 extern char xbegin asm(".Lxbegin"); 9412 extern char skip_rtm asm(".Lskip_rtm"); 9413 9414 /* 9415 * L1 wants to intercept #DB exceptions encountered in L2. 9416 */ 9417 vmcs_write(EXC_BITMAP, BIT(DB_VECTOR)); 9418 9419 /* 9420 * Start L2 and run it up to the first point of interest. 9421 */ 9422 test_set_guest(vmx_db_test_guest); 9423 enter_guest(); 9424 9425 /* 9426 * Hardware-delivered #DB trap for single-step sets the 9427 * standard that L0 has to follow for emulated instructions. 9428 */ 9429 single_step_guest("Hardware delivered single-step", starting_dr6, 0); 9430 check_db_exit(false, false, false, &post_nop, DR_STEP, starting_dr6); 9431 9432 /* 9433 * Hardware-delivered #DB trap for single-step in MOVSS shadow 9434 * also sets the standard that L0 has to follow for emulated 9435 * instructions. Here, we establish the VMCS pending debug 9436 * exceptions to indicate that the simulated MOVSS triggered a 9437 * data breakpoint as well as the single-step trap. 9438 */ 9439 single_step_guest("Hardware delivered single-step in MOVSS shadow", 9440 starting_dr6, BIT(12) | DR_STEP | DR_TRAP0 ); 9441 check_db_exit(false, false, false, &post_movss_nop, DR_STEP | DR_TRAP0, 9442 starting_dr6); 9443 9444 /* 9445 * L0 synthesized #DB trap for single-step is buggy, because 9446 * kvm (a) clobbers DR6 too early, and (b) tries its best to 9447 * reconstitute the exit qualification from the prematurely 9448 * modified DR6, but fails miserably. 9449 */ 9450 single_step_guest("Software synthesized single-step", starting_dr6, 0); 9451 check_db_exit(false, false, false, &post_wbinvd, DR_STEP, starting_dr6); 9452 9453 /* 9454 * L0 synthesized #DB trap for single-step in MOVSS shadow is 9455 * even worse, because L0 also leaves the pending debug 9456 * exceptions in the VMCS instead of accumulating them into 9457 * the exit qualification field for the #DB exception. 9458 */ 9459 single_step_guest("Software synthesized single-step in MOVSS shadow", 9460 starting_dr6, BIT(12) | DR_STEP | DR_TRAP0); 9461 check_db_exit(true, false, true, &post_movss_wbinvd, DR_STEP | DR_TRAP0, 9462 starting_dr6); 9463 9464 /* 9465 * Optional RTM test for hardware that supports RTM, to 9466 * demonstrate that the current volume 3 of the SDM 9467 * (325384-067US), table 27-1 is incorrect. Bit 16 of the exit 9468 * qualification for debug exceptions is not reserved. It is 9469 * set to 1 if a debug exception (#DB) or a breakpoint 9470 * exception (#BP) occurs inside an RTM region while advanced 9471 * debugging of RTM transactional regions is enabled. 9472 */ 9473 if (this_cpu_has(X86_FEATURE_RTM)) { 9474 vmcs_write(ENT_CONTROLS, 9475 vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 9476 /* 9477 * Set DR7.RTM[bit 11] and IA32_DEBUGCTL.RTM[bit 15] 9478 * in the guest to enable advanced debugging of RTM 9479 * transactional regions. 9480 */ 9481 vmcs_write(GUEST_DR7, BIT(11)); 9482 vmcs_write(GUEST_DEBUGCTL, BIT(15)); 9483 single_step_guest("Hardware delivered single-step in " 9484 "transactional region", starting_dr6, 0); 9485 check_db_exit(false, false, false, &xbegin, BIT(16), 9486 starting_dr6); 9487 } else { 9488 vmcs_write(GUEST_RIP, (u64)&skip_rtm); 9489 enter_guest(); 9490 } 9491 } 9492 9493 static void enable_vid(void) 9494 { 9495 void *virtual_apic_page; 9496 9497 assert(cpu_has_apicv()); 9498 9499 disable_intercept_for_x2apic_msrs(); 9500 9501 virtual_apic_page = alloc_page(); 9502 vmcs_write(APIC_VIRT_ADDR, (u64)virtual_apic_page); 9503 9504 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 9505 9506 vmcs_write(EOI_EXIT_BITMAP0, 0x0); 9507 vmcs_write(EOI_EXIT_BITMAP1, 0x0); 9508 vmcs_write(EOI_EXIT_BITMAP2, 0x0); 9509 vmcs_write(EOI_EXIT_BITMAP3, 0x0); 9510 9511 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY | CPU_TPR_SHADOW); 9512 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_VINTD | CPU_VIRT_X2APIC); 9513 } 9514 9515 static void trigger_ioapic_scan_thread(void *data) 9516 { 9517 /* Wait until other CPU entered L2 */ 9518 while (vmx_get_test_stage() != 1) 9519 ; 9520 9521 /* Trigger ioapic scan */ 9522 ioapic_set_redir(0xf, 0x79, TRIGGER_LEVEL); 9523 vmx_set_test_stage(2); 9524 } 9525 9526 static void irq_79_handler_guest(isr_regs_t *regs) 9527 { 9528 eoi(); 9529 9530 /* L1 expects vmexit on VMX_VMCALL and not VMX_EOI_INDUCED */ 9531 vmcall(); 9532 } 9533 9534 /* 9535 * Constant for num of busy-loop iterations after which 9536 * a timer interrupt should have happened in host 9537 */ 9538 #define TIMER_INTERRUPT_DELAY 100000000 9539 9540 static void vmx_eoi_bitmap_ioapic_scan_test_guest(void) 9541 { 9542 handle_irq(0x79, irq_79_handler_guest); 9543 irq_enable(); 9544 9545 /* Signal to L1 CPU to trigger ioapic scan */ 9546 vmx_set_test_stage(1); 9547 /* Wait until L1 CPU to trigger ioapic scan */ 9548 while (vmx_get_test_stage() != 2) 9549 ; 9550 9551 /* 9552 * Wait for L0 timer interrupt to be raised while we run in L2 9553 * such that L0 will process the IOAPIC scan request before 9554 * resuming L2 9555 */ 9556 delay(TIMER_INTERRUPT_DELAY); 9557 9558 asm volatile ("int $0x79"); 9559 } 9560 9561 static void vmx_eoi_bitmap_ioapic_scan_test(void) 9562 { 9563 if (!cpu_has_apicv() || (cpu_count() < 2)) { 9564 report_skip(__func__); 9565 return; 9566 } 9567 9568 enable_vid(); 9569 9570 on_cpu_async(1, trigger_ioapic_scan_thread, NULL); 9571 test_set_guest(vmx_eoi_bitmap_ioapic_scan_test_guest); 9572 9573 /* 9574 * Launch L2. 9575 * We expect the exit reason to be VMX_VMCALL (and not EOI INDUCED). 9576 * In case the reason isn't VMX_VMCALL, the asserion inside 9577 * skip_exit_vmcall() will fail. 9578 */ 9579 enter_guest(); 9580 skip_exit_vmcall(); 9581 9582 /* Let L2 finish */ 9583 enter_guest(); 9584 report(1, __func__); 9585 } 9586 9587 #define HLT_WITH_RVI_VECTOR (0xf1) 9588 9589 bool vmx_hlt_with_rvi_guest_isr_fired; 9590 static void vmx_hlt_with_rvi_guest_isr(isr_regs_t *regs) 9591 { 9592 vmx_hlt_with_rvi_guest_isr_fired = true; 9593 eoi(); 9594 } 9595 9596 static void vmx_hlt_with_rvi_guest(void) 9597 { 9598 handle_irq(HLT_WITH_RVI_VECTOR, vmx_hlt_with_rvi_guest_isr); 9599 9600 irq_enable(); 9601 asm volatile ("nop"); 9602 9603 vmcall(); 9604 } 9605 9606 static void vmx_hlt_with_rvi_test(void) 9607 { 9608 if (!cpu_has_apicv()) { 9609 report_skip(__func__); 9610 return; 9611 } 9612 9613 enable_vid(); 9614 9615 vmx_hlt_with_rvi_guest_isr_fired = false; 9616 test_set_guest(vmx_hlt_with_rvi_guest); 9617 9618 enter_guest(); 9619 skip_exit_vmcall(); 9620 9621 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 9622 vmcs_write(GUEST_INT_STATUS, HLT_WITH_RVI_VECTOR); 9623 enter_guest(); 9624 9625 report(vmx_hlt_with_rvi_guest_isr_fired, "Interrupt raised in guest"); 9626 } 9627 9628 static void set_irq_line_thread(void *data) 9629 { 9630 /* Wait until other CPU entered L2 */ 9631 while (vmx_get_test_stage() != 1) 9632 ; 9633 9634 /* Set irq-line 0xf to raise vector 0x78 for vCPU 0 */ 9635 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 9636 vmx_set_test_stage(2); 9637 } 9638 9639 static bool irq_78_handler_vmcall_before_eoi; 9640 static void irq_78_handler_guest(isr_regs_t *regs) 9641 { 9642 set_irq_line(0xf, 0); 9643 if (irq_78_handler_vmcall_before_eoi) 9644 vmcall(); 9645 eoi(); 9646 vmcall(); 9647 } 9648 9649 static void vmx_apic_passthrough_guest(void) 9650 { 9651 handle_irq(0x78, irq_78_handler_guest); 9652 irq_enable(); 9653 9654 /* If requested, wait for other CPU to trigger ioapic scan */ 9655 if (vmx_get_test_stage() < 1) { 9656 vmx_set_test_stage(1); 9657 while (vmx_get_test_stage() != 2) 9658 ; 9659 } 9660 9661 set_irq_line(0xf, 1); 9662 } 9663 9664 static void vmx_apic_passthrough(bool set_irq_line_from_thread) 9665 { 9666 if (set_irq_line_from_thread && (cpu_count() < 2)) { 9667 report_skip(__func__); 9668 return; 9669 } 9670 9671 /* Test device is required for generating IRQs */ 9672 if (!test_device_enabled()) { 9673 report_skip(__func__); 9674 return; 9675 } 9676 u64 cpu_ctrl_0 = CPU_SECONDARY; 9677 u64 cpu_ctrl_1 = 0; 9678 9679 disable_intercept_for_x2apic_msrs(); 9680 9681 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 9682 9683 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 9684 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 9685 9686 if (set_irq_line_from_thread) { 9687 irq_78_handler_vmcall_before_eoi = false; 9688 on_cpu_async(1, set_irq_line_thread, NULL); 9689 } else { 9690 irq_78_handler_vmcall_before_eoi = true; 9691 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 9692 vmx_set_test_stage(2); 9693 } 9694 test_set_guest(vmx_apic_passthrough_guest); 9695 9696 if (irq_78_handler_vmcall_before_eoi) { 9697 /* Before EOI remote_irr should still be set */ 9698 enter_guest(); 9699 skip_exit_vmcall(); 9700 TEST_ASSERT_EQ_MSG(1, (int)ioapic_read_redir(0xf).remote_irr, 9701 "IOAPIC pass-through: remote_irr=1 before EOI"); 9702 } 9703 9704 /* After EOI remote_irr should be cleared */ 9705 enter_guest(); 9706 skip_exit_vmcall(); 9707 TEST_ASSERT_EQ_MSG(0, (int)ioapic_read_redir(0xf).remote_irr, 9708 "IOAPIC pass-through: remote_irr=0 after EOI"); 9709 9710 /* Let L2 finish */ 9711 enter_guest(); 9712 report(1, __func__); 9713 } 9714 9715 static void vmx_apic_passthrough_test(void) 9716 { 9717 vmx_apic_passthrough(false); 9718 } 9719 9720 static void vmx_apic_passthrough_thread_test(void) 9721 { 9722 vmx_apic_passthrough(true); 9723 } 9724 9725 static void vmx_apic_passthrough_tpr_threshold_guest(void) 9726 { 9727 cli(); 9728 apic_set_tpr(0); 9729 } 9730 9731 static bool vmx_apic_passthrough_tpr_threshold_ipi_isr_fired; 9732 static void vmx_apic_passthrough_tpr_threshold_ipi_isr(isr_regs_t *regs) 9733 { 9734 vmx_apic_passthrough_tpr_threshold_ipi_isr_fired = true; 9735 eoi(); 9736 } 9737 9738 static void vmx_apic_passthrough_tpr_threshold_test(void) 9739 { 9740 int ipi_vector = 0xe1; 9741 9742 disable_intercept_for_x2apic_msrs(); 9743 vmcs_clear_bits(PIN_CONTROLS, PIN_EXTINT); 9744 9745 /* Raise L0 TPR-threshold by queueing vector in LAPIC IRR */ 9746 cli(); 9747 apic_set_tpr((ipi_vector >> 4) + 1); 9748 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | 9749 APIC_DM_FIXED | ipi_vector, 9750 0); 9751 9752 test_set_guest(vmx_apic_passthrough_tpr_threshold_guest); 9753 enter_guest(); 9754 9755 report(apic_get_tpr() == 0, "TPR was zero by guest"); 9756 9757 /* Clean pending self-IPI */ 9758 vmx_apic_passthrough_tpr_threshold_ipi_isr_fired = false; 9759 handle_irq(ipi_vector, vmx_apic_passthrough_tpr_threshold_ipi_isr); 9760 sti(); 9761 asm volatile ("nop"); 9762 report(vmx_apic_passthrough_tpr_threshold_ipi_isr_fired, "self-IPI fired"); 9763 9764 report(1, __func__); 9765 } 9766 9767 static u64 init_signal_test_exit_reason; 9768 static bool init_signal_test_thread_continued; 9769 9770 static void init_signal_test_thread(void *data) 9771 { 9772 struct vmcs *test_vmcs = data; 9773 9774 /* Enter VMX operation (i.e. exec VMXON) */ 9775 u64 *ap_vmxon_region = alloc_page(); 9776 enable_vmx(); 9777 init_vmx(ap_vmxon_region); 9778 _vmx_on(ap_vmxon_region); 9779 9780 /* Signal CPU have entered VMX operation */ 9781 vmx_set_test_stage(1); 9782 9783 /* Wait for BSP CPU to send INIT signal */ 9784 while (vmx_get_test_stage() != 2) 9785 ; 9786 9787 /* 9788 * Signal that we continue as usual as INIT signal 9789 * should be blocked while CPU is in VMX operation 9790 */ 9791 vmx_set_test_stage(3); 9792 9793 /* Wait for signal to enter VMX non-root mode */ 9794 while (vmx_get_test_stage() != 4) 9795 ; 9796 9797 /* Enter VMX non-root mode */ 9798 test_set_guest(v2_null_test_guest); 9799 make_vmcs_current(test_vmcs); 9800 enter_guest(); 9801 /* Save exit reason for BSP CPU to compare to expected result */ 9802 init_signal_test_exit_reason = vmcs_read(EXI_REASON); 9803 /* VMCLEAR test-vmcs so it could be loaded by BSP CPU */ 9804 vmcs_clear(test_vmcs); 9805 launched = false; 9806 /* Signal that CPU exited to VMX root mode */ 9807 vmx_set_test_stage(5); 9808 9809 /* Wait for BSP CPU to signal to exit VMX operation */ 9810 while (vmx_get_test_stage() != 6) 9811 ; 9812 9813 /* Exit VMX operation (i.e. exec VMXOFF) */ 9814 vmx_off(); 9815 9816 /* 9817 * Signal to BSP CPU that we continue as usual as INIT signal 9818 * should have been consumed by VMX_INIT exit from guest 9819 */ 9820 vmx_set_test_stage(7); 9821 9822 /* Wait for BSP CPU to signal to enter VMX operation */ 9823 while (vmx_get_test_stage() != 8) 9824 ; 9825 /* Enter VMX operation (i.e. exec VMXON) */ 9826 _vmx_on(ap_vmxon_region); 9827 /* Signal to BSP we are in VMX operation */ 9828 vmx_set_test_stage(9); 9829 9830 /* Wait for BSP CPU to send INIT signal */ 9831 while (vmx_get_test_stage() != 10) 9832 ; 9833 9834 /* Exit VMX operation (i.e. exec VMXOFF) */ 9835 vmx_off(); 9836 9837 /* 9838 * Exiting VMX operation should result in latched 9839 * INIT signal being processed. Therefore, we should 9840 * never reach the below code. Thus, signal to BSP 9841 * CPU if we have reached here so it is able to 9842 * report an issue if it happens. 9843 */ 9844 init_signal_test_thread_continued = true; 9845 } 9846 9847 #define INIT_SIGNAL_TEST_DELAY 100000000ULL 9848 9849 static void vmx_init_signal_test(void) 9850 { 9851 struct vmcs *test_vmcs; 9852 9853 if (cpu_count() < 2) { 9854 report_skip(__func__); 9855 return; 9856 } 9857 9858 /* VMCLEAR test-vmcs so it could be loaded by other CPU */ 9859 vmcs_save(&test_vmcs); 9860 vmcs_clear(test_vmcs); 9861 9862 vmx_set_test_stage(0); 9863 on_cpu_async(1, init_signal_test_thread, test_vmcs); 9864 9865 /* Wait for other CPU to enter VMX operation */ 9866 while (vmx_get_test_stage() != 1) 9867 ; 9868 9869 /* Send INIT signal to other CPU */ 9870 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_INIT | APIC_INT_ASSERT, 9871 id_map[1]); 9872 /* Signal other CPU we have sent INIT signal */ 9873 vmx_set_test_stage(2); 9874 9875 /* 9876 * Wait reasonable amount of time for INIT signal to 9877 * be received on other CPU and verify that other CPU 9878 * have proceed as usual to next test stage as INIT 9879 * signal should be blocked while other CPU in 9880 * VMX operation 9881 */ 9882 delay(INIT_SIGNAL_TEST_DELAY); 9883 report(vmx_get_test_stage() == 3, 9884 "INIT signal blocked when CPU in VMX operation"); 9885 /* No point to continue if we failed at this point */ 9886 if (vmx_get_test_stage() != 3) 9887 return; 9888 9889 /* Signal other CPU to enter VMX non-root mode */ 9890 init_signal_test_exit_reason = -1ull; 9891 vmx_set_test_stage(4); 9892 /* 9893 * Wait reasonable amont of time for other CPU 9894 * to exit to VMX root mode 9895 */ 9896 delay(INIT_SIGNAL_TEST_DELAY); 9897 if (vmx_get_test_stage() != 5) { 9898 report_fail("Pending INIT signal didn't result in VMX exit"); 9899 return; 9900 } 9901 report(init_signal_test_exit_reason == VMX_INIT, 9902 "INIT signal during VMX non-root mode result in exit-reason %s (%lu)", 9903 exit_reason_description(init_signal_test_exit_reason), 9904 init_signal_test_exit_reason); 9905 9906 /* Run guest to completion */ 9907 make_vmcs_current(test_vmcs); 9908 enter_guest(); 9909 9910 /* Signal other CPU to exit VMX operation */ 9911 init_signal_test_thread_continued = false; 9912 vmx_set_test_stage(6); 9913 9914 /* Wait reasonable amount of time for other CPU to exit VMX operation */ 9915 delay(INIT_SIGNAL_TEST_DELAY); 9916 report(vmx_get_test_stage() == 7, 9917 "INIT signal consumed on VMX_INIT exit"); 9918 /* No point to continue if we failed at this point */ 9919 if (vmx_get_test_stage() != 7) 9920 return; 9921 9922 /* Signal other CPU to enter VMX operation */ 9923 vmx_set_test_stage(8); 9924 /* Wait for other CPU to enter VMX operation */ 9925 while (vmx_get_test_stage() != 9) 9926 ; 9927 9928 /* Send INIT signal to other CPU */ 9929 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_INIT | APIC_INT_ASSERT, 9930 id_map[1]); 9931 /* Signal other CPU we have sent INIT signal */ 9932 vmx_set_test_stage(10); 9933 9934 /* 9935 * Wait reasonable amount of time for other CPU 9936 * to exit VMX operation and process INIT signal 9937 */ 9938 delay(INIT_SIGNAL_TEST_DELAY); 9939 report(!init_signal_test_thread_continued, 9940 "INIT signal processed after exit VMX operation"); 9941 9942 /* 9943 * TODO: Send SIPI to other CPU to sipi_entry (See x86/cstart64.S) 9944 * to re-init it to kvm-unit-tests standard environment. 9945 * Somehow (?) verify that SIPI was indeed received. 9946 */ 9947 } 9948 9949 #define SIPI_SIGNAL_TEST_DELAY 100000000ULL 9950 9951 static void vmx_sipi_test_guest(void) 9952 { 9953 if (apic_id() == 0) { 9954 /* wait AP enter guest with activity=WAIT_SIPI */ 9955 while (vmx_get_test_stage() != 1) 9956 ; 9957 delay(SIPI_SIGNAL_TEST_DELAY); 9958 9959 /* First SIPI signal */ 9960 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_STARTUP | APIC_INT_ASSERT, id_map[1]); 9961 report(1, "BSP(L2): Send first SIPI to cpu[%d]", id_map[1]); 9962 9963 /* wait AP enter guest */ 9964 while (vmx_get_test_stage() != 2) 9965 ; 9966 delay(SIPI_SIGNAL_TEST_DELAY); 9967 9968 /* Second SIPI signal should be ignored since AP is not in WAIT_SIPI state */ 9969 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_STARTUP | APIC_INT_ASSERT, id_map[1]); 9970 report(1, "BSP(L2): Send second SIPI to cpu[%d]", id_map[1]); 9971 9972 /* Delay a while to check whether second SIPI would cause VMExit */ 9973 delay(SIPI_SIGNAL_TEST_DELAY); 9974 9975 /* Test is done, notify AP to exit test */ 9976 vmx_set_test_stage(3); 9977 9978 /* wait AP exit non-root mode */ 9979 while (vmx_get_test_stage() != 5) 9980 ; 9981 } else { 9982 /* wait BSP notify test is done */ 9983 while (vmx_get_test_stage() != 3) 9984 ; 9985 9986 /* AP exit guest */ 9987 vmx_set_test_stage(4); 9988 } 9989 } 9990 9991 static void sipi_test_ap_thread(void *data) 9992 { 9993 struct vmcs *ap_vmcs; 9994 u64 *ap_vmxon_region; 9995 void *ap_stack, *ap_syscall_stack; 9996 u64 cpu_ctrl_0 = CPU_SECONDARY; 9997 u64 cpu_ctrl_1 = 0; 9998 9999 /* Enter VMX operation (i.e. exec VMXON) */ 10000 ap_vmxon_region = alloc_page(); 10001 enable_vmx(); 10002 init_vmx(ap_vmxon_region); 10003 _vmx_on(ap_vmxon_region); 10004 init_vmcs(&ap_vmcs); 10005 make_vmcs_current(ap_vmcs); 10006 10007 /* Set stack for AP */ 10008 ap_stack = alloc_page(); 10009 ap_syscall_stack = alloc_page(); 10010 vmcs_write(GUEST_RSP, (u64)(ap_stack + PAGE_SIZE - 1)); 10011 vmcs_write(GUEST_SYSENTER_ESP, (u64)(ap_syscall_stack + PAGE_SIZE - 1)); 10012 10013 /* passthrough lapic to L2 */ 10014 disable_intercept_for_x2apic_msrs(); 10015 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 10016 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 10017 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 10018 10019 /* Set guest activity state to wait-for-SIPI state */ 10020 vmcs_write(GUEST_ACTV_STATE, ACTV_WAIT_SIPI); 10021 10022 vmx_set_test_stage(1); 10023 10024 /* AP enter guest */ 10025 enter_guest(); 10026 10027 if (vmcs_read(EXI_REASON) == VMX_SIPI) { 10028 report(1, "AP: Handle SIPI VMExit"); 10029 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 10030 vmx_set_test_stage(2); 10031 } else { 10032 report_fail("AP: Unexpected VMExit, reason=%ld", vmcs_read(EXI_REASON)); 10033 vmx_off(); 10034 return; 10035 } 10036 10037 /* AP enter guest */ 10038 enter_guest(); 10039 10040 report(vmcs_read(EXI_REASON) != VMX_SIPI, 10041 "AP: should no SIPI VMExit since activity is not in WAIT_SIPI state"); 10042 10043 /* notify BSP that AP is already exit from non-root mode */ 10044 vmx_set_test_stage(5); 10045 10046 /* Leave VMX operation */ 10047 vmx_off(); 10048 } 10049 10050 static void vmx_sipi_signal_test(void) 10051 { 10052 if (!(rdmsr(MSR_IA32_VMX_MISC) & MSR_IA32_VMX_MISC_ACTIVITY_WAIT_SIPI)) { 10053 printf("\tACTIVITY_WAIT_SIPI state is not supported.\n"); 10054 return; 10055 } 10056 10057 if (cpu_count() < 2) { 10058 report_skip(__func__); 10059 return; 10060 } 10061 10062 u64 cpu_ctrl_0 = CPU_SECONDARY; 10063 u64 cpu_ctrl_1 = 0; 10064 10065 /* passthrough lapic to L2 */ 10066 disable_intercept_for_x2apic_msrs(); 10067 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 10068 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 10069 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 10070 10071 test_set_guest(vmx_sipi_test_guest); 10072 10073 /* update CR3 on AP */ 10074 on_cpu(1, update_cr3, (void *)read_cr3()); 10075 10076 /* start AP */ 10077 on_cpu_async(1, sipi_test_ap_thread, NULL); 10078 10079 vmx_set_test_stage(0); 10080 10081 /* BSP enter guest */ 10082 enter_guest(); 10083 } 10084 10085 10086 enum vmcs_access { 10087 ACCESS_VMREAD, 10088 ACCESS_VMWRITE, 10089 ACCESS_NONE, 10090 }; 10091 10092 struct vmcs_shadow_test_common { 10093 enum vmcs_access op; 10094 enum Reason reason; 10095 u64 field; 10096 u64 value; 10097 u64 flags; 10098 u64 time; 10099 } l1_l2_common; 10100 10101 static inline u64 vmread_flags(u64 field, u64 *val) 10102 { 10103 u64 flags; 10104 10105 asm volatile ("vmread %2, %1; pushf; pop %0" 10106 : "=r" (flags), "=rm" (*val) : "r" (field) : "cc"); 10107 return flags & X86_EFLAGS_ALU; 10108 } 10109 10110 static inline u64 vmwrite_flags(u64 field, u64 val) 10111 { 10112 u64 flags; 10113 10114 asm volatile ("vmwrite %1, %2; pushf; pop %0" 10115 : "=r"(flags) : "rm" (val), "r" (field) : "cc"); 10116 return flags & X86_EFLAGS_ALU; 10117 } 10118 10119 static void vmx_vmcs_shadow_test_guest(void) 10120 { 10121 struct vmcs_shadow_test_common *c = &l1_l2_common; 10122 u64 start; 10123 10124 while (c->op != ACCESS_NONE) { 10125 start = rdtsc(); 10126 switch (c->op) { 10127 default: 10128 c->flags = -1ull; 10129 break; 10130 case ACCESS_VMREAD: 10131 c->flags = vmread_flags(c->field, &c->value); 10132 break; 10133 case ACCESS_VMWRITE: 10134 c->flags = vmwrite_flags(c->field, 0); 10135 break; 10136 } 10137 c->time = rdtsc() - start; 10138 vmcall(); 10139 } 10140 } 10141 10142 static u64 vmread_from_shadow(u64 field) 10143 { 10144 struct vmcs *primary; 10145 struct vmcs *shadow; 10146 u64 value; 10147 10148 TEST_ASSERT(!vmcs_save(&primary)); 10149 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 10150 TEST_ASSERT(!make_vmcs_current(shadow)); 10151 value = vmcs_read(field); 10152 TEST_ASSERT(!make_vmcs_current(primary)); 10153 return value; 10154 } 10155 10156 static u64 vmwrite_to_shadow(u64 field, u64 value) 10157 { 10158 struct vmcs *primary; 10159 struct vmcs *shadow; 10160 10161 TEST_ASSERT(!vmcs_save(&primary)); 10162 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 10163 TEST_ASSERT(!make_vmcs_current(shadow)); 10164 vmcs_write(field, value); 10165 value = vmcs_read(field); 10166 TEST_ASSERT(!make_vmcs_current(primary)); 10167 return value; 10168 } 10169 10170 static void vmcs_shadow_test_access(u8 *bitmap[2], enum vmcs_access access) 10171 { 10172 struct vmcs_shadow_test_common *c = &l1_l2_common; 10173 10174 c->op = access; 10175 vmcs_write(VMX_INST_ERROR, 0); 10176 enter_guest(); 10177 c->reason = vmcs_read(EXI_REASON) & 0xffff; 10178 if (c->reason != VMX_VMCALL) { 10179 skip_exit_insn(); 10180 enter_guest(); 10181 } 10182 skip_exit_vmcall(); 10183 } 10184 10185 static void vmcs_shadow_test_field(u8 *bitmap[2], u64 field) 10186 { 10187 struct vmcs_shadow_test_common *c = &l1_l2_common; 10188 struct vmcs *shadow; 10189 u64 value; 10190 uintptr_t flags[2]; 10191 bool good_shadow; 10192 u32 vmx_inst_error; 10193 10194 report_prefix_pushf("field %lx", field); 10195 c->field = field; 10196 10197 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 10198 if (shadow != (struct vmcs *)-1ull) { 10199 flags[ACCESS_VMREAD] = vmread_flags(field, &value); 10200 flags[ACCESS_VMWRITE] = vmwrite_flags(field, value); 10201 good_shadow = !flags[ACCESS_VMREAD] && !flags[ACCESS_VMWRITE]; 10202 } else { 10203 /* 10204 * When VMCS link pointer is -1ull, VMWRITE/VMREAD on 10205 * shadowed-fields should fail with setting RFLAGS.CF. 10206 */ 10207 flags[ACCESS_VMREAD] = X86_EFLAGS_CF; 10208 flags[ACCESS_VMWRITE] = X86_EFLAGS_CF; 10209 good_shadow = false; 10210 } 10211 10212 /* Intercept both VMREAD and VMWRITE. */ 10213 report_prefix_push("no VMREAD/VMWRITE permission"); 10214 /* VMWRITE/VMREAD done on reserved-bit should always intercept */ 10215 if (!(field >> VMCS_FIELD_RESERVED_SHIFT)) { 10216 set_bit(field, bitmap[ACCESS_VMREAD]); 10217 set_bit(field, bitmap[ACCESS_VMWRITE]); 10218 } 10219 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10220 report(c->reason == VMX_VMWRITE, "not shadowed for VMWRITE"); 10221 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10222 report(c->reason == VMX_VMREAD, "not shadowed for VMREAD"); 10223 report_prefix_pop(); 10224 10225 if (field >> VMCS_FIELD_RESERVED_SHIFT) 10226 goto out; 10227 10228 /* Permit shadowed VMREAD. */ 10229 report_prefix_push("VMREAD permission only"); 10230 clear_bit(field, bitmap[ACCESS_VMREAD]); 10231 set_bit(field, bitmap[ACCESS_VMWRITE]); 10232 if (good_shadow) 10233 value = vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 10234 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10235 report(c->reason == VMX_VMWRITE, "not shadowed for VMWRITE"); 10236 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10237 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10238 report(c->reason == VMX_VMCALL, "shadowed for VMREAD (in %ld cycles)", 10239 c->time); 10240 report(c->flags == flags[ACCESS_VMREAD], 10241 "ALU flags after VMREAD (%lx) are as expected (%lx)", 10242 c->flags, flags[ACCESS_VMREAD]); 10243 if (good_shadow) 10244 report(c->value == value, 10245 "value read from shadow (%lx) is as expected (%lx)", 10246 c->value, value); 10247 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 10248 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10249 "VMX_INST_ERROR (%d) is as expected (%d)", 10250 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10251 report_prefix_pop(); 10252 10253 /* Permit shadowed VMWRITE. */ 10254 report_prefix_push("VMWRITE permission only"); 10255 set_bit(field, bitmap[ACCESS_VMREAD]); 10256 clear_bit(field, bitmap[ACCESS_VMWRITE]); 10257 if (good_shadow) 10258 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 10259 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10260 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10261 report(c->reason == VMX_VMCALL, 10262 "shadowed for VMWRITE (in %ld cycles)", 10263 c->time); 10264 report(c->flags == flags[ACCESS_VMREAD], 10265 "ALU flags after VMWRITE (%lx) are as expected (%lx)", 10266 c->flags, flags[ACCESS_VMREAD]); 10267 if (good_shadow) { 10268 value = vmread_from_shadow(field); 10269 report(value == 0, 10270 "shadow VMCS value (%lx) is as expected (%lx)", value, 10271 0ul); 10272 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 10273 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10274 "VMX_INST_ERROR (%d) is as expected (%d)", 10275 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10276 } 10277 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10278 report(c->reason == VMX_VMREAD, "not shadowed for VMREAD"); 10279 report_prefix_pop(); 10280 10281 /* Permit shadowed VMREAD and VMWRITE. */ 10282 report_prefix_push("VMREAD and VMWRITE permission"); 10283 clear_bit(field, bitmap[ACCESS_VMREAD]); 10284 clear_bit(field, bitmap[ACCESS_VMWRITE]); 10285 if (good_shadow) 10286 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 10287 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10288 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10289 report(c->reason == VMX_VMCALL, 10290 "shadowed for VMWRITE (in %ld cycles)", 10291 c->time); 10292 report(c->flags == flags[ACCESS_VMREAD], 10293 "ALU flags after VMWRITE (%lx) are as expected (%lx)", 10294 c->flags, flags[ACCESS_VMREAD]); 10295 if (good_shadow) { 10296 value = vmread_from_shadow(field); 10297 report(value == 0, 10298 "shadow VMCS value (%lx) is as expected (%lx)", value, 10299 0ul); 10300 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 10301 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10302 "VMX_INST_ERROR (%d) is as expected (%d)", 10303 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10304 } 10305 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10306 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10307 report(c->reason == VMX_VMCALL, "shadowed for VMREAD (in %ld cycles)", 10308 c->time); 10309 report(c->flags == flags[ACCESS_VMREAD], 10310 "ALU flags after VMREAD (%lx) are as expected (%lx)", 10311 c->flags, flags[ACCESS_VMREAD]); 10312 if (good_shadow) 10313 report(c->value == 0, 10314 "value read from shadow (%lx) is as expected (%lx)", 10315 c->value, 0ul); 10316 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 10317 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10318 "VMX_INST_ERROR (%d) is as expected (%d)", 10319 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10320 report_prefix_pop(); 10321 10322 out: 10323 report_prefix_pop(); 10324 } 10325 10326 static void vmx_vmcs_shadow_test_body(u8 *bitmap[2]) 10327 { 10328 unsigned base; 10329 unsigned index; 10330 unsigned bit; 10331 unsigned highest_index = rdmsr(MSR_IA32_VMX_VMCS_ENUM); 10332 10333 /* Run test on all possible valid VMCS fields */ 10334 for (base = 0; 10335 base < (1 << VMCS_FIELD_RESERVED_SHIFT); 10336 base += (1 << VMCS_FIELD_TYPE_SHIFT)) 10337 for (index = 0; index <= highest_index; index++) 10338 vmcs_shadow_test_field(bitmap, base + index); 10339 10340 /* 10341 * Run tests on some invalid VMCS fields 10342 * (Have reserved bit set). 10343 */ 10344 for (bit = VMCS_FIELD_RESERVED_SHIFT; bit < VMCS_FIELD_BIT_SIZE; bit++) 10345 vmcs_shadow_test_field(bitmap, (1ull << bit)); 10346 } 10347 10348 static void vmx_vmcs_shadow_test(void) 10349 { 10350 u8 *bitmap[2]; 10351 struct vmcs *shadow; 10352 10353 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 10354 printf("\t'Activate secondary controls' not supported.\n"); 10355 return; 10356 } 10357 10358 if (!(ctrl_cpu_rev[1].clr & CPU_SHADOW_VMCS)) { 10359 printf("\t'VMCS shadowing' not supported.\n"); 10360 return; 10361 } 10362 10363 if (!(rdmsr(MSR_IA32_VMX_MISC) & 10364 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS)) { 10365 printf("\tVMWRITE can't modify VM-exit information fields.\n"); 10366 return; 10367 } 10368 10369 test_set_guest(vmx_vmcs_shadow_test_guest); 10370 10371 bitmap[ACCESS_VMREAD] = alloc_page(); 10372 bitmap[ACCESS_VMWRITE] = alloc_page(); 10373 10374 vmcs_write(VMREAD_BITMAP, virt_to_phys(bitmap[ACCESS_VMREAD])); 10375 vmcs_write(VMWRITE_BITMAP, virt_to_phys(bitmap[ACCESS_VMWRITE])); 10376 10377 shadow = alloc_page(); 10378 shadow->hdr.revision_id = basic.revision; 10379 shadow->hdr.shadow_vmcs = 1; 10380 TEST_ASSERT(!vmcs_clear(shadow)); 10381 10382 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_RDTSC); 10383 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY); 10384 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_SHADOW_VMCS); 10385 10386 vmcs_write(VMCS_LINK_PTR, virt_to_phys(shadow)); 10387 report_prefix_push("valid link pointer"); 10388 vmx_vmcs_shadow_test_body(bitmap); 10389 report_prefix_pop(); 10390 10391 vmcs_write(VMCS_LINK_PTR, -1ull); 10392 report_prefix_push("invalid link pointer"); 10393 vmx_vmcs_shadow_test_body(bitmap); 10394 report_prefix_pop(); 10395 10396 l1_l2_common.op = ACCESS_NONE; 10397 enter_guest(); 10398 } 10399 10400 /* 10401 * This test monitors the difference between a guest RDTSC instruction 10402 * and the IA32_TIME_STAMP_COUNTER MSR value stored in the VMCS12 10403 * VM-exit MSR-store list when taking a VM-exit on the instruction 10404 * following RDTSC. 10405 */ 10406 #define RDTSC_DIFF_ITERS 100000 10407 #define RDTSC_DIFF_FAILS 100 10408 #define HOST_CAPTURED_GUEST_TSC_DIFF_THRESHOLD 750 10409 10410 /* 10411 * Set 'use TSC offsetting' and set the guest offset to the 10412 * inverse of the host's current TSC value, so that the guest starts running 10413 * with an effective TSC value of 0. 10414 */ 10415 static void reset_guest_tsc_to_zero(void) 10416 { 10417 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_USE_TSC_OFFSET); 10418 vmcs_write(TSC_OFFSET, -rdtsc()); 10419 } 10420 10421 static void rdtsc_vmexit_diff_test_guest(void) 10422 { 10423 int i; 10424 10425 for (i = 0; i < RDTSC_DIFF_ITERS; i++) 10426 /* Ensure rdtsc is the last instruction before the vmcall. */ 10427 asm volatile("rdtsc; vmcall" : : : "eax", "edx"); 10428 } 10429 10430 /* 10431 * This function only considers the "use TSC offsetting" VM-execution 10432 * control. It does not handle "use TSC scaling" (because the latter 10433 * isn't available to the host today.) 10434 */ 10435 static unsigned long long host_time_to_guest_time(unsigned long long t) 10436 { 10437 TEST_ASSERT(!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 10438 !(vmcs_read(CPU_EXEC_CTRL1) & CPU_USE_TSC_SCALING)); 10439 10440 if (vmcs_read(CPU_EXEC_CTRL0) & CPU_USE_TSC_OFFSET) 10441 t += vmcs_read(TSC_OFFSET); 10442 10443 return t; 10444 } 10445 10446 static unsigned long long rdtsc_vmexit_diff_test_iteration(void) 10447 { 10448 unsigned long long guest_tsc, host_to_guest_tsc; 10449 10450 enter_guest(); 10451 skip_exit_vmcall(); 10452 guest_tsc = (u32) regs.rax + (regs.rdx << 32); 10453 host_to_guest_tsc = host_time_to_guest_time(exit_msr_store[0].value); 10454 10455 return host_to_guest_tsc - guest_tsc; 10456 } 10457 10458 static void rdtsc_vmexit_diff_test(void) 10459 { 10460 unsigned long long delta; 10461 int fail = 0; 10462 int i; 10463 10464 if (!(ctrl_cpu_rev[0].clr & CPU_USE_TSC_OFFSET)) 10465 test_skip("CPU doesn't support the 'use TSC offsetting' processor-based VM-execution control.\n"); 10466 10467 test_set_guest(rdtsc_vmexit_diff_test_guest); 10468 10469 reset_guest_tsc_to_zero(); 10470 10471 /* 10472 * Set up the VMCS12 VM-exit MSR-store list to store just one 10473 * MSR: IA32_TIME_STAMP_COUNTER. Note that the value stored is 10474 * in the host time domain (i.e., it is not adjusted according 10475 * to the TSC multiplier and TSC offset fields in the VMCS12, 10476 * as a guest RDTSC would be.) 10477 */ 10478 exit_msr_store = alloc_page(); 10479 exit_msr_store[0].index = MSR_IA32_TSC; 10480 vmcs_write(EXI_MSR_ST_CNT, 1); 10481 vmcs_write(EXIT_MSR_ST_ADDR, virt_to_phys(exit_msr_store)); 10482 10483 for (i = 0; i < RDTSC_DIFF_ITERS && fail < RDTSC_DIFF_FAILS; i++) { 10484 delta = rdtsc_vmexit_diff_test_iteration(); 10485 if (delta >= HOST_CAPTURED_GUEST_TSC_DIFF_THRESHOLD) 10486 fail++; 10487 } 10488 10489 enter_guest(); 10490 10491 report(fail < RDTSC_DIFF_FAILS, 10492 "RDTSC to VM-exit delta too high in %d of %d iterations, last = %llu", 10493 fail, i, delta); 10494 } 10495 10496 static int invalid_msr_init(struct vmcs *vmcs) 10497 { 10498 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 10499 printf("\tPreemption timer is not supported\n"); 10500 return VMX_TEST_EXIT; 10501 } 10502 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 10503 preempt_val = 10000000; 10504 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 10505 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 10506 10507 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 10508 printf("\tSave preemption value is not supported\n"); 10509 10510 vmcs_write(ENT_MSR_LD_CNT, 1); 10511 vmcs_write(ENTER_MSR_LD_ADDR, (u64)0x13370000); 10512 10513 return VMX_TEST_START; 10514 } 10515 10516 10517 static void invalid_msr_main(void) 10518 { 10519 report_fail("Invalid MSR load"); 10520 } 10521 10522 static int invalid_msr_exit_handler(union exit_reason exit_reason) 10523 { 10524 report_fail("Invalid MSR load"); 10525 print_vmexit_info(exit_reason); 10526 return VMX_TEST_EXIT; 10527 } 10528 10529 static int invalid_msr_entry_failure(struct vmentry_result *result) 10530 { 10531 report(result->exit_reason.failed_vmentry && 10532 result->exit_reason.basic == VMX_FAIL_MSR, "Invalid MSR load"); 10533 return VMX_TEST_VMEXIT; 10534 } 10535 10536 /* 10537 * The max number of MSRs in an atomic switch MSR list is: 10538 * (111B + 1) * 512 = 4096 10539 * 10540 * Each list entry consumes: 10541 * 4-byte MSR index + 4 bytes reserved + 8-byte data = 16 bytes 10542 * 10543 * Allocate 128 kB to cover max_msr_list_size (i.e., 64 kB) and then some. 10544 */ 10545 static const u32 msr_list_page_order = 5; 10546 10547 static void atomic_switch_msr_limit_test_guest(void) 10548 { 10549 vmcall(); 10550 } 10551 10552 static void populate_msr_list(struct vmx_msr_entry *msr_list, 10553 size_t byte_capacity, int count) 10554 { 10555 int i; 10556 10557 for (i = 0; i < count; i++) { 10558 msr_list[i].index = MSR_IA32_TSC; 10559 msr_list[i].reserved = 0; 10560 msr_list[i].value = 0x1234567890abcdef; 10561 } 10562 10563 memset(msr_list + count, 0xff, 10564 byte_capacity - count * sizeof(*msr_list)); 10565 } 10566 10567 static int max_msr_list_size(void) 10568 { 10569 u32 vmx_misc = rdmsr(MSR_IA32_VMX_MISC); 10570 u32 factor = ((vmx_misc & GENMASK(27, 25)) >> 25) + 1; 10571 10572 return factor * 512; 10573 } 10574 10575 static void atomic_switch_msrs_test(int count) 10576 { 10577 struct vmx_msr_entry *vm_enter_load; 10578 struct vmx_msr_entry *vm_exit_load; 10579 struct vmx_msr_entry *vm_exit_store; 10580 int max_allowed = max_msr_list_size(); 10581 int byte_capacity = 1ul << (msr_list_page_order + PAGE_SHIFT); 10582 /* Exceeding the max MSR list size at exit trigers KVM to abort. */ 10583 int exit_count = count > max_allowed ? max_allowed : count; 10584 int cleanup_count = count > max_allowed ? 2 : 1; 10585 int i; 10586 10587 /* 10588 * Check for the IA32_TSC MSR, 10589 * available with the "TSC flag" and used to populate the MSR lists. 10590 */ 10591 if (!(cpuid(1).d & (1 << 4))) { 10592 report_skip(__func__); 10593 return; 10594 } 10595 10596 /* Set L2 guest. */ 10597 test_set_guest(atomic_switch_msr_limit_test_guest); 10598 10599 /* Setup atomic MSR switch lists. */ 10600 vm_enter_load = alloc_pages(msr_list_page_order); 10601 vm_exit_load = alloc_pages(msr_list_page_order); 10602 vm_exit_store = alloc_pages(msr_list_page_order); 10603 10604 vmcs_write(ENTER_MSR_LD_ADDR, (u64)vm_enter_load); 10605 vmcs_write(EXIT_MSR_LD_ADDR, (u64)vm_exit_load); 10606 vmcs_write(EXIT_MSR_ST_ADDR, (u64)vm_exit_store); 10607 10608 /* 10609 * VM-Enter should succeed up to the max number of MSRs per list, and 10610 * should not consume junk beyond the last entry. 10611 */ 10612 populate_msr_list(vm_enter_load, byte_capacity, count); 10613 populate_msr_list(vm_exit_load, byte_capacity, exit_count); 10614 populate_msr_list(vm_exit_store, byte_capacity, exit_count); 10615 10616 vmcs_write(ENT_MSR_LD_CNT, count); 10617 vmcs_write(EXI_MSR_LD_CNT, exit_count); 10618 vmcs_write(EXI_MSR_ST_CNT, exit_count); 10619 10620 if (count <= max_allowed) { 10621 enter_guest(); 10622 assert_exit_reason(VMX_VMCALL); 10623 skip_exit_vmcall(); 10624 } else { 10625 u32 exit_qual; 10626 10627 test_guest_state("Invalid MSR Load Count", true, count, 10628 "ENT_MSR_LD_CNT"); 10629 10630 exit_qual = vmcs_read(EXI_QUALIFICATION); 10631 report(exit_qual == max_allowed + 1, "exit_qual, %u, is %u.", 10632 exit_qual, max_allowed + 1); 10633 } 10634 10635 /* Cleanup. */ 10636 vmcs_write(ENT_MSR_LD_CNT, 0); 10637 vmcs_write(EXI_MSR_LD_CNT, 0); 10638 vmcs_write(EXI_MSR_ST_CNT, 0); 10639 for (i = 0; i < cleanup_count; i++) { 10640 enter_guest(); 10641 skip_exit_vmcall(); 10642 } 10643 free_pages_by_order(vm_enter_load, msr_list_page_order); 10644 free_pages_by_order(vm_exit_load, msr_list_page_order); 10645 free_pages_by_order(vm_exit_store, msr_list_page_order); 10646 } 10647 10648 static void atomic_switch_max_msrs_test(void) 10649 { 10650 atomic_switch_msrs_test(max_msr_list_size()); 10651 } 10652 10653 static void atomic_switch_overflow_msrs_test(void) 10654 { 10655 if (test_device_enabled()) 10656 atomic_switch_msrs_test(max_msr_list_size() + 1); 10657 else 10658 test_skip("Test is only supported on KVM"); 10659 } 10660 10661 #define TEST(name) { #name, .v2 = name } 10662 10663 /* name/init/guest_main/exit_handler/syscall_handler/guest_regs */ 10664 struct vmx_test vmx_tests[] = { 10665 { "null", NULL, basic_guest_main, basic_exit_handler, NULL, {0} }, 10666 { "vmenter", NULL, vmenter_main, vmenter_exit_handler, NULL, {0} }, 10667 { "preemption timer", preemption_timer_init, preemption_timer_main, 10668 preemption_timer_exit_handler, NULL, {0} }, 10669 { "control field PAT", test_ctrl_pat_init, test_ctrl_pat_main, 10670 test_ctrl_pat_exit_handler, NULL, {0} }, 10671 { "control field EFER", test_ctrl_efer_init, test_ctrl_efer_main, 10672 test_ctrl_efer_exit_handler, NULL, {0} }, 10673 { "CR shadowing", NULL, cr_shadowing_main, 10674 cr_shadowing_exit_handler, NULL, {0} }, 10675 { "I/O bitmap", iobmp_init, iobmp_main, iobmp_exit_handler, 10676 NULL, {0} }, 10677 { "instruction intercept", insn_intercept_init, insn_intercept_main, 10678 insn_intercept_exit_handler, NULL, {0} }, 10679 { "EPT A/D disabled", ept_init, ept_main, ept_exit_handler, NULL, {0} }, 10680 { "EPT A/D enabled", eptad_init, eptad_main, eptad_exit_handler, NULL, {0} }, 10681 { "PML", pml_init, pml_main, pml_exit_handler, NULL, {0} }, 10682 { "VPID", vpid_init, vpid_main, vpid_exit_handler, NULL, {0} }, 10683 { "interrupt", interrupt_init, interrupt_main, 10684 interrupt_exit_handler, NULL, {0} }, 10685 { "nmi_hlt", nmi_hlt_init, nmi_hlt_main, 10686 nmi_hlt_exit_handler, NULL, {0} }, 10687 { "debug controls", dbgctls_init, dbgctls_main, dbgctls_exit_handler, 10688 NULL, {0} }, 10689 { "MSR switch", msr_switch_init, msr_switch_main, 10690 msr_switch_exit_handler, NULL, {0}, msr_switch_entry_failure }, 10691 { "vmmcall", vmmcall_init, vmmcall_main, vmmcall_exit_handler, NULL, {0} }, 10692 { "disable RDTSCP", disable_rdtscp_init, disable_rdtscp_main, 10693 disable_rdtscp_exit_handler, NULL, {0} }, 10694 { "int3", int3_init, int3_guest_main, int3_exit_handler, NULL, {0} }, 10695 { "into", into_init, into_guest_main, into_exit_handler, NULL, {0} }, 10696 { "exit_monitor_from_l2_test", NULL, exit_monitor_from_l2_main, 10697 exit_monitor_from_l2_handler, NULL, {0} }, 10698 { "invalid_msr", invalid_msr_init, invalid_msr_main, 10699 invalid_msr_exit_handler, NULL, {0}, invalid_msr_entry_failure}, 10700 /* Basic V2 tests. */ 10701 TEST(v2_null_test), 10702 TEST(v2_multiple_entries_test), 10703 TEST(fixture_test_case1), 10704 TEST(fixture_test_case2), 10705 /* Opcode tests. */ 10706 TEST(invvpid_test_v2), 10707 /* VM-entry tests */ 10708 TEST(vmx_controls_test), 10709 TEST(vmx_host_state_area_test), 10710 TEST(vmx_guest_state_area_test), 10711 TEST(vmentry_movss_shadow_test), 10712 TEST(vmentry_unrestricted_guest_test), 10713 /* APICv tests */ 10714 TEST(vmx_eoi_bitmap_ioapic_scan_test), 10715 TEST(vmx_hlt_with_rvi_test), 10716 TEST(apic_reg_virt_test), 10717 TEST(virt_x2apic_mode_test), 10718 /* APIC pass-through tests */ 10719 TEST(vmx_apic_passthrough_test), 10720 TEST(vmx_apic_passthrough_thread_test), 10721 TEST(vmx_apic_passthrough_tpr_threshold_test), 10722 TEST(vmx_init_signal_test), 10723 TEST(vmx_sipi_signal_test), 10724 /* VMCS Shadowing tests */ 10725 TEST(vmx_vmcs_shadow_test), 10726 /* Regression tests */ 10727 TEST(vmx_cr_load_test), 10728 TEST(vmx_cr4_osxsave_test), 10729 TEST(vmx_nm_test), 10730 TEST(vmx_db_test), 10731 TEST(vmx_nmi_window_test), 10732 TEST(vmx_intr_window_test), 10733 TEST(vmx_pending_event_test), 10734 TEST(vmx_pending_event_hlt_test), 10735 TEST(vmx_store_tsc_test), 10736 TEST(vmx_preemption_timer_zero_test), 10737 TEST(vmx_preemption_timer_tf_test), 10738 TEST(vmx_preemption_timer_expiry_test), 10739 /* EPT access tests. */ 10740 TEST(ept_access_test_not_present), 10741 TEST(ept_access_test_read_only), 10742 TEST(ept_access_test_write_only), 10743 TEST(ept_access_test_read_write), 10744 TEST(ept_access_test_execute_only), 10745 TEST(ept_access_test_read_execute), 10746 TEST(ept_access_test_write_execute), 10747 TEST(ept_access_test_read_write_execute), 10748 TEST(ept_access_test_reserved_bits), 10749 TEST(ept_access_test_ignored_bits), 10750 TEST(ept_access_test_paddr_not_present_ad_disabled), 10751 TEST(ept_access_test_paddr_not_present_ad_enabled), 10752 TEST(ept_access_test_paddr_read_only_ad_disabled), 10753 TEST(ept_access_test_paddr_read_only_ad_enabled), 10754 TEST(ept_access_test_paddr_read_write), 10755 TEST(ept_access_test_paddr_read_write_execute), 10756 TEST(ept_access_test_paddr_read_execute_ad_disabled), 10757 TEST(ept_access_test_paddr_read_execute_ad_enabled), 10758 TEST(ept_access_test_paddr_not_present_page_fault), 10759 TEST(ept_access_test_force_2m_page), 10760 /* Atomic MSR switch tests. */ 10761 TEST(atomic_switch_max_msrs_test), 10762 TEST(atomic_switch_overflow_msrs_test), 10763 TEST(rdtsc_vmexit_diff_test), 10764 TEST(vmx_mtf_test), 10765 TEST(vmx_mtf_pdpte_test), 10766 { NULL, NULL, NULL, NULL, NULL, {0} }, 10767 }; 10768