1 /* 2 * All test cases of nested virtualization should be in this file 3 * 4 * Author : Arthur Chunqi Li <yzt356@gmail.com> 5 */ 6 7 #include <asm/debugreg.h> 8 9 #include "vmx.h" 10 #include "msr.h" 11 #include "processor.h" 12 #include "vm.h" 13 #include "pci.h" 14 #include "fwcfg.h" 15 #include "isr.h" 16 #include "desc.h" 17 #include "apic.h" 18 #include "types.h" 19 #include "vmalloc.h" 20 #include "alloc_page.h" 21 #include "smp.h" 22 #include "delay.h" 23 24 #define NONCANONICAL 0xaaaaaaaaaaaaaaaaull 25 26 #define VPID_CAP_INVVPID_TYPES_SHIFT 40 27 28 u64 ia32_pat; 29 u64 ia32_efer; 30 void *io_bitmap_a, *io_bitmap_b; 31 u16 ioport; 32 33 unsigned long *pml4; 34 u64 eptp; 35 void *data_page1, *data_page2; 36 37 phys_addr_t pci_physaddr; 38 39 void *pml_log; 40 #define PML_INDEX 512 41 42 static inline unsigned ffs(unsigned x) 43 { 44 int pos = -1; 45 46 __asm__ __volatile__("bsf %1, %%eax; cmovnz %%eax, %0" 47 : "+r"(pos) : "rm"(x) : "eax"); 48 return pos + 1; 49 } 50 51 static inline void vmcall(void) 52 { 53 asm volatile("vmcall"); 54 } 55 56 static void basic_guest_main(void) 57 { 58 report(1, "Basic VMX test"); 59 } 60 61 static int basic_exit_handler(union exit_reason exit_reason) 62 { 63 report(0, "Basic VMX test"); 64 print_vmexit_info(exit_reason); 65 return VMX_TEST_EXIT; 66 } 67 68 static void vmenter_main(void) 69 { 70 u64 rax; 71 u64 rsp, resume_rsp; 72 73 report(1, "test vmlaunch"); 74 75 asm volatile( 76 "mov %%rsp, %0\n\t" 77 "mov %3, %%rax\n\t" 78 "vmcall\n\t" 79 "mov %%rax, %1\n\t" 80 "mov %%rsp, %2\n\t" 81 : "=r"(rsp), "=r"(rax), "=r"(resume_rsp) 82 : "g"(0xABCD)); 83 report((rax == 0xFFFF) && (rsp == resume_rsp), "test vmresume"); 84 } 85 86 static int vmenter_exit_handler(union exit_reason exit_reason) 87 { 88 u64 guest_rip = vmcs_read(GUEST_RIP); 89 90 switch (exit_reason.basic) { 91 case VMX_VMCALL: 92 if (regs.rax != 0xABCD) { 93 report(0, "test vmresume"); 94 return VMX_TEST_VMEXIT; 95 } 96 regs.rax = 0xFFFF; 97 vmcs_write(GUEST_RIP, guest_rip + 3); 98 return VMX_TEST_RESUME; 99 default: 100 report(0, "test vmresume"); 101 print_vmexit_info(exit_reason); 102 } 103 return VMX_TEST_VMEXIT; 104 } 105 106 u32 preempt_scale; 107 volatile unsigned long long tsc_val; 108 volatile u32 preempt_val; 109 u64 saved_rip; 110 111 static int preemption_timer_init(struct vmcs *vmcs) 112 { 113 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 114 printf("\tPreemption timer is not supported\n"); 115 return VMX_TEST_EXIT; 116 } 117 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 118 preempt_val = 10000000; 119 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 120 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 121 122 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 123 printf("\tSave preemption value is not supported\n"); 124 125 return VMX_TEST_START; 126 } 127 128 static void preemption_timer_main(void) 129 { 130 tsc_val = rdtsc(); 131 if (ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) { 132 vmx_set_test_stage(0); 133 vmcall(); 134 if (vmx_get_test_stage() == 1) 135 vmcall(); 136 } 137 vmx_set_test_stage(1); 138 while (vmx_get_test_stage() == 1) { 139 if (((rdtsc() - tsc_val) >> preempt_scale) 140 > 10 * preempt_val) { 141 vmx_set_test_stage(2); 142 vmcall(); 143 } 144 } 145 tsc_val = rdtsc(); 146 asm volatile ("hlt"); 147 vmcall(); 148 vmx_set_test_stage(5); 149 vmcall(); 150 } 151 152 static int preemption_timer_exit_handler(union exit_reason exit_reason) 153 { 154 bool guest_halted; 155 u64 guest_rip; 156 u32 insn_len; 157 u32 ctrl_exit; 158 159 guest_rip = vmcs_read(GUEST_RIP); 160 insn_len = vmcs_read(EXI_INST_LEN); 161 switch (exit_reason.basic) { 162 case VMX_PREEMPT: 163 switch (vmx_get_test_stage()) { 164 case 1: 165 case 2: 166 report(((rdtsc() - tsc_val) >> preempt_scale) >= preempt_val, 167 "busy-wait for preemption timer"); 168 vmx_set_test_stage(3); 169 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 170 return VMX_TEST_RESUME; 171 case 3: 172 guest_halted = 173 (vmcs_read(GUEST_ACTV_STATE) == ACTV_HLT); 174 report(((rdtsc() - tsc_val) >> preempt_scale) >= preempt_val 175 && guest_halted, 176 "preemption timer during hlt"); 177 vmx_set_test_stage(4); 178 vmcs_write(PIN_CONTROLS, 179 vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 180 vmcs_write(EXI_CONTROLS, 181 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_PREEMPT); 182 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 183 return VMX_TEST_RESUME; 184 case 4: 185 report(saved_rip == guest_rip, 186 "preemption timer with 0 value"); 187 break; 188 default: 189 report(false, "Invalid stage."); 190 print_vmexit_info(exit_reason); 191 break; 192 } 193 break; 194 case VMX_VMCALL: 195 vmcs_write(GUEST_RIP, guest_rip + insn_len); 196 switch (vmx_get_test_stage()) { 197 case 0: 198 report(vmcs_read(PREEMPT_TIMER_VALUE) == preempt_val, 199 "Keep preemption value"); 200 vmx_set_test_stage(1); 201 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 202 ctrl_exit = (vmcs_read(EXI_CONTROLS) | 203 EXI_SAVE_PREEMPT) & ctrl_exit_rev.clr; 204 vmcs_write(EXI_CONTROLS, ctrl_exit); 205 return VMX_TEST_RESUME; 206 case 1: 207 report(vmcs_read(PREEMPT_TIMER_VALUE) < preempt_val, 208 "Save preemption value"); 209 return VMX_TEST_RESUME; 210 case 2: 211 report(0, "busy-wait for preemption timer"); 212 vmx_set_test_stage(3); 213 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 214 return VMX_TEST_RESUME; 215 case 3: 216 report(0, "preemption timer during hlt"); 217 vmx_set_test_stage(4); 218 /* fall through */ 219 case 4: 220 vmcs_write(PIN_CONTROLS, 221 vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 222 vmcs_write(PREEMPT_TIMER_VALUE, 0); 223 saved_rip = guest_rip + insn_len; 224 return VMX_TEST_RESUME; 225 case 5: 226 report(0, 227 "preemption timer with 0 value (vmcall stage 5)"); 228 break; 229 default: 230 // Should not reach here 231 report(false, "unexpected stage, %d", 232 vmx_get_test_stage()); 233 print_vmexit_info(exit_reason); 234 return VMX_TEST_VMEXIT; 235 } 236 break; 237 default: 238 report(false, "Unknown exit reason, 0x%x", exit_reason.full); 239 print_vmexit_info(exit_reason); 240 } 241 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 242 return VMX_TEST_VMEXIT; 243 } 244 245 static void msr_bmp_init(void) 246 { 247 void *msr_bitmap; 248 u32 ctrl_cpu0; 249 250 msr_bitmap = alloc_page(); 251 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 252 ctrl_cpu0 |= CPU_MSR_BITMAP; 253 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 254 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 255 } 256 257 static void *get_msr_bitmap(void) 258 { 259 void *msr_bitmap; 260 261 if (vmcs_read(CPU_EXEC_CTRL0) & CPU_MSR_BITMAP) { 262 msr_bitmap = (void *)vmcs_read(MSR_BITMAP); 263 } else { 264 msr_bitmap = alloc_page(); 265 memset(msr_bitmap, 0xff, PAGE_SIZE); 266 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 267 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_MSR_BITMAP); 268 } 269 270 return msr_bitmap; 271 } 272 273 static void disable_intercept_for_x2apic_msrs(void) 274 { 275 unsigned long *msr_bitmap = (unsigned long *)get_msr_bitmap(); 276 u32 msr; 277 278 for (msr = APIC_BASE_MSR; 279 msr < (APIC_BASE_MSR+0xff); 280 msr += BITS_PER_LONG) { 281 unsigned int word = msr / BITS_PER_LONG; 282 283 msr_bitmap[word] = 0; 284 msr_bitmap[word + (0x800 / sizeof(long))] = 0; 285 } 286 } 287 288 static int test_ctrl_pat_init(struct vmcs *vmcs) 289 { 290 u64 ctrl_ent; 291 u64 ctrl_exi; 292 293 msr_bmp_init(); 294 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT) && 295 !(ctrl_exit_rev.clr & EXI_LOAD_PAT) && 296 !(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 297 printf("\tSave/load PAT is not supported\n"); 298 return 1; 299 } 300 301 ctrl_ent = vmcs_read(ENT_CONTROLS); 302 ctrl_exi = vmcs_read(EXI_CONTROLS); 303 ctrl_ent |= ctrl_enter_rev.clr & ENT_LOAD_PAT; 304 ctrl_exi |= ctrl_exit_rev.clr & (EXI_SAVE_PAT | EXI_LOAD_PAT); 305 vmcs_write(ENT_CONTROLS, ctrl_ent); 306 vmcs_write(EXI_CONTROLS, ctrl_exi); 307 ia32_pat = rdmsr(MSR_IA32_CR_PAT); 308 vmcs_write(GUEST_PAT, 0x0); 309 vmcs_write(HOST_PAT, ia32_pat); 310 return VMX_TEST_START; 311 } 312 313 static void test_ctrl_pat_main(void) 314 { 315 u64 guest_ia32_pat; 316 317 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 318 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) 319 printf("\tENT_LOAD_PAT is not supported.\n"); 320 else { 321 if (guest_ia32_pat != 0) { 322 report(0, "Entry load PAT"); 323 return; 324 } 325 } 326 wrmsr(MSR_IA32_CR_PAT, 0x6); 327 vmcall(); 328 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 329 if (ctrl_enter_rev.clr & ENT_LOAD_PAT) 330 report(guest_ia32_pat == ia32_pat, "Entry load PAT"); 331 } 332 333 static int test_ctrl_pat_exit_handler(union exit_reason exit_reason) 334 { 335 u64 guest_rip; 336 u64 guest_pat; 337 338 guest_rip = vmcs_read(GUEST_RIP); 339 switch (exit_reason.basic) { 340 case VMX_VMCALL: 341 guest_pat = vmcs_read(GUEST_PAT); 342 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT)) { 343 printf("\tEXI_SAVE_PAT is not supported\n"); 344 vmcs_write(GUEST_PAT, 0x6); 345 } else { 346 report(guest_pat == 0x6, "Exit save PAT"); 347 } 348 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) 349 printf("\tEXI_LOAD_PAT is not supported\n"); 350 else 351 report(rdmsr(MSR_IA32_CR_PAT) == ia32_pat, 352 "Exit load PAT"); 353 vmcs_write(GUEST_PAT, ia32_pat); 354 vmcs_write(GUEST_RIP, guest_rip + 3); 355 return VMX_TEST_RESUME; 356 default: 357 printf("ERROR : Unknown exit reason, 0x%x.\n", exit_reason.full); 358 break; 359 } 360 return VMX_TEST_VMEXIT; 361 } 362 363 static int test_ctrl_efer_init(struct vmcs *vmcs) 364 { 365 u64 ctrl_ent; 366 u64 ctrl_exi; 367 368 msr_bmp_init(); 369 ctrl_ent = vmcs_read(ENT_CONTROLS) | ENT_LOAD_EFER; 370 ctrl_exi = vmcs_read(EXI_CONTROLS) | EXI_SAVE_EFER | EXI_LOAD_EFER; 371 vmcs_write(ENT_CONTROLS, ctrl_ent & ctrl_enter_rev.clr); 372 vmcs_write(EXI_CONTROLS, ctrl_exi & ctrl_exit_rev.clr); 373 ia32_efer = rdmsr(MSR_EFER); 374 vmcs_write(GUEST_EFER, ia32_efer ^ EFER_NX); 375 vmcs_write(HOST_EFER, ia32_efer ^ EFER_NX); 376 return VMX_TEST_START; 377 } 378 379 static void test_ctrl_efer_main(void) 380 { 381 u64 guest_ia32_efer; 382 383 guest_ia32_efer = rdmsr(MSR_EFER); 384 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) 385 printf("\tENT_LOAD_EFER is not supported.\n"); 386 else { 387 if (guest_ia32_efer != (ia32_efer ^ EFER_NX)) { 388 report(0, "Entry load EFER"); 389 return; 390 } 391 } 392 wrmsr(MSR_EFER, ia32_efer); 393 vmcall(); 394 guest_ia32_efer = rdmsr(MSR_EFER); 395 if (ctrl_enter_rev.clr & ENT_LOAD_EFER) 396 report(guest_ia32_efer == ia32_efer, "Entry load EFER"); 397 } 398 399 static int test_ctrl_efer_exit_handler(union exit_reason exit_reason) 400 { 401 u64 guest_rip; 402 u64 guest_efer; 403 404 guest_rip = vmcs_read(GUEST_RIP); 405 switch (exit_reason.basic) { 406 case VMX_VMCALL: 407 guest_efer = vmcs_read(GUEST_EFER); 408 if (!(ctrl_exit_rev.clr & EXI_SAVE_EFER)) { 409 printf("\tEXI_SAVE_EFER is not supported\n"); 410 vmcs_write(GUEST_EFER, ia32_efer); 411 } else { 412 report(guest_efer == ia32_efer, "Exit save EFER"); 413 } 414 if (!(ctrl_exit_rev.clr & EXI_LOAD_EFER)) { 415 printf("\tEXI_LOAD_EFER is not supported\n"); 416 wrmsr(MSR_EFER, ia32_efer ^ EFER_NX); 417 } else { 418 report(rdmsr(MSR_EFER) == (ia32_efer ^ EFER_NX), 419 "Exit load EFER"); 420 } 421 vmcs_write(GUEST_PAT, ia32_efer); 422 vmcs_write(GUEST_RIP, guest_rip + 3); 423 return VMX_TEST_RESUME; 424 default: 425 printf("ERROR : Unknown exit reason, 0x%x.\n", exit_reason.full); 426 break; 427 } 428 return VMX_TEST_VMEXIT; 429 } 430 431 u32 guest_cr0, guest_cr4; 432 433 static void cr_shadowing_main(void) 434 { 435 u32 cr0, cr4, tmp; 436 437 // Test read through 438 vmx_set_test_stage(0); 439 guest_cr0 = read_cr0(); 440 if (vmx_get_test_stage() == 1) 441 report(0, "Read through CR0"); 442 else 443 vmcall(); 444 vmx_set_test_stage(1); 445 guest_cr4 = read_cr4(); 446 if (vmx_get_test_stage() == 2) 447 report(0, "Read through CR4"); 448 else 449 vmcall(); 450 // Test write through 451 guest_cr0 = guest_cr0 ^ (X86_CR0_TS | X86_CR0_MP); 452 guest_cr4 = guest_cr4 ^ (X86_CR4_TSD | X86_CR4_DE); 453 vmx_set_test_stage(2); 454 write_cr0(guest_cr0); 455 if (vmx_get_test_stage() == 3) 456 report(0, "Write throuth CR0"); 457 else 458 vmcall(); 459 vmx_set_test_stage(3); 460 write_cr4(guest_cr4); 461 if (vmx_get_test_stage() == 4) 462 report(0, "Write through CR4"); 463 else 464 vmcall(); 465 // Test read shadow 466 vmx_set_test_stage(4); 467 vmcall(); 468 cr0 = read_cr0(); 469 if (vmx_get_test_stage() != 5) 470 report(cr0 == guest_cr0, "Read shadowing CR0"); 471 vmx_set_test_stage(5); 472 cr4 = read_cr4(); 473 if (vmx_get_test_stage() != 6) 474 report(cr4 == guest_cr4, "Read shadowing CR4"); 475 // Test write shadow (same value with shadow) 476 vmx_set_test_stage(6); 477 write_cr0(guest_cr0); 478 if (vmx_get_test_stage() == 7) 479 report(0, "Write shadowing CR0 (same value with shadow)"); 480 else 481 vmcall(); 482 vmx_set_test_stage(7); 483 write_cr4(guest_cr4); 484 if (vmx_get_test_stage() == 8) 485 report(0, "Write shadowing CR4 (same value with shadow)"); 486 else 487 vmcall(); 488 // Test write shadow (different value) 489 vmx_set_test_stage(8); 490 tmp = guest_cr0 ^ X86_CR0_TS; 491 asm volatile("mov %0, %%rsi\n\t" 492 "mov %%rsi, %%cr0\n\t" 493 ::"m"(tmp) 494 :"rsi", "memory", "cc"); 495 report(vmx_get_test_stage() == 9, 496 "Write shadowing different X86_CR0_TS"); 497 vmx_set_test_stage(9); 498 tmp = guest_cr0 ^ X86_CR0_MP; 499 asm volatile("mov %0, %%rsi\n\t" 500 "mov %%rsi, %%cr0\n\t" 501 ::"m"(tmp) 502 :"rsi", "memory", "cc"); 503 report(vmx_get_test_stage() == 10, 504 "Write shadowing different X86_CR0_MP"); 505 vmx_set_test_stage(10); 506 tmp = guest_cr4 ^ X86_CR4_TSD; 507 asm volatile("mov %0, %%rsi\n\t" 508 "mov %%rsi, %%cr4\n\t" 509 ::"m"(tmp) 510 :"rsi", "memory", "cc"); 511 report(vmx_get_test_stage() == 11, 512 "Write shadowing different X86_CR4_TSD"); 513 vmx_set_test_stage(11); 514 tmp = guest_cr4 ^ X86_CR4_DE; 515 asm volatile("mov %0, %%rsi\n\t" 516 "mov %%rsi, %%cr4\n\t" 517 ::"m"(tmp) 518 :"rsi", "memory", "cc"); 519 report(vmx_get_test_stage() == 12, 520 "Write shadowing different X86_CR4_DE"); 521 } 522 523 static int cr_shadowing_exit_handler(union exit_reason exit_reason) 524 { 525 u64 guest_rip; 526 u32 insn_len; 527 u32 exit_qual; 528 529 guest_rip = vmcs_read(GUEST_RIP); 530 insn_len = vmcs_read(EXI_INST_LEN); 531 exit_qual = vmcs_read(EXI_QUALIFICATION); 532 switch (exit_reason.basic) { 533 case VMX_VMCALL: 534 switch (vmx_get_test_stage()) { 535 case 0: 536 report(guest_cr0 == vmcs_read(GUEST_CR0), 537 "Read through CR0"); 538 break; 539 case 1: 540 report(guest_cr4 == vmcs_read(GUEST_CR4), 541 "Read through CR4"); 542 break; 543 case 2: 544 report(guest_cr0 == vmcs_read(GUEST_CR0), 545 "Write through CR0"); 546 break; 547 case 3: 548 report(guest_cr4 == vmcs_read(GUEST_CR4), 549 "Write through CR4"); 550 break; 551 case 4: 552 guest_cr0 = vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP); 553 guest_cr4 = vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE); 554 vmcs_write(CR0_MASK, X86_CR0_TS | X86_CR0_MP); 555 vmcs_write(CR0_READ_SHADOW, guest_cr0 & (X86_CR0_TS | X86_CR0_MP)); 556 vmcs_write(CR4_MASK, X86_CR4_TSD | X86_CR4_DE); 557 vmcs_write(CR4_READ_SHADOW, guest_cr4 & (X86_CR4_TSD | X86_CR4_DE)); 558 break; 559 case 6: 560 report(guest_cr0 == (vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP)), 561 "Write shadowing CR0 (same value)"); 562 break; 563 case 7: 564 report(guest_cr4 == (vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE)), 565 "Write shadowing CR4 (same value)"); 566 break; 567 default: 568 // Should not reach here 569 report(false, "unexpected stage, %d", 570 vmx_get_test_stage()); 571 print_vmexit_info(exit_reason); 572 return VMX_TEST_VMEXIT; 573 } 574 vmcs_write(GUEST_RIP, guest_rip + insn_len); 575 return VMX_TEST_RESUME; 576 case VMX_CR: 577 switch (vmx_get_test_stage()) { 578 case 4: 579 report(0, "Read shadowing CR0"); 580 vmx_inc_test_stage(); 581 break; 582 case 5: 583 report(0, "Read shadowing CR4"); 584 vmx_inc_test_stage(); 585 break; 586 case 6: 587 report(0, "Write shadowing CR0 (same value)"); 588 vmx_inc_test_stage(); 589 break; 590 case 7: 591 report(0, "Write shadowing CR4 (same value)"); 592 vmx_inc_test_stage(); 593 break; 594 case 8: 595 case 9: 596 // 0x600 encodes "mov %esi, %cr0" 597 if (exit_qual == 0x600) 598 vmx_inc_test_stage(); 599 break; 600 case 10: 601 case 11: 602 // 0x604 encodes "mov %esi, %cr4" 603 if (exit_qual == 0x604) 604 vmx_inc_test_stage(); 605 break; 606 default: 607 // Should not reach here 608 report(false, "unexpected stage, %d", 609 vmx_get_test_stage()); 610 print_vmexit_info(exit_reason); 611 return VMX_TEST_VMEXIT; 612 } 613 vmcs_write(GUEST_RIP, guest_rip + insn_len); 614 return VMX_TEST_RESUME; 615 default: 616 report(false, "Unknown exit reason, 0x%x", exit_reason.full); 617 print_vmexit_info(exit_reason); 618 } 619 return VMX_TEST_VMEXIT; 620 } 621 622 static int iobmp_init(struct vmcs *vmcs) 623 { 624 u32 ctrl_cpu0; 625 626 io_bitmap_a = alloc_page(); 627 io_bitmap_b = alloc_page(); 628 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 629 ctrl_cpu0 |= CPU_IO_BITMAP; 630 ctrl_cpu0 &= (~CPU_IO); 631 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 632 vmcs_write(IO_BITMAP_A, (u64)io_bitmap_a); 633 vmcs_write(IO_BITMAP_B, (u64)io_bitmap_b); 634 return VMX_TEST_START; 635 } 636 637 static void iobmp_main(void) 638 { 639 // stage 0, test IO pass 640 vmx_set_test_stage(0); 641 inb(0x5000); 642 outb(0x0, 0x5000); 643 report(vmx_get_test_stage() == 0, "I/O bitmap - I/O pass"); 644 // test IO width, in/out 645 ((u8 *)io_bitmap_a)[0] = 0xFF; 646 vmx_set_test_stage(2); 647 inb(0x0); 648 report(vmx_get_test_stage() == 3, "I/O bitmap - trap in"); 649 vmx_set_test_stage(3); 650 outw(0x0, 0x0); 651 report(vmx_get_test_stage() == 4, "I/O bitmap - trap out"); 652 vmx_set_test_stage(4); 653 inl(0x0); 654 report(vmx_get_test_stage() == 5, "I/O bitmap - I/O width, long"); 655 // test low/high IO port 656 vmx_set_test_stage(5); 657 ((u8 *)io_bitmap_a)[0x5000 / 8] = (1 << (0x5000 % 8)); 658 inb(0x5000); 659 report(vmx_get_test_stage() == 6, "I/O bitmap - I/O port, low part"); 660 vmx_set_test_stage(6); 661 ((u8 *)io_bitmap_b)[0x1000 / 8] = (1 << (0x1000 % 8)); 662 inb(0x9000); 663 report(vmx_get_test_stage() == 7, "I/O bitmap - I/O port, high part"); 664 // test partial pass 665 vmx_set_test_stage(7); 666 inl(0x4FFF); 667 report(vmx_get_test_stage() == 8, "I/O bitmap - partial pass"); 668 // test overrun 669 vmx_set_test_stage(8); 670 memset(io_bitmap_a, 0x0, PAGE_SIZE); 671 memset(io_bitmap_b, 0x0, PAGE_SIZE); 672 inl(0xFFFF); 673 report(vmx_get_test_stage() == 9, "I/O bitmap - overrun"); 674 vmx_set_test_stage(9); 675 vmcall(); 676 outb(0x0, 0x0); 677 report(vmx_get_test_stage() == 9, 678 "I/O bitmap - ignore unconditional exiting"); 679 vmx_set_test_stage(10); 680 vmcall(); 681 outb(0x0, 0x0); 682 report(vmx_get_test_stage() == 11, 683 "I/O bitmap - unconditional exiting"); 684 } 685 686 static int iobmp_exit_handler(union exit_reason exit_reason) 687 { 688 u64 guest_rip; 689 ulong exit_qual; 690 u32 insn_len, ctrl_cpu0; 691 692 guest_rip = vmcs_read(GUEST_RIP); 693 exit_qual = vmcs_read(EXI_QUALIFICATION); 694 insn_len = vmcs_read(EXI_INST_LEN); 695 switch (exit_reason.basic) { 696 case VMX_IO: 697 switch (vmx_get_test_stage()) { 698 case 0: 699 case 1: 700 vmx_inc_test_stage(); 701 break; 702 case 2: 703 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_BYTE, 704 "I/O bitmap - I/O width, byte"); 705 report(exit_qual & VMX_IO_IN, 706 "I/O bitmap - I/O direction, in"); 707 vmx_inc_test_stage(); 708 break; 709 case 3: 710 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_WORD, 711 "I/O bitmap - I/O width, word"); 712 report(!(exit_qual & VMX_IO_IN), 713 "I/O bitmap - I/O direction, out"); 714 vmx_inc_test_stage(); 715 break; 716 case 4: 717 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_LONG, 718 "I/O bitmap - I/O width, long"); 719 vmx_inc_test_stage(); 720 break; 721 case 5: 722 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x5000) 723 vmx_inc_test_stage(); 724 break; 725 case 6: 726 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x9000) 727 vmx_inc_test_stage(); 728 break; 729 case 7: 730 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x4FFF) 731 vmx_inc_test_stage(); 732 break; 733 case 8: 734 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0xFFFF) 735 vmx_inc_test_stage(); 736 break; 737 case 9: 738 case 10: 739 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 740 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0 & ~CPU_IO); 741 vmx_inc_test_stage(); 742 break; 743 default: 744 // Should not reach here 745 report(false, "unexpected stage, %d", 746 vmx_get_test_stage()); 747 print_vmexit_info(exit_reason); 748 return VMX_TEST_VMEXIT; 749 } 750 vmcs_write(GUEST_RIP, guest_rip + insn_len); 751 return VMX_TEST_RESUME; 752 case VMX_VMCALL: 753 switch (vmx_get_test_stage()) { 754 case 9: 755 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 756 ctrl_cpu0 |= CPU_IO | CPU_IO_BITMAP; 757 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 758 break; 759 case 10: 760 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 761 ctrl_cpu0 = (ctrl_cpu0 & ~CPU_IO_BITMAP) | CPU_IO; 762 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 763 break; 764 default: 765 // Should not reach here 766 report(false, "unexpected stage, %d", 767 vmx_get_test_stage()); 768 print_vmexit_info(exit_reason); 769 return VMX_TEST_VMEXIT; 770 } 771 vmcs_write(GUEST_RIP, guest_rip + insn_len); 772 return VMX_TEST_RESUME; 773 default: 774 printf("guest_rip = %#lx\n", guest_rip); 775 printf("\tERROR : Unknown exit reason, 0x%x\n", exit_reason.full); 776 break; 777 } 778 return VMX_TEST_VMEXIT; 779 } 780 781 #define INSN_CPU0 0 782 #define INSN_CPU1 1 783 #define INSN_ALWAYS_TRAP 2 784 785 #define FIELD_EXIT_QUAL (1 << 0) 786 #define FIELD_INSN_INFO (1 << 1) 787 788 asm( 789 "insn_hlt: hlt;ret\n\t" 790 "insn_invlpg: invlpg 0x12345678;ret\n\t" 791 "insn_mwait: xor %eax, %eax; xor %ecx, %ecx; mwait;ret\n\t" 792 "insn_rdpmc: xor %ecx, %ecx; rdpmc;ret\n\t" 793 "insn_rdtsc: rdtsc;ret\n\t" 794 "insn_cr3_load: mov cr3,%rax; mov %rax,%cr3;ret\n\t" 795 "insn_cr3_store: mov %cr3,%rax;ret\n\t" 796 #ifdef __x86_64__ 797 "insn_cr8_load: xor %eax, %eax; mov %rax,%cr8;ret\n\t" 798 "insn_cr8_store: mov %cr8,%rax;ret\n\t" 799 #endif 800 "insn_monitor: xor %eax, %eax; xor %ecx, %ecx; xor %edx, %edx; monitor;ret\n\t" 801 "insn_pause: pause;ret\n\t" 802 "insn_wbinvd: wbinvd;ret\n\t" 803 "insn_cpuid: mov $10, %eax; cpuid;ret\n\t" 804 "insn_invd: invd;ret\n\t" 805 "insn_sgdt: sgdt gdt64_desc;ret\n\t" 806 "insn_lgdt: lgdt gdt64_desc;ret\n\t" 807 "insn_sidt: sidt idt_descr;ret\n\t" 808 "insn_lidt: lidt idt_descr;ret\n\t" 809 "insn_sldt: sldt %ax;ret\n\t" 810 "insn_lldt: xor %eax, %eax; lldt %ax;ret\n\t" 811 "insn_str: str %ax;ret\n\t" 812 "insn_rdrand: rdrand %rax;ret\n\t" 813 "insn_rdseed: rdseed %rax;ret\n\t" 814 ); 815 extern void insn_hlt(void); 816 extern void insn_invlpg(void); 817 extern void insn_mwait(void); 818 extern void insn_rdpmc(void); 819 extern void insn_rdtsc(void); 820 extern void insn_cr3_load(void); 821 extern void insn_cr3_store(void); 822 #ifdef __x86_64__ 823 extern void insn_cr8_load(void); 824 extern void insn_cr8_store(void); 825 #endif 826 extern void insn_monitor(void); 827 extern void insn_pause(void); 828 extern void insn_wbinvd(void); 829 extern void insn_sgdt(void); 830 extern void insn_lgdt(void); 831 extern void insn_sidt(void); 832 extern void insn_lidt(void); 833 extern void insn_sldt(void); 834 extern void insn_lldt(void); 835 extern void insn_str(void); 836 extern void insn_cpuid(void); 837 extern void insn_invd(void); 838 extern void insn_rdrand(void); 839 extern void insn_rdseed(void); 840 841 u32 cur_insn; 842 u64 cr3; 843 844 #define X86_FEATURE_MONITOR (1 << 3) 845 846 typedef bool (*supported_fn)(void); 847 848 static bool monitor_supported(void) 849 { 850 return this_cpu_has(X86_FEATURE_MWAIT); 851 } 852 853 struct insn_table { 854 const char *name; 855 u32 flag; 856 void (*insn_func)(void); 857 u32 type; 858 u32 reason; 859 ulong exit_qual; 860 u32 insn_info; 861 // Use FIELD_EXIT_QUAL and FIELD_INSN_INFO to define 862 // which field need to be tested, reason is always tested 863 u32 test_field; 864 const supported_fn supported_fn; 865 u8 disabled; 866 }; 867 868 /* 869 * Add more test cases of instruction intercept here. Elements in this 870 * table is: 871 * name/control flag/insn function/type/exit reason/exit qulification/ 872 * instruction info/field to test 873 * The last field defines which fields (exit_qual and insn_info) need to be 874 * tested in exit handler. If set to 0, only "reason" is checked. 875 */ 876 static struct insn_table insn_table[] = { 877 // Flags for Primary Processor-Based VM-Execution Controls 878 {"HLT", CPU_HLT, insn_hlt, INSN_CPU0, 12, 0, 0, 0}, 879 {"INVLPG", CPU_INVLPG, insn_invlpg, INSN_CPU0, 14, 880 0x12345678, 0, FIELD_EXIT_QUAL}, 881 {"MWAIT", CPU_MWAIT, insn_mwait, INSN_CPU0, 36, 0, 0, 0, &monitor_supported}, 882 {"RDPMC", CPU_RDPMC, insn_rdpmc, INSN_CPU0, 15, 0, 0, 0}, 883 {"RDTSC", CPU_RDTSC, insn_rdtsc, INSN_CPU0, 16, 0, 0, 0}, 884 {"CR3 load", CPU_CR3_LOAD, insn_cr3_load, INSN_CPU0, 28, 0x3, 0, 885 FIELD_EXIT_QUAL}, 886 {"CR3 store", CPU_CR3_STORE, insn_cr3_store, INSN_CPU0, 28, 0x13, 0, 887 FIELD_EXIT_QUAL}, 888 #ifdef __x86_64__ 889 {"CR8 load", CPU_CR8_LOAD, insn_cr8_load, INSN_CPU0, 28, 0x8, 0, 890 FIELD_EXIT_QUAL}, 891 {"CR8 store", CPU_CR8_STORE, insn_cr8_store, INSN_CPU0, 28, 0x18, 0, 892 FIELD_EXIT_QUAL}, 893 #endif 894 {"MONITOR", CPU_MONITOR, insn_monitor, INSN_CPU0, 39, 0, 0, 0, &monitor_supported}, 895 {"PAUSE", CPU_PAUSE, insn_pause, INSN_CPU0, 40, 0, 0, 0}, 896 // Flags for Secondary Processor-Based VM-Execution Controls 897 {"WBINVD", CPU_WBINVD, insn_wbinvd, INSN_CPU1, 54, 0, 0, 0}, 898 {"DESC_TABLE (SGDT)", CPU_DESC_TABLE, insn_sgdt, INSN_CPU1, 46, 0, 0, 0}, 899 {"DESC_TABLE (LGDT)", CPU_DESC_TABLE, insn_lgdt, INSN_CPU1, 46, 0, 0, 0}, 900 {"DESC_TABLE (SIDT)", CPU_DESC_TABLE, insn_sidt, INSN_CPU1, 46, 0, 0, 0}, 901 {"DESC_TABLE (LIDT)", CPU_DESC_TABLE, insn_lidt, INSN_CPU1, 46, 0, 0, 0}, 902 {"DESC_TABLE (SLDT)", CPU_DESC_TABLE, insn_sldt, INSN_CPU1, 47, 0, 0, 0}, 903 {"DESC_TABLE (LLDT)", CPU_DESC_TABLE, insn_lldt, INSN_CPU1, 47, 0, 0, 0}, 904 {"DESC_TABLE (STR)", CPU_DESC_TABLE, insn_str, INSN_CPU1, 47, 0, 0, 0}, 905 /* LTR causes a #GP if done with a busy selector, so it is not tested. */ 906 {"RDRAND", CPU_RDRAND, insn_rdrand, INSN_CPU1, VMX_RDRAND, 0, 0, 0}, 907 {"RDSEED", CPU_RDSEED, insn_rdseed, INSN_CPU1, VMX_RDSEED, 0, 0, 0}, 908 // Instructions always trap 909 {"CPUID", 0, insn_cpuid, INSN_ALWAYS_TRAP, 10, 0, 0, 0}, 910 {"INVD", 0, insn_invd, INSN_ALWAYS_TRAP, 13, 0, 0, 0}, 911 // Instructions never trap 912 {NULL}, 913 }; 914 915 static int insn_intercept_init(struct vmcs *vmcs) 916 { 917 u32 ctrl_cpu, cur_insn; 918 919 ctrl_cpu = ctrl_cpu_rev[0].set | CPU_SECONDARY; 920 ctrl_cpu &= ctrl_cpu_rev[0].clr; 921 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu); 922 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu_rev[1].set); 923 cr3 = read_cr3(); 924 925 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 926 if (insn_table[cur_insn].supported_fn == NULL) 927 continue; 928 insn_table[cur_insn].disabled = !insn_table[cur_insn].supported_fn(); 929 } 930 return VMX_TEST_START; 931 } 932 933 static void insn_intercept_main(void) 934 { 935 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 936 vmx_set_test_stage(cur_insn * 2); 937 if ((insn_table[cur_insn].type == INSN_CPU0 && 938 !(ctrl_cpu_rev[0].clr & insn_table[cur_insn].flag)) || 939 (insn_table[cur_insn].type == INSN_CPU1 && 940 !(ctrl_cpu_rev[1].clr & insn_table[cur_insn].flag))) { 941 printf("\tCPU_CTRL%d.CPU_%s is not supported.\n", 942 insn_table[cur_insn].type - INSN_CPU0, 943 insn_table[cur_insn].name); 944 continue; 945 } 946 947 if (insn_table[cur_insn].disabled) { 948 printf("\tFeature required for %s is not supported.\n", 949 insn_table[cur_insn].name); 950 continue; 951 } 952 953 if ((insn_table[cur_insn].type == INSN_CPU0 && 954 !(ctrl_cpu_rev[0].set & insn_table[cur_insn].flag)) || 955 (insn_table[cur_insn].type == INSN_CPU1 && 956 !(ctrl_cpu_rev[1].set & insn_table[cur_insn].flag))) { 957 /* skip hlt, it stalls the guest and is tested below */ 958 if (insn_table[cur_insn].insn_func != insn_hlt) 959 insn_table[cur_insn].insn_func(); 960 report(vmx_get_test_stage() == cur_insn * 2, 961 "execute %s", 962 insn_table[cur_insn].name); 963 } else if (insn_table[cur_insn].type != INSN_ALWAYS_TRAP) 964 printf("\tCPU_CTRL%d.CPU_%s always traps.\n", 965 insn_table[cur_insn].type - INSN_CPU0, 966 insn_table[cur_insn].name); 967 968 vmcall(); 969 970 insn_table[cur_insn].insn_func(); 971 report(vmx_get_test_stage() == cur_insn * 2 + 1, 972 "intercept %s", 973 insn_table[cur_insn].name); 974 975 vmx_set_test_stage(cur_insn * 2 + 1); 976 vmcall(); 977 } 978 } 979 980 static int insn_intercept_exit_handler(union exit_reason exit_reason) 981 { 982 u64 guest_rip; 983 ulong exit_qual; 984 u32 insn_len; 985 u32 insn_info; 986 bool pass; 987 988 guest_rip = vmcs_read(GUEST_RIP); 989 exit_qual = vmcs_read(EXI_QUALIFICATION); 990 insn_len = vmcs_read(EXI_INST_LEN); 991 insn_info = vmcs_read(EXI_INST_INFO); 992 993 if (exit_reason.basic == VMX_VMCALL) { 994 u32 val = 0; 995 996 if (insn_table[cur_insn].type == INSN_CPU0) 997 val = vmcs_read(CPU_EXEC_CTRL0); 998 else if (insn_table[cur_insn].type == INSN_CPU1) 999 val = vmcs_read(CPU_EXEC_CTRL1); 1000 1001 if (vmx_get_test_stage() & 1) 1002 val &= ~insn_table[cur_insn].flag; 1003 else 1004 val |= insn_table[cur_insn].flag; 1005 1006 if (insn_table[cur_insn].type == INSN_CPU0) 1007 vmcs_write(CPU_EXEC_CTRL0, val | ctrl_cpu_rev[0].set); 1008 else if (insn_table[cur_insn].type == INSN_CPU1) 1009 vmcs_write(CPU_EXEC_CTRL1, val | ctrl_cpu_rev[1].set); 1010 } else { 1011 pass = (cur_insn * 2 == vmx_get_test_stage()) && 1012 insn_table[cur_insn].reason == exit_reason.full; 1013 if (insn_table[cur_insn].test_field & FIELD_EXIT_QUAL && 1014 insn_table[cur_insn].exit_qual != exit_qual) 1015 pass = false; 1016 if (insn_table[cur_insn].test_field & FIELD_INSN_INFO && 1017 insn_table[cur_insn].insn_info != insn_info) 1018 pass = false; 1019 if (pass) 1020 vmx_inc_test_stage(); 1021 } 1022 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1023 return VMX_TEST_RESUME; 1024 } 1025 1026 /** 1027 * __setup_ept - Setup the VMCS fields to enable Extended Page Tables (EPT) 1028 * @hpa: Host physical address of the top-level, a.k.a. root, EPT table 1029 * @enable_ad: Whether or not to enable Access/Dirty bits for EPT entries 1030 * 1031 * Returns 0 on success, 1 on failure. 1032 * 1033 * Note that @hpa doesn't need to point at actual memory if VM-Launch is 1034 * expected to fail, e.g. setup_dummy_ept() arbitrarily passes '0' to satisfy 1035 * the various EPTP consistency checks, but doesn't ensure backing for HPA '0'. 1036 */ 1037 static int __setup_ept(u64 hpa, bool enable_ad) 1038 { 1039 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1040 !(ctrl_cpu_rev[1].clr & CPU_EPT)) { 1041 printf("\tEPT is not supported"); 1042 return 1; 1043 } 1044 if (!(ept_vpid.val & EPT_CAP_WB)) { 1045 printf("WB memtype for EPT walks not supported\n"); 1046 return 1; 1047 } 1048 if (!(ept_vpid.val & EPT_CAP_PWL4)) { 1049 printf("\tPWL4 is not supported\n"); 1050 return 1; 1051 } 1052 1053 eptp = EPT_MEM_TYPE_WB; 1054 eptp |= (3 << EPTP_PG_WALK_LEN_SHIFT); 1055 eptp |= hpa; 1056 if (enable_ad) 1057 eptp |= EPTP_AD_FLAG; 1058 1059 vmcs_write(EPTP, eptp); 1060 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0)| CPU_SECONDARY); 1061 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1)| CPU_EPT); 1062 1063 return 0; 1064 } 1065 1066 /** 1067 * setup_ept - Enable Extended Page Tables (EPT) and setup an identity map 1068 * @enable_ad: Whether or not to enable Access/Dirty bits for EPT entries 1069 * 1070 * Returns 0 on success, 1 on failure. 1071 * 1072 * This is the "real" function for setting up EPT tables, i.e. use this for 1073 * tests that need to run code in the guest with EPT enabled. 1074 */ 1075 static int setup_ept(bool enable_ad) 1076 { 1077 unsigned long end_of_memory; 1078 1079 pml4 = alloc_page(); 1080 1081 if (__setup_ept(virt_to_phys(pml4), enable_ad)) 1082 return 1; 1083 1084 end_of_memory = fwcfg_get_u64(FW_CFG_RAM_SIZE); 1085 if (end_of_memory < (1ul << 32)) 1086 end_of_memory = (1ul << 32); 1087 /* Cannot use large EPT pages if we need to track EPT 1088 * accessed/dirty bits at 4K granularity. 1089 */ 1090 setup_ept_range(pml4, 0, end_of_memory, 0, 1091 !enable_ad && ept_2m_supported(), 1092 EPT_WA | EPT_RA | EPT_EA); 1093 return 0; 1094 } 1095 1096 /** 1097 * setup_dummy_ept - Enable Extended Page Tables (EPT) with a dummy root HPA 1098 * 1099 * Setup EPT using a semi-arbitrary dummy root HPA. This function is intended 1100 * for use by tests that need EPT enabled to verify dependent VMCS controls 1101 * but never expect to fully enter the guest, i.e. don't need setup the actual 1102 * EPT tables. 1103 */ 1104 static void setup_dummy_ept(void) 1105 { 1106 if (__setup_ept(0, false)) 1107 report_abort("EPT setup unexpectedly failed"); 1108 } 1109 1110 static int enable_unrestricted_guest(void) 1111 { 1112 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1113 !(ctrl_cpu_rev[1].clr & CPU_URG) || 1114 !(ctrl_cpu_rev[1].clr & CPU_EPT)) 1115 return 1; 1116 1117 setup_dummy_ept(); 1118 1119 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 1120 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | CPU_URG); 1121 1122 return 0; 1123 } 1124 1125 static void ept_enable_ad_bits(void) 1126 { 1127 eptp |= EPTP_AD_FLAG; 1128 vmcs_write(EPTP, eptp); 1129 } 1130 1131 static void ept_disable_ad_bits(void) 1132 { 1133 eptp &= ~EPTP_AD_FLAG; 1134 vmcs_write(EPTP, eptp); 1135 } 1136 1137 static int ept_ad_enabled(void) 1138 { 1139 return eptp & EPTP_AD_FLAG; 1140 } 1141 1142 static void ept_enable_ad_bits_or_skip_test(void) 1143 { 1144 if (!ept_ad_bits_supported()) 1145 test_skip("EPT AD bits not supported."); 1146 ept_enable_ad_bits(); 1147 } 1148 1149 static int apic_version; 1150 1151 static int ept_init_common(bool have_ad) 1152 { 1153 int ret; 1154 struct pci_dev pcidev; 1155 1156 if (setup_ept(have_ad)) 1157 return VMX_TEST_EXIT; 1158 data_page1 = alloc_page(); 1159 data_page2 = alloc_page(); 1160 *((u32 *)data_page1) = MAGIC_VAL_1; 1161 *((u32 *)data_page2) = MAGIC_VAL_2; 1162 install_ept(pml4, (unsigned long)data_page1, (unsigned long)data_page2, 1163 EPT_RA | EPT_WA | EPT_EA); 1164 1165 apic_version = apic_read(APIC_LVR); 1166 1167 ret = pci_find_dev(PCI_VENDOR_ID_REDHAT, PCI_DEVICE_ID_REDHAT_TEST); 1168 if (ret != PCIDEVADDR_INVALID) { 1169 pci_dev_init(&pcidev, ret); 1170 pci_physaddr = pcidev.resource[PCI_TESTDEV_BAR_MEM]; 1171 } 1172 1173 return VMX_TEST_START; 1174 } 1175 1176 static int ept_init(struct vmcs *vmcs) 1177 { 1178 return ept_init_common(false); 1179 } 1180 1181 static void ept_common(void) 1182 { 1183 vmx_set_test_stage(0); 1184 if (*((u32 *)data_page2) != MAGIC_VAL_1 || 1185 *((u32 *)data_page1) != MAGIC_VAL_1) 1186 report(0, "EPT basic framework - read"); 1187 else { 1188 *((u32 *)data_page2) = MAGIC_VAL_3; 1189 vmcall(); 1190 if (vmx_get_test_stage() == 1) { 1191 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1192 *((u32 *)data_page2) == MAGIC_VAL_2) 1193 report(1, "EPT basic framework"); 1194 else 1195 report(1, "EPT basic framework - remap"); 1196 } 1197 } 1198 // Test EPT Misconfigurations 1199 vmx_set_test_stage(1); 1200 vmcall(); 1201 *((u32 *)data_page1) = MAGIC_VAL_1; 1202 if (vmx_get_test_stage() != 2) { 1203 report(0, "EPT misconfigurations"); 1204 goto t1; 1205 } 1206 vmx_set_test_stage(2); 1207 vmcall(); 1208 *((u32 *)data_page1) = MAGIC_VAL_1; 1209 report(vmx_get_test_stage() == 3, "EPT misconfigurations"); 1210 t1: 1211 // Test EPT violation 1212 vmx_set_test_stage(3); 1213 vmcall(); 1214 *((u32 *)data_page1) = MAGIC_VAL_1; 1215 report(vmx_get_test_stage() == 4, "EPT violation - page permission"); 1216 // Violation caused by EPT paging structure 1217 vmx_set_test_stage(4); 1218 vmcall(); 1219 *((u32 *)data_page1) = MAGIC_VAL_2; 1220 report(vmx_get_test_stage() == 5, "EPT violation - paging structure"); 1221 1222 // MMIO Read/Write 1223 vmx_set_test_stage(5); 1224 vmcall(); 1225 1226 *(u32 volatile *)pci_physaddr; 1227 report(vmx_get_test_stage() == 6, "MMIO EPT violation - read"); 1228 1229 *(u32 volatile *)pci_physaddr = MAGIC_VAL_1; 1230 report(vmx_get_test_stage() == 7, "MMIO EPT violation - write"); 1231 } 1232 1233 static void ept_main(void) 1234 { 1235 ept_common(); 1236 1237 // Test EPT access to L1 MMIO 1238 vmx_set_test_stage(7); 1239 report(*((u32 *)0xfee00030UL) == apic_version, "EPT - MMIO access"); 1240 1241 // Test invalid operand for INVEPT 1242 vmcall(); 1243 report(vmx_get_test_stage() == 8, "EPT - unsupported INVEPT"); 1244 } 1245 1246 static bool invept_test(int type, u64 eptp) 1247 { 1248 bool ret, supported; 1249 1250 supported = ept_vpid.val & (EPT_CAP_INVEPT_SINGLE >> INVEPT_SINGLE << type); 1251 ret = invept(type, eptp); 1252 1253 if (ret == !supported) 1254 return false; 1255 1256 if (!supported) 1257 printf("WARNING: unsupported invept passed!\n"); 1258 else 1259 printf("WARNING: invept failed!\n"); 1260 1261 return true; 1262 } 1263 1264 static int pml_exit_handler(union exit_reason exit_reason) 1265 { 1266 u16 index, count; 1267 u64 *pmlbuf = pml_log; 1268 u64 guest_rip = vmcs_read(GUEST_RIP);; 1269 u64 guest_cr3 = vmcs_read(GUEST_CR3); 1270 u32 insn_len = vmcs_read(EXI_INST_LEN); 1271 1272 switch (exit_reason.basic) { 1273 case VMX_VMCALL: 1274 switch (vmx_get_test_stage()) { 1275 case 0: 1276 index = vmcs_read(GUEST_PML_INDEX); 1277 for (count = index + 1; count < PML_INDEX; count++) { 1278 if (pmlbuf[count] == (u64)data_page2) { 1279 vmx_inc_test_stage(); 1280 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1281 break; 1282 } 1283 } 1284 break; 1285 case 1: 1286 index = vmcs_read(GUEST_PML_INDEX); 1287 /* Keep clearing the dirty bit till a overflow */ 1288 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1289 break; 1290 default: 1291 report(false, "unexpected stage, %d.", 1292 vmx_get_test_stage()); 1293 print_vmexit_info(exit_reason); 1294 return VMX_TEST_VMEXIT; 1295 } 1296 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1297 return VMX_TEST_RESUME; 1298 case VMX_PML_FULL: 1299 vmx_inc_test_stage(); 1300 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1301 return VMX_TEST_RESUME; 1302 default: 1303 report(false, "Unknown exit reason, 0x%x", exit_reason.full); 1304 print_vmexit_info(exit_reason); 1305 } 1306 return VMX_TEST_VMEXIT; 1307 } 1308 1309 static int ept_exit_handler_common(union exit_reason exit_reason, bool have_ad) 1310 { 1311 u64 guest_rip; 1312 u64 guest_cr3; 1313 u32 insn_len; 1314 u32 exit_qual; 1315 static unsigned long data_page1_pte, data_page1_pte_pte, memaddr_pte, 1316 guest_pte_addr; 1317 1318 guest_rip = vmcs_read(GUEST_RIP); 1319 guest_cr3 = vmcs_read(GUEST_CR3); 1320 insn_len = vmcs_read(EXI_INST_LEN); 1321 exit_qual = vmcs_read(EXI_QUALIFICATION); 1322 pteval_t *ptep; 1323 switch (exit_reason.basic) { 1324 case VMX_VMCALL: 1325 switch (vmx_get_test_stage()) { 1326 case 0: 1327 check_ept_ad(pml4, guest_cr3, 1328 (unsigned long)data_page1, 1329 have_ad ? EPT_ACCESS_FLAG : 0, 1330 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1331 check_ept_ad(pml4, guest_cr3, 1332 (unsigned long)data_page2, 1333 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0, 1334 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1335 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1336 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1337 if (have_ad) 1338 ept_sync(INVEPT_SINGLE, eptp);; 1339 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1340 *((u32 *)data_page2) == MAGIC_VAL_2) { 1341 vmx_inc_test_stage(); 1342 install_ept(pml4, (unsigned long)data_page2, 1343 (unsigned long)data_page2, 1344 EPT_RA | EPT_WA | EPT_EA); 1345 } else 1346 report(0, "EPT basic framework - write"); 1347 break; 1348 case 1: 1349 install_ept(pml4, (unsigned long)data_page1, 1350 (unsigned long)data_page1, EPT_WA); 1351 ept_sync(INVEPT_SINGLE, eptp); 1352 break; 1353 case 2: 1354 install_ept(pml4, (unsigned long)data_page1, 1355 (unsigned long)data_page1, 1356 EPT_RA | EPT_WA | EPT_EA | 1357 (2 << EPT_MEM_TYPE_SHIFT)); 1358 ept_sync(INVEPT_SINGLE, eptp); 1359 break; 1360 case 3: 1361 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1362 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)data_page1, 1363 1, &data_page1_pte)); 1364 set_ept_pte(pml4, (unsigned long)data_page1, 1365 1, data_page1_pte & ~EPT_PRESENT); 1366 ept_sync(INVEPT_SINGLE, eptp); 1367 break; 1368 case 4: 1369 ptep = get_pte_level((pgd_t *)guest_cr3, data_page1, /*level=*/2); 1370 guest_pte_addr = virt_to_phys(ptep) & PAGE_MASK; 1371 1372 TEST_ASSERT(get_ept_pte(pml4, guest_pte_addr, 2, &data_page1_pte_pte)); 1373 set_ept_pte(pml4, guest_pte_addr, 2, 1374 data_page1_pte_pte & ~EPT_PRESENT); 1375 ept_sync(INVEPT_SINGLE, eptp); 1376 break; 1377 case 5: 1378 install_ept(pml4, (unsigned long)pci_physaddr, 1379 (unsigned long)pci_physaddr, 0); 1380 ept_sync(INVEPT_SINGLE, eptp); 1381 break; 1382 case 7: 1383 if (!invept_test(0, eptp)) 1384 vmx_inc_test_stage(); 1385 break; 1386 // Should not reach here 1387 default: 1388 report(false, "ERROR - unexpected stage, %d.", 1389 vmx_get_test_stage()); 1390 print_vmexit_info(exit_reason); 1391 return VMX_TEST_VMEXIT; 1392 } 1393 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1394 return VMX_TEST_RESUME; 1395 case VMX_EPT_MISCONFIG: 1396 switch (vmx_get_test_stage()) { 1397 case 1: 1398 case 2: 1399 vmx_inc_test_stage(); 1400 install_ept(pml4, (unsigned long)data_page1, 1401 (unsigned long)data_page1, 1402 EPT_RA | EPT_WA | EPT_EA); 1403 ept_sync(INVEPT_SINGLE, eptp); 1404 break; 1405 // Should not reach here 1406 default: 1407 report(false, "ERROR - unexpected stage, %d.", 1408 vmx_get_test_stage()); 1409 print_vmexit_info(exit_reason); 1410 return VMX_TEST_VMEXIT; 1411 } 1412 return VMX_TEST_RESUME; 1413 case VMX_EPT_VIOLATION: 1414 /* 1415 * Exit-qualifications are masked not to account for advanced 1416 * VM-exit information. Once KVM supports this feature, this 1417 * masking should be removed. 1418 */ 1419 exit_qual &= ~EPT_VLT_GUEST_MASK; 1420 1421 switch(vmx_get_test_stage()) { 1422 case 3: 1423 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1424 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1425 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1426 if (exit_qual == (EPT_VLT_WR | EPT_VLT_LADDR_VLD | 1427 EPT_VLT_PADDR)) 1428 vmx_inc_test_stage(); 1429 set_ept_pte(pml4, (unsigned long)data_page1, 1430 1, data_page1_pte | (EPT_PRESENT)); 1431 ept_sync(INVEPT_SINGLE, eptp); 1432 break; 1433 case 4: 1434 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1435 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1436 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1437 if (exit_qual == (EPT_VLT_RD | 1438 (have_ad ? EPT_VLT_WR : 0) | 1439 EPT_VLT_LADDR_VLD)) 1440 vmx_inc_test_stage(); 1441 set_ept_pte(pml4, guest_pte_addr, 2, 1442 data_page1_pte_pte | (EPT_PRESENT)); 1443 ept_sync(INVEPT_SINGLE, eptp); 1444 break; 1445 case 5: 1446 if (exit_qual & EPT_VLT_RD) 1447 vmx_inc_test_stage(); 1448 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1449 1, &memaddr_pte)); 1450 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA); 1451 ept_sync(INVEPT_SINGLE, eptp); 1452 break; 1453 case 6: 1454 if (exit_qual & EPT_VLT_WR) 1455 vmx_inc_test_stage(); 1456 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1457 1, &memaddr_pte)); 1458 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA | EPT_WA); 1459 ept_sync(INVEPT_SINGLE, eptp); 1460 break; 1461 default: 1462 // Should not reach here 1463 report(false, "ERROR : unexpected stage, %d", 1464 vmx_get_test_stage()); 1465 print_vmexit_info(exit_reason); 1466 return VMX_TEST_VMEXIT; 1467 } 1468 return VMX_TEST_RESUME; 1469 default: 1470 report(false, "Unknown exit reason, 0x%x", exit_reason.full); 1471 print_vmexit_info(exit_reason); 1472 } 1473 return VMX_TEST_VMEXIT; 1474 } 1475 1476 static int ept_exit_handler(union exit_reason exit_reason) 1477 { 1478 return ept_exit_handler_common(exit_reason, false); 1479 } 1480 1481 static int eptad_init(struct vmcs *vmcs) 1482 { 1483 int r = ept_init_common(true); 1484 1485 if (r == VMX_TEST_EXIT) 1486 return r; 1487 1488 if ((rdmsr(MSR_IA32_VMX_EPT_VPID_CAP) & EPT_CAP_AD_FLAG) == 0) { 1489 printf("\tEPT A/D bits are not supported"); 1490 return VMX_TEST_EXIT; 1491 } 1492 1493 return r; 1494 } 1495 1496 static int pml_init(struct vmcs *vmcs) 1497 { 1498 u32 ctrl_cpu; 1499 int r = eptad_init(vmcs); 1500 1501 if (r == VMX_TEST_EXIT) 1502 return r; 1503 1504 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1505 !(ctrl_cpu_rev[1].clr & CPU_PML)) { 1506 printf("\tPML is not supported"); 1507 return VMX_TEST_EXIT; 1508 } 1509 1510 pml_log = alloc_page(); 1511 vmcs_write(PMLADDR, (u64)pml_log); 1512 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1513 1514 ctrl_cpu = vmcs_read(CPU_EXEC_CTRL1) | CPU_PML; 1515 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu); 1516 1517 return VMX_TEST_START; 1518 } 1519 1520 static void pml_main(void) 1521 { 1522 int count = 0; 1523 1524 vmx_set_test_stage(0); 1525 *((u32 *)data_page2) = 0x1; 1526 vmcall(); 1527 report(vmx_get_test_stage() == 1, "PML - Dirty GPA Logging"); 1528 1529 while (vmx_get_test_stage() == 1) { 1530 vmcall(); 1531 *((u32 *)data_page2) = 0x1; 1532 if (count++ > PML_INDEX) 1533 break; 1534 } 1535 report(vmx_get_test_stage() == 2, "PML Full Event"); 1536 } 1537 1538 static void eptad_main(void) 1539 { 1540 ept_common(); 1541 } 1542 1543 static int eptad_exit_handler(union exit_reason exit_reason) 1544 { 1545 return ept_exit_handler_common(exit_reason, true); 1546 } 1547 1548 static bool invvpid_test(int type, u16 vpid) 1549 { 1550 bool ret, supported; 1551 1552 supported = ept_vpid.val & 1553 (VPID_CAP_INVVPID_ADDR >> INVVPID_ADDR << type); 1554 ret = invvpid(type, vpid, 0); 1555 1556 if (ret == !supported) 1557 return false; 1558 1559 if (!supported) 1560 printf("WARNING: unsupported invvpid passed!\n"); 1561 else 1562 printf("WARNING: invvpid failed!\n"); 1563 1564 return true; 1565 } 1566 1567 static int vpid_init(struct vmcs *vmcs) 1568 { 1569 u32 ctrl_cpu1; 1570 1571 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1572 !(ctrl_cpu_rev[1].clr & CPU_VPID)) { 1573 printf("\tVPID is not supported"); 1574 return VMX_TEST_EXIT; 1575 } 1576 1577 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 1578 ctrl_cpu1 |= CPU_VPID; 1579 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 1580 return VMX_TEST_START; 1581 } 1582 1583 static void vpid_main(void) 1584 { 1585 vmx_set_test_stage(0); 1586 vmcall(); 1587 report(vmx_get_test_stage() == 1, "INVVPID SINGLE ADDRESS"); 1588 vmx_set_test_stage(2); 1589 vmcall(); 1590 report(vmx_get_test_stage() == 3, "INVVPID SINGLE"); 1591 vmx_set_test_stage(4); 1592 vmcall(); 1593 report(vmx_get_test_stage() == 5, "INVVPID ALL"); 1594 } 1595 1596 static int vpid_exit_handler(union exit_reason exit_reason) 1597 { 1598 u64 guest_rip; 1599 u32 insn_len; 1600 1601 guest_rip = vmcs_read(GUEST_RIP); 1602 insn_len = vmcs_read(EXI_INST_LEN); 1603 1604 switch (exit_reason.basic) { 1605 case VMX_VMCALL: 1606 switch(vmx_get_test_stage()) { 1607 case 0: 1608 if (!invvpid_test(INVVPID_ADDR, 1)) 1609 vmx_inc_test_stage(); 1610 break; 1611 case 2: 1612 if (!invvpid_test(INVVPID_CONTEXT_GLOBAL, 1)) 1613 vmx_inc_test_stage(); 1614 break; 1615 case 4: 1616 if (!invvpid_test(INVVPID_ALL, 1)) 1617 vmx_inc_test_stage(); 1618 break; 1619 default: 1620 report(false, "ERROR: unexpected stage, %d", 1621 vmx_get_test_stage()); 1622 print_vmexit_info(exit_reason); 1623 return VMX_TEST_VMEXIT; 1624 } 1625 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1626 return VMX_TEST_RESUME; 1627 default: 1628 report(false, "Unknown exit reason, 0x%x", exit_reason.full); 1629 print_vmexit_info(exit_reason); 1630 } 1631 return VMX_TEST_VMEXIT; 1632 } 1633 1634 #define TIMER_VECTOR 222 1635 1636 static volatile bool timer_fired; 1637 1638 static void timer_isr(isr_regs_t *regs) 1639 { 1640 timer_fired = true; 1641 apic_write(APIC_EOI, 0); 1642 } 1643 1644 static int interrupt_init(struct vmcs *vmcs) 1645 { 1646 msr_bmp_init(); 1647 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1648 handle_irq(TIMER_VECTOR, timer_isr); 1649 return VMX_TEST_START; 1650 } 1651 1652 static void interrupt_main(void) 1653 { 1654 long long start, loops; 1655 1656 vmx_set_test_stage(0); 1657 1658 apic_write(APIC_LVTT, TIMER_VECTOR); 1659 irq_enable(); 1660 1661 apic_write(APIC_TMICT, 1); 1662 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1663 asm volatile ("nop"); 1664 report(timer_fired, "direct interrupt while running guest"); 1665 1666 apic_write(APIC_TMICT, 0); 1667 irq_disable(); 1668 vmcall(); 1669 timer_fired = false; 1670 apic_write(APIC_TMICT, 1); 1671 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1672 asm volatile ("nop"); 1673 report(timer_fired, "intercepted interrupt while running guest"); 1674 1675 irq_enable(); 1676 apic_write(APIC_TMICT, 0); 1677 irq_disable(); 1678 vmcall(); 1679 timer_fired = false; 1680 start = rdtsc(); 1681 apic_write(APIC_TMICT, 1000000); 1682 1683 asm volatile ("sti; hlt"); 1684 1685 report(rdtsc() - start > 1000000 && timer_fired, 1686 "direct interrupt + hlt"); 1687 1688 apic_write(APIC_TMICT, 0); 1689 irq_disable(); 1690 vmcall(); 1691 timer_fired = false; 1692 start = rdtsc(); 1693 apic_write(APIC_TMICT, 1000000); 1694 1695 asm volatile ("sti; hlt"); 1696 1697 report(rdtsc() - start > 10000 && timer_fired, 1698 "intercepted interrupt + hlt"); 1699 1700 apic_write(APIC_TMICT, 0); 1701 irq_disable(); 1702 vmcall(); 1703 timer_fired = false; 1704 start = rdtsc(); 1705 apic_write(APIC_TMICT, 1000000); 1706 1707 irq_enable(); 1708 asm volatile ("nop"); 1709 vmcall(); 1710 1711 report(rdtsc() - start > 10000 && timer_fired, 1712 "direct interrupt + activity state hlt"); 1713 1714 apic_write(APIC_TMICT, 0); 1715 irq_disable(); 1716 vmcall(); 1717 timer_fired = false; 1718 start = rdtsc(); 1719 apic_write(APIC_TMICT, 1000000); 1720 1721 irq_enable(); 1722 asm volatile ("nop"); 1723 vmcall(); 1724 1725 report(rdtsc() - start > 10000 && timer_fired, 1726 "intercepted interrupt + activity state hlt"); 1727 1728 apic_write(APIC_TMICT, 0); 1729 irq_disable(); 1730 vmx_set_test_stage(7); 1731 vmcall(); 1732 timer_fired = false; 1733 apic_write(APIC_TMICT, 1); 1734 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1735 asm volatile ("nop"); 1736 report(timer_fired, 1737 "running a guest with interrupt acknowledgement set"); 1738 1739 apic_write(APIC_TMICT, 0); 1740 irq_enable(); 1741 timer_fired = false; 1742 vmcall(); 1743 report(timer_fired, "Inject an event to a halted guest"); 1744 } 1745 1746 static int interrupt_exit_handler(union exit_reason exit_reason) 1747 { 1748 u64 guest_rip = vmcs_read(GUEST_RIP); 1749 u32 insn_len = vmcs_read(EXI_INST_LEN); 1750 1751 switch (exit_reason.basic) { 1752 case VMX_VMCALL: 1753 switch (vmx_get_test_stage()) { 1754 case 0: 1755 case 2: 1756 case 5: 1757 vmcs_write(PIN_CONTROLS, 1758 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1759 break; 1760 case 7: 1761 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_INTA); 1762 vmcs_write(PIN_CONTROLS, 1763 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1764 break; 1765 case 1: 1766 case 3: 1767 vmcs_write(PIN_CONTROLS, 1768 vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1769 break; 1770 case 4: 1771 case 6: 1772 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1773 break; 1774 1775 case 8: 1776 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1777 vmcs_write(ENT_INTR_INFO, 1778 TIMER_VECTOR | 1779 (VMX_INTR_TYPE_EXT_INTR << INTR_INFO_INTR_TYPE_SHIFT) | 1780 INTR_INFO_VALID_MASK); 1781 break; 1782 } 1783 vmx_inc_test_stage(); 1784 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1785 return VMX_TEST_RESUME; 1786 case VMX_EXTINT: 1787 if (vmcs_read(EXI_CONTROLS) & EXI_INTA) { 1788 int vector = vmcs_read(EXI_INTR_INFO) & 0xff; 1789 handle_external_interrupt(vector); 1790 } else { 1791 irq_enable(); 1792 asm volatile ("nop"); 1793 irq_disable(); 1794 } 1795 if (vmx_get_test_stage() >= 2) 1796 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 1797 return VMX_TEST_RESUME; 1798 default: 1799 report(false, "Unknown exit reason, 0x%x", exit_reason.full); 1800 print_vmexit_info(exit_reason); 1801 } 1802 1803 return VMX_TEST_VMEXIT; 1804 } 1805 1806 static int dbgctls_init(struct vmcs *vmcs) 1807 { 1808 u64 dr7 = 0x402; 1809 u64 zero = 0; 1810 1811 msr_bmp_init(); 1812 asm volatile( 1813 "mov %0,%%dr0\n\t" 1814 "mov %0,%%dr1\n\t" 1815 "mov %0,%%dr2\n\t" 1816 "mov %1,%%dr7\n\t" 1817 : : "r" (zero), "r" (dr7)); 1818 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1819 vmcs_write(GUEST_DR7, 0x404); 1820 vmcs_write(GUEST_DEBUGCTL, 0x2); 1821 1822 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 1823 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_SAVE_DBGCTLS); 1824 1825 return VMX_TEST_START; 1826 } 1827 1828 static void dbgctls_main(void) 1829 { 1830 u64 dr7, debugctl; 1831 1832 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1833 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1834 /* Commented out: KVM does not support DEBUGCTL so far */ 1835 (void)debugctl; 1836 report(dr7 == 0x404, "Load debug controls" /* && debugctl == 0x2 */); 1837 1838 dr7 = 0x408; 1839 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1840 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1841 1842 vmx_set_test_stage(0); 1843 vmcall(); 1844 report(vmx_get_test_stage() == 1, "Save debug controls"); 1845 1846 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS || 1847 ctrl_exit_rev.set & EXI_SAVE_DBGCTLS) { 1848 printf("\tDebug controls are always loaded/saved\n"); 1849 return; 1850 } 1851 vmx_set_test_stage(2); 1852 vmcall(); 1853 1854 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1855 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1856 /* Commented out: KVM does not support DEBUGCTL so far */ 1857 (void)debugctl; 1858 report(dr7 == 0x402, 1859 "Guest=host debug controls" /* && debugctl == 0x1 */); 1860 1861 dr7 = 0x408; 1862 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1863 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1864 1865 vmx_set_test_stage(3); 1866 vmcall(); 1867 report(vmx_get_test_stage() == 4, "Don't save debug controls"); 1868 } 1869 1870 static int dbgctls_exit_handler(union exit_reason exit_reason) 1871 { 1872 u32 insn_len = vmcs_read(EXI_INST_LEN); 1873 u64 guest_rip = vmcs_read(GUEST_RIP); 1874 u64 dr7, debugctl; 1875 1876 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1877 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1878 1879 switch (exit_reason.basic) { 1880 case VMX_VMCALL: 1881 switch (vmx_get_test_stage()) { 1882 case 0: 1883 if (dr7 == 0x400 && debugctl == 0 && 1884 vmcs_read(GUEST_DR7) == 0x408 /* && 1885 Commented out: KVM does not support DEBUGCTL so far 1886 vmcs_read(GUEST_DEBUGCTL) == 0x3 */) 1887 vmx_inc_test_stage(); 1888 break; 1889 case 2: 1890 dr7 = 0x402; 1891 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1892 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1893 vmcs_write(GUEST_DR7, 0x404); 1894 vmcs_write(GUEST_DEBUGCTL, 0x2); 1895 1896 vmcs_write(ENT_CONTROLS, 1897 vmcs_read(ENT_CONTROLS) & ~ENT_LOAD_DBGCTLS); 1898 vmcs_write(EXI_CONTROLS, 1899 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_DBGCTLS); 1900 break; 1901 case 3: 1902 if (dr7 == 0x400 && debugctl == 0 && 1903 vmcs_read(GUEST_DR7) == 0x404 /* && 1904 Commented out: KVM does not support DEBUGCTL so far 1905 vmcs_read(GUEST_DEBUGCTL) == 0x2 */) 1906 vmx_inc_test_stage(); 1907 break; 1908 } 1909 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1910 return VMX_TEST_RESUME; 1911 default: 1912 report(false, "Unknown exit reason, %d", exit_reason.full); 1913 print_vmexit_info(exit_reason); 1914 } 1915 return VMX_TEST_VMEXIT; 1916 } 1917 1918 struct vmx_msr_entry { 1919 u32 index; 1920 u32 reserved; 1921 u64 value; 1922 } __attribute__((packed)); 1923 1924 #define MSR_MAGIC 0x31415926 1925 struct vmx_msr_entry *exit_msr_store, *entry_msr_load, *exit_msr_load; 1926 1927 static int msr_switch_init(struct vmcs *vmcs) 1928 { 1929 msr_bmp_init(); 1930 exit_msr_store = alloc_page(); 1931 exit_msr_load = alloc_page(); 1932 entry_msr_load = alloc_page(); 1933 entry_msr_load[0].index = MSR_KERNEL_GS_BASE; 1934 entry_msr_load[0].value = MSR_MAGIC; 1935 1936 vmx_set_test_stage(1); 1937 vmcs_write(ENT_MSR_LD_CNT, 1); 1938 vmcs_write(ENTER_MSR_LD_ADDR, (u64)entry_msr_load); 1939 vmcs_write(EXI_MSR_ST_CNT, 1); 1940 vmcs_write(EXIT_MSR_ST_ADDR, (u64)exit_msr_store); 1941 vmcs_write(EXI_MSR_LD_CNT, 1); 1942 vmcs_write(EXIT_MSR_LD_ADDR, (u64)exit_msr_load); 1943 return VMX_TEST_START; 1944 } 1945 1946 static void msr_switch_main(void) 1947 { 1948 if (vmx_get_test_stage() == 1) { 1949 report(rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC, 1950 "VM entry MSR load"); 1951 vmx_set_test_stage(2); 1952 wrmsr(MSR_KERNEL_GS_BASE, MSR_MAGIC + 1); 1953 exit_msr_store[0].index = MSR_KERNEL_GS_BASE; 1954 exit_msr_load[0].index = MSR_KERNEL_GS_BASE; 1955 exit_msr_load[0].value = MSR_MAGIC + 2; 1956 } 1957 vmcall(); 1958 } 1959 1960 static int msr_switch_exit_handler(union exit_reason exit_reason) 1961 { 1962 if (exit_reason.basic == VMX_VMCALL && vmx_get_test_stage() == 2) { 1963 report(exit_msr_store[0].value == MSR_MAGIC + 1, 1964 "VM exit MSR store"); 1965 report(rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC + 2, 1966 "VM exit MSR load"); 1967 vmx_set_test_stage(3); 1968 entry_msr_load[0].index = MSR_FS_BASE; 1969 return VMX_TEST_RESUME; 1970 } 1971 printf("ERROR %s: unexpected stage=%u or reason=0x%x\n", 1972 __func__, vmx_get_test_stage(), exit_reason.full); 1973 return VMX_TEST_EXIT; 1974 } 1975 1976 static int msr_switch_entry_failure(struct vmentry_result *result) 1977 { 1978 if (result->vm_fail) { 1979 printf("ERROR %s: VM-Fail on %s\n", __func__, result->instr); 1980 return VMX_TEST_EXIT; 1981 } 1982 1983 if (result->exit_reason.failed_vmentry && 1984 result->exit_reason.basic == VMX_FAIL_MSR && 1985 vmx_get_test_stage() == 3) { 1986 report(vmcs_read(EXI_QUALIFICATION) == 1, 1987 "VM entry MSR load: try to load FS_BASE"); 1988 return VMX_TEST_VMEXIT; 1989 } 1990 printf("ERROR %s: unexpected stage=%u or reason=%x\n", 1991 __func__, vmx_get_test_stage(), result->exit_reason.full); 1992 return VMX_TEST_EXIT; 1993 } 1994 1995 static int vmmcall_init(struct vmcs *vmcs) 1996 { 1997 vmcs_write(EXC_BITMAP, 1 << UD_VECTOR); 1998 return VMX_TEST_START; 1999 } 2000 2001 static void vmmcall_main(void) 2002 { 2003 asm volatile( 2004 "mov $0xABCD, %%rax\n\t" 2005 "vmmcall\n\t" 2006 ::: "rax"); 2007 2008 report(0, "VMMCALL"); 2009 } 2010 2011 static int vmmcall_exit_handler(union exit_reason exit_reason) 2012 { 2013 switch (exit_reason.basic) { 2014 case VMX_VMCALL: 2015 printf("here\n"); 2016 report(0, "VMMCALL triggers #UD"); 2017 break; 2018 case VMX_EXC_NMI: 2019 report((vmcs_read(EXI_INTR_INFO) & 0xff) == UD_VECTOR, 2020 "VMMCALL triggers #UD"); 2021 break; 2022 default: 2023 report(false, "Unknown exit reason, 0x%x", exit_reason.full); 2024 print_vmexit_info(exit_reason); 2025 } 2026 2027 return VMX_TEST_VMEXIT; 2028 } 2029 2030 static int disable_rdtscp_init(struct vmcs *vmcs) 2031 { 2032 u32 ctrl_cpu1; 2033 2034 if (ctrl_cpu_rev[0].clr & CPU_SECONDARY) { 2035 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 2036 ctrl_cpu1 &= ~CPU_RDTSCP; 2037 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 2038 } 2039 2040 return VMX_TEST_START; 2041 } 2042 2043 static void disable_rdtscp_ud_handler(struct ex_regs *regs) 2044 { 2045 switch (vmx_get_test_stage()) { 2046 case 0: 2047 report(true, "RDTSCP triggers #UD"); 2048 vmx_inc_test_stage(); 2049 regs->rip += 3; 2050 break; 2051 case 2: 2052 report(true, "RDPID triggers #UD"); 2053 vmx_inc_test_stage(); 2054 regs->rip += 4; 2055 break; 2056 } 2057 return; 2058 2059 } 2060 2061 static void disable_rdtscp_main(void) 2062 { 2063 /* Test that #UD is properly injected in L2. */ 2064 handle_exception(UD_VECTOR, disable_rdtscp_ud_handler); 2065 2066 vmx_set_test_stage(0); 2067 asm volatile("rdtscp" : : : "eax", "ecx", "edx"); 2068 vmcall(); 2069 asm volatile(".byte 0xf3, 0x0f, 0xc7, 0xf8" : : : "eax"); 2070 2071 handle_exception(UD_VECTOR, 0); 2072 vmcall(); 2073 } 2074 2075 static int disable_rdtscp_exit_handler(union exit_reason exit_reason) 2076 { 2077 switch (exit_reason.basic) { 2078 case VMX_VMCALL: 2079 switch (vmx_get_test_stage()) { 2080 case 0: 2081 report(false, "RDTSCP triggers #UD"); 2082 vmx_inc_test_stage(); 2083 /* fallthrough */ 2084 case 1: 2085 vmx_inc_test_stage(); 2086 vmcs_write(GUEST_RIP, vmcs_read(GUEST_RIP) + 3); 2087 return VMX_TEST_RESUME; 2088 case 2: 2089 report(false, "RDPID triggers #UD"); 2090 break; 2091 } 2092 break; 2093 2094 default: 2095 report(false, "Unknown exit reason, 0x%x", exit_reason.full); 2096 print_vmexit_info(exit_reason); 2097 } 2098 return VMX_TEST_VMEXIT; 2099 } 2100 2101 static int int3_init(struct vmcs *vmcs) 2102 { 2103 vmcs_write(EXC_BITMAP, ~0u); 2104 return VMX_TEST_START; 2105 } 2106 2107 static void int3_guest_main(void) 2108 { 2109 asm volatile ("int3"); 2110 } 2111 2112 static int int3_exit_handler(union exit_reason exit_reason) 2113 { 2114 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2115 2116 report(exit_reason.basic == VMX_EXC_NMI && 2117 (intr_info & INTR_INFO_VALID_MASK) && 2118 (intr_info & INTR_INFO_VECTOR_MASK) == BP_VECTOR && 2119 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2120 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION, 2121 "L1 intercepts #BP"); 2122 2123 return VMX_TEST_VMEXIT; 2124 } 2125 2126 static int into_init(struct vmcs *vmcs) 2127 { 2128 vmcs_write(EXC_BITMAP, ~0u); 2129 return VMX_TEST_START; 2130 } 2131 2132 static void into_guest_main(void) 2133 { 2134 struct far_pointer32 fp = { 2135 .offset = (uintptr_t)&&into, 2136 .selector = KERNEL_CS32, 2137 }; 2138 register uintptr_t rsp asm("rsp"); 2139 2140 if (fp.offset != (uintptr_t)&&into) { 2141 printf("Code address too high.\n"); 2142 return; 2143 } 2144 if ((u32)rsp != rsp) { 2145 printf("Stack address too high.\n"); 2146 return; 2147 } 2148 2149 asm goto ("lcall *%0" : : "m" (fp) : "rax" : into); 2150 return; 2151 into: 2152 asm volatile (".code32;" 2153 "movl $0x7fffffff, %eax;" 2154 "addl %eax, %eax;" 2155 "into;" 2156 "lret;" 2157 ".code64"); 2158 __builtin_unreachable(); 2159 } 2160 2161 static int into_exit_handler(union exit_reason exit_reason) 2162 { 2163 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2164 2165 report(exit_reason.basic == VMX_EXC_NMI && 2166 (intr_info & INTR_INFO_VALID_MASK) && 2167 (intr_info & INTR_INFO_VECTOR_MASK) == OF_VECTOR && 2168 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2169 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION, 2170 "L1 intercepts #OF"); 2171 2172 return VMX_TEST_VMEXIT; 2173 } 2174 2175 static void exit_monitor_from_l2_main(void) 2176 { 2177 printf("Calling exit(0) from l2...\n"); 2178 exit(0); 2179 } 2180 2181 static int exit_monitor_from_l2_handler(union exit_reason exit_reason) 2182 { 2183 report(false, "The guest should have killed the VMM"); 2184 return VMX_TEST_EXIT; 2185 } 2186 2187 static void assert_exit_reason(u64 expected) 2188 { 2189 u64 actual = vmcs_read(EXI_REASON); 2190 2191 TEST_ASSERT_EQ_MSG(expected, actual, "Expected %s, got %s.", 2192 exit_reason_description(expected), 2193 exit_reason_description(actual)); 2194 } 2195 2196 static void skip_exit_insn(void) 2197 { 2198 u64 guest_rip = vmcs_read(GUEST_RIP); 2199 u32 insn_len = vmcs_read(EXI_INST_LEN); 2200 vmcs_write(GUEST_RIP, guest_rip + insn_len); 2201 } 2202 2203 static void skip_exit_vmcall(void) 2204 { 2205 assert_exit_reason(VMX_VMCALL); 2206 skip_exit_insn(); 2207 } 2208 2209 static void v2_null_test_guest(void) 2210 { 2211 } 2212 2213 static void v2_null_test(void) 2214 { 2215 test_set_guest(v2_null_test_guest); 2216 enter_guest(); 2217 report(1, __func__); 2218 } 2219 2220 static void v2_multiple_entries_test_guest(void) 2221 { 2222 vmx_set_test_stage(1); 2223 vmcall(); 2224 vmx_set_test_stage(2); 2225 } 2226 2227 static void v2_multiple_entries_test(void) 2228 { 2229 test_set_guest(v2_multiple_entries_test_guest); 2230 enter_guest(); 2231 TEST_ASSERT_EQ(vmx_get_test_stage(), 1); 2232 skip_exit_vmcall(); 2233 enter_guest(); 2234 TEST_ASSERT_EQ(vmx_get_test_stage(), 2); 2235 report(1, __func__); 2236 } 2237 2238 static int fixture_test_data = 1; 2239 2240 static void fixture_test_teardown(void *data) 2241 { 2242 *((int *) data) = 1; 2243 } 2244 2245 static void fixture_test_guest(void) 2246 { 2247 fixture_test_data++; 2248 } 2249 2250 2251 static void fixture_test_setup(void) 2252 { 2253 TEST_ASSERT_EQ_MSG(1, fixture_test_data, 2254 "fixture_test_teardown didn't run?!"); 2255 fixture_test_data = 2; 2256 test_add_teardown(fixture_test_teardown, &fixture_test_data); 2257 test_set_guest(fixture_test_guest); 2258 } 2259 2260 static void fixture_test_case1(void) 2261 { 2262 fixture_test_setup(); 2263 TEST_ASSERT_EQ(2, fixture_test_data); 2264 enter_guest(); 2265 TEST_ASSERT_EQ(3, fixture_test_data); 2266 report(1, __func__); 2267 } 2268 2269 static void fixture_test_case2(void) 2270 { 2271 fixture_test_setup(); 2272 TEST_ASSERT_EQ(2, fixture_test_data); 2273 enter_guest(); 2274 TEST_ASSERT_EQ(3, fixture_test_data); 2275 report(1, __func__); 2276 } 2277 2278 enum ept_access_op { 2279 OP_READ, 2280 OP_WRITE, 2281 OP_EXEC, 2282 OP_FLUSH_TLB, 2283 OP_EXIT, 2284 }; 2285 2286 static struct ept_access_test_data { 2287 unsigned long gpa; 2288 unsigned long *gva; 2289 unsigned long hpa; 2290 unsigned long *hva; 2291 enum ept_access_op op; 2292 } ept_access_test_data; 2293 2294 extern unsigned char ret42_start; 2295 extern unsigned char ret42_end; 2296 2297 /* Returns 42. */ 2298 asm( 2299 ".align 64\n" 2300 "ret42_start:\n" 2301 "mov $42, %eax\n" 2302 "ret\n" 2303 "ret42_end:\n" 2304 ); 2305 2306 static void 2307 diagnose_ept_violation_qual(u64 expected, u64 actual) 2308 { 2309 2310 #define DIAGNOSE(flag) \ 2311 do { \ 2312 if ((expected & flag) != (actual & flag)) \ 2313 printf(#flag " %sexpected\n", \ 2314 (expected & flag) ? "" : "un"); \ 2315 } while (0) 2316 2317 DIAGNOSE(EPT_VLT_RD); 2318 DIAGNOSE(EPT_VLT_WR); 2319 DIAGNOSE(EPT_VLT_FETCH); 2320 DIAGNOSE(EPT_VLT_PERM_RD); 2321 DIAGNOSE(EPT_VLT_PERM_WR); 2322 DIAGNOSE(EPT_VLT_PERM_EX); 2323 DIAGNOSE(EPT_VLT_LADDR_VLD); 2324 DIAGNOSE(EPT_VLT_PADDR); 2325 2326 #undef DIAGNOSE 2327 } 2328 2329 static void do_ept_access_op(enum ept_access_op op) 2330 { 2331 ept_access_test_data.op = op; 2332 enter_guest(); 2333 } 2334 2335 /* 2336 * Force the guest to flush its TLB (i.e., flush gva -> gpa mappings). Only 2337 * needed by tests that modify guest PTEs. 2338 */ 2339 static void ept_access_test_guest_flush_tlb(void) 2340 { 2341 do_ept_access_op(OP_FLUSH_TLB); 2342 skip_exit_vmcall(); 2343 } 2344 2345 /* 2346 * Modifies the EPT entry at @level in the mapping of @gpa. First clears the 2347 * bits in @clear then sets the bits in @set. @mkhuge transforms the entry into 2348 * a huge page. 2349 */ 2350 static unsigned long ept_twiddle(unsigned long gpa, bool mkhuge, int level, 2351 unsigned long clear, unsigned long set) 2352 { 2353 struct ept_access_test_data *data = &ept_access_test_data; 2354 unsigned long orig_pte; 2355 unsigned long pte; 2356 2357 /* Screw with the mapping at the requested level. */ 2358 TEST_ASSERT(get_ept_pte(pml4, gpa, level, &orig_pte)); 2359 pte = orig_pte; 2360 if (mkhuge) 2361 pte = (orig_pte & ~EPT_ADDR_MASK) | data->hpa | EPT_LARGE_PAGE; 2362 else 2363 pte = orig_pte; 2364 pte = (pte & ~clear) | set; 2365 set_ept_pte(pml4, gpa, level, pte); 2366 ept_sync(INVEPT_SINGLE, eptp); 2367 2368 return orig_pte; 2369 } 2370 2371 static void ept_untwiddle(unsigned long gpa, int level, unsigned long orig_pte) 2372 { 2373 set_ept_pte(pml4, gpa, level, orig_pte); 2374 ept_sync(INVEPT_SINGLE, eptp); 2375 } 2376 2377 static void do_ept_violation(bool leaf, enum ept_access_op op, 2378 u64 expected_qual, u64 expected_paddr) 2379 { 2380 u64 qual; 2381 2382 /* Try the access and observe the violation. */ 2383 do_ept_access_op(op); 2384 2385 assert_exit_reason(VMX_EPT_VIOLATION); 2386 2387 qual = vmcs_read(EXI_QUALIFICATION); 2388 2389 /* Mask undefined bits (which may later be defined in certain cases). */ 2390 qual &= ~(EPT_VLT_GUEST_USER | EPT_VLT_GUEST_RW | EPT_VLT_GUEST_EX | 2391 EPT_VLT_PERM_USER_EX); 2392 2393 diagnose_ept_violation_qual(expected_qual, qual); 2394 TEST_EXPECT_EQ(expected_qual, qual); 2395 2396 #if 0 2397 /* Disable for now otherwise every test will fail */ 2398 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2399 (unsigned long) ( 2400 op == OP_EXEC ? data->gva + 1 : data->gva)); 2401 #endif 2402 /* 2403 * TODO: tests that probe expected_paddr in pages other than the one at 2404 * the beginning of the 1g region. 2405 */ 2406 TEST_EXPECT_EQ(vmcs_read(INFO_PHYS_ADDR), expected_paddr); 2407 } 2408 2409 static void 2410 ept_violation_at_level_mkhuge(bool mkhuge, int level, unsigned long clear, 2411 unsigned long set, enum ept_access_op op, 2412 u64 expected_qual) 2413 { 2414 struct ept_access_test_data *data = &ept_access_test_data; 2415 unsigned long orig_pte; 2416 2417 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2418 2419 do_ept_violation(level == 1 || mkhuge, op, expected_qual, 2420 op == OP_EXEC ? data->gpa + sizeof(unsigned long) : 2421 data->gpa); 2422 2423 /* Fix the violation and resume the op loop. */ 2424 ept_untwiddle(data->gpa, level, orig_pte); 2425 enter_guest(); 2426 skip_exit_vmcall(); 2427 } 2428 2429 static void 2430 ept_violation_at_level(int level, unsigned long clear, unsigned long set, 2431 enum ept_access_op op, u64 expected_qual) 2432 { 2433 ept_violation_at_level_mkhuge(false, level, clear, set, op, 2434 expected_qual); 2435 if (ept_huge_pages_supported(level)) 2436 ept_violation_at_level_mkhuge(true, level, clear, set, op, 2437 expected_qual); 2438 } 2439 2440 static void ept_violation(unsigned long clear, unsigned long set, 2441 enum ept_access_op op, u64 expected_qual) 2442 { 2443 ept_violation_at_level(1, clear, set, op, expected_qual); 2444 ept_violation_at_level(2, clear, set, op, expected_qual); 2445 ept_violation_at_level(3, clear, set, op, expected_qual); 2446 ept_violation_at_level(4, clear, set, op, expected_qual); 2447 } 2448 2449 static void ept_access_violation(unsigned long access, enum ept_access_op op, 2450 u64 expected_qual) 2451 { 2452 ept_violation(EPT_PRESENT, access, op, 2453 expected_qual | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2454 } 2455 2456 /* 2457 * For translations that don't involve a GVA, that is physical address (paddr) 2458 * accesses, EPT violations don't set the flag EPT_VLT_PADDR. For a typical 2459 * guest memory access, the hardware does GVA -> GPA -> HPA. However, certain 2460 * translations don't involve GVAs, such as when the hardware does the guest 2461 * page table walk. For example, in translating GVA_1 -> GPA_1, the guest MMU 2462 * might try to set an A bit on a guest PTE. If the GPA_2 that the PTE resides 2463 * on isn't present in the EPT, then the EPT violation will be for GPA_2 and 2464 * the EPT_VLT_PADDR bit will be clear in the exit qualification. 2465 * 2466 * Note that paddr violations can also be triggered by loading PAE page tables 2467 * with wonky addresses. We don't test that yet. 2468 * 2469 * This function modifies the EPT entry that maps the GPA that the guest page 2470 * table entry mapping ept_access_test_data.gva resides on. 2471 * 2472 * @ept_access EPT permissions to set. Other permissions are cleared. 2473 * 2474 * @pte_ad Set the A/D bits on the guest PTE accordingly. 2475 * 2476 * @op Guest operation to perform with 2477 * ept_access_test_data.gva. 2478 * 2479 * @expect_violation 2480 * Is a violation expected during the paddr access? 2481 * 2482 * @expected_qual Expected qualification for the EPT violation. 2483 * EPT_VLT_PADDR should be clear. 2484 */ 2485 static void ept_access_paddr(unsigned long ept_access, unsigned long pte_ad, 2486 enum ept_access_op op, bool expect_violation, 2487 u64 expected_qual) 2488 { 2489 struct ept_access_test_data *data = &ept_access_test_data; 2490 unsigned long *ptep; 2491 unsigned long gpa; 2492 unsigned long orig_epte; 2493 unsigned long epte; 2494 int i; 2495 2496 /* Modify the guest PTE mapping data->gva according to @pte_ad. */ 2497 ptep = get_pte_level(current_page_table(), data->gva, /*level=*/1); 2498 TEST_ASSERT(ptep); 2499 TEST_ASSERT_EQ(*ptep & PT_ADDR_MASK, data->gpa); 2500 *ptep = (*ptep & ~PT_AD_MASK) | pte_ad; 2501 ept_access_test_guest_flush_tlb(); 2502 2503 /* 2504 * Now modify the access bits on the EPT entry for the GPA that the 2505 * guest PTE resides on. Note that by modifying a single EPT entry, 2506 * we're potentially affecting 512 guest PTEs. However, we've carefully 2507 * constructed our test such that those other 511 PTEs aren't used by 2508 * the guest: data->gva is at the beginning of a 1G huge page, thus the 2509 * PTE we're modifying is at the beginning of a 4K page and the 2510 * following 511 entires are also under our control (and not touched by 2511 * the guest). 2512 */ 2513 gpa = virt_to_phys(ptep); 2514 TEST_ASSERT_EQ(gpa & ~PAGE_MASK, 0); 2515 /* 2516 * Make sure the guest page table page is mapped with a 4K EPT entry, 2517 * otherwise our level=1 twiddling below will fail. We use the 2518 * identity map (gpa = gpa) since page tables are shared with the host. 2519 */ 2520 install_ept(pml4, gpa, gpa, EPT_PRESENT); 2521 orig_epte = ept_twiddle(gpa, /*mkhuge=*/0, /*level=*/1, 2522 /*clear=*/EPT_PRESENT, /*set=*/ept_access); 2523 2524 if (expect_violation) { 2525 do_ept_violation(/*leaf=*/true, op, 2526 expected_qual | EPT_VLT_LADDR_VLD, gpa); 2527 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2528 do_ept_access_op(op); 2529 } else { 2530 do_ept_access_op(op); 2531 if (ept_ad_enabled()) { 2532 for (i = EPT_PAGE_LEVEL; i > 0; i--) { 2533 TEST_ASSERT(get_ept_pte(pml4, gpa, i, &epte)); 2534 TEST_ASSERT(epte & EPT_ACCESS_FLAG); 2535 if (i == 1) 2536 TEST_ASSERT(epte & EPT_DIRTY_FLAG); 2537 else 2538 TEST_ASSERT_EQ(epte & EPT_DIRTY_FLAG, 0); 2539 } 2540 } 2541 2542 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2543 } 2544 2545 TEST_ASSERT(*ptep & PT_ACCESSED_MASK); 2546 if ((pte_ad & PT_DIRTY_MASK) || op == OP_WRITE) 2547 TEST_ASSERT(*ptep & PT_DIRTY_MASK); 2548 2549 skip_exit_vmcall(); 2550 } 2551 2552 static void ept_access_allowed_paddr(unsigned long ept_access, 2553 unsigned long pte_ad, 2554 enum ept_access_op op) 2555 { 2556 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/false, 2557 /*expected_qual=*/-1); 2558 } 2559 2560 static void ept_access_violation_paddr(unsigned long ept_access, 2561 unsigned long pte_ad, 2562 enum ept_access_op op, 2563 u64 expected_qual) 2564 { 2565 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/true, 2566 expected_qual); 2567 } 2568 2569 2570 static void ept_allowed_at_level_mkhuge(bool mkhuge, int level, 2571 unsigned long clear, 2572 unsigned long set, 2573 enum ept_access_op op) 2574 { 2575 struct ept_access_test_data *data = &ept_access_test_data; 2576 unsigned long orig_pte; 2577 2578 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2579 2580 /* No violation. Should proceed to vmcall. */ 2581 do_ept_access_op(op); 2582 skip_exit_vmcall(); 2583 2584 ept_untwiddle(data->gpa, level, orig_pte); 2585 } 2586 2587 static void ept_allowed_at_level(int level, unsigned long clear, 2588 unsigned long set, enum ept_access_op op) 2589 { 2590 ept_allowed_at_level_mkhuge(false, level, clear, set, op); 2591 if (ept_huge_pages_supported(level)) 2592 ept_allowed_at_level_mkhuge(true, level, clear, set, op); 2593 } 2594 2595 static void ept_allowed(unsigned long clear, unsigned long set, 2596 enum ept_access_op op) 2597 { 2598 ept_allowed_at_level(1, clear, set, op); 2599 ept_allowed_at_level(2, clear, set, op); 2600 ept_allowed_at_level(3, clear, set, op); 2601 ept_allowed_at_level(4, clear, set, op); 2602 } 2603 2604 static void ept_ignored_bit(int bit) 2605 { 2606 /* Set the bit. */ 2607 ept_allowed(0, 1ul << bit, OP_READ); 2608 ept_allowed(0, 1ul << bit, OP_WRITE); 2609 ept_allowed(0, 1ul << bit, OP_EXEC); 2610 2611 /* Clear the bit. */ 2612 ept_allowed(1ul << bit, 0, OP_READ); 2613 ept_allowed(1ul << bit, 0, OP_WRITE); 2614 ept_allowed(1ul << bit, 0, OP_EXEC); 2615 } 2616 2617 static void ept_access_allowed(unsigned long access, enum ept_access_op op) 2618 { 2619 ept_allowed(EPT_PRESENT, access, op); 2620 } 2621 2622 2623 static void ept_misconfig_at_level_mkhuge_op(bool mkhuge, int level, 2624 unsigned long clear, 2625 unsigned long set, 2626 enum ept_access_op op) 2627 { 2628 struct ept_access_test_data *data = &ept_access_test_data; 2629 unsigned long orig_pte; 2630 2631 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2632 2633 do_ept_access_op(op); 2634 assert_exit_reason(VMX_EPT_MISCONFIG); 2635 2636 /* Intel 27.2.1, "For all other VM exits, this field is cleared." */ 2637 #if 0 2638 /* broken: */ 2639 TEST_EXPECT_EQ_MSG(vmcs_read(EXI_QUALIFICATION), 0); 2640 #endif 2641 #if 0 2642 /* 2643 * broken: 2644 * According to description of exit qual for EPT violation, 2645 * EPT_VLT_LADDR_VLD indicates if GUEST_LINEAR_ADDRESS is valid. 2646 * However, I can't find anything that says GUEST_LINEAR_ADDRESS ought 2647 * to be set for msiconfig. 2648 */ 2649 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2650 (unsigned long) ( 2651 op == OP_EXEC ? data->gva + 1 : data->gva)); 2652 #endif 2653 2654 /* Fix the violation and resume the op loop. */ 2655 ept_untwiddle(data->gpa, level, orig_pte); 2656 enter_guest(); 2657 skip_exit_vmcall(); 2658 } 2659 2660 static void ept_misconfig_at_level_mkhuge(bool mkhuge, int level, 2661 unsigned long clear, 2662 unsigned long set) 2663 { 2664 /* The op shouldn't matter (read, write, exec), so try them all! */ 2665 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_READ); 2666 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_WRITE); 2667 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_EXEC); 2668 } 2669 2670 static void ept_misconfig_at_level(int level, unsigned long clear, 2671 unsigned long set) 2672 { 2673 ept_misconfig_at_level_mkhuge(false, level, clear, set); 2674 if (ept_huge_pages_supported(level)) 2675 ept_misconfig_at_level_mkhuge(true, level, clear, set); 2676 } 2677 2678 static void ept_misconfig(unsigned long clear, unsigned long set) 2679 { 2680 ept_misconfig_at_level(1, clear, set); 2681 ept_misconfig_at_level(2, clear, set); 2682 ept_misconfig_at_level(3, clear, set); 2683 ept_misconfig_at_level(4, clear, set); 2684 } 2685 2686 static void ept_access_misconfig(unsigned long access) 2687 { 2688 ept_misconfig(EPT_PRESENT, access); 2689 } 2690 2691 static void ept_reserved_bit_at_level_nohuge(int level, int bit) 2692 { 2693 /* Setting the bit causes a misconfig. */ 2694 ept_misconfig_at_level_mkhuge(false, level, 0, 1ul << bit); 2695 2696 /* Making the entry non-present turns reserved bits into ignored. */ 2697 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2698 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2699 } 2700 2701 static void ept_reserved_bit_at_level_huge(int level, int bit) 2702 { 2703 /* Setting the bit causes a misconfig. */ 2704 ept_misconfig_at_level_mkhuge(true, level, 0, 1ul << bit); 2705 2706 /* Making the entry non-present turns reserved bits into ignored. */ 2707 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2708 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2709 } 2710 2711 static void ept_reserved_bit_at_level(int level, int bit) 2712 { 2713 /* Setting the bit causes a misconfig. */ 2714 ept_misconfig_at_level(level, 0, 1ul << bit); 2715 2716 /* Making the entry non-present turns reserved bits into ignored. */ 2717 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2718 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2719 } 2720 2721 static void ept_reserved_bit(int bit) 2722 { 2723 ept_reserved_bit_at_level(1, bit); 2724 ept_reserved_bit_at_level(2, bit); 2725 ept_reserved_bit_at_level(3, bit); 2726 ept_reserved_bit_at_level(4, bit); 2727 } 2728 2729 #define PAGE_2M_ORDER 9 2730 #define PAGE_1G_ORDER 18 2731 2732 static void *get_1g_page(void) 2733 { 2734 static void *alloc; 2735 2736 if (!alloc) 2737 alloc = alloc_pages(PAGE_1G_ORDER); 2738 return alloc; 2739 } 2740 2741 static void ept_access_test_teardown(void *unused) 2742 { 2743 /* Exit the guest cleanly. */ 2744 do_ept_access_op(OP_EXIT); 2745 } 2746 2747 static void ept_access_test_guest(void) 2748 { 2749 struct ept_access_test_data *data = &ept_access_test_data; 2750 int (*code)(void) = (int (*)(void)) &data->gva[1]; 2751 2752 while (true) { 2753 switch (data->op) { 2754 case OP_READ: 2755 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_1); 2756 break; 2757 case OP_WRITE: 2758 *data->gva = MAGIC_VAL_2; 2759 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_2); 2760 *data->gva = MAGIC_VAL_1; 2761 break; 2762 case OP_EXEC: 2763 TEST_ASSERT_EQ(42, code()); 2764 break; 2765 case OP_FLUSH_TLB: 2766 write_cr3(read_cr3()); 2767 break; 2768 case OP_EXIT: 2769 return; 2770 default: 2771 TEST_ASSERT_MSG(false, "Unknown op %d", data->op); 2772 } 2773 vmcall(); 2774 } 2775 } 2776 2777 static void ept_access_test_setup(void) 2778 { 2779 struct ept_access_test_data *data = &ept_access_test_data; 2780 unsigned long npages = 1ul << PAGE_1G_ORDER; 2781 unsigned long size = npages * PAGE_SIZE; 2782 unsigned long *page_table = current_page_table(); 2783 unsigned long pte; 2784 2785 if (setup_ept(false)) 2786 test_skip("EPT not supported"); 2787 2788 /* We use data->gpa = 1 << 39 so that test data has a separate pml4 entry */ 2789 if (cpuid_maxphyaddr() < 40) 2790 test_skip("Test needs MAXPHYADDR >= 40"); 2791 2792 test_set_guest(ept_access_test_guest); 2793 test_add_teardown(ept_access_test_teardown, NULL); 2794 2795 data->hva = get_1g_page(); 2796 TEST_ASSERT(data->hva); 2797 data->hpa = virt_to_phys(data->hva); 2798 2799 data->gpa = 1ul << 39; 2800 data->gva = (void *) ALIGN((unsigned long) alloc_vpages(npages * 2), 2801 size); 2802 TEST_ASSERT(!any_present_pages(page_table, data->gva, size)); 2803 install_pages(page_table, data->gpa, size, data->gva); 2804 2805 /* 2806 * Make sure nothing's mapped here so the tests that screw with the 2807 * pml4 entry don't inadvertently break something. 2808 */ 2809 TEST_ASSERT(get_ept_pte(pml4, data->gpa, 4, &pte) && pte == 0); 2810 TEST_ASSERT(get_ept_pte(pml4, data->gpa + size - 1, 4, &pte) && pte == 0); 2811 install_ept(pml4, data->hpa, data->gpa, EPT_PRESENT); 2812 2813 data->hva[0] = MAGIC_VAL_1; 2814 memcpy(&data->hva[1], &ret42_start, &ret42_end - &ret42_start); 2815 } 2816 2817 static void ept_access_test_not_present(void) 2818 { 2819 ept_access_test_setup(); 2820 /* --- */ 2821 ept_access_violation(0, OP_READ, EPT_VLT_RD); 2822 ept_access_violation(0, OP_WRITE, EPT_VLT_WR); 2823 ept_access_violation(0, OP_EXEC, EPT_VLT_FETCH); 2824 } 2825 2826 static void ept_access_test_read_only(void) 2827 { 2828 ept_access_test_setup(); 2829 2830 /* r-- */ 2831 ept_access_allowed(EPT_RA, OP_READ); 2832 ept_access_violation(EPT_RA, OP_WRITE, EPT_VLT_WR | EPT_VLT_PERM_RD); 2833 ept_access_violation(EPT_RA, OP_EXEC, EPT_VLT_FETCH | EPT_VLT_PERM_RD); 2834 } 2835 2836 static void ept_access_test_write_only(void) 2837 { 2838 ept_access_test_setup(); 2839 /* -w- */ 2840 ept_access_misconfig(EPT_WA); 2841 } 2842 2843 static void ept_access_test_read_write(void) 2844 { 2845 ept_access_test_setup(); 2846 /* rw- */ 2847 ept_access_allowed(EPT_RA | EPT_WA, OP_READ); 2848 ept_access_allowed(EPT_RA | EPT_WA, OP_WRITE); 2849 ept_access_violation(EPT_RA | EPT_WA, OP_EXEC, 2850 EPT_VLT_FETCH | EPT_VLT_PERM_RD | EPT_VLT_PERM_WR); 2851 } 2852 2853 2854 static void ept_access_test_execute_only(void) 2855 { 2856 ept_access_test_setup(); 2857 /* --x */ 2858 if (ept_execute_only_supported()) { 2859 ept_access_violation(EPT_EA, OP_READ, 2860 EPT_VLT_RD | EPT_VLT_PERM_EX); 2861 ept_access_violation(EPT_EA, OP_WRITE, 2862 EPT_VLT_WR | EPT_VLT_PERM_EX); 2863 ept_access_allowed(EPT_EA, OP_EXEC); 2864 } else { 2865 ept_access_misconfig(EPT_EA); 2866 } 2867 } 2868 2869 static void ept_access_test_read_execute(void) 2870 { 2871 ept_access_test_setup(); 2872 /* r-x */ 2873 ept_access_allowed(EPT_RA | EPT_EA, OP_READ); 2874 ept_access_violation(EPT_RA | EPT_EA, OP_WRITE, 2875 EPT_VLT_WR | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX); 2876 ept_access_allowed(EPT_RA | EPT_EA, OP_EXEC); 2877 } 2878 2879 static void ept_access_test_write_execute(void) 2880 { 2881 ept_access_test_setup(); 2882 /* -wx */ 2883 ept_access_misconfig(EPT_WA | EPT_EA); 2884 } 2885 2886 static void ept_access_test_read_write_execute(void) 2887 { 2888 ept_access_test_setup(); 2889 /* rwx */ 2890 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_READ); 2891 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_WRITE); 2892 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_EXEC); 2893 } 2894 2895 static void ept_access_test_reserved_bits(void) 2896 { 2897 int i; 2898 int maxphyaddr; 2899 2900 ept_access_test_setup(); 2901 2902 /* Reserved bits above maxphyaddr. */ 2903 maxphyaddr = cpuid_maxphyaddr(); 2904 for (i = maxphyaddr; i <= 51; i++) { 2905 report_prefix_pushf("reserved_bit=%d", i); 2906 ept_reserved_bit(i); 2907 report_prefix_pop(); 2908 } 2909 2910 /* Level-specific reserved bits. */ 2911 ept_reserved_bit_at_level_nohuge(2, 3); 2912 ept_reserved_bit_at_level_nohuge(2, 4); 2913 ept_reserved_bit_at_level_nohuge(2, 5); 2914 ept_reserved_bit_at_level_nohuge(2, 6); 2915 /* 2M alignment. */ 2916 for (i = 12; i < 20; i++) { 2917 report_prefix_pushf("reserved_bit=%d", i); 2918 ept_reserved_bit_at_level_huge(2, i); 2919 report_prefix_pop(); 2920 } 2921 ept_reserved_bit_at_level_nohuge(3, 3); 2922 ept_reserved_bit_at_level_nohuge(3, 4); 2923 ept_reserved_bit_at_level_nohuge(3, 5); 2924 ept_reserved_bit_at_level_nohuge(3, 6); 2925 /* 1G alignment. */ 2926 for (i = 12; i < 29; i++) { 2927 report_prefix_pushf("reserved_bit=%d", i); 2928 ept_reserved_bit_at_level_huge(3, i); 2929 report_prefix_pop(); 2930 } 2931 ept_reserved_bit_at_level(4, 3); 2932 ept_reserved_bit_at_level(4, 4); 2933 ept_reserved_bit_at_level(4, 5); 2934 ept_reserved_bit_at_level(4, 6); 2935 ept_reserved_bit_at_level(4, 7); 2936 } 2937 2938 static void ept_access_test_ignored_bits(void) 2939 { 2940 ept_access_test_setup(); 2941 /* 2942 * Bits ignored at every level. Bits 8 and 9 (A and D) are ignored as 2943 * far as translation is concerned even if AD bits are enabled in the 2944 * EPTP. Bit 63 is ignored because "EPT-violation #VE" VM-execution 2945 * control is 0. 2946 */ 2947 ept_ignored_bit(8); 2948 ept_ignored_bit(9); 2949 ept_ignored_bit(10); 2950 ept_ignored_bit(11); 2951 ept_ignored_bit(52); 2952 ept_ignored_bit(53); 2953 ept_ignored_bit(54); 2954 ept_ignored_bit(55); 2955 ept_ignored_bit(56); 2956 ept_ignored_bit(57); 2957 ept_ignored_bit(58); 2958 ept_ignored_bit(59); 2959 ept_ignored_bit(60); 2960 ept_ignored_bit(61); 2961 ept_ignored_bit(62); 2962 ept_ignored_bit(63); 2963 } 2964 2965 static void ept_access_test_paddr_not_present_ad_disabled(void) 2966 { 2967 ept_access_test_setup(); 2968 ept_disable_ad_bits(); 2969 2970 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, EPT_VLT_RD); 2971 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, EPT_VLT_RD); 2972 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, EPT_VLT_RD); 2973 } 2974 2975 static void ept_access_test_paddr_not_present_ad_enabled(void) 2976 { 2977 u64 qual = EPT_VLT_RD | EPT_VLT_WR; 2978 2979 ept_access_test_setup(); 2980 ept_enable_ad_bits_or_skip_test(); 2981 2982 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, qual); 2983 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, qual); 2984 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, qual); 2985 } 2986 2987 static void ept_access_test_paddr_read_only_ad_disabled(void) 2988 { 2989 /* 2990 * When EPT AD bits are disabled, all accesses to guest paging 2991 * structures are reported separately as a read and (after 2992 * translation of the GPA to host physical address) a read+write 2993 * if the A/D bits have to be set. 2994 */ 2995 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 2996 2997 ept_access_test_setup(); 2998 ept_disable_ad_bits(); 2999 3000 /* Can't update A bit, so all accesses fail. */ 3001 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 3002 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 3003 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 3004 /* AD bits disabled, so only writes try to update the D bit. */ 3005 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ); 3006 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 3007 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC); 3008 /* Both A and D already set, so read-only is OK. */ 3009 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_READ); 3010 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_WRITE); 3011 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_EXEC); 3012 } 3013 3014 static void ept_access_test_paddr_read_only_ad_enabled(void) 3015 { 3016 /* 3017 * When EPT AD bits are enabled, all accesses to guest paging 3018 * structures are considered writes as far as EPT translation 3019 * is concerned. 3020 */ 3021 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 3022 3023 ept_access_test_setup(); 3024 ept_enable_ad_bits_or_skip_test(); 3025 3026 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 3027 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 3028 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 3029 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ, qual); 3030 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 3031 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC, qual); 3032 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_READ, qual); 3033 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_WRITE, qual); 3034 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_EXEC, qual); 3035 } 3036 3037 static void ept_access_test_paddr_read_write(void) 3038 { 3039 ept_access_test_setup(); 3040 /* Read-write access to paging structure. */ 3041 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_READ); 3042 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_WRITE); 3043 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_EXEC); 3044 } 3045 3046 static void ept_access_test_paddr_read_write_execute(void) 3047 { 3048 ept_access_test_setup(); 3049 /* RWX access to paging structure. */ 3050 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_READ); 3051 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_WRITE); 3052 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_EXEC); 3053 } 3054 3055 static void ept_access_test_paddr_read_execute_ad_disabled(void) 3056 { 3057 /* 3058 * When EPT AD bits are disabled, all accesses to guest paging 3059 * structures are reported separately as a read and (after 3060 * translation of the GPA to host physical address) a read+write 3061 * if the A/D bits have to be set. 3062 */ 3063 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3064 3065 ept_access_test_setup(); 3066 ept_disable_ad_bits(); 3067 3068 /* Can't update A bit, so all accesses fail. */ 3069 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3070 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3071 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3072 /* AD bits disabled, so only writes try to update the D bit. */ 3073 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ); 3074 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3075 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC); 3076 /* Both A and D already set, so read-only is OK. */ 3077 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ); 3078 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE); 3079 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC); 3080 } 3081 3082 static void ept_access_test_paddr_read_execute_ad_enabled(void) 3083 { 3084 /* 3085 * When EPT AD bits are enabled, all accesses to guest paging 3086 * structures are considered writes as far as EPT translation 3087 * is concerned. 3088 */ 3089 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3090 3091 ept_access_test_setup(); 3092 ept_enable_ad_bits_or_skip_test(); 3093 3094 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3095 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3096 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3097 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ, qual); 3098 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3099 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC, qual); 3100 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ, qual); 3101 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE, qual); 3102 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC, qual); 3103 } 3104 3105 static void ept_access_test_paddr_not_present_page_fault(void) 3106 { 3107 ept_access_test_setup(); 3108 /* 3109 * TODO: test no EPT violation as long as guest PF occurs. e.g., GPA is 3110 * page is read-only in EPT but GVA is also mapped read only in PT. 3111 * Thus guest page fault before host takes EPT violation for trying to 3112 * update A bit. 3113 */ 3114 } 3115 3116 static void ept_access_test_force_2m_page(void) 3117 { 3118 ept_access_test_setup(); 3119 3120 TEST_ASSERT_EQ(ept_2m_supported(), true); 3121 ept_allowed_at_level_mkhuge(true, 2, 0, 0, OP_READ); 3122 ept_violation_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_RA, OP_WRITE, 3123 EPT_VLT_WR | EPT_VLT_PERM_RD | 3124 EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 3125 ept_misconfig_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_WA); 3126 } 3127 3128 static bool invvpid_valid(u64 type, u64 vpid, u64 gla) 3129 { 3130 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3131 3132 TEST_ASSERT(msr & VPID_CAP_INVVPID); 3133 3134 if (type < INVVPID_ADDR || type > INVVPID_CONTEXT_LOCAL) 3135 return false; 3136 3137 if (!(msr & (1ull << (type + VPID_CAP_INVVPID_TYPES_SHIFT)))) 3138 return false; 3139 3140 if (vpid >> 16) 3141 return false; 3142 3143 if (type != INVVPID_ALL && !vpid) 3144 return false; 3145 3146 if (type == INVVPID_ADDR && !is_canonical(gla)) 3147 return false; 3148 3149 return true; 3150 } 3151 3152 static void try_invvpid(u64 type, u64 vpid, u64 gla) 3153 { 3154 int rc; 3155 bool valid = invvpid_valid(type, vpid, gla); 3156 u64 expected = valid ? VMXERR_UNSUPPORTED_VMCS_COMPONENT 3157 : VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID; 3158 /* 3159 * Set VMX_INST_ERROR to VMXERR_UNVALID_VMCS_COMPONENT, so 3160 * that we can tell if it is updated by INVVPID. 3161 */ 3162 vmcs_read(~0); 3163 rc = invvpid(type, vpid, gla); 3164 report(!rc == valid, "INVVPID type %ld VPID %lx GLA %lx %s", type, 3165 vpid, gla, 3166 valid ? "passes" : "fails"); 3167 report(vmcs_read(VMX_INST_ERROR) == expected, 3168 "After %s INVVPID, VMX_INST_ERR is %ld (actual %ld)", 3169 rc ? "failed" : "successful", 3170 expected, vmcs_read(VMX_INST_ERROR)); 3171 } 3172 3173 static void ds_invvpid(void *data) 3174 { 3175 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3176 u64 type = ffs(msr >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 3177 3178 TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 3179 asm volatile("invvpid %0, %1" 3180 : 3181 : "m"(*(struct invvpid_operand *)data), 3182 "r"(type)); 3183 } 3184 3185 /* 3186 * The SS override is ignored in 64-bit mode, so we use an addressing 3187 * mode with %rsp as the base register to generate an implicit SS 3188 * reference. 3189 */ 3190 static void ss_invvpid(void *data) 3191 { 3192 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3193 u64 type = ffs(msr >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 3194 3195 TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 3196 asm volatile("sub %%rsp,%0; invvpid (%%rsp,%0,1), %1" 3197 : "+r"(data) 3198 : "r"(type)); 3199 } 3200 3201 static void invvpid_test_gp(void) 3202 { 3203 bool fault; 3204 3205 fault = test_for_exception(GP_VECTOR, &ds_invvpid, 3206 (void *)NONCANONICAL); 3207 report(fault, "INVVPID with non-canonical DS operand raises #GP"); 3208 } 3209 3210 static void invvpid_test_ss(void) 3211 { 3212 bool fault; 3213 3214 fault = test_for_exception(SS_VECTOR, &ss_invvpid, 3215 (void *)NONCANONICAL); 3216 report(fault, "INVVPID with non-canonical SS operand raises #SS"); 3217 } 3218 3219 static void invvpid_test_pf(void) 3220 { 3221 void *vpage = alloc_vpage(); 3222 bool fault; 3223 3224 fault = test_for_exception(PF_VECTOR, &ds_invvpid, vpage); 3225 report(fault, "INVVPID with unmapped operand raises #PF"); 3226 } 3227 3228 static void try_compat_invvpid(void *unused) 3229 { 3230 struct far_pointer32 fp = { 3231 .offset = (uintptr_t)&&invvpid, 3232 .selector = KERNEL_CS32, 3233 }; 3234 register uintptr_t rsp asm("rsp"); 3235 3236 TEST_ASSERT_MSG(fp.offset == (uintptr_t)&&invvpid, 3237 "Code address too high."); 3238 TEST_ASSERT_MSG(rsp == (u32)rsp, "Stack address too high."); 3239 3240 asm goto ("lcall *%0" : : "m" (fp) : "rax" : invvpid); 3241 return; 3242 invvpid: 3243 asm volatile (".code32;" 3244 "invvpid (%eax), %eax;" 3245 "lret;" 3246 ".code64"); 3247 __builtin_unreachable(); 3248 } 3249 3250 static void invvpid_test_compatibility_mode(void) 3251 { 3252 bool fault; 3253 3254 fault = test_for_exception(UD_VECTOR, &try_compat_invvpid, NULL); 3255 report(fault, "Compatibility mode INVVPID raises #UD"); 3256 } 3257 3258 static void invvpid_test_not_in_vmx_operation(void) 3259 { 3260 bool fault; 3261 3262 TEST_ASSERT(!vmx_off()); 3263 fault = test_for_exception(UD_VECTOR, &ds_invvpid, NULL); 3264 report(fault, "INVVPID outside of VMX operation raises #UD"); 3265 TEST_ASSERT(!vmx_on()); 3266 } 3267 3268 /* 3269 * This does not test real-address mode, virtual-8086 mode, protected mode, 3270 * or CPL > 0. 3271 */ 3272 static void invvpid_test_v2(void) 3273 { 3274 u64 msr; 3275 int i; 3276 unsigned types = 0; 3277 unsigned type; 3278 3279 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 3280 !(ctrl_cpu_rev[1].clr & CPU_VPID)) 3281 test_skip("VPID not supported"); 3282 3283 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3284 3285 if (!(msr & VPID_CAP_INVVPID)) 3286 test_skip("INVVPID not supported.\n"); 3287 3288 if (msr & VPID_CAP_INVVPID_ADDR) 3289 types |= 1u << INVVPID_ADDR; 3290 if (msr & VPID_CAP_INVVPID_CXTGLB) 3291 types |= 1u << INVVPID_CONTEXT_GLOBAL; 3292 if (msr & VPID_CAP_INVVPID_ALL) 3293 types |= 1u << INVVPID_ALL; 3294 if (msr & VPID_CAP_INVVPID_CXTLOC) 3295 types |= 1u << INVVPID_CONTEXT_LOCAL; 3296 3297 if (!types) 3298 test_skip("No INVVPID types supported.\n"); 3299 3300 for (i = -127; i < 128; i++) 3301 try_invvpid(i, 0xffff, 0); 3302 3303 /* 3304 * VPID must not be more than 16 bits. 3305 */ 3306 for (i = 0; i < 64; i++) 3307 for (type = 0; type < 4; type++) 3308 if (types & (1u << type)) 3309 try_invvpid(type, 1ul << i, 0); 3310 3311 /* 3312 * VPID must not be zero, except for "all contexts." 3313 */ 3314 for (type = 0; type < 4; type++) 3315 if (types & (1u << type)) 3316 try_invvpid(type, 0, 0); 3317 3318 /* 3319 * The gla operand is only validated for single-address INVVPID. 3320 */ 3321 if (types & (1u << INVVPID_ADDR)) 3322 try_invvpid(INVVPID_ADDR, 0xffff, NONCANONICAL); 3323 3324 invvpid_test_gp(); 3325 invvpid_test_ss(); 3326 invvpid_test_pf(); 3327 invvpid_test_compatibility_mode(); 3328 invvpid_test_not_in_vmx_operation(); 3329 } 3330 3331 /* 3332 * Test for early VMLAUNCH failure. Returns true if VMLAUNCH makes it 3333 * at least as far as the guest-state checks. Returns false if the 3334 * VMLAUNCH fails early and execution falls through to the next 3335 * instruction. 3336 */ 3337 static bool vmlaunch_succeeds(void) 3338 { 3339 u32 exit_reason; 3340 3341 /* 3342 * Indirectly set VMX_INST_ERR to 12 ("VMREAD/VMWRITE from/to 3343 * unsupported VMCS component"). The caller can then check 3344 * to see if a failed VM-entry sets VMX_INST_ERR as expected. 3345 */ 3346 vmcs_write(~0u, 0); 3347 3348 vmcs_write(HOST_RIP, (uintptr_t)&&success); 3349 __asm__ __volatile__ goto ("vmwrite %%rsp, %0; vmlaunch" 3350 : 3351 : "r" ((u64)HOST_RSP) 3352 : "cc", "memory" 3353 : success); 3354 return false; 3355 success: 3356 exit_reason = vmcs_read(EXI_REASON); 3357 TEST_ASSERT(exit_reason == (VMX_FAIL_STATE | VMX_ENTRY_FAILURE) || 3358 exit_reason == (VMX_FAIL_MSR | VMX_ENTRY_FAILURE)); 3359 return true; 3360 } 3361 3362 /* 3363 * Try to launch the current VMCS. 3364 */ 3365 static void test_vmx_vmlaunch(u32 xerror) 3366 { 3367 bool success = vmlaunch_succeeds(); 3368 u32 vmx_inst_err; 3369 3370 report(success == !xerror, "vmlaunch %s", 3371 !xerror ? "succeeds" : "fails"); 3372 if (!success && xerror) { 3373 vmx_inst_err = vmcs_read(VMX_INST_ERROR); 3374 report(vmx_inst_err == xerror, 3375 "VMX inst error is %d (actual %d)", xerror, 3376 vmx_inst_err); 3377 } 3378 } 3379 3380 /* 3381 * Try to launch the current VMCS, and expect one of two possible 3382 * errors (or success) codes. 3383 */ 3384 static void test_vmx_vmlaunch2(u32 xerror1, u32 xerror2) 3385 { 3386 bool success = vmlaunch_succeeds(); 3387 u32 vmx_inst_err; 3388 3389 if (!xerror1 == !xerror2) 3390 report(success == !xerror1, "vmlaunch %s", 3391 !xerror1 ? "succeeds" : "fails"); 3392 3393 if (!success && (xerror1 || xerror2)) { 3394 vmx_inst_err = vmcs_read(VMX_INST_ERROR); 3395 report(vmx_inst_err == xerror1 || vmx_inst_err == xerror2, 3396 "VMX inst error is %d or %d (actual %d)", xerror1, 3397 xerror2, vmx_inst_err); 3398 } 3399 } 3400 3401 static void test_vmx_invalid_controls(void) 3402 { 3403 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_CONTROL_FIELD); 3404 } 3405 3406 static void test_vmx_valid_controls(void) 3407 { 3408 test_vmx_vmlaunch(0); 3409 } 3410 3411 /* 3412 * Test a particular value of a VM-execution control bit, if the value 3413 * is required or if the value is zero. 3414 */ 3415 static void test_rsvd_ctl_bit_value(const char *name, union vmx_ctrl_msr msr, 3416 enum Encoding encoding, unsigned bit, 3417 unsigned val) 3418 { 3419 u32 mask = 1u << bit; 3420 bool expected; 3421 u32 controls; 3422 3423 if (msr.set & mask) 3424 TEST_ASSERT(msr.clr & mask); 3425 3426 /* 3427 * We can't arbitrarily turn on a control bit, because it may 3428 * introduce dependencies on other VMCS fields. So, we only 3429 * test turning on bits that have a required setting. 3430 */ 3431 if (val && (msr.clr & mask) && !(msr.set & mask)) 3432 return; 3433 3434 report_prefix_pushf("%s %s bit %d", 3435 val ? "Set" : "Clear", name, bit); 3436 3437 controls = vmcs_read(encoding); 3438 if (val) { 3439 vmcs_write(encoding, msr.set | mask); 3440 expected = (msr.clr & mask); 3441 } else { 3442 vmcs_write(encoding, msr.set & ~mask); 3443 expected = !(msr.set & mask); 3444 } 3445 if (expected) 3446 test_vmx_valid_controls(); 3447 else 3448 test_vmx_invalid_controls(); 3449 vmcs_write(encoding, controls); 3450 report_prefix_pop(); 3451 } 3452 3453 /* 3454 * Test reserved values of a VM-execution control bit, based on the 3455 * allowed bit settings from the corresponding VMX capability MSR. 3456 */ 3457 static void test_rsvd_ctl_bit(const char *name, union vmx_ctrl_msr msr, 3458 enum Encoding encoding, unsigned bit) 3459 { 3460 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 0); 3461 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 1); 3462 } 3463 3464 /* 3465 * Reserved bits in the pin-based VM-execution controls must be set 3466 * properly. Software may consult the VMX capability MSRs to determine 3467 * the proper settings. 3468 * [Intel SDM] 3469 */ 3470 static void test_pin_based_ctls(void) 3471 { 3472 unsigned bit; 3473 3474 printf("%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PIN" : 3475 "MSR_IA32_VMX_PINBASED_CTLS", ctrl_pin_rev.val); 3476 for (bit = 0; bit < 32; bit++) 3477 test_rsvd_ctl_bit("pin-based controls", 3478 ctrl_pin_rev, PIN_CONTROLS, bit); 3479 } 3480 3481 /* 3482 * Reserved bits in the primary processor-based VM-execution controls 3483 * must be set properly. Software may consult the VMX capability MSRs 3484 * to determine the proper settings. 3485 * [Intel SDM] 3486 */ 3487 static void test_primary_processor_based_ctls(void) 3488 { 3489 unsigned bit; 3490 3491 printf("\n%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PROC" : 3492 "MSR_IA32_VMX_PROCBASED_CTLS", ctrl_cpu_rev[0].val); 3493 for (bit = 0; bit < 32; bit++) 3494 test_rsvd_ctl_bit("primary processor-based controls", 3495 ctrl_cpu_rev[0], CPU_EXEC_CTRL0, bit); 3496 } 3497 3498 /* 3499 * If the "activate secondary controls" primary processor-based 3500 * VM-execution control is 1, reserved bits in the secondary 3501 * processor-based VM-execution controls must be cleared. Software may 3502 * consult the VMX capability MSRs to determine which bits are 3503 * reserved. 3504 * If the "activate secondary controls" primary processor-based 3505 * VM-execution control is 0 (or if the processor does not support the 3506 * 1-setting of that control), no checks are performed on the 3507 * secondary processor-based VM-execution controls. 3508 * [Intel SDM] 3509 */ 3510 static void test_secondary_processor_based_ctls(void) 3511 { 3512 u32 primary; 3513 u32 secondary; 3514 unsigned bit; 3515 3516 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) 3517 return; 3518 3519 primary = vmcs_read(CPU_EXEC_CTRL0); 3520 secondary = vmcs_read(CPU_EXEC_CTRL1); 3521 3522 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3523 printf("\nMSR_IA32_VMX_PROCBASED_CTLS2: %lx\n", ctrl_cpu_rev[1].val); 3524 for (bit = 0; bit < 32; bit++) 3525 test_rsvd_ctl_bit("secondary processor-based controls", 3526 ctrl_cpu_rev[1], CPU_EXEC_CTRL1, bit); 3527 3528 /* 3529 * When the "activate secondary controls" VM-execution control 3530 * is clear, there are no checks on the secondary controls. 3531 */ 3532 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3533 vmcs_write(CPU_EXEC_CTRL1, ~0); 3534 report(vmlaunch_succeeds(), 3535 "Secondary processor-based controls ignored"); 3536 vmcs_write(CPU_EXEC_CTRL1, secondary); 3537 vmcs_write(CPU_EXEC_CTRL0, primary); 3538 } 3539 3540 static void try_cr3_target_count(unsigned i, unsigned max) 3541 { 3542 report_prefix_pushf("CR3 target count 0x%x", i); 3543 vmcs_write(CR3_TARGET_COUNT, i); 3544 if (i <= max) 3545 test_vmx_valid_controls(); 3546 else 3547 test_vmx_invalid_controls(); 3548 report_prefix_pop(); 3549 } 3550 3551 /* 3552 * The CR3-target count must not be greater than 4. Future processors 3553 * may support a different number of CR3-target values. Software 3554 * should read the VMX capability MSR IA32_VMX_MISC to determine the 3555 * number of values supported. 3556 * [Intel SDM] 3557 */ 3558 static void test_cr3_targets(void) 3559 { 3560 unsigned supported_targets = (rdmsr(MSR_IA32_VMX_MISC) >> 16) & 0x1ff; 3561 u32 cr3_targets = vmcs_read(CR3_TARGET_COUNT); 3562 unsigned i; 3563 3564 printf("\nSupported CR3 targets: %d\n", supported_targets); 3565 TEST_ASSERT(supported_targets <= 256); 3566 3567 try_cr3_target_count(-1u, supported_targets); 3568 try_cr3_target_count(0x80000000, supported_targets); 3569 try_cr3_target_count(0x7fffffff, supported_targets); 3570 for (i = 0; i <= supported_targets + 1; i++) 3571 try_cr3_target_count(i, supported_targets); 3572 vmcs_write(CR3_TARGET_COUNT, cr3_targets); 3573 3574 /* VMWRITE to nonexistent target fields should fail. */ 3575 for (i = supported_targets; i < 256; i++) 3576 TEST_ASSERT(vmcs_write(CR3_TARGET_0 + i*2, 0)); 3577 } 3578 3579 /* 3580 * Test a particular address setting in the VMCS 3581 */ 3582 static void test_vmcs_addr(const char *name, 3583 enum Encoding encoding, 3584 u64 align, 3585 bool ignored, 3586 bool skip_beyond_mapped_ram, 3587 u64 addr) 3588 { 3589 report_prefix_pushf("%s = %lx", name, addr); 3590 vmcs_write(encoding, addr); 3591 if (skip_beyond_mapped_ram && 3592 addr > fwcfg_get_u64(FW_CFG_RAM_SIZE) - align && 3593 addr < (1ul << cpuid_maxphyaddr())) 3594 printf("Skipping physical address beyond mapped RAM\n"); 3595 else if (ignored || (IS_ALIGNED(addr, align) && 3596 addr < (1ul << cpuid_maxphyaddr()))) 3597 test_vmx_valid_controls(); 3598 else 3599 test_vmx_invalid_controls(); 3600 report_prefix_pop(); 3601 } 3602 3603 /* 3604 * Test interesting values for a VMCS address 3605 */ 3606 static void test_vmcs_addr_values(const char *name, 3607 enum Encoding encoding, 3608 u64 align, 3609 bool ignored, 3610 bool skip_beyond_mapped_ram, 3611 u32 bit_start, u32 bit_end) 3612 { 3613 unsigned i; 3614 u64 orig_val = vmcs_read(encoding); 3615 3616 for (i = bit_start; i <= bit_end; i++) 3617 test_vmcs_addr(name, encoding, align, ignored, 3618 skip_beyond_mapped_ram, 1ul << i); 3619 3620 test_vmcs_addr(name, encoding, align, ignored, 3621 skip_beyond_mapped_ram, PAGE_SIZE - 1); 3622 test_vmcs_addr(name, encoding, align, ignored, 3623 skip_beyond_mapped_ram, PAGE_SIZE); 3624 test_vmcs_addr(name, encoding, align, ignored, 3625 skip_beyond_mapped_ram, 3626 (1ul << cpuid_maxphyaddr()) - PAGE_SIZE); 3627 test_vmcs_addr(name, encoding, align, ignored, 3628 skip_beyond_mapped_ram, -1ul); 3629 3630 vmcs_write(encoding, orig_val); 3631 } 3632 3633 /* 3634 * Test a physical address reference in the VMCS, when the corresponding 3635 * feature is enabled and when the corresponding feature is disabled. 3636 */ 3637 static void test_vmcs_addr_reference(u32 control_bit, enum Encoding field, 3638 const char *field_name, 3639 const char *control_name, u64 align, 3640 bool skip_beyond_mapped_ram, 3641 bool control_primary) 3642 { 3643 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 3644 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 3645 u64 page_addr; 3646 3647 if (control_primary) { 3648 if (!(ctrl_cpu_rev[0].clr & control_bit)) 3649 return; 3650 } else { 3651 if (!(ctrl_cpu_rev[1].clr & control_bit)) 3652 return; 3653 } 3654 3655 page_addr = vmcs_read(field); 3656 3657 report_prefix_pushf("%s enabled", control_name); 3658 if (control_primary) { 3659 vmcs_write(CPU_EXEC_CTRL0, primary | control_bit); 3660 } else { 3661 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3662 vmcs_write(CPU_EXEC_CTRL1, secondary | control_bit); 3663 } 3664 3665 test_vmcs_addr_values(field_name, field, align, false, 3666 skip_beyond_mapped_ram, 0, 63); 3667 report_prefix_pop(); 3668 3669 report_prefix_pushf("%s disabled", control_name); 3670 if (control_primary) { 3671 vmcs_write(CPU_EXEC_CTRL0, primary & ~control_bit); 3672 } else { 3673 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3674 vmcs_write(CPU_EXEC_CTRL1, secondary & ~control_bit); 3675 } 3676 3677 test_vmcs_addr_values(field_name, field, align, true, false, 0, 63); 3678 report_prefix_pop(); 3679 3680 vmcs_write(field, page_addr); 3681 vmcs_write(CPU_EXEC_CTRL0, primary); 3682 vmcs_write(CPU_EXEC_CTRL1, secondary); 3683 } 3684 3685 /* 3686 * If the "use I/O bitmaps" VM-execution control is 1, bits 11:0 of 3687 * each I/O-bitmap address must be 0. Neither address should set any 3688 * bits beyond the processor's physical-address width. 3689 * [Intel SDM] 3690 */ 3691 static void test_io_bitmaps(void) 3692 { 3693 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_A, 3694 "I/O bitmap A", "Use I/O bitmaps", 3695 PAGE_SIZE, false, true); 3696 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_B, 3697 "I/O bitmap B", "Use I/O bitmaps", 3698 PAGE_SIZE, false, true); 3699 } 3700 3701 /* 3702 * If the "use MSR bitmaps" VM-execution control is 1, bits 11:0 of 3703 * the MSR-bitmap address must be 0. The address should not set any 3704 * bits beyond the processor's physical-address width. 3705 * [Intel SDM] 3706 */ 3707 static void test_msr_bitmap(void) 3708 { 3709 test_vmcs_addr_reference(CPU_MSR_BITMAP, MSR_BITMAP, 3710 "MSR bitmap", "Use MSR bitmaps", 3711 PAGE_SIZE, false, true); 3712 } 3713 3714 /* 3715 * If the "use TPR shadow" VM-execution control is 1, the virtual-APIC 3716 * address must satisfy the following checks: 3717 * - Bits 11:0 of the address must be 0. 3718 * - The address should not set any bits beyond the processor's 3719 * physical-address width. 3720 * [Intel SDM] 3721 */ 3722 static void test_apic_virt_addr(void) 3723 { 3724 /* 3725 * Ensure the processor will never use the virtual-APIC page, since 3726 * we will point it to invalid RAM. Otherwise KVM is puzzled about 3727 * what we're trying to achieve and fails vmentry. 3728 */ 3729 u32 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 3730 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0 | CPU_CR8_LOAD | CPU_CR8_STORE); 3731 test_vmcs_addr_reference(CPU_TPR_SHADOW, APIC_VIRT_ADDR, 3732 "virtual-APIC address", "Use TPR shadow", 3733 PAGE_SIZE, false, true); 3734 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 3735 } 3736 3737 /* 3738 * If the "virtualize APIC-accesses" VM-execution control is 1, the 3739 * APIC-access address must satisfy the following checks: 3740 * - Bits 11:0 of the address must be 0. 3741 * - The address should not set any bits beyond the processor's 3742 * physical-address width. 3743 * [Intel SDM] 3744 */ 3745 static void test_apic_access_addr(void) 3746 { 3747 void *apic_access_page = alloc_page(); 3748 3749 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_page)); 3750 3751 test_vmcs_addr_reference(CPU_VIRT_APIC_ACCESSES, APIC_ACCS_ADDR, 3752 "APIC-access address", 3753 "virtualize APIC-accesses", PAGE_SIZE, 3754 true, false); 3755 } 3756 3757 static bool set_bit_pattern(u8 mask, u32 *secondary) 3758 { 3759 u8 i; 3760 bool flag = false; 3761 u32 test_bits[3] = { 3762 CPU_VIRT_X2APIC, 3763 CPU_APIC_REG_VIRT, 3764 CPU_VINTD 3765 }; 3766 3767 for (i = 0; i < ARRAY_SIZE(test_bits); i++) { 3768 if ((mask & (1u << i)) && 3769 (ctrl_cpu_rev[1].clr & test_bits[i])) { 3770 *secondary |= test_bits[i]; 3771 flag = true; 3772 } 3773 } 3774 3775 return (flag); 3776 } 3777 3778 /* 3779 * If the "use TPR shadow" VM-execution control is 0, the following 3780 * VM-execution controls must also be 0: 3781 * - virtualize x2APIC mode 3782 * - APIC-register virtualization 3783 * - virtual-interrupt delivery 3784 * [Intel SDM] 3785 * 3786 * 2. If the "virtualize x2APIC mode" VM-execution control is 1, the 3787 * "virtualize APIC accesses" VM-execution control must be 0. 3788 * [Intel SDM] 3789 */ 3790 static void test_apic_virtual_ctls(void) 3791 { 3792 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3793 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3794 u32 primary = saved_primary; 3795 u32 secondary = saved_secondary; 3796 bool ctrl = false; 3797 char str[10] = "disabled"; 3798 u8 i = 0, j; 3799 3800 /* 3801 * First test 3802 */ 3803 if (!((ctrl_cpu_rev[0].clr & (CPU_SECONDARY | CPU_TPR_SHADOW)) == 3804 (CPU_SECONDARY | CPU_TPR_SHADOW))) 3805 return; 3806 3807 primary |= CPU_SECONDARY; 3808 primary &= ~CPU_TPR_SHADOW; 3809 vmcs_write(CPU_EXEC_CTRL0, primary); 3810 3811 while (1) { 3812 for (j = 1; j < 8; j++) { 3813 secondary &= ~(CPU_VIRT_X2APIC | CPU_APIC_REG_VIRT | CPU_VINTD); 3814 if (primary & CPU_TPR_SHADOW) { 3815 ctrl = true; 3816 } else { 3817 if (! set_bit_pattern(j, &secondary)) 3818 ctrl = true; 3819 else 3820 ctrl = false; 3821 } 3822 3823 vmcs_write(CPU_EXEC_CTRL1, secondary); 3824 report_prefix_pushf("Use TPR shadow %s, virtualize x2APIC mode %s, APIC-register virtualization %s, virtual-interrupt delivery %s", 3825 str, (secondary & CPU_VIRT_X2APIC) ? "enabled" : "disabled", (secondary & CPU_APIC_REG_VIRT) ? "enabled" : "disabled", (secondary & CPU_VINTD) ? "enabled" : "disabled"); 3826 if (ctrl) 3827 test_vmx_valid_controls(); 3828 else 3829 test_vmx_invalid_controls(); 3830 report_prefix_pop(); 3831 } 3832 3833 if (i == 1) 3834 break; 3835 i++; 3836 3837 primary |= CPU_TPR_SHADOW; 3838 vmcs_write(CPU_EXEC_CTRL0, primary); 3839 strcpy(str, "enabled"); 3840 } 3841 3842 /* 3843 * Second test 3844 */ 3845 u32 apic_virt_ctls = (CPU_VIRT_X2APIC | CPU_VIRT_APIC_ACCESSES); 3846 3847 primary = saved_primary; 3848 secondary = saved_secondary; 3849 if (!((ctrl_cpu_rev[1].clr & apic_virt_ctls) == apic_virt_ctls)) 3850 return; 3851 3852 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3853 secondary &= ~CPU_VIRT_APIC_ACCESSES; 3854 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_X2APIC); 3855 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access disabled"); 3856 test_vmx_valid_controls(); 3857 report_prefix_pop(); 3858 3859 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_APIC_ACCESSES); 3860 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access enabled"); 3861 test_vmx_valid_controls(); 3862 report_prefix_pop(); 3863 3864 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_X2APIC); 3865 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access enabled"); 3866 test_vmx_invalid_controls(); 3867 report_prefix_pop(); 3868 3869 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_APIC_ACCESSES); 3870 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access disabled"); 3871 test_vmx_valid_controls(); 3872 report_prefix_pop(); 3873 3874 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3875 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3876 } 3877 3878 /* 3879 * If the "virtual-interrupt delivery" VM-execution control is 1, the 3880 * "external-interrupt exiting" VM-execution control must be 1. 3881 * [Intel SDM] 3882 */ 3883 static void test_virtual_intr_ctls(void) 3884 { 3885 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3886 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3887 u32 saved_pin = vmcs_read(PIN_CONTROLS); 3888 u32 primary = saved_primary; 3889 u32 secondary = saved_secondary; 3890 u32 pin = saved_pin; 3891 3892 if (!((ctrl_cpu_rev[1].clr & CPU_VINTD) && 3893 (ctrl_pin_rev.clr & PIN_EXTINT))) 3894 return; 3895 3896 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 3897 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VINTD); 3898 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 3899 report_prefix_pushf("Virtualize interrupt-delivery disabled; external-interrupt exiting disabled"); 3900 test_vmx_valid_controls(); 3901 report_prefix_pop(); 3902 3903 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VINTD); 3904 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 3905 test_vmx_invalid_controls(); 3906 report_prefix_pop(); 3907 3908 vmcs_write(PIN_CONTROLS, pin | PIN_EXTINT); 3909 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting enabled"); 3910 test_vmx_valid_controls(); 3911 report_prefix_pop(); 3912 3913 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 3914 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 3915 test_vmx_invalid_controls(); 3916 report_prefix_pop(); 3917 3918 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3919 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3920 vmcs_write(PIN_CONTROLS, saved_pin); 3921 } 3922 3923 static void test_pi_desc_addr(u64 addr, bool ctrl) 3924 { 3925 vmcs_write(POSTED_INTR_DESC_ADDR, addr); 3926 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-descriptor-address 0x%lx", addr); 3927 if (ctrl) 3928 test_vmx_valid_controls(); 3929 else 3930 test_vmx_invalid_controls(); 3931 report_prefix_pop(); 3932 } 3933 3934 /* 3935 * If the “process posted interrupts†VM-execution control is 1, the 3936 * following must be true: 3937 * 3938 * - The “virtual-interrupt delivery†VM-execution control is 1. 3939 * - The “acknowledge interrupt on exit†VM-exit control is 1. 3940 * - The posted-interrupt notification vector has a value in the 3941 * - range 0–255 (bits 15:8 are all 0). 3942 * - Bits 5:0 of the posted-interrupt descriptor address are all 0. 3943 * - The posted-interrupt descriptor address does not set any bits 3944 * beyond the processor's physical-address width. 3945 * [Intel SDM] 3946 */ 3947 static void test_posted_intr(void) 3948 { 3949 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3950 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3951 u32 saved_pin = vmcs_read(PIN_CONTROLS); 3952 u32 exit_ctl_saved = vmcs_read(EXI_CONTROLS); 3953 u32 primary = saved_primary; 3954 u32 secondary = saved_secondary; 3955 u32 pin = saved_pin; 3956 u32 exit_ctl = exit_ctl_saved; 3957 u16 vec; 3958 int i; 3959 3960 if (!((ctrl_pin_rev.clr & PIN_POST_INTR) && 3961 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 3962 (ctrl_exit_rev.clr & EXI_INTA))) 3963 return; 3964 3965 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 3966 3967 /* 3968 * Test virtual-interrupt-delivery and acknowledge-interrupt-on-exit 3969 */ 3970 pin |= PIN_POST_INTR; 3971 vmcs_write(PIN_CONTROLS, pin); 3972 secondary &= ~CPU_VINTD; 3973 vmcs_write(CPU_EXEC_CTRL1, secondary); 3974 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled"); 3975 test_vmx_invalid_controls(); 3976 report_prefix_pop(); 3977 3978 secondary |= CPU_VINTD; 3979 vmcs_write(CPU_EXEC_CTRL1, secondary); 3980 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled"); 3981 test_vmx_invalid_controls(); 3982 report_prefix_pop(); 3983 3984 exit_ctl &= ~EXI_INTA; 3985 vmcs_write(EXI_CONTROLS, exit_ctl); 3986 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit disabled"); 3987 test_vmx_invalid_controls(); 3988 report_prefix_pop(); 3989 3990 exit_ctl |= EXI_INTA; 3991 vmcs_write(EXI_CONTROLS, exit_ctl); 3992 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 3993 test_vmx_valid_controls(); 3994 report_prefix_pop(); 3995 3996 secondary &= ~CPU_VINTD; 3997 vmcs_write(CPU_EXEC_CTRL1, secondary); 3998 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled; acknowledge-interrupt-on-exit enabled"); 3999 test_vmx_invalid_controls(); 4000 report_prefix_pop(); 4001 4002 secondary |= CPU_VINTD; 4003 vmcs_write(CPU_EXEC_CTRL1, secondary); 4004 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 4005 test_vmx_valid_controls(); 4006 report_prefix_pop(); 4007 4008 /* 4009 * Test posted-interrupt notification vector 4010 */ 4011 for (i = 0; i < 8; i++) { 4012 vec = (1ul << i); 4013 vmcs_write(PINV, vec); 4014 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 4015 test_vmx_valid_controls(); 4016 report_prefix_pop(); 4017 } 4018 for (i = 8; i < 16; i++) { 4019 vec = (1ul << i); 4020 vmcs_write(PINV, vec); 4021 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 4022 test_vmx_invalid_controls(); 4023 report_prefix_pop(); 4024 } 4025 4026 vec &= ~(0xff << 8); 4027 vmcs_write(PINV, vec); 4028 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 4029 test_vmx_valid_controls(); 4030 report_prefix_pop(); 4031 4032 /* 4033 * Test posted-interrupt descriptor addresss 4034 */ 4035 for (i = 0; i < 6; i++) { 4036 test_pi_desc_addr(1ul << i, false); 4037 } 4038 4039 test_pi_desc_addr(0xf0, false); 4040 test_pi_desc_addr(0xff, false); 4041 test_pi_desc_addr(0x0f, false); 4042 test_pi_desc_addr(0x8000, true); 4043 test_pi_desc_addr(0x00, true); 4044 test_pi_desc_addr(0xc000, true); 4045 4046 test_vmcs_addr_values("process-posted interrupts", 4047 POSTED_INTR_DESC_ADDR, 64, 4048 false, false, 0, 63); 4049 4050 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 4051 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 4052 vmcs_write(PIN_CONTROLS, saved_pin); 4053 } 4054 4055 static void test_apic_ctls(void) 4056 { 4057 test_apic_virt_addr(); 4058 test_apic_access_addr(); 4059 test_apic_virtual_ctls(); 4060 test_virtual_intr_ctls(); 4061 test_posted_intr(); 4062 } 4063 4064 /* 4065 * If the “enable VPID†VM-execution control is 1, the value of the 4066 * of the VPID VM-execution control field must not be 0000H. 4067 * [Intel SDM] 4068 */ 4069 static void test_vpid(void) 4070 { 4071 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 4072 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 4073 u16 vpid = 0x0000; 4074 int i; 4075 4076 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4077 (ctrl_cpu_rev[1].clr & CPU_VPID))) { 4078 printf("Secondary controls and/or VPID not supported\n"); 4079 return; 4080 } 4081 4082 vmcs_write(CPU_EXEC_CTRL0, saved_primary | CPU_SECONDARY); 4083 vmcs_write(CPU_EXEC_CTRL1, saved_secondary & ~CPU_VPID); 4084 vmcs_write(VPID, vpid); 4085 report_prefix_pushf("VPID disabled; VPID value %x", vpid); 4086 test_vmx_valid_controls(); 4087 report_prefix_pop(); 4088 4089 vmcs_write(CPU_EXEC_CTRL1, saved_secondary | CPU_VPID); 4090 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 4091 test_vmx_invalid_controls(); 4092 report_prefix_pop(); 4093 4094 for (i = 0; i < 16; i++) { 4095 vpid = (short)1 << i;; 4096 vmcs_write(VPID, vpid); 4097 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 4098 test_vmx_valid_controls(); 4099 report_prefix_pop(); 4100 } 4101 4102 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 4103 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 4104 } 4105 4106 static void set_vtpr(unsigned vtpr) 4107 { 4108 *(u32 *)phys_to_virt(vmcs_read(APIC_VIRT_ADDR) + APIC_TASKPRI) = vtpr; 4109 } 4110 4111 static void try_tpr_threshold_and_vtpr(unsigned threshold, unsigned vtpr) 4112 { 4113 bool valid = true; 4114 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4115 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4116 4117 if ((primary & CPU_TPR_SHADOW) && 4118 (!(primary & CPU_SECONDARY) || 4119 !(secondary & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 4120 valid = (threshold & 0xf) <= ((vtpr >> 4) & 0xf); 4121 4122 set_vtpr(vtpr); 4123 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0x%x", 4124 threshold, (vtpr >> 4) & 0xf); 4125 if (valid) 4126 test_vmx_valid_controls(); 4127 else 4128 test_vmx_invalid_controls(); 4129 report_prefix_pop(); 4130 } 4131 4132 static void test_invalid_event_injection(void) 4133 { 4134 u32 ent_intr_info_save = vmcs_read(ENT_INTR_INFO); 4135 u32 ent_intr_error_save = vmcs_read(ENT_INTR_ERROR); 4136 u32 ent_inst_len_save = vmcs_read(ENT_INST_LEN); 4137 u32 primary_save = vmcs_read(CPU_EXEC_CTRL0); 4138 u32 secondary_save = vmcs_read(CPU_EXEC_CTRL1); 4139 u64 guest_cr0_save = vmcs_read(GUEST_CR0); 4140 u32 ent_intr_info_base = INTR_INFO_VALID_MASK; 4141 u32 ent_intr_info, ent_intr_err, ent_intr_len; 4142 u32 cnt; 4143 4144 /* Setup */ 4145 report_prefix_push("invalid event injection"); 4146 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4147 vmcs_write(ENT_INST_LEN, 0x00000001); 4148 4149 /* The field’s interruption type is not set to a reserved value. */ 4150 ent_intr_info = ent_intr_info_base | INTR_TYPE_RESERVED | DE_VECTOR; 4151 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4152 "RESERVED interruption type invalid [-]", 4153 ent_intr_info); 4154 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4155 test_vmx_invalid_controls(); 4156 report_prefix_pop(); 4157 4158 ent_intr_info = ent_intr_info_base | INTR_TYPE_EXT_INTR | 4159 DE_VECTOR; 4160 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4161 "RESERVED interruption type invalid [+]", 4162 ent_intr_info); 4163 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4164 test_vmx_valid_controls(); 4165 report_prefix_pop(); 4166 4167 /* If the interruption type is other event, the vector is 0. */ 4168 ent_intr_info = ent_intr_info_base | INTR_TYPE_OTHER_EVENT | DB_VECTOR; 4169 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4170 "(OTHER EVENT && vector != 0) invalid [-]", 4171 ent_intr_info); 4172 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4173 test_vmx_invalid_controls(); 4174 report_prefix_pop(); 4175 4176 /* If the interruption type is NMI, the vector is 2 (negative case). */ 4177 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | DE_VECTOR; 4178 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4179 "(NMI && vector != 2) invalid [-]", ent_intr_info); 4180 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4181 test_vmx_invalid_controls(); 4182 report_prefix_pop(); 4183 4184 /* If the interruption type is NMI, the vector is 2 (positive case). */ 4185 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | NMI_VECTOR; 4186 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4187 "(NMI && vector == 2) valid [+]", ent_intr_info); 4188 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4189 test_vmx_valid_controls(); 4190 report_prefix_pop(); 4191 4192 /* 4193 * If the interruption type 4194 * is HW exception, the vector is at most 31. 4195 */ 4196 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 0x20; 4197 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4198 "(HW exception && vector > 31) invalid [-]", 4199 ent_intr_info); 4200 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4201 test_vmx_invalid_controls(); 4202 report_prefix_pop(); 4203 4204 /* 4205 * deliver-error-code is 1 iff either 4206 * (a) the "unrestricted guest" VM-execution control is 0 4207 * (b) CR0.PE is set. 4208 */ 4209 4210 /* Assert that unrestricted guest is disabled or unsupported */ 4211 assert(!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 4212 !(secondary_save & CPU_URG)); 4213 4214 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4215 GP_VECTOR; 4216 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4217 "error code <-> (!URG || prot_mode) [-]", 4218 ent_intr_info); 4219 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4220 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4221 test_vmx_invalid_controls(); 4222 report_prefix_pop(); 4223 4224 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4225 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4226 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4227 "error code <-> (!URG || prot_mode) [+]", 4228 ent_intr_info); 4229 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4230 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4231 test_vmx_valid_controls(); 4232 report_prefix_pop(); 4233 4234 if (enable_unrestricted_guest()) 4235 goto skip_unrestricted_guest; 4236 4237 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4238 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4239 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4240 "error code <-> (!URG || prot_mode) [-]", 4241 ent_intr_info); 4242 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4243 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4244 test_vmx_invalid_controls(); 4245 report_prefix_pop(); 4246 4247 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4248 GP_VECTOR; 4249 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4250 "error code <-> (!URG || prot_mode) [-]", 4251 ent_intr_info); 4252 vmcs_write(GUEST_CR0, guest_cr0_save | X86_CR0_PE); 4253 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4254 test_vmx_invalid_controls(); 4255 report_prefix_pop(); 4256 4257 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4258 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4259 4260 skip_unrestricted_guest: 4261 vmcs_write(GUEST_CR0, guest_cr0_save); 4262 4263 /* deliver-error-code is 1 iff the interruption type is HW exception */ 4264 report_prefix_push("error code <-> HW exception"); 4265 for (cnt = 0; cnt < 8; cnt++) { 4266 u32 exception_type_mask = cnt << 8; 4267 u32 deliver_error_code_mask = 4268 exception_type_mask != INTR_TYPE_HARD_EXCEPTION ? 4269 INTR_INFO_DELIVER_CODE_MASK : 0; 4270 4271 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4272 exception_type_mask | GP_VECTOR; 4273 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4274 ent_intr_info); 4275 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4276 test_vmx_invalid_controls(); 4277 report_prefix_pop(); 4278 } 4279 report_prefix_pop(); 4280 4281 /* 4282 * deliver-error-code is 1 iff the the vector 4283 * indicates an exception that would normally deliver an error code 4284 */ 4285 report_prefix_push("error code <-> vector delivers error code"); 4286 for (cnt = 0; cnt < 32; cnt++) { 4287 bool has_error_code = false; 4288 u32 deliver_error_code_mask; 4289 4290 switch (cnt) { 4291 case DF_VECTOR: 4292 case TS_VECTOR: 4293 case NP_VECTOR: 4294 case SS_VECTOR: 4295 case GP_VECTOR: 4296 case PF_VECTOR: 4297 case AC_VECTOR: 4298 has_error_code = true; 4299 } 4300 4301 /* Negative case */ 4302 deliver_error_code_mask = has_error_code ? 4303 0 : 4304 INTR_INFO_DELIVER_CODE_MASK; 4305 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4306 INTR_TYPE_HARD_EXCEPTION | cnt; 4307 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4308 ent_intr_info); 4309 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4310 test_vmx_invalid_controls(); 4311 report_prefix_pop(); 4312 4313 /* Positive case */ 4314 deliver_error_code_mask = has_error_code ? 4315 INTR_INFO_DELIVER_CODE_MASK : 4316 0; 4317 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4318 INTR_TYPE_HARD_EXCEPTION | cnt; 4319 report_prefix_pushf("VM-entry intr info=0x%x [+]", 4320 ent_intr_info); 4321 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4322 test_vmx_valid_controls(); 4323 report_prefix_pop(); 4324 } 4325 report_prefix_pop(); 4326 4327 /* Reserved bits in the field (30:12) are 0. */ 4328 report_prefix_push("reserved bits clear"); 4329 for (cnt = 12; cnt <= 30; cnt++) { 4330 ent_intr_info = ent_intr_info_base | 4331 INTR_INFO_DELIVER_CODE_MASK | 4332 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR | 4333 (1U << cnt); 4334 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4335 ent_intr_info); 4336 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4337 test_vmx_invalid_controls(); 4338 report_prefix_pop(); 4339 } 4340 report_prefix_pop(); 4341 4342 /* 4343 * If deliver-error-code is 1 4344 * bits 31:16 of the VM-entry exception error-code field are 0. 4345 */ 4346 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4347 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4348 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4349 "VM-entry exception error code[31:16] clear", 4350 ent_intr_info); 4351 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4352 for (cnt = 16; cnt <= 31; cnt++) { 4353 ent_intr_err = 1U << cnt; 4354 report_prefix_pushf("VM-entry intr error=0x%x [-]", 4355 ent_intr_err); 4356 vmcs_write(ENT_INTR_ERROR, ent_intr_err); 4357 test_vmx_invalid_controls(); 4358 report_prefix_pop(); 4359 } 4360 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4361 report_prefix_pop(); 4362 4363 /* 4364 * If the interruption type is software interrupt, software exception, 4365 * or privileged software exception, the VM-entry instruction-length 4366 * field is in the range 0–15. 4367 */ 4368 4369 for (cnt = 0; cnt < 3; cnt++) { 4370 switch (cnt) { 4371 case 0: 4372 ent_intr_info = ent_intr_info_base | 4373 INTR_TYPE_SOFT_INTR; 4374 break; 4375 case 1: 4376 ent_intr_info = ent_intr_info_base | 4377 INTR_TYPE_SOFT_EXCEPTION; 4378 break; 4379 case 2: 4380 ent_intr_info = ent_intr_info_base | 4381 INTR_TYPE_PRIV_SW_EXCEPTION; 4382 break; 4383 } 4384 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4385 "VM-entry instruction-length check", 4386 ent_intr_info); 4387 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4388 4389 /* Instruction length set to -1 (0xFFFFFFFF) should fail */ 4390 ent_intr_len = -1; 4391 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4392 ent_intr_len); 4393 vmcs_write(ENT_INST_LEN, ent_intr_len); 4394 test_vmx_invalid_controls(); 4395 report_prefix_pop(); 4396 4397 /* Instruction length set to 16 should fail */ 4398 ent_intr_len = 0x00000010; 4399 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4400 ent_intr_len); 4401 vmcs_write(ENT_INST_LEN, 0x00000010); 4402 test_vmx_invalid_controls(); 4403 report_prefix_pop(); 4404 4405 report_prefix_pop(); 4406 } 4407 4408 /* Cleanup */ 4409 vmcs_write(ENT_INTR_INFO, ent_intr_info_save); 4410 vmcs_write(ENT_INTR_ERROR, ent_intr_error_save); 4411 vmcs_write(ENT_INST_LEN, ent_inst_len_save); 4412 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4413 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4414 vmcs_write(GUEST_CR0, guest_cr0_save); 4415 report_prefix_pop(); 4416 } 4417 4418 /* 4419 * Test interesting vTPR values for a given TPR threshold. 4420 */ 4421 static void test_vtpr_values(unsigned threshold) 4422 { 4423 try_tpr_threshold_and_vtpr(threshold, (threshold - 1) << 4); 4424 try_tpr_threshold_and_vtpr(threshold, threshold << 4); 4425 try_tpr_threshold_and_vtpr(threshold, (threshold + 1) << 4); 4426 } 4427 4428 static void try_tpr_threshold(unsigned threshold) 4429 { 4430 bool valid = true; 4431 4432 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4433 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4434 4435 if ((primary & CPU_TPR_SHADOW) && !((primary & CPU_SECONDARY) && 4436 (secondary & CPU_VINTD))) 4437 valid = !(threshold >> 4); 4438 4439 set_vtpr(-1); 4440 vmcs_write(TPR_THRESHOLD, threshold); 4441 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0xf", threshold); 4442 if (valid) 4443 test_vmx_valid_controls(); 4444 else 4445 test_vmx_invalid_controls(); 4446 report_prefix_pop(); 4447 4448 if (valid) 4449 test_vtpr_values(threshold); 4450 } 4451 4452 /* 4453 * Test interesting TPR threshold values. 4454 */ 4455 static void test_tpr_threshold_values(void) 4456 { 4457 unsigned i; 4458 4459 for (i = 0; i < 0x10; i++) 4460 try_tpr_threshold(i); 4461 for (i = 4; i < 32; i++) 4462 try_tpr_threshold(1u << i); 4463 try_tpr_threshold(-1u); 4464 try_tpr_threshold(0x7fffffff); 4465 } 4466 4467 /* 4468 * This test covers the following two VM entry checks: 4469 * 4470 * i) If the "use TPR shadow" VM-execution control is 1 and the 4471 * "virtual-interrupt delivery" VM-execution control is 0, bits 4472 * 31:4 of the TPR threshold VM-execution control field must 4473 be 0. 4474 * [Intel SDM] 4475 * 4476 * ii) If the "use TPR shadow" VM-execution control is 1, the 4477 * "virtual-interrupt delivery" VM-execution control is 0 4478 * and the "virtualize APIC accesses" VM-execution control 4479 * is 0, the value of bits 3:0 of the TPR threshold VM-execution 4480 * control field must not be greater than the value of bits 4481 * 7:4 of VTPR. 4482 * [Intel SDM] 4483 */ 4484 static void test_tpr_threshold(void) 4485 { 4486 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4487 u64 apic_virt_addr = vmcs_read(APIC_VIRT_ADDR); 4488 u64 threshold = vmcs_read(TPR_THRESHOLD); 4489 void *virtual_apic_page; 4490 4491 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) 4492 return; 4493 4494 virtual_apic_page = alloc_page(); 4495 memset(virtual_apic_page, 0xff, PAGE_SIZE); 4496 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 4497 4498 vmcs_write(CPU_EXEC_CTRL0, primary & ~(CPU_TPR_SHADOW | CPU_SECONDARY)); 4499 report_prefix_pushf("Use TPR shadow disabled, secondary controls disabled"); 4500 test_tpr_threshold_values(); 4501 report_prefix_pop(); 4502 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_TPR_SHADOW); 4503 report_prefix_pushf("Use TPR shadow enabled, secondary controls disabled"); 4504 test_tpr_threshold_values(); 4505 report_prefix_pop(); 4506 4507 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4508 (ctrl_cpu_rev[1].clr & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 4509 goto out; 4510 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4511 4512 if (ctrl_cpu_rev[1].clr & CPU_VINTD) { 4513 vmcs_write(CPU_EXEC_CTRL1, CPU_VINTD); 4514 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4515 test_tpr_threshold_values(); 4516 report_prefix_pop(); 4517 4518 vmcs_write(CPU_EXEC_CTRL0, 4519 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4520 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4521 test_tpr_threshold_values(); 4522 report_prefix_pop(); 4523 } 4524 4525 if (ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES) { 4526 vmcs_write(CPU_EXEC_CTRL0, 4527 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4528 vmcs_write(CPU_EXEC_CTRL1, CPU_VIRT_APIC_ACCESSES); 4529 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4530 test_tpr_threshold_values(); 4531 report_prefix_pop(); 4532 4533 vmcs_write(CPU_EXEC_CTRL0, 4534 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4535 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4536 test_tpr_threshold_values(); 4537 report_prefix_pop(); 4538 } 4539 4540 if ((ctrl_cpu_rev[1].clr & 4541 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) == 4542 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) { 4543 vmcs_write(CPU_EXEC_CTRL0, 4544 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4545 vmcs_write(CPU_EXEC_CTRL1, 4546 CPU_VINTD | CPU_VIRT_APIC_ACCESSES); 4547 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4548 test_tpr_threshold_values(); 4549 report_prefix_pop(); 4550 4551 vmcs_write(CPU_EXEC_CTRL0, 4552 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4553 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4554 test_tpr_threshold_values(); 4555 report_prefix_pop(); 4556 } 4557 4558 vmcs_write(CPU_EXEC_CTRL1, secondary); 4559 out: 4560 vmcs_write(TPR_THRESHOLD, threshold); 4561 vmcs_write(APIC_VIRT_ADDR, apic_virt_addr); 4562 vmcs_write(CPU_EXEC_CTRL0, primary); 4563 } 4564 4565 /* 4566 * This test verifies the following two vmentry checks: 4567 * 4568 * If the "NMI exiting" VM-execution control is 0, "Virtual NMIs" 4569 * VM-execution control must be 0. 4570 * [Intel SDM] 4571 * 4572 * If the “virtual NMIs” VM-execution control is 0, the “NMI-window 4573 * exiting” VM-execution control must be 0. 4574 * [Intel SDM] 4575 */ 4576 static void test_nmi_ctrls(void) 4577 { 4578 u32 pin_ctrls, cpu_ctrls0, test_pin_ctrls, test_cpu_ctrls0; 4579 4580 if ((ctrl_pin_rev.clr & (PIN_NMI | PIN_VIRT_NMI)) != 4581 (PIN_NMI | PIN_VIRT_NMI)) { 4582 printf("NMI exiting and Virtual NMIs are not supported !\n"); 4583 return; 4584 } 4585 4586 /* Save the controls so that we can restore them after our tests */ 4587 pin_ctrls = vmcs_read(PIN_CONTROLS); 4588 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 4589 4590 test_pin_ctrls = pin_ctrls & ~(PIN_NMI | PIN_VIRT_NMI); 4591 test_cpu_ctrls0 = cpu_ctrls0 & ~CPU_NMI_WINDOW; 4592 4593 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4594 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs disabled"); 4595 test_vmx_valid_controls(); 4596 report_prefix_pop(); 4597 4598 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_VIRT_NMI); 4599 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs enabled"); 4600 test_vmx_invalid_controls(); 4601 report_prefix_pop(); 4602 4603 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4604 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs enabled"); 4605 test_vmx_valid_controls(); 4606 report_prefix_pop(); 4607 4608 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_NMI); 4609 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs disabled"); 4610 test_vmx_valid_controls(); 4611 report_prefix_pop(); 4612 4613 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 4614 report_info("NMI-window exiting is not supported, skipping..."); 4615 goto done; 4616 } 4617 4618 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4619 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4620 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting enabled"); 4621 test_vmx_invalid_controls(); 4622 report_prefix_pop(); 4623 4624 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4625 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4626 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting disabled"); 4627 test_vmx_valid_controls(); 4628 report_prefix_pop(); 4629 4630 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4631 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4632 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting enabled"); 4633 test_vmx_valid_controls(); 4634 report_prefix_pop(); 4635 4636 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4637 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4638 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting disabled"); 4639 test_vmx_valid_controls(); 4640 report_prefix_pop(); 4641 4642 /* Restore the controls to their original values */ 4643 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 4644 done: 4645 vmcs_write(PIN_CONTROLS, pin_ctrls); 4646 } 4647 4648 static void test_eptp_ad_bit(u64 eptp, bool ctrl) 4649 { 4650 vmcs_write(EPTP, eptp); 4651 report_prefix_pushf("Enable-EPT enabled; EPT accessed and dirty flag %s", 4652 (eptp & EPTP_AD_FLAG) ? "1": "0"); 4653 if (ctrl) 4654 test_vmx_valid_controls(); 4655 else 4656 test_vmx_invalid_controls(); 4657 report_prefix_pop(); 4658 4659 } 4660 4661 /* 4662 * 1. If the "enable EPT" VM-execution control is 1, the "EPTP VM-execution" 4663 * control field must satisfy the following checks: 4664 * 4665 * - The EPT memory type (bits 2:0) must be a value supported by the 4666 * processor as indicated in the IA32_VMX_EPT_VPID_CAP MSR. 4667 * - Bits 5:3 (1 less than the EPT page-walk length) must be 3, 4668 * indicating an EPT page-walk length of 4. 4669 * - Bit 6 (enable bit for accessed and dirty flags for EPT) must be 4670 * 0 if bit 21 of the IA32_VMX_EPT_VPID_CAP MSR is read as 0, 4671 * indicating that the processor does not support accessed and dirty 4672 * dirty flags for EPT. 4673 * - Reserved bits 11:7 and 63:N (where N is the processor's 4674 * physical-address width) must all be 0. 4675 * 4676 * 2. If the "unrestricted guest" VM-execution control is 1, the 4677 * "enable EPT" VM-execution control must also be 1. 4678 */ 4679 static void test_ept_eptp(void) 4680 { 4681 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4682 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4683 u64 eptp_saved = vmcs_read(EPTP); 4684 u32 primary = primary_saved; 4685 u32 secondary = secondary_saved; 4686 u64 msr, eptp = eptp_saved; 4687 bool un_cache = false; 4688 bool wr_bk = false; 4689 bool ctrl; 4690 u32 i, maxphysaddr; 4691 u64 j, resv_bits_mask = 0; 4692 4693 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4694 (ctrl_cpu_rev[1].clr & CPU_EPT))) { 4695 printf("\"CPU secondary\" and/or \"enable EPT\" execution controls are not supported !\n"); 4696 return; 4697 } 4698 4699 /* 4700 * Memory type (bits 2:0) 4701 */ 4702 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 4703 if (msr & EPT_CAP_UC) 4704 un_cache = true; 4705 if (msr & EPT_CAP_WB) 4706 wr_bk = true; 4707 4708 primary |= CPU_SECONDARY; 4709 vmcs_write(CPU_EXEC_CTRL0, primary); 4710 secondary |= CPU_EPT; 4711 vmcs_write(CPU_EXEC_CTRL1, secondary); 4712 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4713 (3ul << EPTP_PG_WALK_LEN_SHIFT); 4714 vmcs_write(EPTP, eptp); 4715 4716 for (i = 0; i < 8; i++) { 4717 if (i == 0) { 4718 if (un_cache) { 4719 report_info("EPT paging structure memory-type is Un-cacheable\n"); 4720 ctrl = true; 4721 } else { 4722 ctrl = false; 4723 } 4724 } else if (i == 6) { 4725 if (wr_bk) { 4726 report_info("EPT paging structure memory-type is Write-back\n"); 4727 ctrl = true; 4728 } else { 4729 ctrl = false; 4730 } 4731 } else { 4732 ctrl = false; 4733 } 4734 4735 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | i; 4736 vmcs_write(EPTP, eptp); 4737 report_prefix_pushf("Enable-EPT enabled; EPT memory type %lu", 4738 eptp & EPT_MEM_TYPE_MASK); 4739 if (ctrl) 4740 test_vmx_valid_controls(); 4741 else 4742 test_vmx_invalid_controls(); 4743 report_prefix_pop(); 4744 } 4745 4746 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | 6ul; 4747 4748 /* 4749 * Page walk length (bits 5:3) 4750 */ 4751 for (i = 0; i < 8; i++) { 4752 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4753 (i << EPTP_PG_WALK_LEN_SHIFT); 4754 if (i == 3) 4755 ctrl = true; 4756 else 4757 ctrl = false; 4758 4759 vmcs_write(EPTP, eptp); 4760 report_prefix_pushf("Enable-EPT enabled; EPT page walk length %lu", 4761 eptp & EPTP_PG_WALK_LEN_MASK); 4762 if (ctrl) 4763 test_vmx_valid_controls(); 4764 else 4765 test_vmx_invalid_controls(); 4766 report_prefix_pop(); 4767 } 4768 4769 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4770 3ul << EPTP_PG_WALK_LEN_SHIFT; 4771 4772 /* 4773 * Accessed and dirty flag (bit 6) 4774 */ 4775 if (msr & EPT_CAP_AD_FLAG) { 4776 report_info("Processor supports accessed and dirty flag"); 4777 eptp &= ~EPTP_AD_FLAG; 4778 test_eptp_ad_bit(eptp, true); 4779 4780 eptp |= EPTP_AD_FLAG; 4781 test_eptp_ad_bit(eptp, true); 4782 } else { 4783 report_info("Processor does not supports accessed and dirty flag"); 4784 eptp &= ~EPTP_AD_FLAG; 4785 test_eptp_ad_bit(eptp, true); 4786 4787 eptp |= EPTP_AD_FLAG; 4788 test_eptp_ad_bit(eptp, false); 4789 } 4790 4791 /* 4792 * Reserved bits [11:7] and [63:N] 4793 */ 4794 for (i = 0; i < 32; i++) { 4795 eptp = (eptp & 4796 ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)) | 4797 (i << EPTP_RESERV_BITS_SHIFT); 4798 vmcs_write(EPTP, eptp); 4799 report_prefix_pushf("Enable-EPT enabled; reserved bits [11:7] %lu", 4800 (eptp >> EPTP_RESERV_BITS_SHIFT) & 4801 EPTP_RESERV_BITS_MASK); 4802 if (i == 0) 4803 test_vmx_valid_controls(); 4804 else 4805 test_vmx_invalid_controls(); 4806 report_prefix_pop(); 4807 } 4808 4809 eptp = (eptp & ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)); 4810 4811 maxphysaddr = cpuid_maxphyaddr(); 4812 for (i = 0; i < (63 - maxphysaddr + 1); i++) { 4813 resv_bits_mask |= 1ul << i; 4814 } 4815 4816 for (j = maxphysaddr - 1; j <= 63; j++) { 4817 eptp = (eptp & ~(resv_bits_mask << maxphysaddr)) | 4818 (j < maxphysaddr ? 0 : 1ul << j); 4819 vmcs_write(EPTP, eptp); 4820 report_prefix_pushf("Enable-EPT enabled; reserved bits [63:N] %lu", 4821 (eptp >> maxphysaddr) & resv_bits_mask); 4822 if (j < maxphysaddr) 4823 test_vmx_valid_controls(); 4824 else 4825 test_vmx_invalid_controls(); 4826 report_prefix_pop(); 4827 } 4828 4829 secondary &= ~(CPU_EPT | CPU_URG); 4830 vmcs_write(CPU_EXEC_CTRL1, secondary); 4831 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest disabled"); 4832 test_vmx_valid_controls(); 4833 report_prefix_pop(); 4834 4835 if (!(ctrl_cpu_rev[1].clr & CPU_URG)) 4836 goto skip_unrestricted_guest; 4837 4838 secondary |= CPU_URG; 4839 vmcs_write(CPU_EXEC_CTRL1, secondary); 4840 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest enabled"); 4841 test_vmx_invalid_controls(); 4842 report_prefix_pop(); 4843 4844 secondary |= CPU_EPT; 4845 setup_dummy_ept(); 4846 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest enabled"); 4847 test_vmx_valid_controls(); 4848 report_prefix_pop(); 4849 4850 skip_unrestricted_guest: 4851 secondary &= ~CPU_URG; 4852 vmcs_write(CPU_EXEC_CTRL1, secondary); 4853 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest disabled"); 4854 test_vmx_valid_controls(); 4855 report_prefix_pop(); 4856 4857 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4858 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4859 vmcs_write(EPTP, eptp_saved); 4860 } 4861 4862 /* 4863 * If the 'enable PML' VM-execution control is 1, the 'enable EPT' 4864 * VM-execution control must also be 1. In addition, the PML address 4865 * must satisfy the following checks: 4866 * 4867 * * Bits 11:0 of the address must be 0. 4868 * * The address should not set any bits beyond the processor's 4869 * physical-address width. 4870 * 4871 * [Intel SDM] 4872 */ 4873 static void test_pml(void) 4874 { 4875 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4876 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4877 u32 primary = primary_saved; 4878 u32 secondary = secondary_saved; 4879 4880 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4881 (ctrl_cpu_rev[1].clr & CPU_EPT) && (ctrl_cpu_rev[1].clr & CPU_PML))) { 4882 printf("\"Secondary execution\" control or \"enable EPT\" control or \"enable PML\" control is not supported !\n"); 4883 return; 4884 } 4885 4886 primary |= CPU_SECONDARY; 4887 vmcs_write(CPU_EXEC_CTRL0, primary); 4888 secondary &= ~(CPU_PML | CPU_EPT); 4889 vmcs_write(CPU_EXEC_CTRL1, secondary); 4890 report_prefix_pushf("enable-PML disabled, enable-EPT disabled"); 4891 test_vmx_valid_controls(); 4892 report_prefix_pop(); 4893 4894 secondary |= CPU_PML; 4895 vmcs_write(CPU_EXEC_CTRL1, secondary); 4896 report_prefix_pushf("enable-PML enabled, enable-EPT disabled"); 4897 test_vmx_invalid_controls(); 4898 report_prefix_pop(); 4899 4900 secondary |= CPU_EPT; 4901 setup_dummy_ept(); 4902 report_prefix_pushf("enable-PML enabled, enable-EPT enabled"); 4903 test_vmx_valid_controls(); 4904 report_prefix_pop(); 4905 4906 secondary &= ~CPU_PML; 4907 vmcs_write(CPU_EXEC_CTRL1, secondary); 4908 report_prefix_pushf("enable-PML disabled, enable EPT enabled"); 4909 test_vmx_valid_controls(); 4910 report_prefix_pop(); 4911 4912 test_vmcs_addr_reference(CPU_PML, PMLADDR, "PML address", "PML", 4913 PAGE_SIZE, false, false); 4914 4915 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4916 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4917 } 4918 4919 /* 4920 * If the "activate VMX-preemption timer" VM-execution control is 0, the 4921 * the "save VMX-preemption timer value" VM-exit control must also be 0. 4922 * 4923 * [Intel SDM] 4924 */ 4925 static void test_vmx_preemption_timer(void) 4926 { 4927 u32 saved_pin = vmcs_read(PIN_CONTROLS); 4928 u32 saved_exit = vmcs_read(EXI_CONTROLS); 4929 u32 pin = saved_pin; 4930 u32 exit = saved_exit; 4931 4932 if (!((ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) || 4933 (ctrl_pin_rev.clr & PIN_PREEMPT))) { 4934 printf("\"Save-VMX-preemption-timer\" control and/or \"Enable-VMX-preemption-timer\" control is not supported\n"); 4935 return; 4936 } 4937 4938 pin |= PIN_PREEMPT; 4939 vmcs_write(PIN_CONTROLS, pin); 4940 exit &= ~EXI_SAVE_PREEMPT; 4941 vmcs_write(EXI_CONTROLS, exit); 4942 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer disabled"); 4943 test_vmx_valid_controls(); 4944 report_prefix_pop(); 4945 4946 exit |= EXI_SAVE_PREEMPT; 4947 vmcs_write(EXI_CONTROLS, exit); 4948 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer enabled"); 4949 test_vmx_valid_controls(); 4950 report_prefix_pop(); 4951 4952 pin &= ~PIN_PREEMPT; 4953 vmcs_write(PIN_CONTROLS, pin); 4954 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer enabled"); 4955 test_vmx_invalid_controls(); 4956 report_prefix_pop(); 4957 4958 exit &= ~EXI_SAVE_PREEMPT; 4959 vmcs_write(EXI_CONTROLS, exit); 4960 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer disabled"); 4961 test_vmx_valid_controls(); 4962 report_prefix_pop(); 4963 4964 vmcs_write(PIN_CONTROLS, saved_pin); 4965 vmcs_write(EXI_CONTROLS, saved_exit); 4966 } 4967 4968 extern unsigned char test_mtf1; 4969 extern unsigned char test_mtf2; 4970 extern unsigned char test_mtf3; 4971 extern unsigned char test_mtf4; 4972 4973 static void test_mtf_guest(void) 4974 { 4975 asm ("vmcall;\n\t" 4976 "out %al, $0x80;\n\t" 4977 "test_mtf1:\n\t" 4978 "vmcall;\n\t" 4979 "out %al, $0x80;\n\t" 4980 "test_mtf2:\n\t" 4981 /* 4982 * Prepare for the 'MOV CR3' test. Attempt to induce a 4983 * general-protection fault by moving a non-canonical address into 4984 * CR3. The 'MOV CR3' instruction does not take an imm64 operand, 4985 * so we must MOV the desired value into a register first. 4986 * 4987 * MOV RAX is done before the VMCALL such that MTF is only enabled 4988 * for the instruction under test. 4989 */ 4990 "mov $0x8000000000000000, %rax;\n\t" 4991 "vmcall;\n\t" 4992 "mov %rax, %cr3;\n\t" 4993 "test_mtf3:\n\t" 4994 "vmcall;\n\t" 4995 /* 4996 * ICEBP/INT1 instruction. Though the instruction is now 4997 * documented, don't rely on assemblers enumerating the 4998 * instruction. Resort to hand assembly. 4999 */ 5000 ".byte 0xf1;\n\t" 5001 "vmcall;\n\t" 5002 "test_mtf4:\n\t" 5003 "mov $0, %eax;\n\t"); 5004 } 5005 5006 static void test_mtf_gp_handler(struct ex_regs *regs) 5007 { 5008 regs->rip = (unsigned long) &test_mtf3; 5009 } 5010 5011 static void test_mtf_db_handler(struct ex_regs *regs) 5012 { 5013 } 5014 5015 static void enable_mtf(void) 5016 { 5017 u32 ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 5018 5019 vmcs_write(CPU_EXEC_CTRL0, ctrl0 | CPU_MTF); 5020 } 5021 5022 static void disable_mtf(void) 5023 { 5024 u32 ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 5025 5026 vmcs_write(CPU_EXEC_CTRL0, ctrl0 & ~CPU_MTF); 5027 } 5028 5029 static void enable_tf(void) 5030 { 5031 unsigned long rflags = vmcs_read(GUEST_RFLAGS); 5032 5033 vmcs_write(GUEST_RFLAGS, rflags | X86_EFLAGS_TF); 5034 } 5035 5036 static void disable_tf(void) 5037 { 5038 unsigned long rflags = vmcs_read(GUEST_RFLAGS); 5039 5040 vmcs_write(GUEST_RFLAGS, rflags & ~X86_EFLAGS_TF); 5041 } 5042 5043 static void report_mtf(const char *insn_name, unsigned long exp_rip) 5044 { 5045 unsigned long rip = vmcs_read(GUEST_RIP); 5046 5047 assert_exit_reason(VMX_MTF); 5048 report(rip == exp_rip, "MTF VM-exit after %s. RIP: 0x%lx (expected 0x%lx)", 5049 insn_name, rip, exp_rip); 5050 } 5051 5052 static void vmx_mtf_test(void) 5053 { 5054 unsigned long pending_dbg; 5055 handler old_gp, old_db; 5056 5057 if (!(ctrl_cpu_rev[0].clr & CPU_MTF)) { 5058 printf("CPU does not support the 'monitor trap flag' processor-based VM-execution control.\n"); 5059 return; 5060 } 5061 5062 test_set_guest(test_mtf_guest); 5063 5064 /* Expect an MTF VM-exit after OUT instruction */ 5065 enter_guest(); 5066 skip_exit_vmcall(); 5067 5068 enable_mtf(); 5069 enter_guest(); 5070 report_mtf("OUT", (unsigned long) &test_mtf1); 5071 disable_mtf(); 5072 5073 /* 5074 * Concurrent #DB trap and MTF on instruction boundary. Expect MTF 5075 * VM-exit with populated 'pending debug exceptions' VMCS field. 5076 */ 5077 enter_guest(); 5078 skip_exit_vmcall(); 5079 5080 enable_mtf(); 5081 enable_tf(); 5082 5083 enter_guest(); 5084 report_mtf("OUT", (unsigned long) &test_mtf2); 5085 pending_dbg = vmcs_read(GUEST_PENDING_DEBUG); 5086 report(pending_dbg & DR_STEP, 5087 "'pending debug exceptions' field after MTF VM-exit: 0x%lx (expected 0x%lx)", 5088 pending_dbg, (unsigned long) DR_STEP); 5089 5090 disable_mtf(); 5091 disable_tf(); 5092 vmcs_write(GUEST_PENDING_DEBUG, 0); 5093 5094 /* 5095 * #GP exception takes priority over MTF. Expect MTF VM-exit with RIP 5096 * advanced to first instruction of #GP handler. 5097 */ 5098 enter_guest(); 5099 skip_exit_vmcall(); 5100 5101 old_gp = handle_exception(GP_VECTOR, test_mtf_gp_handler); 5102 5103 enable_mtf(); 5104 enter_guest(); 5105 report_mtf("MOV CR3", (unsigned long) get_idt_addr(&boot_idt[GP_VECTOR])); 5106 disable_mtf(); 5107 5108 /* 5109 * Concurrent MTF and privileged software exception (i.e. ICEBP/INT1). 5110 * MTF should follow the delivery of #DB trap, though the SDM doesn't 5111 * provide clear indication of the relative priority. 5112 */ 5113 enter_guest(); 5114 skip_exit_vmcall(); 5115 5116 handle_exception(GP_VECTOR, old_gp); 5117 old_db = handle_exception(DB_VECTOR, test_mtf_db_handler); 5118 5119 enable_mtf(); 5120 enter_guest(); 5121 report_mtf("INT1", (unsigned long) get_idt_addr(&boot_idt[DB_VECTOR])); 5122 disable_mtf(); 5123 5124 enter_guest(); 5125 skip_exit_vmcall(); 5126 handle_exception(DB_VECTOR, old_db); 5127 vmcs_write(ENT_INTR_INFO, INTR_INFO_VALID_MASK | INTR_TYPE_OTHER_EVENT); 5128 enter_guest(); 5129 report_mtf("injected MTF", (unsigned long) &test_mtf4); 5130 enter_guest(); 5131 } 5132 5133 /* 5134 * Tests for VM-execution control fields 5135 */ 5136 static void test_vm_execution_ctls(void) 5137 { 5138 test_pin_based_ctls(); 5139 test_primary_processor_based_ctls(); 5140 test_secondary_processor_based_ctls(); 5141 test_cr3_targets(); 5142 test_io_bitmaps(); 5143 test_msr_bitmap(); 5144 test_apic_ctls(); 5145 test_tpr_threshold(); 5146 test_nmi_ctrls(); 5147 test_pml(); 5148 test_vpid(); 5149 test_ept_eptp(); 5150 test_vmx_preemption_timer(); 5151 } 5152 5153 /* 5154 * The following checks are performed for the VM-entry MSR-load address if 5155 * the VM-entry MSR-load count field is non-zero: 5156 * 5157 * - The lower 4 bits of the VM-entry MSR-load address must be 0. 5158 * The address should not set any bits beyond the processor’s 5159 * physical-address width. 5160 * 5161 * - The address of the last byte in the VM-entry MSR-load area 5162 * should not set any bits beyond the processor’s physical-address 5163 * width. The address of this last byte is VM-entry MSR-load address 5164 * + (MSR count * 16) - 1. (The arithmetic used for the computation 5165 * uses more bits than the processor’s physical-address width.) 5166 * 5167 * 5168 * [Intel SDM] 5169 */ 5170 static void test_entry_msr_load(void) 5171 { 5172 entry_msr_load = alloc_page(); 5173 u64 tmp; 5174 u32 entry_msr_ld_cnt = 1; 5175 int i; 5176 u32 addr_len = 64; 5177 5178 vmcs_write(ENT_MSR_LD_CNT, entry_msr_ld_cnt); 5179 5180 /* Check first 4 bits of VM-entry MSR-load address */ 5181 for (i = 0; i < 4; i++) { 5182 tmp = (u64)entry_msr_load | 1ull << i; 5183 vmcs_write(ENTER_MSR_LD_ADDR, tmp); 5184 report_prefix_pushf("VM-entry MSR-load addr [4:0] %lx", 5185 tmp & 0xf); 5186 test_vmx_invalid_controls(); 5187 report_prefix_pop(); 5188 } 5189 5190 if (basic.val & (1ul << 48)) 5191 addr_len = 32; 5192 5193 test_vmcs_addr_values("VM-entry-MSR-load address", 5194 ENTER_MSR_LD_ADDR, 16, false, false, 5195 4, addr_len - 1); 5196 5197 /* 5198 * Check last byte of VM-entry MSR-load address 5199 */ 5200 entry_msr_load = (struct vmx_msr_entry *)((u64)entry_msr_load & ~0xf); 5201 5202 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 5203 i < 64; i++) { 5204 tmp = ((u64)entry_msr_load + entry_msr_ld_cnt * 16 - 1) | 5205 1ul << i; 5206 vmcs_write(ENTER_MSR_LD_ADDR, 5207 tmp - (entry_msr_ld_cnt * 16 - 1)); 5208 test_vmx_invalid_controls(); 5209 } 5210 5211 vmcs_write(ENT_MSR_LD_CNT, 2); 5212 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 5213 test_vmx_invalid_controls(); 5214 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 5215 test_vmx_valid_controls(); 5216 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 5217 test_vmx_valid_controls(); 5218 } 5219 5220 static struct vmx_state_area_test_data { 5221 u32 msr; 5222 u64 exp; 5223 bool enabled; 5224 } vmx_state_area_test_data; 5225 5226 static void guest_state_test_main(void) 5227 { 5228 u64 obs; 5229 struct vmx_state_area_test_data *data = &vmx_state_area_test_data; 5230 5231 while (1) { 5232 if (vmx_get_test_stage() == 2) 5233 break; 5234 5235 if (data->enabled) { 5236 obs = rdmsr(data->msr); 5237 report(data->exp == obs, 5238 "Guest state is 0x%lx (expected 0x%lx)", 5239 obs, data->exp); 5240 } 5241 5242 vmcall(); 5243 } 5244 5245 asm volatile("fnop"); 5246 } 5247 5248 static void test_guest_state(const char *test, bool xfail, u64 field, 5249 const char * field_name) 5250 { 5251 struct vmentry_result result; 5252 u8 abort_flags; 5253 5254 abort_flags = ABORT_ON_EARLY_VMENTRY_FAIL; 5255 if (!xfail) 5256 abort_flags = ABORT_ON_INVALID_GUEST_STATE; 5257 5258 __enter_guest(abort_flags, &result); 5259 5260 report(result.exit_reason.failed_vmentry == xfail && 5261 ((xfail && result.exit_reason.basic == VMX_FAIL_STATE) || 5262 (!xfail && result.exit_reason.basic == VMX_VMCALL)) && 5263 (!xfail || vmcs_read(EXI_QUALIFICATION) == ENTRY_FAIL_DEFAULT), 5264 "%s, %s %lx", test, field_name, field); 5265 5266 if (!result.exit_reason.failed_vmentry) 5267 skip_exit_insn(); 5268 } 5269 5270 /* 5271 * Tests for VM-entry control fields 5272 */ 5273 static void test_vm_entry_ctls(void) 5274 { 5275 test_invalid_event_injection(); 5276 test_entry_msr_load(); 5277 } 5278 5279 /* 5280 * The following checks are performed for the VM-exit MSR-store address if 5281 * the VM-exit MSR-store count field is non-zero: 5282 * 5283 * - The lower 4 bits of the VM-exit MSR-store address must be 0. 5284 * The address should not set any bits beyond the processor’s 5285 * physical-address width. 5286 * 5287 * - The address of the last byte in the VM-exit MSR-store area 5288 * should not set any bits beyond the processor’s physical-address 5289 * width. The address of this last byte is VM-exit MSR-store address 5290 * + (MSR count * 16) - 1. (The arithmetic used for the computation 5291 * uses more bits than the processor’s physical-address width.) 5292 * 5293 * If IA32_VMX_BASIC[48] is read as 1, neither address should set any bits 5294 * in the range 63:32. 5295 * 5296 * [Intel SDM] 5297 */ 5298 static void test_exit_msr_store(void) 5299 { 5300 exit_msr_store = alloc_page(); 5301 u64 tmp; 5302 u32 exit_msr_st_cnt = 1; 5303 int i; 5304 u32 addr_len = 64; 5305 5306 vmcs_write(EXI_MSR_ST_CNT, exit_msr_st_cnt); 5307 5308 /* Check first 4 bits of VM-exit MSR-store address */ 5309 for (i = 0; i < 4; i++) { 5310 tmp = (u64)exit_msr_store | 1ull << i; 5311 vmcs_write(EXIT_MSR_ST_ADDR, tmp); 5312 report_prefix_pushf("VM-exit MSR-store addr [4:0] %lx", 5313 tmp & 0xf); 5314 test_vmx_invalid_controls(); 5315 report_prefix_pop(); 5316 } 5317 5318 if (basic.val & (1ul << 48)) 5319 addr_len = 32; 5320 5321 test_vmcs_addr_values("VM-exit-MSR-store address", 5322 EXIT_MSR_ST_ADDR, 16, false, false, 5323 4, addr_len - 1); 5324 5325 /* 5326 * Check last byte of VM-exit MSR-store address 5327 */ 5328 exit_msr_store = (struct vmx_msr_entry *)((u64)exit_msr_store & ~0xf); 5329 5330 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 5331 i < 64; i++) { 5332 tmp = ((u64)exit_msr_store + exit_msr_st_cnt * 16 - 1) | 5333 1ul << i; 5334 vmcs_write(EXIT_MSR_ST_ADDR, 5335 tmp - (exit_msr_st_cnt * 16 - 1)); 5336 test_vmx_invalid_controls(); 5337 } 5338 5339 vmcs_write(EXI_MSR_ST_CNT, 2); 5340 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 5341 test_vmx_invalid_controls(); 5342 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 5343 test_vmx_valid_controls(); 5344 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 5345 test_vmx_valid_controls(); 5346 } 5347 5348 /* 5349 * Tests for VM-exit controls 5350 */ 5351 static void test_vm_exit_ctls(void) 5352 { 5353 test_exit_msr_store(); 5354 } 5355 5356 /* 5357 * Check that the virtual CPU checks all of the VMX controls as 5358 * documented in the Intel SDM. 5359 */ 5360 static void vmx_controls_test(void) 5361 { 5362 /* 5363 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 5364 * fail due to invalid guest state, should we make it that 5365 * far. 5366 */ 5367 vmcs_write(GUEST_RFLAGS, 0); 5368 5369 test_vm_execution_ctls(); 5370 test_vm_exit_ctls(); 5371 test_vm_entry_ctls(); 5372 } 5373 5374 struct apic_reg_virt_config { 5375 bool apic_register_virtualization; 5376 bool use_tpr_shadow; 5377 bool virtualize_apic_accesses; 5378 bool virtualize_x2apic_mode; 5379 bool activate_secondary_controls; 5380 }; 5381 5382 struct apic_reg_test { 5383 const char *name; 5384 struct apic_reg_virt_config apic_reg_virt_config; 5385 }; 5386 5387 struct apic_reg_virt_expectation { 5388 enum Reason rd_exit_reason; 5389 enum Reason wr_exit_reason; 5390 u32 val; 5391 u32 (*virt_fn)(u32); 5392 5393 /* 5394 * If false, accessing the APIC access address from L2 is treated as a 5395 * normal memory operation, rather than triggering virtualization. 5396 */ 5397 bool virtualize_apic_accesses; 5398 }; 5399 5400 static u32 apic_virt_identity(u32 val) 5401 { 5402 return val; 5403 } 5404 5405 static u32 apic_virt_nibble1(u32 val) 5406 { 5407 return val & 0xf0; 5408 } 5409 5410 static u32 apic_virt_byte3(u32 val) 5411 { 5412 return val & (0xff << 24); 5413 } 5414 5415 static bool apic_reg_virt_exit_expectation( 5416 u32 reg, struct apic_reg_virt_config *config, 5417 struct apic_reg_virt_expectation *expectation) 5418 { 5419 /* Good configs, where some L2 APIC accesses are virtualized. */ 5420 bool virtualize_apic_accesses_only = 5421 config->virtualize_apic_accesses && 5422 !config->use_tpr_shadow && 5423 !config->apic_register_virtualization && 5424 !config->virtualize_x2apic_mode && 5425 config->activate_secondary_controls; 5426 bool virtualize_apic_accesses_and_use_tpr_shadow = 5427 config->virtualize_apic_accesses && 5428 config->use_tpr_shadow && 5429 !config->apic_register_virtualization && 5430 !config->virtualize_x2apic_mode && 5431 config->activate_secondary_controls; 5432 bool apic_register_virtualization = 5433 config->virtualize_apic_accesses && 5434 config->use_tpr_shadow && 5435 config->apic_register_virtualization && 5436 !config->virtualize_x2apic_mode && 5437 config->activate_secondary_controls; 5438 5439 expectation->val = MAGIC_VAL_1; 5440 expectation->virt_fn = apic_virt_identity; 5441 expectation->virtualize_apic_accesses = 5442 config->virtualize_apic_accesses && 5443 config->activate_secondary_controls; 5444 if (virtualize_apic_accesses_only) { 5445 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5446 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5447 } else if (virtualize_apic_accesses_and_use_tpr_shadow) { 5448 switch (reg) { 5449 case APIC_TASKPRI: 5450 expectation->rd_exit_reason = VMX_VMCALL; 5451 expectation->wr_exit_reason = VMX_VMCALL; 5452 expectation->virt_fn = apic_virt_nibble1; 5453 break; 5454 default: 5455 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5456 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5457 } 5458 } else if (apic_register_virtualization) { 5459 expectation->rd_exit_reason = VMX_VMCALL; 5460 5461 switch (reg) { 5462 case APIC_ID: 5463 case APIC_EOI: 5464 case APIC_LDR: 5465 case APIC_DFR: 5466 case APIC_SPIV: 5467 case APIC_ESR: 5468 case APIC_ICR: 5469 case APIC_LVTT: 5470 case APIC_LVTTHMR: 5471 case APIC_LVTPC: 5472 case APIC_LVT0: 5473 case APIC_LVT1: 5474 case APIC_LVTERR: 5475 case APIC_TMICT: 5476 case APIC_TDCR: 5477 expectation->wr_exit_reason = VMX_APIC_WRITE; 5478 break; 5479 case APIC_LVR: 5480 case APIC_ISR ... APIC_ISR + 0x70: 5481 case APIC_TMR ... APIC_TMR + 0x70: 5482 case APIC_IRR ... APIC_IRR + 0x70: 5483 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5484 break; 5485 case APIC_TASKPRI: 5486 expectation->wr_exit_reason = VMX_VMCALL; 5487 expectation->virt_fn = apic_virt_nibble1; 5488 break; 5489 case APIC_ICR2: 5490 expectation->wr_exit_reason = VMX_VMCALL; 5491 expectation->virt_fn = apic_virt_byte3; 5492 break; 5493 default: 5494 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5495 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5496 } 5497 } else if (!expectation->virtualize_apic_accesses) { 5498 /* 5499 * No APIC registers are directly virtualized. This includes 5500 * VTPR, which can be virtualized through MOV to/from CR8 via 5501 * the use TPR shadow control, but not through directly 5502 * accessing VTPR. 5503 */ 5504 expectation->rd_exit_reason = VMX_VMCALL; 5505 expectation->wr_exit_reason = VMX_VMCALL; 5506 } else { 5507 printf("Cannot parse APIC register virtualization config:\n" 5508 "\tvirtualize_apic_accesses: %d\n" 5509 "\tuse_tpr_shadow: %d\n" 5510 "\tapic_register_virtualization: %d\n" 5511 "\tvirtualize_x2apic_mode: %d\n" 5512 "\tactivate_secondary_controls: %d\n", 5513 config->virtualize_apic_accesses, 5514 config->use_tpr_shadow, 5515 config->apic_register_virtualization, 5516 config->virtualize_x2apic_mode, 5517 config->activate_secondary_controls); 5518 5519 return false; 5520 } 5521 5522 return true; 5523 } 5524 5525 struct apic_reg_test apic_reg_tests[] = { 5526 /* Good configs, where some L2 APIC accesses are virtualized. */ 5527 { 5528 .name = "Virtualize APIC accesses", 5529 .apic_reg_virt_config = { 5530 .virtualize_apic_accesses = true, 5531 .use_tpr_shadow = false, 5532 .apic_register_virtualization = false, 5533 .virtualize_x2apic_mode = false, 5534 .activate_secondary_controls = true, 5535 }, 5536 }, 5537 { 5538 .name = "Virtualize APIC accesses + Use TPR shadow", 5539 .apic_reg_virt_config = { 5540 .virtualize_apic_accesses = true, 5541 .use_tpr_shadow = true, 5542 .apic_register_virtualization = false, 5543 .virtualize_x2apic_mode = false, 5544 .activate_secondary_controls = true, 5545 }, 5546 }, 5547 { 5548 .name = "APIC-register virtualization", 5549 .apic_reg_virt_config = { 5550 .virtualize_apic_accesses = true, 5551 .use_tpr_shadow = true, 5552 .apic_register_virtualization = true, 5553 .virtualize_x2apic_mode = false, 5554 .activate_secondary_controls = true, 5555 }, 5556 }, 5557 5558 /* 5559 * Test that the secondary processor-based VM-execution controls are 5560 * correctly ignored when "activate secondary controls" is disabled. 5561 */ 5562 { 5563 .name = "Activate secondary controls off", 5564 .apic_reg_virt_config = { 5565 .virtualize_apic_accesses = true, 5566 .use_tpr_shadow = false, 5567 .apic_register_virtualization = true, 5568 .virtualize_x2apic_mode = true, 5569 .activate_secondary_controls = false, 5570 }, 5571 }, 5572 { 5573 .name = "Activate secondary controls off + Use TPR shadow", 5574 .apic_reg_virt_config = { 5575 .virtualize_apic_accesses = true, 5576 .use_tpr_shadow = true, 5577 .apic_register_virtualization = true, 5578 .virtualize_x2apic_mode = true, 5579 .activate_secondary_controls = false, 5580 }, 5581 }, 5582 5583 /* 5584 * Test that the APIC access address is treated like an arbitrary memory 5585 * address when "virtualize APIC accesses" is disabled. 5586 */ 5587 { 5588 .name = "Virtualize APIC accesses off + Use TPR shadow", 5589 .apic_reg_virt_config = { 5590 .virtualize_apic_accesses = false, 5591 .use_tpr_shadow = true, 5592 .apic_register_virtualization = true, 5593 .virtualize_x2apic_mode = true, 5594 .activate_secondary_controls = true, 5595 }, 5596 }, 5597 5598 /* 5599 * Test that VM entry fails due to invalid controls when 5600 * "APIC-register virtualization" is enabled while "use TPR shadow" is 5601 * disabled. 5602 */ 5603 { 5604 .name = "APIC-register virtualization + Use TPR shadow off", 5605 .apic_reg_virt_config = { 5606 .virtualize_apic_accesses = true, 5607 .use_tpr_shadow = false, 5608 .apic_register_virtualization = true, 5609 .virtualize_x2apic_mode = false, 5610 .activate_secondary_controls = true, 5611 }, 5612 }, 5613 5614 /* 5615 * Test that VM entry fails due to invalid controls when 5616 * "Virtualize x2APIC mode" is enabled while "use TPR shadow" is 5617 * disabled. 5618 */ 5619 { 5620 .name = "Virtualize x2APIC mode + Use TPR shadow off", 5621 .apic_reg_virt_config = { 5622 .virtualize_apic_accesses = false, 5623 .use_tpr_shadow = false, 5624 .apic_register_virtualization = false, 5625 .virtualize_x2apic_mode = true, 5626 .activate_secondary_controls = true, 5627 }, 5628 }, 5629 { 5630 .name = "Virtualize x2APIC mode + Use TPR shadow off v2", 5631 .apic_reg_virt_config = { 5632 .virtualize_apic_accesses = false, 5633 .use_tpr_shadow = false, 5634 .apic_register_virtualization = true, 5635 .virtualize_x2apic_mode = true, 5636 .activate_secondary_controls = true, 5637 }, 5638 }, 5639 5640 /* 5641 * Test that VM entry fails due to invalid controls when 5642 * "virtualize x2APIC mode" is enabled while "virtualize APIC accesses" 5643 * is enabled. 5644 */ 5645 { 5646 .name = "Virtualize x2APIC mode + Virtualize APIC accesses", 5647 .apic_reg_virt_config = { 5648 .virtualize_apic_accesses = true, 5649 .use_tpr_shadow = true, 5650 .apic_register_virtualization = false, 5651 .virtualize_x2apic_mode = true, 5652 .activate_secondary_controls = true, 5653 }, 5654 }, 5655 { 5656 .name = "Virtualize x2APIC mode + Virtualize APIC accesses v2", 5657 .apic_reg_virt_config = { 5658 .virtualize_apic_accesses = true, 5659 .use_tpr_shadow = true, 5660 .apic_register_virtualization = true, 5661 .virtualize_x2apic_mode = true, 5662 .activate_secondary_controls = true, 5663 }, 5664 }, 5665 }; 5666 5667 enum Apic_op { 5668 APIC_OP_XAPIC_RD, 5669 APIC_OP_XAPIC_WR, 5670 TERMINATE, 5671 }; 5672 5673 static u32 vmx_xapic_read(u32 *apic_access_address, u32 reg) 5674 { 5675 return *(volatile u32 *)((uintptr_t)apic_access_address + reg); 5676 } 5677 5678 static void vmx_xapic_write(u32 *apic_access_address, u32 reg, u32 val) 5679 { 5680 *(volatile u32 *)((uintptr_t)apic_access_address + reg) = val; 5681 } 5682 5683 struct apic_reg_virt_guest_args { 5684 enum Apic_op op; 5685 u32 *apic_access_address; 5686 u32 reg; 5687 u32 val; 5688 bool check_rd; 5689 u32 (*virt_fn)(u32); 5690 } apic_reg_virt_guest_args; 5691 5692 static void apic_reg_virt_guest(void) 5693 { 5694 volatile struct apic_reg_virt_guest_args *args = 5695 &apic_reg_virt_guest_args; 5696 5697 for (;;) { 5698 enum Apic_op op = args->op; 5699 u32 *apic_access_address = args->apic_access_address; 5700 u32 reg = args->reg; 5701 u32 val = args->val; 5702 bool check_rd = args->check_rd; 5703 u32 (*virt_fn)(u32) = args->virt_fn; 5704 5705 if (op == TERMINATE) 5706 break; 5707 5708 if (op == APIC_OP_XAPIC_RD) { 5709 u32 ret = vmx_xapic_read(apic_access_address, reg); 5710 5711 if (check_rd) { 5712 u32 want = virt_fn(val); 5713 u32 got = virt_fn(ret); 5714 5715 report(got == want, 5716 "read 0x%x, expected 0x%x.", got, want); 5717 } 5718 } else if (op == APIC_OP_XAPIC_WR) { 5719 vmx_xapic_write(apic_access_address, reg, val); 5720 } 5721 5722 /* 5723 * The L1 should always execute a vmcall after it's done testing 5724 * an individual APIC operation. This helps to validate that the 5725 * L1 and L2 are in sync with each other, as expected. 5726 */ 5727 vmcall(); 5728 } 5729 } 5730 5731 static void test_xapic_rd( 5732 u32 reg, struct apic_reg_virt_expectation *expectation, 5733 u32 *apic_access_address, u32 *virtual_apic_page) 5734 { 5735 u32 val = expectation->val; 5736 u32 exit_reason_want = expectation->rd_exit_reason; 5737 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 5738 5739 report_prefix_pushf("xapic - reading 0x%03x", reg); 5740 5741 /* Configure guest to do an xapic read */ 5742 args->op = APIC_OP_XAPIC_RD; 5743 args->apic_access_address = apic_access_address; 5744 args->reg = reg; 5745 args->val = val; 5746 args->check_rd = exit_reason_want == VMX_VMCALL; 5747 args->virt_fn = expectation->virt_fn; 5748 5749 /* Setup virtual APIC page */ 5750 if (!expectation->virtualize_apic_accesses) { 5751 apic_access_address[apic_reg_index(reg)] = val; 5752 virtual_apic_page[apic_reg_index(reg)] = 0; 5753 } else if (exit_reason_want == VMX_VMCALL) { 5754 apic_access_address[apic_reg_index(reg)] = 0; 5755 virtual_apic_page[apic_reg_index(reg)] = val; 5756 } 5757 5758 /* Enter guest */ 5759 enter_guest(); 5760 5761 /* 5762 * Validate the behavior and 5763 * pass a magic value back to the guest. 5764 */ 5765 if (exit_reason_want == VMX_APIC_ACCESS) { 5766 u32 apic_page_offset = vmcs_read(EXI_QUALIFICATION) & 0xfff; 5767 5768 assert_exit_reason(exit_reason_want); 5769 report(apic_page_offset == reg, 5770 "got APIC access exit @ page offset 0x%03x, want 0x%03x", 5771 apic_page_offset, reg); 5772 skip_exit_insn(); 5773 5774 /* Reenter guest so it can consume/check rcx and exit again. */ 5775 enter_guest(); 5776 } else if (exit_reason_want != VMX_VMCALL) { 5777 report(false, "Oops, bad exit expectation: %u.", 5778 exit_reason_want); 5779 } 5780 5781 skip_exit_vmcall(); 5782 report_prefix_pop(); 5783 } 5784 5785 static void test_xapic_wr( 5786 u32 reg, struct apic_reg_virt_expectation *expectation, 5787 u32 *apic_access_address, u32 *virtual_apic_page) 5788 { 5789 u32 val = expectation->val; 5790 u32 exit_reason_want = expectation->wr_exit_reason; 5791 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 5792 bool virtualized = 5793 expectation->virtualize_apic_accesses && 5794 (exit_reason_want == VMX_APIC_WRITE || 5795 exit_reason_want == VMX_VMCALL); 5796 bool checked = false; 5797 5798 report_prefix_pushf("xapic - writing 0x%x to 0x%03x", val, reg); 5799 5800 /* Configure guest to do an xapic read */ 5801 args->op = APIC_OP_XAPIC_WR; 5802 args->apic_access_address = apic_access_address; 5803 args->reg = reg; 5804 args->val = val; 5805 5806 /* Setup virtual APIC page */ 5807 if (virtualized || !expectation->virtualize_apic_accesses) { 5808 apic_access_address[apic_reg_index(reg)] = 0; 5809 virtual_apic_page[apic_reg_index(reg)] = 0; 5810 } 5811 5812 /* Enter guest */ 5813 enter_guest(); 5814 5815 /* 5816 * Validate the behavior and 5817 * pass a magic value back to the guest. 5818 */ 5819 if (exit_reason_want == VMX_APIC_ACCESS) { 5820 u32 apic_page_offset = vmcs_read(EXI_QUALIFICATION) & 0xfff; 5821 5822 assert_exit_reason(exit_reason_want); 5823 report(apic_page_offset == reg, 5824 "got APIC access exit @ page offset 0x%03x, want 0x%03x", 5825 apic_page_offset, reg); 5826 skip_exit_insn(); 5827 5828 /* Reenter guest so it can consume/check rcx and exit again. */ 5829 enter_guest(); 5830 } else if (exit_reason_want == VMX_APIC_WRITE) { 5831 assert_exit_reason(exit_reason_want); 5832 report(virtual_apic_page[apic_reg_index(reg)] == val, 5833 "got APIC write exit @ page offset 0x%03x; val is 0x%x, want 0x%x", 5834 apic_reg_index(reg), 5835 virtual_apic_page[apic_reg_index(reg)], val); 5836 checked = true; 5837 5838 /* Reenter guest so it can consume/check rcx and exit again. */ 5839 enter_guest(); 5840 } else if (exit_reason_want != VMX_VMCALL) { 5841 report(false, "Oops, bad exit expectation: %u.", 5842 exit_reason_want); 5843 } 5844 5845 assert_exit_reason(VMX_VMCALL); 5846 if (virtualized && !checked) { 5847 u32 want = expectation->virt_fn(val); 5848 u32 got = virtual_apic_page[apic_reg_index(reg)]; 5849 got = expectation->virt_fn(got); 5850 5851 report(got == want, "exitless write; val is 0x%x, want 0x%x", 5852 got, want); 5853 } else if (!expectation->virtualize_apic_accesses && !checked) { 5854 u32 got = apic_access_address[apic_reg_index(reg)]; 5855 5856 report(got == val, 5857 "non-virtualized write; val is 0x%x, want 0x%x", got, 5858 val); 5859 } else if (!expectation->virtualize_apic_accesses && checked) { 5860 report(false, 5861 "Non-virtualized write was prematurely checked!"); 5862 } 5863 5864 skip_exit_vmcall(); 5865 report_prefix_pop(); 5866 } 5867 5868 enum Config_type { 5869 CONFIG_TYPE_GOOD, 5870 CONFIG_TYPE_UNSUPPORTED, 5871 CONFIG_TYPE_VMENTRY_FAILS_EARLY, 5872 }; 5873 5874 static enum Config_type configure_apic_reg_virt_test( 5875 struct apic_reg_virt_config *apic_reg_virt_config) 5876 { 5877 u32 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 5878 u32 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 5879 /* Configs where L2 entry fails early, due to invalid controls. */ 5880 bool use_tpr_shadow_incorrectly_off = 5881 !apic_reg_virt_config->use_tpr_shadow && 5882 (apic_reg_virt_config->apic_register_virtualization || 5883 apic_reg_virt_config->virtualize_x2apic_mode) && 5884 apic_reg_virt_config->activate_secondary_controls; 5885 bool virtualize_apic_accesses_incorrectly_on = 5886 apic_reg_virt_config->virtualize_apic_accesses && 5887 apic_reg_virt_config->virtualize_x2apic_mode && 5888 apic_reg_virt_config->activate_secondary_controls; 5889 bool vmentry_fails_early = 5890 use_tpr_shadow_incorrectly_off || 5891 virtualize_apic_accesses_incorrectly_on; 5892 5893 if (apic_reg_virt_config->activate_secondary_controls) { 5894 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 5895 printf("VM-execution control \"activate secondary controls\" NOT supported.\n"); 5896 return CONFIG_TYPE_UNSUPPORTED; 5897 } 5898 cpu_exec_ctrl0 |= CPU_SECONDARY; 5899 } else { 5900 cpu_exec_ctrl0 &= ~CPU_SECONDARY; 5901 } 5902 5903 if (apic_reg_virt_config->virtualize_apic_accesses) { 5904 if (!(ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES)) { 5905 printf("VM-execution control \"virtualize APIC accesses\" NOT supported.\n"); 5906 return CONFIG_TYPE_UNSUPPORTED; 5907 } 5908 cpu_exec_ctrl1 |= CPU_VIRT_APIC_ACCESSES; 5909 } else { 5910 cpu_exec_ctrl1 &= ~CPU_VIRT_APIC_ACCESSES; 5911 } 5912 5913 if (apic_reg_virt_config->use_tpr_shadow) { 5914 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) { 5915 printf("VM-execution control \"use TPR shadow\" NOT supported.\n"); 5916 return CONFIG_TYPE_UNSUPPORTED; 5917 } 5918 cpu_exec_ctrl0 |= CPU_TPR_SHADOW; 5919 } else { 5920 cpu_exec_ctrl0 &= ~CPU_TPR_SHADOW; 5921 } 5922 5923 if (apic_reg_virt_config->apic_register_virtualization) { 5924 if (!(ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT)) { 5925 printf("VM-execution control \"APIC-register virtualization\" NOT supported.\n"); 5926 return CONFIG_TYPE_UNSUPPORTED; 5927 } 5928 cpu_exec_ctrl1 |= CPU_APIC_REG_VIRT; 5929 } else { 5930 cpu_exec_ctrl1 &= ~CPU_APIC_REG_VIRT; 5931 } 5932 5933 if (apic_reg_virt_config->virtualize_x2apic_mode) { 5934 if (!(ctrl_cpu_rev[1].clr & CPU_VIRT_X2APIC)) { 5935 printf("VM-execution control \"virtualize x2APIC mode\" NOT supported.\n"); 5936 return CONFIG_TYPE_UNSUPPORTED; 5937 } 5938 cpu_exec_ctrl1 |= CPU_VIRT_X2APIC; 5939 } else { 5940 cpu_exec_ctrl1 &= ~CPU_VIRT_X2APIC; 5941 } 5942 5943 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 5944 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 5945 5946 if (vmentry_fails_early) 5947 return CONFIG_TYPE_VMENTRY_FAILS_EARLY; 5948 5949 return CONFIG_TYPE_GOOD; 5950 } 5951 5952 static bool cpu_has_apicv(void) 5953 { 5954 return ((ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT) && 5955 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 5956 (ctrl_pin_rev.clr & PIN_POST_INTR)); 5957 } 5958 5959 /* Validates APIC register access across valid virtualization configurations. */ 5960 static void apic_reg_virt_test(void) 5961 { 5962 u32 *apic_access_address; 5963 u32 *virtual_apic_page; 5964 u64 control; 5965 u64 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 5966 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 5967 int i; 5968 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 5969 5970 if (!cpu_has_apicv()) { 5971 report_skip(__func__); 5972 return; 5973 } 5974 5975 control = cpu_exec_ctrl1; 5976 control &= ~CPU_VINTD; 5977 vmcs_write(CPU_EXEC_CTRL1, control); 5978 5979 test_set_guest(apic_reg_virt_guest); 5980 5981 /* 5982 * From the SDM: The 1-setting of the "virtualize APIC accesses" 5983 * VM-execution is guaranteed to apply only if translations to the 5984 * APIC-access address use a 4-KByte page. 5985 */ 5986 apic_access_address = alloc_page(); 5987 force_4k_page(apic_access_address); 5988 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_address)); 5989 5990 virtual_apic_page = alloc_page(); 5991 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 5992 5993 for (i = 0; i < ARRAY_SIZE(apic_reg_tests); i++) { 5994 struct apic_reg_test *apic_reg_test = &apic_reg_tests[i]; 5995 struct apic_reg_virt_config *apic_reg_virt_config = 5996 &apic_reg_test->apic_reg_virt_config; 5997 enum Config_type config_type; 5998 u32 reg; 5999 6000 printf("--- %s test ---\n", apic_reg_test->name); 6001 config_type = 6002 configure_apic_reg_virt_test(apic_reg_virt_config); 6003 if (config_type == CONFIG_TYPE_UNSUPPORTED) { 6004 printf("Skip because of missing features.\n"); 6005 continue; 6006 } 6007 6008 if (config_type == CONFIG_TYPE_VMENTRY_FAILS_EARLY) { 6009 enter_guest_with_bad_controls(); 6010 continue; 6011 } 6012 6013 for (reg = 0; reg < PAGE_SIZE / sizeof(u32); reg += 0x10) { 6014 struct apic_reg_virt_expectation expectation = {}; 6015 bool ok; 6016 6017 ok = apic_reg_virt_exit_expectation( 6018 reg, apic_reg_virt_config, &expectation); 6019 if (!ok) { 6020 report(false, "Malformed test."); 6021 break; 6022 } 6023 6024 test_xapic_rd(reg, &expectation, apic_access_address, 6025 virtual_apic_page); 6026 test_xapic_wr(reg, &expectation, apic_access_address, 6027 virtual_apic_page); 6028 } 6029 } 6030 6031 /* Terminate the guest */ 6032 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6033 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6034 args->op = TERMINATE; 6035 enter_guest(); 6036 assert_exit_reason(VMX_VMCALL); 6037 } 6038 6039 struct virt_x2apic_mode_config { 6040 struct apic_reg_virt_config apic_reg_virt_config; 6041 bool virtual_interrupt_delivery; 6042 bool use_msr_bitmaps; 6043 bool disable_x2apic_msr_intercepts; 6044 bool disable_x2apic; 6045 }; 6046 6047 struct virt_x2apic_mode_test_case { 6048 const char *name; 6049 struct virt_x2apic_mode_config virt_x2apic_mode_config; 6050 }; 6051 6052 enum Virt_x2apic_mode_behavior_type { 6053 X2APIC_ACCESS_VIRTUALIZED, 6054 X2APIC_ACCESS_PASSED_THROUGH, 6055 X2APIC_ACCESS_TRIGGERS_GP, 6056 }; 6057 6058 struct virt_x2apic_mode_expectation { 6059 enum Reason rd_exit_reason; 6060 enum Reason wr_exit_reason; 6061 6062 /* 6063 * RDMSR and WRMSR handle 64-bit values. However, except for ICR, all of 6064 * the x2APIC registers are 32 bits. Notice: 6065 * 1. vmx_x2apic_read() clears the upper 32 bits for 32-bit registers. 6066 * 2. vmx_x2apic_write() expects the val arg to be well-formed. 6067 */ 6068 u64 rd_val; 6069 u64 wr_val; 6070 6071 /* 6072 * Compares input to virtualized output; 6073 * 1st arg is pointer to return expected virtualization output. 6074 */ 6075 u64 (*virt_fn)(u64); 6076 6077 enum Virt_x2apic_mode_behavior_type rd_behavior; 6078 enum Virt_x2apic_mode_behavior_type wr_behavior; 6079 bool wr_only; 6080 }; 6081 6082 static u64 virt_x2apic_mode_identity(u64 val) 6083 { 6084 return val; 6085 } 6086 6087 static u64 virt_x2apic_mode_nibble1(u64 val) 6088 { 6089 return val & 0xf0; 6090 } 6091 6092 static void virt_x2apic_mode_rd_expectation( 6093 u32 reg, bool virt_x2apic_mode_on, bool disable_x2apic, 6094 bool apic_register_virtualization, bool virtual_interrupt_delivery, 6095 struct virt_x2apic_mode_expectation *expectation) 6096 { 6097 bool readable = 6098 !x2apic_reg_reserved(reg) && 6099 reg != APIC_EOI; 6100 6101 expectation->rd_exit_reason = VMX_VMCALL; 6102 expectation->virt_fn = virt_x2apic_mode_identity; 6103 if (virt_x2apic_mode_on && apic_register_virtualization) { 6104 expectation->rd_val = MAGIC_VAL_1; 6105 if (reg == APIC_PROCPRI && virtual_interrupt_delivery) 6106 expectation->virt_fn = virt_x2apic_mode_nibble1; 6107 else if (reg == APIC_TASKPRI) 6108 expectation->virt_fn = virt_x2apic_mode_nibble1; 6109 expectation->rd_behavior = X2APIC_ACCESS_VIRTUALIZED; 6110 } else if (virt_x2apic_mode_on && !apic_register_virtualization && 6111 reg == APIC_TASKPRI) { 6112 expectation->rd_val = MAGIC_VAL_1; 6113 expectation->virt_fn = virt_x2apic_mode_nibble1; 6114 expectation->rd_behavior = X2APIC_ACCESS_VIRTUALIZED; 6115 } else if (!disable_x2apic && readable) { 6116 expectation->rd_val = apic_read(reg); 6117 expectation->rd_behavior = X2APIC_ACCESS_PASSED_THROUGH; 6118 } else { 6119 expectation->rd_behavior = X2APIC_ACCESS_TRIGGERS_GP; 6120 } 6121 } 6122 6123 /* 6124 * get_x2apic_wr_val() creates an innocuous write value for an x2APIC register. 6125 * 6126 * For writable registers, get_x2apic_wr_val() deposits the write value into the 6127 * val pointer arg and returns true. For non-writable registers, val is not 6128 * modified and get_x2apic_wr_val() returns false. 6129 */ 6130 static bool get_x2apic_wr_val(u32 reg, u64 *val) 6131 { 6132 switch (reg) { 6133 case APIC_TASKPRI: 6134 /* Bits 31:8 are reserved. */ 6135 *val &= 0xff; 6136 break; 6137 case APIC_EOI: 6138 case APIC_ESR: 6139 case APIC_TMICT: 6140 /* 6141 * EOI, ESR: WRMSR of a non-zero value causes #GP(0). 6142 * TMICT: A write of 0 to the initial-count register effectively 6143 * stops the local APIC timer, in both one-shot and 6144 * periodic mode. 6145 */ 6146 *val = 0; 6147 break; 6148 case APIC_SPIV: 6149 case APIC_LVTT: 6150 case APIC_LVTTHMR: 6151 case APIC_LVTPC: 6152 case APIC_LVT0: 6153 case APIC_LVT1: 6154 case APIC_LVTERR: 6155 case APIC_TDCR: 6156 /* 6157 * To avoid writing a 1 to a reserved bit or causing some other 6158 * unintended side effect, read the current value and use it as 6159 * the write value. 6160 */ 6161 *val = apic_read(reg); 6162 break; 6163 case APIC_CMCI: 6164 if (!apic_lvt_entry_supported(6)) 6165 return false; 6166 *val = apic_read(reg); 6167 break; 6168 case APIC_ICR: 6169 *val = 0x40000 | 0xf1; 6170 break; 6171 case APIC_SELF_IPI: 6172 /* 6173 * With special processing (i.e., virtualize x2APIC mode + 6174 * virtual interrupt delivery), writing zero causes an 6175 * APIC-write VM exit. We plan to add a test for enabling 6176 * "virtual-interrupt delivery" in VMCS12, and that's where we 6177 * will test a self IPI with special processing. 6178 */ 6179 *val = 0x0; 6180 break; 6181 default: 6182 return false; 6183 } 6184 6185 return true; 6186 } 6187 6188 static bool special_processing_applies(u32 reg, u64 *val, 6189 bool virt_int_delivery) 6190 { 6191 bool special_processing = 6192 (reg == APIC_TASKPRI) || 6193 (virt_int_delivery && 6194 (reg == APIC_EOI || reg == APIC_SELF_IPI)); 6195 6196 if (special_processing) { 6197 TEST_ASSERT(get_x2apic_wr_val(reg, val)); 6198 return true; 6199 } 6200 6201 return false; 6202 } 6203 6204 static void virt_x2apic_mode_wr_expectation( 6205 u32 reg, bool virt_x2apic_mode_on, bool disable_x2apic, 6206 bool virt_int_delivery, 6207 struct virt_x2apic_mode_expectation *expectation) 6208 { 6209 expectation->wr_exit_reason = VMX_VMCALL; 6210 expectation->wr_val = MAGIC_VAL_1; 6211 expectation->wr_only = false; 6212 6213 if (virt_x2apic_mode_on && 6214 special_processing_applies(reg, &expectation->wr_val, 6215 virt_int_delivery)) { 6216 expectation->wr_behavior = X2APIC_ACCESS_VIRTUALIZED; 6217 if (reg == APIC_SELF_IPI) 6218 expectation->wr_exit_reason = VMX_APIC_WRITE; 6219 } else if (!disable_x2apic && 6220 get_x2apic_wr_val(reg, &expectation->wr_val)) { 6221 expectation->wr_behavior = X2APIC_ACCESS_PASSED_THROUGH; 6222 if (reg == APIC_EOI || reg == APIC_SELF_IPI) 6223 expectation->wr_only = true; 6224 if (reg == APIC_ICR) 6225 expectation->wr_exit_reason = VMX_EXTINT; 6226 } else { 6227 expectation->wr_behavior = X2APIC_ACCESS_TRIGGERS_GP; 6228 /* 6229 * Writing 1 to a reserved bit triggers a #GP. 6230 * Thus, set the write value to 0, which seems 6231 * the most likely to detect a missed #GP. 6232 */ 6233 expectation->wr_val = 0; 6234 } 6235 } 6236 6237 static void virt_x2apic_mode_exit_expectation( 6238 u32 reg, struct virt_x2apic_mode_config *config, 6239 struct virt_x2apic_mode_expectation *expectation) 6240 { 6241 struct apic_reg_virt_config *base_config = 6242 &config->apic_reg_virt_config; 6243 bool virt_x2apic_mode_on = 6244 base_config->virtualize_x2apic_mode && 6245 config->use_msr_bitmaps && 6246 config->disable_x2apic_msr_intercepts && 6247 base_config->activate_secondary_controls; 6248 6249 virt_x2apic_mode_wr_expectation( 6250 reg, virt_x2apic_mode_on, config->disable_x2apic, 6251 config->virtual_interrupt_delivery, expectation); 6252 virt_x2apic_mode_rd_expectation( 6253 reg, virt_x2apic_mode_on, config->disable_x2apic, 6254 base_config->apic_register_virtualization, 6255 config->virtual_interrupt_delivery, expectation); 6256 } 6257 6258 struct virt_x2apic_mode_test_case virt_x2apic_mode_tests[] = { 6259 /* 6260 * Baseline "virtualize x2APIC mode" configuration: 6261 * - virtualize x2APIC mode 6262 * - virtual-interrupt delivery 6263 * - APIC-register virtualization 6264 * - x2APIC MSR intercepts disabled 6265 * 6266 * Reads come from virtual APIC page, special processing applies to 6267 * VTPR, EOI, and SELF IPI, and all other writes pass through to L1 6268 * APIC. 6269 */ 6270 { 6271 .name = "Baseline", 6272 .virt_x2apic_mode_config = { 6273 .virtual_interrupt_delivery = true, 6274 .use_msr_bitmaps = true, 6275 .disable_x2apic_msr_intercepts = true, 6276 .disable_x2apic = false, 6277 .apic_reg_virt_config = { 6278 .apic_register_virtualization = true, 6279 .use_tpr_shadow = true, 6280 .virtualize_apic_accesses = false, 6281 .virtualize_x2apic_mode = true, 6282 .activate_secondary_controls = true, 6283 }, 6284 }, 6285 }, 6286 { 6287 .name = "Baseline w/ x2apic disabled", 6288 .virt_x2apic_mode_config = { 6289 .virtual_interrupt_delivery = true, 6290 .use_msr_bitmaps = true, 6291 .disable_x2apic_msr_intercepts = true, 6292 .disable_x2apic = true, 6293 .apic_reg_virt_config = { 6294 .apic_register_virtualization = true, 6295 .use_tpr_shadow = true, 6296 .virtualize_apic_accesses = false, 6297 .virtualize_x2apic_mode = true, 6298 .activate_secondary_controls = true, 6299 }, 6300 }, 6301 }, 6302 6303 /* 6304 * Baseline, minus virtual-interrupt delivery. Reads come from virtual 6305 * APIC page, special processing applies to VTPR, and all other writes 6306 * pass through to L1 APIC. 6307 */ 6308 { 6309 .name = "Baseline - virtual interrupt delivery", 6310 .virt_x2apic_mode_config = { 6311 .virtual_interrupt_delivery = false, 6312 .use_msr_bitmaps = true, 6313 .disable_x2apic_msr_intercepts = true, 6314 .disable_x2apic = false, 6315 .apic_reg_virt_config = { 6316 .apic_register_virtualization = true, 6317 .use_tpr_shadow = true, 6318 .virtualize_apic_accesses = false, 6319 .virtualize_x2apic_mode = true, 6320 .activate_secondary_controls = true, 6321 }, 6322 }, 6323 }, 6324 6325 /* 6326 * Baseline, minus APIC-register virtualization. x2APIC reads pass 6327 * through to L1's APIC, unless reading VTPR 6328 */ 6329 { 6330 .name = "Virtualize x2APIC mode, no APIC reg virt", 6331 .virt_x2apic_mode_config = { 6332 .virtual_interrupt_delivery = true, 6333 .use_msr_bitmaps = true, 6334 .disable_x2apic_msr_intercepts = true, 6335 .disable_x2apic = false, 6336 .apic_reg_virt_config = { 6337 .apic_register_virtualization = false, 6338 .use_tpr_shadow = true, 6339 .virtualize_apic_accesses = false, 6340 .virtualize_x2apic_mode = true, 6341 .activate_secondary_controls = true, 6342 }, 6343 }, 6344 }, 6345 { 6346 .name = "Virtualize x2APIC mode, no APIC reg virt, x2APIC off", 6347 .virt_x2apic_mode_config = { 6348 .virtual_interrupt_delivery = true, 6349 .use_msr_bitmaps = true, 6350 .disable_x2apic_msr_intercepts = true, 6351 .disable_x2apic = true, 6352 .apic_reg_virt_config = { 6353 .apic_register_virtualization = false, 6354 .use_tpr_shadow = true, 6355 .virtualize_apic_accesses = false, 6356 .virtualize_x2apic_mode = true, 6357 .activate_secondary_controls = true, 6358 }, 6359 }, 6360 }, 6361 6362 /* 6363 * Enable "virtualize x2APIC mode" and "APIC-register virtualization", 6364 * and disable intercepts for the x2APIC MSRs, but fail to enable 6365 * "activate secondary controls" (i.e. L2 gets access to L1's x2APIC 6366 * MSRs). 6367 */ 6368 { 6369 .name = "Fail to enable activate secondary controls", 6370 .virt_x2apic_mode_config = { 6371 .virtual_interrupt_delivery = true, 6372 .use_msr_bitmaps = true, 6373 .disable_x2apic_msr_intercepts = true, 6374 .disable_x2apic = false, 6375 .apic_reg_virt_config = { 6376 .apic_register_virtualization = true, 6377 .use_tpr_shadow = true, 6378 .virtualize_apic_accesses = false, 6379 .virtualize_x2apic_mode = true, 6380 .activate_secondary_controls = false, 6381 }, 6382 }, 6383 }, 6384 6385 /* 6386 * Enable "APIC-register virtualization" and enable "activate secondary 6387 * controls" and disable intercepts for the x2APIC MSRs, but do not 6388 * enable the "virtualize x2APIC mode" VM-execution control (i.e. L2 6389 * gets access to L1's x2APIC MSRs). 6390 */ 6391 { 6392 .name = "Fail to enable virtualize x2APIC mode", 6393 .virt_x2apic_mode_config = { 6394 .virtual_interrupt_delivery = true, 6395 .use_msr_bitmaps = true, 6396 .disable_x2apic_msr_intercepts = true, 6397 .disable_x2apic = false, 6398 .apic_reg_virt_config = { 6399 .apic_register_virtualization = true, 6400 .use_tpr_shadow = true, 6401 .virtualize_apic_accesses = false, 6402 .virtualize_x2apic_mode = false, 6403 .activate_secondary_controls = true, 6404 }, 6405 }, 6406 }, 6407 6408 /* 6409 * Disable "Virtualize x2APIC mode", disable x2APIC MSR intercepts, and 6410 * enable "APIC-register virtualization" --> L2 gets L1's x2APIC MSRs. 6411 */ 6412 { 6413 .name = "Baseline", 6414 .virt_x2apic_mode_config = { 6415 .virtual_interrupt_delivery = true, 6416 .use_msr_bitmaps = true, 6417 .disable_x2apic_msr_intercepts = true, 6418 .disable_x2apic = false, 6419 .apic_reg_virt_config = { 6420 .apic_register_virtualization = true, 6421 .use_tpr_shadow = true, 6422 .virtualize_apic_accesses = false, 6423 .virtualize_x2apic_mode = false, 6424 .activate_secondary_controls = true, 6425 }, 6426 }, 6427 }, 6428 }; 6429 6430 enum X2apic_op { 6431 X2APIC_OP_RD, 6432 X2APIC_OP_WR, 6433 X2APIC_TERMINATE, 6434 }; 6435 6436 static u64 vmx_x2apic_read(u32 reg) 6437 { 6438 u32 msr_addr = x2apic_msr(reg); 6439 u64 val; 6440 6441 val = rdmsr(msr_addr); 6442 6443 return val; 6444 } 6445 6446 static void vmx_x2apic_write(u32 reg, u64 val) 6447 { 6448 u32 msr_addr = x2apic_msr(reg); 6449 6450 wrmsr(msr_addr, val); 6451 } 6452 6453 struct virt_x2apic_mode_guest_args { 6454 enum X2apic_op op; 6455 u32 reg; 6456 u64 val; 6457 bool should_gp; 6458 u64 (*virt_fn)(u64); 6459 } virt_x2apic_mode_guest_args; 6460 6461 static volatile bool handle_x2apic_gp_ran; 6462 static volatile u32 handle_x2apic_gp_insn_len; 6463 static void handle_x2apic_gp(struct ex_regs *regs) 6464 { 6465 handle_x2apic_gp_ran = true; 6466 regs->rip += handle_x2apic_gp_insn_len; 6467 } 6468 6469 static handler setup_x2apic_gp_handler(void) 6470 { 6471 handler old_handler; 6472 6473 old_handler = handle_exception(GP_VECTOR, handle_x2apic_gp); 6474 /* RDMSR and WRMSR are both 2 bytes, assuming no prefixes. */ 6475 handle_x2apic_gp_insn_len = 2; 6476 6477 return old_handler; 6478 } 6479 6480 static void teardown_x2apic_gp_handler(handler old_handler) 6481 { 6482 handle_exception(GP_VECTOR, old_handler); 6483 6484 /* 6485 * Defensively reset instruction length, so that if the handler is 6486 * incorrectly used, it will loop infinitely, rather than run off into 6487 * la la land. 6488 */ 6489 handle_x2apic_gp_insn_len = 0; 6490 handle_x2apic_gp_ran = false; 6491 } 6492 6493 static void virt_x2apic_mode_guest(void) 6494 { 6495 volatile struct virt_x2apic_mode_guest_args *args = 6496 &virt_x2apic_mode_guest_args; 6497 6498 for (;;) { 6499 enum X2apic_op op = args->op; 6500 u32 reg = args->reg; 6501 u64 val = args->val; 6502 bool should_gp = args->should_gp; 6503 u64 (*virt_fn)(u64) = args->virt_fn; 6504 handler old_handler; 6505 6506 if (op == X2APIC_TERMINATE) 6507 break; 6508 6509 if (should_gp) { 6510 TEST_ASSERT(!handle_x2apic_gp_ran); 6511 old_handler = setup_x2apic_gp_handler(); 6512 } 6513 6514 if (op == X2APIC_OP_RD) { 6515 u64 ret = vmx_x2apic_read(reg); 6516 6517 if (!should_gp) { 6518 u64 want = virt_fn(val); 6519 u64 got = virt_fn(ret); 6520 6521 report(got == want, 6522 "APIC read; got 0x%lx, want 0x%lx.", 6523 got, want); 6524 } 6525 } else if (op == X2APIC_OP_WR) { 6526 vmx_x2apic_write(reg, val); 6527 } 6528 6529 if (should_gp) { 6530 report(handle_x2apic_gp_ran, 6531 "x2APIC op triggered GP."); 6532 teardown_x2apic_gp_handler(old_handler); 6533 } 6534 6535 /* 6536 * The L1 should always execute a vmcall after it's done testing 6537 * an individual APIC operation. This helps to validate that the 6538 * L1 and L2 are in sync with each other, as expected. 6539 */ 6540 vmcall(); 6541 } 6542 } 6543 6544 static void test_x2apic_rd( 6545 u32 reg, struct virt_x2apic_mode_expectation *expectation, 6546 u32 *virtual_apic_page) 6547 { 6548 u64 val = expectation->rd_val; 6549 u32 exit_reason_want = expectation->rd_exit_reason; 6550 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6551 6552 report_prefix_pushf("x2apic - reading 0x%03x", reg); 6553 6554 /* Configure guest to do an x2apic read */ 6555 args->op = X2APIC_OP_RD; 6556 args->reg = reg; 6557 args->val = val; 6558 args->should_gp = expectation->rd_behavior == X2APIC_ACCESS_TRIGGERS_GP; 6559 args->virt_fn = expectation->virt_fn; 6560 6561 /* Setup virtual APIC page */ 6562 if (expectation->rd_behavior == X2APIC_ACCESS_VIRTUALIZED) 6563 virtual_apic_page[apic_reg_index(reg)] = (u32)val; 6564 6565 /* Enter guest */ 6566 enter_guest(); 6567 6568 if (exit_reason_want != VMX_VMCALL) { 6569 report(false, "Oops, bad exit expectation: %u.", 6570 exit_reason_want); 6571 } 6572 6573 skip_exit_vmcall(); 6574 report_prefix_pop(); 6575 } 6576 6577 static volatile bool handle_x2apic_ipi_ran; 6578 static void handle_x2apic_ipi(isr_regs_t *regs) 6579 { 6580 handle_x2apic_ipi_ran = true; 6581 eoi(); 6582 } 6583 6584 static void test_x2apic_wr( 6585 u32 reg, struct virt_x2apic_mode_expectation *expectation, 6586 u32 *virtual_apic_page) 6587 { 6588 u64 val = expectation->wr_val; 6589 u32 exit_reason_want = expectation->wr_exit_reason; 6590 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6591 int ipi_vector = 0xf1; 6592 u32 restore_val = 0; 6593 6594 report_prefix_pushf("x2apic - writing 0x%lx to 0x%03x", val, reg); 6595 6596 /* Configure guest to do an x2apic read */ 6597 args->op = X2APIC_OP_WR; 6598 args->reg = reg; 6599 args->val = val; 6600 args->should_gp = expectation->wr_behavior == X2APIC_ACCESS_TRIGGERS_GP; 6601 6602 /* Setup virtual APIC page */ 6603 if (expectation->wr_behavior == X2APIC_ACCESS_VIRTUALIZED) 6604 virtual_apic_page[apic_reg_index(reg)] = 0; 6605 if (expectation->wr_behavior == X2APIC_ACCESS_PASSED_THROUGH && !expectation->wr_only) 6606 restore_val = apic_read(reg); 6607 6608 /* Setup IPI handler */ 6609 handle_x2apic_ipi_ran = false; 6610 handle_irq(ipi_vector, handle_x2apic_ipi); 6611 6612 /* Enter guest */ 6613 enter_guest(); 6614 6615 /* 6616 * Validate the behavior and 6617 * pass a magic value back to the guest. 6618 */ 6619 if (exit_reason_want == VMX_EXTINT) { 6620 assert_exit_reason(exit_reason_want); 6621 6622 /* Clear the external interrupt. */ 6623 irq_enable(); 6624 asm volatile ("nop"); 6625 irq_disable(); 6626 report(handle_x2apic_ipi_ran, 6627 "Got pending interrupt after IRQ enabled."); 6628 6629 enter_guest(); 6630 } else if (exit_reason_want == VMX_APIC_WRITE) { 6631 assert_exit_reason(exit_reason_want); 6632 report(virtual_apic_page[apic_reg_index(reg)] == val, 6633 "got APIC write exit @ page offset 0x%03x; val is 0x%x, want 0x%lx", 6634 apic_reg_index(reg), 6635 virtual_apic_page[apic_reg_index(reg)], val); 6636 6637 /* Reenter guest so it can consume/check rcx and exit again. */ 6638 enter_guest(); 6639 } else if (exit_reason_want != VMX_VMCALL) { 6640 report(false, "Oops, bad exit expectation: %u.", 6641 exit_reason_want); 6642 } 6643 6644 assert_exit_reason(VMX_VMCALL); 6645 if (expectation->wr_behavior == X2APIC_ACCESS_VIRTUALIZED) { 6646 u64 want = val; 6647 u32 got = virtual_apic_page[apic_reg_index(reg)]; 6648 6649 report(got == want, "x2APIC write; got 0x%x, want 0x%lx", got, 6650 want); 6651 } else if (expectation->wr_behavior == X2APIC_ACCESS_PASSED_THROUGH) { 6652 if (!expectation->wr_only) { 6653 u32 got = apic_read(reg); 6654 bool ok; 6655 6656 /* 6657 * When L1's TPR is passed through to L2, the lower 6658 * nibble can be lost. For example, if L2 executes 6659 * WRMSR(0x808, 0x78), then, L1 might read 0x70. 6660 * 6661 * Here's how the lower nibble can get lost: 6662 * 1. L2 executes WRMSR(0x808, 0x78). 6663 * 2. L2 exits to L0 with a WRMSR exit. 6664 * 3. L0 emulates WRMSR, by writing L1's TPR. 6665 * 4. L0 re-enters L2. 6666 * 5. L2 exits to L0 (reason doesn't matter). 6667 * 6. L0 reflects L2's exit to L1. 6668 * 7. Before entering L1, L0 exits to user-space 6669 * (e.g., to satisfy TPR access reporting). 6670 * 8. User-space executes KVM_SET_REGS ioctl, which 6671 * clears the lower nibble of L1's TPR. 6672 */ 6673 if (reg == APIC_TASKPRI) { 6674 got = apic_virt_nibble1(got); 6675 val = apic_virt_nibble1(val); 6676 } 6677 6678 ok = got == val; 6679 report(ok, 6680 "non-virtualized write; val is 0x%x, want 0x%lx", 6681 got, val); 6682 apic_write(reg, restore_val); 6683 } else { 6684 report(true, "non-virtualized and write-only OK"); 6685 } 6686 } 6687 skip_exit_insn(); 6688 6689 report_prefix_pop(); 6690 } 6691 6692 static enum Config_type configure_virt_x2apic_mode_test( 6693 struct virt_x2apic_mode_config *virt_x2apic_mode_config, 6694 u8 *msr_bitmap_page) 6695 { 6696 int msr; 6697 u32 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6698 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6699 6700 /* x2apic-specific VMCS config */ 6701 if (virt_x2apic_mode_config->use_msr_bitmaps) { 6702 /* virt_x2apic_mode_test() checks for MSR bitmaps support */ 6703 cpu_exec_ctrl0 |= CPU_MSR_BITMAP; 6704 } else { 6705 cpu_exec_ctrl0 &= ~CPU_MSR_BITMAP; 6706 } 6707 6708 if (virt_x2apic_mode_config->virtual_interrupt_delivery) { 6709 if (!(ctrl_cpu_rev[1].clr & CPU_VINTD)) { 6710 report_skip("VM-execution control \"virtual-interrupt delivery\" NOT supported.\n"); 6711 return CONFIG_TYPE_UNSUPPORTED; 6712 } 6713 cpu_exec_ctrl1 |= CPU_VINTD; 6714 } else { 6715 cpu_exec_ctrl1 &= ~CPU_VINTD; 6716 } 6717 6718 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6719 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6720 6721 /* x2APIC MSR intercepts are usually off for "Virtualize x2APIC mode" */ 6722 for (msr = 0x800; msr <= 0x8ff; msr++) { 6723 if (virt_x2apic_mode_config->disable_x2apic_msr_intercepts) { 6724 clear_bit(msr, msr_bitmap_page + 0x000); 6725 clear_bit(msr, msr_bitmap_page + 0x800); 6726 } else { 6727 set_bit(msr, msr_bitmap_page + 0x000); 6728 set_bit(msr, msr_bitmap_page + 0x800); 6729 } 6730 } 6731 6732 /* x2APIC mode can impact virtualization */ 6733 reset_apic(); 6734 if (!virt_x2apic_mode_config->disable_x2apic) 6735 enable_x2apic(); 6736 6737 return configure_apic_reg_virt_test( 6738 &virt_x2apic_mode_config->apic_reg_virt_config); 6739 } 6740 6741 static void virt_x2apic_mode_test(void) 6742 { 6743 u32 *virtual_apic_page; 6744 u8 *msr_bitmap_page; 6745 u64 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6746 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6747 int i; 6748 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6749 6750 if (!cpu_has_apicv()) { 6751 report_skip(__func__); 6752 return; 6753 } 6754 6755 /* 6756 * This is to exercise an issue in KVM's logic to merge L0's and L1's 6757 * MSR bitmaps. Previously, an L1 could get at L0's x2APIC MSRs by 6758 * writing the IA32_SPEC_CTRL MSR or the IA32_PRED_CMD MSRs. KVM would 6759 * then proceed to manipulate the MSR bitmaps, as if VMCS12 had the 6760 * "Virtualize x2APIC mod" control set, even when it didn't. 6761 */ 6762 if (has_spec_ctrl()) 6763 wrmsr(MSR_IA32_SPEC_CTRL, 1); 6764 6765 /* 6766 * Check that VMCS12 supports: 6767 * - "Virtual-APIC address", indicated by "use TPR shadow" 6768 * - "MSR-bitmap address", indicated by "use MSR bitmaps" 6769 */ 6770 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) { 6771 report_skip("VM-execution control \"use TPR shadow\" NOT supported.\n"); 6772 return; 6773 } else if (!(ctrl_cpu_rev[0].clr & CPU_MSR_BITMAP)) { 6774 report_skip("VM-execution control \"use MSR bitmaps\" NOT supported.\n"); 6775 return; 6776 } 6777 6778 test_set_guest(virt_x2apic_mode_guest); 6779 6780 virtual_apic_page = alloc_page(); 6781 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 6782 6783 msr_bitmap_page = alloc_page(); 6784 memset(msr_bitmap_page, 0xff, PAGE_SIZE); 6785 vmcs_write(MSR_BITMAP, virt_to_phys(msr_bitmap_page)); 6786 6787 for (i = 0; i < ARRAY_SIZE(virt_x2apic_mode_tests); i++) { 6788 struct virt_x2apic_mode_test_case *virt_x2apic_mode_test_case = 6789 &virt_x2apic_mode_tests[i]; 6790 struct virt_x2apic_mode_config *virt_x2apic_mode_config = 6791 &virt_x2apic_mode_test_case->virt_x2apic_mode_config; 6792 enum Config_type config_type; 6793 u32 reg; 6794 6795 printf("--- %s test ---\n", virt_x2apic_mode_test_case->name); 6796 config_type = 6797 configure_virt_x2apic_mode_test(virt_x2apic_mode_config, 6798 msr_bitmap_page); 6799 if (config_type == CONFIG_TYPE_UNSUPPORTED) { 6800 report_skip("Skip because of missing features.\n"); 6801 continue; 6802 } else if (config_type == CONFIG_TYPE_VMENTRY_FAILS_EARLY) { 6803 enter_guest_with_bad_controls(); 6804 continue; 6805 } 6806 6807 for (reg = 0; reg < PAGE_SIZE / sizeof(u32); reg += 0x10) { 6808 struct virt_x2apic_mode_expectation expectation; 6809 6810 virt_x2apic_mode_exit_expectation( 6811 reg, virt_x2apic_mode_config, &expectation); 6812 6813 test_x2apic_rd(reg, &expectation, virtual_apic_page); 6814 test_x2apic_wr(reg, &expectation, virtual_apic_page); 6815 } 6816 } 6817 6818 6819 /* Terminate the guest */ 6820 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6821 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6822 args->op = X2APIC_TERMINATE; 6823 enter_guest(); 6824 assert_exit_reason(VMX_VMCALL); 6825 } 6826 6827 static void test_ctl_reg(const char *cr_name, u64 cr, u64 fixed0, u64 fixed1) 6828 { 6829 u64 val; 6830 u64 cr_saved = vmcs_read(cr); 6831 int i; 6832 6833 val = fixed0 & fixed1; 6834 if (cr == HOST_CR4) 6835 vmcs_write(cr, val | X86_CR4_PAE); 6836 else 6837 vmcs_write(cr, val); 6838 report_prefix_pushf("%s %lx", cr_name, val); 6839 if (val == fixed0) 6840 test_vmx_vmlaunch(0); 6841 else 6842 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 6843 report_prefix_pop(); 6844 6845 for (i = 0; i < 64; i++) { 6846 6847 /* Set a bit when the corresponding bit in fixed1 is 0 */ 6848 if ((fixed1 & (1ull << i)) == 0) { 6849 if (cr == HOST_CR4 && ((1ull << i) & X86_CR4_SMEP || 6850 (1ull << i) & X86_CR4_SMAP)) 6851 continue; 6852 6853 vmcs_write(cr, cr_saved | (1ull << i)); 6854 report_prefix_pushf("%s %llx", cr_name, 6855 cr_saved | (1ull << i)); 6856 test_vmx_vmlaunch( 6857 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 6858 report_prefix_pop(); 6859 } 6860 6861 /* Unset a bit when the corresponding bit in fixed0 is 1 */ 6862 if (fixed0 & (1ull << i)) { 6863 vmcs_write(cr, cr_saved & ~(1ull << i)); 6864 report_prefix_pushf("%s %llx", cr_name, 6865 cr_saved & ~(1ull << i)); 6866 test_vmx_vmlaunch( 6867 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 6868 report_prefix_pop(); 6869 } 6870 } 6871 6872 vmcs_write(cr, cr_saved); 6873 } 6874 6875 /* 6876 * 1. The CR0 field must not set any bit to a value not supported in VMX 6877 * operation. 6878 * 2. The CR4 field must not set any bit to a value not supported in VMX 6879 * operation. 6880 * 3. On processors that support Intel 64 architecture, the CR3 field must 6881 * be such that bits 63:52 and bits in the range 51:32 beyond the 6882 * processor’s physical-address width must be 0. 6883 * 6884 * [Intel SDM] 6885 */ 6886 static void test_host_ctl_regs(void) 6887 { 6888 u64 fixed0, fixed1, cr3, cr3_saved; 6889 int i; 6890 6891 /* Test CR0 */ 6892 fixed0 = rdmsr(MSR_IA32_VMX_CR0_FIXED0); 6893 fixed1 = rdmsr(MSR_IA32_VMX_CR0_FIXED1); 6894 test_ctl_reg("HOST_CR0", HOST_CR0, fixed0, fixed1); 6895 6896 /* Test CR4 */ 6897 fixed0 = rdmsr(MSR_IA32_VMX_CR4_FIXED0); 6898 fixed1 = rdmsr(MSR_IA32_VMX_CR4_FIXED1) & 6899 ~(X86_CR4_SMEP | X86_CR4_SMAP); 6900 test_ctl_reg("HOST_CR4", HOST_CR4, fixed0, fixed1); 6901 6902 /* Test CR3 */ 6903 cr3_saved = vmcs_read(HOST_CR3); 6904 for (i = cpuid_maxphyaddr(); i < 64; i++) { 6905 cr3 = cr3_saved | (1ul << i); 6906 vmcs_write(HOST_CR3, cr3); 6907 report_prefix_pushf("HOST_CR3 %lx", cr3); 6908 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 6909 report_prefix_pop(); 6910 } 6911 6912 vmcs_write(HOST_CR3, cr3_saved); 6913 } 6914 6915 static void test_efer_vmlaunch(u32 fld, bool ok) 6916 { 6917 if (fld == HOST_EFER) { 6918 if (ok) 6919 test_vmx_vmlaunch(0); 6920 else 6921 test_vmx_vmlaunch2(VMXERR_ENTRY_INVALID_CONTROL_FIELD, 6922 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 6923 } else { 6924 test_guest_state("EFER test", !ok, GUEST_EFER, "GUEST_EFER"); 6925 } 6926 } 6927 6928 static void test_efer_one(u32 fld, const char * fld_name, u64 efer, 6929 u32 ctrl_fld, u64 ctrl, 6930 int i, const char *efer_bit_name) 6931 { 6932 bool ok; 6933 6934 ok = true; 6935 if (ctrl_fld == EXI_CONTROLS && (ctrl & EXI_LOAD_EFER)) { 6936 if (!!(efer & EFER_LMA) != !!(ctrl & EXI_HOST_64)) 6937 ok = false; 6938 if (!!(efer & EFER_LME) != !!(ctrl & EXI_HOST_64)) 6939 ok = false; 6940 } 6941 if (ctrl_fld == ENT_CONTROLS && (ctrl & ENT_LOAD_EFER)) { 6942 /* Check LMA too since CR0.PG is set. */ 6943 if (!!(efer & EFER_LMA) != !!(ctrl & ENT_GUEST_64)) 6944 ok = false; 6945 if (!!(efer & EFER_LME) != !!(ctrl & ENT_GUEST_64)) 6946 ok = false; 6947 } 6948 6949 /* 6950 * Skip the test if it would enter the guest in 32-bit mode. 6951 * Perhaps write the test in assembly and make sure it 6952 * can be run in either mode? 6953 */ 6954 if (fld == GUEST_EFER && ok && !(ctrl & ENT_GUEST_64)) 6955 return; 6956 6957 vmcs_write(ctrl_fld, ctrl); 6958 vmcs_write(fld, efer); 6959 report_prefix_pushf("%s %s bit turned %s, controls %s", 6960 fld_name, efer_bit_name, 6961 (i & 1) ? "on" : "off", 6962 (i & 2) ? "on" : "off"); 6963 6964 test_efer_vmlaunch(fld, ok); 6965 report_prefix_pop(); 6966 } 6967 6968 static void test_efer_bit(u32 fld, const char * fld_name, 6969 u32 ctrl_fld, u64 ctrl_bit, u64 efer_bit, 6970 const char *efer_bit_name) 6971 { 6972 u64 efer_saved = vmcs_read(fld); 6973 u32 ctrl_saved = vmcs_read(ctrl_fld); 6974 int i; 6975 6976 for (i = 0; i < 4; i++) { 6977 u64 efer = efer_saved & ~efer_bit; 6978 u64 ctrl = ctrl_saved & ~ctrl_bit; 6979 6980 if (i & 1) 6981 efer |= efer_bit; 6982 if (i & 2) 6983 ctrl |= ctrl_bit; 6984 6985 test_efer_one(fld, fld_name, efer, ctrl_fld, ctrl, 6986 i, efer_bit_name); 6987 } 6988 6989 vmcs_write(ctrl_fld, ctrl_saved); 6990 vmcs_write(fld, efer_saved); 6991 } 6992 6993 static void test_efer(u32 fld, const char * fld_name, u32 ctrl_fld, 6994 u64 ctrl_bit1, u64 ctrl_bit2) 6995 { 6996 u64 efer_saved = vmcs_read(fld); 6997 u32 ctrl_saved = vmcs_read(ctrl_fld); 6998 u64 efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 6999 u64 i; 7000 u64 efer; 7001 7002 if (cpu_has_efer_nx()) 7003 efer_reserved_bits &= ~EFER_NX; 7004 7005 if (!ctrl_bit1) { 7006 printf("\"Load-IA32-EFER\" exit control not supported\n"); 7007 goto test_entry_exit_mode; 7008 } 7009 7010 report_prefix_pushf("%s %lx", fld_name, efer_saved); 7011 test_efer_vmlaunch(fld, true); 7012 report_prefix_pop(); 7013 7014 /* 7015 * Check reserved bits 7016 */ 7017 vmcs_write(ctrl_fld, ctrl_saved & ~ctrl_bit1); 7018 for (i = 0; i < 64; i++) { 7019 if ((1ull << i) & efer_reserved_bits) { 7020 efer = efer_saved | (1ull << i); 7021 vmcs_write(fld, efer); 7022 report_prefix_pushf("%s %lx", fld_name, efer); 7023 test_efer_vmlaunch(fld, true); 7024 report_prefix_pop(); 7025 } 7026 } 7027 7028 vmcs_write(ctrl_fld, ctrl_saved | ctrl_bit1); 7029 for (i = 0; i < 64; i++) { 7030 if ((1ull << i) & efer_reserved_bits) { 7031 efer = efer_saved | (1ull << i); 7032 vmcs_write(fld, efer); 7033 report_prefix_pushf("%s %lx", fld_name, efer); 7034 test_efer_vmlaunch(fld, false); 7035 report_prefix_pop(); 7036 } 7037 } 7038 7039 vmcs_write(ctrl_fld, ctrl_saved); 7040 vmcs_write(fld, efer_saved); 7041 7042 /* 7043 * Check LMA and LME bits 7044 */ 7045 test_efer_bit(fld, fld_name, 7046 ctrl_fld, ctrl_bit1, 7047 EFER_LMA, 7048 "EFER_LMA"); 7049 test_efer_bit(fld, fld_name, 7050 ctrl_fld, ctrl_bit1, 7051 EFER_LME, 7052 "EFER_LME"); 7053 7054 test_entry_exit_mode: 7055 test_efer_bit(fld, fld_name, 7056 ctrl_fld, ctrl_bit2, 7057 EFER_LMA, 7058 "EFER_LMA"); 7059 test_efer_bit(fld, fld_name, 7060 ctrl_fld, ctrl_bit2, 7061 EFER_LME, 7062 "EFER_LME"); 7063 } 7064 7065 /* 7066 * If the 'load IA32_EFER' VM-exit control is 1, bits reserved in the 7067 * IA32_EFER MSR must be 0 in the field for that register. In addition, 7068 * the values of the LMA and LME bits in the field must each be that of 7069 * the 'host address-space size' VM-exit control. 7070 * 7071 * [Intel SDM] 7072 */ 7073 static void test_host_efer(void) 7074 { 7075 test_efer(HOST_EFER, "HOST_EFER", EXI_CONTROLS, 7076 ctrl_exit_rev.clr & EXI_LOAD_EFER, 7077 EXI_HOST_64); 7078 } 7079 7080 /* 7081 * If the 'load IA32_EFER' VM-enter control is 1, bits reserved in the 7082 * IA32_EFER MSR must be 0 in the field for that register. In addition, 7083 * the values of the LMA and LME bits in the field must each be that of 7084 * the 'IA32e-mode guest' VM-exit control. 7085 */ 7086 static void test_guest_efer(void) 7087 { 7088 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) { 7089 printf("\"Load-IA32-EFER\" entry control not supported\n"); 7090 return; 7091 } 7092 7093 vmcs_write(GUEST_EFER, rdmsr(MSR_EFER)); 7094 test_efer(GUEST_EFER, "GUEST_EFER", ENT_CONTROLS, 7095 ctrl_enter_rev.clr & ENT_LOAD_EFER, 7096 ENT_GUEST_64); 7097 } 7098 7099 /* 7100 * PAT values higher than 8 are uninteresting since they're likely lumped 7101 * in with "8". We only test values above 8 one bit at a time, 7102 * in order to reduce the number of VM-Entries and keep the runtime reasonable. 7103 */ 7104 #define PAT_VAL_LIMIT 8 7105 7106 static void test_pat(u32 field, const char * field_name, u32 ctrl_field, 7107 u64 ctrl_bit) 7108 { 7109 u32 ctrl_saved = vmcs_read(ctrl_field); 7110 u64 pat_saved = vmcs_read(field); 7111 u64 i, val; 7112 u32 j; 7113 int error; 7114 7115 vmcs_clear_bits(ctrl_field, ctrl_bit); 7116 7117 for (i = 0; i < 256; i = (i < PAT_VAL_LIMIT) ? i + 1 : i * 2) { 7118 /* Test PAT0..PAT7 fields */ 7119 for (j = 0; j < (i ? 8 : 1); j++) { 7120 val = i << j * 8; 7121 vmcs_write(field, val); 7122 if (field == HOST_PAT) { 7123 report_prefix_pushf("%s %lx", field_name, val); 7124 test_vmx_vmlaunch(0); 7125 report_prefix_pop(); 7126 7127 } else { // GUEST_PAT 7128 test_guest_state("ENT_LOAD_PAT enabled", false, 7129 val, "GUEST_PAT"); 7130 } 7131 } 7132 } 7133 7134 vmcs_set_bits(ctrl_field, ctrl_bit); 7135 for (i = 0; i < 256; i = (i < PAT_VAL_LIMIT) ? i + 1 : i * 2) { 7136 /* Test PAT0..PAT7 fields */ 7137 for (j = 0; j < (i ? 8 : 1); j++) { 7138 val = i << j * 8; 7139 vmcs_write(field, val); 7140 7141 if (field == HOST_PAT) { 7142 report_prefix_pushf("%s %lx", field_name, val); 7143 if (i == 0x2 || i == 0x3 || i >= 0x8) 7144 error = 7145 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD; 7146 else 7147 error = 0; 7148 7149 test_vmx_vmlaunch(error); 7150 report_prefix_pop(); 7151 7152 } else { // GUEST_PAT 7153 error = (i == 0x2 || i == 0x3 || i >= 0x8); 7154 test_guest_state("ENT_LOAD_PAT enabled", !!error, 7155 val, "GUEST_PAT"); 7156 } 7157 7158 } 7159 } 7160 7161 vmcs_write(ctrl_field, ctrl_saved); 7162 vmcs_write(field, pat_saved); 7163 } 7164 7165 /* 7166 * If the "load IA32_PAT" VM-exit control is 1, the value of the field 7167 * for the IA32_PAT MSR must be one that could be written by WRMSR 7168 * without fault at CPL 0. Specifically, each of the 8 bytes in the 7169 * field must have one of the values 0 (UC), 1 (WC), 4 (WT), 5 (WP), 7170 * 6 (WB), or 7 (UC-). 7171 * 7172 * [Intel SDM] 7173 */ 7174 static void test_load_host_pat(void) 7175 { 7176 /* 7177 * "load IA32_PAT" VM-exit control 7178 */ 7179 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) { 7180 printf("\"Load-IA32-PAT\" exit control not supported\n"); 7181 return; 7182 } 7183 7184 test_pat(HOST_PAT, "HOST_PAT", EXI_CONTROLS, EXI_LOAD_PAT); 7185 } 7186 7187 union cpuidA_eax { 7188 struct { 7189 unsigned int version_id:8; 7190 unsigned int num_counters_gp:8; 7191 unsigned int bit_width:8; 7192 unsigned int mask_length:8; 7193 } split; 7194 unsigned int full; 7195 }; 7196 7197 union cpuidA_edx { 7198 struct { 7199 unsigned int num_counters_fixed:5; 7200 unsigned int bit_width_fixed:8; 7201 unsigned int reserved:9; 7202 } split; 7203 unsigned int full; 7204 }; 7205 7206 static bool valid_pgc(u64 val) 7207 { 7208 struct cpuid id; 7209 union cpuidA_eax eax; 7210 union cpuidA_edx edx; 7211 u64 mask; 7212 7213 id = cpuid(0xA); 7214 eax.full = id.a; 7215 edx.full = id.d; 7216 mask = ~(((1ull << eax.split.num_counters_gp) - 1) | 7217 (((1ull << edx.split.num_counters_fixed) - 1) << 32)); 7218 7219 return !(val & mask); 7220 } 7221 7222 static void test_pgc_vmlaunch(u32 xerror, u32 xreason, bool xfail, bool host) 7223 { 7224 u32 inst_err; 7225 u64 obs; 7226 bool success; 7227 struct vmx_state_area_test_data *data = &vmx_state_area_test_data; 7228 7229 if (host) { 7230 success = vmlaunch_succeeds(); 7231 obs = rdmsr(data->msr); 7232 if (!success) { 7233 inst_err = vmcs_read(VMX_INST_ERROR); 7234 report(xerror == inst_err, "vmlaunch failed, " 7235 "VMX Inst Error is %d (expected %d)", 7236 inst_err, xerror); 7237 } else { 7238 report(!data->enabled || data->exp == obs, 7239 "Host state is 0x%lx (expected 0x%lx)", 7240 obs, data->exp); 7241 report(success != xfail, "vmlaunch succeeded"); 7242 } 7243 } else { 7244 test_guest_state("load GUEST_PERF_GLOBAL_CTRL", xfail, 7245 GUEST_PERF_GLOBAL_CTRL, 7246 "GUEST_PERF_GLOBAL_CTRL"); 7247 } 7248 } 7249 7250 /* 7251 * test_load_perf_global_ctrl is a generic function for testing the 7252 * "load IA32_PERF_GLOBAL_CTRL" VM-{Entry,Exit} controls. This test function 7253 * tests the provided ctrl_val when disabled and enabled. 7254 * 7255 * @nr: VMCS field number corresponding to the host/guest state field 7256 * @name: Name of the above VMCS field for printing in test report 7257 * @ctrl_nr: VMCS field number corresponding to the VM-{Entry,Exit} control 7258 * @ctrl_val: Bit to set on the ctrl_field 7259 */ 7260 static void test_perf_global_ctrl(u32 nr, const char *name, u32 ctrl_nr, 7261 const char *ctrl_name, u64 ctrl_val) 7262 { 7263 u64 ctrl_saved = vmcs_read(ctrl_nr); 7264 u64 pgc_saved = vmcs_read(nr); 7265 u64 i, val; 7266 bool host = nr == HOST_PERF_GLOBAL_CTRL; 7267 struct vmx_state_area_test_data *data = &vmx_state_area_test_data; 7268 7269 data->msr = MSR_CORE_PERF_GLOBAL_CTRL; 7270 msr_bmp_init(); 7271 vmcs_write(ctrl_nr, ctrl_saved & ~ctrl_val); 7272 data->enabled = false; 7273 report_prefix_pushf("\"load IA32_PERF_GLOBAL_CTRL\"=0 on %s", 7274 ctrl_name); 7275 7276 for (i = 0; i < 64; i++) { 7277 val = 1ull << i; 7278 vmcs_write(nr, val); 7279 report_prefix_pushf("%s = 0x%lx", name, val); 7280 test_pgc_vmlaunch(0, VMX_VMCALL, false, host); 7281 report_prefix_pop(); 7282 } 7283 report_prefix_pop(); 7284 7285 vmcs_write(ctrl_nr, ctrl_saved | ctrl_val); 7286 data->enabled = true; 7287 report_prefix_pushf("\"load IA32_PERF_GLOBAL_CTRL\"=1 on %s", 7288 ctrl_name); 7289 for (i = 0; i < 64; i++) { 7290 val = 1ull << i; 7291 data->exp = val; 7292 vmcs_write(nr, val); 7293 report_prefix_pushf("%s = 0x%lx", name, val); 7294 if (valid_pgc(val)) { 7295 test_pgc_vmlaunch(0, VMX_VMCALL, false, host); 7296 } else { 7297 if (host) 7298 test_pgc_vmlaunch( 7299 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, 7300 0, 7301 true, 7302 host); 7303 else 7304 test_pgc_vmlaunch( 7305 0, 7306 VMX_ENTRY_FAILURE | VMX_FAIL_STATE, 7307 true, 7308 host); 7309 } 7310 report_prefix_pop(); 7311 } 7312 7313 data->enabled = false; 7314 report_prefix_pop(); 7315 vmcs_write(ctrl_nr, ctrl_saved); 7316 vmcs_write(nr, pgc_saved); 7317 } 7318 7319 static void test_load_host_perf_global_ctrl(void) 7320 { 7321 if (!(ctrl_exit_rev.clr & EXI_LOAD_PERF)) { 7322 printf("\"load IA32_PERF_GLOBAL_CTRL\" exit control not supported\n"); 7323 return; 7324 } 7325 7326 test_perf_global_ctrl(HOST_PERF_GLOBAL_CTRL, "HOST_PERF_GLOBAL_CTRL", 7327 EXI_CONTROLS, "EXI_CONTROLS", EXI_LOAD_PERF); 7328 } 7329 7330 7331 static void test_load_guest_perf_global_ctrl(void) 7332 { 7333 if (!(ctrl_enter_rev.clr & ENT_LOAD_PERF)) { 7334 printf("\"load IA32_PERF_GLOBAL_CTRL\" entry control not supported\n"); 7335 return; 7336 } 7337 7338 test_perf_global_ctrl(GUEST_PERF_GLOBAL_CTRL, "GUEST_PERF_GLOBAL_CTRL", 7339 ENT_CONTROLS, "ENT_CONTROLS", ENT_LOAD_PERF); 7340 } 7341 7342 7343 /* 7344 * test_vmcs_field - test a value for the given VMCS field 7345 * @field: VMCS field 7346 * @field_name: string name of VMCS field 7347 * @bit_start: starting bit 7348 * @bit_end: ending bit 7349 * @val: value that the bit range must or must not contain 7350 * @valid_val: whether value given in 'val' must be valid or not 7351 * @error: expected VMCS error when vmentry fails for an invalid value 7352 */ 7353 static void test_vmcs_field(u64 field, const char *field_name, u32 bit_start, 7354 u32 bit_end, u64 val, bool valid_val, u32 error) 7355 { 7356 u64 field_saved = vmcs_read(field); 7357 u32 i; 7358 u64 tmp; 7359 u32 bit_on; 7360 u64 mask = ~0ull; 7361 7362 mask = (mask >> bit_end) << bit_end; 7363 mask = mask | ((1 << bit_start) - 1); 7364 tmp = (field_saved & mask) | (val << bit_start); 7365 7366 vmcs_write(field, tmp); 7367 report_prefix_pushf("%s %lx", field_name, tmp); 7368 if (valid_val) 7369 test_vmx_vmlaunch(0); 7370 else 7371 test_vmx_vmlaunch(error); 7372 report_prefix_pop(); 7373 7374 for (i = bit_start; i <= bit_end; i = i + 2) { 7375 bit_on = ((1ull < i) & (val << bit_start)) ? 0 : 1; 7376 if (bit_on) 7377 tmp = field_saved | (1ull << i); 7378 else 7379 tmp = field_saved & ~(1ull << i); 7380 vmcs_write(field, tmp); 7381 report_prefix_pushf("%s %lx", field_name, tmp); 7382 if (valid_val) 7383 test_vmx_vmlaunch(error); 7384 else 7385 test_vmx_vmlaunch(0); 7386 report_prefix_pop(); 7387 } 7388 7389 vmcs_write(field, field_saved); 7390 } 7391 7392 static void test_canonical(u64 field, const char * field_name, bool host) 7393 { 7394 u64 addr_saved = vmcs_read(field); 7395 7396 /* 7397 * Use the existing value if possible. Writing a random canonical 7398 * value is not an option as doing so would corrupt the field being 7399 * tested and likely hose the test. 7400 */ 7401 if (is_canonical(addr_saved)) { 7402 if (host) { 7403 report_prefix_pushf("%s %lx", field_name, addr_saved); 7404 test_vmx_vmlaunch(0); 7405 report_prefix_pop(); 7406 } else { 7407 test_guest_state("Test canonical address", false, 7408 addr_saved, field_name); 7409 } 7410 } 7411 7412 vmcs_write(field, NONCANONICAL); 7413 7414 if (host) { 7415 report_prefix_pushf("%s %llx", field_name, NONCANONICAL); 7416 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7417 report_prefix_pop(); 7418 } else { 7419 test_guest_state("Test non-canonical address", true, 7420 NONCANONICAL, field_name); 7421 } 7422 7423 vmcs_write(field, addr_saved); 7424 } 7425 7426 #define TEST_RPL_TI_FLAGS(reg, name) \ 7427 test_vmcs_field(reg, name, 0, 2, 0x0, true, \ 7428 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7429 7430 #define TEST_CS_TR_FLAGS(reg, name) \ 7431 test_vmcs_field(reg, name, 3, 15, 0x0000, false, \ 7432 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7433 7434 /* 7435 * 1. In the selector field for each of CS, SS, DS, ES, FS, GS and TR, the 7436 * RPL (bits 1:0) and the TI flag (bit 2) must be 0. 7437 * 2. The selector fields for CS and TR cannot be 0000H. 7438 * 3. The selector field for SS cannot be 0000H if the "host address-space 7439 * size" VM-exit control is 0. 7440 * 4. On processors that support Intel 64 architecture, the base-address 7441 * fields for FS, GS and TR must contain canonical addresses. 7442 */ 7443 static void test_host_segment_regs(void) 7444 { 7445 u16 selector_saved; 7446 7447 /* 7448 * Test RPL and TI flags 7449 */ 7450 TEST_RPL_TI_FLAGS(HOST_SEL_CS, "HOST_SEL_CS"); 7451 TEST_RPL_TI_FLAGS(HOST_SEL_SS, "HOST_SEL_SS"); 7452 TEST_RPL_TI_FLAGS(HOST_SEL_DS, "HOST_SEL_DS"); 7453 TEST_RPL_TI_FLAGS(HOST_SEL_ES, "HOST_SEL_ES"); 7454 TEST_RPL_TI_FLAGS(HOST_SEL_FS, "HOST_SEL_FS"); 7455 TEST_RPL_TI_FLAGS(HOST_SEL_GS, "HOST_SEL_GS"); 7456 TEST_RPL_TI_FLAGS(HOST_SEL_TR, "HOST_SEL_TR"); 7457 7458 /* 7459 * Test that CS and TR fields can not be 0x0000 7460 */ 7461 TEST_CS_TR_FLAGS(HOST_SEL_CS, "HOST_SEL_CS"); 7462 TEST_CS_TR_FLAGS(HOST_SEL_TR, "HOST_SEL_TR"); 7463 7464 /* 7465 * SS field can not be 0x0000 if "host address-space size" VM-exit 7466 * control is 0 7467 */ 7468 selector_saved = vmcs_read(HOST_SEL_SS); 7469 vmcs_write(HOST_SEL_SS, 0); 7470 report_prefix_pushf("HOST_SEL_SS 0"); 7471 if (vmcs_read(EXI_CONTROLS) & EXI_HOST_64) { 7472 test_vmx_vmlaunch(0); 7473 } else { 7474 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7475 } 7476 report_prefix_pop(); 7477 7478 vmcs_write(HOST_SEL_SS, selector_saved); 7479 7480 #ifdef __x86_64__ 7481 /* 7482 * Base address for FS, GS and TR must be canonical 7483 */ 7484 test_canonical(HOST_BASE_FS, "HOST_BASE_FS", true); 7485 test_canonical(HOST_BASE_GS, "HOST_BASE_GS", true); 7486 test_canonical(HOST_BASE_TR, "HOST_BASE_TR", true); 7487 #endif 7488 } 7489 7490 /* 7491 * On processors that support Intel 64 architecture, the base-address 7492 * fields for GDTR and IDTR must contain canonical addresses. 7493 */ 7494 static void test_host_desc_tables(void) 7495 { 7496 #ifdef __x86_64__ 7497 test_canonical(HOST_BASE_GDTR, "HOST_BASE_GDTR", true); 7498 test_canonical(HOST_BASE_IDTR, "HOST_BASE_IDTR", true); 7499 #endif 7500 } 7501 7502 /* 7503 * If the "host address-space size" VM-exit control is 0, the following must 7504 * hold: 7505 * - The "IA-32e mode guest" VM-entry control is 0. 7506 * - Bit 17 of the CR4 field (corresponding to CR4.PCIDE) is 0. 7507 * - Bits 63:32 in the RIP field are 0. 7508 * 7509 * If the "host address-space size" VM-exit control is 1, the following must 7510 * hold: 7511 * - Bit 5 of the CR4 field (corresponding to CR4.PAE) is 1. 7512 * - The RIP field contains a canonical address. 7513 * 7514 */ 7515 static void test_host_addr_size(void) 7516 { 7517 u64 cr4_saved = vmcs_read(HOST_CR4); 7518 u64 rip_saved = vmcs_read(HOST_RIP); 7519 u64 entry_ctrl_saved = vmcs_read(ENT_CONTROLS); 7520 int i; 7521 u64 tmp; 7522 7523 if (vmcs_read(EXI_CONTROLS) & EXI_HOST_64) { 7524 vmcs_write(ENT_CONTROLS, entry_ctrl_saved | ENT_GUEST_64); 7525 report_prefix_pushf("\"IA-32e mode guest\" enabled"); 7526 test_vmx_vmlaunch(0); 7527 report_prefix_pop(); 7528 7529 vmcs_write(HOST_CR4, cr4_saved | X86_CR4_PCIDE); 7530 report_prefix_pushf("\"CR4.PCIDE\" set"); 7531 test_vmx_vmlaunch(0); 7532 report_prefix_pop(); 7533 7534 for (i = 32; i <= 63; i = i + 4) { 7535 tmp = rip_saved | 1ull << i; 7536 vmcs_write(HOST_RIP, tmp); 7537 report_prefix_pushf("HOST_RIP %lx", tmp); 7538 test_vmx_vmlaunch(0); 7539 report_prefix_pop(); 7540 } 7541 7542 if (cr4_saved & X86_CR4_PAE) { 7543 vmcs_write(HOST_CR4, cr4_saved & ~X86_CR4_PAE); 7544 report_prefix_pushf("\"CR4.PAE\" unset"); 7545 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7546 } else { 7547 report_prefix_pushf("\"CR4.PAE\" set"); 7548 test_vmx_vmlaunch(0); 7549 } 7550 report_prefix_pop(); 7551 7552 vmcs_write(HOST_RIP, NONCANONICAL); 7553 report_prefix_pushf("HOST_RIP %llx", NONCANONICAL); 7554 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7555 report_prefix_pop(); 7556 7557 vmcs_write(ENT_CONTROLS, entry_ctrl_saved | ENT_GUEST_64); 7558 vmcs_write(HOST_RIP, rip_saved); 7559 vmcs_write(HOST_CR4, cr4_saved); 7560 } 7561 } 7562 7563 /* 7564 * Check that the virtual CPU checks the VMX Host State Area as 7565 * documented in the Intel SDM. 7566 */ 7567 static void vmx_host_state_area_test(void) 7568 { 7569 /* 7570 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 7571 * fail due to invalid guest state, should we make it that 7572 * far. 7573 */ 7574 vmcs_write(GUEST_RFLAGS, 0); 7575 7576 test_host_ctl_regs(); 7577 7578 test_canonical(HOST_SYSENTER_ESP, "HOST_SYSENTER_ESP", true); 7579 test_canonical(HOST_SYSENTER_EIP, "HOST_SYSENTER_EIP", true); 7580 7581 test_host_efer(); 7582 test_load_host_pat(); 7583 test_host_segment_regs(); 7584 test_host_desc_tables(); 7585 test_host_addr_size(); 7586 test_load_host_perf_global_ctrl(); 7587 } 7588 7589 /* 7590 * If the "load debug controls" VM-entry control is 1, bits 63:32 in 7591 * the DR7 field must be 0. 7592 * 7593 * [Intel SDM] 7594 */ 7595 static void test_guest_dr7(void) 7596 { 7597 u32 ent_saved = vmcs_read(ENT_CONTROLS); 7598 u64 dr7_saved = vmcs_read(GUEST_DR7); 7599 u64 val; 7600 int i; 7601 7602 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS) { 7603 vmcs_clear_bits(ENT_CONTROLS, ENT_LOAD_DBGCTLS); 7604 for (i = 0; i < 64; i++) { 7605 val = 1ull << i; 7606 vmcs_write(GUEST_DR7, val); 7607 test_guest_state("ENT_LOAD_DBGCTLS disabled", false, 7608 val, "GUEST_DR7"); 7609 } 7610 } 7611 if (ctrl_enter_rev.clr & ENT_LOAD_DBGCTLS) { 7612 vmcs_set_bits(ENT_CONTROLS, ENT_LOAD_DBGCTLS); 7613 for (i = 0; i < 64; i++) { 7614 val = 1ull << i; 7615 vmcs_write(GUEST_DR7, val); 7616 test_guest_state("ENT_LOAD_DBGCTLS enabled", i >= 32, 7617 val, "GUEST_DR7"); 7618 } 7619 } 7620 vmcs_write(GUEST_DR7, dr7_saved); 7621 vmcs_write(ENT_CONTROLS, ent_saved); 7622 } 7623 7624 /* 7625 * If the "load IA32_PAT" VM-entry control is 1, the value of the field 7626 * for the IA32_PAT MSR must be one that could be written by WRMSR 7627 * without fault at CPL 0. Specifically, each of the 8 bytes in the 7628 * field must have one of the values 0 (UC), 1 (WC), 4 (WT), 5 (WP), 7629 * 6 (WB), or 7 (UC-). 7630 * 7631 * [Intel SDM] 7632 */ 7633 static void test_load_guest_pat(void) 7634 { 7635 /* 7636 * "load IA32_PAT" VM-entry control 7637 */ 7638 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 7639 printf("\"Load-IA32-PAT\" entry control not supported\n"); 7640 return; 7641 } 7642 7643 test_pat(GUEST_PAT, "GUEST_PAT", ENT_CONTROLS, ENT_LOAD_PAT); 7644 } 7645 7646 #define MSR_IA32_BNDCFGS_RSVD_MASK 0x00000ffc 7647 7648 /* 7649 * If the “load IA32_BNDCFGS†VM-entry control is 1, the following 7650 * checks are performed on the field for the IA32_BNDCFGS MSR: 7651 * 7652 * — Bits reserved in the IA32_BNDCFGS MSR must be 0. 7653 * — The linear address in bits 63:12 must be canonical. 7654 * 7655 * [Intel SDM] 7656 */ 7657 static void test_load_guest_bndcfgs(void) 7658 { 7659 u64 bndcfgs_saved = vmcs_read(GUEST_BNDCFGS); 7660 u64 bndcfgs; 7661 7662 if (!(ctrl_enter_rev.clr & ENT_LOAD_BNDCFGS)) { 7663 printf("\"Load-IA32-BNDCFGS\" entry control not supported\n"); 7664 return; 7665 } 7666 7667 vmcs_clear_bits(ENT_CONTROLS, ENT_LOAD_BNDCFGS); 7668 7669 vmcs_write(GUEST_BNDCFGS, NONCANONICAL); 7670 test_guest_state("ENT_LOAD_BNDCFGS disabled", false, 7671 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7672 bndcfgs = bndcfgs_saved | MSR_IA32_BNDCFGS_RSVD_MASK; 7673 vmcs_write(GUEST_BNDCFGS, bndcfgs); 7674 test_guest_state("ENT_LOAD_BNDCFGS disabled", false, 7675 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7676 7677 vmcs_set_bits(ENT_CONTROLS, ENT_LOAD_BNDCFGS); 7678 7679 vmcs_write(GUEST_BNDCFGS, NONCANONICAL); 7680 test_guest_state("ENT_LOAD_BNDCFGS enabled", true, 7681 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7682 bndcfgs = bndcfgs_saved | MSR_IA32_BNDCFGS_RSVD_MASK; 7683 vmcs_write(GUEST_BNDCFGS, bndcfgs); 7684 test_guest_state("ENT_LOAD_BNDCFGS enabled", true, 7685 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7686 7687 vmcs_write(GUEST_BNDCFGS, bndcfgs_saved); 7688 } 7689 7690 /* 7691 * Check that the virtual CPU checks the VMX Guest State Area as 7692 * documented in the Intel SDM. 7693 */ 7694 static void vmx_guest_state_area_test(void) 7695 { 7696 vmx_set_test_stage(1); 7697 test_set_guest(guest_state_test_main); 7698 7699 /* 7700 * The IA32_SYSENTER_ESP field and the IA32_SYSENTER_EIP field 7701 * must each contain a canonical address. 7702 */ 7703 test_canonical(GUEST_SYSENTER_ESP, "GUEST_SYSENTER_ESP", false); 7704 test_canonical(GUEST_SYSENTER_EIP, "GUEST_SYSENTER_EIP", false); 7705 7706 test_guest_dr7(); 7707 test_load_guest_pat(); 7708 test_guest_efer(); 7709 test_load_guest_perf_global_ctrl(); 7710 test_load_guest_bndcfgs(); 7711 7712 /* 7713 * Let the guest finish execution 7714 */ 7715 vmx_set_test_stage(2); 7716 enter_guest(); 7717 } 7718 7719 static bool valid_vmcs_for_vmentry(void) 7720 { 7721 struct vmcs *current_vmcs = NULL; 7722 7723 if (vmcs_save(¤t_vmcs)) 7724 return false; 7725 7726 return current_vmcs && !current_vmcs->hdr.shadow_vmcs; 7727 } 7728 7729 static void try_vmentry_in_movss_shadow(void) 7730 { 7731 u32 vm_inst_err; 7732 u32 flags; 7733 bool early_failure = false; 7734 u32 expected_flags = X86_EFLAGS_FIXED; 7735 bool valid_vmcs = valid_vmcs_for_vmentry(); 7736 7737 expected_flags |= valid_vmcs ? X86_EFLAGS_ZF : X86_EFLAGS_CF; 7738 7739 /* 7740 * Indirectly set VM_INST_ERR to 12 ("VMREAD/VMWRITE from/to 7741 * unsupported VMCS component"). 7742 */ 7743 vmcs_write(~0u, 0); 7744 7745 __asm__ __volatile__ ("mov %[host_rsp], %%edx;" 7746 "vmwrite %%rsp, %%rdx;" 7747 "mov 0f, %%rax;" 7748 "mov %[host_rip], %%edx;" 7749 "vmwrite %%rax, %%rdx;" 7750 "mov $-1, %%ah;" 7751 "sahf;" 7752 "mov %%ss, %%ax;" 7753 "mov %%ax, %%ss;" 7754 "vmlaunch;" 7755 "mov $1, %[early_failure];" 7756 "0: lahf;" 7757 "movzbl %%ah, %[flags]" 7758 : [early_failure] "+r" (early_failure), 7759 [flags] "=&a" (flags) 7760 : [host_rsp] "i" (HOST_RSP), 7761 [host_rip] "i" (HOST_RIP) 7762 : "rdx", "cc", "memory"); 7763 vm_inst_err = vmcs_read(VMX_INST_ERROR); 7764 7765 report(early_failure, "Early VM-entry failure"); 7766 report(flags == expected_flags, "RFLAGS[8:0] is %x (actual %x)", 7767 expected_flags, flags); 7768 if (valid_vmcs) 7769 report(vm_inst_err == VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, 7770 "VM-instruction error is %d (actual %d)", 7771 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, vm_inst_err); 7772 } 7773 7774 static void vmentry_movss_shadow_test(void) 7775 { 7776 struct vmcs *orig_vmcs; 7777 7778 TEST_ASSERT(!vmcs_save(&orig_vmcs)); 7779 7780 /* 7781 * Set the launched flag on the current VMCS to verify the correct 7782 * error priority, below. 7783 */ 7784 test_set_guest(v2_null_test_guest); 7785 enter_guest(); 7786 7787 /* 7788 * With bit 1 of the guest's RFLAGS clear, VM-entry should 7789 * fail due to invalid guest state (if we make it that far). 7790 */ 7791 vmcs_write(GUEST_RFLAGS, 0); 7792 7793 /* 7794 * "VM entry with events blocked by MOV SS" takes precedence over 7795 * "VMLAUNCH with non-clear VMCS." 7796 */ 7797 report_prefix_push("valid current-VMCS"); 7798 try_vmentry_in_movss_shadow(); 7799 report_prefix_pop(); 7800 7801 /* 7802 * VMfailInvalid takes precedence over "VM entry with events 7803 * blocked by MOV SS." 7804 */ 7805 TEST_ASSERT(!vmcs_clear(orig_vmcs)); 7806 report_prefix_push("no current-VMCS"); 7807 try_vmentry_in_movss_shadow(); 7808 report_prefix_pop(); 7809 7810 TEST_ASSERT(!make_vmcs_current(orig_vmcs)); 7811 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 7812 } 7813 7814 static void vmx_cr_load_test(void) 7815 { 7816 unsigned long cr3, cr4, orig_cr3, orig_cr4; 7817 7818 orig_cr4 = read_cr4(); 7819 orig_cr3 = read_cr3(); 7820 7821 if (!this_cpu_has(X86_FEATURE_PCID)) { 7822 report_skip("PCID not detected"); 7823 return; 7824 } 7825 if (!this_cpu_has(X86_FEATURE_MCE)) { 7826 report_skip("MCE not detected"); 7827 return; 7828 } 7829 7830 TEST_ASSERT(!(orig_cr3 & X86_CR3_PCID_MASK)); 7831 7832 /* Enable PCID for L1. */ 7833 cr4 = orig_cr4 | X86_CR4_PCIDE; 7834 cr3 = orig_cr3 | 0x1; 7835 TEST_ASSERT(!write_cr4_checking(cr4)); 7836 write_cr3(cr3); 7837 7838 test_set_guest(v2_null_test_guest); 7839 vmcs_write(HOST_CR4, cr4); 7840 vmcs_write(HOST_CR3, cr3); 7841 enter_guest(); 7842 7843 /* 7844 * No exception is expected. 7845 * 7846 * NB. KVM loads the last guest write to CR4 into CR4 read 7847 * shadow. In order to trigger an exit to KVM, we can toggle a 7848 * bit that is owned by KVM. We use CR4.MCE, which shall 7849 * have no side effect because normally no guest MCE (e.g., as the 7850 * result of bad memory) would happen during this test. 7851 */ 7852 TEST_ASSERT(!write_cr4_checking(cr4 ^ X86_CR4_MCE)); 7853 7854 /* Cleanup L1 state. */ 7855 write_cr3(orig_cr3); 7856 TEST_ASSERT(!write_cr4_checking(orig_cr4)); 7857 } 7858 7859 static void vmx_nm_test_guest(void) 7860 { 7861 write_cr0(read_cr0() | X86_CR0_TS); 7862 asm volatile("fnop"); 7863 } 7864 7865 static void check_nm_exit(const char *test) 7866 { 7867 u32 reason = vmcs_read(EXI_REASON); 7868 u32 intr_info = vmcs_read(EXI_INTR_INFO); 7869 const u32 expected = INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 7870 NM_VECTOR; 7871 7872 report(reason == VMX_EXC_NMI && intr_info == expected, "%s", test); 7873 } 7874 7875 /* 7876 * This test checks that: 7877 * 7878 * (a) If L2 launches with CR0.TS clear, but later sets CR0.TS, then 7879 * a subsequent #NM VM-exit is reflected to L1. 7880 * 7881 * (b) If L2 launches with CR0.TS clear and CR0.EM set, then a 7882 * subsequent #NM VM-exit is reflected to L1. 7883 */ 7884 static void vmx_nm_test(void) 7885 { 7886 unsigned long cr0 = read_cr0(); 7887 7888 test_set_guest(vmx_nm_test_guest); 7889 7890 /* 7891 * L1 wants to intercept #NM exceptions encountered in L2. 7892 */ 7893 vmcs_write(EXC_BITMAP, 1 << NM_VECTOR); 7894 7895 /* 7896 * Launch L2 with CR0.TS clear, but don't claim host ownership of 7897 * any CR0 bits. L2 will set CR0.TS and then try to execute fnop, 7898 * which will raise #NM. L0 should reflect the #NM VM-exit to L1. 7899 */ 7900 vmcs_write(CR0_MASK, 0); 7901 vmcs_write(GUEST_CR0, cr0 & ~X86_CR0_TS); 7902 enter_guest(); 7903 check_nm_exit("fnop with CR0.TS set in L2 triggers #NM VM-exit to L1"); 7904 7905 /* 7906 * Re-enter L2 at the fnop instruction, with CR0.TS clear but 7907 * CR0.EM set. The fnop will still raise #NM, and L0 should 7908 * reflect the #NM VM-exit to L1. 7909 */ 7910 vmcs_write(GUEST_CR0, (cr0 & ~X86_CR0_TS) | X86_CR0_EM); 7911 enter_guest(); 7912 check_nm_exit("fnop with CR0.EM set in L2 triggers #NM VM-exit to L1"); 7913 7914 /* 7915 * Re-enter L2 at the fnop instruction, with both CR0.TS and 7916 * CR0.EM clear. There will be no #NM, and the L2 guest should 7917 * exit normally. 7918 */ 7919 vmcs_write(GUEST_CR0, cr0 & ~(X86_CR0_TS | X86_CR0_EM)); 7920 enter_guest(); 7921 } 7922 7923 bool vmx_pending_event_ipi_fired; 7924 static void vmx_pending_event_ipi_isr(isr_regs_t *regs) 7925 { 7926 vmx_pending_event_ipi_fired = true; 7927 eoi(); 7928 } 7929 7930 bool vmx_pending_event_guest_run; 7931 static void vmx_pending_event_guest(void) 7932 { 7933 vmcall(); 7934 vmx_pending_event_guest_run = true; 7935 } 7936 7937 static void vmx_pending_event_test_core(bool guest_hlt) 7938 { 7939 int ipi_vector = 0xf1; 7940 7941 vmx_pending_event_ipi_fired = false; 7942 handle_irq(ipi_vector, vmx_pending_event_ipi_isr); 7943 7944 vmx_pending_event_guest_run = false; 7945 test_set_guest(vmx_pending_event_guest); 7946 7947 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 7948 7949 enter_guest(); 7950 skip_exit_vmcall(); 7951 7952 if (guest_hlt) 7953 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 7954 7955 irq_disable(); 7956 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | 7957 APIC_DM_FIXED | ipi_vector, 7958 0); 7959 7960 enter_guest(); 7961 7962 assert_exit_reason(VMX_EXTINT); 7963 report(!vmx_pending_event_guest_run, 7964 "Guest did not run before host received IPI"); 7965 7966 irq_enable(); 7967 asm volatile ("nop"); 7968 irq_disable(); 7969 report(vmx_pending_event_ipi_fired, 7970 "Got pending interrupt after IRQ enabled"); 7971 7972 if (guest_hlt) 7973 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 7974 7975 enter_guest(); 7976 report(vmx_pending_event_guest_run, 7977 "Guest finished running when no interrupt"); 7978 } 7979 7980 static void vmx_pending_event_test(void) 7981 { 7982 vmx_pending_event_test_core(false); 7983 } 7984 7985 static void vmx_pending_event_hlt_test(void) 7986 { 7987 vmx_pending_event_test_core(true); 7988 } 7989 7990 static int vmx_window_test_db_count; 7991 7992 static void vmx_window_test_db_handler(struct ex_regs *regs) 7993 { 7994 vmx_window_test_db_count++; 7995 } 7996 7997 static void vmx_nmi_window_test_guest(void) 7998 { 7999 handle_exception(DB_VECTOR, vmx_window_test_db_handler); 8000 8001 asm volatile("vmcall\n\t" 8002 "nop\n\t"); 8003 8004 handle_exception(DB_VECTOR, NULL); 8005 } 8006 8007 static void verify_nmi_window_exit(u64 rip) 8008 { 8009 u32 exit_reason = vmcs_read(EXI_REASON); 8010 8011 report(exit_reason == VMX_NMI_WINDOW, 8012 "Exit reason (%d) is 'NMI window'", exit_reason); 8013 report(vmcs_read(GUEST_RIP) == rip, "RIP (%#lx) is %#lx", 8014 vmcs_read(GUEST_RIP), rip); 8015 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 8016 } 8017 8018 static void vmx_nmi_window_test(void) 8019 { 8020 u64 nop_addr; 8021 void *db_fault_addr = get_idt_addr(&boot_idt[DB_VECTOR]); 8022 8023 if (!(ctrl_pin_rev.clr & PIN_VIRT_NMI)) { 8024 report_skip("CPU does not support the \"Virtual NMIs\" VM-execution control."); 8025 return; 8026 } 8027 8028 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 8029 report_skip("CPU does not support the \"NMI-window exiting\" VM-execution control."); 8030 return; 8031 } 8032 8033 vmx_window_test_db_count = 0; 8034 8035 report_prefix_push("NMI-window"); 8036 test_set_guest(vmx_nmi_window_test_guest); 8037 vmcs_set_bits(PIN_CONTROLS, PIN_VIRT_NMI); 8038 enter_guest(); 8039 skip_exit_vmcall(); 8040 nop_addr = vmcs_read(GUEST_RIP); 8041 8042 /* 8043 * Ask for "NMI-window exiting," and expect an immediate VM-exit. 8044 * RIP will not advance. 8045 */ 8046 report_prefix_push("active, no blocking"); 8047 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 8048 enter_guest(); 8049 verify_nmi_window_exit(nop_addr); 8050 report_prefix_pop(); 8051 8052 /* 8053 * Ask for "NMI-window exiting" in a MOV-SS shadow, and expect 8054 * a VM-exit on the next instruction after the nop. (The nop 8055 * is one byte.) 8056 */ 8057 report_prefix_push("active, blocking by MOV-SS"); 8058 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 8059 enter_guest(); 8060 verify_nmi_window_exit(nop_addr + 1); 8061 report_prefix_pop(); 8062 8063 /* 8064 * Ask for "NMI-window exiting" (with event injection), and 8065 * expect a VM-exit after the event is injected. (RIP should 8066 * be at the address specified in the IDT entry for #DB.) 8067 */ 8068 report_prefix_push("active, no blocking, injecting #DB"); 8069 vmcs_write(ENT_INTR_INFO, 8070 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 8071 enter_guest(); 8072 verify_nmi_window_exit((u64)db_fault_addr); 8073 report_prefix_pop(); 8074 8075 /* 8076 * Ask for "NMI-window exiting" with NMI blocking, and expect 8077 * a VM-exit after the next IRET (i.e. after the #DB handler 8078 * returns). So, RIP should be back at one byte past the nop. 8079 */ 8080 report_prefix_push("active, blocking by NMI"); 8081 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_NMI); 8082 enter_guest(); 8083 verify_nmi_window_exit(nop_addr + 1); 8084 report(vmx_window_test_db_count == 1, 8085 "#DB handler executed once (actual %d times)", 8086 vmx_window_test_db_count); 8087 report_prefix_pop(); 8088 8089 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 8090 report_skip("CPU does not support activity state HLT."); 8091 } else { 8092 /* 8093 * Ask for "NMI-window exiting" when entering activity 8094 * state HLT, and expect an immediate VM-exit. RIP is 8095 * still one byte past the nop. 8096 */ 8097 report_prefix_push("halted, no blocking"); 8098 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8099 enter_guest(); 8100 verify_nmi_window_exit(nop_addr + 1); 8101 report_prefix_pop(); 8102 8103 /* 8104 * Ask for "NMI-window exiting" when entering activity 8105 * state HLT (with event injection), and expect a 8106 * VM-exit after the event is injected. (RIP should be 8107 * at the address specified in the IDT entry for #DB.) 8108 */ 8109 report_prefix_push("halted, no blocking, injecting #DB"); 8110 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8111 vmcs_write(ENT_INTR_INFO, 8112 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 8113 DB_VECTOR); 8114 enter_guest(); 8115 verify_nmi_window_exit((u64)db_fault_addr); 8116 report_prefix_pop(); 8117 } 8118 8119 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 8120 enter_guest(); 8121 report_prefix_pop(); 8122 } 8123 8124 static void vmx_intr_window_test_guest(void) 8125 { 8126 handle_exception(DB_VECTOR, vmx_window_test_db_handler); 8127 8128 /* 8129 * The two consecutive STIs are to ensure that only the first 8130 * one has a shadow. Note that NOP and STI are one byte 8131 * instructions. 8132 */ 8133 asm volatile("vmcall\n\t" 8134 "nop\n\t" 8135 "sti\n\t" 8136 "sti\n\t"); 8137 8138 handle_exception(DB_VECTOR, NULL); 8139 } 8140 8141 static void verify_intr_window_exit(u64 rip) 8142 { 8143 u32 exit_reason = vmcs_read(EXI_REASON); 8144 8145 report(exit_reason == VMX_INTR_WINDOW, 8146 "Exit reason (%d) is 'interrupt window'", exit_reason); 8147 report(vmcs_read(GUEST_RIP) == rip, "RIP (%#lx) is %#lx", 8148 vmcs_read(GUEST_RIP), rip); 8149 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 8150 } 8151 8152 static void vmx_intr_window_test(void) 8153 { 8154 u64 vmcall_addr; 8155 u64 nop_addr; 8156 unsigned int orig_db_gate_type; 8157 void *db_fault_addr = get_idt_addr(&boot_idt[DB_VECTOR]); 8158 8159 if (!(ctrl_cpu_rev[0].clr & CPU_INTR_WINDOW)) { 8160 report_skip("CPU does not support the \"interrupt-window exiting\" VM-execution control."); 8161 return; 8162 } 8163 8164 /* 8165 * Change the IDT entry for #DB from interrupt gate to trap gate, 8166 * so that it won't clear RFLAGS.IF. We don't want interrupts to 8167 * be disabled after vectoring a #DB. 8168 */ 8169 orig_db_gate_type = boot_idt[DB_VECTOR].type; 8170 boot_idt[DB_VECTOR].type = 15; 8171 8172 report_prefix_push("interrupt-window"); 8173 test_set_guest(vmx_intr_window_test_guest); 8174 enter_guest(); 8175 assert_exit_reason(VMX_VMCALL); 8176 vmcall_addr = vmcs_read(GUEST_RIP); 8177 8178 /* 8179 * Ask for "interrupt-window exiting" with RFLAGS.IF set and 8180 * no blocking; expect an immediate VM-exit. Note that we have 8181 * not advanced past the vmcall instruction yet, so RIP should 8182 * point to the vmcall instruction. 8183 */ 8184 report_prefix_push("active, no blocking, RFLAGS.IF=1"); 8185 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8186 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_IF); 8187 enter_guest(); 8188 verify_intr_window_exit(vmcall_addr); 8189 report_prefix_pop(); 8190 8191 /* 8192 * Ask for "interrupt-window exiting" (with event injection) 8193 * with RFLAGS.IF set and no blocking; expect a VM-exit after 8194 * the event is injected. That is, RIP should should be at the 8195 * address specified in the IDT entry for #DB. 8196 */ 8197 report_prefix_push("active, no blocking, RFLAGS.IF=1, injecting #DB"); 8198 vmcs_write(ENT_INTR_INFO, 8199 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 8200 vmcall_addr = vmcs_read(GUEST_RIP); 8201 enter_guest(); 8202 verify_intr_window_exit((u64)db_fault_addr); 8203 report_prefix_pop(); 8204 8205 /* 8206 * Let the L2 guest run through the IRET, back to the VMCALL. 8207 * We have to clear the "interrupt-window exiting" 8208 * VM-execution control, or it would just keep causing 8209 * VM-exits. Then, advance past the VMCALL and set the 8210 * "interrupt-window exiting" VM-execution control again. 8211 */ 8212 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8213 enter_guest(); 8214 skip_exit_vmcall(); 8215 nop_addr = vmcs_read(GUEST_RIP); 8216 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8217 8218 /* 8219 * Ask for "interrupt-window exiting" in a MOV-SS shadow with 8220 * RFLAGS.IF set, and expect a VM-exit on the next 8221 * instruction. (NOP is one byte.) 8222 */ 8223 report_prefix_push("active, blocking by MOV-SS, RFLAGS.IF=1"); 8224 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 8225 enter_guest(); 8226 verify_intr_window_exit(nop_addr + 1); 8227 report_prefix_pop(); 8228 8229 /* 8230 * Back up to the NOP and ask for "interrupt-window exiting" 8231 * in an STI shadow with RFLAGS.IF set, and expect a VM-exit 8232 * on the next instruction. (NOP is one byte.) 8233 */ 8234 report_prefix_push("active, blocking by STI, RFLAGS.IF=1"); 8235 vmcs_write(GUEST_RIP, nop_addr); 8236 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_STI); 8237 enter_guest(); 8238 verify_intr_window_exit(nop_addr + 1); 8239 report_prefix_pop(); 8240 8241 /* 8242 * Ask for "interrupt-window exiting" with RFLAGS.IF clear, 8243 * and expect a VM-exit on the instruction following the STI 8244 * shadow. Only the first STI (which is one byte past the NOP) 8245 * should have a shadow. The second STI (which is two bytes 8246 * past the NOP) has no shadow. Therefore, the interrupt 8247 * window opens at three bytes past the NOP. 8248 */ 8249 report_prefix_push("active, RFLAGS.IF = 0"); 8250 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 8251 enter_guest(); 8252 verify_intr_window_exit(nop_addr + 3); 8253 report_prefix_pop(); 8254 8255 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 8256 report_skip("CPU does not support activity state HLT."); 8257 } else { 8258 /* 8259 * Ask for "interrupt-window exiting" when entering 8260 * activity state HLT, and expect an immediate 8261 * VM-exit. RIP is still three bytes past the nop. 8262 */ 8263 report_prefix_push("halted, no blocking"); 8264 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8265 enter_guest(); 8266 verify_intr_window_exit(nop_addr + 3); 8267 report_prefix_pop(); 8268 8269 /* 8270 * Ask for "interrupt-window exiting" when entering 8271 * activity state HLT (with event injection), and 8272 * expect a VM-exit after the event is injected. That 8273 * is, RIP should should be at the address specified 8274 * in the IDT entry for #DB. 8275 */ 8276 report_prefix_push("halted, no blocking, injecting #DB"); 8277 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8278 vmcs_write(ENT_INTR_INFO, 8279 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 8280 DB_VECTOR); 8281 enter_guest(); 8282 verify_intr_window_exit((u64)db_fault_addr); 8283 report_prefix_pop(); 8284 } 8285 8286 boot_idt[DB_VECTOR].type = orig_db_gate_type; 8287 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8288 enter_guest(); 8289 report_prefix_pop(); 8290 } 8291 8292 #define GUEST_TSC_OFFSET (1u << 30) 8293 8294 static u64 guest_tsc; 8295 8296 static void vmx_store_tsc_test_guest(void) 8297 { 8298 guest_tsc = rdtsc(); 8299 } 8300 8301 /* 8302 * This test ensures that when IA32_TSC is in the VM-exit MSR-store 8303 * list, the value saved is not subject to the TSC offset that is 8304 * applied to RDTSC/RDTSCP/RDMSR(IA32_TSC) in guest execution. 8305 */ 8306 static void vmx_store_tsc_test(void) 8307 { 8308 struct vmx_msr_entry msr_entry = { .index = MSR_IA32_TSC }; 8309 u64 low, high; 8310 8311 if (!(ctrl_cpu_rev[0].clr & CPU_USE_TSC_OFFSET)) { 8312 report_skip("'Use TSC offsetting' not supported"); 8313 return; 8314 } 8315 8316 test_set_guest(vmx_store_tsc_test_guest); 8317 8318 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_USE_TSC_OFFSET); 8319 vmcs_write(EXI_MSR_ST_CNT, 1); 8320 vmcs_write(EXIT_MSR_ST_ADDR, virt_to_phys(&msr_entry)); 8321 vmcs_write(TSC_OFFSET, GUEST_TSC_OFFSET); 8322 8323 low = rdtsc(); 8324 enter_guest(); 8325 high = rdtsc(); 8326 8327 report(low + GUEST_TSC_OFFSET <= guest_tsc && 8328 guest_tsc <= high + GUEST_TSC_OFFSET, 8329 "RDTSC value in the guest (%lu) is in range [%lu, %lu]", 8330 guest_tsc, low + GUEST_TSC_OFFSET, high + GUEST_TSC_OFFSET); 8331 report(low <= msr_entry.value && msr_entry.value <= high, 8332 "IA32_TSC value saved in the VM-exit MSR-store list (%lu) is in range [%lu, %lu]", 8333 msr_entry.value, low, high); 8334 } 8335 8336 static void vmx_preemption_timer_zero_test_db_handler(struct ex_regs *regs) 8337 { 8338 } 8339 8340 static void vmx_preemption_timer_zero_test_guest(void) 8341 { 8342 while (vmx_get_test_stage() < 3) 8343 vmcall(); 8344 } 8345 8346 static void vmx_preemption_timer_zero_activate_preemption_timer(void) 8347 { 8348 vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT); 8349 vmcs_write(PREEMPT_TIMER_VALUE, 0); 8350 } 8351 8352 static void vmx_preemption_timer_zero_advance_past_vmcall(void) 8353 { 8354 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 8355 enter_guest(); 8356 skip_exit_vmcall(); 8357 } 8358 8359 static void vmx_preemption_timer_zero_inject_db(bool intercept_db) 8360 { 8361 vmx_preemption_timer_zero_activate_preemption_timer(); 8362 vmcs_write(ENT_INTR_INFO, INTR_INFO_VALID_MASK | 8363 INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 8364 vmcs_write(EXC_BITMAP, intercept_db ? 1 << DB_VECTOR : 0); 8365 enter_guest(); 8366 } 8367 8368 static void vmx_preemption_timer_zero_set_pending_dbg(u32 exception_bitmap) 8369 { 8370 vmx_preemption_timer_zero_activate_preemption_timer(); 8371 vmcs_write(GUEST_PENDING_DEBUG, BIT(12) | DR_TRAP1); 8372 vmcs_write(EXC_BITMAP, exception_bitmap); 8373 enter_guest(); 8374 } 8375 8376 static void vmx_preemption_timer_zero_expect_preempt_at_rip(u64 expected_rip) 8377 { 8378 u32 reason = (u32)vmcs_read(EXI_REASON); 8379 u64 guest_rip = vmcs_read(GUEST_RIP); 8380 8381 report(reason == VMX_PREEMPT && guest_rip == expected_rip, 8382 "Exit reason is 0x%x (expected 0x%x) and guest RIP is %lx (0x%lx expected).", 8383 reason, VMX_PREEMPT, guest_rip, expected_rip); 8384 } 8385 8386 /* 8387 * This test ensures that when the VMX preemption timer is zero at 8388 * VM-entry, a VM-exit occurs after any event injection and after any 8389 * pending debug exceptions are raised, but before execution of any 8390 * guest instructions. 8391 */ 8392 static void vmx_preemption_timer_zero_test(void) 8393 { 8394 u64 db_fault_address = (u64)get_idt_addr(&boot_idt[DB_VECTOR]); 8395 handler old_db; 8396 u32 reason; 8397 8398 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 8399 report_skip("'Activate VMX-preemption timer' not supported"); 8400 return; 8401 } 8402 8403 /* 8404 * Install a custom #DB handler that doesn't abort. 8405 */ 8406 old_db = handle_exception(DB_VECTOR, 8407 vmx_preemption_timer_zero_test_db_handler); 8408 8409 test_set_guest(vmx_preemption_timer_zero_test_guest); 8410 8411 /* 8412 * VMX-preemption timer should fire after event injection. 8413 */ 8414 vmx_set_test_stage(0); 8415 vmx_preemption_timer_zero_inject_db(0); 8416 vmx_preemption_timer_zero_expect_preempt_at_rip(db_fault_address); 8417 vmx_preemption_timer_zero_advance_past_vmcall(); 8418 8419 /* 8420 * VMX-preemption timer should fire after event injection. 8421 * Exception bitmap is irrelevant, since you can't intercept 8422 * an event that you injected. 8423 */ 8424 vmx_set_test_stage(1); 8425 vmx_preemption_timer_zero_inject_db(1 << DB_VECTOR); 8426 vmx_preemption_timer_zero_expect_preempt_at_rip(db_fault_address); 8427 vmx_preemption_timer_zero_advance_past_vmcall(); 8428 8429 /* 8430 * VMX-preemption timer should fire after pending debug exceptions 8431 * have delivered a #DB trap. 8432 */ 8433 vmx_set_test_stage(2); 8434 vmx_preemption_timer_zero_set_pending_dbg(0); 8435 vmx_preemption_timer_zero_expect_preempt_at_rip(db_fault_address); 8436 vmx_preemption_timer_zero_advance_past_vmcall(); 8437 8438 /* 8439 * VMX-preemption timer would fire after pending debug exceptions 8440 * have delivered a #DB trap, but in this case, the #DB trap is 8441 * intercepted. 8442 */ 8443 vmx_set_test_stage(3); 8444 vmx_preemption_timer_zero_set_pending_dbg(1 << DB_VECTOR); 8445 reason = (u32)vmcs_read(EXI_REASON); 8446 report(reason == VMX_EXC_NMI, "Exit reason is 0x%x (expected 0x%x)", 8447 reason, VMX_EXC_NMI); 8448 8449 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 8450 enter_guest(); 8451 8452 handle_exception(DB_VECTOR, old_db); 8453 } 8454 8455 static u64 vmx_preemption_timer_tf_test_prev_rip; 8456 8457 static void vmx_preemption_timer_tf_test_db_handler(struct ex_regs *regs) 8458 { 8459 extern char vmx_preemption_timer_tf_test_endloop; 8460 8461 if (vmx_get_test_stage() == 2) { 8462 /* 8463 * Stage 2 means that we're done, one way or another. 8464 * Arrange for the iret to drop us out of the wbinvd 8465 * loop and stop single-stepping. 8466 */ 8467 regs->rip = (u64)&vmx_preemption_timer_tf_test_endloop; 8468 regs->rflags &= ~X86_EFLAGS_TF; 8469 } else if (regs->rip == vmx_preemption_timer_tf_test_prev_rip) { 8470 /* 8471 * The RIP should alternate between the wbinvd and the 8472 * jmp instruction in the code below. If we ever see 8473 * the same instruction twice in a row, that means a 8474 * single-step trap has been dropped. Let the 8475 * hypervisor know about the failure by executing a 8476 * VMCALL. 8477 */ 8478 vmcall(); 8479 } 8480 vmx_preemption_timer_tf_test_prev_rip = regs->rip; 8481 } 8482 8483 static void vmx_preemption_timer_tf_test_guest(void) 8484 { 8485 /* 8486 * The hypervisor doesn't intercept WBINVD, so the loop below 8487 * shouldn't be a problem--it's just two instructions 8488 * executing in VMX non-root mode. However, when the 8489 * hypervisor is running in a virtual environment, the parent 8490 * hypervisor might intercept WBINVD and emulate it. If the 8491 * parent hypervisor is broken, the single-step trap after the 8492 * WBINVD might be lost. 8493 */ 8494 asm volatile("vmcall\n\t" 8495 "0: wbinvd\n\t" 8496 "1: jmp 0b\n\t" 8497 "vmx_preemption_timer_tf_test_endloop:"); 8498 } 8499 8500 /* 8501 * Ensure that the delivery of a "VMX-preemption timer expired" 8502 * VM-exit doesn't disrupt single-stepping in the guest. Note that 8503 * passing this test doesn't ensure correctness, because the test will 8504 * only fail if the VMX-preemtion timer fires at the right time (or 8505 * the wrong time, as it were). 8506 */ 8507 static void vmx_preemption_timer_tf_test(void) 8508 { 8509 handler old_db; 8510 u32 reason; 8511 int i; 8512 8513 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 8514 report_skip("'Activate VMX-preemption timer' not supported"); 8515 return; 8516 } 8517 8518 old_db = handle_exception(DB_VECTOR, 8519 vmx_preemption_timer_tf_test_db_handler); 8520 8521 test_set_guest(vmx_preemption_timer_tf_test_guest); 8522 8523 enter_guest(); 8524 skip_exit_vmcall(); 8525 8526 vmx_set_test_stage(1); 8527 vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT); 8528 vmcs_write(PREEMPT_TIMER_VALUE, 50000); 8529 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_TF); 8530 8531 /* 8532 * The only exit we should see is "VMX-preemption timer 8533 * expired." If we get a VMCALL exit, that means the #DB 8534 * handler has detected a missing single-step trap. It doesn't 8535 * matter where the guest RIP is when the VMX-preemption timer 8536 * expires (whether it's in the WBINVD loop or in the #DB 8537 * handler)--a single-step trap should never be discarded. 8538 */ 8539 for (i = 0; i < 10000; i++) { 8540 enter_guest(); 8541 reason = (u32)vmcs_read(EXI_REASON); 8542 if (reason == VMX_PREEMPT) 8543 continue; 8544 TEST_ASSERT(reason == VMX_VMCALL); 8545 skip_exit_insn(); 8546 break; 8547 } 8548 8549 report(reason == VMX_PREEMPT, "No single-step traps skipped"); 8550 8551 vmx_set_test_stage(2); 8552 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 8553 enter_guest(); 8554 8555 handle_exception(DB_VECTOR, old_db); 8556 } 8557 8558 static void vmx_db_test_guest(void) 8559 { 8560 /* 8561 * For a hardware generated single-step #DB. 8562 */ 8563 asm volatile("vmcall;" 8564 "nop;" 8565 ".Lpost_nop:"); 8566 /* 8567 * ...in a MOVSS shadow, with pending debug exceptions. 8568 */ 8569 asm volatile("vmcall;" 8570 "nop;" 8571 ".Lpost_movss_nop:"); 8572 /* 8573 * For an L0 synthesized single-step #DB. (L0 intercepts WBINVD and 8574 * emulates it in software.) 8575 */ 8576 asm volatile("vmcall;" 8577 "wbinvd;" 8578 ".Lpost_wbinvd:"); 8579 /* 8580 * ...in a MOVSS shadow, with pending debug exceptions. 8581 */ 8582 asm volatile("vmcall;" 8583 "wbinvd;" 8584 ".Lpost_movss_wbinvd:"); 8585 /* 8586 * For a hardware generated single-step #DB in a transactional region. 8587 */ 8588 asm volatile("vmcall;" 8589 ".Lxbegin: xbegin .Lskip_rtm;" 8590 "xend;" 8591 ".Lskip_rtm:"); 8592 } 8593 8594 /* 8595 * Clear the pending debug exceptions and RFLAGS.TF and re-enter 8596 * L2. No #DB is delivered and L2 continues to the next point of 8597 * interest. 8598 */ 8599 static void dismiss_db(void) 8600 { 8601 vmcs_write(GUEST_PENDING_DEBUG, 0); 8602 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 8603 enter_guest(); 8604 } 8605 8606 /* 8607 * Check a variety of VMCS fields relevant to an intercepted #DB exception. 8608 * Then throw away the #DB exception and resume L2. 8609 */ 8610 static void check_db_exit(bool xfail_qual, bool xfail_dr6, bool xfail_pdbg, 8611 void *expected_rip, u64 expected_exit_qual, 8612 u64 expected_dr6) 8613 { 8614 u32 reason = vmcs_read(EXI_REASON); 8615 u32 intr_info = vmcs_read(EXI_INTR_INFO); 8616 u64 exit_qual = vmcs_read(EXI_QUALIFICATION); 8617 u64 guest_rip = vmcs_read(GUEST_RIP); 8618 u64 guest_pending_dbg = vmcs_read(GUEST_PENDING_DEBUG); 8619 u64 dr6 = read_dr6(); 8620 const u32 expected_intr_info = INTR_INFO_VALID_MASK | 8621 INTR_TYPE_HARD_EXCEPTION | DB_VECTOR; 8622 8623 report(reason == VMX_EXC_NMI && intr_info == expected_intr_info, 8624 "Expected #DB VM-exit"); 8625 report((u64)expected_rip == guest_rip, "Expected RIP %p (actual %lx)", 8626 expected_rip, guest_rip); 8627 report_xfail(xfail_pdbg, 0 == guest_pending_dbg, 8628 "Expected pending debug exceptions 0 (actual %lx)", 8629 guest_pending_dbg); 8630 report_xfail(xfail_qual, expected_exit_qual == exit_qual, 8631 "Expected exit qualification %lx (actual %lx)", 8632 expected_exit_qual, exit_qual); 8633 report_xfail(xfail_dr6, expected_dr6 == dr6, 8634 "Expected DR6 %lx (actual %lx)", expected_dr6, dr6); 8635 dismiss_db(); 8636 } 8637 8638 /* 8639 * Assuming the guest has just exited on a VMCALL instruction, skip 8640 * over the vmcall, and set the guest's RFLAGS.TF in the VMCS. If 8641 * pending debug exceptions are non-zero, set the VMCS up as if the 8642 * previous instruction was a MOVSS that generated the indicated 8643 * pending debug exceptions. Then enter L2. 8644 */ 8645 static void single_step_guest(const char *test_name, u64 starting_dr6, 8646 u64 pending_debug_exceptions) 8647 { 8648 printf("\n%s\n", test_name); 8649 skip_exit_vmcall(); 8650 write_dr6(starting_dr6); 8651 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_TF); 8652 if (pending_debug_exceptions) { 8653 vmcs_write(GUEST_PENDING_DEBUG, pending_debug_exceptions); 8654 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 8655 } 8656 enter_guest(); 8657 } 8658 8659 /* 8660 * When L1 intercepts #DB, verify that a single-step trap clears 8661 * pending debug exceptions, populates the exit qualification field 8662 * properly, and that DR6 is not prematurely clobbered. In a 8663 * (simulated) MOVSS shadow, make sure that the pending debug 8664 * exception bits are properly accumulated into the exit qualification 8665 * field. 8666 */ 8667 static void vmx_db_test(void) 8668 { 8669 /* 8670 * We are going to set a few arbitrary bits in DR6 to verify that 8671 * (a) DR6 is not modified by an intercepted #DB, and 8672 * (b) stale bits in DR6 (DR6.BD, in particular) don't leak into 8673 * the exit qualification field for a subsequent #DB exception. 8674 */ 8675 const u64 starting_dr6 = DR6_RESERVED | BIT(13) | DR_TRAP3 | DR_TRAP1; 8676 extern char post_nop asm(".Lpost_nop"); 8677 extern char post_movss_nop asm(".Lpost_movss_nop"); 8678 extern char post_wbinvd asm(".Lpost_wbinvd"); 8679 extern char post_movss_wbinvd asm(".Lpost_movss_wbinvd"); 8680 extern char xbegin asm(".Lxbegin"); 8681 extern char skip_rtm asm(".Lskip_rtm"); 8682 8683 /* 8684 * L1 wants to intercept #DB exceptions encountered in L2. 8685 */ 8686 vmcs_write(EXC_BITMAP, BIT(DB_VECTOR)); 8687 8688 /* 8689 * Start L2 and run it up to the first point of interest. 8690 */ 8691 test_set_guest(vmx_db_test_guest); 8692 enter_guest(); 8693 8694 /* 8695 * Hardware-delivered #DB trap for single-step sets the 8696 * standard that L0 has to follow for emulated instructions. 8697 */ 8698 single_step_guest("Hardware delivered single-step", starting_dr6, 0); 8699 check_db_exit(false, false, false, &post_nop, DR_STEP, starting_dr6); 8700 8701 /* 8702 * Hardware-delivered #DB trap for single-step in MOVSS shadow 8703 * also sets the standard that L0 has to follow for emulated 8704 * instructions. Here, we establish the VMCS pending debug 8705 * exceptions to indicate that the simulated MOVSS triggered a 8706 * data breakpoint as well as the single-step trap. 8707 */ 8708 single_step_guest("Hardware delivered single-step in MOVSS shadow", 8709 starting_dr6, BIT(12) | DR_STEP | DR_TRAP0 ); 8710 check_db_exit(false, false, false, &post_movss_nop, DR_STEP | DR_TRAP0, 8711 starting_dr6); 8712 8713 /* 8714 * L0 synthesized #DB trap for single-step is buggy, because 8715 * kvm (a) clobbers DR6 too early, and (b) tries its best to 8716 * reconstitute the exit qualification from the prematurely 8717 * modified DR6, but fails miserably. 8718 */ 8719 single_step_guest("Software synthesized single-step", starting_dr6, 0); 8720 check_db_exit(false, false, false, &post_wbinvd, DR_STEP, starting_dr6); 8721 8722 /* 8723 * L0 synthesized #DB trap for single-step in MOVSS shadow is 8724 * even worse, because L0 also leaves the pending debug 8725 * exceptions in the VMCS instead of accumulating them into 8726 * the exit qualification field for the #DB exception. 8727 */ 8728 single_step_guest("Software synthesized single-step in MOVSS shadow", 8729 starting_dr6, BIT(12) | DR_STEP | DR_TRAP0); 8730 check_db_exit(true, false, true, &post_movss_wbinvd, DR_STEP | DR_TRAP0, 8731 starting_dr6); 8732 8733 /* 8734 * Optional RTM test for hardware that supports RTM, to 8735 * demonstrate that the current volume 3 of the SDM 8736 * (325384-067US), table 27-1 is incorrect. Bit 16 of the exit 8737 * qualification for debug exceptions is not reserved. It is 8738 * set to 1 if a debug exception (#DB) or a breakpoint 8739 * exception (#BP) occurs inside an RTM region while advanced 8740 * debugging of RTM transactional regions is enabled. 8741 */ 8742 if (this_cpu_has(X86_FEATURE_RTM)) { 8743 vmcs_write(ENT_CONTROLS, 8744 vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 8745 /* 8746 * Set DR7.RTM[bit 11] and IA32_DEBUGCTL.RTM[bit 15] 8747 * in the guest to enable advanced debugging of RTM 8748 * transactional regions. 8749 */ 8750 vmcs_write(GUEST_DR7, BIT(11)); 8751 vmcs_write(GUEST_DEBUGCTL, BIT(15)); 8752 single_step_guest("Hardware delivered single-step in " 8753 "transactional region", starting_dr6, 0); 8754 check_db_exit(false, false, false, &xbegin, BIT(16), 8755 starting_dr6); 8756 } else { 8757 vmcs_write(GUEST_RIP, (u64)&skip_rtm); 8758 enter_guest(); 8759 } 8760 } 8761 8762 static void enable_vid(void) 8763 { 8764 void *virtual_apic_page; 8765 8766 assert(cpu_has_apicv()); 8767 8768 disable_intercept_for_x2apic_msrs(); 8769 8770 virtual_apic_page = alloc_page(); 8771 vmcs_write(APIC_VIRT_ADDR, (u64)virtual_apic_page); 8772 8773 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 8774 8775 vmcs_write(EOI_EXIT_BITMAP0, 0x0); 8776 vmcs_write(EOI_EXIT_BITMAP1, 0x0); 8777 vmcs_write(EOI_EXIT_BITMAP2, 0x0); 8778 vmcs_write(EOI_EXIT_BITMAP3, 0x0); 8779 8780 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY | CPU_TPR_SHADOW); 8781 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_VINTD | CPU_VIRT_X2APIC); 8782 } 8783 8784 static void trigger_ioapic_scan_thread(void *data) 8785 { 8786 /* Wait until other CPU entered L2 */ 8787 while (vmx_get_test_stage() != 1) 8788 ; 8789 8790 /* Trigger ioapic scan */ 8791 ioapic_set_redir(0xf, 0x79, TRIGGER_LEVEL); 8792 vmx_set_test_stage(2); 8793 } 8794 8795 static void irq_79_handler_guest(isr_regs_t *regs) 8796 { 8797 eoi(); 8798 8799 /* L1 expects vmexit on VMX_VMCALL and not VMX_EOI_INDUCED */ 8800 vmcall(); 8801 } 8802 8803 /* 8804 * Constant for num of busy-loop iterations after which 8805 * a timer interrupt should have happened in host 8806 */ 8807 #define TIMER_INTERRUPT_DELAY 100000000 8808 8809 static void vmx_eoi_bitmap_ioapic_scan_test_guest(void) 8810 { 8811 handle_irq(0x79, irq_79_handler_guest); 8812 irq_enable(); 8813 8814 /* Signal to L1 CPU to trigger ioapic scan */ 8815 vmx_set_test_stage(1); 8816 /* Wait until L1 CPU to trigger ioapic scan */ 8817 while (vmx_get_test_stage() != 2) 8818 ; 8819 8820 /* 8821 * Wait for L0 timer interrupt to be raised while we run in L2 8822 * such that L0 will process the IOAPIC scan request before 8823 * resuming L2 8824 */ 8825 delay(TIMER_INTERRUPT_DELAY); 8826 8827 asm volatile ("int $0x79"); 8828 } 8829 8830 static void vmx_eoi_bitmap_ioapic_scan_test(void) 8831 { 8832 if (!cpu_has_apicv() || (cpu_count() < 2)) { 8833 report_skip(__func__); 8834 return; 8835 } 8836 8837 enable_vid(); 8838 8839 on_cpu_async(1, trigger_ioapic_scan_thread, NULL); 8840 test_set_guest(vmx_eoi_bitmap_ioapic_scan_test_guest); 8841 8842 /* 8843 * Launch L2. 8844 * We expect the exit reason to be VMX_VMCALL (and not EOI INDUCED). 8845 * In case the reason isn't VMX_VMCALL, the asserion inside 8846 * skip_exit_vmcall() will fail. 8847 */ 8848 enter_guest(); 8849 skip_exit_vmcall(); 8850 8851 /* Let L2 finish */ 8852 enter_guest(); 8853 report(1, __func__); 8854 } 8855 8856 #define HLT_WITH_RVI_VECTOR (0xf1) 8857 8858 bool vmx_hlt_with_rvi_guest_isr_fired; 8859 static void vmx_hlt_with_rvi_guest_isr(isr_regs_t *regs) 8860 { 8861 vmx_hlt_with_rvi_guest_isr_fired = true; 8862 eoi(); 8863 } 8864 8865 static void vmx_hlt_with_rvi_guest(void) 8866 { 8867 handle_irq(HLT_WITH_RVI_VECTOR, vmx_hlt_with_rvi_guest_isr); 8868 8869 irq_enable(); 8870 asm volatile ("nop"); 8871 8872 vmcall(); 8873 } 8874 8875 static void vmx_hlt_with_rvi_test(void) 8876 { 8877 if (!cpu_has_apicv()) { 8878 report_skip(__func__); 8879 return; 8880 } 8881 8882 enable_vid(); 8883 8884 vmx_hlt_with_rvi_guest_isr_fired = false; 8885 test_set_guest(vmx_hlt_with_rvi_guest); 8886 8887 enter_guest(); 8888 skip_exit_vmcall(); 8889 8890 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8891 vmcs_write(GUEST_INT_STATUS, HLT_WITH_RVI_VECTOR); 8892 enter_guest(); 8893 8894 report(vmx_hlt_with_rvi_guest_isr_fired, "Interrupt raised in guest"); 8895 } 8896 8897 static void set_irq_line_thread(void *data) 8898 { 8899 /* Wait until other CPU entered L2 */ 8900 while (vmx_get_test_stage() != 1) 8901 ; 8902 8903 /* Set irq-line 0xf to raise vector 0x78 for vCPU 0 */ 8904 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 8905 vmx_set_test_stage(2); 8906 } 8907 8908 static bool irq_78_handler_vmcall_before_eoi; 8909 static void irq_78_handler_guest(isr_regs_t *regs) 8910 { 8911 set_irq_line(0xf, 0); 8912 if (irq_78_handler_vmcall_before_eoi) 8913 vmcall(); 8914 eoi(); 8915 vmcall(); 8916 } 8917 8918 static void vmx_apic_passthrough_guest(void) 8919 { 8920 handle_irq(0x78, irq_78_handler_guest); 8921 irq_enable(); 8922 8923 /* If requested, wait for other CPU to trigger ioapic scan */ 8924 if (vmx_get_test_stage() < 1) { 8925 vmx_set_test_stage(1); 8926 while (vmx_get_test_stage() != 2) 8927 ; 8928 } 8929 8930 set_irq_line(0xf, 1); 8931 } 8932 8933 static void vmx_apic_passthrough(bool set_irq_line_from_thread) 8934 { 8935 if (set_irq_line_from_thread && (cpu_count() < 2)) { 8936 report_skip(__func__); 8937 return; 8938 } 8939 8940 /* Test device is required for generating IRQs */ 8941 if (!test_device_enabled()) { 8942 report_skip(__func__); 8943 return; 8944 } 8945 u64 cpu_ctrl_0 = CPU_SECONDARY; 8946 u64 cpu_ctrl_1 = 0; 8947 8948 disable_intercept_for_x2apic_msrs(); 8949 8950 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 8951 8952 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 8953 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 8954 8955 if (set_irq_line_from_thread) { 8956 irq_78_handler_vmcall_before_eoi = false; 8957 on_cpu_async(1, set_irq_line_thread, NULL); 8958 } else { 8959 irq_78_handler_vmcall_before_eoi = true; 8960 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 8961 vmx_set_test_stage(2); 8962 } 8963 test_set_guest(vmx_apic_passthrough_guest); 8964 8965 if (irq_78_handler_vmcall_before_eoi) { 8966 /* Before EOI remote_irr should still be set */ 8967 enter_guest(); 8968 skip_exit_vmcall(); 8969 TEST_ASSERT_EQ_MSG(1, (int)ioapic_read_redir(0xf).remote_irr, 8970 "IOAPIC pass-through: remote_irr=1 before EOI"); 8971 } 8972 8973 /* After EOI remote_irr should be cleared */ 8974 enter_guest(); 8975 skip_exit_vmcall(); 8976 TEST_ASSERT_EQ_MSG(0, (int)ioapic_read_redir(0xf).remote_irr, 8977 "IOAPIC pass-through: remote_irr=0 after EOI"); 8978 8979 /* Let L2 finish */ 8980 enter_guest(); 8981 report(1, __func__); 8982 } 8983 8984 static void vmx_apic_passthrough_test(void) 8985 { 8986 vmx_apic_passthrough(false); 8987 } 8988 8989 static void vmx_apic_passthrough_thread_test(void) 8990 { 8991 vmx_apic_passthrough(true); 8992 } 8993 8994 static void vmx_apic_passthrough_tpr_threshold_guest(void) 8995 { 8996 cli(); 8997 apic_set_tpr(0); 8998 } 8999 9000 static bool vmx_apic_passthrough_tpr_threshold_ipi_isr_fired; 9001 static void vmx_apic_passthrough_tpr_threshold_ipi_isr(isr_regs_t *regs) 9002 { 9003 vmx_apic_passthrough_tpr_threshold_ipi_isr_fired = true; 9004 eoi(); 9005 } 9006 9007 static void vmx_apic_passthrough_tpr_threshold_test(void) 9008 { 9009 int ipi_vector = 0xe1; 9010 9011 disable_intercept_for_x2apic_msrs(); 9012 vmcs_clear_bits(PIN_CONTROLS, PIN_EXTINT); 9013 9014 /* Raise L0 TPR-threshold by queueing vector in LAPIC IRR */ 9015 cli(); 9016 apic_set_tpr((ipi_vector >> 4) + 1); 9017 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | 9018 APIC_DM_FIXED | ipi_vector, 9019 0); 9020 9021 test_set_guest(vmx_apic_passthrough_tpr_threshold_guest); 9022 enter_guest(); 9023 9024 report(apic_get_tpr() == 0, "TPR was zero by guest"); 9025 9026 /* Clean pending self-IPI */ 9027 vmx_apic_passthrough_tpr_threshold_ipi_isr_fired = false; 9028 handle_irq(ipi_vector, vmx_apic_passthrough_tpr_threshold_ipi_isr); 9029 sti(); 9030 asm volatile ("nop"); 9031 report(vmx_apic_passthrough_tpr_threshold_ipi_isr_fired, "self-IPI fired"); 9032 9033 report(1, __func__); 9034 } 9035 9036 static u64 init_signal_test_exit_reason; 9037 static bool init_signal_test_thread_continued; 9038 9039 static void init_signal_test_thread(void *data) 9040 { 9041 struct vmcs *test_vmcs = data; 9042 9043 /* Enter VMX operation (i.e. exec VMXON) */ 9044 u64 *ap_vmxon_region = alloc_page(); 9045 enable_vmx(); 9046 init_vmx(ap_vmxon_region); 9047 _vmx_on(ap_vmxon_region); 9048 9049 /* Signal CPU have entered VMX operation */ 9050 vmx_set_test_stage(1); 9051 9052 /* Wait for BSP CPU to send INIT signal */ 9053 while (vmx_get_test_stage() != 2) 9054 ; 9055 9056 /* 9057 * Signal that we continue as usual as INIT signal 9058 * should be blocked while CPU is in VMX operation 9059 */ 9060 vmx_set_test_stage(3); 9061 9062 /* Wait for signal to enter VMX non-root mode */ 9063 while (vmx_get_test_stage() != 4) 9064 ; 9065 9066 /* Enter VMX non-root mode */ 9067 test_set_guest(v2_null_test_guest); 9068 make_vmcs_current(test_vmcs); 9069 enter_guest(); 9070 /* Save exit reason for BSP CPU to compare to expected result */ 9071 init_signal_test_exit_reason = vmcs_read(EXI_REASON); 9072 /* VMCLEAR test-vmcs so it could be loaded by BSP CPU */ 9073 vmcs_clear(test_vmcs); 9074 launched = false; 9075 /* Signal that CPU exited to VMX root mode */ 9076 vmx_set_test_stage(5); 9077 9078 /* Wait for BSP CPU to signal to exit VMX operation */ 9079 while (vmx_get_test_stage() != 6) 9080 ; 9081 9082 /* Exit VMX operation (i.e. exec VMXOFF) */ 9083 vmx_off(); 9084 9085 /* 9086 * Signal to BSP CPU that we continue as usual as INIT signal 9087 * should have been consumed by VMX_INIT exit from guest 9088 */ 9089 vmx_set_test_stage(7); 9090 9091 /* Wait for BSP CPU to signal to enter VMX operation */ 9092 while (vmx_get_test_stage() != 8) 9093 ; 9094 /* Enter VMX operation (i.e. exec VMXON) */ 9095 _vmx_on(ap_vmxon_region); 9096 /* Signal to BSP we are in VMX operation */ 9097 vmx_set_test_stage(9); 9098 9099 /* Wait for BSP CPU to send INIT signal */ 9100 while (vmx_get_test_stage() != 10) 9101 ; 9102 9103 /* Exit VMX operation (i.e. exec VMXOFF) */ 9104 vmx_off(); 9105 9106 /* 9107 * Exiting VMX operation should result in latched 9108 * INIT signal being processed. Therefore, we should 9109 * never reach the below code. Thus, signal to BSP 9110 * CPU if we have reached here so it is able to 9111 * report an issue if it happens. 9112 */ 9113 init_signal_test_thread_continued = true; 9114 } 9115 9116 #define INIT_SIGNAL_TEST_DELAY 100000000ULL 9117 9118 static void vmx_init_signal_test(void) 9119 { 9120 struct vmcs *test_vmcs; 9121 9122 if (cpu_count() < 2) { 9123 report_skip(__func__); 9124 return; 9125 } 9126 9127 /* VMCLEAR test-vmcs so it could be loaded by other CPU */ 9128 vmcs_save(&test_vmcs); 9129 vmcs_clear(test_vmcs); 9130 9131 vmx_set_test_stage(0); 9132 on_cpu_async(1, init_signal_test_thread, test_vmcs); 9133 9134 /* Wait for other CPU to enter VMX operation */ 9135 while (vmx_get_test_stage() != 1) 9136 ; 9137 9138 /* Send INIT signal to other CPU */ 9139 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_INIT | APIC_INT_ASSERT, 9140 id_map[1]); 9141 /* Signal other CPU we have sent INIT signal */ 9142 vmx_set_test_stage(2); 9143 9144 /* 9145 * Wait reasonable amount of time for INIT signal to 9146 * be received on other CPU and verify that other CPU 9147 * have proceed as usual to next test stage as INIT 9148 * signal should be blocked while other CPU in 9149 * VMX operation 9150 */ 9151 delay(INIT_SIGNAL_TEST_DELAY); 9152 report(vmx_get_test_stage() == 3, 9153 "INIT signal blocked when CPU in VMX operation"); 9154 /* No point to continue if we failed at this point */ 9155 if (vmx_get_test_stage() != 3) 9156 return; 9157 9158 /* Signal other CPU to enter VMX non-root mode */ 9159 init_signal_test_exit_reason = -1ull; 9160 vmx_set_test_stage(4); 9161 /* 9162 * Wait reasonable amont of time for other CPU 9163 * to exit to VMX root mode 9164 */ 9165 delay(INIT_SIGNAL_TEST_DELAY); 9166 if (vmx_get_test_stage() != 5) { 9167 report(false, "Pending INIT signal didn't result in VMX exit"); 9168 return; 9169 } 9170 report(init_signal_test_exit_reason == VMX_INIT, 9171 "INIT signal during VMX non-root mode result in exit-reason %s (%lu)", 9172 exit_reason_description(init_signal_test_exit_reason), 9173 init_signal_test_exit_reason); 9174 9175 /* Run guest to completion */ 9176 make_vmcs_current(test_vmcs); 9177 enter_guest(); 9178 9179 /* Signal other CPU to exit VMX operation */ 9180 init_signal_test_thread_continued = false; 9181 vmx_set_test_stage(6); 9182 9183 /* Wait reasonable amount of time for other CPU to exit VMX operation */ 9184 delay(INIT_SIGNAL_TEST_DELAY); 9185 report(vmx_get_test_stage() == 7, 9186 "INIT signal consumed on VMX_INIT exit"); 9187 /* No point to continue if we failed at this point */ 9188 if (vmx_get_test_stage() != 7) 9189 return; 9190 9191 /* Signal other CPU to enter VMX operation */ 9192 vmx_set_test_stage(8); 9193 /* Wait for other CPU to enter VMX operation */ 9194 while (vmx_get_test_stage() != 9) 9195 ; 9196 9197 /* Send INIT signal to other CPU */ 9198 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_INIT | APIC_INT_ASSERT, 9199 id_map[1]); 9200 /* Signal other CPU we have sent INIT signal */ 9201 vmx_set_test_stage(10); 9202 9203 /* 9204 * Wait reasonable amount of time for other CPU 9205 * to exit VMX operation and process INIT signal 9206 */ 9207 delay(INIT_SIGNAL_TEST_DELAY); 9208 report(!init_signal_test_thread_continued, 9209 "INIT signal processed after exit VMX operation"); 9210 9211 /* 9212 * TODO: Send SIPI to other CPU to sipi_entry (See x86/cstart64.S) 9213 * to re-init it to kvm-unit-tests standard environment. 9214 * Somehow (?) verify that SIPI was indeed received. 9215 */ 9216 } 9217 9218 enum vmcs_access { 9219 ACCESS_VMREAD, 9220 ACCESS_VMWRITE, 9221 ACCESS_NONE, 9222 }; 9223 9224 struct vmcs_shadow_test_common { 9225 enum vmcs_access op; 9226 enum Reason reason; 9227 u64 field; 9228 u64 value; 9229 u64 flags; 9230 u64 time; 9231 } l1_l2_common; 9232 9233 static inline u64 vmread_flags(u64 field, u64 *val) 9234 { 9235 u64 flags; 9236 9237 asm volatile ("vmread %2, %1; pushf; pop %0" 9238 : "=r" (flags), "=rm" (*val) : "r" (field) : "cc"); 9239 return flags & X86_EFLAGS_ALU; 9240 } 9241 9242 static inline u64 vmwrite_flags(u64 field, u64 val) 9243 { 9244 u64 flags; 9245 9246 asm volatile ("vmwrite %1, %2; pushf; pop %0" 9247 : "=r"(flags) : "rm" (val), "r" (field) : "cc"); 9248 return flags & X86_EFLAGS_ALU; 9249 } 9250 9251 static void vmx_vmcs_shadow_test_guest(void) 9252 { 9253 struct vmcs_shadow_test_common *c = &l1_l2_common; 9254 u64 start; 9255 9256 while (c->op != ACCESS_NONE) { 9257 start = rdtsc(); 9258 switch (c->op) { 9259 default: 9260 c->flags = -1ull; 9261 break; 9262 case ACCESS_VMREAD: 9263 c->flags = vmread_flags(c->field, &c->value); 9264 break; 9265 case ACCESS_VMWRITE: 9266 c->flags = vmwrite_flags(c->field, 0); 9267 break; 9268 } 9269 c->time = rdtsc() - start; 9270 vmcall(); 9271 } 9272 } 9273 9274 static u64 vmread_from_shadow(u64 field) 9275 { 9276 struct vmcs *primary; 9277 struct vmcs *shadow; 9278 u64 value; 9279 9280 TEST_ASSERT(!vmcs_save(&primary)); 9281 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 9282 TEST_ASSERT(!make_vmcs_current(shadow)); 9283 value = vmcs_read(field); 9284 TEST_ASSERT(!make_vmcs_current(primary)); 9285 return value; 9286 } 9287 9288 static u64 vmwrite_to_shadow(u64 field, u64 value) 9289 { 9290 struct vmcs *primary; 9291 struct vmcs *shadow; 9292 9293 TEST_ASSERT(!vmcs_save(&primary)); 9294 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 9295 TEST_ASSERT(!make_vmcs_current(shadow)); 9296 vmcs_write(field, value); 9297 value = vmcs_read(field); 9298 TEST_ASSERT(!make_vmcs_current(primary)); 9299 return value; 9300 } 9301 9302 static void vmcs_shadow_test_access(u8 *bitmap[2], enum vmcs_access access) 9303 { 9304 struct vmcs_shadow_test_common *c = &l1_l2_common; 9305 9306 c->op = access; 9307 vmcs_write(VMX_INST_ERROR, 0); 9308 enter_guest(); 9309 c->reason = vmcs_read(EXI_REASON) & 0xffff; 9310 if (c->reason != VMX_VMCALL) { 9311 skip_exit_insn(); 9312 enter_guest(); 9313 } 9314 skip_exit_vmcall(); 9315 } 9316 9317 static void vmcs_shadow_test_field(u8 *bitmap[2], u64 field) 9318 { 9319 struct vmcs_shadow_test_common *c = &l1_l2_common; 9320 struct vmcs *shadow; 9321 u64 value; 9322 uintptr_t flags[2]; 9323 bool good_shadow; 9324 u32 vmx_inst_error; 9325 9326 report_prefix_pushf("field %lx", field); 9327 c->field = field; 9328 9329 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 9330 if (shadow != (struct vmcs *)-1ull) { 9331 flags[ACCESS_VMREAD] = vmread_flags(field, &value); 9332 flags[ACCESS_VMWRITE] = vmwrite_flags(field, value); 9333 good_shadow = !flags[ACCESS_VMREAD] && !flags[ACCESS_VMWRITE]; 9334 } else { 9335 /* 9336 * When VMCS link pointer is -1ull, VMWRITE/VMREAD on 9337 * shadowed-fields should fail with setting RFLAGS.CF. 9338 */ 9339 flags[ACCESS_VMREAD] = X86_EFLAGS_CF; 9340 flags[ACCESS_VMWRITE] = X86_EFLAGS_CF; 9341 good_shadow = false; 9342 } 9343 9344 /* Intercept both VMREAD and VMWRITE. */ 9345 report_prefix_push("no VMREAD/VMWRITE permission"); 9346 /* VMWRITE/VMREAD done on reserved-bit should always intercept */ 9347 if (!(field >> VMCS_FIELD_RESERVED_SHIFT)) { 9348 set_bit(field, bitmap[ACCESS_VMREAD]); 9349 set_bit(field, bitmap[ACCESS_VMWRITE]); 9350 } 9351 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 9352 report(c->reason == VMX_VMWRITE, "not shadowed for VMWRITE"); 9353 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 9354 report(c->reason == VMX_VMREAD, "not shadowed for VMREAD"); 9355 report_prefix_pop(); 9356 9357 if (field >> VMCS_FIELD_RESERVED_SHIFT) 9358 goto out; 9359 9360 /* Permit shadowed VMREAD. */ 9361 report_prefix_push("VMREAD permission only"); 9362 clear_bit(field, bitmap[ACCESS_VMREAD]); 9363 set_bit(field, bitmap[ACCESS_VMWRITE]); 9364 if (good_shadow) 9365 value = vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 9366 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 9367 report(c->reason == VMX_VMWRITE, "not shadowed for VMWRITE"); 9368 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 9369 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 9370 report(c->reason == VMX_VMCALL, "shadowed for VMREAD (in %ld cycles)", 9371 c->time); 9372 report(c->flags == flags[ACCESS_VMREAD], 9373 "ALU flags after VMREAD (%lx) are as expected (%lx)", 9374 c->flags, flags[ACCESS_VMREAD]); 9375 if (good_shadow) 9376 report(c->value == value, 9377 "value read from shadow (%lx) is as expected (%lx)", 9378 c->value, value); 9379 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 9380 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 9381 "VMX_INST_ERROR (%d) is as expected (%d)", 9382 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 9383 report_prefix_pop(); 9384 9385 /* Permit shadowed VMWRITE. */ 9386 report_prefix_push("VMWRITE permission only"); 9387 set_bit(field, bitmap[ACCESS_VMREAD]); 9388 clear_bit(field, bitmap[ACCESS_VMWRITE]); 9389 if (good_shadow) 9390 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 9391 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 9392 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 9393 report(c->reason == VMX_VMCALL, 9394 "shadowed for VMWRITE (in %ld cycles)", 9395 c->time); 9396 report(c->flags == flags[ACCESS_VMREAD], 9397 "ALU flags after VMWRITE (%lx) are as expected (%lx)", 9398 c->flags, flags[ACCESS_VMREAD]); 9399 if (good_shadow) { 9400 value = vmread_from_shadow(field); 9401 report(value == 0, 9402 "shadow VMCS value (%lx) is as expected (%lx)", value, 9403 0ul); 9404 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 9405 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 9406 "VMX_INST_ERROR (%d) is as expected (%d)", 9407 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 9408 } 9409 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 9410 report(c->reason == VMX_VMREAD, "not shadowed for VMREAD"); 9411 report_prefix_pop(); 9412 9413 /* Permit shadowed VMREAD and VMWRITE. */ 9414 report_prefix_push("VMREAD and VMWRITE permission"); 9415 clear_bit(field, bitmap[ACCESS_VMREAD]); 9416 clear_bit(field, bitmap[ACCESS_VMWRITE]); 9417 if (good_shadow) 9418 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 9419 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 9420 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 9421 report(c->reason == VMX_VMCALL, 9422 "shadowed for VMWRITE (in %ld cycles)", 9423 c->time); 9424 report(c->flags == flags[ACCESS_VMREAD], 9425 "ALU flags after VMWRITE (%lx) are as expected (%lx)", 9426 c->flags, flags[ACCESS_VMREAD]); 9427 if (good_shadow) { 9428 value = vmread_from_shadow(field); 9429 report(value == 0, 9430 "shadow VMCS value (%lx) is as expected (%lx)", value, 9431 0ul); 9432 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 9433 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 9434 "VMX_INST_ERROR (%d) is as expected (%d)", 9435 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 9436 } 9437 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 9438 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 9439 report(c->reason == VMX_VMCALL, "shadowed for VMREAD (in %ld cycles)", 9440 c->time); 9441 report(c->flags == flags[ACCESS_VMREAD], 9442 "ALU flags after VMREAD (%lx) are as expected (%lx)", 9443 c->flags, flags[ACCESS_VMREAD]); 9444 if (good_shadow) 9445 report(c->value == 0, 9446 "value read from shadow (%lx) is as expected (%lx)", 9447 c->value, 0ul); 9448 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 9449 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 9450 "VMX_INST_ERROR (%d) is as expected (%d)", 9451 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 9452 report_prefix_pop(); 9453 9454 out: 9455 report_prefix_pop(); 9456 } 9457 9458 static void vmx_vmcs_shadow_test_body(u8 *bitmap[2]) 9459 { 9460 unsigned base; 9461 unsigned index; 9462 unsigned bit; 9463 unsigned highest_index = rdmsr(MSR_IA32_VMX_VMCS_ENUM); 9464 9465 /* Run test on all possible valid VMCS fields */ 9466 for (base = 0; 9467 base < (1 << VMCS_FIELD_RESERVED_SHIFT); 9468 base += (1 << VMCS_FIELD_TYPE_SHIFT)) 9469 for (index = 0; index <= highest_index; index++) 9470 vmcs_shadow_test_field(bitmap, base + index); 9471 9472 /* 9473 * Run tests on some invalid VMCS fields 9474 * (Have reserved bit set). 9475 */ 9476 for (bit = VMCS_FIELD_RESERVED_SHIFT; bit < VMCS_FIELD_BIT_SIZE; bit++) 9477 vmcs_shadow_test_field(bitmap, (1ull << bit)); 9478 } 9479 9480 static void vmx_vmcs_shadow_test(void) 9481 { 9482 u8 *bitmap[2]; 9483 struct vmcs *shadow; 9484 9485 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 9486 printf("\t'Activate secondary controls' not supported.\n"); 9487 return; 9488 } 9489 9490 if (!(ctrl_cpu_rev[1].clr & CPU_SHADOW_VMCS)) { 9491 printf("\t'VMCS shadowing' not supported.\n"); 9492 return; 9493 } 9494 9495 if (!(rdmsr(MSR_IA32_VMX_MISC) & 9496 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS)) { 9497 printf("\tVMWRITE can't modify VM-exit information fields.\n"); 9498 return; 9499 } 9500 9501 test_set_guest(vmx_vmcs_shadow_test_guest); 9502 9503 bitmap[ACCESS_VMREAD] = alloc_page(); 9504 bitmap[ACCESS_VMWRITE] = alloc_page(); 9505 9506 vmcs_write(VMREAD_BITMAP, virt_to_phys(bitmap[ACCESS_VMREAD])); 9507 vmcs_write(VMWRITE_BITMAP, virt_to_phys(bitmap[ACCESS_VMWRITE])); 9508 9509 shadow = alloc_page(); 9510 shadow->hdr.revision_id = basic.revision; 9511 shadow->hdr.shadow_vmcs = 1; 9512 TEST_ASSERT(!vmcs_clear(shadow)); 9513 9514 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_RDTSC); 9515 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY); 9516 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_SHADOW_VMCS); 9517 9518 vmcs_write(VMCS_LINK_PTR, virt_to_phys(shadow)); 9519 report_prefix_push("valid link pointer"); 9520 vmx_vmcs_shadow_test_body(bitmap); 9521 report_prefix_pop(); 9522 9523 vmcs_write(VMCS_LINK_PTR, -1ull); 9524 report_prefix_push("invalid link pointer"); 9525 vmx_vmcs_shadow_test_body(bitmap); 9526 report_prefix_pop(); 9527 9528 l1_l2_common.op = ACCESS_NONE; 9529 enter_guest(); 9530 } 9531 9532 /* 9533 * This test monitors the difference between a guest RDTSC instruction 9534 * and the IA32_TIME_STAMP_COUNTER MSR value stored in the VMCS12 9535 * VM-exit MSR-store list when taking a VM-exit on the instruction 9536 * following RDTSC. 9537 */ 9538 #define RDTSC_DIFF_ITERS 100000 9539 #define RDTSC_DIFF_FAILS 100 9540 #define HOST_CAPTURED_GUEST_TSC_DIFF_THRESHOLD 750 9541 9542 /* 9543 * Set 'use TSC offsetting' and set the guest offset to the 9544 * inverse of the host's current TSC value, so that the guest starts running 9545 * with an effective TSC value of 0. 9546 */ 9547 static void reset_guest_tsc_to_zero(void) 9548 { 9549 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_USE_TSC_OFFSET); 9550 vmcs_write(TSC_OFFSET, -rdtsc()); 9551 } 9552 9553 static void rdtsc_vmexit_diff_test_guest(void) 9554 { 9555 int i; 9556 9557 for (i = 0; i < RDTSC_DIFF_ITERS; i++) 9558 /* Ensure rdtsc is the last instruction before the vmcall. */ 9559 asm volatile("rdtsc; vmcall" : : : "eax", "edx"); 9560 } 9561 9562 /* 9563 * This function only considers the "use TSC offsetting" VM-execution 9564 * control. It does not handle "use TSC scaling" (because the latter 9565 * isn't available to the host today.) 9566 */ 9567 static unsigned long long host_time_to_guest_time(unsigned long long t) 9568 { 9569 TEST_ASSERT(!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 9570 !(vmcs_read(CPU_EXEC_CTRL1) & CPU_USE_TSC_SCALING)); 9571 9572 if (vmcs_read(CPU_EXEC_CTRL0) & CPU_USE_TSC_OFFSET) 9573 t += vmcs_read(TSC_OFFSET); 9574 9575 return t; 9576 } 9577 9578 static unsigned long long rdtsc_vmexit_diff_test_iteration(void) 9579 { 9580 unsigned long long guest_tsc, host_to_guest_tsc; 9581 9582 enter_guest(); 9583 skip_exit_vmcall(); 9584 guest_tsc = (u32) regs.rax + (regs.rdx << 32); 9585 host_to_guest_tsc = host_time_to_guest_time(exit_msr_store[0].value); 9586 9587 return host_to_guest_tsc - guest_tsc; 9588 } 9589 9590 static void rdtsc_vmexit_diff_test(void) 9591 { 9592 int fail = 0; 9593 int i; 9594 9595 if (!(ctrl_cpu_rev[0].clr & CPU_USE_TSC_OFFSET)) 9596 test_skip("CPU doesn't support the 'use TSC offsetting' processor-based VM-execution control.\n"); 9597 9598 test_set_guest(rdtsc_vmexit_diff_test_guest); 9599 9600 reset_guest_tsc_to_zero(); 9601 9602 /* 9603 * Set up the VMCS12 VM-exit MSR-store list to store just one 9604 * MSR: IA32_TIME_STAMP_COUNTER. Note that the value stored is 9605 * in the host time domain (i.e., it is not adjusted according 9606 * to the TSC multiplier and TSC offset fields in the VMCS12, 9607 * as a guest RDTSC would be.) 9608 */ 9609 exit_msr_store = alloc_page(); 9610 exit_msr_store[0].index = MSR_IA32_TSC; 9611 vmcs_write(EXI_MSR_ST_CNT, 1); 9612 vmcs_write(EXIT_MSR_ST_ADDR, virt_to_phys(exit_msr_store)); 9613 9614 for (i = 0; i < RDTSC_DIFF_ITERS; i++) { 9615 if (rdtsc_vmexit_diff_test_iteration() >= 9616 HOST_CAPTURED_GUEST_TSC_DIFF_THRESHOLD) 9617 fail++; 9618 } 9619 9620 enter_guest(); 9621 9622 report(fail < RDTSC_DIFF_FAILS, 9623 "RDTSC to VM-exit delta too high in %d of %d iterations", 9624 fail, RDTSC_DIFF_ITERS); 9625 } 9626 9627 static int invalid_msr_init(struct vmcs *vmcs) 9628 { 9629 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 9630 printf("\tPreemption timer is not supported\n"); 9631 return VMX_TEST_EXIT; 9632 } 9633 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 9634 preempt_val = 10000000; 9635 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 9636 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 9637 9638 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 9639 printf("\tSave preemption value is not supported\n"); 9640 9641 vmcs_write(ENT_MSR_LD_CNT, 1); 9642 vmcs_write(ENTER_MSR_LD_ADDR, (u64)0x13370000); 9643 9644 return VMX_TEST_START; 9645 } 9646 9647 9648 static void invalid_msr_main(void) 9649 { 9650 report(0, "Invalid MSR load"); 9651 } 9652 9653 static int invalid_msr_exit_handler(union exit_reason exit_reason) 9654 { 9655 report(0, "Invalid MSR load"); 9656 print_vmexit_info(exit_reason); 9657 return VMX_TEST_EXIT; 9658 } 9659 9660 static int invalid_msr_entry_failure(struct vmentry_result *result) 9661 { 9662 report(result->exit_reason.failed_vmentry && 9663 result->exit_reason.basic == VMX_FAIL_MSR, "Invalid MSR load"); 9664 return VMX_TEST_VMEXIT; 9665 } 9666 9667 /* 9668 * The max number of MSRs in an atomic switch MSR list is: 9669 * (111B + 1) * 512 = 4096 9670 * 9671 * Each list entry consumes: 9672 * 4-byte MSR index + 4 bytes reserved + 8-byte data = 16 bytes 9673 * 9674 * Allocate 128 kB to cover max_msr_list_size (i.e., 64 kB) and then some. 9675 */ 9676 static const u32 msr_list_page_order = 5; 9677 9678 static void atomic_switch_msr_limit_test_guest(void) 9679 { 9680 vmcall(); 9681 } 9682 9683 static void populate_msr_list(struct vmx_msr_entry *msr_list, 9684 size_t byte_capacity, int count) 9685 { 9686 int i; 9687 9688 for (i = 0; i < count; i++) { 9689 msr_list[i].index = MSR_IA32_TSC; 9690 msr_list[i].reserved = 0; 9691 msr_list[i].value = 0x1234567890abcdef; 9692 } 9693 9694 memset(msr_list + count, 0xff, 9695 byte_capacity - count * sizeof(*msr_list)); 9696 } 9697 9698 static int max_msr_list_size(void) 9699 { 9700 u32 vmx_misc = rdmsr(MSR_IA32_VMX_MISC); 9701 u32 factor = ((vmx_misc & GENMASK(27, 25)) >> 25) + 1; 9702 9703 return factor * 512; 9704 } 9705 9706 static void atomic_switch_msrs_test(int count) 9707 { 9708 struct vmx_msr_entry *vm_enter_load; 9709 struct vmx_msr_entry *vm_exit_load; 9710 struct vmx_msr_entry *vm_exit_store; 9711 int max_allowed = max_msr_list_size(); 9712 int byte_capacity = 1ul << (msr_list_page_order + PAGE_SHIFT); 9713 /* Exceeding the max MSR list size at exit trigers KVM to abort. */ 9714 int exit_count = count > max_allowed ? max_allowed : count; 9715 int cleanup_count = count > max_allowed ? 2 : 1; 9716 int i; 9717 9718 /* 9719 * Check for the IA32_TSC MSR, 9720 * available with the "TSC flag" and used to populate the MSR lists. 9721 */ 9722 if (!(cpuid(1).d & (1 << 4))) { 9723 report_skip(__func__); 9724 return; 9725 } 9726 9727 /* Set L2 guest. */ 9728 test_set_guest(atomic_switch_msr_limit_test_guest); 9729 9730 /* Setup atomic MSR switch lists. */ 9731 vm_enter_load = alloc_pages(msr_list_page_order); 9732 vm_exit_load = alloc_pages(msr_list_page_order); 9733 vm_exit_store = alloc_pages(msr_list_page_order); 9734 9735 vmcs_write(ENTER_MSR_LD_ADDR, (u64)vm_enter_load); 9736 vmcs_write(EXIT_MSR_LD_ADDR, (u64)vm_exit_load); 9737 vmcs_write(EXIT_MSR_ST_ADDR, (u64)vm_exit_store); 9738 9739 /* 9740 * VM-Enter should succeed up to the max number of MSRs per list, and 9741 * should not consume junk beyond the last entry. 9742 */ 9743 populate_msr_list(vm_enter_load, byte_capacity, count); 9744 populate_msr_list(vm_exit_load, byte_capacity, exit_count); 9745 populate_msr_list(vm_exit_store, byte_capacity, exit_count); 9746 9747 vmcs_write(ENT_MSR_LD_CNT, count); 9748 vmcs_write(EXI_MSR_LD_CNT, exit_count); 9749 vmcs_write(EXI_MSR_ST_CNT, exit_count); 9750 9751 if (count <= max_allowed) { 9752 enter_guest(); 9753 assert_exit_reason(VMX_VMCALL); 9754 skip_exit_vmcall(); 9755 } else { 9756 u32 exit_qual; 9757 9758 test_guest_state("Invalid MSR Load Count", true, count, 9759 "ENT_MSR_LD_CNT"); 9760 9761 exit_qual = vmcs_read(EXI_QUALIFICATION); 9762 report(exit_qual == max_allowed + 1, "exit_qual, %u, is %u.", 9763 exit_qual, max_allowed + 1); 9764 } 9765 9766 /* Cleanup. */ 9767 vmcs_write(ENT_MSR_LD_CNT, 0); 9768 vmcs_write(EXI_MSR_LD_CNT, 0); 9769 vmcs_write(EXI_MSR_ST_CNT, 0); 9770 for (i = 0; i < cleanup_count; i++) { 9771 enter_guest(); 9772 skip_exit_vmcall(); 9773 } 9774 free_pages_by_order(vm_enter_load, msr_list_page_order); 9775 free_pages_by_order(vm_exit_load, msr_list_page_order); 9776 free_pages_by_order(vm_exit_store, msr_list_page_order); 9777 } 9778 9779 static void atomic_switch_max_msrs_test(void) 9780 { 9781 atomic_switch_msrs_test(max_msr_list_size()); 9782 } 9783 9784 static void atomic_switch_overflow_msrs_test(void) 9785 { 9786 if (test_device_enabled()) 9787 atomic_switch_msrs_test(max_msr_list_size() + 1); 9788 else 9789 test_skip("Test is only supported on KVM"); 9790 } 9791 9792 #define TEST(name) { #name, .v2 = name } 9793 9794 /* name/init/guest_main/exit_handler/syscall_handler/guest_regs */ 9795 struct vmx_test vmx_tests[] = { 9796 { "null", NULL, basic_guest_main, basic_exit_handler, NULL, {0} }, 9797 { "vmenter", NULL, vmenter_main, vmenter_exit_handler, NULL, {0} }, 9798 { "preemption timer", preemption_timer_init, preemption_timer_main, 9799 preemption_timer_exit_handler, NULL, {0} }, 9800 { "control field PAT", test_ctrl_pat_init, test_ctrl_pat_main, 9801 test_ctrl_pat_exit_handler, NULL, {0} }, 9802 { "control field EFER", test_ctrl_efer_init, test_ctrl_efer_main, 9803 test_ctrl_efer_exit_handler, NULL, {0} }, 9804 { "CR shadowing", NULL, cr_shadowing_main, 9805 cr_shadowing_exit_handler, NULL, {0} }, 9806 { "I/O bitmap", iobmp_init, iobmp_main, iobmp_exit_handler, 9807 NULL, {0} }, 9808 { "instruction intercept", insn_intercept_init, insn_intercept_main, 9809 insn_intercept_exit_handler, NULL, {0} }, 9810 { "EPT A/D disabled", ept_init, ept_main, ept_exit_handler, NULL, {0} }, 9811 { "EPT A/D enabled", eptad_init, eptad_main, eptad_exit_handler, NULL, {0} }, 9812 { "PML", pml_init, pml_main, pml_exit_handler, NULL, {0} }, 9813 { "VPID", vpid_init, vpid_main, vpid_exit_handler, NULL, {0} }, 9814 { "interrupt", interrupt_init, interrupt_main, 9815 interrupt_exit_handler, NULL, {0} }, 9816 { "debug controls", dbgctls_init, dbgctls_main, dbgctls_exit_handler, 9817 NULL, {0} }, 9818 { "MSR switch", msr_switch_init, msr_switch_main, 9819 msr_switch_exit_handler, NULL, {0}, msr_switch_entry_failure }, 9820 { "vmmcall", vmmcall_init, vmmcall_main, vmmcall_exit_handler, NULL, {0} }, 9821 { "disable RDTSCP", disable_rdtscp_init, disable_rdtscp_main, 9822 disable_rdtscp_exit_handler, NULL, {0} }, 9823 { "int3", int3_init, int3_guest_main, int3_exit_handler, NULL, {0} }, 9824 { "into", into_init, into_guest_main, into_exit_handler, NULL, {0} }, 9825 { "exit_monitor_from_l2_test", NULL, exit_monitor_from_l2_main, 9826 exit_monitor_from_l2_handler, NULL, {0} }, 9827 { "invalid_msr", invalid_msr_init, invalid_msr_main, 9828 invalid_msr_exit_handler, NULL, {0}, invalid_msr_entry_failure}, 9829 /* Basic V2 tests. */ 9830 TEST(v2_null_test), 9831 TEST(v2_multiple_entries_test), 9832 TEST(fixture_test_case1), 9833 TEST(fixture_test_case2), 9834 /* Opcode tests. */ 9835 TEST(invvpid_test_v2), 9836 /* VM-entry tests */ 9837 TEST(vmx_controls_test), 9838 TEST(vmx_host_state_area_test), 9839 TEST(vmx_guest_state_area_test), 9840 TEST(vmentry_movss_shadow_test), 9841 /* APICv tests */ 9842 TEST(vmx_eoi_bitmap_ioapic_scan_test), 9843 TEST(vmx_hlt_with_rvi_test), 9844 TEST(apic_reg_virt_test), 9845 TEST(virt_x2apic_mode_test), 9846 /* APIC pass-through tests */ 9847 TEST(vmx_apic_passthrough_test), 9848 TEST(vmx_apic_passthrough_thread_test), 9849 TEST(vmx_apic_passthrough_tpr_threshold_test), 9850 TEST(vmx_init_signal_test), 9851 /* VMCS Shadowing tests */ 9852 TEST(vmx_vmcs_shadow_test), 9853 /* Regression tests */ 9854 TEST(vmx_cr_load_test), 9855 TEST(vmx_nm_test), 9856 TEST(vmx_db_test), 9857 TEST(vmx_nmi_window_test), 9858 TEST(vmx_intr_window_test), 9859 TEST(vmx_pending_event_test), 9860 TEST(vmx_pending_event_hlt_test), 9861 TEST(vmx_store_tsc_test), 9862 TEST(vmx_preemption_timer_zero_test), 9863 TEST(vmx_preemption_timer_tf_test), 9864 /* EPT access tests. */ 9865 TEST(ept_access_test_not_present), 9866 TEST(ept_access_test_read_only), 9867 TEST(ept_access_test_write_only), 9868 TEST(ept_access_test_read_write), 9869 TEST(ept_access_test_execute_only), 9870 TEST(ept_access_test_read_execute), 9871 TEST(ept_access_test_write_execute), 9872 TEST(ept_access_test_read_write_execute), 9873 TEST(ept_access_test_reserved_bits), 9874 TEST(ept_access_test_ignored_bits), 9875 TEST(ept_access_test_paddr_not_present_ad_disabled), 9876 TEST(ept_access_test_paddr_not_present_ad_enabled), 9877 TEST(ept_access_test_paddr_read_only_ad_disabled), 9878 TEST(ept_access_test_paddr_read_only_ad_enabled), 9879 TEST(ept_access_test_paddr_read_write), 9880 TEST(ept_access_test_paddr_read_write_execute), 9881 TEST(ept_access_test_paddr_read_execute_ad_disabled), 9882 TEST(ept_access_test_paddr_read_execute_ad_enabled), 9883 TEST(ept_access_test_paddr_not_present_page_fault), 9884 TEST(ept_access_test_force_2m_page), 9885 /* Atomic MSR switch tests. */ 9886 TEST(atomic_switch_max_msrs_test), 9887 TEST(atomic_switch_overflow_msrs_test), 9888 TEST(rdtsc_vmexit_diff_test), 9889 TEST(vmx_mtf_test), 9890 { NULL, NULL, NULL, NULL, NULL, {0} }, 9891 }; 9892