1 /* 2 * All test cases of nested virtualization should be in this file 3 * 4 * Author : Arthur Chunqi Li <yzt356@gmail.com> 5 */ 6 7 #include <asm/debugreg.h> 8 9 #include "vmx.h" 10 #include "msr.h" 11 #include "processor.h" 12 #include "vm.h" 13 #include "pci.h" 14 #include "fwcfg.h" 15 #include "isr.h" 16 #include "desc.h" 17 #include "apic.h" 18 #include "types.h" 19 #include "vmalloc.h" 20 #include "alloc_page.h" 21 #include "smp.h" 22 #include "delay.h" 23 24 #define NONCANONICAL 0xaaaaaaaaaaaaaaaaull 25 26 #define VPID_CAP_INVVPID_TYPES_SHIFT 40 27 28 u64 ia32_pat; 29 u64 ia32_efer; 30 void *io_bitmap_a, *io_bitmap_b; 31 u16 ioport; 32 33 unsigned long *pml4; 34 u64 eptp; 35 void *data_page1, *data_page2; 36 37 phys_addr_t pci_physaddr; 38 39 void *pml_log; 40 #define PML_INDEX 512 41 42 static inline unsigned ffs(unsigned x) 43 { 44 int pos = -1; 45 46 __asm__ __volatile__("bsf %1, %%eax; cmovnz %%eax, %0" 47 : "+r"(pos) : "rm"(x) : "eax"); 48 return pos + 1; 49 } 50 51 static inline void vmcall(void) 52 { 53 asm volatile("vmcall"); 54 } 55 56 static void basic_guest_main(void) 57 { 58 report(1, "Basic VMX test"); 59 } 60 61 static int basic_exit_handler(void) 62 { 63 report(0, "Basic VMX test"); 64 print_vmexit_info(); 65 return VMX_TEST_EXIT; 66 } 67 68 static void vmenter_main(void) 69 { 70 u64 rax; 71 u64 rsp, resume_rsp; 72 73 report(1, "test vmlaunch"); 74 75 asm volatile( 76 "mov %%rsp, %0\n\t" 77 "mov %3, %%rax\n\t" 78 "vmcall\n\t" 79 "mov %%rax, %1\n\t" 80 "mov %%rsp, %2\n\t" 81 : "=r"(rsp), "=r"(rax), "=r"(resume_rsp) 82 : "g"(0xABCD)); 83 report((rax == 0xFFFF) && (rsp == resume_rsp), "test vmresume"); 84 } 85 86 static int vmenter_exit_handler(void) 87 { 88 u64 guest_rip; 89 ulong reason; 90 91 guest_rip = vmcs_read(GUEST_RIP); 92 reason = vmcs_read(EXI_REASON) & 0xff; 93 switch (reason) { 94 case VMX_VMCALL: 95 if (regs.rax != 0xABCD) { 96 report(0, "test vmresume"); 97 return VMX_TEST_VMEXIT; 98 } 99 regs.rax = 0xFFFF; 100 vmcs_write(GUEST_RIP, guest_rip + 3); 101 return VMX_TEST_RESUME; 102 default: 103 report(0, "test vmresume"); 104 print_vmexit_info(); 105 } 106 return VMX_TEST_VMEXIT; 107 } 108 109 u32 preempt_scale; 110 volatile unsigned long long tsc_val; 111 volatile u32 preempt_val; 112 u64 saved_rip; 113 114 static int preemption_timer_init(struct vmcs *vmcs) 115 { 116 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 117 printf("\tPreemption timer is not supported\n"); 118 return VMX_TEST_EXIT; 119 } 120 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 121 preempt_val = 10000000; 122 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 123 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 124 125 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 126 printf("\tSave preemption value is not supported\n"); 127 128 return VMX_TEST_START; 129 } 130 131 static void preemption_timer_main(void) 132 { 133 tsc_val = rdtsc(); 134 if (ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) { 135 vmx_set_test_stage(0); 136 vmcall(); 137 if (vmx_get_test_stage() == 1) 138 vmcall(); 139 } 140 vmx_set_test_stage(1); 141 while (vmx_get_test_stage() == 1) { 142 if (((rdtsc() - tsc_val) >> preempt_scale) 143 > 10 * preempt_val) { 144 vmx_set_test_stage(2); 145 vmcall(); 146 } 147 } 148 tsc_val = rdtsc(); 149 asm volatile ("hlt"); 150 vmcall(); 151 vmx_set_test_stage(5); 152 vmcall(); 153 } 154 155 static int preemption_timer_exit_handler(void) 156 { 157 bool guest_halted; 158 u64 guest_rip; 159 ulong reason; 160 u32 insn_len; 161 u32 ctrl_exit; 162 163 guest_rip = vmcs_read(GUEST_RIP); 164 reason = vmcs_read(EXI_REASON) & 0xff; 165 insn_len = vmcs_read(EXI_INST_LEN); 166 switch (reason) { 167 case VMX_PREEMPT: 168 switch (vmx_get_test_stage()) { 169 case 1: 170 case 2: 171 report(((rdtsc() - tsc_val) >> preempt_scale) >= preempt_val, 172 "busy-wait for preemption timer"); 173 vmx_set_test_stage(3); 174 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 175 return VMX_TEST_RESUME; 176 case 3: 177 guest_halted = 178 (vmcs_read(GUEST_ACTV_STATE) == ACTV_HLT); 179 report(((rdtsc() - tsc_val) >> preempt_scale) >= preempt_val 180 && guest_halted, 181 "preemption timer during hlt"); 182 vmx_set_test_stage(4); 183 vmcs_write(PIN_CONTROLS, 184 vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 185 vmcs_write(EXI_CONTROLS, 186 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_PREEMPT); 187 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 188 return VMX_TEST_RESUME; 189 case 4: 190 report(saved_rip == guest_rip, 191 "preemption timer with 0 value"); 192 break; 193 default: 194 report(false, "Invalid stage."); 195 print_vmexit_info(); 196 break; 197 } 198 break; 199 case VMX_VMCALL: 200 vmcs_write(GUEST_RIP, guest_rip + insn_len); 201 switch (vmx_get_test_stage()) { 202 case 0: 203 report(vmcs_read(PREEMPT_TIMER_VALUE) == preempt_val, 204 "Keep preemption value"); 205 vmx_set_test_stage(1); 206 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 207 ctrl_exit = (vmcs_read(EXI_CONTROLS) | 208 EXI_SAVE_PREEMPT) & ctrl_exit_rev.clr; 209 vmcs_write(EXI_CONTROLS, ctrl_exit); 210 return VMX_TEST_RESUME; 211 case 1: 212 report(vmcs_read(PREEMPT_TIMER_VALUE) < preempt_val, 213 "Save preemption value"); 214 return VMX_TEST_RESUME; 215 case 2: 216 report(0, "busy-wait for preemption timer"); 217 vmx_set_test_stage(3); 218 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 219 return VMX_TEST_RESUME; 220 case 3: 221 report(0, "preemption timer during hlt"); 222 vmx_set_test_stage(4); 223 /* fall through */ 224 case 4: 225 vmcs_write(PIN_CONTROLS, 226 vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 227 vmcs_write(PREEMPT_TIMER_VALUE, 0); 228 saved_rip = guest_rip + insn_len; 229 return VMX_TEST_RESUME; 230 case 5: 231 report(0, 232 "preemption timer with 0 value (vmcall stage 5)"); 233 break; 234 default: 235 // Should not reach here 236 report(false, "unexpected stage, %d", 237 vmx_get_test_stage()); 238 print_vmexit_info(); 239 return VMX_TEST_VMEXIT; 240 } 241 break; 242 default: 243 report(false, "Unknown exit reason, %ld", reason); 244 print_vmexit_info(); 245 } 246 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 247 return VMX_TEST_VMEXIT; 248 } 249 250 static void msr_bmp_init(void) 251 { 252 void *msr_bitmap; 253 u32 ctrl_cpu0; 254 255 msr_bitmap = alloc_page(); 256 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 257 ctrl_cpu0 |= CPU_MSR_BITMAP; 258 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 259 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 260 } 261 262 static void *get_msr_bitmap(void) 263 { 264 void *msr_bitmap; 265 266 if (vmcs_read(CPU_EXEC_CTRL0) & CPU_MSR_BITMAP) { 267 msr_bitmap = (void *)vmcs_read(MSR_BITMAP); 268 } else { 269 msr_bitmap = alloc_page(); 270 memset(msr_bitmap, 0xff, PAGE_SIZE); 271 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 272 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_MSR_BITMAP); 273 } 274 275 return msr_bitmap; 276 } 277 278 static void disable_intercept_for_x2apic_msrs(void) 279 { 280 unsigned long *msr_bitmap = (unsigned long *)get_msr_bitmap(); 281 u32 msr; 282 283 for (msr = APIC_BASE_MSR; 284 msr < (APIC_BASE_MSR+0xff); 285 msr += BITS_PER_LONG) { 286 unsigned int word = msr / BITS_PER_LONG; 287 288 msr_bitmap[word] = 0; 289 msr_bitmap[word + (0x800 / sizeof(long))] = 0; 290 } 291 } 292 293 static int test_ctrl_pat_init(struct vmcs *vmcs) 294 { 295 u64 ctrl_ent; 296 u64 ctrl_exi; 297 298 msr_bmp_init(); 299 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT) && 300 !(ctrl_exit_rev.clr & EXI_LOAD_PAT) && 301 !(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 302 printf("\tSave/load PAT is not supported\n"); 303 return 1; 304 } 305 306 ctrl_ent = vmcs_read(ENT_CONTROLS); 307 ctrl_exi = vmcs_read(EXI_CONTROLS); 308 ctrl_ent |= ctrl_enter_rev.clr & ENT_LOAD_PAT; 309 ctrl_exi |= ctrl_exit_rev.clr & (EXI_SAVE_PAT | EXI_LOAD_PAT); 310 vmcs_write(ENT_CONTROLS, ctrl_ent); 311 vmcs_write(EXI_CONTROLS, ctrl_exi); 312 ia32_pat = rdmsr(MSR_IA32_CR_PAT); 313 vmcs_write(GUEST_PAT, 0x0); 314 vmcs_write(HOST_PAT, ia32_pat); 315 return VMX_TEST_START; 316 } 317 318 static void test_ctrl_pat_main(void) 319 { 320 u64 guest_ia32_pat; 321 322 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 323 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) 324 printf("\tENT_LOAD_PAT is not supported.\n"); 325 else { 326 if (guest_ia32_pat != 0) { 327 report(0, "Entry load PAT"); 328 return; 329 } 330 } 331 wrmsr(MSR_IA32_CR_PAT, 0x6); 332 vmcall(); 333 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 334 if (ctrl_enter_rev.clr & ENT_LOAD_PAT) 335 report(guest_ia32_pat == ia32_pat, "Entry load PAT"); 336 } 337 338 static int test_ctrl_pat_exit_handler(void) 339 { 340 u64 guest_rip; 341 ulong reason; 342 u64 guest_pat; 343 344 guest_rip = vmcs_read(GUEST_RIP); 345 reason = vmcs_read(EXI_REASON) & 0xff; 346 switch (reason) { 347 case VMX_VMCALL: 348 guest_pat = vmcs_read(GUEST_PAT); 349 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT)) { 350 printf("\tEXI_SAVE_PAT is not supported\n"); 351 vmcs_write(GUEST_PAT, 0x6); 352 } else { 353 report(guest_pat == 0x6, "Exit save PAT"); 354 } 355 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) 356 printf("\tEXI_LOAD_PAT is not supported\n"); 357 else 358 report(rdmsr(MSR_IA32_CR_PAT) == ia32_pat, 359 "Exit load PAT"); 360 vmcs_write(GUEST_PAT, ia32_pat); 361 vmcs_write(GUEST_RIP, guest_rip + 3); 362 return VMX_TEST_RESUME; 363 default: 364 printf("ERROR : Undefined exit reason, reason = %ld.\n", reason); 365 break; 366 } 367 return VMX_TEST_VMEXIT; 368 } 369 370 static int test_ctrl_efer_init(struct vmcs *vmcs) 371 { 372 u64 ctrl_ent; 373 u64 ctrl_exi; 374 375 msr_bmp_init(); 376 ctrl_ent = vmcs_read(ENT_CONTROLS) | ENT_LOAD_EFER; 377 ctrl_exi = vmcs_read(EXI_CONTROLS) | EXI_SAVE_EFER | EXI_LOAD_EFER; 378 vmcs_write(ENT_CONTROLS, ctrl_ent & ctrl_enter_rev.clr); 379 vmcs_write(EXI_CONTROLS, ctrl_exi & ctrl_exit_rev.clr); 380 ia32_efer = rdmsr(MSR_EFER); 381 vmcs_write(GUEST_EFER, ia32_efer ^ EFER_NX); 382 vmcs_write(HOST_EFER, ia32_efer ^ EFER_NX); 383 return VMX_TEST_START; 384 } 385 386 static void test_ctrl_efer_main(void) 387 { 388 u64 guest_ia32_efer; 389 390 guest_ia32_efer = rdmsr(MSR_EFER); 391 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) 392 printf("\tENT_LOAD_EFER is not supported.\n"); 393 else { 394 if (guest_ia32_efer != (ia32_efer ^ EFER_NX)) { 395 report(0, "Entry load EFER"); 396 return; 397 } 398 } 399 wrmsr(MSR_EFER, ia32_efer); 400 vmcall(); 401 guest_ia32_efer = rdmsr(MSR_EFER); 402 if (ctrl_enter_rev.clr & ENT_LOAD_EFER) 403 report(guest_ia32_efer == ia32_efer, "Entry load EFER"); 404 } 405 406 static int test_ctrl_efer_exit_handler(void) 407 { 408 u64 guest_rip; 409 ulong reason; 410 u64 guest_efer; 411 412 guest_rip = vmcs_read(GUEST_RIP); 413 reason = vmcs_read(EXI_REASON) & 0xff; 414 switch (reason) { 415 case VMX_VMCALL: 416 guest_efer = vmcs_read(GUEST_EFER); 417 if (!(ctrl_exit_rev.clr & EXI_SAVE_EFER)) { 418 printf("\tEXI_SAVE_EFER is not supported\n"); 419 vmcs_write(GUEST_EFER, ia32_efer); 420 } else { 421 report(guest_efer == ia32_efer, "Exit save EFER"); 422 } 423 if (!(ctrl_exit_rev.clr & EXI_LOAD_EFER)) { 424 printf("\tEXI_LOAD_EFER is not supported\n"); 425 wrmsr(MSR_EFER, ia32_efer ^ EFER_NX); 426 } else { 427 report(rdmsr(MSR_EFER) == (ia32_efer ^ EFER_NX), 428 "Exit load EFER"); 429 } 430 vmcs_write(GUEST_PAT, ia32_efer); 431 vmcs_write(GUEST_RIP, guest_rip + 3); 432 return VMX_TEST_RESUME; 433 default: 434 printf("ERROR : Undefined exit reason, reason = %ld.\n", reason); 435 break; 436 } 437 return VMX_TEST_VMEXIT; 438 } 439 440 u32 guest_cr0, guest_cr4; 441 442 static void cr_shadowing_main(void) 443 { 444 u32 cr0, cr4, tmp; 445 446 // Test read through 447 vmx_set_test_stage(0); 448 guest_cr0 = read_cr0(); 449 if (vmx_get_test_stage() == 1) 450 report(0, "Read through CR0"); 451 else 452 vmcall(); 453 vmx_set_test_stage(1); 454 guest_cr4 = read_cr4(); 455 if (vmx_get_test_stage() == 2) 456 report(0, "Read through CR4"); 457 else 458 vmcall(); 459 // Test write through 460 guest_cr0 = guest_cr0 ^ (X86_CR0_TS | X86_CR0_MP); 461 guest_cr4 = guest_cr4 ^ (X86_CR4_TSD | X86_CR4_DE); 462 vmx_set_test_stage(2); 463 write_cr0(guest_cr0); 464 if (vmx_get_test_stage() == 3) 465 report(0, "Write throuth CR0"); 466 else 467 vmcall(); 468 vmx_set_test_stage(3); 469 write_cr4(guest_cr4); 470 if (vmx_get_test_stage() == 4) 471 report(0, "Write through CR4"); 472 else 473 vmcall(); 474 // Test read shadow 475 vmx_set_test_stage(4); 476 vmcall(); 477 cr0 = read_cr0(); 478 if (vmx_get_test_stage() != 5) 479 report(cr0 == guest_cr0, "Read shadowing CR0"); 480 vmx_set_test_stage(5); 481 cr4 = read_cr4(); 482 if (vmx_get_test_stage() != 6) 483 report(cr4 == guest_cr4, "Read shadowing CR4"); 484 // Test write shadow (same value with shadow) 485 vmx_set_test_stage(6); 486 write_cr0(guest_cr0); 487 if (vmx_get_test_stage() == 7) 488 report(0, "Write shadowing CR0 (same value with shadow)"); 489 else 490 vmcall(); 491 vmx_set_test_stage(7); 492 write_cr4(guest_cr4); 493 if (vmx_get_test_stage() == 8) 494 report(0, "Write shadowing CR4 (same value with shadow)"); 495 else 496 vmcall(); 497 // Test write shadow (different value) 498 vmx_set_test_stage(8); 499 tmp = guest_cr0 ^ X86_CR0_TS; 500 asm volatile("mov %0, %%rsi\n\t" 501 "mov %%rsi, %%cr0\n\t" 502 ::"m"(tmp) 503 :"rsi", "memory", "cc"); 504 report(vmx_get_test_stage() == 9, 505 "Write shadowing different X86_CR0_TS"); 506 vmx_set_test_stage(9); 507 tmp = guest_cr0 ^ X86_CR0_MP; 508 asm volatile("mov %0, %%rsi\n\t" 509 "mov %%rsi, %%cr0\n\t" 510 ::"m"(tmp) 511 :"rsi", "memory", "cc"); 512 report(vmx_get_test_stage() == 10, 513 "Write shadowing different X86_CR0_MP"); 514 vmx_set_test_stage(10); 515 tmp = guest_cr4 ^ X86_CR4_TSD; 516 asm volatile("mov %0, %%rsi\n\t" 517 "mov %%rsi, %%cr4\n\t" 518 ::"m"(tmp) 519 :"rsi", "memory", "cc"); 520 report(vmx_get_test_stage() == 11, 521 "Write shadowing different X86_CR4_TSD"); 522 vmx_set_test_stage(11); 523 tmp = guest_cr4 ^ X86_CR4_DE; 524 asm volatile("mov %0, %%rsi\n\t" 525 "mov %%rsi, %%cr4\n\t" 526 ::"m"(tmp) 527 :"rsi", "memory", "cc"); 528 report(vmx_get_test_stage() == 12, 529 "Write shadowing different X86_CR4_DE"); 530 } 531 532 static int cr_shadowing_exit_handler(void) 533 { 534 u64 guest_rip; 535 ulong reason; 536 u32 insn_len; 537 u32 exit_qual; 538 539 guest_rip = vmcs_read(GUEST_RIP); 540 reason = vmcs_read(EXI_REASON) & 0xff; 541 insn_len = vmcs_read(EXI_INST_LEN); 542 exit_qual = vmcs_read(EXI_QUALIFICATION); 543 switch (reason) { 544 case VMX_VMCALL: 545 switch (vmx_get_test_stage()) { 546 case 0: 547 report(guest_cr0 == vmcs_read(GUEST_CR0), 548 "Read through CR0"); 549 break; 550 case 1: 551 report(guest_cr4 == vmcs_read(GUEST_CR4), 552 "Read through CR4"); 553 break; 554 case 2: 555 report(guest_cr0 == vmcs_read(GUEST_CR0), 556 "Write through CR0"); 557 break; 558 case 3: 559 report(guest_cr4 == vmcs_read(GUEST_CR4), 560 "Write through CR4"); 561 break; 562 case 4: 563 guest_cr0 = vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP); 564 guest_cr4 = vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE); 565 vmcs_write(CR0_MASK, X86_CR0_TS | X86_CR0_MP); 566 vmcs_write(CR0_READ_SHADOW, guest_cr0 & (X86_CR0_TS | X86_CR0_MP)); 567 vmcs_write(CR4_MASK, X86_CR4_TSD | X86_CR4_DE); 568 vmcs_write(CR4_READ_SHADOW, guest_cr4 & (X86_CR4_TSD | X86_CR4_DE)); 569 break; 570 case 6: 571 report(guest_cr0 == (vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP)), 572 "Write shadowing CR0 (same value)"); 573 break; 574 case 7: 575 report(guest_cr4 == (vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE)), 576 "Write shadowing CR4 (same value)"); 577 break; 578 default: 579 // Should not reach here 580 report(false, "unexpected stage, %d", 581 vmx_get_test_stage()); 582 print_vmexit_info(); 583 return VMX_TEST_VMEXIT; 584 } 585 vmcs_write(GUEST_RIP, guest_rip + insn_len); 586 return VMX_TEST_RESUME; 587 case VMX_CR: 588 switch (vmx_get_test_stage()) { 589 case 4: 590 report(0, "Read shadowing CR0"); 591 vmx_inc_test_stage(); 592 break; 593 case 5: 594 report(0, "Read shadowing CR4"); 595 vmx_inc_test_stage(); 596 break; 597 case 6: 598 report(0, "Write shadowing CR0 (same value)"); 599 vmx_inc_test_stage(); 600 break; 601 case 7: 602 report(0, "Write shadowing CR4 (same value)"); 603 vmx_inc_test_stage(); 604 break; 605 case 8: 606 case 9: 607 // 0x600 encodes "mov %esi, %cr0" 608 if (exit_qual == 0x600) 609 vmx_inc_test_stage(); 610 break; 611 case 10: 612 case 11: 613 // 0x604 encodes "mov %esi, %cr4" 614 if (exit_qual == 0x604) 615 vmx_inc_test_stage(); 616 break; 617 default: 618 // Should not reach here 619 report(false, "unexpected stage, %d", 620 vmx_get_test_stage()); 621 print_vmexit_info(); 622 return VMX_TEST_VMEXIT; 623 } 624 vmcs_write(GUEST_RIP, guest_rip + insn_len); 625 return VMX_TEST_RESUME; 626 default: 627 report(false, "Unknown exit reason, %ld", reason); 628 print_vmexit_info(); 629 } 630 return VMX_TEST_VMEXIT; 631 } 632 633 static int iobmp_init(struct vmcs *vmcs) 634 { 635 u32 ctrl_cpu0; 636 637 io_bitmap_a = alloc_page(); 638 io_bitmap_b = alloc_page(); 639 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 640 ctrl_cpu0 |= CPU_IO_BITMAP; 641 ctrl_cpu0 &= (~CPU_IO); 642 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 643 vmcs_write(IO_BITMAP_A, (u64)io_bitmap_a); 644 vmcs_write(IO_BITMAP_B, (u64)io_bitmap_b); 645 return VMX_TEST_START; 646 } 647 648 static void iobmp_main(void) 649 { 650 // stage 0, test IO pass 651 vmx_set_test_stage(0); 652 inb(0x5000); 653 outb(0x0, 0x5000); 654 report(vmx_get_test_stage() == 0, "I/O bitmap - I/O pass"); 655 // test IO width, in/out 656 ((u8 *)io_bitmap_a)[0] = 0xFF; 657 vmx_set_test_stage(2); 658 inb(0x0); 659 report(vmx_get_test_stage() == 3, "I/O bitmap - trap in"); 660 vmx_set_test_stage(3); 661 outw(0x0, 0x0); 662 report(vmx_get_test_stage() == 4, "I/O bitmap - trap out"); 663 vmx_set_test_stage(4); 664 inl(0x0); 665 report(vmx_get_test_stage() == 5, "I/O bitmap - I/O width, long"); 666 // test low/high IO port 667 vmx_set_test_stage(5); 668 ((u8 *)io_bitmap_a)[0x5000 / 8] = (1 << (0x5000 % 8)); 669 inb(0x5000); 670 report(vmx_get_test_stage() == 6, "I/O bitmap - I/O port, low part"); 671 vmx_set_test_stage(6); 672 ((u8 *)io_bitmap_b)[0x1000 / 8] = (1 << (0x1000 % 8)); 673 inb(0x9000); 674 report(vmx_get_test_stage() == 7, "I/O bitmap - I/O port, high part"); 675 // test partial pass 676 vmx_set_test_stage(7); 677 inl(0x4FFF); 678 report(vmx_get_test_stage() == 8, "I/O bitmap - partial pass"); 679 // test overrun 680 vmx_set_test_stage(8); 681 memset(io_bitmap_a, 0x0, PAGE_SIZE); 682 memset(io_bitmap_b, 0x0, PAGE_SIZE); 683 inl(0xFFFF); 684 report(vmx_get_test_stage() == 9, "I/O bitmap - overrun"); 685 vmx_set_test_stage(9); 686 vmcall(); 687 outb(0x0, 0x0); 688 report(vmx_get_test_stage() == 9, 689 "I/O bitmap - ignore unconditional exiting"); 690 vmx_set_test_stage(10); 691 vmcall(); 692 outb(0x0, 0x0); 693 report(vmx_get_test_stage() == 11, 694 "I/O bitmap - unconditional exiting"); 695 } 696 697 static int iobmp_exit_handler(void) 698 { 699 u64 guest_rip; 700 ulong reason, exit_qual; 701 u32 insn_len, ctrl_cpu0; 702 703 guest_rip = vmcs_read(GUEST_RIP); 704 reason = vmcs_read(EXI_REASON) & 0xff; 705 exit_qual = vmcs_read(EXI_QUALIFICATION); 706 insn_len = vmcs_read(EXI_INST_LEN); 707 switch (reason) { 708 case VMX_IO: 709 switch (vmx_get_test_stage()) { 710 case 0: 711 case 1: 712 vmx_inc_test_stage(); 713 break; 714 case 2: 715 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_BYTE, 716 "I/O bitmap - I/O width, byte"); 717 report(exit_qual & VMX_IO_IN, 718 "I/O bitmap - I/O direction, in"); 719 vmx_inc_test_stage(); 720 break; 721 case 3: 722 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_WORD, 723 "I/O bitmap - I/O width, word"); 724 report(!(exit_qual & VMX_IO_IN), 725 "I/O bitmap - I/O direction, out"); 726 vmx_inc_test_stage(); 727 break; 728 case 4: 729 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_LONG, 730 "I/O bitmap - I/O width, long"); 731 vmx_inc_test_stage(); 732 break; 733 case 5: 734 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x5000) 735 vmx_inc_test_stage(); 736 break; 737 case 6: 738 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x9000) 739 vmx_inc_test_stage(); 740 break; 741 case 7: 742 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x4FFF) 743 vmx_inc_test_stage(); 744 break; 745 case 8: 746 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0xFFFF) 747 vmx_inc_test_stage(); 748 break; 749 case 9: 750 case 10: 751 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 752 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0 & ~CPU_IO); 753 vmx_inc_test_stage(); 754 break; 755 default: 756 // Should not reach here 757 report(false, "unexpected stage, %d", 758 vmx_get_test_stage()); 759 print_vmexit_info(); 760 return VMX_TEST_VMEXIT; 761 } 762 vmcs_write(GUEST_RIP, guest_rip + insn_len); 763 return VMX_TEST_RESUME; 764 case VMX_VMCALL: 765 switch (vmx_get_test_stage()) { 766 case 9: 767 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 768 ctrl_cpu0 |= CPU_IO | CPU_IO_BITMAP; 769 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 770 break; 771 case 10: 772 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 773 ctrl_cpu0 = (ctrl_cpu0 & ~CPU_IO_BITMAP) | CPU_IO; 774 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 775 break; 776 default: 777 // Should not reach here 778 report(false, "unexpected stage, %d", 779 vmx_get_test_stage()); 780 print_vmexit_info(); 781 return VMX_TEST_VMEXIT; 782 } 783 vmcs_write(GUEST_RIP, guest_rip + insn_len); 784 return VMX_TEST_RESUME; 785 default: 786 printf("guest_rip = %#lx\n", guest_rip); 787 printf("\tERROR : Undefined exit reason, reason = %ld.\n", reason); 788 break; 789 } 790 return VMX_TEST_VMEXIT; 791 } 792 793 #define INSN_CPU0 0 794 #define INSN_CPU1 1 795 #define INSN_ALWAYS_TRAP 2 796 797 #define FIELD_EXIT_QUAL (1 << 0) 798 #define FIELD_INSN_INFO (1 << 1) 799 800 asm( 801 "insn_hlt: hlt;ret\n\t" 802 "insn_invlpg: invlpg 0x12345678;ret\n\t" 803 "insn_mwait: xor %eax, %eax; xor %ecx, %ecx; mwait;ret\n\t" 804 "insn_rdpmc: xor %ecx, %ecx; rdpmc;ret\n\t" 805 "insn_rdtsc: rdtsc;ret\n\t" 806 "insn_cr3_load: mov cr3,%rax; mov %rax,%cr3;ret\n\t" 807 "insn_cr3_store: mov %cr3,%rax;ret\n\t" 808 #ifdef __x86_64__ 809 "insn_cr8_load: xor %eax, %eax; mov %rax,%cr8;ret\n\t" 810 "insn_cr8_store: mov %cr8,%rax;ret\n\t" 811 #endif 812 "insn_monitor: xor %eax, %eax; xor %ecx, %ecx; xor %edx, %edx; monitor;ret\n\t" 813 "insn_pause: pause;ret\n\t" 814 "insn_wbinvd: wbinvd;ret\n\t" 815 "insn_cpuid: mov $10, %eax; cpuid;ret\n\t" 816 "insn_invd: invd;ret\n\t" 817 "insn_sgdt: sgdt gdt64_desc;ret\n\t" 818 "insn_lgdt: lgdt gdt64_desc;ret\n\t" 819 "insn_sidt: sidt idt_descr;ret\n\t" 820 "insn_lidt: lidt idt_descr;ret\n\t" 821 "insn_sldt: sldt %ax;ret\n\t" 822 "insn_lldt: xor %eax, %eax; lldt %ax;ret\n\t" 823 "insn_str: str %ax;ret\n\t" 824 "insn_rdrand: rdrand %rax;ret\n\t" 825 "insn_rdseed: rdseed %rax;ret\n\t" 826 ); 827 extern void insn_hlt(void); 828 extern void insn_invlpg(void); 829 extern void insn_mwait(void); 830 extern void insn_rdpmc(void); 831 extern void insn_rdtsc(void); 832 extern void insn_cr3_load(void); 833 extern void insn_cr3_store(void); 834 #ifdef __x86_64__ 835 extern void insn_cr8_load(void); 836 extern void insn_cr8_store(void); 837 #endif 838 extern void insn_monitor(void); 839 extern void insn_pause(void); 840 extern void insn_wbinvd(void); 841 extern void insn_sgdt(void); 842 extern void insn_lgdt(void); 843 extern void insn_sidt(void); 844 extern void insn_lidt(void); 845 extern void insn_sldt(void); 846 extern void insn_lldt(void); 847 extern void insn_str(void); 848 extern void insn_cpuid(void); 849 extern void insn_invd(void); 850 extern void insn_rdrand(void); 851 extern void insn_rdseed(void); 852 853 u32 cur_insn; 854 u64 cr3; 855 856 #define X86_FEATURE_MONITOR (1 << 3) 857 858 typedef bool (*supported_fn)(void); 859 860 static bool monitor_supported(void) 861 { 862 return this_cpu_has(X86_FEATURE_MWAIT); 863 } 864 865 struct insn_table { 866 const char *name; 867 u32 flag; 868 void (*insn_func)(void); 869 u32 type; 870 u32 reason; 871 ulong exit_qual; 872 u32 insn_info; 873 // Use FIELD_EXIT_QUAL and FIELD_INSN_INFO to define 874 // which field need to be tested, reason is always tested 875 u32 test_field; 876 const supported_fn supported_fn; 877 u8 disabled; 878 }; 879 880 /* 881 * Add more test cases of instruction intercept here. Elements in this 882 * table is: 883 * name/control flag/insn function/type/exit reason/exit qulification/ 884 * instruction info/field to test 885 * The last field defines which fields (exit_qual and insn_info) need to be 886 * tested in exit handler. If set to 0, only "reason" is checked. 887 */ 888 static struct insn_table insn_table[] = { 889 // Flags for Primary Processor-Based VM-Execution Controls 890 {"HLT", CPU_HLT, insn_hlt, INSN_CPU0, 12, 0, 0, 0}, 891 {"INVLPG", CPU_INVLPG, insn_invlpg, INSN_CPU0, 14, 892 0x12345678, 0, FIELD_EXIT_QUAL}, 893 {"MWAIT", CPU_MWAIT, insn_mwait, INSN_CPU0, 36, 0, 0, 0, &monitor_supported}, 894 {"RDPMC", CPU_RDPMC, insn_rdpmc, INSN_CPU0, 15, 0, 0, 0}, 895 {"RDTSC", CPU_RDTSC, insn_rdtsc, INSN_CPU0, 16, 0, 0, 0}, 896 {"CR3 load", CPU_CR3_LOAD, insn_cr3_load, INSN_CPU0, 28, 0x3, 0, 897 FIELD_EXIT_QUAL}, 898 {"CR3 store", CPU_CR3_STORE, insn_cr3_store, INSN_CPU0, 28, 0x13, 0, 899 FIELD_EXIT_QUAL}, 900 #ifdef __x86_64__ 901 {"CR8 load", CPU_CR8_LOAD, insn_cr8_load, INSN_CPU0, 28, 0x8, 0, 902 FIELD_EXIT_QUAL}, 903 {"CR8 store", CPU_CR8_STORE, insn_cr8_store, INSN_CPU0, 28, 0x18, 0, 904 FIELD_EXIT_QUAL}, 905 #endif 906 {"MONITOR", CPU_MONITOR, insn_monitor, INSN_CPU0, 39, 0, 0, 0, &monitor_supported}, 907 {"PAUSE", CPU_PAUSE, insn_pause, INSN_CPU0, 40, 0, 0, 0}, 908 // Flags for Secondary Processor-Based VM-Execution Controls 909 {"WBINVD", CPU_WBINVD, insn_wbinvd, INSN_CPU1, 54, 0, 0, 0}, 910 {"DESC_TABLE (SGDT)", CPU_DESC_TABLE, insn_sgdt, INSN_CPU1, 46, 0, 0, 0}, 911 {"DESC_TABLE (LGDT)", CPU_DESC_TABLE, insn_lgdt, INSN_CPU1, 46, 0, 0, 0}, 912 {"DESC_TABLE (SIDT)", CPU_DESC_TABLE, insn_sidt, INSN_CPU1, 46, 0, 0, 0}, 913 {"DESC_TABLE (LIDT)", CPU_DESC_TABLE, insn_lidt, INSN_CPU1, 46, 0, 0, 0}, 914 {"DESC_TABLE (SLDT)", CPU_DESC_TABLE, insn_sldt, INSN_CPU1, 47, 0, 0, 0}, 915 {"DESC_TABLE (LLDT)", CPU_DESC_TABLE, insn_lldt, INSN_CPU1, 47, 0, 0, 0}, 916 {"DESC_TABLE (STR)", CPU_DESC_TABLE, insn_str, INSN_CPU1, 47, 0, 0, 0}, 917 /* LTR causes a #GP if done with a busy selector, so it is not tested. */ 918 {"RDRAND", CPU_RDRAND, insn_rdrand, INSN_CPU1, VMX_RDRAND, 0, 0, 0}, 919 {"RDSEED", CPU_RDSEED, insn_rdseed, INSN_CPU1, VMX_RDSEED, 0, 0, 0}, 920 // Instructions always trap 921 {"CPUID", 0, insn_cpuid, INSN_ALWAYS_TRAP, 10, 0, 0, 0}, 922 {"INVD", 0, insn_invd, INSN_ALWAYS_TRAP, 13, 0, 0, 0}, 923 // Instructions never trap 924 {NULL}, 925 }; 926 927 static int insn_intercept_init(struct vmcs *vmcs) 928 { 929 u32 ctrl_cpu, cur_insn; 930 931 ctrl_cpu = ctrl_cpu_rev[0].set | CPU_SECONDARY; 932 ctrl_cpu &= ctrl_cpu_rev[0].clr; 933 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu); 934 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu_rev[1].set); 935 cr3 = read_cr3(); 936 937 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 938 if (insn_table[cur_insn].supported_fn == NULL) 939 continue; 940 insn_table[cur_insn].disabled = !insn_table[cur_insn].supported_fn(); 941 } 942 return VMX_TEST_START; 943 } 944 945 static void insn_intercept_main(void) 946 { 947 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 948 vmx_set_test_stage(cur_insn * 2); 949 if ((insn_table[cur_insn].type == INSN_CPU0 && 950 !(ctrl_cpu_rev[0].clr & insn_table[cur_insn].flag)) || 951 (insn_table[cur_insn].type == INSN_CPU1 && 952 !(ctrl_cpu_rev[1].clr & insn_table[cur_insn].flag))) { 953 printf("\tCPU_CTRL%d.CPU_%s is not supported.\n", 954 insn_table[cur_insn].type - INSN_CPU0, 955 insn_table[cur_insn].name); 956 continue; 957 } 958 959 if (insn_table[cur_insn].disabled) { 960 printf("\tFeature required for %s is not supported.\n", 961 insn_table[cur_insn].name); 962 continue; 963 } 964 965 if ((insn_table[cur_insn].type == INSN_CPU0 && 966 !(ctrl_cpu_rev[0].set & insn_table[cur_insn].flag)) || 967 (insn_table[cur_insn].type == INSN_CPU1 && 968 !(ctrl_cpu_rev[1].set & insn_table[cur_insn].flag))) { 969 /* skip hlt, it stalls the guest and is tested below */ 970 if (insn_table[cur_insn].insn_func != insn_hlt) 971 insn_table[cur_insn].insn_func(); 972 report(vmx_get_test_stage() == cur_insn * 2, 973 "execute %s", 974 insn_table[cur_insn].name); 975 } else if (insn_table[cur_insn].type != INSN_ALWAYS_TRAP) 976 printf("\tCPU_CTRL%d.CPU_%s always traps.\n", 977 insn_table[cur_insn].type - INSN_CPU0, 978 insn_table[cur_insn].name); 979 980 vmcall(); 981 982 insn_table[cur_insn].insn_func(); 983 report(vmx_get_test_stage() == cur_insn * 2 + 1, 984 "intercept %s", 985 insn_table[cur_insn].name); 986 987 vmx_set_test_stage(cur_insn * 2 + 1); 988 vmcall(); 989 } 990 } 991 992 static int insn_intercept_exit_handler(void) 993 { 994 u64 guest_rip; 995 u32 reason; 996 ulong exit_qual; 997 u32 insn_len; 998 u32 insn_info; 999 bool pass; 1000 1001 guest_rip = vmcs_read(GUEST_RIP); 1002 reason = vmcs_read(EXI_REASON) & 0xff; 1003 exit_qual = vmcs_read(EXI_QUALIFICATION); 1004 insn_len = vmcs_read(EXI_INST_LEN); 1005 insn_info = vmcs_read(EXI_INST_INFO); 1006 1007 if (reason == VMX_VMCALL) { 1008 u32 val = 0; 1009 1010 if (insn_table[cur_insn].type == INSN_CPU0) 1011 val = vmcs_read(CPU_EXEC_CTRL0); 1012 else if (insn_table[cur_insn].type == INSN_CPU1) 1013 val = vmcs_read(CPU_EXEC_CTRL1); 1014 1015 if (vmx_get_test_stage() & 1) 1016 val &= ~insn_table[cur_insn].flag; 1017 else 1018 val |= insn_table[cur_insn].flag; 1019 1020 if (insn_table[cur_insn].type == INSN_CPU0) 1021 vmcs_write(CPU_EXEC_CTRL0, val | ctrl_cpu_rev[0].set); 1022 else if (insn_table[cur_insn].type == INSN_CPU1) 1023 vmcs_write(CPU_EXEC_CTRL1, val | ctrl_cpu_rev[1].set); 1024 } else { 1025 pass = (cur_insn * 2 == vmx_get_test_stage()) && 1026 insn_table[cur_insn].reason == reason; 1027 if (insn_table[cur_insn].test_field & FIELD_EXIT_QUAL && 1028 insn_table[cur_insn].exit_qual != exit_qual) 1029 pass = false; 1030 if (insn_table[cur_insn].test_field & FIELD_INSN_INFO && 1031 insn_table[cur_insn].insn_info != insn_info) 1032 pass = false; 1033 if (pass) 1034 vmx_inc_test_stage(); 1035 } 1036 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1037 return VMX_TEST_RESUME; 1038 } 1039 1040 /** 1041 * __setup_ept - Setup the VMCS fields to enable Extended Page Tables (EPT) 1042 * @hpa: Host physical address of the top-level, a.k.a. root, EPT table 1043 * @enable_ad: Whether or not to enable Access/Dirty bits for EPT entries 1044 * 1045 * Returns 0 on success, 1 on failure. 1046 * 1047 * Note that @hpa doesn't need to point at actual memory if VM-Launch is 1048 * expected to fail, e.g. setup_dummy_ept() arbitrarily passes '0' to satisfy 1049 * the various EPTP consistency checks, but doesn't ensure backing for HPA '0'. 1050 */ 1051 static int __setup_ept(u64 hpa, bool enable_ad) 1052 { 1053 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1054 !(ctrl_cpu_rev[1].clr & CPU_EPT)) { 1055 printf("\tEPT is not supported"); 1056 return 1; 1057 } 1058 if (!(ept_vpid.val & EPT_CAP_WB)) { 1059 printf("WB memtype for EPT walks not supported\n"); 1060 return 1; 1061 } 1062 if (!(ept_vpid.val & EPT_CAP_PWL4)) { 1063 printf("\tPWL4 is not supported\n"); 1064 return 1; 1065 } 1066 1067 eptp = EPT_MEM_TYPE_WB; 1068 eptp |= (3 << EPTP_PG_WALK_LEN_SHIFT); 1069 eptp |= hpa; 1070 if (enable_ad) 1071 eptp |= EPTP_AD_FLAG; 1072 1073 vmcs_write(EPTP, eptp); 1074 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0)| CPU_SECONDARY); 1075 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1)| CPU_EPT); 1076 1077 return 0; 1078 } 1079 1080 /** 1081 * setup_ept - Enable Extended Page Tables (EPT) and setup an identity map 1082 * @enable_ad: Whether or not to enable Access/Dirty bits for EPT entries 1083 * 1084 * Returns 0 on success, 1 on failure. 1085 * 1086 * This is the "real" function for setting up EPT tables, i.e. use this for 1087 * tests that need to run code in the guest with EPT enabled. 1088 */ 1089 static int setup_ept(bool enable_ad) 1090 { 1091 unsigned long end_of_memory; 1092 1093 pml4 = alloc_page(); 1094 1095 if (__setup_ept(virt_to_phys(pml4), enable_ad)) 1096 return 1; 1097 1098 end_of_memory = fwcfg_get_u64(FW_CFG_RAM_SIZE); 1099 if (end_of_memory < (1ul << 32)) 1100 end_of_memory = (1ul << 32); 1101 /* Cannot use large EPT pages if we need to track EPT 1102 * accessed/dirty bits at 4K granularity. 1103 */ 1104 setup_ept_range(pml4, 0, end_of_memory, 0, 1105 !enable_ad && ept_2m_supported(), 1106 EPT_WA | EPT_RA | EPT_EA); 1107 return 0; 1108 } 1109 1110 /** 1111 * setup_dummy_ept - Enable Extended Page Tables (EPT) with a dummy root HPA 1112 * 1113 * Setup EPT using a semi-arbitrary dummy root HPA. This function is intended 1114 * for use by tests that need EPT enabled to verify dependent VMCS controls 1115 * but never expect to fully enter the guest, i.e. don't need setup the actual 1116 * EPT tables. 1117 */ 1118 static void setup_dummy_ept(void) 1119 { 1120 if (__setup_ept(0, false)) 1121 report_abort("EPT setup unexpectedly failed"); 1122 } 1123 1124 static int enable_unrestricted_guest(void) 1125 { 1126 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1127 !(ctrl_cpu_rev[1].clr & CPU_URG) || 1128 !(ctrl_cpu_rev[1].clr & CPU_EPT)) 1129 return 1; 1130 1131 setup_dummy_ept(); 1132 1133 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 1134 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | CPU_URG); 1135 1136 return 0; 1137 } 1138 1139 static void ept_enable_ad_bits(void) 1140 { 1141 eptp |= EPTP_AD_FLAG; 1142 vmcs_write(EPTP, eptp); 1143 } 1144 1145 static void ept_disable_ad_bits(void) 1146 { 1147 eptp &= ~EPTP_AD_FLAG; 1148 vmcs_write(EPTP, eptp); 1149 } 1150 1151 static int ept_ad_enabled(void) 1152 { 1153 return eptp & EPTP_AD_FLAG; 1154 } 1155 1156 static void ept_enable_ad_bits_or_skip_test(void) 1157 { 1158 if (!ept_ad_bits_supported()) 1159 test_skip("EPT AD bits not supported."); 1160 ept_enable_ad_bits(); 1161 } 1162 1163 static int apic_version; 1164 1165 static int ept_init_common(bool have_ad) 1166 { 1167 int ret; 1168 struct pci_dev pcidev; 1169 1170 if (setup_ept(have_ad)) 1171 return VMX_TEST_EXIT; 1172 data_page1 = alloc_page(); 1173 data_page2 = alloc_page(); 1174 *((u32 *)data_page1) = MAGIC_VAL_1; 1175 *((u32 *)data_page2) = MAGIC_VAL_2; 1176 install_ept(pml4, (unsigned long)data_page1, (unsigned long)data_page2, 1177 EPT_RA | EPT_WA | EPT_EA); 1178 1179 apic_version = apic_read(APIC_LVR); 1180 1181 ret = pci_find_dev(PCI_VENDOR_ID_REDHAT, PCI_DEVICE_ID_REDHAT_TEST); 1182 if (ret != PCIDEVADDR_INVALID) { 1183 pci_dev_init(&pcidev, ret); 1184 pci_physaddr = pcidev.resource[PCI_TESTDEV_BAR_MEM]; 1185 } 1186 1187 return VMX_TEST_START; 1188 } 1189 1190 static int ept_init(struct vmcs *vmcs) 1191 { 1192 return ept_init_common(false); 1193 } 1194 1195 static void ept_common(void) 1196 { 1197 vmx_set_test_stage(0); 1198 if (*((u32 *)data_page2) != MAGIC_VAL_1 || 1199 *((u32 *)data_page1) != MAGIC_VAL_1) 1200 report(0, "EPT basic framework - read"); 1201 else { 1202 *((u32 *)data_page2) = MAGIC_VAL_3; 1203 vmcall(); 1204 if (vmx_get_test_stage() == 1) { 1205 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1206 *((u32 *)data_page2) == MAGIC_VAL_2) 1207 report(1, "EPT basic framework"); 1208 else 1209 report(1, "EPT basic framework - remap"); 1210 } 1211 } 1212 // Test EPT Misconfigurations 1213 vmx_set_test_stage(1); 1214 vmcall(); 1215 *((u32 *)data_page1) = MAGIC_VAL_1; 1216 if (vmx_get_test_stage() != 2) { 1217 report(0, "EPT misconfigurations"); 1218 goto t1; 1219 } 1220 vmx_set_test_stage(2); 1221 vmcall(); 1222 *((u32 *)data_page1) = MAGIC_VAL_1; 1223 report(vmx_get_test_stage() == 3, "EPT misconfigurations"); 1224 t1: 1225 // Test EPT violation 1226 vmx_set_test_stage(3); 1227 vmcall(); 1228 *((u32 *)data_page1) = MAGIC_VAL_1; 1229 report(vmx_get_test_stage() == 4, "EPT violation - page permission"); 1230 // Violation caused by EPT paging structure 1231 vmx_set_test_stage(4); 1232 vmcall(); 1233 *((u32 *)data_page1) = MAGIC_VAL_2; 1234 report(vmx_get_test_stage() == 5, "EPT violation - paging structure"); 1235 1236 // MMIO Read/Write 1237 vmx_set_test_stage(5); 1238 vmcall(); 1239 1240 *(u32 volatile *)pci_physaddr; 1241 report(vmx_get_test_stage() == 6, "MMIO EPT violation - read"); 1242 1243 *(u32 volatile *)pci_physaddr = MAGIC_VAL_1; 1244 report(vmx_get_test_stage() == 7, "MMIO EPT violation - write"); 1245 } 1246 1247 static void ept_main(void) 1248 { 1249 ept_common(); 1250 1251 // Test EPT access to L1 MMIO 1252 vmx_set_test_stage(7); 1253 report(*((u32 *)0xfee00030UL) == apic_version, "EPT - MMIO access"); 1254 1255 // Test invalid operand for INVEPT 1256 vmcall(); 1257 report(vmx_get_test_stage() == 8, "EPT - unsupported INVEPT"); 1258 } 1259 1260 static bool invept_test(int type, u64 eptp) 1261 { 1262 bool ret, supported; 1263 1264 supported = ept_vpid.val & (EPT_CAP_INVEPT_SINGLE >> INVEPT_SINGLE << type); 1265 ret = invept(type, eptp); 1266 1267 if (ret == !supported) 1268 return false; 1269 1270 if (!supported) 1271 printf("WARNING: unsupported invept passed!\n"); 1272 else 1273 printf("WARNING: invept failed!\n"); 1274 1275 return true; 1276 } 1277 1278 static int pml_exit_handler(void) 1279 { 1280 u16 index, count; 1281 ulong reason = vmcs_read(EXI_REASON) & 0xff; 1282 u64 *pmlbuf = pml_log; 1283 u64 guest_rip = vmcs_read(GUEST_RIP);; 1284 u64 guest_cr3 = vmcs_read(GUEST_CR3); 1285 u32 insn_len = vmcs_read(EXI_INST_LEN); 1286 1287 switch (reason) { 1288 case VMX_VMCALL: 1289 switch (vmx_get_test_stage()) { 1290 case 0: 1291 index = vmcs_read(GUEST_PML_INDEX); 1292 for (count = index + 1; count < PML_INDEX; count++) { 1293 if (pmlbuf[count] == (u64)data_page2) { 1294 vmx_inc_test_stage(); 1295 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1296 break; 1297 } 1298 } 1299 break; 1300 case 1: 1301 index = vmcs_read(GUEST_PML_INDEX); 1302 /* Keep clearing the dirty bit till a overflow */ 1303 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1304 break; 1305 default: 1306 report(false, "unexpected stage, %d.", 1307 vmx_get_test_stage()); 1308 print_vmexit_info(); 1309 return VMX_TEST_VMEXIT; 1310 } 1311 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1312 return VMX_TEST_RESUME; 1313 case VMX_PML_FULL: 1314 vmx_inc_test_stage(); 1315 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1316 return VMX_TEST_RESUME; 1317 default: 1318 report(false, "Unknown exit reason, %ld", reason); 1319 print_vmexit_info(); 1320 } 1321 return VMX_TEST_VMEXIT; 1322 } 1323 1324 static int ept_exit_handler_common(bool have_ad) 1325 { 1326 u64 guest_rip; 1327 u64 guest_cr3; 1328 ulong reason; 1329 u32 insn_len; 1330 u32 exit_qual; 1331 static unsigned long data_page1_pte, data_page1_pte_pte, memaddr_pte; 1332 1333 guest_rip = vmcs_read(GUEST_RIP); 1334 guest_cr3 = vmcs_read(GUEST_CR3); 1335 reason = vmcs_read(EXI_REASON) & 0xff; 1336 insn_len = vmcs_read(EXI_INST_LEN); 1337 exit_qual = vmcs_read(EXI_QUALIFICATION); 1338 switch (reason) { 1339 case VMX_VMCALL: 1340 switch (vmx_get_test_stage()) { 1341 case 0: 1342 check_ept_ad(pml4, guest_cr3, 1343 (unsigned long)data_page1, 1344 have_ad ? EPT_ACCESS_FLAG : 0, 1345 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1346 check_ept_ad(pml4, guest_cr3, 1347 (unsigned long)data_page2, 1348 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0, 1349 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1350 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1351 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1352 if (have_ad) 1353 ept_sync(INVEPT_SINGLE, eptp);; 1354 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1355 *((u32 *)data_page2) == MAGIC_VAL_2) { 1356 vmx_inc_test_stage(); 1357 install_ept(pml4, (unsigned long)data_page2, 1358 (unsigned long)data_page2, 1359 EPT_RA | EPT_WA | EPT_EA); 1360 } else 1361 report(0, "EPT basic framework - write"); 1362 break; 1363 case 1: 1364 install_ept(pml4, (unsigned long)data_page1, 1365 (unsigned long)data_page1, EPT_WA); 1366 ept_sync(INVEPT_SINGLE, eptp); 1367 break; 1368 case 2: 1369 install_ept(pml4, (unsigned long)data_page1, 1370 (unsigned long)data_page1, 1371 EPT_RA | EPT_WA | EPT_EA | 1372 (2 << EPT_MEM_TYPE_SHIFT)); 1373 ept_sync(INVEPT_SINGLE, eptp); 1374 break; 1375 case 3: 1376 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1377 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)data_page1, 1378 1, &data_page1_pte)); 1379 set_ept_pte(pml4, (unsigned long)data_page1, 1380 1, data_page1_pte & ~EPT_PRESENT); 1381 ept_sync(INVEPT_SINGLE, eptp); 1382 break; 1383 case 4: 1384 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)data_page1, 1385 2, &data_page1_pte)); 1386 data_page1_pte &= PAGE_MASK; 1387 TEST_ASSERT(get_ept_pte(pml4, data_page1_pte, 1388 2, &data_page1_pte_pte)); 1389 set_ept_pte(pml4, data_page1_pte, 2, 1390 data_page1_pte_pte & ~EPT_PRESENT); 1391 ept_sync(INVEPT_SINGLE, eptp); 1392 break; 1393 case 5: 1394 install_ept(pml4, (unsigned long)pci_physaddr, 1395 (unsigned long)pci_physaddr, 0); 1396 ept_sync(INVEPT_SINGLE, eptp); 1397 break; 1398 case 7: 1399 if (!invept_test(0, eptp)) 1400 vmx_inc_test_stage(); 1401 break; 1402 // Should not reach here 1403 default: 1404 report(false, "ERROR - unexpected stage, %d.", 1405 vmx_get_test_stage()); 1406 print_vmexit_info(); 1407 return VMX_TEST_VMEXIT; 1408 } 1409 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1410 return VMX_TEST_RESUME; 1411 case VMX_EPT_MISCONFIG: 1412 switch (vmx_get_test_stage()) { 1413 case 1: 1414 case 2: 1415 vmx_inc_test_stage(); 1416 install_ept(pml4, (unsigned long)data_page1, 1417 (unsigned long)data_page1, 1418 EPT_RA | EPT_WA | EPT_EA); 1419 ept_sync(INVEPT_SINGLE, eptp); 1420 break; 1421 // Should not reach here 1422 default: 1423 report(false, "ERROR - unexpected stage, %d.", 1424 vmx_get_test_stage()); 1425 print_vmexit_info(); 1426 return VMX_TEST_VMEXIT; 1427 } 1428 return VMX_TEST_RESUME; 1429 case VMX_EPT_VIOLATION: 1430 /* 1431 * Exit-qualifications are masked not to account for advanced 1432 * VM-exit information. Once KVM supports this feature, this 1433 * masking should be removed. 1434 */ 1435 exit_qual &= ~EPT_VLT_GUEST_MASK; 1436 1437 switch(vmx_get_test_stage()) { 1438 case 3: 1439 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1440 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1441 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1442 if (exit_qual == (EPT_VLT_WR | EPT_VLT_LADDR_VLD | 1443 EPT_VLT_PADDR)) 1444 vmx_inc_test_stage(); 1445 set_ept_pte(pml4, (unsigned long)data_page1, 1446 1, data_page1_pte | (EPT_PRESENT)); 1447 ept_sync(INVEPT_SINGLE, eptp); 1448 break; 1449 case 4: 1450 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1451 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1452 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1453 if (exit_qual == (EPT_VLT_RD | 1454 (have_ad ? EPT_VLT_WR : 0) | 1455 EPT_VLT_LADDR_VLD)) 1456 vmx_inc_test_stage(); 1457 set_ept_pte(pml4, data_page1_pte, 2, 1458 data_page1_pte_pte | (EPT_PRESENT)); 1459 ept_sync(INVEPT_SINGLE, eptp); 1460 break; 1461 case 5: 1462 if (exit_qual & EPT_VLT_RD) 1463 vmx_inc_test_stage(); 1464 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1465 1, &memaddr_pte)); 1466 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA); 1467 ept_sync(INVEPT_SINGLE, eptp); 1468 break; 1469 case 6: 1470 if (exit_qual & EPT_VLT_WR) 1471 vmx_inc_test_stage(); 1472 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1473 1, &memaddr_pte)); 1474 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA | EPT_WA); 1475 ept_sync(INVEPT_SINGLE, eptp); 1476 break; 1477 default: 1478 // Should not reach here 1479 report(false, "ERROR : unexpected stage, %d", 1480 vmx_get_test_stage()); 1481 print_vmexit_info(); 1482 return VMX_TEST_VMEXIT; 1483 } 1484 return VMX_TEST_RESUME; 1485 default: 1486 report(false, "Unknown exit reason, %ld", reason); 1487 print_vmexit_info(); 1488 } 1489 return VMX_TEST_VMEXIT; 1490 } 1491 1492 static int ept_exit_handler(void) 1493 { 1494 return ept_exit_handler_common(false); 1495 } 1496 1497 static int eptad_init(struct vmcs *vmcs) 1498 { 1499 int r = ept_init_common(true); 1500 1501 if (r == VMX_TEST_EXIT) 1502 return r; 1503 1504 if ((rdmsr(MSR_IA32_VMX_EPT_VPID_CAP) & EPT_CAP_AD_FLAG) == 0) { 1505 printf("\tEPT A/D bits are not supported"); 1506 return VMX_TEST_EXIT; 1507 } 1508 1509 return r; 1510 } 1511 1512 static int pml_init(struct vmcs *vmcs) 1513 { 1514 u32 ctrl_cpu; 1515 int r = eptad_init(vmcs); 1516 1517 if (r == VMX_TEST_EXIT) 1518 return r; 1519 1520 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1521 !(ctrl_cpu_rev[1].clr & CPU_PML)) { 1522 printf("\tPML is not supported"); 1523 return VMX_TEST_EXIT; 1524 } 1525 1526 pml_log = alloc_page(); 1527 vmcs_write(PMLADDR, (u64)pml_log); 1528 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1529 1530 ctrl_cpu = vmcs_read(CPU_EXEC_CTRL1) | CPU_PML; 1531 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu); 1532 1533 return VMX_TEST_START; 1534 } 1535 1536 static void pml_main(void) 1537 { 1538 int count = 0; 1539 1540 vmx_set_test_stage(0); 1541 *((u32 *)data_page2) = 0x1; 1542 vmcall(); 1543 report(vmx_get_test_stage() == 1, "PML - Dirty GPA Logging"); 1544 1545 while (vmx_get_test_stage() == 1) { 1546 vmcall(); 1547 *((u32 *)data_page2) = 0x1; 1548 if (count++ > PML_INDEX) 1549 break; 1550 } 1551 report(vmx_get_test_stage() == 2, "PML Full Event"); 1552 } 1553 1554 static void eptad_main(void) 1555 { 1556 ept_common(); 1557 } 1558 1559 static int eptad_exit_handler(void) 1560 { 1561 return ept_exit_handler_common(true); 1562 } 1563 1564 static bool invvpid_test(int type, u16 vpid) 1565 { 1566 bool ret, supported; 1567 1568 supported = ept_vpid.val & 1569 (VPID_CAP_INVVPID_ADDR >> INVVPID_ADDR << type); 1570 ret = invvpid(type, vpid, 0); 1571 1572 if (ret == !supported) 1573 return false; 1574 1575 if (!supported) 1576 printf("WARNING: unsupported invvpid passed!\n"); 1577 else 1578 printf("WARNING: invvpid failed!\n"); 1579 1580 return true; 1581 } 1582 1583 static int vpid_init(struct vmcs *vmcs) 1584 { 1585 u32 ctrl_cpu1; 1586 1587 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1588 !(ctrl_cpu_rev[1].clr & CPU_VPID)) { 1589 printf("\tVPID is not supported"); 1590 return VMX_TEST_EXIT; 1591 } 1592 1593 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 1594 ctrl_cpu1 |= CPU_VPID; 1595 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 1596 return VMX_TEST_START; 1597 } 1598 1599 static void vpid_main(void) 1600 { 1601 vmx_set_test_stage(0); 1602 vmcall(); 1603 report(vmx_get_test_stage() == 1, "INVVPID SINGLE ADDRESS"); 1604 vmx_set_test_stage(2); 1605 vmcall(); 1606 report(vmx_get_test_stage() == 3, "INVVPID SINGLE"); 1607 vmx_set_test_stage(4); 1608 vmcall(); 1609 report(vmx_get_test_stage() == 5, "INVVPID ALL"); 1610 } 1611 1612 static int vpid_exit_handler(void) 1613 { 1614 u64 guest_rip; 1615 ulong reason; 1616 u32 insn_len; 1617 1618 guest_rip = vmcs_read(GUEST_RIP); 1619 reason = vmcs_read(EXI_REASON) & 0xff; 1620 insn_len = vmcs_read(EXI_INST_LEN); 1621 1622 switch (reason) { 1623 case VMX_VMCALL: 1624 switch(vmx_get_test_stage()) { 1625 case 0: 1626 if (!invvpid_test(INVVPID_ADDR, 1)) 1627 vmx_inc_test_stage(); 1628 break; 1629 case 2: 1630 if (!invvpid_test(INVVPID_CONTEXT_GLOBAL, 1)) 1631 vmx_inc_test_stage(); 1632 break; 1633 case 4: 1634 if (!invvpid_test(INVVPID_ALL, 1)) 1635 vmx_inc_test_stage(); 1636 break; 1637 default: 1638 report(false, "ERROR: unexpected stage, %d", 1639 vmx_get_test_stage()); 1640 print_vmexit_info(); 1641 return VMX_TEST_VMEXIT; 1642 } 1643 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1644 return VMX_TEST_RESUME; 1645 default: 1646 report(false, "Unknown exit reason, %ld", reason); 1647 print_vmexit_info(); 1648 } 1649 return VMX_TEST_VMEXIT; 1650 } 1651 1652 #define TIMER_VECTOR 222 1653 1654 static volatile bool timer_fired; 1655 1656 static void timer_isr(isr_regs_t *regs) 1657 { 1658 timer_fired = true; 1659 apic_write(APIC_EOI, 0); 1660 } 1661 1662 static int interrupt_init(struct vmcs *vmcs) 1663 { 1664 msr_bmp_init(); 1665 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1666 handle_irq(TIMER_VECTOR, timer_isr); 1667 return VMX_TEST_START; 1668 } 1669 1670 static void interrupt_main(void) 1671 { 1672 long long start, loops; 1673 1674 vmx_set_test_stage(0); 1675 1676 apic_write(APIC_LVTT, TIMER_VECTOR); 1677 irq_enable(); 1678 1679 apic_write(APIC_TMICT, 1); 1680 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1681 asm volatile ("nop"); 1682 report(timer_fired, "direct interrupt while running guest"); 1683 1684 apic_write(APIC_TMICT, 0); 1685 irq_disable(); 1686 vmcall(); 1687 timer_fired = false; 1688 apic_write(APIC_TMICT, 1); 1689 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1690 asm volatile ("nop"); 1691 report(timer_fired, "intercepted interrupt while running guest"); 1692 1693 irq_enable(); 1694 apic_write(APIC_TMICT, 0); 1695 irq_disable(); 1696 vmcall(); 1697 timer_fired = false; 1698 start = rdtsc(); 1699 apic_write(APIC_TMICT, 1000000); 1700 1701 asm volatile ("sti; hlt"); 1702 1703 report(rdtsc() - start > 1000000 && timer_fired, 1704 "direct interrupt + hlt"); 1705 1706 apic_write(APIC_TMICT, 0); 1707 irq_disable(); 1708 vmcall(); 1709 timer_fired = false; 1710 start = rdtsc(); 1711 apic_write(APIC_TMICT, 1000000); 1712 1713 asm volatile ("sti; hlt"); 1714 1715 report(rdtsc() - start > 10000 && timer_fired, 1716 "intercepted interrupt + hlt"); 1717 1718 apic_write(APIC_TMICT, 0); 1719 irq_disable(); 1720 vmcall(); 1721 timer_fired = false; 1722 start = rdtsc(); 1723 apic_write(APIC_TMICT, 1000000); 1724 1725 irq_enable(); 1726 asm volatile ("nop"); 1727 vmcall(); 1728 1729 report(rdtsc() - start > 10000 && timer_fired, 1730 "direct interrupt + activity state hlt"); 1731 1732 apic_write(APIC_TMICT, 0); 1733 irq_disable(); 1734 vmcall(); 1735 timer_fired = false; 1736 start = rdtsc(); 1737 apic_write(APIC_TMICT, 1000000); 1738 1739 irq_enable(); 1740 asm volatile ("nop"); 1741 vmcall(); 1742 1743 report(rdtsc() - start > 10000 && timer_fired, 1744 "intercepted interrupt + activity state hlt"); 1745 1746 apic_write(APIC_TMICT, 0); 1747 irq_disable(); 1748 vmx_set_test_stage(7); 1749 vmcall(); 1750 timer_fired = false; 1751 apic_write(APIC_TMICT, 1); 1752 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1753 asm volatile ("nop"); 1754 report(timer_fired, 1755 "running a guest with interrupt acknowledgement set"); 1756 1757 apic_write(APIC_TMICT, 0); 1758 irq_enable(); 1759 timer_fired = false; 1760 vmcall(); 1761 report(timer_fired, "Inject an event to a halted guest"); 1762 } 1763 1764 static int interrupt_exit_handler(void) 1765 { 1766 u64 guest_rip = vmcs_read(GUEST_RIP); 1767 ulong reason = vmcs_read(EXI_REASON) & 0xff; 1768 u32 insn_len = vmcs_read(EXI_INST_LEN); 1769 1770 switch (reason) { 1771 case VMX_VMCALL: 1772 switch (vmx_get_test_stage()) { 1773 case 0: 1774 case 2: 1775 case 5: 1776 vmcs_write(PIN_CONTROLS, 1777 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1778 break; 1779 case 7: 1780 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_INTA); 1781 vmcs_write(PIN_CONTROLS, 1782 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1783 break; 1784 case 1: 1785 case 3: 1786 vmcs_write(PIN_CONTROLS, 1787 vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1788 break; 1789 case 4: 1790 case 6: 1791 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1792 break; 1793 1794 case 8: 1795 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1796 vmcs_write(ENT_INTR_INFO, 1797 TIMER_VECTOR | 1798 (VMX_INTR_TYPE_EXT_INTR << INTR_INFO_INTR_TYPE_SHIFT) | 1799 INTR_INFO_VALID_MASK); 1800 break; 1801 } 1802 vmx_inc_test_stage(); 1803 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1804 return VMX_TEST_RESUME; 1805 case VMX_EXTINT: 1806 if (vmcs_read(EXI_CONTROLS) & EXI_INTA) { 1807 int vector = vmcs_read(EXI_INTR_INFO) & 0xff; 1808 handle_external_interrupt(vector); 1809 } else { 1810 irq_enable(); 1811 asm volatile ("nop"); 1812 irq_disable(); 1813 } 1814 if (vmx_get_test_stage() >= 2) 1815 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 1816 return VMX_TEST_RESUME; 1817 default: 1818 report(false, "Unknown exit reason, %ld", reason); 1819 print_vmexit_info(); 1820 } 1821 1822 return VMX_TEST_VMEXIT; 1823 } 1824 1825 static int dbgctls_init(struct vmcs *vmcs) 1826 { 1827 u64 dr7 = 0x402; 1828 u64 zero = 0; 1829 1830 msr_bmp_init(); 1831 asm volatile( 1832 "mov %0,%%dr0\n\t" 1833 "mov %0,%%dr1\n\t" 1834 "mov %0,%%dr2\n\t" 1835 "mov %1,%%dr7\n\t" 1836 : : "r" (zero), "r" (dr7)); 1837 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1838 vmcs_write(GUEST_DR7, 0x404); 1839 vmcs_write(GUEST_DEBUGCTL, 0x2); 1840 1841 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 1842 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_SAVE_DBGCTLS); 1843 1844 return VMX_TEST_START; 1845 } 1846 1847 static void dbgctls_main(void) 1848 { 1849 u64 dr7, debugctl; 1850 1851 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1852 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1853 /* Commented out: KVM does not support DEBUGCTL so far */ 1854 (void)debugctl; 1855 report(dr7 == 0x404, "Load debug controls" /* && debugctl == 0x2 */); 1856 1857 dr7 = 0x408; 1858 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1859 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1860 1861 vmx_set_test_stage(0); 1862 vmcall(); 1863 report(vmx_get_test_stage() == 1, "Save debug controls"); 1864 1865 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS || 1866 ctrl_exit_rev.set & EXI_SAVE_DBGCTLS) { 1867 printf("\tDebug controls are always loaded/saved\n"); 1868 return; 1869 } 1870 vmx_set_test_stage(2); 1871 vmcall(); 1872 1873 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1874 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1875 /* Commented out: KVM does not support DEBUGCTL so far */ 1876 (void)debugctl; 1877 report(dr7 == 0x402, 1878 "Guest=host debug controls" /* && debugctl == 0x1 */); 1879 1880 dr7 = 0x408; 1881 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1882 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1883 1884 vmx_set_test_stage(3); 1885 vmcall(); 1886 report(vmx_get_test_stage() == 4, "Don't save debug controls"); 1887 } 1888 1889 static int dbgctls_exit_handler(void) 1890 { 1891 unsigned int reason = vmcs_read(EXI_REASON) & 0xff; 1892 u32 insn_len = vmcs_read(EXI_INST_LEN); 1893 u64 guest_rip = vmcs_read(GUEST_RIP); 1894 u64 dr7, debugctl; 1895 1896 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1897 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1898 1899 switch (reason) { 1900 case VMX_VMCALL: 1901 switch (vmx_get_test_stage()) { 1902 case 0: 1903 if (dr7 == 0x400 && debugctl == 0 && 1904 vmcs_read(GUEST_DR7) == 0x408 /* && 1905 Commented out: KVM does not support DEBUGCTL so far 1906 vmcs_read(GUEST_DEBUGCTL) == 0x3 */) 1907 vmx_inc_test_stage(); 1908 break; 1909 case 2: 1910 dr7 = 0x402; 1911 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1912 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1913 vmcs_write(GUEST_DR7, 0x404); 1914 vmcs_write(GUEST_DEBUGCTL, 0x2); 1915 1916 vmcs_write(ENT_CONTROLS, 1917 vmcs_read(ENT_CONTROLS) & ~ENT_LOAD_DBGCTLS); 1918 vmcs_write(EXI_CONTROLS, 1919 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_DBGCTLS); 1920 break; 1921 case 3: 1922 if (dr7 == 0x400 && debugctl == 0 && 1923 vmcs_read(GUEST_DR7) == 0x404 /* && 1924 Commented out: KVM does not support DEBUGCTL so far 1925 vmcs_read(GUEST_DEBUGCTL) == 0x2 */) 1926 vmx_inc_test_stage(); 1927 break; 1928 } 1929 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1930 return VMX_TEST_RESUME; 1931 default: 1932 report(false, "Unknown exit reason, %d", reason); 1933 print_vmexit_info(); 1934 } 1935 return VMX_TEST_VMEXIT; 1936 } 1937 1938 struct vmx_msr_entry { 1939 u32 index; 1940 u32 reserved; 1941 u64 value; 1942 } __attribute__((packed)); 1943 1944 #define MSR_MAGIC 0x31415926 1945 struct vmx_msr_entry *exit_msr_store, *entry_msr_load, *exit_msr_load; 1946 1947 static int msr_switch_init(struct vmcs *vmcs) 1948 { 1949 msr_bmp_init(); 1950 exit_msr_store = alloc_page(); 1951 exit_msr_load = alloc_page(); 1952 entry_msr_load = alloc_page(); 1953 entry_msr_load[0].index = MSR_KERNEL_GS_BASE; 1954 entry_msr_load[0].value = MSR_MAGIC; 1955 1956 vmx_set_test_stage(1); 1957 vmcs_write(ENT_MSR_LD_CNT, 1); 1958 vmcs_write(ENTER_MSR_LD_ADDR, (u64)entry_msr_load); 1959 vmcs_write(EXI_MSR_ST_CNT, 1); 1960 vmcs_write(EXIT_MSR_ST_ADDR, (u64)exit_msr_store); 1961 vmcs_write(EXI_MSR_LD_CNT, 1); 1962 vmcs_write(EXIT_MSR_LD_ADDR, (u64)exit_msr_load); 1963 return VMX_TEST_START; 1964 } 1965 1966 static void msr_switch_main(void) 1967 { 1968 if (vmx_get_test_stage() == 1) { 1969 report(rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC, 1970 "VM entry MSR load"); 1971 vmx_set_test_stage(2); 1972 wrmsr(MSR_KERNEL_GS_BASE, MSR_MAGIC + 1); 1973 exit_msr_store[0].index = MSR_KERNEL_GS_BASE; 1974 exit_msr_load[0].index = MSR_KERNEL_GS_BASE; 1975 exit_msr_load[0].value = MSR_MAGIC + 2; 1976 } 1977 vmcall(); 1978 } 1979 1980 static int msr_switch_exit_handler(void) 1981 { 1982 ulong reason; 1983 1984 reason = vmcs_read(EXI_REASON); 1985 if (reason == VMX_VMCALL && vmx_get_test_stage() == 2) { 1986 report(exit_msr_store[0].value == MSR_MAGIC + 1, 1987 "VM exit MSR store"); 1988 report(rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC + 2, 1989 "VM exit MSR load"); 1990 vmx_set_test_stage(3); 1991 entry_msr_load[0].index = MSR_FS_BASE; 1992 return VMX_TEST_RESUME; 1993 } 1994 printf("ERROR %s: unexpected stage=%u or reason=%lu\n", 1995 __func__, vmx_get_test_stage(), reason); 1996 return VMX_TEST_EXIT; 1997 } 1998 1999 static int msr_switch_entry_failure(struct vmentry_result *result) 2000 { 2001 if (result->vm_fail) { 2002 printf("ERROR %s: VM-Fail on %s\n", __func__, result->instr); 2003 return VMX_TEST_EXIT; 2004 } 2005 2006 if (result->exit_reason.failed_vmentry && 2007 result->exit_reason.basic == VMX_FAIL_MSR && 2008 vmx_get_test_stage() == 3) { 2009 report(vmcs_read(EXI_QUALIFICATION) == 1, 2010 "VM entry MSR load: try to load FS_BASE"); 2011 return VMX_TEST_VMEXIT; 2012 } 2013 printf("ERROR %s: unexpected stage=%u or reason=%x\n", 2014 __func__, vmx_get_test_stage(), result->exit_reason.full); 2015 return VMX_TEST_EXIT; 2016 } 2017 2018 static int vmmcall_init(struct vmcs *vmcs) 2019 { 2020 vmcs_write(EXC_BITMAP, 1 << UD_VECTOR); 2021 return VMX_TEST_START; 2022 } 2023 2024 static void vmmcall_main(void) 2025 { 2026 asm volatile( 2027 "mov $0xABCD, %%rax\n\t" 2028 "vmmcall\n\t" 2029 ::: "rax"); 2030 2031 report(0, "VMMCALL"); 2032 } 2033 2034 static int vmmcall_exit_handler(void) 2035 { 2036 ulong reason; 2037 2038 reason = vmcs_read(EXI_REASON); 2039 switch (reason) { 2040 case VMX_VMCALL: 2041 printf("here\n"); 2042 report(0, "VMMCALL triggers #UD"); 2043 break; 2044 case VMX_EXC_NMI: 2045 report((vmcs_read(EXI_INTR_INFO) & 0xff) == UD_VECTOR, 2046 "VMMCALL triggers #UD"); 2047 break; 2048 default: 2049 report(false, "Unknown exit reason, %ld", reason); 2050 print_vmexit_info(); 2051 } 2052 2053 return VMX_TEST_VMEXIT; 2054 } 2055 2056 static int disable_rdtscp_init(struct vmcs *vmcs) 2057 { 2058 u32 ctrl_cpu1; 2059 2060 if (ctrl_cpu_rev[0].clr & CPU_SECONDARY) { 2061 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 2062 ctrl_cpu1 &= ~CPU_RDTSCP; 2063 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 2064 } 2065 2066 return VMX_TEST_START; 2067 } 2068 2069 static void disable_rdtscp_ud_handler(struct ex_regs *regs) 2070 { 2071 switch (vmx_get_test_stage()) { 2072 case 0: 2073 report(true, "RDTSCP triggers #UD"); 2074 vmx_inc_test_stage(); 2075 regs->rip += 3; 2076 break; 2077 case 2: 2078 report(true, "RDPID triggers #UD"); 2079 vmx_inc_test_stage(); 2080 regs->rip += 4; 2081 break; 2082 } 2083 return; 2084 2085 } 2086 2087 static void disable_rdtscp_main(void) 2088 { 2089 /* Test that #UD is properly injected in L2. */ 2090 handle_exception(UD_VECTOR, disable_rdtscp_ud_handler); 2091 2092 vmx_set_test_stage(0); 2093 asm volatile("rdtscp" : : : "eax", "ecx", "edx"); 2094 vmcall(); 2095 asm volatile(".byte 0xf3, 0x0f, 0xc7, 0xf8" : : : "eax"); 2096 2097 handle_exception(UD_VECTOR, 0); 2098 vmcall(); 2099 } 2100 2101 static int disable_rdtscp_exit_handler(void) 2102 { 2103 unsigned int reason = vmcs_read(EXI_REASON) & 0xff; 2104 2105 switch (reason) { 2106 case VMX_VMCALL: 2107 switch (vmx_get_test_stage()) { 2108 case 0: 2109 report(false, "RDTSCP triggers #UD"); 2110 vmx_inc_test_stage(); 2111 /* fallthrough */ 2112 case 1: 2113 vmx_inc_test_stage(); 2114 vmcs_write(GUEST_RIP, vmcs_read(GUEST_RIP) + 3); 2115 return VMX_TEST_RESUME; 2116 case 2: 2117 report(false, "RDPID triggers #UD"); 2118 break; 2119 } 2120 break; 2121 2122 default: 2123 report(false, "Unknown exit reason, %d", reason); 2124 print_vmexit_info(); 2125 } 2126 return VMX_TEST_VMEXIT; 2127 } 2128 2129 static int int3_init(struct vmcs *vmcs) 2130 { 2131 vmcs_write(EXC_BITMAP, ~0u); 2132 return VMX_TEST_START; 2133 } 2134 2135 static void int3_guest_main(void) 2136 { 2137 asm volatile ("int3"); 2138 } 2139 2140 static int int3_exit_handler(void) 2141 { 2142 u32 reason = vmcs_read(EXI_REASON); 2143 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2144 2145 report(reason == VMX_EXC_NMI && (intr_info & INTR_INFO_VALID_MASK) && 2146 (intr_info & INTR_INFO_VECTOR_MASK) == BP_VECTOR && 2147 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2148 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION, 2149 "L1 intercepts #BP"); 2150 2151 return VMX_TEST_VMEXIT; 2152 } 2153 2154 static int into_init(struct vmcs *vmcs) 2155 { 2156 vmcs_write(EXC_BITMAP, ~0u); 2157 return VMX_TEST_START; 2158 } 2159 2160 static void into_guest_main(void) 2161 { 2162 struct far_pointer32 fp = { 2163 .offset = (uintptr_t)&&into, 2164 .selector = KERNEL_CS32, 2165 }; 2166 register uintptr_t rsp asm("rsp"); 2167 2168 if (fp.offset != (uintptr_t)&&into) { 2169 printf("Code address too high.\n"); 2170 return; 2171 } 2172 if ((u32)rsp != rsp) { 2173 printf("Stack address too high.\n"); 2174 return; 2175 } 2176 2177 asm goto ("lcall *%0" : : "m" (fp) : "rax" : into); 2178 return; 2179 into: 2180 asm volatile (".code32;" 2181 "movl $0x7fffffff, %eax;" 2182 "addl %eax, %eax;" 2183 "into;" 2184 "lret;" 2185 ".code64"); 2186 __builtin_unreachable(); 2187 } 2188 2189 static int into_exit_handler(void) 2190 { 2191 u32 reason = vmcs_read(EXI_REASON); 2192 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2193 2194 report(reason == VMX_EXC_NMI && (intr_info & INTR_INFO_VALID_MASK) && 2195 (intr_info & INTR_INFO_VECTOR_MASK) == OF_VECTOR && 2196 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2197 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION, 2198 "L1 intercepts #OF"); 2199 2200 return VMX_TEST_VMEXIT; 2201 } 2202 2203 static void exit_monitor_from_l2_main(void) 2204 { 2205 printf("Calling exit(0) from l2...\n"); 2206 exit(0); 2207 } 2208 2209 static int exit_monitor_from_l2_handler(void) 2210 { 2211 report(false, "The guest should have killed the VMM"); 2212 return VMX_TEST_EXIT; 2213 } 2214 2215 static void assert_exit_reason(u64 expected) 2216 { 2217 u64 actual = vmcs_read(EXI_REASON); 2218 2219 TEST_ASSERT_EQ_MSG(expected, actual, "Expected %s, got %s.", 2220 exit_reason_description(expected), 2221 exit_reason_description(actual)); 2222 } 2223 2224 static void skip_exit_insn(void) 2225 { 2226 u64 guest_rip = vmcs_read(GUEST_RIP); 2227 u32 insn_len = vmcs_read(EXI_INST_LEN); 2228 vmcs_write(GUEST_RIP, guest_rip + insn_len); 2229 } 2230 2231 static void skip_exit_vmcall(void) 2232 { 2233 assert_exit_reason(VMX_VMCALL); 2234 skip_exit_insn(); 2235 } 2236 2237 static void v2_null_test_guest(void) 2238 { 2239 } 2240 2241 static void v2_null_test(void) 2242 { 2243 test_set_guest(v2_null_test_guest); 2244 enter_guest(); 2245 report(1, __func__); 2246 } 2247 2248 static void v2_multiple_entries_test_guest(void) 2249 { 2250 vmx_set_test_stage(1); 2251 vmcall(); 2252 vmx_set_test_stage(2); 2253 } 2254 2255 static void v2_multiple_entries_test(void) 2256 { 2257 test_set_guest(v2_multiple_entries_test_guest); 2258 enter_guest(); 2259 TEST_ASSERT_EQ(vmx_get_test_stage(), 1); 2260 skip_exit_vmcall(); 2261 enter_guest(); 2262 TEST_ASSERT_EQ(vmx_get_test_stage(), 2); 2263 report(1, __func__); 2264 } 2265 2266 static int fixture_test_data = 1; 2267 2268 static void fixture_test_teardown(void *data) 2269 { 2270 *((int *) data) = 1; 2271 } 2272 2273 static void fixture_test_guest(void) 2274 { 2275 fixture_test_data++; 2276 } 2277 2278 2279 static void fixture_test_setup(void) 2280 { 2281 TEST_ASSERT_EQ_MSG(1, fixture_test_data, 2282 "fixture_test_teardown didn't run?!"); 2283 fixture_test_data = 2; 2284 test_add_teardown(fixture_test_teardown, &fixture_test_data); 2285 test_set_guest(fixture_test_guest); 2286 } 2287 2288 static void fixture_test_case1(void) 2289 { 2290 fixture_test_setup(); 2291 TEST_ASSERT_EQ(2, fixture_test_data); 2292 enter_guest(); 2293 TEST_ASSERT_EQ(3, fixture_test_data); 2294 report(1, __func__); 2295 } 2296 2297 static void fixture_test_case2(void) 2298 { 2299 fixture_test_setup(); 2300 TEST_ASSERT_EQ(2, fixture_test_data); 2301 enter_guest(); 2302 TEST_ASSERT_EQ(3, fixture_test_data); 2303 report(1, __func__); 2304 } 2305 2306 enum ept_access_op { 2307 OP_READ, 2308 OP_WRITE, 2309 OP_EXEC, 2310 OP_FLUSH_TLB, 2311 OP_EXIT, 2312 }; 2313 2314 static struct ept_access_test_data { 2315 unsigned long gpa; 2316 unsigned long *gva; 2317 unsigned long hpa; 2318 unsigned long *hva; 2319 enum ept_access_op op; 2320 } ept_access_test_data; 2321 2322 extern unsigned char ret42_start; 2323 extern unsigned char ret42_end; 2324 2325 /* Returns 42. */ 2326 asm( 2327 ".align 64\n" 2328 "ret42_start:\n" 2329 "mov $42, %eax\n" 2330 "ret\n" 2331 "ret42_end:\n" 2332 ); 2333 2334 static void 2335 diagnose_ept_violation_qual(u64 expected, u64 actual) 2336 { 2337 2338 #define DIAGNOSE(flag) \ 2339 do { \ 2340 if ((expected & flag) != (actual & flag)) \ 2341 printf(#flag " %sexpected\n", \ 2342 (expected & flag) ? "" : "un"); \ 2343 } while (0) 2344 2345 DIAGNOSE(EPT_VLT_RD); 2346 DIAGNOSE(EPT_VLT_WR); 2347 DIAGNOSE(EPT_VLT_FETCH); 2348 DIAGNOSE(EPT_VLT_PERM_RD); 2349 DIAGNOSE(EPT_VLT_PERM_WR); 2350 DIAGNOSE(EPT_VLT_PERM_EX); 2351 DIAGNOSE(EPT_VLT_LADDR_VLD); 2352 DIAGNOSE(EPT_VLT_PADDR); 2353 2354 #undef DIAGNOSE 2355 } 2356 2357 static void do_ept_access_op(enum ept_access_op op) 2358 { 2359 ept_access_test_data.op = op; 2360 enter_guest(); 2361 } 2362 2363 /* 2364 * Force the guest to flush its TLB (i.e., flush gva -> gpa mappings). Only 2365 * needed by tests that modify guest PTEs. 2366 */ 2367 static void ept_access_test_guest_flush_tlb(void) 2368 { 2369 do_ept_access_op(OP_FLUSH_TLB); 2370 skip_exit_vmcall(); 2371 } 2372 2373 /* 2374 * Modifies the EPT entry at @level in the mapping of @gpa. First clears the 2375 * bits in @clear then sets the bits in @set. @mkhuge transforms the entry into 2376 * a huge page. 2377 */ 2378 static unsigned long ept_twiddle(unsigned long gpa, bool mkhuge, int level, 2379 unsigned long clear, unsigned long set) 2380 { 2381 struct ept_access_test_data *data = &ept_access_test_data; 2382 unsigned long orig_pte; 2383 unsigned long pte; 2384 2385 /* Screw with the mapping at the requested level. */ 2386 TEST_ASSERT(get_ept_pte(pml4, gpa, level, &orig_pte)); 2387 pte = orig_pte; 2388 if (mkhuge) 2389 pte = (orig_pte & ~EPT_ADDR_MASK) | data->hpa | EPT_LARGE_PAGE; 2390 else 2391 pte = orig_pte; 2392 pte = (pte & ~clear) | set; 2393 set_ept_pte(pml4, gpa, level, pte); 2394 ept_sync(INVEPT_SINGLE, eptp); 2395 2396 return orig_pte; 2397 } 2398 2399 static void ept_untwiddle(unsigned long gpa, int level, unsigned long orig_pte) 2400 { 2401 set_ept_pte(pml4, gpa, level, orig_pte); 2402 ept_sync(INVEPT_SINGLE, eptp); 2403 } 2404 2405 static void do_ept_violation(bool leaf, enum ept_access_op op, 2406 u64 expected_qual, u64 expected_paddr) 2407 { 2408 u64 qual; 2409 2410 /* Try the access and observe the violation. */ 2411 do_ept_access_op(op); 2412 2413 assert_exit_reason(VMX_EPT_VIOLATION); 2414 2415 qual = vmcs_read(EXI_QUALIFICATION); 2416 2417 /* Mask undefined bits (which may later be defined in certain cases). */ 2418 qual &= ~(EPT_VLT_GUEST_USER | EPT_VLT_GUEST_RW | EPT_VLT_GUEST_EX | 2419 EPT_VLT_PERM_USER_EX); 2420 2421 diagnose_ept_violation_qual(expected_qual, qual); 2422 TEST_EXPECT_EQ(expected_qual, qual); 2423 2424 #if 0 2425 /* Disable for now otherwise every test will fail */ 2426 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2427 (unsigned long) ( 2428 op == OP_EXEC ? data->gva + 1 : data->gva)); 2429 #endif 2430 /* 2431 * TODO: tests that probe expected_paddr in pages other than the one at 2432 * the beginning of the 1g region. 2433 */ 2434 TEST_EXPECT_EQ(vmcs_read(INFO_PHYS_ADDR), expected_paddr); 2435 } 2436 2437 static void 2438 ept_violation_at_level_mkhuge(bool mkhuge, int level, unsigned long clear, 2439 unsigned long set, enum ept_access_op op, 2440 u64 expected_qual) 2441 { 2442 struct ept_access_test_data *data = &ept_access_test_data; 2443 unsigned long orig_pte; 2444 2445 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2446 2447 do_ept_violation(level == 1 || mkhuge, op, expected_qual, 2448 op == OP_EXEC ? data->gpa + sizeof(unsigned long) : 2449 data->gpa); 2450 2451 /* Fix the violation and resume the op loop. */ 2452 ept_untwiddle(data->gpa, level, orig_pte); 2453 enter_guest(); 2454 skip_exit_vmcall(); 2455 } 2456 2457 static void 2458 ept_violation_at_level(int level, unsigned long clear, unsigned long set, 2459 enum ept_access_op op, u64 expected_qual) 2460 { 2461 ept_violation_at_level_mkhuge(false, level, clear, set, op, 2462 expected_qual); 2463 if (ept_huge_pages_supported(level)) 2464 ept_violation_at_level_mkhuge(true, level, clear, set, op, 2465 expected_qual); 2466 } 2467 2468 static void ept_violation(unsigned long clear, unsigned long set, 2469 enum ept_access_op op, u64 expected_qual) 2470 { 2471 ept_violation_at_level(1, clear, set, op, expected_qual); 2472 ept_violation_at_level(2, clear, set, op, expected_qual); 2473 ept_violation_at_level(3, clear, set, op, expected_qual); 2474 ept_violation_at_level(4, clear, set, op, expected_qual); 2475 } 2476 2477 static void ept_access_violation(unsigned long access, enum ept_access_op op, 2478 u64 expected_qual) 2479 { 2480 ept_violation(EPT_PRESENT, access, op, 2481 expected_qual | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2482 } 2483 2484 /* 2485 * For translations that don't involve a GVA, that is physical address (paddr) 2486 * accesses, EPT violations don't set the flag EPT_VLT_PADDR. For a typical 2487 * guest memory access, the hardware does GVA -> GPA -> HPA. However, certain 2488 * translations don't involve GVAs, such as when the hardware does the guest 2489 * page table walk. For example, in translating GVA_1 -> GPA_1, the guest MMU 2490 * might try to set an A bit on a guest PTE. If the GPA_2 that the PTE resides 2491 * on isn't present in the EPT, then the EPT violation will be for GPA_2 and 2492 * the EPT_VLT_PADDR bit will be clear in the exit qualification. 2493 * 2494 * Note that paddr violations can also be triggered by loading PAE page tables 2495 * with wonky addresses. We don't test that yet. 2496 * 2497 * This function modifies the EPT entry that maps the GPA that the guest page 2498 * table entry mapping ept_access_test_data.gva resides on. 2499 * 2500 * @ept_access EPT permissions to set. Other permissions are cleared. 2501 * 2502 * @pte_ad Set the A/D bits on the guest PTE accordingly. 2503 * 2504 * @op Guest operation to perform with 2505 * ept_access_test_data.gva. 2506 * 2507 * @expect_violation 2508 * Is a violation expected during the paddr access? 2509 * 2510 * @expected_qual Expected qualification for the EPT violation. 2511 * EPT_VLT_PADDR should be clear. 2512 */ 2513 static void ept_access_paddr(unsigned long ept_access, unsigned long pte_ad, 2514 enum ept_access_op op, bool expect_violation, 2515 u64 expected_qual) 2516 { 2517 struct ept_access_test_data *data = &ept_access_test_data; 2518 unsigned long *ptep; 2519 unsigned long gpa; 2520 unsigned long orig_epte; 2521 unsigned long epte; 2522 int i; 2523 2524 /* Modify the guest PTE mapping data->gva according to @pte_ad. */ 2525 ptep = get_pte_level(current_page_table(), data->gva, /*level=*/1); 2526 TEST_ASSERT(ptep); 2527 TEST_ASSERT_EQ(*ptep & PT_ADDR_MASK, data->gpa); 2528 *ptep = (*ptep & ~PT_AD_MASK) | pte_ad; 2529 ept_access_test_guest_flush_tlb(); 2530 2531 /* 2532 * Now modify the access bits on the EPT entry for the GPA that the 2533 * guest PTE resides on. Note that by modifying a single EPT entry, 2534 * we're potentially affecting 512 guest PTEs. However, we've carefully 2535 * constructed our test such that those other 511 PTEs aren't used by 2536 * the guest: data->gva is at the beginning of a 1G huge page, thus the 2537 * PTE we're modifying is at the beginning of a 4K page and the 2538 * following 511 entires are also under our control (and not touched by 2539 * the guest). 2540 */ 2541 gpa = virt_to_phys(ptep); 2542 TEST_ASSERT_EQ(gpa & ~PAGE_MASK, 0); 2543 /* 2544 * Make sure the guest page table page is mapped with a 4K EPT entry, 2545 * otherwise our level=1 twiddling below will fail. We use the 2546 * identity map (gpa = gpa) since page tables are shared with the host. 2547 */ 2548 install_ept(pml4, gpa, gpa, EPT_PRESENT); 2549 orig_epte = ept_twiddle(gpa, /*mkhuge=*/0, /*level=*/1, 2550 /*clear=*/EPT_PRESENT, /*set=*/ept_access); 2551 2552 if (expect_violation) { 2553 do_ept_violation(/*leaf=*/true, op, 2554 expected_qual | EPT_VLT_LADDR_VLD, gpa); 2555 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2556 do_ept_access_op(op); 2557 } else { 2558 do_ept_access_op(op); 2559 if (ept_ad_enabled()) { 2560 for (i = EPT_PAGE_LEVEL; i > 0; i--) { 2561 TEST_ASSERT(get_ept_pte(pml4, gpa, i, &epte)); 2562 TEST_ASSERT(epte & EPT_ACCESS_FLAG); 2563 if (i == 1) 2564 TEST_ASSERT(epte & EPT_DIRTY_FLAG); 2565 else 2566 TEST_ASSERT_EQ(epte & EPT_DIRTY_FLAG, 0); 2567 } 2568 } 2569 2570 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2571 } 2572 2573 TEST_ASSERT(*ptep & PT_ACCESSED_MASK); 2574 if ((pte_ad & PT_DIRTY_MASK) || op == OP_WRITE) 2575 TEST_ASSERT(*ptep & PT_DIRTY_MASK); 2576 2577 skip_exit_vmcall(); 2578 } 2579 2580 static void ept_access_allowed_paddr(unsigned long ept_access, 2581 unsigned long pte_ad, 2582 enum ept_access_op op) 2583 { 2584 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/false, 2585 /*expected_qual=*/-1); 2586 } 2587 2588 static void ept_access_violation_paddr(unsigned long ept_access, 2589 unsigned long pte_ad, 2590 enum ept_access_op op, 2591 u64 expected_qual) 2592 { 2593 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/true, 2594 expected_qual); 2595 } 2596 2597 2598 static void ept_allowed_at_level_mkhuge(bool mkhuge, int level, 2599 unsigned long clear, 2600 unsigned long set, 2601 enum ept_access_op op) 2602 { 2603 struct ept_access_test_data *data = &ept_access_test_data; 2604 unsigned long orig_pte; 2605 2606 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2607 2608 /* No violation. Should proceed to vmcall. */ 2609 do_ept_access_op(op); 2610 skip_exit_vmcall(); 2611 2612 ept_untwiddle(data->gpa, level, orig_pte); 2613 } 2614 2615 static void ept_allowed_at_level(int level, unsigned long clear, 2616 unsigned long set, enum ept_access_op op) 2617 { 2618 ept_allowed_at_level_mkhuge(false, level, clear, set, op); 2619 if (ept_huge_pages_supported(level)) 2620 ept_allowed_at_level_mkhuge(true, level, clear, set, op); 2621 } 2622 2623 static void ept_allowed(unsigned long clear, unsigned long set, 2624 enum ept_access_op op) 2625 { 2626 ept_allowed_at_level(1, clear, set, op); 2627 ept_allowed_at_level(2, clear, set, op); 2628 ept_allowed_at_level(3, clear, set, op); 2629 ept_allowed_at_level(4, clear, set, op); 2630 } 2631 2632 static void ept_ignored_bit(int bit) 2633 { 2634 /* Set the bit. */ 2635 ept_allowed(0, 1ul << bit, OP_READ); 2636 ept_allowed(0, 1ul << bit, OP_WRITE); 2637 ept_allowed(0, 1ul << bit, OP_EXEC); 2638 2639 /* Clear the bit. */ 2640 ept_allowed(1ul << bit, 0, OP_READ); 2641 ept_allowed(1ul << bit, 0, OP_WRITE); 2642 ept_allowed(1ul << bit, 0, OP_EXEC); 2643 } 2644 2645 static void ept_access_allowed(unsigned long access, enum ept_access_op op) 2646 { 2647 ept_allowed(EPT_PRESENT, access, op); 2648 } 2649 2650 2651 static void ept_misconfig_at_level_mkhuge_op(bool mkhuge, int level, 2652 unsigned long clear, 2653 unsigned long set, 2654 enum ept_access_op op) 2655 { 2656 struct ept_access_test_data *data = &ept_access_test_data; 2657 unsigned long orig_pte; 2658 2659 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2660 2661 do_ept_access_op(op); 2662 assert_exit_reason(VMX_EPT_MISCONFIG); 2663 2664 /* Intel 27.2.1, "For all other VM exits, this field is cleared." */ 2665 #if 0 2666 /* broken: */ 2667 TEST_EXPECT_EQ_MSG(vmcs_read(EXI_QUALIFICATION), 0); 2668 #endif 2669 #if 0 2670 /* 2671 * broken: 2672 * According to description of exit qual for EPT violation, 2673 * EPT_VLT_LADDR_VLD indicates if GUEST_LINEAR_ADDRESS is valid. 2674 * However, I can't find anything that says GUEST_LINEAR_ADDRESS ought 2675 * to be set for msiconfig. 2676 */ 2677 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2678 (unsigned long) ( 2679 op == OP_EXEC ? data->gva + 1 : data->gva)); 2680 #endif 2681 2682 /* Fix the violation and resume the op loop. */ 2683 ept_untwiddle(data->gpa, level, orig_pte); 2684 enter_guest(); 2685 skip_exit_vmcall(); 2686 } 2687 2688 static void ept_misconfig_at_level_mkhuge(bool mkhuge, int level, 2689 unsigned long clear, 2690 unsigned long set) 2691 { 2692 /* The op shouldn't matter (read, write, exec), so try them all! */ 2693 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_READ); 2694 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_WRITE); 2695 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_EXEC); 2696 } 2697 2698 static void ept_misconfig_at_level(int level, unsigned long clear, 2699 unsigned long set) 2700 { 2701 ept_misconfig_at_level_mkhuge(false, level, clear, set); 2702 if (ept_huge_pages_supported(level)) 2703 ept_misconfig_at_level_mkhuge(true, level, clear, set); 2704 } 2705 2706 static void ept_misconfig(unsigned long clear, unsigned long set) 2707 { 2708 ept_misconfig_at_level(1, clear, set); 2709 ept_misconfig_at_level(2, clear, set); 2710 ept_misconfig_at_level(3, clear, set); 2711 ept_misconfig_at_level(4, clear, set); 2712 } 2713 2714 static void ept_access_misconfig(unsigned long access) 2715 { 2716 ept_misconfig(EPT_PRESENT, access); 2717 } 2718 2719 static void ept_reserved_bit_at_level_nohuge(int level, int bit) 2720 { 2721 /* Setting the bit causes a misconfig. */ 2722 ept_misconfig_at_level_mkhuge(false, level, 0, 1ul << bit); 2723 2724 /* Making the entry non-present turns reserved bits into ignored. */ 2725 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2726 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2727 } 2728 2729 static void ept_reserved_bit_at_level_huge(int level, int bit) 2730 { 2731 /* Setting the bit causes a misconfig. */ 2732 ept_misconfig_at_level_mkhuge(true, level, 0, 1ul << bit); 2733 2734 /* Making the entry non-present turns reserved bits into ignored. */ 2735 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2736 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2737 } 2738 2739 static void ept_reserved_bit_at_level(int level, int bit) 2740 { 2741 /* Setting the bit causes a misconfig. */ 2742 ept_misconfig_at_level(level, 0, 1ul << bit); 2743 2744 /* Making the entry non-present turns reserved bits into ignored. */ 2745 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2746 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2747 } 2748 2749 static void ept_reserved_bit(int bit) 2750 { 2751 ept_reserved_bit_at_level(1, bit); 2752 ept_reserved_bit_at_level(2, bit); 2753 ept_reserved_bit_at_level(3, bit); 2754 ept_reserved_bit_at_level(4, bit); 2755 } 2756 2757 #define PAGE_2M_ORDER 9 2758 #define PAGE_1G_ORDER 18 2759 2760 static void *get_1g_page(void) 2761 { 2762 static void *alloc; 2763 2764 if (!alloc) 2765 alloc = alloc_pages(PAGE_1G_ORDER); 2766 return alloc; 2767 } 2768 2769 static void ept_access_test_teardown(void *unused) 2770 { 2771 /* Exit the guest cleanly. */ 2772 do_ept_access_op(OP_EXIT); 2773 } 2774 2775 static void ept_access_test_guest(void) 2776 { 2777 struct ept_access_test_data *data = &ept_access_test_data; 2778 int (*code)(void) = (int (*)(void)) &data->gva[1]; 2779 2780 while (true) { 2781 switch (data->op) { 2782 case OP_READ: 2783 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_1); 2784 break; 2785 case OP_WRITE: 2786 *data->gva = MAGIC_VAL_2; 2787 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_2); 2788 *data->gva = MAGIC_VAL_1; 2789 break; 2790 case OP_EXEC: 2791 TEST_ASSERT_EQ(42, code()); 2792 break; 2793 case OP_FLUSH_TLB: 2794 write_cr3(read_cr3()); 2795 break; 2796 case OP_EXIT: 2797 return; 2798 default: 2799 TEST_ASSERT_MSG(false, "Unknown op %d", data->op); 2800 } 2801 vmcall(); 2802 } 2803 } 2804 2805 static void ept_access_test_setup(void) 2806 { 2807 struct ept_access_test_data *data = &ept_access_test_data; 2808 unsigned long npages = 1ul << PAGE_1G_ORDER; 2809 unsigned long size = npages * PAGE_SIZE; 2810 unsigned long *page_table = current_page_table(); 2811 unsigned long pte; 2812 2813 if (setup_ept(false)) 2814 test_skip("EPT not supported"); 2815 2816 /* We use data->gpa = 1 << 39 so that test data has a separate pml4 entry */ 2817 if (cpuid_maxphyaddr() < 40) 2818 test_skip("Test needs MAXPHYADDR >= 40"); 2819 2820 test_set_guest(ept_access_test_guest); 2821 test_add_teardown(ept_access_test_teardown, NULL); 2822 2823 data->hva = get_1g_page(); 2824 TEST_ASSERT(data->hva); 2825 data->hpa = virt_to_phys(data->hva); 2826 2827 data->gpa = 1ul << 39; 2828 data->gva = (void *) ALIGN((unsigned long) alloc_vpages(npages * 2), 2829 size); 2830 TEST_ASSERT(!any_present_pages(page_table, data->gva, size)); 2831 install_pages(page_table, data->gpa, size, data->gva); 2832 2833 /* 2834 * Make sure nothing's mapped here so the tests that screw with the 2835 * pml4 entry don't inadvertently break something. 2836 */ 2837 TEST_ASSERT(get_ept_pte(pml4, data->gpa, 4, &pte) && pte == 0); 2838 TEST_ASSERT(get_ept_pte(pml4, data->gpa + size - 1, 4, &pte) && pte == 0); 2839 install_ept(pml4, data->hpa, data->gpa, EPT_PRESENT); 2840 2841 data->hva[0] = MAGIC_VAL_1; 2842 memcpy(&data->hva[1], &ret42_start, &ret42_end - &ret42_start); 2843 } 2844 2845 static void ept_access_test_not_present(void) 2846 { 2847 ept_access_test_setup(); 2848 /* --- */ 2849 ept_access_violation(0, OP_READ, EPT_VLT_RD); 2850 ept_access_violation(0, OP_WRITE, EPT_VLT_WR); 2851 ept_access_violation(0, OP_EXEC, EPT_VLT_FETCH); 2852 } 2853 2854 static void ept_access_test_read_only(void) 2855 { 2856 ept_access_test_setup(); 2857 2858 /* r-- */ 2859 ept_access_allowed(EPT_RA, OP_READ); 2860 ept_access_violation(EPT_RA, OP_WRITE, EPT_VLT_WR | EPT_VLT_PERM_RD); 2861 ept_access_violation(EPT_RA, OP_EXEC, EPT_VLT_FETCH | EPT_VLT_PERM_RD); 2862 } 2863 2864 static void ept_access_test_write_only(void) 2865 { 2866 ept_access_test_setup(); 2867 /* -w- */ 2868 ept_access_misconfig(EPT_WA); 2869 } 2870 2871 static void ept_access_test_read_write(void) 2872 { 2873 ept_access_test_setup(); 2874 /* rw- */ 2875 ept_access_allowed(EPT_RA | EPT_WA, OP_READ); 2876 ept_access_allowed(EPT_RA | EPT_WA, OP_WRITE); 2877 ept_access_violation(EPT_RA | EPT_WA, OP_EXEC, 2878 EPT_VLT_FETCH | EPT_VLT_PERM_RD | EPT_VLT_PERM_WR); 2879 } 2880 2881 2882 static void ept_access_test_execute_only(void) 2883 { 2884 ept_access_test_setup(); 2885 /* --x */ 2886 if (ept_execute_only_supported()) { 2887 ept_access_violation(EPT_EA, OP_READ, 2888 EPT_VLT_RD | EPT_VLT_PERM_EX); 2889 ept_access_violation(EPT_EA, OP_WRITE, 2890 EPT_VLT_WR | EPT_VLT_PERM_EX); 2891 ept_access_allowed(EPT_EA, OP_EXEC); 2892 } else { 2893 ept_access_misconfig(EPT_EA); 2894 } 2895 } 2896 2897 static void ept_access_test_read_execute(void) 2898 { 2899 ept_access_test_setup(); 2900 /* r-x */ 2901 ept_access_allowed(EPT_RA | EPT_EA, OP_READ); 2902 ept_access_violation(EPT_RA | EPT_EA, OP_WRITE, 2903 EPT_VLT_WR | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX); 2904 ept_access_allowed(EPT_RA | EPT_EA, OP_EXEC); 2905 } 2906 2907 static void ept_access_test_write_execute(void) 2908 { 2909 ept_access_test_setup(); 2910 /* -wx */ 2911 ept_access_misconfig(EPT_WA | EPT_EA); 2912 } 2913 2914 static void ept_access_test_read_write_execute(void) 2915 { 2916 ept_access_test_setup(); 2917 /* rwx */ 2918 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_READ); 2919 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_WRITE); 2920 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_EXEC); 2921 } 2922 2923 static void ept_access_test_reserved_bits(void) 2924 { 2925 int i; 2926 int maxphyaddr; 2927 2928 ept_access_test_setup(); 2929 2930 /* Reserved bits above maxphyaddr. */ 2931 maxphyaddr = cpuid_maxphyaddr(); 2932 for (i = maxphyaddr; i <= 51; i++) { 2933 report_prefix_pushf("reserved_bit=%d", i); 2934 ept_reserved_bit(i); 2935 report_prefix_pop(); 2936 } 2937 2938 /* Level-specific reserved bits. */ 2939 ept_reserved_bit_at_level_nohuge(2, 3); 2940 ept_reserved_bit_at_level_nohuge(2, 4); 2941 ept_reserved_bit_at_level_nohuge(2, 5); 2942 ept_reserved_bit_at_level_nohuge(2, 6); 2943 /* 2M alignment. */ 2944 for (i = 12; i < 20; i++) { 2945 report_prefix_pushf("reserved_bit=%d", i); 2946 ept_reserved_bit_at_level_huge(2, i); 2947 report_prefix_pop(); 2948 } 2949 ept_reserved_bit_at_level_nohuge(3, 3); 2950 ept_reserved_bit_at_level_nohuge(3, 4); 2951 ept_reserved_bit_at_level_nohuge(3, 5); 2952 ept_reserved_bit_at_level_nohuge(3, 6); 2953 /* 1G alignment. */ 2954 for (i = 12; i < 29; i++) { 2955 report_prefix_pushf("reserved_bit=%d", i); 2956 ept_reserved_bit_at_level_huge(3, i); 2957 report_prefix_pop(); 2958 } 2959 ept_reserved_bit_at_level(4, 3); 2960 ept_reserved_bit_at_level(4, 4); 2961 ept_reserved_bit_at_level(4, 5); 2962 ept_reserved_bit_at_level(4, 6); 2963 ept_reserved_bit_at_level(4, 7); 2964 } 2965 2966 static void ept_access_test_ignored_bits(void) 2967 { 2968 ept_access_test_setup(); 2969 /* 2970 * Bits ignored at every level. Bits 8 and 9 (A and D) are ignored as 2971 * far as translation is concerned even if AD bits are enabled in the 2972 * EPTP. Bit 63 is ignored because "EPT-violation #VE" VM-execution 2973 * control is 0. 2974 */ 2975 ept_ignored_bit(8); 2976 ept_ignored_bit(9); 2977 ept_ignored_bit(10); 2978 ept_ignored_bit(11); 2979 ept_ignored_bit(52); 2980 ept_ignored_bit(53); 2981 ept_ignored_bit(54); 2982 ept_ignored_bit(55); 2983 ept_ignored_bit(56); 2984 ept_ignored_bit(57); 2985 ept_ignored_bit(58); 2986 ept_ignored_bit(59); 2987 ept_ignored_bit(60); 2988 ept_ignored_bit(61); 2989 ept_ignored_bit(62); 2990 ept_ignored_bit(63); 2991 } 2992 2993 static void ept_access_test_paddr_not_present_ad_disabled(void) 2994 { 2995 ept_access_test_setup(); 2996 ept_disable_ad_bits(); 2997 2998 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, EPT_VLT_RD); 2999 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, EPT_VLT_RD); 3000 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, EPT_VLT_RD); 3001 } 3002 3003 static void ept_access_test_paddr_not_present_ad_enabled(void) 3004 { 3005 u64 qual = EPT_VLT_RD | EPT_VLT_WR; 3006 3007 ept_access_test_setup(); 3008 ept_enable_ad_bits_or_skip_test(); 3009 3010 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, qual); 3011 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, qual); 3012 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, qual); 3013 } 3014 3015 static void ept_access_test_paddr_read_only_ad_disabled(void) 3016 { 3017 /* 3018 * When EPT AD bits are disabled, all accesses to guest paging 3019 * structures are reported separately as a read and (after 3020 * translation of the GPA to host physical address) a read+write 3021 * if the A/D bits have to be set. 3022 */ 3023 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 3024 3025 ept_access_test_setup(); 3026 ept_disable_ad_bits(); 3027 3028 /* Can't update A bit, so all accesses fail. */ 3029 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 3030 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 3031 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 3032 /* AD bits disabled, so only writes try to update the D bit. */ 3033 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ); 3034 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 3035 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC); 3036 /* Both A and D already set, so read-only is OK. */ 3037 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_READ); 3038 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_WRITE); 3039 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_EXEC); 3040 } 3041 3042 static void ept_access_test_paddr_read_only_ad_enabled(void) 3043 { 3044 /* 3045 * When EPT AD bits are enabled, all accesses to guest paging 3046 * structures are considered writes as far as EPT translation 3047 * is concerned. 3048 */ 3049 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 3050 3051 ept_access_test_setup(); 3052 ept_enable_ad_bits_or_skip_test(); 3053 3054 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 3055 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 3056 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 3057 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ, qual); 3058 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 3059 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC, qual); 3060 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_READ, qual); 3061 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_WRITE, qual); 3062 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_EXEC, qual); 3063 } 3064 3065 static void ept_access_test_paddr_read_write(void) 3066 { 3067 ept_access_test_setup(); 3068 /* Read-write access to paging structure. */ 3069 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_READ); 3070 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_WRITE); 3071 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_EXEC); 3072 } 3073 3074 static void ept_access_test_paddr_read_write_execute(void) 3075 { 3076 ept_access_test_setup(); 3077 /* RWX access to paging structure. */ 3078 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_READ); 3079 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_WRITE); 3080 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_EXEC); 3081 } 3082 3083 static void ept_access_test_paddr_read_execute_ad_disabled(void) 3084 { 3085 /* 3086 * When EPT AD bits are disabled, all accesses to guest paging 3087 * structures are reported separately as a read and (after 3088 * translation of the GPA to host physical address) a read+write 3089 * if the A/D bits have to be set. 3090 */ 3091 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3092 3093 ept_access_test_setup(); 3094 ept_disable_ad_bits(); 3095 3096 /* Can't update A bit, so all accesses fail. */ 3097 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3098 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3099 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3100 /* AD bits disabled, so only writes try to update the D bit. */ 3101 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ); 3102 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3103 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC); 3104 /* Both A and D already set, so read-only is OK. */ 3105 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ); 3106 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE); 3107 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC); 3108 } 3109 3110 static void ept_access_test_paddr_read_execute_ad_enabled(void) 3111 { 3112 /* 3113 * When EPT AD bits are enabled, all accesses to guest paging 3114 * structures are considered writes as far as EPT translation 3115 * is concerned. 3116 */ 3117 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3118 3119 ept_access_test_setup(); 3120 ept_enable_ad_bits_or_skip_test(); 3121 3122 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3123 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3124 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3125 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ, qual); 3126 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3127 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC, qual); 3128 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ, qual); 3129 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE, qual); 3130 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC, qual); 3131 } 3132 3133 static void ept_access_test_paddr_not_present_page_fault(void) 3134 { 3135 ept_access_test_setup(); 3136 /* 3137 * TODO: test no EPT violation as long as guest PF occurs. e.g., GPA is 3138 * page is read-only in EPT but GVA is also mapped read only in PT. 3139 * Thus guest page fault before host takes EPT violation for trying to 3140 * update A bit. 3141 */ 3142 } 3143 3144 static void ept_access_test_force_2m_page(void) 3145 { 3146 ept_access_test_setup(); 3147 3148 TEST_ASSERT_EQ(ept_2m_supported(), true); 3149 ept_allowed_at_level_mkhuge(true, 2, 0, 0, OP_READ); 3150 ept_violation_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_RA, OP_WRITE, 3151 EPT_VLT_WR | EPT_VLT_PERM_RD | 3152 EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 3153 ept_misconfig_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_WA); 3154 } 3155 3156 static bool invvpid_valid(u64 type, u64 vpid, u64 gla) 3157 { 3158 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3159 3160 TEST_ASSERT(msr & VPID_CAP_INVVPID); 3161 3162 if (type < INVVPID_ADDR || type > INVVPID_CONTEXT_LOCAL) 3163 return false; 3164 3165 if (!(msr & (1ull << (type + VPID_CAP_INVVPID_TYPES_SHIFT)))) 3166 return false; 3167 3168 if (vpid >> 16) 3169 return false; 3170 3171 if (type != INVVPID_ALL && !vpid) 3172 return false; 3173 3174 if (type == INVVPID_ADDR && !is_canonical(gla)) 3175 return false; 3176 3177 return true; 3178 } 3179 3180 static void try_invvpid(u64 type, u64 vpid, u64 gla) 3181 { 3182 int rc; 3183 bool valid = invvpid_valid(type, vpid, gla); 3184 u64 expected = valid ? VMXERR_UNSUPPORTED_VMCS_COMPONENT 3185 : VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID; 3186 /* 3187 * Set VMX_INST_ERROR to VMXERR_UNVALID_VMCS_COMPONENT, so 3188 * that we can tell if it is updated by INVVPID. 3189 */ 3190 vmcs_read(~0); 3191 rc = invvpid(type, vpid, gla); 3192 report(!rc == valid, "INVVPID type %ld VPID %lx GLA %lx %s", type, 3193 vpid, gla, 3194 valid ? "passes" : "fails"); 3195 report(vmcs_read(VMX_INST_ERROR) == expected, 3196 "After %s INVVPID, VMX_INST_ERR is %ld (actual %ld)", 3197 rc ? "failed" : "successful", 3198 expected, vmcs_read(VMX_INST_ERROR)); 3199 } 3200 3201 static void ds_invvpid(void *data) 3202 { 3203 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3204 u64 type = ffs(msr >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 3205 3206 TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 3207 asm volatile("invvpid %0, %1" 3208 : 3209 : "m"(*(struct invvpid_operand *)data), 3210 "r"(type)); 3211 } 3212 3213 /* 3214 * The SS override is ignored in 64-bit mode, so we use an addressing 3215 * mode with %rsp as the base register to generate an implicit SS 3216 * reference. 3217 */ 3218 static void ss_invvpid(void *data) 3219 { 3220 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3221 u64 type = ffs(msr >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 3222 3223 TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 3224 asm volatile("sub %%rsp,%0; invvpid (%%rsp,%0,1), %1" 3225 : "+r"(data) 3226 : "r"(type)); 3227 } 3228 3229 static void invvpid_test_gp(void) 3230 { 3231 bool fault; 3232 3233 fault = test_for_exception(GP_VECTOR, &ds_invvpid, 3234 (void *)NONCANONICAL); 3235 report(fault, "INVVPID with non-canonical DS operand raises #GP"); 3236 } 3237 3238 static void invvpid_test_ss(void) 3239 { 3240 bool fault; 3241 3242 fault = test_for_exception(SS_VECTOR, &ss_invvpid, 3243 (void *)NONCANONICAL); 3244 report(fault, "INVVPID with non-canonical SS operand raises #SS"); 3245 } 3246 3247 static void invvpid_test_pf(void) 3248 { 3249 void *vpage = alloc_vpage(); 3250 bool fault; 3251 3252 fault = test_for_exception(PF_VECTOR, &ds_invvpid, vpage); 3253 report(fault, "INVVPID with unmapped operand raises #PF"); 3254 } 3255 3256 static void try_compat_invvpid(void *unused) 3257 { 3258 struct far_pointer32 fp = { 3259 .offset = (uintptr_t)&&invvpid, 3260 .selector = KERNEL_CS32, 3261 }; 3262 register uintptr_t rsp asm("rsp"); 3263 3264 TEST_ASSERT_MSG(fp.offset == (uintptr_t)&&invvpid, 3265 "Code address too high."); 3266 TEST_ASSERT_MSG(rsp == (u32)rsp, "Stack address too high."); 3267 3268 asm goto ("lcall *%0" : : "m" (fp) : "rax" : invvpid); 3269 return; 3270 invvpid: 3271 asm volatile (".code32;" 3272 "invvpid (%eax), %eax;" 3273 "lret;" 3274 ".code64"); 3275 __builtin_unreachable(); 3276 } 3277 3278 static void invvpid_test_compatibility_mode(void) 3279 { 3280 bool fault; 3281 3282 fault = test_for_exception(UD_VECTOR, &try_compat_invvpid, NULL); 3283 report(fault, "Compatibility mode INVVPID raises #UD"); 3284 } 3285 3286 static void invvpid_test_not_in_vmx_operation(void) 3287 { 3288 bool fault; 3289 3290 TEST_ASSERT(!vmx_off()); 3291 fault = test_for_exception(UD_VECTOR, &ds_invvpid, NULL); 3292 report(fault, "INVVPID outside of VMX operation raises #UD"); 3293 TEST_ASSERT(!vmx_on()); 3294 } 3295 3296 /* 3297 * This does not test real-address mode, virtual-8086 mode, protected mode, 3298 * or CPL > 0. 3299 */ 3300 static void invvpid_test_v2(void) 3301 { 3302 u64 msr; 3303 int i; 3304 unsigned types = 0; 3305 unsigned type; 3306 3307 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 3308 !(ctrl_cpu_rev[1].clr & CPU_VPID)) 3309 test_skip("VPID not supported"); 3310 3311 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3312 3313 if (!(msr & VPID_CAP_INVVPID)) 3314 test_skip("INVVPID not supported.\n"); 3315 3316 if (msr & VPID_CAP_INVVPID_ADDR) 3317 types |= 1u << INVVPID_ADDR; 3318 if (msr & VPID_CAP_INVVPID_CXTGLB) 3319 types |= 1u << INVVPID_CONTEXT_GLOBAL; 3320 if (msr & VPID_CAP_INVVPID_ALL) 3321 types |= 1u << INVVPID_ALL; 3322 if (msr & VPID_CAP_INVVPID_CXTLOC) 3323 types |= 1u << INVVPID_CONTEXT_LOCAL; 3324 3325 if (!types) 3326 test_skip("No INVVPID types supported.\n"); 3327 3328 for (i = -127; i < 128; i++) 3329 try_invvpid(i, 0xffff, 0); 3330 3331 /* 3332 * VPID must not be more than 16 bits. 3333 */ 3334 for (i = 0; i < 64; i++) 3335 for (type = 0; type < 4; type++) 3336 if (types & (1u << type)) 3337 try_invvpid(type, 1ul << i, 0); 3338 3339 /* 3340 * VPID must not be zero, except for "all contexts." 3341 */ 3342 for (type = 0; type < 4; type++) 3343 if (types & (1u << type)) 3344 try_invvpid(type, 0, 0); 3345 3346 /* 3347 * The gla operand is only validated for single-address INVVPID. 3348 */ 3349 if (types & (1u << INVVPID_ADDR)) 3350 try_invvpid(INVVPID_ADDR, 0xffff, NONCANONICAL); 3351 3352 invvpid_test_gp(); 3353 invvpid_test_ss(); 3354 invvpid_test_pf(); 3355 invvpid_test_compatibility_mode(); 3356 invvpid_test_not_in_vmx_operation(); 3357 } 3358 3359 /* 3360 * Test for early VMLAUNCH failure. Returns true if VMLAUNCH makes it 3361 * at least as far as the guest-state checks. Returns false if the 3362 * VMLAUNCH fails early and execution falls through to the next 3363 * instruction. 3364 */ 3365 static bool vmlaunch_succeeds(void) 3366 { 3367 u32 exit_reason; 3368 3369 /* 3370 * Indirectly set VMX_INST_ERR to 12 ("VMREAD/VMWRITE from/to 3371 * unsupported VMCS component"). The caller can then check 3372 * to see if a failed VM-entry sets VMX_INST_ERR as expected. 3373 */ 3374 vmcs_write(~0u, 0); 3375 3376 vmcs_write(HOST_RIP, (uintptr_t)&&success); 3377 __asm__ __volatile__ goto ("vmwrite %%rsp, %0; vmlaunch" 3378 : 3379 : "r" ((u64)HOST_RSP) 3380 : "cc", "memory" 3381 : success); 3382 return false; 3383 success: 3384 exit_reason = vmcs_read(EXI_REASON); 3385 TEST_ASSERT(exit_reason == (VMX_FAIL_STATE | VMX_ENTRY_FAILURE) || 3386 exit_reason == (VMX_FAIL_MSR | VMX_ENTRY_FAILURE)); 3387 return true; 3388 } 3389 3390 /* 3391 * Try to launch the current VMCS. 3392 */ 3393 static void test_vmx_vmlaunch(u32 xerror) 3394 { 3395 bool success = vmlaunch_succeeds(); 3396 u32 vmx_inst_err; 3397 3398 report(success == !xerror, "vmlaunch %s", 3399 !xerror ? "succeeds" : "fails"); 3400 if (!success && xerror) { 3401 vmx_inst_err = vmcs_read(VMX_INST_ERROR); 3402 report(vmx_inst_err == xerror, 3403 "VMX inst error is %d (actual %d)", xerror, 3404 vmx_inst_err); 3405 } 3406 } 3407 3408 static void test_vmx_invalid_controls(void) 3409 { 3410 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_CONTROL_FIELD); 3411 } 3412 3413 static void test_vmx_valid_controls(void) 3414 { 3415 test_vmx_vmlaunch(0); 3416 } 3417 3418 /* 3419 * Test a particular value of a VM-execution control bit, if the value 3420 * is required or if the value is zero. 3421 */ 3422 static void test_rsvd_ctl_bit_value(const char *name, union vmx_ctrl_msr msr, 3423 enum Encoding encoding, unsigned bit, 3424 unsigned val) 3425 { 3426 u32 mask = 1u << bit; 3427 bool expected; 3428 u32 controls; 3429 3430 if (msr.set & mask) 3431 TEST_ASSERT(msr.clr & mask); 3432 3433 /* 3434 * We can't arbitrarily turn on a control bit, because it may 3435 * introduce dependencies on other VMCS fields. So, we only 3436 * test turning on bits that have a required setting. 3437 */ 3438 if (val && (msr.clr & mask) && !(msr.set & mask)) 3439 return; 3440 3441 report_prefix_pushf("%s %s bit %d", 3442 val ? "Set" : "Clear", name, bit); 3443 3444 controls = vmcs_read(encoding); 3445 if (val) { 3446 vmcs_write(encoding, msr.set | mask); 3447 expected = (msr.clr & mask); 3448 } else { 3449 vmcs_write(encoding, msr.set & ~mask); 3450 expected = !(msr.set & mask); 3451 } 3452 if (expected) 3453 test_vmx_valid_controls(); 3454 else 3455 test_vmx_invalid_controls(); 3456 vmcs_write(encoding, controls); 3457 report_prefix_pop(); 3458 } 3459 3460 /* 3461 * Test reserved values of a VM-execution control bit, based on the 3462 * allowed bit settings from the corresponding VMX capability MSR. 3463 */ 3464 static void test_rsvd_ctl_bit(const char *name, union vmx_ctrl_msr msr, 3465 enum Encoding encoding, unsigned bit) 3466 { 3467 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 0); 3468 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 1); 3469 } 3470 3471 /* 3472 * Reserved bits in the pin-based VM-execution controls must be set 3473 * properly. Software may consult the VMX capability MSRs to determine 3474 * the proper settings. 3475 * [Intel SDM] 3476 */ 3477 static void test_pin_based_ctls(void) 3478 { 3479 unsigned bit; 3480 3481 printf("%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PIN" : 3482 "MSR_IA32_VMX_PINBASED_CTLS", ctrl_pin_rev.val); 3483 for (bit = 0; bit < 32; bit++) 3484 test_rsvd_ctl_bit("pin-based controls", 3485 ctrl_pin_rev, PIN_CONTROLS, bit); 3486 } 3487 3488 /* 3489 * Reserved bits in the primary processor-based VM-execution controls 3490 * must be set properly. Software may consult the VMX capability MSRs 3491 * to determine the proper settings. 3492 * [Intel SDM] 3493 */ 3494 static void test_primary_processor_based_ctls(void) 3495 { 3496 unsigned bit; 3497 3498 printf("\n%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PROC" : 3499 "MSR_IA32_VMX_PROCBASED_CTLS", ctrl_cpu_rev[0].val); 3500 for (bit = 0; bit < 32; bit++) 3501 test_rsvd_ctl_bit("primary processor-based controls", 3502 ctrl_cpu_rev[0], CPU_EXEC_CTRL0, bit); 3503 } 3504 3505 /* 3506 * If the "activate secondary controls" primary processor-based 3507 * VM-execution control is 1, reserved bits in the secondary 3508 * processor-based VM-execution controls must be cleared. Software may 3509 * consult the VMX capability MSRs to determine which bits are 3510 * reserved. 3511 * If the "activate secondary controls" primary processor-based 3512 * VM-execution control is 0 (or if the processor does not support the 3513 * 1-setting of that control), no checks are performed on the 3514 * secondary processor-based VM-execution controls. 3515 * [Intel SDM] 3516 */ 3517 static void test_secondary_processor_based_ctls(void) 3518 { 3519 u32 primary; 3520 u32 secondary; 3521 unsigned bit; 3522 3523 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) 3524 return; 3525 3526 primary = vmcs_read(CPU_EXEC_CTRL0); 3527 secondary = vmcs_read(CPU_EXEC_CTRL1); 3528 3529 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3530 printf("\nMSR_IA32_VMX_PROCBASED_CTLS2: %lx\n", ctrl_cpu_rev[1].val); 3531 for (bit = 0; bit < 32; bit++) 3532 test_rsvd_ctl_bit("secondary processor-based controls", 3533 ctrl_cpu_rev[1], CPU_EXEC_CTRL1, bit); 3534 3535 /* 3536 * When the "activate secondary controls" VM-execution control 3537 * is clear, there are no checks on the secondary controls. 3538 */ 3539 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3540 vmcs_write(CPU_EXEC_CTRL1, ~0); 3541 report(vmlaunch_succeeds(), 3542 "Secondary processor-based controls ignored"); 3543 vmcs_write(CPU_EXEC_CTRL1, secondary); 3544 vmcs_write(CPU_EXEC_CTRL0, primary); 3545 } 3546 3547 static void try_cr3_target_count(unsigned i, unsigned max) 3548 { 3549 report_prefix_pushf("CR3 target count 0x%x", i); 3550 vmcs_write(CR3_TARGET_COUNT, i); 3551 if (i <= max) 3552 test_vmx_valid_controls(); 3553 else 3554 test_vmx_invalid_controls(); 3555 report_prefix_pop(); 3556 } 3557 3558 /* 3559 * The CR3-target count must not be greater than 4. Future processors 3560 * may support a different number of CR3-target values. Software 3561 * should read the VMX capability MSR IA32_VMX_MISC to determine the 3562 * number of values supported. 3563 * [Intel SDM] 3564 */ 3565 static void test_cr3_targets(void) 3566 { 3567 unsigned supported_targets = (rdmsr(MSR_IA32_VMX_MISC) >> 16) & 0x1ff; 3568 u32 cr3_targets = vmcs_read(CR3_TARGET_COUNT); 3569 unsigned i; 3570 3571 printf("\nSupported CR3 targets: %d\n", supported_targets); 3572 TEST_ASSERT(supported_targets <= 256); 3573 3574 try_cr3_target_count(-1u, supported_targets); 3575 try_cr3_target_count(0x80000000, supported_targets); 3576 try_cr3_target_count(0x7fffffff, supported_targets); 3577 for (i = 0; i <= supported_targets + 1; i++) 3578 try_cr3_target_count(i, supported_targets); 3579 vmcs_write(CR3_TARGET_COUNT, cr3_targets); 3580 } 3581 3582 /* 3583 * Test a particular address setting in the VMCS 3584 */ 3585 static void test_vmcs_addr(const char *name, 3586 enum Encoding encoding, 3587 u64 align, 3588 bool ignored, 3589 bool skip_beyond_mapped_ram, 3590 u64 addr) 3591 { 3592 report_prefix_pushf("%s = %lx", name, addr); 3593 vmcs_write(encoding, addr); 3594 if (skip_beyond_mapped_ram && 3595 addr > fwcfg_get_u64(FW_CFG_RAM_SIZE) - align && 3596 addr < (1ul << cpuid_maxphyaddr())) 3597 printf("Skipping physical address beyond mapped RAM\n"); 3598 else if (ignored || (IS_ALIGNED(addr, align) && 3599 addr < (1ul << cpuid_maxphyaddr()))) 3600 test_vmx_valid_controls(); 3601 else 3602 test_vmx_invalid_controls(); 3603 report_prefix_pop(); 3604 } 3605 3606 /* 3607 * Test interesting values for a VMCS address 3608 */ 3609 static void test_vmcs_addr_values(const char *name, 3610 enum Encoding encoding, 3611 u64 align, 3612 bool ignored, 3613 bool skip_beyond_mapped_ram, 3614 u32 bit_start, u32 bit_end) 3615 { 3616 unsigned i; 3617 u64 orig_val = vmcs_read(encoding); 3618 3619 for (i = bit_start; i <= bit_end; i++) 3620 test_vmcs_addr(name, encoding, align, ignored, 3621 skip_beyond_mapped_ram, 1ul << i); 3622 3623 test_vmcs_addr(name, encoding, align, ignored, 3624 skip_beyond_mapped_ram, PAGE_SIZE - 1); 3625 test_vmcs_addr(name, encoding, align, ignored, 3626 skip_beyond_mapped_ram, PAGE_SIZE); 3627 test_vmcs_addr(name, encoding, align, ignored, 3628 skip_beyond_mapped_ram, 3629 (1ul << cpuid_maxphyaddr()) - PAGE_SIZE); 3630 test_vmcs_addr(name, encoding, align, ignored, 3631 skip_beyond_mapped_ram, -1ul); 3632 3633 vmcs_write(encoding, orig_val); 3634 } 3635 3636 /* 3637 * Test a physical address reference in the VMCS, when the corresponding 3638 * feature is enabled and when the corresponding feature is disabled. 3639 */ 3640 static void test_vmcs_addr_reference(u32 control_bit, enum Encoding field, 3641 const char *field_name, 3642 const char *control_name, u64 align, 3643 bool skip_beyond_mapped_ram, 3644 bool control_primary) 3645 { 3646 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 3647 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 3648 u64 page_addr; 3649 3650 if (control_primary) { 3651 if (!(ctrl_cpu_rev[0].clr & control_bit)) 3652 return; 3653 } else { 3654 if (!(ctrl_cpu_rev[1].clr & control_bit)) 3655 return; 3656 } 3657 3658 page_addr = vmcs_read(field); 3659 3660 report_prefix_pushf("%s enabled", control_name); 3661 if (control_primary) { 3662 vmcs_write(CPU_EXEC_CTRL0, primary | control_bit); 3663 } else { 3664 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3665 vmcs_write(CPU_EXEC_CTRL1, secondary | control_bit); 3666 } 3667 3668 test_vmcs_addr_values(field_name, field, align, false, 3669 skip_beyond_mapped_ram, 0, 63); 3670 report_prefix_pop(); 3671 3672 report_prefix_pushf("%s disabled", control_name); 3673 if (control_primary) { 3674 vmcs_write(CPU_EXEC_CTRL0, primary & ~control_bit); 3675 } else { 3676 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3677 vmcs_write(CPU_EXEC_CTRL1, secondary & ~control_bit); 3678 } 3679 3680 test_vmcs_addr_values(field_name, field, align, true, false, 0, 63); 3681 report_prefix_pop(); 3682 3683 vmcs_write(field, page_addr); 3684 vmcs_write(CPU_EXEC_CTRL0, primary); 3685 vmcs_write(CPU_EXEC_CTRL1, secondary); 3686 } 3687 3688 /* 3689 * If the "use I/O bitmaps" VM-execution control is 1, bits 11:0 of 3690 * each I/O-bitmap address must be 0. Neither address should set any 3691 * bits beyond the processor's physical-address width. 3692 * [Intel SDM] 3693 */ 3694 static void test_io_bitmaps(void) 3695 { 3696 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_A, 3697 "I/O bitmap A", "Use I/O bitmaps", 3698 PAGE_SIZE, false, true); 3699 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_B, 3700 "I/O bitmap B", "Use I/O bitmaps", 3701 PAGE_SIZE, false, true); 3702 } 3703 3704 /* 3705 * If the "use MSR bitmaps" VM-execution control is 1, bits 11:0 of 3706 * the MSR-bitmap address must be 0. The address should not set any 3707 * bits beyond the processor's physical-address width. 3708 * [Intel SDM] 3709 */ 3710 static void test_msr_bitmap(void) 3711 { 3712 test_vmcs_addr_reference(CPU_MSR_BITMAP, MSR_BITMAP, 3713 "MSR bitmap", "Use MSR bitmaps", 3714 PAGE_SIZE, false, true); 3715 } 3716 3717 /* 3718 * If the "use TPR shadow" VM-execution control is 1, the virtual-APIC 3719 * address must satisfy the following checks: 3720 * - Bits 11:0 of the address must be 0. 3721 * - The address should not set any bits beyond the processor's 3722 * physical-address width. 3723 * [Intel SDM] 3724 */ 3725 static void test_apic_virt_addr(void) 3726 { 3727 /* 3728 * Ensure the processor will never use the virtual-APIC page, since 3729 * we will point it to invalid RAM. Otherwise KVM is puzzled about 3730 * what we're trying to achieve and fails vmentry. 3731 */ 3732 u32 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 3733 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0 | CPU_CR8_LOAD | CPU_CR8_STORE); 3734 test_vmcs_addr_reference(CPU_TPR_SHADOW, APIC_VIRT_ADDR, 3735 "virtual-APIC address", "Use TPR shadow", 3736 PAGE_SIZE, false, true); 3737 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 3738 } 3739 3740 /* 3741 * If the "virtualize APIC-accesses" VM-execution control is 1, the 3742 * APIC-access address must satisfy the following checks: 3743 * - Bits 11:0 of the address must be 0. 3744 * - The address should not set any bits beyond the processor's 3745 * physical-address width. 3746 * [Intel SDM] 3747 */ 3748 static void test_apic_access_addr(void) 3749 { 3750 void *apic_access_page = alloc_page(); 3751 3752 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_page)); 3753 3754 test_vmcs_addr_reference(CPU_VIRT_APIC_ACCESSES, APIC_ACCS_ADDR, 3755 "APIC-access address", 3756 "virtualize APIC-accesses", PAGE_SIZE, 3757 true, false); 3758 } 3759 3760 static bool set_bit_pattern(u8 mask, u32 *secondary) 3761 { 3762 u8 i; 3763 bool flag = false; 3764 u32 test_bits[3] = { 3765 CPU_VIRT_X2APIC, 3766 CPU_APIC_REG_VIRT, 3767 CPU_VINTD 3768 }; 3769 3770 for (i = 0; i < ARRAY_SIZE(test_bits); i++) { 3771 if ((mask & (1u << i)) && 3772 (ctrl_cpu_rev[1].clr & test_bits[i])) { 3773 *secondary |= test_bits[i]; 3774 flag = true; 3775 } 3776 } 3777 3778 return (flag); 3779 } 3780 3781 /* 3782 * If the "use TPR shadow" VM-execution control is 0, the following 3783 * VM-execution controls must also be 0: 3784 * - virtualize x2APIC mode 3785 * - APIC-register virtualization 3786 * - virtual-interrupt delivery 3787 * [Intel SDM] 3788 * 3789 * 2. If the "virtualize x2APIC mode" VM-execution control is 1, the 3790 * "virtualize APIC accesses" VM-execution control must be 0. 3791 * [Intel SDM] 3792 */ 3793 static void test_apic_virtual_ctls(void) 3794 { 3795 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3796 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3797 u32 primary = saved_primary; 3798 u32 secondary = saved_secondary; 3799 bool ctrl = false; 3800 char str[10] = "disabled"; 3801 u8 i = 0, j; 3802 3803 /* 3804 * First test 3805 */ 3806 if (!((ctrl_cpu_rev[0].clr & (CPU_SECONDARY | CPU_TPR_SHADOW)) == 3807 (CPU_SECONDARY | CPU_TPR_SHADOW))) 3808 return; 3809 3810 primary |= CPU_SECONDARY; 3811 primary &= ~CPU_TPR_SHADOW; 3812 vmcs_write(CPU_EXEC_CTRL0, primary); 3813 3814 while (1) { 3815 for (j = 1; j < 8; j++) { 3816 secondary &= ~(CPU_VIRT_X2APIC | CPU_APIC_REG_VIRT | CPU_VINTD); 3817 if (primary & CPU_TPR_SHADOW) { 3818 ctrl = true; 3819 } else { 3820 if (! set_bit_pattern(j, &secondary)) 3821 ctrl = true; 3822 else 3823 ctrl = false; 3824 } 3825 3826 vmcs_write(CPU_EXEC_CTRL1, secondary); 3827 report_prefix_pushf("Use TPR shadow %s, virtualize x2APIC mode %s, APIC-register virtualization %s, virtual-interrupt delivery %s", 3828 str, (secondary & CPU_VIRT_X2APIC) ? "enabled" : "disabled", (secondary & CPU_APIC_REG_VIRT) ? "enabled" : "disabled", (secondary & CPU_VINTD) ? "enabled" : "disabled"); 3829 if (ctrl) 3830 test_vmx_valid_controls(); 3831 else 3832 test_vmx_invalid_controls(); 3833 report_prefix_pop(); 3834 } 3835 3836 if (i == 1) 3837 break; 3838 i++; 3839 3840 primary |= CPU_TPR_SHADOW; 3841 vmcs_write(CPU_EXEC_CTRL0, primary); 3842 strcpy(str, "enabled"); 3843 } 3844 3845 /* 3846 * Second test 3847 */ 3848 u32 apic_virt_ctls = (CPU_VIRT_X2APIC | CPU_VIRT_APIC_ACCESSES); 3849 3850 primary = saved_primary; 3851 secondary = saved_secondary; 3852 if (!((ctrl_cpu_rev[1].clr & apic_virt_ctls) == apic_virt_ctls)) 3853 return; 3854 3855 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3856 secondary &= ~CPU_VIRT_APIC_ACCESSES; 3857 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_X2APIC); 3858 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access disabled"); 3859 test_vmx_valid_controls(); 3860 report_prefix_pop(); 3861 3862 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_APIC_ACCESSES); 3863 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access enabled"); 3864 test_vmx_valid_controls(); 3865 report_prefix_pop(); 3866 3867 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_X2APIC); 3868 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access enabled"); 3869 test_vmx_invalid_controls(); 3870 report_prefix_pop(); 3871 3872 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_APIC_ACCESSES); 3873 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access disabled"); 3874 test_vmx_valid_controls(); 3875 report_prefix_pop(); 3876 3877 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3878 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3879 } 3880 3881 /* 3882 * If the "virtual-interrupt delivery" VM-execution control is 1, the 3883 * "external-interrupt exiting" VM-execution control must be 1. 3884 * [Intel SDM] 3885 */ 3886 static void test_virtual_intr_ctls(void) 3887 { 3888 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3889 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3890 u32 saved_pin = vmcs_read(PIN_CONTROLS); 3891 u32 primary = saved_primary; 3892 u32 secondary = saved_secondary; 3893 u32 pin = saved_pin; 3894 3895 if (!((ctrl_cpu_rev[1].clr & CPU_VINTD) && 3896 (ctrl_pin_rev.clr & PIN_EXTINT))) 3897 return; 3898 3899 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 3900 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VINTD); 3901 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 3902 report_prefix_pushf("Virtualize interrupt-delivery disabled; external-interrupt exiting disabled"); 3903 test_vmx_valid_controls(); 3904 report_prefix_pop(); 3905 3906 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VINTD); 3907 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 3908 test_vmx_invalid_controls(); 3909 report_prefix_pop(); 3910 3911 vmcs_write(PIN_CONTROLS, pin | PIN_EXTINT); 3912 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting enabled"); 3913 test_vmx_valid_controls(); 3914 report_prefix_pop(); 3915 3916 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 3917 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 3918 test_vmx_invalid_controls(); 3919 report_prefix_pop(); 3920 3921 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3922 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3923 vmcs_write(PIN_CONTROLS, saved_pin); 3924 } 3925 3926 static void test_pi_desc_addr(u64 addr, bool ctrl) 3927 { 3928 vmcs_write(POSTED_INTR_DESC_ADDR, addr); 3929 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-descriptor-address 0x%lx", addr); 3930 if (ctrl) 3931 test_vmx_valid_controls(); 3932 else 3933 test_vmx_invalid_controls(); 3934 report_prefix_pop(); 3935 } 3936 3937 /* 3938 * If the “process posted interrupts†VM-execution control is 1, the 3939 * following must be true: 3940 * 3941 * - The “virtual-interrupt delivery†VM-execution control is 1. 3942 * - The “acknowledge interrupt on exit†VM-exit control is 1. 3943 * - The posted-interrupt notification vector has a value in the 3944 * - range 0–255 (bits 15:8 are all 0). 3945 * - Bits 5:0 of the posted-interrupt descriptor address are all 0. 3946 * - The posted-interrupt descriptor address does not set any bits 3947 * beyond the processor's physical-address width. 3948 * [Intel SDM] 3949 */ 3950 static void test_posted_intr(void) 3951 { 3952 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3953 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3954 u32 saved_pin = vmcs_read(PIN_CONTROLS); 3955 u32 exit_ctl_saved = vmcs_read(EXI_CONTROLS); 3956 u32 primary = saved_primary; 3957 u32 secondary = saved_secondary; 3958 u32 pin = saved_pin; 3959 u32 exit_ctl = exit_ctl_saved; 3960 u16 vec; 3961 int i; 3962 3963 if (!((ctrl_pin_rev.clr & PIN_POST_INTR) && 3964 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 3965 (ctrl_exit_rev.clr & EXI_INTA))) 3966 return; 3967 3968 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 3969 3970 /* 3971 * Test virtual-interrupt-delivery and acknowledge-interrupt-on-exit 3972 */ 3973 pin |= PIN_POST_INTR; 3974 vmcs_write(PIN_CONTROLS, pin); 3975 secondary &= ~CPU_VINTD; 3976 vmcs_write(CPU_EXEC_CTRL1, secondary); 3977 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled"); 3978 test_vmx_invalid_controls(); 3979 report_prefix_pop(); 3980 3981 secondary |= CPU_VINTD; 3982 vmcs_write(CPU_EXEC_CTRL1, secondary); 3983 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled"); 3984 test_vmx_invalid_controls(); 3985 report_prefix_pop(); 3986 3987 exit_ctl &= ~EXI_INTA; 3988 vmcs_write(EXI_CONTROLS, exit_ctl); 3989 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit disabled"); 3990 test_vmx_invalid_controls(); 3991 report_prefix_pop(); 3992 3993 exit_ctl |= EXI_INTA; 3994 vmcs_write(EXI_CONTROLS, exit_ctl); 3995 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 3996 test_vmx_valid_controls(); 3997 report_prefix_pop(); 3998 3999 secondary &= ~CPU_VINTD; 4000 vmcs_write(CPU_EXEC_CTRL1, secondary); 4001 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled; acknowledge-interrupt-on-exit enabled"); 4002 test_vmx_invalid_controls(); 4003 report_prefix_pop(); 4004 4005 secondary |= CPU_VINTD; 4006 vmcs_write(CPU_EXEC_CTRL1, secondary); 4007 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 4008 test_vmx_valid_controls(); 4009 report_prefix_pop(); 4010 4011 /* 4012 * Test posted-interrupt notification vector 4013 */ 4014 for (i = 0; i < 8; i++) { 4015 vec = (1ul << i); 4016 vmcs_write(PINV, vec); 4017 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 4018 test_vmx_valid_controls(); 4019 report_prefix_pop(); 4020 } 4021 for (i = 8; i < 16; i++) { 4022 vec = (1ul << i); 4023 vmcs_write(PINV, vec); 4024 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 4025 test_vmx_invalid_controls(); 4026 report_prefix_pop(); 4027 } 4028 4029 vec &= ~(0xff << 8); 4030 vmcs_write(PINV, vec); 4031 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 4032 test_vmx_valid_controls(); 4033 report_prefix_pop(); 4034 4035 /* 4036 * Test posted-interrupt descriptor addresss 4037 */ 4038 for (i = 0; i < 6; i++) { 4039 test_pi_desc_addr(1ul << i, false); 4040 } 4041 4042 test_pi_desc_addr(0xf0, false); 4043 test_pi_desc_addr(0xff, false); 4044 test_pi_desc_addr(0x0f, false); 4045 test_pi_desc_addr(0x8000, true); 4046 test_pi_desc_addr(0x00, true); 4047 test_pi_desc_addr(0xc000, true); 4048 4049 test_vmcs_addr_values("process-posted interrupts", 4050 POSTED_INTR_DESC_ADDR, 64, 4051 false, false, 0, 63); 4052 4053 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 4054 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 4055 vmcs_write(PIN_CONTROLS, saved_pin); 4056 } 4057 4058 static void test_apic_ctls(void) 4059 { 4060 test_apic_virt_addr(); 4061 test_apic_access_addr(); 4062 test_apic_virtual_ctls(); 4063 test_virtual_intr_ctls(); 4064 test_posted_intr(); 4065 } 4066 4067 /* 4068 * If the “enable VPID†VM-execution control is 1, the value of the 4069 * of the VPID VM-execution control field must not be 0000H. 4070 * [Intel SDM] 4071 */ 4072 static void test_vpid(void) 4073 { 4074 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 4075 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 4076 u16 vpid = 0x0000; 4077 int i; 4078 4079 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4080 (ctrl_cpu_rev[1].clr & CPU_VPID))) { 4081 printf("Secondary controls and/or VPID not supported\n"); 4082 return; 4083 } 4084 4085 vmcs_write(CPU_EXEC_CTRL0, saved_primary | CPU_SECONDARY); 4086 vmcs_write(CPU_EXEC_CTRL1, saved_secondary & ~CPU_VPID); 4087 vmcs_write(VPID, vpid); 4088 report_prefix_pushf("VPID disabled; VPID value %x", vpid); 4089 test_vmx_valid_controls(); 4090 report_prefix_pop(); 4091 4092 vmcs_write(CPU_EXEC_CTRL1, saved_secondary | CPU_VPID); 4093 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 4094 test_vmx_invalid_controls(); 4095 report_prefix_pop(); 4096 4097 for (i = 0; i < 16; i++) { 4098 vpid = (short)1 << i;; 4099 vmcs_write(VPID, vpid); 4100 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 4101 test_vmx_valid_controls(); 4102 report_prefix_pop(); 4103 } 4104 4105 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 4106 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 4107 } 4108 4109 static void set_vtpr(unsigned vtpr) 4110 { 4111 *(u32 *)phys_to_virt(vmcs_read(APIC_VIRT_ADDR) + APIC_TASKPRI) = vtpr; 4112 } 4113 4114 static void try_tpr_threshold_and_vtpr(unsigned threshold, unsigned vtpr) 4115 { 4116 bool valid = true; 4117 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4118 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4119 4120 if ((primary & CPU_TPR_SHADOW) && 4121 (!(primary & CPU_SECONDARY) || 4122 !(secondary & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 4123 valid = (threshold & 0xf) <= ((vtpr >> 4) & 0xf); 4124 4125 set_vtpr(vtpr); 4126 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0x%x", 4127 threshold, (vtpr >> 4) & 0xf); 4128 if (valid) 4129 test_vmx_valid_controls(); 4130 else 4131 test_vmx_invalid_controls(); 4132 report_prefix_pop(); 4133 } 4134 4135 static void test_invalid_event_injection(void) 4136 { 4137 u32 ent_intr_info_save = vmcs_read(ENT_INTR_INFO); 4138 u32 ent_intr_error_save = vmcs_read(ENT_INTR_ERROR); 4139 u32 ent_inst_len_save = vmcs_read(ENT_INST_LEN); 4140 u32 primary_save = vmcs_read(CPU_EXEC_CTRL0); 4141 u32 secondary_save = vmcs_read(CPU_EXEC_CTRL1); 4142 u64 guest_cr0_save = vmcs_read(GUEST_CR0); 4143 u32 ent_intr_info_base = INTR_INFO_VALID_MASK; 4144 u32 ent_intr_info, ent_intr_err, ent_intr_len; 4145 u32 cnt; 4146 4147 /* Setup */ 4148 report_prefix_push("invalid event injection"); 4149 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4150 vmcs_write(ENT_INST_LEN, 0x00000001); 4151 4152 /* The field’s interruption type is not set to a reserved value. */ 4153 ent_intr_info = ent_intr_info_base | INTR_TYPE_RESERVED | DE_VECTOR; 4154 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4155 "RESERVED interruption type invalid [-]", 4156 ent_intr_info); 4157 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4158 test_vmx_invalid_controls(); 4159 report_prefix_pop(); 4160 4161 ent_intr_info = ent_intr_info_base | INTR_TYPE_EXT_INTR | 4162 DE_VECTOR; 4163 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4164 "RESERVED interruption type invalid [+]", 4165 ent_intr_info); 4166 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4167 test_vmx_valid_controls(); 4168 report_prefix_pop(); 4169 4170 /* If the interruption type is other event, the vector is 0. */ 4171 ent_intr_info = ent_intr_info_base | INTR_TYPE_OTHER_EVENT | DB_VECTOR; 4172 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4173 "(OTHER EVENT && vector != 0) invalid [-]", 4174 ent_intr_info); 4175 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4176 test_vmx_invalid_controls(); 4177 report_prefix_pop(); 4178 4179 /* If the interruption type is NMI, the vector is 2 (negative case). */ 4180 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | DE_VECTOR; 4181 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4182 "(NMI && vector != 2) invalid [-]", ent_intr_info); 4183 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4184 test_vmx_invalid_controls(); 4185 report_prefix_pop(); 4186 4187 /* If the interruption type is NMI, the vector is 2 (positive case). */ 4188 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | NMI_VECTOR; 4189 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4190 "(NMI && vector == 2) valid [+]", ent_intr_info); 4191 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4192 test_vmx_valid_controls(); 4193 report_prefix_pop(); 4194 4195 /* 4196 * If the interruption type 4197 * is HW exception, the vector is at most 31. 4198 */ 4199 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 0x20; 4200 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4201 "(HW exception && vector > 31) invalid [-]", 4202 ent_intr_info); 4203 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4204 test_vmx_invalid_controls(); 4205 report_prefix_pop(); 4206 4207 /* 4208 * deliver-error-code is 1 iff either 4209 * (a) the "unrestricted guest" VM-execution control is 0 4210 * (b) CR0.PE is set. 4211 */ 4212 4213 /* Assert that unrestricted guest is disabled or unsupported */ 4214 assert(!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 4215 !(secondary_save & CPU_URG)); 4216 4217 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4218 GP_VECTOR; 4219 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4220 "error code <-> (!URG || prot_mode) [-]", 4221 ent_intr_info); 4222 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4223 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4224 test_vmx_invalid_controls(); 4225 report_prefix_pop(); 4226 4227 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4228 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4229 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4230 "error code <-> (!URG || prot_mode) [+]", 4231 ent_intr_info); 4232 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4233 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4234 test_vmx_valid_controls(); 4235 report_prefix_pop(); 4236 4237 if (enable_unrestricted_guest()) 4238 goto skip_unrestricted_guest; 4239 4240 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4241 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4242 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4243 "error code <-> (!URG || prot_mode) [-]", 4244 ent_intr_info); 4245 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4246 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4247 test_vmx_invalid_controls(); 4248 report_prefix_pop(); 4249 4250 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4251 GP_VECTOR; 4252 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4253 "error code <-> (!URG || prot_mode) [-]", 4254 ent_intr_info); 4255 vmcs_write(GUEST_CR0, guest_cr0_save | X86_CR0_PE); 4256 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4257 test_vmx_invalid_controls(); 4258 report_prefix_pop(); 4259 4260 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4261 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4262 4263 skip_unrestricted_guest: 4264 vmcs_write(GUEST_CR0, guest_cr0_save); 4265 4266 /* deliver-error-code is 1 iff the interruption type is HW exception */ 4267 report_prefix_push("error code <-> HW exception"); 4268 for (cnt = 0; cnt < 8; cnt++) { 4269 u32 exception_type_mask = cnt << 8; 4270 u32 deliver_error_code_mask = 4271 exception_type_mask != INTR_TYPE_HARD_EXCEPTION ? 4272 INTR_INFO_DELIVER_CODE_MASK : 0; 4273 4274 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4275 exception_type_mask | GP_VECTOR; 4276 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4277 ent_intr_info); 4278 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4279 test_vmx_invalid_controls(); 4280 report_prefix_pop(); 4281 } 4282 report_prefix_pop(); 4283 4284 /* 4285 * deliver-error-code is 1 iff the the vector 4286 * indicates an exception that would normally deliver an error code 4287 */ 4288 report_prefix_push("error code <-> vector delivers error code"); 4289 for (cnt = 0; cnt < 32; cnt++) { 4290 bool has_error_code = false; 4291 u32 deliver_error_code_mask; 4292 4293 switch (cnt) { 4294 case DF_VECTOR: 4295 case TS_VECTOR: 4296 case NP_VECTOR: 4297 case SS_VECTOR: 4298 case GP_VECTOR: 4299 case PF_VECTOR: 4300 case AC_VECTOR: 4301 has_error_code = true; 4302 } 4303 4304 /* Negative case */ 4305 deliver_error_code_mask = has_error_code ? 4306 0 : 4307 INTR_INFO_DELIVER_CODE_MASK; 4308 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4309 INTR_TYPE_HARD_EXCEPTION | cnt; 4310 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4311 ent_intr_info); 4312 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4313 test_vmx_invalid_controls(); 4314 report_prefix_pop(); 4315 4316 /* Positive case */ 4317 deliver_error_code_mask = has_error_code ? 4318 INTR_INFO_DELIVER_CODE_MASK : 4319 0; 4320 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4321 INTR_TYPE_HARD_EXCEPTION | cnt; 4322 report_prefix_pushf("VM-entry intr info=0x%x [+]", 4323 ent_intr_info); 4324 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4325 test_vmx_valid_controls(); 4326 report_prefix_pop(); 4327 } 4328 report_prefix_pop(); 4329 4330 /* Reserved bits in the field (30:12) are 0. */ 4331 report_prefix_push("reserved bits clear"); 4332 for (cnt = 12; cnt <= 30; cnt++) { 4333 ent_intr_info = ent_intr_info_base | 4334 INTR_INFO_DELIVER_CODE_MASK | 4335 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR | 4336 (1U << cnt); 4337 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4338 ent_intr_info); 4339 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4340 test_vmx_invalid_controls(); 4341 report_prefix_pop(); 4342 } 4343 report_prefix_pop(); 4344 4345 /* 4346 * If deliver-error-code is 1 4347 * bits 31:16 of the VM-entry exception error-code field are 0. 4348 */ 4349 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4350 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4351 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4352 "VM-entry exception error code[31:16] clear", 4353 ent_intr_info); 4354 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4355 for (cnt = 16; cnt <= 31; cnt++) { 4356 ent_intr_err = 1U << cnt; 4357 report_prefix_pushf("VM-entry intr error=0x%x [-]", 4358 ent_intr_err); 4359 vmcs_write(ENT_INTR_ERROR, ent_intr_err); 4360 test_vmx_invalid_controls(); 4361 report_prefix_pop(); 4362 } 4363 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4364 report_prefix_pop(); 4365 4366 /* 4367 * If the interruption type is software interrupt, software exception, 4368 * or privileged software exception, the VM-entry instruction-length 4369 * field is in the range 0–15. 4370 */ 4371 4372 for (cnt = 0; cnt < 3; cnt++) { 4373 switch (cnt) { 4374 case 0: 4375 ent_intr_info = ent_intr_info_base | 4376 INTR_TYPE_SOFT_INTR; 4377 break; 4378 case 1: 4379 ent_intr_info = ent_intr_info_base | 4380 INTR_TYPE_SOFT_EXCEPTION; 4381 break; 4382 case 2: 4383 ent_intr_info = ent_intr_info_base | 4384 INTR_TYPE_PRIV_SW_EXCEPTION; 4385 break; 4386 } 4387 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4388 "VM-entry instruction-length check", 4389 ent_intr_info); 4390 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4391 4392 /* Instruction length set to -1 (0xFFFFFFFF) should fail */ 4393 ent_intr_len = -1; 4394 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4395 ent_intr_len); 4396 vmcs_write(ENT_INST_LEN, ent_intr_len); 4397 test_vmx_invalid_controls(); 4398 report_prefix_pop(); 4399 4400 /* Instruction length set to 16 should fail */ 4401 ent_intr_len = 0x00000010; 4402 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4403 ent_intr_len); 4404 vmcs_write(ENT_INST_LEN, 0x00000010); 4405 test_vmx_invalid_controls(); 4406 report_prefix_pop(); 4407 4408 report_prefix_pop(); 4409 } 4410 4411 /* Cleanup */ 4412 vmcs_write(ENT_INTR_INFO, ent_intr_info_save); 4413 vmcs_write(ENT_INTR_ERROR, ent_intr_error_save); 4414 vmcs_write(ENT_INST_LEN, ent_inst_len_save); 4415 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4416 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4417 vmcs_write(GUEST_CR0, guest_cr0_save); 4418 report_prefix_pop(); 4419 } 4420 4421 /* 4422 * Test interesting vTPR values for a given TPR threshold. 4423 */ 4424 static void test_vtpr_values(unsigned threshold) 4425 { 4426 try_tpr_threshold_and_vtpr(threshold, (threshold - 1) << 4); 4427 try_tpr_threshold_and_vtpr(threshold, threshold << 4); 4428 try_tpr_threshold_and_vtpr(threshold, (threshold + 1) << 4); 4429 } 4430 4431 static void try_tpr_threshold(unsigned threshold) 4432 { 4433 bool valid = true; 4434 4435 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4436 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4437 4438 if ((primary & CPU_TPR_SHADOW) && !((primary & CPU_SECONDARY) && 4439 (secondary & CPU_VINTD))) 4440 valid = !(threshold >> 4); 4441 4442 set_vtpr(-1); 4443 vmcs_write(TPR_THRESHOLD, threshold); 4444 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0xf", threshold); 4445 if (valid) 4446 test_vmx_valid_controls(); 4447 else 4448 test_vmx_invalid_controls(); 4449 report_prefix_pop(); 4450 4451 if (valid) 4452 test_vtpr_values(threshold); 4453 } 4454 4455 /* 4456 * Test interesting TPR threshold values. 4457 */ 4458 static void test_tpr_threshold_values(void) 4459 { 4460 unsigned i; 4461 4462 for (i = 0; i < 0x10; i++) 4463 try_tpr_threshold(i); 4464 for (i = 4; i < 32; i++) 4465 try_tpr_threshold(1u << i); 4466 try_tpr_threshold(-1u); 4467 try_tpr_threshold(0x7fffffff); 4468 } 4469 4470 /* 4471 * This test covers the following two VM entry checks: 4472 * 4473 * i) If the "use TPR shadow" VM-execution control is 1 and the 4474 * "virtual-interrupt delivery" VM-execution control is 0, bits 4475 * 31:4 of the TPR threshold VM-execution control field must 4476 be 0. 4477 * [Intel SDM] 4478 * 4479 * ii) If the "use TPR shadow" VM-execution control is 1, the 4480 * "virtual-interrupt delivery" VM-execution control is 0 4481 * and the "virtualize APIC accesses" VM-execution control 4482 * is 0, the value of bits 3:0 of the TPR threshold VM-execution 4483 * control field must not be greater than the value of bits 4484 * 7:4 of VTPR. 4485 * [Intel SDM] 4486 */ 4487 static void test_tpr_threshold(void) 4488 { 4489 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4490 u64 apic_virt_addr = vmcs_read(APIC_VIRT_ADDR); 4491 u64 threshold = vmcs_read(TPR_THRESHOLD); 4492 void *virtual_apic_page; 4493 4494 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) 4495 return; 4496 4497 virtual_apic_page = alloc_page(); 4498 memset(virtual_apic_page, 0xff, PAGE_SIZE); 4499 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 4500 4501 vmcs_write(CPU_EXEC_CTRL0, primary & ~(CPU_TPR_SHADOW | CPU_SECONDARY)); 4502 report_prefix_pushf("Use TPR shadow disabled, secondary controls disabled"); 4503 test_tpr_threshold_values(); 4504 report_prefix_pop(); 4505 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_TPR_SHADOW); 4506 report_prefix_pushf("Use TPR shadow enabled, secondary controls disabled"); 4507 test_tpr_threshold_values(); 4508 report_prefix_pop(); 4509 4510 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4511 (ctrl_cpu_rev[1].clr & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 4512 goto out; 4513 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4514 4515 if (ctrl_cpu_rev[1].clr & CPU_VINTD) { 4516 vmcs_write(CPU_EXEC_CTRL1, CPU_VINTD); 4517 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4518 test_tpr_threshold_values(); 4519 report_prefix_pop(); 4520 4521 vmcs_write(CPU_EXEC_CTRL0, 4522 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4523 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4524 test_tpr_threshold_values(); 4525 report_prefix_pop(); 4526 } 4527 4528 if (ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES) { 4529 vmcs_write(CPU_EXEC_CTRL0, 4530 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4531 vmcs_write(CPU_EXEC_CTRL1, CPU_VIRT_APIC_ACCESSES); 4532 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4533 test_tpr_threshold_values(); 4534 report_prefix_pop(); 4535 4536 vmcs_write(CPU_EXEC_CTRL0, 4537 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4538 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4539 test_tpr_threshold_values(); 4540 report_prefix_pop(); 4541 } 4542 4543 if ((ctrl_cpu_rev[1].clr & 4544 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) == 4545 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) { 4546 vmcs_write(CPU_EXEC_CTRL0, 4547 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4548 vmcs_write(CPU_EXEC_CTRL1, 4549 CPU_VINTD | CPU_VIRT_APIC_ACCESSES); 4550 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4551 test_tpr_threshold_values(); 4552 report_prefix_pop(); 4553 4554 vmcs_write(CPU_EXEC_CTRL0, 4555 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4556 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4557 test_tpr_threshold_values(); 4558 report_prefix_pop(); 4559 } 4560 4561 vmcs_write(CPU_EXEC_CTRL1, secondary); 4562 out: 4563 vmcs_write(TPR_THRESHOLD, threshold); 4564 vmcs_write(APIC_VIRT_ADDR, apic_virt_addr); 4565 vmcs_write(CPU_EXEC_CTRL0, primary); 4566 } 4567 4568 /* 4569 * This test verifies the following two vmentry checks: 4570 * 4571 * If the "NMI exiting" VM-execution control is 0, "Virtual NMIs" 4572 * VM-execution control must be 0. 4573 * [Intel SDM] 4574 * 4575 * If the “virtual NMIs” VM-execution control is 0, the “NMI-window 4576 * exiting” VM-execution control must be 0. 4577 * [Intel SDM] 4578 */ 4579 static void test_nmi_ctrls(void) 4580 { 4581 u32 pin_ctrls, cpu_ctrls0, test_pin_ctrls, test_cpu_ctrls0; 4582 4583 if ((ctrl_pin_rev.clr & (PIN_NMI | PIN_VIRT_NMI)) != 4584 (PIN_NMI | PIN_VIRT_NMI)) { 4585 printf("NMI exiting and Virtual NMIs are not supported !\n"); 4586 return; 4587 } 4588 4589 /* Save the controls so that we can restore them after our tests */ 4590 pin_ctrls = vmcs_read(PIN_CONTROLS); 4591 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 4592 4593 test_pin_ctrls = pin_ctrls & ~(PIN_NMI | PIN_VIRT_NMI); 4594 test_cpu_ctrls0 = cpu_ctrls0 & ~CPU_NMI_WINDOW; 4595 4596 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4597 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs disabled"); 4598 test_vmx_valid_controls(); 4599 report_prefix_pop(); 4600 4601 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_VIRT_NMI); 4602 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs enabled"); 4603 test_vmx_invalid_controls(); 4604 report_prefix_pop(); 4605 4606 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4607 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs enabled"); 4608 test_vmx_valid_controls(); 4609 report_prefix_pop(); 4610 4611 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_NMI); 4612 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs disabled"); 4613 test_vmx_valid_controls(); 4614 report_prefix_pop(); 4615 4616 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 4617 report_info("NMI-window exiting is not supported, skipping..."); 4618 goto done; 4619 } 4620 4621 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4622 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4623 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting enabled"); 4624 test_vmx_invalid_controls(); 4625 report_prefix_pop(); 4626 4627 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4628 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4629 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting disabled"); 4630 test_vmx_valid_controls(); 4631 report_prefix_pop(); 4632 4633 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4634 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4635 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting enabled"); 4636 test_vmx_valid_controls(); 4637 report_prefix_pop(); 4638 4639 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4640 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4641 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting disabled"); 4642 test_vmx_valid_controls(); 4643 report_prefix_pop(); 4644 4645 /* Restore the controls to their original values */ 4646 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 4647 done: 4648 vmcs_write(PIN_CONTROLS, pin_ctrls); 4649 } 4650 4651 static void test_eptp_ad_bit(u64 eptp, bool ctrl) 4652 { 4653 vmcs_write(EPTP, eptp); 4654 report_prefix_pushf("Enable-EPT enabled; EPT accessed and dirty flag %s", 4655 (eptp & EPTP_AD_FLAG) ? "1": "0"); 4656 if (ctrl) 4657 test_vmx_valid_controls(); 4658 else 4659 test_vmx_invalid_controls(); 4660 report_prefix_pop(); 4661 4662 } 4663 4664 /* 4665 * 1. If the "enable EPT" VM-execution control is 1, the "EPTP VM-execution" 4666 * control field must satisfy the following checks: 4667 * 4668 * - The EPT memory type (bits 2:0) must be a value supported by the 4669 * processor as indicated in the IA32_VMX_EPT_VPID_CAP MSR. 4670 * - Bits 5:3 (1 less than the EPT page-walk length) must be 3, 4671 * indicating an EPT page-walk length of 4. 4672 * - Bit 6 (enable bit for accessed and dirty flags for EPT) must be 4673 * 0 if bit 21 of the IA32_VMX_EPT_VPID_CAP MSR is read as 0, 4674 * indicating that the processor does not support accessed and dirty 4675 * dirty flags for EPT. 4676 * - Reserved bits 11:7 and 63:N (where N is the processor's 4677 * physical-address width) must all be 0. 4678 * 4679 * 2. If the "unrestricted guest" VM-execution control is 1, the 4680 * "enable EPT" VM-execution control must also be 1. 4681 */ 4682 static void test_ept_eptp(void) 4683 { 4684 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4685 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4686 u64 eptp_saved = vmcs_read(EPTP); 4687 u32 primary = primary_saved; 4688 u32 secondary = secondary_saved; 4689 u64 msr, eptp = eptp_saved; 4690 bool un_cache = false; 4691 bool wr_bk = false; 4692 bool ctrl; 4693 u32 i, maxphysaddr; 4694 u64 j, resv_bits_mask = 0; 4695 4696 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4697 (ctrl_cpu_rev[1].clr & CPU_EPT))) { 4698 printf("\"CPU secondary\" and/or \"enable EPT\" execution controls are not supported !\n"); 4699 return; 4700 } 4701 4702 /* 4703 * Memory type (bits 2:0) 4704 */ 4705 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 4706 if (msr & EPT_CAP_UC) 4707 un_cache = true; 4708 if (msr & EPT_CAP_WB) 4709 wr_bk = true; 4710 4711 primary |= CPU_SECONDARY; 4712 vmcs_write(CPU_EXEC_CTRL0, primary); 4713 secondary |= CPU_EPT; 4714 vmcs_write(CPU_EXEC_CTRL1, secondary); 4715 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4716 (3ul << EPTP_PG_WALK_LEN_SHIFT); 4717 vmcs_write(EPTP, eptp); 4718 4719 for (i = 0; i < 8; i++) { 4720 if (i == 0) { 4721 if (un_cache) { 4722 report_info("EPT paging structure memory-type is Un-cacheable\n"); 4723 ctrl = true; 4724 } else { 4725 ctrl = false; 4726 } 4727 } else if (i == 6) { 4728 if (wr_bk) { 4729 report_info("EPT paging structure memory-type is Write-back\n"); 4730 ctrl = true; 4731 } else { 4732 ctrl = false; 4733 } 4734 } else { 4735 ctrl = false; 4736 } 4737 4738 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | i; 4739 vmcs_write(EPTP, eptp); 4740 report_prefix_pushf("Enable-EPT enabled; EPT memory type %lu", 4741 eptp & EPT_MEM_TYPE_MASK); 4742 if (ctrl) 4743 test_vmx_valid_controls(); 4744 else 4745 test_vmx_invalid_controls(); 4746 report_prefix_pop(); 4747 } 4748 4749 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | 6ul; 4750 4751 /* 4752 * Page walk length (bits 5:3) 4753 */ 4754 for (i = 0; i < 8; i++) { 4755 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4756 (i << EPTP_PG_WALK_LEN_SHIFT); 4757 if (i == 3) 4758 ctrl = true; 4759 else 4760 ctrl = false; 4761 4762 vmcs_write(EPTP, eptp); 4763 report_prefix_pushf("Enable-EPT enabled; EPT page walk length %lu", 4764 eptp & EPTP_PG_WALK_LEN_MASK); 4765 if (ctrl) 4766 test_vmx_valid_controls(); 4767 else 4768 test_vmx_invalid_controls(); 4769 report_prefix_pop(); 4770 } 4771 4772 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4773 3ul << EPTP_PG_WALK_LEN_SHIFT; 4774 4775 /* 4776 * Accessed and dirty flag (bit 6) 4777 */ 4778 if (msr & EPT_CAP_AD_FLAG) { 4779 report_info("Processor supports accessed and dirty flag"); 4780 eptp &= ~EPTP_AD_FLAG; 4781 test_eptp_ad_bit(eptp, true); 4782 4783 eptp |= EPTP_AD_FLAG; 4784 test_eptp_ad_bit(eptp, true); 4785 } else { 4786 report_info("Processor does not supports accessed and dirty flag"); 4787 eptp &= ~EPTP_AD_FLAG; 4788 test_eptp_ad_bit(eptp, true); 4789 4790 eptp |= EPTP_AD_FLAG; 4791 test_eptp_ad_bit(eptp, false); 4792 } 4793 4794 /* 4795 * Reserved bits [11:7] and [63:N] 4796 */ 4797 for (i = 0; i < 32; i++) { 4798 eptp = (eptp & 4799 ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)) | 4800 (i << EPTP_RESERV_BITS_SHIFT); 4801 vmcs_write(EPTP, eptp); 4802 report_prefix_pushf("Enable-EPT enabled; reserved bits [11:7] %lu", 4803 (eptp >> EPTP_RESERV_BITS_SHIFT) & 4804 EPTP_RESERV_BITS_MASK); 4805 if (i == 0) 4806 test_vmx_valid_controls(); 4807 else 4808 test_vmx_invalid_controls(); 4809 report_prefix_pop(); 4810 } 4811 4812 eptp = (eptp & ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)); 4813 4814 maxphysaddr = cpuid_maxphyaddr(); 4815 for (i = 0; i < (63 - maxphysaddr + 1); i++) { 4816 resv_bits_mask |= 1ul << i; 4817 } 4818 4819 for (j = maxphysaddr - 1; j <= 63; j++) { 4820 eptp = (eptp & ~(resv_bits_mask << maxphysaddr)) | 4821 (j < maxphysaddr ? 0 : 1ul << j); 4822 vmcs_write(EPTP, eptp); 4823 report_prefix_pushf("Enable-EPT enabled; reserved bits [63:N] %lu", 4824 (eptp >> maxphysaddr) & resv_bits_mask); 4825 if (j < maxphysaddr) 4826 test_vmx_valid_controls(); 4827 else 4828 test_vmx_invalid_controls(); 4829 report_prefix_pop(); 4830 } 4831 4832 secondary &= ~(CPU_EPT | CPU_URG); 4833 vmcs_write(CPU_EXEC_CTRL1, secondary); 4834 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest disabled"); 4835 test_vmx_valid_controls(); 4836 report_prefix_pop(); 4837 4838 if (!(ctrl_cpu_rev[1].clr & CPU_URG)) 4839 goto skip_unrestricted_guest; 4840 4841 secondary |= CPU_URG; 4842 vmcs_write(CPU_EXEC_CTRL1, secondary); 4843 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest enabled"); 4844 test_vmx_invalid_controls(); 4845 report_prefix_pop(); 4846 4847 secondary |= CPU_EPT; 4848 setup_dummy_ept(); 4849 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest enabled"); 4850 test_vmx_valid_controls(); 4851 report_prefix_pop(); 4852 4853 skip_unrestricted_guest: 4854 secondary &= ~CPU_URG; 4855 vmcs_write(CPU_EXEC_CTRL1, secondary); 4856 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest disabled"); 4857 test_vmx_valid_controls(); 4858 report_prefix_pop(); 4859 4860 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4861 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4862 vmcs_write(EPTP, eptp_saved); 4863 } 4864 4865 /* 4866 * If the 'enable PML' VM-execution control is 1, the 'enable EPT' 4867 * VM-execution control must also be 1. In addition, the PML address 4868 * must satisfy the following checks: 4869 * 4870 * * Bits 11:0 of the address must be 0. 4871 * * The address should not set any bits beyond the processor's 4872 * physical-address width. 4873 * 4874 * [Intel SDM] 4875 */ 4876 static void test_pml(void) 4877 { 4878 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4879 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4880 u32 primary = primary_saved; 4881 u32 secondary = secondary_saved; 4882 4883 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4884 (ctrl_cpu_rev[1].clr & CPU_EPT) && (ctrl_cpu_rev[1].clr & CPU_PML))) { 4885 printf("\"Secondary execution\" control or \"enable EPT\" control or \"enable PML\" control is not supported !\n"); 4886 return; 4887 } 4888 4889 primary |= CPU_SECONDARY; 4890 vmcs_write(CPU_EXEC_CTRL0, primary); 4891 secondary &= ~(CPU_PML | CPU_EPT); 4892 vmcs_write(CPU_EXEC_CTRL1, secondary); 4893 report_prefix_pushf("enable-PML disabled, enable-EPT disabled"); 4894 test_vmx_valid_controls(); 4895 report_prefix_pop(); 4896 4897 secondary |= CPU_PML; 4898 vmcs_write(CPU_EXEC_CTRL1, secondary); 4899 report_prefix_pushf("enable-PML enabled, enable-EPT disabled"); 4900 test_vmx_invalid_controls(); 4901 report_prefix_pop(); 4902 4903 secondary |= CPU_EPT; 4904 setup_dummy_ept(); 4905 report_prefix_pushf("enable-PML enabled, enable-EPT enabled"); 4906 test_vmx_valid_controls(); 4907 report_prefix_pop(); 4908 4909 secondary &= ~CPU_PML; 4910 vmcs_write(CPU_EXEC_CTRL1, secondary); 4911 report_prefix_pushf("enable-PML disabled, enable EPT enabled"); 4912 test_vmx_valid_controls(); 4913 report_prefix_pop(); 4914 4915 test_vmcs_addr_reference(CPU_PML, PMLADDR, "PML address", "PML", 4916 PAGE_SIZE, false, false); 4917 4918 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4919 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4920 } 4921 4922 /* 4923 * If the "activate VMX-preemption timer" VM-execution control is 0, the 4924 * the "save VMX-preemption timer value" VM-exit control must also be 0. 4925 * 4926 * [Intel SDM] 4927 */ 4928 static void test_vmx_preemption_timer(void) 4929 { 4930 u32 saved_pin = vmcs_read(PIN_CONTROLS); 4931 u32 saved_exit = vmcs_read(EXI_CONTROLS); 4932 u32 pin = saved_pin; 4933 u32 exit = saved_exit; 4934 4935 if (!((ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) || 4936 (ctrl_pin_rev.clr & PIN_PREEMPT))) { 4937 printf("\"Save-VMX-preemption-timer\" control and/or \"Enable-VMX-preemption-timer\" control is not supported\n"); 4938 return; 4939 } 4940 4941 pin |= PIN_PREEMPT; 4942 vmcs_write(PIN_CONTROLS, pin); 4943 exit &= ~EXI_SAVE_PREEMPT; 4944 vmcs_write(EXI_CONTROLS, exit); 4945 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer disabled"); 4946 test_vmx_valid_controls(); 4947 report_prefix_pop(); 4948 4949 exit |= EXI_SAVE_PREEMPT; 4950 vmcs_write(EXI_CONTROLS, exit); 4951 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer enabled"); 4952 test_vmx_valid_controls(); 4953 report_prefix_pop(); 4954 4955 pin &= ~PIN_PREEMPT; 4956 vmcs_write(PIN_CONTROLS, pin); 4957 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer enabled"); 4958 test_vmx_invalid_controls(); 4959 report_prefix_pop(); 4960 4961 exit &= ~EXI_SAVE_PREEMPT; 4962 vmcs_write(EXI_CONTROLS, exit); 4963 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer disabled"); 4964 test_vmx_valid_controls(); 4965 report_prefix_pop(); 4966 4967 vmcs_write(PIN_CONTROLS, saved_pin); 4968 vmcs_write(EXI_CONTROLS, saved_exit); 4969 } 4970 4971 extern unsigned char test_mtf1; 4972 extern unsigned char test_mtf2; 4973 extern unsigned char test_mtf3; 4974 4975 static void test_mtf_guest(void) 4976 { 4977 asm ("vmcall;\n\t" 4978 "out %al, $0x80;\n\t" 4979 "test_mtf1:\n\t" 4980 "vmcall;\n\t" 4981 "out %al, $0x80;\n\t" 4982 "test_mtf2:\n\t" 4983 /* 4984 * Prepare for the 'MOV CR3' test. Attempt to induce a 4985 * general-protection fault by moving a non-canonical address into 4986 * CR3. The 'MOV CR3' instruction does not take an imm64 operand, 4987 * so we must MOV the desired value into a register first. 4988 * 4989 * MOV RAX is done before the VMCALL such that MTF is only enabled 4990 * for the instruction under test. 4991 */ 4992 "mov $0x8000000000000000, %rax;\n\t" 4993 "vmcall;\n\t" 4994 "mov %rax, %cr3;\n\t" 4995 "test_mtf3:\n\t" 4996 "vmcall;\n\t" 4997 /* 4998 * ICEBP/INT1 instruction. Though the instruction is now 4999 * documented, don't rely on assemblers enumerating the 5000 * instruction. Resort to hand assembly. 5001 */ 5002 ".byte 0xf1;\n\t"); 5003 } 5004 5005 static void test_mtf_gp_handler(struct ex_regs *regs) 5006 { 5007 regs->rip = (unsigned long) &test_mtf3; 5008 } 5009 5010 static void test_mtf_db_handler(struct ex_regs *regs) 5011 { 5012 } 5013 5014 static void enable_mtf(void) 5015 { 5016 u32 ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 5017 5018 vmcs_write(CPU_EXEC_CTRL0, ctrl0 | CPU_MTF); 5019 } 5020 5021 static void disable_mtf(void) 5022 { 5023 u32 ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 5024 5025 vmcs_write(CPU_EXEC_CTRL0, ctrl0 & ~CPU_MTF); 5026 } 5027 5028 static void enable_tf(void) 5029 { 5030 unsigned long rflags = vmcs_read(GUEST_RFLAGS); 5031 5032 vmcs_write(GUEST_RFLAGS, rflags | X86_EFLAGS_TF); 5033 } 5034 5035 static void disable_tf(void) 5036 { 5037 unsigned long rflags = vmcs_read(GUEST_RFLAGS); 5038 5039 vmcs_write(GUEST_RFLAGS, rflags & ~X86_EFLAGS_TF); 5040 } 5041 5042 static void report_mtf(const char *insn_name, unsigned long exp_rip) 5043 { 5044 unsigned long rip = vmcs_read(GUEST_RIP); 5045 5046 assert_exit_reason(VMX_MTF); 5047 report(rip == exp_rip, "MTF VM-exit after %s instruction. RIP: 0x%lx (expected 0x%lx)", 5048 insn_name, rip, exp_rip); 5049 } 5050 5051 static void vmx_mtf_test(void) 5052 { 5053 unsigned long pending_dbg; 5054 handler old_gp, old_db; 5055 5056 if (!(ctrl_cpu_rev[0].clr & CPU_MTF)) { 5057 printf("CPU does not support the 'monitor trap flag' processor-based VM-execution control.\n"); 5058 return; 5059 } 5060 5061 test_set_guest(test_mtf_guest); 5062 5063 /* Expect an MTF VM-exit after OUT instruction */ 5064 enter_guest(); 5065 skip_exit_vmcall(); 5066 5067 enable_mtf(); 5068 enter_guest(); 5069 report_mtf("OUT", (unsigned long) &test_mtf1); 5070 disable_mtf(); 5071 5072 /* 5073 * Concurrent #DB trap and MTF on instruction boundary. Expect MTF 5074 * VM-exit with populated 'pending debug exceptions' VMCS field. 5075 */ 5076 enter_guest(); 5077 skip_exit_vmcall(); 5078 5079 enable_mtf(); 5080 enable_tf(); 5081 5082 enter_guest(); 5083 report_mtf("OUT", (unsigned long) &test_mtf2); 5084 pending_dbg = vmcs_read(GUEST_PENDING_DEBUG); 5085 report(pending_dbg & DR_STEP, 5086 "'pending debug exceptions' field after MTF VM-exit: 0x%lx (expected 0x%lx)", 5087 pending_dbg, (unsigned long) DR_STEP); 5088 5089 disable_mtf(); 5090 disable_tf(); 5091 vmcs_write(GUEST_PENDING_DEBUG, 0); 5092 5093 /* 5094 * #GP exception takes priority over MTF. Expect MTF VM-exit with RIP 5095 * advanced to first instruction of #GP handler. 5096 */ 5097 enter_guest(); 5098 skip_exit_vmcall(); 5099 5100 old_gp = handle_exception(GP_VECTOR, test_mtf_gp_handler); 5101 5102 enable_mtf(); 5103 enter_guest(); 5104 report_mtf("MOV CR3", (unsigned long) get_idt_addr(&boot_idt[GP_VECTOR])); 5105 disable_mtf(); 5106 5107 /* 5108 * Concurrent MTF and privileged software exception (i.e. ICEBP/INT1). 5109 * MTF should follow the delivery of #DB trap, though the SDM doesn't 5110 * provide clear indication of the relative priority. 5111 */ 5112 enter_guest(); 5113 skip_exit_vmcall(); 5114 5115 handle_exception(GP_VECTOR, old_gp); 5116 old_db = handle_exception(DB_VECTOR, test_mtf_db_handler); 5117 5118 enable_mtf(); 5119 enter_guest(); 5120 report_mtf("INT1", (unsigned long) get_idt_addr(&boot_idt[DB_VECTOR])); 5121 disable_mtf(); 5122 5123 enter_guest(); 5124 handle_exception(DB_VECTOR, old_db); 5125 } 5126 5127 /* 5128 * Tests for VM-execution control fields 5129 */ 5130 static void test_vm_execution_ctls(void) 5131 { 5132 test_pin_based_ctls(); 5133 test_primary_processor_based_ctls(); 5134 test_secondary_processor_based_ctls(); 5135 test_cr3_targets(); 5136 test_io_bitmaps(); 5137 test_msr_bitmap(); 5138 test_apic_ctls(); 5139 test_tpr_threshold(); 5140 test_nmi_ctrls(); 5141 test_pml(); 5142 test_vpid(); 5143 test_ept_eptp(); 5144 test_vmx_preemption_timer(); 5145 } 5146 5147 /* 5148 * The following checks are performed for the VM-entry MSR-load address if 5149 * the VM-entry MSR-load count field is non-zero: 5150 * 5151 * - The lower 4 bits of the VM-entry MSR-load address must be 0. 5152 * The address should not set any bits beyond the processor’s 5153 * physical-address width. 5154 * 5155 * - The address of the last byte in the VM-entry MSR-load area 5156 * should not set any bits beyond the processor’s physical-address 5157 * width. The address of this last byte is VM-entry MSR-load address 5158 * + (MSR count * 16) - 1. (The arithmetic used for the computation 5159 * uses more bits than the processor’s physical-address width.) 5160 * 5161 * 5162 * [Intel SDM] 5163 */ 5164 static void test_entry_msr_load(void) 5165 { 5166 entry_msr_load = alloc_page(); 5167 u64 tmp; 5168 u32 entry_msr_ld_cnt = 1; 5169 int i; 5170 u32 addr_len = 64; 5171 5172 vmcs_write(ENT_MSR_LD_CNT, entry_msr_ld_cnt); 5173 5174 /* Check first 4 bits of VM-entry MSR-load address */ 5175 for (i = 0; i < 4; i++) { 5176 tmp = (u64)entry_msr_load | 1ull << i; 5177 vmcs_write(ENTER_MSR_LD_ADDR, tmp); 5178 report_prefix_pushf("VM-entry MSR-load addr [4:0] %lx", 5179 tmp & 0xf); 5180 test_vmx_invalid_controls(); 5181 report_prefix_pop(); 5182 } 5183 5184 if (basic.val & (1ul << 48)) 5185 addr_len = 32; 5186 5187 test_vmcs_addr_values("VM-entry-MSR-load address", 5188 ENTER_MSR_LD_ADDR, 16, false, false, 5189 4, addr_len - 1); 5190 5191 /* 5192 * Check last byte of VM-entry MSR-load address 5193 */ 5194 entry_msr_load = (struct vmx_msr_entry *)((u64)entry_msr_load & ~0xf); 5195 5196 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 5197 i < 64; i++) { 5198 tmp = ((u64)entry_msr_load + entry_msr_ld_cnt * 16 - 1) | 5199 1ul << i; 5200 vmcs_write(ENTER_MSR_LD_ADDR, 5201 tmp - (entry_msr_ld_cnt * 16 - 1)); 5202 test_vmx_invalid_controls(); 5203 } 5204 5205 vmcs_write(ENT_MSR_LD_CNT, 2); 5206 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 5207 test_vmx_invalid_controls(); 5208 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 5209 test_vmx_valid_controls(); 5210 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 5211 test_vmx_valid_controls(); 5212 } 5213 5214 static struct vmx_state_area_test_data { 5215 u32 msr; 5216 u64 exp; 5217 bool enabled; 5218 } vmx_state_area_test_data; 5219 5220 static void guest_state_test_main(void) 5221 { 5222 u64 obs; 5223 struct vmx_state_area_test_data *data = &vmx_state_area_test_data; 5224 5225 while (1) { 5226 if (vmx_get_test_stage() == 2) 5227 break; 5228 5229 if (data->enabled) { 5230 obs = rdmsr(data->msr); 5231 report(data->exp == obs, 5232 "Guest state is 0x%lx (expected 0x%lx)", 5233 obs, data->exp); 5234 } 5235 5236 vmcall(); 5237 } 5238 5239 asm volatile("fnop"); 5240 } 5241 5242 static void advance_guest_state_test(void) 5243 { 5244 u32 reason = vmcs_read(EXI_REASON); 5245 if (! (reason & 0x80000000)) { 5246 u64 guest_rip = vmcs_read(GUEST_RIP); 5247 u32 insn_len = vmcs_read(EXI_INST_LEN); 5248 vmcs_write(GUEST_RIP, guest_rip + insn_len); 5249 } 5250 } 5251 5252 static void report_guest_state_test(const char *test, u32 xreason, 5253 u64 field, const char * field_name) 5254 { 5255 u32 reason = vmcs_read(EXI_REASON); 5256 5257 report(reason == xreason, "%s, %s %lx", test, field_name, field); 5258 advance_guest_state_test(); 5259 } 5260 5261 /* 5262 * Tests for VM-entry control fields 5263 */ 5264 static void test_vm_entry_ctls(void) 5265 { 5266 test_invalid_event_injection(); 5267 test_entry_msr_load(); 5268 } 5269 5270 /* 5271 * The following checks are performed for the VM-exit MSR-store address if 5272 * the VM-exit MSR-store count field is non-zero: 5273 * 5274 * - The lower 4 bits of the VM-exit MSR-store address must be 0. 5275 * The address should not set any bits beyond the processor’s 5276 * physical-address width. 5277 * 5278 * - The address of the last byte in the VM-exit MSR-store area 5279 * should not set any bits beyond the processor’s physical-address 5280 * width. The address of this last byte is VM-exit MSR-store address 5281 * + (MSR count * 16) - 1. (The arithmetic used for the computation 5282 * uses more bits than the processor’s physical-address width.) 5283 * 5284 * If IA32_VMX_BASIC[48] is read as 1, neither address should set any bits 5285 * in the range 63:32. 5286 * 5287 * [Intel SDM] 5288 */ 5289 static void test_exit_msr_store(void) 5290 { 5291 exit_msr_store = alloc_page(); 5292 u64 tmp; 5293 u32 exit_msr_st_cnt = 1; 5294 int i; 5295 u32 addr_len = 64; 5296 5297 vmcs_write(EXI_MSR_ST_CNT, exit_msr_st_cnt); 5298 5299 /* Check first 4 bits of VM-exit MSR-store address */ 5300 for (i = 0; i < 4; i++) { 5301 tmp = (u64)exit_msr_store | 1ull << i; 5302 vmcs_write(EXIT_MSR_ST_ADDR, tmp); 5303 report_prefix_pushf("VM-exit MSR-store addr [4:0] %lx", 5304 tmp & 0xf); 5305 test_vmx_invalid_controls(); 5306 report_prefix_pop(); 5307 } 5308 5309 if (basic.val & (1ul << 48)) 5310 addr_len = 32; 5311 5312 test_vmcs_addr_values("VM-exit-MSR-store address", 5313 EXIT_MSR_ST_ADDR, 16, false, false, 5314 4, addr_len - 1); 5315 5316 /* 5317 * Check last byte of VM-exit MSR-store address 5318 */ 5319 exit_msr_store = (struct vmx_msr_entry *)((u64)exit_msr_store & ~0xf); 5320 5321 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 5322 i < 64; i++) { 5323 tmp = ((u64)exit_msr_store + exit_msr_st_cnt * 16 - 1) | 5324 1ul << i; 5325 vmcs_write(EXIT_MSR_ST_ADDR, 5326 tmp - (exit_msr_st_cnt * 16 - 1)); 5327 test_vmx_invalid_controls(); 5328 } 5329 5330 vmcs_write(EXI_MSR_ST_CNT, 2); 5331 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 5332 test_vmx_invalid_controls(); 5333 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 5334 test_vmx_valid_controls(); 5335 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 5336 test_vmx_valid_controls(); 5337 } 5338 5339 /* 5340 * Tests for VM-exit controls 5341 */ 5342 static void test_vm_exit_ctls(void) 5343 { 5344 test_exit_msr_store(); 5345 } 5346 5347 /* 5348 * Check that the virtual CPU checks all of the VMX controls as 5349 * documented in the Intel SDM. 5350 */ 5351 static void vmx_controls_test(void) 5352 { 5353 /* 5354 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 5355 * fail due to invalid guest state, should we make it that 5356 * far. 5357 */ 5358 vmcs_write(GUEST_RFLAGS, 0); 5359 5360 test_vm_execution_ctls(); 5361 test_vm_exit_ctls(); 5362 test_vm_entry_ctls(); 5363 } 5364 5365 struct apic_reg_virt_config { 5366 bool apic_register_virtualization; 5367 bool use_tpr_shadow; 5368 bool virtualize_apic_accesses; 5369 bool virtualize_x2apic_mode; 5370 bool activate_secondary_controls; 5371 }; 5372 5373 struct apic_reg_test { 5374 const char *name; 5375 struct apic_reg_virt_config apic_reg_virt_config; 5376 }; 5377 5378 struct apic_reg_virt_expectation { 5379 enum Reason rd_exit_reason; 5380 enum Reason wr_exit_reason; 5381 u32 val; 5382 u32 (*virt_fn)(u32); 5383 5384 /* 5385 * If false, accessing the APIC access address from L2 is treated as a 5386 * normal memory operation, rather than triggering virtualization. 5387 */ 5388 bool virtualize_apic_accesses; 5389 }; 5390 5391 static u32 apic_virt_identity(u32 val) 5392 { 5393 return val; 5394 } 5395 5396 static u32 apic_virt_nibble1(u32 val) 5397 { 5398 return val & 0xf0; 5399 } 5400 5401 static u32 apic_virt_byte3(u32 val) 5402 { 5403 return val & (0xff << 24); 5404 } 5405 5406 static bool apic_reg_virt_exit_expectation( 5407 u32 reg, struct apic_reg_virt_config *config, 5408 struct apic_reg_virt_expectation *expectation) 5409 { 5410 /* Good configs, where some L2 APIC accesses are virtualized. */ 5411 bool virtualize_apic_accesses_only = 5412 config->virtualize_apic_accesses && 5413 !config->use_tpr_shadow && 5414 !config->apic_register_virtualization && 5415 !config->virtualize_x2apic_mode && 5416 config->activate_secondary_controls; 5417 bool virtualize_apic_accesses_and_use_tpr_shadow = 5418 config->virtualize_apic_accesses && 5419 config->use_tpr_shadow && 5420 !config->apic_register_virtualization && 5421 !config->virtualize_x2apic_mode && 5422 config->activate_secondary_controls; 5423 bool apic_register_virtualization = 5424 config->virtualize_apic_accesses && 5425 config->use_tpr_shadow && 5426 config->apic_register_virtualization && 5427 !config->virtualize_x2apic_mode && 5428 config->activate_secondary_controls; 5429 5430 expectation->val = MAGIC_VAL_1; 5431 expectation->virt_fn = apic_virt_identity; 5432 expectation->virtualize_apic_accesses = 5433 config->virtualize_apic_accesses && 5434 config->activate_secondary_controls; 5435 if (virtualize_apic_accesses_only) { 5436 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5437 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5438 } else if (virtualize_apic_accesses_and_use_tpr_shadow) { 5439 switch (reg) { 5440 case APIC_TASKPRI: 5441 expectation->rd_exit_reason = VMX_VMCALL; 5442 expectation->wr_exit_reason = VMX_VMCALL; 5443 expectation->virt_fn = apic_virt_nibble1; 5444 break; 5445 default: 5446 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5447 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5448 } 5449 } else if (apic_register_virtualization) { 5450 expectation->rd_exit_reason = VMX_VMCALL; 5451 5452 switch (reg) { 5453 case APIC_ID: 5454 case APIC_EOI: 5455 case APIC_LDR: 5456 case APIC_DFR: 5457 case APIC_SPIV: 5458 case APIC_ESR: 5459 case APIC_ICR: 5460 case APIC_LVTT: 5461 case APIC_LVTTHMR: 5462 case APIC_LVTPC: 5463 case APIC_LVT0: 5464 case APIC_LVT1: 5465 case APIC_LVTERR: 5466 case APIC_TMICT: 5467 case APIC_TDCR: 5468 expectation->wr_exit_reason = VMX_APIC_WRITE; 5469 break; 5470 case APIC_LVR: 5471 case APIC_ISR ... APIC_ISR + 0x70: 5472 case APIC_TMR ... APIC_TMR + 0x70: 5473 case APIC_IRR ... APIC_IRR + 0x70: 5474 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5475 break; 5476 case APIC_TASKPRI: 5477 expectation->wr_exit_reason = VMX_VMCALL; 5478 expectation->virt_fn = apic_virt_nibble1; 5479 break; 5480 case APIC_ICR2: 5481 expectation->wr_exit_reason = VMX_VMCALL; 5482 expectation->virt_fn = apic_virt_byte3; 5483 break; 5484 default: 5485 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5486 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5487 } 5488 } else if (!expectation->virtualize_apic_accesses) { 5489 /* 5490 * No APIC registers are directly virtualized. This includes 5491 * VTPR, which can be virtualized through MOV to/from CR8 via 5492 * the use TPR shadow control, but not through directly 5493 * accessing VTPR. 5494 */ 5495 expectation->rd_exit_reason = VMX_VMCALL; 5496 expectation->wr_exit_reason = VMX_VMCALL; 5497 } else { 5498 printf("Cannot parse APIC register virtualization config:\n" 5499 "\tvirtualize_apic_accesses: %d\n" 5500 "\tuse_tpr_shadow: %d\n" 5501 "\tapic_register_virtualization: %d\n" 5502 "\tvirtualize_x2apic_mode: %d\n" 5503 "\tactivate_secondary_controls: %d\n", 5504 config->virtualize_apic_accesses, 5505 config->use_tpr_shadow, 5506 config->apic_register_virtualization, 5507 config->virtualize_x2apic_mode, 5508 config->activate_secondary_controls); 5509 5510 return false; 5511 } 5512 5513 return true; 5514 } 5515 5516 struct apic_reg_test apic_reg_tests[] = { 5517 /* Good configs, where some L2 APIC accesses are virtualized. */ 5518 { 5519 .name = "Virtualize APIC accesses", 5520 .apic_reg_virt_config = { 5521 .virtualize_apic_accesses = true, 5522 .use_tpr_shadow = false, 5523 .apic_register_virtualization = false, 5524 .virtualize_x2apic_mode = false, 5525 .activate_secondary_controls = true, 5526 }, 5527 }, 5528 { 5529 .name = "Virtualize APIC accesses + Use TPR shadow", 5530 .apic_reg_virt_config = { 5531 .virtualize_apic_accesses = true, 5532 .use_tpr_shadow = true, 5533 .apic_register_virtualization = false, 5534 .virtualize_x2apic_mode = false, 5535 .activate_secondary_controls = true, 5536 }, 5537 }, 5538 { 5539 .name = "APIC-register virtualization", 5540 .apic_reg_virt_config = { 5541 .virtualize_apic_accesses = true, 5542 .use_tpr_shadow = true, 5543 .apic_register_virtualization = true, 5544 .virtualize_x2apic_mode = false, 5545 .activate_secondary_controls = true, 5546 }, 5547 }, 5548 5549 /* 5550 * Test that the secondary processor-based VM-execution controls are 5551 * correctly ignored when "activate secondary controls" is disabled. 5552 */ 5553 { 5554 .name = "Activate secondary controls off", 5555 .apic_reg_virt_config = { 5556 .virtualize_apic_accesses = true, 5557 .use_tpr_shadow = false, 5558 .apic_register_virtualization = true, 5559 .virtualize_x2apic_mode = true, 5560 .activate_secondary_controls = false, 5561 }, 5562 }, 5563 { 5564 .name = "Activate secondary controls off + Use TPR shadow", 5565 .apic_reg_virt_config = { 5566 .virtualize_apic_accesses = true, 5567 .use_tpr_shadow = true, 5568 .apic_register_virtualization = true, 5569 .virtualize_x2apic_mode = true, 5570 .activate_secondary_controls = false, 5571 }, 5572 }, 5573 5574 /* 5575 * Test that the APIC access address is treated like an arbitrary memory 5576 * address when "virtualize APIC accesses" is disabled. 5577 */ 5578 { 5579 .name = "Virtualize APIC accesses off + Use TPR shadow", 5580 .apic_reg_virt_config = { 5581 .virtualize_apic_accesses = false, 5582 .use_tpr_shadow = true, 5583 .apic_register_virtualization = true, 5584 .virtualize_x2apic_mode = true, 5585 .activate_secondary_controls = true, 5586 }, 5587 }, 5588 5589 /* 5590 * Test that VM entry fails due to invalid controls when 5591 * "APIC-register virtualization" is enabled while "use TPR shadow" is 5592 * disabled. 5593 */ 5594 { 5595 .name = "APIC-register virtualization + Use TPR shadow off", 5596 .apic_reg_virt_config = { 5597 .virtualize_apic_accesses = true, 5598 .use_tpr_shadow = false, 5599 .apic_register_virtualization = true, 5600 .virtualize_x2apic_mode = false, 5601 .activate_secondary_controls = true, 5602 }, 5603 }, 5604 5605 /* 5606 * Test that VM entry fails due to invalid controls when 5607 * "Virtualize x2APIC mode" is enabled while "use TPR shadow" is 5608 * disabled. 5609 */ 5610 { 5611 .name = "Virtualize x2APIC mode + Use TPR shadow off", 5612 .apic_reg_virt_config = { 5613 .virtualize_apic_accesses = false, 5614 .use_tpr_shadow = false, 5615 .apic_register_virtualization = false, 5616 .virtualize_x2apic_mode = true, 5617 .activate_secondary_controls = true, 5618 }, 5619 }, 5620 { 5621 .name = "Virtualize x2APIC mode + Use TPR shadow off v2", 5622 .apic_reg_virt_config = { 5623 .virtualize_apic_accesses = false, 5624 .use_tpr_shadow = false, 5625 .apic_register_virtualization = true, 5626 .virtualize_x2apic_mode = true, 5627 .activate_secondary_controls = true, 5628 }, 5629 }, 5630 5631 /* 5632 * Test that VM entry fails due to invalid controls when 5633 * "virtualize x2APIC mode" is enabled while "virtualize APIC accesses" 5634 * is enabled. 5635 */ 5636 { 5637 .name = "Virtualize x2APIC mode + Virtualize APIC accesses", 5638 .apic_reg_virt_config = { 5639 .virtualize_apic_accesses = true, 5640 .use_tpr_shadow = true, 5641 .apic_register_virtualization = false, 5642 .virtualize_x2apic_mode = true, 5643 .activate_secondary_controls = true, 5644 }, 5645 }, 5646 { 5647 .name = "Virtualize x2APIC mode + Virtualize APIC accesses v2", 5648 .apic_reg_virt_config = { 5649 .virtualize_apic_accesses = true, 5650 .use_tpr_shadow = true, 5651 .apic_register_virtualization = true, 5652 .virtualize_x2apic_mode = true, 5653 .activate_secondary_controls = true, 5654 }, 5655 }, 5656 }; 5657 5658 enum Apic_op { 5659 APIC_OP_XAPIC_RD, 5660 APIC_OP_XAPIC_WR, 5661 TERMINATE, 5662 }; 5663 5664 static u32 vmx_xapic_read(u32 *apic_access_address, u32 reg) 5665 { 5666 return *(volatile u32 *)((uintptr_t)apic_access_address + reg); 5667 } 5668 5669 static void vmx_xapic_write(u32 *apic_access_address, u32 reg, u32 val) 5670 { 5671 *(volatile u32 *)((uintptr_t)apic_access_address + reg) = val; 5672 } 5673 5674 struct apic_reg_virt_guest_args { 5675 enum Apic_op op; 5676 u32 *apic_access_address; 5677 u32 reg; 5678 u32 val; 5679 bool check_rd; 5680 u32 (*virt_fn)(u32); 5681 } apic_reg_virt_guest_args; 5682 5683 static void apic_reg_virt_guest(void) 5684 { 5685 volatile struct apic_reg_virt_guest_args *args = 5686 &apic_reg_virt_guest_args; 5687 5688 for (;;) { 5689 enum Apic_op op = args->op; 5690 u32 *apic_access_address = args->apic_access_address; 5691 u32 reg = args->reg; 5692 u32 val = args->val; 5693 bool check_rd = args->check_rd; 5694 u32 (*virt_fn)(u32) = args->virt_fn; 5695 5696 if (op == TERMINATE) 5697 break; 5698 5699 if (op == APIC_OP_XAPIC_RD) { 5700 u32 ret = vmx_xapic_read(apic_access_address, reg); 5701 5702 if (check_rd) { 5703 u32 want = virt_fn(val); 5704 u32 got = virt_fn(ret); 5705 5706 report(got == want, 5707 "read 0x%x, expected 0x%x.", got, want); 5708 } 5709 } else if (op == APIC_OP_XAPIC_WR) { 5710 vmx_xapic_write(apic_access_address, reg, val); 5711 } 5712 5713 /* 5714 * The L1 should always execute a vmcall after it's done testing 5715 * an individual APIC operation. This helps to validate that the 5716 * L1 and L2 are in sync with each other, as expected. 5717 */ 5718 vmcall(); 5719 } 5720 } 5721 5722 static void test_xapic_rd( 5723 u32 reg, struct apic_reg_virt_expectation *expectation, 5724 u32 *apic_access_address, u32 *virtual_apic_page) 5725 { 5726 u32 val = expectation->val; 5727 u32 exit_reason_want = expectation->rd_exit_reason; 5728 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 5729 5730 report_prefix_pushf("xapic - reading 0x%03x", reg); 5731 5732 /* Configure guest to do an xapic read */ 5733 args->op = APIC_OP_XAPIC_RD; 5734 args->apic_access_address = apic_access_address; 5735 args->reg = reg; 5736 args->val = val; 5737 args->check_rd = exit_reason_want == VMX_VMCALL; 5738 args->virt_fn = expectation->virt_fn; 5739 5740 /* Setup virtual APIC page */ 5741 if (!expectation->virtualize_apic_accesses) { 5742 apic_access_address[apic_reg_index(reg)] = val; 5743 virtual_apic_page[apic_reg_index(reg)] = 0; 5744 } else if (exit_reason_want == VMX_VMCALL) { 5745 apic_access_address[apic_reg_index(reg)] = 0; 5746 virtual_apic_page[apic_reg_index(reg)] = val; 5747 } 5748 5749 /* Enter guest */ 5750 enter_guest(); 5751 5752 /* 5753 * Validate the behavior and 5754 * pass a magic value back to the guest. 5755 */ 5756 if (exit_reason_want == VMX_APIC_ACCESS) { 5757 u32 apic_page_offset = vmcs_read(EXI_QUALIFICATION) & 0xfff; 5758 5759 assert_exit_reason(exit_reason_want); 5760 report(apic_page_offset == reg, 5761 "got APIC access exit @ page offset 0x%03x, want 0x%03x", 5762 apic_page_offset, reg); 5763 skip_exit_insn(); 5764 5765 /* Reenter guest so it can consume/check rcx and exit again. */ 5766 enter_guest(); 5767 } else if (exit_reason_want != VMX_VMCALL) { 5768 report(false, "Oops, bad exit expectation: %u.", 5769 exit_reason_want); 5770 } 5771 5772 skip_exit_vmcall(); 5773 report_prefix_pop(); 5774 } 5775 5776 static void test_xapic_wr( 5777 u32 reg, struct apic_reg_virt_expectation *expectation, 5778 u32 *apic_access_address, u32 *virtual_apic_page) 5779 { 5780 u32 val = expectation->val; 5781 u32 exit_reason_want = expectation->wr_exit_reason; 5782 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 5783 bool virtualized = 5784 expectation->virtualize_apic_accesses && 5785 (exit_reason_want == VMX_APIC_WRITE || 5786 exit_reason_want == VMX_VMCALL); 5787 bool checked = false; 5788 5789 report_prefix_pushf("xapic - writing 0x%x to 0x%03x", val, reg); 5790 5791 /* Configure guest to do an xapic read */ 5792 args->op = APIC_OP_XAPIC_WR; 5793 args->apic_access_address = apic_access_address; 5794 args->reg = reg; 5795 args->val = val; 5796 5797 /* Setup virtual APIC page */ 5798 if (virtualized || !expectation->virtualize_apic_accesses) { 5799 apic_access_address[apic_reg_index(reg)] = 0; 5800 virtual_apic_page[apic_reg_index(reg)] = 0; 5801 } 5802 5803 /* Enter guest */ 5804 enter_guest(); 5805 5806 /* 5807 * Validate the behavior and 5808 * pass a magic value back to the guest. 5809 */ 5810 if (exit_reason_want == VMX_APIC_ACCESS) { 5811 u32 apic_page_offset = vmcs_read(EXI_QUALIFICATION) & 0xfff; 5812 5813 assert_exit_reason(exit_reason_want); 5814 report(apic_page_offset == reg, 5815 "got APIC access exit @ page offset 0x%03x, want 0x%03x", 5816 apic_page_offset, reg); 5817 skip_exit_insn(); 5818 5819 /* Reenter guest so it can consume/check rcx and exit again. */ 5820 enter_guest(); 5821 } else if (exit_reason_want == VMX_APIC_WRITE) { 5822 assert_exit_reason(exit_reason_want); 5823 report(virtual_apic_page[apic_reg_index(reg)] == val, 5824 "got APIC write exit @ page offset 0x%03x; val is 0x%x, want 0x%x", 5825 apic_reg_index(reg), 5826 virtual_apic_page[apic_reg_index(reg)], val); 5827 checked = true; 5828 5829 /* Reenter guest so it can consume/check rcx and exit again. */ 5830 enter_guest(); 5831 } else if (exit_reason_want != VMX_VMCALL) { 5832 report(false, "Oops, bad exit expectation: %u.", 5833 exit_reason_want); 5834 } 5835 5836 assert_exit_reason(VMX_VMCALL); 5837 if (virtualized && !checked) { 5838 u32 want = expectation->virt_fn(val); 5839 u32 got = virtual_apic_page[apic_reg_index(reg)]; 5840 got = expectation->virt_fn(got); 5841 5842 report(got == want, "exitless write; val is 0x%x, want 0x%x", 5843 got, want); 5844 } else if (!expectation->virtualize_apic_accesses && !checked) { 5845 u32 got = apic_access_address[apic_reg_index(reg)]; 5846 5847 report(got == val, 5848 "non-virtualized write; val is 0x%x, want 0x%x", got, 5849 val); 5850 } else if (!expectation->virtualize_apic_accesses && checked) { 5851 report(false, 5852 "Non-virtualized write was prematurely checked!"); 5853 } 5854 5855 skip_exit_vmcall(); 5856 report_prefix_pop(); 5857 } 5858 5859 enum Config_type { 5860 CONFIG_TYPE_GOOD, 5861 CONFIG_TYPE_UNSUPPORTED, 5862 CONFIG_TYPE_VMENTRY_FAILS_EARLY, 5863 }; 5864 5865 static enum Config_type configure_apic_reg_virt_test( 5866 struct apic_reg_virt_config *apic_reg_virt_config) 5867 { 5868 u32 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 5869 u32 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 5870 /* Configs where L2 entry fails early, due to invalid controls. */ 5871 bool use_tpr_shadow_incorrectly_off = 5872 !apic_reg_virt_config->use_tpr_shadow && 5873 (apic_reg_virt_config->apic_register_virtualization || 5874 apic_reg_virt_config->virtualize_x2apic_mode) && 5875 apic_reg_virt_config->activate_secondary_controls; 5876 bool virtualize_apic_accesses_incorrectly_on = 5877 apic_reg_virt_config->virtualize_apic_accesses && 5878 apic_reg_virt_config->virtualize_x2apic_mode && 5879 apic_reg_virt_config->activate_secondary_controls; 5880 bool vmentry_fails_early = 5881 use_tpr_shadow_incorrectly_off || 5882 virtualize_apic_accesses_incorrectly_on; 5883 5884 if (apic_reg_virt_config->activate_secondary_controls) { 5885 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 5886 printf("VM-execution control \"activate secondary controls\" NOT supported.\n"); 5887 return CONFIG_TYPE_UNSUPPORTED; 5888 } 5889 cpu_exec_ctrl0 |= CPU_SECONDARY; 5890 } else { 5891 cpu_exec_ctrl0 &= ~CPU_SECONDARY; 5892 } 5893 5894 if (apic_reg_virt_config->virtualize_apic_accesses) { 5895 if (!(ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES)) { 5896 printf("VM-execution control \"virtualize APIC accesses\" NOT supported.\n"); 5897 return CONFIG_TYPE_UNSUPPORTED; 5898 } 5899 cpu_exec_ctrl1 |= CPU_VIRT_APIC_ACCESSES; 5900 } else { 5901 cpu_exec_ctrl1 &= ~CPU_VIRT_APIC_ACCESSES; 5902 } 5903 5904 if (apic_reg_virt_config->use_tpr_shadow) { 5905 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) { 5906 printf("VM-execution control \"use TPR shadow\" NOT supported.\n"); 5907 return CONFIG_TYPE_UNSUPPORTED; 5908 } 5909 cpu_exec_ctrl0 |= CPU_TPR_SHADOW; 5910 } else { 5911 cpu_exec_ctrl0 &= ~CPU_TPR_SHADOW; 5912 } 5913 5914 if (apic_reg_virt_config->apic_register_virtualization) { 5915 if (!(ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT)) { 5916 printf("VM-execution control \"APIC-register virtualization\" NOT supported.\n"); 5917 return CONFIG_TYPE_UNSUPPORTED; 5918 } 5919 cpu_exec_ctrl1 |= CPU_APIC_REG_VIRT; 5920 } else { 5921 cpu_exec_ctrl1 &= ~CPU_APIC_REG_VIRT; 5922 } 5923 5924 if (apic_reg_virt_config->virtualize_x2apic_mode) { 5925 if (!(ctrl_cpu_rev[1].clr & CPU_VIRT_X2APIC)) { 5926 printf("VM-execution control \"virtualize x2APIC mode\" NOT supported.\n"); 5927 return CONFIG_TYPE_UNSUPPORTED; 5928 } 5929 cpu_exec_ctrl1 |= CPU_VIRT_X2APIC; 5930 } else { 5931 cpu_exec_ctrl1 &= ~CPU_VIRT_X2APIC; 5932 } 5933 5934 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 5935 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 5936 5937 if (vmentry_fails_early) 5938 return CONFIG_TYPE_VMENTRY_FAILS_EARLY; 5939 5940 return CONFIG_TYPE_GOOD; 5941 } 5942 5943 static bool cpu_has_apicv(void) 5944 { 5945 return ((ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT) && 5946 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 5947 (ctrl_pin_rev.clr & PIN_POST_INTR)); 5948 } 5949 5950 /* Validates APIC register access across valid virtualization configurations. */ 5951 static void apic_reg_virt_test(void) 5952 { 5953 u32 *apic_access_address; 5954 u32 *virtual_apic_page; 5955 u64 control; 5956 u64 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 5957 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 5958 int i; 5959 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 5960 5961 if (!cpu_has_apicv()) { 5962 report_skip(__func__); 5963 return; 5964 } 5965 5966 control = cpu_exec_ctrl1; 5967 control &= ~CPU_VINTD; 5968 vmcs_write(CPU_EXEC_CTRL1, control); 5969 5970 test_set_guest(apic_reg_virt_guest); 5971 5972 /* 5973 * From the SDM: The 1-setting of the "virtualize APIC accesses" 5974 * VM-execution is guaranteed to apply only if translations to the 5975 * APIC-access address use a 4-KByte page. 5976 */ 5977 apic_access_address = alloc_page(); 5978 force_4k_page(apic_access_address); 5979 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_address)); 5980 5981 virtual_apic_page = alloc_page(); 5982 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 5983 5984 for (i = 0; i < ARRAY_SIZE(apic_reg_tests); i++) { 5985 struct apic_reg_test *apic_reg_test = &apic_reg_tests[i]; 5986 struct apic_reg_virt_config *apic_reg_virt_config = 5987 &apic_reg_test->apic_reg_virt_config; 5988 enum Config_type config_type; 5989 u32 reg; 5990 5991 printf("--- %s test ---\n", apic_reg_test->name); 5992 config_type = 5993 configure_apic_reg_virt_test(apic_reg_virt_config); 5994 if (config_type == CONFIG_TYPE_UNSUPPORTED) { 5995 printf("Skip because of missing features.\n"); 5996 continue; 5997 } 5998 5999 if (config_type == CONFIG_TYPE_VMENTRY_FAILS_EARLY) { 6000 enter_guest_with_bad_controls(); 6001 continue; 6002 } 6003 6004 for (reg = 0; reg < PAGE_SIZE / sizeof(u32); reg += 0x10) { 6005 struct apic_reg_virt_expectation expectation = {}; 6006 bool ok; 6007 6008 ok = apic_reg_virt_exit_expectation( 6009 reg, apic_reg_virt_config, &expectation); 6010 if (!ok) { 6011 report(false, "Malformed test."); 6012 break; 6013 } 6014 6015 test_xapic_rd(reg, &expectation, apic_access_address, 6016 virtual_apic_page); 6017 test_xapic_wr(reg, &expectation, apic_access_address, 6018 virtual_apic_page); 6019 } 6020 } 6021 6022 /* Terminate the guest */ 6023 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6024 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6025 args->op = TERMINATE; 6026 enter_guest(); 6027 assert_exit_reason(VMX_VMCALL); 6028 } 6029 6030 struct virt_x2apic_mode_config { 6031 struct apic_reg_virt_config apic_reg_virt_config; 6032 bool virtual_interrupt_delivery; 6033 bool use_msr_bitmaps; 6034 bool disable_x2apic_msr_intercepts; 6035 bool disable_x2apic; 6036 }; 6037 6038 struct virt_x2apic_mode_test_case { 6039 const char *name; 6040 struct virt_x2apic_mode_config virt_x2apic_mode_config; 6041 }; 6042 6043 enum Virt_x2apic_mode_behavior_type { 6044 X2APIC_ACCESS_VIRTUALIZED, 6045 X2APIC_ACCESS_PASSED_THROUGH, 6046 X2APIC_ACCESS_TRIGGERS_GP, 6047 }; 6048 6049 struct virt_x2apic_mode_expectation { 6050 enum Reason rd_exit_reason; 6051 enum Reason wr_exit_reason; 6052 6053 /* 6054 * RDMSR and WRMSR handle 64-bit values. However, except for ICR, all of 6055 * the x2APIC registers are 32 bits. Notice: 6056 * 1. vmx_x2apic_read() clears the upper 32 bits for 32-bit registers. 6057 * 2. vmx_x2apic_write() expects the val arg to be well-formed. 6058 */ 6059 u64 rd_val; 6060 u64 wr_val; 6061 6062 /* 6063 * Compares input to virtualized output; 6064 * 1st arg is pointer to return expected virtualization output. 6065 */ 6066 u64 (*virt_fn)(u64); 6067 6068 enum Virt_x2apic_mode_behavior_type rd_behavior; 6069 enum Virt_x2apic_mode_behavior_type wr_behavior; 6070 bool wr_only; 6071 }; 6072 6073 static u64 virt_x2apic_mode_identity(u64 val) 6074 { 6075 return val; 6076 } 6077 6078 static u64 virt_x2apic_mode_nibble1(u64 val) 6079 { 6080 return val & 0xf0; 6081 } 6082 6083 static void virt_x2apic_mode_rd_expectation( 6084 u32 reg, bool virt_x2apic_mode_on, bool disable_x2apic, 6085 bool apic_register_virtualization, bool virtual_interrupt_delivery, 6086 struct virt_x2apic_mode_expectation *expectation) 6087 { 6088 bool readable = 6089 !x2apic_reg_reserved(reg) && 6090 reg != APIC_EOI; 6091 6092 expectation->rd_exit_reason = VMX_VMCALL; 6093 expectation->virt_fn = virt_x2apic_mode_identity; 6094 if (virt_x2apic_mode_on && apic_register_virtualization) { 6095 expectation->rd_val = MAGIC_VAL_1; 6096 if (reg == APIC_PROCPRI && virtual_interrupt_delivery) 6097 expectation->virt_fn = virt_x2apic_mode_nibble1; 6098 else if (reg == APIC_TASKPRI) 6099 expectation->virt_fn = virt_x2apic_mode_nibble1; 6100 expectation->rd_behavior = X2APIC_ACCESS_VIRTUALIZED; 6101 } else if (virt_x2apic_mode_on && !apic_register_virtualization && 6102 reg == APIC_TASKPRI) { 6103 expectation->rd_val = MAGIC_VAL_1; 6104 expectation->virt_fn = virt_x2apic_mode_nibble1; 6105 expectation->rd_behavior = X2APIC_ACCESS_VIRTUALIZED; 6106 } else if (!disable_x2apic && readable) { 6107 expectation->rd_val = apic_read(reg); 6108 expectation->rd_behavior = X2APIC_ACCESS_PASSED_THROUGH; 6109 } else { 6110 expectation->rd_behavior = X2APIC_ACCESS_TRIGGERS_GP; 6111 } 6112 } 6113 6114 /* 6115 * get_x2apic_wr_val() creates an innocuous write value for an x2APIC register. 6116 * 6117 * For writable registers, get_x2apic_wr_val() deposits the write value into the 6118 * val pointer arg and returns true. For non-writable registers, val is not 6119 * modified and get_x2apic_wr_val() returns false. 6120 */ 6121 static bool get_x2apic_wr_val(u32 reg, u64 *val) 6122 { 6123 switch (reg) { 6124 case APIC_TASKPRI: 6125 /* Bits 31:8 are reserved. */ 6126 *val &= 0xff; 6127 break; 6128 case APIC_EOI: 6129 case APIC_ESR: 6130 case APIC_TMICT: 6131 /* 6132 * EOI, ESR: WRMSR of a non-zero value causes #GP(0). 6133 * TMICT: A write of 0 to the initial-count register effectively 6134 * stops the local APIC timer, in both one-shot and 6135 * periodic mode. 6136 */ 6137 *val = 0; 6138 break; 6139 case APIC_SPIV: 6140 case APIC_LVTT: 6141 case APIC_LVTTHMR: 6142 case APIC_LVTPC: 6143 case APIC_LVT0: 6144 case APIC_LVT1: 6145 case APIC_LVTERR: 6146 case APIC_TDCR: 6147 /* 6148 * To avoid writing a 1 to a reserved bit or causing some other 6149 * unintended side effect, read the current value and use it as 6150 * the write value. 6151 */ 6152 *val = apic_read(reg); 6153 break; 6154 case APIC_CMCI: 6155 if (!apic_lvt_entry_supported(6)) 6156 return false; 6157 *val = apic_read(reg); 6158 break; 6159 case APIC_ICR: 6160 *val = 0x40000 | 0xf1; 6161 break; 6162 case APIC_SELF_IPI: 6163 /* 6164 * With special processing (i.e., virtualize x2APIC mode + 6165 * virtual interrupt delivery), writing zero causes an 6166 * APIC-write VM exit. We plan to add a test for enabling 6167 * "virtual-interrupt delivery" in VMCS12, and that's where we 6168 * will test a self IPI with special processing. 6169 */ 6170 *val = 0x0; 6171 break; 6172 default: 6173 return false; 6174 } 6175 6176 return true; 6177 } 6178 6179 static bool special_processing_applies(u32 reg, u64 *val, 6180 bool virt_int_delivery) 6181 { 6182 bool special_processing = 6183 (reg == APIC_TASKPRI) || 6184 (virt_int_delivery && 6185 (reg == APIC_EOI || reg == APIC_SELF_IPI)); 6186 6187 if (special_processing) { 6188 TEST_ASSERT(get_x2apic_wr_val(reg, val)); 6189 return true; 6190 } 6191 6192 return false; 6193 } 6194 6195 static void virt_x2apic_mode_wr_expectation( 6196 u32 reg, bool virt_x2apic_mode_on, bool disable_x2apic, 6197 bool virt_int_delivery, 6198 struct virt_x2apic_mode_expectation *expectation) 6199 { 6200 expectation->wr_exit_reason = VMX_VMCALL; 6201 expectation->wr_val = MAGIC_VAL_1; 6202 expectation->wr_only = false; 6203 6204 if (virt_x2apic_mode_on && 6205 special_processing_applies(reg, &expectation->wr_val, 6206 virt_int_delivery)) { 6207 expectation->wr_behavior = X2APIC_ACCESS_VIRTUALIZED; 6208 if (reg == APIC_SELF_IPI) 6209 expectation->wr_exit_reason = VMX_APIC_WRITE; 6210 } else if (!disable_x2apic && 6211 get_x2apic_wr_val(reg, &expectation->wr_val)) { 6212 expectation->wr_behavior = X2APIC_ACCESS_PASSED_THROUGH; 6213 if (reg == APIC_EOI || reg == APIC_SELF_IPI) 6214 expectation->wr_only = true; 6215 if (reg == APIC_ICR) 6216 expectation->wr_exit_reason = VMX_EXTINT; 6217 } else { 6218 expectation->wr_behavior = X2APIC_ACCESS_TRIGGERS_GP; 6219 /* 6220 * Writing 1 to a reserved bit triggers a #GP. 6221 * Thus, set the write value to 0, which seems 6222 * the most likely to detect a missed #GP. 6223 */ 6224 expectation->wr_val = 0; 6225 } 6226 } 6227 6228 static void virt_x2apic_mode_exit_expectation( 6229 u32 reg, struct virt_x2apic_mode_config *config, 6230 struct virt_x2apic_mode_expectation *expectation) 6231 { 6232 struct apic_reg_virt_config *base_config = 6233 &config->apic_reg_virt_config; 6234 bool virt_x2apic_mode_on = 6235 base_config->virtualize_x2apic_mode && 6236 config->use_msr_bitmaps && 6237 config->disable_x2apic_msr_intercepts && 6238 base_config->activate_secondary_controls; 6239 6240 virt_x2apic_mode_wr_expectation( 6241 reg, virt_x2apic_mode_on, config->disable_x2apic, 6242 config->virtual_interrupt_delivery, expectation); 6243 virt_x2apic_mode_rd_expectation( 6244 reg, virt_x2apic_mode_on, config->disable_x2apic, 6245 base_config->apic_register_virtualization, 6246 config->virtual_interrupt_delivery, expectation); 6247 } 6248 6249 struct virt_x2apic_mode_test_case virt_x2apic_mode_tests[] = { 6250 /* 6251 * Baseline "virtualize x2APIC mode" configuration: 6252 * - virtualize x2APIC mode 6253 * - virtual-interrupt delivery 6254 * - APIC-register virtualization 6255 * - x2APIC MSR intercepts disabled 6256 * 6257 * Reads come from virtual APIC page, special processing applies to 6258 * VTPR, EOI, and SELF IPI, and all other writes pass through to L1 6259 * APIC. 6260 */ 6261 { 6262 .name = "Baseline", 6263 .virt_x2apic_mode_config = { 6264 .virtual_interrupt_delivery = true, 6265 .use_msr_bitmaps = true, 6266 .disable_x2apic_msr_intercepts = true, 6267 .disable_x2apic = false, 6268 .apic_reg_virt_config = { 6269 .apic_register_virtualization = true, 6270 .use_tpr_shadow = true, 6271 .virtualize_apic_accesses = false, 6272 .virtualize_x2apic_mode = true, 6273 .activate_secondary_controls = true, 6274 }, 6275 }, 6276 }, 6277 { 6278 .name = "Baseline w/ x2apic disabled", 6279 .virt_x2apic_mode_config = { 6280 .virtual_interrupt_delivery = true, 6281 .use_msr_bitmaps = true, 6282 .disable_x2apic_msr_intercepts = true, 6283 .disable_x2apic = true, 6284 .apic_reg_virt_config = { 6285 .apic_register_virtualization = true, 6286 .use_tpr_shadow = true, 6287 .virtualize_apic_accesses = false, 6288 .virtualize_x2apic_mode = true, 6289 .activate_secondary_controls = true, 6290 }, 6291 }, 6292 }, 6293 6294 /* 6295 * Baseline, minus virtual-interrupt delivery. Reads come from virtual 6296 * APIC page, special processing applies to VTPR, and all other writes 6297 * pass through to L1 APIC. 6298 */ 6299 { 6300 .name = "Baseline - virtual interrupt delivery", 6301 .virt_x2apic_mode_config = { 6302 .virtual_interrupt_delivery = false, 6303 .use_msr_bitmaps = true, 6304 .disable_x2apic_msr_intercepts = true, 6305 .disable_x2apic = false, 6306 .apic_reg_virt_config = { 6307 .apic_register_virtualization = true, 6308 .use_tpr_shadow = true, 6309 .virtualize_apic_accesses = false, 6310 .virtualize_x2apic_mode = true, 6311 .activate_secondary_controls = true, 6312 }, 6313 }, 6314 }, 6315 6316 /* 6317 * Baseline, minus APIC-register virtualization. x2APIC reads pass 6318 * through to L1's APIC, unless reading VTPR 6319 */ 6320 { 6321 .name = "Virtualize x2APIC mode, no APIC reg virt", 6322 .virt_x2apic_mode_config = { 6323 .virtual_interrupt_delivery = true, 6324 .use_msr_bitmaps = true, 6325 .disable_x2apic_msr_intercepts = true, 6326 .disable_x2apic = false, 6327 .apic_reg_virt_config = { 6328 .apic_register_virtualization = false, 6329 .use_tpr_shadow = true, 6330 .virtualize_apic_accesses = false, 6331 .virtualize_x2apic_mode = true, 6332 .activate_secondary_controls = true, 6333 }, 6334 }, 6335 }, 6336 { 6337 .name = "Virtualize x2APIC mode, no APIC reg virt, x2APIC off", 6338 .virt_x2apic_mode_config = { 6339 .virtual_interrupt_delivery = true, 6340 .use_msr_bitmaps = true, 6341 .disable_x2apic_msr_intercepts = true, 6342 .disable_x2apic = true, 6343 .apic_reg_virt_config = { 6344 .apic_register_virtualization = false, 6345 .use_tpr_shadow = true, 6346 .virtualize_apic_accesses = false, 6347 .virtualize_x2apic_mode = true, 6348 .activate_secondary_controls = true, 6349 }, 6350 }, 6351 }, 6352 6353 /* 6354 * Enable "virtualize x2APIC mode" and "APIC-register virtualization", 6355 * and disable intercepts for the x2APIC MSRs, but fail to enable 6356 * "activate secondary controls" (i.e. L2 gets access to L1's x2APIC 6357 * MSRs). 6358 */ 6359 { 6360 .name = "Fail to enable activate secondary controls", 6361 .virt_x2apic_mode_config = { 6362 .virtual_interrupt_delivery = true, 6363 .use_msr_bitmaps = true, 6364 .disable_x2apic_msr_intercepts = true, 6365 .disable_x2apic = false, 6366 .apic_reg_virt_config = { 6367 .apic_register_virtualization = true, 6368 .use_tpr_shadow = true, 6369 .virtualize_apic_accesses = false, 6370 .virtualize_x2apic_mode = true, 6371 .activate_secondary_controls = false, 6372 }, 6373 }, 6374 }, 6375 6376 /* 6377 * Enable "APIC-register virtualization" and enable "activate secondary 6378 * controls" and disable intercepts for the x2APIC MSRs, but do not 6379 * enable the "virtualize x2APIC mode" VM-execution control (i.e. L2 6380 * gets access to L1's x2APIC MSRs). 6381 */ 6382 { 6383 .name = "Fail to enable virtualize x2APIC mode", 6384 .virt_x2apic_mode_config = { 6385 .virtual_interrupt_delivery = true, 6386 .use_msr_bitmaps = true, 6387 .disable_x2apic_msr_intercepts = true, 6388 .disable_x2apic = false, 6389 .apic_reg_virt_config = { 6390 .apic_register_virtualization = true, 6391 .use_tpr_shadow = true, 6392 .virtualize_apic_accesses = false, 6393 .virtualize_x2apic_mode = false, 6394 .activate_secondary_controls = true, 6395 }, 6396 }, 6397 }, 6398 6399 /* 6400 * Disable "Virtualize x2APIC mode", disable x2APIC MSR intercepts, and 6401 * enable "APIC-register virtualization" --> L2 gets L1's x2APIC MSRs. 6402 */ 6403 { 6404 .name = "Baseline", 6405 .virt_x2apic_mode_config = { 6406 .virtual_interrupt_delivery = true, 6407 .use_msr_bitmaps = true, 6408 .disable_x2apic_msr_intercepts = true, 6409 .disable_x2apic = false, 6410 .apic_reg_virt_config = { 6411 .apic_register_virtualization = true, 6412 .use_tpr_shadow = true, 6413 .virtualize_apic_accesses = false, 6414 .virtualize_x2apic_mode = false, 6415 .activate_secondary_controls = true, 6416 }, 6417 }, 6418 }, 6419 }; 6420 6421 enum X2apic_op { 6422 X2APIC_OP_RD, 6423 X2APIC_OP_WR, 6424 X2APIC_TERMINATE, 6425 }; 6426 6427 static u64 vmx_x2apic_read(u32 reg) 6428 { 6429 u32 msr_addr = x2apic_msr(reg); 6430 u64 val; 6431 6432 val = rdmsr(msr_addr); 6433 6434 return val; 6435 } 6436 6437 static void vmx_x2apic_write(u32 reg, u64 val) 6438 { 6439 u32 msr_addr = x2apic_msr(reg); 6440 6441 wrmsr(msr_addr, val); 6442 } 6443 6444 struct virt_x2apic_mode_guest_args { 6445 enum X2apic_op op; 6446 u32 reg; 6447 u64 val; 6448 bool should_gp; 6449 u64 (*virt_fn)(u64); 6450 } virt_x2apic_mode_guest_args; 6451 6452 static volatile bool handle_x2apic_gp_ran; 6453 static volatile u32 handle_x2apic_gp_insn_len; 6454 static void handle_x2apic_gp(struct ex_regs *regs) 6455 { 6456 handle_x2apic_gp_ran = true; 6457 regs->rip += handle_x2apic_gp_insn_len; 6458 } 6459 6460 static handler setup_x2apic_gp_handler(void) 6461 { 6462 handler old_handler; 6463 6464 old_handler = handle_exception(GP_VECTOR, handle_x2apic_gp); 6465 /* RDMSR and WRMSR are both 2 bytes, assuming no prefixes. */ 6466 handle_x2apic_gp_insn_len = 2; 6467 6468 return old_handler; 6469 } 6470 6471 static void teardown_x2apic_gp_handler(handler old_handler) 6472 { 6473 handle_exception(GP_VECTOR, old_handler); 6474 6475 /* 6476 * Defensively reset instruction length, so that if the handler is 6477 * incorrectly used, it will loop infinitely, rather than run off into 6478 * la la land. 6479 */ 6480 handle_x2apic_gp_insn_len = 0; 6481 handle_x2apic_gp_ran = false; 6482 } 6483 6484 static void virt_x2apic_mode_guest(void) 6485 { 6486 volatile struct virt_x2apic_mode_guest_args *args = 6487 &virt_x2apic_mode_guest_args; 6488 6489 for (;;) { 6490 enum X2apic_op op = args->op; 6491 u32 reg = args->reg; 6492 u64 val = args->val; 6493 bool should_gp = args->should_gp; 6494 u64 (*virt_fn)(u64) = args->virt_fn; 6495 handler old_handler; 6496 6497 if (op == X2APIC_TERMINATE) 6498 break; 6499 6500 if (should_gp) { 6501 TEST_ASSERT(!handle_x2apic_gp_ran); 6502 old_handler = setup_x2apic_gp_handler(); 6503 } 6504 6505 if (op == X2APIC_OP_RD) { 6506 u64 ret = vmx_x2apic_read(reg); 6507 6508 if (!should_gp) { 6509 u64 want = virt_fn(val); 6510 u64 got = virt_fn(ret); 6511 6512 report(got == want, 6513 "APIC read; got 0x%lx, want 0x%lx.", 6514 got, want); 6515 } 6516 } else if (op == X2APIC_OP_WR) { 6517 vmx_x2apic_write(reg, val); 6518 } 6519 6520 if (should_gp) { 6521 report(handle_x2apic_gp_ran, 6522 "x2APIC op triggered GP."); 6523 teardown_x2apic_gp_handler(old_handler); 6524 } 6525 6526 /* 6527 * The L1 should always execute a vmcall after it's done testing 6528 * an individual APIC operation. This helps to validate that the 6529 * L1 and L2 are in sync with each other, as expected. 6530 */ 6531 vmcall(); 6532 } 6533 } 6534 6535 static void test_x2apic_rd( 6536 u32 reg, struct virt_x2apic_mode_expectation *expectation, 6537 u32 *virtual_apic_page) 6538 { 6539 u64 val = expectation->rd_val; 6540 u32 exit_reason_want = expectation->rd_exit_reason; 6541 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6542 6543 report_prefix_pushf("x2apic - reading 0x%03x", reg); 6544 6545 /* Configure guest to do an x2apic read */ 6546 args->op = X2APIC_OP_RD; 6547 args->reg = reg; 6548 args->val = val; 6549 args->should_gp = expectation->rd_behavior == X2APIC_ACCESS_TRIGGERS_GP; 6550 args->virt_fn = expectation->virt_fn; 6551 6552 /* Setup virtual APIC page */ 6553 if (expectation->rd_behavior == X2APIC_ACCESS_VIRTUALIZED) 6554 virtual_apic_page[apic_reg_index(reg)] = (u32)val; 6555 6556 /* Enter guest */ 6557 enter_guest(); 6558 6559 if (exit_reason_want != VMX_VMCALL) { 6560 report(false, "Oops, bad exit expectation: %u.", 6561 exit_reason_want); 6562 } 6563 6564 skip_exit_vmcall(); 6565 report_prefix_pop(); 6566 } 6567 6568 static volatile bool handle_x2apic_ipi_ran; 6569 static void handle_x2apic_ipi(isr_regs_t *regs) 6570 { 6571 handle_x2apic_ipi_ran = true; 6572 eoi(); 6573 } 6574 6575 static void test_x2apic_wr( 6576 u32 reg, struct virt_x2apic_mode_expectation *expectation, 6577 u32 *virtual_apic_page) 6578 { 6579 u64 val = expectation->wr_val; 6580 u32 exit_reason_want = expectation->wr_exit_reason; 6581 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6582 int ipi_vector = 0xf1; 6583 u32 restore_val = 0; 6584 6585 report_prefix_pushf("x2apic - writing 0x%lx to 0x%03x", val, reg); 6586 6587 /* Configure guest to do an x2apic read */ 6588 args->op = X2APIC_OP_WR; 6589 args->reg = reg; 6590 args->val = val; 6591 args->should_gp = expectation->wr_behavior == X2APIC_ACCESS_TRIGGERS_GP; 6592 6593 /* Setup virtual APIC page */ 6594 if (expectation->wr_behavior == X2APIC_ACCESS_VIRTUALIZED) 6595 virtual_apic_page[apic_reg_index(reg)] = 0; 6596 if (expectation->wr_behavior == X2APIC_ACCESS_PASSED_THROUGH && !expectation->wr_only) 6597 restore_val = apic_read(reg); 6598 6599 /* Setup IPI handler */ 6600 handle_x2apic_ipi_ran = false; 6601 handle_irq(ipi_vector, handle_x2apic_ipi); 6602 6603 /* Enter guest */ 6604 enter_guest(); 6605 6606 /* 6607 * Validate the behavior and 6608 * pass a magic value back to the guest. 6609 */ 6610 if (exit_reason_want == VMX_EXTINT) { 6611 assert_exit_reason(exit_reason_want); 6612 6613 /* Clear the external interrupt. */ 6614 irq_enable(); 6615 asm volatile ("nop"); 6616 irq_disable(); 6617 report(handle_x2apic_ipi_ran, 6618 "Got pending interrupt after IRQ enabled."); 6619 6620 enter_guest(); 6621 } else if (exit_reason_want == VMX_APIC_WRITE) { 6622 assert_exit_reason(exit_reason_want); 6623 report(virtual_apic_page[apic_reg_index(reg)] == val, 6624 "got APIC write exit @ page offset 0x%03x; val is 0x%x, want 0x%lx", 6625 apic_reg_index(reg), 6626 virtual_apic_page[apic_reg_index(reg)], val); 6627 6628 /* Reenter guest so it can consume/check rcx and exit again. */ 6629 enter_guest(); 6630 } else if (exit_reason_want != VMX_VMCALL) { 6631 report(false, "Oops, bad exit expectation: %u.", 6632 exit_reason_want); 6633 } 6634 6635 assert_exit_reason(VMX_VMCALL); 6636 if (expectation->wr_behavior == X2APIC_ACCESS_VIRTUALIZED) { 6637 u64 want = val; 6638 u32 got = virtual_apic_page[apic_reg_index(reg)]; 6639 6640 report(got == want, "x2APIC write; got 0x%x, want 0x%lx", got, 6641 want); 6642 } else if (expectation->wr_behavior == X2APIC_ACCESS_PASSED_THROUGH) { 6643 if (!expectation->wr_only) { 6644 u32 got = apic_read(reg); 6645 bool ok; 6646 6647 /* 6648 * When L1's TPR is passed through to L2, the lower 6649 * nibble can be lost. For example, if L2 executes 6650 * WRMSR(0x808, 0x78), then, L1 might read 0x70. 6651 * 6652 * Here's how the lower nibble can get lost: 6653 * 1. L2 executes WRMSR(0x808, 0x78). 6654 * 2. L2 exits to L0 with a WRMSR exit. 6655 * 3. L0 emulates WRMSR, by writing L1's TPR. 6656 * 4. L0 re-enters L2. 6657 * 5. L2 exits to L0 (reason doesn't matter). 6658 * 6. L0 reflects L2's exit to L1. 6659 * 7. Before entering L1, L0 exits to user-space 6660 * (e.g., to satisfy TPR access reporting). 6661 * 8. User-space executes KVM_SET_REGS ioctl, which 6662 * clears the lower nibble of L1's TPR. 6663 */ 6664 if (reg == APIC_TASKPRI) { 6665 got = apic_virt_nibble1(got); 6666 val = apic_virt_nibble1(val); 6667 } 6668 6669 ok = got == val; 6670 report(ok, 6671 "non-virtualized write; val is 0x%x, want 0x%lx", 6672 got, val); 6673 apic_write(reg, restore_val); 6674 } else { 6675 report(true, "non-virtualized and write-only OK"); 6676 } 6677 } 6678 skip_exit_insn(); 6679 6680 report_prefix_pop(); 6681 } 6682 6683 static enum Config_type configure_virt_x2apic_mode_test( 6684 struct virt_x2apic_mode_config *virt_x2apic_mode_config, 6685 u8 *msr_bitmap_page) 6686 { 6687 int msr; 6688 u32 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6689 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6690 6691 /* x2apic-specific VMCS config */ 6692 if (virt_x2apic_mode_config->use_msr_bitmaps) { 6693 /* virt_x2apic_mode_test() checks for MSR bitmaps support */ 6694 cpu_exec_ctrl0 |= CPU_MSR_BITMAP; 6695 } else { 6696 cpu_exec_ctrl0 &= ~CPU_MSR_BITMAP; 6697 } 6698 6699 if (virt_x2apic_mode_config->virtual_interrupt_delivery) { 6700 if (!(ctrl_cpu_rev[1].clr & CPU_VINTD)) { 6701 report_skip("VM-execution control \"virtual-interrupt delivery\" NOT supported.\n"); 6702 return CONFIG_TYPE_UNSUPPORTED; 6703 } 6704 cpu_exec_ctrl1 |= CPU_VINTD; 6705 } else { 6706 cpu_exec_ctrl1 &= ~CPU_VINTD; 6707 } 6708 6709 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6710 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6711 6712 /* x2APIC MSR intercepts are usually off for "Virtualize x2APIC mode" */ 6713 for (msr = 0x800; msr <= 0x8ff; msr++) { 6714 if (virt_x2apic_mode_config->disable_x2apic_msr_intercepts) { 6715 clear_bit(msr, msr_bitmap_page + 0x000); 6716 clear_bit(msr, msr_bitmap_page + 0x800); 6717 } else { 6718 set_bit(msr, msr_bitmap_page + 0x000); 6719 set_bit(msr, msr_bitmap_page + 0x800); 6720 } 6721 } 6722 6723 /* x2APIC mode can impact virtualization */ 6724 reset_apic(); 6725 if (!virt_x2apic_mode_config->disable_x2apic) 6726 enable_x2apic(); 6727 6728 return configure_apic_reg_virt_test( 6729 &virt_x2apic_mode_config->apic_reg_virt_config); 6730 } 6731 6732 static void virt_x2apic_mode_test(void) 6733 { 6734 u32 *virtual_apic_page; 6735 u8 *msr_bitmap_page; 6736 u64 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6737 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6738 int i; 6739 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6740 6741 if (!cpu_has_apicv()) { 6742 report_skip(__func__); 6743 return; 6744 } 6745 6746 /* 6747 * This is to exercise an issue in KVM's logic to merge L0's and L1's 6748 * MSR bitmaps. Previously, an L1 could get at L0's x2APIC MSRs by 6749 * writing the IA32_SPEC_CTRL MSR or the IA32_PRED_CMD MSRs. KVM would 6750 * then proceed to manipulate the MSR bitmaps, as if VMCS12 had the 6751 * "Virtualize x2APIC mod" control set, even when it didn't. 6752 */ 6753 if (has_spec_ctrl()) 6754 wrmsr(MSR_IA32_SPEC_CTRL, 1); 6755 6756 /* 6757 * Check that VMCS12 supports: 6758 * - "Virtual-APIC address", indicated by "use TPR shadow" 6759 * - "MSR-bitmap address", indicated by "use MSR bitmaps" 6760 */ 6761 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) { 6762 report_skip("VM-execution control \"use TPR shadow\" NOT supported.\n"); 6763 return; 6764 } else if (!(ctrl_cpu_rev[0].clr & CPU_MSR_BITMAP)) { 6765 report_skip("VM-execution control \"use MSR bitmaps\" NOT supported.\n"); 6766 return; 6767 } 6768 6769 test_set_guest(virt_x2apic_mode_guest); 6770 6771 virtual_apic_page = alloc_page(); 6772 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 6773 6774 msr_bitmap_page = alloc_page(); 6775 memset(msr_bitmap_page, 0xff, PAGE_SIZE); 6776 vmcs_write(MSR_BITMAP, virt_to_phys(msr_bitmap_page)); 6777 6778 for (i = 0; i < ARRAY_SIZE(virt_x2apic_mode_tests); i++) { 6779 struct virt_x2apic_mode_test_case *virt_x2apic_mode_test_case = 6780 &virt_x2apic_mode_tests[i]; 6781 struct virt_x2apic_mode_config *virt_x2apic_mode_config = 6782 &virt_x2apic_mode_test_case->virt_x2apic_mode_config; 6783 enum Config_type config_type; 6784 u32 reg; 6785 6786 printf("--- %s test ---\n", virt_x2apic_mode_test_case->name); 6787 config_type = 6788 configure_virt_x2apic_mode_test(virt_x2apic_mode_config, 6789 msr_bitmap_page); 6790 if (config_type == CONFIG_TYPE_UNSUPPORTED) { 6791 report_skip("Skip because of missing features.\n"); 6792 continue; 6793 } else if (config_type == CONFIG_TYPE_VMENTRY_FAILS_EARLY) { 6794 enter_guest_with_bad_controls(); 6795 continue; 6796 } 6797 6798 for (reg = 0; reg < PAGE_SIZE / sizeof(u32); reg += 0x10) { 6799 struct virt_x2apic_mode_expectation expectation; 6800 6801 virt_x2apic_mode_exit_expectation( 6802 reg, virt_x2apic_mode_config, &expectation); 6803 6804 test_x2apic_rd(reg, &expectation, virtual_apic_page); 6805 test_x2apic_wr(reg, &expectation, virtual_apic_page); 6806 } 6807 } 6808 6809 6810 /* Terminate the guest */ 6811 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6812 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6813 args->op = X2APIC_TERMINATE; 6814 enter_guest(); 6815 assert_exit_reason(VMX_VMCALL); 6816 } 6817 6818 static void test_ctl_reg(const char *cr_name, u64 cr, u64 fixed0, u64 fixed1) 6819 { 6820 u64 val; 6821 u64 cr_saved = vmcs_read(cr); 6822 int i; 6823 6824 val = fixed0 & fixed1; 6825 if (cr == HOST_CR4) 6826 vmcs_write(cr, val | X86_CR4_PAE); 6827 else 6828 vmcs_write(cr, val); 6829 report_prefix_pushf("%s %lx", cr_name, val); 6830 if (val == fixed0) 6831 test_vmx_vmlaunch(0); 6832 else 6833 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 6834 report_prefix_pop(); 6835 6836 for (i = 0; i < 64; i++) { 6837 6838 /* Set a bit when the corresponding bit in fixed1 is 0 */ 6839 if ((fixed1 & (1ull << i)) == 0) { 6840 if (cr == HOST_CR4 && ((1ull << i) & X86_CR4_SMEP || 6841 (1ull << i) & X86_CR4_SMAP)) 6842 continue; 6843 6844 vmcs_write(cr, cr_saved | (1ull << i)); 6845 report_prefix_pushf("%s %llx", cr_name, 6846 cr_saved | (1ull << i)); 6847 test_vmx_vmlaunch( 6848 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 6849 report_prefix_pop(); 6850 } 6851 6852 /* Unset a bit when the corresponding bit in fixed0 is 1 */ 6853 if (fixed0 & (1ull << i)) { 6854 vmcs_write(cr, cr_saved & ~(1ull << i)); 6855 report_prefix_pushf("%s %llx", cr_name, 6856 cr_saved & ~(1ull << i)); 6857 test_vmx_vmlaunch( 6858 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 6859 report_prefix_pop(); 6860 } 6861 } 6862 6863 vmcs_write(cr, cr_saved); 6864 } 6865 6866 /* 6867 * 1. The CR0 field must not set any bit to a value not supported in VMX 6868 * operation. 6869 * 2. The CR4 field must not set any bit to a value not supported in VMX 6870 * operation. 6871 * 3. On processors that support Intel 64 architecture, the CR3 field must 6872 * be such that bits 63:52 and bits in the range 51:32 beyond the 6873 * processor’s physical-address width must be 0. 6874 * 6875 * [Intel SDM] 6876 */ 6877 static void test_host_ctl_regs(void) 6878 { 6879 u64 fixed0, fixed1, cr3, cr3_saved; 6880 int i; 6881 6882 /* Test CR0 */ 6883 fixed0 = rdmsr(MSR_IA32_VMX_CR0_FIXED0); 6884 fixed1 = rdmsr(MSR_IA32_VMX_CR0_FIXED1); 6885 test_ctl_reg("HOST_CR0", HOST_CR0, fixed0, fixed1); 6886 6887 /* Test CR4 */ 6888 fixed0 = rdmsr(MSR_IA32_VMX_CR4_FIXED0); 6889 fixed1 = rdmsr(MSR_IA32_VMX_CR4_FIXED1) & 6890 ~(X86_CR4_SMEP | X86_CR4_SMAP); 6891 test_ctl_reg("HOST_CR4", HOST_CR4, fixed0, fixed1); 6892 6893 /* Test CR3 */ 6894 cr3_saved = vmcs_read(HOST_CR3); 6895 for (i = cpuid_maxphyaddr(); i < 64; i++) { 6896 cr3 = cr3_saved | (1ul << i); 6897 vmcs_write(HOST_CR3, cr3); 6898 report_prefix_pushf("HOST_CR3 %lx", cr3); 6899 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 6900 report_prefix_pop(); 6901 } 6902 6903 vmcs_write(HOST_CR3, cr3_saved); 6904 } 6905 6906 static void test_efer_vmlaunch(u32 fld, bool ok) 6907 { 6908 if (fld == HOST_EFER) { 6909 if (ok) 6910 test_vmx_vmlaunch(0); 6911 else 6912 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 6913 } else { 6914 if (ok) { 6915 enter_guest(); 6916 report(vmcs_read(EXI_REASON) == VMX_VMCALL, 6917 "vmlaunch succeeds"); 6918 } else { 6919 enter_guest_with_invalid_guest_state(); 6920 report(vmcs_read(EXI_REASON) == (VMX_ENTRY_FAILURE | VMX_FAIL_STATE), 6921 "vmlaunch fails"); 6922 } 6923 advance_guest_state_test(); 6924 } 6925 } 6926 6927 static void test_efer_one(u32 fld, const char * fld_name, u64 efer, 6928 u32 ctrl_fld, u64 ctrl, 6929 int i, const char *efer_bit_name) 6930 { 6931 bool ok; 6932 6933 ok = true; 6934 if (ctrl_fld == EXI_CONTROLS && (ctrl & EXI_LOAD_EFER)) { 6935 if (!!(efer & EFER_LMA) != !!(ctrl & EXI_HOST_64)) 6936 ok = false; 6937 if (!!(efer & EFER_LME) != !!(ctrl & EXI_HOST_64)) 6938 ok = false; 6939 } 6940 if (ctrl_fld == ENT_CONTROLS && (ctrl & ENT_LOAD_EFER)) { 6941 /* Check LMA too since CR0.PG is set. */ 6942 if (!!(efer & EFER_LMA) != !!(ctrl & ENT_GUEST_64)) 6943 ok = false; 6944 if (!!(efer & EFER_LME) != !!(ctrl & ENT_GUEST_64)) 6945 ok = false; 6946 } 6947 6948 /* 6949 * Skip the test if it would enter the guest in 32-bit mode. 6950 * Perhaps write the test in assembly and make sure it 6951 * can be run in either mode? 6952 */ 6953 if (fld == GUEST_EFER && ok && !(ctrl & ENT_GUEST_64)) 6954 return; 6955 6956 vmcs_write(ctrl_fld, ctrl); 6957 vmcs_write(fld, efer); 6958 report_prefix_pushf("%s %s bit turned %s, controls %s", 6959 fld_name, efer_bit_name, 6960 (i & 1) ? "on" : "off", 6961 (i & 2) ? "on" : "off"); 6962 6963 test_efer_vmlaunch(fld, ok); 6964 report_prefix_pop(); 6965 } 6966 6967 static void test_efer_bit(u32 fld, const char * fld_name, 6968 u32 ctrl_fld, u64 ctrl_bit, u64 efer_bit, 6969 const char *efer_bit_name) 6970 { 6971 u64 efer_saved = vmcs_read(fld); 6972 u32 ctrl_saved = vmcs_read(ctrl_fld); 6973 int i; 6974 6975 for (i = 0; i < 4; i++) { 6976 u64 efer = efer_saved & ~efer_bit; 6977 u64 ctrl = ctrl_saved & ~ctrl_bit; 6978 6979 if (i & 1) 6980 efer |= efer_bit; 6981 if (i & 2) 6982 ctrl |= ctrl_bit; 6983 6984 test_efer_one(fld, fld_name, efer, ctrl_fld, ctrl, 6985 i, efer_bit_name); 6986 } 6987 6988 vmcs_write(ctrl_fld, ctrl_saved); 6989 vmcs_write(fld, efer_saved); 6990 } 6991 6992 static void test_efer(u32 fld, const char * fld_name, u32 ctrl_fld, 6993 u64 ctrl_bit1, u64 ctrl_bit2) 6994 { 6995 u64 efer_saved = vmcs_read(fld); 6996 u32 ctrl_saved = vmcs_read(ctrl_fld); 6997 u64 efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 6998 u64 i; 6999 u64 efer; 7000 7001 if (cpu_has_efer_nx()) 7002 efer_reserved_bits &= ~EFER_NX; 7003 7004 if (!ctrl_bit1) { 7005 printf("\"Load-IA32-EFER\" exit control not supported\n"); 7006 goto test_entry_exit_mode; 7007 } 7008 7009 report_prefix_pushf("%s %lx", fld_name, efer_saved); 7010 test_efer_vmlaunch(fld, true); 7011 report_prefix_pop(); 7012 7013 /* 7014 * Check reserved bits 7015 */ 7016 vmcs_write(ctrl_fld, ctrl_saved & ~ctrl_bit1); 7017 for (i = 0; i < 64; i++) { 7018 if ((1ull << i) & efer_reserved_bits) { 7019 efer = efer_saved | (1ull << i); 7020 vmcs_write(fld, efer); 7021 report_prefix_pushf("%s %lx", fld_name, efer); 7022 test_efer_vmlaunch(fld, true); 7023 report_prefix_pop(); 7024 } 7025 } 7026 7027 vmcs_write(ctrl_fld, ctrl_saved | ctrl_bit1); 7028 for (i = 0; i < 64; i++) { 7029 if ((1ull << i) & efer_reserved_bits) { 7030 efer = efer_saved | (1ull << i); 7031 vmcs_write(fld, efer); 7032 report_prefix_pushf("%s %lx", fld_name, efer); 7033 test_efer_vmlaunch(fld, false); 7034 report_prefix_pop(); 7035 } 7036 } 7037 7038 vmcs_write(ctrl_fld, ctrl_saved); 7039 vmcs_write(fld, efer_saved); 7040 7041 /* 7042 * Check LMA and LME bits 7043 */ 7044 test_efer_bit(fld, fld_name, 7045 ctrl_fld, ctrl_bit1, 7046 EFER_LMA, 7047 "EFER_LMA"); 7048 test_efer_bit(fld, fld_name, 7049 ctrl_fld, ctrl_bit1, 7050 EFER_LME, 7051 "EFER_LME"); 7052 7053 test_entry_exit_mode: 7054 test_efer_bit(fld, fld_name, 7055 ctrl_fld, ctrl_bit2, 7056 EFER_LMA, 7057 "EFER_LMA"); 7058 test_efer_bit(fld, fld_name, 7059 ctrl_fld, ctrl_bit2, 7060 EFER_LME, 7061 "EFER_LME"); 7062 } 7063 7064 /* 7065 * If the 'load IA32_EFER' VM-exit control is 1, bits reserved in the 7066 * IA32_EFER MSR must be 0 in the field for that register. In addition, 7067 * the values of the LMA and LME bits in the field must each be that of 7068 * the 'host address-space size' VM-exit control. 7069 * 7070 * [Intel SDM] 7071 */ 7072 static void test_host_efer(void) 7073 { 7074 test_efer(HOST_EFER, "HOST_EFER", EXI_CONTROLS, 7075 ctrl_exit_rev.clr & EXI_LOAD_EFER, 7076 EXI_HOST_64); 7077 } 7078 7079 /* 7080 * If the 'load IA32_EFER' VM-enter control is 1, bits reserved in the 7081 * IA32_EFER MSR must be 0 in the field for that register. In addition, 7082 * the values of the LMA and LME bits in the field must each be that of 7083 * the 'IA32e-mode guest' VM-exit control. 7084 */ 7085 static void test_guest_efer(void) 7086 { 7087 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) { 7088 printf("\"Load-IA32-EFER\" entry control not supported\n"); 7089 return; 7090 } 7091 7092 vmcs_write(GUEST_EFER, rdmsr(MSR_EFER)); 7093 test_efer(GUEST_EFER, "GUEST_EFER", ENT_CONTROLS, 7094 ctrl_enter_rev.clr & ENT_LOAD_EFER, 7095 ENT_GUEST_64); 7096 } 7097 7098 /* 7099 * PAT values higher than 8 are uninteresting since they're likely lumped 7100 * in with "8". We only test values above 8 one bit at a time, 7101 * in order to reduce the number of VM-Entries and keep the runtime reasonable. 7102 */ 7103 #define PAT_VAL_LIMIT 8 7104 7105 static void test_pat(u32 field, const char * field_name, u32 ctrl_field, 7106 u64 ctrl_bit) 7107 { 7108 u32 ctrl_saved = vmcs_read(ctrl_field); 7109 u64 pat_saved = vmcs_read(field); 7110 u64 i, val; 7111 u32 j; 7112 int error; 7113 7114 vmcs_clear_bits(ctrl_field, ctrl_bit); 7115 7116 for (i = 0; i < 256; i = (i < PAT_VAL_LIMIT) ? i + 1 : i * 2) { 7117 /* Test PAT0..PAT7 fields */ 7118 for (j = 0; j < (i ? 8 : 1); j++) { 7119 val = i << j * 8; 7120 vmcs_write(field, val); 7121 if (field == HOST_PAT) { 7122 report_prefix_pushf("%s %lx", field_name, val); 7123 test_vmx_vmlaunch(0); 7124 report_prefix_pop(); 7125 7126 } else { // GUEST_PAT 7127 enter_guest(); 7128 report_guest_state_test("ENT_LOAD_PAT enabled", 7129 VMX_VMCALL, val, 7130 "GUEST_PAT"); 7131 } 7132 } 7133 } 7134 7135 vmcs_set_bits(ctrl_field, ctrl_bit); 7136 for (i = 0; i < 256; i = (i < PAT_VAL_LIMIT) ? i + 1 : i * 2) { 7137 /* Test PAT0..PAT7 fields */ 7138 for (j = 0; j < (i ? 8 : 1); j++) { 7139 val = i << j * 8; 7140 vmcs_write(field, val); 7141 7142 if (field == HOST_PAT) { 7143 report_prefix_pushf("%s %lx", field_name, val); 7144 if (i == 0x2 || i == 0x3 || i >= 0x8) 7145 error = 7146 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD; 7147 else 7148 error = 0; 7149 7150 test_vmx_vmlaunch(error); 7151 report_prefix_pop(); 7152 7153 } else { // GUEST_PAT 7154 if (i == 0x2 || i == 0x3 || i >= 0x8) { 7155 enter_guest_with_invalid_guest_state(); 7156 report_guest_state_test("ENT_LOAD_PAT " 7157 "enabled", 7158 VMX_FAIL_STATE | VMX_ENTRY_FAILURE, 7159 val, 7160 "GUEST_PAT"); 7161 } else { 7162 enter_guest(); 7163 report_guest_state_test("ENT_LOAD_PAT " 7164 "enabled", 7165 VMX_VMCALL, 7166 val, 7167 "GUEST_PAT"); 7168 } 7169 } 7170 7171 } 7172 } 7173 7174 vmcs_write(ctrl_field, ctrl_saved); 7175 vmcs_write(field, pat_saved); 7176 } 7177 7178 /* 7179 * If the "load IA32_PAT" VM-exit control is 1, the value of the field 7180 * for the IA32_PAT MSR must be one that could be written by WRMSR 7181 * without fault at CPL 0. Specifically, each of the 8 bytes in the 7182 * field must have one of the values 0 (UC), 1 (WC), 4 (WT), 5 (WP), 7183 * 6 (WB), or 7 (UC-). 7184 * 7185 * [Intel SDM] 7186 */ 7187 static void test_load_host_pat(void) 7188 { 7189 /* 7190 * "load IA32_PAT" VM-exit control 7191 */ 7192 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) { 7193 printf("\"Load-IA32-PAT\" exit control not supported\n"); 7194 return; 7195 } 7196 7197 test_pat(HOST_PAT, "HOST_PAT", EXI_CONTROLS, EXI_LOAD_PAT); 7198 } 7199 7200 union cpuidA_eax { 7201 struct { 7202 unsigned int version_id:8; 7203 unsigned int num_counters_gp:8; 7204 unsigned int bit_width:8; 7205 unsigned int mask_length:8; 7206 } split; 7207 unsigned int full; 7208 }; 7209 7210 union cpuidA_edx { 7211 struct { 7212 unsigned int num_counters_fixed:5; 7213 unsigned int bit_width_fixed:8; 7214 unsigned int reserved:9; 7215 } split; 7216 unsigned int full; 7217 }; 7218 7219 static bool valid_pgc(u64 val) 7220 { 7221 struct cpuid id; 7222 union cpuidA_eax eax; 7223 union cpuidA_edx edx; 7224 u64 mask; 7225 7226 id = cpuid(0xA); 7227 eax.full = id.a; 7228 edx.full = id.d; 7229 mask = ~(((1ull << eax.split.num_counters_gp) - 1) | 7230 (((1ull << edx.split.num_counters_fixed) - 1) << 32)); 7231 7232 return !(val & mask); 7233 } 7234 7235 static void test_pgc_vmlaunch(u32 xerror, u32 xreason, bool xfail, bool host) 7236 { 7237 u32 inst_err; 7238 u64 obs; 7239 bool success; 7240 struct vmx_state_area_test_data *data = &vmx_state_area_test_data; 7241 7242 if (host) { 7243 success = vmlaunch_succeeds(); 7244 obs = rdmsr(data->msr); 7245 if (!success) { 7246 inst_err = vmcs_read(VMX_INST_ERROR); 7247 report(xerror == inst_err, "vmlaunch failed, " 7248 "VMX Inst Error is %d (expected %d)", 7249 inst_err, xerror); 7250 } else { 7251 report(!data->enabled || data->exp == obs, 7252 "Host state is 0x%lx (expected 0x%lx)", 7253 obs, data->exp); 7254 report(success != xfail, "vmlaunch succeeded"); 7255 } 7256 } else { 7257 if (xfail) { 7258 enter_guest_with_invalid_guest_state(); 7259 } else { 7260 enter_guest(); 7261 } 7262 report_guest_state_test("load GUEST_PERF_GLOBAL_CTRL", 7263 xreason, GUEST_PERF_GLOBAL_CTRL, 7264 "GUEST_PERF_GLOBAL_CTRL"); 7265 } 7266 } 7267 7268 /* 7269 * test_load_perf_global_ctrl is a generic function for testing the 7270 * "load IA32_PERF_GLOBAL_CTRL" VM-{Entry,Exit} controls. This test function 7271 * tests the provided ctrl_val when disabled and enabled. 7272 * 7273 * @nr: VMCS field number corresponding to the host/guest state field 7274 * @name: Name of the above VMCS field for printing in test report 7275 * @ctrl_nr: VMCS field number corresponding to the VM-{Entry,Exit} control 7276 * @ctrl_val: Bit to set on the ctrl_field 7277 */ 7278 static void test_perf_global_ctrl(u32 nr, const char *name, u32 ctrl_nr, 7279 const char *ctrl_name, u64 ctrl_val) 7280 { 7281 u64 ctrl_saved = vmcs_read(ctrl_nr); 7282 u64 pgc_saved = vmcs_read(nr); 7283 u64 i, val; 7284 bool host = nr == HOST_PERF_GLOBAL_CTRL; 7285 struct vmx_state_area_test_data *data = &vmx_state_area_test_data; 7286 7287 data->msr = MSR_CORE_PERF_GLOBAL_CTRL; 7288 msr_bmp_init(); 7289 vmcs_write(ctrl_nr, ctrl_saved & ~ctrl_val); 7290 data->enabled = false; 7291 report_prefix_pushf("\"load IA32_PERF_GLOBAL_CTRL\"=0 on %s", 7292 ctrl_name); 7293 7294 for (i = 0; i < 64; i++) { 7295 val = 1ull << i; 7296 vmcs_write(nr, val); 7297 report_prefix_pushf("%s = 0x%lx", name, val); 7298 test_pgc_vmlaunch(0, VMX_VMCALL, false, host); 7299 report_prefix_pop(); 7300 } 7301 report_prefix_pop(); 7302 7303 vmcs_write(ctrl_nr, ctrl_saved | ctrl_val); 7304 data->enabled = true; 7305 report_prefix_pushf("\"load IA32_PERF_GLOBAL_CTRL\"=1 on %s", 7306 ctrl_name); 7307 for (i = 0; i < 64; i++) { 7308 val = 1ull << i; 7309 data->exp = val; 7310 vmcs_write(nr, val); 7311 report_prefix_pushf("%s = 0x%lx", name, val); 7312 if (valid_pgc(val)) { 7313 test_pgc_vmlaunch(0, VMX_VMCALL, false, host); 7314 } else { 7315 if (host) 7316 test_pgc_vmlaunch( 7317 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, 7318 0, 7319 true, 7320 host); 7321 else 7322 test_pgc_vmlaunch( 7323 0, 7324 VMX_ENTRY_FAILURE | VMX_FAIL_STATE, 7325 true, 7326 host); 7327 } 7328 report_prefix_pop(); 7329 } 7330 7331 data->enabled = false; 7332 report_prefix_pop(); 7333 vmcs_write(ctrl_nr, ctrl_saved); 7334 vmcs_write(nr, pgc_saved); 7335 } 7336 7337 static void test_load_host_perf_global_ctrl(void) 7338 { 7339 if (!(ctrl_exit_rev.clr & EXI_LOAD_PERF)) { 7340 printf("\"load IA32_PERF_GLOBAL_CTRL\" exit control not supported\n"); 7341 return; 7342 } 7343 7344 test_perf_global_ctrl(HOST_PERF_GLOBAL_CTRL, "HOST_PERF_GLOBAL_CTRL", 7345 EXI_CONTROLS, "EXI_CONTROLS", EXI_LOAD_PERF); 7346 } 7347 7348 7349 static void test_load_guest_perf_global_ctrl(void) 7350 { 7351 if (!(ctrl_enter_rev.clr & ENT_LOAD_PERF)) { 7352 printf("\"load IA32_PERF_GLOBAL_CTRL\" entry control not supported\n"); 7353 return; 7354 } 7355 7356 test_perf_global_ctrl(GUEST_PERF_GLOBAL_CTRL, "GUEST_PERF_GLOBAL_CTRL", 7357 ENT_CONTROLS, "ENT_CONTROLS", ENT_LOAD_PERF); 7358 } 7359 7360 7361 /* 7362 * test_vmcs_field - test a value for the given VMCS field 7363 * @field: VMCS field 7364 * @field_name: string name of VMCS field 7365 * @bit_start: starting bit 7366 * @bit_end: ending bit 7367 * @val: value that the bit range must or must not contain 7368 * @valid_val: whether value given in 'val' must be valid or not 7369 * @error: expected VMCS error when vmentry fails for an invalid value 7370 */ 7371 static void test_vmcs_field(u64 field, const char *field_name, u32 bit_start, 7372 u32 bit_end, u64 val, bool valid_val, u32 error) 7373 { 7374 u64 field_saved = vmcs_read(field); 7375 u32 i; 7376 u64 tmp; 7377 u32 bit_on; 7378 u64 mask = ~0ull; 7379 7380 mask = (mask >> bit_end) << bit_end; 7381 mask = mask | ((1 << bit_start) - 1); 7382 tmp = (field_saved & mask) | (val << bit_start); 7383 7384 vmcs_write(field, tmp); 7385 report_prefix_pushf("%s %lx", field_name, tmp); 7386 if (valid_val) 7387 test_vmx_vmlaunch(0); 7388 else 7389 test_vmx_vmlaunch(error); 7390 report_prefix_pop(); 7391 7392 for (i = bit_start; i <= bit_end; i = i + 2) { 7393 bit_on = ((1ull < i) & (val << bit_start)) ? 0 : 1; 7394 if (bit_on) 7395 tmp = field_saved | (1ull << i); 7396 else 7397 tmp = field_saved & ~(1ull << i); 7398 vmcs_write(field, tmp); 7399 report_prefix_pushf("%s %lx", field_name, tmp); 7400 if (valid_val) 7401 test_vmx_vmlaunch(error); 7402 else 7403 test_vmx_vmlaunch(0); 7404 report_prefix_pop(); 7405 } 7406 7407 vmcs_write(field, field_saved); 7408 } 7409 7410 static void test_canonical(u64 field, const char * field_name, bool host) 7411 { 7412 u64 addr_saved = vmcs_read(field); 7413 7414 if (is_canonical(addr_saved)) { 7415 if (host) { 7416 report_prefix_pushf("%s %lx", field_name, addr_saved); 7417 test_vmx_vmlaunch(0); 7418 report_prefix_pop(); 7419 } else { 7420 enter_guest(); 7421 report_guest_state_test("Test canonical address", 7422 VMX_VMCALL, addr_saved, 7423 field_name); 7424 } 7425 7426 vmcs_write(field, NONCANONICAL); 7427 7428 if (host) { 7429 report_prefix_pushf("%s %llx", field_name, NONCANONICAL); 7430 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7431 report_prefix_pop(); 7432 } else { 7433 enter_guest_with_invalid_guest_state(); 7434 report_guest_state_test("Test canonical address", 7435 VMX_FAIL_STATE | VMX_ENTRY_FAILURE, 7436 NONCANONICAL, field_name); 7437 } 7438 7439 vmcs_write(field, addr_saved); 7440 } else { 7441 if (host) { 7442 report_prefix_pushf("%s %llx", field_name, NONCANONICAL); 7443 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7444 report_prefix_pop(); 7445 } else { 7446 enter_guest_with_invalid_guest_state(); 7447 report_guest_state_test("Test canonical address", 7448 VMX_FAIL_STATE | VMX_ENTRY_FAILURE, 7449 NONCANONICAL, field_name); 7450 } 7451 } 7452 } 7453 7454 #define TEST_RPL_TI_FLAGS(reg, name) \ 7455 test_vmcs_field(reg, name, 0, 2, 0x0, true, \ 7456 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7457 7458 #define TEST_CS_TR_FLAGS(reg, name) \ 7459 test_vmcs_field(reg, name, 3, 15, 0x0000, false, \ 7460 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7461 7462 /* 7463 * 1. In the selector field for each of CS, SS, DS, ES, FS, GS and TR, the 7464 * RPL (bits 1:0) and the TI flag (bit 2) must be 0. 7465 * 2. The selector fields for CS and TR cannot be 0000H. 7466 * 3. The selector field for SS cannot be 0000H if the "host address-space 7467 * size" VM-exit control is 0. 7468 * 4. On processors that support Intel 64 architecture, the base-address 7469 * fields for FS, GS and TR must contain canonical addresses. 7470 */ 7471 static void test_host_segment_regs(void) 7472 { 7473 u16 selector_saved; 7474 7475 /* 7476 * Test RPL and TI flags 7477 */ 7478 TEST_RPL_TI_FLAGS(HOST_SEL_CS, "HOST_SEL_CS"); 7479 TEST_RPL_TI_FLAGS(HOST_SEL_SS, "HOST_SEL_SS"); 7480 TEST_RPL_TI_FLAGS(HOST_SEL_DS, "HOST_SEL_DS"); 7481 TEST_RPL_TI_FLAGS(HOST_SEL_ES, "HOST_SEL_ES"); 7482 TEST_RPL_TI_FLAGS(HOST_SEL_FS, "HOST_SEL_FS"); 7483 TEST_RPL_TI_FLAGS(HOST_SEL_GS, "HOST_SEL_GS"); 7484 TEST_RPL_TI_FLAGS(HOST_SEL_TR, "HOST_SEL_TR"); 7485 7486 /* 7487 * Test that CS and TR fields can not be 0x0000 7488 */ 7489 TEST_CS_TR_FLAGS(HOST_SEL_CS, "HOST_SEL_CS"); 7490 TEST_CS_TR_FLAGS(HOST_SEL_TR, "HOST_SEL_TR"); 7491 7492 /* 7493 * SS field can not be 0x0000 if "host address-space size" VM-exit 7494 * control is 0 7495 */ 7496 selector_saved = vmcs_read(HOST_SEL_SS); 7497 vmcs_write(HOST_SEL_SS, 0); 7498 report_prefix_pushf("HOST_SEL_SS 0"); 7499 if (vmcs_read(EXI_CONTROLS) & EXI_HOST_64) { 7500 test_vmx_vmlaunch(0); 7501 } else { 7502 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7503 } 7504 report_prefix_pop(); 7505 7506 vmcs_write(HOST_SEL_SS, selector_saved); 7507 7508 #ifdef __x86_64__ 7509 /* 7510 * Base address for FS, GS and TR must be canonical 7511 */ 7512 test_canonical(HOST_BASE_FS, "HOST_BASE_FS", true); 7513 test_canonical(HOST_BASE_GS, "HOST_BASE_GS", true); 7514 test_canonical(HOST_BASE_TR, "HOST_BASE_TR", true); 7515 #endif 7516 } 7517 7518 /* 7519 * On processors that support Intel 64 architecture, the base-address 7520 * fields for GDTR and IDTR must contain canonical addresses. 7521 */ 7522 static void test_host_desc_tables(void) 7523 { 7524 #ifdef __x86_64__ 7525 test_canonical(HOST_BASE_GDTR, "HOST_BASE_GDTR", true); 7526 test_canonical(HOST_BASE_IDTR, "HOST_BASE_IDTR", true); 7527 #endif 7528 } 7529 7530 /* 7531 * If the "host address-space size" VM-exit control is 0, the following must 7532 * hold: 7533 * - The "IA-32e mode guest" VM-entry control is 0. 7534 * - Bit 17 of the CR4 field (corresponding to CR4.PCIDE) is 0. 7535 * - Bits 63:32 in the RIP field are 0. 7536 * 7537 * If the "host address-space size" VM-exit control is 1, the following must 7538 * hold: 7539 * - Bit 5 of the CR4 field (corresponding to CR4.PAE) is 1. 7540 * - The RIP field contains a canonical address. 7541 * 7542 */ 7543 static void test_host_addr_size(void) 7544 { 7545 u64 cr4_saved = vmcs_read(HOST_CR4); 7546 u64 rip_saved = vmcs_read(HOST_RIP); 7547 u64 entry_ctrl_saved = vmcs_read(ENT_CONTROLS); 7548 int i; 7549 u64 tmp; 7550 7551 if (vmcs_read(EXI_CONTROLS) & EXI_HOST_64) { 7552 vmcs_write(ENT_CONTROLS, entry_ctrl_saved | ENT_GUEST_64); 7553 report_prefix_pushf("\"IA-32e mode guest\" enabled"); 7554 test_vmx_vmlaunch(0); 7555 report_prefix_pop(); 7556 7557 vmcs_write(HOST_CR4, cr4_saved | X86_CR4_PCIDE); 7558 report_prefix_pushf("\"CR4.PCIDE\" set"); 7559 test_vmx_vmlaunch(0); 7560 report_prefix_pop(); 7561 7562 for (i = 32; i <= 63; i = i + 4) { 7563 tmp = rip_saved | 1ull << i; 7564 vmcs_write(HOST_RIP, tmp); 7565 report_prefix_pushf("HOST_RIP %lx", tmp); 7566 test_vmx_vmlaunch(0); 7567 report_prefix_pop(); 7568 } 7569 7570 if (cr4_saved & X86_CR4_PAE) { 7571 vmcs_write(HOST_CR4, cr4_saved & ~X86_CR4_PAE); 7572 report_prefix_pushf("\"CR4.PAE\" unset"); 7573 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7574 } else { 7575 report_prefix_pushf("\"CR4.PAE\" set"); 7576 test_vmx_vmlaunch(0); 7577 } 7578 report_prefix_pop(); 7579 7580 vmcs_write(HOST_RIP, NONCANONICAL); 7581 report_prefix_pushf("HOST_RIP %llx", NONCANONICAL); 7582 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7583 report_prefix_pop(); 7584 7585 vmcs_write(ENT_CONTROLS, entry_ctrl_saved | ENT_GUEST_64); 7586 vmcs_write(HOST_RIP, rip_saved); 7587 vmcs_write(HOST_CR4, cr4_saved); 7588 } 7589 } 7590 7591 /* 7592 * Check that the virtual CPU checks the VMX Host State Area as 7593 * documented in the Intel SDM. 7594 */ 7595 static void vmx_host_state_area_test(void) 7596 { 7597 /* 7598 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 7599 * fail due to invalid guest state, should we make it that 7600 * far. 7601 */ 7602 vmcs_write(GUEST_RFLAGS, 0); 7603 7604 test_host_ctl_regs(); 7605 7606 test_canonical(HOST_SYSENTER_ESP, "HOST_SYSENTER_ESP", true); 7607 test_canonical(HOST_SYSENTER_EIP, "HOST_SYSENTER_EIP", true); 7608 7609 test_host_efer(); 7610 test_load_host_pat(); 7611 test_host_segment_regs(); 7612 test_host_desc_tables(); 7613 test_host_addr_size(); 7614 test_load_host_perf_global_ctrl(); 7615 } 7616 7617 /* 7618 * If the "load debug controls" VM-entry control is 1, bits 63:32 in 7619 * the DR7 field must be 0. 7620 * 7621 * [Intel SDM] 7622 */ 7623 static void test_guest_dr7(void) 7624 { 7625 u32 ent_saved = vmcs_read(ENT_CONTROLS); 7626 u64 dr7_saved = vmcs_read(GUEST_DR7); 7627 u64 val; 7628 int i; 7629 7630 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS) { 7631 vmcs_clear_bits(ENT_CONTROLS, ENT_LOAD_DBGCTLS); 7632 for (i = 0; i < 64; i++) { 7633 val = 1ull << i; 7634 vmcs_write(GUEST_DR7, val); 7635 enter_guest(); 7636 report_guest_state_test("ENT_LOAD_DBGCTLS disabled", 7637 VMX_VMCALL, val, "GUEST_DR7"); 7638 } 7639 } 7640 if (ctrl_enter_rev.clr & ENT_LOAD_DBGCTLS) { 7641 vmcs_set_bits(ENT_CONTROLS, ENT_LOAD_DBGCTLS); 7642 for (i = 0; i < 64; i++) { 7643 val = 1ull << i; 7644 vmcs_write(GUEST_DR7, val); 7645 if (i < 32) 7646 enter_guest(); 7647 else 7648 enter_guest_with_invalid_guest_state(); 7649 report_guest_state_test("ENT_LOAD_DBGCTLS enabled", 7650 i < 32 ? VMX_VMCALL : 7651 VMX_ENTRY_FAILURE | 7652 VMX_FAIL_STATE, 7653 val, "GUEST_DR7"); 7654 } 7655 } 7656 vmcs_write(GUEST_DR7, dr7_saved); 7657 vmcs_write(ENT_CONTROLS, ent_saved); 7658 } 7659 7660 /* 7661 * If the "load IA32_PAT" VM-entry control is 1, the value of the field 7662 * for the IA32_PAT MSR must be one that could be written by WRMSR 7663 * without fault at CPL 0. Specifically, each of the 8 bytes in the 7664 * field must have one of the values 0 (UC), 1 (WC), 4 (WT), 5 (WP), 7665 * 6 (WB), or 7 (UC-). 7666 * 7667 * [Intel SDM] 7668 */ 7669 static void test_load_guest_pat(void) 7670 { 7671 /* 7672 * "load IA32_PAT" VM-entry control 7673 */ 7674 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 7675 printf("\"Load-IA32-PAT\" entry control not supported\n"); 7676 return; 7677 } 7678 7679 test_pat(GUEST_PAT, "GUEST_PAT", ENT_CONTROLS, ENT_LOAD_PAT); 7680 } 7681 7682 /* 7683 * Check that the virtual CPU checks the VMX Guest State Area as 7684 * documented in the Intel SDM. 7685 */ 7686 static void vmx_guest_state_area_test(void) 7687 { 7688 vmx_set_test_stage(1); 7689 test_set_guest(guest_state_test_main); 7690 7691 /* 7692 * The IA32_SYSENTER_ESP field and the IA32_SYSENTER_EIP field 7693 * must each contain a canonical address. 7694 */ 7695 test_canonical(GUEST_SYSENTER_ESP, "GUEST_SYSENTER_ESP", false); 7696 test_canonical(GUEST_SYSENTER_EIP, "GUEST_SYSENTER_EIP", false); 7697 7698 test_guest_dr7(); 7699 test_load_guest_pat(); 7700 test_guest_efer(); 7701 test_load_guest_perf_global_ctrl(); 7702 7703 /* 7704 * Let the guest finish execution 7705 */ 7706 vmx_set_test_stage(2); 7707 enter_guest(); 7708 } 7709 7710 static bool valid_vmcs_for_vmentry(void) 7711 { 7712 struct vmcs *current_vmcs = NULL; 7713 7714 if (vmcs_save(¤t_vmcs)) 7715 return false; 7716 7717 return current_vmcs && !current_vmcs->hdr.shadow_vmcs; 7718 } 7719 7720 static void try_vmentry_in_movss_shadow(void) 7721 { 7722 u32 vm_inst_err; 7723 u32 flags; 7724 bool early_failure = false; 7725 u32 expected_flags = X86_EFLAGS_FIXED; 7726 bool valid_vmcs = valid_vmcs_for_vmentry(); 7727 7728 expected_flags |= valid_vmcs ? X86_EFLAGS_ZF : X86_EFLAGS_CF; 7729 7730 /* 7731 * Indirectly set VM_INST_ERR to 12 ("VMREAD/VMWRITE from/to 7732 * unsupported VMCS component"). 7733 */ 7734 vmcs_write(~0u, 0); 7735 7736 __asm__ __volatile__ ("mov %[host_rsp], %%edx;" 7737 "vmwrite %%rsp, %%rdx;" 7738 "mov 0f, %%rax;" 7739 "mov %[host_rip], %%edx;" 7740 "vmwrite %%rax, %%rdx;" 7741 "mov $-1, %%ah;" 7742 "sahf;" 7743 "mov %%ss, %%ax;" 7744 "mov %%ax, %%ss;" 7745 "vmlaunch;" 7746 "mov $1, %[early_failure];" 7747 "0: lahf;" 7748 "movzbl %%ah, %[flags]" 7749 : [early_failure] "+r" (early_failure), 7750 [flags] "=&a" (flags) 7751 : [host_rsp] "i" (HOST_RSP), 7752 [host_rip] "i" (HOST_RIP) 7753 : "rdx", "cc", "memory"); 7754 vm_inst_err = vmcs_read(VMX_INST_ERROR); 7755 7756 report(early_failure, "Early VM-entry failure"); 7757 report(flags == expected_flags, "RFLAGS[8:0] is %x (actual %x)", 7758 expected_flags, flags); 7759 if (valid_vmcs) 7760 report(vm_inst_err == VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, 7761 "VM-instruction error is %d (actual %d)", 7762 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, vm_inst_err); 7763 } 7764 7765 static void vmentry_movss_shadow_test(void) 7766 { 7767 struct vmcs *orig_vmcs; 7768 7769 TEST_ASSERT(!vmcs_save(&orig_vmcs)); 7770 7771 /* 7772 * Set the launched flag on the current VMCS to verify the correct 7773 * error priority, below. 7774 */ 7775 test_set_guest(v2_null_test_guest); 7776 enter_guest(); 7777 7778 /* 7779 * With bit 1 of the guest's RFLAGS clear, VM-entry should 7780 * fail due to invalid guest state (if we make it that far). 7781 */ 7782 vmcs_write(GUEST_RFLAGS, 0); 7783 7784 /* 7785 * "VM entry with events blocked by MOV SS" takes precedence over 7786 * "VMLAUNCH with non-clear VMCS." 7787 */ 7788 report_prefix_push("valid current-VMCS"); 7789 try_vmentry_in_movss_shadow(); 7790 report_prefix_pop(); 7791 7792 /* 7793 * VMfailInvalid takes precedence over "VM entry with events 7794 * blocked by MOV SS." 7795 */ 7796 TEST_ASSERT(!vmcs_clear(orig_vmcs)); 7797 report_prefix_push("no current-VMCS"); 7798 try_vmentry_in_movss_shadow(); 7799 report_prefix_pop(); 7800 7801 TEST_ASSERT(!make_vmcs_current(orig_vmcs)); 7802 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 7803 } 7804 7805 static void vmx_cr_load_test(void) 7806 { 7807 unsigned long cr3, cr4, orig_cr3, orig_cr4; 7808 7809 orig_cr4 = read_cr4(); 7810 orig_cr3 = read_cr3(); 7811 7812 if (!this_cpu_has(X86_FEATURE_PCID)) { 7813 report_skip("PCID not detected"); 7814 return; 7815 } 7816 if (!this_cpu_has(X86_FEATURE_MCE)) { 7817 report_skip("MCE not detected"); 7818 return; 7819 } 7820 7821 TEST_ASSERT(!(orig_cr3 & X86_CR3_PCID_MASK)); 7822 7823 /* Enable PCID for L1. */ 7824 cr4 = orig_cr4 | X86_CR4_PCIDE; 7825 cr3 = orig_cr3 | 0x1; 7826 TEST_ASSERT(!write_cr4_checking(cr4)); 7827 write_cr3(cr3); 7828 7829 test_set_guest(v2_null_test_guest); 7830 vmcs_write(HOST_CR4, cr4); 7831 vmcs_write(HOST_CR3, cr3); 7832 enter_guest(); 7833 7834 /* 7835 * No exception is expected. 7836 * 7837 * NB. KVM loads the last guest write to CR4 into CR4 read 7838 * shadow. In order to trigger an exit to KVM, we can toggle a 7839 * bit that is owned by KVM. We use CR4.MCE, which shall 7840 * have no side effect because normally no guest MCE (e.g., as the 7841 * result of bad memory) would happen during this test. 7842 */ 7843 TEST_ASSERT(!write_cr4_checking(cr4 ^ X86_CR4_MCE)); 7844 7845 /* Cleanup L1 state. */ 7846 write_cr3(orig_cr3); 7847 TEST_ASSERT(!write_cr4_checking(orig_cr4)); 7848 } 7849 7850 static void vmx_nm_test_guest(void) 7851 { 7852 write_cr0(read_cr0() | X86_CR0_TS); 7853 asm volatile("fnop"); 7854 } 7855 7856 static void check_nm_exit(const char *test) 7857 { 7858 u32 reason = vmcs_read(EXI_REASON); 7859 u32 intr_info = vmcs_read(EXI_INTR_INFO); 7860 const u32 expected = INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 7861 NM_VECTOR; 7862 7863 report(reason == VMX_EXC_NMI && intr_info == expected, "%s", test); 7864 } 7865 7866 /* 7867 * This test checks that: 7868 * 7869 * (a) If L2 launches with CR0.TS clear, but later sets CR0.TS, then 7870 * a subsequent #NM VM-exit is reflected to L1. 7871 * 7872 * (b) If L2 launches with CR0.TS clear and CR0.EM set, then a 7873 * subsequent #NM VM-exit is reflected to L1. 7874 */ 7875 static void vmx_nm_test(void) 7876 { 7877 unsigned long cr0 = read_cr0(); 7878 7879 test_set_guest(vmx_nm_test_guest); 7880 7881 /* 7882 * L1 wants to intercept #NM exceptions encountered in L2. 7883 */ 7884 vmcs_write(EXC_BITMAP, 1 << NM_VECTOR); 7885 7886 /* 7887 * Launch L2 with CR0.TS clear, but don't claim host ownership of 7888 * any CR0 bits. L2 will set CR0.TS and then try to execute fnop, 7889 * which will raise #NM. L0 should reflect the #NM VM-exit to L1. 7890 */ 7891 vmcs_write(CR0_MASK, 0); 7892 vmcs_write(GUEST_CR0, cr0 & ~X86_CR0_TS); 7893 enter_guest(); 7894 check_nm_exit("fnop with CR0.TS set in L2 triggers #NM VM-exit to L1"); 7895 7896 /* 7897 * Re-enter L2 at the fnop instruction, with CR0.TS clear but 7898 * CR0.EM set. The fnop will still raise #NM, and L0 should 7899 * reflect the #NM VM-exit to L1. 7900 */ 7901 vmcs_write(GUEST_CR0, (cr0 & ~X86_CR0_TS) | X86_CR0_EM); 7902 enter_guest(); 7903 check_nm_exit("fnop with CR0.EM set in L2 triggers #NM VM-exit to L1"); 7904 7905 /* 7906 * Re-enter L2 at the fnop instruction, with both CR0.TS and 7907 * CR0.EM clear. There will be no #NM, and the L2 guest should 7908 * exit normally. 7909 */ 7910 vmcs_write(GUEST_CR0, cr0 & ~(X86_CR0_TS | X86_CR0_EM)); 7911 enter_guest(); 7912 } 7913 7914 bool vmx_pending_event_ipi_fired; 7915 static void vmx_pending_event_ipi_isr(isr_regs_t *regs) 7916 { 7917 vmx_pending_event_ipi_fired = true; 7918 eoi(); 7919 } 7920 7921 bool vmx_pending_event_guest_run; 7922 static void vmx_pending_event_guest(void) 7923 { 7924 vmcall(); 7925 vmx_pending_event_guest_run = true; 7926 } 7927 7928 static void vmx_pending_event_test_core(bool guest_hlt) 7929 { 7930 int ipi_vector = 0xf1; 7931 7932 vmx_pending_event_ipi_fired = false; 7933 handle_irq(ipi_vector, vmx_pending_event_ipi_isr); 7934 7935 vmx_pending_event_guest_run = false; 7936 test_set_guest(vmx_pending_event_guest); 7937 7938 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 7939 7940 enter_guest(); 7941 skip_exit_vmcall(); 7942 7943 if (guest_hlt) 7944 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 7945 7946 irq_disable(); 7947 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | 7948 APIC_DM_FIXED | ipi_vector, 7949 0); 7950 7951 enter_guest(); 7952 7953 assert_exit_reason(VMX_EXTINT); 7954 report(!vmx_pending_event_guest_run, 7955 "Guest did not run before host received IPI"); 7956 7957 irq_enable(); 7958 asm volatile ("nop"); 7959 irq_disable(); 7960 report(vmx_pending_event_ipi_fired, 7961 "Got pending interrupt after IRQ enabled"); 7962 7963 if (guest_hlt) 7964 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 7965 7966 enter_guest(); 7967 report(vmx_pending_event_guest_run, 7968 "Guest finished running when no interrupt"); 7969 } 7970 7971 static void vmx_pending_event_test(void) 7972 { 7973 vmx_pending_event_test_core(false); 7974 } 7975 7976 static void vmx_pending_event_hlt_test(void) 7977 { 7978 vmx_pending_event_test_core(true); 7979 } 7980 7981 static int vmx_window_test_db_count; 7982 7983 static void vmx_window_test_db_handler(struct ex_regs *regs) 7984 { 7985 vmx_window_test_db_count++; 7986 } 7987 7988 static void vmx_nmi_window_test_guest(void) 7989 { 7990 handle_exception(DB_VECTOR, vmx_window_test_db_handler); 7991 7992 asm volatile("vmcall\n\t" 7993 "nop\n\t"); 7994 7995 handle_exception(DB_VECTOR, NULL); 7996 } 7997 7998 static void verify_nmi_window_exit(u64 rip) 7999 { 8000 u32 exit_reason = vmcs_read(EXI_REASON); 8001 8002 report(exit_reason == VMX_NMI_WINDOW, 8003 "Exit reason (%d) is 'NMI window'", exit_reason); 8004 report(vmcs_read(GUEST_RIP) == rip, "RIP (%#lx) is %#lx", 8005 vmcs_read(GUEST_RIP), rip); 8006 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 8007 } 8008 8009 static void vmx_nmi_window_test(void) 8010 { 8011 u64 nop_addr; 8012 void *db_fault_addr = get_idt_addr(&boot_idt[DB_VECTOR]); 8013 8014 if (!(ctrl_pin_rev.clr & PIN_VIRT_NMI)) { 8015 report_skip("CPU does not support the \"Virtual NMIs\" VM-execution control."); 8016 return; 8017 } 8018 8019 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 8020 report_skip("CPU does not support the \"NMI-window exiting\" VM-execution control."); 8021 return; 8022 } 8023 8024 vmx_window_test_db_count = 0; 8025 8026 report_prefix_push("NMI-window"); 8027 test_set_guest(vmx_nmi_window_test_guest); 8028 vmcs_set_bits(PIN_CONTROLS, PIN_VIRT_NMI); 8029 enter_guest(); 8030 skip_exit_vmcall(); 8031 nop_addr = vmcs_read(GUEST_RIP); 8032 8033 /* 8034 * Ask for "NMI-window exiting," and expect an immediate VM-exit. 8035 * RIP will not advance. 8036 */ 8037 report_prefix_push("active, no blocking"); 8038 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 8039 enter_guest(); 8040 verify_nmi_window_exit(nop_addr); 8041 report_prefix_pop(); 8042 8043 /* 8044 * Ask for "NMI-window exiting" in a MOV-SS shadow, and expect 8045 * a VM-exit on the next instruction after the nop. (The nop 8046 * is one byte.) 8047 */ 8048 report_prefix_push("active, blocking by MOV-SS"); 8049 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 8050 enter_guest(); 8051 verify_nmi_window_exit(nop_addr + 1); 8052 report_prefix_pop(); 8053 8054 /* 8055 * Ask for "NMI-window exiting" (with event injection), and 8056 * expect a VM-exit after the event is injected. (RIP should 8057 * be at the address specified in the IDT entry for #DB.) 8058 */ 8059 report_prefix_push("active, no blocking, injecting #DB"); 8060 vmcs_write(ENT_INTR_INFO, 8061 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 8062 enter_guest(); 8063 verify_nmi_window_exit((u64)db_fault_addr); 8064 report_prefix_pop(); 8065 8066 /* 8067 * Ask for "NMI-window exiting" with NMI blocking, and expect 8068 * a VM-exit after the next IRET (i.e. after the #DB handler 8069 * returns). So, RIP should be back at one byte past the nop. 8070 */ 8071 report_prefix_push("active, blocking by NMI"); 8072 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_NMI); 8073 enter_guest(); 8074 verify_nmi_window_exit(nop_addr + 1); 8075 report(vmx_window_test_db_count == 1, 8076 "#DB handler executed once (actual %d times)", 8077 vmx_window_test_db_count); 8078 report_prefix_pop(); 8079 8080 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 8081 report_skip("CPU does not support activity state HLT."); 8082 } else { 8083 /* 8084 * Ask for "NMI-window exiting" when entering activity 8085 * state HLT, and expect an immediate VM-exit. RIP is 8086 * still one byte past the nop. 8087 */ 8088 report_prefix_push("halted, no blocking"); 8089 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8090 enter_guest(); 8091 verify_nmi_window_exit(nop_addr + 1); 8092 report_prefix_pop(); 8093 8094 /* 8095 * Ask for "NMI-window exiting" when entering activity 8096 * state HLT (with event injection), and expect a 8097 * VM-exit after the event is injected. (RIP should be 8098 * at the address specified in the IDT entry for #DB.) 8099 */ 8100 report_prefix_push("halted, no blocking, injecting #DB"); 8101 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8102 vmcs_write(ENT_INTR_INFO, 8103 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 8104 DB_VECTOR); 8105 enter_guest(); 8106 verify_nmi_window_exit((u64)db_fault_addr); 8107 report_prefix_pop(); 8108 } 8109 8110 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 8111 enter_guest(); 8112 report_prefix_pop(); 8113 } 8114 8115 static void vmx_intr_window_test_guest(void) 8116 { 8117 handle_exception(DB_VECTOR, vmx_window_test_db_handler); 8118 8119 /* 8120 * The two consecutive STIs are to ensure that only the first 8121 * one has a shadow. Note that NOP and STI are one byte 8122 * instructions. 8123 */ 8124 asm volatile("vmcall\n\t" 8125 "nop\n\t" 8126 "sti\n\t" 8127 "sti\n\t"); 8128 8129 handle_exception(DB_VECTOR, NULL); 8130 } 8131 8132 static void verify_intr_window_exit(u64 rip) 8133 { 8134 u32 exit_reason = vmcs_read(EXI_REASON); 8135 8136 report(exit_reason == VMX_INTR_WINDOW, 8137 "Exit reason (%d) is 'interrupt window'", exit_reason); 8138 report(vmcs_read(GUEST_RIP) == rip, "RIP (%#lx) is %#lx", 8139 vmcs_read(GUEST_RIP), rip); 8140 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 8141 } 8142 8143 static void vmx_intr_window_test(void) 8144 { 8145 u64 vmcall_addr; 8146 u64 nop_addr; 8147 unsigned int orig_db_gate_type; 8148 void *db_fault_addr = get_idt_addr(&boot_idt[DB_VECTOR]); 8149 8150 if (!(ctrl_cpu_rev[0].clr & CPU_INTR_WINDOW)) { 8151 report_skip("CPU does not support the \"interrupt-window exiting\" VM-execution control."); 8152 return; 8153 } 8154 8155 /* 8156 * Change the IDT entry for #DB from interrupt gate to trap gate, 8157 * so that it won't clear RFLAGS.IF. We don't want interrupts to 8158 * be disabled after vectoring a #DB. 8159 */ 8160 orig_db_gate_type = boot_idt[DB_VECTOR].type; 8161 boot_idt[DB_VECTOR].type = 15; 8162 8163 report_prefix_push("interrupt-window"); 8164 test_set_guest(vmx_intr_window_test_guest); 8165 enter_guest(); 8166 assert_exit_reason(VMX_VMCALL); 8167 vmcall_addr = vmcs_read(GUEST_RIP); 8168 8169 /* 8170 * Ask for "interrupt-window exiting" with RFLAGS.IF set and 8171 * no blocking; expect an immediate VM-exit. Note that we have 8172 * not advanced past the vmcall instruction yet, so RIP should 8173 * point to the vmcall instruction. 8174 */ 8175 report_prefix_push("active, no blocking, RFLAGS.IF=1"); 8176 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8177 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_IF); 8178 enter_guest(); 8179 verify_intr_window_exit(vmcall_addr); 8180 report_prefix_pop(); 8181 8182 /* 8183 * Ask for "interrupt-window exiting" (with event injection) 8184 * with RFLAGS.IF set and no blocking; expect a VM-exit after 8185 * the event is injected. That is, RIP should should be at the 8186 * address specified in the IDT entry for #DB. 8187 */ 8188 report_prefix_push("active, no blocking, RFLAGS.IF=1, injecting #DB"); 8189 vmcs_write(ENT_INTR_INFO, 8190 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 8191 vmcall_addr = vmcs_read(GUEST_RIP); 8192 enter_guest(); 8193 verify_intr_window_exit((u64)db_fault_addr); 8194 report_prefix_pop(); 8195 8196 /* 8197 * Let the L2 guest run through the IRET, back to the VMCALL. 8198 * We have to clear the "interrupt-window exiting" 8199 * VM-execution control, or it would just keep causing 8200 * VM-exits. Then, advance past the VMCALL and set the 8201 * "interrupt-window exiting" VM-execution control again. 8202 */ 8203 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8204 enter_guest(); 8205 skip_exit_vmcall(); 8206 nop_addr = vmcs_read(GUEST_RIP); 8207 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8208 8209 /* 8210 * Ask for "interrupt-window exiting" in a MOV-SS shadow with 8211 * RFLAGS.IF set, and expect a VM-exit on the next 8212 * instruction. (NOP is one byte.) 8213 */ 8214 report_prefix_push("active, blocking by MOV-SS, RFLAGS.IF=1"); 8215 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 8216 enter_guest(); 8217 verify_intr_window_exit(nop_addr + 1); 8218 report_prefix_pop(); 8219 8220 /* 8221 * Back up to the NOP and ask for "interrupt-window exiting" 8222 * in an STI shadow with RFLAGS.IF set, and expect a VM-exit 8223 * on the next instruction. (NOP is one byte.) 8224 */ 8225 report_prefix_push("active, blocking by STI, RFLAGS.IF=1"); 8226 vmcs_write(GUEST_RIP, nop_addr); 8227 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_STI); 8228 enter_guest(); 8229 verify_intr_window_exit(nop_addr + 1); 8230 report_prefix_pop(); 8231 8232 /* 8233 * Ask for "interrupt-window exiting" with RFLAGS.IF clear, 8234 * and expect a VM-exit on the instruction following the STI 8235 * shadow. Only the first STI (which is one byte past the NOP) 8236 * should have a shadow. The second STI (which is two bytes 8237 * past the NOP) has no shadow. Therefore, the interrupt 8238 * window opens at three bytes past the NOP. 8239 */ 8240 report_prefix_push("active, RFLAGS.IF = 0"); 8241 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 8242 enter_guest(); 8243 verify_intr_window_exit(nop_addr + 3); 8244 report_prefix_pop(); 8245 8246 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 8247 report_skip("CPU does not support activity state HLT."); 8248 } else { 8249 /* 8250 * Ask for "interrupt-window exiting" when entering 8251 * activity state HLT, and expect an immediate 8252 * VM-exit. RIP is still three bytes past the nop. 8253 */ 8254 report_prefix_push("halted, no blocking"); 8255 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8256 enter_guest(); 8257 verify_intr_window_exit(nop_addr + 3); 8258 report_prefix_pop(); 8259 8260 /* 8261 * Ask for "interrupt-window exiting" when entering 8262 * activity state HLT (with event injection), and 8263 * expect a VM-exit after the event is injected. That 8264 * is, RIP should should be at the address specified 8265 * in the IDT entry for #DB. 8266 */ 8267 report_prefix_push("halted, no blocking, injecting #DB"); 8268 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8269 vmcs_write(ENT_INTR_INFO, 8270 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 8271 DB_VECTOR); 8272 enter_guest(); 8273 verify_intr_window_exit((u64)db_fault_addr); 8274 report_prefix_pop(); 8275 } 8276 8277 boot_idt[DB_VECTOR].type = orig_db_gate_type; 8278 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8279 enter_guest(); 8280 report_prefix_pop(); 8281 } 8282 8283 #define GUEST_TSC_OFFSET (1u << 30) 8284 8285 static u64 guest_tsc; 8286 8287 static void vmx_store_tsc_test_guest(void) 8288 { 8289 guest_tsc = rdtsc(); 8290 } 8291 8292 /* 8293 * This test ensures that when IA32_TSC is in the VM-exit MSR-store 8294 * list, the value saved is not subject to the TSC offset that is 8295 * applied to RDTSC/RDTSCP/RDMSR(IA32_TSC) in guest execution. 8296 */ 8297 static void vmx_store_tsc_test(void) 8298 { 8299 struct vmx_msr_entry msr_entry = { .index = MSR_IA32_TSC }; 8300 u64 low, high; 8301 8302 if (!(ctrl_cpu_rev[0].clr & CPU_USE_TSC_OFFSET)) { 8303 report_skip("'Use TSC offsetting' not supported"); 8304 return; 8305 } 8306 8307 test_set_guest(vmx_store_tsc_test_guest); 8308 8309 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_USE_TSC_OFFSET); 8310 vmcs_write(EXI_MSR_ST_CNT, 1); 8311 vmcs_write(EXIT_MSR_ST_ADDR, virt_to_phys(&msr_entry)); 8312 vmcs_write(TSC_OFFSET, GUEST_TSC_OFFSET); 8313 8314 low = rdtsc(); 8315 enter_guest(); 8316 high = rdtsc(); 8317 8318 report(low + GUEST_TSC_OFFSET <= guest_tsc && 8319 guest_tsc <= high + GUEST_TSC_OFFSET, 8320 "RDTSC value in the guest (%lu) is in range [%lu, %lu]", 8321 guest_tsc, low + GUEST_TSC_OFFSET, high + GUEST_TSC_OFFSET); 8322 report(low <= msr_entry.value && msr_entry.value <= high, 8323 "IA32_TSC value saved in the VM-exit MSR-store list (%lu) is in range [%lu, %lu]", 8324 msr_entry.value, low, high); 8325 } 8326 8327 static void vmx_db_test_guest(void) 8328 { 8329 /* 8330 * For a hardware generated single-step #DB. 8331 */ 8332 asm volatile("vmcall;" 8333 "nop;" 8334 ".Lpost_nop:"); 8335 /* 8336 * ...in a MOVSS shadow, with pending debug exceptions. 8337 */ 8338 asm volatile("vmcall;" 8339 "nop;" 8340 ".Lpost_movss_nop:"); 8341 /* 8342 * For an L0 synthesized single-step #DB. (L0 intercepts WBINVD and 8343 * emulates it in software.) 8344 */ 8345 asm volatile("vmcall;" 8346 "wbinvd;" 8347 ".Lpost_wbinvd:"); 8348 /* 8349 * ...in a MOVSS shadow, with pending debug exceptions. 8350 */ 8351 asm volatile("vmcall;" 8352 "wbinvd;" 8353 ".Lpost_movss_wbinvd:"); 8354 /* 8355 * For a hardware generated single-step #DB in a transactional region. 8356 */ 8357 asm volatile("vmcall;" 8358 ".Lxbegin: xbegin .Lskip_rtm;" 8359 "xend;" 8360 ".Lskip_rtm:"); 8361 } 8362 8363 /* 8364 * Clear the pending debug exceptions and RFLAGS.TF and re-enter 8365 * L2. No #DB is delivered and L2 continues to the next point of 8366 * interest. 8367 */ 8368 static void dismiss_db(void) 8369 { 8370 vmcs_write(GUEST_PENDING_DEBUG, 0); 8371 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 8372 enter_guest(); 8373 } 8374 8375 /* 8376 * Check a variety of VMCS fields relevant to an intercepted #DB exception. 8377 * Then throw away the #DB exception and resume L2. 8378 */ 8379 static void check_db_exit(bool xfail_qual, bool xfail_dr6, bool xfail_pdbg, 8380 void *expected_rip, u64 expected_exit_qual, 8381 u64 expected_dr6) 8382 { 8383 u32 reason = vmcs_read(EXI_REASON); 8384 u32 intr_info = vmcs_read(EXI_INTR_INFO); 8385 u64 exit_qual = vmcs_read(EXI_QUALIFICATION); 8386 u64 guest_rip = vmcs_read(GUEST_RIP); 8387 u64 guest_pending_dbg = vmcs_read(GUEST_PENDING_DEBUG); 8388 u64 dr6 = read_dr6(); 8389 const u32 expected_intr_info = INTR_INFO_VALID_MASK | 8390 INTR_TYPE_HARD_EXCEPTION | DB_VECTOR; 8391 8392 report(reason == VMX_EXC_NMI && intr_info == expected_intr_info, 8393 "Expected #DB VM-exit"); 8394 report((u64)expected_rip == guest_rip, "Expected RIP %p (actual %lx)", 8395 expected_rip, guest_rip); 8396 report_xfail(xfail_pdbg, 0 == guest_pending_dbg, 8397 "Expected pending debug exceptions 0 (actual %lx)", 8398 guest_pending_dbg); 8399 report_xfail(xfail_qual, expected_exit_qual == exit_qual, 8400 "Expected exit qualification %lx (actual %lx)", 8401 expected_exit_qual, exit_qual); 8402 report_xfail(xfail_dr6, expected_dr6 == dr6, 8403 "Expected DR6 %lx (actual %lx)", expected_dr6, dr6); 8404 dismiss_db(); 8405 } 8406 8407 /* 8408 * Assuming the guest has just exited on a VMCALL instruction, skip 8409 * over the vmcall, and set the guest's RFLAGS.TF in the VMCS. If 8410 * pending debug exceptions are non-zero, set the VMCS up as if the 8411 * previous instruction was a MOVSS that generated the indicated 8412 * pending debug exceptions. Then enter L2. 8413 */ 8414 static void single_step_guest(const char *test_name, u64 starting_dr6, 8415 u64 pending_debug_exceptions) 8416 { 8417 printf("\n%s\n", test_name); 8418 skip_exit_vmcall(); 8419 write_dr6(starting_dr6); 8420 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_TF); 8421 if (pending_debug_exceptions) { 8422 vmcs_write(GUEST_PENDING_DEBUG, pending_debug_exceptions); 8423 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 8424 } 8425 enter_guest(); 8426 } 8427 8428 /* 8429 * When L1 intercepts #DB, verify that a single-step trap clears 8430 * pending debug exceptions, populates the exit qualification field 8431 * properly, and that DR6 is not prematurely clobbered. In a 8432 * (simulated) MOVSS shadow, make sure that the pending debug 8433 * exception bits are properly accumulated into the exit qualification 8434 * field. 8435 */ 8436 static void vmx_db_test(void) 8437 { 8438 /* 8439 * We are going to set a few arbitrary bits in DR6 to verify that 8440 * (a) DR6 is not modified by an intercepted #DB, and 8441 * (b) stale bits in DR6 (DR6.BD, in particular) don't leak into 8442 * the exit qualification field for a subsequent #DB exception. 8443 */ 8444 const u64 starting_dr6 = DR6_RESERVED | BIT(13) | DR_TRAP3 | DR_TRAP1; 8445 extern char post_nop asm(".Lpost_nop"); 8446 extern char post_movss_nop asm(".Lpost_movss_nop"); 8447 extern char post_wbinvd asm(".Lpost_wbinvd"); 8448 extern char post_movss_wbinvd asm(".Lpost_movss_wbinvd"); 8449 extern char xbegin asm(".Lxbegin"); 8450 extern char skip_rtm asm(".Lskip_rtm"); 8451 8452 /* 8453 * L1 wants to intercept #DB exceptions encountered in L2. 8454 */ 8455 vmcs_write(EXC_BITMAP, BIT(DB_VECTOR)); 8456 8457 /* 8458 * Start L2 and run it up to the first point of interest. 8459 */ 8460 test_set_guest(vmx_db_test_guest); 8461 enter_guest(); 8462 8463 /* 8464 * Hardware-delivered #DB trap for single-step sets the 8465 * standard that L0 has to follow for emulated instructions. 8466 */ 8467 single_step_guest("Hardware delivered single-step", starting_dr6, 0); 8468 check_db_exit(false, false, false, &post_nop, DR_STEP, starting_dr6); 8469 8470 /* 8471 * Hardware-delivered #DB trap for single-step in MOVSS shadow 8472 * also sets the standard that L0 has to follow for emulated 8473 * instructions. Here, we establish the VMCS pending debug 8474 * exceptions to indicate that the simulated MOVSS triggered a 8475 * data breakpoint as well as the single-step trap. 8476 */ 8477 single_step_guest("Hardware delivered single-step in MOVSS shadow", 8478 starting_dr6, BIT(12) | DR_STEP | DR_TRAP0 ); 8479 check_db_exit(false, false, false, &post_movss_nop, DR_STEP | DR_TRAP0, 8480 starting_dr6); 8481 8482 /* 8483 * L0 synthesized #DB trap for single-step is buggy, because 8484 * kvm (a) clobbers DR6 too early, and (b) tries its best to 8485 * reconstitute the exit qualification from the prematurely 8486 * modified DR6, but fails miserably. 8487 */ 8488 single_step_guest("Software synthesized single-step", starting_dr6, 0); 8489 check_db_exit(false, false, false, &post_wbinvd, DR_STEP, starting_dr6); 8490 8491 /* 8492 * L0 synthesized #DB trap for single-step in MOVSS shadow is 8493 * even worse, because L0 also leaves the pending debug 8494 * exceptions in the VMCS instead of accumulating them into 8495 * the exit qualification field for the #DB exception. 8496 */ 8497 single_step_guest("Software synthesized single-step in MOVSS shadow", 8498 starting_dr6, BIT(12) | DR_STEP | DR_TRAP0); 8499 check_db_exit(true, false, true, &post_movss_wbinvd, DR_STEP | DR_TRAP0, 8500 starting_dr6); 8501 8502 /* 8503 * Optional RTM test for hardware that supports RTM, to 8504 * demonstrate that the current volume 3 of the SDM 8505 * (325384-067US), table 27-1 is incorrect. Bit 16 of the exit 8506 * qualification for debug exceptions is not reserved. It is 8507 * set to 1 if a debug exception (#DB) or a breakpoint 8508 * exception (#BP) occurs inside an RTM region while advanced 8509 * debugging of RTM transactional regions is enabled. 8510 */ 8511 if (this_cpu_has(X86_FEATURE_RTM)) { 8512 vmcs_write(ENT_CONTROLS, 8513 vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 8514 /* 8515 * Set DR7.RTM[bit 11] and IA32_DEBUGCTL.RTM[bit 15] 8516 * in the guest to enable advanced debugging of RTM 8517 * transactional regions. 8518 */ 8519 vmcs_write(GUEST_DR7, BIT(11)); 8520 vmcs_write(GUEST_DEBUGCTL, BIT(15)); 8521 single_step_guest("Hardware delivered single-step in " 8522 "transactional region", starting_dr6, 0); 8523 check_db_exit(false, false, false, &xbegin, BIT(16), 8524 starting_dr6); 8525 } else { 8526 vmcs_write(GUEST_RIP, (u64)&skip_rtm); 8527 enter_guest(); 8528 } 8529 } 8530 8531 static void enable_vid(void) 8532 { 8533 void *virtual_apic_page; 8534 8535 assert(cpu_has_apicv()); 8536 8537 disable_intercept_for_x2apic_msrs(); 8538 8539 virtual_apic_page = alloc_page(); 8540 vmcs_write(APIC_VIRT_ADDR, (u64)virtual_apic_page); 8541 8542 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 8543 8544 vmcs_write(EOI_EXIT_BITMAP0, 0x0); 8545 vmcs_write(EOI_EXIT_BITMAP1, 0x0); 8546 vmcs_write(EOI_EXIT_BITMAP2, 0x0); 8547 vmcs_write(EOI_EXIT_BITMAP3, 0x0); 8548 8549 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY | CPU_TPR_SHADOW); 8550 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_VINTD | CPU_VIRT_X2APIC); 8551 } 8552 8553 static void trigger_ioapic_scan_thread(void *data) 8554 { 8555 /* Wait until other CPU entered L2 */ 8556 while (vmx_get_test_stage() != 1) 8557 ; 8558 8559 /* Trigger ioapic scan */ 8560 ioapic_set_redir(0xf, 0x79, TRIGGER_LEVEL); 8561 vmx_set_test_stage(2); 8562 } 8563 8564 static void irq_79_handler_guest(isr_regs_t *regs) 8565 { 8566 eoi(); 8567 8568 /* L1 expects vmexit on VMX_VMCALL and not VMX_EOI_INDUCED */ 8569 vmcall(); 8570 } 8571 8572 /* 8573 * Constant for num of busy-loop iterations after which 8574 * a timer interrupt should have happened in host 8575 */ 8576 #define TIMER_INTERRUPT_DELAY 100000000 8577 8578 static void vmx_eoi_bitmap_ioapic_scan_test_guest(void) 8579 { 8580 handle_irq(0x79, irq_79_handler_guest); 8581 irq_enable(); 8582 8583 /* Signal to L1 CPU to trigger ioapic scan */ 8584 vmx_set_test_stage(1); 8585 /* Wait until L1 CPU to trigger ioapic scan */ 8586 while (vmx_get_test_stage() != 2) 8587 ; 8588 8589 /* 8590 * Wait for L0 timer interrupt to be raised while we run in L2 8591 * such that L0 will process the IOAPIC scan request before 8592 * resuming L2 8593 */ 8594 delay(TIMER_INTERRUPT_DELAY); 8595 8596 asm volatile ("int $0x79"); 8597 } 8598 8599 static void vmx_eoi_bitmap_ioapic_scan_test(void) 8600 { 8601 if (!cpu_has_apicv() || (cpu_count() < 2)) { 8602 report_skip(__func__); 8603 return; 8604 } 8605 8606 enable_vid(); 8607 8608 on_cpu_async(1, trigger_ioapic_scan_thread, NULL); 8609 test_set_guest(vmx_eoi_bitmap_ioapic_scan_test_guest); 8610 8611 /* 8612 * Launch L2. 8613 * We expect the exit reason to be VMX_VMCALL (and not EOI INDUCED). 8614 * In case the reason isn't VMX_VMCALL, the asserion inside 8615 * skip_exit_vmcall() will fail. 8616 */ 8617 enter_guest(); 8618 skip_exit_vmcall(); 8619 8620 /* Let L2 finish */ 8621 enter_guest(); 8622 report(1, __func__); 8623 } 8624 8625 #define HLT_WITH_RVI_VECTOR (0xf1) 8626 8627 bool vmx_hlt_with_rvi_guest_isr_fired; 8628 static void vmx_hlt_with_rvi_guest_isr(isr_regs_t *regs) 8629 { 8630 vmx_hlt_with_rvi_guest_isr_fired = true; 8631 eoi(); 8632 } 8633 8634 static void vmx_hlt_with_rvi_guest(void) 8635 { 8636 handle_irq(HLT_WITH_RVI_VECTOR, vmx_hlt_with_rvi_guest_isr); 8637 8638 irq_enable(); 8639 asm volatile ("nop"); 8640 8641 vmcall(); 8642 } 8643 8644 static void vmx_hlt_with_rvi_test(void) 8645 { 8646 if (!cpu_has_apicv()) { 8647 report_skip(__func__); 8648 return; 8649 } 8650 8651 enable_vid(); 8652 8653 vmx_hlt_with_rvi_guest_isr_fired = false; 8654 test_set_guest(vmx_hlt_with_rvi_guest); 8655 8656 enter_guest(); 8657 skip_exit_vmcall(); 8658 8659 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8660 vmcs_write(GUEST_INT_STATUS, HLT_WITH_RVI_VECTOR); 8661 enter_guest(); 8662 8663 report(vmx_hlt_with_rvi_guest_isr_fired, "Interrupt raised in guest"); 8664 } 8665 8666 static void set_irq_line_thread(void *data) 8667 { 8668 /* Wait until other CPU entered L2 */ 8669 while (vmx_get_test_stage() != 1) 8670 ; 8671 8672 /* Set irq-line 0xf to raise vector 0x78 for vCPU 0 */ 8673 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 8674 vmx_set_test_stage(2); 8675 } 8676 8677 static bool irq_78_handler_vmcall_before_eoi; 8678 static void irq_78_handler_guest(isr_regs_t *regs) 8679 { 8680 set_irq_line(0xf, 0); 8681 if (irq_78_handler_vmcall_before_eoi) 8682 vmcall(); 8683 eoi(); 8684 vmcall(); 8685 } 8686 8687 static void vmx_apic_passthrough_guest(void) 8688 { 8689 handle_irq(0x78, irq_78_handler_guest); 8690 irq_enable(); 8691 8692 /* If requested, wait for other CPU to trigger ioapic scan */ 8693 if (vmx_get_test_stage() < 1) { 8694 vmx_set_test_stage(1); 8695 while (vmx_get_test_stage() != 2) 8696 ; 8697 } 8698 8699 set_irq_line(0xf, 1); 8700 } 8701 8702 static void vmx_apic_passthrough(bool set_irq_line_from_thread) 8703 { 8704 if (set_irq_line_from_thread && (cpu_count() < 2)) { 8705 report_skip(__func__); 8706 return; 8707 } 8708 8709 /* Test device is required for generating IRQs */ 8710 if (!test_device_enabled()) { 8711 report_skip(__func__); 8712 return; 8713 } 8714 u64 cpu_ctrl_0 = CPU_SECONDARY; 8715 u64 cpu_ctrl_1 = 0; 8716 8717 disable_intercept_for_x2apic_msrs(); 8718 8719 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 8720 8721 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 8722 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 8723 8724 if (set_irq_line_from_thread) { 8725 irq_78_handler_vmcall_before_eoi = false; 8726 on_cpu_async(1, set_irq_line_thread, NULL); 8727 } else { 8728 irq_78_handler_vmcall_before_eoi = true; 8729 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 8730 vmx_set_test_stage(2); 8731 } 8732 test_set_guest(vmx_apic_passthrough_guest); 8733 8734 if (irq_78_handler_vmcall_before_eoi) { 8735 /* Before EOI remote_irr should still be set */ 8736 enter_guest(); 8737 skip_exit_vmcall(); 8738 TEST_ASSERT_EQ_MSG(1, (int)ioapic_read_redir(0xf).remote_irr, 8739 "IOAPIC pass-through: remote_irr=1 before EOI"); 8740 } 8741 8742 /* After EOI remote_irr should be cleared */ 8743 enter_guest(); 8744 skip_exit_vmcall(); 8745 TEST_ASSERT_EQ_MSG(0, (int)ioapic_read_redir(0xf).remote_irr, 8746 "IOAPIC pass-through: remote_irr=0 after EOI"); 8747 8748 /* Let L2 finish */ 8749 enter_guest(); 8750 report(1, __func__); 8751 } 8752 8753 static void vmx_apic_passthrough_test(void) 8754 { 8755 vmx_apic_passthrough(false); 8756 } 8757 8758 static void vmx_apic_passthrough_thread_test(void) 8759 { 8760 vmx_apic_passthrough(true); 8761 } 8762 8763 static void vmx_apic_passthrough_tpr_threshold_guest(void) 8764 { 8765 cli(); 8766 apic_set_tpr(0); 8767 } 8768 8769 static bool vmx_apic_passthrough_tpr_threshold_ipi_isr_fired; 8770 static void vmx_apic_passthrough_tpr_threshold_ipi_isr(isr_regs_t *regs) 8771 { 8772 vmx_apic_passthrough_tpr_threshold_ipi_isr_fired = true; 8773 eoi(); 8774 } 8775 8776 static void vmx_apic_passthrough_tpr_threshold_test(void) 8777 { 8778 int ipi_vector = 0xe1; 8779 8780 disable_intercept_for_x2apic_msrs(); 8781 vmcs_clear_bits(PIN_CONTROLS, PIN_EXTINT); 8782 8783 /* Raise L0 TPR-threshold by queueing vector in LAPIC IRR */ 8784 cli(); 8785 apic_set_tpr((ipi_vector >> 4) + 1); 8786 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | 8787 APIC_DM_FIXED | ipi_vector, 8788 0); 8789 8790 test_set_guest(vmx_apic_passthrough_tpr_threshold_guest); 8791 enter_guest(); 8792 8793 report(apic_get_tpr() == 0, "TPR was zero by guest"); 8794 8795 /* Clean pending self-IPI */ 8796 vmx_apic_passthrough_tpr_threshold_ipi_isr_fired = false; 8797 handle_irq(ipi_vector, vmx_apic_passthrough_tpr_threshold_ipi_isr); 8798 sti(); 8799 asm volatile ("nop"); 8800 report(vmx_apic_passthrough_tpr_threshold_ipi_isr_fired, "self-IPI fired"); 8801 8802 report(1, __func__); 8803 } 8804 8805 static u64 init_signal_test_exit_reason; 8806 static bool init_signal_test_thread_continued; 8807 8808 static void init_signal_test_thread(void *data) 8809 { 8810 struct vmcs *test_vmcs = data; 8811 8812 /* Enter VMX operation (i.e. exec VMXON) */ 8813 u64 *ap_vmxon_region = alloc_page(); 8814 enable_vmx(); 8815 init_vmx(ap_vmxon_region); 8816 _vmx_on(ap_vmxon_region); 8817 8818 /* Signal CPU have entered VMX operation */ 8819 vmx_set_test_stage(1); 8820 8821 /* Wait for BSP CPU to send INIT signal */ 8822 while (vmx_get_test_stage() != 2) 8823 ; 8824 8825 /* 8826 * Signal that we continue as usual as INIT signal 8827 * should be blocked while CPU is in VMX operation 8828 */ 8829 vmx_set_test_stage(3); 8830 8831 /* Wait for signal to enter VMX non-root mode */ 8832 while (vmx_get_test_stage() != 4) 8833 ; 8834 8835 /* Enter VMX non-root mode */ 8836 test_set_guest(v2_null_test_guest); 8837 make_vmcs_current(test_vmcs); 8838 enter_guest(); 8839 /* Save exit reason for BSP CPU to compare to expected result */ 8840 init_signal_test_exit_reason = vmcs_read(EXI_REASON); 8841 /* VMCLEAR test-vmcs so it could be loaded by BSP CPU */ 8842 vmcs_clear(test_vmcs); 8843 launched = false; 8844 /* Signal that CPU exited to VMX root mode */ 8845 vmx_set_test_stage(5); 8846 8847 /* Wait for BSP CPU to signal to exit VMX operation */ 8848 while (vmx_get_test_stage() != 6) 8849 ; 8850 8851 /* Exit VMX operation (i.e. exec VMXOFF) */ 8852 vmx_off(); 8853 8854 /* 8855 * Signal to BSP CPU that we continue as usual as INIT signal 8856 * should have been consumed by VMX_INIT exit from guest 8857 */ 8858 vmx_set_test_stage(7); 8859 8860 /* Wait for BSP CPU to signal to enter VMX operation */ 8861 while (vmx_get_test_stage() != 8) 8862 ; 8863 /* Enter VMX operation (i.e. exec VMXON) */ 8864 _vmx_on(ap_vmxon_region); 8865 /* Signal to BSP we are in VMX operation */ 8866 vmx_set_test_stage(9); 8867 8868 /* Wait for BSP CPU to send INIT signal */ 8869 while (vmx_get_test_stage() != 10) 8870 ; 8871 8872 /* Exit VMX operation (i.e. exec VMXOFF) */ 8873 vmx_off(); 8874 8875 /* 8876 * Exiting VMX operation should result in latched 8877 * INIT signal being processed. Therefore, we should 8878 * never reach the below code. Thus, signal to BSP 8879 * CPU if we have reached here so it is able to 8880 * report an issue if it happens. 8881 */ 8882 init_signal_test_thread_continued = true; 8883 } 8884 8885 #define INIT_SIGNAL_TEST_DELAY 100000000ULL 8886 8887 static void vmx_init_signal_test(void) 8888 { 8889 struct vmcs *test_vmcs; 8890 8891 if (cpu_count() < 2) { 8892 report_skip(__func__); 8893 return; 8894 } 8895 8896 /* VMCLEAR test-vmcs so it could be loaded by other CPU */ 8897 vmcs_save(&test_vmcs); 8898 vmcs_clear(test_vmcs); 8899 8900 vmx_set_test_stage(0); 8901 on_cpu_async(1, init_signal_test_thread, test_vmcs); 8902 8903 /* Wait for other CPU to enter VMX operation */ 8904 while (vmx_get_test_stage() != 1) 8905 ; 8906 8907 /* Send INIT signal to other CPU */ 8908 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_INIT | APIC_INT_ASSERT, 8909 id_map[1]); 8910 /* Signal other CPU we have sent INIT signal */ 8911 vmx_set_test_stage(2); 8912 8913 /* 8914 * Wait reasonable amount of time for INIT signal to 8915 * be received on other CPU and verify that other CPU 8916 * have proceed as usual to next test stage as INIT 8917 * signal should be blocked while other CPU in 8918 * VMX operation 8919 */ 8920 delay(INIT_SIGNAL_TEST_DELAY); 8921 report(vmx_get_test_stage() == 3, 8922 "INIT signal blocked when CPU in VMX operation"); 8923 /* No point to continue if we failed at this point */ 8924 if (vmx_get_test_stage() != 3) 8925 return; 8926 8927 /* Signal other CPU to enter VMX non-root mode */ 8928 init_signal_test_exit_reason = -1ull; 8929 vmx_set_test_stage(4); 8930 /* 8931 * Wait reasonable amont of time for other CPU 8932 * to exit to VMX root mode 8933 */ 8934 delay(INIT_SIGNAL_TEST_DELAY); 8935 if (vmx_get_test_stage() != 5) { 8936 report(false, "Pending INIT signal didn't result in VMX exit"); 8937 return; 8938 } 8939 report(init_signal_test_exit_reason == VMX_INIT, 8940 "INIT signal during VMX non-root mode result in exit-reason %s (%lu)", 8941 exit_reason_description(init_signal_test_exit_reason), 8942 init_signal_test_exit_reason); 8943 8944 /* Run guest to completion */ 8945 make_vmcs_current(test_vmcs); 8946 enter_guest(); 8947 8948 /* Signal other CPU to exit VMX operation */ 8949 init_signal_test_thread_continued = false; 8950 vmx_set_test_stage(6); 8951 8952 /* Wait reasonable amount of time for other CPU to exit VMX operation */ 8953 delay(INIT_SIGNAL_TEST_DELAY); 8954 report(vmx_get_test_stage() == 7, 8955 "INIT signal consumed on VMX_INIT exit"); 8956 /* No point to continue if we failed at this point */ 8957 if (vmx_get_test_stage() != 7) 8958 return; 8959 8960 /* Signal other CPU to enter VMX operation */ 8961 vmx_set_test_stage(8); 8962 /* Wait for other CPU to enter VMX operation */ 8963 while (vmx_get_test_stage() != 9) 8964 ; 8965 8966 /* Send INIT signal to other CPU */ 8967 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_INIT | APIC_INT_ASSERT, 8968 id_map[1]); 8969 /* Signal other CPU we have sent INIT signal */ 8970 vmx_set_test_stage(10); 8971 8972 /* 8973 * Wait reasonable amount of time for other CPU 8974 * to exit VMX operation and process INIT signal 8975 */ 8976 delay(INIT_SIGNAL_TEST_DELAY); 8977 report(!init_signal_test_thread_continued, 8978 "INIT signal processed after exit VMX operation"); 8979 8980 /* 8981 * TODO: Send SIPI to other CPU to sipi_entry (See x86/cstart64.S) 8982 * to re-init it to kvm-unit-tests standard environment. 8983 * Somehow (?) verify that SIPI was indeed received. 8984 */ 8985 } 8986 8987 enum vmcs_access { 8988 ACCESS_VMREAD, 8989 ACCESS_VMWRITE, 8990 ACCESS_NONE, 8991 }; 8992 8993 struct vmcs_shadow_test_common { 8994 enum vmcs_access op; 8995 enum Reason reason; 8996 u64 field; 8997 u64 value; 8998 u64 flags; 8999 u64 time; 9000 } l1_l2_common; 9001 9002 static inline u64 vmread_flags(u64 field, u64 *val) 9003 { 9004 u64 flags; 9005 9006 asm volatile ("vmread %2, %1; pushf; pop %0" 9007 : "=r" (flags), "=rm" (*val) : "r" (field) : "cc"); 9008 return flags & X86_EFLAGS_ALU; 9009 } 9010 9011 static inline u64 vmwrite_flags(u64 field, u64 val) 9012 { 9013 u64 flags; 9014 9015 asm volatile ("vmwrite %1, %2; pushf; pop %0" 9016 : "=r"(flags) : "rm" (val), "r" (field) : "cc"); 9017 return flags & X86_EFLAGS_ALU; 9018 } 9019 9020 static void vmx_vmcs_shadow_test_guest(void) 9021 { 9022 struct vmcs_shadow_test_common *c = &l1_l2_common; 9023 u64 start; 9024 9025 while (c->op != ACCESS_NONE) { 9026 start = rdtsc(); 9027 switch (c->op) { 9028 default: 9029 c->flags = -1ull; 9030 break; 9031 case ACCESS_VMREAD: 9032 c->flags = vmread_flags(c->field, &c->value); 9033 break; 9034 case ACCESS_VMWRITE: 9035 c->flags = vmwrite_flags(c->field, 0); 9036 break; 9037 } 9038 c->time = rdtsc() - start; 9039 vmcall(); 9040 } 9041 } 9042 9043 static u64 vmread_from_shadow(u64 field) 9044 { 9045 struct vmcs *primary; 9046 struct vmcs *shadow; 9047 u64 value; 9048 9049 TEST_ASSERT(!vmcs_save(&primary)); 9050 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 9051 TEST_ASSERT(!make_vmcs_current(shadow)); 9052 value = vmcs_read(field); 9053 TEST_ASSERT(!make_vmcs_current(primary)); 9054 return value; 9055 } 9056 9057 static u64 vmwrite_to_shadow(u64 field, u64 value) 9058 { 9059 struct vmcs *primary; 9060 struct vmcs *shadow; 9061 9062 TEST_ASSERT(!vmcs_save(&primary)); 9063 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 9064 TEST_ASSERT(!make_vmcs_current(shadow)); 9065 vmcs_write(field, value); 9066 value = vmcs_read(field); 9067 TEST_ASSERT(!make_vmcs_current(primary)); 9068 return value; 9069 } 9070 9071 static void vmcs_shadow_test_access(u8 *bitmap[2], enum vmcs_access access) 9072 { 9073 struct vmcs_shadow_test_common *c = &l1_l2_common; 9074 9075 c->op = access; 9076 vmcs_write(VMX_INST_ERROR, 0); 9077 enter_guest(); 9078 c->reason = vmcs_read(EXI_REASON) & 0xffff; 9079 if (c->reason != VMX_VMCALL) { 9080 skip_exit_insn(); 9081 enter_guest(); 9082 } 9083 skip_exit_vmcall(); 9084 } 9085 9086 static void vmcs_shadow_test_field(u8 *bitmap[2], u64 field) 9087 { 9088 struct vmcs_shadow_test_common *c = &l1_l2_common; 9089 struct vmcs *shadow; 9090 u64 value; 9091 uintptr_t flags[2]; 9092 bool good_shadow; 9093 u32 vmx_inst_error; 9094 9095 report_prefix_pushf("field %lx", field); 9096 c->field = field; 9097 9098 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 9099 if (shadow != (struct vmcs *)-1ull) { 9100 flags[ACCESS_VMREAD] = vmread_flags(field, &value); 9101 flags[ACCESS_VMWRITE] = vmwrite_flags(field, value); 9102 good_shadow = !flags[ACCESS_VMREAD] && !flags[ACCESS_VMWRITE]; 9103 } else { 9104 /* 9105 * When VMCS link pointer is -1ull, VMWRITE/VMREAD on 9106 * shadowed-fields should fail with setting RFLAGS.CF. 9107 */ 9108 flags[ACCESS_VMREAD] = X86_EFLAGS_CF; 9109 flags[ACCESS_VMWRITE] = X86_EFLAGS_CF; 9110 good_shadow = false; 9111 } 9112 9113 /* Intercept both VMREAD and VMWRITE. */ 9114 report_prefix_push("no VMREAD/VMWRITE permission"); 9115 /* VMWRITE/VMREAD done on reserved-bit should always intercept */ 9116 if (!(field >> VMCS_FIELD_RESERVED_SHIFT)) { 9117 set_bit(field, bitmap[ACCESS_VMREAD]); 9118 set_bit(field, bitmap[ACCESS_VMWRITE]); 9119 } 9120 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 9121 report(c->reason == VMX_VMWRITE, "not shadowed for VMWRITE"); 9122 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 9123 report(c->reason == VMX_VMREAD, "not shadowed for VMREAD"); 9124 report_prefix_pop(); 9125 9126 if (field >> VMCS_FIELD_RESERVED_SHIFT) 9127 goto out; 9128 9129 /* Permit shadowed VMREAD. */ 9130 report_prefix_push("VMREAD permission only"); 9131 clear_bit(field, bitmap[ACCESS_VMREAD]); 9132 set_bit(field, bitmap[ACCESS_VMWRITE]); 9133 if (good_shadow) 9134 value = vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 9135 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 9136 report(c->reason == VMX_VMWRITE, "not shadowed for VMWRITE"); 9137 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 9138 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 9139 report(c->reason == VMX_VMCALL, "shadowed for VMREAD (in %ld cycles)", 9140 c->time); 9141 report(c->flags == flags[ACCESS_VMREAD], 9142 "ALU flags after VMREAD (%lx) are as expected (%lx)", 9143 c->flags, flags[ACCESS_VMREAD]); 9144 if (good_shadow) 9145 report(c->value == value, 9146 "value read from shadow (%lx) is as expected (%lx)", 9147 c->value, value); 9148 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 9149 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 9150 "VMX_INST_ERROR (%d) is as expected (%d)", 9151 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 9152 report_prefix_pop(); 9153 9154 /* Permit shadowed VMWRITE. */ 9155 report_prefix_push("VMWRITE permission only"); 9156 set_bit(field, bitmap[ACCESS_VMREAD]); 9157 clear_bit(field, bitmap[ACCESS_VMWRITE]); 9158 if (good_shadow) 9159 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 9160 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 9161 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 9162 report(c->reason == VMX_VMCALL, 9163 "shadowed for VMWRITE (in %ld cycles)", 9164 c->time); 9165 report(c->flags == flags[ACCESS_VMREAD], 9166 "ALU flags after VMWRITE (%lx) are as expected (%lx)", 9167 c->flags, flags[ACCESS_VMREAD]); 9168 if (good_shadow) { 9169 value = vmread_from_shadow(field); 9170 report(value == 0, 9171 "shadow VMCS value (%lx) is as expected (%lx)", value, 9172 0ul); 9173 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 9174 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 9175 "VMX_INST_ERROR (%d) is as expected (%d)", 9176 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 9177 } 9178 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 9179 report(c->reason == VMX_VMREAD, "not shadowed for VMREAD"); 9180 report_prefix_pop(); 9181 9182 /* Permit shadowed VMREAD and VMWRITE. */ 9183 report_prefix_push("VMREAD and VMWRITE permission"); 9184 clear_bit(field, bitmap[ACCESS_VMREAD]); 9185 clear_bit(field, bitmap[ACCESS_VMWRITE]); 9186 if (good_shadow) 9187 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 9188 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 9189 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 9190 report(c->reason == VMX_VMCALL, 9191 "shadowed for VMWRITE (in %ld cycles)", 9192 c->time); 9193 report(c->flags == flags[ACCESS_VMREAD], 9194 "ALU flags after VMWRITE (%lx) are as expected (%lx)", 9195 c->flags, flags[ACCESS_VMREAD]); 9196 if (good_shadow) { 9197 value = vmread_from_shadow(field); 9198 report(value == 0, 9199 "shadow VMCS value (%lx) is as expected (%lx)", value, 9200 0ul); 9201 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 9202 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 9203 "VMX_INST_ERROR (%d) is as expected (%d)", 9204 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 9205 } 9206 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 9207 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 9208 report(c->reason == VMX_VMCALL, "shadowed for VMREAD (in %ld cycles)", 9209 c->time); 9210 report(c->flags == flags[ACCESS_VMREAD], 9211 "ALU flags after VMREAD (%lx) are as expected (%lx)", 9212 c->flags, flags[ACCESS_VMREAD]); 9213 if (good_shadow) 9214 report(c->value == 0, 9215 "value read from shadow (%lx) is as expected (%lx)", 9216 c->value, 0ul); 9217 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 9218 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 9219 "VMX_INST_ERROR (%d) is as expected (%d)", 9220 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 9221 report_prefix_pop(); 9222 9223 out: 9224 report_prefix_pop(); 9225 } 9226 9227 static void vmx_vmcs_shadow_test_body(u8 *bitmap[2]) 9228 { 9229 unsigned base; 9230 unsigned index; 9231 unsigned bit; 9232 unsigned highest_index = rdmsr(MSR_IA32_VMX_VMCS_ENUM); 9233 9234 /* Run test on all possible valid VMCS fields */ 9235 for (base = 0; 9236 base < (1 << VMCS_FIELD_RESERVED_SHIFT); 9237 base += (1 << VMCS_FIELD_TYPE_SHIFT)) 9238 for (index = 0; index <= highest_index; index++) 9239 vmcs_shadow_test_field(bitmap, base + index); 9240 9241 /* 9242 * Run tests on some invalid VMCS fields 9243 * (Have reserved bit set). 9244 */ 9245 for (bit = VMCS_FIELD_RESERVED_SHIFT; bit < VMCS_FIELD_BIT_SIZE; bit++) 9246 vmcs_shadow_test_field(bitmap, (1ull << bit)); 9247 } 9248 9249 static void vmx_vmcs_shadow_test(void) 9250 { 9251 u8 *bitmap[2]; 9252 struct vmcs *shadow; 9253 9254 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 9255 printf("\t'Activate secondary controls' not supported.\n"); 9256 return; 9257 } 9258 9259 if (!(ctrl_cpu_rev[1].clr & CPU_SHADOW_VMCS)) { 9260 printf("\t'VMCS shadowing' not supported.\n"); 9261 return; 9262 } 9263 9264 if (!(rdmsr(MSR_IA32_VMX_MISC) & 9265 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS)) { 9266 printf("\tVMWRITE can't modify VM-exit information fields.\n"); 9267 return; 9268 } 9269 9270 test_set_guest(vmx_vmcs_shadow_test_guest); 9271 9272 bitmap[ACCESS_VMREAD] = alloc_page(); 9273 bitmap[ACCESS_VMWRITE] = alloc_page(); 9274 9275 vmcs_write(VMREAD_BITMAP, virt_to_phys(bitmap[ACCESS_VMREAD])); 9276 vmcs_write(VMWRITE_BITMAP, virt_to_phys(bitmap[ACCESS_VMWRITE])); 9277 9278 shadow = alloc_page(); 9279 shadow->hdr.revision_id = basic.revision; 9280 shadow->hdr.shadow_vmcs = 1; 9281 TEST_ASSERT(!vmcs_clear(shadow)); 9282 9283 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_RDTSC); 9284 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY); 9285 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_SHADOW_VMCS); 9286 9287 vmcs_write(VMCS_LINK_PTR, virt_to_phys(shadow)); 9288 report_prefix_push("valid link pointer"); 9289 vmx_vmcs_shadow_test_body(bitmap); 9290 report_prefix_pop(); 9291 9292 vmcs_write(VMCS_LINK_PTR, -1ull); 9293 report_prefix_push("invalid link pointer"); 9294 vmx_vmcs_shadow_test_body(bitmap); 9295 report_prefix_pop(); 9296 9297 l1_l2_common.op = ACCESS_NONE; 9298 enter_guest(); 9299 } 9300 9301 /* 9302 * This test monitors the difference between a guest RDTSC instruction 9303 * and the IA32_TIME_STAMP_COUNTER MSR value stored in the VMCS12 9304 * VM-exit MSR-store list when taking a VM-exit on the instruction 9305 * following RDTSC. 9306 */ 9307 #define RDTSC_DIFF_ITERS 100000 9308 #define RDTSC_DIFF_FAILS 100 9309 #define HOST_CAPTURED_GUEST_TSC_DIFF_THRESHOLD 750 9310 9311 /* 9312 * Set 'use TSC offsetting' and set the guest offset to the 9313 * inverse of the host's current TSC value, so that the guest starts running 9314 * with an effective TSC value of 0. 9315 */ 9316 static void reset_guest_tsc_to_zero(void) 9317 { 9318 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_USE_TSC_OFFSET); 9319 vmcs_write(TSC_OFFSET, -rdtsc()); 9320 } 9321 9322 static void rdtsc_vmexit_diff_test_guest(void) 9323 { 9324 int i; 9325 9326 for (i = 0; i < RDTSC_DIFF_ITERS; i++) 9327 /* Ensure rdtsc is the last instruction before the vmcall. */ 9328 asm volatile("rdtsc; vmcall" : : : "eax", "edx"); 9329 } 9330 9331 /* 9332 * This function only considers the "use TSC offsetting" VM-execution 9333 * control. It does not handle "use TSC scaling" (because the latter 9334 * isn't available to the host today.) 9335 */ 9336 static unsigned long long host_time_to_guest_time(unsigned long long t) 9337 { 9338 TEST_ASSERT(!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 9339 !(vmcs_read(CPU_EXEC_CTRL1) & CPU_USE_TSC_SCALING)); 9340 9341 if (vmcs_read(CPU_EXEC_CTRL0) & CPU_USE_TSC_OFFSET) 9342 t += vmcs_read(TSC_OFFSET); 9343 9344 return t; 9345 } 9346 9347 static unsigned long long rdtsc_vmexit_diff_test_iteration(void) 9348 { 9349 unsigned long long guest_tsc, host_to_guest_tsc; 9350 9351 enter_guest(); 9352 skip_exit_vmcall(); 9353 guest_tsc = (u32) regs.rax + (regs.rdx << 32); 9354 host_to_guest_tsc = host_time_to_guest_time(exit_msr_store[0].value); 9355 9356 return host_to_guest_tsc - guest_tsc; 9357 } 9358 9359 static void rdtsc_vmexit_diff_test(void) 9360 { 9361 int fail = 0; 9362 int i; 9363 9364 if (!(ctrl_cpu_rev[0].clr & CPU_USE_TSC_OFFSET)) 9365 test_skip("CPU doesn't support the 'use TSC offsetting' processor-based VM-execution control.\n"); 9366 9367 test_set_guest(rdtsc_vmexit_diff_test_guest); 9368 9369 reset_guest_tsc_to_zero(); 9370 9371 /* 9372 * Set up the VMCS12 VM-exit MSR-store list to store just one 9373 * MSR: IA32_TIME_STAMP_COUNTER. Note that the value stored is 9374 * in the host time domain (i.e., it is not adjusted according 9375 * to the TSC multiplier and TSC offset fields in the VMCS12, 9376 * as a guest RDTSC would be.) 9377 */ 9378 exit_msr_store = alloc_page(); 9379 exit_msr_store[0].index = MSR_IA32_TSC; 9380 vmcs_write(EXI_MSR_ST_CNT, 1); 9381 vmcs_write(EXIT_MSR_ST_ADDR, virt_to_phys(exit_msr_store)); 9382 9383 for (i = 0; i < RDTSC_DIFF_ITERS; i++) { 9384 if (rdtsc_vmexit_diff_test_iteration() >= 9385 HOST_CAPTURED_GUEST_TSC_DIFF_THRESHOLD) 9386 fail++; 9387 } 9388 9389 enter_guest(); 9390 9391 report(fail < RDTSC_DIFF_FAILS, 9392 "RDTSC to VM-exit delta too high in %d of %d iterations", 9393 fail, RDTSC_DIFF_ITERS); 9394 } 9395 9396 static int invalid_msr_init(struct vmcs *vmcs) 9397 { 9398 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 9399 printf("\tPreemption timer is not supported\n"); 9400 return VMX_TEST_EXIT; 9401 } 9402 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 9403 preempt_val = 10000000; 9404 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 9405 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 9406 9407 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 9408 printf("\tSave preemption value is not supported\n"); 9409 9410 vmcs_write(ENT_MSR_LD_CNT, 1); 9411 vmcs_write(ENTER_MSR_LD_ADDR, (u64)0x13370000); 9412 9413 return VMX_TEST_START; 9414 } 9415 9416 9417 static void invalid_msr_main(void) 9418 { 9419 report(0, "Invalid MSR load"); 9420 } 9421 9422 static int invalid_msr_exit_handler(void) 9423 { 9424 report(0, "Invalid MSR load"); 9425 print_vmexit_info(); 9426 return VMX_TEST_EXIT; 9427 } 9428 9429 static int invalid_msr_entry_failure(struct vmentry_result *result) 9430 { 9431 report(result->exit_reason.failed_vmentry && 9432 result->exit_reason.basic == VMX_FAIL_MSR, "Invalid MSR load"); 9433 return VMX_TEST_VMEXIT; 9434 } 9435 9436 /* 9437 * The max number of MSRs in an atomic switch MSR list is: 9438 * (111B + 1) * 512 = 4096 9439 * 9440 * Each list entry consumes: 9441 * 4-byte MSR index + 4 bytes reserved + 8-byte data = 16 bytes 9442 * 9443 * Allocate 128 kB to cover max_msr_list_size (i.e., 64 kB) and then some. 9444 */ 9445 static const u32 msr_list_page_order = 5; 9446 9447 static void atomic_switch_msr_limit_test_guest(void) 9448 { 9449 vmcall(); 9450 } 9451 9452 static void populate_msr_list(struct vmx_msr_entry *msr_list, 9453 size_t byte_capacity, int count) 9454 { 9455 int i; 9456 9457 for (i = 0; i < count; i++) { 9458 msr_list[i].index = MSR_IA32_TSC; 9459 msr_list[i].reserved = 0; 9460 msr_list[i].value = 0x1234567890abcdef; 9461 } 9462 9463 memset(msr_list + count, 0xff, 9464 byte_capacity - count * sizeof(*msr_list)); 9465 } 9466 9467 static int max_msr_list_size(void) 9468 { 9469 u32 vmx_misc = rdmsr(MSR_IA32_VMX_MISC); 9470 u32 factor = ((vmx_misc & GENMASK(27, 25)) >> 25) + 1; 9471 9472 return factor * 512; 9473 } 9474 9475 static void atomic_switch_msrs_test(int count) 9476 { 9477 struct vmx_msr_entry *vm_enter_load; 9478 struct vmx_msr_entry *vm_exit_load; 9479 struct vmx_msr_entry *vm_exit_store; 9480 int max_allowed = max_msr_list_size(); 9481 int byte_capacity = 1ul << (msr_list_page_order + PAGE_SHIFT); 9482 /* Exceeding the max MSR list size at exit trigers KVM to abort. */ 9483 int exit_count = count > max_allowed ? max_allowed : count; 9484 int cleanup_count = count > max_allowed ? 2 : 1; 9485 int i; 9486 9487 /* 9488 * Check for the IA32_TSC MSR, 9489 * available with the "TSC flag" and used to populate the MSR lists. 9490 */ 9491 if (!(cpuid(1).d & (1 << 4))) { 9492 report_skip(__func__); 9493 return; 9494 } 9495 9496 /* Set L2 guest. */ 9497 test_set_guest(atomic_switch_msr_limit_test_guest); 9498 9499 /* Setup atomic MSR switch lists. */ 9500 vm_enter_load = alloc_pages(msr_list_page_order); 9501 vm_exit_load = alloc_pages(msr_list_page_order); 9502 vm_exit_store = alloc_pages(msr_list_page_order); 9503 9504 vmcs_write(ENTER_MSR_LD_ADDR, (u64)vm_enter_load); 9505 vmcs_write(EXIT_MSR_LD_ADDR, (u64)vm_exit_load); 9506 vmcs_write(EXIT_MSR_ST_ADDR, (u64)vm_exit_store); 9507 9508 /* 9509 * VM-Enter should succeed up to the max number of MSRs per list, and 9510 * should not consume junk beyond the last entry. 9511 */ 9512 populate_msr_list(vm_enter_load, byte_capacity, count); 9513 populate_msr_list(vm_exit_load, byte_capacity, exit_count); 9514 populate_msr_list(vm_exit_store, byte_capacity, exit_count); 9515 9516 vmcs_write(ENT_MSR_LD_CNT, count); 9517 vmcs_write(EXI_MSR_LD_CNT, exit_count); 9518 vmcs_write(EXI_MSR_ST_CNT, exit_count); 9519 9520 if (count <= max_allowed) { 9521 enter_guest(); 9522 assert_exit_reason(VMX_VMCALL); 9523 skip_exit_vmcall(); 9524 } else { 9525 u32 exit_reason; 9526 u32 exit_reason_want; 9527 u32 exit_qual; 9528 9529 enter_guest_with_invalid_guest_state(); 9530 9531 exit_reason = vmcs_read(EXI_REASON); 9532 exit_reason_want = VMX_FAIL_MSR | VMX_ENTRY_FAILURE; 9533 report(exit_reason == exit_reason_want, 9534 "exit_reason, %u, is %u.", exit_reason, 9535 exit_reason_want); 9536 9537 exit_qual = vmcs_read(EXI_QUALIFICATION); 9538 report(exit_qual == max_allowed + 1, "exit_qual, %u, is %u.", 9539 exit_qual, max_allowed + 1); 9540 } 9541 9542 /* Cleanup. */ 9543 vmcs_write(ENT_MSR_LD_CNT, 0); 9544 vmcs_write(EXI_MSR_LD_CNT, 0); 9545 vmcs_write(EXI_MSR_ST_CNT, 0); 9546 for (i = 0; i < cleanup_count; i++) { 9547 enter_guest(); 9548 skip_exit_vmcall(); 9549 } 9550 free_pages_by_order(vm_enter_load, msr_list_page_order); 9551 free_pages_by_order(vm_exit_load, msr_list_page_order); 9552 free_pages_by_order(vm_exit_store, msr_list_page_order); 9553 } 9554 9555 static void atomic_switch_max_msrs_test(void) 9556 { 9557 atomic_switch_msrs_test(max_msr_list_size()); 9558 } 9559 9560 static void atomic_switch_overflow_msrs_test(void) 9561 { 9562 atomic_switch_msrs_test(max_msr_list_size() + 1); 9563 } 9564 9565 #define TEST(name) { #name, .v2 = name } 9566 9567 /* name/init/guest_main/exit_handler/syscall_handler/guest_regs */ 9568 struct vmx_test vmx_tests[] = { 9569 { "null", NULL, basic_guest_main, basic_exit_handler, NULL, {0} }, 9570 { "vmenter", NULL, vmenter_main, vmenter_exit_handler, NULL, {0} }, 9571 { "preemption timer", preemption_timer_init, preemption_timer_main, 9572 preemption_timer_exit_handler, NULL, {0} }, 9573 { "control field PAT", test_ctrl_pat_init, test_ctrl_pat_main, 9574 test_ctrl_pat_exit_handler, NULL, {0} }, 9575 { "control field EFER", test_ctrl_efer_init, test_ctrl_efer_main, 9576 test_ctrl_efer_exit_handler, NULL, {0} }, 9577 { "CR shadowing", NULL, cr_shadowing_main, 9578 cr_shadowing_exit_handler, NULL, {0} }, 9579 { "I/O bitmap", iobmp_init, iobmp_main, iobmp_exit_handler, 9580 NULL, {0} }, 9581 { "instruction intercept", insn_intercept_init, insn_intercept_main, 9582 insn_intercept_exit_handler, NULL, {0} }, 9583 { "EPT A/D disabled", ept_init, ept_main, ept_exit_handler, NULL, {0} }, 9584 { "EPT A/D enabled", eptad_init, eptad_main, eptad_exit_handler, NULL, {0} }, 9585 { "PML", pml_init, pml_main, pml_exit_handler, NULL, {0} }, 9586 { "VPID", vpid_init, vpid_main, vpid_exit_handler, NULL, {0} }, 9587 { "interrupt", interrupt_init, interrupt_main, 9588 interrupt_exit_handler, NULL, {0} }, 9589 { "debug controls", dbgctls_init, dbgctls_main, dbgctls_exit_handler, 9590 NULL, {0} }, 9591 { "MSR switch", msr_switch_init, msr_switch_main, 9592 msr_switch_exit_handler, NULL, {0}, msr_switch_entry_failure }, 9593 { "vmmcall", vmmcall_init, vmmcall_main, vmmcall_exit_handler, NULL, {0} }, 9594 { "disable RDTSCP", disable_rdtscp_init, disable_rdtscp_main, 9595 disable_rdtscp_exit_handler, NULL, {0} }, 9596 { "int3", int3_init, int3_guest_main, int3_exit_handler, NULL, {0} }, 9597 { "into", into_init, into_guest_main, into_exit_handler, NULL, {0} }, 9598 { "exit_monitor_from_l2_test", NULL, exit_monitor_from_l2_main, 9599 exit_monitor_from_l2_handler, NULL, {0} }, 9600 { "invalid_msr", invalid_msr_init, invalid_msr_main, 9601 invalid_msr_exit_handler, NULL, {0}, invalid_msr_entry_failure}, 9602 /* Basic V2 tests. */ 9603 TEST(v2_null_test), 9604 TEST(v2_multiple_entries_test), 9605 TEST(fixture_test_case1), 9606 TEST(fixture_test_case2), 9607 /* Opcode tests. */ 9608 TEST(invvpid_test_v2), 9609 /* VM-entry tests */ 9610 TEST(vmx_controls_test), 9611 TEST(vmx_host_state_area_test), 9612 TEST(vmx_guest_state_area_test), 9613 TEST(vmentry_movss_shadow_test), 9614 /* APICv tests */ 9615 TEST(vmx_eoi_bitmap_ioapic_scan_test), 9616 TEST(vmx_hlt_with_rvi_test), 9617 TEST(apic_reg_virt_test), 9618 TEST(virt_x2apic_mode_test), 9619 /* APIC pass-through tests */ 9620 TEST(vmx_apic_passthrough_test), 9621 TEST(vmx_apic_passthrough_thread_test), 9622 TEST(vmx_apic_passthrough_tpr_threshold_test), 9623 TEST(vmx_init_signal_test), 9624 /* VMCS Shadowing tests */ 9625 TEST(vmx_vmcs_shadow_test), 9626 /* Regression tests */ 9627 TEST(vmx_cr_load_test), 9628 TEST(vmx_nm_test), 9629 TEST(vmx_db_test), 9630 TEST(vmx_nmi_window_test), 9631 TEST(vmx_intr_window_test), 9632 TEST(vmx_pending_event_test), 9633 TEST(vmx_pending_event_hlt_test), 9634 TEST(vmx_store_tsc_test), 9635 /* EPT access tests. */ 9636 TEST(ept_access_test_not_present), 9637 TEST(ept_access_test_read_only), 9638 TEST(ept_access_test_write_only), 9639 TEST(ept_access_test_read_write), 9640 TEST(ept_access_test_execute_only), 9641 TEST(ept_access_test_read_execute), 9642 TEST(ept_access_test_write_execute), 9643 TEST(ept_access_test_read_write_execute), 9644 TEST(ept_access_test_reserved_bits), 9645 TEST(ept_access_test_ignored_bits), 9646 TEST(ept_access_test_paddr_not_present_ad_disabled), 9647 TEST(ept_access_test_paddr_not_present_ad_enabled), 9648 TEST(ept_access_test_paddr_read_only_ad_disabled), 9649 TEST(ept_access_test_paddr_read_only_ad_enabled), 9650 TEST(ept_access_test_paddr_read_write), 9651 TEST(ept_access_test_paddr_read_write_execute), 9652 TEST(ept_access_test_paddr_read_execute_ad_disabled), 9653 TEST(ept_access_test_paddr_read_execute_ad_enabled), 9654 TEST(ept_access_test_paddr_not_present_page_fault), 9655 TEST(ept_access_test_force_2m_page), 9656 /* Atomic MSR switch tests. */ 9657 TEST(atomic_switch_max_msrs_test), 9658 TEST(atomic_switch_overflow_msrs_test), 9659 TEST(rdtsc_vmexit_diff_test), 9660 TEST(vmx_mtf_test), 9661 { NULL, NULL, NULL, NULL, NULL, {0} }, 9662 }; 9663