1 /* 2 * All test cases of nested virtualization should be in this file 3 * 4 * Author : Arthur Chunqi Li <yzt356@gmail.com> 5 */ 6 #include "vmx.h" 7 #include "msr.h" 8 #include "processor.h" 9 #include "vm.h" 10 #include "io.h" 11 #include "fwcfg.h" 12 #include "isr.h" 13 #include "apic.h" 14 #include "types.h" 15 16 u64 ia32_pat; 17 u64 ia32_efer; 18 void *io_bitmap_a, *io_bitmap_b; 19 u16 ioport; 20 21 unsigned long *pml4; 22 u64 eptp; 23 void *data_page1, *data_page2; 24 25 static inline void vmcall() 26 { 27 asm volatile("vmcall"); 28 } 29 30 void basic_guest_main() 31 { 32 } 33 34 int basic_exit_handler() 35 { 36 report("Basic VMX test", 0); 37 print_vmexit_info(); 38 return VMX_TEST_EXIT; 39 } 40 41 void vmenter_main() 42 { 43 u64 rax; 44 u64 rsp, resume_rsp; 45 46 report("test vmlaunch", 1); 47 48 asm volatile( 49 "mov %%rsp, %0\n\t" 50 "mov %3, %%rax\n\t" 51 "vmcall\n\t" 52 "mov %%rax, %1\n\t" 53 "mov %%rsp, %2\n\t" 54 : "=r"(rsp), "=r"(rax), "=r"(resume_rsp) 55 : "g"(0xABCD)); 56 report("test vmresume", (rax == 0xFFFF) && (rsp == resume_rsp)); 57 } 58 59 int vmenter_exit_handler() 60 { 61 u64 guest_rip; 62 ulong reason; 63 64 guest_rip = vmcs_read(GUEST_RIP); 65 reason = vmcs_read(EXI_REASON) & 0xff; 66 switch (reason) { 67 case VMX_VMCALL: 68 if (regs.rax != 0xABCD) { 69 report("test vmresume", 0); 70 return VMX_TEST_VMEXIT; 71 } 72 regs.rax = 0xFFFF; 73 vmcs_write(GUEST_RIP, guest_rip + 3); 74 return VMX_TEST_RESUME; 75 default: 76 report("test vmresume", 0); 77 print_vmexit_info(); 78 } 79 return VMX_TEST_VMEXIT; 80 } 81 82 u32 preempt_scale; 83 volatile unsigned long long tsc_val; 84 volatile u32 preempt_val; 85 u64 saved_rip; 86 87 int preemption_timer_init() 88 { 89 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 90 printf("\tPreemption timer is not supported\n"); 91 return VMX_TEST_EXIT; 92 } 93 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 94 preempt_val = 10000000; 95 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 96 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 97 98 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 99 printf("\tSave preemption value is not supported\n"); 100 101 return VMX_TEST_START; 102 } 103 104 void preemption_timer_main() 105 { 106 tsc_val = rdtsc(); 107 if (ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) { 108 vmx_set_test_stage(0); 109 vmcall(); 110 if (vmx_get_test_stage() == 1) 111 vmcall(); 112 } 113 vmx_set_test_stage(1); 114 while (vmx_get_test_stage() == 1) { 115 if (((rdtsc() - tsc_val) >> preempt_scale) 116 > 10 * preempt_val) { 117 vmx_set_test_stage(2); 118 vmcall(); 119 } 120 } 121 tsc_val = rdtsc(); 122 asm volatile ("hlt"); 123 vmcall(); 124 vmx_set_test_stage(5); 125 vmcall(); 126 } 127 128 int preemption_timer_exit_handler() 129 { 130 bool guest_halted; 131 u64 guest_rip; 132 ulong reason; 133 u32 insn_len; 134 u32 ctrl_exit; 135 136 guest_rip = vmcs_read(GUEST_RIP); 137 reason = vmcs_read(EXI_REASON) & 0xff; 138 insn_len = vmcs_read(EXI_INST_LEN); 139 switch (reason) { 140 case VMX_PREEMPT: 141 switch (vmx_get_test_stage()) { 142 case 1: 143 case 2: 144 report("busy-wait for preemption timer", 145 ((rdtsc() - tsc_val) >> preempt_scale) >= 146 preempt_val); 147 vmx_set_test_stage(3); 148 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 149 return VMX_TEST_RESUME; 150 case 3: 151 guest_halted = 152 (vmcs_read(GUEST_ACTV_STATE) == ACTV_HLT); 153 report("preemption timer during hlt", 154 ((rdtsc() - tsc_val) >> preempt_scale) >= 155 preempt_val && guest_halted); 156 vmx_set_test_stage(4); 157 vmcs_write(PIN_CONTROLS, 158 vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 159 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 160 return VMX_TEST_RESUME; 161 case 4: 162 report("preemption timer with 0 value", 163 saved_rip == guest_rip); 164 break; 165 default: 166 printf("Invalid stage.\n"); 167 print_vmexit_info(); 168 break; 169 } 170 break; 171 case VMX_VMCALL: 172 vmcs_write(GUEST_RIP, guest_rip + insn_len); 173 switch (vmx_get_test_stage()) { 174 case 0: 175 report("Keep preemption value", 176 vmcs_read(PREEMPT_TIMER_VALUE) == preempt_val); 177 vmx_set_test_stage(1); 178 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 179 ctrl_exit = (vmcs_read(EXI_CONTROLS) | 180 EXI_SAVE_PREEMPT) & ctrl_exit_rev.clr; 181 vmcs_write(EXI_CONTROLS, ctrl_exit); 182 return VMX_TEST_RESUME; 183 case 1: 184 report("Save preemption value", 185 vmcs_read(PREEMPT_TIMER_VALUE) < preempt_val); 186 return VMX_TEST_RESUME; 187 case 2: 188 report("busy-wait for preemption timer", 0); 189 vmx_set_test_stage(3); 190 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 191 return VMX_TEST_RESUME; 192 case 3: 193 report("preemption timer during hlt", 0); 194 vmx_set_test_stage(4); 195 /* fall through */ 196 case 4: 197 vmcs_write(PIN_CONTROLS, 198 vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 199 vmcs_write(PREEMPT_TIMER_VALUE, 0); 200 saved_rip = guest_rip + insn_len; 201 return VMX_TEST_RESUME; 202 case 5: 203 report("preemption timer with 0 value (vmcall stage 5)", 0); 204 break; 205 default: 206 // Should not reach here 207 printf("ERROR : unexpected stage, %d\n", 208 vmx_get_test_stage()); 209 print_vmexit_info(); 210 return VMX_TEST_VMEXIT; 211 } 212 break; 213 default: 214 printf("Unknown exit reason, %ld\n", reason); 215 print_vmexit_info(); 216 } 217 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 218 return VMX_TEST_VMEXIT; 219 } 220 221 void msr_bmp_init() 222 { 223 void *msr_bitmap; 224 u32 ctrl_cpu0; 225 226 msr_bitmap = alloc_page(); 227 memset(msr_bitmap, 0x0, PAGE_SIZE); 228 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 229 ctrl_cpu0 |= CPU_MSR_BITMAP; 230 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 231 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 232 } 233 234 static int test_ctrl_pat_init() 235 { 236 u64 ctrl_ent; 237 u64 ctrl_exi; 238 239 msr_bmp_init(); 240 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT) && 241 !(ctrl_exit_rev.clr & EXI_LOAD_PAT) && 242 !(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 243 printf("\tSave/load PAT is not supported\n"); 244 return 1; 245 } 246 247 ctrl_ent = vmcs_read(ENT_CONTROLS); 248 ctrl_exi = vmcs_read(EXI_CONTROLS); 249 ctrl_ent |= ctrl_enter_rev.clr & ENT_LOAD_PAT; 250 ctrl_exi |= ctrl_exit_rev.clr & (EXI_SAVE_PAT | EXI_LOAD_PAT); 251 vmcs_write(ENT_CONTROLS, ctrl_ent); 252 vmcs_write(EXI_CONTROLS, ctrl_exi); 253 ia32_pat = rdmsr(MSR_IA32_CR_PAT); 254 vmcs_write(GUEST_PAT, 0x0); 255 vmcs_write(HOST_PAT, ia32_pat); 256 return VMX_TEST_START; 257 } 258 259 static void test_ctrl_pat_main() 260 { 261 u64 guest_ia32_pat; 262 263 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 264 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) 265 printf("\tENT_LOAD_PAT is not supported.\n"); 266 else { 267 if (guest_ia32_pat != 0) { 268 report("Entry load PAT", 0); 269 return; 270 } 271 } 272 wrmsr(MSR_IA32_CR_PAT, 0x6); 273 vmcall(); 274 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 275 if (ctrl_enter_rev.clr & ENT_LOAD_PAT) 276 report("Entry load PAT", guest_ia32_pat == ia32_pat); 277 } 278 279 static int test_ctrl_pat_exit_handler() 280 { 281 u64 guest_rip; 282 ulong reason; 283 u64 guest_pat; 284 285 guest_rip = vmcs_read(GUEST_RIP); 286 reason = vmcs_read(EXI_REASON) & 0xff; 287 switch (reason) { 288 case VMX_VMCALL: 289 guest_pat = vmcs_read(GUEST_PAT); 290 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT)) { 291 printf("\tEXI_SAVE_PAT is not supported\n"); 292 vmcs_write(GUEST_PAT, 0x6); 293 } else { 294 report("Exit save PAT", guest_pat == 0x6); 295 } 296 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) 297 printf("\tEXI_LOAD_PAT is not supported\n"); 298 else 299 report("Exit load PAT", rdmsr(MSR_IA32_CR_PAT) == ia32_pat); 300 vmcs_write(GUEST_PAT, ia32_pat); 301 vmcs_write(GUEST_RIP, guest_rip + 3); 302 return VMX_TEST_RESUME; 303 default: 304 printf("ERROR : Undefined exit reason, reason = %ld.\n", reason); 305 break; 306 } 307 return VMX_TEST_VMEXIT; 308 } 309 310 static int test_ctrl_efer_init() 311 { 312 u64 ctrl_ent; 313 u64 ctrl_exi; 314 315 msr_bmp_init(); 316 ctrl_ent = vmcs_read(ENT_CONTROLS) | ENT_LOAD_EFER; 317 ctrl_exi = vmcs_read(EXI_CONTROLS) | EXI_SAVE_EFER | EXI_LOAD_EFER; 318 vmcs_write(ENT_CONTROLS, ctrl_ent & ctrl_enter_rev.clr); 319 vmcs_write(EXI_CONTROLS, ctrl_exi & ctrl_exit_rev.clr); 320 ia32_efer = rdmsr(MSR_EFER); 321 vmcs_write(GUEST_EFER, ia32_efer ^ EFER_NX); 322 vmcs_write(HOST_EFER, ia32_efer ^ EFER_NX); 323 return VMX_TEST_START; 324 } 325 326 static void test_ctrl_efer_main() 327 { 328 u64 guest_ia32_efer; 329 330 guest_ia32_efer = rdmsr(MSR_EFER); 331 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) 332 printf("\tENT_LOAD_EFER is not supported.\n"); 333 else { 334 if (guest_ia32_efer != (ia32_efer ^ EFER_NX)) { 335 report("Entry load EFER", 0); 336 return; 337 } 338 } 339 wrmsr(MSR_EFER, ia32_efer); 340 vmcall(); 341 guest_ia32_efer = rdmsr(MSR_EFER); 342 if (ctrl_enter_rev.clr & ENT_LOAD_EFER) 343 report("Entry load EFER", guest_ia32_efer == ia32_efer); 344 } 345 346 static int test_ctrl_efer_exit_handler() 347 { 348 u64 guest_rip; 349 ulong reason; 350 u64 guest_efer; 351 352 guest_rip = vmcs_read(GUEST_RIP); 353 reason = vmcs_read(EXI_REASON) & 0xff; 354 switch (reason) { 355 case VMX_VMCALL: 356 guest_efer = vmcs_read(GUEST_EFER); 357 if (!(ctrl_exit_rev.clr & EXI_SAVE_EFER)) { 358 printf("\tEXI_SAVE_EFER is not supported\n"); 359 vmcs_write(GUEST_EFER, ia32_efer); 360 } else { 361 report("Exit save EFER", guest_efer == ia32_efer); 362 } 363 if (!(ctrl_exit_rev.clr & EXI_LOAD_EFER)) { 364 printf("\tEXI_LOAD_EFER is not supported\n"); 365 wrmsr(MSR_EFER, ia32_efer ^ EFER_NX); 366 } else { 367 report("Exit load EFER", rdmsr(MSR_EFER) == (ia32_efer ^ EFER_NX)); 368 } 369 vmcs_write(GUEST_PAT, ia32_efer); 370 vmcs_write(GUEST_RIP, guest_rip + 3); 371 return VMX_TEST_RESUME; 372 default: 373 printf("ERROR : Undefined exit reason, reason = %ld.\n", reason); 374 break; 375 } 376 return VMX_TEST_VMEXIT; 377 } 378 379 u32 guest_cr0, guest_cr4; 380 381 static void cr_shadowing_main() 382 { 383 u32 cr0, cr4, tmp; 384 385 // Test read through 386 vmx_set_test_stage(0); 387 guest_cr0 = read_cr0(); 388 if (vmx_get_test_stage() == 1) 389 report("Read through CR0", 0); 390 else 391 vmcall(); 392 vmx_set_test_stage(1); 393 guest_cr4 = read_cr4(); 394 if (vmx_get_test_stage() == 2) 395 report("Read through CR4", 0); 396 else 397 vmcall(); 398 // Test write through 399 guest_cr0 = guest_cr0 ^ (X86_CR0_TS | X86_CR0_MP); 400 guest_cr4 = guest_cr4 ^ (X86_CR4_TSD | X86_CR4_DE); 401 vmx_set_test_stage(2); 402 write_cr0(guest_cr0); 403 if (vmx_get_test_stage() == 3) 404 report("Write throuth CR0", 0); 405 else 406 vmcall(); 407 vmx_set_test_stage(3); 408 write_cr4(guest_cr4); 409 if (vmx_get_test_stage() == 4) 410 report("Write through CR4", 0); 411 else 412 vmcall(); 413 // Test read shadow 414 vmx_set_test_stage(4); 415 vmcall(); 416 cr0 = read_cr0(); 417 if (vmx_get_test_stage() != 5) 418 report("Read shadowing CR0", cr0 == guest_cr0); 419 vmx_set_test_stage(5); 420 cr4 = read_cr4(); 421 if (vmx_get_test_stage() != 6) 422 report("Read shadowing CR4", cr4 == guest_cr4); 423 // Test write shadow (same value with shadow) 424 vmx_set_test_stage(6); 425 write_cr0(guest_cr0); 426 if (vmx_get_test_stage() == 7) 427 report("Write shadowing CR0 (same value with shadow)", 0); 428 else 429 vmcall(); 430 vmx_set_test_stage(7); 431 write_cr4(guest_cr4); 432 if (vmx_get_test_stage() == 8) 433 report("Write shadowing CR4 (same value with shadow)", 0); 434 else 435 vmcall(); 436 // Test write shadow (different value) 437 vmx_set_test_stage(8); 438 tmp = guest_cr0 ^ X86_CR0_TS; 439 asm volatile("mov %0, %%rsi\n\t" 440 "mov %%rsi, %%cr0\n\t" 441 ::"m"(tmp) 442 :"rsi", "memory", "cc"); 443 report("Write shadowing different X86_CR0_TS", vmx_get_test_stage() == 9); 444 vmx_set_test_stage(9); 445 tmp = guest_cr0 ^ X86_CR0_MP; 446 asm volatile("mov %0, %%rsi\n\t" 447 "mov %%rsi, %%cr0\n\t" 448 ::"m"(tmp) 449 :"rsi", "memory", "cc"); 450 report("Write shadowing different X86_CR0_MP", vmx_get_test_stage() == 10); 451 vmx_set_test_stage(10); 452 tmp = guest_cr4 ^ X86_CR4_TSD; 453 asm volatile("mov %0, %%rsi\n\t" 454 "mov %%rsi, %%cr4\n\t" 455 ::"m"(tmp) 456 :"rsi", "memory", "cc"); 457 report("Write shadowing different X86_CR4_TSD", vmx_get_test_stage() == 11); 458 vmx_set_test_stage(11); 459 tmp = guest_cr4 ^ X86_CR4_DE; 460 asm volatile("mov %0, %%rsi\n\t" 461 "mov %%rsi, %%cr4\n\t" 462 ::"m"(tmp) 463 :"rsi", "memory", "cc"); 464 report("Write shadowing different X86_CR4_DE", vmx_get_test_stage() == 12); 465 } 466 467 static int cr_shadowing_exit_handler() 468 { 469 u64 guest_rip; 470 ulong reason; 471 u32 insn_len; 472 u32 exit_qual; 473 474 guest_rip = vmcs_read(GUEST_RIP); 475 reason = vmcs_read(EXI_REASON) & 0xff; 476 insn_len = vmcs_read(EXI_INST_LEN); 477 exit_qual = vmcs_read(EXI_QUALIFICATION); 478 switch (reason) { 479 case VMX_VMCALL: 480 switch (vmx_get_test_stage()) { 481 case 0: 482 report("Read through CR0", guest_cr0 == vmcs_read(GUEST_CR0)); 483 break; 484 case 1: 485 report("Read through CR4", guest_cr4 == vmcs_read(GUEST_CR4)); 486 break; 487 case 2: 488 report("Write through CR0", guest_cr0 == vmcs_read(GUEST_CR0)); 489 break; 490 case 3: 491 report("Write through CR4", guest_cr4 == vmcs_read(GUEST_CR4)); 492 break; 493 case 4: 494 guest_cr0 = vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP); 495 guest_cr4 = vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE); 496 vmcs_write(CR0_MASK, X86_CR0_TS | X86_CR0_MP); 497 vmcs_write(CR0_READ_SHADOW, guest_cr0 & (X86_CR0_TS | X86_CR0_MP)); 498 vmcs_write(CR4_MASK, X86_CR4_TSD | X86_CR4_DE); 499 vmcs_write(CR4_READ_SHADOW, guest_cr4 & (X86_CR4_TSD | X86_CR4_DE)); 500 break; 501 case 6: 502 report("Write shadowing CR0 (same value)", 503 guest_cr0 == (vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP))); 504 break; 505 case 7: 506 report("Write shadowing CR4 (same value)", 507 guest_cr4 == (vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE))); 508 break; 509 default: 510 // Should not reach here 511 printf("ERROR : unexpected stage, %d\n", 512 vmx_get_test_stage()); 513 print_vmexit_info(); 514 return VMX_TEST_VMEXIT; 515 } 516 vmcs_write(GUEST_RIP, guest_rip + insn_len); 517 return VMX_TEST_RESUME; 518 case VMX_CR: 519 switch (vmx_get_test_stage()) { 520 case 4: 521 report("Read shadowing CR0", 0); 522 vmx_inc_test_stage(); 523 break; 524 case 5: 525 report("Read shadowing CR4", 0); 526 vmx_inc_test_stage(); 527 break; 528 case 6: 529 report("Write shadowing CR0 (same value)", 0); 530 vmx_inc_test_stage(); 531 break; 532 case 7: 533 report("Write shadowing CR4 (same value)", 0); 534 vmx_inc_test_stage(); 535 break; 536 case 8: 537 case 9: 538 // 0x600 encodes "mov %esi, %cr0" 539 if (exit_qual == 0x600) 540 vmx_inc_test_stage(); 541 break; 542 case 10: 543 case 11: 544 // 0x604 encodes "mov %esi, %cr4" 545 if (exit_qual == 0x604) 546 vmx_inc_test_stage(); 547 break; 548 default: 549 // Should not reach here 550 printf("ERROR : unexpected stage, %d\n", 551 vmx_get_test_stage()); 552 print_vmexit_info(); 553 return VMX_TEST_VMEXIT; 554 } 555 vmcs_write(GUEST_RIP, guest_rip + insn_len); 556 return VMX_TEST_RESUME; 557 default: 558 printf("Unknown exit reason, %ld\n", reason); 559 print_vmexit_info(); 560 } 561 return VMX_TEST_VMEXIT; 562 } 563 564 static int iobmp_init() 565 { 566 u32 ctrl_cpu0; 567 568 io_bitmap_a = alloc_page(); 569 io_bitmap_b = alloc_page(); 570 memset(io_bitmap_a, 0x0, PAGE_SIZE); 571 memset(io_bitmap_b, 0x0, PAGE_SIZE); 572 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 573 ctrl_cpu0 |= CPU_IO_BITMAP; 574 ctrl_cpu0 &= (~CPU_IO); 575 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 576 vmcs_write(IO_BITMAP_A, (u64)io_bitmap_a); 577 vmcs_write(IO_BITMAP_B, (u64)io_bitmap_b); 578 return VMX_TEST_START; 579 } 580 581 static void iobmp_main() 582 { 583 // stage 0, test IO pass 584 vmx_set_test_stage(0); 585 inb(0x5000); 586 outb(0x0, 0x5000); 587 report("I/O bitmap - I/O pass", vmx_get_test_stage() == 0); 588 // test IO width, in/out 589 ((u8 *)io_bitmap_a)[0] = 0xFF; 590 vmx_set_test_stage(2); 591 inb(0x0); 592 report("I/O bitmap - trap in", vmx_get_test_stage() == 3); 593 vmx_set_test_stage(3); 594 outw(0x0, 0x0); 595 report("I/O bitmap - trap out", vmx_get_test_stage() == 4); 596 vmx_set_test_stage(4); 597 inl(0x0); 598 report("I/O bitmap - I/O width, long", vmx_get_test_stage() == 5); 599 // test low/high IO port 600 vmx_set_test_stage(5); 601 ((u8 *)io_bitmap_a)[0x5000 / 8] = (1 << (0x5000 % 8)); 602 inb(0x5000); 603 report("I/O bitmap - I/O port, low part", vmx_get_test_stage() == 6); 604 vmx_set_test_stage(6); 605 ((u8 *)io_bitmap_b)[0x1000 / 8] = (1 << (0x1000 % 8)); 606 inb(0x9000); 607 report("I/O bitmap - I/O port, high part", vmx_get_test_stage() == 7); 608 // test partial pass 609 vmx_set_test_stage(7); 610 inl(0x4FFF); 611 report("I/O bitmap - partial pass", vmx_get_test_stage() == 8); 612 // test overrun 613 vmx_set_test_stage(8); 614 memset(io_bitmap_a, 0x0, PAGE_SIZE); 615 memset(io_bitmap_b, 0x0, PAGE_SIZE); 616 inl(0xFFFF); 617 report("I/O bitmap - overrun", vmx_get_test_stage() == 9); 618 vmx_set_test_stage(9); 619 vmcall(); 620 outb(0x0, 0x0); 621 report("I/O bitmap - ignore unconditional exiting", 622 vmx_get_test_stage() == 9); 623 vmx_set_test_stage(10); 624 vmcall(); 625 outb(0x0, 0x0); 626 report("I/O bitmap - unconditional exiting", 627 vmx_get_test_stage() == 11); 628 } 629 630 static int iobmp_exit_handler() 631 { 632 u64 guest_rip; 633 ulong reason, exit_qual; 634 u32 insn_len, ctrl_cpu0; 635 636 guest_rip = vmcs_read(GUEST_RIP); 637 reason = vmcs_read(EXI_REASON) & 0xff; 638 exit_qual = vmcs_read(EXI_QUALIFICATION); 639 insn_len = vmcs_read(EXI_INST_LEN); 640 switch (reason) { 641 case VMX_IO: 642 switch (vmx_get_test_stage()) { 643 case 0: 644 case 1: 645 vmx_inc_test_stage(); 646 break; 647 case 2: 648 report("I/O bitmap - I/O width, byte", 649 (exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_BYTE); 650 report("I/O bitmap - I/O direction, in", exit_qual & VMX_IO_IN); 651 vmx_inc_test_stage(); 652 break; 653 case 3: 654 report("I/O bitmap - I/O width, word", 655 (exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_WORD); 656 report("I/O bitmap - I/O direction, out", 657 !(exit_qual & VMX_IO_IN)); 658 vmx_inc_test_stage(); 659 break; 660 case 4: 661 report("I/O bitmap - I/O width, long", 662 (exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_LONG); 663 vmx_inc_test_stage(); 664 break; 665 case 5: 666 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x5000) 667 vmx_inc_test_stage(); 668 break; 669 case 6: 670 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x9000) 671 vmx_inc_test_stage(); 672 break; 673 case 7: 674 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x4FFF) 675 vmx_inc_test_stage(); 676 break; 677 case 8: 678 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0xFFFF) 679 vmx_inc_test_stage(); 680 break; 681 case 9: 682 case 10: 683 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 684 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0 & ~CPU_IO); 685 vmx_inc_test_stage(); 686 break; 687 default: 688 // Should not reach here 689 printf("ERROR : unexpected stage, %d\n", 690 vmx_get_test_stage()); 691 print_vmexit_info(); 692 return VMX_TEST_VMEXIT; 693 } 694 vmcs_write(GUEST_RIP, guest_rip + insn_len); 695 return VMX_TEST_RESUME; 696 case VMX_VMCALL: 697 switch (vmx_get_test_stage()) { 698 case 9: 699 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 700 ctrl_cpu0 |= CPU_IO | CPU_IO_BITMAP; 701 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 702 break; 703 case 10: 704 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 705 ctrl_cpu0 = (ctrl_cpu0 & ~CPU_IO_BITMAP) | CPU_IO; 706 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 707 break; 708 default: 709 // Should not reach here 710 printf("ERROR : unexpected stage, %d\n", 711 vmx_get_test_stage()); 712 print_vmexit_info(); 713 return VMX_TEST_VMEXIT; 714 } 715 vmcs_write(GUEST_RIP, guest_rip + insn_len); 716 return VMX_TEST_RESUME; 717 default: 718 printf("guest_rip = 0x%lx\n", guest_rip); 719 printf("\tERROR : Undefined exit reason, reason = %ld.\n", reason); 720 break; 721 } 722 return VMX_TEST_VMEXIT; 723 } 724 725 #define INSN_CPU0 0 726 #define INSN_CPU1 1 727 #define INSN_ALWAYS_TRAP 2 728 729 #define FIELD_EXIT_QUAL (1 << 0) 730 #define FIELD_INSN_INFO (1 << 1) 731 732 asm( 733 "insn_hlt: hlt;ret\n\t" 734 "insn_invlpg: invlpg 0x12345678;ret\n\t" 735 "insn_mwait: mwait;ret\n\t" 736 "insn_rdpmc: xor %ecx, %ecx; rdpmc;ret\n\t" 737 "insn_rdtsc: rdtsc;ret\n\t" 738 "insn_cr3_load: mov cr3,%rax; mov %rax,%cr3;ret\n\t" 739 "insn_cr3_store: mov %cr3,%rax;ret\n\t" 740 #ifdef __x86_64__ 741 "insn_cr8_load: mov %rax,%cr8;ret\n\t" 742 "insn_cr8_store: mov %cr8,%rax;ret\n\t" 743 #endif 744 "insn_monitor: monitor;ret\n\t" 745 "insn_pause: pause;ret\n\t" 746 "insn_wbinvd: wbinvd;ret\n\t" 747 "insn_cpuid: cpuid;ret\n\t" 748 "insn_invd: invd;ret\n\t" 749 ); 750 extern void insn_hlt(); 751 extern void insn_invlpg(); 752 extern void insn_mwait(); 753 extern void insn_rdpmc(); 754 extern void insn_rdtsc(); 755 extern void insn_cr3_load(); 756 extern void insn_cr3_store(); 757 #ifdef __x86_64__ 758 extern void insn_cr8_load(); 759 extern void insn_cr8_store(); 760 #endif 761 extern void insn_monitor(); 762 extern void insn_pause(); 763 extern void insn_wbinvd(); 764 extern void insn_cpuid(); 765 extern void insn_invd(); 766 767 u32 cur_insn; 768 u64 cr3; 769 770 struct insn_table { 771 const char *name; 772 u32 flag; 773 void (*insn_func)(); 774 u32 type; 775 u32 reason; 776 ulong exit_qual; 777 u32 insn_info; 778 // Use FIELD_EXIT_QUAL and FIELD_INSN_INFO to define 779 // which field need to be tested, reason is always tested 780 u32 test_field; 781 }; 782 783 /* 784 * Add more test cases of instruction intercept here. Elements in this 785 * table is: 786 * name/control flag/insn function/type/exit reason/exit qulification/ 787 * instruction info/field to test 788 * The last field defines which fields (exit_qual and insn_info) need to be 789 * tested in exit handler. If set to 0, only "reason" is checked. 790 */ 791 static struct insn_table insn_table[] = { 792 // Flags for Primary Processor-Based VM-Execution Controls 793 {"HLT", CPU_HLT, insn_hlt, INSN_CPU0, 12, 0, 0, 0}, 794 {"INVLPG", CPU_INVLPG, insn_invlpg, INSN_CPU0, 14, 795 0x12345678, 0, FIELD_EXIT_QUAL}, 796 {"MWAIT", CPU_MWAIT, insn_mwait, INSN_CPU0, 36, 0, 0, 0}, 797 {"RDPMC", CPU_RDPMC, insn_rdpmc, INSN_CPU0, 15, 0, 0, 0}, 798 {"RDTSC", CPU_RDTSC, insn_rdtsc, INSN_CPU0, 16, 0, 0, 0}, 799 {"CR3 load", CPU_CR3_LOAD, insn_cr3_load, INSN_CPU0, 28, 0x3, 0, 800 FIELD_EXIT_QUAL}, 801 {"CR3 store", CPU_CR3_STORE, insn_cr3_store, INSN_CPU0, 28, 0x13, 0, 802 FIELD_EXIT_QUAL}, 803 #ifdef __x86_64__ 804 {"CR8 load", CPU_CR8_LOAD, insn_cr8_load, INSN_CPU0, 28, 0x8, 0, 805 FIELD_EXIT_QUAL}, 806 {"CR8 store", CPU_CR8_STORE, insn_cr8_store, INSN_CPU0, 28, 0x18, 0, 807 FIELD_EXIT_QUAL}, 808 #endif 809 {"MONITOR", CPU_MONITOR, insn_monitor, INSN_CPU0, 39, 0, 0, 0}, 810 {"PAUSE", CPU_PAUSE, insn_pause, INSN_CPU0, 40, 0, 0, 0}, 811 // Flags for Secondary Processor-Based VM-Execution Controls 812 {"WBINVD", CPU_WBINVD, insn_wbinvd, INSN_CPU1, 54, 0, 0, 0}, 813 // Instructions always trap 814 {"CPUID", 0, insn_cpuid, INSN_ALWAYS_TRAP, 10, 0, 0, 0}, 815 {"INVD", 0, insn_invd, INSN_ALWAYS_TRAP, 13, 0, 0, 0}, 816 // Instructions never trap 817 {NULL}, 818 }; 819 820 static int insn_intercept_init() 821 { 822 u32 ctrl_cpu; 823 824 ctrl_cpu = ctrl_cpu_rev[0].set | CPU_SECONDARY; 825 ctrl_cpu &= ctrl_cpu_rev[0].clr; 826 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu); 827 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu_rev[1].set); 828 cr3 = read_cr3(); 829 return VMX_TEST_START; 830 } 831 832 static void insn_intercept_main() 833 { 834 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 835 vmx_set_test_stage(cur_insn * 2); 836 if ((insn_table[cur_insn].type == INSN_CPU0 && 837 !(ctrl_cpu_rev[0].clr & insn_table[cur_insn].flag)) || 838 (insn_table[cur_insn].type == INSN_CPU1 && 839 !(ctrl_cpu_rev[1].clr & insn_table[cur_insn].flag))) { 840 printf("\tCPU_CTRL%d.CPU_%s is not supported.\n", 841 insn_table[cur_insn].type - INSN_CPU0, 842 insn_table[cur_insn].name); 843 continue; 844 } 845 846 if ((insn_table[cur_insn].type == INSN_CPU0 && 847 !(ctrl_cpu_rev[0].set & insn_table[cur_insn].flag)) || 848 (insn_table[cur_insn].type == INSN_CPU1 && 849 !(ctrl_cpu_rev[1].set & insn_table[cur_insn].flag))) { 850 /* skip hlt, it stalls the guest and is tested below */ 851 if (insn_table[cur_insn].insn_func != insn_hlt) 852 insn_table[cur_insn].insn_func(); 853 report("execute %s", vmx_get_test_stage() == cur_insn * 2, 854 insn_table[cur_insn].name); 855 } else if (insn_table[cur_insn].type != INSN_ALWAYS_TRAP) 856 printf("\tCPU_CTRL%d.CPU_%s always traps.\n", 857 insn_table[cur_insn].type - INSN_CPU0, 858 insn_table[cur_insn].name); 859 860 vmcall(); 861 862 insn_table[cur_insn].insn_func(); 863 report("intercept %s", vmx_get_test_stage() == cur_insn * 2 + 1, 864 insn_table[cur_insn].name); 865 866 vmx_set_test_stage(cur_insn * 2 + 1); 867 vmcall(); 868 } 869 } 870 871 static int insn_intercept_exit_handler() 872 { 873 u64 guest_rip; 874 u32 reason; 875 ulong exit_qual; 876 u32 insn_len; 877 u32 insn_info; 878 bool pass; 879 880 guest_rip = vmcs_read(GUEST_RIP); 881 reason = vmcs_read(EXI_REASON) & 0xff; 882 exit_qual = vmcs_read(EXI_QUALIFICATION); 883 insn_len = vmcs_read(EXI_INST_LEN); 884 insn_info = vmcs_read(EXI_INST_INFO); 885 886 if (reason == VMX_VMCALL) { 887 u32 val = 0; 888 889 if (insn_table[cur_insn].type == INSN_CPU0) 890 val = vmcs_read(CPU_EXEC_CTRL0); 891 else if (insn_table[cur_insn].type == INSN_CPU1) 892 val = vmcs_read(CPU_EXEC_CTRL1); 893 894 if (vmx_get_test_stage() & 1) 895 val &= ~insn_table[cur_insn].flag; 896 else 897 val |= insn_table[cur_insn].flag; 898 899 if (insn_table[cur_insn].type == INSN_CPU0) 900 vmcs_write(CPU_EXEC_CTRL0, val | ctrl_cpu_rev[0].set); 901 else if (insn_table[cur_insn].type == INSN_CPU1) 902 vmcs_write(CPU_EXEC_CTRL1, val | ctrl_cpu_rev[1].set); 903 } else { 904 pass = (cur_insn * 2 == vmx_get_test_stage()) && 905 insn_table[cur_insn].reason == reason; 906 if (insn_table[cur_insn].test_field & FIELD_EXIT_QUAL && 907 insn_table[cur_insn].exit_qual != exit_qual) 908 pass = false; 909 if (insn_table[cur_insn].test_field & FIELD_INSN_INFO && 910 insn_table[cur_insn].insn_info != insn_info) 911 pass = false; 912 if (pass) 913 vmx_inc_test_stage(); 914 } 915 vmcs_write(GUEST_RIP, guest_rip + insn_len); 916 return VMX_TEST_RESUME; 917 } 918 919 920 static int setup_ept() 921 { 922 int support_2m; 923 unsigned long end_of_memory; 924 925 if (!(ept_vpid.val & EPT_CAP_UC) && 926 !(ept_vpid.val & EPT_CAP_WB)) { 927 printf("\tEPT paging-structure memory type " 928 "UC&WB are not supported\n"); 929 return 1; 930 } 931 if (ept_vpid.val & EPT_CAP_UC) 932 eptp = EPT_MEM_TYPE_UC; 933 else 934 eptp = EPT_MEM_TYPE_WB; 935 if (!(ept_vpid.val & EPT_CAP_PWL4)) { 936 printf("\tPWL4 is not supported\n"); 937 return 1; 938 } 939 eptp |= (3 << EPTP_PG_WALK_LEN_SHIFT); 940 pml4 = alloc_page(); 941 memset(pml4, 0, PAGE_SIZE); 942 eptp |= virt_to_phys(pml4); 943 vmcs_write(EPTP, eptp); 944 support_2m = !!(ept_vpid.val & EPT_CAP_2M_PAGE); 945 end_of_memory = fwcfg_get_u64(FW_CFG_RAM_SIZE); 946 if (end_of_memory < (1ul << 32)) 947 end_of_memory = (1ul << 32); 948 setup_ept_range(pml4, 0, end_of_memory, 0, support_2m, 949 EPT_WA | EPT_RA | EPT_EA); 950 return 0; 951 } 952 953 static int apic_version; 954 955 static int ept_init() 956 { 957 u32 ctrl_cpu[2]; 958 959 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 960 !(ctrl_cpu_rev[1].clr & CPU_EPT)) { 961 printf("\tEPT is not supported"); 962 return VMX_TEST_EXIT; 963 } 964 965 ctrl_cpu[0] = vmcs_read(CPU_EXEC_CTRL0); 966 ctrl_cpu[1] = vmcs_read(CPU_EXEC_CTRL1); 967 ctrl_cpu[0] = (ctrl_cpu[0] | CPU_SECONDARY) 968 & ctrl_cpu_rev[0].clr; 969 ctrl_cpu[1] = (ctrl_cpu[1] | CPU_EPT) 970 & ctrl_cpu_rev[1].clr; 971 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu[0]); 972 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu[1]); 973 if (setup_ept()) 974 return VMX_TEST_EXIT; 975 data_page1 = alloc_page(); 976 data_page2 = alloc_page(); 977 memset(data_page1, 0x0, PAGE_SIZE); 978 memset(data_page2, 0x0, PAGE_SIZE); 979 *((u32 *)data_page1) = MAGIC_VAL_1; 980 *((u32 *)data_page2) = MAGIC_VAL_2; 981 install_ept(pml4, (unsigned long)data_page1, (unsigned long)data_page2, 982 EPT_RA | EPT_WA | EPT_EA); 983 984 apic_version = *((u32 *)0xfee00030UL); 985 return VMX_TEST_START; 986 } 987 988 static void ept_main() 989 { 990 vmx_set_test_stage(0); 991 if (*((u32 *)data_page2) != MAGIC_VAL_1 || 992 *((u32 *)data_page1) != MAGIC_VAL_1) 993 report("EPT basic framework - read", 0); 994 else { 995 *((u32 *)data_page2) = MAGIC_VAL_3; 996 vmcall(); 997 if (vmx_get_test_stage() == 1) { 998 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 999 *((u32 *)data_page2) == MAGIC_VAL_2) 1000 report("EPT basic framework", 1); 1001 else 1002 report("EPT basic framework - remap", 1); 1003 } 1004 } 1005 // Test EPT Misconfigurations 1006 vmx_set_test_stage(1); 1007 vmcall(); 1008 *((u32 *)data_page1) = MAGIC_VAL_1; 1009 if (vmx_get_test_stage() != 2) { 1010 report("EPT misconfigurations", 0); 1011 goto t1; 1012 } 1013 vmx_set_test_stage(2); 1014 vmcall(); 1015 *((u32 *)data_page1) = MAGIC_VAL_1; 1016 report("EPT misconfigurations", vmx_get_test_stage() == 3); 1017 t1: 1018 // Test EPT violation 1019 vmx_set_test_stage(3); 1020 vmcall(); 1021 *((u32 *)data_page1) = MAGIC_VAL_1; 1022 report("EPT violation - page permission", vmx_get_test_stage() == 4); 1023 // Violation caused by EPT paging structure 1024 vmx_set_test_stage(4); 1025 vmcall(); 1026 *((u32 *)data_page1) = MAGIC_VAL_2; 1027 report("EPT violation - paging structure", vmx_get_test_stage() == 5); 1028 1029 // Test EPT access to L1 MMIO 1030 vmx_set_test_stage(6); 1031 report("EPT - MMIO access", *((u32 *)0xfee00030UL) == apic_version); 1032 1033 // Test invalid operand for INVEPT 1034 vmcall(); 1035 report("EPT - unsupported INVEPT", vmx_get_test_stage() == 7); 1036 } 1037 1038 bool invept_test(int type, u64 eptp) 1039 { 1040 bool ret, supported; 1041 1042 supported = ept_vpid.val & (EPT_CAP_INVEPT_SINGLE >> INVEPT_SINGLE << type); 1043 ret = invept(type, eptp); 1044 1045 if (ret == !supported) 1046 return false; 1047 1048 if (!supported) 1049 printf("WARNING: unsupported invept passed!\n"); 1050 else 1051 printf("WARNING: invept failed!\n"); 1052 1053 return true; 1054 } 1055 1056 static int ept_exit_handler() 1057 { 1058 u64 guest_rip; 1059 ulong reason; 1060 u32 insn_len; 1061 u32 exit_qual; 1062 static unsigned long data_page1_pte, data_page1_pte_pte; 1063 1064 guest_rip = vmcs_read(GUEST_RIP); 1065 reason = vmcs_read(EXI_REASON) & 0xff; 1066 insn_len = vmcs_read(EXI_INST_LEN); 1067 exit_qual = vmcs_read(EXI_QUALIFICATION); 1068 switch (reason) { 1069 case VMX_VMCALL: 1070 switch (vmx_get_test_stage()) { 1071 case 0: 1072 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1073 *((u32 *)data_page2) == MAGIC_VAL_2) { 1074 vmx_inc_test_stage(); 1075 install_ept(pml4, (unsigned long)data_page2, 1076 (unsigned long)data_page2, 1077 EPT_RA | EPT_WA | EPT_EA); 1078 } else 1079 report("EPT basic framework - write\n", 0); 1080 break; 1081 case 1: 1082 install_ept(pml4, (unsigned long)data_page1, 1083 (unsigned long)data_page1, EPT_WA); 1084 ept_sync(INVEPT_SINGLE, eptp); 1085 break; 1086 case 2: 1087 install_ept(pml4, (unsigned long)data_page1, 1088 (unsigned long)data_page1, 1089 EPT_RA | EPT_WA | EPT_EA | 1090 (2 << EPT_MEM_TYPE_SHIFT)); 1091 ept_sync(INVEPT_SINGLE, eptp); 1092 break; 1093 case 3: 1094 data_page1_pte = get_ept_pte(pml4, 1095 (unsigned long)data_page1, 1); 1096 set_ept_pte(pml4, (unsigned long)data_page1, 1097 1, data_page1_pte & (~EPT_PRESENT)); 1098 ept_sync(INVEPT_SINGLE, eptp); 1099 break; 1100 case 4: 1101 data_page1_pte = get_ept_pte(pml4, 1102 (unsigned long)data_page1, 2); 1103 data_page1_pte &= PAGE_MASK; 1104 data_page1_pte_pte = get_ept_pte(pml4, data_page1_pte, 2); 1105 set_ept_pte(pml4, data_page1_pte, 2, 1106 data_page1_pte_pte & (~EPT_PRESENT)); 1107 ept_sync(INVEPT_SINGLE, eptp); 1108 break; 1109 case 6: 1110 if (!invept_test(0, eptp)) 1111 vmx_inc_test_stage(); 1112 break; 1113 // Should not reach here 1114 default: 1115 printf("ERROR - unexpected stage, %d.\n", 1116 vmx_get_test_stage()); 1117 print_vmexit_info(); 1118 return VMX_TEST_VMEXIT; 1119 } 1120 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1121 return VMX_TEST_RESUME; 1122 case VMX_EPT_MISCONFIG: 1123 switch (vmx_get_test_stage()) { 1124 case 1: 1125 case 2: 1126 vmx_inc_test_stage(); 1127 install_ept(pml4, (unsigned long)data_page1, 1128 (unsigned long)data_page1, 1129 EPT_RA | EPT_WA | EPT_EA); 1130 ept_sync(INVEPT_SINGLE, eptp); 1131 break; 1132 // Should not reach here 1133 default: 1134 printf("ERROR - unexpected stage, %d.\n", 1135 vmx_get_test_stage()); 1136 print_vmexit_info(); 1137 return VMX_TEST_VMEXIT; 1138 } 1139 return VMX_TEST_RESUME; 1140 case VMX_EPT_VIOLATION: 1141 switch(vmx_get_test_stage()) { 1142 case 3: 1143 if (exit_qual == (EPT_VLT_WR | EPT_VLT_LADDR_VLD | 1144 EPT_VLT_PADDR)) 1145 vmx_inc_test_stage(); 1146 set_ept_pte(pml4, (unsigned long)data_page1, 1147 1, data_page1_pte | (EPT_PRESENT)); 1148 ept_sync(INVEPT_SINGLE, eptp); 1149 break; 1150 case 4: 1151 if (exit_qual == (EPT_VLT_RD | EPT_VLT_LADDR_VLD)) 1152 vmx_inc_test_stage(); 1153 set_ept_pte(pml4, data_page1_pte, 2, 1154 data_page1_pte_pte | (EPT_PRESENT)); 1155 ept_sync(INVEPT_SINGLE, eptp); 1156 break; 1157 default: 1158 // Should not reach here 1159 printf("ERROR : unexpected stage, %d\n", 1160 vmx_get_test_stage()); 1161 print_vmexit_info(); 1162 return VMX_TEST_VMEXIT; 1163 } 1164 return VMX_TEST_RESUME; 1165 default: 1166 printf("Unknown exit reason, %ld\n", reason); 1167 print_vmexit_info(); 1168 } 1169 return VMX_TEST_VMEXIT; 1170 } 1171 1172 bool invvpid_test(int type, u16 vpid) 1173 { 1174 bool ret, supported; 1175 1176 supported = ept_vpid.val & (VPID_CAP_INVVPID_SINGLE >> INVVPID_SINGLE << type); 1177 ret = invvpid(type, vpid, 0); 1178 1179 if (ret == !supported) 1180 return false; 1181 1182 if (!supported) 1183 printf("WARNING: unsupported invvpid passed!\n"); 1184 else 1185 printf("WARNING: invvpid failed!\n"); 1186 1187 return true; 1188 } 1189 1190 static int vpid_init() 1191 { 1192 u32 ctrl_cpu1; 1193 1194 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1195 !(ctrl_cpu_rev[1].clr & CPU_VPID)) { 1196 printf("\tVPID is not supported"); 1197 return VMX_TEST_EXIT; 1198 } 1199 1200 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 1201 ctrl_cpu1 |= CPU_VPID; 1202 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 1203 return VMX_TEST_START; 1204 } 1205 1206 static void vpid_main() 1207 { 1208 vmx_set_test_stage(0); 1209 vmcall(); 1210 report("INVVPID SINGLE ADDRESS", vmx_get_test_stage() == 1); 1211 vmx_set_test_stage(2); 1212 vmcall(); 1213 report("INVVPID SINGLE", vmx_get_test_stage() == 3); 1214 vmx_set_test_stage(4); 1215 vmcall(); 1216 report("INVVPID ALL", vmx_get_test_stage() == 5); 1217 } 1218 1219 static int vpid_exit_handler() 1220 { 1221 u64 guest_rip; 1222 ulong reason; 1223 u32 insn_len; 1224 1225 guest_rip = vmcs_read(GUEST_RIP); 1226 reason = vmcs_read(EXI_REASON) & 0xff; 1227 insn_len = vmcs_read(EXI_INST_LEN); 1228 1229 switch (reason) { 1230 case VMX_VMCALL: 1231 switch(vmx_get_test_stage()) { 1232 case 0: 1233 if (!invvpid_test(INVVPID_SINGLE_ADDRESS, 1)) 1234 vmx_inc_test_stage(); 1235 break; 1236 case 2: 1237 if (!invvpid_test(INVVPID_SINGLE, 1)) 1238 vmx_inc_test_stage(); 1239 break; 1240 case 4: 1241 if (!invvpid_test(INVVPID_ALL, 1)) 1242 vmx_inc_test_stage(); 1243 break; 1244 default: 1245 printf("ERROR: unexpected stage, %d\n", 1246 vmx_get_test_stage()); 1247 print_vmexit_info(); 1248 return VMX_TEST_VMEXIT; 1249 } 1250 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1251 return VMX_TEST_RESUME; 1252 default: 1253 printf("Unknown exit reason, %ld\n", reason); 1254 print_vmexit_info(); 1255 } 1256 return VMX_TEST_VMEXIT; 1257 } 1258 1259 #define TIMER_VECTOR 222 1260 1261 static volatile bool timer_fired; 1262 1263 static void timer_isr(isr_regs_t *regs) 1264 { 1265 timer_fired = true; 1266 apic_write(APIC_EOI, 0); 1267 } 1268 1269 static int interrupt_init(struct vmcs *vmcs) 1270 { 1271 msr_bmp_init(); 1272 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1273 handle_irq(TIMER_VECTOR, timer_isr); 1274 return VMX_TEST_START; 1275 } 1276 1277 static void interrupt_main(void) 1278 { 1279 long long start, loops; 1280 1281 vmx_set_test_stage(0); 1282 1283 apic_write(APIC_LVTT, TIMER_VECTOR); 1284 irq_enable(); 1285 1286 apic_write(APIC_TMICT, 1); 1287 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1288 asm volatile ("nop"); 1289 report("direct interrupt while running guest", timer_fired); 1290 1291 apic_write(APIC_TMICT, 0); 1292 irq_disable(); 1293 vmcall(); 1294 timer_fired = false; 1295 apic_write(APIC_TMICT, 1); 1296 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1297 asm volatile ("nop"); 1298 report("intercepted interrupt while running guest", timer_fired); 1299 1300 irq_enable(); 1301 apic_write(APIC_TMICT, 0); 1302 irq_disable(); 1303 vmcall(); 1304 timer_fired = false; 1305 start = rdtsc(); 1306 apic_write(APIC_TMICT, 1000000); 1307 1308 asm volatile ("sti; hlt"); 1309 1310 report("direct interrupt + hlt", 1311 rdtsc() - start > 1000000 && timer_fired); 1312 1313 apic_write(APIC_TMICT, 0); 1314 irq_disable(); 1315 vmcall(); 1316 timer_fired = false; 1317 start = rdtsc(); 1318 apic_write(APIC_TMICT, 1000000); 1319 1320 asm volatile ("sti; hlt"); 1321 1322 report("intercepted interrupt + hlt", 1323 rdtsc() - start > 10000 && timer_fired); 1324 1325 apic_write(APIC_TMICT, 0); 1326 irq_disable(); 1327 vmcall(); 1328 timer_fired = false; 1329 start = rdtsc(); 1330 apic_write(APIC_TMICT, 1000000); 1331 1332 irq_enable(); 1333 asm volatile ("nop"); 1334 vmcall(); 1335 1336 report("direct interrupt + activity state hlt", 1337 rdtsc() - start > 10000 && timer_fired); 1338 1339 apic_write(APIC_TMICT, 0); 1340 irq_disable(); 1341 vmcall(); 1342 timer_fired = false; 1343 start = rdtsc(); 1344 apic_write(APIC_TMICT, 1000000); 1345 1346 irq_enable(); 1347 asm volatile ("nop"); 1348 vmcall(); 1349 1350 report("intercepted interrupt + activity state hlt", 1351 rdtsc() - start > 10000 && timer_fired); 1352 1353 apic_write(APIC_TMICT, 0); 1354 irq_disable(); 1355 vmx_set_test_stage(7); 1356 vmcall(); 1357 timer_fired = false; 1358 apic_write(APIC_TMICT, 1); 1359 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1360 asm volatile ("nop"); 1361 report("running a guest with interrupt acknowledgement set", timer_fired); 1362 } 1363 1364 static int interrupt_exit_handler(void) 1365 { 1366 u64 guest_rip = vmcs_read(GUEST_RIP); 1367 ulong reason = vmcs_read(EXI_REASON) & 0xff; 1368 u32 insn_len = vmcs_read(EXI_INST_LEN); 1369 1370 switch (reason) { 1371 case VMX_VMCALL: 1372 switch (vmx_get_test_stage()) { 1373 case 0: 1374 case 2: 1375 case 5: 1376 vmcs_write(PIN_CONTROLS, 1377 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1378 break; 1379 case 7: 1380 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_INTA); 1381 vmcs_write(PIN_CONTROLS, 1382 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1383 break; 1384 case 1: 1385 case 3: 1386 vmcs_write(PIN_CONTROLS, 1387 vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1388 break; 1389 case 4: 1390 case 6: 1391 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1392 break; 1393 } 1394 vmx_inc_test_stage(); 1395 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1396 return VMX_TEST_RESUME; 1397 case VMX_EXTINT: 1398 if (vmcs_read(EXI_CONTROLS) & EXI_INTA) { 1399 int vector = vmcs_read(EXI_INTR_INFO) & 0xff; 1400 handle_external_interrupt(vector); 1401 } else { 1402 irq_enable(); 1403 asm volatile ("nop"); 1404 irq_disable(); 1405 } 1406 if (vmx_get_test_stage() >= 2) 1407 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 1408 return VMX_TEST_RESUME; 1409 default: 1410 printf("Unknown exit reason, %ld\n", reason); 1411 print_vmexit_info(); 1412 } 1413 1414 return VMX_TEST_VMEXIT; 1415 } 1416 1417 static int dbgctls_init(struct vmcs *vmcs) 1418 { 1419 u64 dr7 = 0x402; 1420 u64 zero = 0; 1421 1422 msr_bmp_init(); 1423 asm volatile( 1424 "mov %0,%%dr0\n\t" 1425 "mov %0,%%dr1\n\t" 1426 "mov %0,%%dr2\n\t" 1427 "mov %1,%%dr7\n\t" 1428 : : "r" (zero), "r" (dr7)); 1429 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1430 vmcs_write(GUEST_DR7, 0x404); 1431 vmcs_write(GUEST_DEBUGCTL, 0x2); 1432 1433 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 1434 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_SAVE_DBGCTLS); 1435 1436 return VMX_TEST_START; 1437 } 1438 1439 static void dbgctls_main(void) 1440 { 1441 u64 dr7, debugctl; 1442 1443 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1444 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1445 /* Commented out: KVM does not support DEBUGCTL so far */ 1446 (void)debugctl; 1447 report("Load debug controls", dr7 == 0x404 /* && debugctl == 0x2 */); 1448 1449 dr7 = 0x408; 1450 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1451 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1452 1453 vmx_set_test_stage(0); 1454 vmcall(); 1455 report("Save debug controls", vmx_get_test_stage() == 1); 1456 1457 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS || 1458 ctrl_exit_rev.set & EXI_SAVE_DBGCTLS) { 1459 printf("\tDebug controls are always loaded/saved\n"); 1460 return; 1461 } 1462 vmx_set_test_stage(2); 1463 vmcall(); 1464 1465 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1466 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1467 /* Commented out: KVM does not support DEBUGCTL so far */ 1468 (void)debugctl; 1469 report("Guest=host debug controls", dr7 == 0x402 /* && debugctl == 0x1 */); 1470 1471 dr7 = 0x408; 1472 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1473 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1474 1475 vmx_set_test_stage(3); 1476 vmcall(); 1477 report("Don't save debug controls", vmx_get_test_stage() == 4); 1478 } 1479 1480 static int dbgctls_exit_handler(void) 1481 { 1482 unsigned int reason = vmcs_read(EXI_REASON) & 0xff; 1483 u32 insn_len = vmcs_read(EXI_INST_LEN); 1484 u64 guest_rip = vmcs_read(GUEST_RIP); 1485 u64 dr7, debugctl; 1486 1487 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1488 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1489 1490 switch (reason) { 1491 case VMX_VMCALL: 1492 switch (vmx_get_test_stage()) { 1493 case 0: 1494 if (dr7 == 0x400 && debugctl == 0 && 1495 vmcs_read(GUEST_DR7) == 0x408 /* && 1496 Commented out: KVM does not support DEBUGCTL so far 1497 vmcs_read(GUEST_DEBUGCTL) == 0x3 */) 1498 vmx_inc_test_stage(); 1499 break; 1500 case 2: 1501 dr7 = 0x402; 1502 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1503 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1504 vmcs_write(GUEST_DR7, 0x404); 1505 vmcs_write(GUEST_DEBUGCTL, 0x2); 1506 1507 vmcs_write(ENT_CONTROLS, 1508 vmcs_read(ENT_CONTROLS) & ~ENT_LOAD_DBGCTLS); 1509 vmcs_write(EXI_CONTROLS, 1510 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_DBGCTLS); 1511 break; 1512 case 3: 1513 if (dr7 == 0x400 && debugctl == 0 && 1514 vmcs_read(GUEST_DR7) == 0x404 /* && 1515 Commented out: KVM does not support DEBUGCTL so far 1516 vmcs_read(GUEST_DEBUGCTL) == 0x2 */) 1517 vmx_inc_test_stage(); 1518 break; 1519 } 1520 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1521 return VMX_TEST_RESUME; 1522 default: 1523 printf("Unknown exit reason, %d\n", reason); 1524 print_vmexit_info(); 1525 } 1526 return VMX_TEST_VMEXIT; 1527 } 1528 1529 struct vmx_msr_entry { 1530 u32 index; 1531 u32 reserved; 1532 u64 value; 1533 } __attribute__((packed)); 1534 1535 #define MSR_MAGIC 0x31415926 1536 struct vmx_msr_entry *exit_msr_store, *entry_msr_load, *exit_msr_load; 1537 1538 static int msr_switch_init(struct vmcs *vmcs) 1539 { 1540 msr_bmp_init(); 1541 exit_msr_store = alloc_page(); 1542 exit_msr_load = alloc_page(); 1543 entry_msr_load = alloc_page(); 1544 memset(exit_msr_store, 0, PAGE_SIZE); 1545 memset(exit_msr_load, 0, PAGE_SIZE); 1546 memset(entry_msr_load, 0, PAGE_SIZE); 1547 entry_msr_load[0].index = MSR_KERNEL_GS_BASE; 1548 entry_msr_load[0].value = MSR_MAGIC; 1549 1550 vmx_set_test_stage(1); 1551 vmcs_write(ENT_MSR_LD_CNT, 1); 1552 vmcs_write(ENTER_MSR_LD_ADDR, (u64)entry_msr_load); 1553 vmcs_write(EXI_MSR_ST_CNT, 1); 1554 vmcs_write(EXIT_MSR_ST_ADDR, (u64)exit_msr_store); 1555 vmcs_write(EXI_MSR_LD_CNT, 1); 1556 vmcs_write(EXIT_MSR_LD_ADDR, (u64)exit_msr_load); 1557 return VMX_TEST_START; 1558 } 1559 1560 static void msr_switch_main() 1561 { 1562 if (vmx_get_test_stage() == 1) { 1563 report("VM entry MSR load", 1564 rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC); 1565 vmx_set_test_stage(2); 1566 wrmsr(MSR_KERNEL_GS_BASE, MSR_MAGIC + 1); 1567 exit_msr_store[0].index = MSR_KERNEL_GS_BASE; 1568 exit_msr_load[0].index = MSR_KERNEL_GS_BASE; 1569 exit_msr_load[0].value = MSR_MAGIC + 2; 1570 } 1571 vmcall(); 1572 } 1573 1574 static int msr_switch_exit_handler() 1575 { 1576 ulong reason; 1577 1578 reason = vmcs_read(EXI_REASON); 1579 if (reason == VMX_VMCALL && vmx_get_test_stage() == 2) { 1580 report("VM exit MSR store", 1581 exit_msr_store[0].value == MSR_MAGIC + 1); 1582 report("VM exit MSR load", 1583 rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC + 2); 1584 vmx_set_test_stage(3); 1585 entry_msr_load[0].index = MSR_FS_BASE; 1586 return VMX_TEST_RESUME; 1587 } 1588 printf("ERROR %s: unexpected stage=%u or reason=%lu\n", 1589 __func__, vmx_get_test_stage(), reason); 1590 return VMX_TEST_EXIT; 1591 } 1592 1593 static int msr_switch_entry_failure(struct vmentry_failure *failure) 1594 { 1595 ulong reason; 1596 1597 if (failure->early) { 1598 printf("ERROR %s: early exit\n", __func__); 1599 return VMX_TEST_EXIT; 1600 } 1601 1602 reason = vmcs_read(EXI_REASON); 1603 if (reason == (VMX_ENTRY_FAILURE | VMX_FAIL_MSR) && 1604 vmx_get_test_stage() == 3) { 1605 report("VM entry MSR load: try to load FS_BASE", 1606 vmcs_read(EXI_QUALIFICATION) == 1); 1607 return VMX_TEST_VMEXIT; 1608 } 1609 printf("ERROR %s: unexpected stage=%u or reason=%lu\n", 1610 __func__, vmx_get_test_stage(), reason); 1611 return VMX_TEST_EXIT; 1612 } 1613 1614 static int vmmcall_init(struct vmcs *vmcs ) 1615 { 1616 vmcs_write(EXC_BITMAP, 1 << UD_VECTOR); 1617 return VMX_TEST_START; 1618 } 1619 1620 static void vmmcall_main(void) 1621 { 1622 asm volatile( 1623 "mov $0xABCD, %%rax\n\t" 1624 "vmmcall\n\t" 1625 ::: "rax"); 1626 1627 report("VMMCALL", 0); 1628 } 1629 1630 static int vmmcall_exit_handler() 1631 { 1632 ulong reason; 1633 1634 reason = vmcs_read(EXI_REASON); 1635 switch (reason) { 1636 case VMX_VMCALL: 1637 printf("here\n"); 1638 report("VMMCALL triggers #UD", 0); 1639 break; 1640 case VMX_EXC_NMI: 1641 report("VMMCALL triggers #UD", 1642 (vmcs_read(EXI_INTR_INFO) & 0xff) == UD_VECTOR); 1643 break; 1644 default: 1645 printf("Unknown exit reason, %ld\n", reason); 1646 print_vmexit_info(); 1647 } 1648 1649 return VMX_TEST_VMEXIT; 1650 } 1651 1652 /* name/init/guest_main/exit_handler/syscall_handler/guest_regs */ 1653 struct vmx_test vmx_tests[] = { 1654 { "null", NULL, basic_guest_main, basic_exit_handler, NULL, {0} }, 1655 { "vmenter", NULL, vmenter_main, vmenter_exit_handler, NULL, {0} }, 1656 { "preemption timer", preemption_timer_init, preemption_timer_main, 1657 preemption_timer_exit_handler, NULL, {0} }, 1658 { "control field PAT", test_ctrl_pat_init, test_ctrl_pat_main, 1659 test_ctrl_pat_exit_handler, NULL, {0} }, 1660 { "control field EFER", test_ctrl_efer_init, test_ctrl_efer_main, 1661 test_ctrl_efer_exit_handler, NULL, {0} }, 1662 { "CR shadowing", NULL, cr_shadowing_main, 1663 cr_shadowing_exit_handler, NULL, {0} }, 1664 { "I/O bitmap", iobmp_init, iobmp_main, iobmp_exit_handler, 1665 NULL, {0} }, 1666 { "instruction intercept", insn_intercept_init, insn_intercept_main, 1667 insn_intercept_exit_handler, NULL, {0} }, 1668 { "EPT framework", ept_init, ept_main, ept_exit_handler, NULL, {0} }, 1669 { "VPID", vpid_init, vpid_main, vpid_exit_handler, NULL, {0} }, 1670 { "interrupt", interrupt_init, interrupt_main, 1671 interrupt_exit_handler, NULL, {0} }, 1672 { "debug controls", dbgctls_init, dbgctls_main, dbgctls_exit_handler, 1673 NULL, {0} }, 1674 { "MSR switch", msr_switch_init, msr_switch_main, 1675 msr_switch_exit_handler, NULL, {0}, msr_switch_entry_failure }, 1676 { "vmmcall", vmmcall_init, vmmcall_main, vmmcall_exit_handler, NULL, {0} }, 1677 { NULL, NULL, NULL, NULL, NULL, {0} }, 1678 }; 1679