1 #ifndef __VMX_H 2 #define __VMX_H 3 4 #include "libcflat.h" 5 #include "processor.h" 6 #include "bitops.h" 7 #include "asm/page.h" 8 9 struct vmcs { 10 u32 revision_id; /* vmcs revision identifier */ 11 u32 abort; /* VMX-abort indicator */ 12 /* VMCS data */ 13 char data[0]; 14 }; 15 16 struct regs { 17 u64 rax; 18 u64 rcx; 19 u64 rdx; 20 u64 rbx; 21 u64 cr2; 22 u64 rbp; 23 u64 rsi; 24 u64 rdi; 25 u64 r8; 26 u64 r9; 27 u64 r10; 28 u64 r11; 29 u64 r12; 30 u64 r13; 31 u64 r14; 32 u64 r15; 33 u64 rflags; 34 }; 35 36 struct vmentry_failure { 37 /* Did a vmlaunch or vmresume fail? */ 38 bool vmlaunch; 39 /* Instruction mnemonic (for convenience). */ 40 const char *instr; 41 /* Did the instruction return right away, or did we jump to HOST_RIP? */ 42 bool early; 43 /* Contents of [re]flags after failed entry. */ 44 unsigned long flags; 45 }; 46 47 struct vmx_test { 48 const char *name; 49 int (*init)(struct vmcs *vmcs); 50 void (*guest_main)(); 51 int (*exit_handler)(); 52 void (*syscall_handler)(u64 syscall_no); 53 struct regs guest_regs; 54 int (*entry_failure_handler)(struct vmentry_failure *failure); 55 struct vmcs *vmcs; 56 int exits; 57 }; 58 59 union vmx_basic { 60 u64 val; 61 struct { 62 u32 revision; 63 u32 size:13, 64 reserved1: 3, 65 width:1, 66 dual:1, 67 type:4, 68 insouts:1, 69 ctrl:1, 70 reserved2:8; 71 }; 72 }; 73 74 union vmx_ctrl_msr { 75 u64 val; 76 struct { 77 u32 set, clr; 78 }; 79 }; 80 81 union vmx_ept_vpid { 82 u64 val; 83 struct { 84 u32:16, 85 super:2, 86 : 2, 87 invept:1, 88 : 11; 89 u32 invvpid:1; 90 }; 91 }; 92 93 enum Encoding { 94 /* 16-Bit Control Fields */ 95 VPID = 0x0000ul, 96 /* Posted-interrupt notification vector */ 97 PINV = 0x0002ul, 98 /* EPTP index */ 99 EPTP_IDX = 0x0004ul, 100 101 /* 16-Bit Guest State Fields */ 102 GUEST_SEL_ES = 0x0800ul, 103 GUEST_SEL_CS = 0x0802ul, 104 GUEST_SEL_SS = 0x0804ul, 105 GUEST_SEL_DS = 0x0806ul, 106 GUEST_SEL_FS = 0x0808ul, 107 GUEST_SEL_GS = 0x080aul, 108 GUEST_SEL_LDTR = 0x080cul, 109 GUEST_SEL_TR = 0x080eul, 110 GUEST_INT_STATUS = 0x0810ul, 111 112 /* 16-Bit Host State Fields */ 113 HOST_SEL_ES = 0x0c00ul, 114 HOST_SEL_CS = 0x0c02ul, 115 HOST_SEL_SS = 0x0c04ul, 116 HOST_SEL_DS = 0x0c06ul, 117 HOST_SEL_FS = 0x0c08ul, 118 HOST_SEL_GS = 0x0c0aul, 119 HOST_SEL_TR = 0x0c0cul, 120 121 /* 64-Bit Control Fields */ 122 IO_BITMAP_A = 0x2000ul, 123 IO_BITMAP_B = 0x2002ul, 124 MSR_BITMAP = 0x2004ul, 125 EXIT_MSR_ST_ADDR = 0x2006ul, 126 EXIT_MSR_LD_ADDR = 0x2008ul, 127 ENTER_MSR_LD_ADDR = 0x200aul, 128 VMCS_EXEC_PTR = 0x200cul, 129 TSC_OFFSET = 0x2010ul, 130 TSC_OFFSET_HI = 0x2011ul, 131 APIC_VIRT_ADDR = 0x2012ul, 132 APIC_ACCS_ADDR = 0x2014ul, 133 EPTP = 0x201aul, 134 EPTP_HI = 0x201bul, 135 136 /* 64-Bit Readonly Data Field */ 137 INFO_PHYS_ADDR = 0x2400ul, 138 139 /* 64-Bit Guest State */ 140 VMCS_LINK_PTR = 0x2800ul, 141 VMCS_LINK_PTR_HI = 0x2801ul, 142 GUEST_DEBUGCTL = 0x2802ul, 143 GUEST_DEBUGCTL_HI = 0x2803ul, 144 GUEST_EFER = 0x2806ul, 145 GUEST_PAT = 0x2804ul, 146 GUEST_PERF_GLOBAL_CTRL = 0x2808ul, 147 GUEST_PDPTE = 0x280aul, 148 149 /* 64-Bit Host State */ 150 HOST_PAT = 0x2c00ul, 151 HOST_EFER = 0x2c02ul, 152 HOST_PERF_GLOBAL_CTRL = 0x2c04ul, 153 154 /* 32-Bit Control Fields */ 155 PIN_CONTROLS = 0x4000ul, 156 CPU_EXEC_CTRL0 = 0x4002ul, 157 EXC_BITMAP = 0x4004ul, 158 PF_ERROR_MASK = 0x4006ul, 159 PF_ERROR_MATCH = 0x4008ul, 160 CR3_TARGET_COUNT = 0x400aul, 161 EXI_CONTROLS = 0x400cul, 162 EXI_MSR_ST_CNT = 0x400eul, 163 EXI_MSR_LD_CNT = 0x4010ul, 164 ENT_CONTROLS = 0x4012ul, 165 ENT_MSR_LD_CNT = 0x4014ul, 166 ENT_INTR_INFO = 0x4016ul, 167 ENT_INTR_ERROR = 0x4018ul, 168 ENT_INST_LEN = 0x401aul, 169 TPR_THRESHOLD = 0x401cul, 170 CPU_EXEC_CTRL1 = 0x401eul, 171 172 /* 32-Bit R/O Data Fields */ 173 VMX_INST_ERROR = 0x4400ul, 174 EXI_REASON = 0x4402ul, 175 EXI_INTR_INFO = 0x4404ul, 176 EXI_INTR_ERROR = 0x4406ul, 177 IDT_VECT_INFO = 0x4408ul, 178 IDT_VECT_ERROR = 0x440aul, 179 EXI_INST_LEN = 0x440cul, 180 EXI_INST_INFO = 0x440eul, 181 182 /* 32-Bit Guest State Fields */ 183 GUEST_LIMIT_ES = 0x4800ul, 184 GUEST_LIMIT_CS = 0x4802ul, 185 GUEST_LIMIT_SS = 0x4804ul, 186 GUEST_LIMIT_DS = 0x4806ul, 187 GUEST_LIMIT_FS = 0x4808ul, 188 GUEST_LIMIT_GS = 0x480aul, 189 GUEST_LIMIT_LDTR = 0x480cul, 190 GUEST_LIMIT_TR = 0x480eul, 191 GUEST_LIMIT_GDTR = 0x4810ul, 192 GUEST_LIMIT_IDTR = 0x4812ul, 193 GUEST_AR_ES = 0x4814ul, 194 GUEST_AR_CS = 0x4816ul, 195 GUEST_AR_SS = 0x4818ul, 196 GUEST_AR_DS = 0x481aul, 197 GUEST_AR_FS = 0x481cul, 198 GUEST_AR_GS = 0x481eul, 199 GUEST_AR_LDTR = 0x4820ul, 200 GUEST_AR_TR = 0x4822ul, 201 GUEST_INTR_STATE = 0x4824ul, 202 GUEST_ACTV_STATE = 0x4826ul, 203 GUEST_SMBASE = 0x4828ul, 204 GUEST_SYSENTER_CS = 0x482aul, 205 PREEMPT_TIMER_VALUE = 0x482eul, 206 207 /* 32-Bit Host State Fields */ 208 HOST_SYSENTER_CS = 0x4c00ul, 209 210 /* Natural-Width Control Fields */ 211 CR0_MASK = 0x6000ul, 212 CR4_MASK = 0x6002ul, 213 CR0_READ_SHADOW = 0x6004ul, 214 CR4_READ_SHADOW = 0x6006ul, 215 CR3_TARGET_0 = 0x6008ul, 216 CR3_TARGET_1 = 0x600aul, 217 CR3_TARGET_2 = 0x600cul, 218 CR3_TARGET_3 = 0x600eul, 219 220 /* Natural-Width R/O Data Fields */ 221 EXI_QUALIFICATION = 0x6400ul, 222 IO_RCX = 0x6402ul, 223 IO_RSI = 0x6404ul, 224 IO_RDI = 0x6406ul, 225 IO_RIP = 0x6408ul, 226 GUEST_LINEAR_ADDRESS = 0x640aul, 227 228 /* Natural-Width Guest State Fields */ 229 GUEST_CR0 = 0x6800ul, 230 GUEST_CR3 = 0x6802ul, 231 GUEST_CR4 = 0x6804ul, 232 GUEST_BASE_ES = 0x6806ul, 233 GUEST_BASE_CS = 0x6808ul, 234 GUEST_BASE_SS = 0x680aul, 235 GUEST_BASE_DS = 0x680cul, 236 GUEST_BASE_FS = 0x680eul, 237 GUEST_BASE_GS = 0x6810ul, 238 GUEST_BASE_LDTR = 0x6812ul, 239 GUEST_BASE_TR = 0x6814ul, 240 GUEST_BASE_GDTR = 0x6816ul, 241 GUEST_BASE_IDTR = 0x6818ul, 242 GUEST_DR7 = 0x681aul, 243 GUEST_RSP = 0x681cul, 244 GUEST_RIP = 0x681eul, 245 GUEST_RFLAGS = 0x6820ul, 246 GUEST_PENDING_DEBUG = 0x6822ul, 247 GUEST_SYSENTER_ESP = 0x6824ul, 248 GUEST_SYSENTER_EIP = 0x6826ul, 249 250 /* Natural-Width Host State Fields */ 251 HOST_CR0 = 0x6c00ul, 252 HOST_CR3 = 0x6c02ul, 253 HOST_CR4 = 0x6c04ul, 254 HOST_BASE_FS = 0x6c06ul, 255 HOST_BASE_GS = 0x6c08ul, 256 HOST_BASE_TR = 0x6c0aul, 257 HOST_BASE_GDTR = 0x6c0cul, 258 HOST_BASE_IDTR = 0x6c0eul, 259 HOST_SYSENTER_ESP = 0x6c10ul, 260 HOST_SYSENTER_EIP = 0x6c12ul, 261 HOST_RSP = 0x6c14ul, 262 HOST_RIP = 0x6c16ul 263 }; 264 265 #define VMX_ENTRY_FAILURE (1ul << 31) 266 #define VMX_ENTRY_FLAGS (X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | \ 267 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF) 268 269 enum Reason { 270 VMX_EXC_NMI = 0, 271 VMX_EXTINT = 1, 272 VMX_TRIPLE_FAULT = 2, 273 VMX_INIT = 3, 274 VMX_SIPI = 4, 275 VMX_SMI_IO = 5, 276 VMX_SMI_OTHER = 6, 277 VMX_INTR_WINDOW = 7, 278 VMX_NMI_WINDOW = 8, 279 VMX_TASK_SWITCH = 9, 280 VMX_CPUID = 10, 281 VMX_GETSEC = 11, 282 VMX_HLT = 12, 283 VMX_INVD = 13, 284 VMX_INVLPG = 14, 285 VMX_RDPMC = 15, 286 VMX_RDTSC = 16, 287 VMX_RSM = 17, 288 VMX_VMCALL = 18, 289 VMX_VMCLEAR = 19, 290 VMX_VMLAUNCH = 20, 291 VMX_VMPTRLD = 21, 292 VMX_VMPTRST = 22, 293 VMX_VMREAD = 23, 294 VMX_VMRESUME = 24, 295 VMX_VMWRITE = 25, 296 VMX_VMXOFF = 26, 297 VMX_VMXON = 27, 298 VMX_CR = 28, 299 VMX_DR = 29, 300 VMX_IO = 30, 301 VMX_RDMSR = 31, 302 VMX_WRMSR = 32, 303 VMX_FAIL_STATE = 33, 304 VMX_FAIL_MSR = 34, 305 VMX_MWAIT = 36, 306 VMX_MTF = 37, 307 VMX_MONITOR = 39, 308 VMX_PAUSE = 40, 309 VMX_FAIL_MCHECK = 41, 310 VMX_TPR_THRESHOLD = 43, 311 VMX_APIC_ACCESS = 44, 312 VMX_GDTR_IDTR = 46, 313 VMX_LDTR_TR = 47, 314 VMX_EPT_VIOLATION = 48, 315 VMX_EPT_MISCONFIG = 49, 316 VMX_INVEPT = 50, 317 VMX_PREEMPT = 52, 318 VMX_INVVPID = 53, 319 VMX_WBINVD = 54, 320 VMX_XSETBV = 55 321 }; 322 323 enum Ctrl_exi { 324 EXI_SAVE_DBGCTLS = 1UL << 2, 325 EXI_HOST_64 = 1UL << 9, 326 EXI_LOAD_PERF = 1UL << 12, 327 EXI_INTA = 1UL << 15, 328 EXI_SAVE_PAT = 1UL << 18, 329 EXI_LOAD_PAT = 1UL << 19, 330 EXI_SAVE_EFER = 1UL << 20, 331 EXI_LOAD_EFER = 1UL << 21, 332 EXI_SAVE_PREEMPT = 1UL << 22, 333 }; 334 335 enum Ctrl_ent { 336 ENT_LOAD_DBGCTLS = 1UL << 2, 337 ENT_GUEST_64 = 1UL << 9, 338 ENT_LOAD_PAT = 1UL << 14, 339 ENT_LOAD_EFER = 1UL << 15, 340 }; 341 342 enum Ctrl_pin { 343 PIN_EXTINT = 1ul << 0, 344 PIN_NMI = 1ul << 3, 345 PIN_VIRT_NMI = 1ul << 5, 346 PIN_PREEMPT = 1ul << 6, 347 }; 348 349 enum Ctrl0 { 350 CPU_INTR_WINDOW = 1ul << 2, 351 CPU_HLT = 1ul << 7, 352 CPU_INVLPG = 1ul << 9, 353 CPU_MWAIT = 1ul << 10, 354 CPU_RDPMC = 1ul << 11, 355 CPU_RDTSC = 1ul << 12, 356 CPU_CR3_LOAD = 1ul << 15, 357 CPU_CR3_STORE = 1ul << 16, 358 CPU_CR8_LOAD = 1ul << 19, 359 CPU_CR8_STORE = 1ul << 20, 360 CPU_TPR_SHADOW = 1ul << 21, 361 CPU_NMI_WINDOW = 1ul << 22, 362 CPU_IO = 1ul << 24, 363 CPU_IO_BITMAP = 1ul << 25, 364 CPU_MSR_BITMAP = 1ul << 28, 365 CPU_MONITOR = 1ul << 29, 366 CPU_PAUSE = 1ul << 30, 367 CPU_SECONDARY = 1ul << 31, 368 }; 369 370 enum Ctrl1 { 371 CPU_EPT = 1ul << 1, 372 CPU_DESC_TABLE = 1ul << 2, 373 CPU_RDTSCP = 1ul << 3, 374 CPU_VPID = 1ul << 5, 375 CPU_URG = 1ul << 7, 376 CPU_WBINVD = 1ul << 6, 377 CPU_RDRAND = 1ul << 11, 378 }; 379 380 #define SAVE_GPR \ 381 "xchg %rax, regs\n\t" \ 382 "xchg %rbx, regs+0x8\n\t" \ 383 "xchg %rcx, regs+0x10\n\t" \ 384 "xchg %rdx, regs+0x18\n\t" \ 385 "xchg %rbp, regs+0x28\n\t" \ 386 "xchg %rsi, regs+0x30\n\t" \ 387 "xchg %rdi, regs+0x38\n\t" \ 388 "xchg %r8, regs+0x40\n\t" \ 389 "xchg %r9, regs+0x48\n\t" \ 390 "xchg %r10, regs+0x50\n\t" \ 391 "xchg %r11, regs+0x58\n\t" \ 392 "xchg %r12, regs+0x60\n\t" \ 393 "xchg %r13, regs+0x68\n\t" \ 394 "xchg %r14, regs+0x70\n\t" \ 395 "xchg %r15, regs+0x78\n\t" 396 397 #define LOAD_GPR SAVE_GPR 398 399 #define SAVE_GPR_C \ 400 "xchg %%rax, regs\n\t" \ 401 "xchg %%rbx, regs+0x8\n\t" \ 402 "xchg %%rcx, regs+0x10\n\t" \ 403 "xchg %%rdx, regs+0x18\n\t" \ 404 "xchg %%rbp, regs+0x28\n\t" \ 405 "xchg %%rsi, regs+0x30\n\t" \ 406 "xchg %%rdi, regs+0x38\n\t" \ 407 "xchg %%r8, regs+0x40\n\t" \ 408 "xchg %%r9, regs+0x48\n\t" \ 409 "xchg %%r10, regs+0x50\n\t" \ 410 "xchg %%r11, regs+0x58\n\t" \ 411 "xchg %%r12, regs+0x60\n\t" \ 412 "xchg %%r13, regs+0x68\n\t" \ 413 "xchg %%r14, regs+0x70\n\t" \ 414 "xchg %%r15, regs+0x78\n\t" 415 416 #define LOAD_GPR_C SAVE_GPR_C 417 418 #define VMX_IO_SIZE_MASK 0x7 419 #define _VMX_IO_BYTE 0 420 #define _VMX_IO_WORD 1 421 #define _VMX_IO_LONG 3 422 #define VMX_IO_DIRECTION_MASK (1ul << 3) 423 #define VMX_IO_IN (1ul << 3) 424 #define VMX_IO_OUT 0 425 #define VMX_IO_STRING (1ul << 4) 426 #define VMX_IO_REP (1ul << 5) 427 #define VMX_IO_OPRAND_IMM (1ul << 6) 428 #define VMX_IO_PORT_MASK 0xFFFF0000 429 #define VMX_IO_PORT_SHIFT 16 430 431 #define VMX_TEST_START 0 432 #define VMX_TEST_VMEXIT 1 433 #define VMX_TEST_EXIT 2 434 #define VMX_TEST_RESUME 3 435 436 #define HYPERCALL_BIT (1ul << 12) 437 #define HYPERCALL_MASK 0xFFF 438 #define HYPERCALL_VMEXIT 0x1 439 440 #define EPTP_PG_WALK_LEN_SHIFT 3ul 441 #define EPTP_AD_FLAG (1ul << 6) 442 443 #define EPT_MEM_TYPE_UC 0ul 444 #define EPT_MEM_TYPE_WC 1ul 445 #define EPT_MEM_TYPE_WT 4ul 446 #define EPT_MEM_TYPE_WP 5ul 447 #define EPT_MEM_TYPE_WB 6ul 448 449 #define EPT_RA 1ul 450 #define EPT_WA 2ul 451 #define EPT_EA 4ul 452 #define EPT_PRESENT (EPT_RA | EPT_WA | EPT_EA) 453 #define EPT_ACCESS_FLAG (1ul << 8) 454 #define EPT_DIRTY_FLAG (1ul << 9) 455 #define EPT_LARGE_PAGE (1ul << 7) 456 #define EPT_MEM_TYPE_SHIFT 3ul 457 #define EPT_IGNORE_PAT (1ul << 6) 458 #define EPT_SUPPRESS_VE (1ull << 63) 459 460 #define EPT_CAP_WT 1ull 461 #define EPT_CAP_PWL4 (1ull << 6) 462 #define EPT_CAP_UC (1ull << 8) 463 #define EPT_CAP_WB (1ull << 14) 464 #define EPT_CAP_2M_PAGE (1ull << 16) 465 #define EPT_CAP_1G_PAGE (1ull << 17) 466 #define EPT_CAP_INVEPT (1ull << 20) 467 #define EPT_CAP_INVEPT_SINGLE (1ull << 25) 468 #define EPT_CAP_INVEPT_ALL (1ull << 26) 469 #define EPT_CAP_AD_FLAG (1ull << 21) 470 #define VPID_CAP_INVVPID (1ull << 32) 471 #define VPID_CAP_INVVPID_SINGLE (1ull << 41) 472 #define VPID_CAP_INVVPID_ALL (1ull << 42) 473 474 #define PAGE_SIZE_2M (512 * PAGE_SIZE) 475 #define PAGE_SIZE_1G (512 * PAGE_SIZE_2M) 476 #define EPT_PAGE_LEVEL 4 477 #define EPT_PGDIR_WIDTH 9 478 #define EPT_PGDIR_MASK 511 479 #define EPT_PGDIR_ENTRIES (1 << EPT_PGDIR_WIDTH) 480 #define EPT_LEVEL_SHIFT(level) (((level)-1) * EPT_PGDIR_WIDTH + 12) 481 #define EPT_ADDR_MASK GENMASK_ULL(51, 12) 482 #define PAGE_MASK_2M (~(PAGE_SIZE_2M-1)) 483 484 #define EPT_VLT_RD 1 485 #define EPT_VLT_WR (1 << 1) 486 #define EPT_VLT_FETCH (1 << 2) 487 #define EPT_VLT_PERM_RD (1 << 3) 488 #define EPT_VLT_PERM_WR (1 << 4) 489 #define EPT_VLT_PERM_EX (1 << 5) 490 #define EPT_VLT_LADDR_VLD (1 << 7) 491 #define EPT_VLT_PADDR (1 << 8) 492 493 #define MAGIC_VAL_1 0x12345678ul 494 #define MAGIC_VAL_2 0x87654321ul 495 #define MAGIC_VAL_3 0xfffffffful 496 497 #define INVEPT_SINGLE 1 498 #define INVEPT_GLOBAL 2 499 500 #define INVVPID_SINGLE_ADDRESS 0 501 #define INVVPID_SINGLE 1 502 #define INVVPID_ALL 2 503 504 #define ACTV_ACTIVE 0 505 #define ACTV_HLT 1 506 507 extern struct regs regs; 508 509 extern union vmx_basic basic; 510 extern union vmx_ctrl_msr ctrl_pin_rev; 511 extern union vmx_ctrl_msr ctrl_cpu_rev[2]; 512 extern union vmx_ctrl_msr ctrl_exit_rev; 513 extern union vmx_ctrl_msr ctrl_enter_rev; 514 extern union vmx_ept_vpid ept_vpid; 515 516 void vmx_set_test_stage(u32 s); 517 u32 vmx_get_test_stage(void); 518 void vmx_inc_test_stage(void); 519 520 static inline int vmcs_clear(struct vmcs *vmcs) 521 { 522 bool ret; 523 u64 rflags = read_rflags() | X86_EFLAGS_CF | X86_EFLAGS_ZF; 524 525 asm volatile ("push %1; popf; vmclear %2; setbe %0" 526 : "=q" (ret) : "q" (rflags), "m" (vmcs) : "cc"); 527 return ret; 528 } 529 530 static inline u64 vmcs_read(enum Encoding enc) 531 { 532 u64 val; 533 asm volatile ("vmread %1, %0" : "=rm" (val) : "r" ((u64)enc) : "cc"); 534 return val; 535 } 536 537 static inline int vmcs_write(enum Encoding enc, u64 val) 538 { 539 bool ret; 540 asm volatile ("vmwrite %1, %2; setbe %0" 541 : "=q"(ret) : "rm" (val), "r" ((u64)enc) : "cc"); 542 return ret; 543 } 544 545 static inline int vmcs_save(struct vmcs **vmcs) 546 { 547 bool ret; 548 u64 rflags = read_rflags() | X86_EFLAGS_CF | X86_EFLAGS_ZF; 549 550 asm volatile ("push %1; popf; vmptrst %2; setbe %0" 551 : "=q" (ret) : "q" (rflags), "m" (*vmcs) : "cc"); 552 return ret; 553 } 554 555 static inline bool invept(unsigned long type, u64 eptp) 556 { 557 bool ret; 558 u64 rflags = read_rflags() | X86_EFLAGS_CF | X86_EFLAGS_ZF; 559 560 struct { 561 u64 eptp, gpa; 562 } operand = {eptp, 0}; 563 asm volatile("push %1; popf; invept %2, %3; setbe %0" 564 : "=q" (ret) : "r" (rflags), "m"(operand),"r"(type) : "cc"); 565 return ret; 566 } 567 568 static inline bool invvpid(unsigned long type, u16 vpid, u64 gva) 569 { 570 bool ret; 571 u64 rflags = read_rflags() | X86_EFLAGS_CF | X86_EFLAGS_ZF; 572 573 struct { 574 u64 vpid : 16; 575 u64 rsvd : 48; 576 u64 gva; 577 } operand = {vpid, 0, gva}; 578 asm volatile("push %1; popf; invvpid %2, %3; setbe %0" 579 : "=q" (ret) : "r" (rflags), "m"(operand),"r"(type) : "cc"); 580 return ret; 581 } 582 583 void print_vmexit_info(); 584 void print_vmentry_failure_info(struct vmentry_failure *failure); 585 void ept_sync(int type, u64 eptp); 586 void vpid_sync(int type, u16 vpid); 587 void install_ept_entry(unsigned long *pml4, int pte_level, 588 unsigned long guest_addr, unsigned long pte, 589 unsigned long *pt_page); 590 void install_1g_ept(unsigned long *pml4, unsigned long phys, 591 unsigned long guest_addr, u64 perm); 592 void install_2m_ept(unsigned long *pml4, unsigned long phys, 593 unsigned long guest_addr, u64 perm); 594 void install_ept(unsigned long *pml4, unsigned long phys, 595 unsigned long guest_addr, u64 perm); 596 void setup_ept_range(unsigned long *pml4, unsigned long start, 597 unsigned long len, int map_1g, int map_2m, u64 perm); 598 unsigned long get_ept_pte(unsigned long *pml4, 599 unsigned long guest_addr, int level); 600 int set_ept_pte(unsigned long *pml4, unsigned long guest_addr, 601 int level, u64 pte_val); 602 603 #endif 604