1 #ifndef __VMX_H 2 #define __VMX_H 3 4 #include "libcflat.h" 5 #include "processor.h" 6 #include "bitops.h" 7 #include "asm/page.h" 8 9 struct vmcs { 10 u32 revision_id; /* vmcs revision identifier */ 11 u32 abort; /* VMX-abort indicator */ 12 /* VMCS data */ 13 char data[0]; 14 }; 15 16 struct regs { 17 u64 rax; 18 u64 rcx; 19 u64 rdx; 20 u64 rbx; 21 u64 cr2; 22 u64 rbp; 23 u64 rsi; 24 u64 rdi; 25 u64 r8; 26 u64 r9; 27 u64 r10; 28 u64 r11; 29 u64 r12; 30 u64 r13; 31 u64 r14; 32 u64 r15; 33 u64 rflags; 34 }; 35 36 struct vmentry_failure { 37 /* Did a vmlaunch or vmresume fail? */ 38 bool vmlaunch; 39 /* Instruction mnemonic (for convenience). */ 40 const char *instr; 41 /* Did the instruction return right away, or did we jump to HOST_RIP? */ 42 bool early; 43 /* Contents of [re]flags after failed entry. */ 44 unsigned long flags; 45 }; 46 47 struct vmx_test { 48 const char *name; 49 int (*init)(struct vmcs *vmcs); 50 void (*guest_main)(); 51 int (*exit_handler)(); 52 void (*syscall_handler)(u64 syscall_no); 53 struct regs guest_regs; 54 int (*entry_failure_handler)(struct vmentry_failure *failure); 55 struct vmcs *vmcs; 56 int exits; 57 /* Alternative test interface. */ 58 void (*v2)(void); 59 }; 60 61 union vmx_basic { 62 u64 val; 63 struct { 64 u32 revision; 65 u32 size:13, 66 reserved1: 3, 67 width:1, 68 dual:1, 69 type:4, 70 insouts:1, 71 ctrl:1, 72 reserved2:8; 73 }; 74 }; 75 76 union vmx_ctrl_msr { 77 u64 val; 78 struct { 79 u32 set, clr; 80 }; 81 }; 82 83 union vmx_ept_vpid { 84 u64 val; 85 struct { 86 u32:16, 87 super:2, 88 : 2, 89 invept:1, 90 : 11; 91 u32 invvpid:1; 92 }; 93 }; 94 95 enum Encoding { 96 /* 16-Bit Control Fields */ 97 VPID = 0x0000ul, 98 /* Posted-interrupt notification vector */ 99 PINV = 0x0002ul, 100 /* EPTP index */ 101 EPTP_IDX = 0x0004ul, 102 103 /* 16-Bit Guest State Fields */ 104 GUEST_SEL_ES = 0x0800ul, 105 GUEST_SEL_CS = 0x0802ul, 106 GUEST_SEL_SS = 0x0804ul, 107 GUEST_SEL_DS = 0x0806ul, 108 GUEST_SEL_FS = 0x0808ul, 109 GUEST_SEL_GS = 0x080aul, 110 GUEST_SEL_LDTR = 0x080cul, 111 GUEST_SEL_TR = 0x080eul, 112 GUEST_INT_STATUS = 0x0810ul, 113 GUEST_PML_INDEX = 0x0812ul, 114 115 /* 16-Bit Host State Fields */ 116 HOST_SEL_ES = 0x0c00ul, 117 HOST_SEL_CS = 0x0c02ul, 118 HOST_SEL_SS = 0x0c04ul, 119 HOST_SEL_DS = 0x0c06ul, 120 HOST_SEL_FS = 0x0c08ul, 121 HOST_SEL_GS = 0x0c0aul, 122 HOST_SEL_TR = 0x0c0cul, 123 124 /* 64-Bit Control Fields */ 125 IO_BITMAP_A = 0x2000ul, 126 IO_BITMAP_B = 0x2002ul, 127 MSR_BITMAP = 0x2004ul, 128 EXIT_MSR_ST_ADDR = 0x2006ul, 129 EXIT_MSR_LD_ADDR = 0x2008ul, 130 ENTER_MSR_LD_ADDR = 0x200aul, 131 VMCS_EXEC_PTR = 0x200cul, 132 TSC_OFFSET = 0x2010ul, 133 TSC_OFFSET_HI = 0x2011ul, 134 APIC_VIRT_ADDR = 0x2012ul, 135 APIC_ACCS_ADDR = 0x2014ul, 136 EPTP = 0x201aul, 137 EPTP_HI = 0x201bul, 138 PMLADDR = 0x200eul, 139 PMLADDR_HI = 0x200ful, 140 141 142 /* 64-Bit Readonly Data Field */ 143 INFO_PHYS_ADDR = 0x2400ul, 144 145 /* 64-Bit Guest State */ 146 VMCS_LINK_PTR = 0x2800ul, 147 VMCS_LINK_PTR_HI = 0x2801ul, 148 GUEST_DEBUGCTL = 0x2802ul, 149 GUEST_DEBUGCTL_HI = 0x2803ul, 150 GUEST_EFER = 0x2806ul, 151 GUEST_PAT = 0x2804ul, 152 GUEST_PERF_GLOBAL_CTRL = 0x2808ul, 153 GUEST_PDPTE = 0x280aul, 154 155 /* 64-Bit Host State */ 156 HOST_PAT = 0x2c00ul, 157 HOST_EFER = 0x2c02ul, 158 HOST_PERF_GLOBAL_CTRL = 0x2c04ul, 159 160 /* 32-Bit Control Fields */ 161 PIN_CONTROLS = 0x4000ul, 162 CPU_EXEC_CTRL0 = 0x4002ul, 163 EXC_BITMAP = 0x4004ul, 164 PF_ERROR_MASK = 0x4006ul, 165 PF_ERROR_MATCH = 0x4008ul, 166 CR3_TARGET_COUNT = 0x400aul, 167 EXI_CONTROLS = 0x400cul, 168 EXI_MSR_ST_CNT = 0x400eul, 169 EXI_MSR_LD_CNT = 0x4010ul, 170 ENT_CONTROLS = 0x4012ul, 171 ENT_MSR_LD_CNT = 0x4014ul, 172 ENT_INTR_INFO = 0x4016ul, 173 ENT_INTR_ERROR = 0x4018ul, 174 ENT_INST_LEN = 0x401aul, 175 TPR_THRESHOLD = 0x401cul, 176 CPU_EXEC_CTRL1 = 0x401eul, 177 178 /* 32-Bit R/O Data Fields */ 179 VMX_INST_ERROR = 0x4400ul, 180 EXI_REASON = 0x4402ul, 181 EXI_INTR_INFO = 0x4404ul, 182 EXI_INTR_ERROR = 0x4406ul, 183 IDT_VECT_INFO = 0x4408ul, 184 IDT_VECT_ERROR = 0x440aul, 185 EXI_INST_LEN = 0x440cul, 186 EXI_INST_INFO = 0x440eul, 187 188 /* 32-Bit Guest State Fields */ 189 GUEST_LIMIT_ES = 0x4800ul, 190 GUEST_LIMIT_CS = 0x4802ul, 191 GUEST_LIMIT_SS = 0x4804ul, 192 GUEST_LIMIT_DS = 0x4806ul, 193 GUEST_LIMIT_FS = 0x4808ul, 194 GUEST_LIMIT_GS = 0x480aul, 195 GUEST_LIMIT_LDTR = 0x480cul, 196 GUEST_LIMIT_TR = 0x480eul, 197 GUEST_LIMIT_GDTR = 0x4810ul, 198 GUEST_LIMIT_IDTR = 0x4812ul, 199 GUEST_AR_ES = 0x4814ul, 200 GUEST_AR_CS = 0x4816ul, 201 GUEST_AR_SS = 0x4818ul, 202 GUEST_AR_DS = 0x481aul, 203 GUEST_AR_FS = 0x481cul, 204 GUEST_AR_GS = 0x481eul, 205 GUEST_AR_LDTR = 0x4820ul, 206 GUEST_AR_TR = 0x4822ul, 207 GUEST_INTR_STATE = 0x4824ul, 208 GUEST_ACTV_STATE = 0x4826ul, 209 GUEST_SMBASE = 0x4828ul, 210 GUEST_SYSENTER_CS = 0x482aul, 211 PREEMPT_TIMER_VALUE = 0x482eul, 212 213 /* 32-Bit Host State Fields */ 214 HOST_SYSENTER_CS = 0x4c00ul, 215 216 /* Natural-Width Control Fields */ 217 CR0_MASK = 0x6000ul, 218 CR4_MASK = 0x6002ul, 219 CR0_READ_SHADOW = 0x6004ul, 220 CR4_READ_SHADOW = 0x6006ul, 221 CR3_TARGET_0 = 0x6008ul, 222 CR3_TARGET_1 = 0x600aul, 223 CR3_TARGET_2 = 0x600cul, 224 CR3_TARGET_3 = 0x600eul, 225 226 /* Natural-Width R/O Data Fields */ 227 EXI_QUALIFICATION = 0x6400ul, 228 IO_RCX = 0x6402ul, 229 IO_RSI = 0x6404ul, 230 IO_RDI = 0x6406ul, 231 IO_RIP = 0x6408ul, 232 GUEST_LINEAR_ADDRESS = 0x640aul, 233 234 /* Natural-Width Guest State Fields */ 235 GUEST_CR0 = 0x6800ul, 236 GUEST_CR3 = 0x6802ul, 237 GUEST_CR4 = 0x6804ul, 238 GUEST_BASE_ES = 0x6806ul, 239 GUEST_BASE_CS = 0x6808ul, 240 GUEST_BASE_SS = 0x680aul, 241 GUEST_BASE_DS = 0x680cul, 242 GUEST_BASE_FS = 0x680eul, 243 GUEST_BASE_GS = 0x6810ul, 244 GUEST_BASE_LDTR = 0x6812ul, 245 GUEST_BASE_TR = 0x6814ul, 246 GUEST_BASE_GDTR = 0x6816ul, 247 GUEST_BASE_IDTR = 0x6818ul, 248 GUEST_DR7 = 0x681aul, 249 GUEST_RSP = 0x681cul, 250 GUEST_RIP = 0x681eul, 251 GUEST_RFLAGS = 0x6820ul, 252 GUEST_PENDING_DEBUG = 0x6822ul, 253 GUEST_SYSENTER_ESP = 0x6824ul, 254 GUEST_SYSENTER_EIP = 0x6826ul, 255 256 /* Natural-Width Host State Fields */ 257 HOST_CR0 = 0x6c00ul, 258 HOST_CR3 = 0x6c02ul, 259 HOST_CR4 = 0x6c04ul, 260 HOST_BASE_FS = 0x6c06ul, 261 HOST_BASE_GS = 0x6c08ul, 262 HOST_BASE_TR = 0x6c0aul, 263 HOST_BASE_GDTR = 0x6c0cul, 264 HOST_BASE_IDTR = 0x6c0eul, 265 HOST_SYSENTER_ESP = 0x6c10ul, 266 HOST_SYSENTER_EIP = 0x6c12ul, 267 HOST_RSP = 0x6c14ul, 268 HOST_RIP = 0x6c16ul 269 }; 270 271 #define VMX_ENTRY_FAILURE (1ul << 31) 272 #define VMX_ENTRY_FLAGS (X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | \ 273 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF) 274 275 enum Reason { 276 VMX_EXC_NMI = 0, 277 VMX_EXTINT = 1, 278 VMX_TRIPLE_FAULT = 2, 279 VMX_INIT = 3, 280 VMX_SIPI = 4, 281 VMX_SMI_IO = 5, 282 VMX_SMI_OTHER = 6, 283 VMX_INTR_WINDOW = 7, 284 VMX_NMI_WINDOW = 8, 285 VMX_TASK_SWITCH = 9, 286 VMX_CPUID = 10, 287 VMX_GETSEC = 11, 288 VMX_HLT = 12, 289 VMX_INVD = 13, 290 VMX_INVLPG = 14, 291 VMX_RDPMC = 15, 292 VMX_RDTSC = 16, 293 VMX_RSM = 17, 294 VMX_VMCALL = 18, 295 VMX_VMCLEAR = 19, 296 VMX_VMLAUNCH = 20, 297 VMX_VMPTRLD = 21, 298 VMX_VMPTRST = 22, 299 VMX_VMREAD = 23, 300 VMX_VMRESUME = 24, 301 VMX_VMWRITE = 25, 302 VMX_VMXOFF = 26, 303 VMX_VMXON = 27, 304 VMX_CR = 28, 305 VMX_DR = 29, 306 VMX_IO = 30, 307 VMX_RDMSR = 31, 308 VMX_WRMSR = 32, 309 VMX_FAIL_STATE = 33, 310 VMX_FAIL_MSR = 34, 311 VMX_MWAIT = 36, 312 VMX_MTF = 37, 313 VMX_MONITOR = 39, 314 VMX_PAUSE = 40, 315 VMX_FAIL_MCHECK = 41, 316 VMX_TPR_THRESHOLD = 43, 317 VMX_APIC_ACCESS = 44, 318 VMX_GDTR_IDTR = 46, 319 VMX_LDTR_TR = 47, 320 VMX_EPT_VIOLATION = 48, 321 VMX_EPT_MISCONFIG = 49, 322 VMX_INVEPT = 50, 323 VMX_PREEMPT = 52, 324 VMX_INVVPID = 53, 325 VMX_WBINVD = 54, 326 VMX_XSETBV = 55, 327 VMX_APIC_WRITE = 56, 328 VMX_RDRAND = 57, 329 VMX_INVPCID = 58, 330 VMX_VMFUNC = 59, 331 VMX_RDSEED = 61, 332 VMX_PML_FULL = 62, 333 VMX_XSAVES = 63, 334 VMX_XRSTORS = 64, 335 }; 336 337 enum Ctrl_exi { 338 EXI_SAVE_DBGCTLS = 1UL << 2, 339 EXI_HOST_64 = 1UL << 9, 340 EXI_LOAD_PERF = 1UL << 12, 341 EXI_INTA = 1UL << 15, 342 EXI_SAVE_PAT = 1UL << 18, 343 EXI_LOAD_PAT = 1UL << 19, 344 EXI_SAVE_EFER = 1UL << 20, 345 EXI_LOAD_EFER = 1UL << 21, 346 EXI_SAVE_PREEMPT = 1UL << 22, 347 }; 348 349 enum Ctrl_ent { 350 ENT_LOAD_DBGCTLS = 1UL << 2, 351 ENT_GUEST_64 = 1UL << 9, 352 ENT_LOAD_PAT = 1UL << 14, 353 ENT_LOAD_EFER = 1UL << 15, 354 }; 355 356 enum Ctrl_pin { 357 PIN_EXTINT = 1ul << 0, 358 PIN_NMI = 1ul << 3, 359 PIN_VIRT_NMI = 1ul << 5, 360 PIN_PREEMPT = 1ul << 6, 361 }; 362 363 enum Ctrl0 { 364 CPU_INTR_WINDOW = 1ul << 2, 365 CPU_HLT = 1ul << 7, 366 CPU_INVLPG = 1ul << 9, 367 CPU_MWAIT = 1ul << 10, 368 CPU_RDPMC = 1ul << 11, 369 CPU_RDTSC = 1ul << 12, 370 CPU_CR3_LOAD = 1ul << 15, 371 CPU_CR3_STORE = 1ul << 16, 372 CPU_CR8_LOAD = 1ul << 19, 373 CPU_CR8_STORE = 1ul << 20, 374 CPU_TPR_SHADOW = 1ul << 21, 375 CPU_NMI_WINDOW = 1ul << 22, 376 CPU_IO = 1ul << 24, 377 CPU_IO_BITMAP = 1ul << 25, 378 CPU_MSR_BITMAP = 1ul << 28, 379 CPU_MONITOR = 1ul << 29, 380 CPU_PAUSE = 1ul << 30, 381 CPU_SECONDARY = 1ul << 31, 382 }; 383 384 enum Ctrl1 { 385 CPU_EPT = 1ul << 1, 386 CPU_DESC_TABLE = 1ul << 2, 387 CPU_RDTSCP = 1ul << 3, 388 CPU_VPID = 1ul << 5, 389 CPU_URG = 1ul << 7, 390 CPU_WBINVD = 1ul << 6, 391 CPU_RDRAND = 1ul << 11, 392 CPU_PML = 1ul << 17, 393 }; 394 395 enum Intr_type { 396 VMX_INTR_TYPE_EXT_INTR = 0, 397 VMX_INTR_TYPE_NMI_INTR = 2, 398 VMX_INTR_TYPE_HARD_EXCEPTION = 3, 399 VMX_INTR_TYPE_SOFT_INTR = 4, 400 VMX_INTR_TYPE_SOFT_EXCEPTION = 6, 401 }; 402 403 /* 404 * Interruption-information format 405 */ 406 #define INTR_INFO_VECTOR_MASK 0xff /* 7:0 */ 407 #define INTR_INFO_INTR_TYPE_MASK 0x700 /* 10:8 */ 408 #define INTR_INFO_DELIVER_CODE_MASK 0x800 /* 11 */ 409 #define INTR_INFO_UNBLOCK_NMI_MASK 0x1000 /* 12 */ 410 #define INTR_INFO_VALID_MASK 0x80000000 /* 31 */ 411 412 #define INTR_INFO_INTR_TYPE_SHIFT 8 413 414 /* 415 * VM-instruction error numbers 416 */ 417 enum vm_instruction_error_number { 418 VMXERR_VMCALL_IN_VMX_ROOT_OPERATION = 1, 419 VMXERR_VMCLEAR_INVALID_ADDRESS = 2, 420 VMXERR_VMCLEAR_VMXON_POINTER = 3, 421 VMXERR_VMLAUNCH_NONCLEAR_VMCS = 4, 422 VMXERR_VMRESUME_NONLAUNCHED_VMCS = 5, 423 VMXERR_VMRESUME_AFTER_VMXOFF = 6, 424 VMXERR_ENTRY_INVALID_CONTROL_FIELD = 7, 425 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD = 8, 426 VMXERR_VMPTRLD_INVALID_ADDRESS = 9, 427 VMXERR_VMPTRLD_VMXON_POINTER = 10, 428 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID = 11, 429 VMXERR_UNSUPPORTED_VMCS_COMPONENT = 12, 430 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT = 13, 431 VMXERR_VMXON_IN_VMX_ROOT_OPERATION = 15, 432 VMXERR_ENTRY_INVALID_EXECUTIVE_VMCS_POINTER = 16, 433 VMXERR_ENTRY_NONLAUNCHED_EXECUTIVE_VMCS = 17, 434 VMXERR_ENTRY_EXECUTIVE_VMCS_POINTER_NOT_VMXON_POINTER = 18, 435 VMXERR_VMCALL_NONCLEAR_VMCS = 19, 436 VMXERR_VMCALL_INVALID_VM_EXIT_CONTROL_FIELDS = 20, 437 VMXERR_VMCALL_INCORRECT_MSEG_REVISION_ID = 22, 438 VMXERR_VMXOFF_UNDER_DUAL_MONITOR_TREATMENT_OF_SMIS_AND_SMM = 23, 439 VMXERR_VMCALL_INVALID_SMM_MONITOR_FEATURES = 24, 440 VMXERR_ENTRY_INVALID_VM_EXECUTION_CONTROL_FIELDS_IN_EXECUTIVE_VMCS = 25, 441 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS = 26, 442 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID = 28, 443 }; 444 445 #define SAVE_GPR \ 446 "xchg %rax, regs\n\t" \ 447 "xchg %rbx, regs+0x8\n\t" \ 448 "xchg %rcx, regs+0x10\n\t" \ 449 "xchg %rdx, regs+0x18\n\t" \ 450 "xchg %rbp, regs+0x28\n\t" \ 451 "xchg %rsi, regs+0x30\n\t" \ 452 "xchg %rdi, regs+0x38\n\t" \ 453 "xchg %r8, regs+0x40\n\t" \ 454 "xchg %r9, regs+0x48\n\t" \ 455 "xchg %r10, regs+0x50\n\t" \ 456 "xchg %r11, regs+0x58\n\t" \ 457 "xchg %r12, regs+0x60\n\t" \ 458 "xchg %r13, regs+0x68\n\t" \ 459 "xchg %r14, regs+0x70\n\t" \ 460 "xchg %r15, regs+0x78\n\t" 461 462 #define LOAD_GPR SAVE_GPR 463 464 #define SAVE_GPR_C \ 465 "xchg %%rax, regs\n\t" \ 466 "xchg %%rbx, regs+0x8\n\t" \ 467 "xchg %%rcx, regs+0x10\n\t" \ 468 "xchg %%rdx, regs+0x18\n\t" \ 469 "xchg %%rbp, regs+0x28\n\t" \ 470 "xchg %%rsi, regs+0x30\n\t" \ 471 "xchg %%rdi, regs+0x38\n\t" \ 472 "xchg %%r8, regs+0x40\n\t" \ 473 "xchg %%r9, regs+0x48\n\t" \ 474 "xchg %%r10, regs+0x50\n\t" \ 475 "xchg %%r11, regs+0x58\n\t" \ 476 "xchg %%r12, regs+0x60\n\t" \ 477 "xchg %%r13, regs+0x68\n\t" \ 478 "xchg %%r14, regs+0x70\n\t" \ 479 "xchg %%r15, regs+0x78\n\t" 480 481 #define LOAD_GPR_C SAVE_GPR_C 482 483 #define VMX_IO_SIZE_MASK 0x7 484 #define _VMX_IO_BYTE 0 485 #define _VMX_IO_WORD 1 486 #define _VMX_IO_LONG 3 487 #define VMX_IO_DIRECTION_MASK (1ul << 3) 488 #define VMX_IO_IN (1ul << 3) 489 #define VMX_IO_OUT 0 490 #define VMX_IO_STRING (1ul << 4) 491 #define VMX_IO_REP (1ul << 5) 492 #define VMX_IO_OPRAND_IMM (1ul << 6) 493 #define VMX_IO_PORT_MASK 0xFFFF0000 494 #define VMX_IO_PORT_SHIFT 16 495 496 #define VMX_TEST_START 0 497 #define VMX_TEST_VMEXIT 1 498 #define VMX_TEST_EXIT 2 499 #define VMX_TEST_RESUME 3 500 #define VMX_TEST_VMABORT 4 501 #define VMX_TEST_VMSKIP 5 502 503 #define HYPERCALL_BIT (1ul << 12) 504 #define HYPERCALL_MASK 0xFFF 505 #define HYPERCALL_VMEXIT 0x1 506 #define HYPERCALL_VMABORT 0x2 507 #define HYPERCALL_VMSKIP 0x3 508 509 #define EPTP_PG_WALK_LEN_SHIFT 3ul 510 #define EPTP_AD_FLAG (1ul << 6) 511 512 #define EPT_MEM_TYPE_UC 0ul 513 #define EPT_MEM_TYPE_WC 1ul 514 #define EPT_MEM_TYPE_WT 4ul 515 #define EPT_MEM_TYPE_WP 5ul 516 #define EPT_MEM_TYPE_WB 6ul 517 518 #define EPT_RA 1ul 519 #define EPT_WA 2ul 520 #define EPT_EA 4ul 521 #define EPT_PRESENT (EPT_RA | EPT_WA | EPT_EA) 522 #define EPT_ACCESS_FLAG (1ul << 8) 523 #define EPT_DIRTY_FLAG (1ul << 9) 524 #define EPT_LARGE_PAGE (1ul << 7) 525 #define EPT_MEM_TYPE_SHIFT 3ul 526 #define EPT_IGNORE_PAT (1ul << 6) 527 #define EPT_SUPPRESS_VE (1ull << 63) 528 529 #define EPT_CAP_WT 1ull 530 #define EPT_CAP_PWL4 (1ull << 6) 531 #define EPT_CAP_UC (1ull << 8) 532 #define EPT_CAP_WB (1ull << 14) 533 #define EPT_CAP_2M_PAGE (1ull << 16) 534 #define EPT_CAP_1G_PAGE (1ull << 17) 535 #define EPT_CAP_INVEPT (1ull << 20) 536 #define EPT_CAP_INVEPT_SINGLE (1ull << 25) 537 #define EPT_CAP_INVEPT_ALL (1ull << 26) 538 #define EPT_CAP_AD_FLAG (1ull << 21) 539 #define VPID_CAP_INVVPID (1ull << 32) 540 #define VPID_CAP_INVVPID_SINGLE (1ull << 41) 541 #define VPID_CAP_INVVPID_ALL (1ull << 42) 542 543 #define PAGE_SIZE_2M (512 * PAGE_SIZE) 544 #define PAGE_SIZE_1G (512 * PAGE_SIZE_2M) 545 #define EPT_PAGE_LEVEL 4 546 #define EPT_PGDIR_WIDTH 9 547 #define EPT_PGDIR_MASK 511 548 #define EPT_PGDIR_ENTRIES (1 << EPT_PGDIR_WIDTH) 549 #define EPT_LEVEL_SHIFT(level) (((level)-1) * EPT_PGDIR_WIDTH + 12) 550 #define EPT_ADDR_MASK GENMASK_ULL(51, 12) 551 #define PAGE_MASK_2M (~(PAGE_SIZE_2M-1)) 552 553 #define EPT_VLT_RD 1 554 #define EPT_VLT_WR (1 << 1) 555 #define EPT_VLT_FETCH (1 << 2) 556 #define EPT_VLT_PERM_RD (1 << 3) 557 #define EPT_VLT_PERM_WR (1 << 4) 558 #define EPT_VLT_PERM_EX (1 << 5) 559 #define EPT_VLT_PERMS (EPT_VLT_PERM_RD | EPT_VLT_PERM_WR | \ 560 EPT_VLT_PERM_EX) 561 #define EPT_VLT_LADDR_VLD (1 << 7) 562 #define EPT_VLT_PADDR (1 << 8) 563 564 #define MAGIC_VAL_1 0x12345678ul 565 #define MAGIC_VAL_2 0x87654321ul 566 #define MAGIC_VAL_3 0xfffffffful 567 #define MAGIC_VAL_4 0xdeadbeeful 568 569 #define INVEPT_SINGLE 1 570 #define INVEPT_GLOBAL 2 571 572 #define INVVPID_SINGLE_ADDRESS 0 573 #define INVVPID_SINGLE 1 574 #define INVVPID_ALL 2 575 576 #define ACTV_ACTIVE 0 577 #define ACTV_HLT 1 578 579 extern struct regs regs; 580 581 extern union vmx_basic basic; 582 extern union vmx_ctrl_msr ctrl_pin_rev; 583 extern union vmx_ctrl_msr ctrl_cpu_rev[2]; 584 extern union vmx_ctrl_msr ctrl_exit_rev; 585 extern union vmx_ctrl_msr ctrl_enter_rev; 586 extern union vmx_ept_vpid ept_vpid; 587 588 void vmx_set_test_stage(u32 s); 589 u32 vmx_get_test_stage(void); 590 void vmx_inc_test_stage(void); 591 592 static inline int make_vmcs_current(struct vmcs *vmcs) 593 { 594 bool ret; 595 u64 rflags = read_rflags() | X86_EFLAGS_CF | X86_EFLAGS_ZF; 596 597 asm volatile ("push %1; popf; vmptrld %2; setbe %0" 598 : "=q" (ret) : "q" (rflags), "m" (vmcs) : "cc"); 599 return ret; 600 } 601 602 static inline int vmcs_clear(struct vmcs *vmcs) 603 { 604 bool ret; 605 u64 rflags = read_rflags() | X86_EFLAGS_CF | X86_EFLAGS_ZF; 606 607 asm volatile ("push %1; popf; vmclear %2; setbe %0" 608 : "=q" (ret) : "q" (rflags), "m" (vmcs) : "cc"); 609 return ret; 610 } 611 612 static inline u64 vmcs_read(enum Encoding enc) 613 { 614 u64 val; 615 asm volatile ("vmread %1, %0" : "=rm" (val) : "r" ((u64)enc) : "cc"); 616 return val; 617 } 618 619 static inline int vmcs_read_checking(enum Encoding enc, u64 *value) 620 { 621 u64 rflags = read_rflags() | X86_EFLAGS_CF | X86_EFLAGS_ZF; 622 u64 encoding = enc; 623 u64 val; 624 625 asm volatile ("shl $8, %%rax;" 626 "sahf;" 627 "vmread %[encoding], %[val];" 628 "lahf;" 629 "shr $8, %%rax" 630 : /* output */ [val]"=rm"(val), "+a"(rflags) 631 : /* input */ [encoding]"r"(encoding) 632 : /* clobber */ "cc"); 633 634 *value = val; 635 return rflags & (X86_EFLAGS_CF | X86_EFLAGS_ZF); 636 } 637 638 static inline int vmcs_write(enum Encoding enc, u64 val) 639 { 640 bool ret; 641 asm volatile ("vmwrite %1, %2; setbe %0" 642 : "=q"(ret) : "rm" (val), "r" ((u64)enc) : "cc"); 643 return ret; 644 } 645 646 static inline int vmcs_save(struct vmcs **vmcs) 647 { 648 bool ret; 649 u64 rflags = read_rflags() | X86_EFLAGS_CF | X86_EFLAGS_ZF; 650 651 asm volatile ("push %1; popf; vmptrst %2; setbe %0" 652 : "=q" (ret) : "q" (rflags), "m" (*vmcs) : "cc"); 653 return ret; 654 } 655 656 static inline bool invept(unsigned long type, u64 eptp) 657 { 658 bool ret; 659 u64 rflags = read_rflags() | X86_EFLAGS_CF | X86_EFLAGS_ZF; 660 661 struct { 662 u64 eptp, gpa; 663 } operand = {eptp, 0}; 664 asm volatile("push %1; popf; invept %2, %3; setbe %0" 665 : "=q" (ret) : "r" (rflags), "m"(operand),"r"(type) : "cc"); 666 return ret; 667 } 668 669 static inline bool invvpid(unsigned long type, u16 vpid, u64 gva) 670 { 671 bool ret; 672 u64 rflags = read_rflags() | X86_EFLAGS_CF | X86_EFLAGS_ZF; 673 674 struct { 675 u64 vpid : 16; 676 u64 rsvd : 48; 677 u64 gva; 678 } operand = {vpid, 0, gva}; 679 asm volatile("push %1; popf; invvpid %2, %3; setbe %0" 680 : "=q" (ret) : "r" (rflags), "m"(operand),"r"(type) : "cc"); 681 return ret; 682 } 683 684 const char *exit_reason_description(u64 reason); 685 void print_vmexit_info(); 686 void print_vmentry_failure_info(struct vmentry_failure *failure); 687 void ept_sync(int type, u64 eptp); 688 void vpid_sync(int type, u16 vpid); 689 void install_ept_entry(unsigned long *pml4, int pte_level, 690 unsigned long guest_addr, unsigned long pte, 691 unsigned long *pt_page); 692 void install_1g_ept(unsigned long *pml4, unsigned long phys, 693 unsigned long guest_addr, u64 perm); 694 void install_2m_ept(unsigned long *pml4, unsigned long phys, 695 unsigned long guest_addr, u64 perm); 696 void install_ept(unsigned long *pml4, unsigned long phys, 697 unsigned long guest_addr, u64 perm); 698 void setup_ept_range(unsigned long *pml4, unsigned long start, 699 unsigned long len, int map_1g, int map_2m, u64 perm); 700 unsigned long get_ept_pte(unsigned long *pml4, 701 unsigned long guest_addr, int level); 702 void set_ept_pte(unsigned long *pml4, unsigned long guest_addr, 703 int level, u64 pte_val); 704 void check_ept_ad(unsigned long *pml4, u64 guest_cr3, 705 unsigned long guest_addr, int expected_gpa_ad, 706 int expected_pt_ad); 707 void clear_ept_ad(unsigned long *pml4, u64 guest_cr3, 708 unsigned long guest_addr); 709 710 bool ept_2m_supported(void); 711 bool ept_1g_supported(void); 712 bool ept_huge_pages_supported(int level); 713 bool ept_execute_only_supported(void); 714 bool ept_ad_bits_supported(void); 715 716 void enter_guest(void); 717 718 typedef void (*test_guest_func)(void); 719 typedef void (*test_teardown_func)(void *data); 720 void test_set_guest(test_guest_func func); 721 void test_add_teardown(test_teardown_func func, void *data); 722 void test_skip(const char *msg); 723 724 void __abort_test(void); 725 726 #define TEST_ASSERT(cond) \ 727 do { \ 728 if (!(cond)) { \ 729 report("%s:%d: Assertion failed: %s", 0, \ 730 __FILE__, __LINE__, #cond); \ 731 dump_stack(); \ 732 __abort_test(); \ 733 } \ 734 report_pass(); \ 735 } while (0) 736 737 #define TEST_ASSERT_MSG(cond, fmt, args...) \ 738 do { \ 739 if (!(cond)) { \ 740 report("%s:%d: Assertion failed: %s\n" fmt, 0, \ 741 __FILE__, __LINE__, #cond, ##args); \ 742 dump_stack(); \ 743 __abort_test(); \ 744 } \ 745 report_pass(); \ 746 } while (0) 747 748 #define __TEST_EQ(a, b, a_str, b_str, assertion, fmt, args...) \ 749 do { \ 750 typeof(a) _a = a; \ 751 typeof(b) _b = b; \ 752 if (_a != _b) { \ 753 char _bin_a[BINSTR_SZ]; \ 754 char _bin_b[BINSTR_SZ]; \ 755 binstr(_a, _bin_a); \ 756 binstr(_b, _bin_b); \ 757 report("%s:%d: %s failed: (%s) == (%s)\n" \ 758 "\tLHS: 0x%016lx - %s - %lu\n" \ 759 "\tRHS: 0x%016lx - %s - %lu%s" fmt, 0, \ 760 __FILE__, __LINE__, \ 761 assertion ? "Assertion" : "Expectation", a_str, b_str, \ 762 (unsigned long) _a, _bin_a, (unsigned long) _a, \ 763 (unsigned long) _b, _bin_b, (unsigned long) _b, \ 764 fmt[0] == '\0' ? "" : "\n", ## args); \ 765 dump_stack(); \ 766 if (assertion) \ 767 __abort_test(); \ 768 } \ 769 report_pass(); \ 770 } while (0) 771 772 #define TEST_ASSERT_EQ(a, b) __TEST_EQ(a, b, #a, #b, 1, "") 773 #define TEST_ASSERT_EQ_MSG(a, b, fmt, args...) \ 774 __TEST_EQ(a, b, #a, #b, 1, fmt, ## args) 775 #define TEST_EXPECT_EQ(a, b) __TEST_EQ(a, b, #a, #b, 0, "") 776 #define TEST_EXPECT_EQ_MSG(a, b, fmt, args...) \ 777 __TEST_EQ(a, b, #a, #b, 0, fmt, ## args) 778 779 #endif 780