1 #ifndef __VMX_H 2 #define __VMX_H 3 4 #include "libcflat.h" 5 #include "processor.h" 6 #include "bitops.h" 7 8 struct vmcs { 9 u32 revision_id; /* vmcs revision identifier */ 10 u32 abort; /* VMX-abort indicator */ 11 /* VMCS data */ 12 char data[0]; 13 }; 14 15 struct regs { 16 u64 rax; 17 u64 rcx; 18 u64 rdx; 19 u64 rbx; 20 u64 cr2; 21 u64 rbp; 22 u64 rsi; 23 u64 rdi; 24 u64 r8; 25 u64 r9; 26 u64 r10; 27 u64 r11; 28 u64 r12; 29 u64 r13; 30 u64 r14; 31 u64 r15; 32 u64 rflags; 33 }; 34 35 struct vmx_test { 36 const char *name; 37 int (*init)(struct vmcs *vmcs); 38 void (*guest_main)(); 39 int (*exit_handler)(); 40 void (*syscall_handler)(u64 syscall_no); 41 struct regs guest_regs; 42 struct vmcs *vmcs; 43 int exits; 44 }; 45 46 union vmx_basic { 47 u64 val; 48 struct { 49 u32 revision; 50 u32 size:13, 51 reserved1: 3, 52 width:1, 53 dual:1, 54 type:4, 55 insouts:1, 56 ctrl:1, 57 reserved2:8; 58 }; 59 }; 60 61 union vmx_ctrl_msr { 62 u64 val; 63 struct { 64 u32 set, clr; 65 }; 66 }; 67 68 union vmx_ept_vpid { 69 u64 val; 70 struct { 71 u32:16, 72 super:2, 73 : 2, 74 invept:1, 75 : 11; 76 u32 invvpid:1; 77 }; 78 }; 79 80 enum Encoding { 81 /* 16-Bit Control Fields */ 82 VPID = 0x0000ul, 83 /* Posted-interrupt notification vector */ 84 PINV = 0x0002ul, 85 /* EPTP index */ 86 EPTP_IDX = 0x0004ul, 87 88 /* 16-Bit Guest State Fields */ 89 GUEST_SEL_ES = 0x0800ul, 90 GUEST_SEL_CS = 0x0802ul, 91 GUEST_SEL_SS = 0x0804ul, 92 GUEST_SEL_DS = 0x0806ul, 93 GUEST_SEL_FS = 0x0808ul, 94 GUEST_SEL_GS = 0x080aul, 95 GUEST_SEL_LDTR = 0x080cul, 96 GUEST_SEL_TR = 0x080eul, 97 GUEST_INT_STATUS = 0x0810ul, 98 99 /* 16-Bit Host State Fields */ 100 HOST_SEL_ES = 0x0c00ul, 101 HOST_SEL_CS = 0x0c02ul, 102 HOST_SEL_SS = 0x0c04ul, 103 HOST_SEL_DS = 0x0c06ul, 104 HOST_SEL_FS = 0x0c08ul, 105 HOST_SEL_GS = 0x0c0aul, 106 HOST_SEL_TR = 0x0c0cul, 107 108 /* 64-Bit Control Fields */ 109 IO_BITMAP_A = 0x2000ul, 110 IO_BITMAP_B = 0x2002ul, 111 MSR_BITMAP = 0x2004ul, 112 EXIT_MSR_ST_ADDR = 0x2006ul, 113 EXIT_MSR_LD_ADDR = 0x2008ul, 114 ENTER_MSR_LD_ADDR = 0x200aul, 115 VMCS_EXEC_PTR = 0x200cul, 116 TSC_OFFSET = 0x2010ul, 117 TSC_OFFSET_HI = 0x2011ul, 118 APIC_VIRT_ADDR = 0x2012ul, 119 APIC_ACCS_ADDR = 0x2014ul, 120 EPTP = 0x201aul, 121 EPTP_HI = 0x201bul, 122 123 /* 64-Bit Readonly Data Field */ 124 INFO_PHYS_ADDR = 0x2400ul, 125 126 /* 64-Bit Guest State */ 127 VMCS_LINK_PTR = 0x2800ul, 128 VMCS_LINK_PTR_HI = 0x2801ul, 129 GUEST_DEBUGCTL = 0x2802ul, 130 GUEST_DEBUGCTL_HI = 0x2803ul, 131 GUEST_EFER = 0x2806ul, 132 GUEST_PAT = 0x2804ul, 133 GUEST_PERF_GLOBAL_CTRL = 0x2808ul, 134 GUEST_PDPTE = 0x280aul, 135 136 /* 64-Bit Host State */ 137 HOST_PAT = 0x2c00ul, 138 HOST_EFER = 0x2c02ul, 139 HOST_PERF_GLOBAL_CTRL = 0x2c04ul, 140 141 /* 32-Bit Control Fields */ 142 PIN_CONTROLS = 0x4000ul, 143 CPU_EXEC_CTRL0 = 0x4002ul, 144 EXC_BITMAP = 0x4004ul, 145 PF_ERROR_MASK = 0x4006ul, 146 PF_ERROR_MATCH = 0x4008ul, 147 CR3_TARGET_COUNT = 0x400aul, 148 EXI_CONTROLS = 0x400cul, 149 EXI_MSR_ST_CNT = 0x400eul, 150 EXI_MSR_LD_CNT = 0x4010ul, 151 ENT_CONTROLS = 0x4012ul, 152 ENT_MSR_LD_CNT = 0x4014ul, 153 ENT_INTR_INFO = 0x4016ul, 154 ENT_INTR_ERROR = 0x4018ul, 155 ENT_INST_LEN = 0x401aul, 156 TPR_THRESHOLD = 0x401cul, 157 CPU_EXEC_CTRL1 = 0x401eul, 158 159 /* 32-Bit R/O Data Fields */ 160 VMX_INST_ERROR = 0x4400ul, 161 EXI_REASON = 0x4402ul, 162 EXI_INTR_INFO = 0x4404ul, 163 EXI_INTR_ERROR = 0x4406ul, 164 IDT_VECT_INFO = 0x4408ul, 165 IDT_VECT_ERROR = 0x440aul, 166 EXI_INST_LEN = 0x440cul, 167 EXI_INST_INFO = 0x440eul, 168 169 /* 32-Bit Guest State Fields */ 170 GUEST_LIMIT_ES = 0x4800ul, 171 GUEST_LIMIT_CS = 0x4802ul, 172 GUEST_LIMIT_SS = 0x4804ul, 173 GUEST_LIMIT_DS = 0x4806ul, 174 GUEST_LIMIT_FS = 0x4808ul, 175 GUEST_LIMIT_GS = 0x480aul, 176 GUEST_LIMIT_LDTR = 0x480cul, 177 GUEST_LIMIT_TR = 0x480eul, 178 GUEST_LIMIT_GDTR = 0x4810ul, 179 GUEST_LIMIT_IDTR = 0x4812ul, 180 GUEST_AR_ES = 0x4814ul, 181 GUEST_AR_CS = 0x4816ul, 182 GUEST_AR_SS = 0x4818ul, 183 GUEST_AR_DS = 0x481aul, 184 GUEST_AR_FS = 0x481cul, 185 GUEST_AR_GS = 0x481eul, 186 GUEST_AR_LDTR = 0x4820ul, 187 GUEST_AR_TR = 0x4822ul, 188 GUEST_INTR_STATE = 0x4824ul, 189 GUEST_ACTV_STATE = 0x4826ul, 190 GUEST_SMBASE = 0x4828ul, 191 GUEST_SYSENTER_CS = 0x482aul, 192 PREEMPT_TIMER_VALUE = 0x482eul, 193 194 /* 32-Bit Host State Fields */ 195 HOST_SYSENTER_CS = 0x4c00ul, 196 197 /* Natural-Width Control Fields */ 198 CR0_MASK = 0x6000ul, 199 CR4_MASK = 0x6002ul, 200 CR0_READ_SHADOW = 0x6004ul, 201 CR4_READ_SHADOW = 0x6006ul, 202 CR3_TARGET_0 = 0x6008ul, 203 CR3_TARGET_1 = 0x600aul, 204 CR3_TARGET_2 = 0x600cul, 205 CR3_TARGET_3 = 0x600eul, 206 207 /* Natural-Width R/O Data Fields */ 208 EXI_QUALIFICATION = 0x6400ul, 209 IO_RCX = 0x6402ul, 210 IO_RSI = 0x6404ul, 211 IO_RDI = 0x6406ul, 212 IO_RIP = 0x6408ul, 213 GUEST_LINEAR_ADDRESS = 0x640aul, 214 215 /* Natural-Width Guest State Fields */ 216 GUEST_CR0 = 0x6800ul, 217 GUEST_CR3 = 0x6802ul, 218 GUEST_CR4 = 0x6804ul, 219 GUEST_BASE_ES = 0x6806ul, 220 GUEST_BASE_CS = 0x6808ul, 221 GUEST_BASE_SS = 0x680aul, 222 GUEST_BASE_DS = 0x680cul, 223 GUEST_BASE_FS = 0x680eul, 224 GUEST_BASE_GS = 0x6810ul, 225 GUEST_BASE_LDTR = 0x6812ul, 226 GUEST_BASE_TR = 0x6814ul, 227 GUEST_BASE_GDTR = 0x6816ul, 228 GUEST_BASE_IDTR = 0x6818ul, 229 GUEST_DR7 = 0x681aul, 230 GUEST_RSP = 0x681cul, 231 GUEST_RIP = 0x681eul, 232 GUEST_RFLAGS = 0x6820ul, 233 GUEST_PENDING_DEBUG = 0x6822ul, 234 GUEST_SYSENTER_ESP = 0x6824ul, 235 GUEST_SYSENTER_EIP = 0x6826ul, 236 237 /* Natural-Width Host State Fields */ 238 HOST_CR0 = 0x6c00ul, 239 HOST_CR3 = 0x6c02ul, 240 HOST_CR4 = 0x6c04ul, 241 HOST_BASE_FS = 0x6c06ul, 242 HOST_BASE_GS = 0x6c08ul, 243 HOST_BASE_TR = 0x6c0aul, 244 HOST_BASE_GDTR = 0x6c0cul, 245 HOST_BASE_IDTR = 0x6c0eul, 246 HOST_SYSENTER_ESP = 0x6c10ul, 247 HOST_SYSENTER_EIP = 0x6c12ul, 248 HOST_RSP = 0x6c14ul, 249 HOST_RIP = 0x6c16ul 250 }; 251 252 enum Reason { 253 VMX_EXC_NMI = 0, 254 VMX_EXTINT = 1, 255 VMX_TRIPLE_FAULT = 2, 256 VMX_INIT = 3, 257 VMX_SIPI = 4, 258 VMX_SMI_IO = 5, 259 VMX_SMI_OTHER = 6, 260 VMX_INTR_WINDOW = 7, 261 VMX_NMI_WINDOW = 8, 262 VMX_TASK_SWITCH = 9, 263 VMX_CPUID = 10, 264 VMX_GETSEC = 11, 265 VMX_HLT = 12, 266 VMX_INVD = 13, 267 VMX_INVLPG = 14, 268 VMX_RDPMC = 15, 269 VMX_RDTSC = 16, 270 VMX_RSM = 17, 271 VMX_VMCALL = 18, 272 VMX_VMCLEAR = 19, 273 VMX_VMLAUNCH = 20, 274 VMX_VMPTRLD = 21, 275 VMX_VMPTRST = 22, 276 VMX_VMREAD = 23, 277 VMX_VMRESUME = 24, 278 VMX_VMWRITE = 25, 279 VMX_VMXOFF = 26, 280 VMX_VMXON = 27, 281 VMX_CR = 28, 282 VMX_DR = 29, 283 VMX_IO = 30, 284 VMX_RDMSR = 31, 285 VMX_WRMSR = 32, 286 VMX_FAIL_STATE = 33, 287 VMX_FAIL_MSR = 34, 288 VMX_MWAIT = 36, 289 VMX_MTF = 37, 290 VMX_MONITOR = 39, 291 VMX_PAUSE = 40, 292 VMX_FAIL_MCHECK = 41, 293 VMX_TPR_THRESHOLD = 43, 294 VMX_APIC_ACCESS = 44, 295 VMX_GDTR_IDTR = 46, 296 VMX_LDTR_TR = 47, 297 VMX_EPT_VIOLATION = 48, 298 VMX_EPT_MISCONFIG = 49, 299 VMX_INVEPT = 50, 300 VMX_PREEMPT = 52, 301 VMX_INVVPID = 53, 302 VMX_WBINVD = 54, 303 VMX_XSETBV = 55 304 }; 305 306 enum Ctrl_exi { 307 EXI_SAVE_DBGCTLS = 1UL << 2, 308 EXI_HOST_64 = 1UL << 9, 309 EXI_LOAD_PERF = 1UL << 12, 310 EXI_INTA = 1UL << 15, 311 EXI_SAVE_PAT = 1UL << 18, 312 EXI_LOAD_PAT = 1UL << 19, 313 EXI_SAVE_EFER = 1UL << 20, 314 EXI_LOAD_EFER = 1UL << 21, 315 EXI_SAVE_PREEMPT = 1UL << 22, 316 }; 317 318 enum Ctrl_ent { 319 ENT_LOAD_DBGCTLS = 1UL << 2, 320 ENT_GUEST_64 = 1UL << 9, 321 ENT_LOAD_PAT = 1UL << 14, 322 ENT_LOAD_EFER = 1UL << 15, 323 }; 324 325 enum Ctrl_pin { 326 PIN_EXTINT = 1ul << 0, 327 PIN_NMI = 1ul << 3, 328 PIN_VIRT_NMI = 1ul << 5, 329 PIN_PREEMPT = 1ul << 6, 330 }; 331 332 enum Ctrl0 { 333 CPU_INTR_WINDOW = 1ul << 2, 334 CPU_HLT = 1ul << 7, 335 CPU_INVLPG = 1ul << 9, 336 CPU_MWAIT = 1ul << 10, 337 CPU_RDPMC = 1ul << 11, 338 CPU_RDTSC = 1ul << 12, 339 CPU_CR3_LOAD = 1ul << 15, 340 CPU_CR3_STORE = 1ul << 16, 341 CPU_CR8_LOAD = 1ul << 19, 342 CPU_CR8_STORE = 1ul << 20, 343 CPU_TPR_SHADOW = 1ul << 21, 344 CPU_NMI_WINDOW = 1ul << 22, 345 CPU_IO = 1ul << 24, 346 CPU_IO_BITMAP = 1ul << 25, 347 CPU_MSR_BITMAP = 1ul << 28, 348 CPU_MONITOR = 1ul << 29, 349 CPU_PAUSE = 1ul << 30, 350 CPU_SECONDARY = 1ul << 31, 351 }; 352 353 enum Ctrl1 { 354 CPU_EPT = 1ul << 1, 355 CPU_VPID = 1ul << 5, 356 CPU_URG = 1ul << 7, 357 CPU_WBINVD = 1ul << 6, 358 CPU_RDRAND = 1ul << 11, 359 }; 360 361 #define SAVE_GPR \ 362 "xchg %rax, regs\n\t" \ 363 "xchg %rbx, regs+0x8\n\t" \ 364 "xchg %rcx, regs+0x10\n\t" \ 365 "xchg %rdx, regs+0x18\n\t" \ 366 "xchg %rbp, regs+0x28\n\t" \ 367 "xchg %rsi, regs+0x30\n\t" \ 368 "xchg %rdi, regs+0x38\n\t" \ 369 "xchg %r8, regs+0x40\n\t" \ 370 "xchg %r9, regs+0x48\n\t" \ 371 "xchg %r10, regs+0x50\n\t" \ 372 "xchg %r11, regs+0x58\n\t" \ 373 "xchg %r12, regs+0x60\n\t" \ 374 "xchg %r13, regs+0x68\n\t" \ 375 "xchg %r14, regs+0x70\n\t" \ 376 "xchg %r15, regs+0x78\n\t" 377 378 #define LOAD_GPR SAVE_GPR 379 380 #define SAVE_GPR_C \ 381 "xchg %%rax, regs\n\t" \ 382 "xchg %%rbx, regs+0x8\n\t" \ 383 "xchg %%rcx, regs+0x10\n\t" \ 384 "xchg %%rdx, regs+0x18\n\t" \ 385 "xchg %%rbp, regs+0x28\n\t" \ 386 "xchg %%rsi, regs+0x30\n\t" \ 387 "xchg %%rdi, regs+0x38\n\t" \ 388 "xchg %%r8, regs+0x40\n\t" \ 389 "xchg %%r9, regs+0x48\n\t" \ 390 "xchg %%r10, regs+0x50\n\t" \ 391 "xchg %%r11, regs+0x58\n\t" \ 392 "xchg %%r12, regs+0x60\n\t" \ 393 "xchg %%r13, regs+0x68\n\t" \ 394 "xchg %%r14, regs+0x70\n\t" \ 395 "xchg %%r15, regs+0x78\n\t" 396 397 #define LOAD_GPR_C SAVE_GPR_C 398 399 #define SAVE_RFLAGS \ 400 "pushf\n\t" \ 401 "pop host_rflags\n\t" 402 403 #define LOAD_RFLAGS \ 404 "push host_rflags\n\t" \ 405 "popf\n\t" 406 407 #define VMX_IO_SIZE_MASK 0x7 408 #define _VMX_IO_BYTE 0 409 #define _VMX_IO_WORD 1 410 #define _VMX_IO_LONG 3 411 #define VMX_IO_DIRECTION_MASK (1ul << 3) 412 #define VMX_IO_IN (1ul << 3) 413 #define VMX_IO_OUT 0 414 #define VMX_IO_STRING (1ul << 4) 415 #define VMX_IO_REP (1ul << 5) 416 #define VMX_IO_OPRAND_IMM (1ul << 6) 417 #define VMX_IO_PORT_MASK 0xFFFF0000 418 #define VMX_IO_PORT_SHIFT 16 419 420 #define VMX_TEST_START 0 421 #define VMX_TEST_VMEXIT 1 422 #define VMX_TEST_EXIT 2 423 #define VMX_TEST_RESUME 3 424 #define VMX_TEST_LAUNCH_ERR 4 425 #define VMX_TEST_RESUME_ERR 5 426 427 #define HYPERCALL_BIT (1ul << 12) 428 #define HYPERCALL_MASK 0xFFF 429 #define HYPERCALL_VMEXIT 0x1 430 431 #define EPTP_PG_WALK_LEN_SHIFT 3ul 432 #define EPTP_AD_FLAG (1ul << 6) 433 434 #define EPT_MEM_TYPE_UC 0ul 435 #define EPT_MEM_TYPE_WC 1ul 436 #define EPT_MEM_TYPE_WT 4ul 437 #define EPT_MEM_TYPE_WP 5ul 438 #define EPT_MEM_TYPE_WB 6ul 439 440 #define EPT_RA 1ul 441 #define EPT_WA 2ul 442 #define EPT_EA 4ul 443 #define EPT_PRESENT (EPT_RA | EPT_WA | EPT_EA) 444 #define EPT_ACCESS_FLAG (1ul << 8) 445 #define EPT_DIRTY_FLAG (1ul << 9) 446 #define EPT_LARGE_PAGE (1ul << 7) 447 #define EPT_MEM_TYPE_SHIFT 3ul 448 #define EPT_IGNORE_PAT (1ul << 6) 449 #define EPT_SUPPRESS_VE (1ull << 63) 450 451 #define EPT_CAP_WT 1ull 452 #define EPT_CAP_PWL4 (1ull << 6) 453 #define EPT_CAP_UC (1ull << 8) 454 #define EPT_CAP_WB (1ull << 14) 455 #define EPT_CAP_2M_PAGE (1ull << 16) 456 #define EPT_CAP_1G_PAGE (1ull << 17) 457 #define EPT_CAP_INVEPT (1ull << 20) 458 #define EPT_CAP_INVEPT_SINGLE (1ull << 25) 459 #define EPT_CAP_INVEPT_ALL (1ull << 26) 460 #define EPT_CAP_AD_FLAG (1ull << 21) 461 #define VPID_CAP_INVVPID (1ull << 32) 462 #define VPID_CAP_INVVPID_SINGLE (1ull << 41) 463 #define VPID_CAP_INVVPID_ALL (1ull << 42) 464 465 #define PAGE_SIZE_2M (512 * PAGE_SIZE) 466 #define PAGE_SIZE_1G (512 * PAGE_SIZE_2M) 467 #define EPT_PAGE_LEVEL 4 468 #define EPT_PGDIR_WIDTH 9 469 #define EPT_PGDIR_MASK 511 470 #define EPT_PGDIR_ENTRIES (1 << EPT_PGDIR_WIDTH) 471 #define EPT_LEVEL_SHIFT(level) (((level)-1) * EPT_PGDIR_WIDTH + 12) 472 #define EPT_ADDR_MASK GENMASK_ULL(51, 12) 473 #define PAGE_MASK (~(PAGE_SIZE-1)) 474 #define PAGE_MASK_2M (~(PAGE_SIZE_2M-1)) 475 476 #define EPT_VLT_RD 1 477 #define EPT_VLT_WR (1 << 1) 478 #define EPT_VLT_FETCH (1 << 2) 479 #define EPT_VLT_PERM_RD (1 << 3) 480 #define EPT_VLT_PERM_WR (1 << 4) 481 #define EPT_VLT_PERM_EX (1 << 5) 482 #define EPT_VLT_LADDR_VLD (1 << 7) 483 #define EPT_VLT_PADDR (1 << 8) 484 485 #define MAGIC_VAL_1 0x12345678ul 486 #define MAGIC_VAL_2 0x87654321ul 487 #define MAGIC_VAL_3 0xfffffffful 488 489 #define INVEPT_SINGLE 1 490 #define INVEPT_GLOBAL 2 491 492 #define INVVPID_SINGLE 1 493 #define INVVPID_ALL 2 494 495 #define ACTV_ACTIVE 0 496 #define ACTV_HLT 1 497 498 extern struct regs regs; 499 500 extern union vmx_basic basic; 501 extern union vmx_ctrl_msr ctrl_pin_rev; 502 extern union vmx_ctrl_msr ctrl_cpu_rev[2]; 503 extern union vmx_ctrl_msr ctrl_exit_rev; 504 extern union vmx_ctrl_msr ctrl_enter_rev; 505 extern union vmx_ept_vpid ept_vpid; 506 507 void vmx_set_test_stage(u32 s); 508 u32 vmx_get_test_stage(void); 509 void vmx_inc_test_stage(void); 510 511 static inline int vmcs_clear(struct vmcs *vmcs) 512 { 513 bool ret; 514 u64 rflags = read_rflags() | X86_EFLAGS_CF | X86_EFLAGS_ZF; 515 516 asm volatile ("push %1; popf; vmclear %2; setbe %0" 517 : "=q" (ret) : "q" (rflags), "m" (vmcs) : "cc"); 518 return ret; 519 } 520 521 static inline u64 vmcs_read(enum Encoding enc) 522 { 523 u64 val; 524 asm volatile ("vmread %1, %0" : "=rm" (val) : "r" ((u64)enc) : "cc"); 525 return val; 526 } 527 528 static inline int vmcs_write(enum Encoding enc, u64 val) 529 { 530 bool ret; 531 asm volatile ("vmwrite %1, %2; setbe %0" 532 : "=q"(ret) : "rm" (val), "r" ((u64)enc) : "cc"); 533 return ret; 534 } 535 536 static inline int vmcs_save(struct vmcs **vmcs) 537 { 538 bool ret; 539 u64 rflags = read_rflags() | X86_EFLAGS_CF | X86_EFLAGS_ZF; 540 541 asm volatile ("push %1; popf; vmptrst %2; setbe %0" 542 : "=q" (ret) : "q" (rflags), "m" (*vmcs) : "cc"); 543 return ret; 544 } 545 546 static inline void invept(unsigned long type, u64 eptp) 547 { 548 struct { 549 u64 eptp, gpa; 550 } operand = {eptp, 0}; 551 asm volatile("invept %0, %1\n" ::"m"(operand),"r"(type)); 552 } 553 554 static inline void invvpid(unsigned long type, u16 vpid, u64 gva) 555 { 556 struct { 557 u64 vpid : 16; 558 u64 rsvd : 48; 559 u64 gva; 560 } operand = {vpid, 0, gva}; 561 asm volatile("invvpid %0, %1\n" ::"m"(operand),"r"(type)); 562 } 563 564 void print_vmexit_info(); 565 void ept_sync(int type, u64 eptp); 566 void vpid_sync(int type, u16 vpid); 567 void install_ept_entry(unsigned long *pml4, int pte_level, 568 unsigned long guest_addr, unsigned long pte, 569 unsigned long *pt_page); 570 void install_1g_ept(unsigned long *pml4, unsigned long phys, 571 unsigned long guest_addr, u64 perm); 572 void install_2m_ept(unsigned long *pml4, unsigned long phys, 573 unsigned long guest_addr, u64 perm); 574 void install_ept(unsigned long *pml4, unsigned long phys, 575 unsigned long guest_addr, u64 perm); 576 void setup_ept_range(unsigned long *pml4, unsigned long start, 577 unsigned long len, int map_1g, int map_2m, u64 perm); 578 unsigned long get_ept_pte(unsigned long *pml4, 579 unsigned long guest_addr, int level); 580 int set_ept_pte(unsigned long *pml4, unsigned long guest_addr, 581 int level, u64 pte_val); 582 583 #endif 584