1 #ifndef __VMX_H 2 #define __VMX_H 3 4 #include "libcflat.h" 5 #include "processor.h" 6 #include "bitops.h" 7 #include "asm/page.h" 8 9 struct vmcs { 10 u32 revision_id; /* vmcs revision identifier */ 11 u32 abort; /* VMX-abort indicator */ 12 /* VMCS data */ 13 char data[0]; 14 }; 15 16 struct regs { 17 u64 rax; 18 u64 rcx; 19 u64 rdx; 20 u64 rbx; 21 u64 cr2; 22 u64 rbp; 23 u64 rsi; 24 u64 rdi; 25 u64 r8; 26 u64 r9; 27 u64 r10; 28 u64 r11; 29 u64 r12; 30 u64 r13; 31 u64 r14; 32 u64 r15; 33 u64 rflags; 34 }; 35 36 struct vmentry_failure { 37 /* Did a vmlaunch or vmresume fail? */ 38 bool vmlaunch; 39 /* Instruction mnemonic (for convenience). */ 40 const char *instr; 41 /* Did the instruction return right away, or did we jump to HOST_RIP? */ 42 bool early; 43 /* Contents of [re]flags after failed entry. */ 44 unsigned long flags; 45 }; 46 47 struct vmx_test { 48 const char *name; 49 int (*init)(struct vmcs *vmcs); 50 void (*guest_main)(); 51 int (*exit_handler)(); 52 void (*syscall_handler)(u64 syscall_no); 53 struct regs guest_regs; 54 int (*entry_failure_handler)(struct vmentry_failure *failure); 55 struct vmcs *vmcs; 56 int exits; 57 /* Alternative test interface. */ 58 void (*v2)(void); 59 }; 60 61 union vmx_basic { 62 u64 val; 63 struct { 64 u32 revision; 65 u32 size:13, 66 reserved1: 3, 67 width:1, 68 dual:1, 69 type:4, 70 insouts:1, 71 ctrl:1, 72 reserved2:8; 73 }; 74 }; 75 76 union vmx_ctrl_msr { 77 u64 val; 78 struct { 79 u32 set, clr; 80 }; 81 }; 82 83 union vmx_ept_vpid { 84 u64 val; 85 struct { 86 u32:16, 87 super:2, 88 : 2, 89 invept:1, 90 : 11; 91 u32 invvpid:1; 92 }; 93 }; 94 95 enum Encoding { 96 /* 16-Bit Control Fields */ 97 VPID = 0x0000ul, 98 /* Posted-interrupt notification vector */ 99 PINV = 0x0002ul, 100 /* EPTP index */ 101 EPTP_IDX = 0x0004ul, 102 103 /* 16-Bit Guest State Fields */ 104 GUEST_SEL_ES = 0x0800ul, 105 GUEST_SEL_CS = 0x0802ul, 106 GUEST_SEL_SS = 0x0804ul, 107 GUEST_SEL_DS = 0x0806ul, 108 GUEST_SEL_FS = 0x0808ul, 109 GUEST_SEL_GS = 0x080aul, 110 GUEST_SEL_LDTR = 0x080cul, 111 GUEST_SEL_TR = 0x080eul, 112 GUEST_INT_STATUS = 0x0810ul, 113 114 /* 16-Bit Host State Fields */ 115 HOST_SEL_ES = 0x0c00ul, 116 HOST_SEL_CS = 0x0c02ul, 117 HOST_SEL_SS = 0x0c04ul, 118 HOST_SEL_DS = 0x0c06ul, 119 HOST_SEL_FS = 0x0c08ul, 120 HOST_SEL_GS = 0x0c0aul, 121 HOST_SEL_TR = 0x0c0cul, 122 123 /* 64-Bit Control Fields */ 124 IO_BITMAP_A = 0x2000ul, 125 IO_BITMAP_B = 0x2002ul, 126 MSR_BITMAP = 0x2004ul, 127 EXIT_MSR_ST_ADDR = 0x2006ul, 128 EXIT_MSR_LD_ADDR = 0x2008ul, 129 ENTER_MSR_LD_ADDR = 0x200aul, 130 VMCS_EXEC_PTR = 0x200cul, 131 TSC_OFFSET = 0x2010ul, 132 TSC_OFFSET_HI = 0x2011ul, 133 APIC_VIRT_ADDR = 0x2012ul, 134 APIC_ACCS_ADDR = 0x2014ul, 135 EPTP = 0x201aul, 136 EPTP_HI = 0x201bul, 137 138 /* 64-Bit Readonly Data Field */ 139 INFO_PHYS_ADDR = 0x2400ul, 140 141 /* 64-Bit Guest State */ 142 VMCS_LINK_PTR = 0x2800ul, 143 VMCS_LINK_PTR_HI = 0x2801ul, 144 GUEST_DEBUGCTL = 0x2802ul, 145 GUEST_DEBUGCTL_HI = 0x2803ul, 146 GUEST_EFER = 0x2806ul, 147 GUEST_PAT = 0x2804ul, 148 GUEST_PERF_GLOBAL_CTRL = 0x2808ul, 149 GUEST_PDPTE = 0x280aul, 150 151 /* 64-Bit Host State */ 152 HOST_PAT = 0x2c00ul, 153 HOST_EFER = 0x2c02ul, 154 HOST_PERF_GLOBAL_CTRL = 0x2c04ul, 155 156 /* 32-Bit Control Fields */ 157 PIN_CONTROLS = 0x4000ul, 158 CPU_EXEC_CTRL0 = 0x4002ul, 159 EXC_BITMAP = 0x4004ul, 160 PF_ERROR_MASK = 0x4006ul, 161 PF_ERROR_MATCH = 0x4008ul, 162 CR3_TARGET_COUNT = 0x400aul, 163 EXI_CONTROLS = 0x400cul, 164 EXI_MSR_ST_CNT = 0x400eul, 165 EXI_MSR_LD_CNT = 0x4010ul, 166 ENT_CONTROLS = 0x4012ul, 167 ENT_MSR_LD_CNT = 0x4014ul, 168 ENT_INTR_INFO = 0x4016ul, 169 ENT_INTR_ERROR = 0x4018ul, 170 ENT_INST_LEN = 0x401aul, 171 TPR_THRESHOLD = 0x401cul, 172 CPU_EXEC_CTRL1 = 0x401eul, 173 174 /* 32-Bit R/O Data Fields */ 175 VMX_INST_ERROR = 0x4400ul, 176 EXI_REASON = 0x4402ul, 177 EXI_INTR_INFO = 0x4404ul, 178 EXI_INTR_ERROR = 0x4406ul, 179 IDT_VECT_INFO = 0x4408ul, 180 IDT_VECT_ERROR = 0x440aul, 181 EXI_INST_LEN = 0x440cul, 182 EXI_INST_INFO = 0x440eul, 183 184 /* 32-Bit Guest State Fields */ 185 GUEST_LIMIT_ES = 0x4800ul, 186 GUEST_LIMIT_CS = 0x4802ul, 187 GUEST_LIMIT_SS = 0x4804ul, 188 GUEST_LIMIT_DS = 0x4806ul, 189 GUEST_LIMIT_FS = 0x4808ul, 190 GUEST_LIMIT_GS = 0x480aul, 191 GUEST_LIMIT_LDTR = 0x480cul, 192 GUEST_LIMIT_TR = 0x480eul, 193 GUEST_LIMIT_GDTR = 0x4810ul, 194 GUEST_LIMIT_IDTR = 0x4812ul, 195 GUEST_AR_ES = 0x4814ul, 196 GUEST_AR_CS = 0x4816ul, 197 GUEST_AR_SS = 0x4818ul, 198 GUEST_AR_DS = 0x481aul, 199 GUEST_AR_FS = 0x481cul, 200 GUEST_AR_GS = 0x481eul, 201 GUEST_AR_LDTR = 0x4820ul, 202 GUEST_AR_TR = 0x4822ul, 203 GUEST_INTR_STATE = 0x4824ul, 204 GUEST_ACTV_STATE = 0x4826ul, 205 GUEST_SMBASE = 0x4828ul, 206 GUEST_SYSENTER_CS = 0x482aul, 207 PREEMPT_TIMER_VALUE = 0x482eul, 208 209 /* 32-Bit Host State Fields */ 210 HOST_SYSENTER_CS = 0x4c00ul, 211 212 /* Natural-Width Control Fields */ 213 CR0_MASK = 0x6000ul, 214 CR4_MASK = 0x6002ul, 215 CR0_READ_SHADOW = 0x6004ul, 216 CR4_READ_SHADOW = 0x6006ul, 217 CR3_TARGET_0 = 0x6008ul, 218 CR3_TARGET_1 = 0x600aul, 219 CR3_TARGET_2 = 0x600cul, 220 CR3_TARGET_3 = 0x600eul, 221 222 /* Natural-Width R/O Data Fields */ 223 EXI_QUALIFICATION = 0x6400ul, 224 IO_RCX = 0x6402ul, 225 IO_RSI = 0x6404ul, 226 IO_RDI = 0x6406ul, 227 IO_RIP = 0x6408ul, 228 GUEST_LINEAR_ADDRESS = 0x640aul, 229 230 /* Natural-Width Guest State Fields */ 231 GUEST_CR0 = 0x6800ul, 232 GUEST_CR3 = 0x6802ul, 233 GUEST_CR4 = 0x6804ul, 234 GUEST_BASE_ES = 0x6806ul, 235 GUEST_BASE_CS = 0x6808ul, 236 GUEST_BASE_SS = 0x680aul, 237 GUEST_BASE_DS = 0x680cul, 238 GUEST_BASE_FS = 0x680eul, 239 GUEST_BASE_GS = 0x6810ul, 240 GUEST_BASE_LDTR = 0x6812ul, 241 GUEST_BASE_TR = 0x6814ul, 242 GUEST_BASE_GDTR = 0x6816ul, 243 GUEST_BASE_IDTR = 0x6818ul, 244 GUEST_DR7 = 0x681aul, 245 GUEST_RSP = 0x681cul, 246 GUEST_RIP = 0x681eul, 247 GUEST_RFLAGS = 0x6820ul, 248 GUEST_PENDING_DEBUG = 0x6822ul, 249 GUEST_SYSENTER_ESP = 0x6824ul, 250 GUEST_SYSENTER_EIP = 0x6826ul, 251 252 /* Natural-Width Host State Fields */ 253 HOST_CR0 = 0x6c00ul, 254 HOST_CR3 = 0x6c02ul, 255 HOST_CR4 = 0x6c04ul, 256 HOST_BASE_FS = 0x6c06ul, 257 HOST_BASE_GS = 0x6c08ul, 258 HOST_BASE_TR = 0x6c0aul, 259 HOST_BASE_GDTR = 0x6c0cul, 260 HOST_BASE_IDTR = 0x6c0eul, 261 HOST_SYSENTER_ESP = 0x6c10ul, 262 HOST_SYSENTER_EIP = 0x6c12ul, 263 HOST_RSP = 0x6c14ul, 264 HOST_RIP = 0x6c16ul 265 }; 266 267 #define VMX_ENTRY_FAILURE (1ul << 31) 268 #define VMX_ENTRY_FLAGS (X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | \ 269 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF) 270 271 enum Reason { 272 VMX_EXC_NMI = 0, 273 VMX_EXTINT = 1, 274 VMX_TRIPLE_FAULT = 2, 275 VMX_INIT = 3, 276 VMX_SIPI = 4, 277 VMX_SMI_IO = 5, 278 VMX_SMI_OTHER = 6, 279 VMX_INTR_WINDOW = 7, 280 VMX_NMI_WINDOW = 8, 281 VMX_TASK_SWITCH = 9, 282 VMX_CPUID = 10, 283 VMX_GETSEC = 11, 284 VMX_HLT = 12, 285 VMX_INVD = 13, 286 VMX_INVLPG = 14, 287 VMX_RDPMC = 15, 288 VMX_RDTSC = 16, 289 VMX_RSM = 17, 290 VMX_VMCALL = 18, 291 VMX_VMCLEAR = 19, 292 VMX_VMLAUNCH = 20, 293 VMX_VMPTRLD = 21, 294 VMX_VMPTRST = 22, 295 VMX_VMREAD = 23, 296 VMX_VMRESUME = 24, 297 VMX_VMWRITE = 25, 298 VMX_VMXOFF = 26, 299 VMX_VMXON = 27, 300 VMX_CR = 28, 301 VMX_DR = 29, 302 VMX_IO = 30, 303 VMX_RDMSR = 31, 304 VMX_WRMSR = 32, 305 VMX_FAIL_STATE = 33, 306 VMX_FAIL_MSR = 34, 307 VMX_MWAIT = 36, 308 VMX_MTF = 37, 309 VMX_MONITOR = 39, 310 VMX_PAUSE = 40, 311 VMX_FAIL_MCHECK = 41, 312 VMX_TPR_THRESHOLD = 43, 313 VMX_APIC_ACCESS = 44, 314 VMX_GDTR_IDTR = 46, 315 VMX_LDTR_TR = 47, 316 VMX_EPT_VIOLATION = 48, 317 VMX_EPT_MISCONFIG = 49, 318 VMX_INVEPT = 50, 319 VMX_PREEMPT = 52, 320 VMX_INVVPID = 53, 321 VMX_WBINVD = 54, 322 VMX_XSETBV = 55, 323 VMX_APIC_WRITE = 56, 324 VMX_RDRAND = 57, 325 VMX_INVPCID = 58, 326 VMX_VMFUNC = 59, 327 VMX_RDSEED = 61, 328 VMX_PML_FULL = 62, 329 VMX_XSAVES = 63, 330 VMX_XRSTORS = 64, 331 }; 332 333 enum Ctrl_exi { 334 EXI_SAVE_DBGCTLS = 1UL << 2, 335 EXI_HOST_64 = 1UL << 9, 336 EXI_LOAD_PERF = 1UL << 12, 337 EXI_INTA = 1UL << 15, 338 EXI_SAVE_PAT = 1UL << 18, 339 EXI_LOAD_PAT = 1UL << 19, 340 EXI_SAVE_EFER = 1UL << 20, 341 EXI_LOAD_EFER = 1UL << 21, 342 EXI_SAVE_PREEMPT = 1UL << 22, 343 }; 344 345 enum Ctrl_ent { 346 ENT_LOAD_DBGCTLS = 1UL << 2, 347 ENT_GUEST_64 = 1UL << 9, 348 ENT_LOAD_PAT = 1UL << 14, 349 ENT_LOAD_EFER = 1UL << 15, 350 }; 351 352 enum Ctrl_pin { 353 PIN_EXTINT = 1ul << 0, 354 PIN_NMI = 1ul << 3, 355 PIN_VIRT_NMI = 1ul << 5, 356 PIN_PREEMPT = 1ul << 6, 357 }; 358 359 enum Ctrl0 { 360 CPU_INTR_WINDOW = 1ul << 2, 361 CPU_HLT = 1ul << 7, 362 CPU_INVLPG = 1ul << 9, 363 CPU_MWAIT = 1ul << 10, 364 CPU_RDPMC = 1ul << 11, 365 CPU_RDTSC = 1ul << 12, 366 CPU_CR3_LOAD = 1ul << 15, 367 CPU_CR3_STORE = 1ul << 16, 368 CPU_CR8_LOAD = 1ul << 19, 369 CPU_CR8_STORE = 1ul << 20, 370 CPU_TPR_SHADOW = 1ul << 21, 371 CPU_NMI_WINDOW = 1ul << 22, 372 CPU_IO = 1ul << 24, 373 CPU_IO_BITMAP = 1ul << 25, 374 CPU_MSR_BITMAP = 1ul << 28, 375 CPU_MONITOR = 1ul << 29, 376 CPU_PAUSE = 1ul << 30, 377 CPU_SECONDARY = 1ul << 31, 378 }; 379 380 enum Ctrl1 { 381 CPU_EPT = 1ul << 1, 382 CPU_DESC_TABLE = 1ul << 2, 383 CPU_RDTSCP = 1ul << 3, 384 CPU_VPID = 1ul << 5, 385 CPU_URG = 1ul << 7, 386 CPU_WBINVD = 1ul << 6, 387 CPU_RDRAND = 1ul << 11, 388 }; 389 390 enum Intr_type { 391 VMX_INTR_TYPE_EXT_INTR = 0, 392 VMX_INTR_TYPE_NMI_INTR = 2, 393 VMX_INTR_TYPE_HARD_EXCEPTION = 3, 394 VMX_INTR_TYPE_SOFT_INTR = 4, 395 VMX_INTR_TYPE_SOFT_EXCEPTION = 6, 396 }; 397 398 /* 399 * Interruption-information format 400 */ 401 #define INTR_INFO_VECTOR_MASK 0xff /* 7:0 */ 402 #define INTR_INFO_INTR_TYPE_MASK 0x700 /* 10:8 */ 403 #define INTR_INFO_DELIVER_CODE_MASK 0x800 /* 11 */ 404 #define INTR_INFO_UNBLOCK_NMI_MASK 0x1000 /* 12 */ 405 #define INTR_INFO_VALID_MASK 0x80000000 /* 31 */ 406 407 #define INTR_INFO_INTR_TYPE_SHIFT 8 408 409 /* 410 * VM-instruction error numbers 411 */ 412 enum vm_instruction_error_number { 413 VMXERR_VMCALL_IN_VMX_ROOT_OPERATION = 1, 414 VMXERR_VMCLEAR_INVALID_ADDRESS = 2, 415 VMXERR_VMCLEAR_VMXON_POINTER = 3, 416 VMXERR_VMLAUNCH_NONCLEAR_VMCS = 4, 417 VMXERR_VMRESUME_NONLAUNCHED_VMCS = 5, 418 VMXERR_VMRESUME_AFTER_VMXOFF = 6, 419 VMXERR_ENTRY_INVALID_CONTROL_FIELD = 7, 420 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD = 8, 421 VMXERR_VMPTRLD_INVALID_ADDRESS = 9, 422 VMXERR_VMPTRLD_VMXON_POINTER = 10, 423 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID = 11, 424 VMXERR_UNSUPPORTED_VMCS_COMPONENT = 12, 425 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT = 13, 426 VMXERR_VMXON_IN_VMX_ROOT_OPERATION = 15, 427 VMXERR_ENTRY_INVALID_EXECUTIVE_VMCS_POINTER = 16, 428 VMXERR_ENTRY_NONLAUNCHED_EXECUTIVE_VMCS = 17, 429 VMXERR_ENTRY_EXECUTIVE_VMCS_POINTER_NOT_VMXON_POINTER = 18, 430 VMXERR_VMCALL_NONCLEAR_VMCS = 19, 431 VMXERR_VMCALL_INVALID_VM_EXIT_CONTROL_FIELDS = 20, 432 VMXERR_VMCALL_INCORRECT_MSEG_REVISION_ID = 22, 433 VMXERR_VMXOFF_UNDER_DUAL_MONITOR_TREATMENT_OF_SMIS_AND_SMM = 23, 434 VMXERR_VMCALL_INVALID_SMM_MONITOR_FEATURES = 24, 435 VMXERR_ENTRY_INVALID_VM_EXECUTION_CONTROL_FIELDS_IN_EXECUTIVE_VMCS = 25, 436 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS = 26, 437 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID = 28, 438 }; 439 440 #define SAVE_GPR \ 441 "xchg %rax, regs\n\t" \ 442 "xchg %rbx, regs+0x8\n\t" \ 443 "xchg %rcx, regs+0x10\n\t" \ 444 "xchg %rdx, regs+0x18\n\t" \ 445 "xchg %rbp, regs+0x28\n\t" \ 446 "xchg %rsi, regs+0x30\n\t" \ 447 "xchg %rdi, regs+0x38\n\t" \ 448 "xchg %r8, regs+0x40\n\t" \ 449 "xchg %r9, regs+0x48\n\t" \ 450 "xchg %r10, regs+0x50\n\t" \ 451 "xchg %r11, regs+0x58\n\t" \ 452 "xchg %r12, regs+0x60\n\t" \ 453 "xchg %r13, regs+0x68\n\t" \ 454 "xchg %r14, regs+0x70\n\t" \ 455 "xchg %r15, regs+0x78\n\t" 456 457 #define LOAD_GPR SAVE_GPR 458 459 #define SAVE_GPR_C \ 460 "xchg %%rax, regs\n\t" \ 461 "xchg %%rbx, regs+0x8\n\t" \ 462 "xchg %%rcx, regs+0x10\n\t" \ 463 "xchg %%rdx, regs+0x18\n\t" \ 464 "xchg %%rbp, regs+0x28\n\t" \ 465 "xchg %%rsi, regs+0x30\n\t" \ 466 "xchg %%rdi, regs+0x38\n\t" \ 467 "xchg %%r8, regs+0x40\n\t" \ 468 "xchg %%r9, regs+0x48\n\t" \ 469 "xchg %%r10, regs+0x50\n\t" \ 470 "xchg %%r11, regs+0x58\n\t" \ 471 "xchg %%r12, regs+0x60\n\t" \ 472 "xchg %%r13, regs+0x68\n\t" \ 473 "xchg %%r14, regs+0x70\n\t" \ 474 "xchg %%r15, regs+0x78\n\t" 475 476 #define LOAD_GPR_C SAVE_GPR_C 477 478 #define VMX_IO_SIZE_MASK 0x7 479 #define _VMX_IO_BYTE 0 480 #define _VMX_IO_WORD 1 481 #define _VMX_IO_LONG 3 482 #define VMX_IO_DIRECTION_MASK (1ul << 3) 483 #define VMX_IO_IN (1ul << 3) 484 #define VMX_IO_OUT 0 485 #define VMX_IO_STRING (1ul << 4) 486 #define VMX_IO_REP (1ul << 5) 487 #define VMX_IO_OPRAND_IMM (1ul << 6) 488 #define VMX_IO_PORT_MASK 0xFFFF0000 489 #define VMX_IO_PORT_SHIFT 16 490 491 #define VMX_TEST_START 0 492 #define VMX_TEST_VMEXIT 1 493 #define VMX_TEST_EXIT 2 494 #define VMX_TEST_RESUME 3 495 #define VMX_TEST_VMABORT 4 496 #define VMX_TEST_VMSKIP 5 497 498 #define HYPERCALL_BIT (1ul << 12) 499 #define HYPERCALL_MASK 0xFFF 500 #define HYPERCALL_VMEXIT 0x1 501 #define HYPERCALL_VMABORT 0x2 502 #define HYPERCALL_VMSKIP 0x3 503 504 #define EPTP_PG_WALK_LEN_SHIFT 3ul 505 #define EPTP_AD_FLAG (1ul << 6) 506 507 #define EPT_MEM_TYPE_UC 0ul 508 #define EPT_MEM_TYPE_WC 1ul 509 #define EPT_MEM_TYPE_WT 4ul 510 #define EPT_MEM_TYPE_WP 5ul 511 #define EPT_MEM_TYPE_WB 6ul 512 513 #define EPT_RA 1ul 514 #define EPT_WA 2ul 515 #define EPT_EA 4ul 516 #define EPT_PRESENT (EPT_RA | EPT_WA | EPT_EA) 517 #define EPT_ACCESS_FLAG (1ul << 8) 518 #define EPT_DIRTY_FLAG (1ul << 9) 519 #define EPT_LARGE_PAGE (1ul << 7) 520 #define EPT_MEM_TYPE_SHIFT 3ul 521 #define EPT_IGNORE_PAT (1ul << 6) 522 #define EPT_SUPPRESS_VE (1ull << 63) 523 524 #define EPT_CAP_WT 1ull 525 #define EPT_CAP_PWL4 (1ull << 6) 526 #define EPT_CAP_UC (1ull << 8) 527 #define EPT_CAP_WB (1ull << 14) 528 #define EPT_CAP_2M_PAGE (1ull << 16) 529 #define EPT_CAP_1G_PAGE (1ull << 17) 530 #define EPT_CAP_INVEPT (1ull << 20) 531 #define EPT_CAP_INVEPT_SINGLE (1ull << 25) 532 #define EPT_CAP_INVEPT_ALL (1ull << 26) 533 #define EPT_CAP_AD_FLAG (1ull << 21) 534 #define VPID_CAP_INVVPID (1ull << 32) 535 #define VPID_CAP_INVVPID_SINGLE (1ull << 41) 536 #define VPID_CAP_INVVPID_ALL (1ull << 42) 537 538 #define PAGE_SIZE_2M (512 * PAGE_SIZE) 539 #define PAGE_SIZE_1G (512 * PAGE_SIZE_2M) 540 #define EPT_PAGE_LEVEL 4 541 #define EPT_PGDIR_WIDTH 9 542 #define EPT_PGDIR_MASK 511 543 #define EPT_PGDIR_ENTRIES (1 << EPT_PGDIR_WIDTH) 544 #define EPT_LEVEL_SHIFT(level) (((level)-1) * EPT_PGDIR_WIDTH + 12) 545 #define EPT_ADDR_MASK GENMASK_ULL(51, 12) 546 #define PAGE_MASK_2M (~(PAGE_SIZE_2M-1)) 547 548 #define EPT_VLT_RD 1 549 #define EPT_VLT_WR (1 << 1) 550 #define EPT_VLT_FETCH (1 << 2) 551 #define EPT_VLT_PERM_RD (1 << 3) 552 #define EPT_VLT_PERM_WR (1 << 4) 553 #define EPT_VLT_PERM_EX (1 << 5) 554 #define EPT_VLT_LADDR_VLD (1 << 7) 555 #define EPT_VLT_PADDR (1 << 8) 556 557 #define MAGIC_VAL_1 0x12345678ul 558 #define MAGIC_VAL_2 0x87654321ul 559 #define MAGIC_VAL_3 0xfffffffful 560 561 #define INVEPT_SINGLE 1 562 #define INVEPT_GLOBAL 2 563 564 #define INVVPID_SINGLE_ADDRESS 0 565 #define INVVPID_SINGLE 1 566 #define INVVPID_ALL 2 567 568 #define ACTV_ACTIVE 0 569 #define ACTV_HLT 1 570 571 extern struct regs regs; 572 573 extern union vmx_basic basic; 574 extern union vmx_ctrl_msr ctrl_pin_rev; 575 extern union vmx_ctrl_msr ctrl_cpu_rev[2]; 576 extern union vmx_ctrl_msr ctrl_exit_rev; 577 extern union vmx_ctrl_msr ctrl_enter_rev; 578 extern union vmx_ept_vpid ept_vpid; 579 580 void vmx_set_test_stage(u32 s); 581 u32 vmx_get_test_stage(void); 582 void vmx_inc_test_stage(void); 583 584 static inline int make_vmcs_current(struct vmcs *vmcs) 585 { 586 bool ret; 587 u64 rflags = read_rflags() | X86_EFLAGS_CF | X86_EFLAGS_ZF; 588 589 asm volatile ("push %1; popf; vmptrld %2; setbe %0" 590 : "=q" (ret) : "q" (rflags), "m" (vmcs) : "cc"); 591 return ret; 592 } 593 594 static inline int vmcs_clear(struct vmcs *vmcs) 595 { 596 bool ret; 597 u64 rflags = read_rflags() | X86_EFLAGS_CF | X86_EFLAGS_ZF; 598 599 asm volatile ("push %1; popf; vmclear %2; setbe %0" 600 : "=q" (ret) : "q" (rflags), "m" (vmcs) : "cc"); 601 return ret; 602 } 603 604 static inline u64 vmcs_read(enum Encoding enc) 605 { 606 u64 val; 607 asm volatile ("vmread %1, %0" : "=rm" (val) : "r" ((u64)enc) : "cc"); 608 return val; 609 } 610 611 static inline int vmcs_read_checking(enum Encoding enc, u64 *value) 612 { 613 u64 rflags = read_rflags() | X86_EFLAGS_CF | X86_EFLAGS_ZF; 614 u64 encoding = enc; 615 u64 val; 616 617 asm volatile ("shl $8, %%rax;" 618 "sahf;" 619 "vmread %[encoding], %[val];" 620 "lahf;" 621 "shr $8, %%rax" 622 : /* output */ [val]"=rm"(val), "+a"(rflags) 623 : /* input */ [encoding]"r"(encoding) 624 : /* clobber */ "cc"); 625 626 *value = val; 627 return rflags & (X86_EFLAGS_CF | X86_EFLAGS_ZF); 628 } 629 630 static inline int vmcs_write(enum Encoding enc, u64 val) 631 { 632 bool ret; 633 asm volatile ("vmwrite %1, %2; setbe %0" 634 : "=q"(ret) : "rm" (val), "r" ((u64)enc) : "cc"); 635 return ret; 636 } 637 638 static inline int vmcs_save(struct vmcs **vmcs) 639 { 640 bool ret; 641 u64 rflags = read_rflags() | X86_EFLAGS_CF | X86_EFLAGS_ZF; 642 643 asm volatile ("push %1; popf; vmptrst %2; setbe %0" 644 : "=q" (ret) : "q" (rflags), "m" (*vmcs) : "cc"); 645 return ret; 646 } 647 648 static inline bool invept(unsigned long type, u64 eptp) 649 { 650 bool ret; 651 u64 rflags = read_rflags() | X86_EFLAGS_CF | X86_EFLAGS_ZF; 652 653 struct { 654 u64 eptp, gpa; 655 } operand = {eptp, 0}; 656 asm volatile("push %1; popf; invept %2, %3; setbe %0" 657 : "=q" (ret) : "r" (rflags), "m"(operand),"r"(type) : "cc"); 658 return ret; 659 } 660 661 static inline bool invvpid(unsigned long type, u16 vpid, u64 gva) 662 { 663 bool ret; 664 u64 rflags = read_rflags() | X86_EFLAGS_CF | X86_EFLAGS_ZF; 665 666 struct { 667 u64 vpid : 16; 668 u64 rsvd : 48; 669 u64 gva; 670 } operand = {vpid, 0, gva}; 671 asm volatile("push %1; popf; invvpid %2, %3; setbe %0" 672 : "=q" (ret) : "r" (rflags), "m"(operand),"r"(type) : "cc"); 673 return ret; 674 } 675 676 const char *exit_reason_description(u64 reason); 677 void print_vmexit_info(); 678 void print_vmentry_failure_info(struct vmentry_failure *failure); 679 void ept_sync(int type, u64 eptp); 680 void vpid_sync(int type, u16 vpid); 681 void install_ept_entry(unsigned long *pml4, int pte_level, 682 unsigned long guest_addr, unsigned long pte, 683 unsigned long *pt_page); 684 void install_1g_ept(unsigned long *pml4, unsigned long phys, 685 unsigned long guest_addr, u64 perm); 686 void install_2m_ept(unsigned long *pml4, unsigned long phys, 687 unsigned long guest_addr, u64 perm); 688 void install_ept(unsigned long *pml4, unsigned long phys, 689 unsigned long guest_addr, u64 perm); 690 void setup_ept_range(unsigned long *pml4, unsigned long start, 691 unsigned long len, int map_1g, int map_2m, u64 perm); 692 unsigned long get_ept_pte(unsigned long *pml4, 693 unsigned long guest_addr, int level); 694 int set_ept_pte(unsigned long *pml4, unsigned long guest_addr, 695 int level, u64 pte_val); 696 void check_ept_ad(unsigned long *pml4, u64 guest_cr3, 697 unsigned long guest_addr, int expected_gpa_ad, 698 int expected_pt_ad); 699 void clear_ept_ad(unsigned long *pml4, u64 guest_cr3, 700 unsigned long guest_addr); 701 702 void enter_guest(void); 703 704 typedef void (*test_guest_func)(void); 705 typedef void (*test_teardown_func)(void *data); 706 void test_set_guest(test_guest_func func); 707 void test_add_teardown(test_teardown_func func, void *data); 708 void test_skip(const char *msg); 709 710 void __abort_test(void); 711 712 #define TEST_ASSERT(cond) \ 713 do { \ 714 if (!(cond)) { \ 715 report("%s:%d: Assertion failed: %s", 0, \ 716 __FILE__, __LINE__, #cond); \ 717 dump_stack(); \ 718 __abort_test(); \ 719 } \ 720 } while (0) 721 722 #define TEST_ASSERT_MSG(cond, fmt, args...) \ 723 do { \ 724 if (!(cond)) { \ 725 report("%s:%d: Assertion failed: %s\n" fmt, 0, \ 726 __FILE__, __LINE__, #cond, ##args); \ 727 dump_stack(); \ 728 __abort_test(); \ 729 } \ 730 } while (0) 731 732 #define __TEST_EQ(a, b, a_str, b_str, assertion, fmt, args...) \ 733 do { \ 734 typeof(a) _a = a; \ 735 typeof(b) _b = b; \ 736 if (_a != _b) { \ 737 char _bin_a[BINSTR_SZ]; \ 738 char _bin_b[BINSTR_SZ]; \ 739 binstr(_a, _bin_a); \ 740 binstr(_b, _bin_b); \ 741 report("%s:%d: %s failed: (%s) == (%s)\n" \ 742 "\tLHS: 0x%016lx - %s - %lu\n" \ 743 "\tRHS: 0x%016lx - %s - %lu%s" fmt, 0, \ 744 __FILE__, __LINE__, \ 745 assertion ? "Assertion" : "Expectation", a_str, b_str, \ 746 (unsigned long) _a, _bin_a, (unsigned long) _a, \ 747 (unsigned long) _b, _bin_b, (unsigned long) _b, \ 748 fmt[0] == '\0' ? "" : "\n", ## args); \ 749 dump_stack(); \ 750 if (assertion) \ 751 __abort_test(); \ 752 } \ 753 } while (0) 754 755 #define TEST_ASSERT_EQ(a, b) __TEST_EQ(a, b, #a, #b, 1, "") 756 #define TEST_ASSERT_EQ_MSG(a, b, fmt, args...) \ 757 __TEST_EQ(a, b, #a, #b, 1, fmt, ## args) 758 #define TEST_EXPECT_EQ(a, b) __TEST_EQ(a, b, #a, #b, 0, "") 759 #define TEST_EXPECT_EQ_MSG(a, b, fmt, args...) \ 760 __TEST_EQ(a, b, #a, #b, 0, fmt, ## args) 761 762 #endif 763