1 #ifndef __VMX_H 2 #define __VMX_H 3 4 #include "libcflat.h" 5 #include "processor.h" 6 #include "bitops.h" 7 #include "asm/page.h" 8 #include "asm/io.h" 9 10 struct vmcs_hdr { 11 u32 revision_id:31; 12 u32 shadow_vmcs:1; 13 }; 14 15 struct vmcs { 16 struct vmcs_hdr hdr; 17 u32 abort; /* VMX-abort indicator */ 18 /* VMCS data */ 19 char data[0]; 20 }; 21 22 struct invvpid_operand { 23 u64 vpid; 24 u64 gla; 25 }; 26 27 struct regs { 28 u64 rax; 29 u64 rcx; 30 u64 rdx; 31 u64 rbx; 32 u64 cr2; 33 u64 rbp; 34 u64 rsi; 35 u64 rdi; 36 u64 r8; 37 u64 r9; 38 u64 r10; 39 u64 r11; 40 u64 r12; 41 u64 r13; 42 u64 r14; 43 u64 r15; 44 u64 rflags; 45 }; 46 47 union exit_reason { 48 struct { 49 u32 basic : 16; 50 u32 reserved16 : 1; 51 u32 reserved17 : 1; 52 u32 reserved18 : 1; 53 u32 reserved19 : 1; 54 u32 reserved20 : 1; 55 u32 reserved21 : 1; 56 u32 reserved22 : 1; 57 u32 reserved23 : 1; 58 u32 reserved24 : 1; 59 u32 reserved25 : 1; 60 u32 reserved26 : 1; 61 u32 enclave_mode : 1; 62 u32 smi_pending_mtf : 1; 63 u32 smi_from_vmx_root : 1; 64 u32 reserved30 : 1; 65 u32 failed_vmentry : 1; 66 }; 67 u32 full; 68 }; 69 70 struct vmentry_result { 71 /* Instruction mnemonic (for convenience). */ 72 const char *instr; 73 /* Did the test attempt vmlaunch or vmresume? */ 74 bool vmlaunch; 75 /* Did the instruction VM-Fail? */ 76 bool vm_fail; 77 /* Did the VM-Entry fully enter the guest? */ 78 bool entered; 79 /* VM-Exit reason, valid iff !vm_fail */ 80 union exit_reason exit_reason; 81 /* Contents of [re]flags after failed entry. */ 82 unsigned long flags; 83 }; 84 85 struct vmx_test { 86 const char *name; 87 int (*init)(struct vmcs *vmcs); 88 void (*guest_main)(void); 89 int (*exit_handler)(union exit_reason exit_reason); 90 void (*syscall_handler)(u64 syscall_no); 91 struct regs guest_regs; 92 int (*entry_failure_handler)(struct vmentry_result *result); 93 struct vmcs *vmcs; 94 int exits; 95 /* Alternative test interface. */ 96 void (*v2)(void); 97 }; 98 99 union vmx_basic { 100 u64 val; 101 struct { 102 u32 revision; 103 u32 size:13, 104 reserved1: 3, 105 width:1, 106 dual:1, 107 type:4, 108 insouts:1, 109 ctrl:1, 110 reserved2:8; 111 }; 112 }; 113 114 union vmx_ctrl_msr { 115 u64 val; 116 struct { 117 u32 set, clr; 118 }; 119 }; 120 121 union vmx_ept_vpid { 122 u64 val; 123 struct { 124 u32:16, 125 super:2, 126 : 2, 127 invept:1, 128 : 11; 129 u32 invvpid:1; 130 }; 131 }; 132 133 enum Encoding { 134 /* 16-Bit Control Fields */ 135 VPID = 0x0000ul, 136 /* Posted-interrupt notification vector */ 137 PINV = 0x0002ul, 138 /* EPTP index */ 139 EPTP_IDX = 0x0004ul, 140 141 /* 16-Bit Guest State Fields */ 142 GUEST_SEL_ES = 0x0800ul, 143 GUEST_SEL_CS = 0x0802ul, 144 GUEST_SEL_SS = 0x0804ul, 145 GUEST_SEL_DS = 0x0806ul, 146 GUEST_SEL_FS = 0x0808ul, 147 GUEST_SEL_GS = 0x080aul, 148 GUEST_SEL_LDTR = 0x080cul, 149 GUEST_SEL_TR = 0x080eul, 150 GUEST_INT_STATUS = 0x0810ul, 151 GUEST_PML_INDEX = 0x0812ul, 152 153 /* 16-Bit Host State Fields */ 154 HOST_SEL_ES = 0x0c00ul, 155 HOST_SEL_CS = 0x0c02ul, 156 HOST_SEL_SS = 0x0c04ul, 157 HOST_SEL_DS = 0x0c06ul, 158 HOST_SEL_FS = 0x0c08ul, 159 HOST_SEL_GS = 0x0c0aul, 160 HOST_SEL_TR = 0x0c0cul, 161 162 /* 64-Bit Control Fields */ 163 IO_BITMAP_A = 0x2000ul, 164 IO_BITMAP_B = 0x2002ul, 165 MSR_BITMAP = 0x2004ul, 166 EXIT_MSR_ST_ADDR = 0x2006ul, 167 EXIT_MSR_LD_ADDR = 0x2008ul, 168 ENTER_MSR_LD_ADDR = 0x200aul, 169 VMCS_EXEC_PTR = 0x200cul, 170 TSC_OFFSET = 0x2010ul, 171 TSC_OFFSET_HI = 0x2011ul, 172 APIC_VIRT_ADDR = 0x2012ul, 173 APIC_ACCS_ADDR = 0x2014ul, 174 POSTED_INTR_DESC_ADDR = 0x2016ul, 175 EPTP = 0x201aul, 176 EPTP_HI = 0x201bul, 177 VMREAD_BITMAP = 0x2026ul, 178 VMREAD_BITMAP_HI = 0x2027ul, 179 VMWRITE_BITMAP = 0x2028ul, 180 VMWRITE_BITMAP_HI = 0x2029ul, 181 EOI_EXIT_BITMAP0 = 0x201cul, 182 EOI_EXIT_BITMAP1 = 0x201eul, 183 EOI_EXIT_BITMAP2 = 0x2020ul, 184 EOI_EXIT_BITMAP3 = 0x2022ul, 185 PMLADDR = 0x200eul, 186 PMLADDR_HI = 0x200ful, 187 188 189 /* 64-Bit Readonly Data Field */ 190 INFO_PHYS_ADDR = 0x2400ul, 191 192 /* 64-Bit Guest State */ 193 VMCS_LINK_PTR = 0x2800ul, 194 VMCS_LINK_PTR_HI = 0x2801ul, 195 GUEST_DEBUGCTL = 0x2802ul, 196 GUEST_DEBUGCTL_HI = 0x2803ul, 197 GUEST_EFER = 0x2806ul, 198 GUEST_PAT = 0x2804ul, 199 GUEST_PERF_GLOBAL_CTRL = 0x2808ul, 200 GUEST_PDPTE = 0x280aul, 201 GUEST_BNDCFGS = 0x2812ul, 202 203 /* 64-Bit Host State */ 204 HOST_PAT = 0x2c00ul, 205 HOST_EFER = 0x2c02ul, 206 HOST_PERF_GLOBAL_CTRL = 0x2c04ul, 207 208 /* 32-Bit Control Fields */ 209 PIN_CONTROLS = 0x4000ul, 210 CPU_EXEC_CTRL0 = 0x4002ul, 211 EXC_BITMAP = 0x4004ul, 212 PF_ERROR_MASK = 0x4006ul, 213 PF_ERROR_MATCH = 0x4008ul, 214 CR3_TARGET_COUNT = 0x400aul, 215 EXI_CONTROLS = 0x400cul, 216 EXI_MSR_ST_CNT = 0x400eul, 217 EXI_MSR_LD_CNT = 0x4010ul, 218 ENT_CONTROLS = 0x4012ul, 219 ENT_MSR_LD_CNT = 0x4014ul, 220 ENT_INTR_INFO = 0x4016ul, 221 ENT_INTR_ERROR = 0x4018ul, 222 ENT_INST_LEN = 0x401aul, 223 TPR_THRESHOLD = 0x401cul, 224 CPU_EXEC_CTRL1 = 0x401eul, 225 226 /* 32-Bit R/O Data Fields */ 227 VMX_INST_ERROR = 0x4400ul, 228 EXI_REASON = 0x4402ul, 229 EXI_INTR_INFO = 0x4404ul, 230 EXI_INTR_ERROR = 0x4406ul, 231 IDT_VECT_INFO = 0x4408ul, 232 IDT_VECT_ERROR = 0x440aul, 233 EXI_INST_LEN = 0x440cul, 234 EXI_INST_INFO = 0x440eul, 235 236 /* 32-Bit Guest State Fields */ 237 GUEST_LIMIT_ES = 0x4800ul, 238 GUEST_LIMIT_CS = 0x4802ul, 239 GUEST_LIMIT_SS = 0x4804ul, 240 GUEST_LIMIT_DS = 0x4806ul, 241 GUEST_LIMIT_FS = 0x4808ul, 242 GUEST_LIMIT_GS = 0x480aul, 243 GUEST_LIMIT_LDTR = 0x480cul, 244 GUEST_LIMIT_TR = 0x480eul, 245 GUEST_LIMIT_GDTR = 0x4810ul, 246 GUEST_LIMIT_IDTR = 0x4812ul, 247 GUEST_AR_ES = 0x4814ul, 248 GUEST_AR_CS = 0x4816ul, 249 GUEST_AR_SS = 0x4818ul, 250 GUEST_AR_DS = 0x481aul, 251 GUEST_AR_FS = 0x481cul, 252 GUEST_AR_GS = 0x481eul, 253 GUEST_AR_LDTR = 0x4820ul, 254 GUEST_AR_TR = 0x4822ul, 255 GUEST_INTR_STATE = 0x4824ul, 256 GUEST_ACTV_STATE = 0x4826ul, 257 GUEST_SMBASE = 0x4828ul, 258 GUEST_SYSENTER_CS = 0x482aul, 259 PREEMPT_TIMER_VALUE = 0x482eul, 260 261 /* 32-Bit Host State Fields */ 262 HOST_SYSENTER_CS = 0x4c00ul, 263 264 /* Natural-Width Control Fields */ 265 CR0_MASK = 0x6000ul, 266 CR4_MASK = 0x6002ul, 267 CR0_READ_SHADOW = 0x6004ul, 268 CR4_READ_SHADOW = 0x6006ul, 269 CR3_TARGET_0 = 0x6008ul, 270 CR3_TARGET_1 = 0x600aul, 271 CR3_TARGET_2 = 0x600cul, 272 CR3_TARGET_3 = 0x600eul, 273 274 /* Natural-Width R/O Data Fields */ 275 EXI_QUALIFICATION = 0x6400ul, 276 IO_RCX = 0x6402ul, 277 IO_RSI = 0x6404ul, 278 IO_RDI = 0x6406ul, 279 IO_RIP = 0x6408ul, 280 GUEST_LINEAR_ADDRESS = 0x640aul, 281 282 /* Natural-Width Guest State Fields */ 283 GUEST_CR0 = 0x6800ul, 284 GUEST_CR3 = 0x6802ul, 285 GUEST_CR4 = 0x6804ul, 286 GUEST_BASE_ES = 0x6806ul, 287 GUEST_BASE_CS = 0x6808ul, 288 GUEST_BASE_SS = 0x680aul, 289 GUEST_BASE_DS = 0x680cul, 290 GUEST_BASE_FS = 0x680eul, 291 GUEST_BASE_GS = 0x6810ul, 292 GUEST_BASE_LDTR = 0x6812ul, 293 GUEST_BASE_TR = 0x6814ul, 294 GUEST_BASE_GDTR = 0x6816ul, 295 GUEST_BASE_IDTR = 0x6818ul, 296 GUEST_DR7 = 0x681aul, 297 GUEST_RSP = 0x681cul, 298 GUEST_RIP = 0x681eul, 299 GUEST_RFLAGS = 0x6820ul, 300 GUEST_PENDING_DEBUG = 0x6822ul, 301 GUEST_SYSENTER_ESP = 0x6824ul, 302 GUEST_SYSENTER_EIP = 0x6826ul, 303 304 /* Natural-Width Host State Fields */ 305 HOST_CR0 = 0x6c00ul, 306 HOST_CR3 = 0x6c02ul, 307 HOST_CR4 = 0x6c04ul, 308 HOST_BASE_FS = 0x6c06ul, 309 HOST_BASE_GS = 0x6c08ul, 310 HOST_BASE_TR = 0x6c0aul, 311 HOST_BASE_GDTR = 0x6c0cul, 312 HOST_BASE_IDTR = 0x6c0eul, 313 HOST_SYSENTER_ESP = 0x6c10ul, 314 HOST_SYSENTER_EIP = 0x6c12ul, 315 HOST_RSP = 0x6c14ul, 316 HOST_RIP = 0x6c16ul 317 }; 318 319 #define VMX_ENTRY_FAILURE (1ul << 31) 320 #define VMX_ENTRY_FLAGS (X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | \ 321 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF) 322 323 enum Reason { 324 VMX_EXC_NMI = 0, 325 VMX_EXTINT = 1, 326 VMX_TRIPLE_FAULT = 2, 327 VMX_INIT = 3, 328 VMX_SIPI = 4, 329 VMX_SMI_IO = 5, 330 VMX_SMI_OTHER = 6, 331 VMX_INTR_WINDOW = 7, 332 VMX_NMI_WINDOW = 8, 333 VMX_TASK_SWITCH = 9, 334 VMX_CPUID = 10, 335 VMX_GETSEC = 11, 336 VMX_HLT = 12, 337 VMX_INVD = 13, 338 VMX_INVLPG = 14, 339 VMX_RDPMC = 15, 340 VMX_RDTSC = 16, 341 VMX_RSM = 17, 342 VMX_VMCALL = 18, 343 VMX_VMCLEAR = 19, 344 VMX_VMLAUNCH = 20, 345 VMX_VMPTRLD = 21, 346 VMX_VMPTRST = 22, 347 VMX_VMREAD = 23, 348 VMX_VMRESUME = 24, 349 VMX_VMWRITE = 25, 350 VMX_VMXOFF = 26, 351 VMX_VMXON = 27, 352 VMX_CR = 28, 353 VMX_DR = 29, 354 VMX_IO = 30, 355 VMX_RDMSR = 31, 356 VMX_WRMSR = 32, 357 VMX_FAIL_STATE = 33, 358 VMX_FAIL_MSR = 34, 359 VMX_MWAIT = 36, 360 VMX_MTF = 37, 361 VMX_MONITOR = 39, 362 VMX_PAUSE = 40, 363 VMX_FAIL_MCHECK = 41, 364 VMX_TPR_THRESHOLD = 43, 365 VMX_APIC_ACCESS = 44, 366 VMX_EOI_INDUCED = 45, 367 VMX_GDTR_IDTR = 46, 368 VMX_LDTR_TR = 47, 369 VMX_EPT_VIOLATION = 48, 370 VMX_EPT_MISCONFIG = 49, 371 VMX_INVEPT = 50, 372 VMX_PREEMPT = 52, 373 VMX_INVVPID = 53, 374 VMX_WBINVD = 54, 375 VMX_XSETBV = 55, 376 VMX_APIC_WRITE = 56, 377 VMX_RDRAND = 57, 378 VMX_INVPCID = 58, 379 VMX_VMFUNC = 59, 380 VMX_RDSEED = 61, 381 VMX_PML_FULL = 62, 382 VMX_XSAVES = 63, 383 VMX_XRSTORS = 64, 384 }; 385 386 enum Ctrl_exi { 387 EXI_SAVE_DBGCTLS = 1UL << 2, 388 EXI_HOST_64 = 1UL << 9, 389 EXI_LOAD_PERF = 1UL << 12, 390 EXI_INTA = 1UL << 15, 391 EXI_SAVE_PAT = 1UL << 18, 392 EXI_LOAD_PAT = 1UL << 19, 393 EXI_SAVE_EFER = 1UL << 20, 394 EXI_LOAD_EFER = 1UL << 21, 395 EXI_SAVE_PREEMPT = 1UL << 22, 396 }; 397 398 enum Ctrl_ent { 399 ENT_LOAD_DBGCTLS = 1UL << 2, 400 ENT_GUEST_64 = 1UL << 9, 401 ENT_LOAD_PERF = 1UL << 13, 402 ENT_LOAD_PAT = 1UL << 14, 403 ENT_LOAD_EFER = 1UL << 15, 404 ENT_LOAD_BNDCFGS = 1UL << 16 405 }; 406 407 enum Ctrl_pin { 408 PIN_EXTINT = 1ul << 0, 409 PIN_NMI = 1ul << 3, 410 PIN_VIRT_NMI = 1ul << 5, 411 PIN_PREEMPT = 1ul << 6, 412 PIN_POST_INTR = 1ul << 7, 413 }; 414 415 enum Ctrl0 { 416 CPU_INTR_WINDOW = 1ul << 2, 417 CPU_USE_TSC_OFFSET = 1ul << 3, 418 CPU_HLT = 1ul << 7, 419 CPU_INVLPG = 1ul << 9, 420 CPU_MWAIT = 1ul << 10, 421 CPU_RDPMC = 1ul << 11, 422 CPU_RDTSC = 1ul << 12, 423 CPU_CR3_LOAD = 1ul << 15, 424 CPU_CR3_STORE = 1ul << 16, 425 CPU_CR8_LOAD = 1ul << 19, 426 CPU_CR8_STORE = 1ul << 20, 427 CPU_TPR_SHADOW = 1ul << 21, 428 CPU_NMI_WINDOW = 1ul << 22, 429 CPU_IO = 1ul << 24, 430 CPU_IO_BITMAP = 1ul << 25, 431 CPU_MTF = 1ul << 27, 432 CPU_MSR_BITMAP = 1ul << 28, 433 CPU_MONITOR = 1ul << 29, 434 CPU_PAUSE = 1ul << 30, 435 CPU_SECONDARY = 1ul << 31, 436 }; 437 438 enum Ctrl1 { 439 CPU_VIRT_APIC_ACCESSES = 1ul << 0, 440 CPU_EPT = 1ul << 1, 441 CPU_DESC_TABLE = 1ul << 2, 442 CPU_RDTSCP = 1ul << 3, 443 CPU_VIRT_X2APIC = 1ul << 4, 444 CPU_VPID = 1ul << 5, 445 CPU_WBINVD = 1ul << 6, 446 CPU_URG = 1ul << 7, 447 CPU_APIC_REG_VIRT = 1ul << 8, 448 CPU_VINTD = 1ul << 9, 449 CPU_RDRAND = 1ul << 11, 450 CPU_SHADOW_VMCS = 1ul << 14, 451 CPU_RDSEED = 1ul << 16, 452 CPU_PML = 1ul << 17, 453 CPU_USE_TSC_SCALING = 1ul << 25, 454 }; 455 456 enum Intr_type { 457 VMX_INTR_TYPE_EXT_INTR = 0, 458 VMX_INTR_TYPE_NMI_INTR = 2, 459 VMX_INTR_TYPE_HARD_EXCEPTION = 3, 460 VMX_INTR_TYPE_SOFT_INTR = 4, 461 VMX_INTR_TYPE_SOFT_EXCEPTION = 6, 462 }; 463 464 /* 465 * Interruption-information format 466 */ 467 #define INTR_INFO_VECTOR_MASK 0xff /* 7:0 */ 468 #define INTR_INFO_INTR_TYPE_MASK 0x700 /* 10:8 */ 469 #define INTR_INFO_DELIVER_CODE_MASK 0x800 /* 11 */ 470 #define INTR_INFO_UNBLOCK_NMI_MASK 0x1000 /* 12 */ 471 #define INTR_INFO_VALID_MASK 0x80000000 /* 31 */ 472 473 #define INTR_INFO_INTR_TYPE_SHIFT 8 474 475 #define INTR_TYPE_EXT_INTR (0 << 8) /* external interrupt */ 476 #define INTR_TYPE_RESERVED (1 << 8) /* reserved */ 477 #define INTR_TYPE_NMI_INTR (2 << 8) /* NMI */ 478 #define INTR_TYPE_HARD_EXCEPTION (3 << 8) /* processor exception */ 479 #define INTR_TYPE_SOFT_INTR (4 << 8) /* software interrupt */ 480 #define INTR_TYPE_PRIV_SW_EXCEPTION (5 << 8) /* priv. software exception */ 481 #define INTR_TYPE_SOFT_EXCEPTION (6 << 8) /* software exception */ 482 #define INTR_TYPE_OTHER_EVENT (7 << 8) /* other event */ 483 484 /* 485 * Guest interruptibility state 486 */ 487 #define GUEST_INTR_STATE_STI (1 << 0) 488 #define GUEST_INTR_STATE_MOVSS (1 << 1) 489 #define GUEST_INTR_STATE_SMI (1 << 2) 490 #define GUEST_INTR_STATE_NMI (1 << 3) 491 #define GUEST_INTR_STATE_ENCLAVE (1 << 4) 492 493 /* 494 * VM-instruction error numbers 495 */ 496 enum vm_instruction_error_number { 497 VMXERR_VMCALL_IN_VMX_ROOT_OPERATION = 1, 498 VMXERR_VMCLEAR_INVALID_ADDRESS = 2, 499 VMXERR_VMCLEAR_VMXON_POINTER = 3, 500 VMXERR_VMLAUNCH_NONCLEAR_VMCS = 4, 501 VMXERR_VMRESUME_NONLAUNCHED_VMCS = 5, 502 VMXERR_VMRESUME_AFTER_VMXOFF = 6, 503 VMXERR_ENTRY_INVALID_CONTROL_FIELD = 7, 504 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD = 8, 505 VMXERR_VMPTRLD_INVALID_ADDRESS = 9, 506 VMXERR_VMPTRLD_VMXON_POINTER = 10, 507 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID = 11, 508 VMXERR_UNSUPPORTED_VMCS_COMPONENT = 12, 509 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT = 13, 510 VMXERR_VMXON_IN_VMX_ROOT_OPERATION = 15, 511 VMXERR_ENTRY_INVALID_EXECUTIVE_VMCS_POINTER = 16, 512 VMXERR_ENTRY_NONLAUNCHED_EXECUTIVE_VMCS = 17, 513 VMXERR_ENTRY_EXECUTIVE_VMCS_POINTER_NOT_VMXON_POINTER = 18, 514 VMXERR_VMCALL_NONCLEAR_VMCS = 19, 515 VMXERR_VMCALL_INVALID_VM_EXIT_CONTROL_FIELDS = 20, 516 VMXERR_VMCALL_INCORRECT_MSEG_REVISION_ID = 22, 517 VMXERR_VMXOFF_UNDER_DUAL_MONITOR_TREATMENT_OF_SMIS_AND_SMM = 23, 518 VMXERR_VMCALL_INVALID_SMM_MONITOR_FEATURES = 24, 519 VMXERR_ENTRY_INVALID_VM_EXECUTION_CONTROL_FIELDS_IN_EXECUTIVE_VMCS = 25, 520 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS = 26, 521 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID = 28, 522 }; 523 524 #define SAVE_GPR \ 525 "xchg %rax, regs\n\t" \ 526 "xchg %rcx, regs+0x8\n\t" \ 527 "xchg %rdx, regs+0x10\n\t" \ 528 "xchg %rbx, regs+0x18\n\t" \ 529 "xchg %rbp, regs+0x28\n\t" \ 530 "xchg %rsi, regs+0x30\n\t" \ 531 "xchg %rdi, regs+0x38\n\t" \ 532 "xchg %r8, regs+0x40\n\t" \ 533 "xchg %r9, regs+0x48\n\t" \ 534 "xchg %r10, regs+0x50\n\t" \ 535 "xchg %r11, regs+0x58\n\t" \ 536 "xchg %r12, regs+0x60\n\t" \ 537 "xchg %r13, regs+0x68\n\t" \ 538 "xchg %r14, regs+0x70\n\t" \ 539 "xchg %r15, regs+0x78\n\t" 540 541 #define LOAD_GPR SAVE_GPR 542 543 #define SAVE_GPR_C \ 544 "xchg %%rax, regs\n\t" \ 545 "xchg %%rcx, regs+0x8\n\t" \ 546 "xchg %%rdx, regs+0x10\n\t" \ 547 "xchg %%rbx, regs+0x18\n\t" \ 548 "xchg %%rbp, regs+0x28\n\t" \ 549 "xchg %%rsi, regs+0x30\n\t" \ 550 "xchg %%rdi, regs+0x38\n\t" \ 551 "xchg %%r8, regs+0x40\n\t" \ 552 "xchg %%r9, regs+0x48\n\t" \ 553 "xchg %%r10, regs+0x50\n\t" \ 554 "xchg %%r11, regs+0x58\n\t" \ 555 "xchg %%r12, regs+0x60\n\t" \ 556 "xchg %%r13, regs+0x68\n\t" \ 557 "xchg %%r14, regs+0x70\n\t" \ 558 "xchg %%r15, regs+0x78\n\t" 559 560 #define LOAD_GPR_C SAVE_GPR_C 561 562 #define VMX_IO_SIZE_MASK 0x7 563 #define _VMX_IO_BYTE 0 564 #define _VMX_IO_WORD 1 565 #define _VMX_IO_LONG 3 566 #define VMX_IO_DIRECTION_MASK (1ul << 3) 567 #define VMX_IO_IN (1ul << 3) 568 #define VMX_IO_OUT 0 569 #define VMX_IO_STRING (1ul << 4) 570 #define VMX_IO_REP (1ul << 5) 571 #define VMX_IO_OPRAND_IMM (1ul << 6) 572 #define VMX_IO_PORT_MASK 0xFFFF0000 573 #define VMX_IO_PORT_SHIFT 16 574 575 #define VMX_TEST_START 0 576 #define VMX_TEST_VMEXIT 1 577 #define VMX_TEST_EXIT 2 578 #define VMX_TEST_RESUME 3 579 #define VMX_TEST_VMABORT 4 580 #define VMX_TEST_VMSKIP 5 581 582 #define HYPERCALL_BIT (1ul << 12) 583 #define HYPERCALL_MASK 0xFFF 584 #define HYPERCALL_VMEXIT 0x1 585 #define HYPERCALL_VMABORT 0x2 586 #define HYPERCALL_VMSKIP 0x3 587 588 #define EPTP_PG_WALK_LEN_SHIFT 3ul 589 #define EPTP_PG_WALK_LEN_MASK 0x38ul 590 #define EPTP_RESERV_BITS_MASK 0x1ful 591 #define EPTP_RESERV_BITS_SHIFT 0x7ul 592 #define EPTP_AD_FLAG (1ul << 6) 593 594 #define EPT_MEM_TYPE_UC 0ul 595 #define EPT_MEM_TYPE_WC 1ul 596 #define EPT_MEM_TYPE_WT 4ul 597 #define EPT_MEM_TYPE_WP 5ul 598 #define EPT_MEM_TYPE_WB 6ul 599 600 #define EPT_RA 1ul 601 #define EPT_WA 2ul 602 #define EPT_EA 4ul 603 #define EPT_PRESENT (EPT_RA | EPT_WA | EPT_EA) 604 #define EPT_ACCESS_FLAG (1ul << 8) 605 #define EPT_DIRTY_FLAG (1ul << 9) 606 #define EPT_LARGE_PAGE (1ul << 7) 607 #define EPT_MEM_TYPE_SHIFT 3ul 608 #define EPT_MEM_TYPE_MASK 0x7ul 609 #define EPT_IGNORE_PAT (1ul << 6) 610 #define EPT_SUPPRESS_VE (1ull << 63) 611 612 #define EPT_CAP_WT 1ull 613 #define EPT_CAP_PWL4 (1ull << 6) 614 #define EPT_CAP_UC (1ull << 8) 615 #define EPT_CAP_WB (1ull << 14) 616 #define EPT_CAP_2M_PAGE (1ull << 16) 617 #define EPT_CAP_1G_PAGE (1ull << 17) 618 #define EPT_CAP_INVEPT (1ull << 20) 619 #define EPT_CAP_INVEPT_SINGLE (1ull << 25) 620 #define EPT_CAP_INVEPT_ALL (1ull << 26) 621 #define EPT_CAP_AD_FLAG (1ull << 21) 622 #define VPID_CAP_INVVPID (1ull << 32) 623 #define VPID_CAP_INVVPID_ADDR (1ull << 40) 624 #define VPID_CAP_INVVPID_CXTGLB (1ull << 41) 625 #define VPID_CAP_INVVPID_ALL (1ull << 42) 626 #define VPID_CAP_INVVPID_CXTLOC (1ull << 43) 627 628 #define PAGE_SIZE_2M (512 * PAGE_SIZE) 629 #define PAGE_SIZE_1G (512 * PAGE_SIZE_2M) 630 #define EPT_PAGE_LEVEL 4 631 #define EPT_PGDIR_WIDTH 9 632 #define EPT_PGDIR_MASK 511 633 #define EPT_PGDIR_ENTRIES (1 << EPT_PGDIR_WIDTH) 634 #define EPT_LEVEL_SHIFT(level) (((level)-1) * EPT_PGDIR_WIDTH + 12) 635 #define EPT_ADDR_MASK GENMASK_ULL(51, 12) 636 #define PAGE_MASK_2M (~(PAGE_SIZE_2M-1)) 637 638 #define EPT_VLT_RD (1ull << 0) 639 #define EPT_VLT_WR (1ull << 1) 640 #define EPT_VLT_FETCH (1ull << 2) 641 #define EPT_VLT_PERM_RD (1ull << 3) 642 #define EPT_VLT_PERM_WR (1ull << 4) 643 #define EPT_VLT_PERM_EX (1ull << 5) 644 #define EPT_VLT_PERM_USER_EX (1ull << 6) 645 #define EPT_VLT_PERMS (EPT_VLT_PERM_RD | EPT_VLT_PERM_WR | \ 646 EPT_VLT_PERM_EX) 647 #define EPT_VLT_LADDR_VLD (1ull << 7) 648 #define EPT_VLT_PADDR (1ull << 8) 649 #define EPT_VLT_GUEST_USER (1ull << 9) 650 #define EPT_VLT_GUEST_RW (1ull << 10) 651 #define EPT_VLT_GUEST_EX (1ull << 11) 652 #define EPT_VLT_GUEST_MASK (EPT_VLT_GUEST_USER | EPT_VLT_GUEST_RW | \ 653 EPT_VLT_GUEST_EX) 654 655 #define MAGIC_VAL_1 0x12345678ul 656 #define MAGIC_VAL_2 0x87654321ul 657 #define MAGIC_VAL_3 0xfffffffful 658 #define MAGIC_VAL_4 0xdeadbeeful 659 660 #define INVEPT_SINGLE 1 661 #define INVEPT_GLOBAL 2 662 663 #define INVVPID_ADDR 0 664 #define INVVPID_CONTEXT_GLOBAL 1 665 #define INVVPID_ALL 2 666 #define INVVPID_CONTEXT_LOCAL 3 667 668 #define ACTV_ACTIVE 0 669 #define ACTV_HLT 1 670 671 /* 672 * VMCS field encoding: 673 * Bit 0: High-access 674 * Bits 1-9: Index 675 * Bits 10-12: Type 676 * Bits 13-15: Width 677 * Bits 15-64: Reserved 678 */ 679 #define VMCS_FIELD_HIGH_SHIFT (0) 680 #define VMCS_FIELD_INDEX_SHIFT (1) 681 #define VMCS_FIELD_INDEX_MASK GENMASK(9, 1) 682 #define VMCS_FIELD_TYPE_SHIFT (10) 683 #define VMCS_FIELD_WIDTH_SHIFT (13) 684 #define VMCS_FIELD_RESERVED_SHIFT (15) 685 #define VMCS_FIELD_BIT_SIZE (BITS_PER_LONG) 686 687 extern struct regs regs; 688 689 extern union vmx_basic basic; 690 extern union vmx_ctrl_msr ctrl_pin_rev; 691 extern union vmx_ctrl_msr ctrl_cpu_rev[2]; 692 extern union vmx_ctrl_msr ctrl_exit_rev; 693 extern union vmx_ctrl_msr ctrl_enter_rev; 694 extern union vmx_ept_vpid ept_vpid; 695 696 extern u64 *bsp_vmxon_region; 697 extern bool launched; 698 699 void vmx_set_test_stage(u32 s); 700 u32 vmx_get_test_stage(void); 701 void vmx_inc_test_stage(void); 702 703 static int _vmx_on(u64 *vmxon_region) 704 { 705 bool ret; 706 u64 rflags = read_rflags() | X86_EFLAGS_CF | X86_EFLAGS_ZF; 707 asm volatile ("push %1; popf; vmxon %2; setbe %0\n\t" 708 : "=q" (ret) : "q" (rflags), "m" (vmxon_region) : "cc"); 709 return ret; 710 } 711 712 static int vmx_on(void) 713 { 714 return _vmx_on(bsp_vmxon_region); 715 } 716 717 static int vmx_off(void) 718 { 719 bool ret; 720 u64 rflags = read_rflags() | X86_EFLAGS_CF | X86_EFLAGS_ZF; 721 722 asm volatile("push %1; popf; vmxoff; setbe %0\n\t" 723 : "=q"(ret) : "q" (rflags) : "cc"); 724 return ret; 725 } 726 727 static inline int make_vmcs_current(struct vmcs *vmcs) 728 { 729 bool ret; 730 u64 rflags = read_rflags() | X86_EFLAGS_CF | X86_EFLAGS_ZF; 731 732 asm volatile ("push %1; popf; vmptrld %2; setbe %0" 733 : "=q" (ret) : "q" (rflags), "m" (vmcs) : "cc"); 734 return ret; 735 } 736 737 static inline int vmcs_clear(struct vmcs *vmcs) 738 { 739 bool ret; 740 u64 rflags = read_rflags() | X86_EFLAGS_CF | X86_EFLAGS_ZF; 741 742 asm volatile ("push %1; popf; vmclear %2; setbe %0" 743 : "=q" (ret) : "q" (rflags), "m" (vmcs) : "cc"); 744 return ret; 745 } 746 747 static inline u64 vmcs_read(enum Encoding enc) 748 { 749 u64 val; 750 asm volatile ("vmread %1, %0" : "=rm" (val) : "r" ((u64)enc) : "cc"); 751 return val; 752 } 753 754 static inline int vmcs_read_checking(enum Encoding enc, u64 *value) 755 { 756 u64 rflags = read_rflags() | X86_EFLAGS_CF | X86_EFLAGS_ZF; 757 u64 encoding = enc; 758 u64 val; 759 760 asm volatile ("shl $8, %%rax;" 761 "sahf;" 762 "vmread %[encoding], %[val];" 763 "lahf;" 764 "shr $8, %%rax" 765 : /* output */ [val]"=rm"(val), "+a"(rflags) 766 : /* input */ [encoding]"r"(encoding) 767 : /* clobber */ "cc"); 768 769 *value = val; 770 return rflags & (X86_EFLAGS_CF | X86_EFLAGS_ZF); 771 } 772 773 static inline int vmcs_write(enum Encoding enc, u64 val) 774 { 775 bool ret; 776 asm volatile ("vmwrite %1, %2; setbe %0" 777 : "=q"(ret) : "rm" (val), "r" ((u64)enc) : "cc"); 778 return ret; 779 } 780 781 static inline int vmcs_set_bits(enum Encoding enc, u64 val) 782 { 783 return vmcs_write(enc, vmcs_read(enc) | val); 784 } 785 786 static inline int vmcs_clear_bits(enum Encoding enc, u64 val) 787 { 788 return vmcs_write(enc, vmcs_read(enc) & ~val); 789 } 790 791 static inline int vmcs_save(struct vmcs **vmcs) 792 { 793 bool ret; 794 unsigned long pa; 795 u64 rflags = read_rflags() | X86_EFLAGS_CF | X86_EFLAGS_ZF; 796 797 asm volatile ("push %2; popf; vmptrst %1; setbe %0" 798 : "=q" (ret), "=m" (pa) : "r" (rflags) : "cc"); 799 *vmcs = (pa == -1ull) ? NULL : phys_to_virt(pa); 800 return ret; 801 } 802 803 static inline bool invept(unsigned long type, u64 eptp) 804 { 805 bool ret; 806 u64 rflags = read_rflags() | X86_EFLAGS_CF | X86_EFLAGS_ZF; 807 808 struct { 809 u64 eptp, gpa; 810 } operand = {eptp, 0}; 811 asm volatile("push %1; popf; invept %2, %3; setbe %0" 812 : "=q" (ret) : "r" (rflags), "m"(operand),"r"(type) : "cc"); 813 return ret; 814 } 815 816 static inline bool invvpid(unsigned long type, u64 vpid, u64 gla) 817 { 818 bool ret; 819 u64 rflags = read_rflags() | X86_EFLAGS_CF | X86_EFLAGS_ZF; 820 821 struct invvpid_operand operand = {vpid, gla}; 822 asm volatile("push %1; popf; invvpid %2, %3; setbe %0" 823 : "=q" (ret) : "r" (rflags), "m"(operand),"r"(type) : "cc"); 824 return ret; 825 } 826 827 void enable_vmx(void); 828 void init_vmx(u64 *vmxon_region); 829 830 const char *exit_reason_description(u64 reason); 831 void print_vmexit_info(union exit_reason exit_reason); 832 void print_vmentry_failure_info(struct vmentry_result *result); 833 void ept_sync(int type, u64 eptp); 834 void vpid_sync(int type, u16 vpid); 835 void install_ept_entry(unsigned long *pml4, int pte_level, 836 unsigned long guest_addr, unsigned long pte, 837 unsigned long *pt_page); 838 void install_1g_ept(unsigned long *pml4, unsigned long phys, 839 unsigned long guest_addr, u64 perm); 840 void install_2m_ept(unsigned long *pml4, unsigned long phys, 841 unsigned long guest_addr, u64 perm); 842 void install_ept(unsigned long *pml4, unsigned long phys, 843 unsigned long guest_addr, u64 perm); 844 void setup_ept_range(unsigned long *pml4, unsigned long start, 845 unsigned long len, int map_1g, int map_2m, u64 perm); 846 bool get_ept_pte(unsigned long *pml4, unsigned long guest_addr, int level, 847 unsigned long *pte); 848 void set_ept_pte(unsigned long *pml4, unsigned long guest_addr, 849 int level, u64 pte_val); 850 void check_ept_ad(unsigned long *pml4, u64 guest_cr3, 851 unsigned long guest_addr, int expected_gpa_ad, 852 int expected_pt_ad); 853 void clear_ept_ad(unsigned long *pml4, u64 guest_cr3, 854 unsigned long guest_addr); 855 856 bool ept_2m_supported(void); 857 bool ept_1g_supported(void); 858 bool ept_huge_pages_supported(int level); 859 bool ept_execute_only_supported(void); 860 bool ept_ad_bits_supported(void); 861 862 #define ABORT_ON_EARLY_VMENTRY_FAIL 0x1 863 #define ABORT_ON_INVALID_GUEST_STATE 0x2 864 865 void __enter_guest(u8 abort_flag, struct vmentry_result *result); 866 void enter_guest(void); 867 void enter_guest_with_bad_controls(void); 868 869 typedef void (*test_guest_func)(void); 870 typedef void (*test_teardown_func)(void *data); 871 void test_set_guest(test_guest_func func); 872 void test_add_teardown(test_teardown_func func, void *data); 873 void test_skip(const char *msg); 874 875 void __abort_test(void); 876 877 #define TEST_ASSERT(cond) \ 878 do { \ 879 if (!(cond)) { \ 880 report(0, "%s:%d: Assertion failed: %s", \ 881 __FILE__, __LINE__, #cond); \ 882 dump_stack(); \ 883 __abort_test(); \ 884 } \ 885 report_pass(); \ 886 } while (0) 887 888 #define TEST_ASSERT_MSG(cond, fmt, args...) \ 889 do { \ 890 if (!(cond)) { \ 891 report(0, "%s:%d: Assertion failed: %s\n" fmt, \ 892 __FILE__, __LINE__, #cond, ##args); \ 893 dump_stack(); \ 894 __abort_test(); \ 895 } \ 896 report_pass(); \ 897 } while (0) 898 899 #define __TEST_EQ(a, b, a_str, b_str, assertion, fmt, args...) \ 900 do { \ 901 typeof(a) _a = a; \ 902 typeof(b) _b = b; \ 903 if (_a != _b) { \ 904 char _bin_a[BINSTR_SZ]; \ 905 char _bin_b[BINSTR_SZ]; \ 906 binstr(_a, _bin_a); \ 907 binstr(_b, _bin_b); \ 908 report(0, \ 909 "%s:%d: %s failed: (%s) == (%s)\n" \ 910 "\tLHS: %#018lx - %s - %lu\n" \ 911 "\tRHS: %#018lx - %s - %lu%s" fmt, \ 912 __FILE__, __LINE__, \ 913 assertion ? "Assertion" : "Expectation", a_str, b_str, \ 914 (unsigned long) _a, _bin_a, (unsigned long) _a, \ 915 (unsigned long) _b, _bin_b, (unsigned long) _b, \ 916 fmt[0] == '\0' ? "" : "\n", ## args); \ 917 dump_stack(); \ 918 if (assertion) \ 919 __abort_test(); \ 920 } \ 921 report_pass(); \ 922 } while (0) 923 924 #define TEST_ASSERT_EQ(a, b) __TEST_EQ(a, b, #a, #b, 1, "") 925 #define TEST_ASSERT_EQ_MSG(a, b, fmt, args...) \ 926 __TEST_EQ(a, b, #a, #b, 1, fmt, ## args) 927 #define TEST_EXPECT_EQ(a, b) __TEST_EQ(a, b, #a, #b, 0, "") 928 #define TEST_EXPECT_EQ_MSG(a, b, fmt, args...) \ 929 __TEST_EQ(a, b, #a, #b, 0, fmt, ## args) 930 931 #endif 932