xref: /kvm-unit-tests/x86/tsx-ctrl.c (revision c8312cbd25df6bf350a9654b6c0364b213ba406c)
16163f75dSPaolo Bonzini /* TSX tests */
26163f75dSPaolo Bonzini 
36163f75dSPaolo Bonzini #include "libcflat.h"
46163f75dSPaolo Bonzini #include "processor.h"
56163f75dSPaolo Bonzini #include "msr.h"
66163f75dSPaolo Bonzini 
try_transaction(void)76163f75dSPaolo Bonzini static bool try_transaction(void)
86163f75dSPaolo Bonzini {
96163f75dSPaolo Bonzini     unsigned x;
106163f75dSPaolo Bonzini     int i;
116163f75dSPaolo Bonzini 
126163f75dSPaolo Bonzini     for (i = 0; i < 100; i++) {
136163f75dSPaolo Bonzini         x = 0;
146163f75dSPaolo Bonzini         /*
156163f75dSPaolo Bonzini          * The value before the transaction is important, so make the
166163f75dSPaolo Bonzini          * operand input/output.
176163f75dSPaolo Bonzini          */
186163f75dSPaolo Bonzini         asm volatile("xbegin 2f; movb $1, %0; xend; 2:" : "+m" (x) : : "eax");
196163f75dSPaolo Bonzini         if (x) {
206163f75dSPaolo Bonzini             return true;
216163f75dSPaolo Bonzini         }
226163f75dSPaolo Bonzini     }
236163f75dSPaolo Bonzini     return false;
246163f75dSPaolo Bonzini }
256163f75dSPaolo Bonzini 
main(int ac,char ** av)266163f75dSPaolo Bonzini int main(int ac, char **av)
276163f75dSPaolo Bonzini {
286163f75dSPaolo Bonzini     if (!this_cpu_has(X86_FEATURE_RTM)) {
296163f75dSPaolo Bonzini         report_skip("TSX not available");
30*c8312cbdSNadav Amit 	return report_summary();
316163f75dSPaolo Bonzini     }
326163f75dSPaolo Bonzini     if (!this_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
336163f75dSPaolo Bonzini         report_skip("ARCH_CAPABILITIES not available");
34*c8312cbdSNadav Amit 	return report_summary();
356163f75dSPaolo Bonzini     }
366163f75dSPaolo Bonzini     if (!(rdmsr(MSR_IA32_ARCH_CAPABILITIES) & ARCH_CAP_TSX_CTRL_MSR)) {
376163f75dSPaolo Bonzini         report_skip("TSX_CTRL not available");
38*c8312cbdSNadav Amit 	return report_summary();
396163f75dSPaolo Bonzini     }
406163f75dSPaolo Bonzini 
41a299895bSThomas Huth     report(rdmsr(MSR_IA32_TSX_CTRL) == 0, "TSX_CTRL should be 0");
42a299895bSThomas Huth     report(try_transaction(), "Transactions do not abort");
436163f75dSPaolo Bonzini 
446163f75dSPaolo Bonzini     wrmsr(MSR_IA32_TSX_CTRL, TSX_CTRL_CPUID_CLEAR);
45a299895bSThomas Huth     report(!this_cpu_has(X86_FEATURE_RTM), "TSX_CTRL hides RTM");
46a299895bSThomas Huth     report(!this_cpu_has(X86_FEATURE_HLE), "TSX_CTRL hides HLE");
476163f75dSPaolo Bonzini 
486163f75dSPaolo Bonzini     /* Microcode might hide HLE unconditionally */
496163f75dSPaolo Bonzini     wrmsr(MSR_IA32_TSX_CTRL, 0);
50a299895bSThomas Huth     report(this_cpu_has(X86_FEATURE_RTM), "TSX_CTRL=0 unhides RTM");
516163f75dSPaolo Bonzini 
526163f75dSPaolo Bonzini     wrmsr(MSR_IA32_TSX_CTRL, TSX_CTRL_RTM_DISABLE);
53a299895bSThomas Huth     report(!try_transaction(), "TSX_CTRL causes transactions to abort");
546163f75dSPaolo Bonzini 
556163f75dSPaolo Bonzini     wrmsr(MSR_IA32_TSX_CTRL, 0);
56a299895bSThomas Huth     report(try_transaction(), "TSX_CTRL=0 causes transactions to succeed");
576163f75dSPaolo Bonzini 
586163f75dSPaolo Bonzini     return report_summary();
596163f75dSPaolo Bonzini }
606163f75dSPaolo Bonzini 
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