1 #include "libcflat.h" 2 #include "desc.h" 3 #include "apic-defs.h" 4 #include "apic.h" 5 #include "processor.h" 6 #include "vm.h" 7 8 #define MAIN_TSS_SEL (FIRST_SPARE_SEL + 0) 9 #define VM86_TSS_SEL (FIRST_SPARE_SEL + 8) 10 #define CONFORM_CS_SEL (FIRST_SPARE_SEL + 16) 11 12 static volatile int test_count; 13 static volatile unsigned int test_divider; 14 15 static char *fault_addr; 16 static ulong fault_phys; 17 18 static inline void io_delay(void) 19 { 20 } 21 22 static void nmi_tss(void) 23 { 24 start: 25 printf("NMI task is running\n"); 26 print_current_tss_info(); 27 test_count++; 28 asm volatile ("iret"); 29 goto start; 30 } 31 32 static void de_tss(void) 33 { 34 start: 35 printf("DE task is running\n"); 36 print_current_tss_info(); 37 test_divider = 10; 38 test_count++; 39 asm volatile ("iret"); 40 goto start; 41 } 42 43 static void of_tss(void) 44 { 45 start: 46 printf("OF task is running\n"); 47 print_current_tss_info(); 48 test_count++; 49 asm volatile ("iret"); 50 goto start; 51 } 52 53 static void bp_tss(void) 54 { 55 start: 56 printf("BP task is running\n"); 57 print_current_tss_info(); 58 test_count++; 59 asm volatile ("iret"); 60 goto start; 61 } 62 63 void do_pf_tss(ulong *error_code) 64 { 65 printf("PF task is running %x %x\n", error_code, *(ulong*)error_code); 66 print_current_tss_info(); 67 if (*(ulong*)error_code == 0x2) /* write access, not present */ 68 test_count++; 69 install_pte(phys_to_virt(read_cr3()), 1, fault_addr, 70 fault_phys | PTE_PRESENT | PTE_WRITE, 0); 71 } 72 73 extern void pf_tss(void); 74 75 asm ( 76 "pf_tss: \n\t" 77 "push %esp \n\t" 78 "call do_pf_tss \n\t" 79 "add $4, %esp \n\t" 80 "iret\n\t" 81 "jmp pf_tss\n\t" 82 ); 83 84 static void jmp_tss(void) 85 { 86 start: 87 printf("JMP to task succeeded\n"); 88 print_current_tss_info(); 89 test_count++; 90 asm volatile ("ljmp $" xstr(TSS_MAIN) ", $0"); 91 goto start; 92 } 93 94 static void irq_tss(void) 95 { 96 start: 97 printf("IRQ task is running\n"); 98 print_current_tss_info(); 99 test_count++; 100 asm volatile ("iret"); 101 test_count++; 102 printf("IRQ task restarts after iret.\n"); 103 goto start; 104 } 105 106 static void user_tss(void) 107 { 108 start: 109 test_count++; 110 asm volatile ("iret"); 111 goto start; 112 } 113 114 void test_kernel_mode_int() 115 { 116 unsigned int res; 117 118 /* test that int $2 triggers task gate */ 119 test_count = 0; 120 set_intr_task_gate(2, nmi_tss); 121 printf("Triggering nmi 2\n"); 122 asm volatile ("int $2"); 123 printf("Return from nmi %d\n", test_count); 124 report("NMI int $2", test_count == 1); 125 126 /* test that external NMI triggers task gate */ 127 test_count = 0; 128 set_intr_task_gate(2, nmi_tss); 129 printf("Triggering nmi through APIC\n"); 130 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_NMI | APIC_INT_ASSERT, 0); 131 io_delay(); 132 printf("Return from APIC nmi\n"); 133 report("NMI external", test_count == 1); 134 135 /* test that external interrupt triggesr task gate */ 136 test_count = 0; 137 printf("Trigger IRQ from APIC\n"); 138 set_intr_task_gate(0xf0, irq_tss); 139 irq_enable(); 140 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | APIC_DM_FIXED | APIC_INT_ASSERT | 0xf0, 0); 141 io_delay(); 142 irq_disable(); 143 printf("Return from APIC IRQ\n"); 144 report("IRQ external", test_count == 1); 145 146 /* test that HW exception triggesr task gate */ 147 set_intr_task_gate(0, de_tss); 148 printf("Try to devide by 0\n"); 149 asm volatile ("divl %3": "=a"(res) 150 : "d"(0), "a"(1500), "m"(test_divider)); 151 printf("Result is %d\n", res); 152 report("DE exeption", res == 150); 153 154 /* test if call HW exeption DE by int $0 triggers task gate */ 155 test_count = 0; 156 set_intr_task_gate(0, de_tss); 157 printf("Call int 0\n"); 158 asm volatile ("int $0"); 159 printf("Return from int 0\n"); 160 report("int $0", test_count == 1); 161 162 /* test if HW exception OF triggers task gate */ 163 test_count = 0; 164 set_intr_task_gate(4, of_tss); 165 printf("Call into\n"); 166 asm volatile ("addb $127, %b0\ninto"::"a"(127)); 167 printf("Return from into\n"); 168 report("OF exeption", test_count); 169 170 /* test if HW exception BP triggers task gate */ 171 test_count = 0; 172 set_intr_task_gate(3, bp_tss); 173 printf("Call int 3\n"); 174 asm volatile ("int $3"); 175 printf("Return from int 3\n"); 176 report("BP exeption", test_count == 1); 177 178 /* 179 * test that PF triggers task gate and error code is placed on 180 * exception task's stack 181 */ 182 fault_addr = alloc_vpage(); 183 fault_phys = (ulong)virt_to_phys(alloc_page()); 184 test_count = 0; 185 set_intr_task_gate(14, pf_tss); 186 printf("Access unmapped page\n"); 187 *fault_addr = 0; 188 printf("Return from pf tss\n"); 189 report("PF exeption", test_count == 1); 190 } 191 192 void test_gdt_task_gate(void) 193 { 194 /* test that calling a task by lcall works */ 195 test_count = 0; 196 tss_intr.eip = (u32)irq_tss; 197 printf("Calling task by lcall\n"); 198 /* hlt opcode is 0xf4 I use destination IP 0xf4f4f4f4 to catch 199 incorrect instruction length calculation */ 200 asm volatile("lcall $" xstr(TSS_INTR) ", $0xf4f4f4f4"); 201 printf("Return from call\n"); 202 report("lcall", test_count == 1); 203 204 /* call the same task again and check that it restarted after iret */ 205 test_count = 0; 206 asm volatile("lcall $" xstr(TSS_INTR) ", $0xf4f4f4f4"); 207 report("lcall2", test_count == 2); 208 209 /* test that calling a task by ljmp works */ 210 test_count = 0; 211 tss_intr.eip = (u32)jmp_tss; 212 printf("Jumping to a task by ljmp\n"); 213 asm volatile ("ljmp $" xstr(TSS_INTR) ", $0xf4f4f4f4"); 214 printf("Jump back succeeded\n"); 215 report("ljmp", test_count == 1); 216 } 217 218 void test_vm86_switch(void) 219 { 220 static tss32_t main_tss; 221 static tss32_t vm86_tss; 222 223 u8 *vm86_start; 224 225 /* Write a 'ud2' instruction somewhere below 1 MB */ 226 vm86_start = (void*) 0x42000; 227 vm86_start[0] = 0x0f; 228 vm86_start[1] = 0x0b; 229 230 /* Main TSS */ 231 set_gdt_entry(MAIN_TSS_SEL, (u32)&main_tss, sizeof(tss32_t) - 1, 0x89, 0); 232 ltr(MAIN_TSS_SEL); 233 main_tss = (tss32_t) { 234 .prev = VM86_TSS_SEL, 235 .cr3 = read_cr3(), 236 }; 237 238 /* VM86 TSS (marked as busy, so we can iret to it) */ 239 set_gdt_entry(VM86_TSS_SEL, (u32)&vm86_tss, sizeof(tss32_t) - 1, 0x8b, 0); 240 vm86_tss = (tss32_t) { 241 .eflags = 0x20002, 242 .cr3 = read_cr3(), 243 .eip = (u32) vm86_start & 0x0f, 244 .cs = (u32) vm86_start >> 4, 245 .ds = 0x1234, 246 .es = 0x2345, 247 }; 248 249 /* Setup task gate to main TSS for #UD */ 250 set_idt_task_gate(6, MAIN_TSS_SEL); 251 252 /* Jump into VM86 task with iret, #UD lets it come back immediately */ 253 printf("Switch to VM86 task and back\n"); 254 asm volatile( 255 "pushf\n" 256 "orw $0x4000, (%esp)\n" 257 "popf\n" 258 "iret\n" 259 ); 260 report("VM86", 1); 261 } 262 263 void test_conforming_switch(void) 264 { 265 /* test lcall with conforming segment, cs.dpl != cs.rpl */ 266 test_count = 0; 267 268 tss_intr.cs = CONFORM_CS_SEL | 3; 269 tss_intr.eip = (u32)user_tss; 270 tss_intr.ds = tss_intr.gs = tss_intr.fs = tss_intr.ss = USER_DS; 271 set_gdt_entry(CONFORM_CS_SEL, 0, 0xffffffff, 0x9f, 0xc0); 272 asm volatile("lcall $" xstr(TSS_INTR) ", $0xf4f4f4f4"); 273 report("lcall with cs.rpl != cs.dpl", test_count == 1); 274 } 275 276 int main() 277 { 278 setup_vm(); 279 setup_idt(); 280 setup_tss32(); 281 282 test_gdt_task_gate(); 283 test_kernel_mode_int(); 284 test_vm86_switch(); 285 test_conforming_switch(); 286 287 return report_summary(); 288 } 289