1 #ifndef X86_SVM_H 2 #define X86_SVM_H 3 4 #include "libcflat.h" 5 6 enum { 7 INTERCEPT_INTR, 8 INTERCEPT_NMI, 9 INTERCEPT_SMI, 10 INTERCEPT_INIT, 11 INTERCEPT_VINTR, 12 INTERCEPT_SELECTIVE_CR0, 13 INTERCEPT_STORE_IDTR, 14 INTERCEPT_STORE_GDTR, 15 INTERCEPT_STORE_LDTR, 16 INTERCEPT_STORE_TR, 17 INTERCEPT_LOAD_IDTR, 18 INTERCEPT_LOAD_GDTR, 19 INTERCEPT_LOAD_LDTR, 20 INTERCEPT_LOAD_TR, 21 INTERCEPT_RDTSC, 22 INTERCEPT_RDPMC, 23 INTERCEPT_PUSHF, 24 INTERCEPT_POPF, 25 INTERCEPT_CPUID, 26 INTERCEPT_RSM, 27 INTERCEPT_IRET, 28 INTERCEPT_INTn, 29 INTERCEPT_INVD, 30 INTERCEPT_PAUSE, 31 INTERCEPT_HLT, 32 INTERCEPT_INVLPG, 33 INTERCEPT_INVLPGA, 34 INTERCEPT_IOIO_PROT, 35 INTERCEPT_MSR_PROT, 36 INTERCEPT_TASK_SWITCH, 37 INTERCEPT_FERR_FREEZE, 38 INTERCEPT_SHUTDOWN, 39 INTERCEPT_VMRUN, 40 INTERCEPT_VMMCALL, 41 INTERCEPT_VMLOAD, 42 INTERCEPT_VMSAVE, 43 INTERCEPT_STGI, 44 INTERCEPT_CLGI, 45 INTERCEPT_SKINIT, 46 INTERCEPT_RDTSCP, 47 INTERCEPT_ICEBP, 48 INTERCEPT_WBINVD, 49 INTERCEPT_MONITOR, 50 INTERCEPT_MWAIT, 51 INTERCEPT_MWAIT_COND, 52 }; 53 54 enum { 55 VMCB_CLEAN_INTERCEPTS = 1, /* Intercept vectors, TSC offset, pause filter count */ 56 VMCB_CLEAN_PERM_MAP = 2, /* IOPM Base and MSRPM Base */ 57 VMCB_CLEAN_ASID = 4, /* ASID */ 58 VMCB_CLEAN_INTR = 8, /* int_ctl, int_vector */ 59 VMCB_CLEAN_NPT = 16, /* npt_en, nCR3, gPAT */ 60 VMCB_CLEAN_CR = 32, /* CR0, CR3, CR4, EFER */ 61 VMCB_CLEAN_DR = 64, /* DR6, DR7 */ 62 VMCB_CLEAN_DT = 128, /* GDT, IDT */ 63 VMCB_CLEAN_SEG = 256, /* CS, DS, SS, ES, CPL */ 64 VMCB_CLEAN_CR2 = 512, /* CR2 only */ 65 VMCB_CLEAN_LBR = 1024, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */ 66 VMCB_CLEAN_AVIC = 2048, /* APIC_BAR, APIC_BACKING_PAGE, 67 PHYSICAL_TABLE pointer, LOGICAL_TABLE pointer */ 68 VMCB_CLEAN_ALL = 4095, 69 }; 70 71 struct __attribute__ ((__packed__)) vmcb_control_area { 72 u16 intercept_cr_read; 73 u16 intercept_cr_write; 74 u16 intercept_dr_read; 75 u16 intercept_dr_write; 76 u32 intercept_exceptions; 77 u64 intercept; 78 u8 reserved_1[40]; 79 u16 pause_filter_thresh; 80 u16 pause_filter_count; 81 u64 iopm_base_pa; 82 u64 msrpm_base_pa; 83 u64 tsc_offset; 84 u32 asid; 85 u8 tlb_ctl; 86 u8 reserved_2[3]; 87 u32 int_ctl; 88 u32 int_vector; 89 u32 int_state; 90 u8 reserved_3[4]; 91 u32 exit_code; 92 u32 exit_code_hi; 93 u64 exit_info_1; 94 u64 exit_info_2; 95 u32 exit_int_info; 96 u32 exit_int_info_err; 97 u64 nested_ctl; 98 u8 reserved_4[16]; 99 u32 event_inj; 100 u32 event_inj_err; 101 u64 nested_cr3; 102 u64 virt_ext; 103 u32 clean; 104 u32 reserved_5; 105 u64 next_rip; 106 u8 insn_len; 107 u8 insn_bytes[15]; 108 u8 reserved_6[800]; 109 }; 110 111 #define TLB_CONTROL_DO_NOTHING 0 112 #define TLB_CONTROL_FLUSH_ALL_ASID 1 113 114 #define V_TPR_MASK 0x0f 115 116 #define V_IRQ_SHIFT 8 117 #define V_IRQ_MASK (1 << V_IRQ_SHIFT) 118 119 #define V_GIF_ENABLED_SHIFT 25 120 #define V_GIF_ENABLED_MASK (1 << V_GIF_ENABLED_SHIFT) 121 122 #define V_GIF_SHIFT 9 123 #define V_GIF_MASK (1 << V_GIF_SHIFT) 124 125 #define V_INTR_PRIO_SHIFT 16 126 #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT) 127 128 #define V_IGN_TPR_SHIFT 20 129 #define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT) 130 131 #define V_INTR_MASKING_SHIFT 24 132 #define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT) 133 134 #define SVM_INTERRUPT_SHADOW_MASK 1 135 136 #define SVM_IOIO_STR_SHIFT 2 137 #define SVM_IOIO_REP_SHIFT 3 138 #define SVM_IOIO_SIZE_SHIFT 4 139 #define SVM_IOIO_ASIZE_SHIFT 7 140 141 #define SVM_IOIO_TYPE_MASK 1 142 #define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT) 143 #define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT) 144 #define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT) 145 #define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT) 146 147 #define SVM_VM_CR_VALID_MASK 0x001fULL 148 #define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL 149 #define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL 150 151 #define TSC_RATIO_DEFAULT 0x0100000000ULL 152 153 struct __attribute__ ((__packed__)) vmcb_seg { 154 u16 selector; 155 u16 attrib; 156 u32 limit; 157 u64 base; 158 }; 159 160 struct __attribute__ ((__packed__)) vmcb_save_area { 161 struct vmcb_seg es; 162 struct vmcb_seg cs; 163 struct vmcb_seg ss; 164 struct vmcb_seg ds; 165 struct vmcb_seg fs; 166 struct vmcb_seg gs; 167 struct vmcb_seg gdtr; 168 struct vmcb_seg ldtr; 169 struct vmcb_seg idtr; 170 struct vmcb_seg tr; 171 u8 reserved_1[43]; 172 u8 cpl; 173 u8 reserved_2[4]; 174 u64 efer; 175 u8 reserved_3[112]; 176 u64 cr4; 177 u64 cr3; 178 u64 cr0; 179 u64 dr7; 180 u64 dr6; 181 u64 rflags; 182 u64 rip; 183 u8 reserved_4[88]; 184 u64 rsp; 185 u8 reserved_5[24]; 186 u64 rax; 187 u64 star; 188 u64 lstar; 189 u64 cstar; 190 u64 sfmask; 191 u64 kernel_gs_base; 192 u64 sysenter_cs; 193 u64 sysenter_esp; 194 u64 sysenter_eip; 195 u64 cr2; 196 u8 reserved_6[32]; 197 u64 g_pat; 198 u64 dbgctl; 199 u64 br_from; 200 u64 br_to; 201 u64 last_excp_from; 202 u64 last_excp_to; 203 }; 204 205 struct __attribute__ ((__packed__)) vmcb { 206 struct vmcb_control_area control; 207 struct vmcb_save_area save; 208 }; 209 210 #define SVM_CPUID_FEATURE_SHIFT 2 211 #define SVM_CPUID_FUNC 0x8000000a 212 213 #define SVM_VM_CR_SVM_DISABLE 4 214 215 #define SVM_SELECTOR_S_SHIFT 4 216 #define SVM_SELECTOR_DPL_SHIFT 5 217 #define SVM_SELECTOR_P_SHIFT 7 218 #define SVM_SELECTOR_AVL_SHIFT 8 219 #define SVM_SELECTOR_L_SHIFT 9 220 #define SVM_SELECTOR_DB_SHIFT 10 221 #define SVM_SELECTOR_G_SHIFT 11 222 223 #define SVM_SELECTOR_TYPE_MASK (0xf) 224 #define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT) 225 #define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT) 226 #define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT) 227 #define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT) 228 #define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT) 229 #define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT) 230 #define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT) 231 232 #define SVM_SELECTOR_WRITE_MASK (1 << 1) 233 #define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK 234 #define SVM_SELECTOR_CODE_MASK (1 << 3) 235 236 #define INTERCEPT_CR0_MASK 1 237 #define INTERCEPT_CR3_MASK (1 << 3) 238 #define INTERCEPT_CR4_MASK (1 << 4) 239 #define INTERCEPT_CR8_MASK (1 << 8) 240 241 #define INTERCEPT_DR0_MASK 1 242 #define INTERCEPT_DR1_MASK (1 << 1) 243 #define INTERCEPT_DR2_MASK (1 << 2) 244 #define INTERCEPT_DR3_MASK (1 << 3) 245 #define INTERCEPT_DR4_MASK (1 << 4) 246 #define INTERCEPT_DR5_MASK (1 << 5) 247 #define INTERCEPT_DR6_MASK (1 << 6) 248 #define INTERCEPT_DR7_MASK (1 << 7) 249 250 #define SVM_EVTINJ_VEC_MASK 0xff 251 252 #define SVM_EVTINJ_TYPE_SHIFT 8 253 #define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT) 254 255 #define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT) 256 #define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT) 257 #define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT) 258 #define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT) 259 260 #define SVM_EVTINJ_VALID (1 << 31) 261 #define SVM_EVTINJ_VALID_ERR (1 << 11) 262 263 #define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK 264 #define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK 265 266 #define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR 267 #define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI 268 #define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT 269 #define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT 270 271 #define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID 272 #define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR 273 274 #define SVM_EXITINFOSHIFT_TS_REASON_IRET 36 275 #define SVM_EXITINFOSHIFT_TS_REASON_JMP 38 276 #define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44 277 278 #define SVM_EXIT_READ_CR0 0x000 279 #define SVM_EXIT_READ_CR3 0x003 280 #define SVM_EXIT_READ_CR4 0x004 281 #define SVM_EXIT_READ_CR8 0x008 282 #define SVM_EXIT_WRITE_CR0 0x010 283 #define SVM_EXIT_WRITE_CR3 0x013 284 #define SVM_EXIT_WRITE_CR4 0x014 285 #define SVM_EXIT_WRITE_CR8 0x018 286 #define SVM_EXIT_READ_DR0 0x020 287 #define SVM_EXIT_READ_DR1 0x021 288 #define SVM_EXIT_READ_DR2 0x022 289 #define SVM_EXIT_READ_DR3 0x023 290 #define SVM_EXIT_READ_DR4 0x024 291 #define SVM_EXIT_READ_DR5 0x025 292 #define SVM_EXIT_READ_DR6 0x026 293 #define SVM_EXIT_READ_DR7 0x027 294 #define SVM_EXIT_WRITE_DR0 0x030 295 #define SVM_EXIT_WRITE_DR1 0x031 296 #define SVM_EXIT_WRITE_DR2 0x032 297 #define SVM_EXIT_WRITE_DR3 0x033 298 #define SVM_EXIT_WRITE_DR4 0x034 299 #define SVM_EXIT_WRITE_DR5 0x035 300 #define SVM_EXIT_WRITE_DR6 0x036 301 #define SVM_EXIT_WRITE_DR7 0x037 302 #define SVM_EXIT_EXCP_BASE 0x040 303 #define SVM_EXIT_INTR 0x060 304 #define SVM_EXIT_NMI 0x061 305 #define SVM_EXIT_SMI 0x062 306 #define SVM_EXIT_INIT 0x063 307 #define SVM_EXIT_VINTR 0x064 308 #define SVM_EXIT_CR0_SEL_WRITE 0x065 309 #define SVM_EXIT_IDTR_READ 0x066 310 #define SVM_EXIT_GDTR_READ 0x067 311 #define SVM_EXIT_LDTR_READ 0x068 312 #define SVM_EXIT_TR_READ 0x069 313 #define SVM_EXIT_IDTR_WRITE 0x06a 314 #define SVM_EXIT_GDTR_WRITE 0x06b 315 #define SVM_EXIT_LDTR_WRITE 0x06c 316 #define SVM_EXIT_TR_WRITE 0x06d 317 #define SVM_EXIT_RDTSC 0x06e 318 #define SVM_EXIT_RDPMC 0x06f 319 #define SVM_EXIT_PUSHF 0x070 320 #define SVM_EXIT_POPF 0x071 321 #define SVM_EXIT_CPUID 0x072 322 #define SVM_EXIT_RSM 0x073 323 #define SVM_EXIT_IRET 0x074 324 #define SVM_EXIT_SWINT 0x075 325 #define SVM_EXIT_INVD 0x076 326 #define SVM_EXIT_PAUSE 0x077 327 #define SVM_EXIT_HLT 0x078 328 #define SVM_EXIT_INVLPG 0x079 329 #define SVM_EXIT_INVLPGA 0x07a 330 #define SVM_EXIT_IOIO 0x07b 331 #define SVM_EXIT_MSR 0x07c 332 #define SVM_EXIT_TASK_SWITCH 0x07d 333 #define SVM_EXIT_FERR_FREEZE 0x07e 334 #define SVM_EXIT_SHUTDOWN 0x07f 335 #define SVM_EXIT_VMRUN 0x080 336 #define SVM_EXIT_VMMCALL 0x081 337 #define SVM_EXIT_VMLOAD 0x082 338 #define SVM_EXIT_VMSAVE 0x083 339 #define SVM_EXIT_STGI 0x084 340 #define SVM_EXIT_CLGI 0x085 341 #define SVM_EXIT_SKINIT 0x086 342 #define SVM_EXIT_RDTSCP 0x087 343 #define SVM_EXIT_ICEBP 0x088 344 #define SVM_EXIT_WBINVD 0x089 345 #define SVM_EXIT_MONITOR 0x08a 346 #define SVM_EXIT_MWAIT 0x08b 347 #define SVM_EXIT_MWAIT_COND 0x08c 348 #define SVM_EXIT_NPF 0x400 349 350 #define SVM_EXIT_ERR -1 351 352 #define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP) 353 354 #define SVM_CR0_RESERVED_MASK 0xffffffff00000000U 355 #define SVM_CR3_LONG_MBZ_MASK 0xfff0000000000000U 356 #define SVM_CR3_LONG_RESERVED_MASK 0x0000000000000fe7U 357 #define SVM_CR3_PAE_LEGACY_RESERVED_MASK 0x0000000000000007U 358 #define SVM_CR4_LEGACY_RESERVED_MASK 0xff08e000U 359 #define SVM_CR4_RESERVED_MASK 0xffffffffff08e000U 360 #define SVM_DR6_RESERVED_MASK 0xffffffffffff1ff0U 361 #define SVM_DR7_RESERVED_MASK 0xffffffff0000cc00U 362 #define SVM_EFER_RESERVED_MASK 0xffffffffffff0200U 363 364 #define MSR_BITMAP_SIZE 8192 365 366 #define LBR_CTL_ENABLE_MASK BIT_ULL(0) 367 368 struct svm_test { 369 const char *name; 370 bool (*supported)(void); 371 void (*prepare)(struct svm_test *test); 372 void (*prepare_gif_clear)(struct svm_test *test); 373 void (*guest_func)(struct svm_test *test); 374 bool (*finished)(struct svm_test *test); 375 bool (*succeeded)(struct svm_test *test); 376 int exits; 377 ulong scratch; 378 /* Alternative test interface. */ 379 void (*v2)(void); 380 int on_vcpu; 381 bool on_vcpu_done; 382 }; 383 384 struct regs { 385 u64 rax; 386 u64 rbx; 387 u64 rcx; 388 u64 rdx; 389 u64 cr2; 390 u64 rbp; 391 u64 rsi; 392 u64 rdi; 393 u64 r8; 394 u64 r9; 395 u64 r10; 396 u64 r11; 397 u64 r12; 398 u64 r13; 399 u64 r14; 400 u64 r15; 401 u64 rflags; 402 }; 403 404 typedef void (*test_guest_func)(struct svm_test *); 405 406 int run_svm_tests(int ac, char **av, struct svm_test *svm_tests); 407 u64 *npt_get_pte(u64 address); 408 u64 *npt_get_pde(u64 address); 409 u64 *npt_get_pdpe(u64 address); 410 u64 *npt_get_pml4e(void); 411 bool smp_supported(void); 412 bool default_supported(void); 413 bool vgif_supported(void); 414 bool lbrv_supported(void); 415 bool tsc_scale_supported(void); 416 bool pause_filter_supported(void); 417 bool pause_threshold_supported(void); 418 void default_prepare(struct svm_test *test); 419 void default_prepare_gif_clear(struct svm_test *test); 420 bool default_finished(struct svm_test *test); 421 bool npt_supported(void); 422 int get_test_stage(struct svm_test *test); 423 void set_test_stage(struct svm_test *test, int s); 424 void inc_test_stage(struct svm_test *test); 425 void vmcb_ident(struct vmcb *vmcb); 426 struct regs get_regs(void); 427 void vmmcall(void); 428 int __svm_vmrun(u64 rip); 429 void __svm_bare_vmrun(void); 430 int svm_vmrun(void); 431 void test_set_guest(test_guest_func func); 432 u64* get_npt_pte(u64 *pml4, u64 guest_addr, int level); 433 434 extern struct vmcb *vmcb; 435 436 static inline void stgi(void) 437 { 438 asm volatile ("stgi"); 439 } 440 441 static inline void clgi(void) 442 { 443 asm volatile ("clgi"); 444 } 445 446 447 448 #define SAVE_GPR_C \ 449 "xchg %%rbx, regs+0x8\n\t" \ 450 "xchg %%rcx, regs+0x10\n\t" \ 451 "xchg %%rdx, regs+0x18\n\t" \ 452 "xchg %%rbp, regs+0x28\n\t" \ 453 "xchg %%rsi, regs+0x30\n\t" \ 454 "xchg %%rdi, regs+0x38\n\t" \ 455 "xchg %%r8, regs+0x40\n\t" \ 456 "xchg %%r9, regs+0x48\n\t" \ 457 "xchg %%r10, regs+0x50\n\t" \ 458 "xchg %%r11, regs+0x58\n\t" \ 459 "xchg %%r12, regs+0x60\n\t" \ 460 "xchg %%r13, regs+0x68\n\t" \ 461 "xchg %%r14, regs+0x70\n\t" \ 462 "xchg %%r15, regs+0x78\n\t" 463 464 #define LOAD_GPR_C SAVE_GPR_C 465 466 #define ASM_PRE_VMRUN_CMD \ 467 "vmload %%rax\n\t" \ 468 "mov regs+0x80, %%r15\n\t" \ 469 "mov %%r15, 0x170(%%rax)\n\t" \ 470 "mov regs, %%r15\n\t" \ 471 "mov %%r15, 0x1f8(%%rax)\n\t" \ 472 LOAD_GPR_C \ 473 474 #define ASM_POST_VMRUN_CMD \ 475 SAVE_GPR_C \ 476 "mov 0x170(%%rax), %%r15\n\t" \ 477 "mov %%r15, regs+0x80\n\t" \ 478 "mov 0x1f8(%%rax), %%r15\n\t" \ 479 "mov %%r15, regs\n\t" \ 480 "vmsave %%rax\n\t" \ 481 482 483 484 #define SVM_BARE_VMRUN \ 485 asm volatile ( \ 486 ASM_PRE_VMRUN_CMD \ 487 "vmrun %%rax\n\t" \ 488 ASM_POST_VMRUN_CMD \ 489 : \ 490 : "a" (virt_to_phys(vmcb)) \ 491 : "memory", "r15") \ 492 493 #endif 494