1 #ifndef X86_SVM_H 2 #define X86_SVM_H 3 4 #include "libcflat.h" 5 6 enum { 7 INTERCEPT_INTR, 8 INTERCEPT_NMI, 9 INTERCEPT_SMI, 10 INTERCEPT_INIT, 11 INTERCEPT_VINTR, 12 INTERCEPT_SELECTIVE_CR0, 13 INTERCEPT_STORE_IDTR, 14 INTERCEPT_STORE_GDTR, 15 INTERCEPT_STORE_LDTR, 16 INTERCEPT_STORE_TR, 17 INTERCEPT_LOAD_IDTR, 18 INTERCEPT_LOAD_GDTR, 19 INTERCEPT_LOAD_LDTR, 20 INTERCEPT_LOAD_TR, 21 INTERCEPT_RDTSC, 22 INTERCEPT_RDPMC, 23 INTERCEPT_PUSHF, 24 INTERCEPT_POPF, 25 INTERCEPT_CPUID, 26 INTERCEPT_RSM, 27 INTERCEPT_IRET, 28 INTERCEPT_INTn, 29 INTERCEPT_INVD, 30 INTERCEPT_PAUSE, 31 INTERCEPT_HLT, 32 INTERCEPT_INVLPG, 33 INTERCEPT_INVLPGA, 34 INTERCEPT_IOIO_PROT, 35 INTERCEPT_MSR_PROT, 36 INTERCEPT_TASK_SWITCH, 37 INTERCEPT_FERR_FREEZE, 38 INTERCEPT_SHUTDOWN, 39 INTERCEPT_VMRUN, 40 INTERCEPT_VMMCALL, 41 INTERCEPT_VMLOAD, 42 INTERCEPT_VMSAVE, 43 INTERCEPT_STGI, 44 INTERCEPT_CLGI, 45 INTERCEPT_SKINIT, 46 INTERCEPT_RDTSCP, 47 INTERCEPT_ICEBP, 48 INTERCEPT_WBINVD, 49 INTERCEPT_MONITOR, 50 INTERCEPT_MWAIT, 51 INTERCEPT_MWAIT_COND, 52 }; 53 54 enum { 55 VMCB_CLEAN_INTERCEPTS = 1, /* Intercept vectors, TSC offset, pause filter count */ 56 VMCB_CLEAN_PERM_MAP = 2, /* IOPM Base and MSRPM Base */ 57 VMCB_CLEAN_ASID = 4, /* ASID */ 58 VMCB_CLEAN_INTR = 8, /* int_ctl, int_vector */ 59 VMCB_CLEAN_NPT = 16, /* npt_en, nCR3, gPAT */ 60 VMCB_CLEAN_CR = 32, /* CR0, CR3, CR4, EFER */ 61 VMCB_CLEAN_DR = 64, /* DR6, DR7 */ 62 VMCB_CLEAN_DT = 128, /* GDT, IDT */ 63 VMCB_CLEAN_SEG = 256, /* CS, DS, SS, ES, CPL */ 64 VMCB_CLEAN_CR2 = 512, /* CR2 only */ 65 VMCB_CLEAN_LBR = 1024, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */ 66 VMCB_CLEAN_AVIC = 2048, /* APIC_BAR, APIC_BACKING_PAGE, 67 PHYSICAL_TABLE pointer, LOGICAL_TABLE pointer */ 68 VMCB_CLEAN_ALL = 4095, 69 }; 70 71 struct __attribute__ ((__packed__)) vmcb_control_area { 72 u16 intercept_cr_read; 73 u16 intercept_cr_write; 74 u16 intercept_dr_read; 75 u16 intercept_dr_write; 76 u32 intercept_exceptions; 77 u64 intercept; 78 u8 reserved_1[42]; 79 u16 pause_filter_count; 80 u64 iopm_base_pa; 81 u64 msrpm_base_pa; 82 u64 tsc_offset; 83 u32 asid; 84 u8 tlb_ctl; 85 u8 reserved_2[3]; 86 u32 int_ctl; 87 u32 int_vector; 88 u32 int_state; 89 u8 reserved_3[4]; 90 u32 exit_code; 91 u32 exit_code_hi; 92 u64 exit_info_1; 93 u64 exit_info_2; 94 u32 exit_int_info; 95 u32 exit_int_info_err; 96 u64 nested_ctl; 97 u8 reserved_4[16]; 98 u32 event_inj; 99 u32 event_inj_err; 100 u64 nested_cr3; 101 u64 lbr_ctl; 102 u32 clean; 103 u32 reserved_5; 104 u64 next_rip; 105 u8 insn_len; 106 u8 insn_bytes[15]; 107 u8 reserved_6[800]; 108 }; 109 110 #define TLB_CONTROL_DO_NOTHING 0 111 #define TLB_CONTROL_FLUSH_ALL_ASID 1 112 113 #define V_TPR_MASK 0x0f 114 115 #define V_IRQ_SHIFT 8 116 #define V_IRQ_MASK (1 << V_IRQ_SHIFT) 117 118 #define V_GIF_ENABLED_SHIFT 25 119 #define V_GIF_ENABLED_MASK (1 << V_GIF_ENABLED_SHIFT) 120 121 #define V_GIF_SHIFT 9 122 #define V_GIF_MASK (1 << V_GIF_SHIFT) 123 124 #define V_INTR_PRIO_SHIFT 16 125 #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT) 126 127 #define V_IGN_TPR_SHIFT 20 128 #define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT) 129 130 #define V_INTR_MASKING_SHIFT 24 131 #define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT) 132 133 #define SVM_INTERRUPT_SHADOW_MASK 1 134 135 #define SVM_IOIO_STR_SHIFT 2 136 #define SVM_IOIO_REP_SHIFT 3 137 #define SVM_IOIO_SIZE_SHIFT 4 138 #define SVM_IOIO_ASIZE_SHIFT 7 139 140 #define SVM_IOIO_TYPE_MASK 1 141 #define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT) 142 #define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT) 143 #define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT) 144 #define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT) 145 146 #define SVM_VM_CR_VALID_MASK 0x001fULL 147 #define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL 148 #define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL 149 150 struct __attribute__ ((__packed__)) vmcb_seg { 151 u16 selector; 152 u16 attrib; 153 u32 limit; 154 u64 base; 155 }; 156 157 struct __attribute__ ((__packed__)) vmcb_save_area { 158 struct vmcb_seg es; 159 struct vmcb_seg cs; 160 struct vmcb_seg ss; 161 struct vmcb_seg ds; 162 struct vmcb_seg fs; 163 struct vmcb_seg gs; 164 struct vmcb_seg gdtr; 165 struct vmcb_seg ldtr; 166 struct vmcb_seg idtr; 167 struct vmcb_seg tr; 168 u8 reserved_1[43]; 169 u8 cpl; 170 u8 reserved_2[4]; 171 u64 efer; 172 u8 reserved_3[112]; 173 u64 cr4; 174 u64 cr3; 175 u64 cr0; 176 u64 dr7; 177 u64 dr6; 178 u64 rflags; 179 u64 rip; 180 u8 reserved_4[88]; 181 u64 rsp; 182 u8 reserved_5[24]; 183 u64 rax; 184 u64 star; 185 u64 lstar; 186 u64 cstar; 187 u64 sfmask; 188 u64 kernel_gs_base; 189 u64 sysenter_cs; 190 u64 sysenter_esp; 191 u64 sysenter_eip; 192 u64 cr2; 193 u8 reserved_6[32]; 194 u64 g_pat; 195 u64 dbgctl; 196 u64 br_from; 197 u64 br_to; 198 u64 last_excp_from; 199 u64 last_excp_to; 200 }; 201 202 struct __attribute__ ((__packed__)) vmcb { 203 struct vmcb_control_area control; 204 struct vmcb_save_area save; 205 }; 206 207 #define SVM_CPUID_FEATURE_SHIFT 2 208 #define SVM_CPUID_FUNC 0x8000000a 209 210 #define SVM_VM_CR_SVM_DISABLE 4 211 212 #define SVM_SELECTOR_S_SHIFT 4 213 #define SVM_SELECTOR_DPL_SHIFT 5 214 #define SVM_SELECTOR_P_SHIFT 7 215 #define SVM_SELECTOR_AVL_SHIFT 8 216 #define SVM_SELECTOR_L_SHIFT 9 217 #define SVM_SELECTOR_DB_SHIFT 10 218 #define SVM_SELECTOR_G_SHIFT 11 219 220 #define SVM_SELECTOR_TYPE_MASK (0xf) 221 #define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT) 222 #define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT) 223 #define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT) 224 #define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT) 225 #define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT) 226 #define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT) 227 #define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT) 228 229 #define SVM_SELECTOR_WRITE_MASK (1 << 1) 230 #define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK 231 #define SVM_SELECTOR_CODE_MASK (1 << 3) 232 233 #define INTERCEPT_CR0_MASK 1 234 #define INTERCEPT_CR3_MASK (1 << 3) 235 #define INTERCEPT_CR4_MASK (1 << 4) 236 #define INTERCEPT_CR8_MASK (1 << 8) 237 238 #define INTERCEPT_DR0_MASK 1 239 #define INTERCEPT_DR1_MASK (1 << 1) 240 #define INTERCEPT_DR2_MASK (1 << 2) 241 #define INTERCEPT_DR3_MASK (1 << 3) 242 #define INTERCEPT_DR4_MASK (1 << 4) 243 #define INTERCEPT_DR5_MASK (1 << 5) 244 #define INTERCEPT_DR6_MASK (1 << 6) 245 #define INTERCEPT_DR7_MASK (1 << 7) 246 247 #define SVM_EVTINJ_VEC_MASK 0xff 248 249 #define SVM_EVTINJ_TYPE_SHIFT 8 250 #define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT) 251 252 #define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT) 253 #define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT) 254 #define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT) 255 #define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT) 256 257 #define SVM_EVTINJ_VALID (1 << 31) 258 #define SVM_EVTINJ_VALID_ERR (1 << 11) 259 260 #define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK 261 #define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK 262 263 #define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR 264 #define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI 265 #define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT 266 #define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT 267 268 #define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID 269 #define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR 270 271 #define SVM_EXITINFOSHIFT_TS_REASON_IRET 36 272 #define SVM_EXITINFOSHIFT_TS_REASON_JMP 38 273 #define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44 274 275 #define SVM_EXIT_READ_CR0 0x000 276 #define SVM_EXIT_READ_CR3 0x003 277 #define SVM_EXIT_READ_CR4 0x004 278 #define SVM_EXIT_READ_CR8 0x008 279 #define SVM_EXIT_WRITE_CR0 0x010 280 #define SVM_EXIT_WRITE_CR3 0x013 281 #define SVM_EXIT_WRITE_CR4 0x014 282 #define SVM_EXIT_WRITE_CR8 0x018 283 #define SVM_EXIT_READ_DR0 0x020 284 #define SVM_EXIT_READ_DR1 0x021 285 #define SVM_EXIT_READ_DR2 0x022 286 #define SVM_EXIT_READ_DR3 0x023 287 #define SVM_EXIT_READ_DR4 0x024 288 #define SVM_EXIT_READ_DR5 0x025 289 #define SVM_EXIT_READ_DR6 0x026 290 #define SVM_EXIT_READ_DR7 0x027 291 #define SVM_EXIT_WRITE_DR0 0x030 292 #define SVM_EXIT_WRITE_DR1 0x031 293 #define SVM_EXIT_WRITE_DR2 0x032 294 #define SVM_EXIT_WRITE_DR3 0x033 295 #define SVM_EXIT_WRITE_DR4 0x034 296 #define SVM_EXIT_WRITE_DR5 0x035 297 #define SVM_EXIT_WRITE_DR6 0x036 298 #define SVM_EXIT_WRITE_DR7 0x037 299 #define SVM_EXIT_EXCP_BASE 0x040 300 #define SVM_EXIT_INTR 0x060 301 #define SVM_EXIT_NMI 0x061 302 #define SVM_EXIT_SMI 0x062 303 #define SVM_EXIT_INIT 0x063 304 #define SVM_EXIT_VINTR 0x064 305 #define SVM_EXIT_CR0_SEL_WRITE 0x065 306 #define SVM_EXIT_IDTR_READ 0x066 307 #define SVM_EXIT_GDTR_READ 0x067 308 #define SVM_EXIT_LDTR_READ 0x068 309 #define SVM_EXIT_TR_READ 0x069 310 #define SVM_EXIT_IDTR_WRITE 0x06a 311 #define SVM_EXIT_GDTR_WRITE 0x06b 312 #define SVM_EXIT_LDTR_WRITE 0x06c 313 #define SVM_EXIT_TR_WRITE 0x06d 314 #define SVM_EXIT_RDTSC 0x06e 315 #define SVM_EXIT_RDPMC 0x06f 316 #define SVM_EXIT_PUSHF 0x070 317 #define SVM_EXIT_POPF 0x071 318 #define SVM_EXIT_CPUID 0x072 319 #define SVM_EXIT_RSM 0x073 320 #define SVM_EXIT_IRET 0x074 321 #define SVM_EXIT_SWINT 0x075 322 #define SVM_EXIT_INVD 0x076 323 #define SVM_EXIT_PAUSE 0x077 324 #define SVM_EXIT_HLT 0x078 325 #define SVM_EXIT_INVLPG 0x079 326 #define SVM_EXIT_INVLPGA 0x07a 327 #define SVM_EXIT_IOIO 0x07b 328 #define SVM_EXIT_MSR 0x07c 329 #define SVM_EXIT_TASK_SWITCH 0x07d 330 #define SVM_EXIT_FERR_FREEZE 0x07e 331 #define SVM_EXIT_SHUTDOWN 0x07f 332 #define SVM_EXIT_VMRUN 0x080 333 #define SVM_EXIT_VMMCALL 0x081 334 #define SVM_EXIT_VMLOAD 0x082 335 #define SVM_EXIT_VMSAVE 0x083 336 #define SVM_EXIT_STGI 0x084 337 #define SVM_EXIT_CLGI 0x085 338 #define SVM_EXIT_SKINIT 0x086 339 #define SVM_EXIT_RDTSCP 0x087 340 #define SVM_EXIT_ICEBP 0x088 341 #define SVM_EXIT_WBINVD 0x089 342 #define SVM_EXIT_MONITOR 0x08a 343 #define SVM_EXIT_MWAIT 0x08b 344 #define SVM_EXIT_MWAIT_COND 0x08c 345 #define SVM_EXIT_NPF 0x400 346 347 #define SVM_EXIT_ERR -1 348 349 #define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP) 350 351 #define SVM_CR0_RESERVED_MASK 0xffffffff00000000U 352 #define SVM_CR3_LONG_MBZ_MASK 0xfff0000000000000U 353 #define SVM_CR3_LONG_RESERVED_MASK 0x0000000000000fe7U 354 #define SVM_CR3_PAE_LEGACY_RESERVED_MASK 0x0000000000000007U 355 #define SVM_CR4_LEGACY_RESERVED_MASK 0xff08e000U 356 #define SVM_CR4_RESERVED_MASK 0xffffffffff08e000U 357 #define SVM_DR6_RESERVED_MASK 0xffffffffffff1ff0U 358 #define SVM_DR7_RESERVED_MASK 0xffffffff0000cc00U 359 #define SVM_EFER_RESERVED_MASK 0xffffffffffff0200U 360 361 #define MSR_BITMAP_SIZE 8192 362 363 struct svm_test { 364 const char *name; 365 bool (*supported)(void); 366 void (*prepare)(struct svm_test *test); 367 void (*prepare_gif_clear)(struct svm_test *test); 368 void (*guest_func)(struct svm_test *test); 369 bool (*finished)(struct svm_test *test); 370 bool (*succeeded)(struct svm_test *test); 371 int exits; 372 ulong scratch; 373 /* Alternative test interface. */ 374 void (*v2)(void); 375 int on_vcpu; 376 bool on_vcpu_done; 377 }; 378 379 struct regs { 380 u64 rax; 381 u64 rbx; 382 u64 rcx; 383 u64 rdx; 384 u64 cr2; 385 u64 rbp; 386 u64 rsi; 387 u64 rdi; 388 u64 r8; 389 u64 r9; 390 u64 r10; 391 u64 r11; 392 u64 r12; 393 u64 r13; 394 u64 r14; 395 u64 r15; 396 u64 rflags; 397 }; 398 399 typedef void (*test_guest_func)(struct svm_test *); 400 401 u64 *npt_get_pte(u64 address); 402 u64 *npt_get_pde(u64 address); 403 u64 *npt_get_pdpe(void); 404 u64 *npt_get_pml4e(void); 405 bool smp_supported(void); 406 bool default_supported(void); 407 bool vgif_supported(void); 408 void default_prepare(struct svm_test *test); 409 void default_prepare_gif_clear(struct svm_test *test); 410 bool default_finished(struct svm_test *test); 411 bool npt_supported(void); 412 int get_test_stage(struct svm_test *test); 413 void set_test_stage(struct svm_test *test, int s); 414 void inc_test_stage(struct svm_test *test); 415 void vmcb_ident(struct vmcb *vmcb); 416 struct regs get_regs(void); 417 void vmmcall(void); 418 int __svm_vmrun(u64 rip); 419 int svm_vmrun(void); 420 void test_set_guest(test_guest_func func); 421 422 extern struct vmcb *vmcb; 423 extern struct svm_test svm_tests[]; 424 425 #endif 426