1 2 #include "x86/msr.h" 3 #include "x86/processor.h" 4 #include "x86/apic-defs.h" 5 #include "x86/apic.h" 6 #include "x86/desc.h" 7 #include "x86/isr.h" 8 #include "x86/vm.h" 9 10 #include "libcflat.h" 11 #include <stdint.h> 12 13 #define FIXED_CNT_INDEX 32 14 #define PC_VECTOR 32 15 16 #define EVNSEL_EVENT_SHIFT 0 17 #define EVNTSEL_UMASK_SHIFT 8 18 #define EVNTSEL_USR_SHIFT 16 19 #define EVNTSEL_OS_SHIFT 17 20 #define EVNTSEL_EDGE_SHIFT 18 21 #define EVNTSEL_PC_SHIFT 19 22 #define EVNTSEL_INT_SHIFT 20 23 #define EVNTSEL_EN_SHIF 22 24 #define EVNTSEL_INV_SHIF 23 25 #define EVNTSEL_CMASK_SHIFT 24 26 27 #define EVNTSEL_EN (1 << EVNTSEL_EN_SHIF) 28 #define EVNTSEL_USR (1 << EVNTSEL_USR_SHIFT) 29 #define EVNTSEL_OS (1 << EVNTSEL_OS_SHIFT) 30 #define EVNTSEL_PC (1 << EVNTSEL_PC_SHIFT) 31 #define EVNTSEL_INT (1 << EVNTSEL_INT_SHIFT) 32 #define EVNTSEL_INV (1 << EVNTSEL_INV_SHIF) 33 34 #define N 1000000 35 36 typedef struct { 37 uint32_t ctr; 38 uint32_t config; 39 uint64_t count; 40 int idx; 41 } pmu_counter_t; 42 43 union cpuid10_eax { 44 struct { 45 unsigned int version_id:8; 46 unsigned int num_counters:8; 47 unsigned int bit_width:8; 48 unsigned int mask_length:8; 49 } split; 50 unsigned int full; 51 } eax; 52 53 union cpuid10_ebx { 54 struct { 55 unsigned int no_unhalted_core_cycles:1; 56 unsigned int no_instructions_retired:1; 57 unsigned int no_unhalted_reference_cycles:1; 58 unsigned int no_llc_reference:1; 59 unsigned int no_llc_misses:1; 60 unsigned int no_branch_instruction_retired:1; 61 unsigned int no_branch_misses_retired:1; 62 } split; 63 unsigned int full; 64 } ebx; 65 66 union cpuid10_edx { 67 struct { 68 unsigned int num_counters_fixed:5; 69 unsigned int bit_width_fixed:8; 70 unsigned int reserved:19; 71 } split; 72 unsigned int full; 73 } edx; 74 75 struct pmu_event { 76 char *name; 77 uint32_t unit_sel; 78 int min; 79 int max; 80 } gp_events[] = { 81 {"core cycles", 0x003c, 1*N, 50*N}, 82 {"instructions", 0x00c0, 10*N, 10.2*N}, 83 {"ref cycles", 0x013c, 0.1*N, 30*N}, 84 {"llc refference", 0x4f2e, 1, 2*N}, 85 {"llc misses", 0x412e, 1, 1*N}, 86 {"branches", 0x00c4, 1*N, 1.1*N}, 87 {"branch misses", 0x00c5, 0, 0.1*N}, 88 }, fixed_events[] = { 89 {"fixed 1", MSR_CORE_PERF_FIXED_CTR0, 10*N, 10.2*N}, 90 {"fixed 2", MSR_CORE_PERF_FIXED_CTR0 + 1, 1*N, 30*N}, 91 {"fixed 3", MSR_CORE_PERF_FIXED_CTR0 + 2, 0.1*N, 30*N} 92 }; 93 94 static int num_counters; 95 96 char *buf; 97 98 static inline void loop() 99 { 100 unsigned long tmp, tmp2, tmp3; 101 102 asm volatile("1: mov (%1), %2; add $64, %1; nop; nop; nop; nop; nop; nop; nop; loop 1b" 103 : "=c"(tmp), "=r"(tmp2), "=r"(tmp3): "0"(N), "1"(buf)); 104 105 } 106 107 volatile uint64_t irq_received; 108 109 static void cnt_overflow(isr_regs_t *regs) 110 { 111 irq_received++; 112 apic_write(APIC_EOI, 0); 113 } 114 115 static bool check_irq(void) 116 { 117 int i; 118 irq_received = 0; 119 irq_enable(); 120 for (i = 0; i < 100000 && !irq_received; i++) 121 asm volatile("pause"); 122 irq_disable(); 123 return irq_received; 124 } 125 126 static bool is_gp(pmu_counter_t *evt) 127 { 128 return evt->ctr < MSR_CORE_PERF_FIXED_CTR0; 129 } 130 131 static int event_to_global_idx(pmu_counter_t *cnt) 132 { 133 return cnt->ctr - (is_gp(cnt) ? MSR_IA32_PERFCTR0 : 134 (MSR_CORE_PERF_FIXED_CTR0 - FIXED_CNT_INDEX)); 135 } 136 137 static struct pmu_event* get_counter_event(pmu_counter_t *cnt) 138 { 139 if (is_gp(cnt)) { 140 int i; 141 142 for (i = 0; i < sizeof(gp_events)/sizeof(gp_events[0]); i++) 143 if (gp_events[i].unit_sel == (cnt->config & 0xffff)) 144 return &gp_events[i]; 145 } else 146 return &fixed_events[cnt->ctr - MSR_CORE_PERF_FIXED_CTR0]; 147 148 return (void*)0; 149 } 150 151 static void global_enable(pmu_counter_t *cnt) 152 { 153 cnt->idx = event_to_global_idx(cnt); 154 155 wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, rdmsr(MSR_CORE_PERF_GLOBAL_CTRL) | 156 (1ull << cnt->idx)); 157 } 158 159 static void global_disable(pmu_counter_t *cnt) 160 { 161 wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, rdmsr(MSR_CORE_PERF_GLOBAL_CTRL) & 162 ~(1ull << cnt->idx)); 163 } 164 165 166 static void start_event(pmu_counter_t *evt) 167 { 168 wrmsr(evt->ctr, evt->count); 169 if (is_gp(evt)) 170 wrmsr(MSR_P6_EVNTSEL0 + event_to_global_idx(evt), 171 evt->config | EVNTSEL_EN); 172 else { 173 uint32_t ctrl = rdmsr(MSR_CORE_PERF_FIXED_CTR_CTRL); 174 int shift = (evt->ctr - MSR_CORE_PERF_FIXED_CTR0) * 4; 175 uint32_t usrospmi = 0; 176 177 if (evt->config & EVNTSEL_OS) 178 usrospmi |= (1 << 0); 179 if (evt->config & EVNTSEL_USR) 180 usrospmi |= (1 << 1); 181 if (evt->config & EVNTSEL_INT) 182 usrospmi |= (1 << 3); // PMI on overflow 183 ctrl = (ctrl & ~(0xf << shift)) | (usrospmi << shift); 184 wrmsr(MSR_CORE_PERF_FIXED_CTR_CTRL, ctrl); 185 } 186 global_enable(evt); 187 } 188 189 static void stop_event(pmu_counter_t *evt) 190 { 191 global_disable(evt); 192 if (is_gp(evt)) 193 wrmsr(MSR_P6_EVNTSEL0 + event_to_global_idx(evt), 194 evt->config & ~EVNTSEL_EN); 195 else { 196 uint32_t ctrl = rdmsr(MSR_CORE_PERF_FIXED_CTR_CTRL); 197 int shift = (evt->ctr - MSR_CORE_PERF_FIXED_CTR0) * 4; 198 wrmsr(MSR_CORE_PERF_FIXED_CTR_CTRL, ctrl & ~(0xf << shift)); 199 } 200 evt->count = rdmsr(evt->ctr); 201 } 202 203 static void measure(pmu_counter_t *evt, int count) 204 { 205 int i; 206 for (i = 0; i < count; i++) 207 start_event(&evt[i]); 208 loop(); 209 for (i = 0; i < count; i++) 210 stop_event(&evt[i]); 211 } 212 213 static bool verify_event(uint64_t count, struct pmu_event *e) 214 { 215 // printf("%lld >= %lld <= %lld\n", e->min, count, e->max); 216 return count >= e->min && count <= e->max; 217 218 } 219 220 static bool verify_counter(pmu_counter_t *cnt) 221 { 222 return verify_event(cnt->count, get_counter_event(cnt)); 223 } 224 225 static void check_gp_counter(struct pmu_event *evt) 226 { 227 pmu_counter_t cnt = { 228 .ctr = MSR_IA32_PERFCTR0, 229 .config = EVNTSEL_OS | EVNTSEL_USR | evt->unit_sel, 230 }; 231 char fmt[100]; 232 int i; 233 234 for (i = 0; i < num_counters; i++, cnt.ctr++) { 235 cnt.count = 0; 236 measure(&cnt, 1); 237 snprintf(fmt, sizeof(fmt), "%s-%%d", evt->name); 238 report(fmt, verify_event(cnt.count, evt), i); 239 } 240 } 241 242 static void check_gp_counters(void) 243 { 244 int i; 245 246 for (i = 0; i < sizeof(gp_events)/sizeof(gp_events[0]); i++) 247 if (!(ebx.full & (1 << i))) 248 check_gp_counter(&gp_events[i]); 249 else 250 printf("GP event '%s' is disabled\n", 251 gp_events[i].name); 252 } 253 254 static void check_fixed_counters(void) 255 { 256 pmu_counter_t cnt = { 257 .config = EVNTSEL_OS | EVNTSEL_USR, 258 }; 259 int i; 260 261 for (i = 0; i < edx.split.num_counters_fixed; i++) { 262 cnt.count = 0; 263 cnt.ctr = fixed_events[i].unit_sel; 264 measure(&cnt, 1); 265 report("fixed-%d", verify_event(cnt.count, &fixed_events[i]), i); 266 } 267 } 268 269 static void check_counters_many(void) 270 { 271 pmu_counter_t cnt[10]; 272 int i, n; 273 274 for (i = 0, n = 0; n < num_counters; i++) { 275 if (ebx.full & (1 << i)) 276 continue; 277 278 cnt[n].count = 0; 279 cnt[n].ctr = MSR_IA32_PERFCTR0 + n; 280 cnt[n].config = EVNTSEL_OS | EVNTSEL_USR | gp_events[i].unit_sel; 281 n++; 282 } 283 for (i = 0; i < edx.split.num_counters_fixed; i++) { 284 cnt[n].count = 0; 285 cnt[n].ctr = fixed_events[i].unit_sel; 286 cnt[n].config = EVNTSEL_OS | EVNTSEL_USR; 287 n++; 288 } 289 290 measure(cnt, n); 291 292 for (i = 0; i < n; i++) 293 if (!verify_counter(&cnt[i])) 294 break; 295 296 report("all counters", i == n); 297 } 298 299 static void check_counter_overflow(void) 300 { 301 uint64_t count; 302 int i; 303 pmu_counter_t cnt = { 304 .ctr = MSR_IA32_PERFCTR0, 305 .config = EVNTSEL_OS | EVNTSEL_USR | gp_events[1].unit_sel /* instructions */, 306 .count = 0, 307 }; 308 measure(&cnt, 1); 309 count = cnt.count; 310 311 /* clear status before test */ 312 wrmsr(MSR_CORE_PERF_GLOBAL_OVF_CTRL, rdmsr(MSR_CORE_PERF_GLOBAL_STATUS)); 313 314 for (i = 0; i < num_counters + 1; i++, cnt.ctr++) { 315 uint64_t status; 316 int idx; 317 if (i == num_counters) 318 cnt.ctr = fixed_events[0].unit_sel; 319 if (i % 2) 320 cnt.config |= EVNTSEL_INT; 321 else 322 cnt.config &= ~EVNTSEL_INT; 323 idx = event_to_global_idx(&cnt); 324 cnt.count = 1 - count; 325 measure(&cnt, 1); 326 report("overflow-%d", cnt.count == 1, i); 327 status = rdmsr(MSR_CORE_PERF_GLOBAL_STATUS); 328 report("overflow status-%d", status & (1ull << idx), i); 329 wrmsr(MSR_CORE_PERF_GLOBAL_OVF_CTRL, status); 330 status = rdmsr(MSR_CORE_PERF_GLOBAL_STATUS); 331 report("overflow status clear-%d", !(status & (1ull << idx)), i); 332 report("overflow irq-%d", check_irq() == (i % 2), i); 333 } 334 } 335 336 static void check_gp_counter_cmask(void) 337 { 338 pmu_counter_t cnt = { 339 .ctr = MSR_IA32_PERFCTR0, 340 .config = EVNTSEL_OS | EVNTSEL_USR | gp_events[1].unit_sel /* instructions */, 341 .count = 0, 342 }; 343 cnt.config |= (0x2 << EVNTSEL_CMASK_SHIFT); 344 measure(&cnt, 1); 345 report("cmask", cnt.count < gp_events[1].min); 346 } 347 348 static void check_rdpmc(void) 349 { 350 uint64_t val = 0x1f3456789ull; 351 int i; 352 353 for (i = 0; i < num_counters; i++) { 354 uint64_t x = (val & 0xffffffff) | 355 ((1ull << (eax.split.bit_width - 32)) - 1) << 32; 356 wrmsr(MSR_IA32_PERFCTR0 + i, val); 357 report("rdpmc-%d", rdpmc(i) == x, i); 358 report("rdpmc fast-%d", rdpmc(i | (1<<31)) == (u32)val, i); 359 } 360 for (i = 0; i < edx.split.num_counters_fixed; i++) { 361 uint64_t x = (val & 0xffffffff) | 362 ((1ull << (edx.split.bit_width_fixed - 32)) - 1) << 32; 363 wrmsr(MSR_CORE_PERF_FIXED_CTR0 + i, val); 364 report("rdpmc fixed-%d", rdpmc(i | (1 << 30)) == x, i); 365 report("rdpmc fixed fast-%d", rdpmc(i | (3<<30)) == (u32)val, i); 366 } 367 } 368 369 int main(int ac, char **av) 370 { 371 struct cpuid id = cpuid(10); 372 373 setup_vm(); 374 setup_idt(); 375 handle_irq(PC_VECTOR, cnt_overflow); 376 buf = vmalloc(N*64); 377 378 eax.full = id.a; 379 ebx.full = id.b; 380 edx.full = id.d; 381 382 if (!eax.split.version_id) { 383 printf("No pmu is detected!\n"); 384 return 1; 385 } 386 printf("PMU version: %d\n", eax.split.version_id); 387 printf("GP counters: %d\n", eax.split.num_counters); 388 printf("GP counter width: %d\n", eax.split.bit_width); 389 printf("Mask length: %d\n", eax.split.mask_length); 390 printf("Fixed counters: %d\n", edx.split.num_counters_fixed); 391 printf("Fixed counter width: %d\n", edx.split.bit_width_fixed); 392 393 num_counters = eax.split.num_counters; 394 if (num_counters > ARRAY_SIZE(gp_events)) 395 num_counters = ARRAY_SIZE(gp_events); 396 397 apic_write(APIC_LVTPC, PC_VECTOR); 398 399 check_gp_counters(); 400 check_fixed_counters(); 401 check_rdpmc(); 402 check_counters_many(); 403 check_counter_overflow(); 404 check_gp_counter_cmask(); 405 406 return report_summary(); 407 } 408