1 2 #include "x86/msr.h" 3 #include "x86/processor.h" 4 #include "x86/apic-defs.h" 5 #include "x86/apic.h" 6 #include "x86/desc.h" 7 #include "x86/isr.h" 8 #include "x86/vm.h" 9 10 #include "libcflat.h" 11 #include <stdint.h> 12 13 #define FIXED_CNT_INDEX 32 14 #define PC_VECTOR 32 15 16 #define EVNSEL_EVENT_SHIFT 0 17 #define EVNTSEL_UMASK_SHIFT 8 18 #define EVNTSEL_USR_SHIFT 16 19 #define EVNTSEL_OS_SHIFT 17 20 #define EVNTSEL_EDGE_SHIFT 18 21 #define EVNTSEL_PC_SHIFT 19 22 #define EVNTSEL_INT_SHIFT 20 23 #define EVNTSEL_EN_SHIF 22 24 #define EVNTSEL_INV_SHIF 23 25 #define EVNTSEL_CMASK_SHIFT 24 26 27 #define EVNTSEL_EN (1 << EVNTSEL_EN_SHIF) 28 #define EVNTSEL_USR (1 << EVNTSEL_USR_SHIFT) 29 #define EVNTSEL_OS (1 << EVNTSEL_OS_SHIFT) 30 #define EVNTSEL_PC (1 << EVNTSEL_PC_SHIFT) 31 #define EVNTSEL_INT (1 << EVNTSEL_INT_SHIFT) 32 #define EVNTSEL_INV (1 << EVNTSEL_INV_SHIF) 33 34 #define N 1000000 35 36 typedef struct { 37 uint32_t ctr; 38 uint32_t config; 39 uint64_t count; 40 int idx; 41 } pmu_counter_t; 42 43 union cpuid10_eax { 44 struct { 45 unsigned int version_id:8; 46 unsigned int num_counters:8; 47 unsigned int bit_width:8; 48 unsigned int mask_length:8; 49 } split; 50 unsigned int full; 51 } eax; 52 53 union cpuid10_ebx { 54 struct { 55 unsigned int no_unhalted_core_cycles:1; 56 unsigned int no_instructions_retired:1; 57 unsigned int no_unhalted_reference_cycles:1; 58 unsigned int no_llc_reference:1; 59 unsigned int no_llc_misses:1; 60 unsigned int no_branch_instruction_retired:1; 61 unsigned int no_branch_misses_retired:1; 62 } split; 63 unsigned int full; 64 } ebx; 65 66 union cpuid10_edx { 67 struct { 68 unsigned int num_counters_fixed:5; 69 unsigned int bit_width_fixed:8; 70 unsigned int reserved:19; 71 } split; 72 unsigned int full; 73 } edx; 74 75 struct pmu_event { 76 const char *name; 77 uint32_t unit_sel; 78 int min; 79 int max; 80 } gp_events[] = { 81 {"core cycles", 0x003c, 1*N, 50*N}, 82 {"instructions", 0x00c0, 10*N, 10.2*N}, 83 {"ref cycles", 0x013c, 0.1*N, 30*N}, 84 {"llc refference", 0x4f2e, 1, 2*N}, 85 {"llc misses", 0x412e, 1, 1*N}, 86 {"branches", 0x00c4, 1*N, 1.1*N}, 87 {"branch misses", 0x00c5, 0, 0.1*N}, 88 }, fixed_events[] = { 89 {"fixed 1", MSR_CORE_PERF_FIXED_CTR0, 10*N, 10.2*N}, 90 {"fixed 2", MSR_CORE_PERF_FIXED_CTR0 + 1, 1*N, 30*N}, 91 {"fixed 3", MSR_CORE_PERF_FIXED_CTR0 + 2, 0.1*N, 30*N} 92 }; 93 94 static int num_counters; 95 96 char *buf; 97 98 static inline void loop() 99 { 100 unsigned long tmp, tmp2, tmp3; 101 102 asm volatile("1: mov (%1), %2; add $64, %1; nop; nop; nop; nop; nop; nop; nop; loop 1b" 103 : "=c"(tmp), "=r"(tmp2), "=r"(tmp3): "0"(N), "1"(buf)); 104 105 } 106 107 volatile uint64_t irq_received; 108 109 static void cnt_overflow(isr_regs_t *regs) 110 { 111 irq_received++; 112 apic_write(APIC_EOI, 0); 113 } 114 115 static bool check_irq(void) 116 { 117 int i; 118 irq_received = 0; 119 irq_enable(); 120 for (i = 0; i < 100000 && !irq_received; i++) 121 asm volatile("pause"); 122 irq_disable(); 123 return irq_received; 124 } 125 126 static bool is_gp(pmu_counter_t *evt) 127 { 128 return evt->ctr < MSR_CORE_PERF_FIXED_CTR0; 129 } 130 131 static int event_to_global_idx(pmu_counter_t *cnt) 132 { 133 return cnt->ctr - (is_gp(cnt) ? MSR_IA32_PERFCTR0 : 134 (MSR_CORE_PERF_FIXED_CTR0 - FIXED_CNT_INDEX)); 135 } 136 137 static struct pmu_event* get_counter_event(pmu_counter_t *cnt) 138 { 139 if (is_gp(cnt)) { 140 int i; 141 142 for (i = 0; i < sizeof(gp_events)/sizeof(gp_events[0]); i++) 143 if (gp_events[i].unit_sel == (cnt->config & 0xffff)) 144 return &gp_events[i]; 145 } else 146 return &fixed_events[cnt->ctr - MSR_CORE_PERF_FIXED_CTR0]; 147 148 return (void*)0; 149 } 150 151 static void global_enable(pmu_counter_t *cnt) 152 { 153 cnt->idx = event_to_global_idx(cnt); 154 155 wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, rdmsr(MSR_CORE_PERF_GLOBAL_CTRL) | 156 (1ull << cnt->idx)); 157 } 158 159 static void global_disable(pmu_counter_t *cnt) 160 { 161 wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, rdmsr(MSR_CORE_PERF_GLOBAL_CTRL) & 162 ~(1ull << cnt->idx)); 163 } 164 165 166 static void start_event(pmu_counter_t *evt) 167 { 168 wrmsr(evt->ctr, evt->count); 169 if (is_gp(evt)) 170 wrmsr(MSR_P6_EVNTSEL0 + event_to_global_idx(evt), 171 evt->config | EVNTSEL_EN); 172 else { 173 uint32_t ctrl = rdmsr(MSR_CORE_PERF_FIXED_CTR_CTRL); 174 int shift = (evt->ctr - MSR_CORE_PERF_FIXED_CTR0) * 4; 175 uint32_t usrospmi = 0; 176 177 if (evt->config & EVNTSEL_OS) 178 usrospmi |= (1 << 0); 179 if (evt->config & EVNTSEL_USR) 180 usrospmi |= (1 << 1); 181 if (evt->config & EVNTSEL_INT) 182 usrospmi |= (1 << 3); // PMI on overflow 183 ctrl = (ctrl & ~(0xf << shift)) | (usrospmi << shift); 184 wrmsr(MSR_CORE_PERF_FIXED_CTR_CTRL, ctrl); 185 } 186 global_enable(evt); 187 } 188 189 static void stop_event(pmu_counter_t *evt) 190 { 191 global_disable(evt); 192 if (is_gp(evt)) 193 wrmsr(MSR_P6_EVNTSEL0 + event_to_global_idx(evt), 194 evt->config & ~EVNTSEL_EN); 195 else { 196 uint32_t ctrl = rdmsr(MSR_CORE_PERF_FIXED_CTR_CTRL); 197 int shift = (evt->ctr - MSR_CORE_PERF_FIXED_CTR0) * 4; 198 wrmsr(MSR_CORE_PERF_FIXED_CTR_CTRL, ctrl & ~(0xf << shift)); 199 } 200 evt->count = rdmsr(evt->ctr); 201 } 202 203 static void measure(pmu_counter_t *evt, int count) 204 { 205 int i; 206 for (i = 0; i < count; i++) 207 start_event(&evt[i]); 208 loop(); 209 for (i = 0; i < count; i++) 210 stop_event(&evt[i]); 211 } 212 213 static bool verify_event(uint64_t count, struct pmu_event *e) 214 { 215 // printf("%lld >= %lld <= %lld\n", e->min, count, e->max); 216 return count >= e->min && count <= e->max; 217 218 } 219 220 static bool verify_counter(pmu_counter_t *cnt) 221 { 222 return verify_event(cnt->count, get_counter_event(cnt)); 223 } 224 225 static void check_gp_counter(struct pmu_event *evt) 226 { 227 pmu_counter_t cnt = { 228 .ctr = MSR_IA32_PERFCTR0, 229 .config = EVNTSEL_OS | EVNTSEL_USR | evt->unit_sel, 230 }; 231 int i; 232 233 for (i = 0; i < num_counters; i++, cnt.ctr++) { 234 cnt.count = 0; 235 measure(&cnt, 1); 236 report("%s-%d", verify_event(cnt.count, evt), evt->name, i); 237 } 238 } 239 240 static void check_gp_counters(void) 241 { 242 int i; 243 244 for (i = 0; i < sizeof(gp_events)/sizeof(gp_events[0]); i++) 245 if (!(ebx.full & (1 << i))) 246 check_gp_counter(&gp_events[i]); 247 else 248 printf("GP event '%s' is disabled\n", 249 gp_events[i].name); 250 } 251 252 static void check_fixed_counters(void) 253 { 254 pmu_counter_t cnt = { 255 .config = EVNTSEL_OS | EVNTSEL_USR, 256 }; 257 int i; 258 259 for (i = 0; i < edx.split.num_counters_fixed; i++) { 260 cnt.count = 0; 261 cnt.ctr = fixed_events[i].unit_sel; 262 measure(&cnt, 1); 263 report("fixed-%d", verify_event(cnt.count, &fixed_events[i]), i); 264 } 265 } 266 267 static void check_counters_many(void) 268 { 269 pmu_counter_t cnt[10]; 270 int i, n; 271 272 for (i = 0, n = 0; n < num_counters; i++) { 273 if (ebx.full & (1 << i)) 274 continue; 275 276 cnt[n].count = 0; 277 cnt[n].ctr = MSR_IA32_PERFCTR0 + n; 278 cnt[n].config = EVNTSEL_OS | EVNTSEL_USR | 279 gp_events[i % ARRAY_SIZE(gp_events)].unit_sel; 280 n++; 281 } 282 for (i = 0; i < edx.split.num_counters_fixed; i++) { 283 cnt[n].count = 0; 284 cnt[n].ctr = fixed_events[i].unit_sel; 285 cnt[n].config = EVNTSEL_OS | EVNTSEL_USR; 286 n++; 287 } 288 289 measure(cnt, n); 290 291 for (i = 0; i < n; i++) 292 if (!verify_counter(&cnt[i])) 293 break; 294 295 report("all counters", i == n); 296 } 297 298 static void check_counter_overflow(void) 299 { 300 uint64_t count; 301 int i; 302 pmu_counter_t cnt = { 303 .ctr = MSR_IA32_PERFCTR0, 304 .config = EVNTSEL_OS | EVNTSEL_USR | gp_events[1].unit_sel /* instructions */, 305 .count = 0, 306 }; 307 measure(&cnt, 1); 308 count = cnt.count; 309 310 /* clear status before test */ 311 wrmsr(MSR_CORE_PERF_GLOBAL_OVF_CTRL, rdmsr(MSR_CORE_PERF_GLOBAL_STATUS)); 312 313 report_prefix_push("overflow"); 314 315 for (i = 0; i < num_counters + 1; i++, cnt.ctr++) { 316 uint64_t status; 317 int idx; 318 if (i == num_counters) 319 cnt.ctr = fixed_events[0].unit_sel; 320 if (i % 2) 321 cnt.config |= EVNTSEL_INT; 322 else 323 cnt.config &= ~EVNTSEL_INT; 324 idx = event_to_global_idx(&cnt); 325 cnt.count = 1 - count; 326 measure(&cnt, 1); 327 report("cntr-%d", cnt.count == 1, i); 328 status = rdmsr(MSR_CORE_PERF_GLOBAL_STATUS); 329 report("status-%d", status & (1ull << idx), i); 330 wrmsr(MSR_CORE_PERF_GLOBAL_OVF_CTRL, status); 331 status = rdmsr(MSR_CORE_PERF_GLOBAL_STATUS); 332 report("status clear-%d", !(status & (1ull << idx)), i); 333 report("irq-%d", check_irq() == (i % 2), i); 334 } 335 336 report_prefix_pop(); 337 } 338 339 static void check_gp_counter_cmask(void) 340 { 341 pmu_counter_t cnt = { 342 .ctr = MSR_IA32_PERFCTR0, 343 .config = EVNTSEL_OS | EVNTSEL_USR | gp_events[1].unit_sel /* instructions */, 344 .count = 0, 345 }; 346 cnt.config |= (0x2 << EVNTSEL_CMASK_SHIFT); 347 measure(&cnt, 1); 348 report("cmask", cnt.count < gp_events[1].min); 349 } 350 351 static void check_rdpmc(void) 352 { 353 uint64_t val = 0x1f3456789ull; 354 int i; 355 356 report_prefix_push("rdpmc"); 357 358 for (i = 0; i < num_counters; i++) { 359 uint64_t x = (val & 0xffffffff) | 360 ((1ull << (eax.split.bit_width - 32)) - 1) << 32; 361 wrmsr(MSR_IA32_PERFCTR0 + i, val); 362 report("cntr-%d", rdpmc(i) == x, i); 363 report("fast-%d", rdpmc(i | (1<<31)) == (u32)val, i); 364 } 365 for (i = 0; i < edx.split.num_counters_fixed; i++) { 366 uint64_t x = (val & 0xffffffff) | 367 ((1ull << (edx.split.bit_width_fixed - 32)) - 1) << 32; 368 wrmsr(MSR_CORE_PERF_FIXED_CTR0 + i, val); 369 report("fixed cntr-%d", rdpmc(i | (1 << 30)) == x, i); 370 report("fixed fast-%d", rdpmc(i | (3<<30)) == (u32)val, i); 371 } 372 373 report_prefix_pop(); 374 } 375 376 int main(int ac, char **av) 377 { 378 struct cpuid id = cpuid(10); 379 380 setup_vm(); 381 setup_idt(); 382 handle_irq(PC_VECTOR, cnt_overflow); 383 buf = vmalloc(N*64); 384 385 eax.full = id.a; 386 ebx.full = id.b; 387 edx.full = id.d; 388 389 if (!eax.split.version_id) { 390 printf("No pmu is detected!\n"); 391 return report_summary(); 392 } 393 printf("PMU version: %d\n", eax.split.version_id); 394 printf("GP counters: %d\n", eax.split.num_counters); 395 printf("GP counter width: %d\n", eax.split.bit_width); 396 printf("Mask length: %d\n", eax.split.mask_length); 397 printf("Fixed counters: %d\n", edx.split.num_counters_fixed); 398 printf("Fixed counter width: %d\n", edx.split.bit_width_fixed); 399 400 num_counters = eax.split.num_counters; 401 402 apic_write(APIC_LVTPC, PC_VECTOR); 403 404 check_gp_counters(); 405 check_fixed_counters(); 406 check_rdpmc(); 407 check_counters_many(); 408 check_counter_overflow(); 409 check_gp_counter_cmask(); 410 411 return report_summary(); 412 } 413