1 #include "libcflat.h" 2 #include "x86/desc.h" 3 #include "x86/processor.h" 4 #include "x86/vm.h" 5 #include "x86/msr.h" 6 7 #define CR0_WP_MASK (1UL << 16) 8 #define PTE_PKEY_BIT 59 9 #define USER_BASE (1 << 24) 10 #define USER_VAR(v) (*((__typeof__(&(v))) (((unsigned long)&v) + USER_BASE))) 11 12 volatile int pf_count = 0; 13 volatile unsigned save; 14 volatile unsigned test; 15 16 static void set_cr0_wp(int wp) 17 { 18 unsigned long cr0 = read_cr0(); 19 20 cr0 &= ~CR0_WP_MASK; 21 if (wp) 22 cr0 |= CR0_WP_MASK; 23 write_cr0(cr0); 24 } 25 26 void do_pf_tss(unsigned long error_code); 27 void do_pf_tss(unsigned long error_code) 28 { 29 pf_count++; 30 save = test; 31 write_pkru(0); 32 } 33 34 extern void pf_tss(void); 35 36 asm ("pf_tss: \n\t" 37 #ifdef __x86_64__ 38 // no task on x86_64, save/restore caller-save regs 39 "push %rax; push %rcx; push %rdx; push %rsi; push %rdi\n" 40 "push %r8; push %r9; push %r10; push %r11\n" 41 "mov 9*8(%rsp),%rdi\n" 42 #endif 43 "call do_pf_tss \n\t" 44 #ifdef __x86_64__ 45 "pop %r11; pop %r10; pop %r9; pop %r8\n" 46 "pop %rdi; pop %rsi; pop %rdx; pop %rcx; pop %rax\n" 47 #endif 48 "add $"S", %"R "sp\n\t" // discard error code 49 "iret"W" \n\t" 50 "jmp pf_tss\n\t" 51 ); 52 53 static void init_test(void) 54 { 55 pf_count = 0; 56 57 invlpg(&test); 58 invlpg(&USER_VAR(test)); 59 write_pkru(0); 60 set_cr0_wp(0); 61 } 62 63 int main(int ac, char **av) 64 { 65 unsigned long i; 66 unsigned int pkey = 0x2; 67 unsigned int pkru_ad = 0x10; 68 unsigned int pkru_wd = 0x20; 69 70 if (!this_cpu_has(X86_FEATURE_PKU)) { 71 printf("PKU not enabled\n"); 72 return report_summary(); 73 } 74 75 setup_vm(); 76 setup_alt_stack(); 77 set_intr_alt_stack(14, pf_tss); 78 wrmsr(MSR_EFER, rdmsr(MSR_EFER) | EFER_LMA); 79 80 for (i = 0; i < USER_BASE; i += PAGE_SIZE) { 81 *get_pte(phys_to_virt(read_cr3()), phys_to_virt(i)) &= ~PT_USER_MASK; 82 *get_pte(phys_to_virt(read_cr3()), phys_to_virt(i)) |= ((unsigned long)pkey << PTE_PKEY_BIT); 83 invlpg((void *)i); 84 } 85 86 for (i = USER_BASE; i < 2 * USER_BASE; i += PAGE_SIZE) { 87 *get_pte(phys_to_virt(read_cr3()), phys_to_virt(i)) &= ~USER_BASE; 88 *get_pte(phys_to_virt(read_cr3()), phys_to_virt(i)) |= ((unsigned long)pkey << PTE_PKEY_BIT); 89 invlpg((void *)i); 90 } 91 92 write_cr4(read_cr4() | X86_CR4_PKE); 93 write_cr3(read_cr3()); 94 95 init_test(); 96 set_cr0_wp(1); 97 write_pkru(pkru_ad); 98 test = 21; 99 report(pf_count == 0 && test == 21, 100 "write to supervisor page when pkru is ad and wp == 1"); 101 102 init_test(); 103 set_cr0_wp(0); 104 write_pkru(pkru_ad); 105 test = 22; 106 report(pf_count == 0 && test == 22, 107 "write to supervisor page when pkru is ad and wp == 0"); 108 109 init_test(); 110 set_cr0_wp(1); 111 write_pkru(pkru_wd); 112 test = 23; 113 report(pf_count == 0 && test == 23, 114 "write to supervisor page when pkru is wd and wp == 1"); 115 116 init_test(); 117 set_cr0_wp(0); 118 write_pkru(pkru_wd); 119 test = 24; 120 report(pf_count == 0 && test == 24, 121 "write to supervisor page when pkru is wd and wp == 0"); 122 123 init_test(); 124 write_pkru(pkru_wd); 125 set_cr0_wp(0); 126 USER_VAR(test) = 25; 127 report(pf_count == 0 && test == 25, 128 "write to user page when pkru is wd and wp == 0"); 129 130 init_test(); 131 write_pkru(pkru_wd); 132 set_cr0_wp(1); 133 USER_VAR(test) = 26; 134 report(pf_count == 1 && test == 26 && save == 25, 135 "write to user page when pkru is wd and wp == 1"); 136 137 init_test(); 138 write_pkru(pkru_ad); 139 (void)USER_VAR(test); 140 report(pf_count == 1 && save == 26, "read from user page when pkru is ad"); 141 142 // TODO: implicit kernel access from ring 3 (e.g. int) 143 144 return report_summary(); 145 } 146