1 /* msr tests */ 2 3 #include "libcflat.h" 4 #include "processor.h" 5 #include "msr.h" 6 #include <stdlib.h> 7 8 /** 9 * This test allows two modes: 10 * 1. Default: the `msr_info' array contains the default test configurations 11 * 2. Custom: by providing command line arguments it is possible to test any MSR and value 12 * Parameters order: 13 * 1. msr index as a base 16 number 14 * 2. value as a base 16 number 15 */ 16 17 struct msr_info { 18 int index; 19 bool is_64bit_only; 20 const char *name; 21 unsigned long long value; 22 }; 23 24 25 #define addr_64 0x0000123456789abcULL 26 #define addr_ul (unsigned long)addr_64 27 28 #define MSR_TEST(msr, val, only64) \ 29 { .index = msr, .name = #msr, .value = val, .is_64bit_only = only64 } 30 31 struct msr_info msr_info[] = 32 { 33 MSR_TEST(MSR_IA32_SYSENTER_CS, 0x1234, false), 34 MSR_TEST(MSR_IA32_SYSENTER_ESP, addr_ul, false), 35 MSR_TEST(MSR_IA32_SYSENTER_EIP, addr_ul, false), 36 // reserved: 1:2, 4:6, 8:10, 13:15, 17, 19:21, 24:33, 35:63 37 MSR_TEST(MSR_IA32_MISC_ENABLE, 0x400c51889, false), 38 MSR_TEST(MSR_IA32_CR_PAT, 0x07070707, false), 39 MSR_TEST(MSR_FS_BASE, addr_64, true), 40 MSR_TEST(MSR_GS_BASE, addr_64, true), 41 MSR_TEST(MSR_KERNEL_GS_BASE, addr_64, true), 42 MSR_TEST(MSR_EFER, EFER_SCE, false), 43 MSR_TEST(MSR_LSTAR, addr_64, true), 44 MSR_TEST(MSR_CSTAR, addr_64, true), 45 MSR_TEST(MSR_SYSCALL_MASK, 0xffffffff, true), 46 // MSR_IA32_DEBUGCTLMSR needs svm feature LBRV 47 // MSR_VM_HSAVE_PA only AMD host 48 }; 49 50 static void test_msr_rw(struct msr_info *msr, unsigned long long val) 51 { 52 unsigned long long r, orig; 53 54 orig = rdmsr(msr->index); 55 /* 56 * Special case EFER since clearing LME/LMA is not allowed in 64-bit mode, 57 * and conversely setting those bits on 32-bit CPUs is not allowed. Treat 58 * the desired value as extra bits to set. 59 */ 60 if (msr->index == MSR_EFER) 61 val |= orig; 62 wrmsr(msr->index, val); 63 r = rdmsr(msr->index); 64 wrmsr(msr->index, orig); 65 if (r != val) { 66 printf("testing %s: output = %#" PRIx32 ":%#" PRIx32 67 " expected = %#" PRIx32 ":%#" PRIx32 "\n", msr->name, 68 (u32)(r >> 32), (u32)r, (u32)(val >> 32), (u32)val); 69 } 70 report(val == r, "%s", msr->name); 71 } 72 73 static void test_wrmsr_fault(struct msr_info *msr, unsigned long long val) 74 { 75 unsigned char vector = wrmsr_checking(msr->index, val); 76 77 report(vector == GP_VECTOR, 78 "Expected #GP on WRSMR(%s, 0x%llx), got vector %d", 79 msr->name, val, vector); 80 } 81 82 static void test_rdmsr_fault(struct msr_info *msr) 83 { 84 unsigned char vector = rdmsr_checking(msr->index); 85 86 report(vector == GP_VECTOR, 87 "Expected #GP on RDSMR(%s), got vector %d", msr->name, vector); 88 } 89 90 static void test_msr(struct msr_info *msr, bool is_64bit_host) 91 { 92 if (is_64bit_host || !msr->is_64bit_only) { 93 test_msr_rw(msr, msr->value); 94 95 /* 96 * The 64-bit only MSRs that take an address always perform 97 * canonical checks on both Intel and AMD. 98 */ 99 if (msr->is_64bit_only && 100 msr->value == addr_64) 101 test_wrmsr_fault(msr, NONCANONICAL); 102 } else { 103 test_wrmsr_fault(msr, msr->value); 104 test_rdmsr_fault(msr); 105 } 106 } 107 108 int main(int ac, char **av) 109 { 110 bool is_64bit_host = this_cpu_has(X86_FEATURE_LM); 111 int i; 112 113 if (ac == 3) { 114 char msr_name[16]; 115 int index = strtoul(av[1], NULL, 0x10); 116 snprintf(msr_name, sizeof(msr_name), "MSR:0x%x", index); 117 118 struct msr_info msr = { 119 .index = index, 120 .name = msr_name, 121 .value = strtoull(av[2], NULL, 0x10) 122 }; 123 test_msr(&msr, is_64bit_host); 124 } else { 125 for (i = 0 ; i < ARRAY_SIZE(msr_info); i++) { 126 test_msr(&msr_info[i], is_64bit_host); 127 } 128 } 129 130 return report_summary(); 131 } 132