1 /* msr tests */ 2 3 #include "libcflat.h" 4 #include "apic.h" 5 #include "processor.h" 6 #include "msr.h" 7 #include <stdlib.h> 8 9 /** 10 * This test allows two modes: 11 * 1. Default: the `msr_info' array contains the default test configurations 12 * 2. Custom: by providing command line arguments it is possible to test any MSR and value 13 * Parameters order: 14 * 1. msr index as a base 16 number 15 * 2. value as a base 16 number 16 */ 17 18 struct msr_info { 19 int index; 20 bool is_64bit_only; 21 const char *name; 22 unsigned long long value; 23 unsigned long long keep; 24 }; 25 26 27 #define addr_64 0x0000123456789abcULL 28 #define addr_ul (unsigned long)addr_64 29 30 #define MSR_TEST(msr, val, ro) \ 31 { .index = msr, .name = #msr, .value = val, .is_64bit_only = false, .keep = ro } 32 #define MSR_TEST_ONLY64(msr, val, ro) \ 33 { .index = msr, .name = #msr, .value = val, .is_64bit_only = true, .keep = ro } 34 35 struct msr_info msr_info[] = 36 { 37 MSR_TEST(MSR_IA32_SYSENTER_CS, 0x1234, 0), 38 MSR_TEST(MSR_IA32_SYSENTER_ESP, addr_ul, 0), 39 MSR_TEST(MSR_IA32_SYSENTER_EIP, addr_ul, 0), 40 // reserved: 1:2, 4:6, 8:10, 13:15, 17, 19:21, 24:33, 35:63 41 // read-only: 7, 11, 12 42 MSR_TEST(MSR_IA32_MISC_ENABLE, 0x400c50809, 0x1880), 43 MSR_TEST(MSR_IA32_CR_PAT, 0x07070707, 0), 44 MSR_TEST_ONLY64(MSR_FS_BASE, addr_64, 0), 45 MSR_TEST_ONLY64(MSR_GS_BASE, addr_64, 0), 46 MSR_TEST_ONLY64(MSR_KERNEL_GS_BASE, addr_64, 0), 47 MSR_TEST(MSR_EFER, EFER_SCE, 0), 48 MSR_TEST_ONLY64(MSR_LSTAR, addr_64, 0), 49 MSR_TEST_ONLY64(MSR_CSTAR, addr_64, 0), 50 MSR_TEST_ONLY64(MSR_SYSCALL_MASK, 0xffffffff, 0), 51 // MSR_IA32_DEBUGCTLMSR needs svm feature LBRV 52 // MSR_VM_HSAVE_PA only AMD host 53 }; 54 55 static void __test_msr_rw(u32 msr, const char *name, unsigned long long val, 56 unsigned long long keep_mask) 57 { 58 unsigned long long r, orig; 59 60 orig = rdmsr(msr); 61 /* 62 * Special case EFER since clearing LME/LMA is not allowed in 64-bit mode, 63 * and conversely setting those bits on 32-bit CPUs is not allowed. Treat 64 * the desired value as extra bits to set. 65 */ 66 if (msr == MSR_EFER) 67 val |= orig; 68 else 69 val = (val & ~keep_mask) | (orig & keep_mask); 70 71 wrmsr(msr, val); 72 r = rdmsr(msr); 73 wrmsr(msr, orig); 74 75 if (r != val) { 76 printf("testing %s: output = %#" PRIx32 ":%#" PRIx32 77 " expected = %#" PRIx32 ":%#" PRIx32 "\n", name, 78 (u32)(r >> 32), (u32)r, (u32)(val >> 32), (u32)val); 79 } 80 report(val == r, "%s", name); 81 } 82 83 static void test_msr_rw(u32 msr, const char *name, unsigned long long val) 84 { 85 __test_msr_rw(msr, name, val, 0); 86 } 87 88 static void test_wrmsr(u32 msr, const char *name, unsigned long long val) 89 { 90 unsigned char vector = wrmsr_safe(msr, val); 91 92 report(!vector, 93 "Expected success on WRSMR(%s, 0x%llx), got vector %d", 94 name, val, vector); 95 } 96 97 static void test_wrmsr_fault(u32 msr, const char *name, unsigned long long val) 98 { 99 unsigned char vector = wrmsr_safe(msr, val); 100 101 report(vector == GP_VECTOR, 102 "Expected #GP on WRSMR(%s, 0x%llx), got vector %d", 103 name, val, vector); 104 } 105 106 static void test_rdmsr_fault(u32 msr, const char *name) 107 { 108 uint64_t ignored; 109 unsigned char vector = rdmsr_safe(msr, &ignored); 110 111 report(vector == GP_VECTOR, 112 "Expected #GP on RDSMR(%s), got vector %d", name, vector); 113 } 114 115 static void test_msr(struct msr_info *msr, bool is_64bit_host) 116 { 117 if (is_64bit_host || !msr->is_64bit_only) { 118 __test_msr_rw(msr->index, msr->name, msr->value, msr->keep); 119 120 /* 121 * The 64-bit only MSRs that take an address always perform 122 * canonical checks on both Intel and AMD. 123 */ 124 if (msr->is_64bit_only && 125 msr->value == addr_64) 126 test_wrmsr_fault(msr->index, msr->name, NONCANONICAL); 127 } else { 128 test_wrmsr_fault(msr->index, msr->name, msr->value); 129 test_rdmsr_fault(msr->index, msr->name); 130 } 131 } 132 133 static void test_custom_msr(int ac, char **av) 134 { 135 bool is_64bit_host = this_cpu_has(X86_FEATURE_LM); 136 char msr_name[32]; 137 int index = strtoul(av[1], NULL, 0x10); 138 snprintf(msr_name, sizeof(msr_name), "MSR:0x%x", index); 139 140 struct msr_info msr = { 141 .index = index, 142 .name = msr_name, 143 .value = strtoull(av[2], NULL, 0x10) 144 }; 145 test_msr(&msr, is_64bit_host); 146 } 147 148 static void test_misc_msrs(void) 149 { 150 bool is_64bit_host = this_cpu_has(X86_FEATURE_LM); 151 int i; 152 153 for (i = 0 ; i < ARRAY_SIZE(msr_info); i++) 154 test_msr(&msr_info[i], is_64bit_host); 155 } 156 157 static void test_mce_msrs(void) 158 { 159 bool is_64bit_host = this_cpu_has(X86_FEATURE_LM); 160 unsigned int nr_mce_banks; 161 char msr_name[32]; 162 int i; 163 164 nr_mce_banks = rdmsr(MSR_IA32_MCG_CAP) & 0xff; 165 for (i = 0; i < nr_mce_banks; i++) { 166 snprintf(msr_name, sizeof(msr_name), "MSR_IA32_MC%u_CTL", i); 167 test_msr_rw(MSR_IA32_MCx_CTL(i), msr_name, 0); 168 test_msr_rw(MSR_IA32_MCx_CTL(i), msr_name, -1ull); 169 test_wrmsr_fault(MSR_IA32_MCx_CTL(i), msr_name, NONCANONICAL); 170 171 snprintf(msr_name, sizeof(msr_name), "MSR_IA32_MC%u_STATUS", i); 172 test_msr_rw(MSR_IA32_MCx_STATUS(i), msr_name, 0); 173 /* 174 * STATUS MSRs can only be written with '0' (to clear the MSR), 175 * except on AMD-based systems with bit 18 set in MSR_K7_HWCR. 176 * That bit is not architectural and should not be set by 177 * default by KVM or by the VMM (though this might fail if run 178 * on bare metal). 179 */ 180 test_wrmsr_fault(MSR_IA32_MCx_STATUS(i), msr_name, 1); 181 182 snprintf(msr_name, sizeof(msr_name), "MSR_IA32_MC%u_ADDR", i); 183 test_msr_rw(MSR_IA32_MCx_ADDR(i), msr_name, 0); 184 test_msr_rw(MSR_IA32_MCx_ADDR(i), msr_name, -1ull); 185 /* 186 * The ADDR is a physical address, and all bits are writable on 187 * 64-bit hosts. Don't test the negative case, as KVM doesn't 188 * enforce checks on bits 63:36 for 32-bit hosts. The behavior 189 * depends on the underlying hardware, e.g. a 32-bit guest on a 190 * 64-bit host may observe 64-bit values in the ADDR MSRs. 191 */ 192 if (is_64bit_host) 193 test_msr_rw(MSR_IA32_MCx_ADDR(i), msr_name, NONCANONICAL); 194 195 snprintf(msr_name, sizeof(msr_name), "MSR_IA32_MC%u_MISC", i); 196 test_msr_rw(MSR_IA32_MCx_MISC(i), msr_name, 0); 197 test_msr_rw(MSR_IA32_MCx_MISC(i), msr_name, -1ull); 198 test_msr_rw(MSR_IA32_MCx_MISC(i), msr_name, NONCANONICAL); 199 } 200 201 /* 202 * The theoretical maximum number of MCE banks is 32 (on Intel CPUs, 203 * without jumping to a new base address), as the last unclaimed MSR is 204 * 0x479; 0x480 begins the VMX MSRs. Verify accesses to theoretically 205 * legal, unsupported MSRs fault. 206 */ 207 for (i = nr_mce_banks; i < 32; i++) { 208 snprintf(msr_name, sizeof(msr_name), "MSR_IA32_MC%u_CTL", i); 209 test_rdmsr_fault(MSR_IA32_MCx_CTL(i), msr_name); 210 test_wrmsr_fault(MSR_IA32_MCx_CTL(i), msr_name, 0); 211 212 snprintf(msr_name, sizeof(msr_name), "MSR_IA32_MC%u_STATUS", i); 213 test_rdmsr_fault(MSR_IA32_MCx_STATUS(i), msr_name); 214 test_wrmsr_fault(MSR_IA32_MCx_STATUS(i), msr_name, 0); 215 216 snprintf(msr_name, sizeof(msr_name), "MSR_IA32_MC%u_ADDR", i); 217 test_rdmsr_fault(MSR_IA32_MCx_ADDR(i), msr_name); 218 test_wrmsr_fault(MSR_IA32_MCx_ADDR(i), msr_name, 0); 219 220 snprintf(msr_name, sizeof(msr_name), "MSR_IA32_MC%u_MISC", i); 221 test_rdmsr_fault(MSR_IA32_MCx_MISC(i), msr_name); 222 test_wrmsr_fault(MSR_IA32_MCx_MISC(i), msr_name, 0); 223 } 224 } 225 226 static void __test_x2apic_msrs(bool x2apic_enabled) 227 { 228 enum x2apic_reg_semantics semantics; 229 unsigned int index, i; 230 char msr_name[32]; 231 232 for (i = 0; i < 0x1000; i += 0x10) { 233 index = x2apic_msr(i); 234 snprintf(msr_name, sizeof(msr_name), "x2APIC MSR 0x%x", index); 235 236 if (x2apic_enabled) 237 semantics = get_x2apic_reg_semantics(i); 238 else 239 semantics = X2APIC_INVALID; 240 241 if (!(semantics & X2APIC_WRITABLE)) 242 test_wrmsr_fault(index, msr_name, 0); 243 244 if (!(semantics & X2APIC_READABLE)) 245 test_rdmsr_fault(index, msr_name); 246 247 /* 248 * Except for ICR, the only 64-bit x2APIC register, bits 64:32 249 * are reserved. ICR is testable if x2APIC is disabled. 250 */ 251 if (!x2apic_enabled || i != APIC_ICR) 252 test_wrmsr_fault(index, msr_name, -1ull); 253 254 /* Bits 31:8 of self-IPI are reserved. */ 255 if (i == APIC_SELF_IPI) { 256 test_wrmsr_fault(index, "x2APIC Self-IPI", 0x100); 257 test_wrmsr_fault(index, "x2APIC Self-IPI", 0xff00); 258 test_wrmsr_fault(index, "x2APIC Self-IPI", 0xff000000ull); 259 } 260 261 if (semantics == X2APIC_RW) 262 __test_msr_rw(index, msr_name, 0, -1ull); 263 else if (semantics == X2APIC_WO) 264 wrmsr(index, 0); 265 else if (semantics == X2APIC_RO) 266 report(!(rdmsr(index) >> 32), 267 "Expected bits 63:32 == 0 for '%s'", msr_name); 268 } 269 } 270 271 static void test_x2apic_msrs(void) 272 { 273 reset_apic(); 274 275 __test_x2apic_msrs(false); 276 277 if (!enable_x2apic()) 278 return; 279 280 __test_x2apic_msrs(true); 281 } 282 283 static void test_cmd_msrs(void) 284 { 285 int i; 286 287 test_rdmsr_fault(MSR_IA32_PRED_CMD, "PRED_CMD"); 288 if (this_cpu_has(X86_FEATURE_SPEC_CTRL) || 289 this_cpu_has(X86_FEATURE_AMD_IBPB)) { 290 test_wrmsr(MSR_IA32_PRED_CMD, "PRED_CMD", 0); 291 test_wrmsr(MSR_IA32_PRED_CMD, "PRED_CMD", PRED_CMD_IBPB); 292 } else { 293 test_wrmsr_fault(MSR_IA32_PRED_CMD, "PRED_CMD", 0); 294 test_wrmsr_fault(MSR_IA32_PRED_CMD, "PRED_CMD", PRED_CMD_IBPB); 295 } 296 297 test_rdmsr_fault(MSR_IA32_FLUSH_CMD, "FLUSH_CMD"); 298 if (this_cpu_has(X86_FEATURE_FLUSH_L1D)) { 299 test_wrmsr(MSR_IA32_FLUSH_CMD, "FLUSH_CMD", 0); 300 test_wrmsr(MSR_IA32_FLUSH_CMD, "FLUSH_CMD", L1D_FLUSH); 301 } else { 302 test_wrmsr_fault(MSR_IA32_FLUSH_CMD, "FLUSH_CMD", 0); 303 test_wrmsr_fault(MSR_IA32_FLUSH_CMD, "FLUSH_CMD", L1D_FLUSH); 304 } 305 for (i = 1; i < 64; i++) 306 test_wrmsr_fault(MSR_IA32_FLUSH_CMD, "FLUSH_CMD", BIT_ULL(i)); 307 } 308 309 int main(int ac, char **av) 310 { 311 /* 312 * If the user provided an MSR+value, test exactly that and skip all 313 * built-in testcases. 314 */ 315 if (ac == 3) { 316 test_custom_msr(ac, av); 317 } else { 318 test_misc_msrs(); 319 test_mce_msrs(); 320 test_x2apic_msrs(); 321 test_cmd_msrs(); 322 } 323 324 return report_summary(); 325 } 326