116c0b05fSPeter Xu /* 216c0b05fSPeter Xu * Intel IOMMU unit test. 316c0b05fSPeter Xu * 416c0b05fSPeter Xu * Copyright (C) 2016 Red Hat, Inc. 516c0b05fSPeter Xu * 616c0b05fSPeter Xu * Authors: 716c0b05fSPeter Xu * Peter Xu <peterx@redhat.com>, 816c0b05fSPeter Xu * 916c0b05fSPeter Xu * This work is licensed under the terms of the GNU LGPL, version 2 or 1016c0b05fSPeter Xu * later. 1116c0b05fSPeter Xu */ 1216c0b05fSPeter Xu 1316c0b05fSPeter Xu #include "intel-iommu.h" 1492d2c192SPeter Xu #include "pci-edu.h" 157f2477c2SPeter Xu #include "x86/apic.h" 1692d2c192SPeter Xu 1792d2c192SPeter Xu #define VTD_TEST_DMAR_4B ("DMAR 4B memcpy test") 187f2477c2SPeter Xu #define VTD_TEST_IR_MSI ("IR MSI") 193223ade2SPeter Xu #define VTD_TEST_IR_IOAPIC ("IR IOAPIC") 2092d2c192SPeter Xu 21c15c99f8SAndrew Jones static struct pci_edu_dev edu_dev; 22c15c99f8SAndrew Jones 23c15c99f8SAndrew Jones static void vtd_test_dmar(void) 2492d2c192SPeter Xu { 25c15c99f8SAndrew Jones struct pci_edu_dev *dev = &edu_dev; 2692d2c192SPeter Xu void *page = alloc_page(); 2792d2c192SPeter Xu 289e8d01f9SPeter Xu report_prefix_push("vtd_dmar"); 299e8d01f9SPeter Xu 3092d2c192SPeter Xu #define DMA_TEST_WORD (0x12345678) 3192d2c192SPeter Xu /* Modify the first 4 bytes of the page */ 3292d2c192SPeter Xu *(uint32_t *)page = DMA_TEST_WORD; 3392d2c192SPeter Xu 3492d2c192SPeter Xu /* 3592d2c192SPeter Xu * Map the newly allocated page into IOVA address 0 (size 4K) 3692d2c192SPeter Xu * of the device address space. Root entry and context entry 3792d2c192SPeter Xu * will be automatically created when needed. 3892d2c192SPeter Xu */ 3992d2c192SPeter Xu vtd_map_range(dev->pci_dev.bdf, 0, virt_to_phys(page), PAGE_SIZE); 4092d2c192SPeter Xu 4192d2c192SPeter Xu /* 4292d2c192SPeter Xu * DMA the first 4 bytes of the page to EDU device buffer 4392d2c192SPeter Xu * offset 0. 4492d2c192SPeter Xu */ 4592d2c192SPeter Xu edu_dma(dev, 0, 4, 0, false); 4692d2c192SPeter Xu 4792d2c192SPeter Xu /* 4892d2c192SPeter Xu * DMA the first 4 bytes of EDU device buffer into the page 4992d2c192SPeter Xu * with offset 4 (so it'll be using 4-7 bytes). 5092d2c192SPeter Xu */ 5192d2c192SPeter Xu edu_dma(dev, 4, 4, 0, true); 5292d2c192SPeter Xu 5392d2c192SPeter Xu /* 5492d2c192SPeter Xu * Check data match between 0-3 bytes and 4-7 bytes of the 5592d2c192SPeter Xu * page. 5692d2c192SPeter Xu */ 5792d2c192SPeter Xu report(VTD_TEST_DMAR_4B, *((uint32_t *)page + 1) == DMA_TEST_WORD); 5892d2c192SPeter Xu 5992d2c192SPeter Xu free_page(page); 609e8d01f9SPeter Xu 619e8d01f9SPeter Xu report_prefix_pop(); 6292d2c192SPeter Xu } 6316c0b05fSPeter Xu 647f2477c2SPeter Xu static volatile bool edu_intr_recved; 657f2477c2SPeter Xu 667f2477c2SPeter Xu static void edu_isr(isr_regs_t *regs) 677f2477c2SPeter Xu { 687f2477c2SPeter Xu edu_intr_recved = true; 697f2477c2SPeter Xu eoi(); 708446858dSAndrew Jones edu_reg_writel(&edu_dev, EDU_REG_INTR_ACK, 718446858dSAndrew Jones edu_reg_readl(&edu_dev, EDU_REG_INTR_STATUS)); 727f2477c2SPeter Xu } 737f2477c2SPeter Xu 74c15c99f8SAndrew Jones static void vtd_test_ir(void) 757f2477c2SPeter Xu { 763223ade2SPeter Xu #define VTD_TEST_VECTOR_IOAPIC (0xed) 773223ade2SPeter Xu #define VTD_TEST_VECTOR_MSI (0xee) 78c15c99f8SAndrew Jones struct pci_edu_dev *dev = &edu_dev; 793223ade2SPeter Xu struct pci_dev *pci_dev = &dev->pci_dev; 803223ade2SPeter Xu 819e8d01f9SPeter Xu report_prefix_push("vtd_ir"); 829e8d01f9SPeter Xu 837f2477c2SPeter Xu irq_enable(); 847f2477c2SPeter Xu 853223ade2SPeter Xu /* This will enable INTx */ 863223ade2SPeter Xu pci_msi_set_enable(pci_dev, false); 873223ade2SPeter Xu vtd_setup_ioapic_irq(pci_dev, VTD_TEST_VECTOR_IOAPIC, 883223ade2SPeter Xu 0, TRIGGER_EDGE); 893223ade2SPeter Xu handle_irq(VTD_TEST_VECTOR_IOAPIC, edu_isr); 903223ade2SPeter Xu 913223ade2SPeter Xu edu_intr_recved = false; 923223ade2SPeter Xu wmb(); 937f2477c2SPeter Xu /* Manually trigger INTR */ 947f2477c2SPeter Xu edu_reg_writel(dev, EDU_REG_INTR_RAISE, 1); 957f2477c2SPeter Xu 967f2477c2SPeter Xu while (!edu_intr_recved) 977f2477c2SPeter Xu cpu_relax(); 987f2477c2SPeter Xu 997f2477c2SPeter Xu /* Clear INTR bits */ 1007f2477c2SPeter Xu edu_reg_writel(dev, EDU_REG_INTR_RAISE, 0); 1017f2477c2SPeter Xu 1027f2477c2SPeter Xu /* We are good as long as we reach here */ 1033223ade2SPeter Xu report(VTD_TEST_IR_IOAPIC, edu_intr_recved == true); 1043223ade2SPeter Xu 1053223ade2SPeter Xu /* 1063223ade2SPeter Xu * Setup EDU PCI device MSI, using interrupt remapping. By 1073223ade2SPeter Xu * default, EDU device is using INTx. 1083223ade2SPeter Xu */ 1093223ade2SPeter Xu if (!vtd_setup_msi(pci_dev, VTD_TEST_VECTOR_MSI, 0)) { 1103223ade2SPeter Xu printf("edu device does not support MSI, skip test\n"); 1113223ade2SPeter Xu report_skip(VTD_TEST_IR_MSI); 1123223ade2SPeter Xu return; 1133223ade2SPeter Xu } 1143223ade2SPeter Xu 1153223ade2SPeter Xu handle_irq(VTD_TEST_VECTOR_MSI, edu_isr); 1163223ade2SPeter Xu 1173223ade2SPeter Xu edu_intr_recved = false; 1183223ade2SPeter Xu wmb(); 1193223ade2SPeter Xu /* Manually trigger INTR */ 1203223ade2SPeter Xu edu_reg_writel(dev, EDU_REG_INTR_RAISE, 1); 1213223ade2SPeter Xu 1223223ade2SPeter Xu while (!edu_intr_recved) 1233223ade2SPeter Xu cpu_relax(); 1243223ade2SPeter Xu 1253223ade2SPeter Xu /* We are good as long as we reach here */ 1263223ade2SPeter Xu report(VTD_TEST_IR_MSI, edu_intr_recved == true); 1279e8d01f9SPeter Xu 1289e8d01f9SPeter Xu report_prefix_pop(); 1297f2477c2SPeter Xu } 1307f2477c2SPeter Xu 13116c0b05fSPeter Xu int main(int argc, char *argv[]) 13216c0b05fSPeter Xu { 13316c0b05fSPeter Xu vtd_init(); 13416c0b05fSPeter Xu 1359e8d01f9SPeter Xu report_prefix_push("vtd_init"); 1369e8d01f9SPeter Xu 13716c0b05fSPeter Xu report("fault status check", vtd_readl(DMAR_FSTS_REG) == 0); 13816c0b05fSPeter Xu report("QI enablement", vtd_readl(DMAR_GSTS_REG) & VTD_GCMD_QI); 13916c0b05fSPeter Xu report("DMAR table setup", vtd_readl(DMAR_GSTS_REG) & VTD_GCMD_ROOT); 14016c0b05fSPeter Xu report("IR table setup", vtd_readl(DMAR_GSTS_REG) & VTD_GCMD_IR_TABLE); 14116c0b05fSPeter Xu report("DMAR enablement", vtd_readl(DMAR_GSTS_REG) & VTD_GCMD_DMAR); 14216c0b05fSPeter Xu report("IR enablement", vtd_readl(DMAR_GSTS_REG) & VTD_GCMD_IR); 14392d2c192SPeter Xu report("DMAR support 39 bits address width", 14492d2c192SPeter Xu vtd_readq(DMAR_CAP_REG) & VTD_CAP_SAGAW); 14592d2c192SPeter Xu report("DMAR support huge pages", vtd_readq(DMAR_CAP_REG) & VTD_CAP_SLLPS); 14692d2c192SPeter Xu 1479e8d01f9SPeter Xu report_prefix_pop(); 1489e8d01f9SPeter Xu 149c15c99f8SAndrew Jones if (!edu_init(&edu_dev)) { 15092d2c192SPeter Xu printf("Please specify \"-device edu\" to do " 15192d2c192SPeter Xu "further IOMMU tests.\n"); 15292d2c192SPeter Xu report_skip(VTD_TEST_DMAR_4B); 1533223ade2SPeter Xu report_skip(VTD_TEST_IR_IOAPIC); 1547f2477c2SPeter Xu report_skip(VTD_TEST_IR_MSI); 1557f2477c2SPeter Xu } else { 15682f2f21aSAndrew Jones printf("Found EDU device:\n"); 157*cb026028SAlexander Gordeev pci_dev_print(&edu_dev.pci_dev); 158c15c99f8SAndrew Jones vtd_test_dmar(); 159c15c99f8SAndrew Jones vtd_test_ir(); 1607f2477c2SPeter Xu } 16116c0b05fSPeter Xu 16216c0b05fSPeter Xu return report_summary(); 16316c0b05fSPeter Xu } 164