1 #include "ioram.h" 2 #include "vm.h" 3 #include "libcflat.h" 4 #include "desc.h" 5 #include "types.h" 6 #include "processor.h" 7 8 #define memset __builtin_memset 9 #define TESTDEV_IO_PORT 0xe0 10 11 static int exceptions; 12 13 struct regs { 14 u64 rax, rbx, rcx, rdx; 15 u64 rsi, rdi, rsp, rbp; 16 u64 r8, r9, r10, r11; 17 u64 r12, r13, r14, r15; 18 u64 rip, rflags; 19 }; 20 struct regs inregs, outregs, save; 21 22 struct insn_desc { 23 u64 ptr; 24 size_t len; 25 }; 26 27 static char st1[] = "abcdefghijklmnop"; 28 29 void test_stringio() 30 { 31 unsigned char r = 0; 32 asm volatile("cld \n\t" 33 "movw %0, %%dx \n\t" 34 "rep outsb \n\t" 35 : : "i"((short)TESTDEV_IO_PORT), 36 "S"(st1), "c"(sizeof(st1) - 1)); 37 asm volatile("inb %1, %0\n\t" : "=a"(r) : "i"((short)TESTDEV_IO_PORT)); 38 report("outsb up", r == st1[sizeof(st1) - 2]); /* last char */ 39 40 asm volatile("std \n\t" 41 "movw %0, %%dx \n\t" 42 "rep outsb \n\t" 43 : : "i"((short)TESTDEV_IO_PORT), 44 "S"(st1 + sizeof(st1) - 2), "c"(sizeof(st1) - 1)); 45 asm volatile("cld \n\t" : : ); 46 asm volatile("in %1, %0\n\t" : "=a"(r) : "i"((short)TESTDEV_IO_PORT)); 47 report("outsb down", r == st1[0]); 48 } 49 50 void test_cmps_one(unsigned char *m1, unsigned char *m3) 51 { 52 void *rsi, *rdi; 53 long rcx, tmp; 54 55 rsi = m1; rdi = m3; rcx = 30; 56 asm volatile("xor %[tmp], %[tmp] \n\t" 57 "repe/cmpsb" 58 : "+S"(rsi), "+D"(rdi), "+c"(rcx), [tmp]"=&r"(tmp) 59 : : "cc"); 60 report("repe/cmpsb (1)", rcx == 0 && rsi == m1 + 30 && rdi == m3 + 30); 61 62 rsi = m1; rdi = m3; rcx = 30; 63 asm volatile("or $1, %[tmp]\n\t" // clear ZF 64 "repe/cmpsb" 65 : "+S"(rsi), "+D"(rdi), "+c"(rcx), [tmp]"=&r"(tmp) 66 : : "cc"); 67 report("repe/cmpsb (1.zf)", rcx == 0 && rsi == m1 + 30 && rdi == m3 + 30); 68 69 rsi = m1; rdi = m3; rcx = 15; 70 asm volatile("xor %[tmp], %[tmp] \n\t" 71 "repe/cmpsw" 72 : "+S"(rsi), "+D"(rdi), "+c"(rcx), [tmp]"=&r"(tmp) 73 : : "cc"); 74 report("repe/cmpsw (1)", rcx == 0 && rsi == m1 + 30 && rdi == m3 + 30); 75 76 rsi = m1; rdi = m3; rcx = 7; 77 asm volatile("xor %[tmp], %[tmp] \n\t" 78 "repe/cmpsl" 79 : "+S"(rsi), "+D"(rdi), "+c"(rcx), [tmp]"=&r"(tmp) 80 : : "cc"); 81 report("repe/cmpll (1)", rcx == 0 && rsi == m1 + 28 && rdi == m3 + 28); 82 83 rsi = m1; rdi = m3; rcx = 4; 84 asm volatile("xor %[tmp], %[tmp] \n\t" 85 "repe/cmpsq" 86 : "+S"(rsi), "+D"(rdi), "+c"(rcx), [tmp]"=&r"(tmp) 87 : : "cc"); 88 report("repe/cmpsq (1)", rcx == 0 && rsi == m1 + 32 && rdi == m3 + 32); 89 90 rsi = m1; rdi = m3; rcx = 130; 91 asm volatile("xor %[tmp], %[tmp] \n\t" 92 "repe/cmpsb" 93 : "+S"(rsi), "+D"(rdi), "+c"(rcx), [tmp]"=&r"(tmp) 94 : : "cc"); 95 report("repe/cmpsb (2)", 96 rcx == 29 && rsi == m1 + 101 && rdi == m3 + 101); 97 98 rsi = m1; rdi = m3; rcx = 65; 99 asm volatile("xor %[tmp], %[tmp] \n\t" 100 "repe/cmpsw" 101 : "+S"(rsi), "+D"(rdi), "+c"(rcx), [tmp]"=&r"(tmp) 102 : : "cc"); 103 report("repe/cmpsw (2)", 104 rcx == 14 && rsi == m1 + 102 && rdi == m3 + 102); 105 106 rsi = m1; rdi = m3; rcx = 32; 107 asm volatile("xor %[tmp], %[tmp] \n\t" 108 "repe/cmpsl" 109 : "+S"(rsi), "+D"(rdi), "+c"(rcx), [tmp]"=&r"(tmp) 110 : : "cc"); 111 report("repe/cmpll (2)", 112 rcx == 6 && rsi == m1 + 104 && rdi == m3 + 104); 113 114 rsi = m1; rdi = m3; rcx = 16; 115 asm volatile("xor %[tmp], %[tmp] \n\t" 116 "repe/cmpsq" 117 : "+S"(rsi), "+D"(rdi), "+c"(rcx), [tmp]"=&r"(tmp) 118 : : "cc"); 119 report("repe/cmpsq (2)", 120 rcx == 3 && rsi == m1 + 104 && rdi == m3 + 104); 121 122 } 123 124 void test_cmps(void *mem) 125 { 126 unsigned char *m1 = mem, *m2 = mem + 1024; 127 unsigned char m3[1024]; 128 129 for (int i = 0; i < 100; ++i) 130 m1[i] = m2[i] = m3[i] = i; 131 for (int i = 100; i < 200; ++i) 132 m1[i] = (m3[i] = m2[i] = i) + 1; 133 test_cmps_one(m1, m3); 134 test_cmps_one(m1, m2); 135 } 136 137 void test_scas(void *mem) 138 { 139 bool z; 140 void *di; 141 142 *(ulong *)mem = 0x77665544332211; 143 144 di = mem; 145 asm ("scasb; setz %0" : "=rm"(z), "+D"(di) : "a"(0xff11)); 146 report("scasb match", di == mem + 1 && z); 147 148 di = mem; 149 asm ("scasb; setz %0" : "=rm"(z), "+D"(di) : "a"(0xff54)); 150 report("scasb mismatch", di == mem + 1 && !z); 151 152 di = mem; 153 asm ("scasw; setz %0" : "=rm"(z), "+D"(di) : "a"(0xff2211)); 154 report("scasw match", di == mem + 2 && z); 155 156 di = mem; 157 asm ("scasw; setz %0" : "=rm"(z), "+D"(di) : "a"(0xffdd11)); 158 report("scasw mismatch", di == mem + 2 && !z); 159 160 di = mem; 161 asm ("scasl; setz %0" : "=rm"(z), "+D"(di) : "a"(0xff44332211ul)); 162 report("scasd match", di == mem + 4 && z); 163 164 di = mem; 165 asm ("scasl; setz %0" : "=rm"(z), "+D"(di) : "a"(0x45332211)); 166 report("scasd mismatch", di == mem + 4 && !z); 167 168 di = mem; 169 asm ("scasq; setz %0" : "=rm"(z), "+D"(di) : "a"(0x77665544332211ul)); 170 report("scasq match", di == mem + 8 && z); 171 172 di = mem; 173 asm ("scasq; setz %0" : "=rm"(z), "+D"(di) : "a"(3)); 174 report("scasq mismatch", di == mem + 8 && !z); 175 } 176 177 void test_cr8(void) 178 { 179 unsigned long src, dst; 180 181 dst = 777; 182 src = 3; 183 asm volatile("mov %[src], %%cr8; mov %%cr8, %[dst]" 184 : [dst]"+r"(dst), [src]"+r"(src)); 185 report("mov %%cr8", dst == 3 && src == 3); 186 } 187 188 void test_push(void *mem) 189 { 190 unsigned long tmp; 191 unsigned long *stack_top = mem + 4096; 192 unsigned long *new_stack_top; 193 unsigned long memw = 0x123456789abcdeful; 194 195 memset(mem, 0x55, (void *)stack_top - mem); 196 197 asm volatile("mov %%rsp, %[tmp] \n\t" 198 "mov %[stack_top], %%rsp \n\t" 199 "pushq $-7 \n\t" 200 "pushq %[reg] \n\t" 201 "pushq (%[mem]) \n\t" 202 "pushq $-7070707 \n\t" 203 "mov %%rsp, %[new_stack_top] \n\t" 204 "mov %[tmp], %%rsp" 205 : [tmp]"=&r"(tmp), [new_stack_top]"=r"(new_stack_top) 206 : [stack_top]"r"(stack_top), 207 [reg]"r"(-17l), [mem]"r"(&memw) 208 : "memory"); 209 210 report("push $imm8", stack_top[-1] == -7ul); 211 report("push %%reg", stack_top[-2] == -17ul); 212 report("push mem", stack_top[-3] == 0x123456789abcdeful); 213 report("push $imm", stack_top[-4] == -7070707); 214 } 215 216 void test_pop(void *mem) 217 { 218 unsigned long tmp, tmp3, rsp, rbp; 219 unsigned long *stack_top = mem + 4096; 220 unsigned long memw = 0x123456789abcdeful; 221 static unsigned long tmp2; 222 223 memset(mem, 0x55, (void *)stack_top - mem); 224 225 asm volatile("pushq %[val] \n\t" 226 "popq (%[mem])" 227 : : [val]"m"(memw), [mem]"r"(mem) : "memory"); 228 report("pop mem", *(unsigned long *)mem == memw); 229 230 memw = 7 - memw; 231 asm volatile("mov %%rsp, %[tmp] \n\t" 232 "mov %[stack_top], %%rsp \n\t" 233 "pushq %[val] \n\t" 234 "popq %[tmp2] \n\t" 235 "mov %[tmp], %%rsp" 236 : [tmp]"=&r"(tmp), [tmp2]"=m"(tmp2) 237 : [val]"r"(memw), [stack_top]"r"(stack_top) 238 : "memory"); 239 report("pop mem (2)", tmp2 == memw); 240 241 memw = 129443 - memw; 242 asm volatile("mov %%rsp, %[tmp] \n\t" 243 "mov %[stack_top], %%rsp \n\t" 244 "pushq %[val] \n\t" 245 "popq %[tmp2] \n\t" 246 "mov %[tmp], %%rsp" 247 : [tmp]"=&r"(tmp), [tmp2]"=r"(tmp2) 248 : [val]"r"(memw), [stack_top]"r"(stack_top) 249 : "memory"); 250 report("pop reg", tmp2 == memw); 251 252 asm volatile("mov %%rsp, %[tmp] \n\t" 253 "mov %[stack_top], %%rsp \n\t" 254 "push $1f \n\t" 255 "ret \n\t" 256 "2: jmp 2b \n\t" 257 "1: mov %[tmp], %%rsp" 258 : [tmp]"=&r"(tmp) : [stack_top]"r"(stack_top) 259 : "memory"); 260 report("ret", 1); 261 262 stack_top[-1] = 0x778899; 263 asm volatile("mov %%rsp, %[tmp] \n\t" 264 "mov %%rbp, %[tmp3] \n\t" 265 "mov %[stack_top], %%rbp \n\t" 266 "leave \n\t" 267 "xchg %%rsp, %[tmp] \n\t" 268 "xchg %%rbp, %[tmp3]" 269 : [tmp]"=&r"(tmp), [tmp3]"=&r"(tmp3) : [stack_top]"r"(stack_top-1) 270 : "memory"); 271 report("leave", tmp == (ulong)stack_top && tmp3 == 0x778899); 272 273 rbp = 0xaa55aa55bb66bb66ULL; 274 rsp = (unsigned long)stack_top; 275 asm volatile("xchg %%rsp, %[rsp] \n\t" 276 "xchg %%rbp, %[rbp] \n\t" 277 "enter $0x1238, $0 \n\t" 278 "xchg %%rsp, %[rsp] \n\t" 279 "xchg %%rbp, %[rbp]" 280 : [rsp]"+a"(rsp), [rbp]"+b"(rbp) : : "memory"); 281 report("enter", 282 rsp == (unsigned long)stack_top - 8 - 0x1238 283 && rbp == (unsigned long)stack_top - 8 284 && stack_top[-1] == 0xaa55aa55bb66bb66ULL); 285 } 286 287 void test_ljmp(void *mem) 288 { 289 unsigned char *m = mem; 290 volatile int res = 1; 291 292 *(unsigned long**)m = &&jmpf; 293 asm volatile ("data16/mov %%cs, %0":"=m"(*(m + sizeof(unsigned long)))); 294 asm volatile ("rex64/ljmp *%0"::"m"(*m)); 295 res = 0; 296 jmpf: 297 report("ljmp", res); 298 } 299 300 void test_incdecnotneg(void *mem) 301 { 302 unsigned long *m = mem, v = 1234; 303 unsigned char *mb = mem, vb = 66; 304 305 *m = 0; 306 307 asm volatile ("incl %0":"+m"(*m)); 308 report("incl", *m == 1); 309 asm volatile ("decl %0":"+m"(*m)); 310 report("decl", *m == 0); 311 asm volatile ("incb %0":"+m"(*m)); 312 report("incb", *m == 1); 313 asm volatile ("decb %0":"+m"(*m)); 314 report("decb", *m == 0); 315 316 asm volatile ("lock incl %0":"+m"(*m)); 317 report("lock incl", *m == 1); 318 asm volatile ("lock decl %0":"+m"(*m)); 319 report("lock decl", *m == 0); 320 asm volatile ("lock incb %0":"+m"(*m)); 321 report("lock incb", *m == 1); 322 asm volatile ("lock decb %0":"+m"(*m)); 323 report("lock decb", *m == 0); 324 325 *m = v; 326 327 asm ("lock negq %0" : "+m"(*m)); v = -v; 328 report("lock negl", *m == v); 329 asm ("lock notq %0" : "+m"(*m)); v = ~v; 330 report("lock notl", *m == v); 331 332 *mb = vb; 333 334 asm ("lock negb %0" : "+m"(*mb)); vb = -vb; 335 report("lock negb", *mb == vb); 336 asm ("lock notb %0" : "+m"(*mb)); vb = ~vb; 337 report("lock notb", *mb == vb); 338 } 339 340 void test_smsw(uint64_t *h_mem) 341 { 342 char mem[16]; 343 unsigned short msw, msw_orig, *pmsw; 344 int i, zero; 345 346 msw_orig = read_cr0(); 347 348 asm("smsw %0" : "=r"(msw)); 349 report("smsw (1)", msw == msw_orig); 350 351 memset(mem, 0, 16); 352 pmsw = (void *)mem; 353 asm("smsw %0" : "=m"(pmsw[4])); 354 zero = 1; 355 for (i = 0; i < 8; ++i) 356 if (i != 4 && pmsw[i]) 357 zero = 0; 358 report("smsw (2)", msw == pmsw[4] && zero); 359 360 /* Trigger exit on smsw */ 361 *h_mem = 0x12345678abcdeful; 362 asm volatile("smsw %0" : "+m"(*h_mem)); 363 report("smsw (3)", msw == (unsigned short)*h_mem && 364 (*h_mem & ~0xfffful) == 0x12345678ab0000ul); 365 } 366 367 void test_lmsw(void) 368 { 369 char mem[16]; 370 unsigned short msw, *pmsw; 371 unsigned long cr0; 372 373 cr0 = read_cr0(); 374 375 msw = cr0 ^ 8; 376 asm("lmsw %0" : : "r"(msw)); 377 printf("before %lx after %lx\n", cr0, read_cr0()); 378 report("lmsw (1)", (cr0 ^ read_cr0()) == 8); 379 380 pmsw = (void *)mem; 381 *pmsw = cr0; 382 asm("lmsw %0" : : "m"(*pmsw)); 383 printf("before %lx after %lx\n", cr0, read_cr0()); 384 report("lmsw (2)", cr0 == read_cr0()); 385 386 /* lmsw can't clear cr0.pe */ 387 msw = (cr0 & ~1ul) ^ 4; /* change EM to force trap */ 388 asm("lmsw %0" : : "r"(msw)); 389 report("lmsw (3)", (cr0 ^ read_cr0()) == 4 && (cr0 & 1)); 390 391 /* back to normal */ 392 msw = cr0; 393 asm("lmsw %0" : : "r"(msw)); 394 } 395 396 void test_xchg(void *mem) 397 { 398 unsigned long *memq = mem; 399 unsigned long rax; 400 401 asm volatile("mov $0x123456789abcdef, %%rax\n\t" 402 "mov %%rax, (%[memq])\n\t" 403 "mov $0xfedcba9876543210, %%rax\n\t" 404 "xchg %%al, (%[memq])\n\t" 405 "mov %%rax, %[rax]\n\t" 406 : [rax]"=r"(rax) 407 : [memq]"r"(memq) 408 : "memory"); 409 report("xchg reg, r/m (1)", 410 rax == 0xfedcba98765432ef && *memq == 0x123456789abcd10); 411 412 asm volatile("mov $0x123456789abcdef, %%rax\n\t" 413 "mov %%rax, (%[memq])\n\t" 414 "mov $0xfedcba9876543210, %%rax\n\t" 415 "xchg %%ax, (%[memq])\n\t" 416 "mov %%rax, %[rax]\n\t" 417 : [rax]"=r"(rax) 418 : [memq]"r"(memq) 419 : "memory"); 420 report("xchg reg, r/m (2)", 421 rax == 0xfedcba987654cdef && *memq == 0x123456789ab3210); 422 423 asm volatile("mov $0x123456789abcdef, %%rax\n\t" 424 "mov %%rax, (%[memq])\n\t" 425 "mov $0xfedcba9876543210, %%rax\n\t" 426 "xchg %%eax, (%[memq])\n\t" 427 "mov %%rax, %[rax]\n\t" 428 : [rax]"=r"(rax) 429 : [memq]"r"(memq) 430 : "memory"); 431 report("xchg reg, r/m (3)", 432 rax == 0x89abcdef && *memq == 0x123456776543210); 433 434 asm volatile("mov $0x123456789abcdef, %%rax\n\t" 435 "mov %%rax, (%[memq])\n\t" 436 "mov $0xfedcba9876543210, %%rax\n\t" 437 "xchg %%rax, (%[memq])\n\t" 438 "mov %%rax, %[rax]\n\t" 439 : [rax]"=r"(rax) 440 : [memq]"r"(memq) 441 : "memory"); 442 report("xchg reg, r/m (4)", 443 rax == 0x123456789abcdef && *memq == 0xfedcba9876543210); 444 } 445 446 void test_xadd(void *mem) 447 { 448 unsigned long *memq = mem; 449 unsigned long rax; 450 451 asm volatile("mov $0x123456789abcdef, %%rax\n\t" 452 "mov %%rax, (%[memq])\n\t" 453 "mov $0xfedcba9876543210, %%rax\n\t" 454 "xadd %%al, (%[memq])\n\t" 455 "mov %%rax, %[rax]\n\t" 456 : [rax]"=r"(rax) 457 : [memq]"r"(memq) 458 : "memory"); 459 report("xadd reg, r/m (1)", 460 rax == 0xfedcba98765432ef && *memq == 0x123456789abcdff); 461 462 asm volatile("mov $0x123456789abcdef, %%rax\n\t" 463 "mov %%rax, (%[memq])\n\t" 464 "mov $0xfedcba9876543210, %%rax\n\t" 465 "xadd %%ax, (%[memq])\n\t" 466 "mov %%rax, %[rax]\n\t" 467 : [rax]"=r"(rax) 468 : [memq]"r"(memq) 469 : "memory"); 470 report("xadd reg, r/m (2)", 471 rax == 0xfedcba987654cdef && *memq == 0x123456789abffff); 472 473 asm volatile("mov $0x123456789abcdef, %%rax\n\t" 474 "mov %%rax, (%[memq])\n\t" 475 "mov $0xfedcba9876543210, %%rax\n\t" 476 "xadd %%eax, (%[memq])\n\t" 477 "mov %%rax, %[rax]\n\t" 478 : [rax]"=r"(rax) 479 : [memq]"r"(memq) 480 : "memory"); 481 report("xadd reg, r/m (3)", 482 rax == 0x89abcdef && *memq == 0x1234567ffffffff); 483 484 asm volatile("mov $0x123456789abcdef, %%rax\n\t" 485 "mov %%rax, (%[memq])\n\t" 486 "mov $0xfedcba9876543210, %%rax\n\t" 487 "xadd %%rax, (%[memq])\n\t" 488 "mov %%rax, %[rax]\n\t" 489 : [rax]"=r"(rax) 490 : [memq]"r"(memq) 491 : "memory"); 492 report("xadd reg, r/m (4)", 493 rax == 0x123456789abcdef && *memq == 0xffffffffffffffff); 494 } 495 496 void test_btc(void *mem) 497 { 498 unsigned int *a = mem; 499 500 memset(mem, 0, 4 * sizeof(unsigned int)); 501 502 asm ("btcl $32, %0" :: "m"(a[0]) : "memory"); 503 asm ("btcl $1, %0" :: "m"(a[1]) : "memory"); 504 asm ("btcl %1, %0" :: "m"(a[0]), "r"(66) : "memory"); 505 report("btcl imm8, r/m", a[0] == 1 && a[1] == 2 && a[2] == 4); 506 507 asm ("btcl %1, %0" :: "m"(a[3]), "r"(-1) : "memory"); 508 report("btcl reg, r/m", a[0] == 1 && a[1] == 2 && a[2] == 0x80000004); 509 510 asm ("btcq %1, %0" : : "m"(a[2]), "r"(-1l) : "memory"); 511 report("btcq reg, r/m", a[0] == 1 && a[1] == 0x80000002 && 512 a[2] == 0x80000004 && a[3] == 0); 513 } 514 515 void test_bsfbsr(void *mem) 516 { 517 unsigned long rax, *memq = mem; 518 unsigned eax, *meml = mem; 519 unsigned short ax, *memw = mem; 520 unsigned char z; 521 522 *memw = 0xc000; 523 asm("bsfw %[mem], %[a]" : [a]"=a"(ax) : [mem]"m"(*memw)); 524 report("bsfw r/m, reg", ax == 14); 525 526 *meml = 0xc0000000; 527 asm("bsfl %[mem], %[a]" : [a]"=a"(eax) : [mem]"m"(*meml)); 528 report("bsfl r/m, reg", eax == 30); 529 530 *memq = 0xc00000000000; 531 asm("bsfq %[mem], %[a]" : [a]"=a"(rax) : [mem]"m"(*memq)); 532 report("bsfq r/m, reg", rax == 46); 533 534 *memq = 0; 535 asm("bsfq %[mem], %[a]; setz %[z]" 536 : [a]"=a"(rax), [z]"=rm"(z) : [mem]"m"(*memq)); 537 report("bsfq r/m, reg", z == 1); 538 539 *memw = 0xc000; 540 asm("bsrw %[mem], %[a]" : [a]"=a"(ax) : [mem]"m"(*memw)); 541 report("bsrw r/m, reg", ax == 15); 542 543 *meml = 0xc0000000; 544 asm("bsrl %[mem], %[a]" : [a]"=a"(eax) : [mem]"m"(*meml)); 545 report("bsrl r/m, reg", eax == 31); 546 547 *memq = 0xc00000000000; 548 asm("bsrq %[mem], %[a]" : [a]"=a"(rax) : [mem]"m"(*memq)); 549 report("bsrq r/m, reg", rax == 47); 550 551 *memq = 0; 552 asm("bsrq %[mem], %[a]; setz %[z]" 553 : [a]"=a"(rax), [z]"=rm"(z) : [mem]"m"(*memq)); 554 report("bsrq r/m, reg", z == 1); 555 } 556 557 static void test_imul(ulong *mem) 558 { 559 ulong a; 560 561 *mem = 51; a = 0x1234567812345678UL; 562 asm ("imulw %1, %%ax" : "+a"(a) : "m"(*mem)); 563 report("imul ax, mem", a == 0x12345678123439e8); 564 565 *mem = 51; a = 0x1234567812345678UL; 566 asm ("imull %1, %%eax" : "+a"(a) : "m"(*mem)); 567 report("imul eax, mem", a == 0xa06d39e8); 568 569 *mem = 51; a = 0x1234567812345678UL; 570 asm ("imulq %1, %%rax" : "+a"(a) : "m"(*mem)); 571 report("imul rax, mem", a == 0xA06D39EBA06D39E8UL); 572 573 *mem = 0x1234567812345678UL; a = 0x8765432187654321L; 574 asm ("imulw $51, %1, %%ax" : "+a"(a) : "m"(*mem)); 575 report("imul ax, mem, imm8", a == 0x87654321876539e8); 576 577 *mem = 0x1234567812345678UL; 578 asm ("imull $51, %1, %%eax" : "+a"(a) : "m"(*mem)); 579 report("imul eax, mem, imm8", a == 0xa06d39e8); 580 581 *mem = 0x1234567812345678UL; 582 asm ("imulq $51, %1, %%rax" : "+a"(a) : "m"(*mem)); 583 report("imul rax, mem, imm8", a == 0xA06D39EBA06D39E8UL); 584 585 *mem = 0x1234567812345678UL; a = 0x8765432187654321L; 586 asm ("imulw $311, %1, %%ax" : "+a"(a) : "m"(*mem)); 587 report("imul ax, mem, imm", a == 0x8765432187650bc8); 588 589 *mem = 0x1234567812345678UL; 590 asm ("imull $311, %1, %%eax" : "+a"(a) : "m"(*mem)); 591 report("imul eax, mem, imm", a == 0x1d950bc8); 592 593 *mem = 0x1234567812345678UL; 594 asm ("imulq $311, %1, %%rax" : "+a"(a) : "m"(*mem)); 595 report("imul rax, mem, imm", a == 0x1D950BDE1D950BC8L); 596 } 597 598 static void test_muldiv(long *mem) 599 { 600 long a, d, aa, dd; 601 u8 ex = 1; 602 603 *mem = 0; a = 1; d = 2; 604 asm (ASM_TRY("1f") "divq %3; movb $0, %2; 1:" 605 : "+a"(a), "+d"(d), "+q"(ex) : "m"(*mem)); 606 report("divq (fault)", a == 1 && d == 2 && ex); 607 608 *mem = 987654321098765UL; a = 123456789012345UL; d = 123456789012345UL; 609 asm (ASM_TRY("1f") "divq %3; movb $0, %2; 1:" 610 : "+a"(a), "+d"(d), "+q"(ex) : "m"(*mem)); 611 report("divq (1)", 612 a == 0x1ffffffb1b963b33ul && d == 0x273ba4384ede2ul && !ex); 613 aa = 0x1111111111111111; dd = 0x2222222222222222; 614 *mem = 0x3333333333333333; a = aa; d = dd; 615 asm("mulb %2" : "+a"(a), "+d"(d) : "m"(*mem)); 616 report("mulb mem", a == 0x1111111111110363 && d == dd); 617 *mem = 0x3333333333333333; a = aa; d = dd; 618 asm("mulw %2" : "+a"(a), "+d"(d) : "m"(*mem)); 619 report("mulw mem", a == 0x111111111111c963 && d == 0x2222222222220369); 620 *mem = 0x3333333333333333; a = aa; d = dd; 621 asm("mull %2" : "+a"(a), "+d"(d) : "m"(*mem)); 622 report("mull mem", a == 0x962fc963 && d == 0x369d036); 623 *mem = 0x3333333333333333; a = aa; d = dd; 624 asm("mulq %2" : "+a"(a), "+d"(d) : "m"(*mem)); 625 report("mulq mem", a == 0x2fc962fc962fc963 && d == 0x369d0369d0369d0); 626 } 627 628 typedef unsigned __attribute__((vector_size(16))) sse128; 629 630 typedef union { 631 sse128 sse; 632 unsigned u[4]; 633 } sse_union; 634 635 static bool sseeq(sse_union *v1, sse_union *v2) 636 { 637 bool ok = true; 638 int i; 639 640 for (i = 0; i < 4; ++i) { 641 ok &= v1->u[i] == v2->u[i]; 642 } 643 644 return ok; 645 } 646 647 static void test_sse(sse_union *mem) 648 { 649 sse_union v; 650 651 write_cr0(read_cr0() & ~6); /* EM, TS */ 652 write_cr4(read_cr4() | 0x200); /* OSFXSR */ 653 v.u[0] = 1; v.u[1] = 2; v.u[2] = 3; v.u[3] = 4; 654 asm("movdqu %1, %0" : "=m"(*mem) : "x"(v.sse)); 655 report("movdqu (read)", sseeq(&v, mem)); 656 mem->u[0] = 5; mem->u[1] = 6; mem->u[2] = 7; mem->u[3] = 8; 657 asm("movdqu %1, %0" : "=x"(v.sse) : "m"(*mem)); 658 report("movdqu (write)", sseeq(mem, &v)); 659 660 v.u[0] = 1; v.u[1] = 2; v.u[2] = 3; v.u[3] = 4; 661 asm("movaps %1, %0" : "=m"(*mem) : "x"(v.sse)); 662 report("movaps (read)", sseeq(mem, &v)); 663 mem->u[0] = 5; mem->u[1] = 6; mem->u[2] = 7; mem->u[3] = 8; 664 asm("movaps %1, %0" : "=x"(v.sse) : "m"(*mem)); 665 report("movaps (write)", sseeq(&v, mem)); 666 667 v.u[0] = 1; v.u[1] = 2; v.u[2] = 3; v.u[3] = 4; 668 asm("movapd %1, %0" : "=m"(*mem) : "x"(v.sse)); 669 report("movapd (read)", sseeq(mem, &v)); 670 mem->u[0] = 5; mem->u[1] = 6; mem->u[2] = 7; mem->u[3] = 8; 671 asm("movapd %1, %0" : "=x"(v.sse) : "m"(*mem)); 672 report("movapd (write)", sseeq(&v, mem)); 673 } 674 675 static void test_mmx(uint64_t *mem) 676 { 677 uint64_t v; 678 679 write_cr0(read_cr0() & ~6); /* EM, TS */ 680 asm volatile("fninit"); 681 v = 0x0102030405060708ULL; 682 asm("movq %1, %0" : "=m"(*mem) : "y"(v)); 683 report("movq (mmx, read)", v == *mem); 684 *mem = 0x8070605040302010ull; 685 asm("movq %1, %0" : "=y"(v) : "m"(*mem)); 686 report("movq (mmx, write)", v == *mem); 687 } 688 689 static void test_rip_relative(unsigned *mem, char *insn_ram) 690 { 691 /* movb $1, mem+2(%rip) */ 692 insn_ram[0] = 0xc6; 693 insn_ram[1] = 0x05; 694 *(unsigned *)&insn_ram[2] = 2 + (char *)mem - (insn_ram + 7); 695 insn_ram[6] = 0x01; 696 /* ret */ 697 insn_ram[7] = 0xc3; 698 699 *mem = 0; 700 asm("callq *%1" : "+m"(*mem) : "r"(insn_ram)); 701 report("movb $imm, 0(%%rip)", *mem == 0x10000); 702 } 703 704 static void test_shld_shrd(u32 *mem) 705 { 706 *mem = 0x12345678; 707 asm("shld %2, %1, %0" : "+m"(*mem) : "r"(0xaaaaaaaaU), "c"((u8)3)); 708 report("shld (cl)", *mem == ((0x12345678 << 3) | 5)); 709 *mem = 0x12345678; 710 asm("shrd %2, %1, %0" : "+m"(*mem) : "r"(0x55555555U), "c"((u8)3)); 711 report("shrd (cl)", *mem == ((0x12345678 >> 3) | (5u << 29))); 712 } 713 714 static void test_cmov(u32 *mem) 715 { 716 u64 val; 717 *mem = 0xabcdef12u; 718 asm ("movq $0x1234567812345678, %%rax\n\t" 719 "cmpl %%eax, %%eax\n\t" 720 "cmovnel (%[mem]), %%eax\n\t" 721 "movq %%rax, %[val]\n\t" 722 : [val]"=r"(val) : [mem]"r"(mem) : "%rax", "cc"); 723 report("cmovnel", val == 0x12345678ul); 724 } 725 726 #define INSN_XCHG_ALL \ 727 "xchg %rax, 0+save \n\t" \ 728 "xchg %rbx, 8+save \n\t" \ 729 "xchg %rcx, 16+save \n\t" \ 730 "xchg %rdx, 24+save \n\t" \ 731 "xchg %rsi, 32+save \n\t" \ 732 "xchg %rdi, 40+save \n\t" \ 733 "xchg %rsp, 48+save \n\t" \ 734 "xchg %rbp, 56+save \n\t" \ 735 "xchg %r8, 64+save \n\t" \ 736 "xchg %r9, 72+save \n\t" \ 737 "xchg %r10, 80+save \n\t" \ 738 "xchg %r11, 88+save \n\t" \ 739 "xchg %r12, 96+save \n\t" \ 740 "xchg %r13, 104+save \n\t" \ 741 "xchg %r14, 112+save \n\t" \ 742 "xchg %r15, 120+save \n\t" 743 744 asm( 745 ".align 4096\n\t" 746 "insn_page:\n\t" 747 "ret\n\t" 748 "pushf\n\t" 749 "push 136+save \n\t" 750 "popf \n\t" 751 INSN_XCHG_ALL 752 "test_insn:\n\t" 753 "in (%dx),%al\n\t" 754 ".skip 31, 0x90\n\t" 755 "test_insn_end:\n\t" 756 INSN_XCHG_ALL 757 "pushf \n\t" 758 "pop 136+save \n\t" 759 "popf \n\t" 760 "ret \n\t" 761 "insn_page_end:\n\t" 762 ".align 4096\n\t" 763 ); 764 765 #define MK_INSN(name, str) \ 766 asm ( \ 767 ".pushsection .data.insn \n\t" \ 768 "insn_" #name ": \n\t" \ 769 ".quad 1001f, 1002f - 1001f \n\t" \ 770 ".popsection \n\t" \ 771 ".pushsection .text.insn, \"ax\" \n\t" \ 772 "1001: \n\t" \ 773 "insn_code_" #name ": " str " \n\t" \ 774 "1002: \n\t" \ 775 ".popsection" \ 776 ); \ 777 extern struct insn_desc insn_##name; 778 779 static void trap_emulator(uint64_t *mem, void *alt_insn_page, 780 struct insn_desc *alt_insn) 781 { 782 ulong *cr3 = (ulong *)read_cr3(); 783 void *insn_ram; 784 extern u8 insn_page[], test_insn[]; 785 786 insn_ram = vmap(virt_to_phys(insn_page), 4096); 787 memcpy(alt_insn_page, insn_page, 4096); 788 memcpy(alt_insn_page + (test_insn - insn_page), 789 (void *)(alt_insn->ptr), alt_insn->len); 790 save = inregs; 791 792 /* Load the code TLB with insn_page, but point the page tables at 793 alt_insn_page (and keep the data TLB clear, for AMD decode assist). 794 This will make the CPU trap on the insn_page instruction but the 795 hypervisor will see alt_insn_page. */ 796 install_page(cr3, virt_to_phys(insn_page), insn_ram); 797 invlpg(insn_ram); 798 /* Load code TLB */ 799 asm volatile("call *%0" : : "r"(insn_ram)); 800 install_page(cr3, virt_to_phys(alt_insn_page), insn_ram); 801 /* Trap, let hypervisor emulate at alt_insn_page */ 802 asm volatile("call *%0": : "r"(insn_ram+1)); 803 804 outregs = save; 805 } 806 807 static void advance_rip_by_3_and_note_exception(struct ex_regs *regs) 808 { 809 ++exceptions; 810 regs->rip += 3; 811 } 812 813 static void test_mmx_movq_mf(uint64_t *mem, uint8_t *insn_page, 814 uint8_t *alt_insn_page, void *insn_ram) 815 { 816 uint16_t fcw = 0; /* all exceptions unmasked */ 817 /* movq %mm0, (%rax) */ 818 void *stack = alloc_page(); 819 820 write_cr0(read_cr0() & ~6); /* TS, EM */ 821 exceptions = 0; 822 handle_exception(MF_VECTOR, advance_rip_by_3_and_note_exception); 823 asm volatile("fninit; fldcw %0" : : "m"(fcw)); 824 asm volatile("fldz; fldz; fdivp"); /* generate exception */ 825 826 MK_INSN(mmx_movq_mf, "movq %mm0, (%rax) \n\t"); 827 inregs = (struct regs){ .rsp=(u64)stack+1024 }; 828 trap_emulator(mem, alt_insn_page, &insn_mmx_movq_mf); 829 /* exit MMX mode */ 830 asm volatile("fnclex; emms"); 831 report("movq mmx generates #MF", exceptions == 1); 832 handle_exception(MF_VECTOR, 0); 833 } 834 835 static void test_jmp_noncanonical(uint64_t *mem) 836 { 837 *mem = 0x1111111111111111ul; 838 839 exceptions = 0; 840 handle_exception(GP_VECTOR, advance_rip_by_3_and_note_exception); 841 asm volatile ("jmp *%0" : : "m"(*mem)); 842 report("jump to non-canonical address", exceptions == 1); 843 handle_exception(GP_VECTOR, 0); 844 } 845 846 static void test_movabs(uint64_t *mem, uint8_t *insn_page, 847 uint8_t *alt_insn_page, void *insn_ram) 848 { 849 /* mov $0x9090909090909090, %rcx */ 850 MK_INSN(movabs, "mov $0x9090909090909090, %rcx\n\t"); 851 inregs = (struct regs){ 0 }; 852 trap_emulator(mem, alt_insn_page, &insn_movabs); 853 report("64-bit mov imm2", outregs.rcx == 0x9090909090909090); 854 } 855 856 static void test_smsw_reg(uint64_t *mem, uint8_t *insn_page, 857 uint8_t *alt_insn_page, void *insn_ram) 858 { 859 unsigned long cr0 = read_cr0(); 860 inregs = (struct regs){ .rax = 0x1234567890abcdeful }; 861 862 MK_INSN(smsww, "smsww %ax\n\t"); 863 trap_emulator(mem, alt_insn_page, &insn_smsww); 864 report("16-bit smsw reg", (u16)outregs.rax == (u16)cr0 && 865 outregs.rax >> 16 == inregs.rax >> 16); 866 867 MK_INSN(smswl, "smswl %eax\n\t"); 868 trap_emulator(mem, alt_insn_page, &insn_smswl); 869 report("32-bit smsw reg", outregs.rax == (u32)cr0); 870 871 MK_INSN(smswq, "smswq %rax\n\t"); 872 trap_emulator(mem, alt_insn_page, &insn_smswq); 873 report("64-bit smsw reg", outregs.rax == cr0); 874 } 875 876 static void test_nop(uint64_t *mem, uint8_t *insn_page, 877 uint8_t *alt_insn_page, void *insn_ram) 878 { 879 inregs = (struct regs){ .rax = 0x1234567890abcdeful }; 880 MK_INSN(nop, "nop\n\t"); 881 trap_emulator(mem, alt_insn_page, &insn_nop); 882 report("nop", outregs.rax == inregs.rax); 883 } 884 885 static void test_mov_dr(uint64_t *mem, uint8_t *insn_page, 886 uint8_t *alt_insn_page, void *insn_ram) 887 { 888 bool rtm_support = cpuid(7).b & (1 << 11); 889 unsigned long dr6_fixed_1 = rtm_support ? 0xfffe0ff0ul : 0xffff0ff0ul; 890 inregs = (struct regs){ .rax = 0 }; 891 MK_INSN(mov_to_dr6, "movq %rax, %dr6\n\t"); 892 trap_emulator(mem, alt_insn_page, &insn_mov_to_dr6); 893 MK_INSN(mov_from_dr6, "movq %dr6, %rax\n\t"); 894 trap_emulator(mem, alt_insn_page, &insn_mov_from_dr6); 895 report("mov_dr6", outregs.rax == dr6_fixed_1); 896 } 897 898 static void test_push16(uint64_t *mem) 899 { 900 uint64_t rsp1, rsp2; 901 uint16_t r; 902 903 asm volatile ( "movq %%rsp, %[rsp1]\n\t" 904 "pushw %[v]\n\t" 905 "popw %[r]\n\t" 906 "movq %%rsp, %[rsp2]\n\t" 907 "movq %[rsp1], %%rsp\n\t" : 908 [rsp1]"=r"(rsp1), [rsp2]"=r"(rsp2), [r]"=r"(r) 909 : [v]"m"(*mem) : "memory"); 910 report("push16", rsp1 == rsp2); 911 } 912 913 static void test_crosspage_mmio(volatile uint8_t *mem) 914 { 915 volatile uint16_t w, *pw; 916 917 pw = (volatile uint16_t *)&mem[4095]; 918 mem[4095] = 0x99; 919 mem[4096] = 0x77; 920 asm volatile("mov %1, %0" : "=r"(w) : "m"(*pw) : "memory"); 921 report("cross-page mmio read", w == 0x7799); 922 asm volatile("mov %1, %0" : "=m"(*pw) : "r"((uint16_t)0x88aa)); 923 report("cross-page mmio write", mem[4095] == 0xaa && mem[4096] == 0x88); 924 } 925 926 static void test_string_io_mmio(volatile uint8_t *mem) 927 { 928 /* Cross MMIO pages.*/ 929 volatile uint8_t *mmio = mem + 4032; 930 931 asm volatile("outw %%ax, %%dx \n\t" : : "a"(0x9999), "d"(TESTDEV_IO_PORT)); 932 933 asm volatile ("cld; rep insb" : : "d" (TESTDEV_IO_PORT), "D" (mmio), "c" (1024)); 934 935 report("string_io_mmio", mmio[1023] == 0x99); 936 } 937 938 /* kvm doesn't allow lidt/lgdt from mmio, so the test is disabled */ 939 #if 0 940 static void test_lgdt_lidt(volatile uint8_t *mem) 941 { 942 struct descriptor_table_ptr orig, fresh = {}; 943 944 sgdt(&orig); 945 *(struct descriptor_table_ptr *)mem = (struct descriptor_table_ptr) { 946 .limit = 0xf234, 947 .base = 0x12345678abcd, 948 }; 949 cli(); 950 asm volatile("lgdt %0" : : "m"(*(struct descriptor_table_ptr *)mem)); 951 sgdt(&fresh); 952 lgdt(&orig); 953 sti(); 954 report("lgdt (long address)", orig.limit == fresh.limit && orig.base == fresh.base); 955 956 sidt(&orig); 957 *(struct descriptor_table_ptr *)mem = (struct descriptor_table_ptr) { 958 .limit = 0x432f, 959 .base = 0xdbca87654321, 960 }; 961 cli(); 962 asm volatile("lidt %0" : : "m"(*(struct descriptor_table_ptr *)mem)); 963 sidt(&fresh); 964 lidt(&orig); 965 sti(); 966 report("lidt (long address)", orig.limit == fresh.limit && orig.base == fresh.base); 967 } 968 #endif 969 970 static void ss_bad_rpl(struct ex_regs *regs) 971 { 972 extern char ss_bad_rpl_cont; 973 974 ++exceptions; 975 regs->rip = (ulong)&ss_bad_rpl_cont; 976 } 977 978 static void test_sreg(volatile uint16_t *mem) 979 { 980 u16 ss = read_ss(); 981 982 // check for null segment load 983 *mem = 0; 984 asm volatile("mov %0, %%ss" : : "m"(*mem)); 985 report("mov null, %%ss", read_ss() == 0); 986 987 // check for exception when ss.rpl != cpl on null segment load 988 exceptions = 0; 989 handle_exception(GP_VECTOR, ss_bad_rpl); 990 *mem = 3; 991 asm volatile("mov %0, %%ss; ss_bad_rpl_cont:" : : "m"(*mem)); 992 report("mov null, %%ss (with ss.rpl != cpl)", exceptions == 1 && read_ss() == 0); 993 handle_exception(GP_VECTOR, 0); 994 write_ss(ss); 995 } 996 997 static void test_lldt(volatile uint16_t *mem) 998 { 999 u64 gdt[] = { 0, 0x0000f82000000ffffull /* ldt descriptor */ }; 1000 struct descriptor_table_ptr gdt_ptr = { .limit = 0xffff, .base = (ulong)&gdt }; 1001 struct descriptor_table_ptr orig_gdt; 1002 1003 cli(); 1004 sgdt(&orig_gdt); 1005 lgdt(&gdt_ptr); 1006 *mem = 0x8; 1007 asm volatile("lldt %0" : : "m"(*mem)); 1008 lgdt(&orig_gdt); 1009 sti(); 1010 report("lldt", sldt() == *mem); 1011 } 1012 1013 static void test_ltr(volatile uint16_t *mem) 1014 { 1015 struct descriptor_table_ptr gdt_ptr; 1016 uint64_t *gdt, *trp; 1017 uint16_t tr = str(); 1018 uint64_t busy_mask = (uint64_t)1 << 41; 1019 1020 sgdt(&gdt_ptr); 1021 gdt = (uint64_t *)gdt_ptr.base; 1022 trp = &gdt[tr >> 3]; 1023 *trp &= ~busy_mask; 1024 *mem = tr; 1025 asm volatile("ltr %0" : : "m"(*mem) : "memory"); 1026 report("ltr", str() == tr && (*trp & busy_mask)); 1027 } 1028 1029 static void test_simplealu(u32 *mem) 1030 { 1031 *mem = 0x1234; 1032 asm("or %1, %0" : "+m"(*mem) : "r"(0x8001)); 1033 report("or", *mem == 0x9235); 1034 asm("add %1, %0" : "+m"(*mem) : "r"(2)); 1035 report("add", *mem == 0x9237); 1036 asm("xor %1, %0" : "+m"(*mem) : "r"(0x1111)); 1037 report("xor", *mem == 0x8326); 1038 asm("sub %1, %0" : "+m"(*mem) : "r"(0x26)); 1039 report("sub", *mem == 0x8300); 1040 asm("clc; adc %1, %0" : "+m"(*mem) : "r"(0x100)); 1041 report("adc(0)", *mem == 0x8400); 1042 asm("stc; adc %1, %0" : "+m"(*mem) : "r"(0x100)); 1043 report("adc(0)", *mem == 0x8501); 1044 asm("clc; sbb %1, %0" : "+m"(*mem) : "r"(0)); 1045 report("sbb(0)", *mem == 0x8501); 1046 asm("stc; sbb %1, %0" : "+m"(*mem) : "r"(0)); 1047 report("sbb(1)", *mem == 0x8500); 1048 asm("and %1, %0" : "+m"(*mem) : "r"(0xfe77)); 1049 report("and", *mem == 0x8400); 1050 asm("test %1, %0" : "+m"(*mem) : "r"(0xf000)); 1051 report("test", *mem == 0x8400); 1052 } 1053 1054 static void illegal_movbe_handler(struct ex_regs *regs) 1055 { 1056 extern char bad_movbe_cont; 1057 1058 ++exceptions; 1059 regs->rip = (ulong)&bad_movbe_cont; 1060 } 1061 1062 static void test_illegal_movbe(void) 1063 { 1064 if (!(cpuid(1).c & (1 << 22))) { 1065 printf("SKIP: illegal movbe\n"); 1066 return; 1067 } 1068 1069 exceptions = 0; 1070 handle_exception(UD_VECTOR, illegal_movbe_handler); 1071 asm volatile(".byte 0x0f; .byte 0x38; .byte 0xf0; .byte 0xc0;\n\t" 1072 " bad_movbe_cont:" : : : "rax"); 1073 report("illegal movbe", exceptions == 1); 1074 handle_exception(UD_VECTOR, 0); 1075 } 1076 1077 int main() 1078 { 1079 void *mem; 1080 void *insn_page, *alt_insn_page; 1081 void *insn_ram; 1082 unsigned long t1, t2; 1083 1084 setup_vm(); 1085 setup_idt(); 1086 mem = alloc_vpages(2); 1087 install_page((void *)read_cr3(), IORAM_BASE_PHYS, mem); 1088 // install the page twice to test cross-page mmio 1089 install_page((void *)read_cr3(), IORAM_BASE_PHYS, mem + 4096); 1090 insn_page = alloc_page(); 1091 alt_insn_page = alloc_page(); 1092 insn_ram = vmap(virt_to_phys(insn_page), 4096); 1093 1094 // test mov reg, r/m and mov r/m, reg 1095 t1 = 0x123456789abcdef; 1096 asm volatile("mov %[t1], (%[mem]) \n\t" 1097 "mov (%[mem]), %[t2]" 1098 : [t2]"=r"(t2) 1099 : [t1]"r"(t1), [mem]"r"(mem) 1100 : "memory"); 1101 report("mov reg, r/m (1)", t2 == 0x123456789abcdef); 1102 1103 test_simplealu(mem); 1104 test_cmps(mem); 1105 test_scas(mem); 1106 1107 test_push(mem); 1108 test_pop(mem); 1109 1110 test_xchg(mem); 1111 test_xadd(mem); 1112 1113 test_cr8(); 1114 1115 test_smsw(mem); 1116 test_lmsw(); 1117 test_ljmp(mem); 1118 test_stringio(); 1119 test_incdecnotneg(mem); 1120 test_btc(mem); 1121 test_bsfbsr(mem); 1122 test_imul(mem); 1123 test_muldiv(mem); 1124 test_sse(mem); 1125 test_mmx(mem); 1126 test_rip_relative(mem, insn_ram); 1127 test_shld_shrd(mem); 1128 //test_lgdt_lidt(mem); 1129 test_sreg(mem); 1130 test_lldt(mem); 1131 test_ltr(mem); 1132 test_cmov(mem); 1133 1134 test_mmx_movq_mf(mem, insn_page, alt_insn_page, insn_ram); 1135 test_movabs(mem, insn_page, alt_insn_page, insn_ram); 1136 test_smsw_reg(mem, insn_page, alt_insn_page, insn_ram); 1137 test_nop(mem, insn_page, alt_insn_page, insn_ram); 1138 test_mov_dr(mem, insn_page, alt_insn_page, insn_ram); 1139 test_push16(mem); 1140 test_crosspage_mmio(mem); 1141 1142 test_string_io_mmio(mem); 1143 1144 test_jmp_noncanonical(mem); 1145 test_illegal_movbe(); 1146 1147 return report_summary(); 1148 } 1149