1 #include "ioram.h" 2 #include "vm.h" 3 #include "libcflat.h" 4 #include "desc.h" 5 #include "types.h" 6 #include "processor.h" 7 8 #define memset __builtin_memset 9 #define TESTDEV_IO_PORT 0xe0 10 11 static int exceptions; 12 13 struct regs { 14 u64 rax, rbx, rcx, rdx; 15 u64 rsi, rdi, rsp, rbp; 16 u64 r8, r9, r10, r11; 17 u64 r12, r13, r14, r15; 18 u64 rip, rflags; 19 }; 20 struct regs inregs, outregs, save; 21 22 struct insn_desc { 23 u64 ptr; 24 size_t len; 25 }; 26 27 static char st1[] = "abcdefghijklmnop"; 28 29 void test_stringio() 30 { 31 unsigned char r = 0; 32 asm volatile("cld \n\t" 33 "movw %0, %%dx \n\t" 34 "rep outsb \n\t" 35 : : "i"((short)TESTDEV_IO_PORT), 36 "S"(st1), "c"(sizeof(st1) - 1)); 37 asm volatile("inb %1, %0\n\t" : "=a"(r) : "i"((short)TESTDEV_IO_PORT)); 38 report("outsb up", r == st1[sizeof(st1) - 2]); /* last char */ 39 40 asm volatile("std \n\t" 41 "movw %0, %%dx \n\t" 42 "rep outsb \n\t" 43 : : "i"((short)TESTDEV_IO_PORT), 44 "S"(st1 + sizeof(st1) - 2), "c"(sizeof(st1) - 1)); 45 asm volatile("cld \n\t" : : ); 46 asm volatile("in %1, %0\n\t" : "=a"(r) : "i"((short)TESTDEV_IO_PORT)); 47 report("outsb down", r == st1[0]); 48 } 49 50 void test_cmps_one(unsigned char *m1, unsigned char *m3) 51 { 52 void *rsi, *rdi; 53 long rcx, tmp; 54 55 rsi = m1; rdi = m3; rcx = 30; 56 asm volatile("xor %[tmp], %[tmp] \n\t" 57 "repe/cmpsb" 58 : "+S"(rsi), "+D"(rdi), "+c"(rcx), [tmp]"=&r"(tmp) 59 : : "cc"); 60 report("repe/cmpsb (1)", rcx == 0 && rsi == m1 + 30 && rdi == m3 + 30); 61 62 rsi = m1; rdi = m3; rcx = 30; 63 asm volatile("or $1, %[tmp]\n\t" // clear ZF 64 "repe/cmpsb" 65 : "+S"(rsi), "+D"(rdi), "+c"(rcx), [tmp]"=&r"(tmp) 66 : : "cc"); 67 report("repe/cmpsb (1.zf)", rcx == 0 && rsi == m1 + 30 && rdi == m3 + 30); 68 69 rsi = m1; rdi = m3; rcx = 15; 70 asm volatile("xor %[tmp], %[tmp] \n\t" 71 "repe/cmpsw" 72 : "+S"(rsi), "+D"(rdi), "+c"(rcx), [tmp]"=&r"(tmp) 73 : : "cc"); 74 report("repe/cmpsw (1)", rcx == 0 && rsi == m1 + 30 && rdi == m3 + 30); 75 76 rsi = m1; rdi = m3; rcx = 7; 77 asm volatile("xor %[tmp], %[tmp] \n\t" 78 "repe/cmpsl" 79 : "+S"(rsi), "+D"(rdi), "+c"(rcx), [tmp]"=&r"(tmp) 80 : : "cc"); 81 report("repe/cmpll (1)", rcx == 0 && rsi == m1 + 28 && rdi == m3 + 28); 82 83 rsi = m1; rdi = m3; rcx = 4; 84 asm volatile("xor %[tmp], %[tmp] \n\t" 85 "repe/cmpsq" 86 : "+S"(rsi), "+D"(rdi), "+c"(rcx), [tmp]"=&r"(tmp) 87 : : "cc"); 88 report("repe/cmpsq (1)", rcx == 0 && rsi == m1 + 32 && rdi == m3 + 32); 89 90 rsi = m1; rdi = m3; rcx = 130; 91 asm volatile("xor %[tmp], %[tmp] \n\t" 92 "repe/cmpsb" 93 : "+S"(rsi), "+D"(rdi), "+c"(rcx), [tmp]"=&r"(tmp) 94 : : "cc"); 95 report("repe/cmpsb (2)", 96 rcx == 29 && rsi == m1 + 101 && rdi == m3 + 101); 97 98 rsi = m1; rdi = m3; rcx = 65; 99 asm volatile("xor %[tmp], %[tmp] \n\t" 100 "repe/cmpsw" 101 : "+S"(rsi), "+D"(rdi), "+c"(rcx), [tmp]"=&r"(tmp) 102 : : "cc"); 103 report("repe/cmpsw (2)", 104 rcx == 14 && rsi == m1 + 102 && rdi == m3 + 102); 105 106 rsi = m1; rdi = m3; rcx = 32; 107 asm volatile("xor %[tmp], %[tmp] \n\t" 108 "repe/cmpsl" 109 : "+S"(rsi), "+D"(rdi), "+c"(rcx), [tmp]"=&r"(tmp) 110 : : "cc"); 111 report("repe/cmpll (2)", 112 rcx == 6 && rsi == m1 + 104 && rdi == m3 + 104); 113 114 rsi = m1; rdi = m3; rcx = 16; 115 asm volatile("xor %[tmp], %[tmp] \n\t" 116 "repe/cmpsq" 117 : "+S"(rsi), "+D"(rdi), "+c"(rcx), [tmp]"=&r"(tmp) 118 : : "cc"); 119 report("repe/cmpsq (2)", 120 rcx == 3 && rsi == m1 + 104 && rdi == m3 + 104); 121 122 } 123 124 void test_cmps(void *mem) 125 { 126 unsigned char *m1 = mem, *m2 = mem + 1024; 127 unsigned char m3[1024]; 128 129 for (int i = 0; i < 100; ++i) 130 m1[i] = m2[i] = m3[i] = i; 131 for (int i = 100; i < 200; ++i) 132 m1[i] = (m3[i] = m2[i] = i) + 1; 133 test_cmps_one(m1, m3); 134 test_cmps_one(m1, m2); 135 } 136 137 void test_scas(void *mem) 138 { 139 bool z; 140 void *di; 141 142 *(ulong *)mem = 0x77665544332211; 143 144 di = mem; 145 asm ("scasb; setz %0" : "=rm"(z), "+D"(di) : "a"(0xff11)); 146 report("scasb match", di == mem + 1 && z); 147 148 di = mem; 149 asm ("scasb; setz %0" : "=rm"(z), "+D"(di) : "a"(0xff54)); 150 report("scasb mismatch", di == mem + 1 && !z); 151 152 di = mem; 153 asm ("scasw; setz %0" : "=rm"(z), "+D"(di) : "a"(0xff2211)); 154 report("scasw match", di == mem + 2 && z); 155 156 di = mem; 157 asm ("scasw; setz %0" : "=rm"(z), "+D"(di) : "a"(0xffdd11)); 158 report("scasw mismatch", di == mem + 2 && !z); 159 160 di = mem; 161 asm ("scasl; setz %0" : "=rm"(z), "+D"(di) : "a"(0xff44332211ul)); 162 report("scasd match", di == mem + 4 && z); 163 164 di = mem; 165 asm ("scasl; setz %0" : "=rm"(z), "+D"(di) : "a"(0x45332211)); 166 report("scasd mismatch", di == mem + 4 && !z); 167 168 di = mem; 169 asm ("scasq; setz %0" : "=rm"(z), "+D"(di) : "a"(0x77665544332211ul)); 170 report("scasq match", di == mem + 8 && z); 171 172 di = mem; 173 asm ("scasq; setz %0" : "=rm"(z), "+D"(di) : "a"(3)); 174 report("scasq mismatch", di == mem + 8 && !z); 175 } 176 177 void test_cr8(void) 178 { 179 unsigned long src, dst; 180 181 dst = 777; 182 src = 3; 183 asm volatile("mov %[src], %%cr8; mov %%cr8, %[dst]" 184 : [dst]"+r"(dst), [src]"+r"(src)); 185 report("mov %%cr8", dst == 3 && src == 3); 186 } 187 188 void test_push(void *mem) 189 { 190 unsigned long tmp; 191 unsigned long *stack_top = mem + 4096; 192 unsigned long *new_stack_top; 193 unsigned long memw = 0x123456789abcdeful; 194 195 memset(mem, 0x55, (void *)stack_top - mem); 196 197 asm volatile("mov %%rsp, %[tmp] \n\t" 198 "mov %[stack_top], %%rsp \n\t" 199 "pushq $-7 \n\t" 200 "pushq %[reg] \n\t" 201 "pushq (%[mem]) \n\t" 202 "pushq $-7070707 \n\t" 203 "mov %%rsp, %[new_stack_top] \n\t" 204 "mov %[tmp], %%rsp" 205 : [tmp]"=&r"(tmp), [new_stack_top]"=r"(new_stack_top) 206 : [stack_top]"r"(stack_top), 207 [reg]"r"(-17l), [mem]"r"(&memw) 208 : "memory"); 209 210 report("push $imm8", stack_top[-1] == -7ul); 211 report("push %%reg", stack_top[-2] == -17ul); 212 report("push mem", stack_top[-3] == 0x123456789abcdeful); 213 report("push $imm", stack_top[-4] == -7070707); 214 } 215 216 void test_pop(void *mem) 217 { 218 unsigned long tmp, tmp3, rsp, rbp; 219 unsigned long *stack_top = mem + 4096; 220 unsigned long memw = 0x123456789abcdeful; 221 static unsigned long tmp2; 222 223 memset(mem, 0x55, (void *)stack_top - mem); 224 225 asm volatile("pushq %[val] \n\t" 226 "popq (%[mem])" 227 : : [val]"m"(memw), [mem]"r"(mem) : "memory"); 228 report("pop mem", *(unsigned long *)mem == memw); 229 230 memw = 7 - memw; 231 asm volatile("mov %%rsp, %[tmp] \n\t" 232 "mov %[stack_top], %%rsp \n\t" 233 "pushq %[val] \n\t" 234 "popq %[tmp2] \n\t" 235 "mov %[tmp], %%rsp" 236 : [tmp]"=&r"(tmp), [tmp2]"=m"(tmp2) 237 : [val]"r"(memw), [stack_top]"r"(stack_top) 238 : "memory"); 239 report("pop mem (2)", tmp2 == memw); 240 241 memw = 129443 - memw; 242 asm volatile("mov %%rsp, %[tmp] \n\t" 243 "mov %[stack_top], %%rsp \n\t" 244 "pushq %[val] \n\t" 245 "popq %[tmp2] \n\t" 246 "mov %[tmp], %%rsp" 247 : [tmp]"=&r"(tmp), [tmp2]"=r"(tmp2) 248 : [val]"r"(memw), [stack_top]"r"(stack_top) 249 : "memory"); 250 report("pop reg", tmp2 == memw); 251 252 asm volatile("mov %%rsp, %[tmp] \n\t" 253 "mov %[stack_top], %%rsp \n\t" 254 "push $1f \n\t" 255 "ret \n\t" 256 "2: jmp 2b \n\t" 257 "1: mov %[tmp], %%rsp" 258 : [tmp]"=&r"(tmp) : [stack_top]"r"(stack_top) 259 : "memory"); 260 report("ret", 1); 261 262 stack_top[-1] = 0x778899; 263 asm volatile("mov %[stack_top], %%r8 \n\t" 264 "mov %%rsp, %%r9 \n\t" 265 "xchg %%rbp, %%r8 \n\t" 266 "leave \n\t" 267 "xchg %%rsp, %%r9 \n\t" 268 "xchg %%rbp, %%r8 \n\t" 269 "mov %%r9, %[tmp] \n\t" 270 "mov %%r8, %[tmp3]" 271 : [tmp]"=&r"(tmp), [tmp3]"=&r"(tmp3) : [stack_top]"r"(stack_top-1) 272 : "memory", "r8", "r9"); 273 report("leave", tmp == (ulong)stack_top && tmp3 == 0x778899); 274 275 rbp = 0xaa55aa55bb66bb66ULL; 276 rsp = (unsigned long)stack_top; 277 asm volatile("mov %[rsp], %%r8 \n\t" 278 "mov %[rbp], %%r9 \n\t" 279 "xchg %%rsp, %%r8 \n\t" 280 "xchg %%rbp, %%r9 \n\t" 281 "enter $0x1238, $0 \n\t" 282 "xchg %%rsp, %%r8 \n\t" 283 "xchg %%rbp, %%r9 \n\t" 284 "xchg %%r8, %[rsp] \n\t" 285 "xchg %%r9, %[rbp]" 286 : [rsp]"+a"(rsp), [rbp]"+b"(rbp) : : "memory", "r8", "r9"); 287 report("enter", 288 rsp == (unsigned long)stack_top - 8 - 0x1238 289 && rbp == (unsigned long)stack_top - 8 290 && stack_top[-1] == 0xaa55aa55bb66bb66ULL); 291 } 292 293 void test_ljmp(void *mem) 294 { 295 unsigned char *m = mem; 296 volatile int res = 1; 297 298 *(unsigned long**)m = &&jmpf; 299 asm volatile ("data16/mov %%cs, %0":"=m"(*(m + sizeof(unsigned long)))); 300 asm volatile ("rex64/ljmp *%0"::"m"(*m)); 301 res = 0; 302 jmpf: 303 report("ljmp", res); 304 } 305 306 void test_incdecnotneg(void *mem) 307 { 308 unsigned long *m = mem, v = 1234; 309 unsigned char *mb = mem, vb = 66; 310 311 *m = 0; 312 313 asm volatile ("incl %0":"+m"(*m)); 314 report("incl", *m == 1); 315 asm volatile ("decl %0":"+m"(*m)); 316 report("decl", *m == 0); 317 asm volatile ("incb %0":"+m"(*m)); 318 report("incb", *m == 1); 319 asm volatile ("decb %0":"+m"(*m)); 320 report("decb", *m == 0); 321 322 asm volatile ("lock incl %0":"+m"(*m)); 323 report("lock incl", *m == 1); 324 asm volatile ("lock decl %0":"+m"(*m)); 325 report("lock decl", *m == 0); 326 asm volatile ("lock incb %0":"+m"(*m)); 327 report("lock incb", *m == 1); 328 asm volatile ("lock decb %0":"+m"(*m)); 329 report("lock decb", *m == 0); 330 331 *m = v; 332 333 asm ("lock negq %0" : "+m"(*m)); v = -v; 334 report("lock negl", *m == v); 335 asm ("lock notq %0" : "+m"(*m)); v = ~v; 336 report("lock notl", *m == v); 337 338 *mb = vb; 339 340 asm ("lock negb %0" : "+m"(*mb)); vb = -vb; 341 report("lock negb", *mb == vb); 342 asm ("lock notb %0" : "+m"(*mb)); vb = ~vb; 343 report("lock notb", *mb == vb); 344 } 345 346 void test_smsw(uint64_t *h_mem) 347 { 348 char mem[16]; 349 unsigned short msw, msw_orig, *pmsw; 350 int i, zero; 351 352 msw_orig = read_cr0(); 353 354 asm("smsw %0" : "=r"(msw)); 355 report("smsw (1)", msw == msw_orig); 356 357 memset(mem, 0, 16); 358 pmsw = (void *)mem; 359 asm("smsw %0" : "=m"(pmsw[4])); 360 zero = 1; 361 for (i = 0; i < 8; ++i) 362 if (i != 4 && pmsw[i]) 363 zero = 0; 364 report("smsw (2)", msw == pmsw[4] && zero); 365 366 /* Trigger exit on smsw */ 367 *h_mem = 0x12345678abcdeful; 368 asm volatile("smsw %0" : "+m"(*h_mem)); 369 report("smsw (3)", msw == (unsigned short)*h_mem && 370 (*h_mem & ~0xfffful) == 0x12345678ab0000ul); 371 } 372 373 void test_lmsw(void) 374 { 375 char mem[16]; 376 unsigned short msw, *pmsw; 377 unsigned long cr0; 378 379 cr0 = read_cr0(); 380 381 msw = cr0 ^ 8; 382 asm("lmsw %0" : : "r"(msw)); 383 printf("before %lx after %lx\n", cr0, read_cr0()); 384 report("lmsw (1)", (cr0 ^ read_cr0()) == 8); 385 386 pmsw = (void *)mem; 387 *pmsw = cr0; 388 asm("lmsw %0" : : "m"(*pmsw)); 389 printf("before %lx after %lx\n", cr0, read_cr0()); 390 report("lmsw (2)", cr0 == read_cr0()); 391 392 /* lmsw can't clear cr0.pe */ 393 msw = (cr0 & ~1ul) ^ 4; /* change EM to force trap */ 394 asm("lmsw %0" : : "r"(msw)); 395 report("lmsw (3)", (cr0 ^ read_cr0()) == 4 && (cr0 & 1)); 396 397 /* back to normal */ 398 msw = cr0; 399 asm("lmsw %0" : : "r"(msw)); 400 } 401 402 void test_xchg(void *mem) 403 { 404 unsigned long *memq = mem; 405 unsigned long rax; 406 407 asm volatile("mov $0x123456789abcdef, %%rax\n\t" 408 "mov %%rax, (%[memq])\n\t" 409 "mov $0xfedcba9876543210, %%rax\n\t" 410 "xchg %%al, (%[memq])\n\t" 411 "mov %%rax, %[rax]\n\t" 412 : [rax]"=r"(rax) 413 : [memq]"r"(memq) 414 : "memory", "rax"); 415 report("xchg reg, r/m (1)", 416 rax == 0xfedcba98765432ef && *memq == 0x123456789abcd10); 417 418 asm volatile("mov $0x123456789abcdef, %%rax\n\t" 419 "mov %%rax, (%[memq])\n\t" 420 "mov $0xfedcba9876543210, %%rax\n\t" 421 "xchg %%ax, (%[memq])\n\t" 422 "mov %%rax, %[rax]\n\t" 423 : [rax]"=r"(rax) 424 : [memq]"r"(memq) 425 : "memory", "rax"); 426 report("xchg reg, r/m (2)", 427 rax == 0xfedcba987654cdef && *memq == 0x123456789ab3210); 428 429 asm volatile("mov $0x123456789abcdef, %%rax\n\t" 430 "mov %%rax, (%[memq])\n\t" 431 "mov $0xfedcba9876543210, %%rax\n\t" 432 "xchg %%eax, (%[memq])\n\t" 433 "mov %%rax, %[rax]\n\t" 434 : [rax]"=r"(rax) 435 : [memq]"r"(memq) 436 : "memory", "rax"); 437 report("xchg reg, r/m (3)", 438 rax == 0x89abcdef && *memq == 0x123456776543210); 439 440 asm volatile("mov $0x123456789abcdef, %%rax\n\t" 441 "mov %%rax, (%[memq])\n\t" 442 "mov $0xfedcba9876543210, %%rax\n\t" 443 "xchg %%rax, (%[memq])\n\t" 444 "mov %%rax, %[rax]\n\t" 445 : [rax]"=r"(rax) 446 : [memq]"r"(memq) 447 : "memory", "rax"); 448 report("xchg reg, r/m (4)", 449 rax == 0x123456789abcdef && *memq == 0xfedcba9876543210); 450 } 451 452 void test_xadd(void *mem) 453 { 454 unsigned long *memq = mem; 455 unsigned long rax; 456 457 asm volatile("mov $0x123456789abcdef, %%rax\n\t" 458 "mov %%rax, (%[memq])\n\t" 459 "mov $0xfedcba9876543210, %%rax\n\t" 460 "xadd %%al, (%[memq])\n\t" 461 "mov %%rax, %[rax]\n\t" 462 : [rax]"=r"(rax) 463 : [memq]"r"(memq) 464 : "memory", "rax"); 465 report("xadd reg, r/m (1)", 466 rax == 0xfedcba98765432ef && *memq == 0x123456789abcdff); 467 468 asm volatile("mov $0x123456789abcdef, %%rax\n\t" 469 "mov %%rax, (%[memq])\n\t" 470 "mov $0xfedcba9876543210, %%rax\n\t" 471 "xadd %%ax, (%[memq])\n\t" 472 "mov %%rax, %[rax]\n\t" 473 : [rax]"=r"(rax) 474 : [memq]"r"(memq) 475 : "memory", "rax"); 476 report("xadd reg, r/m (2)", 477 rax == 0xfedcba987654cdef && *memq == 0x123456789abffff); 478 479 asm volatile("mov $0x123456789abcdef, %%rax\n\t" 480 "mov %%rax, (%[memq])\n\t" 481 "mov $0xfedcba9876543210, %%rax\n\t" 482 "xadd %%eax, (%[memq])\n\t" 483 "mov %%rax, %[rax]\n\t" 484 : [rax]"=r"(rax) 485 : [memq]"r"(memq) 486 : "memory", "rax"); 487 report("xadd reg, r/m (3)", 488 rax == 0x89abcdef && *memq == 0x1234567ffffffff); 489 490 asm volatile("mov $0x123456789abcdef, %%rax\n\t" 491 "mov %%rax, (%[memq])\n\t" 492 "mov $0xfedcba9876543210, %%rax\n\t" 493 "xadd %%rax, (%[memq])\n\t" 494 "mov %%rax, %[rax]\n\t" 495 : [rax]"=r"(rax) 496 : [memq]"r"(memq) 497 : "memory", "rax"); 498 report("xadd reg, r/m (4)", 499 rax == 0x123456789abcdef && *memq == 0xffffffffffffffff); 500 } 501 502 void test_btc(void *mem) 503 { 504 unsigned int *a = mem; 505 506 memset(mem, 0, 4 * sizeof(unsigned int)); 507 508 asm ("btcl $32, %0" :: "m"(a[0]) : "memory"); 509 asm ("btcl $1, %0" :: "m"(a[1]) : "memory"); 510 asm ("btcl %1, %0" :: "m"(a[0]), "r"(66) : "memory"); 511 report("btcl imm8, r/m", a[0] == 1 && a[1] == 2 && a[2] == 4); 512 513 asm ("btcl %1, %0" :: "m"(a[3]), "r"(-1) : "memory"); 514 report("btcl reg, r/m", a[0] == 1 && a[1] == 2 && a[2] == 0x80000004); 515 516 asm ("btcq %1, %0" : : "m"(a[2]), "r"(-1l) : "memory"); 517 report("btcq reg, r/m", a[0] == 1 && a[1] == 0x80000002 && 518 a[2] == 0x80000004 && a[3] == 0); 519 } 520 521 void test_bsfbsr(void *mem) 522 { 523 unsigned long rax, *memq = mem; 524 unsigned eax, *meml = mem; 525 unsigned short ax, *memw = mem; 526 unsigned char z; 527 528 *memw = 0xc000; 529 asm("bsfw %[mem], %[a]" : [a]"=a"(ax) : [mem]"m"(*memw)); 530 report("bsfw r/m, reg", ax == 14); 531 532 *meml = 0xc0000000; 533 asm("bsfl %[mem], %[a]" : [a]"=a"(eax) : [mem]"m"(*meml)); 534 report("bsfl r/m, reg", eax == 30); 535 536 *memq = 0xc00000000000; 537 asm("bsfq %[mem], %[a]" : [a]"=a"(rax) : [mem]"m"(*memq)); 538 report("bsfq r/m, reg", rax == 46); 539 540 *memq = 0; 541 asm("bsfq %[mem], %[a]; setz %[z]" 542 : [a]"=a"(rax), [z]"=rm"(z) : [mem]"m"(*memq)); 543 report("bsfq r/m, reg", z == 1); 544 545 *memw = 0xc000; 546 asm("bsrw %[mem], %[a]" : [a]"=a"(ax) : [mem]"m"(*memw)); 547 report("bsrw r/m, reg", ax == 15); 548 549 *meml = 0xc0000000; 550 asm("bsrl %[mem], %[a]" : [a]"=a"(eax) : [mem]"m"(*meml)); 551 report("bsrl r/m, reg", eax == 31); 552 553 *memq = 0xc00000000000; 554 asm("bsrq %[mem], %[a]" : [a]"=a"(rax) : [mem]"m"(*memq)); 555 report("bsrq r/m, reg", rax == 47); 556 557 *memq = 0; 558 asm("bsrq %[mem], %[a]; setz %[z]" 559 : [a]"=a"(rax), [z]"=rm"(z) : [mem]"m"(*memq)); 560 report("bsrq r/m, reg", z == 1); 561 } 562 563 static void test_imul(ulong *mem) 564 { 565 ulong a; 566 567 *mem = 51; a = 0x1234567812345678UL; 568 asm ("imulw %1, %%ax" : "+a"(a) : "m"(*mem)); 569 report("imul ax, mem", a == 0x12345678123439e8); 570 571 *mem = 51; a = 0x1234567812345678UL; 572 asm ("imull %1, %%eax" : "+a"(a) : "m"(*mem)); 573 report("imul eax, mem", a == 0xa06d39e8); 574 575 *mem = 51; a = 0x1234567812345678UL; 576 asm ("imulq %1, %%rax" : "+a"(a) : "m"(*mem)); 577 report("imul rax, mem", a == 0xA06D39EBA06D39E8UL); 578 579 *mem = 0x1234567812345678UL; a = 0x8765432187654321L; 580 asm ("imulw $51, %1, %%ax" : "+a"(a) : "m"(*mem)); 581 report("imul ax, mem, imm8", a == 0x87654321876539e8); 582 583 *mem = 0x1234567812345678UL; 584 asm ("imull $51, %1, %%eax" : "+a"(a) : "m"(*mem)); 585 report("imul eax, mem, imm8", a == 0xa06d39e8); 586 587 *mem = 0x1234567812345678UL; 588 asm ("imulq $51, %1, %%rax" : "+a"(a) : "m"(*mem)); 589 report("imul rax, mem, imm8", a == 0xA06D39EBA06D39E8UL); 590 591 *mem = 0x1234567812345678UL; a = 0x8765432187654321L; 592 asm ("imulw $311, %1, %%ax" : "+a"(a) : "m"(*mem)); 593 report("imul ax, mem, imm", a == 0x8765432187650bc8); 594 595 *mem = 0x1234567812345678UL; 596 asm ("imull $311, %1, %%eax" : "+a"(a) : "m"(*mem)); 597 report("imul eax, mem, imm", a == 0x1d950bc8); 598 599 *mem = 0x1234567812345678UL; 600 asm ("imulq $311, %1, %%rax" : "+a"(a) : "m"(*mem)); 601 report("imul rax, mem, imm", a == 0x1D950BDE1D950BC8L); 602 } 603 604 static void test_muldiv(long *mem) 605 { 606 long a, d, aa, dd; 607 u8 ex = 1; 608 609 *mem = 0; a = 1; d = 2; 610 asm (ASM_TRY("1f") "divq %3; movb $0, %2; 1:" 611 : "+a"(a), "+d"(d), "+q"(ex) : "m"(*mem)); 612 report("divq (fault)", a == 1 && d == 2 && ex); 613 614 *mem = 987654321098765UL; a = 123456789012345UL; d = 123456789012345UL; 615 asm (ASM_TRY("1f") "divq %3; movb $0, %2; 1:" 616 : "+a"(a), "+d"(d), "+q"(ex) : "m"(*mem)); 617 report("divq (1)", 618 a == 0x1ffffffb1b963b33ul && d == 0x273ba4384ede2ul && !ex); 619 aa = 0x1111111111111111; dd = 0x2222222222222222; 620 *mem = 0x3333333333333333; a = aa; d = dd; 621 asm("mulb %2" : "+a"(a), "+d"(d) : "m"(*mem)); 622 report("mulb mem", a == 0x1111111111110363 && d == dd); 623 *mem = 0x3333333333333333; a = aa; d = dd; 624 asm("mulw %2" : "+a"(a), "+d"(d) : "m"(*mem)); 625 report("mulw mem", a == 0x111111111111c963 && d == 0x2222222222220369); 626 *mem = 0x3333333333333333; a = aa; d = dd; 627 asm("mull %2" : "+a"(a), "+d"(d) : "m"(*mem)); 628 report("mull mem", a == 0x962fc963 && d == 0x369d036); 629 *mem = 0x3333333333333333; a = aa; d = dd; 630 asm("mulq %2" : "+a"(a), "+d"(d) : "m"(*mem)); 631 report("mulq mem", a == 0x2fc962fc962fc963 && d == 0x369d0369d0369d0); 632 } 633 634 typedef unsigned __attribute__((vector_size(16))) sse128; 635 636 typedef union { 637 sse128 sse; 638 unsigned u[4]; 639 } sse_union; 640 641 static bool sseeq(sse_union *v1, sse_union *v2) 642 { 643 bool ok = true; 644 int i; 645 646 for (i = 0; i < 4; ++i) { 647 ok &= v1->u[i] == v2->u[i]; 648 } 649 650 return ok; 651 } 652 653 static void test_sse(sse_union *mem) 654 { 655 sse_union v; 656 657 write_cr0(read_cr0() & ~6); /* EM, TS */ 658 write_cr4(read_cr4() | 0x200); /* OSFXSR */ 659 v.u[0] = 1; v.u[1] = 2; v.u[2] = 3; v.u[3] = 4; 660 asm("movdqu %1, %0" : "=m"(*mem) : "x"(v.sse)); 661 report("movdqu (read)", sseeq(&v, mem)); 662 mem->u[0] = 5; mem->u[1] = 6; mem->u[2] = 7; mem->u[3] = 8; 663 asm("movdqu %1, %0" : "=x"(v.sse) : "m"(*mem)); 664 report("movdqu (write)", sseeq(mem, &v)); 665 666 v.u[0] = 1; v.u[1] = 2; v.u[2] = 3; v.u[3] = 4; 667 asm("movaps %1, %0" : "=m"(*mem) : "x"(v.sse)); 668 report("movaps (read)", sseeq(mem, &v)); 669 mem->u[0] = 5; mem->u[1] = 6; mem->u[2] = 7; mem->u[3] = 8; 670 asm("movaps %1, %0" : "=x"(v.sse) : "m"(*mem)); 671 report("movaps (write)", sseeq(&v, mem)); 672 673 v.u[0] = 1; v.u[1] = 2; v.u[2] = 3; v.u[3] = 4; 674 asm("movapd %1, %0" : "=m"(*mem) : "x"(v.sse)); 675 report("movapd (read)", sseeq(mem, &v)); 676 mem->u[0] = 5; mem->u[1] = 6; mem->u[2] = 7; mem->u[3] = 8; 677 asm("movapd %1, %0" : "=x"(v.sse) : "m"(*mem)); 678 report("movapd (write)", sseeq(&v, mem)); 679 } 680 681 static void test_mmx(uint64_t *mem) 682 { 683 uint64_t v; 684 685 write_cr0(read_cr0() & ~6); /* EM, TS */ 686 asm volatile("fninit"); 687 v = 0x0102030405060708ULL; 688 asm("movq %1, %0" : "=m"(*mem) : "y"(v)); 689 report("movq (mmx, read)", v == *mem); 690 *mem = 0x8070605040302010ull; 691 asm("movq %1, %0" : "=y"(v) : "m"(*mem)); 692 report("movq (mmx, write)", v == *mem); 693 } 694 695 static void test_rip_relative(unsigned *mem, char *insn_ram) 696 { 697 /* movb $1, mem+2(%rip) */ 698 insn_ram[0] = 0xc6; 699 insn_ram[1] = 0x05; 700 *(unsigned *)&insn_ram[2] = 2 + (char *)mem - (insn_ram + 7); 701 insn_ram[6] = 0x01; 702 /* ret */ 703 insn_ram[7] = 0xc3; 704 705 *mem = 0; 706 asm("callq *%1" : "+m"(*mem) : "r"(insn_ram)); 707 report("movb $imm, 0(%%rip)", *mem == 0x10000); 708 } 709 710 static void test_shld_shrd(u32 *mem) 711 { 712 *mem = 0x12345678; 713 asm("shld %2, %1, %0" : "+m"(*mem) : "r"(0xaaaaaaaaU), "c"((u8)3)); 714 report("shld (cl)", *mem == ((0x12345678 << 3) | 5)); 715 *mem = 0x12345678; 716 asm("shrd %2, %1, %0" : "+m"(*mem) : "r"(0x55555555U), "c"((u8)3)); 717 report("shrd (cl)", *mem == ((0x12345678 >> 3) | (5u << 29))); 718 } 719 720 static void test_cmov(u32 *mem) 721 { 722 u64 val; 723 *mem = 0xabcdef12u; 724 asm ("movq $0x1234567812345678, %%rax\n\t" 725 "cmpl %%eax, %%eax\n\t" 726 "cmovnel (%[mem]), %%eax\n\t" 727 "movq %%rax, %[val]\n\t" 728 : [val]"=r"(val) : [mem]"r"(mem) : "%rax", "cc"); 729 report("cmovnel", val == 0x12345678ul); 730 } 731 732 #define INSN_XCHG_ALL \ 733 "xchg %rax, 0+save \n\t" \ 734 "xchg %rbx, 8+save \n\t" \ 735 "xchg %rcx, 16+save \n\t" \ 736 "xchg %rdx, 24+save \n\t" \ 737 "xchg %rsi, 32+save \n\t" \ 738 "xchg %rdi, 40+save \n\t" \ 739 "xchg %rsp, 48+save \n\t" \ 740 "xchg %rbp, 56+save \n\t" \ 741 "xchg %r8, 64+save \n\t" \ 742 "xchg %r9, 72+save \n\t" \ 743 "xchg %r10, 80+save \n\t" \ 744 "xchg %r11, 88+save \n\t" \ 745 "xchg %r12, 96+save \n\t" \ 746 "xchg %r13, 104+save \n\t" \ 747 "xchg %r14, 112+save \n\t" \ 748 "xchg %r15, 120+save \n\t" 749 750 asm( 751 ".align 4096\n\t" 752 "insn_page:\n\t" 753 "ret\n\t" 754 "pushf\n\t" 755 "push 136+save \n\t" 756 "popf \n\t" 757 INSN_XCHG_ALL 758 "test_insn:\n\t" 759 "in (%dx),%al\n\t" 760 ".skip 31, 0x90\n\t" 761 "test_insn_end:\n\t" 762 INSN_XCHG_ALL 763 "pushf \n\t" 764 "pop 136+save \n\t" 765 "popf \n\t" 766 "ret \n\t" 767 "insn_page_end:\n\t" 768 ".align 4096\n\t" 769 ); 770 771 #define MK_INSN(name, str) \ 772 asm ( \ 773 ".pushsection .data.insn \n\t" \ 774 "insn_" #name ": \n\t" \ 775 ".quad 1001f, 1002f - 1001f \n\t" \ 776 ".popsection \n\t" \ 777 ".pushsection .text.insn, \"ax\" \n\t" \ 778 "1001: \n\t" \ 779 "insn_code_" #name ": " str " \n\t" \ 780 "1002: \n\t" \ 781 ".popsection" \ 782 ); \ 783 extern struct insn_desc insn_##name; 784 785 static void trap_emulator(uint64_t *mem, void *alt_insn_page, 786 struct insn_desc *alt_insn) 787 { 788 ulong *cr3 = (ulong *)read_cr3(); 789 void *insn_ram; 790 extern u8 insn_page[], test_insn[]; 791 792 insn_ram = vmap(virt_to_phys(insn_page), 4096); 793 memcpy(alt_insn_page, insn_page, 4096); 794 memcpy(alt_insn_page + (test_insn - insn_page), 795 (void *)(alt_insn->ptr), alt_insn->len); 796 save = inregs; 797 798 /* Load the code TLB with insn_page, but point the page tables at 799 alt_insn_page (and keep the data TLB clear, for AMD decode assist). 800 This will make the CPU trap on the insn_page instruction but the 801 hypervisor will see alt_insn_page. */ 802 install_page(cr3, virt_to_phys(insn_page), insn_ram); 803 invlpg(insn_ram); 804 /* Load code TLB */ 805 asm volatile("call *%0" : : "r"(insn_ram)); 806 install_page(cr3, virt_to_phys(alt_insn_page), insn_ram); 807 /* Trap, let hypervisor emulate at alt_insn_page */ 808 asm volatile("call *%0": : "r"(insn_ram+1)); 809 810 outregs = save; 811 } 812 813 static unsigned long rip_advance; 814 815 static void advance_rip_and_note_exception(struct ex_regs *regs) 816 { 817 ++exceptions; 818 regs->rip += rip_advance; 819 } 820 821 static void test_mmx_movq_mf(uint64_t *mem, uint8_t *insn_page, 822 uint8_t *alt_insn_page, void *insn_ram) 823 { 824 uint16_t fcw = 0; /* all exceptions unmasked */ 825 /* movq %mm0, (%rax) */ 826 void *stack = alloc_page(); 827 828 write_cr0(read_cr0() & ~6); /* TS, EM */ 829 exceptions = 0; 830 handle_exception(MF_VECTOR, advance_rip_and_note_exception); 831 asm volatile("fninit; fldcw %0" : : "m"(fcw)); 832 asm volatile("fldz; fldz; fdivp"); /* generate exception */ 833 834 MK_INSN(mmx_movq_mf, "movq %mm0, (%rax) \n\t"); 835 rip_advance = insn_mmx_movq_mf.len; 836 inregs = (struct regs){ .rsp=(u64)stack+1024 }; 837 trap_emulator(mem, alt_insn_page, &insn_mmx_movq_mf); 838 /* exit MMX mode */ 839 asm volatile("fnclex; emms"); 840 report("movq mmx generates #MF", exceptions == 1); 841 handle_exception(MF_VECTOR, 0); 842 } 843 844 static void test_jmp_noncanonical(uint64_t *mem) 845 { 846 extern char nc_jmp_start, nc_jmp_end; 847 848 *mem = 0x1111111111111111ul; 849 850 exceptions = 0; 851 rip_advance = &nc_jmp_end - &nc_jmp_start; 852 handle_exception(GP_VECTOR, advance_rip_and_note_exception); 853 asm volatile ("nc_jmp_start: jmp *%0; nc_jmp_end:" : : "m"(*mem)); 854 report("jump to non-canonical address", exceptions == 1); 855 handle_exception(GP_VECTOR, 0); 856 } 857 858 static void test_movabs(uint64_t *mem, uint8_t *insn_page, 859 uint8_t *alt_insn_page, void *insn_ram) 860 { 861 /* mov $0x9090909090909090, %rcx */ 862 MK_INSN(movabs, "mov $0x9090909090909090, %rcx\n\t"); 863 inregs = (struct regs){ 0 }; 864 trap_emulator(mem, alt_insn_page, &insn_movabs); 865 report("64-bit mov imm2", outregs.rcx == 0x9090909090909090); 866 } 867 868 static void test_smsw_reg(uint64_t *mem, uint8_t *insn_page, 869 uint8_t *alt_insn_page, void *insn_ram) 870 { 871 unsigned long cr0 = read_cr0(); 872 inregs = (struct regs){ .rax = 0x1234567890abcdeful }; 873 874 MK_INSN(smsww, "smsww %ax\n\t"); 875 trap_emulator(mem, alt_insn_page, &insn_smsww); 876 report("16-bit smsw reg", (u16)outregs.rax == (u16)cr0 && 877 outregs.rax >> 16 == inregs.rax >> 16); 878 879 MK_INSN(smswl, "smswl %eax\n\t"); 880 trap_emulator(mem, alt_insn_page, &insn_smswl); 881 report("32-bit smsw reg", outregs.rax == (u32)cr0); 882 883 MK_INSN(smswq, "smswq %rax\n\t"); 884 trap_emulator(mem, alt_insn_page, &insn_smswq); 885 report("64-bit smsw reg", outregs.rax == cr0); 886 } 887 888 static void test_nop(uint64_t *mem, uint8_t *insn_page, 889 uint8_t *alt_insn_page, void *insn_ram) 890 { 891 inregs = (struct regs){ .rax = 0x1234567890abcdeful }; 892 MK_INSN(nop, "nop\n\t"); 893 trap_emulator(mem, alt_insn_page, &insn_nop); 894 report("nop", outregs.rax == inregs.rax); 895 } 896 897 static void test_mov_dr(uint64_t *mem, uint8_t *insn_page, 898 uint8_t *alt_insn_page, void *insn_ram) 899 { 900 bool rtm_support = cpuid(7).b & (1 << 11); 901 unsigned long dr6_fixed_1 = rtm_support ? 0xfffe0ff0ul : 0xffff0ff0ul; 902 inregs = (struct regs){ .rax = 0 }; 903 MK_INSN(mov_to_dr6, "movq %rax, %dr6\n\t"); 904 trap_emulator(mem, alt_insn_page, &insn_mov_to_dr6); 905 MK_INSN(mov_from_dr6, "movq %dr6, %rax\n\t"); 906 trap_emulator(mem, alt_insn_page, &insn_mov_from_dr6); 907 report("mov_dr6", outregs.rax == dr6_fixed_1); 908 } 909 910 static void test_push16(uint64_t *mem) 911 { 912 uint64_t rsp1, rsp2; 913 uint16_t r; 914 915 asm volatile ( "movq %%rsp, %[rsp1]\n\t" 916 "pushw %[v]\n\t" 917 "popw %[r]\n\t" 918 "movq %%rsp, %[rsp2]\n\t" 919 "movq %[rsp1], %%rsp\n\t" : 920 [rsp1]"=r"(rsp1), [rsp2]"=r"(rsp2), [r]"=r"(r) 921 : [v]"m"(*mem) : "memory"); 922 report("push16", rsp1 == rsp2); 923 } 924 925 static void test_crosspage_mmio(volatile uint8_t *mem) 926 { 927 volatile uint16_t w, *pw; 928 929 pw = (volatile uint16_t *)&mem[4095]; 930 mem[4095] = 0x99; 931 mem[4096] = 0x77; 932 asm volatile("mov %1, %0" : "=r"(w) : "m"(*pw) : "memory"); 933 report("cross-page mmio read", w == 0x7799); 934 asm volatile("mov %1, %0" : "=m"(*pw) : "r"((uint16_t)0x88aa)); 935 report("cross-page mmio write", mem[4095] == 0xaa && mem[4096] == 0x88); 936 } 937 938 static void test_string_io_mmio(volatile uint8_t *mem) 939 { 940 /* Cross MMIO pages.*/ 941 volatile uint8_t *mmio = mem + 4032; 942 943 asm volatile("outw %%ax, %%dx \n\t" : : "a"(0x9999), "d"(TESTDEV_IO_PORT)); 944 945 asm volatile ("cld; rep insb" : : "d" (TESTDEV_IO_PORT), "D" (mmio), "c" (1024)); 946 947 report("string_io_mmio", mmio[1023] == 0x99); 948 } 949 950 /* kvm doesn't allow lidt/lgdt from mmio, so the test is disabled */ 951 #if 0 952 static void test_lgdt_lidt(volatile uint8_t *mem) 953 { 954 struct descriptor_table_ptr orig, fresh = {}; 955 956 sgdt(&orig); 957 *(struct descriptor_table_ptr *)mem = (struct descriptor_table_ptr) { 958 .limit = 0xf234, 959 .base = 0x12345678abcd, 960 }; 961 cli(); 962 asm volatile("lgdt %0" : : "m"(*(struct descriptor_table_ptr *)mem)); 963 sgdt(&fresh); 964 lgdt(&orig); 965 sti(); 966 report("lgdt (long address)", orig.limit == fresh.limit && orig.base == fresh.base); 967 968 sidt(&orig); 969 *(struct descriptor_table_ptr *)mem = (struct descriptor_table_ptr) { 970 .limit = 0x432f, 971 .base = 0xdbca87654321, 972 }; 973 cli(); 974 asm volatile("lidt %0" : : "m"(*(struct descriptor_table_ptr *)mem)); 975 sidt(&fresh); 976 lidt(&orig); 977 sti(); 978 report("lidt (long address)", orig.limit == fresh.limit && orig.base == fresh.base); 979 } 980 #endif 981 982 static void ss_bad_rpl(struct ex_regs *regs) 983 { 984 extern char ss_bad_rpl_cont; 985 986 ++exceptions; 987 regs->rip = (ulong)&ss_bad_rpl_cont; 988 } 989 990 static void test_sreg(volatile uint16_t *mem) 991 { 992 u16 ss = read_ss(); 993 994 // check for null segment load 995 *mem = 0; 996 asm volatile("mov %0, %%ss" : : "m"(*mem)); 997 report("mov null, %%ss", read_ss() == 0); 998 999 // check for exception when ss.rpl != cpl on null segment load 1000 exceptions = 0; 1001 handle_exception(GP_VECTOR, ss_bad_rpl); 1002 *mem = 3; 1003 asm volatile("mov %0, %%ss; ss_bad_rpl_cont:" : : "m"(*mem)); 1004 report("mov null, %%ss (with ss.rpl != cpl)", exceptions == 1 && read_ss() == 0); 1005 handle_exception(GP_VECTOR, 0); 1006 write_ss(ss); 1007 } 1008 1009 /* Broken emulation causes triple fault, which skips the other tests. */ 1010 #if 0 1011 static void test_lldt(volatile uint16_t *mem) 1012 { 1013 u64 gdt[] = { 0, /* null descriptor */ 1014 #ifdef __X86_64__ 1015 0, /* ldt descriptor is 16 bytes in long mode */ 1016 #endif 1017 0x0000f82000000ffffull /* ldt descriptor */ }; 1018 struct descriptor_table_ptr gdt_ptr = { .limit = sizeof(gdt) - 1, 1019 .base = (ulong)&gdt }; 1020 struct descriptor_table_ptr orig_gdt; 1021 1022 cli(); 1023 sgdt(&orig_gdt); 1024 lgdt(&gdt_ptr); 1025 *mem = 0x8; 1026 asm volatile("lldt %0" : : "m"(*mem)); 1027 lgdt(&orig_gdt); 1028 sti(); 1029 report("lldt", sldt() == *mem); 1030 } 1031 #endif 1032 1033 static void test_ltr(volatile uint16_t *mem) 1034 { 1035 struct descriptor_table_ptr gdt_ptr; 1036 uint64_t *gdt, *trp; 1037 uint16_t tr = str(); 1038 uint64_t busy_mask = (uint64_t)1 << 41; 1039 1040 sgdt(&gdt_ptr); 1041 gdt = (uint64_t *)gdt_ptr.base; 1042 trp = &gdt[tr >> 3]; 1043 *trp &= ~busy_mask; 1044 *mem = tr; 1045 asm volatile("ltr %0" : : "m"(*mem) : "memory"); 1046 report("ltr", str() == tr && (*trp & busy_mask)); 1047 } 1048 1049 static void test_simplealu(u32 *mem) 1050 { 1051 *mem = 0x1234; 1052 asm("or %1, %0" : "+m"(*mem) : "r"(0x8001)); 1053 report("or", *mem == 0x9235); 1054 asm("add %1, %0" : "+m"(*mem) : "r"(2)); 1055 report("add", *mem == 0x9237); 1056 asm("xor %1, %0" : "+m"(*mem) : "r"(0x1111)); 1057 report("xor", *mem == 0x8326); 1058 asm("sub %1, %0" : "+m"(*mem) : "r"(0x26)); 1059 report("sub", *mem == 0x8300); 1060 asm("clc; adc %1, %0" : "+m"(*mem) : "r"(0x100)); 1061 report("adc(0)", *mem == 0x8400); 1062 asm("stc; adc %1, %0" : "+m"(*mem) : "r"(0x100)); 1063 report("adc(0)", *mem == 0x8501); 1064 asm("clc; sbb %1, %0" : "+m"(*mem) : "r"(0)); 1065 report("sbb(0)", *mem == 0x8501); 1066 asm("stc; sbb %1, %0" : "+m"(*mem) : "r"(0)); 1067 report("sbb(1)", *mem == 0x8500); 1068 asm("and %1, %0" : "+m"(*mem) : "r"(0xfe77)); 1069 report("and", *mem == 0x8400); 1070 asm("test %1, %0" : "+m"(*mem) : "r"(0xf000)); 1071 report("test", *mem == 0x8400); 1072 } 1073 1074 static void illegal_movbe_handler(struct ex_regs *regs) 1075 { 1076 extern char bad_movbe_cont; 1077 1078 ++exceptions; 1079 regs->rip = (ulong)&bad_movbe_cont; 1080 } 1081 1082 static void test_illegal_movbe(void) 1083 { 1084 if (!(cpuid(1).c & (1 << 22))) { 1085 report_skip("illegal movbe"); 1086 return; 1087 } 1088 1089 exceptions = 0; 1090 handle_exception(UD_VECTOR, illegal_movbe_handler); 1091 asm volatile(".byte 0x0f; .byte 0x38; .byte 0xf0; .byte 0xc0;\n\t" 1092 " bad_movbe_cont:" : : : "rax"); 1093 report("illegal movbe", exceptions == 1); 1094 handle_exception(UD_VECTOR, 0); 1095 } 1096 1097 int main() 1098 { 1099 void *mem; 1100 void *insn_page, *alt_insn_page; 1101 void *insn_ram; 1102 unsigned long t1, t2; 1103 1104 setup_vm(); 1105 setup_idt(); 1106 mem = alloc_vpages(2); 1107 install_page((void *)read_cr3(), IORAM_BASE_PHYS, mem); 1108 // install the page twice to test cross-page mmio 1109 install_page((void *)read_cr3(), IORAM_BASE_PHYS, mem + 4096); 1110 insn_page = alloc_page(); 1111 alt_insn_page = alloc_page(); 1112 insn_ram = vmap(virt_to_phys(insn_page), 4096); 1113 1114 // test mov reg, r/m and mov r/m, reg 1115 t1 = 0x123456789abcdef; 1116 asm volatile("mov %[t1], (%[mem]) \n\t" 1117 "mov (%[mem]), %[t2]" 1118 : [t2]"=r"(t2) 1119 : [t1]"r"(t1), [mem]"r"(mem) 1120 : "memory"); 1121 report("mov reg, r/m (1)", t2 == 0x123456789abcdef); 1122 1123 test_simplealu(mem); 1124 test_cmps(mem); 1125 test_scas(mem); 1126 1127 test_push(mem); 1128 test_pop(mem); 1129 1130 test_xchg(mem); 1131 test_xadd(mem); 1132 1133 test_cr8(); 1134 1135 test_smsw(mem); 1136 test_lmsw(); 1137 test_ljmp(mem); 1138 test_stringio(); 1139 test_incdecnotneg(mem); 1140 test_btc(mem); 1141 test_bsfbsr(mem); 1142 test_imul(mem); 1143 test_muldiv(mem); 1144 test_sse(mem); 1145 test_mmx(mem); 1146 test_rip_relative(mem, insn_ram); 1147 test_shld_shrd(mem); 1148 //test_lgdt_lidt(mem); 1149 test_sreg(mem); 1150 //test_lldt(mem); 1151 test_ltr(mem); 1152 test_cmov(mem); 1153 1154 test_mmx_movq_mf(mem, insn_page, alt_insn_page, insn_ram); 1155 test_movabs(mem, insn_page, alt_insn_page, insn_ram); 1156 test_smsw_reg(mem, insn_page, alt_insn_page, insn_ram); 1157 test_nop(mem, insn_page, alt_insn_page, insn_ram); 1158 test_mov_dr(mem, insn_page, alt_insn_page, insn_ram); 1159 test_push16(mem); 1160 test_crosspage_mmio(mem); 1161 1162 test_string_io_mmio(mem); 1163 1164 test_jmp_noncanonical(mem); 1165 test_illegal_movbe(); 1166 1167 return report_summary(); 1168 } 1169