1 #include <asm/debugreg.h> 2 3 #include "ioram.h" 4 #include "vm.h" 5 #include "libcflat.h" 6 #include "desc.h" 7 #include "types.h" 8 #include "processor.h" 9 #include "vmalloc.h" 10 #include "alloc_page.h" 11 #include "usermode.h" 12 13 #define TESTDEV_IO_PORT 0xe0 14 15 #define MAGIC_NUM 0xdeadbeefdeadbeefUL 16 #define GS_BASE 0x400000 17 18 static int exceptions; 19 20 struct regs { 21 u64 rax, rbx, rcx, rdx; 22 u64 rsi, rdi, rsp, rbp; 23 u64 r8, r9, r10, r11; 24 u64 r12, r13, r14, r15; 25 u64 rip, rflags; 26 }; 27 struct regs inregs, outregs, save; 28 29 struct insn_desc { 30 u64 ptr; 31 size_t len; 32 }; 33 34 static char st1[] = "abcdefghijklmnop"; 35 36 static void test_stringio(void) 37 { 38 unsigned char r = 0; 39 asm volatile("cld \n\t" 40 "movw %0, %%dx \n\t" 41 "rep outsb \n\t" 42 : : "i"((short)TESTDEV_IO_PORT), 43 "S"(st1), "c"(sizeof(st1) - 1)); 44 asm volatile("inb %1, %0\n\t" : "=a"(r) : "i"((short)TESTDEV_IO_PORT)); 45 report(r == st1[sizeof(st1) - 2], "outsb up"); /* last char */ 46 47 asm volatile("std \n\t" 48 "movw %0, %%dx \n\t" 49 "rep outsb \n\t" 50 : : "i"((short)TESTDEV_IO_PORT), 51 "S"(st1 + sizeof(st1) - 2), "c"(sizeof(st1) - 1)); 52 asm volatile("cld \n\t" : : ); 53 asm volatile("in %1, %0\n\t" : "=a"(r) : "i"((short)TESTDEV_IO_PORT)); 54 report(r == st1[0], "outsb down"); 55 } 56 57 static void test_cmps_one(unsigned char *m1, unsigned char *m3) 58 { 59 void *rsi, *rdi; 60 long rcx, tmp; 61 62 rsi = m1; rdi = m3; rcx = 30; 63 asm volatile("xor %[tmp], %[tmp] \n\t" 64 "repe cmpsb" 65 : "+S"(rsi), "+D"(rdi), "+c"(rcx), [tmp]"=&r"(tmp) 66 : : "cc"); 67 report(rcx == 0 && rsi == m1 + 30 && rdi == m3 + 30, "repe/cmpsb (1)"); 68 69 rsi = m1; rdi = m3; rcx = 30; 70 asm volatile("or $1, %[tmp]\n\t" // clear ZF 71 "repe cmpsb" 72 : "+S"(rsi), "+D"(rdi), "+c"(rcx), [tmp]"=&r"(tmp) 73 : : "cc"); 74 report(rcx == 0 && rsi == m1 + 30 && rdi == m3 + 30, 75 "repe cmpsb (1.zf)"); 76 77 rsi = m1; rdi = m3; rcx = 15; 78 asm volatile("xor %[tmp], %[tmp] \n\t" 79 "repe cmpsw" 80 : "+S"(rsi), "+D"(rdi), "+c"(rcx), [tmp]"=&r"(tmp) 81 : : "cc"); 82 report(rcx == 0 && rsi == m1 + 30 && rdi == m3 + 30, "repe cmpsw (1)"); 83 84 rsi = m1; rdi = m3; rcx = 7; 85 asm volatile("xor %[tmp], %[tmp] \n\t" 86 "repe cmpsl" 87 : "+S"(rsi), "+D"(rdi), "+c"(rcx), [tmp]"=&r"(tmp) 88 : : "cc"); 89 report(rcx == 0 && rsi == m1 + 28 && rdi == m3 + 28, "repe cmpll (1)"); 90 91 rsi = m1; rdi = m3; rcx = 4; 92 asm volatile("xor %[tmp], %[tmp] \n\t" 93 "repe cmpsq" 94 : "+S"(rsi), "+D"(rdi), "+c"(rcx), [tmp]"=&r"(tmp) 95 : : "cc"); 96 report(rcx == 0 && rsi == m1 + 32 && rdi == m3 + 32, "repe cmpsq (1)"); 97 98 rsi = m1; rdi = m3; rcx = 130; 99 asm volatile("xor %[tmp], %[tmp] \n\t" 100 "repe cmpsb" 101 : "+S"(rsi), "+D"(rdi), "+c"(rcx), [tmp]"=&r"(tmp) 102 : : "cc"); 103 report(rcx == 29 && rsi == m1 + 101 && rdi == m3 + 101, 104 "repe cmpsb (2)"); 105 106 rsi = m1; rdi = m3; rcx = 65; 107 asm volatile("xor %[tmp], %[tmp] \n\t" 108 "repe cmpsw" 109 : "+S"(rsi), "+D"(rdi), "+c"(rcx), [tmp]"=&r"(tmp) 110 : : "cc"); 111 report(rcx == 14 && rsi == m1 + 102 && rdi == m3 + 102, 112 "repe cmpsw (2)"); 113 114 rsi = m1; rdi = m3; rcx = 32; 115 asm volatile("xor %[tmp], %[tmp] \n\t" 116 "repe cmpsl" 117 : "+S"(rsi), "+D"(rdi), "+c"(rcx), [tmp]"=&r"(tmp) 118 : : "cc"); 119 report(rcx == 6 && rsi == m1 + 104 && rdi == m3 + 104, 120 "repe cmpll (2)"); 121 122 rsi = m1; rdi = m3; rcx = 16; 123 asm volatile("xor %[tmp], %[tmp] \n\t" 124 "repe cmpsq" 125 : "+S"(rsi), "+D"(rdi), "+c"(rcx), [tmp]"=&r"(tmp) 126 : : "cc"); 127 report(rcx == 3 && rsi == m1 + 104 && rdi == m3 + 104, 128 "repe cmpsq (2)"); 129 130 } 131 132 static void test_cmps(void *mem) 133 { 134 unsigned char *m1 = mem, *m2 = mem + 1024; 135 unsigned char m3[1024]; 136 137 for (int i = 0; i < 100; ++i) 138 m1[i] = m2[i] = m3[i] = i; 139 for (int i = 100; i < 200; ++i) 140 m1[i] = (m3[i] = m2[i] = i) + 1; 141 test_cmps_one(m1, m3); 142 test_cmps_one(m1, m2); 143 } 144 145 static void test_scas(void *mem) 146 { 147 bool z; 148 void *di; 149 150 *(ulong *)mem = 0x77665544332211; 151 152 di = mem; 153 asm ("scasb; setz %0" : "=rm"(z), "+D"(di) : "a"(0xff11)); 154 report(di == mem + 1 && z, "scasb match"); 155 156 di = mem; 157 asm ("scasb; setz %0" : "=rm"(z), "+D"(di) : "a"(0xff54)); 158 report(di == mem + 1 && !z, "scasb mismatch"); 159 160 di = mem; 161 asm ("scasw; setz %0" : "=rm"(z), "+D"(di) : "a"(0xff2211)); 162 report(di == mem + 2 && z, "scasw match"); 163 164 di = mem; 165 asm ("scasw; setz %0" : "=rm"(z), "+D"(di) : "a"(0xffdd11)); 166 report(di == mem + 2 && !z, "scasw mismatch"); 167 168 di = mem; 169 asm ("scasl; setz %0" : "=rm"(z), "+D"(di) : "a"(0xff44332211ul)); 170 report(di == mem + 4 && z, "scasd match"); 171 172 di = mem; 173 asm ("scasl; setz %0" : "=rm"(z), "+D"(di) : "a"(0x45332211)); 174 report(di == mem + 4 && !z, "scasd mismatch"); 175 176 di = mem; 177 asm ("scasq; setz %0" : "=rm"(z), "+D"(di) : "a"(0x77665544332211ul)); 178 report(di == mem + 8 && z, "scasq match"); 179 180 di = mem; 181 asm ("scasq; setz %0" : "=rm"(z), "+D"(di) : "a"(3)); 182 report(di == mem + 8 && !z, "scasq mismatch"); 183 } 184 185 static void test_cr8(void) 186 { 187 unsigned long src, dst; 188 189 dst = 777; 190 src = 3; 191 asm volatile("mov %[src], %%cr8; mov %%cr8, %[dst]" 192 : [dst]"+r"(dst), [src]"+r"(src)); 193 report(dst == 3 && src == 3, "mov %%cr8"); 194 } 195 196 static void test_push(void *mem) 197 { 198 unsigned long tmp; 199 unsigned long *stack_top = mem + 4096; 200 unsigned long *new_stack_top; 201 unsigned long memw = 0x123456789abcdeful; 202 203 memset(mem, 0x55, (void *)stack_top - mem); 204 205 asm volatile("mov %%rsp, %[tmp] \n\t" 206 "mov %[stack_top], %%rsp \n\t" 207 "pushq $-7 \n\t" 208 "pushq %[reg] \n\t" 209 "pushq (%[mem]) \n\t" 210 "pushq $-7070707 \n\t" 211 "mov %%rsp, %[new_stack_top] \n\t" 212 "mov %[tmp], %%rsp" 213 : [tmp]"=&r"(tmp), [new_stack_top]"=r"(new_stack_top) 214 : [stack_top]"r"(stack_top), 215 [reg]"r"(-17l), [mem]"r"(&memw) 216 : "memory"); 217 218 report(stack_top[-1] == -7ul, "push $imm8"); 219 report(stack_top[-2] == -17ul, "push %%reg"); 220 report(stack_top[-3] == 0x123456789abcdeful, "push mem"); 221 report(stack_top[-4] == -7070707, "push $imm"); 222 } 223 224 static void test_pop(void *mem) 225 { 226 unsigned long tmp, tmp3, rsp, rbp; 227 unsigned long *stack_top = mem + 4096; 228 unsigned long memw = 0x123456789abcdeful; 229 static unsigned long tmp2; 230 231 memset(mem, 0x55, (void *)stack_top - mem); 232 233 asm volatile("pushq %[val] \n\t" 234 "popq (%[mem])" 235 : : [val]"m"(memw), [mem]"r"(mem) : "memory"); 236 report(*(unsigned long *)mem == memw, "pop mem"); 237 238 memw = 7 - memw; 239 asm volatile("mov %%rsp, %[tmp] \n\t" 240 "mov %[stack_top], %%rsp \n\t" 241 "pushq %[val] \n\t" 242 "popq %[tmp2] \n\t" 243 "mov %[tmp], %%rsp" 244 : [tmp]"=&r"(tmp), [tmp2]"=m"(tmp2) 245 : [val]"r"(memw), [stack_top]"r"(stack_top) 246 : "memory"); 247 report(tmp2 == memw, "pop mem (2)"); 248 249 memw = 129443 - memw; 250 asm volatile("mov %%rsp, %[tmp] \n\t" 251 "mov %[stack_top], %%rsp \n\t" 252 "pushq %[val] \n\t" 253 "popq %[tmp2] \n\t" 254 "mov %[tmp], %%rsp" 255 : [tmp]"=&r"(tmp), [tmp2]"=r"(tmp2) 256 : [val]"r"(memw), [stack_top]"r"(stack_top) 257 : "memory"); 258 report(tmp2 == memw, "pop reg"); 259 260 asm volatile("mov %%rsp, %[tmp] \n\t" 261 "mov %[stack_top], %%rsp \n\t" 262 "lea 1f(%%rip), %%rax \n\t" 263 "push %%rax \n\t" 264 "ret \n\t" 265 "2: jmp 2b \n\t" 266 "1: mov %[tmp], %%rsp" 267 : [tmp]"=&r"(tmp) : [stack_top]"r"(stack_top) 268 : "memory", "rax"); 269 report_pass("ret"); 270 271 stack_top[-1] = 0x778899; 272 asm volatile("mov %[stack_top], %%r8 \n\t" 273 "mov %%rsp, %%r9 \n\t" 274 "xchg %%rbp, %%r8 \n\t" 275 "leave \n\t" 276 "xchg %%rsp, %%r9 \n\t" 277 "xchg %%rbp, %%r8 \n\t" 278 "mov %%r9, %[tmp] \n\t" 279 "mov %%r8, %[tmp3]" 280 : [tmp]"=&r"(tmp), [tmp3]"=&r"(tmp3) : [stack_top]"r"(stack_top-1) 281 : "memory", "r8", "r9"); 282 report(tmp == (ulong)stack_top && tmp3 == 0x778899, "leave"); 283 284 rbp = 0xaa55aa55bb66bb66ULL; 285 rsp = (unsigned long)stack_top; 286 asm volatile("mov %[rsp], %%r8 \n\t" 287 "mov %[rbp], %%r9 \n\t" 288 "xchg %%rsp, %%r8 \n\t" 289 "xchg %%rbp, %%r9 \n\t" 290 "enter $0x1238, $0 \n\t" 291 "xchg %%rsp, %%r8 \n\t" 292 "xchg %%rbp, %%r9 \n\t" 293 "xchg %%r8, %[rsp] \n\t" 294 "xchg %%r9, %[rbp]" 295 : [rsp]"+a"(rsp), [rbp]"+b"(rbp) : : "memory", "r8", "r9"); 296 report(rsp == (unsigned long)stack_top - 8 - 0x1238 297 && rbp == (unsigned long)stack_top - 8 298 && stack_top[-1] == 0xaa55aa55bb66bb66ULL, 299 "enter"); 300 } 301 302 static void test_ljmp(void *mem) 303 { 304 unsigned char *m = mem; 305 volatile int res = 1; 306 307 *(unsigned long**)m = &&jmpf; 308 asm volatile ("data16 mov %%cs, %0":"=m"(*(m + sizeof(unsigned long)))); 309 asm volatile ("rex64 ljmp *%0"::"m"(*m)); 310 res = 0; 311 jmpf: 312 report(res, "ljmp"); 313 } 314 315 static void test_incdecnotneg(void *mem) 316 { 317 unsigned long *m = mem, v = 1234; 318 unsigned char *mb = mem, vb = 66; 319 320 *m = 0; 321 322 asm volatile ("incl %0":"+m"(*m)); 323 report(*m == 1, "incl"); 324 asm volatile ("decl %0":"+m"(*m)); 325 report(*m == 0, "decl"); 326 asm volatile ("incb %0":"+m"(*m)); 327 report(*m == 1, "incb"); 328 asm volatile ("decb %0":"+m"(*m)); 329 report(*m == 0, "decb"); 330 331 asm volatile ("lock incl %0":"+m"(*m)); 332 report(*m == 1, "lock incl"); 333 asm volatile ("lock decl %0":"+m"(*m)); 334 report(*m == 0, "lock decl"); 335 asm volatile ("lock incb %0":"+m"(*m)); 336 report(*m == 1, "lock incb"); 337 asm volatile ("lock decb %0":"+m"(*m)); 338 report(*m == 0, "lock decb"); 339 340 *m = v; 341 342 asm ("lock negq %0" : "+m"(*m)); v = -v; 343 report(*m == v, "lock negl"); 344 asm ("lock notq %0" : "+m"(*m)); v = ~v; 345 report(*m == v, "lock notl"); 346 347 *mb = vb; 348 349 asm ("lock negb %0" : "+m"(*mb)); vb = -vb; 350 report(*mb == vb, "lock negb"); 351 asm ("lock notb %0" : "+m"(*mb)); vb = ~vb; 352 report(*mb == vb, "lock notb"); 353 } 354 355 static void test_smsw(uint64_t *h_mem) 356 { 357 char mem[16]; 358 unsigned short msw, msw_orig, *pmsw; 359 int i, zero; 360 361 msw_orig = read_cr0(); 362 363 asm("smsw %0" : "=r"(msw)); 364 report(msw == msw_orig, "smsw (1)"); 365 366 memset(mem, 0, 16); 367 pmsw = (void *)mem; 368 asm("smsw %0" : "=m"(pmsw[4])); 369 zero = 1; 370 for (i = 0; i < 8; ++i) 371 if (i != 4 && pmsw[i]) 372 zero = 0; 373 report(msw == pmsw[4] && zero, "smsw (2)"); 374 375 /* Trigger exit on smsw */ 376 *h_mem = 0x12345678abcdeful; 377 asm volatile("smsw %0" : "+m"(*h_mem)); 378 report(msw == (unsigned short)*h_mem && 379 (*h_mem & ~0xfffful) == 0x12345678ab0000ul, "smsw (3)"); 380 } 381 382 static void test_lmsw(void) 383 { 384 char mem[16]; 385 unsigned short msw, *pmsw; 386 unsigned long cr0; 387 388 cr0 = read_cr0(); 389 390 msw = cr0 ^ 8; 391 asm("lmsw %0" : : "r"(msw)); 392 printf("before %lx after %lx\n", cr0, read_cr0()); 393 report((cr0 ^ read_cr0()) == 8, "lmsw (1)"); 394 395 pmsw = (void *)mem; 396 *pmsw = cr0; 397 asm("lmsw %0" : : "m"(*pmsw)); 398 printf("before %lx after %lx\n", cr0, read_cr0()); 399 report(cr0 == read_cr0(), "lmsw (2)"); 400 401 /* lmsw can't clear cr0.pe */ 402 msw = (cr0 & ~1ul) ^ 4; /* change EM to force trap */ 403 asm("lmsw %0" : : "r"(msw)); 404 report((cr0 ^ read_cr0()) == 4 && (cr0 & 1), "lmsw (3)"); 405 406 /* back to normal */ 407 msw = cr0; 408 asm("lmsw %0" : : "r"(msw)); 409 } 410 411 static void test_xchg(void *mem) 412 { 413 unsigned long *memq = mem; 414 unsigned long rax; 415 416 asm volatile("mov $0x123456789abcdef, %%rax\n\t" 417 "mov %%rax, (%[memq])\n\t" 418 "mov $0xfedcba9876543210, %%rax\n\t" 419 "xchg %%al, (%[memq])\n\t" 420 "mov %%rax, %[rax]\n\t" 421 : [rax]"=r"(rax) 422 : [memq]"r"(memq) 423 : "memory", "rax"); 424 report(rax == 0xfedcba98765432ef && *memq == 0x123456789abcd10, 425 "xchg reg, r/m (1)"); 426 427 asm volatile("mov $0x123456789abcdef, %%rax\n\t" 428 "mov %%rax, (%[memq])\n\t" 429 "mov $0xfedcba9876543210, %%rax\n\t" 430 "xchg %%ax, (%[memq])\n\t" 431 "mov %%rax, %[rax]\n\t" 432 : [rax]"=r"(rax) 433 : [memq]"r"(memq) 434 : "memory", "rax"); 435 report(rax == 0xfedcba987654cdef && *memq == 0x123456789ab3210, 436 "xchg reg, r/m (2)"); 437 438 asm volatile("mov $0x123456789abcdef, %%rax\n\t" 439 "mov %%rax, (%[memq])\n\t" 440 "mov $0xfedcba9876543210, %%rax\n\t" 441 "xchg %%eax, (%[memq])\n\t" 442 "mov %%rax, %[rax]\n\t" 443 : [rax]"=r"(rax) 444 : [memq]"r"(memq) 445 : "memory", "rax"); 446 report(rax == 0x89abcdef && *memq == 0x123456776543210, 447 "xchg reg, r/m (3)"); 448 449 asm volatile("mov $0x123456789abcdef, %%rax\n\t" 450 "mov %%rax, (%[memq])\n\t" 451 "mov $0xfedcba9876543210, %%rax\n\t" 452 "xchg %%rax, (%[memq])\n\t" 453 "mov %%rax, %[rax]\n\t" 454 : [rax]"=r"(rax) 455 : [memq]"r"(memq) 456 : "memory", "rax"); 457 report(rax == 0x123456789abcdef && *memq == 0xfedcba9876543210, 458 "xchg reg, r/m (4)"); 459 } 460 461 static void test_xadd(void *mem) 462 { 463 unsigned long *memq = mem; 464 unsigned long rax; 465 466 asm volatile("mov $0x123456789abcdef, %%rax\n\t" 467 "mov %%rax, (%[memq])\n\t" 468 "mov $0xfedcba9876543210, %%rax\n\t" 469 "xadd %%al, (%[memq])\n\t" 470 "mov %%rax, %[rax]\n\t" 471 : [rax]"=r"(rax) 472 : [memq]"r"(memq) 473 : "memory", "rax"); 474 report(rax == 0xfedcba98765432ef && *memq == 0x123456789abcdff, 475 "xadd reg, r/m (1)"); 476 477 asm volatile("mov $0x123456789abcdef, %%rax\n\t" 478 "mov %%rax, (%[memq])\n\t" 479 "mov $0xfedcba9876543210, %%rax\n\t" 480 "xadd %%ax, (%[memq])\n\t" 481 "mov %%rax, %[rax]\n\t" 482 : [rax]"=r"(rax) 483 : [memq]"r"(memq) 484 : "memory", "rax"); 485 report(rax == 0xfedcba987654cdef && *memq == 0x123456789abffff, 486 "xadd reg, r/m (2)"); 487 488 asm volatile("mov $0x123456789abcdef, %%rax\n\t" 489 "mov %%rax, (%[memq])\n\t" 490 "mov $0xfedcba9876543210, %%rax\n\t" 491 "xadd %%eax, (%[memq])\n\t" 492 "mov %%rax, %[rax]\n\t" 493 : [rax]"=r"(rax) 494 : [memq]"r"(memq) 495 : "memory", "rax"); 496 report(rax == 0x89abcdef && *memq == 0x1234567ffffffff, 497 "xadd reg, r/m (3)"); 498 499 asm volatile("mov $0x123456789abcdef, %%rax\n\t" 500 "mov %%rax, (%[memq])\n\t" 501 "mov $0xfedcba9876543210, %%rax\n\t" 502 "xadd %%rax, (%[memq])\n\t" 503 "mov %%rax, %[rax]\n\t" 504 : [rax]"=r"(rax) 505 : [memq]"r"(memq) 506 : "memory", "rax"); 507 report(rax == 0x123456789abcdef && *memq == 0xffffffffffffffff, 508 "xadd reg, r/m (4)"); 509 } 510 511 static void test_btc(void *mem) 512 { 513 unsigned int *a = mem; 514 515 memset(mem, 0, 4 * sizeof(unsigned int)); 516 517 asm ("btcl $32, %0" :: "m"(a[0]) : "memory"); 518 asm ("btcl $1, %0" :: "m"(a[1]) : "memory"); 519 asm ("btcl %1, %0" :: "m"(a[0]), "r"(66) : "memory"); 520 report(a[0] == 1 && a[1] == 2 && a[2] == 4, "btcl imm8, r/m"); 521 522 asm ("btcl %1, %0" :: "m"(a[3]), "r"(-1) : "memory"); 523 report(a[0] == 1 && a[1] == 2 && a[2] == 0x80000004, "btcl reg, r/m"); 524 525 asm ("btcq %1, %0" : : "m"(a[2]), "r"(-1l) : "memory"); 526 report(a[0] == 1 && a[1] == 0x80000002 && a[2] == 0x80000004 && a[3] == 0, 527 "btcq reg, r/m"); 528 } 529 530 static void test_bsfbsr(void *mem) 531 { 532 unsigned long rax, *memq = mem; 533 unsigned eax, *meml = mem; 534 unsigned short ax, *memw = mem; 535 unsigned char z; 536 537 *memw = 0xc000; 538 asm("bsfw %[mem], %[a]" : [a]"=a"(ax) : [mem]"m"(*memw)); 539 report(ax == 14, "bsfw r/m, reg"); 540 541 *meml = 0xc0000000; 542 asm("bsfl %[mem], %[a]" : [a]"=a"(eax) : [mem]"m"(*meml)); 543 report(eax == 30, "bsfl r/m, reg"); 544 545 *memq = 0xc00000000000; 546 asm("bsfq %[mem], %[a]" : [a]"=a"(rax) : [mem]"m"(*memq)); 547 report(rax == 46, "bsfq r/m, reg"); 548 549 *memq = 0; 550 asm("bsfq %[mem], %[a]; setz %[z]" 551 : [a]"=a"(rax), [z]"=rm"(z) : [mem]"m"(*memq)); 552 report(z == 1, "bsfq r/m, reg"); 553 554 *memw = 0xc000; 555 asm("bsrw %[mem], %[a]" : [a]"=a"(ax) : [mem]"m"(*memw)); 556 report(ax == 15, "bsrw r/m, reg"); 557 558 *meml = 0xc0000000; 559 asm("bsrl %[mem], %[a]" : [a]"=a"(eax) : [mem]"m"(*meml)); 560 report(eax == 31, "bsrl r/m, reg"); 561 562 *memq = 0xc00000000000; 563 asm("bsrq %[mem], %[a]" : [a]"=a"(rax) : [mem]"m"(*memq)); 564 report(rax == 47, "bsrq r/m, reg"); 565 566 *memq = 0; 567 asm("bsrq %[mem], %[a]; setz %[z]" 568 : [a]"=a"(rax), [z]"=rm"(z) : [mem]"m"(*memq)); 569 report(z == 1, "bsrq r/m, reg"); 570 } 571 572 static void test_imul(ulong *mem) 573 { 574 ulong a; 575 576 *mem = 51; a = 0x1234567812345678UL; 577 asm ("imulw %1, %%ax" : "+a"(a) : "m"(*mem)); 578 report(a == 0x12345678123439e8, "imul ax, mem"); 579 580 *mem = 51; a = 0x1234567812345678UL; 581 asm ("imull %1, %%eax" : "+a"(a) : "m"(*mem)); 582 report(a == 0xa06d39e8, "imul eax, mem"); 583 584 *mem = 51; a = 0x1234567812345678UL; 585 asm ("imulq %1, %%rax" : "+a"(a) : "m"(*mem)); 586 report(a == 0xA06D39EBA06D39E8UL, "imul rax, mem"); 587 588 *mem = 0x1234567812345678UL; a = 0x8765432187654321L; 589 asm ("imulw $51, %1, %%ax" : "+a"(a) : "m"(*mem)); 590 report(a == 0x87654321876539e8, "imul ax, mem, imm8"); 591 592 *mem = 0x1234567812345678UL; 593 asm ("imull $51, %1, %%eax" : "+a"(a) : "m"(*mem)); 594 report(a == 0xa06d39e8, "imul eax, mem, imm8"); 595 596 *mem = 0x1234567812345678UL; 597 asm ("imulq $51, %1, %%rax" : "+a"(a) : "m"(*mem)); 598 report(a == 0xA06D39EBA06D39E8UL, "imul rax, mem, imm8"); 599 600 *mem = 0x1234567812345678UL; a = 0x8765432187654321L; 601 asm ("imulw $311, %1, %%ax" : "+a"(a) : "m"(*mem)); 602 report(a == 0x8765432187650bc8, "imul ax, mem, imm"); 603 604 *mem = 0x1234567812345678UL; 605 asm ("imull $311, %1, %%eax" : "+a"(a) : "m"(*mem)); 606 report(a == 0x1d950bc8, "imul eax, mem, imm"); 607 608 *mem = 0x1234567812345678UL; 609 asm ("imulq $311, %1, %%rax" : "+a"(a) : "m"(*mem)); 610 report(a == 0x1D950BDE1D950BC8L, "imul rax, mem, imm"); 611 } 612 613 static void test_muldiv(long *mem) 614 { 615 long a, d, aa, dd; 616 u8 ex = 1; 617 618 *mem = 0; a = 1; d = 2; 619 asm (ASM_TRY("1f") "divq %3; movb $0, %2; 1:" 620 : "+a"(a), "+d"(d), "+q"(ex) : "m"(*mem)); 621 report(a == 1 && d == 2 && ex, "divq (fault)"); 622 623 *mem = 987654321098765UL; a = 123456789012345UL; d = 123456789012345UL; 624 asm (ASM_TRY("1f") "divq %3; movb $0, %2; 1:" 625 : "+a"(a), "+d"(d), "+q"(ex) : "m"(*mem)); 626 report(a == 0x1ffffffb1b963b33ul && d == 0x273ba4384ede2ul && !ex, 627 "divq (1)"); 628 aa = 0x1111111111111111; dd = 0x2222222222222222; 629 *mem = 0x3333333333333333; a = aa; d = dd; 630 asm("mulb %2" : "+a"(a), "+d"(d) : "m"(*mem)); 631 report(a == 0x1111111111110363 && d == dd, "mulb mem"); 632 *mem = 0x3333333333333333; a = aa; d = dd; 633 asm("mulw %2" : "+a"(a), "+d"(d) : "m"(*mem)); 634 report(a == 0x111111111111c963 && d == 0x2222222222220369, "mulw mem"); 635 *mem = 0x3333333333333333; a = aa; d = dd; 636 asm("mull %2" : "+a"(a), "+d"(d) : "m"(*mem)); 637 report(a == 0x962fc963 && d == 0x369d036, "mull mem"); 638 *mem = 0x3333333333333333; a = aa; d = dd; 639 asm("mulq %2" : "+a"(a), "+d"(d) : "m"(*mem)); 640 report(a == 0x2fc962fc962fc963 && d == 0x369d0369d0369d0, "mulq mem"); 641 } 642 643 typedef unsigned __attribute__((vector_size(16))) sse128; 644 645 static bool sseeq(uint32_t *v1, uint32_t *v2) 646 { 647 bool ok = true; 648 int i; 649 650 for (i = 0; i < 4; ++i) { 651 ok &= v1[i] == v2[i]; 652 } 653 654 return ok; 655 } 656 657 static __attribute__((target("sse2"))) void test_sse(uint32_t *mem) 658 { 659 sse128 vv; 660 uint32_t *v = (uint32_t *)&vv; 661 662 write_cr0(read_cr0() & ~6); /* EM, TS */ 663 write_cr4(read_cr4() | 0x200); /* OSFXSR */ 664 memset(&vv, 0, sizeof(vv)); 665 666 #define TEST_RW_SSE(insn) do { \ 667 v[0] = 1; v[1] = 2; v[2] = 3; v[3] = 4; \ 668 asm(insn " %1, %0" : "=m"(*mem) : "x"(vv) : "memory"); \ 669 report(sseeq(v, mem), insn " (read)"); \ 670 mem[0] = 5; mem[1] = 6; mem[2] = 7; mem[3] = 8; \ 671 asm(insn " %1, %0" : "=x"(vv) : "m"(*mem) : "memory"); \ 672 report(sseeq(v, mem), insn " (write)"); \ 673 } while (0) 674 675 TEST_RW_SSE("movdqu"); 676 TEST_RW_SSE("movaps"); 677 TEST_RW_SSE("movapd"); 678 TEST_RW_SSE("movups"); 679 TEST_RW_SSE("movupd"); 680 #undef TEST_RW_SSE 681 } 682 683 static void unaligned_movaps_handler(struct ex_regs *regs) 684 { 685 extern char unaligned_movaps_cont; 686 687 ++exceptions; 688 regs->rip = (ulong)&unaligned_movaps_cont; 689 } 690 691 static void cross_movups_handler(struct ex_regs *regs) 692 { 693 extern char cross_movups_cont; 694 695 ++exceptions; 696 regs->rip = (ulong)&cross_movups_cont; 697 } 698 699 static __attribute__((target("sse2"))) void test_sse_exceptions(void *cross_mem) 700 { 701 sse128 vv; 702 uint32_t *v = (uint32_t *)&vv; 703 uint32_t *mem; 704 uint8_t *bytes = cross_mem; // aligned on PAGE_SIZE*2 705 void *page2 = (void *)(&bytes[4096]); 706 struct pte_search search; 707 pteval_t orig_pte; 708 handler old; 709 710 // setup memory for unaligned access 711 mem = (uint32_t *)(&bytes[8]); 712 713 // test unaligned access for movups, movupd and movaps 714 v[0] = 1; v[1] = 2; v[2] = 3; v[3] = 4; 715 mem[0] = 5; mem[1] = 6; mem[2] = 8; mem[3] = 9; 716 asm("movups %1, %0" : "=m"(*mem) : "x"(vv) : "memory"); 717 report(sseeq(v, mem), "movups unaligned"); 718 719 v[0] = 1; v[1] = 2; v[2] = 3; v[3] = 4; 720 mem[0] = 5; mem[1] = 6; mem[2] = 7; mem[3] = 8; 721 asm("movupd %1, %0" : "=m"(*mem) : "x"(vv) : "memory"); 722 report(sseeq(v, mem), "movupd unaligned"); 723 exceptions = 0; 724 old = handle_exception(GP_VECTOR, unaligned_movaps_handler); 725 asm("movaps %1, %0\n\t unaligned_movaps_cont:" 726 : "=m"(*mem) : "x"(vv)); 727 handle_exception(GP_VECTOR, old); 728 report(exceptions == 1, "unaligned movaps exception"); 729 730 // setup memory for cross page access 731 mem = (uint32_t *)(&bytes[4096-8]); 732 v[0] = 1; v[1] = 2; v[2] = 3; v[3] = 4; 733 mem[0] = 5; mem[1] = 6; mem[2] = 7; mem[3] = 8; 734 735 asm("movups %1, %0" : "=m"(*mem) : "x"(vv) : "memory"); 736 report(sseeq(v, mem), "movups unaligned crosspage"); 737 738 // invalidate second page 739 search = find_pte_level(current_page_table(), page2, 1); 740 orig_pte = *search.pte; 741 install_pte(current_page_table(), 1, page2, 0, NULL); 742 invlpg(page2); 743 744 exceptions = 0; 745 old = handle_exception(PF_VECTOR, cross_movups_handler); 746 asm("movups %1, %0\n\t cross_movups_cont:" : "=m"(*mem) : "x"(vv) : 747 "memory"); 748 handle_exception(PF_VECTOR, old); 749 report(exceptions == 1, "movups crosspage exception"); 750 751 // restore invalidated page 752 install_pte(current_page_table(), 1, page2, orig_pte, NULL); 753 } 754 755 static void test_mmx(uint64_t *mem) 756 { 757 uint64_t v; 758 759 write_cr0(read_cr0() & ~6); /* EM, TS */ 760 asm volatile("fninit"); 761 v = 0x0102030405060708ULL; 762 asm("movq %1, %0" : "=m"(*mem) : "y"(v)); 763 report(v == *mem, "movq (mmx, read)"); 764 *mem = 0x8070605040302010ull; 765 asm("movq %1, %0" : "=y"(v) : "m"(*mem)); 766 report(v == *mem, "movq (mmx, write)"); 767 } 768 769 static void test_rip_relative(unsigned *mem, char *insn_ram) 770 { 771 /* movb $1, mem+2(%rip) */ 772 insn_ram[0] = 0xc6; 773 insn_ram[1] = 0x05; 774 *(unsigned *)&insn_ram[2] = 2 + (char *)mem - (insn_ram + 7); 775 insn_ram[6] = 0x01; 776 /* ret */ 777 insn_ram[7] = 0xc3; 778 779 *mem = 0; 780 asm("callq *%1" : "+m"(*mem) : "r"(insn_ram)); 781 report(*mem == 0x10000, "movb $imm, 0(%%rip)"); 782 } 783 784 static void test_shld_shrd(u32 *mem) 785 { 786 *mem = 0x12345678; 787 asm("shld %2, %1, %0" : "+m"(*mem) : "r"(0xaaaaaaaaU), "c"((u8)3)); 788 report(*mem == ((0x12345678 << 3) | 5), "shld (cl)"); 789 *mem = 0x12345678; 790 asm("shrd %2, %1, %0" : "+m"(*mem) : "r"(0x55555555U), "c"((u8)3)); 791 report(*mem == ((0x12345678 >> 3) | (5u << 29)), "shrd (cl)"); 792 } 793 794 static void test_cmov(u32 *mem) 795 { 796 u64 val; 797 *mem = 0xabcdef12u; 798 asm ("movq $0x1234567812345678, %%rax\n\t" 799 "cmpl %%eax, %%eax\n\t" 800 "cmovnel (%[mem]), %%eax\n\t" 801 "movq %%rax, %[val]\n\t" 802 : [val]"=r"(val) : [mem]"r"(mem) : "%rax", "cc"); 803 report(val == 0x12345678ul, "cmovnel"); 804 } 805 806 static unsigned long rip_advance; 807 808 static void advance_rip_and_note_exception(struct ex_regs *regs) 809 { 810 ++exceptions; 811 regs->rip += rip_advance; 812 } 813 814 static void test_mmx_movq_mf(uint64_t *mem) 815 { 816 /* movq %mm0, (%rax) */ 817 extern char movq_start, movq_end; 818 handler old; 819 820 uint16_t fcw = 0; /* all exceptions unmasked */ 821 write_cr0(read_cr0() & ~6); /* TS, EM */ 822 exceptions = 0; 823 old = handle_exception(MF_VECTOR, advance_rip_and_note_exception); 824 asm volatile("fninit; fldcw %0" : : "m"(fcw)); 825 asm volatile("fldz; fldz; fdivp"); /* generate exception */ 826 827 rip_advance = &movq_end - &movq_start; 828 asm(KVM_FEP "movq_start: movq %mm0, (%rax); movq_end:"); 829 /* exit MMX mode */ 830 asm volatile("fnclex; emms"); 831 report(exceptions == 1, "movq mmx generates #MF"); 832 handle_exception(MF_VECTOR, old); 833 } 834 835 static void test_jmp_noncanonical(uint64_t *mem) 836 { 837 extern char nc_jmp_start, nc_jmp_end; 838 handler old; 839 840 *mem = 0x1111111111111111ul; 841 842 exceptions = 0; 843 rip_advance = &nc_jmp_end - &nc_jmp_start; 844 old = handle_exception(GP_VECTOR, advance_rip_and_note_exception); 845 asm volatile ("nc_jmp_start: jmp *%0; nc_jmp_end:" : : "m"(*mem)); 846 report(exceptions == 1, "jump to non-canonical address"); 847 handle_exception(GP_VECTOR, old); 848 } 849 850 static void test_movabs(uint64_t *mem) 851 { 852 /* mov $0x9090909090909090, %rcx */ 853 unsigned long rcx; 854 asm(KVM_FEP "mov $0x9090909090909090, %0" : "=c" (rcx) : "0" (0)); 855 report(rcx == 0x9090909090909090, "64-bit mov imm2"); 856 } 857 858 static void test_smsw_reg(uint64_t *mem) 859 { 860 unsigned long cr0 = read_cr0(); 861 unsigned long rax; 862 const unsigned long in_rax = 0x1234567890abcdeful; 863 864 asm(KVM_FEP "smsww %w0\n\t" : "=a" (rax) : "0" (in_rax)); 865 report((u16)rax == (u16)cr0 && rax >> 16 == in_rax >> 16, 866 "16-bit smsw reg"); 867 868 asm(KVM_FEP "smswl %k0\n\t" : "=a" (rax) : "0" (in_rax)); 869 report(rax == (u32)cr0, "32-bit smsw reg"); 870 871 asm(KVM_FEP "smswq %q0\n\t" : "=a" (rax) : "0" (in_rax)); 872 report(rax == cr0, "64-bit smsw reg"); 873 } 874 875 static void test_nop(uint64_t *mem) 876 { 877 unsigned long rax; 878 const unsigned long in_rax = 0x1234567890abcdeful; 879 asm(KVM_FEP "nop\n\t" : "=a" (rax) : "0" (in_rax)); 880 report(rax == in_rax, "nop"); 881 } 882 883 static void test_mov_dr(uint64_t *mem) 884 { 885 unsigned long rax; 886 887 asm(KVM_FEP "movq %0, %%dr6\n\t" 888 KVM_FEP "movq %%dr6, %0\n\t" : "=a" (rax) : "a" (0)); 889 890 if (this_cpu_has(X86_FEATURE_RTM)) 891 report(rax == (DR6_ACTIVE_LOW & ~DR6_RTM), "mov_dr6"); 892 else 893 report(rax == DR6_ACTIVE_LOW, "mov_dr6"); 894 } 895 896 static void test_illegal_lea(void) 897 { 898 unsigned int vector; 899 900 asm volatile (ASM_TRY_FEP("1f") 901 ".byte 0x8d; .byte 0xc0\n\t" 902 "1:" 903 : : : "memory", "eax"); 904 905 vector = exception_vector(); 906 report(vector == UD_VECTOR, 907 "Wanted #UD on LEA with /reg, got vector = %u", vector); 908 } 909 910 static void test_push16(uint64_t *mem) 911 { 912 uint64_t rsp1, rsp2; 913 uint16_t r; 914 915 asm volatile ( "movq %%rsp, %[rsp1]\n\t" 916 "pushw %[v]\n\t" 917 "popw %[r]\n\t" 918 "movq %%rsp, %[rsp2]\n\t" 919 "movq %[rsp1], %%rsp\n\t" : 920 [rsp1]"=r"(rsp1), [rsp2]"=r"(rsp2), [r]"=r"(r) 921 : [v]"m"(*mem) : "memory"); 922 report(rsp1 == rsp2, "push16"); 923 } 924 925 static void test_crosspage_mmio(volatile uint8_t *mem) 926 { 927 volatile uint16_t w, *pw; 928 929 pw = (volatile uint16_t *)&mem[4095]; 930 mem[4095] = 0x99; 931 mem[4096] = 0x77; 932 asm volatile("mov %1, %0" : "=r"(w) : "m"(*pw) : "memory"); 933 report(w == 0x7799, "cross-page mmio read"); 934 asm volatile("mov %1, %0" : "=m"(*pw) : "r"((uint16_t)0x88aa)); 935 report(mem[4095] == 0xaa && mem[4096] == 0x88, "cross-page mmio write"); 936 } 937 938 static void test_string_io_mmio(volatile uint8_t *mem) 939 { 940 /* Cross MMIO pages.*/ 941 volatile uint8_t *mmio = mem + 4032; 942 943 asm volatile("outw %%ax, %%dx \n\t" : : "a"(0x9999), "d"(TESTDEV_IO_PORT)); 944 945 asm volatile ("cld; rep insb" : : "d" (TESTDEV_IO_PORT), "D" (mmio), "c" (1024)); 946 947 report(mmio[1023] == 0x99, "string_io_mmio"); 948 } 949 950 /* kvm doesn't allow lidt/lgdt from mmio, so the test is disabled */ 951 #if 0 952 static void test_lgdt_lidt(volatile uint8_t *mem) 953 { 954 struct descriptor_table_ptr orig, fresh = {}; 955 956 sgdt(&orig); 957 *(struct descriptor_table_ptr *)mem = (struct descriptor_table_ptr) { 958 .limit = 0xf234, 959 .base = 0x12345678abcd, 960 }; 961 cli(); 962 asm volatile("lgdt %0" : : "m"(*(struct descriptor_table_ptr *)mem)); 963 sgdt(&fresh); 964 lgdt(&orig); 965 sti(); 966 report(orig.limit == fresh.limit && orig.base == fresh.base, 967 "lgdt (long address)"); 968 969 sidt(&orig); 970 *(struct descriptor_table_ptr *)mem = (struct descriptor_table_ptr) { 971 .limit = 0x432f, 972 .base = 0xdbca87654321, 973 }; 974 cli(); 975 asm volatile("lidt %0" : : "m"(*(struct descriptor_table_ptr *)mem)); 976 sidt(&fresh); 977 lidt(&orig); 978 sti(); 979 report(orig.limit == fresh.limit && orig.base == fresh.base, 980 "lidt (long address)"); 981 } 982 #endif 983 984 static void ss_bad_rpl(struct ex_regs *regs) 985 { 986 extern char ss_bad_rpl_cont; 987 988 ++exceptions; 989 regs->rip = (ulong)&ss_bad_rpl_cont; 990 } 991 992 static void test_sreg(volatile uint16_t *mem) 993 { 994 u16 ss = read_ss(); 995 handler old; 996 997 // check for null segment load 998 *mem = 0; 999 asm volatile("mov %0, %%ss" : : "m"(*mem)); 1000 report(read_ss() == 0, "mov null, %%ss"); 1001 1002 // check for exception when ss.rpl != cpl on null segment load 1003 exceptions = 0; 1004 old = handle_exception(GP_VECTOR, ss_bad_rpl); 1005 *mem = 3; 1006 asm volatile("mov %0, %%ss; ss_bad_rpl_cont:" : : "m"(*mem)); 1007 report(exceptions == 1 && read_ss() == 0, 1008 "mov null, %%ss (with ss.rpl != cpl)"); 1009 handle_exception(GP_VECTOR, old); 1010 write_ss(ss); 1011 } 1012 1013 static uint64_t usr_gs_mov(void) 1014 { 1015 static uint64_t dummy = MAGIC_NUM; 1016 uint64_t dummy_ptr = (uint64_t)&dummy; 1017 uint64_t ret; 1018 1019 dummy_ptr -= GS_BASE; 1020 asm volatile("mov %%gs:(%%rcx), %%rax" : "=a"(ret): "c"(dummy_ptr) :); 1021 1022 return ret; 1023 } 1024 1025 static void test_iret(void) 1026 { 1027 uint64_t val; 1028 bool raised_vector; 1029 1030 /* Update GS base to 4MiB */ 1031 wrmsr(MSR_GS_BASE, GS_BASE); 1032 1033 /* 1034 * Per the SDM, jumping to user mode via `iret`, which is returning to 1035 * outer privilege level, for segment registers (ES, FS, GS, and DS) 1036 * if the check fails, the segment selector becomes null. 1037 * 1038 * In our test case, GS becomes null. 1039 */ 1040 val = run_in_user((usermode_func)usr_gs_mov, GP_VECTOR, 1041 0, 0, 0, 0, &raised_vector); 1042 1043 report(val == MAGIC_NUM, "Test ret/iret with a nullified segment"); 1044 } 1045 1046 /* Broken emulation causes triple fault, which skips the other tests. */ 1047 #if 0 1048 static void test_lldt(volatile uint16_t *mem) 1049 { 1050 u64 gdt[] = { 0, /* null descriptor */ 1051 #ifdef __X86_64__ 1052 0, /* ldt descriptor is 16 bytes in long mode */ 1053 #endif 1054 0x0000f82000000ffffull /* ldt descriptor */ }; 1055 struct descriptor_table_ptr gdt_ptr = { .limit = sizeof(gdt) - 1, 1056 .base = (ulong)&gdt }; 1057 struct descriptor_table_ptr orig_gdt; 1058 1059 cli(); 1060 sgdt(&orig_gdt); 1061 lgdt(&gdt_ptr); 1062 *mem = 0x8; 1063 asm volatile("lldt %0" : : "m"(*mem)); 1064 lgdt(&orig_gdt); 1065 sti(); 1066 report(sldt() == *mem, "lldt"); 1067 } 1068 #endif 1069 1070 static void test_ltr(volatile uint16_t *mem) 1071 { 1072 struct descriptor_table_ptr gdt_ptr; 1073 uint64_t *gdt, *trp; 1074 uint16_t tr = str(); 1075 uint64_t busy_mask = (uint64_t)1 << 41; 1076 1077 sgdt(&gdt_ptr); 1078 gdt = (uint64_t *)gdt_ptr.base; 1079 trp = &gdt[tr >> 3]; 1080 *trp &= ~busy_mask; 1081 *mem = tr; 1082 asm volatile("ltr %0" : : "m"(*mem) : "memory"); 1083 report(str() == tr && (*trp & busy_mask), "ltr"); 1084 } 1085 1086 static void test_simplealu(u32 *mem) 1087 { 1088 *mem = 0x1234; 1089 asm("or %1, %0" : "+m"(*mem) : "r"(0x8001)); 1090 report(*mem == 0x9235, "or"); 1091 asm("add %1, %0" : "+m"(*mem) : "r"(2)); 1092 report(*mem == 0x9237, "add"); 1093 asm("xor %1, %0" : "+m"(*mem) : "r"(0x1111)); 1094 report(*mem == 0x8326, "xor"); 1095 asm("sub %1, %0" : "+m"(*mem) : "r"(0x26)); 1096 report(*mem == 0x8300, "sub"); 1097 asm("clc; adc %1, %0" : "+m"(*mem) : "r"(0x100)); 1098 report(*mem == 0x8400, "adc(0)"); 1099 asm("stc; adc %1, %0" : "+m"(*mem) : "r"(0x100)); 1100 report(*mem == 0x8501, "adc(0)"); 1101 asm("clc; sbb %1, %0" : "+m"(*mem) : "r"(0)); 1102 report(*mem == 0x8501, "sbb(0)"); 1103 asm("stc; sbb %1, %0" : "+m"(*mem) : "r"(0)); 1104 report(*mem == 0x8500, "sbb(1)"); 1105 asm("and %1, %0" : "+m"(*mem) : "r"(0xfe77)); 1106 report(*mem == 0x8400, "and"); 1107 asm("test %1, %0" : "+m"(*mem) : "r"(0xf000)); 1108 report(*mem == 0x8400, "test"); 1109 } 1110 1111 static void test_illegal_movbe(void) 1112 { 1113 unsigned int vector; 1114 1115 if (!this_cpu_has(X86_FEATURE_MOVBE)) { 1116 report_skip("MOVBE unsupported by CPU"); 1117 return; 1118 } 1119 1120 asm volatile(ASM_TRY("1f") 1121 ".byte 0x0f; .byte 0x38; .byte 0xf0; .byte 0xc0;\n\t" 1122 "1:" 1123 : : : "memory", "rax"); 1124 1125 vector = exception_vector(); 1126 report(vector == UD_VECTOR, 1127 "Wanted #UD on MOVBE with /reg, got vector = %u", vector); 1128 } 1129 1130 int main(void) 1131 { 1132 void *mem; 1133 void *insn_page; 1134 void *insn_ram; 1135 void *cross_mem; 1136 unsigned long t1, t2; 1137 1138 setup_vm(); 1139 1140 mem = alloc_vpages(2); 1141 install_page((void *)read_cr3(), IORAM_BASE_PHYS, mem); 1142 // install the page twice to test cross-page mmio 1143 install_page((void *)read_cr3(), IORAM_BASE_PHYS, mem + 4096); 1144 insn_page = alloc_page(); 1145 insn_ram = vmap(virt_to_phys(insn_page), 4096); 1146 cross_mem = vmap(virt_to_phys(alloc_pages(2)), 2 * PAGE_SIZE); 1147 1148 // test mov reg, r/m and mov r/m, reg 1149 t1 = 0x123456789abcdef; 1150 asm volatile("mov %[t1], (%[mem]) \n\t" 1151 "mov (%[mem]), %[t2]" 1152 : [t2]"=r"(t2) 1153 : [t1]"r"(t1), [mem]"r"(mem) 1154 : "memory"); 1155 report(t2 == 0x123456789abcdef, "mov reg, r/m (1)"); 1156 1157 test_simplealu(mem); 1158 test_cmps(mem); 1159 test_scas(mem); 1160 1161 test_push(mem); 1162 test_pop(mem); 1163 1164 test_xchg(mem); 1165 test_xadd(mem); 1166 1167 test_cr8(); 1168 1169 test_smsw(mem); 1170 test_lmsw(); 1171 test_ljmp(mem); 1172 test_stringio(); 1173 test_incdecnotneg(mem); 1174 test_btc(mem); 1175 test_bsfbsr(mem); 1176 test_imul(mem); 1177 test_muldiv(mem); 1178 test_sse(mem); 1179 test_sse_exceptions(cross_mem); 1180 test_mmx(mem); 1181 test_rip_relative(mem, insn_ram); 1182 test_shld_shrd(mem); 1183 //test_lgdt_lidt(mem); 1184 test_sreg(mem); 1185 test_iret(); 1186 //test_lldt(mem); 1187 test_ltr(mem); 1188 test_cmov(mem); 1189 1190 if (is_fep_available()) { 1191 test_mmx_movq_mf(mem); 1192 test_movabs(mem); 1193 test_smsw_reg(mem); 1194 test_nop(mem); 1195 test_mov_dr(mem); 1196 test_illegal_lea(); 1197 } else { 1198 report_skip("skipping register-only tests, " 1199 "use kvm.force_emulation_prefix=1 to enable"); 1200 } 1201 1202 test_push16(mem); 1203 test_crosspage_mmio(mem); 1204 1205 test_string_io_mmio(mem); 1206 1207 test_jmp_noncanonical(mem); 1208 test_illegal_movbe(); 1209 1210 return report_summary(); 1211 } 1212