1 #include "ioram.h" 2 #include "vm.h" 3 #include "libcflat.h" 4 #include "desc.h" 5 #include "types.h" 6 #include "processor.h" 7 #include "vmalloc.h" 8 #include "alloc_page.h" 9 10 #define memset __builtin_memset 11 #define TESTDEV_IO_PORT 0xe0 12 13 static int exceptions; 14 15 struct regs { 16 u64 rax, rbx, rcx, rdx; 17 u64 rsi, rdi, rsp, rbp; 18 u64 r8, r9, r10, r11; 19 u64 r12, r13, r14, r15; 20 u64 rip, rflags; 21 }; 22 struct regs inregs, outregs, save; 23 24 struct insn_desc { 25 u64 ptr; 26 size_t len; 27 }; 28 29 static char st1[] = "abcdefghijklmnop"; 30 31 void test_stringio() 32 { 33 unsigned char r = 0; 34 asm volatile("cld \n\t" 35 "movw %0, %%dx \n\t" 36 "rep outsb \n\t" 37 : : "i"((short)TESTDEV_IO_PORT), 38 "S"(st1), "c"(sizeof(st1) - 1)); 39 asm volatile("inb %1, %0\n\t" : "=a"(r) : "i"((short)TESTDEV_IO_PORT)); 40 report("outsb up", r == st1[sizeof(st1) - 2]); /* last char */ 41 42 asm volatile("std \n\t" 43 "movw %0, %%dx \n\t" 44 "rep outsb \n\t" 45 : : "i"((short)TESTDEV_IO_PORT), 46 "S"(st1 + sizeof(st1) - 2), "c"(sizeof(st1) - 1)); 47 asm volatile("cld \n\t" : : ); 48 asm volatile("in %1, %0\n\t" : "=a"(r) : "i"((short)TESTDEV_IO_PORT)); 49 report("outsb down", r == st1[0]); 50 } 51 52 void test_cmps_one(unsigned char *m1, unsigned char *m3) 53 { 54 void *rsi, *rdi; 55 long rcx, tmp; 56 57 rsi = m1; rdi = m3; rcx = 30; 58 asm volatile("xor %[tmp], %[tmp] \n\t" 59 "repe/cmpsb" 60 : "+S"(rsi), "+D"(rdi), "+c"(rcx), [tmp]"=&r"(tmp) 61 : : "cc"); 62 report("repe/cmpsb (1)", rcx == 0 && rsi == m1 + 30 && rdi == m3 + 30); 63 64 rsi = m1; rdi = m3; rcx = 30; 65 asm volatile("or $1, %[tmp]\n\t" // clear ZF 66 "repe/cmpsb" 67 : "+S"(rsi), "+D"(rdi), "+c"(rcx), [tmp]"=&r"(tmp) 68 : : "cc"); 69 report("repe/cmpsb (1.zf)", rcx == 0 && rsi == m1 + 30 && rdi == m3 + 30); 70 71 rsi = m1; rdi = m3; rcx = 15; 72 asm volatile("xor %[tmp], %[tmp] \n\t" 73 "repe/cmpsw" 74 : "+S"(rsi), "+D"(rdi), "+c"(rcx), [tmp]"=&r"(tmp) 75 : : "cc"); 76 report("repe/cmpsw (1)", rcx == 0 && rsi == m1 + 30 && rdi == m3 + 30); 77 78 rsi = m1; rdi = m3; rcx = 7; 79 asm volatile("xor %[tmp], %[tmp] \n\t" 80 "repe/cmpsl" 81 : "+S"(rsi), "+D"(rdi), "+c"(rcx), [tmp]"=&r"(tmp) 82 : : "cc"); 83 report("repe/cmpll (1)", rcx == 0 && rsi == m1 + 28 && rdi == m3 + 28); 84 85 rsi = m1; rdi = m3; rcx = 4; 86 asm volatile("xor %[tmp], %[tmp] \n\t" 87 "repe/cmpsq" 88 : "+S"(rsi), "+D"(rdi), "+c"(rcx), [tmp]"=&r"(tmp) 89 : : "cc"); 90 report("repe/cmpsq (1)", rcx == 0 && rsi == m1 + 32 && rdi == m3 + 32); 91 92 rsi = m1; rdi = m3; rcx = 130; 93 asm volatile("xor %[tmp], %[tmp] \n\t" 94 "repe/cmpsb" 95 : "+S"(rsi), "+D"(rdi), "+c"(rcx), [tmp]"=&r"(tmp) 96 : : "cc"); 97 report("repe/cmpsb (2)", 98 rcx == 29 && rsi == m1 + 101 && rdi == m3 + 101); 99 100 rsi = m1; rdi = m3; rcx = 65; 101 asm volatile("xor %[tmp], %[tmp] \n\t" 102 "repe/cmpsw" 103 : "+S"(rsi), "+D"(rdi), "+c"(rcx), [tmp]"=&r"(tmp) 104 : : "cc"); 105 report("repe/cmpsw (2)", 106 rcx == 14 && rsi == m1 + 102 && rdi == m3 + 102); 107 108 rsi = m1; rdi = m3; rcx = 32; 109 asm volatile("xor %[tmp], %[tmp] \n\t" 110 "repe/cmpsl" 111 : "+S"(rsi), "+D"(rdi), "+c"(rcx), [tmp]"=&r"(tmp) 112 : : "cc"); 113 report("repe/cmpll (2)", 114 rcx == 6 && rsi == m1 + 104 && rdi == m3 + 104); 115 116 rsi = m1; rdi = m3; rcx = 16; 117 asm volatile("xor %[tmp], %[tmp] \n\t" 118 "repe/cmpsq" 119 : "+S"(rsi), "+D"(rdi), "+c"(rcx), [tmp]"=&r"(tmp) 120 : : "cc"); 121 report("repe/cmpsq (2)", 122 rcx == 3 && rsi == m1 + 104 && rdi == m3 + 104); 123 124 } 125 126 void test_cmps(void *mem) 127 { 128 unsigned char *m1 = mem, *m2 = mem + 1024; 129 unsigned char m3[1024]; 130 131 for (int i = 0; i < 100; ++i) 132 m1[i] = m2[i] = m3[i] = i; 133 for (int i = 100; i < 200; ++i) 134 m1[i] = (m3[i] = m2[i] = i) + 1; 135 test_cmps_one(m1, m3); 136 test_cmps_one(m1, m2); 137 } 138 139 void test_scas(void *mem) 140 { 141 bool z; 142 void *di; 143 144 *(ulong *)mem = 0x77665544332211; 145 146 di = mem; 147 asm ("scasb; setz %0" : "=rm"(z), "+D"(di) : "a"(0xff11)); 148 report("scasb match", di == mem + 1 && z); 149 150 di = mem; 151 asm ("scasb; setz %0" : "=rm"(z), "+D"(di) : "a"(0xff54)); 152 report("scasb mismatch", di == mem + 1 && !z); 153 154 di = mem; 155 asm ("scasw; setz %0" : "=rm"(z), "+D"(di) : "a"(0xff2211)); 156 report("scasw match", di == mem + 2 && z); 157 158 di = mem; 159 asm ("scasw; setz %0" : "=rm"(z), "+D"(di) : "a"(0xffdd11)); 160 report("scasw mismatch", di == mem + 2 && !z); 161 162 di = mem; 163 asm ("scasl; setz %0" : "=rm"(z), "+D"(di) : "a"(0xff44332211ul)); 164 report("scasd match", di == mem + 4 && z); 165 166 di = mem; 167 asm ("scasl; setz %0" : "=rm"(z), "+D"(di) : "a"(0x45332211)); 168 report("scasd mismatch", di == mem + 4 && !z); 169 170 di = mem; 171 asm ("scasq; setz %0" : "=rm"(z), "+D"(di) : "a"(0x77665544332211ul)); 172 report("scasq match", di == mem + 8 && z); 173 174 di = mem; 175 asm ("scasq; setz %0" : "=rm"(z), "+D"(di) : "a"(3)); 176 report("scasq mismatch", di == mem + 8 && !z); 177 } 178 179 void test_cr8(void) 180 { 181 unsigned long src, dst; 182 183 dst = 777; 184 src = 3; 185 asm volatile("mov %[src], %%cr8; mov %%cr8, %[dst]" 186 : [dst]"+r"(dst), [src]"+r"(src)); 187 report("mov %%cr8", dst == 3 && src == 3); 188 } 189 190 void test_push(void *mem) 191 { 192 unsigned long tmp; 193 unsigned long *stack_top = mem + 4096; 194 unsigned long *new_stack_top; 195 unsigned long memw = 0x123456789abcdeful; 196 197 memset(mem, 0x55, (void *)stack_top - mem); 198 199 asm volatile("mov %%rsp, %[tmp] \n\t" 200 "mov %[stack_top], %%rsp \n\t" 201 "pushq $-7 \n\t" 202 "pushq %[reg] \n\t" 203 "pushq (%[mem]) \n\t" 204 "pushq $-7070707 \n\t" 205 "mov %%rsp, %[new_stack_top] \n\t" 206 "mov %[tmp], %%rsp" 207 : [tmp]"=&r"(tmp), [new_stack_top]"=r"(new_stack_top) 208 : [stack_top]"r"(stack_top), 209 [reg]"r"(-17l), [mem]"r"(&memw) 210 : "memory"); 211 212 report("push $imm8", stack_top[-1] == -7ul); 213 report("push %%reg", stack_top[-2] == -17ul); 214 report("push mem", stack_top[-3] == 0x123456789abcdeful); 215 report("push $imm", stack_top[-4] == -7070707); 216 } 217 218 void test_pop(void *mem) 219 { 220 unsigned long tmp, tmp3, rsp, rbp; 221 unsigned long *stack_top = mem + 4096; 222 unsigned long memw = 0x123456789abcdeful; 223 static unsigned long tmp2; 224 225 memset(mem, 0x55, (void *)stack_top - mem); 226 227 asm volatile("pushq %[val] \n\t" 228 "popq (%[mem])" 229 : : [val]"m"(memw), [mem]"r"(mem) : "memory"); 230 report("pop mem", *(unsigned long *)mem == memw); 231 232 memw = 7 - memw; 233 asm volatile("mov %%rsp, %[tmp] \n\t" 234 "mov %[stack_top], %%rsp \n\t" 235 "pushq %[val] \n\t" 236 "popq %[tmp2] \n\t" 237 "mov %[tmp], %%rsp" 238 : [tmp]"=&r"(tmp), [tmp2]"=m"(tmp2) 239 : [val]"r"(memw), [stack_top]"r"(stack_top) 240 : "memory"); 241 report("pop mem (2)", tmp2 == memw); 242 243 memw = 129443 - memw; 244 asm volatile("mov %%rsp, %[tmp] \n\t" 245 "mov %[stack_top], %%rsp \n\t" 246 "pushq %[val] \n\t" 247 "popq %[tmp2] \n\t" 248 "mov %[tmp], %%rsp" 249 : [tmp]"=&r"(tmp), [tmp2]"=r"(tmp2) 250 : [val]"r"(memw), [stack_top]"r"(stack_top) 251 : "memory"); 252 report("pop reg", tmp2 == memw); 253 254 asm volatile("mov %%rsp, %[tmp] \n\t" 255 "mov %[stack_top], %%rsp \n\t" 256 "push $1f \n\t" 257 "ret \n\t" 258 "2: jmp 2b \n\t" 259 "1: mov %[tmp], %%rsp" 260 : [tmp]"=&r"(tmp) : [stack_top]"r"(stack_top) 261 : "memory"); 262 report("ret", 1); 263 264 stack_top[-1] = 0x778899; 265 asm volatile("mov %[stack_top], %%r8 \n\t" 266 "mov %%rsp, %%r9 \n\t" 267 "xchg %%rbp, %%r8 \n\t" 268 "leave \n\t" 269 "xchg %%rsp, %%r9 \n\t" 270 "xchg %%rbp, %%r8 \n\t" 271 "mov %%r9, %[tmp] \n\t" 272 "mov %%r8, %[tmp3]" 273 : [tmp]"=&r"(tmp), [tmp3]"=&r"(tmp3) : [stack_top]"r"(stack_top-1) 274 : "memory", "r8", "r9"); 275 report("leave", tmp == (ulong)stack_top && tmp3 == 0x778899); 276 277 rbp = 0xaa55aa55bb66bb66ULL; 278 rsp = (unsigned long)stack_top; 279 asm volatile("mov %[rsp], %%r8 \n\t" 280 "mov %[rbp], %%r9 \n\t" 281 "xchg %%rsp, %%r8 \n\t" 282 "xchg %%rbp, %%r9 \n\t" 283 "enter $0x1238, $0 \n\t" 284 "xchg %%rsp, %%r8 \n\t" 285 "xchg %%rbp, %%r9 \n\t" 286 "xchg %%r8, %[rsp] \n\t" 287 "xchg %%r9, %[rbp]" 288 : [rsp]"+a"(rsp), [rbp]"+b"(rbp) : : "memory", "r8", "r9"); 289 report("enter", 290 rsp == (unsigned long)stack_top - 8 - 0x1238 291 && rbp == (unsigned long)stack_top - 8 292 && stack_top[-1] == 0xaa55aa55bb66bb66ULL); 293 } 294 295 void test_ljmp(void *mem) 296 { 297 unsigned char *m = mem; 298 volatile int res = 1; 299 300 *(unsigned long**)m = &&jmpf; 301 asm volatile ("data16/mov %%cs, %0":"=m"(*(m + sizeof(unsigned long)))); 302 asm volatile ("rex64/ljmp *%0"::"m"(*m)); 303 res = 0; 304 jmpf: 305 report("ljmp", res); 306 } 307 308 void test_incdecnotneg(void *mem) 309 { 310 unsigned long *m = mem, v = 1234; 311 unsigned char *mb = mem, vb = 66; 312 313 *m = 0; 314 315 asm volatile ("incl %0":"+m"(*m)); 316 report("incl", *m == 1); 317 asm volatile ("decl %0":"+m"(*m)); 318 report("decl", *m == 0); 319 asm volatile ("incb %0":"+m"(*m)); 320 report("incb", *m == 1); 321 asm volatile ("decb %0":"+m"(*m)); 322 report("decb", *m == 0); 323 324 asm volatile ("lock incl %0":"+m"(*m)); 325 report("lock incl", *m == 1); 326 asm volatile ("lock decl %0":"+m"(*m)); 327 report("lock decl", *m == 0); 328 asm volatile ("lock incb %0":"+m"(*m)); 329 report("lock incb", *m == 1); 330 asm volatile ("lock decb %0":"+m"(*m)); 331 report("lock decb", *m == 0); 332 333 *m = v; 334 335 asm ("lock negq %0" : "+m"(*m)); v = -v; 336 report("lock negl", *m == v); 337 asm ("lock notq %0" : "+m"(*m)); v = ~v; 338 report("lock notl", *m == v); 339 340 *mb = vb; 341 342 asm ("lock negb %0" : "+m"(*mb)); vb = -vb; 343 report("lock negb", *mb == vb); 344 asm ("lock notb %0" : "+m"(*mb)); vb = ~vb; 345 report("lock notb", *mb == vb); 346 } 347 348 void test_smsw(uint64_t *h_mem) 349 { 350 char mem[16]; 351 unsigned short msw, msw_orig, *pmsw; 352 int i, zero; 353 354 msw_orig = read_cr0(); 355 356 asm("smsw %0" : "=r"(msw)); 357 report("smsw (1)", msw == msw_orig); 358 359 memset(mem, 0, 16); 360 pmsw = (void *)mem; 361 asm("smsw %0" : "=m"(pmsw[4])); 362 zero = 1; 363 for (i = 0; i < 8; ++i) 364 if (i != 4 && pmsw[i]) 365 zero = 0; 366 report("smsw (2)", msw == pmsw[4] && zero); 367 368 /* Trigger exit on smsw */ 369 *h_mem = 0x12345678abcdeful; 370 asm volatile("smsw %0" : "+m"(*h_mem)); 371 report("smsw (3)", msw == (unsigned short)*h_mem && 372 (*h_mem & ~0xfffful) == 0x12345678ab0000ul); 373 } 374 375 void test_lmsw(void) 376 { 377 char mem[16]; 378 unsigned short msw, *pmsw; 379 unsigned long cr0; 380 381 cr0 = read_cr0(); 382 383 msw = cr0 ^ 8; 384 asm("lmsw %0" : : "r"(msw)); 385 printf("before %lx after %lx\n", cr0, read_cr0()); 386 report("lmsw (1)", (cr0 ^ read_cr0()) == 8); 387 388 pmsw = (void *)mem; 389 *pmsw = cr0; 390 asm("lmsw %0" : : "m"(*pmsw)); 391 printf("before %lx after %lx\n", cr0, read_cr0()); 392 report("lmsw (2)", cr0 == read_cr0()); 393 394 /* lmsw can't clear cr0.pe */ 395 msw = (cr0 & ~1ul) ^ 4; /* change EM to force trap */ 396 asm("lmsw %0" : : "r"(msw)); 397 report("lmsw (3)", (cr0 ^ read_cr0()) == 4 && (cr0 & 1)); 398 399 /* back to normal */ 400 msw = cr0; 401 asm("lmsw %0" : : "r"(msw)); 402 } 403 404 void test_xchg(void *mem) 405 { 406 unsigned long *memq = mem; 407 unsigned long rax; 408 409 asm volatile("mov $0x123456789abcdef, %%rax\n\t" 410 "mov %%rax, (%[memq])\n\t" 411 "mov $0xfedcba9876543210, %%rax\n\t" 412 "xchg %%al, (%[memq])\n\t" 413 "mov %%rax, %[rax]\n\t" 414 : [rax]"=r"(rax) 415 : [memq]"r"(memq) 416 : "memory", "rax"); 417 report("xchg reg, r/m (1)", 418 rax == 0xfedcba98765432ef && *memq == 0x123456789abcd10); 419 420 asm volatile("mov $0x123456789abcdef, %%rax\n\t" 421 "mov %%rax, (%[memq])\n\t" 422 "mov $0xfedcba9876543210, %%rax\n\t" 423 "xchg %%ax, (%[memq])\n\t" 424 "mov %%rax, %[rax]\n\t" 425 : [rax]"=r"(rax) 426 : [memq]"r"(memq) 427 : "memory", "rax"); 428 report("xchg reg, r/m (2)", 429 rax == 0xfedcba987654cdef && *memq == 0x123456789ab3210); 430 431 asm volatile("mov $0x123456789abcdef, %%rax\n\t" 432 "mov %%rax, (%[memq])\n\t" 433 "mov $0xfedcba9876543210, %%rax\n\t" 434 "xchg %%eax, (%[memq])\n\t" 435 "mov %%rax, %[rax]\n\t" 436 : [rax]"=r"(rax) 437 : [memq]"r"(memq) 438 : "memory", "rax"); 439 report("xchg reg, r/m (3)", 440 rax == 0x89abcdef && *memq == 0x123456776543210); 441 442 asm volatile("mov $0x123456789abcdef, %%rax\n\t" 443 "mov %%rax, (%[memq])\n\t" 444 "mov $0xfedcba9876543210, %%rax\n\t" 445 "xchg %%rax, (%[memq])\n\t" 446 "mov %%rax, %[rax]\n\t" 447 : [rax]"=r"(rax) 448 : [memq]"r"(memq) 449 : "memory", "rax"); 450 report("xchg reg, r/m (4)", 451 rax == 0x123456789abcdef && *memq == 0xfedcba9876543210); 452 } 453 454 void test_xadd(void *mem) 455 { 456 unsigned long *memq = mem; 457 unsigned long rax; 458 459 asm volatile("mov $0x123456789abcdef, %%rax\n\t" 460 "mov %%rax, (%[memq])\n\t" 461 "mov $0xfedcba9876543210, %%rax\n\t" 462 "xadd %%al, (%[memq])\n\t" 463 "mov %%rax, %[rax]\n\t" 464 : [rax]"=r"(rax) 465 : [memq]"r"(memq) 466 : "memory", "rax"); 467 report("xadd reg, r/m (1)", 468 rax == 0xfedcba98765432ef && *memq == 0x123456789abcdff); 469 470 asm volatile("mov $0x123456789abcdef, %%rax\n\t" 471 "mov %%rax, (%[memq])\n\t" 472 "mov $0xfedcba9876543210, %%rax\n\t" 473 "xadd %%ax, (%[memq])\n\t" 474 "mov %%rax, %[rax]\n\t" 475 : [rax]"=r"(rax) 476 : [memq]"r"(memq) 477 : "memory", "rax"); 478 report("xadd reg, r/m (2)", 479 rax == 0xfedcba987654cdef && *memq == 0x123456789abffff); 480 481 asm volatile("mov $0x123456789abcdef, %%rax\n\t" 482 "mov %%rax, (%[memq])\n\t" 483 "mov $0xfedcba9876543210, %%rax\n\t" 484 "xadd %%eax, (%[memq])\n\t" 485 "mov %%rax, %[rax]\n\t" 486 : [rax]"=r"(rax) 487 : [memq]"r"(memq) 488 : "memory", "rax"); 489 report("xadd reg, r/m (3)", 490 rax == 0x89abcdef && *memq == 0x1234567ffffffff); 491 492 asm volatile("mov $0x123456789abcdef, %%rax\n\t" 493 "mov %%rax, (%[memq])\n\t" 494 "mov $0xfedcba9876543210, %%rax\n\t" 495 "xadd %%rax, (%[memq])\n\t" 496 "mov %%rax, %[rax]\n\t" 497 : [rax]"=r"(rax) 498 : [memq]"r"(memq) 499 : "memory", "rax"); 500 report("xadd reg, r/m (4)", 501 rax == 0x123456789abcdef && *memq == 0xffffffffffffffff); 502 } 503 504 void test_btc(void *mem) 505 { 506 unsigned int *a = mem; 507 508 memset(mem, 0, 4 * sizeof(unsigned int)); 509 510 asm ("btcl $32, %0" :: "m"(a[0]) : "memory"); 511 asm ("btcl $1, %0" :: "m"(a[1]) : "memory"); 512 asm ("btcl %1, %0" :: "m"(a[0]), "r"(66) : "memory"); 513 report("btcl imm8, r/m", a[0] == 1 && a[1] == 2 && a[2] == 4); 514 515 asm ("btcl %1, %0" :: "m"(a[3]), "r"(-1) : "memory"); 516 report("btcl reg, r/m", a[0] == 1 && a[1] == 2 && a[2] == 0x80000004); 517 518 asm ("btcq %1, %0" : : "m"(a[2]), "r"(-1l) : "memory"); 519 report("btcq reg, r/m", a[0] == 1 && a[1] == 0x80000002 && 520 a[2] == 0x80000004 && a[3] == 0); 521 } 522 523 void test_bsfbsr(void *mem) 524 { 525 unsigned long rax, *memq = mem; 526 unsigned eax, *meml = mem; 527 unsigned short ax, *memw = mem; 528 unsigned char z; 529 530 *memw = 0xc000; 531 asm("bsfw %[mem], %[a]" : [a]"=a"(ax) : [mem]"m"(*memw)); 532 report("bsfw r/m, reg", ax == 14); 533 534 *meml = 0xc0000000; 535 asm("bsfl %[mem], %[a]" : [a]"=a"(eax) : [mem]"m"(*meml)); 536 report("bsfl r/m, reg", eax == 30); 537 538 *memq = 0xc00000000000; 539 asm("bsfq %[mem], %[a]" : [a]"=a"(rax) : [mem]"m"(*memq)); 540 report("bsfq r/m, reg", rax == 46); 541 542 *memq = 0; 543 asm("bsfq %[mem], %[a]; setz %[z]" 544 : [a]"=a"(rax), [z]"=rm"(z) : [mem]"m"(*memq)); 545 report("bsfq r/m, reg", z == 1); 546 547 *memw = 0xc000; 548 asm("bsrw %[mem], %[a]" : [a]"=a"(ax) : [mem]"m"(*memw)); 549 report("bsrw r/m, reg", ax == 15); 550 551 *meml = 0xc0000000; 552 asm("bsrl %[mem], %[a]" : [a]"=a"(eax) : [mem]"m"(*meml)); 553 report("bsrl r/m, reg", eax == 31); 554 555 *memq = 0xc00000000000; 556 asm("bsrq %[mem], %[a]" : [a]"=a"(rax) : [mem]"m"(*memq)); 557 report("bsrq r/m, reg", rax == 47); 558 559 *memq = 0; 560 asm("bsrq %[mem], %[a]; setz %[z]" 561 : [a]"=a"(rax), [z]"=rm"(z) : [mem]"m"(*memq)); 562 report("bsrq r/m, reg", z == 1); 563 } 564 565 static void test_imul(ulong *mem) 566 { 567 ulong a; 568 569 *mem = 51; a = 0x1234567812345678UL; 570 asm ("imulw %1, %%ax" : "+a"(a) : "m"(*mem)); 571 report("imul ax, mem", a == 0x12345678123439e8); 572 573 *mem = 51; a = 0x1234567812345678UL; 574 asm ("imull %1, %%eax" : "+a"(a) : "m"(*mem)); 575 report("imul eax, mem", a == 0xa06d39e8); 576 577 *mem = 51; a = 0x1234567812345678UL; 578 asm ("imulq %1, %%rax" : "+a"(a) : "m"(*mem)); 579 report("imul rax, mem", a == 0xA06D39EBA06D39E8UL); 580 581 *mem = 0x1234567812345678UL; a = 0x8765432187654321L; 582 asm ("imulw $51, %1, %%ax" : "+a"(a) : "m"(*mem)); 583 report("imul ax, mem, imm8", a == 0x87654321876539e8); 584 585 *mem = 0x1234567812345678UL; 586 asm ("imull $51, %1, %%eax" : "+a"(a) : "m"(*mem)); 587 report("imul eax, mem, imm8", a == 0xa06d39e8); 588 589 *mem = 0x1234567812345678UL; 590 asm ("imulq $51, %1, %%rax" : "+a"(a) : "m"(*mem)); 591 report("imul rax, mem, imm8", a == 0xA06D39EBA06D39E8UL); 592 593 *mem = 0x1234567812345678UL; a = 0x8765432187654321L; 594 asm ("imulw $311, %1, %%ax" : "+a"(a) : "m"(*mem)); 595 report("imul ax, mem, imm", a == 0x8765432187650bc8); 596 597 *mem = 0x1234567812345678UL; 598 asm ("imull $311, %1, %%eax" : "+a"(a) : "m"(*mem)); 599 report("imul eax, mem, imm", a == 0x1d950bc8); 600 601 *mem = 0x1234567812345678UL; 602 asm ("imulq $311, %1, %%rax" : "+a"(a) : "m"(*mem)); 603 report("imul rax, mem, imm", a == 0x1D950BDE1D950BC8L); 604 } 605 606 static void test_muldiv(long *mem) 607 { 608 long a, d, aa, dd; 609 u8 ex = 1; 610 611 *mem = 0; a = 1; d = 2; 612 asm (ASM_TRY("1f") "divq %3; movb $0, %2; 1:" 613 : "+a"(a), "+d"(d), "+q"(ex) : "m"(*mem)); 614 report("divq (fault)", a == 1 && d == 2 && ex); 615 616 *mem = 987654321098765UL; a = 123456789012345UL; d = 123456789012345UL; 617 asm (ASM_TRY("1f") "divq %3; movb $0, %2; 1:" 618 : "+a"(a), "+d"(d), "+q"(ex) : "m"(*mem)); 619 report("divq (1)", 620 a == 0x1ffffffb1b963b33ul && d == 0x273ba4384ede2ul && !ex); 621 aa = 0x1111111111111111; dd = 0x2222222222222222; 622 *mem = 0x3333333333333333; a = aa; d = dd; 623 asm("mulb %2" : "+a"(a), "+d"(d) : "m"(*mem)); 624 report("mulb mem", a == 0x1111111111110363 && d == dd); 625 *mem = 0x3333333333333333; a = aa; d = dd; 626 asm("mulw %2" : "+a"(a), "+d"(d) : "m"(*mem)); 627 report("mulw mem", a == 0x111111111111c963 && d == 0x2222222222220369); 628 *mem = 0x3333333333333333; a = aa; d = dd; 629 asm("mull %2" : "+a"(a), "+d"(d) : "m"(*mem)); 630 report("mull mem", a == 0x962fc963 && d == 0x369d036); 631 *mem = 0x3333333333333333; a = aa; d = dd; 632 asm("mulq %2" : "+a"(a), "+d"(d) : "m"(*mem)); 633 report("mulq mem", a == 0x2fc962fc962fc963 && d == 0x369d0369d0369d0); 634 } 635 636 typedef unsigned __attribute__((vector_size(16))) sse128; 637 638 typedef union { 639 sse128 sse; 640 unsigned u[4]; 641 } sse_union; 642 643 static bool sseeq(sse_union *v1, sse_union *v2) 644 { 645 bool ok = true; 646 int i; 647 648 for (i = 0; i < 4; ++i) { 649 ok &= v1->u[i] == v2->u[i]; 650 } 651 652 return ok; 653 } 654 655 static void test_sse(sse_union *mem) 656 { 657 sse_union v; 658 659 write_cr0(read_cr0() & ~6); /* EM, TS */ 660 write_cr4(read_cr4() | 0x200); /* OSFXSR */ 661 v.u[0] = 1; v.u[1] = 2; v.u[2] = 3; v.u[3] = 4; 662 asm("movdqu %1, %0" : "=m"(*mem) : "x"(v.sse)); 663 report("movdqu (read)", sseeq(&v, mem)); 664 mem->u[0] = 5; mem->u[1] = 6; mem->u[2] = 7; mem->u[3] = 8; 665 asm("movdqu %1, %0" : "=x"(v.sse) : "m"(*mem)); 666 report("movdqu (write)", sseeq(mem, &v)); 667 668 v.u[0] = 1; v.u[1] = 2; v.u[2] = 3; v.u[3] = 4; 669 asm("movaps %1, %0" : "=m"(*mem) : "x"(v.sse)); 670 report("movaps (read)", sseeq(mem, &v)); 671 mem->u[0] = 5; mem->u[1] = 6; mem->u[2] = 7; mem->u[3] = 8; 672 asm("movaps %1, %0" : "=x"(v.sse) : "m"(*mem)); 673 report("movaps (write)", sseeq(&v, mem)); 674 675 v.u[0] = 1; v.u[1] = 2; v.u[2] = 3; v.u[3] = 4; 676 asm("movapd %1, %0" : "=m"(*mem) : "x"(v.sse)); 677 report("movapd (read)", sseeq(mem, &v)); 678 mem->u[0] = 5; mem->u[1] = 6; mem->u[2] = 7; mem->u[3] = 8; 679 asm("movapd %1, %0" : "=x"(v.sse) : "m"(*mem)); 680 report("movapd (write)", sseeq(&v, mem)); 681 } 682 683 static void test_mmx(uint64_t *mem) 684 { 685 uint64_t v; 686 687 write_cr0(read_cr0() & ~6); /* EM, TS */ 688 asm volatile("fninit"); 689 v = 0x0102030405060708ULL; 690 asm("movq %1, %0" : "=m"(*mem) : "y"(v)); 691 report("movq (mmx, read)", v == *mem); 692 *mem = 0x8070605040302010ull; 693 asm("movq %1, %0" : "=y"(v) : "m"(*mem)); 694 report("movq (mmx, write)", v == *mem); 695 } 696 697 static void test_rip_relative(unsigned *mem, char *insn_ram) 698 { 699 /* movb $1, mem+2(%rip) */ 700 insn_ram[0] = 0xc6; 701 insn_ram[1] = 0x05; 702 *(unsigned *)&insn_ram[2] = 2 + (char *)mem - (insn_ram + 7); 703 insn_ram[6] = 0x01; 704 /* ret */ 705 insn_ram[7] = 0xc3; 706 707 *mem = 0; 708 asm("callq *%1" : "+m"(*mem) : "r"(insn_ram)); 709 report("movb $imm, 0(%%rip)", *mem == 0x10000); 710 } 711 712 static void test_shld_shrd(u32 *mem) 713 { 714 *mem = 0x12345678; 715 asm("shld %2, %1, %0" : "+m"(*mem) : "r"(0xaaaaaaaaU), "c"((u8)3)); 716 report("shld (cl)", *mem == ((0x12345678 << 3) | 5)); 717 *mem = 0x12345678; 718 asm("shrd %2, %1, %0" : "+m"(*mem) : "r"(0x55555555U), "c"((u8)3)); 719 report("shrd (cl)", *mem == ((0x12345678 >> 3) | (5u << 29))); 720 } 721 722 static void test_cmov(u32 *mem) 723 { 724 u64 val; 725 *mem = 0xabcdef12u; 726 asm ("movq $0x1234567812345678, %%rax\n\t" 727 "cmpl %%eax, %%eax\n\t" 728 "cmovnel (%[mem]), %%eax\n\t" 729 "movq %%rax, %[val]\n\t" 730 : [val]"=r"(val) : [mem]"r"(mem) : "%rax", "cc"); 731 report("cmovnel", val == 0x12345678ul); 732 } 733 734 #define INSN_XCHG_ALL \ 735 "xchg %rax, 0+save \n\t" \ 736 "xchg %rbx, 8+save \n\t" \ 737 "xchg %rcx, 16+save \n\t" \ 738 "xchg %rdx, 24+save \n\t" \ 739 "xchg %rsi, 32+save \n\t" \ 740 "xchg %rdi, 40+save \n\t" \ 741 "xchg %rsp, 48+save \n\t" \ 742 "xchg %rbp, 56+save \n\t" \ 743 "xchg %r8, 64+save \n\t" \ 744 "xchg %r9, 72+save \n\t" \ 745 "xchg %r10, 80+save \n\t" \ 746 "xchg %r11, 88+save \n\t" \ 747 "xchg %r12, 96+save \n\t" \ 748 "xchg %r13, 104+save \n\t" \ 749 "xchg %r14, 112+save \n\t" \ 750 "xchg %r15, 120+save \n\t" 751 752 asm( 753 ".align 4096\n\t" 754 "insn_page:\n\t" 755 "ret\n\t" 756 "pushf\n\t" 757 "push 136+save \n\t" 758 "popf \n\t" 759 INSN_XCHG_ALL 760 "test_insn:\n\t" 761 "in (%dx),%al\n\t" 762 ".skip 31, 0x90\n\t" 763 "test_insn_end:\n\t" 764 INSN_XCHG_ALL 765 "pushf \n\t" 766 "pop 136+save \n\t" 767 "popf \n\t" 768 "ret \n\t" 769 "insn_page_end:\n\t" 770 ".align 4096\n\t" 771 ); 772 773 #define MK_INSN(name, str) \ 774 asm ( \ 775 ".pushsection .data.insn \n\t" \ 776 "insn_" #name ": \n\t" \ 777 ".quad 1001f, 1002f - 1001f \n\t" \ 778 ".popsection \n\t" \ 779 ".pushsection .text.insn, \"ax\" \n\t" \ 780 "1001: \n\t" \ 781 "insn_code_" #name ": " str " \n\t" \ 782 "1002: \n\t" \ 783 ".popsection" \ 784 ); \ 785 extern struct insn_desc insn_##name; 786 787 static void trap_emulator(uint64_t *mem, void *alt_insn_page, 788 struct insn_desc *alt_insn) 789 { 790 ulong *cr3 = (ulong *)read_cr3(); 791 void *insn_ram; 792 extern u8 insn_page[], test_insn[]; 793 794 insn_ram = vmap(virt_to_phys(insn_page), 4096); 795 memcpy(alt_insn_page, insn_page, 4096); 796 memcpy(alt_insn_page + (test_insn - insn_page), 797 (void *)(alt_insn->ptr), alt_insn->len); 798 save = inregs; 799 800 /* Load the code TLB with insn_page, but point the page tables at 801 alt_insn_page (and keep the data TLB clear, for AMD decode assist). 802 This will make the CPU trap on the insn_page instruction but the 803 hypervisor will see alt_insn_page. */ 804 install_page(cr3, virt_to_phys(insn_page), insn_ram); 805 invlpg(insn_ram); 806 /* Load code TLB */ 807 asm volatile("call *%0" : : "r"(insn_ram)); 808 install_page(cr3, virt_to_phys(alt_insn_page), insn_ram); 809 /* Trap, let hypervisor emulate at alt_insn_page */ 810 asm volatile("call *%0": : "r"(insn_ram+1)); 811 812 outregs = save; 813 } 814 815 static unsigned long rip_advance; 816 817 static void advance_rip_and_note_exception(struct ex_regs *regs) 818 { 819 ++exceptions; 820 regs->rip += rip_advance; 821 } 822 823 static void test_mmx_movq_mf(uint64_t *mem, uint8_t *insn_page, 824 uint8_t *alt_insn_page, void *insn_ram) 825 { 826 uint16_t fcw = 0; /* all exceptions unmasked */ 827 /* movq %mm0, (%rax) */ 828 void *stack = alloc_page(); 829 830 write_cr0(read_cr0() & ~6); /* TS, EM */ 831 exceptions = 0; 832 handle_exception(MF_VECTOR, advance_rip_and_note_exception); 833 asm volatile("fninit; fldcw %0" : : "m"(fcw)); 834 asm volatile("fldz; fldz; fdivp"); /* generate exception */ 835 836 MK_INSN(mmx_movq_mf, "movq %mm0, (%rax) \n\t"); 837 rip_advance = insn_mmx_movq_mf.len; 838 inregs = (struct regs){ .rsp=(u64)stack+1024 }; 839 trap_emulator(mem, alt_insn_page, &insn_mmx_movq_mf); 840 /* exit MMX mode */ 841 asm volatile("fnclex; emms"); 842 report("movq mmx generates #MF", exceptions == 1); 843 handle_exception(MF_VECTOR, 0); 844 } 845 846 static void test_jmp_noncanonical(uint64_t *mem) 847 { 848 extern char nc_jmp_start, nc_jmp_end; 849 850 *mem = 0x1111111111111111ul; 851 852 exceptions = 0; 853 rip_advance = &nc_jmp_end - &nc_jmp_start; 854 handle_exception(GP_VECTOR, advance_rip_and_note_exception); 855 asm volatile ("nc_jmp_start: jmp *%0; nc_jmp_end:" : : "m"(*mem)); 856 report("jump to non-canonical address", exceptions == 1); 857 handle_exception(GP_VECTOR, 0); 858 } 859 860 static void test_movabs(uint64_t *mem, uint8_t *insn_page, 861 uint8_t *alt_insn_page, void *insn_ram) 862 { 863 /* mov $0x9090909090909090, %rcx */ 864 MK_INSN(movabs, "mov $0x9090909090909090, %rcx\n\t"); 865 inregs = (struct regs){ 0 }; 866 trap_emulator(mem, alt_insn_page, &insn_movabs); 867 report("64-bit mov imm2", outregs.rcx == 0x9090909090909090); 868 } 869 870 static void test_smsw_reg(uint64_t *mem, uint8_t *insn_page, 871 uint8_t *alt_insn_page, void *insn_ram) 872 { 873 unsigned long cr0 = read_cr0(); 874 inregs = (struct regs){ .rax = 0x1234567890abcdeful }; 875 876 MK_INSN(smsww, "smsww %ax\n\t"); 877 trap_emulator(mem, alt_insn_page, &insn_smsww); 878 report("16-bit smsw reg", (u16)outregs.rax == (u16)cr0 && 879 outregs.rax >> 16 == inregs.rax >> 16); 880 881 MK_INSN(smswl, "smswl %eax\n\t"); 882 trap_emulator(mem, alt_insn_page, &insn_smswl); 883 report("32-bit smsw reg", outregs.rax == (u32)cr0); 884 885 MK_INSN(smswq, "smswq %rax\n\t"); 886 trap_emulator(mem, alt_insn_page, &insn_smswq); 887 report("64-bit smsw reg", outregs.rax == cr0); 888 } 889 890 static void test_nop(uint64_t *mem, uint8_t *insn_page, 891 uint8_t *alt_insn_page, void *insn_ram) 892 { 893 inregs = (struct regs){ .rax = 0x1234567890abcdeful }; 894 MK_INSN(nop, "nop\n\t"); 895 trap_emulator(mem, alt_insn_page, &insn_nop); 896 report("nop", outregs.rax == inregs.rax); 897 } 898 899 static void test_mov_dr(uint64_t *mem, uint8_t *insn_page, 900 uint8_t *alt_insn_page, void *insn_ram) 901 { 902 bool rtm_support = cpuid(7).b & (1 << 11); 903 unsigned long dr6_fixed_1 = rtm_support ? 0xfffe0ff0ul : 0xffff0ff0ul; 904 inregs = (struct regs){ .rax = 0 }; 905 MK_INSN(mov_to_dr6, "movq %rax, %dr6\n\t"); 906 trap_emulator(mem, alt_insn_page, &insn_mov_to_dr6); 907 MK_INSN(mov_from_dr6, "movq %dr6, %rax\n\t"); 908 trap_emulator(mem, alt_insn_page, &insn_mov_from_dr6); 909 report("mov_dr6", outregs.rax == dr6_fixed_1); 910 } 911 912 static void test_push16(uint64_t *mem) 913 { 914 uint64_t rsp1, rsp2; 915 uint16_t r; 916 917 asm volatile ( "movq %%rsp, %[rsp1]\n\t" 918 "pushw %[v]\n\t" 919 "popw %[r]\n\t" 920 "movq %%rsp, %[rsp2]\n\t" 921 "movq %[rsp1], %%rsp\n\t" : 922 [rsp1]"=r"(rsp1), [rsp2]"=r"(rsp2), [r]"=r"(r) 923 : [v]"m"(*mem) : "memory"); 924 report("push16", rsp1 == rsp2); 925 } 926 927 static void test_crosspage_mmio(volatile uint8_t *mem) 928 { 929 volatile uint16_t w, *pw; 930 931 pw = (volatile uint16_t *)&mem[4095]; 932 mem[4095] = 0x99; 933 mem[4096] = 0x77; 934 asm volatile("mov %1, %0" : "=r"(w) : "m"(*pw) : "memory"); 935 report("cross-page mmio read", w == 0x7799); 936 asm volatile("mov %1, %0" : "=m"(*pw) : "r"((uint16_t)0x88aa)); 937 report("cross-page mmio write", mem[4095] == 0xaa && mem[4096] == 0x88); 938 } 939 940 static void test_string_io_mmio(volatile uint8_t *mem) 941 { 942 /* Cross MMIO pages.*/ 943 volatile uint8_t *mmio = mem + 4032; 944 945 asm volatile("outw %%ax, %%dx \n\t" : : "a"(0x9999), "d"(TESTDEV_IO_PORT)); 946 947 asm volatile ("cld; rep insb" : : "d" (TESTDEV_IO_PORT), "D" (mmio), "c" (1024)); 948 949 report("string_io_mmio", mmio[1023] == 0x99); 950 } 951 952 /* kvm doesn't allow lidt/lgdt from mmio, so the test is disabled */ 953 #if 0 954 static void test_lgdt_lidt(volatile uint8_t *mem) 955 { 956 struct descriptor_table_ptr orig, fresh = {}; 957 958 sgdt(&orig); 959 *(struct descriptor_table_ptr *)mem = (struct descriptor_table_ptr) { 960 .limit = 0xf234, 961 .base = 0x12345678abcd, 962 }; 963 cli(); 964 asm volatile("lgdt %0" : : "m"(*(struct descriptor_table_ptr *)mem)); 965 sgdt(&fresh); 966 lgdt(&orig); 967 sti(); 968 report("lgdt (long address)", orig.limit == fresh.limit && orig.base == fresh.base); 969 970 sidt(&orig); 971 *(struct descriptor_table_ptr *)mem = (struct descriptor_table_ptr) { 972 .limit = 0x432f, 973 .base = 0xdbca87654321, 974 }; 975 cli(); 976 asm volatile("lidt %0" : : "m"(*(struct descriptor_table_ptr *)mem)); 977 sidt(&fresh); 978 lidt(&orig); 979 sti(); 980 report("lidt (long address)", orig.limit == fresh.limit && orig.base == fresh.base); 981 } 982 #endif 983 984 static void ss_bad_rpl(struct ex_regs *regs) 985 { 986 extern char ss_bad_rpl_cont; 987 988 ++exceptions; 989 regs->rip = (ulong)&ss_bad_rpl_cont; 990 } 991 992 static void test_sreg(volatile uint16_t *mem) 993 { 994 u16 ss = read_ss(); 995 996 // check for null segment load 997 *mem = 0; 998 asm volatile("mov %0, %%ss" : : "m"(*mem)); 999 report("mov null, %%ss", read_ss() == 0); 1000 1001 // check for exception when ss.rpl != cpl on null segment load 1002 exceptions = 0; 1003 handle_exception(GP_VECTOR, ss_bad_rpl); 1004 *mem = 3; 1005 asm volatile("mov %0, %%ss; ss_bad_rpl_cont:" : : "m"(*mem)); 1006 report("mov null, %%ss (with ss.rpl != cpl)", exceptions == 1 && read_ss() == 0); 1007 handle_exception(GP_VECTOR, 0); 1008 write_ss(ss); 1009 } 1010 1011 /* Broken emulation causes triple fault, which skips the other tests. */ 1012 #if 0 1013 static void test_lldt(volatile uint16_t *mem) 1014 { 1015 u64 gdt[] = { 0, /* null descriptor */ 1016 #ifdef __X86_64__ 1017 0, /* ldt descriptor is 16 bytes in long mode */ 1018 #endif 1019 0x0000f82000000ffffull /* ldt descriptor */ }; 1020 struct descriptor_table_ptr gdt_ptr = { .limit = sizeof(gdt) - 1, 1021 .base = (ulong)&gdt }; 1022 struct descriptor_table_ptr orig_gdt; 1023 1024 cli(); 1025 sgdt(&orig_gdt); 1026 lgdt(&gdt_ptr); 1027 *mem = 0x8; 1028 asm volatile("lldt %0" : : "m"(*mem)); 1029 lgdt(&orig_gdt); 1030 sti(); 1031 report("lldt", sldt() == *mem); 1032 } 1033 #endif 1034 1035 static void test_ltr(volatile uint16_t *mem) 1036 { 1037 struct descriptor_table_ptr gdt_ptr; 1038 uint64_t *gdt, *trp; 1039 uint16_t tr = str(); 1040 uint64_t busy_mask = (uint64_t)1 << 41; 1041 1042 sgdt(&gdt_ptr); 1043 gdt = (uint64_t *)gdt_ptr.base; 1044 trp = &gdt[tr >> 3]; 1045 *trp &= ~busy_mask; 1046 *mem = tr; 1047 asm volatile("ltr %0" : : "m"(*mem) : "memory"); 1048 report("ltr", str() == tr && (*trp & busy_mask)); 1049 } 1050 1051 static void test_simplealu(u32 *mem) 1052 { 1053 *mem = 0x1234; 1054 asm("or %1, %0" : "+m"(*mem) : "r"(0x8001)); 1055 report("or", *mem == 0x9235); 1056 asm("add %1, %0" : "+m"(*mem) : "r"(2)); 1057 report("add", *mem == 0x9237); 1058 asm("xor %1, %0" : "+m"(*mem) : "r"(0x1111)); 1059 report("xor", *mem == 0x8326); 1060 asm("sub %1, %0" : "+m"(*mem) : "r"(0x26)); 1061 report("sub", *mem == 0x8300); 1062 asm("clc; adc %1, %0" : "+m"(*mem) : "r"(0x100)); 1063 report("adc(0)", *mem == 0x8400); 1064 asm("stc; adc %1, %0" : "+m"(*mem) : "r"(0x100)); 1065 report("adc(0)", *mem == 0x8501); 1066 asm("clc; sbb %1, %0" : "+m"(*mem) : "r"(0)); 1067 report("sbb(0)", *mem == 0x8501); 1068 asm("stc; sbb %1, %0" : "+m"(*mem) : "r"(0)); 1069 report("sbb(1)", *mem == 0x8500); 1070 asm("and %1, %0" : "+m"(*mem) : "r"(0xfe77)); 1071 report("and", *mem == 0x8400); 1072 asm("test %1, %0" : "+m"(*mem) : "r"(0xf000)); 1073 report("test", *mem == 0x8400); 1074 } 1075 1076 static void illegal_movbe_handler(struct ex_regs *regs) 1077 { 1078 extern char bad_movbe_cont; 1079 1080 ++exceptions; 1081 regs->rip = (ulong)&bad_movbe_cont; 1082 } 1083 1084 static void test_illegal_movbe(void) 1085 { 1086 if (!(cpuid(1).c & (1 << 22))) { 1087 report_skip("illegal movbe"); 1088 return; 1089 } 1090 1091 exceptions = 0; 1092 handle_exception(UD_VECTOR, illegal_movbe_handler); 1093 asm volatile(".byte 0x0f; .byte 0x38; .byte 0xf0; .byte 0xc0;\n\t" 1094 " bad_movbe_cont:" : : : "rax"); 1095 report("illegal movbe", exceptions == 1); 1096 handle_exception(UD_VECTOR, 0); 1097 } 1098 1099 int main() 1100 { 1101 void *mem; 1102 void *insn_page, *alt_insn_page; 1103 void *insn_ram; 1104 unsigned long t1, t2; 1105 1106 setup_vm(); 1107 setup_idt(); 1108 mem = alloc_vpages(2); 1109 install_page((void *)read_cr3(), IORAM_BASE_PHYS, mem); 1110 // install the page twice to test cross-page mmio 1111 install_page((void *)read_cr3(), IORAM_BASE_PHYS, mem + 4096); 1112 insn_page = alloc_page(); 1113 alt_insn_page = alloc_page(); 1114 insn_ram = vmap(virt_to_phys(insn_page), 4096); 1115 1116 // test mov reg, r/m and mov r/m, reg 1117 t1 = 0x123456789abcdef; 1118 asm volatile("mov %[t1], (%[mem]) \n\t" 1119 "mov (%[mem]), %[t2]" 1120 : [t2]"=r"(t2) 1121 : [t1]"r"(t1), [mem]"r"(mem) 1122 : "memory"); 1123 report("mov reg, r/m (1)", t2 == 0x123456789abcdef); 1124 1125 test_simplealu(mem); 1126 test_cmps(mem); 1127 test_scas(mem); 1128 1129 test_push(mem); 1130 test_pop(mem); 1131 1132 test_xchg(mem); 1133 test_xadd(mem); 1134 1135 test_cr8(); 1136 1137 test_smsw(mem); 1138 test_lmsw(); 1139 test_ljmp(mem); 1140 test_stringio(); 1141 test_incdecnotneg(mem); 1142 test_btc(mem); 1143 test_bsfbsr(mem); 1144 test_imul(mem); 1145 test_muldiv(mem); 1146 test_sse(mem); 1147 test_mmx(mem); 1148 test_rip_relative(mem, insn_ram); 1149 test_shld_shrd(mem); 1150 //test_lgdt_lidt(mem); 1151 test_sreg(mem); 1152 //test_lldt(mem); 1153 test_ltr(mem); 1154 test_cmov(mem); 1155 1156 test_mmx_movq_mf(mem, insn_page, alt_insn_page, insn_ram); 1157 test_movabs(mem, insn_page, alt_insn_page, insn_ram); 1158 test_smsw_reg(mem, insn_page, alt_insn_page, insn_ram); 1159 test_nop(mem, insn_page, alt_insn_page, insn_ram); 1160 test_mov_dr(mem, insn_page, alt_insn_page, insn_ram); 1161 test_push16(mem); 1162 test_crosspage_mmio(mem); 1163 1164 test_string_io_mmio(mem); 1165 1166 test_jmp_noncanonical(mem); 1167 test_illegal_movbe(); 1168 1169 return report_summary(); 1170 } 1171