1 2 #include "libcflat.h" 3 #include "desc.h" 4 #include "processor.h" 5 6 #define smp_id() 0 7 8 #define true 1 9 #define false 0 10 11 static _Bool verbose = false; 12 13 typedef unsigned long pt_element_t; 14 static int cpuid_7_ebx; 15 static int cpuid_7_ecx; 16 static int invalid_mask; 17 18 #define PAGE_SIZE ((pt_element_t)4096) 19 #define PAGE_MASK (~(PAGE_SIZE-1)) 20 21 #define PT_BASE_ADDR_MASK ((pt_element_t)((((pt_element_t)1 << 40) - 1) & PAGE_MASK)) 22 #define PT_PSE_BASE_ADDR_MASK (PT_BASE_ADDR_MASK & ~(1ull << 21)) 23 24 #define PT_PRESENT_MASK ((pt_element_t)1 << 0) 25 #define PT_WRITABLE_MASK ((pt_element_t)1 << 1) 26 #define PT_USER_MASK ((pt_element_t)1 << 2) 27 #define PT_ACCESSED_MASK ((pt_element_t)1 << 5) 28 #define PT_DIRTY_MASK ((pt_element_t)1 << 6) 29 #define PT_PSE_MASK ((pt_element_t)1 << 7) 30 #define PT_NX_MASK ((pt_element_t)1 << 63) 31 32 #define CR0_WP_MASK (1UL << 16) 33 #define CR4_SMEP_MASK (1UL << 20) 34 35 #define PFERR_PRESENT_MASK (1U << 0) 36 #define PFERR_WRITE_MASK (1U << 1) 37 #define PFERR_USER_MASK (1U << 2) 38 #define PFERR_RESERVED_MASK (1U << 3) 39 #define PFERR_FETCH_MASK (1U << 4) 40 #define PFERR_PK_MASK (1U << 5) 41 42 #define MSR_EFER 0xc0000080 43 #define EFER_NX_MASK (1ull << 11) 44 45 #define PT_INDEX(address, level) \ 46 ((address) >> (12 + ((level)-1) * 9)) & 511 47 48 /* 49 * page table access check tests 50 */ 51 52 enum { 53 AC_PTE_PRESENT_BIT, 54 AC_PTE_WRITABLE_BIT, 55 AC_PTE_USER_BIT, 56 AC_PTE_ACCESSED_BIT, 57 AC_PTE_DIRTY_BIT, 58 AC_PTE_NX_BIT, 59 AC_PTE_BIT51_BIT, 60 61 AC_PDE_PRESENT_BIT, 62 AC_PDE_WRITABLE_BIT, 63 AC_PDE_USER_BIT, 64 AC_PDE_ACCESSED_BIT, 65 AC_PDE_DIRTY_BIT, 66 AC_PDE_PSE_BIT, 67 AC_PDE_NX_BIT, 68 AC_PDE_BIT51_BIT, 69 AC_PDE_BIT13_BIT, 70 71 AC_PKU_AD_BIT, 72 AC_PKU_WD_BIT, 73 AC_PKU_PKEY_BIT, 74 75 AC_ACCESS_USER_BIT, 76 AC_ACCESS_WRITE_BIT, 77 AC_ACCESS_FETCH_BIT, 78 AC_ACCESS_TWICE_BIT, 79 80 AC_CPU_EFER_NX_BIT, 81 AC_CPU_CR0_WP_BIT, 82 AC_CPU_CR4_SMEP_BIT, 83 AC_CPU_CR4_PKE_BIT, 84 85 NR_AC_FLAGS 86 }; 87 88 #define AC_PTE_PRESENT_MASK (1 << AC_PTE_PRESENT_BIT) 89 #define AC_PTE_WRITABLE_MASK (1 << AC_PTE_WRITABLE_BIT) 90 #define AC_PTE_USER_MASK (1 << AC_PTE_USER_BIT) 91 #define AC_PTE_ACCESSED_MASK (1 << AC_PTE_ACCESSED_BIT) 92 #define AC_PTE_DIRTY_MASK (1 << AC_PTE_DIRTY_BIT) 93 #define AC_PTE_NX_MASK (1 << AC_PTE_NX_BIT) 94 #define AC_PTE_BIT51_MASK (1 << AC_PTE_BIT51_BIT) 95 96 #define AC_PDE_PRESENT_MASK (1 << AC_PDE_PRESENT_BIT) 97 #define AC_PDE_WRITABLE_MASK (1 << AC_PDE_WRITABLE_BIT) 98 #define AC_PDE_USER_MASK (1 << AC_PDE_USER_BIT) 99 #define AC_PDE_ACCESSED_MASK (1 << AC_PDE_ACCESSED_BIT) 100 #define AC_PDE_DIRTY_MASK (1 << AC_PDE_DIRTY_BIT) 101 #define AC_PDE_PSE_MASK (1 << AC_PDE_PSE_BIT) 102 #define AC_PDE_NX_MASK (1 << AC_PDE_NX_BIT) 103 #define AC_PDE_BIT51_MASK (1 << AC_PDE_BIT51_BIT) 104 #define AC_PDE_BIT13_MASK (1 << AC_PDE_BIT13_BIT) 105 106 #define AC_PKU_AD_MASK (1 << AC_PKU_AD_BIT) 107 #define AC_PKU_WD_MASK (1 << AC_PKU_WD_BIT) 108 #define AC_PKU_PKEY_MASK (1 << AC_PKU_PKEY_BIT) 109 110 #define AC_ACCESS_USER_MASK (1 << AC_ACCESS_USER_BIT) 111 #define AC_ACCESS_WRITE_MASK (1 << AC_ACCESS_WRITE_BIT) 112 #define AC_ACCESS_FETCH_MASK (1 << AC_ACCESS_FETCH_BIT) 113 #define AC_ACCESS_TWICE_MASK (1 << AC_ACCESS_TWICE_BIT) 114 115 #define AC_CPU_EFER_NX_MASK (1 << AC_CPU_EFER_NX_BIT) 116 #define AC_CPU_CR0_WP_MASK (1 << AC_CPU_CR0_WP_BIT) 117 #define AC_CPU_CR4_SMEP_MASK (1 << AC_CPU_CR4_SMEP_BIT) 118 #define AC_CPU_CR4_PKE_MASK (1 << AC_CPU_CR4_PKE_BIT) 119 120 const char *ac_names[] = { 121 [AC_PTE_PRESENT_BIT] = "pte.p", 122 [AC_PTE_ACCESSED_BIT] = "pte.a", 123 [AC_PTE_WRITABLE_BIT] = "pte.rw", 124 [AC_PTE_USER_BIT] = "pte.user", 125 [AC_PTE_DIRTY_BIT] = "pte.d", 126 [AC_PTE_NX_BIT] = "pte.nx", 127 [AC_PTE_BIT51_BIT] = "pte.51", 128 [AC_PDE_PRESENT_BIT] = "pde.p", 129 [AC_PDE_ACCESSED_BIT] = "pde.a", 130 [AC_PDE_WRITABLE_BIT] = "pde.rw", 131 [AC_PDE_USER_BIT] = "pde.user", 132 [AC_PDE_DIRTY_BIT] = "pde.d", 133 [AC_PDE_PSE_BIT] = "pde.pse", 134 [AC_PDE_NX_BIT] = "pde.nx", 135 [AC_PDE_BIT51_BIT] = "pde.51", 136 [AC_PDE_BIT13_BIT] = "pde.13", 137 [AC_PKU_AD_BIT] = "pkru.ad", 138 [AC_PKU_WD_BIT] = "pkru.wd", 139 [AC_PKU_PKEY_BIT] = "pkey=1", 140 [AC_ACCESS_WRITE_BIT] = "write", 141 [AC_ACCESS_USER_BIT] = "user", 142 [AC_ACCESS_FETCH_BIT] = "fetch", 143 [AC_ACCESS_TWICE_BIT] = "twice", 144 [AC_CPU_EFER_NX_BIT] = "efer.nx", 145 [AC_CPU_CR0_WP_BIT] = "cr0.wp", 146 [AC_CPU_CR4_SMEP_BIT] = "cr4.smep", 147 [AC_CPU_CR4_PKE_BIT] = "cr4.pke", 148 }; 149 150 static inline void *va(pt_element_t phys) 151 { 152 return (void *)phys; 153 } 154 155 typedef struct { 156 pt_element_t pt_pool; 157 unsigned pt_pool_size; 158 unsigned pt_pool_current; 159 } ac_pool_t; 160 161 typedef struct { 162 unsigned flags; 163 void *virt; 164 pt_element_t phys; 165 pt_element_t *ptep; 166 pt_element_t expected_pte; 167 pt_element_t *pdep; 168 pt_element_t expected_pde; 169 pt_element_t ignore_pde; 170 int expected_fault; 171 unsigned expected_error; 172 } ac_test_t; 173 174 typedef struct { 175 unsigned short limit; 176 unsigned long linear_addr; 177 } __attribute__((packed)) descriptor_table_t; 178 179 180 static void ac_test_show(ac_test_t *at); 181 182 int write_cr4_checking(unsigned long val) 183 { 184 asm volatile(ASM_TRY("1f") 185 "mov %0,%%cr4\n\t" 186 "1:": : "r" (val)); 187 return exception_vector(); 188 } 189 190 void set_cr0_wp(int wp) 191 { 192 unsigned long cr0 = read_cr0(); 193 unsigned long old_cr0 = cr0; 194 195 cr0 &= ~CR0_WP_MASK; 196 if (wp) 197 cr0 |= CR0_WP_MASK; 198 if (old_cr0 != cr0) 199 write_cr0(cr0); 200 } 201 202 void set_cr4_smep(int smep) 203 { 204 unsigned long cr4 = read_cr4(); 205 unsigned long old_cr4 = cr4; 206 extern u64 ptl2[]; 207 208 cr4 &= ~CR4_SMEP_MASK; 209 if (smep) 210 cr4 |= CR4_SMEP_MASK; 211 if (old_cr4 == cr4) 212 return; 213 214 if (smep) 215 ptl2[2] &= ~PT_USER_MASK; 216 write_cr4(cr4); 217 if (!smep) 218 ptl2[2] |= PT_USER_MASK; 219 } 220 221 void set_cr4_pke(int pke) 222 { 223 unsigned long cr4 = read_cr4(); 224 unsigned long old_cr4 = cr4; 225 226 cr4 &= ~X86_CR4_PKE; 227 if (pke) 228 cr4 |= X86_CR4_PKE; 229 if (old_cr4 == cr4) 230 return; 231 232 /* Check that protection keys do not affect accesses when CR4.PKE=0. */ 233 if ((read_cr4() & X86_CR4_PKE) && !pke) { 234 write_pkru(0xfffffffc); 235 } 236 write_cr4(cr4); 237 } 238 239 void set_efer_nx(int nx) 240 { 241 unsigned long long efer = rdmsr(MSR_EFER); 242 unsigned long long old_efer = efer; 243 244 efer &= ~EFER_NX_MASK; 245 if (nx) 246 efer |= EFER_NX_MASK; 247 if (old_efer != efer) 248 wrmsr(MSR_EFER, efer); 249 } 250 251 static void ac_env_int(ac_pool_t *pool) 252 { 253 extern char page_fault, kernel_entry; 254 set_idt_entry(14, &page_fault, 0); 255 set_idt_entry(0x20, &kernel_entry, 3); 256 257 pool->pt_pool = 33 * 1024 * 1024; 258 pool->pt_pool_size = 120 * 1024 * 1024 - pool->pt_pool; 259 pool->pt_pool_current = 0; 260 } 261 262 void ac_test_init(ac_test_t *at, void *virt) 263 { 264 wrmsr(MSR_EFER, rdmsr(MSR_EFER) | EFER_NX_MASK); 265 set_cr0_wp(1); 266 at->flags = 0; 267 at->virt = virt; 268 at->phys = 32 * 1024 * 1024; 269 } 270 271 int ac_test_bump_one(ac_test_t *at) 272 { 273 at->flags = ((at->flags | invalid_mask) + 1) & ~invalid_mask; 274 return at->flags < (1 << NR_AC_FLAGS); 275 } 276 277 #define F(x) ((flags & x##_MASK) != 0) 278 279 _Bool ac_test_legal(ac_test_t *at) 280 { 281 int flags = at->flags; 282 283 if (F(AC_ACCESS_FETCH) && F(AC_ACCESS_WRITE)) 284 return false; 285 286 /* 287 * Since we convert current page to kernel page when cr4.smep=1, 288 * we can't switch to user mode. 289 */ 290 if (F(AC_ACCESS_USER) && F(AC_CPU_CR4_SMEP)) 291 return false; 292 293 /* 294 * Only test protection key faults if CR4.PKE=1. 295 */ 296 if (!F(AC_CPU_CR4_PKE) && 297 (F(AC_PKU_AD) || F(AC_PKU_WD))) { 298 return false; 299 } 300 301 /* 302 * pde.bit13 checks handling of reserved bits in largepage PDEs. It is 303 * meaningless if there is a PTE. 304 */ 305 if (!F(AC_PDE_PSE) && F(AC_PDE_BIT13)) 306 return false; 307 308 return true; 309 } 310 311 int ac_test_bump(ac_test_t *at) 312 { 313 int ret; 314 315 ret = ac_test_bump_one(at); 316 while (ret && !ac_test_legal(at)) 317 ret = ac_test_bump_one(at); 318 return ret; 319 } 320 321 pt_element_t ac_test_alloc_pt(ac_pool_t *pool) 322 { 323 pt_element_t ret = pool->pt_pool + pool->pt_pool_current; 324 pool->pt_pool_current += PAGE_SIZE; 325 return ret; 326 } 327 328 _Bool ac_test_enough_room(ac_pool_t *pool) 329 { 330 return pool->pt_pool_current + 4 * PAGE_SIZE <= pool->pt_pool_size; 331 } 332 333 void ac_test_reset_pt_pool(ac_pool_t *pool) 334 { 335 pool->pt_pool_current = 0; 336 } 337 338 pt_element_t ac_test_permissions(ac_test_t *at, unsigned flags, bool writable, 339 bool user, bool executable) 340 { 341 bool kwritable = !F(AC_CPU_CR0_WP) && !F(AC_ACCESS_USER); 342 pt_element_t expected = 0; 343 344 if (F(AC_ACCESS_USER) && !user) 345 at->expected_fault = 1; 346 347 if (F(AC_ACCESS_WRITE) && !writable && !kwritable) 348 at->expected_fault = 1; 349 350 if (F(AC_ACCESS_FETCH) && !executable) 351 at->expected_fault = 1; 352 353 if (F(AC_ACCESS_FETCH) && user && F(AC_CPU_CR4_SMEP)) 354 at->expected_fault = 1; 355 356 if (user && !F(AC_ACCESS_FETCH) && 357 F(AC_PKU_PKEY) && F(AC_CPU_CR4_PKE) && 358 !at->expected_fault) { 359 if (F(AC_PKU_AD)) { 360 at->expected_fault = 1; 361 at->expected_error |= PFERR_PK_MASK; 362 } else if (F(AC_ACCESS_WRITE) && F(AC_PKU_WD) && !kwritable) { 363 at->expected_fault = 1; 364 at->expected_error |= PFERR_PK_MASK; 365 } 366 } 367 368 if (!at->expected_fault) { 369 expected |= PT_ACCESSED_MASK; 370 if (F(AC_ACCESS_WRITE)) 371 expected |= PT_DIRTY_MASK; 372 } 373 374 return expected; 375 } 376 377 void ac_emulate_access(ac_test_t *at, unsigned flags) 378 { 379 bool pde_valid, pte_valid; 380 bool user, writable, executable; 381 382 if (F(AC_ACCESS_USER)) 383 at->expected_error |= PFERR_USER_MASK; 384 385 if (F(AC_ACCESS_WRITE)) 386 at->expected_error |= PFERR_WRITE_MASK; 387 388 if (F(AC_ACCESS_FETCH)) 389 at->expected_error |= PFERR_FETCH_MASK; 390 391 if (!F(AC_PDE_ACCESSED)) 392 at->ignore_pde = PT_ACCESSED_MASK; 393 394 pde_valid = F(AC_PDE_PRESENT) 395 && !F(AC_PDE_BIT51) && !F(AC_PDE_BIT13) 396 && !(F(AC_PDE_NX) && !F(AC_CPU_EFER_NX)); 397 398 if (!pde_valid) { 399 at->expected_fault = 1; 400 if (F(AC_PDE_PRESENT)) { 401 at->expected_error |= PFERR_RESERVED_MASK; 402 } else { 403 at->expected_error &= ~PFERR_PRESENT_MASK; 404 } 405 goto fault; 406 } 407 408 writable = F(AC_PDE_WRITABLE); 409 user = F(AC_PDE_USER); 410 executable = !F(AC_PDE_NX); 411 412 if (F(AC_PDE_PSE)) { 413 at->expected_pde |= ac_test_permissions(at, flags, writable, user, 414 executable); 415 goto no_pte; 416 } 417 418 at->expected_pde |= PT_ACCESSED_MASK; 419 420 pte_valid = F(AC_PTE_PRESENT) 421 && !F(AC_PTE_BIT51) 422 && !(F(AC_PTE_NX) && !F(AC_CPU_EFER_NX)); 423 424 if (!pte_valid) { 425 at->expected_fault = 1; 426 if (F(AC_PTE_PRESENT)) { 427 at->expected_error |= PFERR_RESERVED_MASK; 428 } else { 429 at->expected_error &= ~PFERR_PRESENT_MASK; 430 } 431 goto fault; 432 } 433 434 writable &= F(AC_PTE_WRITABLE); 435 user &= F(AC_PTE_USER); 436 executable &= !F(AC_PTE_NX); 437 438 at->expected_pte |= ac_test_permissions(at, flags, writable, user, 439 executable); 440 441 no_pte: 442 fault: 443 if (!at->expected_fault) 444 at->ignore_pde = 0; 445 if (!F(AC_CPU_EFER_NX) && !F(AC_CPU_CR4_SMEP)) 446 at->expected_error &= ~PFERR_FETCH_MASK; 447 } 448 449 void ac_set_expected_status(ac_test_t *at) 450 { 451 invlpg(at->virt); 452 453 if (at->ptep) 454 at->expected_pte = *at->ptep; 455 at->expected_pde = *at->pdep; 456 at->ignore_pde = 0; 457 at->expected_fault = 0; 458 at->expected_error = PFERR_PRESENT_MASK; 459 460 if (at->flags & AC_ACCESS_TWICE_MASK) { 461 ac_emulate_access(at, at->flags & ~AC_ACCESS_WRITE_MASK 462 & ~AC_ACCESS_FETCH_MASK & ~AC_ACCESS_USER_MASK); 463 at->expected_fault = 0; 464 at->expected_error = PFERR_PRESENT_MASK; 465 at->ignore_pde = 0; 466 } 467 468 ac_emulate_access(at, at->flags); 469 } 470 471 void __ac_setup_specific_pages(ac_test_t *at, ac_pool_t *pool, u64 pd_page, 472 u64 pt_page) 473 474 { 475 unsigned long root = read_cr3(); 476 int flags = at->flags; 477 478 if (!ac_test_enough_room(pool)) 479 ac_test_reset_pt_pool(pool); 480 481 at->ptep = 0; 482 for (int i = 4; i >= 1 && (i >= 2 || !F(AC_PDE_PSE)); --i) { 483 pt_element_t *vroot = va(root & PT_BASE_ADDR_MASK); 484 unsigned index = PT_INDEX((unsigned long)at->virt, i); 485 pt_element_t pte = 0; 486 switch (i) { 487 case 4: 488 case 3: 489 pte = pd_page ? pd_page : ac_test_alloc_pt(pool); 490 pte |= PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK; 491 break; 492 case 2: 493 if (!F(AC_PDE_PSE)) { 494 pte = pt_page ? pt_page : ac_test_alloc_pt(pool); 495 /* The protection key is ignored on non-leaf entries. */ 496 if (F(AC_PKU_PKEY)) 497 pte |= 2ull << 59; 498 } else { 499 pte = at->phys & PT_PSE_BASE_ADDR_MASK; 500 pte |= PT_PSE_MASK; 501 if (F(AC_PKU_PKEY)) 502 pte |= 1ull << 59; 503 } 504 if (F(AC_PDE_PRESENT)) 505 pte |= PT_PRESENT_MASK; 506 if (F(AC_PDE_WRITABLE)) 507 pte |= PT_WRITABLE_MASK; 508 if (F(AC_PDE_USER)) 509 pte |= PT_USER_MASK; 510 if (F(AC_PDE_ACCESSED)) 511 pte |= PT_ACCESSED_MASK; 512 if (F(AC_PDE_DIRTY)) 513 pte |= PT_DIRTY_MASK; 514 if (F(AC_PDE_NX)) 515 pte |= PT_NX_MASK; 516 if (F(AC_PDE_BIT51)) 517 pte |= 1ull << 51; 518 if (F(AC_PDE_BIT13)) 519 pte |= 1ull << 13; 520 at->pdep = &vroot[index]; 521 break; 522 case 1: 523 pte = at->phys & PT_BASE_ADDR_MASK; 524 if (F(AC_PKU_PKEY)) 525 pte |= 1ull << 59; 526 if (F(AC_PTE_PRESENT)) 527 pte |= PT_PRESENT_MASK; 528 if (F(AC_PTE_WRITABLE)) 529 pte |= PT_WRITABLE_MASK; 530 if (F(AC_PTE_USER)) 531 pte |= PT_USER_MASK; 532 if (F(AC_PTE_ACCESSED)) 533 pte |= PT_ACCESSED_MASK; 534 if (F(AC_PTE_DIRTY)) 535 pte |= PT_DIRTY_MASK; 536 if (F(AC_PTE_NX)) 537 pte |= PT_NX_MASK; 538 if (F(AC_PTE_BIT51)) 539 pte |= 1ull << 51; 540 at->ptep = &vroot[index]; 541 break; 542 } 543 vroot[index] = pte; 544 root = vroot[index]; 545 } 546 ac_set_expected_status(at); 547 } 548 549 static void ac_test_setup_pte(ac_test_t *at, ac_pool_t *pool) 550 { 551 __ac_setup_specific_pages(at, pool, 0, 0); 552 } 553 554 static void ac_setup_specific_pages(ac_test_t *at, ac_pool_t *pool, 555 u64 pd_page, u64 pt_page) 556 { 557 return __ac_setup_specific_pages(at, pool, pd_page, pt_page); 558 } 559 560 static void dump_mapping(ac_test_t *at) 561 { 562 unsigned long root = read_cr3(); 563 int flags = at->flags; 564 int i; 565 566 printf("Dump mapping: address: %p\n", at->virt); 567 for (i = 4; i >= 1 && (i >= 2 || !F(AC_PDE_PSE)); --i) { 568 pt_element_t *vroot = va(root & PT_BASE_ADDR_MASK); 569 unsigned index = PT_INDEX((unsigned long)at->virt, i); 570 pt_element_t pte = vroot[index]; 571 572 printf("------L%d: %lx\n", i, pte); 573 root = vroot[index]; 574 } 575 } 576 577 static void ac_test_check(ac_test_t *at, _Bool *success_ret, _Bool cond, 578 const char *fmt, ...) 579 { 580 va_list ap; 581 char buf[500]; 582 583 if (!*success_ret) { 584 return; 585 } 586 587 if (!cond) { 588 return; 589 } 590 591 *success_ret = false; 592 593 if (!verbose) { 594 puts("\n"); 595 ac_test_show(at); 596 } 597 598 va_start(ap, fmt); 599 vsnprintf(buf, sizeof(buf), fmt, ap); 600 va_end(ap); 601 printf("FAIL: %s\n", buf); 602 dump_mapping(at); 603 } 604 605 static int pt_match(pt_element_t pte1, pt_element_t pte2, pt_element_t ignore) 606 { 607 pte1 &= ~ignore; 608 pte2 &= ~ignore; 609 return pte1 == pte2; 610 } 611 612 int ac_test_do_access(ac_test_t *at) 613 { 614 static unsigned unique = 42; 615 int fault = 0; 616 unsigned e; 617 static unsigned char user_stack[4096]; 618 unsigned long rsp; 619 _Bool success = true; 620 int flags = at->flags; 621 622 ++unique; 623 if (!(unique & 65535)) { 624 puts("."); 625 } 626 627 *((unsigned char *)at->phys) = 0xc3; /* ret */ 628 629 unsigned r = unique; 630 set_cr0_wp(F(AC_CPU_CR0_WP)); 631 set_efer_nx(F(AC_CPU_EFER_NX)); 632 set_cr4_pke(F(AC_CPU_CR4_PKE)); 633 if (F(AC_CPU_CR4_PKE)) { 634 /* WD2=AD2=1, WD1=F(AC_PKU_WD), AD1=F(AC_PKU_AD) */ 635 write_pkru(0x30 | (F(AC_PKU_WD) ? 8 : 0) | 636 (F(AC_PKU_AD) ? 4 : 0)); 637 } 638 639 set_cr4_smep(F(AC_CPU_CR4_SMEP)); 640 641 if (F(AC_ACCESS_TWICE)) { 642 asm volatile ( 643 "mov $fixed2, %%rsi \n\t" 644 "mov (%[addr]), %[reg] \n\t" 645 "fixed2:" 646 : [reg]"=r"(r), [fault]"=a"(fault), "=b"(e) 647 : [addr]"r"(at->virt) 648 : "rsi" 649 ); 650 fault = 0; 651 } 652 653 asm volatile ("mov $fixed1, %%rsi \n\t" 654 "mov %%rsp, %%rdx \n\t" 655 "cmp $0, %[user] \n\t" 656 "jz do_access \n\t" 657 "push %%rax; mov %[user_ds], %%ax; mov %%ax, %%ds; pop %%rax \n\t" 658 "pushq %[user_ds] \n\t" 659 "pushq %[user_stack_top] \n\t" 660 "pushfq \n\t" 661 "pushq %[user_cs] \n\t" 662 "pushq $do_access \n\t" 663 "iretq \n" 664 "do_access: \n\t" 665 "cmp $0, %[fetch] \n\t" 666 "jnz 2f \n\t" 667 "cmp $0, %[write] \n\t" 668 "jnz 1f \n\t" 669 "mov (%[addr]), %[reg] \n\t" 670 "jmp done \n\t" 671 "1: mov %[reg], (%[addr]) \n\t" 672 "jmp done \n\t" 673 "2: call *%[addr] \n\t" 674 "done: \n" 675 "fixed1: \n" 676 "int %[kernel_entry_vector] \n\t" 677 "back_to_kernel:" 678 : [reg]"+r"(r), "+a"(fault), "=b"(e), "=&d"(rsp) 679 : [addr]"r"(at->virt), 680 [write]"r"(F(AC_ACCESS_WRITE)), 681 [user]"r"(F(AC_ACCESS_USER)), 682 [fetch]"r"(F(AC_ACCESS_FETCH)), 683 [user_ds]"i"(USER_DS), 684 [user_cs]"i"(USER_CS), 685 [user_stack_top]"r"(user_stack + sizeof user_stack), 686 [kernel_entry_vector]"i"(0x20) 687 : "rsi"); 688 689 asm volatile (".section .text.pf \n\t" 690 "page_fault: \n\t" 691 "pop %rbx \n\t" 692 "mov %rsi, (%rsp) \n\t" 693 "movl $1, %eax \n\t" 694 "iretq \n\t" 695 ".section .text"); 696 697 asm volatile (".section .text.entry \n\t" 698 "kernel_entry: \n\t" 699 "mov %rdx, %rsp \n\t" 700 "jmp back_to_kernel \n\t" 701 ".section .text"); 702 703 ac_test_check(at, &success, fault && !at->expected_fault, 704 "unexpected fault"); 705 ac_test_check(at, &success, !fault && at->expected_fault, 706 "unexpected access"); 707 ac_test_check(at, &success, fault && e != at->expected_error, 708 "error code %x expected %x", e, at->expected_error); 709 ac_test_check(at, &success, at->ptep && *at->ptep != at->expected_pte, 710 "pte %x expected %x", *at->ptep, at->expected_pte); 711 ac_test_check(at, &success, 712 !pt_match(*at->pdep, at->expected_pde, at->ignore_pde), 713 "pde %x expected %x", *at->pdep, at->expected_pde); 714 715 if (success && verbose) { 716 printf("PASS\n"); 717 } 718 return success; 719 } 720 721 static void ac_test_show(ac_test_t *at) 722 { 723 char line[5000]; 724 725 *line = 0; 726 strcat(line, "test"); 727 for (int i = 0; i < NR_AC_FLAGS; ++i) 728 if (at->flags & (1 << i)) { 729 strcat(line, " "); 730 strcat(line, ac_names[i]); 731 } 732 strcat(line, ": "); 733 printf("%s", line); 734 } 735 736 /* 737 * This test case is used to triger the bug which is fixed by 738 * commit e09e90a5 in the kvm tree 739 */ 740 static int corrupt_hugepage_triger(ac_pool_t *pool) 741 { 742 ac_test_t at1, at2; 743 744 ac_test_init(&at1, (void *)(0x123400000000)); 745 ac_test_init(&at2, (void *)(0x666600000000)); 746 747 at2.flags = AC_CPU_CR0_WP_MASK | AC_PDE_PSE_MASK | AC_PDE_PRESENT_MASK; 748 ac_test_setup_pte(&at2, pool); 749 if (!ac_test_do_access(&at2)) 750 goto err; 751 752 at1.flags = at2.flags | AC_PDE_WRITABLE_MASK; 753 ac_test_setup_pte(&at1, pool); 754 if (!ac_test_do_access(&at1)) 755 goto err; 756 757 at1.flags |= AC_ACCESS_WRITE_MASK; 758 ac_set_expected_status(&at1); 759 if (!ac_test_do_access(&at1)) 760 goto err; 761 762 at2.flags |= AC_ACCESS_WRITE_MASK; 763 ac_set_expected_status(&at2); 764 if (!ac_test_do_access(&at2)) 765 goto err; 766 767 return 1; 768 769 err: 770 printf("corrupt_hugepage_triger test fail\n"); 771 return 0; 772 } 773 774 /* 775 * This test case is used to triger the bug which is fixed by 776 * commit 3ddf6c06e13e in the kvm tree 777 */ 778 static int check_pfec_on_prefetch_pte(ac_pool_t *pool) 779 { 780 ac_test_t at1, at2; 781 782 ac_test_init(&at1, (void *)(0x123406001000)); 783 ac_test_init(&at2, (void *)(0x123406003000)); 784 785 at1.flags = AC_PDE_PRESENT_MASK | AC_PTE_PRESENT_MASK; 786 ac_setup_specific_pages(&at1, pool, 30 * 1024 * 1024, 30 * 1024 * 1024); 787 788 at2.flags = at1.flags | AC_PTE_NX_MASK; 789 ac_setup_specific_pages(&at2, pool, 30 * 1024 * 1024, 30 * 1024 * 1024); 790 791 if (!ac_test_do_access(&at1)) { 792 printf("%s: prepare fail\n", __FUNCTION__); 793 goto err; 794 } 795 796 if (!ac_test_do_access(&at2)) { 797 printf("%s: check PFEC on prefetch pte path fail\n", 798 __FUNCTION__); 799 goto err; 800 } 801 802 return 1; 803 804 err: 805 return 0; 806 } 807 808 /* 809 * If the write-fault access is from supervisor and CR0.WP is not set on the 810 * vcpu, kvm will fix it by adjusting pte access - it sets the W bit on pte 811 * and clears U bit. This is the chance that kvm can change pte access from 812 * readonly to writable. 813 * 814 * Unfortunately, the pte access is the access of 'direct' shadow page table, 815 * means direct sp.role.access = pte_access, then we will create a writable 816 * spte entry on the readonly shadow page table. It will cause Dirty bit is 817 * not tracked when two guest ptes point to the same large page. Note, it 818 * does not have other impact except Dirty bit since cr0.wp is encoded into 819 * sp.role. 820 * 821 * Note: to trigger this bug, hugepage should be disabled on host. 822 */ 823 static int check_large_pte_dirty_for_nowp(ac_pool_t *pool) 824 { 825 ac_test_t at1, at2; 826 827 ac_test_init(&at1, (void *)(0x123403000000)); 828 ac_test_init(&at2, (void *)(0x666606000000)); 829 830 at2.flags = AC_PDE_PRESENT_MASK | AC_PDE_PSE_MASK; 831 ac_test_setup_pte(&at2, pool); 832 if (!ac_test_do_access(&at2)) { 833 printf("%s: read on the first mapping fail.\n", __FUNCTION__); 834 goto err; 835 } 836 837 at1.flags = at2.flags | AC_ACCESS_WRITE_MASK; 838 ac_test_setup_pte(&at1, pool); 839 if (!ac_test_do_access(&at1)) { 840 printf("%s: write on the second mapping fail.\n", __FUNCTION__); 841 goto err; 842 } 843 844 at2.flags |= AC_ACCESS_WRITE_MASK; 845 ac_set_expected_status(&at2); 846 if (!ac_test_do_access(&at2)) { 847 printf("%s: write on the first mapping fail.\n", __FUNCTION__); 848 goto err; 849 } 850 851 return 1; 852 853 err: 854 return 0; 855 } 856 857 static int check_smep_andnot_wp(ac_pool_t *pool) 858 { 859 ac_test_t at1; 860 int err_prepare_andnot_wp, err_smep_andnot_wp; 861 862 if (!(cpuid_7_ebx & (1 << 7))) { 863 return 1; 864 } 865 866 ac_test_init(&at1, (void *)(0x123406001000)); 867 868 at1.flags = AC_PDE_PRESENT_MASK | AC_PTE_PRESENT_MASK | 869 AC_PDE_USER_MASK | AC_PTE_USER_MASK | 870 AC_PDE_ACCESSED_MASK | AC_PTE_ACCESSED_MASK | 871 AC_CPU_CR4_SMEP_MASK | 872 AC_CPU_CR0_WP_MASK | 873 AC_ACCESS_WRITE_MASK; 874 ac_test_setup_pte(&at1, pool); 875 876 /* 877 * Here we write the ro user page when 878 * cr0.wp=0, then we execute it and SMEP 879 * fault should happen. 880 */ 881 err_prepare_andnot_wp = ac_test_do_access(&at1); 882 if (!err_prepare_andnot_wp) { 883 printf("%s: SMEP prepare fail\n", __FUNCTION__); 884 goto clean_up; 885 } 886 887 at1.flags &= ~AC_ACCESS_WRITE_MASK; 888 at1.flags |= AC_ACCESS_FETCH_MASK; 889 ac_set_expected_status(&at1); 890 err_smep_andnot_wp = ac_test_do_access(&at1); 891 892 clean_up: 893 set_cr4_smep(0); 894 895 if (!err_prepare_andnot_wp) 896 goto err; 897 if (!err_smep_andnot_wp) { 898 printf("%s: check SMEP without wp fail\n", __FUNCTION__); 899 goto err; 900 } 901 return 1; 902 903 err: 904 return 0; 905 } 906 907 int ac_test_exec(ac_test_t *at, ac_pool_t *pool) 908 { 909 int r; 910 911 if (verbose) { 912 ac_test_show(at); 913 } 914 ac_test_setup_pte(at, pool); 915 r = ac_test_do_access(at); 916 return r; 917 } 918 919 typedef int (*ac_test_fn)(ac_pool_t *pool); 920 const ac_test_fn ac_test_cases[] = 921 { 922 corrupt_hugepage_triger, 923 check_pfec_on_prefetch_pte, 924 check_large_pte_dirty_for_nowp, 925 check_smep_andnot_wp 926 }; 927 928 int ac_test_run(void) 929 { 930 ac_test_t at; 931 ac_pool_t pool; 932 int i, tests, successes; 933 934 printf("run\n"); 935 tests = successes = 0; 936 937 if (cpuid_7_ecx & (1 << 3)) { 938 set_cr4_pke(1); 939 set_cr4_pke(0); 940 /* Now PKRU = 0xFFFFFFFF. */ 941 } else { 942 unsigned long cr4 = read_cr4(); 943 tests++; 944 if (write_cr4_checking(cr4 | X86_CR4_PKE) == GP_VECTOR) { 945 successes++; 946 invalid_mask |= AC_PKU_AD_MASK; 947 invalid_mask |= AC_PKU_WD_MASK; 948 invalid_mask |= AC_PKU_PKEY_MASK; 949 invalid_mask |= AC_CPU_CR4_PKE_MASK; 950 printf("CR4.PKE not available, disabling PKE tests\n"); 951 } else { 952 printf("Set PKE in CR4 - expect #GP: FAIL!\n"); 953 set_cr4_pke(0); 954 } 955 } 956 957 if (!(cpuid_7_ebx & (1 << 7))) { 958 unsigned long cr4 = read_cr4(); 959 tests++; 960 if (write_cr4_checking(cr4 | CR4_SMEP_MASK) == GP_VECTOR) { 961 successes++; 962 invalid_mask |= AC_CPU_CR4_SMEP_MASK; 963 printf("CR4.SMEP not available, disabling SMEP tests\n"); 964 } else { 965 printf("Set SMEP in CR4 - expect #GP: FAIL!\n"); 966 set_cr4_smep(0); 967 } 968 } 969 970 ac_env_int(&pool); 971 ac_test_init(&at, (void *)(0x123400000000 + 16 * smp_id())); 972 do { 973 ++tests; 974 successes += ac_test_exec(&at, &pool); 975 } while (ac_test_bump(&at)); 976 977 for (i = 0; i < ARRAY_SIZE(ac_test_cases); i++) { 978 ++tests; 979 successes += ac_test_cases[i](&pool); 980 } 981 982 printf("\n%d tests, %d failures\n", tests, tests - successes); 983 984 return successes == tests; 985 } 986 987 int main() 988 { 989 int r; 990 991 setup_idt(); 992 993 cpuid_7_ebx = cpuid(7).b; 994 cpuid_7_ecx = cpuid(7).c; 995 996 printf("starting test\n\n"); 997 r = ac_test_run(); 998 return r ? 0 : 1; 999 } 1000