1/* 2 * s390x startup code 3 * 4 * Copyright (c) 2017 Red Hat Inc 5 * 6 * Authors: 7 * Thomas Huth <thuth@redhat.com> 8 * David Hildenbrand <david@redhat.com> 9 * 10 * This code is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU Library General Public License version 2. 12 */ 13#include <asm/asm-offsets.h> 14 15.section .init 16 17/* entry point - for KVM + TCG we directly start in 64 bit mode */ 18 .globl start 19start: 20 /* setup stack */ 21 larl %r15, stacktop 22 /* setup initial PSW mask + control registers*/ 23 larl %r1, initital_psw 24 lpswe 0(%r1) 25init_psw_cont: 26 /* setup pgm interrupt handler */ 27 larl %r1, pgm_int_psw 28 mvc GEN_LC_PGM_NEW_PSW(16), 0(%r1) 29 /* setup cr0, enabling e.g. AFP-register control */ 30 larl %r1, initital_cr0 31 lctlg %c0, %c0, 0(%r1) 32 /* call setup() */ 33 brasl %r14, setup 34 /* forward test parameter */ 35 larl %r2, __argc 36 llgf %r2, 0(%r2) 37 larl %r3, __argv 38 /* call to main() */ 39 brasl %r14, main 40 /* forward exit code */ 41 lgr %r3, %r2 42 /* call exit() */ 43 j exit 44 45pgm_int: 46 /* save grs 0-15 */ 47 stmg %r0, %r15, GEN_LC_SW_INT_GRS 48 /* save fprs 0-15 + fpc */ 49 larl %r1, GEN_LC_SW_INT_FPRS 50 std %f0, 0(%r1) 51 std %f1, 8(%r1) 52 std %f2, 16(%r1) 53 std %f3, 24(%r1) 54 std %f4, 32(%r1) 55 std %f5, 40(%r1) 56 std %f6, 48(%r1) 57 std %f7, 56(%r1) 58 std %f8, 64(%r1) 59 std %f9, 72(%r1) 60 std %f10, 80(%r1) 61 std %f11, 88(%r1) 62 std %f12, 96(%r1) 63 std %f13, 104(%r1) 64 std %f14, 112(%r1) 65 std %f15, 120(%r1) 66 stfpc GEN_LC_SW_INT_FPC 67 /* call our c handler */ 68 brasl %r14, handle_pgm_int 69 /* restore fprs 0-15 + fpc */ 70 larl %r1, GEN_LC_SW_INT_FPRS 71 ld %f0, 0(%r1) 72 ld %f1, 8(%r1) 73 ld %f2, 16(%r1) 74 ld %f3, 24(%r1) 75 ld %f4, 32(%r1) 76 ld %f5, 40(%r1) 77 ld %f6, 48(%r1) 78 ld %f7, 56(%r1) 79 ld %f8, 64(%r1) 80 ld %f9, 72(%r1) 81 ld %f10, 80(%r1) 82 ld %f11, 88(%r1) 83 ld %f12, 96(%r1) 84 ld %f13, 104(%r1) 85 ld %f14, 112(%r1) 86 ld %f15, 120(%r1) 87 lfpc GEN_LC_SW_INT_FPC 88 /* restore grs 0-15 */ 89 lmg %r0, %r15, GEN_LC_SW_INT_GRS 90 lpswe GEN_LC_PGM_OLD_PSW 91 92 .align 8 93initital_psw: 94 .quad 0x0000000180000000, init_psw_cont 95pgm_int_psw: 96 .quad 0x0000000180000000, pgm_int 97initital_cr0: 98 /* enable AFP-register control, so FP regs (+BFP instr) can be used */ 99 .quad 0x0000000000040000 100