1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * s390x startup code 4 * 5 * Copyright (c) 2017 Red Hat Inc 6 * Copyright (c) 2019 IBM Corp. 7 * 8 * Authors: 9 * Thomas Huth <thuth@redhat.com> 10 * David Hildenbrand <david@redhat.com> 11 * Janosch Frank <frankja@linux.ibm.com> 12 */ 13#include <asm/asm-offsets.h> 14#include <asm/sigp.h> 15 16#include "macros.S" 17.section .init 18 19/* 20 * Short init between 0x10000 and 0x10480 and then jump to 0x11000. 21 * 0x10480 - 0x11000 are written to by bootloader. 22 * 23 * For KVM and TCG kernel boot we are in 64 bit z/Arch mode. 24 * When booting from disk the initial short psw is in 31 bit mode. 25 * When running under LPAR or z/VM, we might start in 31 bit and esam mode. 26 */ 27 .globl start 28start: 29 /* Switch to z/Architecture mode and 64-bit */ 30 slr %r0, %r0 # Set cpuid to zero 31 lhi %r1, 2 # mode 2 = esame 32 sigp %r1, %r0, SIGP_SET_ARCHITECTURE 33 /* XOR all registers with themselves to clear them fully. */ 34 .irp i, 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 35 xgr \i,\i 36 .endr 37 sam64 # Set addressing mode to 64 bit 38 /* setup stack */ 39 larl %r15, stackptr 40 /* setup initial PSW mask + control registers*/ 41 larl %r1, initial_psw 42 lpswe 0(%r1) 43clear_bss_start: 44 larl %r2, __bss_start 45 larl %r3, __bss_end 46 slgr %r3, %r2 # Get sizeof bss 47 aghi %r3,-1 48 srlg %r4,%r3,8 # Calc number of 256 byte chunks 49 ltgr %r4,%r4 50 lgr %r1,%r2 51 jz clear_bss_remainder # If none, clear remaining bytes 52clear_bss_loop: 53 xc 0(256,%r1), 0(%r1) # Clear 256 byte chunks via xor 54 la %r1, 256(%r1) 55 brctg %r4, clear_bss_loop 56clear_bss_remainder: 57 larl %r2, memsetxc 58 ex %r3, 0(%r2) 59 /* setup pgm interrupt handler */ 60 larl %r1, pgm_int_psw 61 mvc GEN_LC_PGM_NEW_PSW(16), 0(%r1) 62 /* setup ext interrupt handler */ 63 larl %r1, ext_int_psw 64 mvc GEN_LC_EXT_NEW_PSW(16), 0(%r1) 65 /* setup mcck interrupt handler */ 66 larl %r1, mcck_int_psw 67 mvc GEN_LC_MCCK_NEW_PSW(16), 0(%r1) 68 /* setup io interrupt handler */ 69 larl %r1, io_int_psw 70 mvc GEN_LC_IO_NEW_PSW(16), 0(%r1) 71 /* setup svc interrupt handler */ 72 larl %r1, svc_int_psw 73 mvc GEN_LC_SVC_NEW_PSW(16), 0(%r1) 74 /* setup cr0, enabling e.g. AFP-register control */ 75 larl %r1, initial_cr0 76 lctlg %c0, %c0, 0(%r1) 77 /* call setup() */ 78 brasl %r14, setup 79 /* forward test parameter */ 80 larl %r2, __argc 81 llgf %r2, 0(%r2) 82 larl %r3, __argv 83 /* call to main() */ 84 brasl %r14, main 85 /* forward exit code */ 86 lgr %r3, %r2 87 /* call exit() */ 88 j exit 89 90memsetxc: 91 xc 0(1,%r1),0(%r1) 92 93.section .text 94pgm_int: 95 CALL_INT_HANDLER handle_pgm_int, GEN_LC_PGM_OLD_PSW 96 97ext_int: 98 CALL_INT_HANDLER handle_ext_int, GEN_LC_EXT_OLD_PSW 99 100mcck_int: 101 CALL_INT_HANDLER handle_mcck_int, GEN_LC_MCCK_OLD_PSW 102 103io_int: 104 CALL_INT_HANDLER handle_io_int, GEN_LC_IO_OLD_PSW 105 106svc_int: 107 CALL_INT_HANDLER handle_svc_int, GEN_LC_SVC_OLD_PSW 108 109 .align 8 110initial_psw: 111 .quad 0x0000000180000000, clear_bss_start 112pgm_int_psw: 113 .quad 0x0000000180000000, pgm_int 114ext_int_psw: 115 .quad 0x0000000180000000, ext_int 116mcck_int_psw: 117 .quad 0x0000000180000000, mcck_int 118io_int_psw: 119 .quad 0x0000000180000000, io_int 120svc_int_psw: 121 .quad 0x0000000180000000, svc_int 122.globl initial_cr0 123initial_cr0: 124 /* enable AFP-register control, so FP regs (+BFP instr) can be used */ 125 .quad 0x0000000000040000 126