1 /* 2 * Test Special Purpose Registers 3 * 4 * Copyright 2017 Thomas Huth, Red Hat Inc. 5 * 6 * This work is licensed under the terms of the GNU LGPL, version 2. 7 * 8 * The basic idea of this test is to check whether the contents of the Special 9 * Purpose Registers (SPRs) are preserved correctly during migration. So we 10 * fill in the SPRs with a well-known value, read the values back (since not 11 * all bits might be retained in the SPRs), then wait for migration to complete 12 * (if the '-w' option has been specified) so that the user has a chance to 13 * migrate the VM. Alternatively, the test can also simply sleep a little bit 14 * with the H_CEDE hypercall, in the hope that we'll get scheduled to another 15 * host CPU and thus register contents might have changed, too (in case of 16 * bugs). Finally, we read back the values from the SPRs and compare them with 17 * the values before the migration. Mismatches are reported as test failures. 18 * Note that we do not test all SPRs since some of the registers change their 19 * content automatically, and some are only accessible with hypervisor privi- 20 * leges or have bad side effects, so we have to omit those registers. 21 */ 22 #include <libcflat.h> 23 #include <util.h> 24 #include <alloc.h> 25 #include <asm/handlers.h> 26 #include <asm/hcall.h> 27 #include <asm/processor.h> 28 #include <asm/barrier.h> 29 30 #define mfspr(nr) ({ \ 31 uint64_t ret; \ 32 asm volatile("mfspr %0,%1" : "=r"(ret) : "i"(nr)); \ 33 ret; \ 34 }) 35 36 #define mtspr(nr, val) \ 37 asm volatile("mtspr %0,%1" : : "i"(nr), "r"(val)) 38 39 uint64_t before[1024], after[1024]; 40 41 static int h_get_term_char(uint64_t termno) 42 { 43 register uint64_t r3 asm("r3") = 0x54; /* H_GET_TERM_CHAR */ 44 register uint64_t r4 asm("r4") = termno; 45 register uint64_t r5 asm("r5"); 46 47 asm volatile (" sc 1 " : "+r"(r3), "+r"(r4), "=r"(r5) 48 : "r"(r3), "r"(r4)); 49 50 return r3 == H_SUCCESS && r4 > 0 ? r5 >> 48 : 0; 51 } 52 53 /* Common SPRs for all PowerPC CPUs */ 54 static void set_sprs_common(uint64_t val) 55 { 56 mtspr(9, val); /* CTR */ 57 // mtspr(273, val); /* SPRG1 */ /* Used by our exception handler */ 58 mtspr(274, val); /* SPRG2 */ 59 mtspr(275, val); /* SPRG3 */ 60 } 61 62 /* SPRs from PowerPC Operating Environment Architecture, Book III, Vers. 2.01 */ 63 static void set_sprs_book3s_201(uint64_t val) 64 { 65 mtspr(18, val); /* DSISR */ 66 mtspr(19, val); /* DAR */ 67 mtspr(152, val); /* CTRL */ 68 mtspr(256, val); /* VRSAVE */ 69 mtspr(786, val); /* MMCRA */ 70 mtspr(795, val); /* MMCR0 */ 71 mtspr(798, val); /* MMCR1 */ 72 } 73 74 /* SPRs from PowerISA 2.07 Book III-S */ 75 static void set_sprs_book3s_207(uint64_t val) 76 { 77 mtspr(3, val); /* DSCR */ 78 mtspr(13, val); /* AMR */ 79 mtspr(17, val); /* DSCR */ 80 mtspr(18, val); /* DSISR */ 81 mtspr(19, val); /* DAR */ 82 mtspr(29, val); /* AMR */ 83 mtspr(61, val); /* IAMR */ 84 // mtspr(152, val); /* CTRL */ /* TODO: Needs a fix in KVM */ 85 mtspr(153, val); /* FSCR */ 86 mtspr(157, val); /* UAMOR */ 87 mtspr(159, val); /* PSPB */ 88 mtspr(256, val); /* VRSAVE */ 89 // mtspr(272, val); /* SPRG0 */ /* Used by our exception handler */ 90 mtspr(769, val); /* MMCR2 */ 91 mtspr(770, val); /* MMCRA */ 92 mtspr(771, val); /* PMC1 */ 93 mtspr(772, val); /* PMC2 */ 94 mtspr(773, val); /* PMC3 */ 95 mtspr(774, val); /* PMC4 */ 96 mtspr(775, val); /* PMC5 */ 97 mtspr(776, val); /* PMC6 */ 98 mtspr(779, (val & 0xfffffffffbab3fffULL) | 0xfa0b2070); /* MMCR0 */ 99 mtspr(784, val); /* SIER */ 100 mtspr(785, val); /* MMCR2 */ 101 mtspr(786, val); /* MMCRA */ 102 mtspr(787, val); /* PMC1 */ 103 mtspr(788, val); /* PMC2 */ 104 mtspr(789, val); /* PMC3 */ 105 mtspr(790, val); /* PMC4 */ 106 mtspr(791, val); /* PMC5 */ 107 mtspr(792, val); /* PMC6 */ 108 mtspr(795, (val & 0xfffffffffbab3fffULL) | 0xfa0b2070); /* MMCR0 */ 109 mtspr(796, val); /* SIAR */ 110 mtspr(797, val); /* SDAR */ 111 mtspr(798, val); /* MMCR1 */ 112 mtspr(800, val); /* BESCRS */ 113 mtspr(801, val); /* BESCCRSU */ 114 mtspr(802, val); /* BESCRR */ 115 mtspr(803, val); /* BESCRRU */ 116 mtspr(804, val); /* EBBHR */ 117 mtspr(805, val); /* EBBRR */ 118 mtspr(806, val); /* BESCR */ 119 mtspr(815, val); /* TAR */ 120 } 121 122 /* SPRs from PowerISA 3.00 Book III */ 123 static void set_sprs_book3s_300(uint64_t val) 124 { 125 set_sprs_book3s_207(val); 126 mtspr(48, val); /* PIDR */ 127 mtspr(144, val); /* TIDR */ 128 mtspr(823, val); /* PSSCR */ 129 } 130 131 static void set_sprs(uint64_t val) 132 { 133 uint32_t pvr = mfspr(287); /* Processor Version Register */ 134 135 set_sprs_common(val); 136 137 switch (pvr >> 16) { 138 case 0x39: /* PPC970 */ 139 case 0x3C: /* PPC970FX */ 140 case 0x44: /* PPC970MP */ 141 set_sprs_book3s_201(val); 142 break; 143 case 0x4b: /* POWER8E */ 144 case 0x4c: /* POWER8NVL */ 145 case 0x4d: /* POWER8 */ 146 set_sprs_book3s_207(val); 147 break; 148 case 0x4e: /* POWER9 */ 149 set_sprs_book3s_300(val); 150 break; 151 default: 152 puts("Warning: Unknown processor version!\n"); 153 } 154 } 155 156 static void get_sprs_common(uint64_t *v) 157 { 158 v[9] = mfspr(9); /* CTR */ 159 // v[273] = mfspr(273); /* SPRG1 */ /* Used by our exception handler */ 160 v[274] = mfspr(274); /* SPRG2 */ 161 v[275] = mfspr(275); /* SPRG3 */ 162 } 163 164 static void get_sprs_book3s_201(uint64_t *v) 165 { 166 v[18] = mfspr(18); /* DSISR */ 167 v[19] = mfspr(19); /* DAR */ 168 v[136] = mfspr(136); /* CTRL */ 169 v[256] = mfspr(256); /* VRSAVE */ 170 v[786] = mfspr(786); /* MMCRA */ 171 v[795] = mfspr(795); /* MMCR0 */ 172 v[798] = mfspr(798); /* MMCR1 */ 173 } 174 175 static void get_sprs_book3s_207(uint64_t *v) 176 { 177 v[3] = mfspr(3); /* DSCR */ 178 v[13] = mfspr(13); /* AMR */ 179 v[17] = mfspr(17); /* DSCR */ 180 v[18] = mfspr(18); /* DSISR */ 181 v[19] = mfspr(19); /* DAR */ 182 v[29] = mfspr(29); /* AMR */ 183 v[61] = mfspr(61); /* IAMR */ 184 // v[136] = mfspr(136); /* CTRL */ /* TODO: Needs a fix in KVM */ 185 v[153] = mfspr(153); /* FSCR */ 186 v[157] = mfspr(157); /* UAMOR */ 187 v[159] = mfspr(159); /* PSPB */ 188 v[256] = mfspr(256); /* VRSAVE */ 189 v[259] = mfspr(259); /* SPRG3 (read only) */ 190 // v[272] = mfspr(272); /* SPRG0 */ /* Used by our exception handler */ 191 v[769] = mfspr(769); /* MMCR2 */ 192 v[770] = mfspr(770); /* MMCRA */ 193 v[771] = mfspr(771); /* PMC1 */ 194 v[772] = mfspr(772); /* PMC2 */ 195 v[773] = mfspr(773); /* PMC3 */ 196 v[774] = mfspr(774); /* PMC4 */ 197 v[775] = mfspr(775); /* PMC5 */ 198 v[776] = mfspr(776); /* PMC6 */ 199 v[779] = mfspr(779); /* MMCR0 */ 200 v[780] = mfspr(780); /* SIAR (read only) */ 201 v[781] = mfspr(781); /* SDAR (read only) */ 202 v[782] = mfspr(782); /* MMCR1 (read only) */ 203 v[784] = mfspr(784); /* SIER */ 204 v[785] = mfspr(785); /* MMCR2 */ 205 v[786] = mfspr(786); /* MMCRA */ 206 v[787] = mfspr(787); /* PMC1 */ 207 v[788] = mfspr(788); /* PMC2 */ 208 v[789] = mfspr(789); /* PMC3 */ 209 v[790] = mfspr(790); /* PMC4 */ 210 v[791] = mfspr(791); /* PMC5 */ 211 v[792] = mfspr(792); /* PMC6 */ 212 v[795] = mfspr(795); /* MMCR0 */ 213 v[796] = mfspr(796); /* SIAR */ 214 v[797] = mfspr(797); /* SDAR */ 215 v[798] = mfspr(798); /* MMCR1 */ 216 v[800] = mfspr(800); /* BESCRS */ 217 v[801] = mfspr(801); /* BESCCRSU */ 218 v[802] = mfspr(802); /* BESCRR */ 219 v[803] = mfspr(803); /* BESCRRU */ 220 v[804] = mfspr(804); /* EBBHR */ 221 v[805] = mfspr(805); /* EBBRR */ 222 v[806] = mfspr(806); /* BESCR */ 223 v[815] = mfspr(815); /* TAR */ 224 } 225 226 static void get_sprs_book3s_300(uint64_t *v) 227 { 228 get_sprs_book3s_207(v); 229 v[48] = mfspr(48); /* PIDR */ 230 v[144] = mfspr(144); /* TIDR */ 231 v[823] = mfspr(823); /* PSSCR */ 232 } 233 234 static void get_sprs(uint64_t *v) 235 { 236 uint32_t pvr = mfspr(287); /* Processor Version Register */ 237 238 get_sprs_common(v); 239 240 switch (pvr >> 16) { 241 case 0x39: /* PPC970 */ 242 case 0x3C: /* PPC970FX */ 243 case 0x44: /* PPC970MP */ 244 get_sprs_book3s_201(v); 245 break; 246 case 0x4b: /* POWER8E */ 247 case 0x4c: /* POWER8NVL */ 248 case 0x4d: /* POWER8 */ 249 get_sprs_book3s_207(v); 250 break; 251 case 0x4e: /* POWER9 */ 252 get_sprs_book3s_300(v); 253 break; 254 } 255 } 256 257 int main(int argc, char **argv) 258 { 259 int i; 260 bool pause = false; 261 uint64_t pat = 0xcafefacec0debabeULL; 262 const uint64_t patterns[] = { 263 0xcafefacec0debabeULL, ~0xcafefacec0debabeULL, 264 0xAAAA5555AAAA5555ULL, 0x5555AAAA5555AAAAULL, 265 0x1234567890ABCDEFULL, 0xFEDCBA0987654321ULL, 266 -1ULL, 267 }; 268 269 for (i = 1; i < argc; i++) { 270 if (!strcmp(argv[i], "-w")) { 271 pause = true; 272 } else if (!strcmp(argv[i], "-p")) { 273 i += 1; 274 if (i >= argc || *argv[i] < '0' 275 || *argv[i] >= '0' + ARRAY_SIZE(patterns)) 276 report_abort("Error: bad value for -p"); 277 pat ^= patterns[*argv[i] - '0']; 278 } else if (!strcmp(argv[i], "-t")) { 279 /* Randomize with timebase register */ 280 asm volatile("mftb %0" : "=r"(i)); 281 pat ^= i; 282 asm volatile("mftb %0" : "=r"(i)); 283 pat ^= ~(uint64_t)i << 32; 284 } else { 285 report_abort("Warning: Unsupported argument: %s", 286 argv[i]); 287 } 288 } 289 290 printf("Settings SPRs to %#lx...\n", pat); 291 set_sprs(pat); 292 293 memset(before, 0, sizeof(before)); 294 memset(after, 0, sizeof(after)); 295 296 get_sprs(before); 297 298 if (pause) { 299 puts("Now migrate the VM, then press a key to continue...\n"); 300 while (h_get_term_char(0) == 0) 301 cpu_relax(); 302 } else { 303 puts("Sleeping...\n"); 304 handle_exception(0x900, &dec_except_handler, NULL); 305 asm volatile ("mtdec %0" : : "r" (0x3FFFFFFF)); 306 hcall(H_CEDE); 307 } 308 309 get_sprs(after); 310 311 puts("Checking SPRs...\n"); 312 for (i = 0; i < 1024; i++) { 313 if (before[i] != 0 || after[i] != 0) 314 report("SPR %d:\t%#018lx <==> %#018lx", 315 before[i] == after[i], i, before[i], after[i]); 316 } 317 318 return report_summary(); 319 } 320