1 /* 2 * Test Special Purpose Registers 3 * 4 * Copyright 2017 Thomas Huth, Red Hat Inc. 5 * 6 * This work is licensed under the terms of the GNU LGPL, version 2. 7 * 8 * The basic idea of this test is to check whether the contents of the Special 9 * Purpose Registers (SPRs) are preserved correctly during migration. So we 10 * fill in the SPRs with a well-known value, read the values back (since not 11 * all bits might be retained in the SPRs), then wait for migration to complete 12 * (if the '-w' option has been specified) so that the user has a chance to 13 * migrate the VM. Alternatively, the test can also simply sleep a little bit 14 * with the H_CEDE hypercall, in the hope that we'll get scheduled to another 15 * host CPU and thus register contents might have changed, too (in case of 16 * bugs). Finally, we read back the values from the SPRs and compare them with 17 * the values before the migration. Mismatches are reported as test failures. 18 * Note that we do not test all SPRs since some of the registers change their 19 * content automatically, and some are only accessible with hypervisor privi- 20 * leges or have bad side effects, so we have to omit those registers. 21 */ 22 #include <libcflat.h> 23 #include <util.h> 24 #include <migrate.h> 25 #include <alloc.h> 26 #include <asm/handlers.h> 27 #include <asm/hcall.h> 28 #include <asm/processor.h> 29 #include <asm/barrier.h> 30 31 #define mfspr(nr) ({ \ 32 uint64_t ret; \ 33 asm volatile("mfspr %0,%1" : "=r"(ret) : "i"(nr)); \ 34 ret; \ 35 }) 36 37 #define mtspr(nr, val) \ 38 asm volatile("mtspr %0,%1" : : "i"(nr), "r"(val)) 39 40 uint64_t before[1024], after[1024]; 41 42 /* Common SPRs for all PowerPC CPUs */ 43 static void set_sprs_common(uint64_t val) 44 { 45 mtspr(9, val); /* CTR */ 46 // mtspr(273, val); /* SPRG1 */ /* Used by our exception handler */ 47 mtspr(274, val); /* SPRG2 */ 48 mtspr(275, val); /* SPRG3 */ 49 } 50 51 /* SPRs from PowerPC Operating Environment Architecture, Book III, Vers. 2.01 */ 52 static void set_sprs_book3s_201(uint64_t val) 53 { 54 mtspr(18, val); /* DSISR */ 55 mtspr(19, val); /* DAR */ 56 mtspr(152, val); /* CTRL */ 57 mtspr(256, val); /* VRSAVE */ 58 mtspr(786, val); /* MMCRA */ 59 mtspr(795, val); /* MMCR0 */ 60 mtspr(798, val); /* MMCR1 */ 61 } 62 63 /* SPRs from PowerISA 2.07 Book III-S */ 64 static void set_sprs_book3s_207(uint64_t val) 65 { 66 mtspr(3, val); /* DSCR */ 67 mtspr(13, val); /* AMR */ 68 mtspr(17, val); /* DSCR */ 69 mtspr(18, val); /* DSISR */ 70 mtspr(19, val); /* DAR */ 71 mtspr(29, val); /* AMR */ 72 mtspr(61, val); /* IAMR */ 73 // mtspr(152, val); /* CTRL */ /* TODO: Needs a fix in KVM */ 74 mtspr(153, val); /* FSCR */ 75 mtspr(157, val); /* UAMOR */ 76 mtspr(159, val); /* PSPB */ 77 mtspr(256, val); /* VRSAVE */ 78 // mtspr(272, val); /* SPRG0 */ /* Used by our exception handler */ 79 mtspr(769, val); /* MMCR2 */ 80 mtspr(770, val); /* MMCRA */ 81 mtspr(771, val); /* PMC1 */ 82 mtspr(772, val); /* PMC2 */ 83 mtspr(773, val); /* PMC3 */ 84 mtspr(774, val); /* PMC4 */ 85 mtspr(775, val); /* PMC5 */ 86 mtspr(776, val); /* PMC6 */ 87 mtspr(779, (val & 0xfffffffffbab3fffULL) | 0xfa0b2070); /* MMCR0 */ 88 mtspr(784, val); /* SIER */ 89 mtspr(785, val); /* MMCR2 */ 90 mtspr(786, val); /* MMCRA */ 91 mtspr(787, val); /* PMC1 */ 92 mtspr(788, val); /* PMC2 */ 93 mtspr(789, val); /* PMC3 */ 94 mtspr(790, val); /* PMC4 */ 95 mtspr(791, val); /* PMC5 */ 96 mtspr(792, val); /* PMC6 */ 97 mtspr(795, (val & 0xfffffffffbab3fffULL) | 0xfa0b2070); /* MMCR0 */ 98 mtspr(796, val); /* SIAR */ 99 mtspr(797, val); /* SDAR */ 100 mtspr(798, val); /* MMCR1 */ 101 mtspr(800, val); /* BESCRS */ 102 mtspr(801, val); /* BESCCRSU */ 103 mtspr(802, val); /* BESCRR */ 104 mtspr(803, val); /* BESCRRU */ 105 mtspr(804, val); /* EBBHR */ 106 mtspr(805, val); /* EBBRR */ 107 mtspr(806, val); /* BESCR */ 108 mtspr(815, val); /* TAR */ 109 } 110 111 /* SPRs from PowerISA 3.00 Book III */ 112 static void set_sprs_book3s_300(uint64_t val) 113 { 114 set_sprs_book3s_207(val); 115 mtspr(48, val); /* PIDR */ 116 mtspr(144, val); /* TIDR */ 117 mtspr(823, val); /* PSSCR */ 118 } 119 120 /* SPRs from Power ISA Version 3.1B */ 121 static void set_sprs_book3s_31(uint64_t val) 122 { 123 set_sprs_book3s_207(val); 124 mtspr(48, val); /* PIDR */ 125 /* 3.1 removes TIDR */ 126 mtspr(823, val); /* PSSCR */ 127 } 128 129 static void set_sprs(uint64_t val) 130 { 131 uint32_t pvr = mfspr(287); /* Processor Version Register */ 132 133 set_sprs_common(val); 134 135 switch (pvr >> 16) { 136 case 0x39: /* PPC970 */ 137 case 0x3C: /* PPC970FX */ 138 case 0x44: /* PPC970MP */ 139 set_sprs_book3s_201(val); 140 break; 141 case 0x4b: /* POWER8E */ 142 case 0x4c: /* POWER8NVL */ 143 case 0x4d: /* POWER8 */ 144 set_sprs_book3s_207(val); 145 break; 146 case 0x4e: /* POWER9 */ 147 set_sprs_book3s_300(val); 148 break; 149 case 0x80: /* POWER10 */ 150 set_sprs_book3s_31(val); 151 break; 152 default: 153 puts("Warning: Unknown processor version!\n"); 154 } 155 } 156 157 static void get_sprs_common(uint64_t *v) 158 { 159 v[9] = mfspr(9); /* CTR */ 160 // v[273] = mfspr(273); /* SPRG1 */ /* Used by our exception handler */ 161 v[274] = mfspr(274); /* SPRG2 */ 162 v[275] = mfspr(275); /* SPRG3 */ 163 } 164 165 static void get_sprs_book3s_201(uint64_t *v) 166 { 167 v[18] = mfspr(18); /* DSISR */ 168 v[19] = mfspr(19); /* DAR */ 169 v[136] = mfspr(136); /* CTRL */ 170 v[256] = mfspr(256); /* VRSAVE */ 171 v[786] = mfspr(786); /* MMCRA */ 172 v[795] = mfspr(795); /* MMCR0 */ 173 v[798] = mfspr(798); /* MMCR1 */ 174 } 175 176 static void get_sprs_book3s_207(uint64_t *v) 177 { 178 v[3] = mfspr(3); /* DSCR */ 179 v[13] = mfspr(13); /* AMR */ 180 v[17] = mfspr(17); /* DSCR */ 181 v[18] = mfspr(18); /* DSISR */ 182 v[19] = mfspr(19); /* DAR */ 183 v[29] = mfspr(29); /* AMR */ 184 v[61] = mfspr(61); /* IAMR */ 185 // v[136] = mfspr(136); /* CTRL */ /* TODO: Needs a fix in KVM */ 186 v[153] = mfspr(153); /* FSCR */ 187 v[157] = mfspr(157); /* UAMOR */ 188 v[159] = mfspr(159); /* PSPB */ 189 v[256] = mfspr(256); /* VRSAVE */ 190 v[259] = mfspr(259); /* SPRG3 (read only) */ 191 // v[272] = mfspr(272); /* SPRG0 */ /* Used by our exception handler */ 192 v[769] = mfspr(769); /* MMCR2 */ 193 v[770] = mfspr(770); /* MMCRA */ 194 v[771] = mfspr(771); /* PMC1 */ 195 v[772] = mfspr(772); /* PMC2 */ 196 v[773] = mfspr(773); /* PMC3 */ 197 v[774] = mfspr(774); /* PMC4 */ 198 v[775] = mfspr(775); /* PMC5 */ 199 v[776] = mfspr(776); /* PMC6 */ 200 v[779] = mfspr(779); /* MMCR0 */ 201 v[780] = mfspr(780); /* SIAR (read only) */ 202 v[781] = mfspr(781); /* SDAR (read only) */ 203 v[782] = mfspr(782); /* MMCR1 (read only) */ 204 v[784] = mfspr(784); /* SIER */ 205 v[785] = mfspr(785); /* MMCR2 */ 206 v[786] = mfspr(786); /* MMCRA */ 207 v[787] = mfspr(787); /* PMC1 */ 208 v[788] = mfspr(788); /* PMC2 */ 209 v[789] = mfspr(789); /* PMC3 */ 210 v[790] = mfspr(790); /* PMC4 */ 211 v[791] = mfspr(791); /* PMC5 */ 212 v[792] = mfspr(792); /* PMC6 */ 213 v[795] = mfspr(795); /* MMCR0 */ 214 v[796] = mfspr(796); /* SIAR */ 215 v[797] = mfspr(797); /* SDAR */ 216 v[798] = mfspr(798); /* MMCR1 */ 217 v[800] = mfspr(800); /* BESCRS */ 218 v[801] = mfspr(801); /* BESCCRSU */ 219 v[802] = mfspr(802); /* BESCRR */ 220 v[803] = mfspr(803); /* BESCRRU */ 221 v[804] = mfspr(804); /* EBBHR */ 222 v[805] = mfspr(805); /* EBBRR */ 223 v[806] = mfspr(806); /* BESCR */ 224 v[815] = mfspr(815); /* TAR */ 225 } 226 227 static void get_sprs_book3s_300(uint64_t *v) 228 { 229 get_sprs_book3s_207(v); 230 v[48] = mfspr(48); /* PIDR */ 231 v[144] = mfspr(144); /* TIDR */ 232 v[823] = mfspr(823); /* PSSCR */ 233 } 234 235 static void get_sprs_book3s_31(uint64_t *v) 236 { 237 get_sprs_book3s_207(v); 238 v[48] = mfspr(48); /* PIDR */ 239 v[823] = mfspr(823); /* PSSCR */ 240 } 241 242 static void get_sprs(uint64_t *v) 243 { 244 uint32_t pvr = mfspr(287); /* Processor Version Register */ 245 246 get_sprs_common(v); 247 248 switch (pvr >> 16) { 249 case 0x39: /* PPC970 */ 250 case 0x3C: /* PPC970FX */ 251 case 0x44: /* PPC970MP */ 252 get_sprs_book3s_201(v); 253 break; 254 case 0x4b: /* POWER8E */ 255 case 0x4c: /* POWER8NVL */ 256 case 0x4d: /* POWER8 */ 257 get_sprs_book3s_207(v); 258 break; 259 case 0x4e: /* POWER9 */ 260 get_sprs_book3s_300(v); 261 break; 262 case 0x80: /* POWER10 */ 263 get_sprs_book3s_31(v); 264 break; 265 } 266 } 267 268 int main(int argc, char **argv) 269 { 270 int i; 271 bool pause = false; 272 uint64_t pat = 0xcafefacec0debabeULL; 273 const uint64_t patterns[] = { 274 0xcafefacec0debabeULL, ~0xcafefacec0debabeULL, 275 0xAAAA5555AAAA5555ULL, 0x5555AAAA5555AAAAULL, 276 0x1234567890ABCDEFULL, 0xFEDCBA0987654321ULL, 277 -1ULL, 278 }; 279 280 for (i = 1; i < argc; i++) { 281 if (!strcmp(argv[i], "-w")) { 282 pause = true; 283 } else if (!strcmp(argv[i], "-p")) { 284 i += 1; 285 if (i >= argc || *argv[i] < '0' 286 || *argv[i] >= '0' + ARRAY_SIZE(patterns)) 287 report_abort("Error: bad value for -p"); 288 pat ^= patterns[*argv[i] - '0']; 289 } else if (!strcmp(argv[i], "-t")) { 290 /* Randomize with timebase register */ 291 asm volatile("mftb %0" : "=r"(i)); 292 pat ^= i; 293 asm volatile("mftb %0" : "=r"(i)); 294 pat ^= ~(uint64_t)i << 32; 295 } else { 296 report_abort("Warning: Unsupported argument: %s", 297 argv[i]); 298 } 299 } 300 301 printf("Settings SPRs to %#lx...\n", pat); 302 set_sprs(pat); 303 304 memset(before, 0, sizeof(before)); 305 memset(after, 0, sizeof(after)); 306 307 get_sprs(before); 308 309 if (pause) { 310 migrate_once(); 311 } else { 312 msleep(2000); 313 } 314 315 get_sprs(after); 316 317 puts("Checking SPRs...\n"); 318 for (i = 0; i < 1024; i++) { 319 if (before[i] != 0 || after[i] != 0) 320 report(before[i] == after[i], 321 "SPR %d:\t%#018lx <==> %#018lx", i, before[i], 322 after[i]); 323 } 324 325 return report_summary(); 326 } 327